BaseTile.md

Rocket/tile/BaseTile

The set of base classes for tiles.

---

• BareTile The base tile definition of all tiles, even the BaseTile.
• BaseTile The tile used by Rocket, which has a TileLink master port.

---

BareTile

abstract class BareTile

The base class of all tiles, even the BaseTile.

abstract class BareTile(implicit p: Parameters) extends LazyModule

abstract class BareTileBundle

The base bundle class of all tiles, even the BaseTile.

abstract class BareTileBundle[+L <: BareTile](_outer: L) extends GenericParameterizedBundle(_outer) {
  val outer = _outer
  implicit val p = outer.p
}

abstract class BareTileModule

The base tile implementation for all tiles, including BaseTile.

abstract class BareTileModule[+L <: BareTile, +B <: BareTileBundle[L]](_outer: L, _io: () => B) extends LazyModuleImp(_outer) {
  val outer = _outer
  val io = _io ()
}

BaseTile

trait HasTileLinkMasterPort

The Tilelink node definition for a base tile.

trait HasTileLinkMasterPort {
  implicit val p: Parameters
  val module: HasTileLinkMasterPortModule
  val masterNode = TLOutputNode()
  val tileBus = LazyModule(new TLXbar) // TileBus xbar for cache backends to connect to
  masterNode := tileBus.node
}

• module pointer to the implementation.
• masterNode TLOutputNode a Tile is a TileLink output node, a master on the system bus.
• tileBus LazModule[TLXbar] the internal TileLink bus for the I$, D$, RoCC, etc.

trait HasTileLinkMasterPortBundle

The bundle for the base tile (TileLink master port) (cake pattern).

trait HasTileLinkMasterPortBundle {
  val outer: HasTileLinkMasterPort
  val master = outer.masterNode.bundleOut
}

trait HasTileLinkMasterPortModule

The base implementation for the base tile's master port (cake pattern).

trait HasTileLinkMasterPortModule {
  val outer: HasTileLinkMasterPort
  val io: HasTileLinkMasterPortBundle
}

trait HasExternallyDrivenTileConstants

The constant value driven as input ports.

trait HasExternallyDrivenTileConstants extends Bundle {
  implicit val p: Parameters
  val hartid = UInt(INPUT, p(MaxHartIdBits))
  val resetVector = UInt(INPUT, p(ResetVectorBits))
}

• hartid UInt the hartid.
  If the hartid is an input port, why there are some modules still take hartid as a parameter?
• resetVector UInt the reset pc address.

abstract class BaseTile

Base tile.

abstract class BaseTile(tileParams: TileParams)(implicit p: Parameters) extends BareTile
    with HasTileParameters
    with HasTileLinkMasterPort {
  override lazy val module = new BaseTileModule(this, () => new BaseTileBundle(this))
}

class BaseTileBundle

Bundle for a base tile.

class BaseTileBundle[+L <: BaseTile](_outer: L) extends BareTileBundle(_outer)
    with HasTileLinkMasterPortBundle
    with HasExternallyDrivenTileConstants

class BaseTileModule

Base implemenation of a tile.

class BaseTileModule[+L <: BaseTile, +B <: BaseTileBundle[L]](_outer: L, _io: () => B) extends BareTileModule(_outer, _io)
    with HasTileLinkMasterPortModule

_{Last updated: 27/07/2017
CC BY-NC-SA 4.0, © (2017) Wei Song
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BSD, © (2012-2014, 2016) The Regents of the University of California (Regents)}