marchid.md

Open-Source RISC-V Architecture IDs

Every RISC-V hart provides an marchid CSR that encodes its base microarchitecture. Any hart may report an architecture ID of 0, indicating unspecified origin. Commercial implementations (those with nonzero mvendorid) may encode any value in marchid with the most-significant bit set, with the low-order bits formatted in a vendor-specific manner. Open-source implementations (which may or may not have a nonzero mvendorid) have the most-significant bit clear, with a globally unique pattern in the low-order bits.

This document contains the canonical list of open-source RISC-V implementations and their architecture IDs. Open-source project maintainers may make pull requests against this repository to request the allocation of an architecture ID.

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Project Name	Maintainers	Point of Contact	Architecture ID	Project URL
Rocket	SiFive, UC Berkeley	Andrew Waterman, SiFive	1	https://github.com/chipsalliance/rocket-chip
BOOM	UC Berkeley	Christopher Celio	2	https://github.com/riscv-boom/riscv-boom
CVA6	OpenHW Group	Florian Zaruba, OpenHW Group	3	https://github.com/openhwgroup/cva6
CV32E40P	OpenHW Group	Davide Schiavone, OpenHW Group	4	https://github.com/openhwgroup/cv32e40p
Spike	SiFive, UC Berkeley	Andrew Waterman, SiFive	5	https://github.com/riscv/riscv-isa-sim
E-Class	IIT Madras	Neel Gala	6	https://gitlab.com/shaktiproject/cores/e-class
ORCA	VectorBlox	Joel Vandergriendt	7	https://github.com/vectorblox/orca
SCR1	Syntacore	Dmitri Pavlov, Syntacore	8	https://github.com/syntacore/scr1
YARVI	Tommy Thorn's Priceless Services	Tommy Thorn	9	https://github.com/tommythorn/yarvi
RVBS	Alexandre Joannou, University of Cambridge	Alexandre Joannou	10	https://github.com/CTSRD-CHERI/RVBS
SweRV EH1	Western Digital Corporation	Thomas Wicki	11	https://github.com/chipsalliance/Cores-SweRV
MSCC	Rongcui Dong	Rongcui Dong	12	https://github.com/rongcuid/MSCC
BlackParrot	The World	Michael B. Taylor, U. Washington	13	https://github.com/black-parrot
BaseJump Manycore	U. Washington	Michael B. Taylor, U. Washington	14	https://github.com/bespoke-silicon-group/bsg_manycore
C-Class	IIT Madras	Neel Gala	15	https://gitlab.com/shaktiproject/cores/c-class
SweRV EL2	Western Digital Corporation	Thomas Wicki	16	https://github.com/chipsalliance/Cores-SweRV-EL2
SweRV EH2	Western Digital Corporation	Thomas Wicki	17	https://github.com/chipsalliance/Cores-SweRV-EH2
SERV	Olof Kindgren Enterprises	Olof Kindgren	18	https://github.com/olofk/serv
NEORV32	Stephan Nolting	Stephan Nolting	19	https://github.com/stnolting/neorv32
CV32E40X	OpenHW Group	Arjan Bink, Silicon Laboratories	20	https://github.com/openhwgroup/cv32e40x
CV32E40S	OpenHW Group	Arjan Bink, Silicon Laboratories	21	https://github.com/openhwgroup/cv32e40s
Ibex	lowRISC	lowRISC Hardware Team	22	https://github.com/lowRISC/ibex
RudolV	Jörg Mische	Jörg Mische	23	https://github.com/bobbl/rudolv
Steel Core	Rafael Calcada	Rafael Calcada	24	https://github.com/rafaelcalcada/steel-core
XiangShan	ICT, CAS	XiangShan Team	25	https://github.com/OpenXiangShan/XiangShan
Hummingbirdv2 E203	Nuclei System Technology	Can Hu, Nuclei System Technology	26	https://github.com/riscv-mcu/e203_hbirdv2
Hazard3	Luke Wren	Luke Wren	27	https://github.com/wren6991/hazard3
CV32E41P	OpenHW Group	Mark Hill, OpenHW Group	28	https://github.com/openhwgroup/cv32e41p
Rift	Jianhu Lab, WUT	Ruige Lee	29	RiftCore, Rift2Core
RISu064	Wenting Zhang	Wenting Zhang	30	https://github.com/zephray/RISu064
AIRISC	Fraunhofer IMS	AIRISC Support	31	https://github.com/Fraunhofer-IMS/airisc_core_complex
Proteus	imec-DistriNet, KU Leuven	Marton Bognar	32	https://github.com/proteus-core/proteus
VexRiscv	SpinalHDL	Charles Papon	33	https://github.com/SpinalHDL/VexRiscv