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logic.lbr
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logic.lbr
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<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE eagle SYSTEM "eagle.dtd">
<eagle version="9.2.2">
<drawing>
<settings>
<setting alwaysvectorfont="no"/>
<setting verticaltext="up"/>
</settings>
<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
<layers>
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<layer number="115" name="ReferenceISLANDS" color="7" fill="1" visible="yes" active="yes"/>
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</layers>
<library>
<packages>
<package name="SOT23-5L">
<description><b>Small Outline Transistor</b><p>
package type OT</description>
<wire x1="1.422" y1="0.81" x2="1.422" y2="-0.81" width="0.1524" layer="21"/>
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<text x="-1.905" y="1.905" size="1.27" layer="25">>NAME</text>
<text x="-1.905" y="-3.429" size="1.27" layer="27">>VALUE</text>
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<rectangle x1="-1.2" y1="0.85" x2="-0.7" y2="1.5" layer="51"/>
</package>
<package name="SC70-5L">
<description><b>SC-70 Package</b></description>
<wire x1="1.1" y1="-0.5" x2="-1.1" y2="-0.5" width="0.2032" layer="51"/>
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</package>
</packages>
<symbols>
<symbol name="GATE_BUFFER_WITH_ENABLE">
<wire x1="-2.54" y1="5.08" x2="6.258559375" y2="0" width="0.254" layer="94"/>
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<pin name="Y" x="10.16" y="0" visible="pad" length="point"/>
<pin name="A" x="-5.08" y="0" visible="pad" length="short"/>
<pin name="!EN" x="2.54" y="-5.08" visible="pad" length="point" rot="R270"/>
<circle x="2.54" y="-3.302" radius="1.016" width="0.254" layer="94"/>
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<text x="5.08" y="-5.08" size="1.778" layer="95" font="vector">>VALUE</text>
</symbol>
<symbol name="POWER_CONSORT">
<wire x1="-2.54" y1="5.08" x2="2.54" y2="5.08" width="0.254" layer="94"/>
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</symbol>
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<devicesets>
<deviceset name="SN74LV1T125">
<description><h1>SN74LV1T125 Single Power Supply Single Buffer Gate with 3-State Output CMOS Logic
Level Shifter</h1>
<p>
<a href="http://www.ti.com/product/sn74lv1t125">Website</a>
<a href="http://www.ti.com/lit/ds/symlink/sn74lv1t125.pdf">Datasheet</a>
</p>
<blockquote cite="http://www.ti.com/product/sn74lv1t125">
<p>
SN74LV1T125 is a low voltage CMOS gate logic that operates at a wider voltage range for industrial, portable, telecom, and automotive applications. The output level is referenced to the supply voltage and is able to support 1.8V/2.5V/3.3V/5V CMOS levels.
</p>
<p>
The input is designed with a lower threshold circuit to match 1.8V input logic at VCC = 3.3V and can be used in 1.8V to 3.3V level up translation. In addition, the 5V tolerant input pins enable down translation (e.g. 3.3V to 2.5V output at VCC = 2.5V). The wide VCC range of 1.8V to 5.5V allows generation of desired output levels to connect to controllers or processors.
</p>
<ul>
<li>Single-Supply Voltage Translator at 5.0/3.3/2.5/1.8V VCC</li>
<li>Operating Range of 1.8V to 5.5V</li>
<li>Up Translation</li>
<li>
<ul>
<li>1.2V(1) to 1.8V at 1.8V VCC</li>
<li>1.5V(1) to 2.5V at 2.5V VCC</li>
<li>1.8V(1) to 3.3V at 3.3V VCC</li>
<li>3.3V to 5.0V at 5.0VVCC</li>
</ul>
</li>
<li>Down Translation</li>
</ul>
</blockquote></description>
<gates>
<gate name="G$1" symbol="GATE_BUFFER_WITH_ENABLE" x="2.54" y="5.08"/>
<gate name="G$2" symbol="POWER_CONSORT" x="25.4" y="5.08"/>
</gates>
<devices>
<device name="DBVR" package="SOT23-5L">
<connects>
<connect gate="G$1" pin="!EN" pad="1"/>
<connect gate="G$1" pin="A" pad="2"/>
<connect gate="G$1" pin="Y" pad="4"/>
<connect gate="G$2" pin="P$V+" pad="5"/>
<connect gate="G$2" pin="P$V-" pad="3"/>
</connects>
<technologies>
<technology name=""/>
</technologies>
</device>
<device name="DCKR" package="SC70-5L">
<connects>
<connect gate="G$1" pin="!EN" pad="1"/>
<connect gate="G$1" pin="A" pad="2"/>
<connect gate="G$1" pin="Y" pad="4"/>
<connect gate="G$2" pin="P$V+" pad="5"/>
<connect gate="G$2" pin="P$V-" pad="3"/>
</connects>
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="MC74VHC1GT125">
<description><h1>MC74VHC1GT125: Single Non-Inverting Buffer, 3-State
</h1>
<p>
<a href="https://www.onsemi.jp/PowerSolutions/product.do?id=MC74VHC1GT125">Website</a>
<a href="https://www.onsemi.jp/PowerSolutions/document/MC74VHC1GT125-D.PDF">Datasheet</a>
</p>
<blockquote cite="https://www.onsemi.jp/PowerSolutions/product.do?id=MC74VHC1GT125">
<p>
The MC74VHC1GT125 is a single gate noninverting buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.
</p>
<p>
The MC74VHC1GT125 requires the 3-state control input (OE(bar)) to be set High to place the output into the high impedance state.
</p>
<p>
The device input is compatible with TTL-type input thresholds and the output has a full 5V CMOS level output swing. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic-level translator from 3.0V CMOS logic to 5.0V CMOS Logic or from 1.8V CMOS logic to 3.0V CMOS Logic while operating at the high-voltage power supply.
</p>
<p>
The MC74VHC1GT125 input structure provides protection when voltages up to 7V are applied, regardless of the supply voltage. This allows the MC74VHC1GT125 to be used to interface 5V circuits to 3V circuits. The output structures also provide protection when VCC = 0V. These input and output structures help prevent device destruction caused by supply voltage - input/output voltage mismatch, battery backup, hot insertion, etc.
</p>
<ul>
<li>High Speed: tPD = 3.5ns (Typ) at VCC = 5V</li>
<li>Low Power Dissipation: ICC= 1µA (Max) at TA = 25°C</li>
<li>TTL-Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V</li>
<li>CMOS-Compatible Outputs: VOH > 0.8 VCC ; VOL < 0.1 VCC @Load</li>
<li>Power Down Protection Provided on Inputs and Outputs</li>
<li>Balanced Propagation Delays</li>
<li>Pin and Function Compatible with Other Standard Logic Families</li>
<li>Chip Complexity:FETs = 62; Equivalent Gates = 16</li>
<li>Pb-Free Packages are Available</li>
</ul>
</blockquote></description>
<gates>
<gate name="G$1" symbol="GATE_BUFFER_WITH_ENABLE" x="2.54" y="5.08"/>
<gate name="G$2" symbol="POWER_CONSORT" x="25.4" y="5.08"/>
</gates>
<devices>
<device name="DF" package="SC70-5L">
<connects>
<connect gate="G$1" pin="!EN" pad="1"/>
<connect gate="G$1" pin="A" pad="2"/>
<connect gate="G$1" pin="Y" pad="4"/>
<connect gate="G$2" pin="P$V+" pad="5"/>
<connect gate="G$2" pin="P$V-" pad="3"/>
</connects>
<technologies>
<technology name=""/>
</technologies>
</device>
<device name="DT" package="SOT23-5L">
<connects>
<connect gate="G$1" pin="!EN" pad="1"/>
<connect gate="G$1" pin="A" pad="2"/>
<connect gate="G$1" pin="Y" pad="4"/>
<connect gate="G$2" pin="P$V+" pad="5"/>
<connect gate="G$2" pin="P$V-" pad="3"/>
</connects>
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
</devicesets>
</library>
</drawing>
</eagle>