- D is the data input.
- clk is the clock input, which triggers the flip-flop on the rising edge.
- rst is the reset input, which asynchronously sets the output to 0 (1'b0) when asserted.
- q is the output of the flip-flop, which stores the value of d on the rising edge of the clock if the reset is not active.
- You can instantiate this module in your Verilog design and connect it to other components as needed. Remember to include the necessary clock and reset signals in your overall design to properly control the flip-flop's behavior.
This testbench includes:
- Clock generation with a 50% duty cycle.
- Stimulus generation to apply and release reset and change the data input.
- A display statement to show the simulation time, inputs, and the flip-flop's output (q) whenever the clock edge occurs.