Day-20

In this code:

• clk is the clock input.
• rst is the reset input. When rst is asserted (1), the counter is reset to 0.
• up_down is the control input. When up_down is asserted (1), the counter counts up, and when it is de-asserted (0), the counter counts down.
• count is the 4-bit output of the counter.

This code uses a synchronous always block to update the counter on the rising edge of the clock (posedge clk). If the reset signal is active (rst), the counter is reset to 0. Depending on the up_down control signal, the counter either increments (counts up) or decrements (counts down) within the range of 0 to 15 (4-bit).

In this testbench:

• We instantiate the UpDownCounter module and connect its inputs and outputs to signals in the testbench.

• We generate a clock signal (clk) that toggles every 5 time units.

• We initialize the rst signal to reset the counter for a short period at the beginning of simulation.

• We then switch the up_down control signal to test counting down.

• Finally, we display the counter value on each rising edge of the clock using the $display system task.

You can use this testbench to simulate and verify the behavior of your up-down counter in a Verilog simulator.