Day-25

In this Verilog module:

• data_in is the 8-bit input data that you want to shift.
• shift_amount is a 3-bit control signal that determines how many positions to shift.
• shift_direction is a control signal that specifies the shifting direction (0 for left, 1 for right).
• data_out is the 8-bit output data after shifting.

The always block uses a case statement to determine the shift direction and amount and calculates the shifted_data accordingly. Left shifting is performed using the << operator, and right shifting is done using the >> operator.

In this testbench:

• We declare the necessary signals for connecting to the shifter module: data_in, shift_amount, shift_direction, and data_out.

• We instantiate the ParallelShifter module and connect its ports to the testbench signals.

• Inside the initial block, we create test cases by changing the values of data_in, shift_amount, and shift_direction. We wait for some time using #10 to allow the shifter to perform the shift operation, and then we compare the data_out with the expected output values.

• You can add more test cases by following the same pattern, and the testbench will display whether each test case passes or fails.