Day-26

In this Verilog Code

In this Verilog module, we have two data ports (data_out1 and data_out2) for reading data from the memory and two write enable signals (write_en1 and write_en2) for writing data to the memory.

The module includes an 8-bit wide memory array memory, and each port has an 8-bit address bus (addr1 and addr2) and an 8-bit data bus (data_in1 and data_in2).

The module performs read and write operations based on the clock signal (clk) and an optional reset signal (rst).

When a write operation is enabled for a specific port, the data is written to the corresponding address in the memory array. When a read operation is requested, the data is read from the memory and provided on the respective data output port. When a write operation is not enabled, the data output is in a high-impedance state (8'bZ).

In this Test bench

1. We instantiate the two_port_ram module and generate a clock signal (clk) with a period of 10 time units.

2. We apply initial values to the inputs, including a reset (rst) signal.

3. We perform write operations by changing the address, data inputs, and write enables for both ports.

4. We then read data from the memory by setting the write enables to 0 and monitoring the data outputs.

5. Finally, we use $finish to end the simulation and display the results at each time step using $display.