Tracepoint extension support (#160)

This PR adds basic [tracepoint extension](https://sourceware.org/gdb/current/onlinedocs/gdb.html/Tracepoints.html) support. Closes #157. 

---------

Co-authored-by: cczetier <cczetier@zetier.com>

Author: cczetier

README.md

@@ -89,6 +89,10 @@ Of course, most use-cases will want to support additional debugging features as
 -   Read auxiliary vector (`info auxv`)
 -   Extra thread info (`info threads`)
 -   Extra library information (`info sharedlibraries`)
+-   Tracepoints
+    - Configure tracepoints and actions to perform when hit
+    - Select and interrogate collected trace frames
+   - _Note:_ Feature support is not exhaustive, and many feature haven't been implemented yet.
 
 _Note:_ GDB features are implemented on an as-needed basis by `gdbstub`'s contributors. If there's a missing GDB feature that you'd like `gdbstub` to implement, please file an issue and/or open a PR!
 

examples/armv4t/emu.rs

@@ -7,6 +7,12 @@ use armv4t_emu::ExampleMem;
 use armv4t_emu::Memory;
 use armv4t_emu::Mode;
 use gdbstub::common::Pid;
+use gdbstub::target::ext::tracepoints::NewTracepoint;
+use gdbstub::target::ext::tracepoints::SourceTracepoint;
+use gdbstub::target::ext::tracepoints::Tracepoint;
+use gdbstub::target::ext::tracepoints::TracepointAction;
+use gdbstub::target::ext::tracepoints::TracepointEnumerateState;
+use std::collections::BTreeMap;
 
 const HLE_RETURN_ADDR: u32 = 0x12345678;
 
@@ -25,6 +31,12 @@ pub enum ExecMode {
     RangeStep(u32, u32),
 }
 
+#[derive(Debug)]
+pub struct TraceFrame {
+    pub number: Tracepoint,
+    pub snapshot: Cpu,
+}
+
 /// incredibly barebones armv4t-based emulator
 pub struct Emu {
     start_addr: u32,
@@ -41,6 +53,19 @@ pub struct Emu {
     pub(crate) breakpoints: Vec<u32>,
     pub(crate) files: Vec<Option<std::fs::File>>,
 
+    pub(crate) tracepoints: BTreeMap<
+        Tracepoint,
+        (
+            NewTracepoint<u32>,
+            Vec<SourceTracepoint<'static, u32>>,
+            Vec<TracepointAction<'static, u32>>,
+        ),
+    >,
+    pub(crate) traceframes: Vec<TraceFrame>,
+    pub(crate) tracepoint_enumerate_state: TracepointEnumerateState<u32>,
+    pub(crate) tracing: bool,
+    pub(crate) selected_frame: Option<usize>,
+
     pub(crate) reported_pid: Pid,
 }
 
@@ -93,6 +118,12 @@ impl Emu {
             breakpoints: Vec::new(),
             files: Vec::new(),
 
+            tracepoints: BTreeMap::new(),
+            traceframes: Vec::new(),
+            tracepoint_enumerate_state: Default::default(),
+            tracing: false,
+            selected_frame: None,
+
             reported_pid: Pid::new(1).unwrap(),
         })
     }
@@ -106,6 +137,26 @@ impl Emu {
 
     /// single-step the interpreter
     pub fn step(&mut self) -> Option<Event> {
+        if self.tracing {
+            let pc = self.cpu.reg_get(self.cpu.mode(), reg::PC);
+            let frames: Vec<_> = self
+                .tracepoints
+                .iter()
+                .filter(|(_tracepoint, (ctp, _source, _actions))| ctp.enabled && ctp.addr == pc)
+                .map(|(tracepoint, _definition)| {
+                    // our `tracepoint_define` restricts our loaded tracepoints to only contain
+                    // register collect actions. instead of only collecting the registers requested
+                    // in the register mask and recording a minimal trace frame, we just collect
+                    // all of them by cloning the cpu itself.
+                    TraceFrame {
+                        number: *tracepoint,
+                        snapshot: self.cpu,
+                    }
+                })
+                .collect();
+            self.traceframes.extend(frames);
+        }
+
         let mut hit_watchpoint = None;
 
         let mut sniffer = MemSniffer::new(&mut self.mem, &self.watchpoints, |access| {

examples/armv4t/gdb/mod.rs

@@ -26,6 +26,7 @@ mod memory_map;
 mod monitor_cmd;
 mod section_offsets;
 mod target_description_xml_override;
+pub(crate) mod tracepoints;
 
 /// Turn a `ArmCoreRegId` into an internal register number of `armv4t_emu`.
 fn cpu_reg_id(id: ArmCoreRegId) -> Option<u8> {
@@ -161,29 +162,46 @@ impl Target for Emu {
     ) -> Option<target::ext::libraries::LibrariesSvr4Ops<'_, Self>> {
         Some(self)
     }
+
+    #[inline(always)]
+    fn support_tracepoints(
+        &mut self,
+    ) -> Option<target::ext::tracepoints::TracepointsOps<'_, Self>> {
+        Some(self)
+    }
 }
 
 impl SingleThreadBase for Emu {
     fn read_registers(
         &mut self,
         regs: &mut custom_arch::ArmCoreRegsCustom,
     ) -> TargetResult<(), Self> {
-        let mode = self.cpu.mode();
+        // if we selected a frame from a tracepoint, return registers from that snapshot
+        let cpu = self
+            .selected_frame
+            .and_then(|selected| self.traceframes.get(selected))
+            .map(|frame| frame.snapshot)
+            .unwrap_or_else(|| self.cpu);
+        let mode = cpu.mode();
 
         for i in 0..13 {
-            regs.core.r[i] = self.cpu.reg_get(mode, i as u8);
+            regs.core.r[i] = cpu.reg_get(mode, i as u8);
         }
-        regs.core.sp = self.cpu.reg_get(mode, reg::SP);
-        regs.core.lr = self.cpu.reg_get(mode, reg::LR);
-        regs.core.pc = self.cpu.reg_get(mode, reg::PC);
-        regs.core.cpsr = self.cpu.reg_get(mode, reg::CPSR);
+        regs.core.sp = cpu.reg_get(mode, reg::SP);
+        regs.core.lr = cpu.reg_get(mode, reg::LR);
+        regs.core.pc = cpu.reg_get(mode, reg::PC);
+        regs.core.cpsr = cpu.reg_get(mode, reg::CPSR);
 
         regs.custom = self.custom_reg;
 
         Ok(())
     }
 
     fn write_registers(&mut self, regs: &custom_arch::ArmCoreRegsCustom) -> TargetResult<(), Self> {
+        if self.selected_frame.is_some() {
+            // we can't modify registers in a tracepoint frame
+            return Err(TargetError::NonFatal);
+        }
         let mode = self.cpu.mode();
 
         for i in 0..13 {
@@ -208,6 +226,12 @@ impl SingleThreadBase for Emu {
     }
 
     fn read_addrs(&mut self, start_addr: u32, data: &mut [u8]) -> TargetResult<usize, Self> {
+        if self.selected_frame.is_some() {
+            // we only support register collection actions for our tracepoint frames.
+            // if we have a selected frame, then we don't have any memory we can
+            // return from the frame snapshot.
+            return Ok(0);
+        }
         // this is a simple emulator, with RAM covering the entire 32 bit address space
         for (addr, val) in (start_addr..).zip(data.iter_mut()) {
             *val = self.mem.r8(addr)
@@ -216,6 +240,11 @@ impl SingleThreadBase for Emu {
     }
 
     fn write_addrs(&mut self, start_addr: u32, data: &[u8]) -> TargetResult<(), Self> {
+        if self.selected_frame.is_some() {
+            // we can't modify memory in a tracepoint frame
+            return Err(TargetError::NonFatal);
+        }
+
         // this is a simple emulator, with RAM covering the entire 32 bit address space
         for (addr, val) in (start_addr..).zip(data.iter().copied()) {
             self.mem.w8(addr, val)