stage-1: count rising edges on PMOD pin 1 using onboard LEDs

Author: dehre

.gitignore

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+.vscode/

constraints/clock-constraint.sdc

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+create_clock  -period 40.00 -name {i_clk} [get_ports {i_clk}]

constraints/pin-constraints.pcf

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+# Go Board Pin Constraints File
+# Family & Device:    iCE40HX1K
+# Package:            VQ100
+
+# Main FPGA Clock
+set_io i_clk 15
+
+# LED Pins:
+set_io o_led_1 56
+set_io o_led_2 57
+set_io o_led_3 59
+set_io o_led_4 60
+
+# Push-Button Switches
+set_io i_switch_1 53
+set_io i_switch_2 51
+set_io i_switch_3 54
+set_io i_switch_4 52
+
+# 7 Segment Outputs
+set_io o_segment1_a 3
+set_io o_segment1_b 4
+set_io o_segment1_c 93
+set_io o_segment1_d 91
+set_io o_segment1_e 90
+set_io o_segment1_f 1
+set_io o_segment1_g 2
+set_io o_segment2_a 100
+set_io o_segment2_b 99
+set_io o_segment2_c 97
+set_io o_segment2_d 95
+set_io o_segment2_e 94
+set_io o_segment2_f 8
+set_io o_segment2_g 96
+
+# UART Outputs
+set_io i_uart_rx 73
+set_io o_uart_tx 74
+
+# PMOD Signals
+set_io io_pmod_1 65
+set_io io_pmod_2 64
+set_io io_pmod_3 63
+set_io io_pmod_4 62
+set_io io_pmod_7 78
+set_io io_pmod_8 79
+set_io io_pmod_9 80
+set_io io_pmod_10 81

src/led-driver.vhd

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+library ieee;
+use ieee.std_logic_1164.all;
+ 
+entity LedDriver is
+  port (
+    i_sel0  : in  std_logic;
+    i_sel1  : in  std_logic;
+    i_sel2  : in  std_logic;
+    i_sel3  : in  std_logic;
+    o_data0 : out std_logic;
+    o_data1 : out std_logic;
+    o_data2 : out std_logic;
+    o_data3 : out std_logic);
+end entity;
+ 
+architecture RTL of LedDriver is
+begin
+  o_data0 <= '1' when i_sel0 = '1' else '0';
+  o_data1 <= '1' when i_sel1 = '1' else '0';
+  o_data2 <= '1' when i_sel2 = '1' else '0';
+  o_data3 <= '1' when i_sel3 = '1' else '0';
+end architecture;

src/main.vhd

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+-- PROJECT TOP.
+-- Counts the number of rising edges on pin 1 of the PMOD connector.
+-- With each rising edge, it turns on the next onboard LED in sequence,
+-- continuously cycling from D1 to D4.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity LedCounter is
+  -- Inputs/Outputs for the top module.
+  port (
+    io_pmod_1 : in  std_logic;  -- Clock signal from PMOD pin 1
+    o_led_1   : out std_logic;  -- Output to onboard LED 1
+    o_led_2   : out std_logic;  -- Output to onboard LED 2
+    o_led_3   : out std_logic;  -- Output to onboard LED 3
+    o_led_4   : out std_logic); -- Output to onboard LED 4
+end entity;
+
+architecture RTL of LedCounter is
+
+  -- Count up to 4 (the number of onboard LEDs).
+  constant COUNT_LIMIT : natural := 4;
+
+  -- Wires connecting the two modules RisingEdgeCounter and LedDriver.
+  signal w_sel0 : std_logic;
+  signal w_sel1 : std_logic;
+  signal w_sel2 : std_logic;
+  signal w_sel3 : std_logic;
+
+begin
+  -- Module tracking the number of rising edges on pmod_1 in a local
+  -- register, and activating the corresponding output signals.
+  RisingEdgeCounterInstance: entity work.RisingEdgeCounter
+    generic map (COUNT_LIMIT => COUNT_LIMIT)
+    port map (
+      i_clk  => io_pmod_1,
+      o_sel0 => w_sel0,
+      o_sel1 => w_sel1,
+      o_sel2 => w_sel2,
+      o_sel3 => w_sel3);
+
+  -- Module activating the correct LED based on the control signals.
+  -- A module is overkill here, but I wanted to experiment with wires.
+  LedDriverInstance: entity work.LedDriver
+    port map (
+      i_sel0  => w_sel0,
+      i_sel1  => w_sel1,
+      i_sel2  => w_sel2,
+      i_sel3  => w_sel3,
+      o_data0 => o_led_1,
+      o_data1 => o_led_2,
+      o_data2 => o_led_3,
+      o_data3 => o_led_4);
+
+end architecture;

src/rising-edge-counter.vhd

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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity RisingEdgeCounter is
+  generic (COUNT_LIMIT : natural);
+  port (
+    i_clk  : in  std_logic;
+    o_sel0 : out std_logic;
+    o_sel1 : out std_logic;
+    o_sel2 : out std_logic;
+    o_sel3 : out std_logic);
+end entity;
+
+architecture RTL of RisingEdgeCounter is
+
+  -- Register storing the number of rising edges,
+  -- from 0 to (<onboard-leds-count> - 1).
+  signal r_count : natural range 0 to COUNT_LIMIT - 1;
+
+begin
+  process (i_clk) is
+  begin
+    if rising_edge(i_clk) then
+      if r_count = COUNT_LIMIT - 1 then
+          r_count <= 0;
+      else
+          r_count <= r_count + 1;
+      end if;
+    end if;
+  end process;
+
+  o_sel0 <= '1' when r_count = 0 else '0';
+  o_sel1 <= '1' when r_count = 1 else '0';
+  o_sel2 <= '1' when r_count = 2 else '0';
+  o_sel3 <= '1' when r_count = 3 else '0';
+
+end architecture;