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DualPortMemory.v
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DualPortMemory.v
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// Quartus Prime Verilog Template
// True Dual Port RAM with single clock
module DualPortMemory
#(parameter DATA_WIDTH=16, parameter ADDR_WIDTH=10)
(
input [(DATA_WIDTH-1):0] data_a, data_b,
input [(ADDR_WIDTH-1):0] addr_a, addr_b,
input we_a, we_b, clk,
output reg [(DATA_WIDTH-1):0] q_a, q_b
);
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
integer i;
initial begin
for(i = 0; i < 1024; i = i+1) //Just initialize all with index.
ram[i] = i[15:0];
$readmemb("initialization.txt", ram); //Initialize a few with specific values.
end
// // Port A
// always @ (posedge clk)
// begin
//
// if(we_a && we_b && (addr_a == addr_b))
// begin
//
// ram[addr_a] <= data_a;
// q_a <= data_a;
// q_b <= data_a;
//
// end
//
// else
// begin
//
// if (we_a)
// begin
// ram[addr_a] <= data_a;
// q_a <= data_a;
// end
// else
// begin
// q_a <= ram[addr_a];
// end
//
// if (we_b)
// begin
// ram[addr_b] <= data_b;
// q_b <= data_b;
// end
// else
// begin
// q_b <= ram[addr_b];
// end
//
// end
// end
// Port A
always @ (posedge clk)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
else
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clk)
begin
if (we_b && (addr_a != addr_b))
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
else
begin
q_b <= ram[addr_b];
end
end
endmodule