Skip to content

Verilog: use value field for type parameter declarators #1447

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Dec 1, 2025
Merged

Verilog: use value field for type parameter declarators #1447

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
3 changes: 2 additions & 1 deletion src/verilog/parser.y
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2032,7 +2032,8 @@ type_assignment: param_identifier '=' data_type
auto base_name = stack_expr($1).id();
stack_expr($$).set(ID_identifier, base_name);
stack_expr($$).set(ID_base_name, base_name);
addswap($$, ID_type, $3);
stack_expr($$).set(ID_value, type_exprt{stack_type($3)});
stack_expr($$).type() = typet{ID_type};

// add to the scope as a type name
PARSER.scopes.add_name(base_name, "", verilog_scopet::TYPEDEF);
Expand Down
3 changes: 2 additions & 1 deletion src/verilog/verilog_elaborate.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -102,7 +102,8 @@ void verilog_typecheckt::collect_symbols(
if(type.id() == ID_type)
{
// much like a typedef
auto symbol_type = to_be_elaborated_typet{declarator.type()};
auto symbol_type =
to_be_elaborated_typet{to_type_expr(declarator.value()).type()};

type_symbolt symbol{full_identifier, symbol_type, mode};

Expand Down
Loading