Fix: control unit was able to support instruction access fault

Fix: memfy blocked if no U-MODE supported
New: testcase to check access fault

Author: dpretet

doc/TODO.md

@@ -30,11 +30,6 @@
 
 # Testcases
 
-Traps
-- [ ] Nested interrupts
-- [ ] Vector interrupts
-- [ ] Interrupts mixed over exceptions
-
 - [X] Faire varier la periode de l'EIRQ
 
 U-mode
@@ -46,8 +41,8 @@ Traps
 - [X] Do something within a loop with interrupt enabled, data needs to be OK
 - [X] WFI in u-mode, interrupt enabled, trapped in m-mode
 - [X] WFI in u-mode, interrupt disabled, NOP
+- [X] Test des exception load/store misaligned
 - [ ] Add test for vector table
-- [ ] Test des exception load/store misaligned
 - [ ] Test MSTATUS.TW
 
 MPU:
@@ -58,11 +53,10 @@ MPU:
     - [X] execute instruction outside allowed regions (U-mode)
     - [X] write data in U-mode
     - [X] read data in U-mode
-    - [ ] read data in M-mode with MPRV=1 + MPP w/ U-mode
-    - [ ] write data in M-mode with MPRV=1 + MPP w/ U-mode
-    - [ ] execute in M-mode without X + locked region
-- [ ] locked access to change configuration
-- [ ] region's permissions overlap
+    - [X] read data in M-mode with MPRV=1 + MPP=U-mode
+    - [X] write data in M-mode with MPRV=1 + MPP=U-mode
+    - [X] execute in M-mode without X + locked region
+- [X] locked access to change configuration
 
 Final:
 - Pass compliance with U-mode

doc/project_mgt_hw.md

@@ -2,11 +2,16 @@
 
 - [ ] v1.6.0: Kernel-capable Hart
     - [X] Supporter des set de config du core en test bench.
-    - [-] Support U-mode
-    - [-] Support PMP/PMA
-    - [ ] Atomic operations for single core
-    - [ ] AXI Exception management with a CLIC
-        - maange all traps into it?
+    - [X] Support U-mode
+    - [X] Support PMP/PMA
+    - [ ] Atomic operations
+        - stage to execute the instruction, controlling ldst Stages
+        - memfy exposes two interfaces for requests.
+        - memfy drives back response along register write channel
+        - support exclusive access in cache, don't substitute tag, so support single access
+        - support exclusive access in memory, track the ID with a LUT
+    - [ ] Advanced Interrupt controller
+        - [ ] AXI Exception management
     - [ ] Zc extension
     - [ ] https://github.com/eembc/coremark
 
@@ -70,6 +75,9 @@ Any new features should be carefully study to ensure a proper exception and inte
     - [ ] Analogue pocket
     - [C] Cloud
 - [ ] Add registers to configure the core in platform (use custom CSR)
+    - Caches
+    - Interconnect
+    - processing: scheduling, hazard detection
 - [ ] Support CLIC controller
 - [ ] Random peripheral
 - [ ] UART: Support 9/10 bits & parity

rtl/friscv_control.sv

@@ -227,6 +227,7 @@ module friscv_control
     logic                   ecall_umode;
     logic                   ecall_mmode;
     logic [2          -1:0] priv_mode;
+    logic [2          -1:0] mpp;
     logic                   load_access_fault;
     logic                   store_access_fault;
 
@@ -359,6 +360,12 @@ module friscv_control
                       mstatus_wr, mstatus,
                       mepc_wr, mepc};
 
+    generate if (USER_MODE) begin: MPP_UMODE
+        assign mpp = sb_mstatus[11+:2];
+    end else begin: MPP_MMODE
+        assign mpp = `MMODE;
+    end
+    endgenerate
 
     ///////////////////////////////////////////////////////////////////////////
     // Input stage
@@ -501,7 +508,7 @@ module friscv_control
     assign proc_instbus[`INST     +: `INST_W   ] = instruction;
     assign proc_instbus[`PC       +: `PC_W     ] = pc_reg;
     assign proc_instbus[`PRIV     +: `PRIV_W   ] = priv_mode;
-    assign proc_instbus[`MPP      +: `PRIV_W   ] = sb_mstatus[11+:2];
+    assign proc_instbus[`MPP      +: `PRIV_W   ] = mpp;
     assign proc_instbus[`MPRV                  ] = sb_mstatus[17];
 
     assign csr_instbus = proc_instbus;