From 18952f3bdb9ff6c6edaebc6933e43573761a8663 Mon Sep 17 00:00:00 2001
From: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com>
Date: Mon, 20 Nov 2023 18:04:27 +0200
Subject: [PATCH] update models with more modules

---
 verilog/dv/vip/sky130_gpio_model.sv | 222 +++++++++++++++++++++++++++-
 1 file changed, 221 insertions(+), 1 deletion(-)

diff --git a/verilog/dv/vip/sky130_gpio_model.sv b/verilog/dv/vip/sky130_gpio_model.sv
index 73c4500b..335deb9e 100644
--- a/verilog/dv/vip/sky130_gpio_model.sv
+++ b/verilog/dv/vip/sky130_gpio_model.sv
@@ -903,4 +903,224 @@ module sky130_fd_sc_hvl__schmittbuf_1 (
     clkbuf bufA(A_buf,A,VPWR,VGND,VPB,VNB);
     assign X = A_buf;
 
-endmodule
\ No newline at end of file
+endmodule
+
+module sky130_fd_sc_hd__dlclkp_4 (
+    GCLK,
+    GATE,
+    CLK ,
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    output GCLK;
+    input  GATE;
+    input  CLK ;
+    input  VPWR;
+    input  VGND;
+    input  VPB ;
+    input  VNB ;
+    assign GCLK = !GATE ? CLK: 1'b0;
+endmodule
+
+module sky130_ef_io__gpiov2_pad (IN_H, PAD_A_NOESD_H, PAD_A_ESD_0_H, PAD_A_ESD_1_H,
+    PAD, DM, HLD_H_N, IN, INP_DIS, IB_MODE_SEL, ENABLE_H, ENABLE_VDDA_H,
+    ENABLE_INP_H, OE_N, TIE_HI_ESD, TIE_LO_ESD, SLOW, VTRIP_SEL, HLD_OVR,
+    ANALOG_EN, ANALOG_SEL, ENABLE_VDDIO, ENABLE_VSWITCH_H, ANALOG_POL, OUT,
+    AMUXBUS_A, AMUXBUS_B, VSSA, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD,
+    VSSIO, VSSD, VSSIO_Q 
+    );
+
+input OUT;  		
+input OE_N;  		
+input HLD_H_N;		
+input ENABLE_H;
+input ENABLE_INP_H;	
+input ENABLE_VDDA_H;	
+input ENABLE_VSWITCH_H;	
+input ENABLE_VDDIO;	
+input INP_DIS;		
+input IB_MODE_SEL;
+input VTRIP_SEL;	
+input SLOW;		
+input HLD_OVR;		
+input ANALOG_EN;	
+input ANALOG_SEL;	
+input ANALOG_POL;	
+input [2:0] DM;		
+
+inout VDDIO;	
+inout VDDIO_Q;	
+inout VDDA;
+inout VCCD;
+inout VSWITCH;
+inout VCCHIB;
+inout VSSA;
+inout VSSD;
+inout VSSIO_Q;
+inout VSSIO;
+
+inout PAD;
+inout PAD_A_NOESD_H,PAD_A_ESD_0_H,PAD_A_ESD_1_H;
+inout AMUXBUS_A;
+inout AMUXBUS_B;
+
+output IN;
+output IN_H;
+output TIE_HI_ESD, TIE_LO_ESD;
+// V-erilator support only 2-state so it can't support pullup or pulldown as it Z and x doesn't exists
+wire is_pullup = (DM == 3'b010) & ~INP_DIS & ~OE_N & `ifndef VERILATOR (PAD === 1'bz) `else 0 `endif;
+wire is_pulldown = (DM == 3'b011) & ~INP_DIS & ~OE_N & `ifndef VERILATOR (PAD === 1'bz) `else 0 `endif;
+wire is_pull_dm =  (DM == 3'b010) | (DM == 3'b011);
+
+// Assign PAD value to IN when INP_DIS is not active
+assign IN = (is_pullup) ? 1'b1 : (is_pulldown) ? 1'b0 : (~INP_DIS) ? PAD : 1'b0;
+assign PAD = (~OE_N & ~is_pull_dm ) ? OUT : 1'bz;
+endmodule
+
+module sky130_ef_io__analog_pad (AMUXBUS_A, AMUXBUS_B, P_PAD, P_CORE
+                                 ,VCCD, VCCHIB, VDDA, VDDIO, VDDIO_Q, VSSA, VSSD, VSSIO, VSSIO_Q, VSWITCH
+                                );
+inout AMUXBUS_A;
+inout AMUXBUS_B;
+inout P_PAD;
+inout P_CORE;
+inout VCCD;
+inout VCCHIB;
+inout VDDA;
+inout VDDIO;
+inout VDDIO_Q;
+inout VSSA;
+inout VSSD;
+inout VSSIO;
+inout VSSIO_Q;
+inout VSWITCH;
+wire pwr_good = VDDIO===1 && VSSIO===0;
+wire pad_sw = pwr_good===1 ? 1'b1 : 1'bx;
+assign P_PAD = P_CORE;
+endmodule
+
+
+module sky130_ef_io__top_power_hvc (AMUXBUS_A, AMUXBUS_B, DRN_HVC,
+	P_CORE, P_PAD, SRC_BDY_HVC, VSSA, VDDA, VSWITCH, VDDIO_Q,
+	VCCHIB, VDDIO, VCCD, VSSIO, VSSD, VSSIO_Q
+);
+  inout AMUXBUS_A;
+  inout AMUXBUS_B;
+
+  inout DRN_HVC;
+  inout P_CORE;
+  inout P_PAD;
+  inout SRC_BDY_HVC;
+  inout VDDIO;	
+  inout VDDIO_Q;
+  inout VDDA;
+  inout VCCD;
+  inout VSWITCH;
+  inout VCCHIB;
+  inout VSSA;
+  inout VSSD;
+  inout VSSIO_Q;
+  inout VSSIO;
+
+assign P_CORE = P_PAD;
+endmodule
+
+module sky130_fd_sc_hd__fill_1 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+endmodule
+
+module sky130_fd_sc_hd__fill_2 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+endmodule
+
+module sky130_fd_sc_hd__decap_6 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+
+
+endmodule
+module sky130_fd_sc_hd__decap_12 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+
+
+endmodule
+module sky130_fd_sc_hd__decap_6 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+
+
+endmodule
+module sky130_fd_sc_hd__decap_4 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+
+
+endmodule
+module sky130_fd_sc_hd__decap_3 (
+    VPWR,
+    VGND,
+    VPB ,
+    VNB
+);
+
+    input VPWR;
+    input VGND;
+    input VPB ;
+    input VNB ;
+
+
+endmodule