diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 7704be8d5..3657d7a6a 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -153,4 +153,3 @@ module counter #(
     end
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 14e4dee2a..383dfe358 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -119,5 +119,3 @@ user_proj_example mprj (
 );
 
 endmodule	// user_project_wrapper
-
-`default_nettype wire