diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/.vs/EMAC_EMAC_EXAMPLE_TAIJI_DUE/v14/.atsuo b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/.vs/EMAC_EMAC_EXAMPLE_TAIJI_DUE/v14/.atsuo new file mode 100644 index 0000000..33a57f6 Binary files /dev/null and b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/.vs/EMAC_EMAC_EXAMPLE_TAIJI_DUE/v14/.atsuo differ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE.atsln b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE.atsln new file mode 100644 index 0000000..e24af81 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE.atsln @@ -0,0 +1,22 @@ + +Microsoft Visual Studio Solution File, Format Version 12.00 +# Atmel Studio Solution File, Format Version 11.00 +VisualStudioVersion = 14.0.23107.0 +MinimumVisualStudioVersion = 10.0.40219.1 +Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "EMAC_EMAC_EXAMPLE_TAIJI_DUE", "EMAC_EMAC_EXAMPLE_TAIJI_DUE\EMAC_EMAC_EXAMPLE_TAIJI_DUE.cproj", "{DCE6C7E3-EE26-4D79-826B-08594B9AD897}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|ARM = Debug|ARM + Release|ARM = Release|ARM + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.ActiveCfg = Debug|ARM + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.Build.0 = Debug|ARM + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.ActiveCfg = Release|ARM + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.Build.0 = Release|ARM + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection +EndGlobal diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/EMAC_EMAC_EXAMPLE_TAIJI_DUE.bin b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/EMAC_EMAC_EXAMPLE_TAIJI_DUE.bin new file mode 100644 index 0000000..c18a185 Binary files /dev/null and b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/EMAC_EMAC_EXAMPLE_TAIJI_DUE.bin differ diff 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+:1056880058090720580907206009072060090720E2 +:105698006809072068090720700907207009072092 +:1056A800780907207809072000000200FFFFFFFFA4 +:0456B8000D42080097 +:040000038000113533 +:00000001FF diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/EMAC_EMAC_EXAMPLE_TAIJI_DUE.lss b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/EMAC_EMAC_EXAMPLE_TAIJI_DUE.lss new file mode 100644 index 0000000..b51212e --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/EMAC_EMAC_EXAMPLE_TAIJI_DUE.lss @@ -0,0 +1,10924 @@ + +EMAC_EMAC_EXAMPLE_TAIJI_DUE.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 00004d20 00080000 00080000 00008000 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .ARM.exidx 00000008 00084d20 00084d20 0000cd20 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 .relocate 00000994 20070000 00084d28 00010000 2**3 + CONTENTS, ALLOC, LOAD, CODE + 3 .bss 00003f54 20070998 000856c0 00010994 2**3 + ALLOC + 4 .stack 00002004 200748ec 00089614 00010994 2**0 + ALLOC + 5 .ARM.attributes 00000029 00000000 00000000 00010994 2**0 + CONTENTS, READONLY + 6 .comment 0000005b 00000000 00000000 000109bd 2**0 + CONTENTS, READONLY + 7 .debug_info 0000cb7e 00000000 00000000 00010a18 2**0 + CONTENTS, READONLY, DEBUGGING + 8 .debug_abbrev 00002157 00000000 00000000 0001d596 2**0 + CONTENTS, READONLY, DEBUGGING + 9 .debug_loc 00005d12 00000000 00000000 0001f6ed 2**0 + CONTENTS, READONLY, DEBUGGING + 10 .debug_aranges 000009e0 00000000 00000000 000253ff 2**0 + CONTENTS, READONLY, DEBUGGING + 11 .debug_ranges 00000978 00000000 00000000 00025ddf 2**0 + CONTENTS, READONLY, DEBUGGING + 12 .debug_macro 00017dab 00000000 00000000 00026757 2**0 + CONTENTS, READONLY, DEBUGGING + 13 .debug_line 0000d199 00000000 00000000 0003e502 2**0 + CONTENTS, READONLY, DEBUGGING + 14 .debug_str 00065341 00000000 00000000 0004b69b 2**0 + CONTENTS, READONLY, DEBUGGING + 15 .debug_frame 00002264 00000000 00000000 000b09dc 2**2 + CONTENTS, READONLY, DEBUGGING + +Disassembly of section .text: + +00080000 <_sfixed>: + 80000: 200768f0 .word 0x200768f0 + 80004: 00081135 .word 0x00081135 + 80008: 00081131 .word 0x00081131 + 8000c: 00081131 .word 0x00081131 + 80010: 00081131 .word 0x00081131 + 80014: 00081131 .word 0x00081131 + 80018: 00081131 .word 0x00081131 + ... + 8002c: 00081131 .word 0x00081131 + 80030: 00081131 .word 0x00081131 + 80034: 00000000 .word 0x00000000 + 80038: 00081131 .word 0x00081131 + 8003c: 00081131 .word 0x00081131 + 80040: 00081131 .word 0x00081131 + 80044: 00081131 .word 0x00081131 + 80048: 00081131 .word 0x00081131 + 8004c: 00081131 .word 0x00081131 + 80050: 00081131 .word 0x00081131 + 80054: 00081131 .word 0x00081131 + 80058: 00081131 .word 0x00081131 + 8005c: 00081131 .word 0x00081131 + 80060: 00081131 .word 0x00081131 + 80064: 00081131 .word 0x00081131 + 80068: 00000000 .word 0x00000000 + 8006c: 00080eed .word 0x00080eed + 80070: 00080f01 .word 0x00080f01 + 80074: 00080f15 .word 0x00080f15 + 80078: 00080f29 .word 0x00080f29 + ... + 80084: 00081131 .word 0x00081131 + 80088: 00081131 .word 0x00081131 + 8008c: 00081131 .word 0x00081131 + 80090: 00081131 .word 0x00081131 + 80094: 00081131 .word 0x00081131 + 80098: 00081131 .word 0x00081131 + 8009c: 00081131 .word 0x00081131 + 800a0: 00081131 .word 0x00081131 + 800a4: 00000000 .word 0x00000000 + 800a8: 00081131 .word 0x00081131 + 800ac: 00081131 .word 0x00081131 + 800b0: 00081131 .word 0x00081131 + 800b4: 00081131 .word 0x00081131 + 800b8: 00081131 .word 0x00081131 + 800bc: 00081131 .word 0x00081131 + 800c0: 00081131 .word 0x00081131 + 800c4: 00081131 .word 0x00081131 + 800c8: 00081131 .word 0x00081131 + 800cc: 00081131 .word 0x00081131 + 800d0: 00081131 .word 0x00081131 + 800d4: 00081131 .word 0x00081131 + 800d8: 00081131 .word 0x00081131 + 800dc: 00081131 .word 0x00081131 + 800e0: 00081131 .word 0x00081131 + 800e4: 00081131 .word 0x00081131 + 800e8: 00081495 .word 0x00081495 + 800ec: 00081131 .word 0x00081131 + 800f0: 00081131 .word 0x00081131 + +000800f4 <__do_global_dtors_aux>: + 800f4: b510 push {r4, lr} + 800f6: 4c05 ldr r4, [pc, #20] ; (8010c <__do_global_dtors_aux+0x18>) + 800f8: 7823 ldrb r3, [r4, #0] + 800fa: b933 cbnz r3, 8010a <__do_global_dtors_aux+0x16> + 800fc: 4b04 ldr r3, [pc, #16] ; (80110 <__do_global_dtors_aux+0x1c>) + 800fe: b113 cbz r3, 80106 <__do_global_dtors_aux+0x12> + 80100: 4804 ldr r0, [pc, #16] ; (80114 <__do_global_dtors_aux+0x20>) + 80102: f3af 8000 nop.w + 80106: 2301 movs r3, #1 + 80108: 7023 strb r3, [r4, #0] + 8010a: bd10 pop {r4, pc} + 8010c: 20070998 .word 0x20070998 + 80110: 00000000 .word 0x00000000 + 80114: 00084d28 .word 0x00084d28 + +00080118 : + 80118: 4b08 ldr r3, [pc, #32] ; (8013c ) + 8011a: b510 push {r4, lr} + 8011c: b11b cbz r3, 80126 + 8011e: 4808 ldr r0, [pc, #32] ; (80140 ) + 80120: 4908 ldr r1, [pc, #32] ; (80144 ) + 80122: f3af 8000 nop.w + 80126: 4808 ldr r0, [pc, #32] ; (80148 ) + 80128: 6803 ldr r3, [r0, #0] + 8012a: b903 cbnz r3, 8012e + 8012c: bd10 pop {r4, pc} + 8012e: 4b07 ldr r3, [pc, #28] ; (8014c ) + 80130: 2b00 cmp r3, #0 + 80132: d0fb beq.n 8012c + 80134: e8bd 4010 ldmia.w sp!, {r4, lr} + 80138: 4718 bx r3 + 8013a: bf00 nop + 8013c: 00000000 .word 0x00000000 + 80140: 00084d28 .word 0x00084d28 + 80144: 2007099c .word 0x2007099c + 80148: 00084d28 .word 0x00084d28 + 8014c: 00000000 .word 0x00000000 + +00080150 : + pmc_disable_udpck(); +} +#endif // CONFIG_USBCLK_SOURCE + +void sysclk_init(void) +{ + 80150: b510 push {r4, lr} + struct pll_config pllcfg; + + /* Set flash wait state to max in case the below clock switching. */ + system_init_flash(CHIP_FREQ_CPU_MAX); + 80152: 480e ldr r0, [pc, #56] ; (8018c ) + 80154: 4b0e ldr r3, [pc, #56] ; (80190 ) + 80156: 4798 blx r3 + pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz); + break; + + + case OSC_MAINCK_XTAL: + pmc_switch_mainck_to_xtal(PMC_OSC_XTAL, + 80158: 2000 movs r0, #0 + 8015a: 213e movs r1, #62 ; 0x3e + 8015c: 4b0d ldr r3, [pc, #52] ; (80194 ) + 8015e: 4798 blx r3 + case OSC_MAINCK_4M_RC: + case OSC_MAINCK_8M_RC: + case OSC_MAINCK_12M_RC: + case OSC_MAINCK_XTAL: + case OSC_MAINCK_BYPASS: + return pmc_osc_is_ready_mainck(); + 80160: 4c0d ldr r4, [pc, #52] ; (80198 ) + 80162: 47a0 blx r4 + * + * \param id A number identifying the oscillator to wait for. + */ +static inline void osc_wait_ready(uint8_t id) +{ + while (!osc_is_ready(id)) { + 80164: 2800 cmp r0, #0 + 80166: d0fc beq.n 80162 +static inline void pll_enable(const struct pll_config *p_cfg, uint32_t ul_pll_id) +{ + Assert(ul_pll_id < NR_PLLS); + + if (ul_pll_id == PLLA_ID) { + pmc_disable_pllack(); // Always stop PLL first! + 80168: 4b0c ldr r3, [pc, #48] ; (8019c ) + 8016a: 4798 blx r3 + PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | p_cfg->ctrl; + 8016c: 4a0c ldr r2, [pc, #48] ; (801a0 ) + 8016e: 4b0d ldr r3, [pc, #52] ; (801a4 ) + 80170: 629a str r2, [r3, #40] ; 0x28 +static inline uint32_t pll_is_locked(uint32_t ul_pll_id) +{ + Assert(ul_pll_id < NR_PLLS); + + if (ul_pll_id == PLLA_ID) { + return pmc_is_locked_pllack(); + 80172: 4c0d ldr r4, [pc, #52] ; (801a8 ) + 80174: 47a0 blx r4 + */ +static inline int pll_wait_for_lock(unsigned int pll_id) +{ + Assert(pll_id < NR_PLLS); + + while (!pll_is_locked(pll_id)) { + 80176: 2800 cmp r0, #0 + 80178: d0fc beq.n 80174 + else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_PLLACK) { + pll_enable_source(CONFIG_PLL0_SOURCE); + pll_config_defaults(&pllcfg, 0); + pll_enable(&pllcfg, 0); + pll_wait_for_lock(0); + pmc_switch_mck_to_pllack(CONFIG_SYSCLK_PRES); + 8017a: 2010 movs r0, #16 + 8017c: 4b0b ldr r3, [pc, #44] ; (801ac ) + 8017e: 4798 blx r3 + pll_wait_for_lock(1); + pmc_switch_mck_to_upllck(CONFIG_SYSCLK_PRES); + } + + /* Update the SystemFrequency variable */ + SystemCoreClockUpdate(); + 80180: 4b0b ldr r3, [pc, #44] ; (801b0 ) + 80182: 4798 blx r3 + + /* Set a flash wait state depending on the new cpu frequency */ + system_init_flash(sysclk_get_cpu_hz()); + 80184: 4801 ldr r0, [pc, #4] ; (8018c ) + 80186: 4b02 ldr r3, [pc, #8] ; (80190 ) + 80188: 4798 blx r3 + 8018a: bd10 pop {r4, pc} + 8018c: 0501bd00 .word 0x0501bd00 + 80190: 200700a5 .word 0x200700a5 + 80194: 00080fa5 .word 0x00080fa5 + 80198: 00080ff9 .word 0x00080ff9 + 8019c: 00081009 .word 0x00081009 + 801a0: 200d3f01 .word 0x200d3f01 + 801a4: 400e0600 .word 0x400e0600 + 801a8: 00081019 .word 0x00081019 + 801ac: 00080f3d .word 0x00080f3d + 801b0: 000811e5 .word 0x000811e5 + +000801b4 <_read>: +int __attribute__((weak)) +_read (int file, char * ptr, int len) +{ + int nChars = 0; + + if (file != 0) { + 801b4: b9a8 cbnz r0, 801e2 <_read+0x2e> +int __attribute__((weak)) +_read (int file, char * ptr, int len); // Remove GCC compiler warning + +int __attribute__((weak)) +_read (int file, char * ptr, int len) +{ + 801b6: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 801ba: 460c mov r4, r1 + 801bc: 4690 mov r8, r2 + + if (file != 0) { + return -1; + } + + for (; len > 0; --len) { + 801be: 2a00 cmp r2, #0 + 801c0: dd0a ble.n 801d8 <_read+0x24> + 801c2: 188f adds r7, r1, r2 + ptr_get(stdio_base, ptr); + 801c4: 4e08 ldr r6, [pc, #32] ; (801e8 <_read+0x34>) + 801c6: 4d09 ldr r5, [pc, #36] ; (801ec <_read+0x38>) + 801c8: 6830 ldr r0, [r6, #0] + 801ca: 4621 mov r1, r4 + 801cc: 682b ldr r3, [r5, #0] + 801ce: 4798 blx r3 + ptr++; + 801d0: 3401 adds r4, #1 + + if (file != 0) { + return -1; + } + + for (; len > 0; --len) { + 801d2: 42bc cmp r4, r7 + 801d4: d1f8 bne.n 801c8 <_read+0x14> + 801d6: e001 b.n 801dc <_read+0x28> + 801d8: f04f 0800 mov.w r8, #0 + ptr_get(stdio_base, ptr); + ptr++; + nChars++; + } + return nChars; + 801dc: 4640 mov r0, r8 + 801de: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +_read (int file, char * ptr, int len) +{ + int nChars = 0; + + if (file != 0) { + return -1; + 801e2: f04f 30ff mov.w r0, #4294967295 + 801e6: 4770 bx lr + 801e8: 200748e4 .word 0x200748e4 + 801ec: 200748dc .word 0x200748dc + +000801f0 <_write>: +int __attribute__((weak)) +_write (int file, const char *ptr, int len) +{ + int nChars = 0; + + if ((file != 1) && (file != 2) && (file!=3)) { + 801f0: 3801 subs r0, #1 + 801f2: 2802 cmp r0, #2 + 801f4: d818 bhi.n 80228 <_write+0x38> +int __attribute__((weak)) +_write (int file, const char *ptr, int len); + +int __attribute__((weak)) +_write (int file, const char *ptr, int len) +{ + 801f6: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 801fa: 460e mov r6, r1 + 801fc: 4614 mov r4, r2 + + if ((file != 1) && (file != 2) && (file!=3)) { + return -1; + } + + for (; len != 0; --len) { + 801fe: b182 cbz r2, 80222 <_write+0x32> + 80200: 460d mov r5, r1 + if (ptr_put(stdio_base, *ptr++) < 0) { + 80202: f8df 8038 ldr.w r8, [pc, #56] ; 8023c <_write+0x4c> + 80206: 4f0c ldr r7, [pc, #48] ; (80238 <_write+0x48>) + 80208: f8d8 0000 ldr.w r0, [r8] + 8020c: f815 1b01 ldrb.w r1, [r5], #1 + 80210: 683b ldr r3, [r7, #0] + 80212: 4798 blx r3 + 80214: 2800 cmp r0, #0 + 80216: db0a blt.n 8022e <_write+0x3e> + 80218: 1ba8 subs r0, r5, r6 + + if ((file != 1) && (file != 2) && (file!=3)) { + return -1; + } + + for (; len != 0; --len) { + 8021a: 3c01 subs r4, #1 + 8021c: d1f4 bne.n 80208 <_write+0x18> + 8021e: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 80222: 2000 movs r0, #0 + if (ptr_put(stdio_base, *ptr++) < 0) { + return -1; + } + ++nChars; + } + return nChars; + 80224: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +_write (int file, const char *ptr, int len) +{ + int nChars = 0; + + if ((file != 1) && (file != 2) && (file!=3)) { + return -1; + 80228: f04f 30ff mov.w r0, #4294967295 + return -1; + } + ++nChars; + } + return nChars; +} + 8022c: 4770 bx lr + return -1; + } + + for (; len != 0; --len) { + if (ptr_put(stdio_base, *ptr++) < 0) { + return -1; + 8022e: f04f 30ff mov.w r0, #4294967295 + } + ++nChars; + } + return nChars; +} + 80232: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 80236: bf00 nop + 80238: 200748e0 .word 0x200748e0 + 8023c: 200748e4 .word 0x200748e4 + +00080240 : +#include "conf_board.h" +#include "gpio.h" +#include "ioport.h" + +void board_init(void) +{ + 80240: b510 push {r4, lr} +#ifndef CONF_BOARD_KEEP_WATCHDOG_AT_INIT + /* Disable the watchdog */ + WDT->WDT_MR = WDT_MR_WDDIS; + 80242: f44f 4200 mov.w r2, #32768 ; 0x8000 + 80246: 4b26 ldr r3, [pc, #152] ; (802e0 ) + 80248: 605a str r2, [r3, #4] + * + * \param ul_id Id (number) of the peripheral clock. + */ +static inline void sysclk_enable_peripheral_clock(uint32_t ul_id) +{ + pmc_enable_periph_clk(ul_id); + 8024a: 200b movs r0, #11 + 8024c: 4c25 ldr r4, [pc, #148] ; (802e4 ) + 8024e: 47a0 blx r4 + 80250: 200c movs r0, #12 + 80252: 47a0 blx r4 + 80254: 200d movs r0, #13 + 80256: 47a0 blx r4 + 80258: 200e movs r0, #14 + 8025a: 47a0 blx r4 + * In new designs IOPORT is used instead. + * Here IOPORT must be initialized for others to use before setting up IO. + */ + ioport_init(); + /* Configure LED pins */ + gpio_configure_pin(LED0_GPIO, LED0_FLAGS); + 8025c: 203b movs r0, #59 ; 0x3b + 8025e: f04f 5160 mov.w r1, #939524096 ; 0x38000000 + 80262: 4c21 ldr r4, [pc, #132] ; (802e8 ) + 80264: 47a0 blx r4 + gpio_configure_pin(LED1_GPIO, LED1_FLAGS); + 80266: 2055 movs r0, #85 ; 0x55 + 80268: f04f 5160 mov.w r1, #939524096 ; 0x38000000 + 8026c: 47a0 blx r4 + gpio_configure_pin(LED2_GPIO, LED2_FLAGS); + 8026e: 2056 movs r0, #86 ; 0x56 + 80270: f04f 5160 mov.w r1, #939524096 ; 0x38000000 + 80274: 47a0 blx r4 + + /* Configure Push Button pins */ + gpio_configure_pin(GPIO_PUSH_BUTTON_1, GPIO_PUSH_BUTTON_1_FLAGS); + 80276: 2068 movs r0, #104 ; 0x68 + 80278: 491c ldr r1, [pc, #112] ; (802ec ) + 8027a: 47a0 blx r4 + gpio_configure_pin(GPIO_PUSH_BUTTON_2, GPIO_PUSH_BUTTON_2_FLAGS); + 8027c: 205c movs r0, #92 ; 0x5c + 8027e: 491c ldr r1, [pc, #112] ; (802f0 ) + 80280: 47a0 blx r4 + +#ifdef CONF_BOARD_UART_CONSOLE + /* Configure UART pins */ + gpio_configure_group(PINS_UART_PIO, PINS_UART, PINS_UART_FLAGS); + 80282: 481c ldr r0, [pc, #112] ; (802f4 ) + 80284: f44f 7140 mov.w r1, #768 ; 0x300 + 80288: 4a1b ldr r2, [pc, #108] ; (802f8 ) + 8028a: 4b1c ldr r3, [pc, #112] ; (802fc ) + 8028c: 4798 blx r3 + gpio_configure_pin(SPI0_SPCK_GPIO, SPI0_SPCK_FLAGS); + gpio_configure_pin(SPI0_NPCS0_GPIO, SPI0_NPCS0_FLAGS); +#endif + +#ifdef CONF_BOARD_EMAC + gpio_configure_pin(PIN_EEMAC_EREFCK, PIN_EMAC_FLAGS); + 8028e: 2020 movs r0, #32 + 80290: f04f 6100 mov.w r1, #134217728 ; 0x8000000 + 80294: 47a0 blx r4 + gpio_configure_pin(PIN_EMAC_ETX0, PIN_EMAC_FLAGS); + 80296: 2022 movs r0, #34 ; 0x22 + 80298: f04f 6100 mov.w r1, #134217728 ; 0x8000000 + 8029c: 47a0 blx r4 + gpio_configure_pin(PIN_EMAC_ETX1, PIN_EMAC_FLAGS); + 8029e: 2023 movs r0, #35 ; 0x23 + 802a0: f04f 6100 mov.w r1, #134217728 ; 0x8000000 + 802a4: 47a0 blx r4 + gpio_configure_pin(PIN_EMAC_ETXEN, PIN_EMAC_FLAGS); + 802a6: 2021 movs r0, #33 ; 0x21 + 802a8: f04f 6100 mov.w r1, #134217728 ; 0x8000000 + 802ac: 47a0 blx r4 + gpio_configure_pin(PIN_EMAC_ECRSDV, PIN_EMAC_FLAGS); + 802ae: 2024 movs r0, #36 ; 0x24 + 802b0: f04f 6100 mov.w r1, #134217728 ; 0x8000000 + 802b4: 47a0 blx r4 + gpio_configure_pin(PIN_EMAC_ERX0, PIN_EMAC_FLAGS); + 802b6: 2025 movs r0, #37 ; 0x25 + 802b8: f04f 6100 mov.w r1, #134217728 ; 0x8000000 + 802bc: 47a0 blx r4 + gpio_configure_pin(PIN_EMAC_ERX1, PIN_EMAC_FLAGS); + 802be: 2026 movs r0, #38 ; 0x26 + 802c0: f04f 6100 mov.w r1, #134217728 ; 0x8000000 + 802c4: 47a0 blx r4 + gpio_configure_pin(PIN_EMAC_ERXER, PIN_EMAC_FLAGS); + 802c6: 2027 movs r0, #39 ; 0x27 + 802c8: f04f 6100 mov.w r1, #134217728 ; 0x8000000 + 802cc: 47a0 blx r4 + gpio_configure_pin(PIN_EMAC_EMDC, PIN_EMAC_FLAGS); + 802ce: 2028 movs r0, #40 ; 0x28 + 802d0: f04f 6100 mov.w r1, #134217728 ; 0x8000000 + 802d4: 47a0 blx r4 + gpio_configure_pin(PIN_EMAC_EMDIO, PIN_EMAC_FLAGS); + 802d6: 2029 movs r0, #41 ; 0x29 + 802d8: f04f 6100 mov.w r1, #134217728 ; 0x8000000 + 802dc: 47a0 blx r4 + 802de: bd10 pop {r4, pc} + 802e0: 400e1a50 .word 0x400e1a50 + 802e4: 00081029 .word 0x00081029 + 802e8: 00080d29 .word 0x00080d29 + 802ec: 28000079 .word 0x28000079 + 802f0: 28000001 .word 0x28000001 + 802f4: 400e0e00 .word 0x400e0e00 + 802f8: 08000001 .word 0x08000001 + 802fc: 00080dfd .word 0x00080dfd + +00080300 : + * + * Return EMAC_OK if successfully, EMAC_TIMEOUT if timeout. + */ +uint8_t ethernet_phy_set_link(Emac *p_emac, uint8_t uc_phy_addr, + uint8_t uc_apply_setting_flag) +{ + 80300: b5f0 push {r4, r5, r6, r7, lr} + 80302: b083 sub sp, #12 + 80304: 4604 mov r4, r0 + 80306: 460f mov r7, r1 + 80308: 4616 mov r6, r2 + * \param uc_enable 0 to disable EMAC management, else to enable it. + */ +static inline void emac_enable_management(Emac* p_emac, uint8_t uc_enable) +{ + if (uc_enable) { + p_emac->EMAC_NCR |= EMAC_NCR_MPE; + 8030a: 6803 ldr r3, [r0, #0] + 8030c: f043 0310 orr.w r3, r3, #16 + 80310: 6003 str r3, [r0, #0] + + emac_enable_management(p_emac, true); + + uc_phy_address = uc_phy_addr; + + uc_rc = emac_phy_read(p_emac, uc_phy_address, MII_BMSR, &ul_stat1); + 80312: 2201 movs r2, #1 + 80314: ab01 add r3, sp, #4 + 80316: 4d35 ldr r5, [pc, #212] ; (803ec ) + 80318: 47a8 blx r5 + if (uc_rc != EMAC_OK) { + 8031a: b120 cbz r0, 80326 + } else { + p_emac->EMAC_NCR &= ~EMAC_NCR_MPE; + 8031c: 6822 ldr r2, [r4, #0] + 8031e: f022 0210 bic.w r2, r2, #16 + 80322: 6022 str r2, [r4, #0] + /* Disable PHY management and start the EMAC transfer */ + emac_enable_management(p_emac, false); + + return uc_rc; + 80324: e05f b.n 803e6 + } + + if ((ul_stat1 & MII_LINK_STATUS) == 0) { + 80326: 9b01 ldr r3, [sp, #4] + 80328: f013 0f04 tst.w r3, #4 + 8032c: d105 bne.n 8033a + 8032e: 6823 ldr r3, [r4, #0] + 80330: f023 0310 bic.w r3, r3, #16 + 80334: 6023 str r3, [r4, #0] + /* Disable PHY management and start the EMAC transfer */ + emac_enable_management(p_emac, false); + + return EMAC_INVALID; + 80336: 20ff movs r0, #255 ; 0xff + 80338: e055 b.n 803e6 + } + + if (uc_apply_setting_flag == 0) { + 8033a: b92e cbnz r6, 80348 + 8033c: 6823 ldr r3, [r4, #0] + 8033e: f023 0310 bic.w r3, r3, #16 + 80342: 6023 str r3, [r4, #0] + /* Disable PHY management and start the EMAC transfer */ + emac_enable_management(p_emac, false); + + return uc_rc; + 80344: 2000 movs r0, #0 + 80346: e04e b.n 803e6 + } + + /* Re-configure Link speed */ + uc_rc = emac_phy_read(p_emac, uc_phy_address, MII_DSCSR, &ul_stat2); + 80348: 4620 mov r0, r4 + 8034a: 4639 mov r1, r7 + 8034c: 2211 movs r2, #17 + 8034e: 466b mov r3, sp + 80350: 4d26 ldr r5, [pc, #152] ; (803ec ) + 80352: 47a8 blx r5 + if (uc_rc != EMAC_OK) { + 80354: b120 cbz r0, 80360 + 80356: 6822 ldr r2, [r4, #0] + 80358: f022 0210 bic.w r2, r2, #16 + 8035c: 6022 str r2, [r4, #0] + /* Disable PHY management and start the EMAC transfer */ + emac_enable_management(p_emac, false); + + return uc_rc; + 8035e: e042 b.n 803e6 + } + + if ((ul_stat1 & MII_100BASE_TX_FD) && (ul_stat2 & MII_100FDX)) { + 80360: 9b01 ldr r3, [sp, #4] + /* Set EMAC for 100BaseTX and Full Duplex */ + uc_speed = true; + uc_fd = true; + } + + if ((ul_stat1 & MII_10BASE_T_FD) && (ul_stat2 & MII_10FDX)) { + 80362: f413 5f80 tst.w r3, #4096 ; 0x1000 + 80366: bf1d ittte ne + 80368: 9a00 ldrne r2, [sp, #0] + 8036a: f482 5200 eorne.w r2, r2, #8192 ; 0x2000 + 8036e: f3c2 3240 ubfxne r2, r2, #13, #1 + 80372: 2201 moveq r2, #1 + /* Set MII for 10BaseT and Full Duplex */ + uc_speed = false; + uc_fd = true; + } + + if ((ul_stat1 & MII_100BASE_T4_HD) && (ul_stat2 & MII_100HDX)) { + 80374: f413 5f00 tst.w r3, #8192 ; 0x2000 + 80378: d003 beq.n 80382 + 8037a: 9900 ldr r1, [sp, #0] + 8037c: f411 4f80 tst.w r1, #16384 ; 0x4000 + 80380: d128 bne.n 803d4 + /* Set MII for 100BaseTX and Half Duplex */ + uc_speed = true; + uc_fd = false; + } + + if ((ul_stat1 & MII_10BASE_T_HD) && (ul_stat2 & MII_10HDX)) { + 80382: f413 6f00 tst.w r3, #2048 ; 0x800 + 80386: d003 beq.n 80390 + 80388: 9b00 ldr r3, [sp, #0] + 8038a: f413 5f80 tst.w r3, #4096 ; 0x1000 + 8038e: d108 bne.n 803a2 + * \param p_emac Pointer to the EMAC instance. + * \param uc_speed 1 to indicate 100Mbps, 0 to 10Mbps. + */ +static inline void emac_set_speed(Emac* p_emac, uint8_t uc_speed) +{ + if (uc_speed) { + 80390: b14a cbz r2, 803a6 + 80392: 2301 movs r3, #1 + 80394: e000 b.n 80398 + } + + if ((ul_stat1 & MII_100BASE_T4_HD) && (ul_stat2 & MII_100HDX)) { + /* Set MII for 100BaseTX and Half Duplex */ + uc_speed = true; + uc_fd = false; + 80396: 2300 movs r3, #0 + p_emac->EMAC_NCFGR |= EMAC_NCFGR_SPD; + 80398: 6862 ldr r2, [r4, #4] + 8039a: f042 0201 orr.w r2, r2, #1 + 8039e: 6062 str r2, [r4, #4] + 803a0: e008 b.n 803b4 + } + + if ((ul_stat1 & MII_10BASE_T_HD) && (ul_stat2 & MII_10HDX)) { + /* Set MII for 10BaseT and Half Duplex */ + uc_speed = false; + uc_fd = false; + 803a2: 2300 movs r3, #0 + 803a4: e002 b.n 803ac + * \param p_emac Pointer to the EMAC instance. + * \param uc_speed 1 to indicate 100Mbps, 0 to 10Mbps. + */ +static inline void emac_set_speed(Emac* p_emac, uint8_t uc_speed) +{ + if (uc_speed) { + 803a6: 2301 movs r3, #1 + 803a8: e000 b.n 803ac + 803aa: 2300 movs r3, #0 + p_emac->EMAC_NCFGR |= EMAC_NCFGR_SPD; + } else { + p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_SPD; + 803ac: 6862 ldr r2, [r4, #4] + 803ae: f022 0201 bic.w r2, r2, #1 + 803b2: 6062 str r2, [r4, #4] + * \param p_emac Pointer to the EMAC instance. + * \param uc_enable 0 to disable the Full-Duplex mode, else to enable it. + */ +static inline void emac_enable_full_duplex(Emac* p_emac, uint8_t uc_enable) +{ + if (uc_enable) { + 803b4: b123 cbz r3, 803c0 + p_emac->EMAC_NCFGR |= EMAC_NCFGR_FD; + 803b6: 6863 ldr r3, [r4, #4] + 803b8: f043 0302 orr.w r3, r3, #2 + 803bc: 6063 str r3, [r4, #4] + 803be: e003 b.n 803c8 + } else { + p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_FD; + 803c0: 6863 ldr r3, [r4, #4] + 803c2: f023 0302 bic.w r3, r3, #2 + 803c6: 6063 str r3, [r4, #4] +static inline void emac_enable_management(Emac* p_emac, uint8_t uc_enable) +{ + if (uc_enable) { + p_emac->EMAC_NCR |= EMAC_NCR_MPE; + } else { + p_emac->EMAC_NCR &= ~EMAC_NCR_MPE; + 803c8: 6823 ldr r3, [r4, #0] + 803ca: f023 0310 bic.w r3, r3, #16 + 803ce: 6023 str r3, [r4, #0] + emac_set_speed(p_emac, uc_speed); + emac_enable_full_duplex(p_emac, uc_fd); + + /* Start the EMAC transfers */ + emac_enable_management(p_emac, false); + return uc_rc; + 803d0: 2000 movs r0, #0 + 803d2: e008 b.n 803e6 + /* Set MII for 100BaseTX and Half Duplex */ + uc_speed = true; + uc_fd = false; + } + + if ((ul_stat1 & MII_10BASE_T_HD) && (ul_stat2 & MII_10HDX)) { + 803d4: f413 6f00 tst.w r3, #2048 ; 0x800 + 803d8: d0dd beq.n 80396 + 803da: 9b00 ldr r3, [sp, #0] + 803dc: f413 5f80 tst.w r3, #4096 ; 0x1000 + 803e0: d1e3 bne.n 803aa + } + + if ((ul_stat1 & MII_100BASE_T4_HD) && (ul_stat2 & MII_100HDX)) { + /* Set MII for 100BaseTX and Half Duplex */ + uc_speed = true; + uc_fd = false; + 803e2: 2300 movs r3, #0 + 803e4: e7d8 b.n 80398 + emac_enable_full_duplex(p_emac, uc_fd); + + /* Start the EMAC transfers */ + emac_enable_management(p_emac, false); + return uc_rc; +} + 803e6: b003 add sp, #12 + 803e8: bdf0 pop {r4, r5, r6, r7, pc} + 803ea: bf00 nop + 803ec: 00080789 .word 0x00080789 + +000803f0 : + * \param uc_phy_addr PHY address. + * + * Return EMAC_OK if successfully, EMAC_TIMEOUT if timeout. + */ +uint8_t ethernet_phy_auto_negotiate(Emac *p_emac, uint8_t uc_phy_addr) +{ + 803f0: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 803f4: b082 sub sp, #8 + 803f6: 4604 mov r4, r0 + 803f8: 460d mov r5, r1 + * \param uc_enable 0 to disable EMAC management, else to enable it. + */ +static inline void emac_enable_management(Emac* p_emac, uint8_t uc_enable) +{ + if (uc_enable) { + p_emac->EMAC_NCR |= EMAC_NCR_MPE; + 803fa: 6803 ldr r3, [r0, #0] + 803fc: f043 0310 orr.w r3, r3, #16 + 80400: 6003 str r3, [r0, #0] + uint8_t uc_rc = EMAC_TIMEOUT; + + emac_enable_management(p_emac, true); + + /* Set up control register */ + uc_rc = emac_phy_read(p_emac, uc_phy_addr, MII_BMCR, &ul_value); + 80402: 2200 movs r2, #0 + 80404: ab01 add r3, sp, #4 + 80406: 4e58 ldr r6, [pc, #352] ; (80568 ) + 80408: 47b0 blx r6 + if (uc_rc != EMAC_OK) { + 8040a: b120 cbz r0, 80416 + } else { + p_emac->EMAC_NCR &= ~EMAC_NCR_MPE; + 8040c: 6822 ldr r2, [r4, #0] + 8040e: f022 0210 bic.w r2, r2, #16 + 80412: 6022 str r2, [r4, #0] + emac_enable_management(p_emac, false); + return uc_rc; + 80414: e0a5 b.n 80562 + } + + ul_value &= ~MII_AUTONEG; /* Remove auto-negotiation enable */ + ul_value &= ~(MII_LOOPBACK | MII_POWER_DOWN); + 80416: 9b01 ldr r3, [sp, #4] + 80418: f423 43b0 bic.w r3, r3, #22528 ; 0x5800 + ul_value |= MII_ISOLATE; /* Electrically isolate PHY */ + 8041c: f443 6380 orr.w r3, r3, #1024 ; 0x400 + 80420: 9301 str r3, [sp, #4] + uc_rc = emac_phy_write(p_emac, uc_phy_addr, MII_BMCR, ul_value); + 80422: 4620 mov r0, r4 + 80424: 4629 mov r1, r5 + 80426: 2200 movs r2, #0 + 80428: 4e50 ldr r6, [pc, #320] ; (8056c ) + 8042a: 47b0 blx r6 + if (uc_rc != EMAC_OK) { + 8042c: b120 cbz r0, 80438 + 8042e: 6822 ldr r2, [r4, #0] + 80430: f022 0210 bic.w r2, r2, #16 + 80434: 6022 str r2, [r4, #0] + emac_enable_management(p_emac, false); + return uc_rc; + 80436: e094 b.n 80562 + * MII advertising for Next page. + * 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3. + */ + ul_phy_anar = MII_TX_FDX | MII_TX_HDX | MII_10_FDX | MII_10_HDX | + MII_AN_IEEE_802_3; + uc_rc = emac_phy_write(p_emac, uc_phy_addr, MII_ANAR, ul_phy_anar); + 80438: 4620 mov r0, r4 + 8043a: 4629 mov r1, r5 + 8043c: 2204 movs r2, #4 + 8043e: f240 13e1 movw r3, #481 ; 0x1e1 + 80442: 4e4a ldr r6, [pc, #296] ; (8056c ) + 80444: 47b0 blx r6 + if (uc_rc != EMAC_OK) { + 80446: b120 cbz r0, 80452 + 80448: 6822 ldr r2, [r4, #0] + 8044a: f022 0210 bic.w r2, r2, #16 + 8044e: 6022 str r2, [r4, #0] + emac_enable_management(p_emac, false); + return uc_rc; + 80450: e087 b.n 80562 + } + + /* Read & modify control register */ + uc_rc = emac_phy_read(p_emac, uc_phy_addr, MII_BMCR, &ul_value); + 80452: 4620 mov r0, r4 + 80454: 4629 mov r1, r5 + 80456: 2200 movs r2, #0 + 80458: ab01 add r3, sp, #4 + 8045a: 4e43 ldr r6, [pc, #268] ; (80568 ) + 8045c: 47b0 blx r6 + if (uc_rc != EMAC_OK) { + 8045e: b120 cbz r0, 8046a + 80460: 6822 ldr r2, [r4, #0] + 80462: f022 0210 bic.w r2, r2, #16 + 80466: 6022 str r2, [r4, #0] + emac_enable_management(p_emac, false); + return uc_rc; + 80468: e07b b.n 80562 + } + + ul_value |= MII_SPEED_SELECT | MII_AUTONEG | MII_DUPLEX_MODE; + 8046a: 9b01 ldr r3, [sp, #4] + 8046c: f443 5344 orr.w r3, r3, #12544 ; 0x3100 + 80470: 9301 str r3, [sp, #4] + uc_rc = emac_phy_write(p_emac, uc_phy_addr, MII_BMCR, ul_value); + 80472: 4620 mov r0, r4 + 80474: 4629 mov r1, r5 + 80476: 2200 movs r2, #0 + 80478: 4e3c ldr r6, [pc, #240] ; (8056c ) + 8047a: 47b0 blx r6 + if (uc_rc != EMAC_OK) { + 8047c: b120 cbz r0, 80488 + 8047e: 6822 ldr r2, [r4, #0] + 80480: f022 0210 bic.w r2, r2, #16 + 80484: 6022 str r2, [r4, #0] + emac_enable_management(p_emac, false); + return uc_rc; + 80486: e06c b.n 80562 + } + + /* Restart auto negotiation */ + ul_value |= MII_RESTART_AUTONEG; + ul_value &= ~MII_ISOLATE; + 80488: 9b01 ldr r3, [sp, #4] + 8048a: f423 6380 bic.w r3, r3, #1024 ; 0x400 + 8048e: f443 7300 orr.w r3, r3, #512 ; 0x200 + 80492: 9301 str r3, [sp, #4] + uc_rc = emac_phy_write(p_emac, uc_phy_addr, MII_BMCR, ul_value); + 80494: 4620 mov r0, r4 + 80496: 4629 mov r1, r5 + 80498: 2200 movs r2, #0 + 8049a: 4e34 ldr r6, [pc, #208] ; (8056c ) + 8049c: 47b0 blx r6 + if (uc_rc != EMAC_OK) { + 8049e: b120 cbz r0, 804aa + 804a0: 6822 ldr r2, [r4, #0] + 804a2: f022 0210 bic.w r2, r2, #16 + 804a6: 6022 str r2, [r4, #0] + emac_enable_management(p_emac, false); + return uc_rc; + 804a8: e05b b.n 80562 + 804aa: 4e31 ldr r6, [pc, #196] ; (80570 ) + } + + /* Check if auto negotiation is completed */ + while (1) { + uc_rc = emac_phy_read(p_emac, uc_phy_addr, MII_BMSR, &ul_value); + 804ac: f04f 0801 mov.w r8, #1 + 804b0: 4f2d ldr r7, [pc, #180] ; (80568 ) + 804b2: 4620 mov r0, r4 + 804b4: 4629 mov r1, r5 + 804b6: 4642 mov r2, r8 + 804b8: ab01 add r3, sp, #4 + 804ba: 47b8 blx r7 + if (uc_rc != EMAC_OK) { + 804bc: b120 cbz r0, 804c8 + 804be: 6822 ldr r2, [r4, #0] + 804c0: f022 0210 bic.w r2, r2, #16 + 804c4: 6022 str r2, [r4, #0] + emac_enable_management(p_emac, false); + return uc_rc; + 804c6: e04c b.n 80562 + } + /* Done successfully */ + if (ul_value & MII_AUTONEG_COMP) { + 804c8: 9b01 ldr r3, [sp, #4] + 804ca: f013 0f20 tst.w r3, #32 + 804ce: d107 bne.n 804e0 + break; + } + + /* Timeout check */ + if (ul_retry_max) { + if (++ul_retry_count >= ul_retry_max) { + 804d0: 3e01 subs r6, #1 + 804d2: d1ee bne.n 804b2 + 804d4: 6823 ldr r3, [r4, #0] + 804d6: f023 0310 bic.w r3, r3, #16 + 804da: 6023 str r3, [r4, #0] + emac_enable_management(p_emac, false); + return EMAC_TIMEOUT; + 804dc: 2001 movs r0, #1 + 804de: e040 b.n 80562 + } + } + } + + /* Get the auto negotiate link partner base page */ + uc_rc = emac_phy_read(p_emac, uc_phy_addr, MII_ANLPAR, &ul_phy_analpar); + 804e0: 4620 mov r0, r4 + 804e2: 4629 mov r1, r5 + 804e4: 2205 movs r2, #5 + 804e6: 466b mov r3, sp + 804e8: 4d1f ldr r5, [pc, #124] ; (80568 ) + 804ea: 47a8 blx r5 + if (uc_rc != EMAC_OK) { + 804ec: b120 cbz r0, 804f8 + 804ee: 6822 ldr r2, [r4, #0] + 804f0: f022 0210 bic.w r2, r2, #16 + 804f4: 6022 str r2, [r4, #0] + emac_enable_management(p_emac, false); + return uc_rc; + 804f6: e034 b.n 80562 + } + + /* Set up the EMAC link speed */ + if ((ul_phy_anar & ul_phy_analpar) & MII_TX_FDX) { + 804f8: 9b00 ldr r3, [sp, #0] + 804fa: f413 7f80 tst.w r3, #256 ; 0x100 + 804fe: d109 bne.n 80514 + /* Set MII for 100BaseTX and Full Duplex */ + uc_speed = true; + uc_fd = true; + } else if ((ul_phy_anar & ul_phy_analpar) & MII_10_FDX) { + 80500: f013 0f40 tst.w r3, #64 ; 0x40 + 80504: d10c bne.n 80520 + * \param p_emac Pointer to the EMAC instance. + * \param uc_speed 1 to indicate 100Mbps, 0 to 10Mbps. + */ +static inline void emac_set_speed(Emac* p_emac, uint8_t uc_speed) +{ + if (uc_speed) { + 80506: f013 0f80 tst.w r3, #128 ; 0x80 + uc_speed = false; + uc_fd = true; + } else if ((ul_phy_anar & ul_phy_analpar) & MII_TX_HDX) { + /* Set MII for 100BaseTX and half Duplex */ + uc_speed = true; + uc_fd = false; + 8050a: bf08 it eq + 8050c: 2300 moveq r3, #0 + 8050e: d009 beq.n 80524 + 80510: 2300 movs r3, #0 + 80512: e000 b.n 80516 + + /* Set up the EMAC link speed */ + if ((ul_phy_anar & ul_phy_analpar) & MII_TX_FDX) { + /* Set MII for 100BaseTX and Full Duplex */ + uc_speed = true; + uc_fd = true; + 80514: 2301 movs r3, #1 + p_emac->EMAC_NCFGR |= EMAC_NCFGR_SPD; + 80516: 6862 ldr r2, [r4, #4] + 80518: f042 0201 orr.w r2, r2, #1 + 8051c: 6062 str r2, [r4, #4] + 8051e: e005 b.n 8052c + } else if ((ul_phy_anar & ul_phy_analpar) & MII_10_FDX) { + /* Set MII for 10BaseT and Full Duplex */ + uc_speed = false; + uc_fd = true; + 80520: 2301 movs r3, #1 + 80522: e7ff b.n 80524 + } else { + p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_SPD; + 80524: 6862 ldr r2, [r4, #4] + 80526: f022 0201 bic.w r2, r2, #1 + 8052a: 6062 str r2, [r4, #4] + * \param p_emac Pointer to the EMAC instance. + * \param uc_enable 0 to disable the Full-Duplex mode, else to enable it. + */ +static inline void emac_enable_full_duplex(Emac* p_emac, uint8_t uc_enable) +{ + if (uc_enable) { + 8052c: b123 cbz r3, 80538 + p_emac->EMAC_NCFGR |= EMAC_NCFGR_FD; + 8052e: 6863 ldr r3, [r4, #4] + 80530: f043 0302 orr.w r3, r3, #2 + 80534: 6063 str r3, [r4, #4] + 80536: e003 b.n 80540 + } else { + p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_FD; + 80538: 6863 ldr r3, [r4, #4] + 8053a: f023 0302 bic.w r3, r3, #2 + 8053e: 6063 str r3, [r4, #4] + * \param uc_enable 0 to disable the RMII mode, else to enable it. + */ +static inline void emac_enable_rmii(Emac* p_emac, uint8_t uc_enable) +{ + if (uc_enable) { + p_emac->EMAC_USRIO |= EMAC_USRIO_RMII; + 80540: f8d4 30c0 ldr.w r3, [r4, #192] ; 0xc0 + 80544: f043 0301 orr.w r3, r3, #1 + 80548: f8c4 30c0 str.w r3, [r4, #192] ; 0xc0 + */ +static inline void emac_enable_transceiver_clock(Emac* p_emac, + uint8_t uc_enable) +{ + if (uc_enable) { + p_emac->EMAC_USRIO |= EMAC_USRIO_CLKEN; + 8054c: f8d4 30c0 ldr.w r3, [r4, #192] ; 0xc0 + 80550: f043 0302 orr.w r3, r3, #2 + 80554: f8c4 30c0 str.w r3, [r4, #192] ; 0xc0 +static inline void emac_enable_management(Emac* p_emac, uint8_t uc_enable) +{ + if (uc_enable) { + p_emac->EMAC_NCR |= EMAC_NCR_MPE; + } else { + p_emac->EMAC_NCR &= ~EMAC_NCR_MPE; + 80558: 6823 ldr r3, [r4, #0] + 8055a: f023 0310 bic.w r3, r3, #16 + 8055e: 6023 str r3, [r4, #0] + + emac_enable_rmii(p_emac, ETH_PHY_MODE); + emac_enable_transceiver_clock(p_emac, true); + + emac_enable_management(p_emac, false); + return uc_rc; + 80560: 2000 movs r0, #0 +} + 80562: b002 add sp, #8 + 80564: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 80568: 00080789 .word 0x00080789 + 8056c: 000807e9 .word 0x000807e9 + 80570: 000f4240 .word 0x000f4240 + +00080574 : + * \param uc_phy_addr PHY address. + * + * \Return EMAC_OK if successfully, EMAC_TIMEOUT if timeout. + */ +uint8_t ethernet_phy_reset(Emac *p_emac, uint8_t uc_phy_addr) +{ + 80574: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} + 80578: b083 sub sp, #12 + 8057a: 4605 mov r5, r0 + 8057c: 4689 mov r9, r1 + uint32_t ul_bmcr = MII_RESET; + 8057e: f44f 4300 mov.w r3, #32768 ; 0x8000 + 80582: ae02 add r6, sp, #8 + 80584: f846 3d04 str.w r3, [r6, #-4]! + * \param uc_enable 0 to disable EMAC management, else to enable it. + */ +static inline void emac_enable_management(Emac* p_emac, uint8_t uc_enable) +{ + if (uc_enable) { + p_emac->EMAC_NCR |= EMAC_NCR_MPE; + 80588: 6802 ldr r2, [r0, #0] + 8058a: f042 0210 orr.w r2, r2, #16 + 8058e: 6002 str r2, [r0, #0] + uint8_t uc_rc = EMAC_TIMEOUT; + + emac_enable_management(p_emac, true); + + ul_bmcr = MII_RESET; + emac_phy_write(p_emac, uc_phy_address, MII_BMCR, ul_bmcr); + 80590: 2200 movs r2, #0 + 80592: 4c0e ldr r4, [pc, #56] ; (805cc ) + 80594: 47a0 blx r4 + */ +uint8_t ethernet_phy_reset(Emac *p_emac, uint8_t uc_phy_addr) +{ + uint32_t ul_bmcr = MII_RESET; + uint8_t uc_phy_address = uc_phy_addr; + uint32_t ul_timeout = ETH_PHY_TIMEOUT; + 80596: 240a movs r4, #10 + + ul_bmcr = MII_RESET; + emac_phy_write(p_emac, uc_phy_address, MII_BMCR, ul_bmcr); + + do { + emac_phy_read(p_emac, uc_phy_address, MII_BMCR, &ul_bmcr); + 80598: f04f 0800 mov.w r8, #0 + 8059c: 4f0c ldr r7, [pc, #48] ; (805d0 ) + 8059e: 4628 mov r0, r5 + 805a0: 4649 mov r1, r9 + 805a2: 4642 mov r2, r8 + 805a4: 4633 mov r3, r6 + 805a6: 47b8 blx r7 + ul_timeout--; + 805a8: 3c01 subs r4, #1 + } while ((ul_bmcr & MII_RESET) && ul_timeout); + 805aa: 9b01 ldr r3, [sp, #4] + 805ac: f413 4f00 tst.w r3, #32768 ; 0x8000 + 805b0: d001 beq.n 805b6 + 805b2: 2c00 cmp r4, #0 + 805b4: d1f3 bne.n 8059e + } else { + p_emac->EMAC_NCR &= ~EMAC_NCR_MPE; + 805b6: 682b ldr r3, [r5, #0] + 805b8: f023 0310 bic.w r3, r3, #16 + 805bc: 602b str r3, [r5, #0] + if (!ul_timeout) { + uc_rc = EMAC_OK; + } + + return (uc_rc); +} + 805be: 1c20 adds r0, r4, #0 + 805c0: bf18 it ne + 805c2: 2001 movne r0, #1 + 805c4: b003 add sp, #12 + 805c6: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + 805ca: bf00 nop + 805cc: 000807e9 .word 0x000807e9 + 805d0: 00080789 .word 0x00080789 + +000805d4 : + */ +static inline uint8_t emac_set_clock(Emac* p_emac, uint32_t ul_mck) +{ + uint32_t ul_clk; + + if (ul_mck > EMAC_CLOCK_SPEED_160MHZ) { + 805d4: 4b39 ldr r3, [pc, #228] ; (806bc ) + 805d6: 429a cmp r2, r3 + 805d8: d86e bhi.n 806b8 + * \param ul_mck EMAC MCK. + * + * Return EMAC_OK if successfully, EMAC_TIMEOUT if timeout. + */ +uint8_t ethernet_phy_init(Emac *p_emac, uint8_t uc_phy_addr, uint32_t mck) +{ + 805da: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} + 805de: b083 sub sp, #12 + return EMAC_INVALID; + } else if (ul_mck > EMAC_CLOCK_SPEED_80MHZ) { + 805e0: 4b37 ldr r3, [pc, #220] ; (806c0 ) + 805e2: 429a cmp r2, r3 + 805e4: d809 bhi.n 805fa + ul_clk = EMAC_NCFGR_CLK_MCK_64; + } else if (ul_mck > EMAC_CLOCK_SPEED_40MHZ) { + 805e6: 4b37 ldr r3, [pc, #220] ; (806c4 ) + 805e8: 429a cmp r2, r3 + 805ea: d809 bhi.n 80600 + ul_clk = EMAC_NCFGR_CLK_MCK_32; + } else if (ul_mck > EMAC_CLOCK_SPEED_20MHZ) { + ul_clk = EMAC_NCFGR_CLK_MCK_16; + } else { + ul_clk = EMAC_NCFGR_CLK_MCK_8; + 805ec: 4b36 ldr r3, [pc, #216] ; (806c8 ) + 805ee: 429a cmp r2, r3 + 805f0: bf8c ite hi + 805f2: f44f 6280 movhi.w r2, #1024 ; 0x400 + 805f6: 2200 movls r2, #0 + 805f8: e004 b.n 80604 + uint32_t ul_clk; + + if (ul_mck > EMAC_CLOCK_SPEED_160MHZ) { + return EMAC_INVALID; + } else if (ul_mck > EMAC_CLOCK_SPEED_80MHZ) { + ul_clk = EMAC_NCFGR_CLK_MCK_64; + 805fa: f44f 6240 mov.w r2, #3072 ; 0xc00 + 805fe: e001 b.n 80604 + } else if (ul_mck > EMAC_CLOCK_SPEED_40MHZ) { + ul_clk = EMAC_NCFGR_CLK_MCK_32; + 80600: f44f 6200 mov.w r2, #2048 ; 0x800 + 80604: 4689 mov r9, r1 + 80606: 4606 mov r6, r0 + ul_clk = EMAC_NCFGR_CLK_MCK_16; + } else { + ul_clk = EMAC_NCFGR_CLK_MCK_8; + } + + p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_CLK_Msk; + 80608: 6843 ldr r3, [r0, #4] + 8060a: f423 6340 bic.w r3, r3, #3072 ; 0xc00 + 8060e: 6043 str r3, [r0, #4] + p_emac->EMAC_NCFGR |= ul_clk; + 80610: 6843 ldr r3, [r0, #4] + 80612: 431a orrs r2, r3 + 80614: 6042 str r2, [r0, #4] + * \return 0xFF when no valid PHY address is found. + */ +static uint8_t ethernet_phy_find_valid(Emac *p_emac, uint8_t uc_phy_addr, + uint8_t addrStart) +{ + uint32_t ul_value = 0; + 80616: ab02 add r3, sp, #8 + 80618: 2200 movs r2, #0 + 8061a: f843 2d04 str.w r2, [r3, #-4]! + * \param uc_enable 0 to disable EMAC management, else to enable it. + */ +static inline void emac_enable_management(Emac* p_emac, uint8_t uc_enable) +{ + if (uc_enable) { + p_emac->EMAC_NCR |= EMAC_NCR_MPE; + 8061e: 6802 ldr r2, [r0, #0] + 80620: f042 0210 orr.w r2, r2, #16 + 80624: 6002 str r2, [r0, #0] + + emac_enable_management(p_emac, true); + + /* Check the current PHY address */ + uc_rc = uc_phy_address; + if (emac_phy_read(p_emac, uc_phy_addr, MII_PHYID1, &ul_value) != EMAC_OK) { + 80626: 2202 movs r2, #2 + 80628: 4c28 ldr r4, [pc, #160] ; (806cc ) + 8062a: 47a0 blx r4 + } + + /* Find another one */ + if (ul_value != MII_OUI_MSB) { + 8062c: f240 1381 movw r3, #385 ; 0x181 + 80630: 9a01 ldr r2, [sp, #4] + 80632: 429a cmp r2, r3 + 80634: d035 beq.n 806a2 + 80636: 464c mov r4, r9 + 80638: 2520 movs r5, #32 + uc_rc = 0xFF; + for (uc_cnt = addrStart; uc_cnt <= ETH_PHY_MAX_ADDR; uc_cnt++) { + uc_phy_address = (uc_phy_address + 1) & 0x1F; + emac_phy_read(p_emac, uc_phy_address, MII_PHYID1, &ul_value); + 8063a: f04f 0802 mov.w r8, #2 + 8063e: 4f23 ldr r7, [pc, #140] ; (806cc ) + + /* Find another one */ + if (ul_value != MII_OUI_MSB) { + uc_rc = 0xFF; + for (uc_cnt = addrStart; uc_cnt <= ETH_PHY_MAX_ADDR; uc_cnt++) { + uc_phy_address = (uc_phy_address + 1) & 0x1F; + 80640: 3401 adds r4, #1 + 80642: f004 041f and.w r4, r4, #31 + emac_phy_read(p_emac, uc_phy_address, MII_PHYID1, &ul_value); + 80646: 4630 mov r0, r6 + 80648: 4621 mov r1, r4 + 8064a: 4642 mov r2, r8 + 8064c: ab01 add r3, sp, #4 + 8064e: 47b8 blx r7 + if (ul_value == MII_OUI_MSB) { + 80650: f240 1381 movw r3, #385 ; 0x181 + 80654: 9a01 ldr r2, [sp, #4] + 80656: 429a cmp r2, r3 + 80658: d004 beq.n 80664 + 8065a: 1e6b subs r3, r5, #1 + } + + /* Find another one */ + if (ul_value != MII_OUI_MSB) { + uc_rc = 0xFF; + for (uc_cnt = addrStart; uc_cnt <= ETH_PHY_MAX_ADDR; uc_cnt++) { + 8065c: f013 05ff ands.w r5, r3, #255 ; 0xff + 80660: d1ee bne.n 80640 + 80662: e012 b.n 8068a + } else { + p_emac->EMAC_NCR &= ~EMAC_NCR_MPE; + 80664: 6833 ldr r3, [r6, #0] + 80666: f023 0310 bic.w r3, r3, #16 + 8066a: 6033 str r3, [r6, #0] + } + } + + emac_enable_management(p_emac, false); + + if (uc_rc != 0xFF) { + 8066c: 2cff cmp r4, #255 ; 0xff + 8066e: d01f beq.n 806b0 + emac_phy_read(p_emac, uc_phy_address, MII_DSCSR, &ul_value); + 80670: 4630 mov r0, r6 + 80672: 4621 mov r1, r4 + 80674: 2211 movs r2, #17 + 80676: ab01 add r3, sp, #4 + 80678: 4d14 ldr r5, [pc, #80] ; (806cc ) + 8067a: 47a8 blx r5 + /* Check PHY Address */ + uc_phy = ethernet_phy_find_valid(p_emac, uc_phy_addr, 0); + if (uc_phy == 0xFF) { + return 0; + } + if (uc_phy != uc_phy_addr) { + 8067c: 45a1 cmp r9, r4 + 8067e: d017 beq.n 806b0 + ethernet_phy_reset(p_emac, uc_phy_addr); + 80680: 4630 mov r0, r6 + 80682: 4649 mov r1, r9 + 80684: 4b12 ldr r3, [pc, #72] ; (806d0 ) + 80686: 4798 blx r3 + 80688: e012 b.n 806b0 + 8068a: 6833 ldr r3, [r6, #0] + 8068c: f023 0310 bic.w r3, r3, #16 + 80690: 6033 str r3, [r6, #0] + 80692: e00d b.n 806b0 + } + + emac_enable_management(p_emac, false); + + if (uc_rc != 0xFF) { + emac_phy_read(p_emac, uc_phy_address, MII_DSCSR, &ul_value); + 80694: 4630 mov r0, r6 + 80696: 4649 mov r1, r9 + 80698: 2211 movs r2, #17 + 8069a: ab01 add r3, sp, #4 + 8069c: 4c0b ldr r4, [pc, #44] ; (806cc ) + 8069e: 47a0 blx r4 + 806a0: e006 b.n 806b0 + 806a2: 6833 ldr r3, [r6, #0] + 806a4: f023 0310 bic.w r3, r3, #16 + 806a8: 6033 str r3, [r6, #0] + } + } + + emac_enable_management(p_emac, false); + + if (uc_rc != 0xFF) { + 806aa: f1b9 0fff cmp.w r9, #255 ; 0xff + 806ae: d1f1 bne.n 80694 + if (uc_phy != uc_phy_addr) { + ethernet_phy_reset(p_emac, uc_phy_addr); + } + + return uc_rc; +} + 806b0: 2000 movs r0, #0 + 806b2: b003 add sp, #12 + 806b4: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + 806b8: 2000 movs r0, #0 + 806ba: 4770 bx lr + 806bc: 09896800 .word 0x09896800 + 806c0: 04c4b400 .word 0x04c4b400 + 806c4: 02625a00 .word 0x02625a00 + 806c8: 01312d00 .word 0x01312d00 + 806cc: 00080789 .word 0x00080789 + 806d0: 00080575 .word 0x00080575 + +000806d4 : +#define CIRC_CLEAR(head, tail) (head = tail = 0) + +/** Increment head or tail */ +static void circ_inc(uint16_t *headortail, uint32_t size) +{ + (*headortail)++; + 806d4: 8803 ldrh r3, [r0, #0] + 806d6: 3301 adds r3, #1 + if((*headortail) >= size) { + 806d8: b29b uxth r3, r3 + (*headortail) = 0; + 806da: 428b cmp r3, r1 + 806dc: bf28 it cs + 806de: 2300 movcs r3, #0 + 806e0: 8003 strh r3, [r0, #0] + 806e2: 4770 bx lr + +000806e4 : + * + * \param p_dev Pointer to EMAC driver instance. + * + */ +static void emac_reset_tx_mem(emac_device_t* p_dev) +{ + 806e4: b4f0 push {r4, r5, r6, r7} + Emac *p_hw = p_dev->p_hw; + 806e6: 6807 ldr r7, [r0, #0] + uint8_t *p_tx_buff = p_dev->p_tx_buffer; + 806e8: 6842 ldr r2, [r0, #4] + emac_tx_descriptor_t *p_td = p_dev->p_tx_dscr; + 806ea: 6905 ldr r5, [r0, #16] +static inline void emac_enable_transmit(Emac* p_emac, uint8_t uc_enable) +{ + if (uc_enable) { + p_emac->EMAC_NCR |= EMAC_NCR_TE; + } else { + p_emac->EMAC_NCR &= ~EMAC_NCR_TE; + 806ec: 683b ldr r3, [r7, #0] + 806ee: f023 0308 bic.w r3, r3, #8 + 806f2: 603b str r3, [r7, #0] + + /* Disable TX */ + emac_enable_transmit(p_hw, 0); + + /* Set up the TX descriptors */ + CIRC_CLEAR(p_dev->us_tx_head, p_dev->us_tx_tail); + 806f4: 2300 movs r3, #0 + 806f6: 8503 strh r3, [r0, #40] ; 0x28 + 806f8: 84c3 strh r3, [r0, #38] ; 0x26 + for (ul_index = 0; ul_index < p_dev->us_tx_list_size; ul_index++) { + 806fa: 8c83 ldrh r3, [r0, #36] ; 0x24 + 806fc: b173 cbz r3, 8071c + 806fe: 4629 mov r1, r5 + 80700: 2300 movs r3, #0 + ul_address = (uint32_t) (&(p_tx_buff[ul_index * EMAC_TX_UNITSIZE])); + p_td[ul_index].addr = ul_address; + p_td[ul_index].status.val = EMAC_TXD_USED; + 80702: f04f 4600 mov.w r6, #2147483648 ; 0x80000000 + + /* Set up the TX descriptors */ + CIRC_CLEAR(p_dev->us_tx_head, p_dev->us_tx_tail); + for (ul_index = 0; ul_index < p_dev->us_tx_list_size; ul_index++) { + ul_address = (uint32_t) (&(p_tx_buff[ul_index * EMAC_TX_UNITSIZE])); + p_td[ul_index].addr = ul_address; + 80706: f845 2033 str.w r2, [r5, r3, lsl #3] + p_td[ul_index].status.val = EMAC_TXD_USED; + 8070a: 604e str r6, [r1, #4] + /* Disable TX */ + emac_enable_transmit(p_hw, 0); + + /* Set up the TX descriptors */ + CIRC_CLEAR(p_dev->us_tx_head, p_dev->us_tx_tail); + for (ul_index = 0; ul_index < p_dev->us_tx_list_size; ul_index++) { + 8070c: 3301 adds r3, #1 + 8070e: 8c84 ldrh r4, [r0, #36] ; 0x24 + 80710: f202 52ee addw r2, r2, #1518 ; 0x5ee + 80714: 3108 adds r1, #8 + 80716: 429c cmp r4, r3 + 80718: d8f5 bhi.n 80706 + 8071a: e000 b.n 8071e + 8071c: 2400 movs r4, #0 + ul_address = (uint32_t) (&(p_tx_buff[ul_index * EMAC_TX_UNITSIZE])); + p_td[ul_index].addr = ul_address; + p_td[ul_index].status.val = EMAC_TXD_USED; + } + p_td[p_dev->us_tx_list_size - 1].status.val = + 8071e: eb05 04c4 add.w r4, r5, r4, lsl #3 + 80722: f04f 4340 mov.w r3, #3221225472 ; 0xc0000000 + 80726: f844 3c04 str.w r3, [r4, #-4] + * \param p_emac Pointer to the EMAC instance. + * \param ul_addr Tx queue address. + */ +static inline void emac_set_tx_queue(Emac* p_emac, uint32_t ul_addr) +{ + p_emac->EMAC_TBQP = EMAC_TBQP_ADDR_Msk & ul_addr; + 8072a: f025 0503 bic.w r5, r5, #3 + 8072e: 61fd str r5, [r7, #28] + EMAC_TXD_USED | EMAC_TXD_WRAP; + + /* Set transmit buffer queue */ + emac_set_tx_queue(p_hw, (uint32_t) p_td); +} + 80730: bcf0 pop {r4, r5, r6, r7} + 80732: 4770 bx lr + +00080734 : + * \brief Disable receiver, reset registers and descriptor list. + * + * \param p_drv Pointer to EMAC Driver instance. + */ +static void emac_reset_rx_mem(emac_device_t* p_dev) +{ + 80734: b4f0 push {r4, r5, r6, r7} + Emac *p_hw = p_dev->p_hw; + 80736: 6807 ldr r7, [r0, #0] + uint8_t *p_rx_buff = p_dev->p_rx_buffer; + 80738: 6882 ldr r2, [r0, #8] + emac_rx_descriptor_t *pRd = p_dev->p_rx_dscr; + 8073a: 68c5 ldr r5, [r0, #12] +static inline void emac_enable_receive(Emac* p_emac, uint8_t uc_enable) +{ + if (uc_enable) { + p_emac->EMAC_NCR |= EMAC_NCR_RE; + } else { + p_emac->EMAC_NCR &= ~EMAC_NCR_RE; + 8073c: 683b ldr r3, [r7, #0] + 8073e: f023 0304 bic.w r3, r3, #4 + 80742: 603b str r3, [r7, #0] + + /* Disable RX */ + emac_enable_receive(p_hw, 0); + + /* Set up the RX descriptors */ + p_dev->us_rx_idx = 0; + 80744: 2300 movs r3, #0 + 80746: 8443 strh r3, [r0, #34] ; 0x22 + for (ul_index = 0; ul_index < p_dev->us_rx_list_size; ul_index++) { + 80748: 8c03 ldrh r3, [r0, #32] + 8074a: b173 cbz r3, 8076a + 8074c: 4629 mov r1, r5 + 8074e: 2300 movs r3, #0 + ul_address = (uint32_t) (&(p_rx_buff[ul_index * EMAC_RX_UNITSIZE])); + pRd[ul_index].addr.val = ul_address & EMAC_RXD_ADDR_MASK; + pRd[ul_index].status.val = 0; + 80750: 461e mov r6, r3 + + /* Set up the RX descriptors */ + p_dev->us_rx_idx = 0; + for (ul_index = 0; ul_index < p_dev->us_rx_list_size; ul_index++) { + ul_address = (uint32_t) (&(p_rx_buff[ul_index * EMAC_RX_UNITSIZE])); + pRd[ul_index].addr.val = ul_address & EMAC_RXD_ADDR_MASK; + 80752: f022 0403 bic.w r4, r2, #3 + 80756: f845 4033 str.w r4, [r5, r3, lsl #3] + pRd[ul_index].status.val = 0; + 8075a: 604e str r6, [r1, #4] + /* Disable RX */ + emac_enable_receive(p_hw, 0); + + /* Set up the RX descriptors */ + p_dev->us_rx_idx = 0; + for (ul_index = 0; ul_index < p_dev->us_rx_list_size; ul_index++) { + 8075c: 3301 adds r3, #1 + 8075e: 8c04 ldrh r4, [r0, #32] + 80760: 3280 adds r2, #128 ; 0x80 + 80762: 3108 adds r1, #8 + 80764: 429c cmp r4, r3 + 80766: d8f4 bhi.n 80752 + 80768: e000 b.n 8076c + 8076a: 2400 movs r4, #0 + ul_address = (uint32_t) (&(p_rx_buff[ul_index * EMAC_RX_UNITSIZE])); + pRd[ul_index].addr.val = ul_address & EMAC_RXD_ADDR_MASK; + pRd[ul_index].status.val = 0; + } + pRd[p_dev->us_rx_list_size - 1].addr.val |= EMAC_RXD_WRAP; + 8076c: f104 5400 add.w r4, r4, #536870912 ; 0x20000000 + 80770: 3c01 subs r4, #1 + 80772: f855 3034 ldr.w r3, [r5, r4, lsl #3] + 80776: f043 0302 orr.w r3, r3, #2 + 8077a: f845 3034 str.w r3, [r5, r4, lsl #3] + * \param p_emac Pointer to the EMAC instance. + * \param ul_addr Rx queue address. + */ +static inline void emac_set_rx_queue(Emac* p_emac, uint32_t ul_addr) +{ + p_emac->EMAC_RBQP = EMAC_RBQP_ADDR_Msk & ul_addr; + 8077e: f025 0503 bic.w r5, r5, #3 + 80782: 61bd str r5, [r7, #24] + + /* Set receive buffer queue */ + emac_set_rx_queue(p_hw, (uint32_t) pRd); +} + 80784: bcf0 pop {r4, r5, r6, r7} + 80786: 4770 bx lr + +00080788 : + * + * \Return EMAC_OK if successfully, EMAC_TIMEOUT if timeout. + */ +uint8_t emac_phy_read(Emac* p_emac, uint8_t uc_phy_address, uint8_t uc_address, + uint32_t* p_value) +{ + 80788: b410 push {r4} + 8078a: b083 sub sp, #12 +static inline void emac_maintain_phy(Emac* p_emac, + uint8_t uc_phy_addr, uint8_t uc_reg_addr, uint8_t uc_rw, + uint16_t us_data) +{ + /* Wait until bus idle */ + while ((p_emac->EMAC_NSR & EMAC_NSR_IDLE) == 0); + 8078c: 6884 ldr r4, [r0, #8] + 8078e: f014 0f04 tst.w r4, #4 + 80792: d0fb beq.n 8078c + /* Write maintain register */ + p_emac->EMAC_MAN = EMAC_MAN_CODE(EMAC_MAN_CODE_VALUE) + | EMAC_MAN_SOF(EMAC_MAN_SOF_VALUE) + | EMAC_MAN_PHYA(uc_phy_addr) + | EMAC_MAN_REGA(uc_reg_addr) + 80794: 0492 lsls r2, r2, #18 + 80796: f402 02f8 and.w r2, r2, #8126464 ; 0x7c0000 + 8079a: f042 42c0 orr.w r2, r2, #1610612736 ; 0x60000000 + 8079e: f442 3200 orr.w r2, r2, #131072 ; 0x20000 + /* Wait until bus idle */ + while ((p_emac->EMAC_NSR & EMAC_NSR_IDLE) == 0); + /* Write maintain register */ + p_emac->EMAC_MAN = EMAC_MAN_CODE(EMAC_MAN_CODE_VALUE) + | EMAC_MAN_SOF(EMAC_MAN_SOF_VALUE) + | EMAC_MAN_PHYA(uc_phy_addr) + 807a2: 05c9 lsls r1, r1, #23 + 807a4: f001 6178 and.w r1, r1, #260046848 ; 0xf800000 + | EMAC_MAN_REGA(uc_reg_addr) + | EMAC_MAN_RW((uc_rw ? EMAC_MAN_RW_TYPE : EMAC_MAN_READ_ONLY)) + | EMAC_MAN_DATA(us_data); + 807a8: 430a orrs r2, r1 + uint16_t us_data) +{ + /* Wait until bus idle */ + while ((p_emac->EMAC_NSR & EMAC_NSR_IDLE) == 0); + /* Write maintain register */ + p_emac->EMAC_MAN = EMAC_MAN_CODE(EMAC_MAN_CODE_VALUE) + 807aa: 6342 str r2, [r0, #52] ; 0x34 + * + * Return EMAC_OK if the operation is completed successfully. + */ +static uint8_t emac_wait_phy(Emac* p_emac, const uint32_t ul_retry) +{ + volatile uint32_t ul_retry_count = 0; + 807ac: 2200 movs r2, #0 + 807ae: 9201 str r2, [sp, #4] + continue; + } + + ul_retry_count++; + + if (ul_retry_count >= ul_retry) { + 807b0: 490c ldr r1, [pc, #48] ; (807e4 ) + 807b2: e005 b.n 807c0 + while (!emac_is_phy_idle(p_emac)) { + if (ul_retry == 0) { + continue; + } + + ul_retry_count++; + 807b4: 9a01 ldr r2, [sp, #4] + 807b6: 3201 adds r2, #1 + 807b8: 9201 str r2, [sp, #4] + + if (ul_retry_count >= ul_retry) { + 807ba: 9a01 ldr r2, [sp, #4] + 807bc: 428a cmp r2, r1 + 807be: d80c bhi.n 807da + * + * \return 1 if PHY is idle. + */ +static inline uint8_t emac_is_phy_idle(Emac* p_emac) +{ + return ((p_emac->EMAC_NSR & EMAC_NSR_IDLE) > 0); + 807c0: 6882 ldr r2, [r0, #8] + */ +static uint8_t emac_wait_phy(Emac* p_emac, const uint32_t ul_retry) +{ + volatile uint32_t ul_retry_count = 0; + + while (!emac_is_phy_idle(p_emac)) { + 807c2: f012 0f04 tst.w r2, #4 + 807c6: d0f5 beq.n 807b4 + * \return Get PHY data. + */ +static inline uint16_t emac_get_phy_data(Emac* p_emac) +{ + /* Wait until bus idle */ + while ((p_emac->EMAC_NSR & EMAC_NSR_IDLE) == 0); + 807c8: 6882 ldr r2, [r0, #8] + 807ca: f012 0f04 tst.w r2, #4 + 807ce: d0fb beq.n 807c8 + /* Return data */ + return (uint16_t) (p_emac->EMAC_MAN & EMAC_MAN_DATA_Msk); + 807d0: 6b42 ldr r2, [r0, #52] ; 0x34 + emac_maintain_phy(p_emac, uc_phy_address, uc_address, 1, 0); + + if (emac_wait_phy(p_emac, MAC_PHY_RETRY_MAX) == EMAC_TIMEOUT) { + return EMAC_TIMEOUT; + } + *p_value = emac_get_phy_data(p_emac); + 807d2: b292 uxth r2, r2 + 807d4: 601a str r2, [r3, #0] + return EMAC_OK; + 807d6: 2000 movs r0, #0 + 807d8: e000 b.n 807dc + uint32_t* p_value) +{ + emac_maintain_phy(p_emac, uc_phy_address, uc_address, 1, 0); + + if (emac_wait_phy(p_emac, MAC_PHY_RETRY_MAX) == EMAC_TIMEOUT) { + return EMAC_TIMEOUT; + 807da: 2001 movs r0, #1 + } + *p_value = emac_get_phy_data(p_emac); + return EMAC_OK; +} + 807dc: b003 add sp, #12 + 807de: f85d 4b04 ldr.w r4, [sp], #4 + 807e2: 4770 bx lr + 807e4: 000f423f .word 0x000f423f + +000807e8 : + * + * \Return EMAC_OK if successfully, EMAC_TIMEOUT if timeout. + */ +uint8_t emac_phy_write(Emac* p_emac, uint8_t uc_phy_address, + uint8_t uc_address, uint32_t ul_value) +{ + 807e8: b410 push {r4} + 807ea: b083 sub sp, #12 +static inline void emac_maintain_phy(Emac* p_emac, + uint8_t uc_phy_addr, uint8_t uc_reg_addr, uint8_t uc_rw, + uint16_t us_data) +{ + /* Wait until bus idle */ + while ((p_emac->EMAC_NSR & EMAC_NSR_IDLE) == 0); + 807ec: 6884 ldr r4, [r0, #8] + 807ee: f014 0f04 tst.w r4, #4 + 807f2: d0fb beq.n 807ec + /* Write maintain register */ + p_emac->EMAC_MAN = EMAC_MAN_CODE(EMAC_MAN_CODE_VALUE) + | EMAC_MAN_SOF(EMAC_MAN_SOF_VALUE) + | EMAC_MAN_PHYA(uc_phy_addr) + | EMAC_MAN_REGA(uc_reg_addr) + 807f4: 0492 lsls r2, r2, #18 + 807f6: f402 02f8 and.w r2, r2, #8126464 ; 0x7c0000 + 807fa: f042 42a0 orr.w r2, r2, #1342177280 ; 0x50000000 + 807fe: f442 3200 orr.w r2, r2, #131072 ; 0x20000 + /* Wait until bus idle */ + while ((p_emac->EMAC_NSR & EMAC_NSR_IDLE) == 0); + /* Write maintain register */ + p_emac->EMAC_MAN = EMAC_MAN_CODE(EMAC_MAN_CODE_VALUE) + | EMAC_MAN_SOF(EMAC_MAN_SOF_VALUE) + | EMAC_MAN_PHYA(uc_phy_addr) + 80802: 05c9 lsls r1, r1, #23 + 80804: f001 6178 and.w r1, r1, #260046848 ; 0xf800000 + 80808: 430a orrs r2, r1 + | EMAC_MAN_REGA(uc_reg_addr) + | EMAC_MAN_RW((uc_rw ? EMAC_MAN_RW_TYPE : EMAC_MAN_READ_ONLY)) + | EMAC_MAN_DATA(us_data); + 8080a: b29b uxth r3, r3 + 8080c: 431a orrs r2, r3 + uint16_t us_data) +{ + /* Wait until bus idle */ + while ((p_emac->EMAC_NSR & EMAC_NSR_IDLE) == 0); + /* Write maintain register */ + p_emac->EMAC_MAN = EMAC_MAN_CODE(EMAC_MAN_CODE_VALUE) + 8080e: 6342 str r2, [r0, #52] ; 0x34 + * + * Return EMAC_OK if the operation is completed successfully. + */ +static uint8_t emac_wait_phy(Emac* p_emac, const uint32_t ul_retry) +{ + volatile uint32_t ul_retry_count = 0; + 80810: 2300 movs r3, #0 + 80812: 9301 str r3, [sp, #4] + continue; + } + + ul_retry_count++; + + if (ul_retry_count >= ul_retry) { + 80814: 4a09 ldr r2, [pc, #36] ; (8083c ) + 80816: e005 b.n 80824 + while (!emac_is_phy_idle(p_emac)) { + if (ul_retry == 0) { + continue; + } + + ul_retry_count++; + 80818: 9b01 ldr r3, [sp, #4] + 8081a: 3301 adds r3, #1 + 8081c: 9301 str r3, [sp, #4] + + if (ul_retry_count >= ul_retry) { + 8081e: 9b01 ldr r3, [sp, #4] + 80820: 4293 cmp r3, r2 + 80822: d805 bhi.n 80830 + * + * \return 1 if PHY is idle. + */ +static inline uint8_t emac_is_phy_idle(Emac* p_emac) +{ + return ((p_emac->EMAC_NSR & EMAC_NSR_IDLE) > 0); + 80824: 6883 ldr r3, [r0, #8] + */ +static uint8_t emac_wait_phy(Emac* p_emac, const uint32_t ul_retry) +{ + volatile uint32_t ul_retry_count = 0; + + while (!emac_is_phy_idle(p_emac)) { + 80826: f013 0f04 tst.w r3, #4 + 8082a: d0f5 beq.n 80818 + + if (ul_retry_count >= ul_retry) { + return EMAC_TIMEOUT; + } + } + return EMAC_OK; + 8082c: 2000 movs r0, #0 + 8082e: e000 b.n 80832 + } + + ul_retry_count++; + + if (ul_retry_count >= ul_retry) { + return EMAC_TIMEOUT; + 80830: 2001 movs r0, #1 + + if (emac_wait_phy(p_emac, MAC_PHY_RETRY_MAX) == EMAC_TIMEOUT) { + return EMAC_TIMEOUT; + } + return EMAC_OK; +} + 80832: b003 add sp, #12 + 80834: f85d 4b04 ldr.w r4, [sp], #4 + 80838: 4770 bx lr + 8083a: bf00 nop + 8083c: 000f423f .word 0x000f423f + +00080840 : + * \param p_emac_dev Pointer to the EMAC device instance. + * \param p_opt EMAC configure options. + */ +void emac_dev_init(Emac* p_emac, emac_device_t* p_emac_dev, + emac_options_t* p_opt) +{ + 80840: b570 push {r4, r5, r6, lr} + 80842: 4604 mov r4, r0 + 80844: 460d mov r5, r1 + 80846: 4616 mov r6, r2 + * \param p_emac Pointer to the EMAC instance. + * \param ul_ncr Network control value. + */ +static inline void emac_network_control(Emac* p_emac, uint32_t ul_ncr) +{ + p_emac->EMAC_NCR = ul_ncr; + 80848: 2300 movs r3, #0 + 8084a: 6003 str r3, [r0, #0] + * \param p_emac Pointer to the EMAC instance. + * \param ul_source Interrupt source(s) to be disabled. + */ +static inline void emac_disable_interrupt(Emac* p_emac, uint32_t ul_source) +{ + p_emac->EMAC_IDR = ul_source; + 8084c: f04f 33ff mov.w r3, #4294967295 + 80850: 62c3 str r3, [r0, #44] ; 0x2c + * + * \param p_emac Pointer to the EMAC instance. + */ +static inline void emac_clear_statistics(Emac* p_emac) +{ + p_emac->EMAC_NCR |= EMAC_NCR_CLRSTAT; + 80852: 6803 ldr r3, [r0, #0] + 80854: f043 0320 orr.w r3, r3, #32 + 80858: 6003 str r3, [r0, #0] + * \param p_emac Pointer to the EMAC instance. + * \param ul_status Receive status. + */ +static inline void emac_clear_rx_status(Emac* p_emac, uint32_t ul_status) +{ + p_emac->EMAC_RSR = ul_status; + 8085a: 2307 movs r3, #7 + 8085c: 6203 str r3, [r0, #32] + * \param p_emac Pointer to the EMAC instance. + * \param ul_status Transmit status. + */ +static inline void emac_clear_tx_status(Emac* p_emac, uint32_t ul_status) +{ + p_emac->EMAC_TSR = ul_status; + 8085e: 2377 movs r3, #119 ; 0x77 + 80860: 6143 str r3, [r0, #20] + * + * \return Interrupt status. + */ +static inline uint32_t emac_get_interrupt_status(Emac* p_emac) +{ + return p_emac->EMAC_ISR; + 80862: 6a43 ldr r3, [r0, #36] ; 0x24 + * + * \return Network configuration. + */ +static inline uint32_t emac_get_configure(Emac* p_emac) +{ + return p_emac->EMAC_NCFGR; + 80864: 6843 ldr r3, [r0, #4] + /* Clear interrupts */ + emac_get_interrupt_status(p_emac); + + /* Enable the copy of data into the buffers + ignore broadcasts, and not copy FCS. */ + emac_set_configure(p_emac, + 80866: f443 3308 orr.w r3, r3, #139264 ; 0x22000 + * \param p_emac Pointer to the EMAC instance. + * \param ul_cfg Network configuration value. + */ +static inline void emac_set_configure(Emac* p_emac, uint32_t ul_cfg) +{ + p_emac->EMAC_NCFGR = ul_cfg; + 8086a: 6043 str r3, [r0, #4] + * \param p_emac Pointer to the EMAC instance. + * \param uc_enable 0 to disable copying all valid frames, else to enable it. + */ +static inline void emac_enable_copy_all(Emac* p_emac, uint8_t uc_enable) +{ + if (uc_enable) { + 8086c: 7813 ldrb r3, [r2, #0] + 8086e: b123 cbz r3, 8087a + p_emac->EMAC_NCFGR |= EMAC_NCFGR_CAF; + 80870: 6843 ldr r3, [r0, #4] + 80872: f043 0310 orr.w r3, r3, #16 + 80876: 6043 str r3, [r0, #4] + 80878: e003 b.n 80882 + } else { + p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_CAF; + 8087a: 6843 ldr r3, [r0, #4] + 8087c: f023 0310 bic.w r3, r3, #16 + 80880: 6043 str r3, [r0, #4] + * \param p_emac Pointer to the EMAC instance. + * \param uc_enable 1 to disable the broadcast, else to enable it. + */ +static inline void emac_disable_broadcast(Emac* p_emac, uint8_t uc_enable) +{ + if (uc_enable) { + 80882: 7873 ldrb r3, [r6, #1] + 80884: b123 cbz r3, 80890 + p_emac->EMAC_NCFGR |= EMAC_NCFGR_NBC; + 80886: 6863 ldr r3, [r4, #4] + 80888: f043 0320 orr.w r3, r3, #32 + 8088c: 6063 str r3, [r4, #4] + 8088e: e003 b.n 80898 + } else { + p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_NBC; + 80890: 6863 ldr r3, [r4, #4] + 80892: f023 0320 bic.w r3, r3, #32 + 80896: 6063 str r3, [r4, #4] + if (p_dev_mm->us_rx_size <= 1 || p_dev_mm->us_tx_size <= 1 || p_tx_cb == NULL) { + return EMAC_PARAM; + } + + /* Assign RX buffers */ + if (((uint32_t) p_dev_mm->p_rx_buffer & 0x7) + 80898: 4b1e ldr r3, [pc, #120] ; (80914 ) + || ((uint32_t) p_dev_mm->p_rx_dscr & 0x7)) { + p_dev_mm->us_rx_size--; + } + p_emac_dev->p_rx_buffer = + (uint8_t *) ((uint32_t) p_dev_mm->p_rx_buffer & 0xFFFFFFF8); + 8089a: f023 0307 bic.w r3, r3, #7 + /* Assign RX buffers */ + if (((uint32_t) p_dev_mm->p_rx_buffer & 0x7) + || ((uint32_t) p_dev_mm->p_rx_dscr & 0x7)) { + p_dev_mm->us_rx_size--; + } + p_emac_dev->p_rx_buffer = + 8089e: 60ab str r3, [r5, #8] + (uint8_t *) ((uint32_t) p_dev_mm->p_rx_buffer & 0xFFFFFFF8); + p_emac_dev->p_rx_dscr = + (emac_rx_descriptor_t *) ((uint32_t) p_dev_mm->p_rx_dscr + 808a0: 4b1d ldr r3, [pc, #116] ; (80918 ) + & 0xFFFFFFF8); + 808a2: f023 0307 bic.w r3, r3, #7 + || ((uint32_t) p_dev_mm->p_rx_dscr & 0x7)) { + p_dev_mm->us_rx_size--; + } + p_emac_dev->p_rx_buffer = + (uint8_t *) ((uint32_t) p_dev_mm->p_rx_buffer & 0xFFFFFFF8); + p_emac_dev->p_rx_dscr = + 808a6: 60eb str r3, [r5, #12] + (emac_rx_descriptor_t *) ((uint32_t) p_dev_mm->p_rx_dscr + & 0xFFFFFFF8); + p_emac_dev->us_rx_list_size = p_dev_mm->us_rx_size; + 808a8: 2310 movs r3, #16 + 808aa: 842b strh r3, [r5, #32] + + /* Assign TX buffers */ + if (((uint32_t) p_dev_mm->p_tx_buffer & 0x7) + 808ac: 4b1b ldr r3, [pc, #108] ; (8091c ) + || ((uint32_t) p_dev_mm->p_tx_dscr & 0x7)) { + p_dev_mm->us_tx_size--; + } + p_emac_dev->p_tx_buffer = + (uint8_t *) ((uint32_t) p_dev_mm->p_tx_buffer & 0xFFFFFFF8); + 808ae: f023 0307 bic.w r3, r3, #7 + /* Assign TX buffers */ + if (((uint32_t) p_dev_mm->p_tx_buffer & 0x7) + || ((uint32_t) p_dev_mm->p_tx_dscr & 0x7)) { + p_dev_mm->us_tx_size--; + } + p_emac_dev->p_tx_buffer = + 808b2: 606b str r3, [r5, #4] + (uint8_t *) ((uint32_t) p_dev_mm->p_tx_buffer & 0xFFFFFFF8); + p_emac_dev->p_tx_dscr = + (emac_tx_descriptor_t *) ((uint32_t) p_dev_mm->p_tx_dscr + 808b4: 4b1a ldr r3, [pc, #104] ; (80920 ) + & 0xFFFFFFF8); + 808b6: f023 0307 bic.w r3, r3, #7 + || ((uint32_t) p_dev_mm->p_tx_dscr & 0x7)) { + p_dev_mm->us_tx_size--; + } + p_emac_dev->p_tx_buffer = + (uint8_t *) ((uint32_t) p_dev_mm->p_tx_buffer & 0xFFFFFFF8); + p_emac_dev->p_tx_dscr = + 808ba: 612b str r3, [r5, #16] + (emac_tx_descriptor_t *) ((uint32_t) p_dev_mm->p_tx_dscr + & 0xFFFFFFF8); + p_emac_dev->us_tx_list_size = p_dev_mm->us_tx_size; + 808bc: 2308 movs r3, #8 + 808be: 84ab strh r3, [r5, #36] ; 0x24 + p_emac_dev->func_tx_cb_list = p_tx_cb; + 808c0: 4b18 ldr r3, [pc, #96] ; (80924 ) + 808c2: 61eb str r3, [r5, #28] + + /* Reset TX & RX */ + emac_reset_rx_mem(p_emac_dev); + 808c4: 4628 mov r0, r5 + 808c6: 4b18 ldr r3, [pc, #96] ; (80928 ) + 808c8: 4798 blx r3 + emac_reset_tx_mem(p_emac_dev); + 808ca: 4628 mov r0, r5 + 808cc: 4b17 ldr r3, [pc, #92] ; (8092c ) + 808ce: 4798 blx r3 + * \param uc_enable 0 to disable EMAC transmit, else to enable it. + */ +static inline void emac_enable_transmit(Emac* p_emac, uint8_t uc_enable) +{ + if (uc_enable) { + p_emac->EMAC_NCR |= EMAC_NCR_TE; + 808d0: 6823 ldr r3, [r4, #0] + 808d2: f043 0308 orr.w r3, r3, #8 + 808d6: 6023 str r3, [r4, #0] + * \param uc_enable 0 to disable EMAC receiver, else to enable it. + */ +static inline void emac_enable_receive(Emac* p_emac, uint8_t uc_enable) +{ + if (uc_enable) { + p_emac->EMAC_NCR |= EMAC_NCR_RE; + 808d8: 6823 ldr r3, [r4, #0] + 808da: f043 0304 orr.w r3, r3, #4 + 808de: 6023 str r3, [r4, #0] + */ +static inline void emac_enable_statistics_write(Emac* p_emac, + uint8_t uc_enable) +{ + if (uc_enable) { + p_emac->EMAC_NCR |= EMAC_NCR_WESTAT; + 808e0: 6823 ldr r3, [r4, #0] + 808e2: f043 0380 orr.w r3, r3, #128 ; 0x80 + 808e6: 6023 str r3, [r4, #0] + * \param p_emac Pointer to the EMAC instance. + * \param ul_source Interrupt source(s) to be enabled. + */ +static inline void emac_enable_interrupt(Emac* p_emac, uint32_t ul_source) +{ + p_emac->EMAC_IER = ul_source; + 808e8: f643 43f4 movw r3, #15604 ; 0x3cf4 + 808ec: 62a3 str r3, [r4, #40] ; 0x28 + * \param p_mac_addr EMAC address. + */ +static inline void emac_set_address(Emac* p_emac, uint8_t uc_index, + uint8_t* p_mac_addr) +{ + p_emac->EMAC_SA[uc_index].EMAC_SAxB = (p_mac_addr[3] << 24) + 808ee: 7972 ldrb r2, [r6, #5] + | (p_mac_addr[2] << 16) + 808f0: 7933 ldrb r3, [r6, #4] + 808f2: 041b lsls r3, r3, #16 + 808f4: ea43 6302 orr.w r3, r3, r2, lsl #24 + | (p_mac_addr[1] << 8) + | (p_mac_addr[0]); + 808f8: 78b2 ldrb r2, [r6, #2] + 808fa: 4313 orrs r3, r2 +static inline void emac_set_address(Emac* p_emac, uint8_t uc_index, + uint8_t* p_mac_addr) +{ + p_emac->EMAC_SA[uc_index].EMAC_SAxB = (p_mac_addr[3] << 24) + | (p_mac_addr[2] << 16) + | (p_mac_addr[1] << 8) + 808fc: 78f2 ldrb r2, [r6, #3] + | (p_mac_addr[0]); + 808fe: ea43 2302 orr.w r3, r3, r2, lsl #8 + * \param p_mac_addr EMAC address. + */ +static inline void emac_set_address(Emac* p_emac, uint8_t uc_index, + uint8_t* p_mac_addr) +{ + p_emac->EMAC_SA[uc_index].EMAC_SAxB = (p_mac_addr[3] << 24) + 80902: f8c4 3098 str.w r3, [r4, #152] ; 0x98 + | (p_mac_addr[2] << 16) + | (p_mac_addr[1] << 8) + | (p_mac_addr[0]); + p_emac->EMAC_SA[uc_index].EMAC_SAxT = (p_mac_addr[5] << 8) + 80906: 79f2 ldrb r2, [r6, #7] + | (p_mac_addr[4]); + 80908: 79b3 ldrb r3, [r6, #6] + 8090a: ea43 2302 orr.w r3, r3, r2, lsl #8 +{ + p_emac->EMAC_SA[uc_index].EMAC_SAxB = (p_mac_addr[3] << 24) + | (p_mac_addr[2] << 16) + | (p_mac_addr[1] << 8) + | (p_mac_addr[0]); + p_emac->EMAC_SA[uc_index].EMAC_SAxT = (p_mac_addr[5] << 8) + 8090e: f8c4 309c str.w r3, [r4, #156] ; 0x9c + 80912: bd70 pop {r4, r5, r6, pc} + 80914: 20073988 .word 0x20073988 + 80918: 20074188 .word 0x20074188 + 8091c: 200709f8 .word 0x200709f8 + 80920: 200709b8 .word 0x200709b8 + 80924: 20073968 .word 0x20073968 + 80928: 00080735 .word 0x00080735 + 8092c: 000806e5 .word 0x000806e5 + +00080930 : + * + * \return EMAC_OK if receiving frame successfully, otherwise failed. + */ +uint32_t emac_dev_read(emac_device_t* p_emac_dev, uint8_t* p_frame, + uint32_t ul_frame_size, uint32_t* p_rcv_size) +{ + 80930: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 80934: b085 sub sp, #20 + uint16_t us_buffer_length; + uint32_t tmp_ul_frame_size = 0; + uint8_t *p_tmp_frame = 0; + uint16_t us_tmp_idx = p_emac_dev->us_rx_idx; + 80936: 8c44 ldrh r4, [r0, #34] ; 0x22 + 80938: f8ad 400e strh.w r4, [sp, #14] + emac_rx_descriptor_t *p_rx_td = + &p_emac_dev->p_rx_dscr[p_emac_dev->us_rx_idx]; + 8093c: 68c6 ldr r6, [r0, #12] + int8_t c_is_frame = 0; + + if (p_frame == NULL) + 8093e: 2900 cmp r1, #0 + 80940: f000 80a0 beq.w 80a84 + 80944: 460f mov r7, r1 +{ + uint16_t us_buffer_length; + uint32_t tmp_ul_frame_size = 0; + uint8_t *p_tmp_frame = 0; + uint16_t us_tmp_idx = p_emac_dev->us_rx_idx; + emac_rx_descriptor_t *p_rx_td = + 80946: eb06 05c4 add.w r5, r6, r4, lsl #3 + + if (p_frame == NULL) + return EMAC_PARAM; + + /* Set the default return value */ + *p_rcv_size = 0; + 8094a: 2100 movs r1, #0 + 8094c: 6019 str r1, [r3, #0] + + /* Process received RX descriptor */ + while ((p_rx_td->addr.val & EMAC_RXD_OWNERSHIP) == EMAC_RXD_OWNERSHIP) { + 8094e: f856 1034 ldr.w r1, [r6, r4, lsl #3] + 80952: f011 0f01 tst.w r1, #1 + 80956: f000 8097 beq.w 80a88 + 8095a: 9700 str r7, [sp, #0] + 8095c: 9301 str r3, [sp, #4] + 8095e: 4693 mov fp, r2 + 80960: 4604 mov r4, r0 + 80962: f04f 0a00 mov.w sl, #0 + 80966: 46d1 mov r9, sl + 80968: 46d0 mov r8, sl + /* Start to gather buffers in a frame */ + c_is_frame = 1; + } + + /* Increment the pointer */ + circ_inc(&us_tmp_idx, p_emac_dev->us_rx_list_size); + 8096a: 4e4f ldr r6, [pc, #316] ; (80aa8 ) + 8096c: 4657 mov r7, sl + *p_rcv_size = 0; + + /* Process received RX descriptor */ + while ((p_rx_td->addr.val & EMAC_RXD_OWNERSHIP) == EMAC_RXD_OWNERSHIP) { + /* A start of frame has been received, discard previous fragments */ + if ((p_rx_td->status.val & EMAC_RXD_SOF) == EMAC_RXD_SOF) { + 8096e: 686b ldr r3, [r5, #4] + 80970: f413 4f80 tst.w r3, #16384 ; 0x4000 + 80974: d019 beq.n 809aa + /* Skip previous fragment */ + while (us_tmp_idx != p_emac_dev->us_rx_idx) { + 80976: 8c63 ldrh r3, [r4, #34] ; 0x22 + 80978: f8bd 200e ldrh.w r2, [sp, #14] + 8097c: 429a cmp r2, r3 + 8097e: f000 8085 beq.w 80a8c + p_rx_td = &p_emac_dev->p_rx_dscr[p_emac_dev->us_rx_idx]; + p_rx_td->addr.val &= ~(EMAC_RXD_OWNERSHIP); + + circ_inc(&p_emac_dev->us_rx_idx, p_emac_dev->us_rx_list_size); + 80982: f104 0722 add.w r7, r4, #34 ; 0x22 + while ((p_rx_td->addr.val & EMAC_RXD_OWNERSHIP) == EMAC_RXD_OWNERSHIP) { + /* A start of frame has been received, discard previous fragments */ + if ((p_rx_td->status.val & EMAC_RXD_SOF) == EMAC_RXD_SOF) { + /* Skip previous fragment */ + while (us_tmp_idx != p_emac_dev->us_rx_idx) { + p_rx_td = &p_emac_dev->p_rx_dscr[p_emac_dev->us_rx_idx]; + 80986: 68e2 ldr r2, [r4, #12] + 80988: eb02 05c3 add.w r5, r2, r3, lsl #3 + p_rx_td->addr.val &= ~(EMAC_RXD_OWNERSHIP); + 8098c: f852 1033 ldr.w r1, [r2, r3, lsl #3] + 80990: f021 0101 bic.w r1, r1, #1 + 80994: f842 1033 str.w r1, [r2, r3, lsl #3] + + circ_inc(&p_emac_dev->us_rx_idx, p_emac_dev->us_rx_list_size); + 80998: 4638 mov r0, r7 + 8099a: 8c21 ldrh r1, [r4, #32] + 8099c: 47b0 blx r6 + /* Process received RX descriptor */ + while ((p_rx_td->addr.val & EMAC_RXD_OWNERSHIP) == EMAC_RXD_OWNERSHIP) { + /* A start of frame has been received, discard previous fragments */ + if ((p_rx_td->status.val & EMAC_RXD_SOF) == EMAC_RXD_SOF) { + /* Skip previous fragment */ + while (us_tmp_idx != p_emac_dev->us_rx_idx) { + 8099e: 8c63 ldrh r3, [r4, #34] ; 0x22 + 809a0: f8bd 200e ldrh.w r2, [sp, #14] + 809a4: 429a cmp r2, r3 + 809a6: d1ee bne.n 80986 + 809a8: e070 b.n 80a8c + /* Start to gather buffers in a frame */ + c_is_frame = 1; + } + + /* Increment the pointer */ + circ_inc(&us_tmp_idx, p_emac_dev->us_rx_list_size); + 809aa: f10d 000e add.w r0, sp, #14 + 809ae: 8c21 ldrh r1, [r4, #32] + 809b0: 47b0 blx r6 + + /* Copy data in the frame buffer */ + if (c_is_frame) { + 809b2: 2f00 cmp r7, #0 + 809b4: d052 beq.n 80a5c + if (us_tmp_idx == p_emac_dev->us_rx_idx) { + 809b6: 8c62 ldrh r2, [r4, #34] ; 0x22 + 809b8: f8bd 300e ldrh.w r3, [sp, #14] + 809bc: 429a cmp r2, r3 + 809be: d114 bne.n 809ea + do { + p_rx_td = &p_emac_dev->p_rx_dscr[p_emac_dev->us_rx_idx]; + p_rx_td->addr.val &= ~(EMAC_RXD_OWNERSHIP); + circ_inc(&p_emac_dev->us_rx_idx, p_emac_dev->us_rx_list_size); + 809c0: f104 0622 add.w r6, r4, #34 ; 0x22 + 809c4: 4d38 ldr r5, [pc, #224] ; (80aa8 ) + + /* Copy data in the frame buffer */ + if (c_is_frame) { + if (us_tmp_idx == p_emac_dev->us_rx_idx) { + do { + p_rx_td = &p_emac_dev->p_rx_dscr[p_emac_dev->us_rx_idx]; + 809c6: 8c61 ldrh r1, [r4, #34] ; 0x22 + 809c8: 68e2 ldr r2, [r4, #12] + p_rx_td->addr.val &= ~(EMAC_RXD_OWNERSHIP); + 809ca: f852 3031 ldr.w r3, [r2, r1, lsl #3] + 809ce: f023 0301 bic.w r3, r3, #1 + 809d2: f842 3031 str.w r3, [r2, r1, lsl #3] + circ_inc(&p_emac_dev->us_rx_idx, p_emac_dev->us_rx_list_size); + 809d6: 4630 mov r0, r6 + 809d8: 8c21 ldrh r1, [r4, #32] + 809da: 47a8 blx r5 + + } while (us_tmp_idx != p_emac_dev->us_rx_idx); + 809dc: 8c62 ldrh r2, [r4, #34] ; 0x22 + 809de: f8bd 300e ldrh.w r3, [sp, #14] + 809e2: 429a cmp r2, r3 + 809e4: d1ef bne.n 809c6 + + return EMAC_RX_NULL; + 809e6: 2003 movs r0, #3 + 809e8: e05a b.n 80aa0 + } + /* Copy the buffer into the application frame */ + us_buffer_length = EMAC_RX_UNITSIZE; + if ((tmp_ul_frame_size + us_buffer_length) > ul_frame_size) { + 809ea: f108 0380 add.w r3, r8, #128 ; 0x80 + 809ee: 455b cmp r3, fp + us_buffer_length = ul_frame_size - tmp_ul_frame_size; + 809f0: bf86 itte hi + 809f2: ebc8 0a0b rsbhi sl, r8, fp + 809f6: fa1f fa8a uxthhi.w sl, sl + } while (us_tmp_idx != p_emac_dev->us_rx_idx); + + return EMAC_RX_NULL; + } + /* Copy the buffer into the application frame */ + us_buffer_length = EMAC_RX_UNITSIZE; + 809fa: f04f 0a80 movls.w sl, #128 ; 0x80 + if ((tmp_ul_frame_size + us_buffer_length) > ul_frame_size) { + us_buffer_length = ul_frame_size - tmp_ul_frame_size; + } + + memcpy(p_tmp_frame, + (void *)(p_rx_td->addr.val & EMAC_RXD_ADDR_MASK), + 809fe: 6829 ldr r1, [r5, #0] + us_buffer_length = EMAC_RX_UNITSIZE; + if ((tmp_ul_frame_size + us_buffer_length) > ul_frame_size) { + us_buffer_length = ul_frame_size - tmp_ul_frame_size; + } + + memcpy(p_tmp_frame, + 80a00: 4648 mov r0, r9 + 80a02: f021 0103 bic.w r1, r1, #3 + 80a06: 4652 mov r2, sl + 80a08: 4b28 ldr r3, [pc, #160] ; (80aac ) + 80a0a: 4798 blx r3 + (void *)(p_rx_td->addr.val & EMAC_RXD_ADDR_MASK), + us_buffer_length); + p_tmp_frame += us_buffer_length; + 80a0c: 44d1 add r9, sl + tmp_ul_frame_size += us_buffer_length; + 80a0e: 44d0 add r8, sl + + /* An end of frame has been received, return the data */ + if ((p_rx_td->status.val & EMAC_RXD_EOF) == EMAC_RXD_EOF) { + 80a10: 686b ldr r3, [r5, #4] + 80a12: f413 4f00 tst.w r3, #32768 ; 0x8000 + 80a16: d028 beq.n 80a6a + /* Frame size from the EMAC */ + *p_rcv_size = (p_rx_td->status.val & EMAC_RXD_LEN_MASK); + 80a18: f3c3 030b ubfx r3, r3, #0, #12 + 80a1c: 9a01 ldr r2, [sp, #4] + 80a1e: 6013 str r3, [r2, #0] + + /* All data have been copied in the application frame buffer => release TD */ + while (p_emac_dev->us_rx_idx != us_tmp_idx) { + 80a20: 8c63 ldrh r3, [r4, #34] ; 0x22 + 80a22: f8bd 200e ldrh.w r2, [sp, #14] + 80a26: 429a cmp r2, r3 + 80a28: d011 beq.n 80a4e + p_rx_td = &p_emac_dev->p_rx_dscr[p_emac_dev->us_rx_idx]; + p_rx_td->addr.val &= ~(EMAC_RXD_OWNERSHIP); + circ_inc(&p_emac_dev->us_rx_idx, p_emac_dev->us_rx_list_size); + 80a2a: f104 0622 add.w r6, r4, #34 ; 0x22 + 80a2e: 4d1e ldr r5, [pc, #120] ; (80aa8 ) + /* Frame size from the EMAC */ + *p_rcv_size = (p_rx_td->status.val & EMAC_RXD_LEN_MASK); + + /* All data have been copied in the application frame buffer => release TD */ + while (p_emac_dev->us_rx_idx != us_tmp_idx) { + p_rx_td = &p_emac_dev->p_rx_dscr[p_emac_dev->us_rx_idx]; + 80a30: 68e1 ldr r1, [r4, #12] + p_rx_td->addr.val &= ~(EMAC_RXD_OWNERSHIP); + 80a32: f851 2033 ldr.w r2, [r1, r3, lsl #3] + 80a36: f022 0201 bic.w r2, r2, #1 + 80a3a: f841 2033 str.w r2, [r1, r3, lsl #3] + circ_inc(&p_emac_dev->us_rx_idx, p_emac_dev->us_rx_list_size); + 80a3e: 4630 mov r0, r6 + 80a40: 8c21 ldrh r1, [r4, #32] + 80a42: 47a8 blx r5 + if ((p_rx_td->status.val & EMAC_RXD_EOF) == EMAC_RXD_EOF) { + /* Frame size from the EMAC */ + *p_rcv_size = (p_rx_td->status.val & EMAC_RXD_LEN_MASK); + + /* All data have been copied in the application frame buffer => release TD */ + while (p_emac_dev->us_rx_idx != us_tmp_idx) { + 80a44: 8c63 ldrh r3, [r4, #34] ; 0x22 + 80a46: f8bd 200e ldrh.w r2, [sp, #14] + 80a4a: 429a cmp r2, r3 + 80a4c: d1f0 bne.n 80a30 + p_rx_td->addr.val &= ~(EMAC_RXD_OWNERSHIP); + circ_inc(&p_emac_dev->us_rx_idx, p_emac_dev->us_rx_list_size); + } + + /* Application frame buffer is too small so that all data have not been copied */ + if (tmp_ul_frame_size < *p_rcv_size) { + 80a4e: 9b01 ldr r3, [sp, #4] + 80a50: 6818 ldr r0, [r3, #0] + return EMAC_SIZE_TOO_SMALL; + } + + return EMAC_OK; + 80a52: 4540 cmp r0, r8 + 80a54: bf8c ite hi + 80a56: 2004 movhi r0, #4 + 80a58: 2000 movls r0, #0 + 80a5a: e021 b.n 80aa0 + } + } + /* SOF has not been detected, skip the fragment */ + else { + p_rx_td->addr.val &= ~(EMAC_RXD_OWNERSHIP); + 80a5c: 682b ldr r3, [r5, #0] + 80a5e: f023 0301 bic.w r3, r3, #1 + 80a62: 602b str r3, [r5, #0] + p_emac_dev->us_rx_idx = us_tmp_idx; + 80a64: f8bd 300e ldrh.w r3, [sp, #14] + 80a68: 8463 strh r3, [r4, #34] ; 0x22 + } + + /* Process the next buffer */ + p_rx_td = &p_emac_dev->p_rx_dscr[us_tmp_idx]; + 80a6a: f8bd 200e ldrh.w r2, [sp, #14] + 80a6e: 68e3 ldr r3, [r4, #12] + 80a70: eb03 05c2 add.w r5, r3, r2, lsl #3 + + /* Set the default return value */ + *p_rcv_size = 0; + + /* Process received RX descriptor */ + while ((p_rx_td->addr.val & EMAC_RXD_OWNERSHIP) == EMAC_RXD_OWNERSHIP) { + 80a74: f853 3032 ldr.w r3, [r3, r2, lsl #3] + 80a78: f013 0f01 tst.w r3, #1 + 80a7c: f47f af77 bne.w 8096e + + /* Process the next buffer */ + p_rx_td = &p_emac_dev->p_rx_dscr[us_tmp_idx]; + } + + return EMAC_RX_NULL; + 80a80: 2003 movs r0, #3 + 80a82: e00d b.n 80aa0 + emac_rx_descriptor_t *p_rx_td = + &p_emac_dev->p_rx_dscr[p_emac_dev->us_rx_idx]; + int8_t c_is_frame = 0; + + if (p_frame == NULL) + return EMAC_PARAM; + 80a84: 2005 movs r0, #5 + 80a86: e00b b.n 80aa0 + + /* Process the next buffer */ + p_rx_td = &p_emac_dev->p_rx_dscr[us_tmp_idx]; + } + + return EMAC_RX_NULL; + 80a88: 2003 movs r0, #3 + 80a8a: e009 b.n 80aa0 + /* Start to gather buffers in a frame */ + c_is_frame = 1; + } + + /* Increment the pointer */ + circ_inc(&us_tmp_idx, p_emac_dev->us_rx_list_size); + 80a8c: f10d 000e add.w r0, sp, #14 + 80a90: 8c21 ldrh r1, [r4, #32] + 80a92: 47b0 blx r6 + 80a94: f8dd 9000 ldr.w r9, [sp] + 80a98: 2701 movs r7, #1 + 80a9a: f04f 0800 mov.w r8, #0 + 80a9e: e78a b.n 809b6 + /* Process the next buffer */ + p_rx_td = &p_emac_dev->p_rx_dscr[us_tmp_idx]; + } + + return EMAC_RX_NULL; +} + 80aa0: b005 add sp, #20 + 80aa2: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 80aa6: bf00 nop + 80aa8: 000806d5 .word 0x000806d5 + 80aac: 00081a91 .word 0x00081a91 + +00080ab0 : + * + * \return Length sent. + */ +uint32_t emac_dev_write(emac_device_t* p_emac_dev, void *p_buffer, + uint32_t ul_size, emac_dev_tx_cb_t func_tx_cb) +{ + 80ab0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + + volatile emac_tx_descriptor_t *p_tx_td; + volatile emac_dev_tx_cb_t *p_func_tx_cb; + + Emac *p_hw = p_emac_dev->p_hw; + 80ab4: 6805 ldr r5, [r0, #0] + + + /* Check parameter */ + if (ul_size > EMAC_TX_UNITSIZE) { + 80ab6: f240 54ee movw r4, #1518 ; 0x5ee + 80aba: 42a2 cmp r2, r4 + 80abc: d833 bhi.n 80b26 + return EMAC_PARAM; + } + + /* Pointers to the current transmit descriptor */ + p_tx_td = &p_emac_dev->p_tx_dscr[p_emac_dev->us_tx_head]; + 80abe: f8d0 e010 ldr.w lr, [r0, #16] + 80ac2: 8cc6 ldrh r6, [r0, #38] ; 0x26 + + /* If no free TxTd, buffer can't be sent, schedule the wakeup callback */ + if (CIRC_SPACE(p_emac_dev->us_tx_head, p_emac_dev->us_tx_tail, + 80ac4: 8d07 ldrh r7, [r0, #40] ; 0x28 + 80ac6: 43f4 mvns r4, r6 + 80ac8: 443c add r4, r7 + 80aca: 8c87 ldrh r7, [r0, #36] ; 0x24 + 80acc: fb94 fcf7 sdiv ip, r4, r7 + 80ad0: fb07 441c mls r4, r7, ip, r4 + 80ad4: b354 cbz r4, 80b2c + 80ad6: 461f mov r7, r3 + 80ad8: 4690 mov r8, r2 + 80ada: 4604 mov r4, r0 + if (ul_size > EMAC_TX_UNITSIZE) { + return EMAC_PARAM; + } + + /* Pointers to the current transmit descriptor */ + p_tx_td = &p_emac_dev->p_tx_dscr[p_emac_dev->us_tx_head]; + 80adc: eb0e 09c6 add.w r9, lr, r6, lsl #3 + p_emac_dev->us_tx_list_size) == 0) { + return EMAC_TX_BUSY; + } + + /* Pointers to the current Tx callback */ + p_func_tx_cb = &p_emac_dev->func_tx_cb_list[p_emac_dev->us_tx_head]; + 80ae0: f8d0 a01c ldr.w sl, [r0, #28] + + /* Set up/copy data to transmission buffer */ + if (p_buffer && ul_size) { + 80ae4: b121 cbz r1, 80af0 + 80ae6: b11a cbz r2, 80af0 + /* Driver manages the ring buffer */ + memcpy((void *)p_tx_td->addr, p_buffer, ul_size); + 80ae8: f85e 0036 ldr.w r0, [lr, r6, lsl #3] + 80aec: 4b11 ldr r3, [pc, #68] ; (80b34 ) + 80aee: 4798 blx r3 + } + + /* Tx callback */ + *p_func_tx_cb = func_tx_cb; + 80af0: f84a 7026 str.w r7, [sl, r6, lsl #2] + + /* Update transmit descriptor status */ + + /* The buffer size defined is the length of ethernet frame, + so it's always the last buffer of the frame. */ + if (p_emac_dev->us_tx_head == p_emac_dev->us_tx_list_size - 1) { + 80af4: 8ce2 ldrh r2, [r4, #38] ; 0x26 + 80af6: 8ca3 ldrh r3, [r4, #36] ; 0x24 + 80af8: 3b01 subs r3, #1 + 80afa: 429a cmp r2, r3 + p_tx_td->status.val = + (ul_size & EMAC_TXD_LEN_MASK) | EMAC_TXD_LAST + 80afc: f3c8 020a ubfx r2, r8, #0, #11 + | EMAC_TXD_WRAP; + 80b00: bf08 it eq + 80b02: f042 4280 orreq.w r2, r2, #1073741824 ; 0x40000000 + } else { + p_tx_td->status.val = + (ul_size & EMAC_TXD_LEN_MASK) | EMAC_TXD_LAST; + 80b06: f442 4200 orr.w r2, r2, #32768 ; 0x8000 + if (p_emac_dev->us_tx_head == p_emac_dev->us_tx_list_size - 1) { + p_tx_td->status.val = + (ul_size & EMAC_TXD_LEN_MASK) | EMAC_TXD_LAST + | EMAC_TXD_WRAP; + } else { + p_tx_td->status.val = + 80b0a: f8c9 2004 str.w r2, [r9, #4] + (ul_size & EMAC_TXD_LEN_MASK) | EMAC_TXD_LAST; + } + + circ_inc(&p_emac_dev->us_tx_head, p_emac_dev->us_tx_list_size); + 80b0e: f104 0026 add.w r0, r4, #38 ; 0x26 + 80b12: 8ca1 ldrh r1, [r4, #36] ; 0x24 + 80b14: 4b08 ldr r3, [pc, #32] ; (80b38 ) + 80b16: 4798 blx r3 + * + * \param p_emac Pointer to the EMAC instance. + */ +static inline void emac_start_transmission(Emac* p_emac) +{ + p_emac->EMAC_NCR |= EMAC_NCR_TSTART; + 80b18: 682b ldr r3, [r5, #0] + 80b1a: f443 7300 orr.w r3, r3, #512 ; 0x200 + 80b1e: 602b str r3, [r5, #0] + + /* Now start to transmit if it is still not done */ + emac_start_transmission(p_hw); + + return EMAC_OK; + 80b20: 2000 movs r0, #0 + 80b22: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + Emac *p_hw = p_emac_dev->p_hw; + + + /* Check parameter */ + if (ul_size > EMAC_TX_UNITSIZE) { + return EMAC_PARAM; + 80b26: 2005 movs r0, #5 + 80b28: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + p_tx_td = &p_emac_dev->p_tx_dscr[p_emac_dev->us_tx_head]; + + /* If no free TxTd, buffer can't be sent, schedule the wakeup callback */ + if (CIRC_SPACE(p_emac_dev->us_tx_head, p_emac_dev->us_tx_tail, + p_emac_dev->us_tx_list_size) == 0) { + return EMAC_TX_BUSY; + 80b2c: 2002 movs r0, #2 + + /* Now start to transmit if it is still not done */ + emac_start_transmission(p_hw); + + return EMAC_OK; +} + 80b2e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 80b32: bf00 nop + 80b34: 00081a91 .word 0x00081a91 + 80b38: 000806d5 .word 0x000806d5 + +00080b3c : + * \brief EMAC Interrupt handler. + * + * \param p_emac_dev Pointer to EMAC device instance. + */ +void emac_handler(emac_device_t* p_emac_dev) +{ + 80b3c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 80b40: b084 sub sp, #16 + 80b42: 4604 mov r4, r0 + Emac *p_hw = p_emac_dev->p_hw; + 80b44: 6807 ldr r7, [r0, #0] + * + * \return Interrupt status. + */ +static inline uint32_t emac_get_interrupt_status(Emac* p_emac) +{ + return p_emac->EMAC_ISR; + 80b46: 6a7b ldr r3, [r7, #36] ; 0x24 + volatile uint32_t ul_rsr; + volatile uint32_t ul_tsr; + uint32_t ul_rx_status_flag; + uint32_t ul_tx_status_flag; + + ul_isr = emac_get_interrupt_status(p_hw); + 80b48: 9303 str r3, [sp, #12] + * + * \param p_emac Pointer to the EMAC instance. + */ +static inline uint32_t emac_get_rx_status(Emac* p_emac) +{ + return p_emac->EMAC_RSR; + 80b4a: 6a3b ldr r3, [r7, #32] + ul_rsr = emac_get_rx_status(p_hw); + 80b4c: 9302 str r3, [sp, #8] + * + * \return Transmit status. + */ +static inline uint32_t emac_get_tx_status(Emac* p_emac) +{ + return p_emac->EMAC_TSR; + 80b4e: 697b ldr r3, [r7, #20] + ul_tsr = emac_get_tx_status(p_hw); + 80b50: 9301 str r3, [sp, #4] + * + * \return Interrupt mask. + */ +static inline uint32_t emac_get_interrupt_mask(Emac* p_emac) +{ + return p_emac->EMAC_IMR; + 80b52: 6b3b ldr r3, [r7, #48] ; 0x30 + + ul_isr &= ~(emac_get_interrupt_mask(p_hw) | 0xFFC300); + 80b54: 9a03 ldr r2, [sp, #12] + 80b56: f443 037f orr.w r3, r3, #16711680 ; 0xff0000 + 80b5a: f443 4343 orr.w r3, r3, #49920 ; 0xc300 + 80b5e: ea22 0303 bic.w r3, r2, r3 + 80b62: 9303 str r3, [sp, #12] + + /* RX packet */ + if ((ul_isr & EMAC_ISR_RCOMP) || (ul_rsr & EMAC_RSR_REC)) { + 80b64: 9b03 ldr r3, [sp, #12] + 80b66: f013 0f02 tst.w r3, #2 + 80b6a: d103 bne.n 80b74 + 80b6c: 9b02 ldr r3, [sp, #8] + 80b6e: f013 0f02 tst.w r3, #2 + 80b72: d010 beq.n 80b96 + ul_rx_status_flag = EMAC_RSR_REC; + + /* Check OVR */ + if (ul_rsr & EMAC_RSR_OVR) { + 80b74: 9b02 ldr r3, [sp, #8] + 80b76: f003 0304 and.w r3, r3, #4 + ul_rx_status_flag |= EMAC_RSR_OVR; + 80b7a: 2b00 cmp r3, #0 + 80b7c: bf0c ite eq + 80b7e: 2002 moveq r0, #2 + 80b80: 2006 movne r0, #6 + } + /* Check BNA */ + if (ul_rsr & EMAC_RSR_BNA) { + 80b82: 9b02 ldr r3, [sp, #8] + 80b84: f013 0f01 tst.w r3, #1 + ul_rx_status_flag |= EMAC_RSR_BNA; + 80b88: bf18 it ne + 80b8a: f040 0001 orrne.w r0, r0, #1 + * \param p_emac Pointer to the EMAC instance. + * \param ul_status Receive status. + */ +static inline void emac_clear_rx_status(Emac* p_emac, uint32_t ul_status) +{ + p_emac->EMAC_RSR = ul_status; + 80b8e: 6238 str r0, [r7, #32] + } + /* Clear status */ + emac_clear_rx_status(p_hw, ul_rx_status_flag); + + /* Invoke callbacks */ + if (p_emac_dev->func_rx_cb) { + 80b90: 6963 ldr r3, [r4, #20] + 80b92: b103 cbz r3, 80b96 + p_emac_dev->func_rx_cb(ul_rx_status_flag); + 80b94: 4798 blx r3 + } + } + + /* TX packet */ + if ((ul_isr & EMAC_ISR_TCOMP) || (ul_tsr & EMAC_TSR_COMP)) { + 80b96: 9b03 ldr r3, [sp, #12] + 80b98: f013 0f80 tst.w r3, #128 ; 0x80 + 80b9c: d103 bne.n 80ba6 + 80b9e: 9b01 ldr r3, [sp, #4] + 80ba0: f013 0f20 tst.w r3, #32 + 80ba4: d067 beq.n 80c76 + ul_tx_status_flag = EMAC_TSR_COMP; + + /* A frame transmitted */ + + /* Check RLE */ + if (ul_tsr & EMAC_TSR_RLES) { + 80ba6: 9b01 ldr r3, [sp, #4] + 80ba8: f013 0f04 tst.w r3, #4 + 80bac: d014 beq.n 80bd8 + /* Status RLE & Number of discarded buffers */ + ul_tx_status_flag = EMAC_TSR_RLES | CIRC_CNT(p_emac_dev->us_tx_head, + 80bae: 8d21 ldrh r1, [r4, #40] ; 0x28 + 80bb0: 8ce3 ldrh r3, [r4, #38] ; 0x26 + 80bb2: 1a5b subs r3, r3, r1 + 80bb4: 8ca5 ldrh r5, [r4, #36] ; 0x24 + 80bb6: fb93 f2f5 sdiv r2, r3, r5 + 80bba: fb05 3512 mls r5, r5, r2, r3 + 80bbe: f045 0504 orr.w r5, r5, #4 + p_emac_dev->us_tx_tail, p_emac_dev->us_tx_list_size); + p_tx_cb = &p_emac_dev->func_tx_cb_list[p_emac_dev->us_tx_tail]; + 80bc2: 69e6 ldr r6, [r4, #28] + 80bc4: eb06 0681 add.w r6, r6, r1, lsl #2 + emac_reset_tx_mem(p_emac_dev); + 80bc8: 4620 mov r0, r4 + 80bca: 4b2c ldr r3, [pc, #176] ; (80c7c ) + 80bcc: 4798 blx r3 + * \param uc_enable 0 to disable EMAC transmit, else to enable it. + */ +static inline void emac_enable_transmit(Emac* p_emac, uint8_t uc_enable) +{ + if (uc_enable) { + p_emac->EMAC_NCR |= EMAC_NCR_TE; + 80bce: 683b ldr r3, [r7, #0] + 80bd0: f043 0308 orr.w r3, r3, #8 + 80bd4: 603b str r3, [r7, #0] + 80bd6: e000 b.n 80bda + } + + /* TX packet */ + if ((ul_isr & EMAC_ISR_TCOMP) || (ul_tsr & EMAC_TSR_COMP)) { + + ul_tx_status_flag = EMAC_TSR_COMP; + 80bd8: 2520 movs r5, #32 + p_tx_cb = &p_emac_dev->func_tx_cb_list[p_emac_dev->us_tx_tail]; + emac_reset_tx_mem(p_emac_dev); + emac_enable_transmit(p_hw, 1); + } + /* Check COL */ + if (ul_tsr & EMAC_TSR_COL) { + 80bda: 9b01 ldr r3, [sp, #4] + 80bdc: f013 0f02 tst.w r3, #2 + ul_tx_status_flag |= EMAC_TSR_COL; + 80be0: bf18 it ne + 80be2: f045 0502 orrne.w r5, r5, #2 + } + /* Check BEX */ + if (ul_tsr & EMAC_TSR_BEX) { + 80be6: 9b01 ldr r3, [sp, #4] + 80be8: f013 0f10 tst.w r3, #16 + ul_tx_status_flag |= EMAC_TSR_BEX; + 80bec: bf18 it ne + 80bee: f045 0510 orrne.w r5, r5, #16 + } + /* Check UND */ + if (ul_tsr & EMAC_TSR_UND) { + 80bf2: 9b01 ldr r3, [sp, #4] + 80bf4: f013 0f40 tst.w r3, #64 ; 0x40 + ul_tx_status_flag |= EMAC_TSR_UND; + 80bf8: bf18 it ne + 80bfa: f045 0540 orrne.w r5, r5, #64 ; 0x40 + * \param p_emac Pointer to the EMAC instance. + * \param ul_status Transmit status. + */ +static inline void emac_clear_tx_status(Emac* p_emac, uint32_t ul_status) +{ + p_emac->EMAC_TSR = ul_status; + 80bfe: 617d str r5, [r7, #20] + } + /* Clear status */ + emac_clear_tx_status(p_hw, ul_tx_status_flag); + + if (!CIRC_EMPTY(p_emac_dev->us_tx_head, p_emac_dev->us_tx_tail)) { + 80c00: 8ce2 ldrh r2, [r4, #38] ; 0x26 + 80c02: 8d23 ldrh r3, [r4, #40] ; 0x28 + 80c04: 429a cmp r2, r3 + 80c06: d01e beq.n 80c46 + /* Notify upper layer that a packet has been sent */ + if (*p_tx_cb) { + (*p_tx_cb) (ul_tx_status_flag); + } + + circ_inc(&p_emac_dev->us_tx_tail, p_emac_dev->us_tx_list_size); + 80c08: f104 0828 add.w r8, r4, #40 ; 0x28 + 80c0c: 4f1c ldr r7, [pc, #112] ; (80c80 ) + emac_clear_tx_status(p_hw, ul_tx_status_flag); + + if (!CIRC_EMPTY(p_emac_dev->us_tx_head, p_emac_dev->us_tx_tail)) { + /* Check the buffers */ + do { + p_tx_td = &p_emac_dev->p_tx_dscr[p_emac_dev->us_tx_tail]; + 80c0e: 8d22 ldrh r2, [r4, #40] ; 0x28 + p_tx_cb = &p_emac_dev->func_tx_cb_list[p_emac_dev->us_tx_tail]; + 80c10: 69e1 ldr r1, [r4, #28] + 80c12: eb01 0682 add.w r6, r1, r2, lsl #2 + /* Any error? Exit if buffer has not been sent yet */ + if ((p_tx_td->status.val & EMAC_TXD_USED) == 0) { + 80c16: 6923 ldr r3, [r4, #16] + 80c18: eb03 03c2 add.w r3, r3, r2, lsl #3 + 80c1c: 685b ldr r3, [r3, #4] + 80c1e: 2b00 cmp r3, #0 + 80c20: da11 bge.n 80c46 + break; + } + + /* Notify upper layer that a packet has been sent */ + if (*p_tx_cb) { + 80c22: f851 3022 ldr.w r3, [r1, r2, lsl #2] + 80c26: b10b cbz r3, 80c2c + (*p_tx_cb) (ul_tx_status_flag); + 80c28: 4628 mov r0, r5 + 80c2a: 4798 blx r3 + } + + circ_inc(&p_emac_dev->us_tx_tail, p_emac_dev->us_tx_list_size); + 80c2c: 4640 mov r0, r8 + 80c2e: 8ca1 ldrh r1, [r4, #36] ; 0x24 + 80c30: 47b8 blx r7 + } while (CIRC_CNT(p_emac_dev->us_tx_head, p_emac_dev->us_tx_tail, + 80c32: 8ce3 ldrh r3, [r4, #38] ; 0x26 + 80c34: 8d22 ldrh r2, [r4, #40] ; 0x28 + 80c36: 1a9b subs r3, r3, r2 + 80c38: 8ca1 ldrh r1, [r4, #36] ; 0x24 + 80c3a: fb93 f2f1 sdiv r2, r3, r1 + 80c3e: fb01 3312 mls r3, r1, r2, r3 + 80c42: 2b00 cmp r3, #0 + 80c44: d1e3 bne.n 80c0e + p_emac_dev->us_tx_list_size)); + } + + if (ul_tsr & EMAC_TSR_RLES) { + 80c46: 9b01 ldr r3, [sp, #4] + 80c48: f013 0f04 tst.w r3, #4 + 80c4c: d003 beq.n 80c56 + /* Notify upper layer RLE */ + if (*p_tx_cb) { + 80c4e: 6833 ldr r3, [r6, #0] + 80c50: b10b cbz r3, 80c56 + (*p_tx_cb) (ul_tx_status_flag); + 80c52: 4628 mov r0, r5 + 80c54: 4798 blx r3 + } + } + + /* If a wakeup has been scheduled, notify upper layer that it can + send other packets, and the sending will be successful. */ + if ((CIRC_SPACE(p_emac_dev->us_tx_head, p_emac_dev->us_tx_tail, + 80c56: 8d22 ldrh r2, [r4, #40] ; 0x28 + 80c58: 8ce3 ldrh r3, [r4, #38] ; 0x26 + 80c5a: 43db mvns r3, r3 + 80c5c: 4413 add r3, r2 + 80c5e: 8ca1 ldrh r1, [r4, #36] ; 0x24 + 80c60: fb93 f2f1 sdiv r2, r3, r1 + 80c64: fb01 3312 mls r3, r1, r2, r3 + p_emac_dev->us_tx_list_size) >= p_emac_dev->uc_wakeup_threshold) + 80c68: f894 202a ldrb.w r2, [r4, #42] ; 0x2a + } + } + + /* If a wakeup has been scheduled, notify upper layer that it can + send other packets, and the sending will be successful. */ + if ((CIRC_SPACE(p_emac_dev->us_tx_head, p_emac_dev->us_tx_tail, + 80c6c: 4293 cmp r3, r2 + 80c6e: db02 blt.n 80c76 + p_emac_dev->us_tx_list_size) >= p_emac_dev->uc_wakeup_threshold) + && p_emac_dev->func_wakeup_cb) { + 80c70: 69a3 ldr r3, [r4, #24] + 80c72: b103 cbz r3, 80c76 + p_emac_dev->func_wakeup_cb(); + 80c74: 4798 blx r3 + } + } +} + 80c76: b004 add sp, #16 + 80c78: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 80c7c: 000806e5 .word 0x000806e5 + 80c80: 000806d5 .word 0x000806d5 + +00080c84 : + const uint32_t ul_mask) +{ + uint32_t ul_sr; + + /* Disable interrupts on the pin(s) */ + p_pio->PIO_IDR = ul_mask; + 80c84: 6442 str r2, [r0, #68] ; 0x44 + case PIO_OUTPUT_1: + case PIO_NOT_A_PIN: + return; + } +#elif (SAM3XA|| SAM3U) + switch (ul_type) { + 80c86: f1b1 5f80 cmp.w r1, #268435456 ; 0x10000000 + 80c8a: d016 beq.n 80cba + 80c8c: d804 bhi.n 80c98 + 80c8e: b1c1 cbz r1, 80cc2 + 80c90: f1b1 6f00 cmp.w r1, #134217728 ; 0x8000000 + 80c94: d00a beq.n 80cac + 80c96: e013 b.n 80cc0 + 80c98: f1b1 5f40 cmp.w r1, #805306368 ; 0x30000000 + 80c9c: d011 beq.n 80cc2 + 80c9e: f1b1 5f60 cmp.w r1, #939524096 ; 0x38000000 + 80ca2: d00e beq.n 80cc2 + 80ca4: f1b1 5f20 cmp.w r1, #671088640 ; 0x28000000 + 80ca8: d10a bne.n 80cc0 + 80caa: 4770 bx lr + case PIO_PERIPH_A: + ul_sr = p_pio->PIO_ABSR; + 80cac: 6f03 ldr r3, [r0, #112] ; 0x70 + p_pio->PIO_ABSR &= (~ul_mask & ul_sr); + 80cae: 6f01 ldr r1, [r0, #112] ; 0x70 + 80cb0: 400b ands r3, r1 + 80cb2: ea23 0302 bic.w r3, r3, r2 + 80cb6: 6703 str r3, [r0, #112] ; 0x70 + break; + 80cb8: e002 b.n 80cc0 + + case PIO_PERIPH_B: + ul_sr = p_pio->PIO_ABSR; + 80cba: 6f03 ldr r3, [r0, #112] ; 0x70 + p_pio->PIO_ABSR = (ul_mask | ul_sr); + 80cbc: 4313 orrs r3, r2 + 80cbe: 6703 str r3, [r0, #112] ; 0x70 +#else +#error "Unsupported device" +#endif + + /* Remove the pins from under the control of PIO */ + p_pio->PIO_PDR = ul_mask; + 80cc0: 6042 str r2, [r0, #4] + 80cc2: 4770 bx lr + +00080cc4 : + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Interrupt sources bit map. + */ +void pio_disable_interrupt(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_IDR = ul_mask; + 80cc4: 6441 str r1, [r0, #68] ; 0x44 + */ +void pio_pull_up(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_pull_up_enable) +{ + /* Enable the pull-up(s) if necessary */ + if (ul_pull_up_enable) { + 80cc6: f012 0f01 tst.w r2, #1 + p_pio->PIO_PUER = ul_mask; + 80cca: bf14 ite ne + 80ccc: 6641 strne r1, [r0, #100] ; 0x64 + } else { + p_pio->PIO_PUDR = ul_mask; + 80cce: 6601 streq r1, [r0, #96] ; 0x60 +{ + pio_disable_interrupt(p_pio, ul_mask); + pio_pull_up(p_pio, ul_mask, ul_attribute & PIO_PULLUP); + + /* Enable Input Filter if necessary */ + if (ul_attribute & (PIO_DEGLITCH | PIO_DEBOUNCE)) { + 80cd0: f012 0f0a tst.w r2, #10 + p_pio->PIO_IFER = ul_mask; + 80cd4: bf14 ite ne + 80cd6: 6201 strne r1, [r0, #32] + } else { + p_pio->PIO_IFDR = ul_mask; + 80cd8: 6241 streq r1, [r0, #36] ; 0x24 + p_pio->PIO_IFSCER = ul_mask; + } + } +#elif (SAM3XA|| SAM3U) + /* Enable de-glitch or de-bounce if necessary */ + if (ul_attribute & PIO_DEGLITCH) { + 80cda: f012 0f02 tst.w r2, #2 + 80cde: d002 beq.n 80ce6 + p_pio->PIO_SCIFSR = ul_mask; + 80ce0: f8c0 1080 str.w r1, [r0, #128] ; 0x80 + 80ce4: e004 b.n 80cf0 + } else { + if (ul_attribute & PIO_DEBOUNCE) { + 80ce6: f012 0f08 tst.w r2, #8 + p_pio->PIO_DIFSR = ul_mask; + 80cea: bf18 it ne + 80cec: f8c0 1084 strne.w r1, [r0, #132] ; 0x84 +#else +#error "Unsupported device" +#endif + + /* Configure pin as input */ + p_pio->PIO_ODR = ul_mask; + 80cf0: 6141 str r1, [r0, #20] + p_pio->PIO_PER = ul_mask; + 80cf2: 6001 str r1, [r0, #0] + 80cf4: 4770 bx lr + 80cf6: bf00 nop + +00080cf8 : + */ +void pio_set_output(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_default_level, + const uint32_t ul_multidrive_enable, + const uint32_t ul_pull_up_enable) +{ + 80cf8: b410 push {r4} + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Interrupt sources bit map. + */ +void pio_disable_interrupt(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_IDR = ul_mask; + 80cfa: 6441 str r1, [r0, #68] ; 0x44 + */ +void pio_pull_up(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_pull_up_enable) +{ + /* Enable the pull-up(s) if necessary */ + if (ul_pull_up_enable) { + 80cfc: 9c01 ldr r4, [sp, #4] + 80cfe: b10c cbz r4, 80d04 + p_pio->PIO_PUER = ul_mask; + 80d00: 6641 str r1, [r0, #100] ; 0x64 + 80d02: e000 b.n 80d06 + } else { + p_pio->PIO_PUDR = ul_mask; + 80d04: 6601 str r1, [r0, #96] ; 0x60 +{ + pio_disable_interrupt(p_pio, ul_mask); + pio_pull_up(p_pio, ul_mask, ul_pull_up_enable); + + /* Enable multi-drive if necessary */ + if (ul_multidrive_enable) { + 80d06: b10b cbz r3, 80d0c + p_pio->PIO_MDER = ul_mask; + 80d08: 6501 str r1, [r0, #80] ; 0x50 + 80d0a: e000 b.n 80d0e + } else { + p_pio->PIO_MDDR = ul_mask; + 80d0c: 6541 str r1, [r0, #84] ; 0x54 + } + + /* Set default value */ + if (ul_default_level) { + 80d0e: b10a cbz r2, 80d14 + p_pio->PIO_SODR = ul_mask; + 80d10: 6301 str r1, [r0, #48] ; 0x30 + 80d12: e000 b.n 80d16 + } else { + p_pio->PIO_CODR = ul_mask; + 80d14: 6341 str r1, [r0, #52] ; 0x34 + } + + /* Configure pin(s) as output(s) */ + p_pio->PIO_OER = ul_mask; + 80d16: 6101 str r1, [r0, #16] + p_pio->PIO_PER = ul_mask; + 80d18: 6001 str r1, [r0, #0] +} + 80d1a: f85d 4b04 ldr.w r4, [sp], #4 + 80d1e: 4770 bx lr + +00080d20 : + * + * \return The interrupt status mask value. + */ +uint32_t pio_get_interrupt_status(const Pio *p_pio) +{ + return p_pio->PIO_ISR; + 80d20: 6cc0 ldr r0, [r0, #76] ; 0x4c +} + 80d22: 4770 bx lr + +00080d24 : + * + * \return The interrupt mask value. + */ +uint32_t pio_get_interrupt_mask(const Pio *p_pio) +{ + return p_pio->PIO_IMR; + 80d24: 6c80 ldr r0, [r0, #72] ; 0x48 +} + 80d26: 4770 bx lr + +00080d28 : + * \param ul_flags Pins attributes. + * + * \return Whether the pin(s) have been configured properly. + */ +uint32_t pio_configure_pin(uint32_t ul_pin, const uint32_t ul_flags) +{ + 80d28: b570 push {r4, r5, r6, lr} + 80d2a: b082 sub sp, #8 + 80d2c: 460d mov r5, r1 + p_pio = PIOC; + } else { + p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5))); + } +#else + p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5))); + 80d2e: 0943 lsrs r3, r0, #5 + 80d30: f503 1300 add.w r3, r3, #2097152 ; 0x200000 + 80d34: f203 7307 addw r3, r3, #1799 ; 0x707 + 80d38: 025c lsls r4, r3, #9 +uint32_t pio_configure_pin(uint32_t ul_pin, const uint32_t ul_flags) +{ + Pio *p_pio = pio_get_pin_group(ul_pin); + + /* Configure pins */ + switch (ul_flags & PIO_TYPE_Msk) { + 80d3a: f001 43f0 and.w r3, r1, #2013265920 ; 0x78000000 + 80d3e: f1b3 5f20 cmp.w r3, #671088640 ; 0x28000000 + 80d42: d030 beq.n 80da6 + 80d44: d806 bhi.n 80d54 + 80d46: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 + 80d4a: d00a beq.n 80d62 + 80d4c: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 + 80d50: d018 beq.n 80d84 + 80d52: e049 b.n 80de8 + 80d54: f1b3 5f40 cmp.w r3, #805306368 ; 0x30000000 + 80d58: d030 beq.n 80dbc + 80d5a: f1b3 5f60 cmp.w r3, #939524096 ; 0x38000000 + 80d5e: d02d beq.n 80dbc + 80d60: e042 b.n 80de8 + case PIO_TYPE_PIO_PERIPH_A: + pio_set_peripheral(p_pio, PIO_PERIPH_A, (1 << (ul_pin & 0x1F))); + 80d62: f000 001f and.w r0, r0, #31 + 80d66: 2601 movs r6, #1 + 80d68: 4086 lsls r6, r0 + 80d6a: 4620 mov r0, r4 + 80d6c: f04f 6100 mov.w r1, #134217728 ; 0x8000000 + 80d70: 4632 mov r2, r6 + 80d72: 4b1f ldr r3, [pc, #124] ; (80df0 ) + 80d74: 4798 blx r3 + */ +void pio_pull_up(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_pull_up_enable) +{ + /* Enable the pull-up(s) if necessary */ + if (ul_pull_up_enable) { + 80d76: f015 0f01 tst.w r5, #1 + p_pio->PIO_PUER = ul_mask; + 80d7a: bf14 ite ne + 80d7c: 6666 strne r6, [r4, #100] ; 0x64 + } else { + p_pio->PIO_PUDR = ul_mask; + 80d7e: 6626 streq r6, [r4, #96] ; 0x60 + + default: + return 0; + } + + return 1; + 80d80: 2001 movs r0, #1 + 80d82: e032 b.n 80dea + pio_set_peripheral(p_pio, PIO_PERIPH_A, (1 << (ul_pin & 0x1F))); + pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)), + (ul_flags & PIO_PULLUP)); + break; + case PIO_TYPE_PIO_PERIPH_B: + pio_set_peripheral(p_pio, PIO_PERIPH_B, (1 << (ul_pin & 0x1F))); + 80d84: f000 001f and.w r0, r0, #31 + 80d88: 2601 movs r6, #1 + 80d8a: 4086 lsls r6, r0 + 80d8c: 4620 mov r0, r4 + 80d8e: f04f 5180 mov.w r1, #268435456 ; 0x10000000 + 80d92: 4632 mov r2, r6 + 80d94: 4b16 ldr r3, [pc, #88] ; (80df0 ) + 80d96: 4798 blx r3 + */ +void pio_pull_up(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_pull_up_enable) +{ + /* Enable the pull-up(s) if necessary */ + if (ul_pull_up_enable) { + 80d98: f015 0f01 tst.w r5, #1 + p_pio->PIO_PUER = ul_mask; + 80d9c: bf14 ite ne + 80d9e: 6666 strne r6, [r4, #100] ; 0x64 + } else { + p_pio->PIO_PUDR = ul_mask; + 80da0: 6626 streq r6, [r4, #96] ; 0x60 + + default: + return 0; + } + + return 1; + 80da2: 2001 movs r0, #1 + 80da4: e021 b.n 80dea + (ul_flags & PIO_PULLUP)); + break; +#endif + + case PIO_TYPE_PIO_INPUT: + pio_set_input(p_pio, (1 << (ul_pin & 0x1F)), ul_flags); + 80da6: f000 031f and.w r3, r0, #31 + 80daa: 2601 movs r6, #1 + 80dac: 4620 mov r0, r4 + 80dae: fa06 f103 lsl.w r1, r6, r3 + 80db2: 462a mov r2, r5 + 80db4: 4b0f ldr r3, [pc, #60] ; (80df4 ) + 80db6: 4798 blx r3 + + default: + return 0; + } + + return 1; + 80db8: 4630 mov r0, r6 + break; +#endif + + case PIO_TYPE_PIO_INPUT: + pio_set_input(p_pio, (1 << (ul_pin & 0x1F)), ul_flags); + break; + 80dba: e016 b.n 80dea + + case PIO_TYPE_PIO_OUTPUT_0: + case PIO_TYPE_PIO_OUTPUT_1: + pio_set_output(p_pio, (1 << (ul_pin & 0x1F)), + 80dbc: f000 031f and.w r3, r0, #31 + 80dc0: 2601 movs r6, #1 + ((ul_flags & PIO_TYPE_PIO_OUTPUT_1) + 80dc2: f005 5260 and.w r2, r5, #939524096 ; 0x38000000 + pio_set_input(p_pio, (1 << (ul_pin & 0x1F)), ul_flags); + break; + + case PIO_TYPE_PIO_OUTPUT_0: + case PIO_TYPE_PIO_OUTPUT_1: + pio_set_output(p_pio, (1 << (ul_pin & 0x1F)), + 80dc6: ea05 0106 and.w r1, r5, r6 + 80dca: 9100 str r1, [sp, #0] + 80dcc: 4620 mov r0, r4 + 80dce: fa06 f103 lsl.w r1, r6, r3 + 80dd2: f1b2 5f60 cmp.w r2, #939524096 ; 0x38000000 + 80dd6: bf14 ite ne + 80dd8: 2200 movne r2, #0 + 80dda: 2201 moveq r2, #1 + 80ddc: f3c5 0380 ubfx r3, r5, #2, #1 + 80de0: 4c05 ldr r4, [pc, #20] ; (80df8 ) + 80de2: 47a0 blx r4 + + default: + return 0; + } + + return 1; + 80de4: 4630 mov r0, r6 + pio_set_output(p_pio, (1 << (ul_pin & 0x1F)), + ((ul_flags & PIO_TYPE_PIO_OUTPUT_1) + == PIO_TYPE_PIO_OUTPUT_1) ? 1 : 0, + (ul_flags & PIO_OPENDRAIN) ? 1 : 0, + (ul_flags & PIO_PULLUP) ? 1 : 0); + break; + 80de6: e000 b.n 80dea + + default: + return 0; + 80de8: 2000 movs r0, #0 + } + + return 1; +} + 80dea: b002 add sp, #8 + 80dec: bd70 pop {r4, r5, r6, pc} + 80dee: bf00 nop + 80df0: 00080c85 .word 0x00080c85 + 80df4: 00080cc5 .word 0x00080cc5 + 80df8: 00080cf9 .word 0x00080cf9 + +00080dfc : + * + * \return Whether the pin(s) have been configured properly. + */ +uint32_t pio_configure_pin_group(Pio *p_pio, + uint32_t ul_mask, const uint32_t ul_flags) +{ + 80dfc: b570 push {r4, r5, r6, lr} + 80dfe: b082 sub sp, #8 + 80e00: 4606 mov r6, r0 + 80e02: 460d mov r5, r1 + 80e04: 4614 mov r4, r2 + /* Configure pins */ + switch (ul_flags & PIO_TYPE_Msk) { + 80e06: f002 43f0 and.w r3, r2, #2013265920 ; 0x78000000 + 80e0a: f1b3 5f20 cmp.w r3, #671088640 ; 0x28000000 + 80e0e: d026 beq.n 80e5e + 80e10: d806 bhi.n 80e20 + 80e12: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 + 80e16: d00a beq.n 80e2e + 80e18: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 + 80e1c: d013 beq.n 80e46 + 80e1e: e034 b.n 80e8a + 80e20: f1b3 5f40 cmp.w r3, #805306368 ; 0x30000000 + 80e24: d01f beq.n 80e66 + 80e26: f1b3 5f60 cmp.w r3, #939524096 ; 0x38000000 + 80e2a: d01c beq.n 80e66 + 80e2c: e02d b.n 80e8a + case PIO_TYPE_PIO_PERIPH_A: + pio_set_peripheral(p_pio, PIO_PERIPH_A, ul_mask); + 80e2e: f04f 6100 mov.w r1, #134217728 ; 0x8000000 + 80e32: 462a mov r2, r5 + 80e34: 4b16 ldr r3, [pc, #88] ; (80e90 ) + 80e36: 4798 blx r3 + */ +void pio_pull_up(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_pull_up_enable) +{ + /* Enable the pull-up(s) if necessary */ + if (ul_pull_up_enable) { + 80e38: f014 0f01 tst.w r4, #1 + p_pio->PIO_PUER = ul_mask; + 80e3c: bf14 ite ne + 80e3e: 6675 strne r5, [r6, #100] ; 0x64 + } else { + p_pio->PIO_PUDR = ul_mask; + 80e40: 6635 streq r5, [r6, #96] ; 0x60 + + default: + return 0; + } + + return 1; + 80e42: 2001 movs r0, #1 + 80e44: e022 b.n 80e8c + case PIO_TYPE_PIO_PERIPH_A: + pio_set_peripheral(p_pio, PIO_PERIPH_A, ul_mask); + pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP)); + break; + case PIO_TYPE_PIO_PERIPH_B: + pio_set_peripheral(p_pio, PIO_PERIPH_B, ul_mask); + 80e46: f04f 5180 mov.w r1, #268435456 ; 0x10000000 + 80e4a: 462a mov r2, r5 + 80e4c: 4b10 ldr r3, [pc, #64] ; (80e90 ) + 80e4e: 4798 blx r3 + */ +void pio_pull_up(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_pull_up_enable) +{ + /* Enable the pull-up(s) if necessary */ + if (ul_pull_up_enable) { + 80e50: f014 0f01 tst.w r4, #1 + p_pio->PIO_PUER = ul_mask; + 80e54: bf14 ite ne + 80e56: 6675 strne r5, [r6, #100] ; 0x64 + } else { + p_pio->PIO_PUDR = ul_mask; + 80e58: 6635 streq r5, [r6, #96] ; 0x60 + + default: + return 0; + } + + return 1; + 80e5a: 2001 movs r0, #1 + 80e5c: e016 b.n 80e8c + pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP)); + break; +#endif + + case PIO_TYPE_PIO_INPUT: + pio_set_input(p_pio, ul_mask, ul_flags); + 80e5e: 4b0d ldr r3, [pc, #52] ; (80e94 ) + 80e60: 4798 blx r3 + + default: + return 0; + } + + return 1; + 80e62: 2001 movs r0, #1 + break; +#endif + + case PIO_TYPE_PIO_INPUT: + pio_set_input(p_pio, ul_mask, ul_flags); + break; + 80e64: e012 b.n 80e8c + + case PIO_TYPE_PIO_OUTPUT_0: + case PIO_TYPE_PIO_OUTPUT_1: + pio_set_output(p_pio, ul_mask, + ((ul_flags & PIO_TYPE_PIO_OUTPUT_1) + 80e66: f004 5260 and.w r2, r4, #939524096 ; 0x38000000 + pio_set_input(p_pio, ul_mask, ul_flags); + break; + + case PIO_TYPE_PIO_OUTPUT_0: + case PIO_TYPE_PIO_OUTPUT_1: + pio_set_output(p_pio, ul_mask, + 80e6a: f004 0301 and.w r3, r4, #1 + 80e6e: 9300 str r3, [sp, #0] + 80e70: 4630 mov r0, r6 + 80e72: 4629 mov r1, r5 + 80e74: f1b2 5f60 cmp.w r2, #939524096 ; 0x38000000 + 80e78: bf14 ite ne + 80e7a: 2200 movne r2, #0 + 80e7c: 2201 moveq r2, #1 + 80e7e: f3c4 0380 ubfx r3, r4, #2, #1 + 80e82: 4c05 ldr r4, [pc, #20] ; (80e98 ) + 80e84: 47a0 blx r4 + + default: + return 0; + } + + return 1; + 80e86: 2001 movs r0, #1 + pio_set_output(p_pio, ul_mask, + ((ul_flags & PIO_TYPE_PIO_OUTPUT_1) + == PIO_TYPE_PIO_OUTPUT_1) ? 1 : 0, + (ul_flags & PIO_OPENDRAIN) ? 1 : 0, + (ul_flags & PIO_PULLUP) ? 1 : 0); + break; + 80e88: e000 b.n 80e8c + + default: + return 0; + 80e8a: 2000 movs r0, #0 + } + + return 1; +} + 80e8c: b002 add sp, #8 + 80e8e: bd70 pop {r4, r5, r6, pc} + 80e90: 00080c85 .word 0x00080c85 + 80e94: 00080cc5 .word 0x00080cc5 + 80e98: 00080cf9 .word 0x00080cf9 + +00080e9c : + * + * \param p_pio PIO controller base address. + * \param ul_id PIO controller ID. + */ +void pio_handler_process(Pio *p_pio, uint32_t ul_id) +{ + 80e9c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 80ea0: 4604 mov r4, r0 + 80ea2: 4688 mov r8, r1 + uint32_t status; + uint32_t i; + + /* Read PIO controller status */ + status = pio_get_interrupt_status(p_pio); + 80ea4: 4b0e ldr r3, [pc, #56] ; (80ee0 ) + 80ea6: 4798 blx r3 + 80ea8: 4605 mov r5, r0 + status &= pio_get_interrupt_mask(p_pio); + 80eaa: 4620 mov r0, r4 + 80eac: 4b0d ldr r3, [pc, #52] ; (80ee4 ) + 80eae: 4798 blx r3 + + /* Check pending events */ + if (status != 0) { + 80eb0: 4005 ands r5, r0 + 80eb2: d013 beq.n 80edc + 80eb4: 4c0c ldr r4, [pc, #48] ; (80ee8 ) + 80eb6: f104 0660 add.w r6, r4, #96 ; 0x60 + /* Find triggering source */ + i = 0; + while (status != 0) { + /* Source is configured on the same controller */ + if (gs_interrupt_sources[i].id == ul_id) { + 80eba: 6823 ldr r3, [r4, #0] + 80ebc: 4543 cmp r3, r8 + 80ebe: d108 bne.n 80ed2 + /* Source has PIOs whose statuses have changed */ + if ((status & gs_interrupt_sources[i].mask) != 0) { + 80ec0: 6861 ldr r1, [r4, #4] + 80ec2: 4229 tst r1, r5 + 80ec4: d005 beq.n 80ed2 + gs_interrupt_sources[i].handler(gs_interrupt_sources[i].id, + 80ec6: 68e3 ldr r3, [r4, #12] + 80ec8: 4640 mov r0, r8 + 80eca: 4798 blx r3 + gs_interrupt_sources[i].mask); + status &= ~(gs_interrupt_sources[i].mask); + 80ecc: 6863 ldr r3, [r4, #4] + 80ece: ea25 0503 bic.w r5, r5, r3 + } + } + i++; + if (i >= MAX_INTERRUPT_SOURCES) { + 80ed2: 42b4 cmp r4, r6 + 80ed4: d002 beq.n 80edc + 80ed6: 3410 adds r4, #16 + + /* Check pending events */ + if (status != 0) { + /* Find triggering source */ + i = 0; + while (status != 0) { + 80ed8: 2d00 cmp r5, #0 + 80eda: d1ee bne.n 80eba + 80edc: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 80ee0: 00080d21 .word 0x00080d21 + 80ee4: 00080d25 .word 0x00080d25 + 80ee8: 20074208 .word 0x20074208 + +00080eec : +/** + * \brief Parallel IO Controller A interrupt handler. + * Redefined PIOA interrupt handler for NVIC interrupt table. + */ +void PIOA_Handler(void) +{ + 80eec: b508 push {r3, lr} + pio_handler_process(PIOA, ID_PIOA); + 80eee: 4802 ldr r0, [pc, #8] ; (80ef8 ) + 80ef0: 210b movs r1, #11 + 80ef2: 4b02 ldr r3, [pc, #8] ; (80efc ) + 80ef4: 4798 blx r3 + 80ef6: bd08 pop {r3, pc} + 80ef8: 400e0e00 .word 0x400e0e00 + 80efc: 00080e9d .word 0x00080e9d + +00080f00 : +/** + * \brief Parallel IO Controller B interrupt handler + * Redefined PIOB interrupt handler for NVIC interrupt table. + */ +void PIOB_Handler(void) +{ + 80f00: b508 push {r3, lr} + pio_handler_process(PIOB, ID_PIOB); + 80f02: 4802 ldr r0, [pc, #8] ; (80f0c ) + 80f04: 210c movs r1, #12 + 80f06: 4b02 ldr r3, [pc, #8] ; (80f10 ) + 80f08: 4798 blx r3 + 80f0a: bd08 pop {r3, pc} + 80f0c: 400e1000 .word 0x400e1000 + 80f10: 00080e9d .word 0x00080e9d + +00080f14 : +/** + * \brief Parallel IO Controller C interrupt handler. + * Redefined PIOC interrupt handler for NVIC interrupt table. + */ +void PIOC_Handler(void) +{ + 80f14: b508 push {r3, lr} + pio_handler_process(PIOC, ID_PIOC); + 80f16: 4802 ldr r0, [pc, #8] ; (80f20 ) + 80f18: 210d movs r1, #13 + 80f1a: 4b02 ldr r3, [pc, #8] ; (80f24 ) + 80f1c: 4798 blx r3 + 80f1e: bd08 pop {r3, pc} + 80f20: 400e1200 .word 0x400e1200 + 80f24: 00080e9d .word 0x00080e9d + +00080f28 : +/** + * \brief Parallel IO Controller D interrupt handler. + * Redefined PIOD interrupt handler for NVIC interrupt table. + */ +void PIOD_Handler(void) +{ + 80f28: b508 push {r3, lr} + pio_handler_process(PIOD, ID_PIOD); + 80f2a: 4802 ldr r0, [pc, #8] ; (80f34 ) + 80f2c: 210e movs r1, #14 + 80f2e: 4b02 ldr r3, [pc, #8] ; (80f38 ) + 80f30: 4798 blx r3 + 80f32: bd08 pop {r3, pc} + 80f34: 400e1400 .word 0x400e1400 + 80f38: 00080e9d .word 0x00080e9d + +00080f3c : + */ +uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; + 80f3c: 4a18 ldr r2, [pc, #96] ; (80fa0 ) + 80f3e: 6b13 ldr r3, [r2, #48] ; 0x30 + 80f40: f023 0370 bic.w r3, r3, #112 ; 0x70 + 80f44: 4318 orrs r0, r3 + 80f46: 6310 str r0, [r2, #48] ; 0x30 + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + 80f48: 6e93 ldr r3, [r2, #104] ; 0x68 + 80f4a: f013 0f08 tst.w r3, #8 + 80f4e: d003 beq.n 80f58 + 80f50: e009 b.n 80f66 + --ul_timeout) { + if (ul_timeout == 0) { + 80f52: 3b01 subs r3, #1 + 80f54: d103 bne.n 80f5e + 80f56: e01e b.n 80f96 +uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + 80f58: f44f 6300 mov.w r3, #2048 ; 0x800 + 80f5c: 4910 ldr r1, [pc, #64] ; (80fa0 ) + 80f5e: 6e8a ldr r2, [r1, #104] ; 0x68 + 80f60: f012 0f08 tst.w r2, #8 + 80f64: d0f5 beq.n 80f52 + if (ul_timeout == 0) { + return 1; + } + } + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | + 80f66: 4a0e ldr r2, [pc, #56] ; (80fa0 ) + 80f68: 6b13 ldr r3, [r2, #48] ; 0x30 + 80f6a: f023 0303 bic.w r3, r3, #3 + 80f6e: f043 0302 orr.w r3, r3, #2 + 80f72: 6313 str r3, [r2, #48] ; 0x30 + PMC_MCKR_CSS_PLLA_CLK; + + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + 80f74: 6e90 ldr r0, [r2, #104] ; 0x68 + 80f76: f010 0008 ands.w r0, r0, #8 + 80f7a: d004 beq.n 80f86 + if (ul_timeout == 0) { + return 1; + } + } + + return 0; + 80f7c: 2000 movs r0, #0 + 80f7e: 4770 bx lr + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | + PMC_MCKR_CSS_PLLA_CLK; + + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + 80f80: 3b01 subs r3, #1 + 80f82: d103 bne.n 80f8c + 80f84: e009 b.n 80f9a + } + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | + PMC_MCKR_CSS_PLLA_CLK; + + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + 80f86: f44f 6300 mov.w r3, #2048 ; 0x800 + 80f8a: 4905 ldr r1, [pc, #20] ; (80fa0 ) + 80f8c: 6e8a ldr r2, [r1, #104] ; 0x68 + 80f8e: f012 0f08 tst.w r2, #8 + 80f92: d0f5 beq.n 80f80 + 80f94: 4770 bx lr + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + 80f96: 2001 movs r0, #1 + 80f98: 4770 bx lr + PMC_MCKR_CSS_PLLA_CLK; + + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + 80f9a: 2001 movs r0, #1 + } + } + + return 0; +} + 80f9c: 4770 bx lr + 80f9e: bf00 nop + 80fa0: 400e0600 .word 0x400e0600 + +00080fa4 : + */ +void pmc_switch_mainck_to_xtal(uint32_t ul_bypass, + uint32_t ul_xtal_startup_time) +{ + /* Enable Main Xtal oscillator */ + if (ul_bypass) { + 80fa4: b138 cbz r0, 80fb6 + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) | + 80fa6: 4911 ldr r1, [pc, #68] ; (80fec ) + 80fa8: 6a0b ldr r3, [r1, #32] + CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY | + 80faa: 4a11 ldr r2, [pc, #68] ; (80ff0 ) + 80fac: 401a ands r2, r3 + 80fae: 4b11 ldr r3, [pc, #68] ; (80ff4 ) + 80fb0: 4313 orrs r3, r2 +void pmc_switch_mainck_to_xtal(uint32_t ul_bypass, + uint32_t ul_xtal_startup_time) +{ + /* Enable Main Xtal oscillator */ + if (ul_bypass) { + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) | + 80fb2: 620b str r3, [r1, #32] + 80fb4: 4770 bx lr + CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY | + CKGR_MOR_MOSCSEL; + } else { + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) | + 80fb6: 4a0d ldr r2, [pc, #52] ; (80fec ) + 80fb8: 6a13 ldr r3, [r2, #32] + CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN | + 80fba: f423 135c bic.w r3, r3, #3604480 ; 0x370000 + 80fbe: f023 0303 bic.w r3, r3, #3 + 80fc2: f443 135c orr.w r3, r3, #3604480 ; 0x370000 + 80fc6: f043 0301 orr.w r3, r3, #1 + CKGR_MOR_MOSCXTST(ul_xtal_startup_time); + 80fca: 0209 lsls r1, r1, #8 + 80fcc: b289 uxth r1, r1 + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) | + CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY | + CKGR_MOR_MOSCSEL; + } else { + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) | + CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN | + 80fce: 430b orrs r3, r1 + if (ul_bypass) { + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) | + CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY | + CKGR_MOR_MOSCSEL; + } else { + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) | + 80fd0: 6213 str r3, [r2, #32] + CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN | + CKGR_MOR_MOSCXTST(ul_xtal_startup_time); + /* Wait the Xtal to stabilize */ + while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)); + 80fd2: 6e93 ldr r3, [r2, #104] ; 0x68 + 80fd4: f013 0f01 tst.w r3, #1 + 80fd8: d0fb beq.n 80fd2 + + PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCSEL; + 80fda: 4a04 ldr r2, [pc, #16] ; (80fec ) + 80fdc: 6a13 ldr r3, [r2, #32] + 80fde: f043 739b orr.w r3, r3, #20316160 ; 0x1360000 + 80fe2: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 80fe6: 6213 str r3, [r2, #32] + 80fe8: 4770 bx lr + 80fea: bf00 nop + 80fec: 400e0600 .word 0x400e0600 + 80ff0: fec8fffc .word 0xfec8fffc + 80ff4: 01370002 .word 0x01370002 + +00080ff8 : + * \retval 1 Xtal is ready. + * \retval 0 Xtal is not ready. + */ +uint32_t pmc_osc_is_ready_mainck(void) +{ + return PMC->PMC_SR & PMC_SR_MOSCSELS; + 80ff8: 4b02 ldr r3, [pc, #8] ; (81004 ) + 80ffa: 6e98 ldr r0, [r3, #104] ; 0x68 +} + 80ffc: f400 3080 and.w r0, r0, #65536 ; 0x10000 + 81000: 4770 bx lr + 81002: bf00 nop + 81004: 400e0600 .word 0x400e0600 + +00081008 : +void pmc_disable_pllack(void) +{ +#if (SAM4C || SAM4CM || SAM4CP || SAMG) + PMC->CKGR_PLLAR = CKGR_PLLAR_MULA(0); +#else + PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0); + 81008: f04f 5200 mov.w r2, #536870912 ; 0x20000000 + 8100c: 4b01 ldr r3, [pc, #4] ; (81014 ) + 8100e: 629a str r2, [r3, #40] ; 0x28 + 81010: 4770 bx lr + 81012: bf00 nop + 81014: 400e0600 .word 0x400e0600 + +00081018 : + * \retval 0 Not locked. + * \retval 1 Locked. + */ +uint32_t pmc_is_locked_pllack(void) +{ + return (PMC->PMC_SR & PMC_SR_LOCKA); + 81018: 4b02 ldr r3, [pc, #8] ; (81024 ) + 8101a: 6e98 ldr r0, [r3, #104] ; 0x68 +} + 8101c: f000 0002 and.w r0, r0, #2 + 81020: 4770 bx lr + 81022: bf00 nop + 81024: 400e0600 .word 0x400e0600 + +00081028 : + * \retval 0 Success. + * \retval 1 Invalid parameter. + */ +uint32_t pmc_enable_periph_clk(uint32_t ul_id) +{ + if (ul_id > MAX_PERIPH_ID) { + 81028: 282c cmp r0, #44 ; 0x2c + 8102a: d81e bhi.n 8106a + return 1; + } + + if (ul_id < 32) { + 8102c: 281f cmp r0, #31 + 8102e: d80c bhi.n 8104a + if ((PMC->PMC_PCSR0 & (1u << ul_id)) != (1u << ul_id)) { + 81030: 4b11 ldr r3, [pc, #68] ; (81078 ) + 81032: 699a ldr r2, [r3, #24] + 81034: 2301 movs r3, #1 + 81036: 4083 lsls r3, r0 + 81038: 401a ands r2, r3 + 8103a: 4293 cmp r3, r2 + 8103c: d017 beq.n 8106e + PMC->PMC_PCER0 = 1 << ul_id; + 8103e: 2301 movs r3, #1 + 81040: 4083 lsls r3, r0 + 81042: 4a0d ldr r2, [pc, #52] ; (81078 ) + 81044: 6113 str r3, [r2, #16] + PMC->PMC_PCER1 = 1 << ul_id; + } +#endif + } + + return 0; + 81046: 2000 movs r0, #0 + 81048: 4770 bx lr + PMC->PMC_PCER0 = 1 << ul_id; + } +#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) + } else { + ul_id -= 32; + if ((PMC->PMC_PCSR1 & (1u << ul_id)) != (1u << ul_id)) { + 8104a: 4b0b ldr r3, [pc, #44] ; (81078 ) + 8104c: f8d3 2108 ldr.w r2, [r3, #264] ; 0x108 + if ((PMC->PMC_PCSR0 & (1u << ul_id)) != (1u << ul_id)) { + PMC->PMC_PCER0 = 1 << ul_id; + } +#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) + } else { + ul_id -= 32; + 81050: 3820 subs r0, #32 + if ((PMC->PMC_PCSR1 & (1u << ul_id)) != (1u << ul_id)) { + 81052: 2301 movs r3, #1 + 81054: 4083 lsls r3, r0 + 81056: 401a ands r2, r3 + 81058: 4293 cmp r3, r2 + 8105a: d00a beq.n 81072 + PMC->PMC_PCER1 = 1 << ul_id; + 8105c: 2301 movs r3, #1 + 8105e: 4083 lsls r3, r0 + 81060: 4a05 ldr r2, [pc, #20] ; (81078 ) + 81062: f8c2 3100 str.w r3, [r2, #256] ; 0x100 + } +#endif + } + + return 0; + 81066: 2000 movs r0, #0 + 81068: 4770 bx lr + * \retval 1 Invalid parameter. + */ +uint32_t pmc_enable_periph_clk(uint32_t ul_id) +{ + if (ul_id > MAX_PERIPH_ID) { + return 1; + 8106a: 2001 movs r0, #1 + 8106c: 4770 bx lr + PMC->PMC_PCER1 = 1 << ul_id; + } +#endif + } + + return 0; + 8106e: 2000 movs r0, #0 + 81070: 4770 bx lr + 81072: 2000 movs r0, #0 +} + 81074: 4770 bx lr + 81076: bf00 nop + 81078: 400e0600 .word 0x400e0600 + +0008107c : + const uint32_t ul_length) +{ + /* Validate the parameters. */ + Assert(p_rstc); + + uint32_t mode = p_rstc->RSTC_MR; + 8107c: 6883 ldr r3, [r0, #8] + + mode &= ~(RSTC_MR_ERSTL_Msk | RSTC_MR_KEY_Msk); + 8107e: f023 437f bic.w r3, r3, #4278190080 ; 0xff000000 + 81082: f423 6370 bic.w r3, r3, #3840 ; 0xf00 + 81086: f043 4325 orr.w r3, r3, #2768240640 ; 0xa5000000 + mode |= (RSTC_MR_ERSTL(ul_length) | RSTC_KEY); + 8108a: 0209 lsls r1, r1, #8 + 8108c: f401 6170 and.w r1, r1, #3840 ; 0xf00 + 81090: 430b orrs r3, r1 + + p_rstc->RSTC_MR = mode; + 81092: 6083 str r3, [r0, #8] + 81094: 4770 bx lr + 81096: bf00 nop + +00081098 : + * \param[out] p_rstc Module hardware register base address pointer + */ +void rstc_reset_extern( + Rstc *p_rstc) +{ + p_rstc->RSTC_CR = RSTC_KEY | RSTC_CR_EXTRST; + 81098: 4b01 ldr r3, [pc, #4] ; (810a0 ) + 8109a: 6003 str r3, [r0, #0] + 8109c: 4770 bx lr + 8109e: bf00 nop + 810a0: a5000008 .word 0xa5000008 + +000810a4 : + * \return RSTC status. + */ +uint32_t rstc_get_status( + Rstc *p_rstc) +{ + return p_rstc->RSTC_SR; + 810a4: 6840 ldr r0, [r0, #4] +} + 810a6: 4770 bx lr + +000810a8 : + * + * \retval 0 Success. + * \retval 1 Bad baud rate generator value. + */ +uint32_t uart_init(Uart *p_uart, const sam_uart_opt_t *p_uart_opt) +{ + 810a8: b410 push {r4} + uint32_t cd = 0; + + /* Reset and disable receiver & transmitter */ + p_uart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX + 810aa: 23ac movs r3, #172 ; 0xac + 810ac: 6003 str r3, [r0, #0] + | UART_CR_RXDIS | UART_CR_TXDIS; + + /* Check and configure baudrate */ + /* Asynchronous, no oversampling */ + cd = (p_uart_opt->ul_mck / p_uart_opt->ul_baudrate) / UART_MCK_DIV; + 810ae: 680b ldr r3, [r1, #0] + 810b0: 684a ldr r2, [r1, #4] + 810b2: fbb3 f3f2 udiv r3, r3, r2 + 810b6: 091b lsrs r3, r3, #4 + if (cd < UART_MCK_DIV_MIN_FACTOR || cd > UART_MCK_DIV_MAX_FACTOR) + 810b8: 1e5c subs r4, r3, #1 + 810ba: f64f 72fe movw r2, #65534 ; 0xfffe + 810be: 4294 cmp r4, r2 + 810c0: d80a bhi.n 810d8 + return 1; + + p_uart->UART_BRGR = cd; + 810c2: 6203 str r3, [r0, #32] + /* Configure mode */ + p_uart->UART_MR = p_uart_opt->ul_mode; + 810c4: 688b ldr r3, [r1, #8] + 810c6: 6043 str r3, [r0, #4] + +#if (!SAMV71 && !SAMV70 && !SAME70 && !SAMS70) + /* Disable PDC channel */ + p_uart->UART_PTCR = UART_PTCR_RXTDIS | UART_PTCR_TXTDIS; + 810c8: f240 2302 movw r3, #514 ; 0x202 + 810cc: f8c0 3120 str.w r3, [r0, #288] ; 0x120 +#endif + + /* Enable receiver and transmitter */ + p_uart->UART_CR = UART_CR_RXEN | UART_CR_TXEN; + 810d0: 2350 movs r3, #80 ; 0x50 + 810d2: 6003 str r3, [r0, #0] + + return 0; + 810d4: 2000 movs r0, #0 + 810d6: e000 b.n 810da + + /* Check and configure baudrate */ + /* Asynchronous, no oversampling */ + cd = (p_uart_opt->ul_mck / p_uart_opt->ul_baudrate) / UART_MCK_DIV; + if (cd < UART_MCK_DIV_MIN_FACTOR || cd > UART_MCK_DIV_MAX_FACTOR) + return 1; + 810d8: 2001 movs r0, #1 + + /* Enable receiver and transmitter */ + p_uart->UART_CR = UART_CR_RXEN | UART_CR_TXEN; + + return 0; +} + 810da: f85d 4b04 ldr.w r4, [sp], #4 + 810de: 4770 bx lr + +000810e0 : + * \retval 1 I/O Failure, UART is not ready. + */ +uint32_t uart_write(Uart *p_uart, const uint8_t uc_data) +{ + /* Check if the transmitter is ready */ + if (!(p_uart->UART_SR & UART_SR_TXRDY)) + 810e0: 6943 ldr r3, [r0, #20] + 810e2: f013 0f02 tst.w r3, #2 + return 1; + + /* Send character */ + p_uart->UART_THR = uc_data; + 810e6: bf1a itte ne + 810e8: 61c1 strne r1, [r0, #28] + return 0; + 810ea: 2000 movne r0, #0 + */ +uint32_t uart_write(Uart *p_uart, const uint8_t uc_data) +{ + /* Check if the transmitter is ready */ + if (!(p_uart->UART_SR & UART_SR_TXRDY)) + return 1; + 810ec: 2001 moveq r0, #1 + + /* Send character */ + p_uart->UART_THR = uc_data; + return 0; +} + 810ee: 4770 bx lr + +000810f0 : + * \retval 1 I/O Failure, UART is not ready. + */ +uint32_t uart_read(Uart *p_uart, uint8_t *puc_data) +{ + /* Check if the receiver is ready */ + if ((p_uart->UART_SR & UART_SR_RXRDY) == 0) + 810f0: 6943 ldr r3, [r0, #20] + 810f2: f013 0f01 tst.w r3, #1 + return 1; + + /* Read character */ + *puc_data = (uint8_t) p_uart->UART_RHR; + 810f6: bf1d ittte ne + 810f8: 6983 ldrne r3, [r0, #24] + 810fa: 700b strbne r3, [r1, #0] + return 0; + 810fc: 2000 movne r0, #0 + */ +uint32_t uart_read(Uart *p_uart, uint8_t *puc_data) +{ + /* Check if the receiver is ready */ + if ((p_uart->UART_SR & UART_SR_RXRDY) == 0) + return 1; + 810fe: 2001 moveq r0, #1 + + /* Read character */ + *puc_data = (uint8_t) p_uart->UART_RHR; + return 0; +} + 81100: 4770 bx lr + 81102: bf00 nop + +00081104 : + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_write(Usart *p_usart, uint32_t c) +{ + if (!(p_usart->US_CSR & US_CSR_TXRDY)) { + 81104: 6943 ldr r3, [r0, #20] + 81106: f013 0f02 tst.w r3, #2 + return 1; + } + + p_usart->US_THR = US_THR_TXCHR(c); + 8110a: bf1d ittte ne + 8110c: f3c1 0108 ubfxne r1, r1, #0, #9 + 81110: 61c1 strne r1, [r0, #28] + return 0; + 81112: 2000 movne r0, #0 + * \retval 1 on failure. + */ +uint32_t usart_write(Usart *p_usart, uint32_t c) +{ + if (!(p_usart->US_CSR & US_CSR_TXRDY)) { + return 1; + 81114: 2001 moveq r0, #1 + } + + p_usart->US_THR = US_THR_TXCHR(c); + return 0; +} + 81116: 4770 bx lr + +00081118 : + * \retval 0 on success. + * \retval 1 if no data is available or errors. + */ +uint32_t usart_read(Usart *p_usart, uint32_t *c) +{ + if (!(p_usart->US_CSR & US_CSR_RXRDY)) { + 81118: 6943 ldr r3, [r0, #20] + 8111a: f013 0f01 tst.w r3, #1 + 8111e: d005 beq.n 8112c + return 1; + } + + /* Read character */ + *c = p_usart->US_RHR & US_RHR_RXCHR_Msk; + 81120: 6983 ldr r3, [r0, #24] + 81122: f3c3 0308 ubfx r3, r3, #0, #9 + 81126: 600b str r3, [r1, #0] + + return 0; + 81128: 2000 movs r0, #0 + 8112a: 4770 bx lr + * \retval 1 if no data is available or errors. + */ +uint32_t usart_read(Usart *p_usart, uint32_t *c) +{ + if (!(p_usart->US_CSR & US_CSR_RXRDY)) { + return 1; + 8112c: 2001 movs r0, #1 + + /* Read character */ + *c = p_usart->US_RHR & US_RHR_RXCHR_Msk; + + return 0; +} + 8112e: 4770 bx lr + +00081130 : + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } + 81130: e7fe b.n 81130 + 81132: bf00 nop + +00081134 : +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + 81134: b508 push {r3, lr} + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + 81136: 4b1f ldr r3, [pc, #124] ; (811b4 ) + 81138: 4a1f ldr r2, [pc, #124] ; (811b8 ) + 8113a: 429a cmp r2, r3 + 8113c: d003 beq.n 81146 + for (; pDest < &_erelocate;) { + 8113e: 4b1f ldr r3, [pc, #124] ; (811bc ) + 81140: 4a1c ldr r2, [pc, #112] ; (811b4 ) + 81142: 429a cmp r2, r3 + 81144: d304 bcc.n 81150 + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + 81146: 4b1e ldr r3, [pc, #120] ; (811c0 ) + 81148: 4a1e ldr r2, [pc, #120] ; (811c4 ) + 8114a: 429a cmp r2, r3 + 8114c: d310 bcc.n 81170 + 8114e: e01b b.n 81188 + 81150: 4918 ldr r1, [pc, #96] ; (811b4 ) + 81152: 1d0a adds r2, r1, #4 + 81154: 4b1c ldr r3, [pc, #112] ; (811c8 ) + 81156: 1a9b subs r3, r3, r2 + 81158: f023 0303 bic.w r3, r3, #3 + 8115c: 3304 adds r3, #4 + 8115e: 4a16 ldr r2, [pc, #88] ; (811b8 ) + 81160: 4413 add r3, r2 + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + 81162: f852 0b04 ldr.w r0, [r2], #4 + 81166: f841 0b04 str.w r0, [r1], #4 + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + 8116a: 429a cmp r2, r3 + 8116c: d1f9 bne.n 81162 + 8116e: e7ea b.n 81146 + 81170: 4b16 ldr r3, [pc, #88] ; (811cc ) + 81172: 4a17 ldr r2, [pc, #92] ; (811d0 ) + 81174: 1ad2 subs r2, r2, r3 + 81176: f022 0203 bic.w r2, r2, #3 + 8117a: 441a add r2, r3 + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + 8117c: 3b04 subs r3, #4 + *pDest++ = 0; + 8117e: 2100 movs r1, #0 + 81180: f843 1b04 str.w r1, [r3], #4 + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + 81184: 4293 cmp r3, r2 + 81186: d1fb bne.n 81180 + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + 81188: 4b12 ldr r3, [pc, #72] ; (811d4 ) + 8118a: f023 4260 bic.w r2, r3, #3758096384 ; 0xe0000000 + 8118e: f022 027f bic.w r2, r2, #127 ; 0x7f + 81192: 4911 ldr r1, [pc, #68] ; (811d8 ) + 81194: 608a str r2, [r1, #8] + + if (((uint32_t) pSrc >= IRAM0_ADDR) && ((uint32_t) pSrc < NFC_RAM_ADDR)) { + 81196: f103 4360 add.w r3, r3, #3758096384 ; 0xe0000000 + 8119a: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 + 8119e: d203 bcs.n 811a8 + SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos; + 811a0: 688b ldr r3, [r1, #8] + 811a2: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000 + 811a6: 608b str r3, [r1, #8] + } + + /* Initialize the C library */ + __libc_init_array(); + 811a8: 4b0c ldr r3, [pc, #48] ; (811dc ) + 811aa: 4798 blx r3 + + /* Branch to main function */ + main(); + 811ac: 4b0c ldr r3, [pc, #48] ; (811e0 ) + 811ae: 4798 blx r3 + + /* Infinite loop */ + while (1); + 811b0: e7fe b.n 811b0 + 811b2: bf00 nop + 811b4: 20070000 .word 0x20070000 + 811b8: 00084d28 .word 0x00084d28 + 811bc: 20070994 .word 0x20070994 + 811c0: 200748ec .word 0x200748ec + 811c4: 20070998 .word 0x20070998 + 811c8: 20070997 .word 0x20070997 + 811cc: 2007099c .word 0x2007099c + 811d0: 200748ef .word 0x200748ef + 811d4: 00080000 .word 0x00080000 + 811d8: e000ed00 .word 0xe000ed00 + 811dc: 00081a19 .word 0x00081a19 + 811e0: 000814a9 .word 0x000814a9 + +000811e4 : +} + +void SystemCoreClockUpdate(void) +{ + /* Determine clock frequency according to clock register values */ + switch (PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) { + 811e4: 4b3e ldr r3, [pc, #248] ; (812e0 ) + 811e6: 6b1b ldr r3, [r3, #48] ; 0x30 + 811e8: f003 0303 and.w r3, r3, #3 + 811ec: 2b03 cmp r3, #3 + 811ee: d85f bhi.n 812b0 + 811f0: e8df f003 tbb [pc, r3] + 811f4: 2b2b0e02 .word 0x2b2b0e02 + case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */ + if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) { + 811f8: 4b3a ldr r3, [pc, #232] ; (812e4 ) + 811fa: 695b ldr r3, [r3, #20] + 811fc: f013 0f80 tst.w r3, #128 ; 0x80 + SystemCoreClock = CHIP_FREQ_XTAL_32K; + 81200: bf14 ite ne + 81202: f44f 4200 movne.w r2, #32768 ; 0x8000 + } else { + SystemCoreClock = CHIP_FREQ_SLCK_RC; + 81206: f44f 42fa moveq.w r2, #32000 ; 0x7d00 + 8120a: 4b37 ldr r3, [pc, #220] ; (812e8 ) + 8120c: 601a str r2, [r3, #0] + 8120e: e04f b.n 812b0 + } + break; + case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */ + if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) { + 81210: 4b33 ldr r3, [pc, #204] ; (812e0 ) + 81212: 6a1b ldr r3, [r3, #32] + 81214: f013 7f80 tst.w r3, #16777216 ; 0x1000000 + 81218: d003 beq.n 81222 + SystemCoreClock = CHIP_FREQ_XTAL_12M; + 8121a: 4a34 ldr r2, [pc, #208] ; (812ec ) + 8121c: 4b32 ldr r3, [pc, #200] ; (812e8 ) + 8121e: 601a str r2, [r3, #0] + 81220: e046 b.n 812b0 + } else { + SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; + 81222: 4a33 ldr r2, [pc, #204] ; (812f0 ) + 81224: 4b30 ldr r3, [pc, #192] ; (812e8 ) + 81226: 601a str r2, [r3, #0] + + switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) { + 81228: 4b2d ldr r3, [pc, #180] ; (812e0 ) + 8122a: 6a1b ldr r3, [r3, #32] + 8122c: f003 0370 and.w r3, r3, #112 ; 0x70 + 81230: 2b10 cmp r3, #16 + 81232: d002 beq.n 8123a + 81234: 2b20 cmp r3, #32 + 81236: d004 beq.n 81242 + 81238: e03a b.n 812b0 + case CKGR_MOR_MOSCRCF_4_MHz: + break; + case CKGR_MOR_MOSCRCF_8_MHz: + SystemCoreClock *= 2U; + 8123a: 4a2e ldr r2, [pc, #184] ; (812f4 ) + 8123c: 4b2a ldr r3, [pc, #168] ; (812e8 ) + 8123e: 601a str r2, [r3, #0] + break; + 81240: e036 b.n 812b0 + case CKGR_MOR_MOSCRCF_12_MHz: + SystemCoreClock *= 3U; + 81242: 4a2a ldr r2, [pc, #168] ; (812ec ) + 81244: 4b28 ldr r3, [pc, #160] ; (812e8 ) + 81246: 601a str r2, [r3, #0] + break; + 81248: e032 b.n 812b0 + } + } + break; + case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */ + case PMC_MCKR_CSS_UPLL_CLK: /* UPLL clock */ + if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) { + 8124a: 4b25 ldr r3, [pc, #148] ; (812e0 ) + 8124c: 6a1b ldr r3, [r3, #32] + 8124e: f013 7f80 tst.w r3, #16777216 ; 0x1000000 + 81252: d003 beq.n 8125c + SystemCoreClock = CHIP_FREQ_XTAL_12M; + 81254: 4a25 ldr r2, [pc, #148] ; (812ec ) + 81256: 4b24 ldr r3, [pc, #144] ; (812e8 ) + 81258: 601a str r2, [r3, #0] + 8125a: e012 b.n 81282 + } else { + SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; + 8125c: 4a24 ldr r2, [pc, #144] ; (812f0 ) + 8125e: 4b22 ldr r3, [pc, #136] ; (812e8 ) + 81260: 601a str r2, [r3, #0] + + switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) { + 81262: 4b1f ldr r3, [pc, #124] ; (812e0 ) + 81264: 6a1b ldr r3, [r3, #32] + 81266: f003 0370 and.w r3, r3, #112 ; 0x70 + 8126a: 2b10 cmp r3, #16 + 8126c: d002 beq.n 81274 + 8126e: 2b20 cmp r3, #32 + 81270: d004 beq.n 8127c + 81272: e006 b.n 81282 + case CKGR_MOR_MOSCRCF_4_MHz: + break; + case CKGR_MOR_MOSCRCF_8_MHz: + SystemCoreClock *= 2U; + 81274: 4a1f ldr r2, [pc, #124] ; (812f4 ) + 81276: 4b1c ldr r3, [pc, #112] ; (812e8 ) + 81278: 601a str r2, [r3, #0] + break; + 8127a: e002 b.n 81282 + case CKGR_MOR_MOSCRCF_12_MHz: + SystemCoreClock *= 3U; + 8127c: 4a1b ldr r2, [pc, #108] ; (812ec ) + 8127e: 4b1a ldr r3, [pc, #104] ; (812e8 ) + 81280: 601a str r2, [r3, #0] + break; + default: + break; + } + } + if ((PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK) { + 81282: 4b17 ldr r3, [pc, #92] ; (812e0 ) + 81284: 6b1b ldr r3, [r3, #48] ; 0x30 + 81286: f003 0303 and.w r3, r3, #3 + 8128a: 2b02 cmp r3, #2 + 8128c: d10d bne.n 812aa + SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >> + 8128e: 4a14 ldr r2, [pc, #80] ; (812e0 ) + 81290: 6a93 ldr r3, [r2, #40] ; 0x28 + CKGR_PLLAR_MULA_Pos) + 1U); + SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >> + 81292: 6a92 ldr r2, [r2, #40] ; 0x28 + 81294: 4814 ldr r0, [pc, #80] ; (812e8 ) + default: + break; + } + } + if ((PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK) { + SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >> + 81296: f3c3 410a ubfx r1, r3, #16, #11 + 8129a: 6803 ldr r3, [r0, #0] + 8129c: fb01 3303 mla r3, r1, r3, r3 + CKGR_PLLAR_MULA_Pos) + 1U); + SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >> + 812a0: b2d2 uxtb r2, r2 + 812a2: fbb3 f3f2 udiv r3, r3, r2 + 812a6: 6003 str r3, [r0, #0] + 812a8: e002 b.n 812b0 + CKGR_PLLAR_DIVA_Pos)); + } else { + SystemCoreClock = SYS_UTMIPLL / 2U; + 812aa: 4a13 ldr r2, [pc, #76] ; (812f8 ) + 812ac: 4b0e ldr r3, [pc, #56] ; (812e8 ) + 812ae: 601a str r2, [r3, #0] + } + break; + } + + if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) { + 812b0: 4b0b ldr r3, [pc, #44] ; (812e0 ) + 812b2: 6b1b ldr r3, [r3, #48] ; 0x30 + 812b4: f003 0370 and.w r3, r3, #112 ; 0x70 + 812b8: 2b70 cmp r3, #112 ; 0x70 + 812ba: d107 bne.n 812cc + SystemCoreClock /= 3U; + 812bc: 4a0a ldr r2, [pc, #40] ; (812e8 ) + 812be: 6813 ldr r3, [r2, #0] + 812c0: 490e ldr r1, [pc, #56] ; (812fc ) + 812c2: fba1 1303 umull r1, r3, r1, r3 + 812c6: 085b lsrs r3, r3, #1 + 812c8: 6013 str r3, [r2, #0] + 812ca: 4770 bx lr + } else { + SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> + 812cc: 4b04 ldr r3, [pc, #16] ; (812e0 ) + 812ce: 6b1a ldr r2, [r3, #48] ; 0x30 + 812d0: 4905 ldr r1, [pc, #20] ; (812e8 ) + 812d2: f3c2 1202 ubfx r2, r2, #4, #3 + 812d6: 680b ldr r3, [r1, #0] + 812d8: 40d3 lsrs r3, r2 + 812da: 600b str r3, [r1, #0] + 812dc: 4770 bx lr + 812de: bf00 nop + 812e0: 400e0600 .word 0x400e0600 + 812e4: 400e1a10 .word 0x400e1a10 + 812e8: 2007012c .word 0x2007012c + 812ec: 00b71b00 .word 0x00b71b00 + 812f0: 003d0900 .word 0x003d0900 + 812f4: 007a1200 .word 0x007a1200 + 812f8: 0e4e1c00 .word 0x0e4e1c00 + 812fc: aaaaaaab .word 0xaaaaaaab + +00081300 <_sbrk>: +{ + static unsigned char *heap = NULL; + unsigned char *prev_heap; + int ramend = (int)&__ram_end__; + + if (heap == NULL) { + 81300: 4b09 ldr r3, [pc, #36] ; (81328 <_sbrk+0x28>) + 81302: 681b ldr r3, [r3, #0] + 81304: b913 cbnz r3, 8130c <_sbrk+0xc> + heap = (unsigned char *)&_end; + 81306: 4a09 ldr r2, [pc, #36] ; (8132c <_sbrk+0x2c>) + 81308: 4b07 ldr r3, [pc, #28] ; (81328 <_sbrk+0x28>) + 8130a: 601a str r2, [r3, #0] + } + prev_heap = heap; + 8130c: 4b06 ldr r3, [pc, #24] ; (81328 <_sbrk+0x28>) + 8130e: 681b ldr r3, [r3, #0] + + if (((int)prev_heap + incr) > ramend) { + 81310: 181a adds r2, r3, r0 + 81312: 4907 ldr r1, [pc, #28] ; (81330 <_sbrk+0x30>) + 81314: 4291 cmp r1, r2 + 81316: db04 blt.n 81322 <_sbrk+0x22> + return (caddr_t) -1; + } + + heap += incr; + 81318: 4610 mov r0, r2 + 8131a: 4a03 ldr r2, [pc, #12] ; (81328 <_sbrk+0x28>) + 8131c: 6010 str r0, [r2, #0] + + return (caddr_t) prev_heap; + 8131e: 4618 mov r0, r3 + 81320: 4770 bx lr + heap = (unsigned char *)&_end; + } + prev_heap = heap; + + if (((int)prev_heap + incr) > ramend) { + return (caddr_t) -1; + 81322: f04f 30ff mov.w r0, #4294967295 + } + + heap += incr; + + return (caddr_t) prev_heap; +} + 81326: 4770 bx lr + 81328: 20074278 .word 0x20074278 + 8132c: 200768f0 .word 0x200768f0 + 81330: 20087ffc .word 0x20087ffc + +00081334 <_close>: +} + +extern int _close(int file) +{ + return -1; +} + 81334: f04f 30ff mov.w r0, #4294967295 + 81338: 4770 bx lr + 8133a: bf00 nop + +0008133c <_fstat>: + +extern int _fstat(int file, struct stat *st) +{ + st->st_mode = S_IFCHR; + 8133c: f44f 5300 mov.w r3, #8192 ; 0x2000 + 81340: 604b str r3, [r1, #4] + + return 0; +} + 81342: 2000 movs r0, #0 + 81344: 4770 bx lr + 81346: bf00 nop + +00081348 <_isatty>: + +extern int _isatty(int file) +{ + return 1; +} + 81348: 2001 movs r0, #1 + 8134a: 4770 bx lr + +0008134c <_lseek>: + +extern int _lseek(int file, int ptr, int dir) +{ + return 0; +} + 8134c: 2000 movs r0, #0 + 8134e: 4770 bx lr + +00081350 : + * \param p_usart Base address of the USART instance. + * \param data Data to read + * + */ +static inline void usart_serial_getchar(usart_if p_usart, uint8_t *data) +{ + 81350: b5f0 push {r4, r5, r6, r7, lr} + 81352: b083 sub sp, #12 + 81354: 4604 mov r4, r0 + 81356: 460d mov r5, r1 + uint32_t val = 0; + 81358: 2300 movs r3, #0 + 8135a: 9301 str r3, [sp, #4] + + /* Avoid Cppcheck Warning */ + UNUSED(val); + +#ifdef UART + if (UART == (Uart*)p_usart) { + 8135c: 4b1f ldr r3, [pc, #124] ; (813dc ) + 8135e: 4298 cmp r0, r3 + 81360: d107 bne.n 81372 + while (uart_read((Uart*)p_usart, data)); + 81362: 461f mov r7, r3 + 81364: 4e1e ldr r6, [pc, #120] ; (813e0 ) + 81366: 4638 mov r0, r7 + 81368: 4629 mov r1, r5 + 8136a: 47b0 blx r6 + 8136c: 2800 cmp r0, #0 + 8136e: d1fa bne.n 81366 + 81370: e019 b.n 813a6 + while (usart_read(p_usart, &val)); + *data = (uint8_t)(val & 0xFF); + } +#else +# ifdef USART0 + if (USART0 == p_usart) { + 81372: 4b1c ldr r3, [pc, #112] ; (813e4 ) + 81374: 4298 cmp r0, r3 + 81376: d109 bne.n 8138c + while (usart_read(p_usart, &val)); + 81378: 461f mov r7, r3 + 8137a: 4e1b ldr r6, [pc, #108] ; (813e8 ) + 8137c: 4638 mov r0, r7 + 8137e: a901 add r1, sp, #4 + 81380: 47b0 blx r6 + 81382: 2800 cmp r0, #0 + 81384: d1fa bne.n 8137c + *data = (uint8_t)(val & 0xFF); + 81386: 9b01 ldr r3, [sp, #4] + 81388: 702b strb r3, [r5, #0] + 8138a: e019 b.n 813c0 + } +# endif +# ifdef USART1 + if (USART1 == p_usart) { + 8138c: 4b17 ldr r3, [pc, #92] ; (813ec ) + 8138e: 4298 cmp r0, r3 + 81390: d109 bne.n 813a6 + while (usart_read(p_usart, &val)); + 81392: 461e mov r6, r3 + 81394: 4c14 ldr r4, [pc, #80] ; (813e8 ) + 81396: 4630 mov r0, r6 + 81398: a901 add r1, sp, #4 + 8139a: 47a0 blx r4 + 8139c: 2800 cmp r0, #0 + 8139e: d1fa bne.n 81396 + *data = (uint8_t)(val & 0xFF); + 813a0: 9b01 ldr r3, [sp, #4] + 813a2: 702b strb r3, [r5, #0] + 813a4: e018 b.n 813d8 + } +# endif +# ifdef USART2 + if (USART2 == p_usart) { + 813a6: 4b12 ldr r3, [pc, #72] ; (813f0 ) + 813a8: 429c cmp r4, r3 + 813aa: d109 bne.n 813c0 + while (usart_read(p_usart, &val)); + 813ac: 461e mov r6, r3 + 813ae: 4c0e ldr r4, [pc, #56] ; (813e8 ) + 813b0: 4630 mov r0, r6 + 813b2: a901 add r1, sp, #4 + 813b4: 47a0 blx r4 + 813b6: 2800 cmp r0, #0 + 813b8: d1fa bne.n 813b0 + *data = (uint8_t)(val & 0xFF); + 813ba: 9b01 ldr r3, [sp, #4] + 813bc: 702b strb r3, [r5, #0] + 813be: e00b b.n 813d8 + } +# endif +# ifdef USART3 + if (USART3 == p_usart) { + 813c0: 4b0c ldr r3, [pc, #48] ; (813f4 ) + 813c2: 429c cmp r4, r3 + 813c4: d108 bne.n 813d8 + while (usart_read(p_usart, &val)); + 813c6: 461e mov r6, r3 + 813c8: 4c07 ldr r4, [pc, #28] ; (813e8 ) + 813ca: 4630 mov r0, r6 + 813cc: a901 add r1, sp, #4 + 813ce: 47a0 blx r4 + 813d0: 2800 cmp r0, #0 + 813d2: d1fa bne.n 813ca + *data = (uint8_t)(val & 0xFF); + 813d4: 9b01 ldr r3, [sp, #4] + 813d6: 702b strb r3, [r5, #0] + *data = (uint8_t)(val & 0xFF); + } +# endif +#endif /* ifdef USART */ + +} + 813d8: b003 add sp, #12 + 813da: bdf0 pop {r4, r5, r6, r7, pc} + 813dc: 400e0800 .word 0x400e0800 + 813e0: 000810f1 .word 0x000810f1 + 813e4: 40098000 .word 0x40098000 + 813e8: 00081119 .word 0x00081119 + 813ec: 4009c000 .word 0x4009c000 + 813f0: 400a0000 .word 0x400a0000 + 813f4: 400a4000 .word 0x400a4000 + +000813f8 : + * \retval 1 The character was written. + * \retval 0 The function timed out before the USART transmitter became + * ready to send. + */ +static inline int usart_serial_putchar(usart_if p_usart, const uint8_t c) +{ + 813f8: b570 push {r4, r5, r6, lr} + 813fa: 460c mov r4, r1 +#ifdef UART + if (UART == (Uart*)p_usart) { + 813fc: 4b1e ldr r3, [pc, #120] ; (81478 ) + 813fe: 4298 cmp r0, r3 + 81400: d108 bne.n 81414 + while (uart_write((Uart*)p_usart, c)!=0); + 81402: 461e mov r6, r3 + 81404: 4d1d ldr r5, [pc, #116] ; (8147c ) + 81406: 4630 mov r0, r6 + 81408: 4621 mov r1, r4 + 8140a: 47a8 blx r5 + 8140c: 2800 cmp r0, #0 + 8140e: d1fa bne.n 81406 + return 1; + 81410: 2001 movs r0, #1 + 81412: bd70 pop {r4, r5, r6, pc} + while (usart_write(p_usart, c)!=0); + return 1; + } +#else +# ifdef USART0 + if (USART0 == p_usart) { + 81414: 4b1a ldr r3, [pc, #104] ; (81480 ) + 81416: 4298 cmp r0, r3 + 81418: d108 bne.n 8142c + while (usart_write(p_usart, c)!=0); + 8141a: 461e mov r6, r3 + 8141c: 4d19 ldr r5, [pc, #100] ; (81484 ) + 8141e: 4630 mov r0, r6 + 81420: 4621 mov r1, r4 + 81422: 47a8 blx r5 + 81424: 2800 cmp r0, #0 + 81426: d1fa bne.n 8141e + return 1; + 81428: 2001 movs r0, #1 + 8142a: bd70 pop {r4, r5, r6, pc} + } +# endif +# ifdef USART1 + if (USART1 == p_usart) { + 8142c: 4b16 ldr r3, [pc, #88] ; (81488 ) + 8142e: 4298 cmp r0, r3 + 81430: d108 bne.n 81444 + while (usart_write(p_usart, c)!=0); + 81432: 461e mov r6, r3 + 81434: 4d13 ldr r5, [pc, #76] ; (81484 ) + 81436: 4630 mov r0, r6 + 81438: 4621 mov r1, r4 + 8143a: 47a8 blx r5 + 8143c: 2800 cmp r0, #0 + 8143e: d1fa bne.n 81436 + return 1; + 81440: 2001 movs r0, #1 + 81442: bd70 pop {r4, r5, r6, pc} + } +# endif +# ifdef USART2 + if (USART2 == p_usart) { + 81444: 4b11 ldr r3, [pc, #68] ; (8148c ) + 81446: 4298 cmp r0, r3 + 81448: d108 bne.n 8145c + while (usart_write(p_usart, c)!=0); + 8144a: 461e mov r6, r3 + 8144c: 4d0d ldr r5, [pc, #52] ; (81484 ) + 8144e: 4630 mov r0, r6 + 81450: 4621 mov r1, r4 + 81452: 47a8 blx r5 + 81454: 2800 cmp r0, #0 + 81456: d1fa bne.n 8144e + return 1; + 81458: 2001 movs r0, #1 + 8145a: bd70 pop {r4, r5, r6, pc} + } +# endif +# ifdef USART3 + if (USART3 == p_usart) { + 8145c: 4b0c ldr r3, [pc, #48] ; (81490 ) + 8145e: 4298 cmp r0, r3 + 81460: d108 bne.n 81474 + while (usart_write(p_usart, c)!=0); + 81462: 461e mov r6, r3 + 81464: 4d07 ldr r5, [pc, #28] ; (81484 ) + 81466: 4630 mov r0, r6 + 81468: 4621 mov r1, r4 + 8146a: 47a8 blx r5 + 8146c: 2800 cmp r0, #0 + 8146e: d1fa bne.n 81466 + return 1; + 81470: 2001 movs r0, #1 + 81472: bd70 pop {r4, r5, r6, pc} + return 1; + } +# endif +#endif /* ifdef USART */ + + return 0; + 81474: 2000 movs r0, #0 +} + 81476: bd70 pop {r4, r5, r6, pc} + 81478: 400e0800 .word 0x400e0800 + 8147c: 000810e1 .word 0x000810e1 + 81480: 40098000 .word 0x40098000 + 81484: 00081105 .word 0x00081105 + 81488: 4009c000 .word 0x4009c000 + 8148c: 400a0000 .word 0x400a0000 + 81490: 400a4000 .word 0x400a4000 + +00081494 : + +/** + * \brief EMAC interrupt handler. + */ +void EMAC_Handler(void) +{ + 81494: b508 push {r3, lr} + emac_handler(&gs_emac_dev); + 81496: 4802 ldr r0, [pc, #8] ; (814a0 ) + 81498: 4b02 ldr r3, [pc, #8] ; (814a4 ) + 8149a: 4798 blx r3 + 8149c: bd08 pop {r3, pc} + 8149e: bf00 nop + 814a0: 2007427c .word 0x2007427c + 814a4: 00080b3d .word 0x00080b3d + +000814a8
: + * \brief EMAC example entry point. + * + * \return Unused (ANSI-C compatibility). + */ +int main(void) +{ + 814a8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 814ac: b099 sub sp, #100 ; 0x64 + uint32_t ul_frm_size; + volatile uint32_t ul_delay; + emac_options_t emac_option; + + /* Initialize the SAM system. */ + sysclk_init(); + 814ae: 4b8a ldr r3, [pc, #552] ; (816d8 ) + 814b0: 4798 blx r3 + board_init(); + 814b2: 4b8a ldr r3, [pc, #552] ; (816dc ) + 814b4: 4798 blx r3 + 814b6: 2008 movs r0, #8 + 814b8: 4d89 ldr r5, [pc, #548] ; (816e0 ) + 814ba: 47a8 blx r5 + * \param opt Options needed to set up RS232 communication (see \ref usart_options_t). + * + */ +static inline void stdio_serial_init(volatile void *usart, const usart_serial_options_t *opt) +{ + stdio_base = (void *)usart; + 814bc: 4c89 ldr r4, [pc, #548] ; (816e4 ) + 814be: 4b8a ldr r3, [pc, #552] ; (816e8 ) + 814c0: 601c str r4, [r3, #0] + ptr_put = (int (*)(void volatile*,char))&usart_serial_putchar; + 814c2: 4a8a ldr r2, [pc, #552] ; (816ec ) + 814c4: 4b8a ldr r3, [pc, #552] ; (816f0 ) + 814c6: 601a str r2, [r3, #0] + ptr_get = (void (*)(void volatile*,char*))&usart_serial_getchar; + 814c8: 4a8a ldr r2, [pc, #552] ; (816f4 ) + 814ca: 4b8b ldr r3, [pc, #556] ; (816f8 ) + 814cc: 601a str r2, [r3, #0] +static inline void usart_serial_init(usart_if p_usart, + usart_serial_options_t *opt) +{ +#if ((!SAM4L) && (!SAMG55)) + sam_uart_opt_t uart_settings; + uart_settings.ul_mck = sysclk_get_peripheral_hz(); + 814ce: 4b8b ldr r3, [pc, #556] ; (816fc ) + 814d0: 9311 str r3, [sp, #68] ; 0x44 + uart_settings.ul_baudrate = opt->baudrate; + 814d2: f44f 33e1 mov.w r3, #115200 ; 0x1c200 + 814d6: 9312 str r3, [sp, #72] ; 0x48 + uart_settings.ul_mode = opt->paritytype; + 814d8: f44f 6300 mov.w r3, #2048 ; 0x800 + 814dc: 9313 str r3, [sp, #76] ; 0x4c + 814de: 2008 movs r0, #8 + 814e0: 47a8 blx r5 + +#ifdef UART + if (UART == (Uart*)p_usart) { + sysclk_enable_peripheral_clock(ID_UART); + /* Configure UART */ + uart_init((Uart*)p_usart, &uart_settings); + 814e2: 4620 mov r0, r4 + 814e4: a911 add r1, sp, #68 ; 0x44 + 814e6: 4b86 ldr r3, [pc, #536] ; (81700 ) + 814e8: 4798 blx r3 + fdevopen((int (*)(char, FILE*))(_write),(int (*)(FILE*))(_read)); +# endif +# if UC3 || SAM + // For AVR32 and SAM GCC + // Specify that stdout and stdin should not be buffered. + setbuf(stdout, NULL); + 814ea: 4d86 ldr r5, [pc, #536] ; (81704 ) + 814ec: 682b ldr r3, [r5, #0] + 814ee: 6898 ldr r0, [r3, #8] + 814f0: 2100 movs r1, #0 + 814f2: 4c85 ldr r4, [pc, #532] ; (81708 ) + 814f4: 47a0 blx r4 + setbuf(stdin, NULL); + 814f6: 682b ldr r3, [r5, #0] + 814f8: 6858 ldr r0, [r3, #4] + 814fa: 2100 movs r1, #0 + 814fc: 47a0 blx r4 + + /* Initialize the console UART. */ + configure_console(); + + puts(STRING_HEADER); + 814fe: 4883 ldr r0, [pc, #524] ; (8170c ) + 81500: 4b83 ldr r3, [pc, #524] ; (81710 ) + 81502: 4798 blx r3 + + /* Display MAC & IP settings */ + printf("-- MAC %x:%x:%x:%x:%x:%x\n\r", + 81504: 231c movs r3, #28 + 81506: 9300 str r3, [sp, #0] + 81508: 23a0 movs r3, #160 ; 0xa0 + 8150a: 9301 str r3, [sp, #4] + 8150c: 2502 movs r5, #2 + 8150e: 9502 str r5, [sp, #8] + 81510: 4880 ldr r0, [pc, #512] ; (81714 ) + 81512: 2100 movs r1, #0 + 81514: 2204 movs r2, #4 + 81516: 2325 movs r3, #37 ; 0x25 + 81518: 4c7f ldr r4, [pc, #508] ; (81718 ) + 8151a: 47a0 blx r4 + gs_uc_mac_address[0], gs_uc_mac_address[1], gs_uc_mac_address[2], + gs_uc_mac_address[3], gs_uc_mac_address[4], gs_uc_mac_address[5]); + + printf("-- IP %d.%d.%d.%d\n\r", gs_uc_ip_address[0], gs_uc_ip_address[1], + 8151c: 9500 str r5, [sp, #0] + 8151e: 487f ldr r0, [pc, #508] ; (8171c ) + 81520: 21c0 movs r1, #192 ; 0xc0 + 81522: 22a8 movs r2, #168 ; 0xa8 + 81524: 2300 movs r3, #0 + 81526: 47a0 blx r4 + gs_uc_ip_address[2], gs_uc_ip_address[3]); + + /* Reset PHY */ + rstc_set_external_reset(RSTC, 13); /* (2^(13+1))/32768 */ + 81528: 4c7d ldr r4, [pc, #500] ; (81720 ) + 8152a: 4620 mov r0, r4 + 8152c: 210d movs r1, #13 + 8152e: 4b7d ldr r3, [pc, #500] ; (81724 ) + 81530: 4798 blx r3 + rstc_reset_extern(RSTC); + 81532: 4620 mov r0, r4 + 81534: 4b7c ldr r3, [pc, #496] ; (81728 ) + 81536: 4798 blx r3 + while (rstc_get_status(RSTC) & RSTC_SR_NRSTL) { + 81538: 4625 mov r5, r4 + 8153a: 4c7c ldr r4, [pc, #496] ; (8172c ) + 8153c: 4628 mov r0, r5 + 8153e: 47a0 blx r4 + 81540: f410 3f80 tst.w r0, #65536 ; 0x10000 + 81544: d1fa bne.n 8153c + }; + rstc_set_external_reset(RSTC, 0); /* restore default */ + 81546: 4876 ldr r0, [pc, #472] ; (81720 ) + 81548: 2100 movs r1, #0 + 8154a: 4b76 ldr r3, [pc, #472] ; (81724 ) + 8154c: 4798 blx r3 + + /* Wait for PHY to be ready (CAT811: Max400ms) */ + ul_delay = sysclk_get_cpu_hz() / 1000 / 3 * 400; + 8154e: 4b78 ldr r3, [pc, #480] ; (81730 ) + 81550: 9316 str r3, [sp, #88] ; 0x58 + while (ul_delay--); + 81552: 9b16 ldr r3, [sp, #88] ; 0x58 + 81554: 1e5a subs r2, r3, #1 + 81556: 9216 str r2, [sp, #88] ; 0x58 + 81558: 2b00 cmp r3, #0 + 8155a: d1fa bne.n 81552 + + /* Enable EMAC clock */ + pmc_enable_periph_clk(ID_EMAC); + 8155c: 202a movs r0, #42 ; 0x2a + 8155e: 4b60 ldr r3, [pc, #384] ; (816e0 ) + 81560: 4798 blx r3 + + /* Fill in EMAC options */ + emac_option.uc_copy_all_frame = 0; + 81562: 2400 movs r4, #0 + 81564: f88d 4050 strb.w r4, [sp, #80] ; 0x50 + emac_option.uc_no_boardcast = 0; + 81568: f88d 4051 strb.w r4, [sp, #81] ; 0x51 + + memcpy(emac_option.uc_mac_addr, gs_uc_mac_address, sizeof(gs_uc_mac_address)); + 8156c: 4b71 ldr r3, [pc, #452] ; (81734 ) + 8156e: 6818 ldr r0, [r3, #0] + 81570: f8cd 0052 str.w r0, [sp, #82] ; 0x52 + 81574: 889b ldrh r3, [r3, #4] + 81576: f8ad 3056 strh.w r3, [sp, #86] ; 0x56 + + gs_emac_dev.p_hw = EMAC; + 8157a: 496f ldr r1, [pc, #444] ; (81738 ) + 8157c: 4d6f ldr r5, [pc, #444] ; (8173c ) + 8157e: 600d str r5, [r1, #0] + + /* Init EMAC driver structure */ + emac_dev_init(EMAC, &gs_emac_dev, &emac_option); + 81580: 4628 mov r0, r5 + 81582: aa14 add r2, sp, #80 ; 0x50 + 81584: 4b6e ldr r3, [pc, #440] ; (81740 ) + 81586: 4798 blx r3 + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ + 81588: f44f 6280 mov.w r2, #1024 ; 0x400 + 8158c: 4b6d ldr r3, [pc, #436] ; (81744 ) + 8158e: 605a str r2, [r3, #4] + + /* Enable Interrupt */ + NVIC_EnableIRQ(EMAC_IRQn); + + /* Init MAC PHY driver */ + if (ethernet_phy_init(EMAC, BOARD_EMAC_PHY_ADDR, sysclk_get_cpu_hz()) + 81590: 4628 mov r0, r5 + 81592: 4621 mov r1, r4 + 81594: 4a59 ldr r2, [pc, #356] ; (816fc ) + 81596: 4b6c ldr r3, [pc, #432] ; (81748 ) + 81598: 4798 blx r3 + 8159a: b118 cbz r0, 815a4 + != EMAC_OK) { + puts("PHY Initialize ERROR!\r"); + 8159c: 486b ldr r0, [pc, #428] ; (8174c ) + 8159e: 4b5c ldr r3, [pc, #368] ; (81710 ) + 815a0: 4798 blx r3 + return -1; + 815a2: e205 b.n 819b0 + } + + /* Auto Negotiate, work in RMII mode */ + if (ethernet_phy_auto_negotiate(EMAC, BOARD_EMAC_PHY_ADDR) != EMAC_OK) { + 815a4: 4865 ldr r0, [pc, #404] ; (8173c ) + 815a6: 2100 movs r1, #0 + 815a8: 4b69 ldr r3, [pc, #420] ; (81750 ) + 815aa: 4798 blx r3 + 815ac: b138 cbz r0, 815be + + puts("Auto Negotiate ERROR!\r"); + 815ae: 4869 ldr r0, [pc, #420] ; (81754 ) + 815b0: 4b57 ldr r3, [pc, #348] ; (81710 ) + 815b2: 4798 blx r3 + return -1; + 815b4: e1fc b.n 819b0 + } + + /* Establish ethernet link */ + while (ethernet_phy_set_link(EMAC, BOARD_EMAC_PHY_ADDR, 1) != EMAC_OK) { + puts("Set link ERROR!\r"); + 815b6: 4868 ldr r0, [pc, #416] ; (81758 ) + 815b8: 4b55 ldr r3, [pc, #340] ; (81710 ) + 815ba: 4798 blx r3 + return -1; + 815bc: e1f8 b.n 819b0 + puts("Auto Negotiate ERROR!\r"); + return -1; + } + + /* Establish ethernet link */ + while (ethernet_phy_set_link(EMAC, BOARD_EMAC_PHY_ADDR, 1) != EMAC_OK) { + 815be: 485f ldr r0, [pc, #380] ; (8173c ) + 815c0: 2100 movs r1, #0 + 815c2: 2201 movs r2, #1 + 815c4: 4b65 ldr r3, [pc, #404] ; (8175c ) + 815c6: 4798 blx r3 + 815c8: 2800 cmp r0, #0 + 815ca: d1f4 bne.n 815b6 + puts("Set link ERROR!\r"); + return -1; + } + + puts("Link detected. \r"); + 815cc: 4864 ldr r0, [pc, #400] ; (81760 ) + 815ce: 4b50 ldr r3, [pc, #320] ; (81710 ) + 815d0: 4798 blx r3 + + while (1) { + /* Process packets */ + if (EMAC_OK != emac_dev_read(&gs_emac_dev, (uint8_t *) gs_uc_eth_buffer, + 815d2: f8df 9164 ldr.w r9, [pc, #356] ; 81738 + 815d6: f8df b198 ldr.w fp, [pc, #408] ; 81770 + 815da: f10b 030b add.w r3, fp, #11 + 815de: 930f str r3, [sp, #60] ; 0x3c + 815e0: 4648 mov r0, r9 + 815e2: 4659 mov r1, fp + 815e4: f44f 62c0 mov.w r2, #1536 ; 0x600 + 815e8: ab17 add r3, sp, #92 ; 0x5c + 815ea: 4c5e ldr r4, [pc, #376] ; (81764 ) + 815ec: 47a0 blx r4 + 815ee: 2800 cmp r0, #0 + 815f0: d1f6 bne.n 815e0 + sizeof(gs_uc_eth_buffer), &ul_frm_size)) { + continue; + } + + if (ul_frm_size > 0) { + 815f2: 9c17 ldr r4, [sp, #92] ; 0x5c + 815f4: 2c00 cmp r4, #0 + 815f6: d0f3 beq.n 815e0 + uint16_t us_pkt_format; + + p_ethernet_header_t p_eth = (p_ethernet_header_t) (p_uc_data); + p_ip_header_t p_ip_header = (p_ip_header_t) (p_uc_data + ETH_HEADER_SIZE); + ip_header_t ip_header; + us_pkt_format = SWAP16(p_eth->et_protlen); + 815f8: f8bb 100c ldrh.w r1, [fp, #12] + 815fc: b289 uxth r1, r1 + 815fe: 0a0b lsrs r3, r1, #8 + 81600: ea43 2101 orr.w r1, r3, r1, lsl #8 + 81604: b289 uxth r1, r1 + + switch (us_pkt_format) { + 81606: f5b1 6f00 cmp.w r1, #2048 ; 0x800 + 8160a: f000 80b3 beq.w 81774 + 8160e: f640 0306 movw r3, #2054 ; 0x806 + 81612: 4299 cmp r1, r3 + 81614: f040 81c8 bne.w 819a8 + uint8_t ul_rc = EMAC_OK; + + p_ethernet_header_t p_eth = (p_ethernet_header_t) p_uc_data; + p_arp_header_t p_arp = (p_arp_header_t) (p_uc_data + ETH_HEADER_SIZE); + + if (SWAP16(p_arp->ar_op) == ARP_REQUEST) { + 81618: f8bb 3014 ldrh.w r3, [fp, #20] + 8161c: b29a uxth r2, r3 + 8161e: 0213 lsls r3, r2, #8 + 81620: b29b uxth r3, r3 + 81622: ea43 2312 orr.w r3, r3, r2, lsr #8 + 81626: 2b01 cmp r3, #1 + 81628: d1da bne.n 815e0 + printf("-- IP %d.%d.%d.%d\n\r", + 8162a: 4e3c ldr r6, [pc, #240] ; (8171c ) + 8162c: f89b 1000 ldrb.w r1, [fp] + 81630: f89b 2001 ldrb.w r2, [fp, #1] + 81634: f89b 3002 ldrb.w r3, [fp, #2] + 81638: f89b 0003 ldrb.w r0, [fp, #3] + 8163c: 9000 str r0, [sp, #0] + 8163e: 4630 mov r0, r6 + 81640: 4d35 ldr r5, [pc, #212] ; (81718 ) + 81642: 47a8 blx r5 + p_eth->et_dest[0], p_eth->et_dest[1], + p_eth->et_dest[2], p_eth->et_dest[3]); + + printf("-- IP %d.%d.%d.%d\n\r", + 81644: f89b 1006 ldrb.w r1, [fp, #6] + 81648: f89b 2007 ldrb.w r2, [fp, #7] + 8164c: f89b 3008 ldrb.w r3, [fp, #8] + 81650: f89b 0009 ldrb.w r0, [fp, #9] + 81654: 9000 str r0, [sp, #0] + 81656: 4630 mov r0, r6 + 81658: 47a8 blx r5 + p_eth->et_src[0], p_eth->et_src[1], + p_eth->et_src[2], p_eth->et_src[3]); + + /* ARP reply operation */ + p_arp->ar_op = SWAP16(ARP_REPLY); + 8165a: f44f 7300 mov.w r3, #512 ; 0x200 + 8165e: f8ab 3014 strh.w r3, [fp, #20] + 81662: 465b mov r3, fp + 81664: 4833 ldr r0, [pc, #204] ; (81734 ) + + /* Fill the destination address and source address */ + for (i = 0; i < 6; i++) { + 81666: 2200 movs r2, #0 + /* Swap ethernet destination address and ethernet source address */ + p_eth->et_dest[i] = p_eth->et_src[i]; + 81668: 7999 ldrb r1, [r3, #6] + 8166a: 7019 strb r1, [r3, #0] + p_eth->et_src[i] = gs_uc_mac_address[i]; + 8166c: f810 1b01 ldrb.w r1, [r0], #1 + 81670: 7199 strb r1, [r3, #6] + p_arp->ar_tha[i] = p_arp->ar_sha[i]; + 81672: 7d9d ldrb r5, [r3, #22] + 81674: f883 5020 strb.w r5, [r3, #32] + p_arp->ar_sha[i] = gs_uc_mac_address[i]; + 81678: 7599 strb r1, [r3, #22] + + /* ARP reply operation */ + p_arp->ar_op = SWAP16(ARP_REPLY); + + /* Fill the destination address and source address */ + for (i = 0; i < 6; i++) { + 8167a: 3201 adds r2, #1 + 8167c: 3301 adds r3, #1 + 8167e: 2a06 cmp r2, #6 + 81680: d1f2 bne.n 81668 + p_arp->ar_tha[i] = p_arp->ar_sha[i]; + p_arp->ar_sha[i] = gs_uc_mac_address[i]; + } + /* Swap the source IP address and the destination IP address */ + for (i = 0; i < 4; i++) { + p_arp->ar_tpa[i] = p_arp->ar_spa[i]; + 81682: f89b 301c ldrb.w r3, [fp, #28] + 81686: f88b 3026 strb.w r3, [fp, #38] ; 0x26 + p_arp->ar_spa[i] = gs_uc_ip_address[i]; + 8168a: 23c0 movs r3, #192 ; 0xc0 + 8168c: f88b 301c strb.w r3, [fp, #28] + p_arp->ar_tha[i] = p_arp->ar_sha[i]; + p_arp->ar_sha[i] = gs_uc_mac_address[i]; + } + /* Swap the source IP address and the destination IP address */ + for (i = 0; i < 4; i++) { + p_arp->ar_tpa[i] = p_arp->ar_spa[i]; + 81690: f89b 301d ldrb.w r3, [fp, #29] + 81694: f88b 3027 strb.w r3, [fp, #39] ; 0x27 + p_arp->ar_spa[i] = gs_uc_ip_address[i]; + 81698: 23a8 movs r3, #168 ; 0xa8 + 8169a: f88b 301d strb.w r3, [fp, #29] + p_arp->ar_tha[i] = p_arp->ar_sha[i]; + p_arp->ar_sha[i] = gs_uc_mac_address[i]; + } + /* Swap the source IP address and the destination IP address */ + for (i = 0; i < 4; i++) { + p_arp->ar_tpa[i] = p_arp->ar_spa[i]; + 8169e: f89b 301e ldrb.w r3, [fp, #30] + 816a2: f88b 3028 strb.w r3, [fp, #40] ; 0x28 + p_arp->ar_spa[i] = gs_uc_ip_address[i]; + 816a6: 2300 movs r3, #0 + 816a8: f88b 301e strb.w r3, [fp, #30] + p_arp->ar_tha[i] = p_arp->ar_sha[i]; + p_arp->ar_sha[i] = gs_uc_mac_address[i]; + } + /* Swap the source IP address and the destination IP address */ + for (i = 0; i < 4; i++) { + p_arp->ar_tpa[i] = p_arp->ar_spa[i]; + 816ac: f89b 201f ldrb.w r2, [fp, #31] + 816b0: f88b 2029 strb.w r2, [fp, #41] ; 0x29 + p_arp->ar_spa[i] = gs_uc_ip_address[i]; + 816b4: 2202 movs r2, #2 + 816b6: f88b 201f strb.w r2, [fp, #31] + } + ul_rc = emac_dev_write(&gs_emac_dev, p_uc_data, ul_size, NULL); + 816ba: 4648 mov r0, r9 + 816bc: 4659 mov r1, fp + 816be: 4622 mov r2, r4 + 816c0: 4c29 ldr r4, [pc, #164] ; (81768 ) + 816c2: 47a0 blx r4 + 816c4: 4601 mov r1, r0 + if (ul_rc != EMAC_OK) { + 816c6: f010 0fff tst.w r0, #255 ; 0xff + 816ca: d089 beq.n 815e0 + printf("E: ARP Send - 0x%x\n\r", ul_rc); + 816cc: 4827 ldr r0, [pc, #156] ; (8176c ) + 816ce: b2c9 uxtb r1, r1 + 816d0: 4b11 ldr r3, [pc, #68] ; (81718 ) + 816d2: 4798 blx r3 + 816d4: e784 b.n 815e0 + 816d6: bf00 nop + 816d8: 00080151 .word 0x00080151 + 816dc: 00080241 .word 0x00080241 + 816e0: 00081029 .word 0x00081029 + 816e4: 400e0800 .word 0x400e0800 + 816e8: 200748e4 .word 0x200748e4 + 816ec: 000813f9 .word 0x000813f9 + 816f0: 200748e0 .word 0x200748e0 + 816f4: 00081351 .word 0x00081351 + 816f8: 200748dc .word 0x200748dc + 816fc: 0501bd00 .word 0x0501bd00 + 81700: 000810a9 .word 0x000810a9 + 81704: 20070558 .word 0x20070558 + 81708: 00081c89 .word 0x00081c89 + 8170c: 000849f0 .word 0x000849f0 + 81710: 00081c79 .word 0x00081c79 + 81714: 00084a40 .word 0x00084a40 + 81718: 00081a69 .word 0x00081a69 + 8171c: 00084a5c .word 0x00084a5c + 81720: 400e1a00 .word 0x400e1a00 + 81724: 0008107d .word 0x0008107d + 81728: 00081099 .word 0x00081099 + 8172c: 000810a5 .word 0x000810a5 + 81730: 00aae600 .word 0x00aae600 + 81734: 000849e8 .word 0x000849e8 + 81738: 2007427c .word 0x2007427c + 8173c: 400b0000 .word 0x400b0000 + 81740: 00080841 .word 0x00080841 + 81744: e000e100 .word 0xe000e100 + 81748: 000805d5 .word 0x000805d5 + 8174c: 00084a74 .word 0x00084a74 + 81750: 000803f1 .word 0x000803f1 + 81754: 00084a8c .word 0x00084a8c + 81758: 00084aa4 .word 0x00084aa4 + 8175c: 00080301 .word 0x00080301 + 81760: 00084ab8 .word 0x00084ab8 + 81764: 00080931 .word 0x00080931 + 81768: 00080ab1 .word 0x00080ab1 + 8176c: 00084acc .word 0x00084acc + 81770: 200742a8 .word 0x200742a8 + break; + + /* IP protocol frame */ + case ETH_PROT_IP: + /* Backup the header */ + memcpy(&ip_header, p_ip_header, sizeof(ip_header_t)); + 81774: f89b 700e ldrb.w r7, [fp, #14] + 81778: f89b 300f ldrb.w r3, [fp, #15] + 8177c: 930d str r3, [sp, #52] ; 0x34 + 8177e: f8bb 6010 ldrh.w r6, [fp, #16] + 81782: f8bb 3012 ldrh.w r3, [fp, #18] + 81786: 9305 str r3, [sp, #20] + 81788: f89b a017 ldrb.w sl, [fp, #23] + 8178c: f8bb 8018 ldrh.w r8, [fp, #24] + 81790: f89b 301a ldrb.w r3, [fp, #26] + 81794: 9306 str r3, [sp, #24] + 81796: f89b 301b ldrb.w r3, [fp, #27] + 8179a: 930e str r3, [sp, #56] ; 0x38 + 8179c: f89b 301c ldrb.w r3, [fp, #28] + 817a0: 930a str r3, [sp, #40] ; 0x28 + 817a2: f89b 301d ldrb.w r3, [fp, #29] + 817a6: 930b str r3, [sp, #44] ; 0x2c + 817a8: f89b 301e ldrb.w r3, [fp, #30] + 817ac: 9309 str r3, [sp, #36] ; 0x24 + 817ae: f89b 301f ldrb.w r3, [fp, #31] + 817b2: 9308 str r3, [sp, #32] + 817b4: f89b 3020 ldrb.w r3, [fp, #32] + 817b8: 9307 str r3, [sp, #28] + 817ba: f89b 3021 ldrb.w r3, [fp, #33] ; 0x21 + 817be: 930c str r3, [sp, #48] ; 0x30 + p_ip_header_t p_ip_header = (p_ip_header_t) (p_uc_data + ETH_HEADER_SIZE); + + p_icmp_echo_header_t p_icmp_echo = + (p_icmp_echo_header_t) ((int8_t *) p_ip_header + + ETH_IP_HEADER_SIZE); + printf("-- IP %d.%d.%d.%d\n\r", p_eth->et_dest[0], p_eth->et_dest[1], + 817c0: f89b 1000 ldrb.w r1, [fp] + 817c4: f89b 2001 ldrb.w r2, [fp, #1] + 817c8: f89b 3002 ldrb.w r3, [fp, #2] + 817cc: f89b 0003 ldrb.w r0, [fp, #3] + 817d0: 9000 str r0, [sp, #0] + 817d2: 487a ldr r0, [pc, #488] ; (819bc ) + 817d4: 4d7a ldr r5, [pc, #488] ; (819c0 ) + 817d6: 47a8 blx r5 + p_eth->et_dest[2], p_eth->et_dest[3]); + + printf("-- IP %d.%d.%d.%d\n\r", + 817d8: f89b 1006 ldrb.w r1, [fp, #6] + 817dc: f89b 2007 ldrb.w r2, [fp, #7] + 817e0: f89b 3008 ldrb.w r3, [fp, #8] + 817e4: f89b 0009 ldrb.w r0, [fp, #9] + 817e8: 9000 str r0, [sp, #0] + 817ea: 4874 ldr r0, [pc, #464] ; (819bc ) + 817ec: 47a8 blx r5 + p_eth->et_src[0], p_eth->et_src[1], p_eth->et_src[2], + p_eth->et_src[3]); + switch (p_ip_header->ip_p) { + 817ee: f89b 3017 ldrb.w r3, [fp, #23] + 817f2: b2db uxtb r3, r3 + 817f4: 2b01 cmp r3, #1 + 817f6: d17b bne.n 818f0 + case IP_PROT_ICMP: + if (p_icmp_echo->type == ICMP_ECHO_REQUEST) { + 817f8: f89b 3022 ldrb.w r3, [fp, #34] ; 0x22 + 817fc: b2db uxtb r3, r3 + 817fe: 2b08 cmp r3, #8 + 81800: d176 bne.n 818f0 + p_icmp_echo->type = ICMP_ECHO_REPLY; + 81802: 2300 movs r3, #0 + 81804: f88b 3022 strb.w r3, [fp, #34] ; 0x22 + p_icmp_echo->code = 0; + 81808: f88b 3023 strb.w r3, [fp, #35] ; 0x23 + p_icmp_echo->cksum = 0; + 8180c: f8ab 3024 strh.w r3, [fp, #36] ; 0x24 + + /* Checksum of the ICMP message */ + ul_icmp_len = (SWAP16(p_ip_header->ip_len) - ETH_IP_HEADER_SIZE); + 81810: f8bb 3010 ldrh.w r3, [fp, #16] + 81814: b29a uxth r2, r3 + 81816: 0213 lsls r3, r2, #8 + 81818: b29b uxth r3, r3 + 8181a: ea43 2312 orr.w r3, r3, r2, lsr #8 + 8181e: f1a3 0e14 sub.w lr, r3, #20 + if (ul_icmp_len % 2) { + 81822: f01e 0f01 tst.w lr, #1 + 81826: d005 beq.n 81834 + *((uint8_t *) p_icmp_echo + ul_icmp_len) = 0; + 81828: 44de add lr, fp + 8182a: 2200 movs r2, #0 + 8182c: f88e 2022 strb.w r2, [lr, #34] ; 0x22 + ul_icmp_len++; + 81830: f1a3 0e13 sub.w lr, r3, #19 + */ +static uint16_t emac_icmp_checksum(uint16_t *p_buff, uint32_t ul_len) +{ + uint32_t i, ul_tmp; + + for (i = 0, ul_tmp = 0; i < ul_len; i++, p_buff++) { + 81834: ea5f 0e5e movs.w lr, lr, lsr #1 + 81838: d011 beq.n 8185e + 8183a: 2200 movs r2, #0 + 8183c: 4611 mov r1, r2 + 8183e: f10b 0022 add.w r0, fp, #34 ; 0x22 + 81842: 9d05 ldr r5, [sp, #20] + + ul_tmp += SWAP16(*p_buff); + 81844: f830 cb02 ldrh.w ip, [r0], #2 + 81848: ea4f 230c mov.w r3, ip, lsl #8 + 8184c: b29b uxth r3, r3 + 8184e: ea43 231c orr.w r3, r3, ip, lsr #8 + 81852: 4419 add r1, r3 + */ +static uint16_t emac_icmp_checksum(uint16_t *p_buff, uint32_t ul_len) +{ + uint32_t i, ul_tmp; + + for (i = 0, ul_tmp = 0; i < ul_len; i++, p_buff++) { + 81854: 3201 adds r2, #1 + 81856: 4572 cmp r2, lr + 81858: d1f4 bne.n 81844 + 8185a: 9505 str r5, [sp, #20] + 8185c: e000 b.n 81860 + 8185e: 2100 movs r1, #0 + + ul_tmp += SWAP16(*p_buff); + } + ul_tmp = (ul_tmp & 0xffff) + (ul_tmp >> 16); + 81860: b28b uxth r3, r1 + 81862: eb03 4311 add.w r3, r3, r1, lsr #16 + + return (uint16_t) (~ul_tmp); + 81866: 43db mvns r3, r3 + 81868: b29b uxth r3, r3 + *((uint8_t *) p_icmp_echo + ul_icmp_len) = 0; + ul_icmp_len++; + } + ul_icmp_len = ul_icmp_len / sizeof(uint16_t); + + p_icmp_echo->cksum = SWAP16( + 8186a: 0a1a lsrs r2, r3, #8 + 8186c: ea42 2303 orr.w r3, r2, r3, lsl #8 + 81870: f8ab 3024 strh.w r3, [fp, #36] ; 0x24 + emac_icmp_checksum((uint16_t *)p_icmp_echo, ul_icmp_len)); + /* Swap the IP destination address and the IP source address */ + for (i = 0; i < 4; i++) { + p_ip_header->ip_dst[i] = + 81874: f89b 301a ldrb.w r3, [fp, #26] + 81878: f88b 301e strb.w r3, [fp, #30] + p_ip_header->ip_src[i]; + p_ip_header->ip_src[i] = gs_uc_ip_address[i]; + 8187c: 23c0 movs r3, #192 ; 0xc0 + 8187e: f88b 301a strb.w r3, [fp, #26] + + p_icmp_echo->cksum = SWAP16( + emac_icmp_checksum((uint16_t *)p_icmp_echo, ul_icmp_len)); + /* Swap the IP destination address and the IP source address */ + for (i = 0; i < 4; i++) { + p_ip_header->ip_dst[i] = + 81882: f89b 301b ldrb.w r3, [fp, #27] + 81886: f88b 301f strb.w r3, [fp, #31] + p_ip_header->ip_src[i]; + p_ip_header->ip_src[i] = gs_uc_ip_address[i]; + 8188a: 23a8 movs r3, #168 ; 0xa8 + 8188c: f88b 301b strb.w r3, [fp, #27] + + p_icmp_echo->cksum = SWAP16( + emac_icmp_checksum((uint16_t *)p_icmp_echo, ul_icmp_len)); + /* Swap the IP destination address and the IP source address */ + for (i = 0; i < 4; i++) { + p_ip_header->ip_dst[i] = + 81890: f89b 301c ldrb.w r3, [fp, #28] + 81894: f88b 3020 strb.w r3, [fp, #32] + p_ip_header->ip_src[i]; + p_ip_header->ip_src[i] = gs_uc_ip_address[i]; + 81898: 2300 movs r3, #0 + 8189a: f88b 301c strb.w r3, [fp, #28] + + p_icmp_echo->cksum = SWAP16( + emac_icmp_checksum((uint16_t *)p_icmp_echo, ul_icmp_len)); + /* Swap the IP destination address and the IP source address */ + for (i = 0; i < 4; i++) { + p_ip_header->ip_dst[i] = + 8189e: f89b 301d ldrb.w r3, [fp, #29] + 818a2: f88b 3021 strb.w r3, [fp, #33] ; 0x21 + p_ip_header->ip_src[i]; + p_ip_header->ip_src[i] = gs_uc_ip_address[i]; + 818a6: 2302 movs r3, #2 + 818a8: f88b 301d strb.w r3, [fp, #29] + 818ac: f10b 0305 add.w r3, fp, #5 + 818b0: 4a44 ldr r2, [pc, #272] ; (819c4 ) + 818b2: 9d05 ldr r5, [sp, #20] + 818b4: 980f ldr r0, [sp, #60] ; 0x3c + } + /* Swap ethernet destination address and ethernet source address */ + for (i = 0; i < 6; i++) { + /* Swap ethernet destination address and ethernet source address */ + p_eth->et_dest[i] = p_eth->et_src[i]; + 818b6: f813 1f01 ldrb.w r1, [r3, #1]! + 818ba: f803 1c06 strb.w r1, [r3, #-6] + p_eth->et_src[i] = gs_uc_mac_address[i]; + 818be: f812 1b01 ldrb.w r1, [r2], #1 + 818c2: 7019 strb r1, [r3, #0] + p_ip_header->ip_dst[i] = + p_ip_header->ip_src[i]; + p_ip_header->ip_src[i] = gs_uc_ip_address[i]; + } + /* Swap ethernet destination address and ethernet source address */ + for (i = 0; i < 6; i++) { + 818c4: 4283 cmp r3, r0 + 818c6: d1f6 bne.n 818b6 + 818c8: 9505 str r5, [sp, #20] + p_eth->et_dest[i] = p_eth->et_src[i]; + p_eth->et_src[i] = gs_uc_mac_address[i]; + } + /* Send the echo_reply */ + ul_rc = emac_dev_write(&gs_emac_dev, p_uc_data, + SWAP16(p_ip_header->ip_len) + 14, NULL); + 818ca: f8bb 2010 ldrh.w r2, [fp, #16] + 818ce: b292 uxth r2, r2 + 818d0: 0213 lsls r3, r2, #8 + 818d2: b29b uxth r3, r3 + 818d4: ea43 2212 orr.w r2, r3, r2, lsr #8 + /* Swap ethernet destination address and ethernet source address */ + p_eth->et_dest[i] = p_eth->et_src[i]; + p_eth->et_src[i] = gs_uc_mac_address[i]; + } + /* Send the echo_reply */ + ul_rc = emac_dev_write(&gs_emac_dev, p_uc_data, + 818d8: 4648 mov r0, r9 + 818da: 4659 mov r1, fp + 818dc: 320e adds r2, #14 + 818de: 2300 movs r3, #0 + 818e0: f8df c130 ldr.w ip, [pc, #304] ; 81a14 + 818e4: 47e0 blx ip + SWAP16(p_ip_header->ip_len) + 14, NULL); + if (ul_rc != EMAC_OK) { + 818e6: 4601 mov r1, r0 + 818e8: b110 cbz r0, 818f0 + printf("E: ICMP Send - 0x%x\n\r", ul_rc); + 818ea: 4837 ldr r0, [pc, #220] ; (819c8 ) + 818ec: 4b34 ldr r3, [pc, #208] ; (819c0 ) + 818ee: 4798 blx r3 + * \param p_ip_header Pointer to the IP header. + * \param ul_size The data size. + */ +static void emac_display_ip_packet(p_ip_header_t p_ip_header, uint32_t ul_size) +{ + printf("======= IP %4d bytes, HEADER ==========\n\r", (int)ul_size); + 818f0: 4836 ldr r0, [pc, #216] ; (819cc ) + 818f2: 4621 mov r1, r4 + 818f4: 4c32 ldr r4, [pc, #200] ; (819c0 ) + 818f6: 47a0 blx r4 + printf(" IP Version = v.%d", (p_ip_header->ip_hl_v & 0xF0) >> 4); + 818f8: 4835 ldr r0, [pc, #212] ; (819d0 ) + 818fa: 0939 lsrs r1, r7, #4 + 818fc: 47a0 blx r4 + printf("\n\r Header Length = %d", p_ip_header->ip_hl_v & 0x0F); + 818fe: 4835 ldr r0, [pc, #212] ; (819d4 ) + 81900: f007 010f and.w r1, r7, #15 + 81904: 47a0 blx r4 + printf("\n\r Type of service = 0x%x", p_ip_header->ip_tos); + 81906: 4834 ldr r0, [pc, #208] ; (819d8 ) + 81908: 990d ldr r1, [sp, #52] ; 0x34 + 8190a: 47a0 blx r4 + printf("\n\r Total IP Length = 0x%X", + (((p_ip_header->ip_len) >> 8) & 0xff) + + (((p_ip_header->ip_len) << 8) & 0xff00)); + 8190c: 0231 lsls r1, r6, #8 + 8190e: b289 uxth r1, r1 +{ + printf("======= IP %4d bytes, HEADER ==========\n\r", (int)ul_size); + printf(" IP Version = v.%d", (p_ip_header->ip_hl_v & 0xF0) >> 4); + printf("\n\r Header Length = %d", p_ip_header->ip_hl_v & 0x0F); + printf("\n\r Type of service = 0x%x", p_ip_header->ip_tos); + printf("\n\r Total IP Length = 0x%X", + 81910: 4832 ldr r0, [pc, #200] ; (819dc ) + 81912: eb01 2116 add.w r1, r1, r6, lsr #8 + 81916: 47a0 blx r4 + (((p_ip_header->ip_len) >> 8) & 0xff) + + (((p_ip_header->ip_len) << 8) & 0xff00)); + printf("\n\r ID = 0x%X", + (((p_ip_header->ip_id) >> 8) & 0xff) + + (((p_ip_header->ip_id) << 8) & 0xff00)); + 81918: 9b05 ldr r3, [sp, #20] + 8191a: 0219 lsls r1, r3, #8 + 8191c: b289 uxth r1, r1 + printf("\n\r Header Length = %d", p_ip_header->ip_hl_v & 0x0F); + printf("\n\r Type of service = 0x%x", p_ip_header->ip_tos); + printf("\n\r Total IP Length = 0x%X", + (((p_ip_header->ip_len) >> 8) & 0xff) + + (((p_ip_header->ip_len) << 8) & 0xff00)); + printf("\n\r ID = 0x%X", + 8191e: 4830 ldr r0, [pc, #192] ; (819e0 ) + 81920: eb01 2113 add.w r1, r1, r3, lsr #8 + 81924: 47a0 blx r4 + (((p_ip_header->ip_id) >> 8) & 0xff) + + (((p_ip_header->ip_id) << 8) & 0xff00)); + printf("\n\r Header Checksum = 0x%X", + (((p_ip_header->ip_sum) >> 8) & 0xff) + + (((p_ip_header->ip_sum) << 8) & 0xff00)); + 81926: ea4f 2108 mov.w r1, r8, lsl #8 + 8192a: b289 uxth r1, r1 + (((p_ip_header->ip_len) >> 8) & 0xff) + + (((p_ip_header->ip_len) << 8) & 0xff00)); + printf("\n\r ID = 0x%X", + (((p_ip_header->ip_id) >> 8) & 0xff) + + (((p_ip_header->ip_id) << 8) & 0xff00)); + printf("\n\r Header Checksum = 0x%X", + 8192c: 482d ldr r0, [pc, #180] ; (819e4 ) + 8192e: eb01 2118 add.w r1, r1, r8, lsr #8 + 81932: 47a0 blx r4 + (((p_ip_header->ip_sum) >> 8) & 0xff) + + (((p_ip_header->ip_sum) << 8) & 0xff00)); + puts("\r Protocol = "); + 81934: 482c ldr r0, [pc, #176] ; (819e8 ) + 81936: 4b2d ldr r3, [pc, #180] ; (819ec ) + 81938: 4798 blx r3 + + switch (p_ip_header->ip_p) { + 8193a: f10a 33ff add.w r3, sl, #4294967295 + 8193e: 2b10 cmp r3, #16 + 81940: d81a bhi.n 81978 + 81942: e8df f003 tbb [pc, r3] + 81946: 1909 .short 0x1909 + 81948: 11190d19 .word 0x11190d19 + 8194c: 19191919 .word 0x19191919 + 81950: 19191919 .word 0x19191919 + 81954: 1919 .short 0x1919 + 81956: 15 .byte 0x15 + 81957: 00 .byte 0x00 + case IP_PROT_ICMP: + puts("ICMP"); + 81958: 4825 ldr r0, [pc, #148] ; (819f0 ) + 8195a: 4b24 ldr r3, [pc, #144] ; (819ec ) + 8195c: 4798 blx r3 + 8195e: e010 b.n 81982 + break; + + case IP_PROT_IP: + puts("IP"); + 81960: 4824 ldr r0, [pc, #144] ; (819f4 ) + 81962: 4b22 ldr r3, [pc, #136] ; (819ec ) + 81964: 4798 blx r3 + 81966: e00c b.n 81982 + break; + + case IP_PROT_TCP: + puts("TCP"); + 81968: 4823 ldr r0, [pc, #140] ; (819f8 ) + 8196a: 4b20 ldr r3, [pc, #128] ; (819ec ) + 8196c: 4798 blx r3 + 8196e: e008 b.n 81982 + break; + + case IP_PROT_UDP: + puts("UDP"); + 81970: 4822 ldr r0, [pc, #136] ; (819fc ) + 81972: 4b1e ldr r3, [pc, #120] ; (819ec ) + 81974: 4798 blx r3 + 81976: e004 b.n 81982 + break; + + default: + printf("%d (0x%X)", p_ip_header->ip_p, p_ip_header->ip_p); + 81978: 4821 ldr r0, [pc, #132] ; (81a00 ) + 8197a: 4651 mov r1, sl + 8197c: 4652 mov r2, sl + 8197e: 4b10 ldr r3, [pc, #64] ; (819c0 ) + 81980: 4798 blx r3 + break; + } + + printf("\n\r IP Src Address = %d:%d:%d:%d", + 81982: 9b0b ldr r3, [sp, #44] ; 0x2c + 81984: 9300 str r3, [sp, #0] + 81986: 481f ldr r0, [pc, #124] ; (81a04 ) + 81988: 9906 ldr r1, [sp, #24] + 8198a: 9a0e ldr r2, [sp, #56] ; 0x38 + 8198c: 9b0a ldr r3, [sp, #40] ; 0x28 + 8198e: 4c0c ldr r4, [pc, #48] ; (819c0 ) + 81990: 47a0 blx r4 + p_ip_header->ip_src[0], + p_ip_header->ip_src[1], + p_ip_header->ip_src[2], p_ip_header->ip_src[3]); + + printf("\n\r IP Dest Address = %d:%d:%d:%d", + 81992: 9b0c ldr r3, [sp, #48] ; 0x30 + 81994: 9300 str r3, [sp, #0] + 81996: 481c ldr r0, [pc, #112] ; (81a08 ) + 81998: 9909 ldr r1, [sp, #36] ; 0x24 + 8199a: 9a08 ldr r2, [sp, #32] + 8199c: 9b07 ldr r3, [sp, #28] + 8199e: 47a0 blx r4 + p_ip_header->ip_dst[0], + p_ip_header->ip_dst[1], + p_ip_header->ip_dst[2], p_ip_header->ip_dst[3]); + puts("\n\r----------------------------------------\r"); + 819a0: 481a ldr r0, [pc, #104] ; (81a0c ) + 819a2: 4b12 ldr r3, [pc, #72] ; (819ec ) + 819a4: 4798 blx r3 + 819a6: e61b b.n 815e0 + /* Dump the IP header */ + emac_display_ip_packet(&ip_header, ul_size); + break; + + default: + printf("=== Default w_pkt_format= 0x%X===\n\r", us_pkt_format); + 819a8: 4819 ldr r0, [pc, #100] ; (81a10 ) + 819aa: 4b05 ldr r3, [pc, #20] ; (819c0 ) + 819ac: 4798 blx r3 + 819ae: e617 b.n 815e0 + if (ul_frm_size > 0) { + /* Handle input frame */ + emac_process_eth_packet((uint8_t *) gs_uc_eth_buffer, ul_frm_size); + } + } +} + 819b0: f04f 30ff mov.w r0, #4294967295 + 819b4: b019 add sp, #100 ; 0x64 + 819b6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 819ba: bf00 nop + 819bc: 00084a5c .word 0x00084a5c + 819c0: 00081a69 .word 0x00081a69 + 819c4: 000849e8 .word 0x000849e8 + 819c8: 00084ae4 .word 0x00084ae4 + 819cc: 00084afc .word 0x00084afc + 819d0: 00084b28 .word 0x00084b28 + 819d4: 00084b44 .word 0x00084b44 + 819d8: 00084b60 .word 0x00084b60 + 819dc: 00084b7c .word 0x00084b7c + 819e0: 00084b98 .word 0x00084b98 + 819e4: 00084bb4 .word 0x00084bb4 + 819e8: 00084bd0 .word 0x00084bd0 + 819ec: 00081c79 .word 0x00081c79 + 819f0: 00084be8 .word 0x00084be8 + 819f4: 00084bf0 .word 0x00084bf0 + 819f8: 00084bf4 .word 0x00084bf4 + 819fc: 00084bf8 .word 0x00084bf8 + 81a00: 00084bfc .word 0x00084bfc + 81a04: 00084c08 .word 0x00084c08 + 81a08: 00084c2c .word 0x00084c2c + 81a0c: 00084c50 .word 0x00084c50 + 81a10: 00084c7c .word 0x00084c7c + 81a14: 00080ab1 .word 0x00080ab1 + +00081a18 <__libc_init_array>: + 81a18: b570 push {r4, r5, r6, lr} + 81a1a: 4e0f ldr r6, [pc, #60] ; (81a58 <__libc_init_array+0x40>) + 81a1c: 4d0f ldr r5, [pc, #60] ; (81a5c <__libc_init_array+0x44>) + 81a1e: 1b76 subs r6, r6, r5 + 81a20: 10b6 asrs r6, r6, #2 + 81a22: bf18 it ne + 81a24: 2400 movne r4, #0 + 81a26: d005 beq.n 81a34 <__libc_init_array+0x1c> + 81a28: 3401 adds r4, #1 + 81a2a: f855 3b04 ldr.w r3, [r5], #4 + 81a2e: 4798 blx r3 + 81a30: 42a6 cmp r6, r4 + 81a32: d1f9 bne.n 81a28 <__libc_init_array+0x10> + 81a34: 4e0a ldr r6, [pc, #40] ; (81a60 <__libc_init_array+0x48>) + 81a36: 4d0b ldr r5, [pc, #44] ; (81a64 <__libc_init_array+0x4c>) + 81a38: f003 f960 bl 84cfc <_init> + 81a3c: 1b76 subs r6, r6, r5 + 81a3e: 10b6 asrs r6, r6, #2 + 81a40: bf18 it ne + 81a42: 2400 movne r4, #0 + 81a44: d006 beq.n 81a54 <__libc_init_array+0x3c> + 81a46: 3401 adds r4, #1 + 81a48: f855 3b04 ldr.w r3, [r5], #4 + 81a4c: 4798 blx r3 + 81a4e: 42a6 cmp r6, r4 + 81a50: d1f9 bne.n 81a46 <__libc_init_array+0x2e> + 81a52: bd70 pop {r4, r5, r6, pc} + 81a54: bd70 pop {r4, r5, r6, pc} + 81a56: bf00 nop + 81a58: 00084d08 .word 0x00084d08 + 81a5c: 00084d08 .word 0x00084d08 + 81a60: 00084d10 .word 0x00084d10 + 81a64: 00084d08 .word 0x00084d08 + +00081a68 : + 81a68: b40f push {r0, r1, r2, r3} + 81a6a: b510 push {r4, lr} + 81a6c: 4b07 ldr r3, [pc, #28] ; (81a8c ) + 81a6e: b082 sub sp, #8 + 81a70: ac04 add r4, sp, #16 + 81a72: f854 2b04 ldr.w r2, [r4], #4 + 81a76: 6818 ldr r0, [r3, #0] + 81a78: 4623 mov r3, r4 + 81a7a: 6881 ldr r1, [r0, #8] + 81a7c: 9401 str r4, [sp, #4] + 81a7e: f000 f9f1 bl 81e64 <_vfiprintf_r> + 81a82: b002 add sp, #8 + 81a84: e8bd 4010 ldmia.w sp!, {r4, lr} + 81a88: b004 add sp, #16 + 81a8a: 4770 bx lr + 81a8c: 20070558 .word 0x20070558 + +00081a90 : + 81a90: 4684 mov ip, r0 + 81a92: ea41 0300 orr.w r3, r1, r0 + 81a96: f013 0303 ands.w r3, r3, #3 + 81a9a: d149 bne.n 81b30 + 81a9c: 3a40 subs r2, #64 ; 0x40 + 81a9e: d323 bcc.n 81ae8 + 81aa0: 680b ldr r3, [r1, #0] + 81aa2: 6003 str r3, [r0, #0] + 81aa4: 684b ldr r3, [r1, #4] + 81aa6: 6043 str r3, [r0, #4] + 81aa8: 688b ldr r3, [r1, #8] + 81aaa: 6083 str r3, [r0, #8] + 81aac: 68cb ldr r3, [r1, #12] + 81aae: 60c3 str r3, [r0, #12] + 81ab0: 690b ldr r3, [r1, #16] + 81ab2: 6103 str r3, [r0, #16] + 81ab4: 694b ldr r3, [r1, #20] + 81ab6: 6143 str r3, [r0, #20] + 81ab8: 698b ldr r3, [r1, #24] + 81aba: 6183 str r3, [r0, #24] + 81abc: 69cb ldr r3, [r1, #28] + 81abe: 61c3 str r3, [r0, #28] + 81ac0: 6a0b ldr r3, [r1, #32] + 81ac2: 6203 str r3, [r0, #32] + 81ac4: 6a4b ldr r3, [r1, #36] ; 0x24 + 81ac6: 6243 str r3, [r0, #36] ; 0x24 + 81ac8: 6a8b ldr r3, [r1, #40] ; 0x28 + 81aca: 6283 str r3, [r0, #40] ; 0x28 + 81acc: 6acb ldr r3, [r1, #44] ; 0x2c + 81ace: 62c3 str r3, [r0, #44] ; 0x2c + 81ad0: 6b0b ldr r3, [r1, #48] ; 0x30 + 81ad2: 6303 str r3, [r0, #48] ; 0x30 + 81ad4: 6b4b ldr r3, [r1, #52] ; 0x34 + 81ad6: 6343 str r3, [r0, #52] ; 0x34 + 81ad8: 6b8b ldr r3, [r1, #56] ; 0x38 + 81ada: 6383 str r3, [r0, #56] ; 0x38 + 81adc: 6bcb ldr r3, [r1, #60] ; 0x3c + 81ade: 63c3 str r3, [r0, #60] ; 0x3c + 81ae0: 3040 adds r0, #64 ; 0x40 + 81ae2: 3140 adds r1, #64 ; 0x40 + 81ae4: 3a40 subs r2, #64 ; 0x40 + 81ae6: d2db bcs.n 81aa0 + 81ae8: 3230 adds r2, #48 ; 0x30 + 81aea: d30b bcc.n 81b04 + 81aec: 680b ldr r3, [r1, #0] + 81aee: 6003 str r3, [r0, #0] + 81af0: 684b ldr r3, [r1, #4] + 81af2: 6043 str r3, [r0, #4] + 81af4: 688b ldr r3, [r1, #8] + 81af6: 6083 str r3, [r0, #8] + 81af8: 68cb ldr r3, [r1, #12] + 81afa: 60c3 str r3, [r0, #12] + 81afc: 3010 adds r0, #16 + 81afe: 3110 adds r1, #16 + 81b00: 3a10 subs r2, #16 + 81b02: d2f3 bcs.n 81aec + 81b04: 320c adds r2, #12 + 81b06: d305 bcc.n 81b14 + 81b08: f851 3b04 ldr.w r3, [r1], #4 + 81b0c: f840 3b04 str.w r3, [r0], #4 + 81b10: 3a04 subs r2, #4 + 81b12: d2f9 bcs.n 81b08 + 81b14: 3204 adds r2, #4 + 81b16: d008 beq.n 81b2a + 81b18: 07d2 lsls r2, r2, #31 + 81b1a: bf1c itt ne + 81b1c: f811 3b01 ldrbne.w r3, [r1], #1 + 81b20: f800 3b01 strbne.w r3, [r0], #1 + 81b24: d301 bcc.n 81b2a + 81b26: 880b ldrh r3, [r1, #0] + 81b28: 8003 strh r3, [r0, #0] + 81b2a: 4660 mov r0, ip + 81b2c: 4770 bx lr + 81b2e: bf00 nop + 81b30: 2a08 cmp r2, #8 + 81b32: d313 bcc.n 81b5c + 81b34: 078b lsls r3, r1, #30 + 81b36: d0b1 beq.n 81a9c + 81b38: f010 0303 ands.w r3, r0, #3 + 81b3c: d0ae beq.n 81a9c + 81b3e: f1c3 0304 rsb r3, r3, #4 + 81b42: 1ad2 subs r2, r2, r3 + 81b44: 07db lsls r3, r3, #31 + 81b46: bf1c itt ne + 81b48: f811 3b01 ldrbne.w r3, [r1], #1 + 81b4c: f800 3b01 strbne.w r3, [r0], #1 + 81b50: d3a4 bcc.n 81a9c + 81b52: f831 3b02 ldrh.w r3, [r1], #2 + 81b56: f820 3b02 strh.w r3, [r0], #2 + 81b5a: e79f b.n 81a9c + 81b5c: 3a04 subs r2, #4 + 81b5e: d3d9 bcc.n 81b14 + 81b60: 3a01 subs r2, #1 + 81b62: f811 3b01 ldrb.w r3, [r1], #1 + 81b66: f800 3b01 strb.w r3, [r0], #1 + 81b6a: d2f9 bcs.n 81b60 + 81b6c: 780b ldrb r3, [r1, #0] + 81b6e: 7003 strb r3, [r0, #0] + 81b70: 784b ldrb r3, [r1, #1] + 81b72: 7043 strb r3, [r0, #1] + 81b74: 788b ldrb r3, [r1, #2] + 81b76: 7083 strb r3, [r0, #2] + 81b78: 4660 mov r0, ip + 81b7a: 4770 bx lr + +00081b7c : + 81b7c: b470 push {r4, r5, r6} + 81b7e: 0784 lsls r4, r0, #30 + 81b80: d046 beq.n 81c10 + 81b82: 1e54 subs r4, r2, #1 + 81b84: 2a00 cmp r2, #0 + 81b86: d041 beq.n 81c0c + 81b88: b2cd uxtb r5, r1 + 81b8a: 4603 mov r3, r0 + 81b8c: e002 b.n 81b94 + 81b8e: 1e62 subs r2, r4, #1 + 81b90: b3e4 cbz r4, 81c0c + 81b92: 4614 mov r4, r2 + 81b94: f803 5b01 strb.w r5, [r3], #1 + 81b98: 079a lsls r2, r3, #30 + 81b9a: d1f8 bne.n 81b8e + 81b9c: 2c03 cmp r4, #3 + 81b9e: d92e bls.n 81bfe + 81ba0: b2cd uxtb r5, r1 + 81ba2: ea45 2505 orr.w r5, r5, r5, lsl #8 + 81ba6: 2c0f cmp r4, #15 + 81ba8: ea45 4505 orr.w r5, r5, r5, lsl #16 + 81bac: d919 bls.n 81be2 + 81bae: 4626 mov r6, r4 + 81bb0: f103 0210 add.w r2, r3, #16 + 81bb4: 3e10 subs r6, #16 + 81bb6: 2e0f cmp r6, #15 + 81bb8: f842 5c10 str.w r5, [r2, #-16] + 81bbc: f842 5c0c str.w r5, [r2, #-12] + 81bc0: f842 5c08 str.w r5, [r2, #-8] + 81bc4: f842 5c04 str.w r5, [r2, #-4] + 81bc8: f102 0210 add.w r2, r2, #16 + 81bcc: d8f2 bhi.n 81bb4 + 81bce: f1a4 0210 sub.w r2, r4, #16 + 81bd2: f022 020f bic.w r2, r2, #15 + 81bd6: f004 040f and.w r4, r4, #15 + 81bda: 3210 adds r2, #16 + 81bdc: 2c03 cmp r4, #3 + 81bde: 4413 add r3, r2 + 81be0: d90d bls.n 81bfe + 81be2: 461e mov r6, r3 + 81be4: 4622 mov r2, r4 + 81be6: 3a04 subs r2, #4 + 81be8: 2a03 cmp r2, #3 + 81bea: f846 5b04 str.w r5, [r6], #4 + 81bee: d8fa bhi.n 81be6 + 81bf0: 1f22 subs r2, r4, #4 + 81bf2: f022 0203 bic.w r2, r2, #3 + 81bf6: 3204 adds r2, #4 + 81bf8: 4413 add r3, r2 + 81bfa: f004 0403 and.w r4, r4, #3 + 81bfe: b12c cbz r4, 81c0c + 81c00: b2c9 uxtb r1, r1 + 81c02: 441c add r4, r3 + 81c04: f803 1b01 strb.w r1, [r3], #1 + 81c08: 42a3 cmp r3, r4 + 81c0a: d1fb bne.n 81c04 + 81c0c: bc70 pop {r4, r5, r6} + 81c0e: 4770 bx lr + 81c10: 4614 mov r4, r2 + 81c12: 4603 mov r3, r0 + 81c14: e7c2 b.n 81b9c + 81c16: bf00 nop + +00081c18 <_puts_r>: + 81c18: b5f0 push {r4, r5, r6, r7, lr} + 81c1a: 4604 mov r4, r0 + 81c1c: b089 sub sp, #36 ; 0x24 + 81c1e: 4608 mov r0, r1 + 81c20: 460d mov r5, r1 + 81c22: f000 f8b5 bl 81d90 + 81c26: 68a3 ldr r3, [r4, #8] + 81c28: 2102 movs r1, #2 + 81c2a: 899a ldrh r2, [r3, #12] + 81c2c: f8df e044 ldr.w lr, [pc, #68] ; 81c74 <_puts_r+0x5c> + 81c30: f100 0c01 add.w ip, r0, #1 + 81c34: 2701 movs r7, #1 + 81c36: ae04 add r6, sp, #16 + 81c38: 9102 str r1, [sp, #8] + 81c3a: 0491 lsls r1, r2, #18 + 81c3c: 9504 str r5, [sp, #16] + 81c3e: 9005 str r0, [sp, #20] + 81c40: f8cd c00c str.w ip, [sp, #12] + 81c44: f8cd e018 str.w lr, [sp, #24] + 81c48: 9707 str r7, [sp, #28] + 81c4a: 9601 str r6, [sp, #4] + 81c4c: d406 bmi.n 81c5c <_puts_r+0x44> + 81c4e: 6e59 ldr r1, [r3, #100] ; 0x64 + 81c50: f442 5200 orr.w r2, r2, #8192 ; 0x2000 + 81c54: f421 5100 bic.w r1, r1, #8192 ; 0x2000 + 81c58: 819a strh r2, [r3, #12] + 81c5a: 6659 str r1, [r3, #100] ; 0x64 + 81c5c: 4620 mov r0, r4 + 81c5e: 4619 mov r1, r3 + 81c60: aa01 add r2, sp, #4 + 81c62: f001 fa9f bl 831a4 <__sfvwrite_r> + 81c66: 2800 cmp r0, #0 + 81c68: bf14 ite ne + 81c6a: f04f 30ff movne.w r0, #4294967295 + 81c6e: 200a moveq r0, #10 + 81c70: b009 add sp, #36 ; 0x24 + 81c72: bdf0 pop {r4, r5, r6, r7, pc} + 81c74: 00084ca8 .word 0x00084ca8 + +00081c78 : + 81c78: 4b02 ldr r3, [pc, #8] ; (81c84 ) + 81c7a: 4601 mov r1, r0 + 81c7c: 6818 ldr r0, [r3, #0] + 81c7e: f7ff bfcb b.w 81c18 <_puts_r> + 81c82: bf00 nop + 81c84: 20070558 .word 0x20070558 + +00081c88 : + 81c88: 2900 cmp r1, #0 + 81c8a: bf0c ite eq + 81c8c: 2202 moveq r2, #2 + 81c8e: 2200 movne r2, #0 + 81c90: f44f 6380 mov.w r3, #1024 ; 0x400 + 81c94: f000 b800 b.w 81c98 + +00081c98 : + 81c98: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 81c9c: 4d3a ldr r5, [pc, #232] ; (81d88 ) + 81c9e: 4604 mov r4, r0 + 81ca0: 682e ldr r6, [r5, #0] + 81ca2: 4690 mov r8, r2 + 81ca4: 460d mov r5, r1 + 81ca6: 461f mov r7, r3 + 81ca8: b116 cbz r6, 81cb0 + 81caa: 6bb3 ldr r3, [r6, #56] ; 0x38 + 81cac: 2b00 cmp r3, #0 + 81cae: d03c beq.n 81d2a + 81cb0: f1b8 0f02 cmp.w r8, #2 + 81cb4: d82f bhi.n 81d16 + 81cb6: 2f00 cmp r7, #0 + 81cb8: db2d blt.n 81d16 + 81cba: 4621 mov r1, r4 + 81cbc: 4630 mov r0, r6 + 81cbe: f001 f82d bl 82d1c <_fflush_r> + 81cc2: 89a1 ldrh r1, [r4, #12] + 81cc4: 2300 movs r3, #0 + 81cc6: 6063 str r3, [r4, #4] + 81cc8: 61a3 str r3, [r4, #24] + 81cca: 060b lsls r3, r1, #24 + 81ccc: d427 bmi.n 81d1e + 81cce: f021 0183 bic.w r1, r1, #131 ; 0x83 + 81cd2: b289 uxth r1, r1 + 81cd4: f1b8 0f02 cmp.w r8, #2 + 81cd8: 81a1 strh r1, [r4, #12] + 81cda: d02a beq.n 81d32 + 81cdc: 2d00 cmp r5, #0 + 81cde: d036 beq.n 81d4e + 81ce0: f1b8 0f01 cmp.w r8, #1 + 81ce4: d011 beq.n 81d0a + 81ce6: b289 uxth r1, r1 + 81ce8: f001 0008 and.w r0, r1, #8 + 81cec: 4b27 ldr r3, [pc, #156] ; (81d8c ) + 81cee: b280 uxth r0, r0 + 81cf0: 63f3 str r3, [r6, #60] ; 0x3c + 81cf2: 6025 str r5, [r4, #0] + 81cf4: 6125 str r5, [r4, #16] + 81cf6: 6167 str r7, [r4, #20] + 81cf8: b178 cbz r0, 81d1a + 81cfa: f011 0f03 tst.w r1, #3 + 81cfe: bf18 it ne + 81d00: 2700 movne r7, #0 + 81d02: 2000 movs r0, #0 + 81d04: 60a7 str r7, [r4, #8] + 81d06: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 81d0a: f041 0101 orr.w r1, r1, #1 + 81d0e: 427b negs r3, r7 + 81d10: 81a1 strh r1, [r4, #12] + 81d12: 61a3 str r3, [r4, #24] + 81d14: e7e7 b.n 81ce6 + 81d16: f04f 30ff mov.w r0, #4294967295 + 81d1a: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 81d1e: 6921 ldr r1, [r4, #16] + 81d20: 4630 mov r0, r6 + 81d22: f001 f967 bl 82ff4 <_free_r> + 81d26: 89a1 ldrh r1, [r4, #12] + 81d28: e7d1 b.n 81cce + 81d2a: 4630 mov r0, r6 + 81d2c: f001 f88a bl 82e44 <__sinit> + 81d30: e7be b.n 81cb0 + 81d32: 2000 movs r0, #0 + 81d34: f104 0343 add.w r3, r4, #67 ; 0x43 + 81d38: f041 0102 orr.w r1, r1, #2 + 81d3c: 2500 movs r5, #0 + 81d3e: 2201 movs r2, #1 + 81d40: 81a1 strh r1, [r4, #12] + 81d42: 60a5 str r5, [r4, #8] + 81d44: 6023 str r3, [r4, #0] + 81d46: 6123 str r3, [r4, #16] + 81d48: 6162 str r2, [r4, #20] + 81d4a: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 81d4e: 2f00 cmp r7, #0 + 81d50: bf08 it eq + 81d52: f44f 6780 moveq.w r7, #1024 ; 0x400 + 81d56: 4638 mov r0, r7 + 81d58: f001 fc56 bl 83608 + 81d5c: 4605 mov r5, r0 + 81d5e: b128 cbz r0, 81d6c + 81d60: 89a1 ldrh r1, [r4, #12] + 81d62: f041 0180 orr.w r1, r1, #128 ; 0x80 + 81d66: b289 uxth r1, r1 + 81d68: 81a1 strh r1, [r4, #12] + 81d6a: e7b9 b.n 81ce0 + 81d6c: f44f 6080 mov.w r0, #1024 ; 0x400 + 81d70: f001 fc4a bl 83608 + 81d74: 4605 mov r5, r0 + 81d76: b918 cbnz r0, 81d80 + 81d78: 89a1 ldrh r1, [r4, #12] + 81d7a: f04f 30ff mov.w r0, #4294967295 + 81d7e: e7d9 b.n 81d34 + 81d80: f44f 6780 mov.w r7, #1024 ; 0x400 + 81d84: e7ec b.n 81d60 + 81d86: bf00 nop + 81d88: 20070558 .word 0x20070558 + 81d8c: 00082d49 .word 0x00082d49 + +00081d90 : + 81d90: f020 0103 bic.w r1, r0, #3 + 81d94: f010 0003 ands.w r0, r0, #3 + 81d98: f1c0 0000 rsb r0, r0, #0 + 81d9c: f851 3b04 ldr.w r3, [r1], #4 + 81da0: f100 0c04 add.w ip, r0, #4 + 81da4: ea4f 0ccc mov.w ip, ip, lsl #3 + 81da8: f06f 0200 mvn.w r2, #0 + 81dac: bf1c itt ne + 81dae: fa22 f20c lsrne.w r2, r2, ip + 81db2: 4313 orrne r3, r2 + 81db4: f04f 0c01 mov.w ip, #1 + 81db8: ea4c 2c0c orr.w ip, ip, ip, lsl #8 + 81dbc: ea4c 4c0c orr.w ip, ip, ip, lsl #16 + 81dc0: eba3 020c sub.w r2, r3, ip + 81dc4: ea22 0203 bic.w r2, r2, r3 + 81dc8: ea12 12cc ands.w r2, r2, ip, lsl #7 + 81dcc: bf04 itt eq + 81dce: f851 3b04 ldreq.w r3, [r1], #4 + 81dd2: 3004 addeq r0, #4 + 81dd4: d0f4 beq.n 81dc0 + 81dd6: f1c2 0100 rsb r1, r2, #0 + 81dda: ea02 0201 and.w r2, r2, r1 + 81dde: fab2 f282 clz r2, r2 + 81de2: f1c2 021f rsb r2, r2, #31 + 81de6: eb00 00d2 add.w r0, r0, r2, lsr #3 + 81dea: 4770 bx lr + +00081dec <__sprint_r.part.0>: + 81dec: 6e4b ldr r3, [r1, #100] ; 0x64 + 81dee: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 81df2: 049c lsls r4, r3, #18 + 81df4: 460f mov r7, r1 + 81df6: 4692 mov sl, r2 + 81df8: d52b bpl.n 81e52 <__sprint_r.part.0+0x66> + 81dfa: 6893 ldr r3, [r2, #8] + 81dfc: 6812 ldr r2, [r2, #0] + 81dfe: b333 cbz r3, 81e4e <__sprint_r.part.0+0x62> + 81e00: 4680 mov r8, r0 + 81e02: f102 0908 add.w r9, r2, #8 + 81e06: e919 0060 ldmdb r9, {r5, r6} + 81e0a: 08b6 lsrs r6, r6, #2 + 81e0c: d017 beq.n 81e3e <__sprint_r.part.0+0x52> + 81e0e: 3d04 subs r5, #4 + 81e10: 2400 movs r4, #0 + 81e12: e001 b.n 81e18 <__sprint_r.part.0+0x2c> + 81e14: 42a6 cmp r6, r4 + 81e16: d010 beq.n 81e3a <__sprint_r.part.0+0x4e> + 81e18: 4640 mov r0, r8 + 81e1a: f855 1f04 ldr.w r1, [r5, #4]! + 81e1e: 463a mov r2, r7 + 81e20: f001 f888 bl 82f34 <_fputwc_r> + 81e24: 1c43 adds r3, r0, #1 + 81e26: f104 0401 add.w r4, r4, #1 + 81e2a: d1f3 bne.n 81e14 <__sprint_r.part.0+0x28> + 81e2c: 2300 movs r3, #0 + 81e2e: f8ca 3008 str.w r3, [sl, #8] + 81e32: f8ca 3004 str.w r3, [sl, #4] + 81e36: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 81e3a: f8da 3008 ldr.w r3, [sl, #8] + 81e3e: eba3 0386 sub.w r3, r3, r6, lsl #2 + 81e42: f8ca 3008 str.w r3, [sl, #8] + 81e46: f109 0908 add.w r9, r9, #8 + 81e4a: 2b00 cmp r3, #0 + 81e4c: d1db bne.n 81e06 <__sprint_r.part.0+0x1a> + 81e4e: 2000 movs r0, #0 + 81e50: e7ec b.n 81e2c <__sprint_r.part.0+0x40> + 81e52: f001 f9a7 bl 831a4 <__sfvwrite_r> + 81e56: 2300 movs r3, #0 + 81e58: f8ca 3008 str.w r3, [sl, #8] + 81e5c: f8ca 3004 str.w r3, [sl, #4] + 81e60: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + +00081e64 <_vfiprintf_r>: + 81e64: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 81e68: b0ab sub sp, #172 ; 0xac + 81e6a: 461c mov r4, r3 + 81e6c: 9100 str r1, [sp, #0] + 81e6e: 4693 mov fp, r2 + 81e70: 9304 str r3, [sp, #16] + 81e72: 9001 str r0, [sp, #4] + 81e74: b118 cbz r0, 81e7e <_vfiprintf_r+0x1a> + 81e76: 6b83 ldr r3, [r0, #56] ; 0x38 + 81e78: 2b00 cmp r3, #0 + 81e7a: f000 80e3 beq.w 82044 <_vfiprintf_r+0x1e0> + 81e7e: 9b00 ldr r3, [sp, #0] + 81e80: 8999 ldrh r1, [r3, #12] + 81e82: b28a uxth r2, r1 + 81e84: 0490 lsls r0, r2, #18 + 81e86: d408 bmi.n 81e9a <_vfiprintf_r+0x36> + 81e88: 4618 mov r0, r3 + 81e8a: 6e5b ldr r3, [r3, #100] ; 0x64 + 81e8c: f441 5200 orr.w r2, r1, #8192 ; 0x2000 + 81e90: f423 5300 bic.w r3, r3, #8192 ; 0x2000 + 81e94: 8182 strh r2, [r0, #12] + 81e96: 6643 str r3, [r0, #100] ; 0x64 + 81e98: b292 uxth r2, r2 + 81e9a: 0711 lsls r1, r2, #28 + 81e9c: f140 80b2 bpl.w 82004 <_vfiprintf_r+0x1a0> + 81ea0: 9b00 ldr r3, [sp, #0] + 81ea2: 691b ldr r3, [r3, #16] + 81ea4: 2b00 cmp r3, #0 + 81ea6: f000 80ad beq.w 82004 <_vfiprintf_r+0x1a0> + 81eaa: f002 021a and.w r2, r2, #26 + 81eae: 2a0a cmp r2, #10 + 81eb0: f000 80b4 beq.w 8201c <_vfiprintf_r+0x1b8> + 81eb4: f10d 0a68 add.w sl, sp, #104 ; 0x68 + 81eb8: 4654 mov r4, sl + 81eba: 2300 movs r3, #0 + 81ebc: 9309 str r3, [sp, #36] ; 0x24 + 81ebe: 9302 str r3, [sp, #8] + 81ec0: 930f str r3, [sp, #60] ; 0x3c + 81ec2: 930e str r3, [sp, #56] ; 0x38 + 81ec4: f8cd a034 str.w sl, [sp, #52] ; 0x34 + 81ec8: f89b 3000 ldrb.w r3, [fp] + 81ecc: 2b00 cmp r3, #0 + 81ece: f000 84a3 beq.w 82818 <_vfiprintf_r+0x9b4> + 81ed2: 2b25 cmp r3, #37 ; 0x25 + 81ed4: f000 84a0 beq.w 82818 <_vfiprintf_r+0x9b4> + 81ed8: 465a mov r2, fp + 81eda: e001 b.n 81ee0 <_vfiprintf_r+0x7c> + 81edc: 2b25 cmp r3, #37 ; 0x25 + 81ede: d003 beq.n 81ee8 <_vfiprintf_r+0x84> + 81ee0: f812 3f01 ldrb.w r3, [r2, #1]! + 81ee4: 2b00 cmp r3, #0 + 81ee6: d1f9 bne.n 81edc <_vfiprintf_r+0x78> + 81ee8: ebcb 0602 rsb r6, fp, r2 + 81eec: 4615 mov r5, r2 + 81eee: b196 cbz r6, 81f16 <_vfiprintf_r+0xb2> + 81ef0: 9b0e ldr r3, [sp, #56] ; 0x38 + 81ef2: 9a0f ldr r2, [sp, #60] ; 0x3c + 81ef4: 3301 adds r3, #1 + 81ef6: 4432 add r2, r6 + 81ef8: 2b07 cmp r3, #7 + 81efa: f8c4 b000 str.w fp, [r4] + 81efe: 6066 str r6, [r4, #4] + 81f00: 920f str r2, [sp, #60] ; 0x3c + 81f02: 930e str r3, [sp, #56] ; 0x38 + 81f04: dd79 ble.n 81ffa <_vfiprintf_r+0x196> + 81f06: 2a00 cmp r2, #0 + 81f08: f040 84ad bne.w 82866 <_vfiprintf_r+0xa02> + 81f0c: 4654 mov r4, sl + 81f0e: 9b02 ldr r3, [sp, #8] + 81f10: 920e str r2, [sp, #56] ; 0x38 + 81f12: 4433 add r3, r6 + 81f14: 9302 str r3, [sp, #8] + 81f16: 782b ldrb r3, [r5, #0] + 81f18: 2b00 cmp r3, #0 + 81f1a: f000 835f beq.w 825dc <_vfiprintf_r+0x778> + 81f1e: f04f 0300 mov.w r3, #0 + 81f22: 2100 movs r1, #0 + 81f24: f04f 3cff mov.w ip, #4294967295 + 81f28: f88d 302f strb.w r3, [sp, #47] ; 0x2f + 81f2c: 1c68 adds r0, r5, #1 + 81f2e: 786b ldrb r3, [r5, #1] + 81f30: 4688 mov r8, r1 + 81f32: 460d mov r5, r1 + 81f34: 4666 mov r6, ip + 81f36: f100 0b01 add.w fp, r0, #1 + 81f3a: f1a3 0220 sub.w r2, r3, #32 + 81f3e: 2a58 cmp r2, #88 ; 0x58 + 81f40: f200 82aa bhi.w 82498 <_vfiprintf_r+0x634> + 81f44: e8df f012 tbh [pc, r2, lsl #1] + 81f48: 02a8029a .word 0x02a8029a + 81f4c: 02a202a8 .word 0x02a202a8 + 81f50: 02a802a8 .word 0x02a802a8 + 81f54: 02a802a8 .word 0x02a802a8 + 81f58: 02a802a8 .word 0x02a802a8 + 81f5c: 02600254 .word 0x02600254 + 81f60: 010d02a8 .word 0x010d02a8 + 81f64: 02a8026c .word 0x02a8026c + 81f68: 012f0129 .word 0x012f0129 + 81f6c: 012f012f .word 0x012f012f + 81f70: 012f012f .word 0x012f012f + 81f74: 012f012f .word 0x012f012f + 81f78: 012f012f .word 0x012f012f + 81f7c: 02a802a8 .word 0x02a802a8 + 81f80: 02a802a8 .word 0x02a802a8 + 81f84: 02a802a8 .word 0x02a802a8 + 81f88: 02a802a8 .word 0x02a802a8 + 81f8c: 02a802a8 .word 0x02a802a8 + 81f90: 02a8013d .word 0x02a8013d + 81f94: 02a802a8 .word 0x02a802a8 + 81f98: 02a802a8 .word 0x02a802a8 + 81f9c: 02a802a8 .word 0x02a802a8 + 81fa0: 02a802a8 .word 0x02a802a8 + 81fa4: 017402a8 .word 0x017402a8 + 81fa8: 02a802a8 .word 0x02a802a8 + 81fac: 02a802a8 .word 0x02a802a8 + 81fb0: 018b02a8 .word 0x018b02a8 + 81fb4: 02a802a8 .word 0x02a802a8 + 81fb8: 02a801a3 .word 0x02a801a3 + 81fbc: 02a802a8 .word 0x02a802a8 + 81fc0: 02a802a8 .word 0x02a802a8 + 81fc4: 02a802a8 .word 0x02a802a8 + 81fc8: 02a802a8 .word 0x02a802a8 + 81fcc: 01c702a8 .word 0x01c702a8 + 81fd0: 02a801da .word 0x02a801da + 81fd4: 02a802a8 .word 0x02a802a8 + 81fd8: 01da0123 .word 0x01da0123 + 81fdc: 02a802a8 .word 0x02a802a8 + 81fe0: 02a8024b .word 0x02a8024b + 81fe4: 01130288 .word 0x01130288 + 81fe8: 020701f4 .word 0x020701f4 + 81fec: 020d02a8 .word 0x020d02a8 + 81ff0: 008102a8 .word 0x008102a8 + 81ff4: 02a802a8 .word 0x02a802a8 + 81ff8: 0232 .short 0x0232 + 81ffa: 3408 adds r4, #8 + 81ffc: 9b02 ldr r3, [sp, #8] + 81ffe: 4433 add r3, r6 + 82000: 9302 str r3, [sp, #8] + 82002: e788 b.n 81f16 <_vfiprintf_r+0xb2> + 82004: 9801 ldr r0, [sp, #4] + 82006: 9900 ldr r1, [sp, #0] + 82008: f000 fd72 bl 82af0 <__swsetup_r> + 8200c: b9a8 cbnz r0, 8203a <_vfiprintf_r+0x1d6> + 8200e: 9b00 ldr r3, [sp, #0] + 82010: 899a ldrh r2, [r3, #12] + 82012: f002 021a and.w r2, r2, #26 + 82016: 2a0a cmp r2, #10 + 82018: f47f af4c bne.w 81eb4 <_vfiprintf_r+0x50> + 8201c: 9b00 ldr r3, [sp, #0] + 8201e: f9b3 300e ldrsh.w r3, [r3, #14] + 82022: 2b00 cmp r3, #0 + 82024: f6ff af46 blt.w 81eb4 <_vfiprintf_r+0x50> + 82028: 9801 ldr r0, [sp, #4] + 8202a: 9900 ldr r1, [sp, #0] + 8202c: 465a mov r2, fp + 8202e: 4623 mov r3, r4 + 82030: f000 fd20 bl 82a74 <__sbprintf> + 82034: b02b add sp, #172 ; 0xac + 82036: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 8203a: f04f 30ff mov.w r0, #4294967295 + 8203e: b02b add sp, #172 ; 0xac + 82040: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 82044: f000 fefe bl 82e44 <__sinit> + 82048: e719 b.n 81e7e <_vfiprintf_r+0x1a> + 8204a: f018 0f20 tst.w r8, #32 + 8204e: 9503 str r5, [sp, #12] + 82050: 46b4 mov ip, r6 + 82052: f000 810c beq.w 8226e <_vfiprintf_r+0x40a> + 82056: 9b04 ldr r3, [sp, #16] + 82058: 3307 adds r3, #7 + 8205a: f023 0307 bic.w r3, r3, #7 + 8205e: f103 0208 add.w r2, r3, #8 + 82062: e9d3 6700 ldrd r6, r7, [r3] + 82066: 9204 str r2, [sp, #16] + 82068: 2301 movs r3, #1 + 8206a: f04f 0200 mov.w r2, #0 + 8206e: 46e1 mov r9, ip + 82070: f88d 202f strb.w r2, [sp, #47] ; 0x2f + 82074: 2500 movs r5, #0 + 82076: f1bc 0f00 cmp.w ip, #0 + 8207a: bfa8 it ge + 8207c: f028 0880 bicge.w r8, r8, #128 ; 0x80 + 82080: ea56 0207 orrs.w r2, r6, r7 + 82084: f040 80c4 bne.w 82210 <_vfiprintf_r+0x3ac> + 82088: f1bc 0f00 cmp.w ip, #0 + 8208c: f000 8380 beq.w 82790 <_vfiprintf_r+0x92c> + 82090: 2b01 cmp r3, #1 + 82092: f000 80c5 beq.w 82220 <_vfiprintf_r+0x3bc> + 82096: 2b02 cmp r3, #2 + 82098: f000 8386 beq.w 827a8 <_vfiprintf_r+0x944> + 8209c: 4651 mov r1, sl + 8209e: 08f2 lsrs r2, r6, #3 + 820a0: ea42 7247 orr.w r2, r2, r7, lsl #29 + 820a4: 08f8 lsrs r0, r7, #3 + 820a6: f006 0307 and.w r3, r6, #7 + 820aa: 4607 mov r7, r0 + 820ac: 4616 mov r6, r2 + 820ae: 3330 adds r3, #48 ; 0x30 + 820b0: ea56 0207 orrs.w r2, r6, r7 + 820b4: f801 3d01 strb.w r3, [r1, #-1]! + 820b8: d1f1 bne.n 8209e <_vfiprintf_r+0x23a> + 820ba: f018 0f01 tst.w r8, #1 + 820be: 9107 str r1, [sp, #28] + 820c0: f040 83fa bne.w 828b8 <_vfiprintf_r+0xa54> + 820c4: ebc1 090a rsb r9, r1, sl + 820c8: 45e1 cmp r9, ip + 820ca: 464e mov r6, r9 + 820cc: bfb8 it lt + 820ce: 4666 movlt r6, ip + 820d0: b105 cbz r5, 820d4 <_vfiprintf_r+0x270> + 820d2: 3601 adds r6, #1 + 820d4: f018 0302 ands.w r3, r8, #2 + 820d8: 9305 str r3, [sp, #20] + 820da: bf18 it ne + 820dc: 3602 addne r6, #2 + 820de: f018 0384 ands.w r3, r8, #132 ; 0x84 + 820e2: 9306 str r3, [sp, #24] + 820e4: f040 81f9 bne.w 824da <_vfiprintf_r+0x676> + 820e8: 9b03 ldr r3, [sp, #12] + 820ea: 1b9d subs r5, r3, r6 + 820ec: 2d00 cmp r5, #0 + 820ee: f340 81f4 ble.w 824da <_vfiprintf_r+0x676> + 820f2: 2d10 cmp r5, #16 + 820f4: f340 848a ble.w 82a0c <_vfiprintf_r+0xba8> + 820f8: 4620 mov r0, r4 + 820fa: f8dd e038 ldr.w lr, [sp, #56] ; 0x38 + 820fe: 4664 mov r4, ip + 82100: 9a0f ldr r2, [sp, #60] ; 0x3c + 82102: 4fc4 ldr r7, [pc, #784] ; (82414 <_vfiprintf_r+0x5b0>) + 82104: 2310 movs r3, #16 + 82106: 4671 mov r1, lr + 82108: 4684 mov ip, r0 + 8210a: e007 b.n 8211c <_vfiprintf_r+0x2b8> + 8210c: f101 0e02 add.w lr, r1, #2 + 82110: 4601 mov r1, r0 + 82112: f10c 0c08 add.w ip, ip, #8 + 82116: 3d10 subs r5, #16 + 82118: 2d10 cmp r5, #16 + 8211a: dd13 ble.n 82144 <_vfiprintf_r+0x2e0> + 8211c: 1c48 adds r0, r1, #1 + 8211e: 3210 adds r2, #16 + 82120: 2807 cmp r0, #7 + 82122: 920f str r2, [sp, #60] ; 0x3c + 82124: f8cc 7000 str.w r7, [ip] + 82128: f8cc 3004 str.w r3, [ip, #4] + 8212c: 900e str r0, [sp, #56] ; 0x38 + 8212e: dded ble.n 8210c <_vfiprintf_r+0x2a8> + 82130: 2a00 cmp r2, #0 + 82132: f040 81c2 bne.w 824ba <_vfiprintf_r+0x656> + 82136: 3d10 subs r5, #16 + 82138: 2d10 cmp r5, #16 + 8213a: 4611 mov r1, r2 + 8213c: f04f 0e01 mov.w lr, #1 + 82140: 46d4 mov ip, sl + 82142: dceb bgt.n 8211c <_vfiprintf_r+0x2b8> + 82144: 4663 mov r3, ip + 82146: 4671 mov r1, lr + 82148: 46a4 mov ip, r4 + 8214a: 461c mov r4, r3 + 8214c: 442a add r2, r5 + 8214e: 2907 cmp r1, #7 + 82150: 920f str r2, [sp, #60] ; 0x3c + 82152: 6027 str r7, [r4, #0] + 82154: 6065 str r5, [r4, #4] + 82156: 910e str r1, [sp, #56] ; 0x38 + 82158: f300 8346 bgt.w 827e8 <_vfiprintf_r+0x984> + 8215c: 3408 adds r4, #8 + 8215e: 1c48 adds r0, r1, #1 + 82160: e1be b.n 824e0 <_vfiprintf_r+0x67c> + 82162: 4658 mov r0, fp + 82164: f048 0804 orr.w r8, r8, #4 + 82168: f89b 3000 ldrb.w r3, [fp] + 8216c: e6e3 b.n 81f36 <_vfiprintf_r+0xd2> + 8216e: f018 0320 ands.w r3, r8, #32 + 82172: 9503 str r5, [sp, #12] + 82174: 46b4 mov ip, r6 + 82176: d062 beq.n 8223e <_vfiprintf_r+0x3da> + 82178: 9b04 ldr r3, [sp, #16] + 8217a: 3307 adds r3, #7 + 8217c: f023 0307 bic.w r3, r3, #7 + 82180: f103 0208 add.w r2, r3, #8 + 82184: e9d3 6700 ldrd r6, r7, [r3] + 82188: 9204 str r2, [sp, #16] + 8218a: 2300 movs r3, #0 + 8218c: e76d b.n 8206a <_vfiprintf_r+0x206> + 8218e: f048 0840 orr.w r8, r8, #64 ; 0x40 + 82192: f89b 3000 ldrb.w r3, [fp] + 82196: 4658 mov r0, fp + 82198: e6cd b.n 81f36 <_vfiprintf_r+0xd2> + 8219a: f048 0880 orr.w r8, r8, #128 ; 0x80 + 8219e: f89b 3000 ldrb.w r3, [fp] + 821a2: 4658 mov r0, fp + 821a4: e6c7 b.n 81f36 <_vfiprintf_r+0xd2> + 821a6: f1a3 0230 sub.w r2, r3, #48 ; 0x30 + 821aa: 2500 movs r5, #0 + 821ac: f81b 3b01 ldrb.w r3, [fp], #1 + 821b0: eb05 0585 add.w r5, r5, r5, lsl #2 + 821b4: eb02 0545 add.w r5, r2, r5, lsl #1 + 821b8: f1a3 0230 sub.w r2, r3, #48 ; 0x30 + 821bc: 2a09 cmp r2, #9 + 821be: d9f5 bls.n 821ac <_vfiprintf_r+0x348> + 821c0: e6bb b.n 81f3a <_vfiprintf_r+0xd6> + 821c2: f048 0810 orr.w r8, r8, #16 + 821c6: f018 0f20 tst.w r8, #32 + 821ca: 9503 str r5, [sp, #12] + 821cc: 46b4 mov ip, r6 + 821ce: f88d 102f strb.w r1, [sp, #47] ; 0x2f + 821d2: f000 809b beq.w 8230c <_vfiprintf_r+0x4a8> + 821d6: 9904 ldr r1, [sp, #16] + 821d8: 3107 adds r1, #7 + 821da: f021 0107 bic.w r1, r1, #7 + 821de: e9d1 2300 ldrd r2, r3, [r1] + 821e2: 4616 mov r6, r2 + 821e4: 461f mov r7, r3 + 821e6: 3108 adds r1, #8 + 821e8: 9104 str r1, [sp, #16] + 821ea: 2a00 cmp r2, #0 + 821ec: f173 0300 sbcs.w r3, r3, #0 + 821f0: f2c0 83a4 blt.w 8293c <_vfiprintf_r+0xad8> + 821f4: f1bc 0f00 cmp.w ip, #0 + 821f8: bfa8 it ge + 821fa: f028 0880 bicge.w r8, r8, #128 ; 0x80 + 821fe: ea56 0207 orrs.w r2, r6, r7 + 82202: f89d 502f ldrb.w r5, [sp, #47] ; 0x2f + 82206: 46e1 mov r9, ip + 82208: f04f 0301 mov.w r3, #1 + 8220c: f43f af3c beq.w 82088 <_vfiprintf_r+0x224> + 82210: 2b01 cmp r3, #1 + 82212: f47f af40 bne.w 82096 <_vfiprintf_r+0x232> + 82216: 2f00 cmp r7, #0 + 82218: bf08 it eq + 8221a: 2e0a cmpeq r6, #10 + 8221c: f080 8332 bcs.w 82884 <_vfiprintf_r+0xa20> + 82220: ab2a add r3, sp, #168 ; 0xa8 + 82222: 3630 adds r6, #48 ; 0x30 + 82224: f803 6d41 strb.w r6, [r3, #-65]! + 82228: ebc3 090a rsb r9, r3, sl + 8222c: 9307 str r3, [sp, #28] + 8222e: e74b b.n 820c8 <_vfiprintf_r+0x264> + 82230: f048 0810 orr.w r8, r8, #16 + 82234: f018 0320 ands.w r3, r8, #32 + 82238: 9503 str r5, [sp, #12] + 8223a: 46b4 mov ip, r6 + 8223c: d19c bne.n 82178 <_vfiprintf_r+0x314> + 8223e: f018 0210 ands.w r2, r8, #16 + 82242: f040 82f7 bne.w 82834 <_vfiprintf_r+0x9d0> + 82246: f018 0340 ands.w r3, r8, #64 ; 0x40 + 8224a: f000 82f3 beq.w 82834 <_vfiprintf_r+0x9d0> + 8224e: 9904 ldr r1, [sp, #16] + 82250: 4613 mov r3, r2 + 82252: 460a mov r2, r1 + 82254: 3204 adds r2, #4 + 82256: 880e ldrh r6, [r1, #0] + 82258: 2700 movs r7, #0 + 8225a: 9204 str r2, [sp, #16] + 8225c: e705 b.n 8206a <_vfiprintf_r+0x206> + 8225e: f048 0810 orr.w r8, r8, #16 + 82262: f018 0f20 tst.w r8, #32 + 82266: 9503 str r5, [sp, #12] + 82268: 46b4 mov ip, r6 + 8226a: f47f aef4 bne.w 82056 <_vfiprintf_r+0x1f2> + 8226e: 9a04 ldr r2, [sp, #16] + 82270: f018 0f10 tst.w r8, #16 + 82274: 4613 mov r3, r2 + 82276: f040 82e4 bne.w 82842 <_vfiprintf_r+0x9de> + 8227a: f018 0f40 tst.w r8, #64 ; 0x40 + 8227e: f000 82e0 beq.w 82842 <_vfiprintf_r+0x9de> + 82282: 8816 ldrh r6, [r2, #0] + 82284: 3204 adds r2, #4 + 82286: 2700 movs r7, #0 + 82288: 2301 movs r3, #1 + 8228a: 9204 str r2, [sp, #16] + 8228c: e6ed b.n 8206a <_vfiprintf_r+0x206> + 8228e: 4a62 ldr r2, [pc, #392] ; (82418 <_vfiprintf_r+0x5b4>) + 82290: f018 0f20 tst.w r8, #32 + 82294: 9503 str r5, [sp, #12] + 82296: 46b4 mov ip, r6 + 82298: f88d 102f strb.w r1, [sp, #47] ; 0x2f + 8229c: 9209 str r2, [sp, #36] ; 0x24 + 8229e: f000 808f beq.w 823c0 <_vfiprintf_r+0x55c> + 822a2: 9a04 ldr r2, [sp, #16] + 822a4: 3207 adds r2, #7 + 822a6: f022 0207 bic.w r2, r2, #7 + 822aa: f102 0108 add.w r1, r2, #8 + 822ae: 9104 str r1, [sp, #16] + 822b0: e9d2 6700 ldrd r6, r7, [r2] + 822b4: f018 0f01 tst.w r8, #1 + 822b8: f000 828f beq.w 827da <_vfiprintf_r+0x976> + 822bc: ea56 0207 orrs.w r2, r6, r7 + 822c0: f000 828b beq.w 827da <_vfiprintf_r+0x976> + 822c4: 2230 movs r2, #48 ; 0x30 + 822c6: f88d 3031 strb.w r3, [sp, #49] ; 0x31 + 822ca: f048 0802 orr.w r8, r8, #2 + 822ce: f88d 2030 strb.w r2, [sp, #48] ; 0x30 + 822d2: 2302 movs r3, #2 + 822d4: e6c9 b.n 8206a <_vfiprintf_r+0x206> + 822d6: 9a04 ldr r2, [sp, #16] + 822d8: 2601 movs r6, #1 + 822da: 6813 ldr r3, [r2, #0] + 822dc: f04f 0100 mov.w r1, #0 + 822e0: f88d 3040 strb.w r3, [sp, #64] ; 0x40 + 822e4: 4613 mov r3, r2 + 822e6: 46b1 mov r9, r6 + 822e8: 3304 adds r3, #4 + 822ea: 9304 str r3, [sp, #16] + 822ec: ab10 add r3, sp, #64 ; 0x40 + 822ee: 9503 str r5, [sp, #12] + 822f0: f88d 102f strb.w r1, [sp, #47] ; 0x2f + 822f4: 9307 str r3, [sp, #28] + 822f6: f04f 0c00 mov.w ip, #0 + 822fa: e6eb b.n 820d4 <_vfiprintf_r+0x270> + 822fc: f018 0f20 tst.w r8, #32 + 82300: 9503 str r5, [sp, #12] + 82302: 46b4 mov ip, r6 + 82304: f88d 102f strb.w r1, [sp, #47] ; 0x2f + 82308: f47f af65 bne.w 821d6 <_vfiprintf_r+0x372> + 8230c: 9a04 ldr r2, [sp, #16] + 8230e: f018 0f10 tst.w r8, #16 + 82312: 4613 mov r3, r2 + 82314: f040 82a0 bne.w 82858 <_vfiprintf_r+0x9f4> + 82318: f018 0f40 tst.w r8, #64 ; 0x40 + 8231c: f000 829c beq.w 82858 <_vfiprintf_r+0x9f4> + 82320: f9b2 6000 ldrsh.w r6, [r2] + 82324: 3304 adds r3, #4 + 82326: 17f7 asrs r7, r6, #31 + 82328: 9304 str r3, [sp, #16] + 8232a: 4632 mov r2, r6 + 8232c: 463b mov r3, r7 + 8232e: e75c b.n 821ea <_vfiprintf_r+0x386> + 82330: 9904 ldr r1, [sp, #16] + 82332: 2378 movs r3, #120 ; 0x78 + 82334: f88d 3031 strb.w r3, [sp, #49] ; 0x31 + 82338: 4b38 ldr r3, [pc, #224] ; (8241c <_vfiprintf_r+0x5b8>) + 8233a: 46b4 mov ip, r6 + 8233c: 2230 movs r2, #48 ; 0x30 + 8233e: 680e ldr r6, [r1, #0] + 82340: 3104 adds r1, #4 + 82342: 9309 str r3, [sp, #36] ; 0x24 + 82344: 9503 str r5, [sp, #12] + 82346: f048 0802 orr.w r8, r8, #2 + 8234a: 9104 str r1, [sp, #16] + 8234c: 2700 movs r7, #0 + 8234e: f88d 2030 strb.w r2, [sp, #48] ; 0x30 + 82352: 2302 movs r3, #2 + 82354: e689 b.n 8206a <_vfiprintf_r+0x206> + 82356: f048 0820 orr.w r8, r8, #32 + 8235a: f89b 3000 ldrb.w r3, [fp] + 8235e: 4658 mov r0, fp + 82360: e5e9 b.n 81f36 <_vfiprintf_r+0xd2> + 82362: f04f 0100 mov.w r1, #0 + 82366: 9a04 ldr r2, [sp, #16] + 82368: 9503 str r5, [sp, #12] + 8236a: 6813 ldr r3, [r2, #0] + 8236c: 46b4 mov ip, r6 + 8236e: 9307 str r3, [sp, #28] + 82370: f88d 102f strb.w r1, [sp, #47] ; 0x2f + 82374: 1d15 adds r5, r2, #4 + 82376: 2b00 cmp r3, #0 + 82378: f000 834e beq.w 82a18 <_vfiprintf_r+0xbb4> + 8237c: 2e00 cmp r6, #0 + 8237e: f2c0 8329 blt.w 829d4 <_vfiprintf_r+0xb70> + 82382: 9e07 ldr r6, [sp, #28] + 82384: 4662 mov r2, ip + 82386: 4630 mov r0, r6 + 82388: 2100 movs r1, #0 + 8238a: f8cd c010 str.w ip, [sp, #16] + 8238e: f001 fbc9 bl 83b24 + 82392: f8dd c010 ldr.w ip, [sp, #16] + 82396: 2800 cmp r0, #0 + 82398: f000 834e beq.w 82a38 <_vfiprintf_r+0xbd4> + 8239c: 9504 str r5, [sp, #16] + 8239e: ebc6 0900 rsb r9, r6, r0 + 823a2: f89d 502f ldrb.w r5, [sp, #47] ; 0x2f + 823a6: f04f 0c00 mov.w ip, #0 + 823aa: e68d b.n 820c8 <_vfiprintf_r+0x264> + 823ac: 4a1b ldr r2, [pc, #108] ; (8241c <_vfiprintf_r+0x5b8>) + 823ae: f018 0f20 tst.w r8, #32 + 823b2: 9503 str r5, [sp, #12] + 823b4: 46b4 mov ip, r6 + 823b6: 9209 str r2, [sp, #36] ; 0x24 + 823b8: f88d 102f strb.w r1, [sp, #47] ; 0x2f + 823bc: f47f af71 bne.w 822a2 <_vfiprintf_r+0x43e> + 823c0: 9904 ldr r1, [sp, #16] + 823c2: f018 0f10 tst.w r8, #16 + 823c6: 460a mov r2, r1 + 823c8: f040 8241 bne.w 8284e <_vfiprintf_r+0x9ea> + 823cc: f018 0f40 tst.w r8, #64 ; 0x40 + 823d0: f000 823d beq.w 8284e <_vfiprintf_r+0x9ea> + 823d4: 3204 adds r2, #4 + 823d6: 880e ldrh r6, [r1, #0] + 823d8: 2700 movs r7, #0 + 823da: 9204 str r2, [sp, #16] + 823dc: e76a b.n 822b4 <_vfiprintf_r+0x450> + 823de: f89b 3000 ldrb.w r3, [fp] + 823e2: 2b6c cmp r3, #108 ; 0x6c + 823e4: f000 82e9 beq.w 829ba <_vfiprintf_r+0xb56> + 823e8: f048 0810 orr.w r8, r8, #16 + 823ec: 4658 mov r0, fp + 823ee: e5a2 b.n 81f36 <_vfiprintf_r+0xd2> + 823f0: 9a04 ldr r2, [sp, #16] + 823f2: 4613 mov r3, r2 + 823f4: 6815 ldr r5, [r2, #0] + 823f6: 3304 adds r3, #4 + 823f8: 2d00 cmp r5, #0 + 823fa: f2c0 82e6 blt.w 829ca <_vfiprintf_r+0xb66> + 823fe: 9304 str r3, [sp, #16] + 82400: f89b 3000 ldrb.w r3, [fp] + 82404: 4658 mov r0, fp + 82406: e596 b.n 81f36 <_vfiprintf_r+0xd2> + 82408: f89b 3000 ldrb.w r3, [fp] + 8240c: 4658 mov r0, fp + 8240e: 212b movs r1, #43 ; 0x2b + 82410: e591 b.n 81f36 <_vfiprintf_r+0xd2> + 82412: bf00 nop + 82414: 00084cec .word 0x00084cec + 82418: 00084cbc .word 0x00084cbc + 8241c: 00084cd0 .word 0x00084cd0 + 82420: f89b 3000 ldrb.w r3, [fp] + 82424: f10b 0001 add.w r0, fp, #1 + 82428: 2b2a cmp r3, #42 ; 0x2a + 8242a: f000 830f beq.w 82a4c <_vfiprintf_r+0xbe8> + 8242e: f1a3 0230 sub.w r2, r3, #48 ; 0x30 + 82432: 2a09 cmp r2, #9 + 82434: 4683 mov fp, r0 + 82436: f04f 0600 mov.w r6, #0 + 8243a: f63f ad7e bhi.w 81f3a <_vfiprintf_r+0xd6> + 8243e: f81b 3b01 ldrb.w r3, [fp], #1 + 82442: eb06 0686 add.w r6, r6, r6, lsl #2 + 82446: eb02 0646 add.w r6, r2, r6, lsl #1 + 8244a: f1a3 0230 sub.w r2, r3, #48 ; 0x30 + 8244e: 2a09 cmp r2, #9 + 82450: d9f5 bls.n 8243e <_vfiprintf_r+0x5da> + 82452: ea46 76e6 orr.w r6, r6, r6, asr #31 + 82456: e570 b.n 81f3a <_vfiprintf_r+0xd6> + 82458: f018 0f20 tst.w r8, #32 + 8245c: f88d 102f strb.w r1, [sp, #47] ; 0x2f + 82460: f000 8283 beq.w 8296a <_vfiprintf_r+0xb06> + 82464: 9a04 ldr r2, [sp, #16] + 82466: 4613 mov r3, r2 + 82468: 3304 adds r3, #4 + 8246a: 9304 str r3, [sp, #16] + 8246c: 9b02 ldr r3, [sp, #8] + 8246e: 6811 ldr r1, [r2, #0] + 82470: 17df asrs r7, r3, #31 + 82472: 461a mov r2, r3 + 82474: 463b mov r3, r7 + 82476: e9c1 2300 strd r2, r3, [r1] + 8247a: e525 b.n 81ec8 <_vfiprintf_r+0x64> + 8247c: 4658 mov r0, fp + 8247e: f89b 3000 ldrb.w r3, [fp] + 82482: 2900 cmp r1, #0 + 82484: f47f ad57 bne.w 81f36 <_vfiprintf_r+0xd2> + 82488: 2120 movs r1, #32 + 8248a: e554 b.n 81f36 <_vfiprintf_r+0xd2> + 8248c: f048 0801 orr.w r8, r8, #1 + 82490: 4658 mov r0, fp + 82492: f89b 3000 ldrb.w r3, [fp] + 82496: e54e b.n 81f36 <_vfiprintf_r+0xd2> + 82498: 9503 str r5, [sp, #12] + 8249a: f88d 102f strb.w r1, [sp, #47] ; 0x2f + 8249e: 2b00 cmp r3, #0 + 824a0: f000 809c beq.w 825dc <_vfiprintf_r+0x778> + 824a4: f88d 3040 strb.w r3, [sp, #64] ; 0x40 + 824a8: f04f 0300 mov.w r3, #0 + 824ac: 2601 movs r6, #1 + 824ae: f88d 302f strb.w r3, [sp, #47] ; 0x2f + 824b2: ab10 add r3, sp, #64 ; 0x40 + 824b4: 46b1 mov r9, r6 + 824b6: 9307 str r3, [sp, #28] + 824b8: e71d b.n 822f6 <_vfiprintf_r+0x492> + 824ba: 9801 ldr r0, [sp, #4] + 824bc: 9900 ldr r1, [sp, #0] + 824be: aa0d add r2, sp, #52 ; 0x34 + 824c0: 9308 str r3, [sp, #32] + 824c2: f7ff fc93 bl 81dec <__sprint_r.part.0> + 824c6: 2800 cmp r0, #0 + 824c8: f040 808f bne.w 825ea <_vfiprintf_r+0x786> + 824cc: 990e ldr r1, [sp, #56] ; 0x38 + 824ce: 46d4 mov ip, sl + 824d0: 9a0f ldr r2, [sp, #60] ; 0x3c + 824d2: f101 0e01 add.w lr, r1, #1 + 824d6: 9b08 ldr r3, [sp, #32] + 824d8: e61d b.n 82116 <_vfiprintf_r+0x2b2> + 824da: 990e ldr r1, [sp, #56] ; 0x38 + 824dc: 9a0f ldr r2, [sp, #60] ; 0x3c + 824de: 1c48 adds r0, r1, #1 + 824e0: f89d 302f ldrb.w r3, [sp, #47] ; 0x2f + 824e4: b16b cbz r3, 82502 <_vfiprintf_r+0x69e> + 824e6: 3201 adds r2, #1 + 824e8: f10d 032f add.w r3, sp, #47 ; 0x2f + 824ec: 2101 movs r1, #1 + 824ee: 2807 cmp r0, #7 + 824f0: 920f str r2, [sp, #60] ; 0x3c + 824f2: 900e str r0, [sp, #56] ; 0x38 + 824f4: 6023 str r3, [r4, #0] + 824f6: 6061 str r1, [r4, #4] + 824f8: f300 8134 bgt.w 82764 <_vfiprintf_r+0x900> + 824fc: 4601 mov r1, r0 + 824fe: 3408 adds r4, #8 + 82500: 3001 adds r0, #1 + 82502: 9b05 ldr r3, [sp, #20] + 82504: b163 cbz r3, 82520 <_vfiprintf_r+0x6bc> + 82506: 3202 adds r2, #2 + 82508: a90c add r1, sp, #48 ; 0x30 + 8250a: 2302 movs r3, #2 + 8250c: 2807 cmp r0, #7 + 8250e: 920f str r2, [sp, #60] ; 0x3c + 82510: 900e str r0, [sp, #56] ; 0x38 + 82512: e884 000a stmia.w r4, {r1, r3} + 82516: f300 8134 bgt.w 82782 <_vfiprintf_r+0x91e> + 8251a: 4601 mov r1, r0 + 8251c: 3408 adds r4, #8 + 8251e: 3001 adds r0, #1 + 82520: 9b06 ldr r3, [sp, #24] + 82522: 2b80 cmp r3, #128 ; 0x80 + 82524: f000 80d4 beq.w 826d0 <_vfiprintf_r+0x86c> + 82528: ebc9 070c rsb r7, r9, ip + 8252c: 2f00 cmp r7, #0 + 8252e: dd2b ble.n 82588 <_vfiprintf_r+0x724> + 82530: 2f10 cmp r7, #16 + 82532: 4dab ldr r5, [pc, #684] ; (827e0 <_vfiprintf_r+0x97c>) + 82534: dd1f ble.n 82576 <_vfiprintf_r+0x712> + 82536: 46a6 mov lr, r4 + 82538: 2310 movs r3, #16 + 8253a: 9c01 ldr r4, [sp, #4] + 8253c: e007 b.n 8254e <_vfiprintf_r+0x6ea> + 8253e: f101 0c02 add.w ip, r1, #2 + 82542: 4601 mov r1, r0 + 82544: f10e 0e08 add.w lr, lr, #8 + 82548: 3f10 subs r7, #16 + 8254a: 2f10 cmp r7, #16 + 8254c: dd11 ble.n 82572 <_vfiprintf_r+0x70e> + 8254e: 1c48 adds r0, r1, #1 + 82550: 3210 adds r2, #16 + 82552: 2807 cmp r0, #7 + 82554: 920f str r2, [sp, #60] ; 0x3c + 82556: f8ce 5000 str.w r5, [lr] + 8255a: f8ce 3004 str.w r3, [lr, #4] + 8255e: 900e str r0, [sp, #56] ; 0x38 + 82560: dded ble.n 8253e <_vfiprintf_r+0x6da> + 82562: bb6a cbnz r2, 825c0 <_vfiprintf_r+0x75c> + 82564: 3f10 subs r7, #16 + 82566: 2f10 cmp r7, #16 + 82568: f04f 0c01 mov.w ip, #1 + 8256c: 4611 mov r1, r2 + 8256e: 46d6 mov lr, sl + 82570: dced bgt.n 8254e <_vfiprintf_r+0x6ea> + 82572: 4674 mov r4, lr + 82574: 4660 mov r0, ip + 82576: 443a add r2, r7 + 82578: 2807 cmp r0, #7 + 8257a: 920f str r2, [sp, #60] ; 0x3c + 8257c: e884 00a0 stmia.w r4, {r5, r7} + 82580: 900e str r0, [sp, #56] ; 0x38 + 82582: dc3b bgt.n 825fc <_vfiprintf_r+0x798> + 82584: 3408 adds r4, #8 + 82586: 3001 adds r0, #1 + 82588: eb02 0309 add.w r3, r2, r9 + 8258c: 9a07 ldr r2, [sp, #28] + 8258e: 2807 cmp r0, #7 + 82590: 930f str r3, [sp, #60] ; 0x3c + 82592: e884 0204 stmia.w r4, {r2, r9} + 82596: 900e str r0, [sp, #56] ; 0x38 + 82598: dd3d ble.n 82616 <_vfiprintf_r+0x7b2> + 8259a: 2b00 cmp r3, #0 + 8259c: f040 813f bne.w 8281e <_vfiprintf_r+0x9ba> + 825a0: f018 0f04 tst.w r8, #4 + 825a4: 930e str r3, [sp, #56] ; 0x38 + 825a6: f040 8130 bne.w 8280a <_vfiprintf_r+0x9a6> + 825aa: 9b02 ldr r3, [sp, #8] + 825ac: 9a03 ldr r2, [sp, #12] + 825ae: 4296 cmp r6, r2 + 825b0: bfac ite ge + 825b2: 199b addge r3, r3, r6 + 825b4: 189b addlt r3, r3, r2 + 825b6: 9302 str r3, [sp, #8] + 825b8: 2300 movs r3, #0 + 825ba: 930e str r3, [sp, #56] ; 0x38 + 825bc: 4654 mov r4, sl + 825be: e483 b.n 81ec8 <_vfiprintf_r+0x64> + 825c0: 4620 mov r0, r4 + 825c2: 9900 ldr r1, [sp, #0] + 825c4: aa0d add r2, sp, #52 ; 0x34 + 825c6: 9305 str r3, [sp, #20] + 825c8: f7ff fc10 bl 81dec <__sprint_r.part.0> + 825cc: b968 cbnz r0, 825ea <_vfiprintf_r+0x786> + 825ce: 990e ldr r1, [sp, #56] ; 0x38 + 825d0: 46d6 mov lr, sl + 825d2: 9a0f ldr r2, [sp, #60] ; 0x3c + 825d4: f101 0c01 add.w ip, r1, #1 + 825d8: 9b05 ldr r3, [sp, #20] + 825da: e7b5 b.n 82548 <_vfiprintf_r+0x6e4> + 825dc: 9b0f ldr r3, [sp, #60] ; 0x3c + 825de: b123 cbz r3, 825ea <_vfiprintf_r+0x786> + 825e0: 9801 ldr r0, [sp, #4] + 825e2: 9900 ldr r1, [sp, #0] + 825e4: aa0d add r2, sp, #52 ; 0x34 + 825e6: f7ff fc01 bl 81dec <__sprint_r.part.0> + 825ea: 9b00 ldr r3, [sp, #0] + 825ec: 899b ldrh r3, [r3, #12] + 825ee: 065b lsls r3, r3, #25 + 825f0: f53f ad23 bmi.w 8203a <_vfiprintf_r+0x1d6> + 825f4: 9802 ldr r0, [sp, #8] + 825f6: b02b add sp, #172 ; 0xac + 825f8: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 825fc: 2a00 cmp r2, #0 + 825fe: f040 8190 bne.w 82922 <_vfiprintf_r+0xabe> + 82602: 464b mov r3, r9 + 82604: 4654 mov r4, sl + 82606: 9907 ldr r1, [sp, #28] + 82608: 2201 movs r2, #1 + 8260a: f8cd 906c str.w r9, [sp, #108] ; 0x6c + 8260e: f8cd 903c str.w r9, [sp, #60] ; 0x3c + 82612: 911a str r1, [sp, #104] ; 0x68 + 82614: 920e str r2, [sp, #56] ; 0x38 + 82616: f104 0208 add.w r2, r4, #8 + 8261a: f018 0f04 tst.w r8, #4 + 8261e: d039 beq.n 82694 <_vfiprintf_r+0x830> + 82620: 9903 ldr r1, [sp, #12] + 82622: 1b8d subs r5, r1, r6 + 82624: 2d00 cmp r5, #0 + 82626: dd35 ble.n 82694 <_vfiprintf_r+0x830> + 82628: 2d10 cmp r5, #16 + 8262a: f340 8200 ble.w 82a2e <_vfiprintf_r+0xbca> + 8262e: 980e ldr r0, [sp, #56] ; 0x38 + 82630: 4f6c ldr r7, [pc, #432] ; (827e4 <_vfiprintf_r+0x980>) + 82632: 2410 movs r4, #16 + 82634: f8dd 8004 ldr.w r8, [sp, #4] + 82638: f8dd 9000 ldr.w r9, [sp] + 8263c: e006 b.n 8264c <_vfiprintf_r+0x7e8> + 8263e: f100 0e02 add.w lr, r0, #2 + 82642: 4608 mov r0, r1 + 82644: 3208 adds r2, #8 + 82646: 3d10 subs r5, #16 + 82648: 2d10 cmp r5, #16 + 8264a: dd10 ble.n 8266e <_vfiprintf_r+0x80a> + 8264c: 1c41 adds r1, r0, #1 + 8264e: 3310 adds r3, #16 + 82650: 2907 cmp r1, #7 + 82652: 930f str r3, [sp, #60] ; 0x3c + 82654: 6017 str r7, [r2, #0] + 82656: 6054 str r4, [r2, #4] + 82658: 910e str r1, [sp, #56] ; 0x38 + 8265a: ddf0 ble.n 8263e <_vfiprintf_r+0x7da> + 8265c: 2b00 cmp r3, #0 + 8265e: d12a bne.n 826b6 <_vfiprintf_r+0x852> + 82660: 3d10 subs r5, #16 + 82662: 2d10 cmp r5, #16 + 82664: f04f 0e01 mov.w lr, #1 + 82668: 4618 mov r0, r3 + 8266a: 4652 mov r2, sl + 8266c: dcee bgt.n 8264c <_vfiprintf_r+0x7e8> + 8266e: 442b add r3, r5 + 82670: f1be 0f07 cmp.w lr, #7 + 82674: 930f str r3, [sp, #60] ; 0x3c + 82676: 6017 str r7, [r2, #0] + 82678: 6055 str r5, [r2, #4] + 8267a: f8cd e038 str.w lr, [sp, #56] ; 0x38 + 8267e: dd09 ble.n 82694 <_vfiprintf_r+0x830> + 82680: 2b00 cmp r3, #0 + 82682: d092 beq.n 825aa <_vfiprintf_r+0x746> + 82684: 9801 ldr r0, [sp, #4] + 82686: 9900 ldr r1, [sp, #0] + 82688: aa0d add r2, sp, #52 ; 0x34 + 8268a: f7ff fbaf bl 81dec <__sprint_r.part.0> + 8268e: 2800 cmp r0, #0 + 82690: d1ab bne.n 825ea <_vfiprintf_r+0x786> + 82692: 9b0f ldr r3, [sp, #60] ; 0x3c + 82694: 9a02 ldr r2, [sp, #8] + 82696: 9903 ldr r1, [sp, #12] + 82698: 428e cmp r6, r1 + 8269a: bfac ite ge + 8269c: 1992 addge r2, r2, r6 + 8269e: 1852 addlt r2, r2, r1 + 826a0: 9202 str r2, [sp, #8] + 826a2: 2b00 cmp r3, #0 + 826a4: d088 beq.n 825b8 <_vfiprintf_r+0x754> + 826a6: 9801 ldr r0, [sp, #4] + 826a8: 9900 ldr r1, [sp, #0] + 826aa: aa0d add r2, sp, #52 ; 0x34 + 826ac: f7ff fb9e bl 81dec <__sprint_r.part.0> + 826b0: 2800 cmp r0, #0 + 826b2: d081 beq.n 825b8 <_vfiprintf_r+0x754> + 826b4: e799 b.n 825ea <_vfiprintf_r+0x786> + 826b6: 4640 mov r0, r8 + 826b8: 4649 mov r1, r9 + 826ba: aa0d add r2, sp, #52 ; 0x34 + 826bc: f7ff fb96 bl 81dec <__sprint_r.part.0> + 826c0: 2800 cmp r0, #0 + 826c2: d192 bne.n 825ea <_vfiprintf_r+0x786> + 826c4: 980e ldr r0, [sp, #56] ; 0x38 + 826c6: 4652 mov r2, sl + 826c8: 9b0f ldr r3, [sp, #60] ; 0x3c + 826ca: f100 0e01 add.w lr, r0, #1 + 826ce: e7ba b.n 82646 <_vfiprintf_r+0x7e2> + 826d0: 9b03 ldr r3, [sp, #12] + 826d2: 1b9f subs r7, r3, r6 + 826d4: 2f00 cmp r7, #0 + 826d6: f77f af27 ble.w 82528 <_vfiprintf_r+0x6c4> + 826da: 2f10 cmp r7, #16 + 826dc: f340 81b3 ble.w 82a46 <_vfiprintf_r+0xbe2> + 826e0: 4620 mov r0, r4 + 826e2: 4d3f ldr r5, [pc, #252] ; (827e0 <_vfiprintf_r+0x97c>) + 826e4: 4664 mov r4, ip + 826e6: 2310 movs r3, #16 + 826e8: 4684 mov ip, r0 + 826ea: e007 b.n 826fc <_vfiprintf_r+0x898> + 826ec: f101 0e02 add.w lr, r1, #2 + 826f0: 4601 mov r1, r0 + 826f2: f10c 0c08 add.w ip, ip, #8 + 826f6: 3f10 subs r7, #16 + 826f8: 2f10 cmp r7, #16 + 826fa: dd11 ble.n 82720 <_vfiprintf_r+0x8bc> + 826fc: 1c48 adds r0, r1, #1 + 826fe: 3210 adds r2, #16 + 82700: 2807 cmp r0, #7 + 82702: 920f str r2, [sp, #60] ; 0x3c + 82704: f8cc 5000 str.w r5, [ip] + 82708: f8cc 3004 str.w r3, [ip, #4] + 8270c: 900e str r0, [sp, #56] ; 0x38 + 8270e: dded ble.n 826ec <_vfiprintf_r+0x888> + 82710: b9c2 cbnz r2, 82744 <_vfiprintf_r+0x8e0> + 82712: 3f10 subs r7, #16 + 82714: 2f10 cmp r7, #16 + 82716: f04f 0e01 mov.w lr, #1 + 8271a: 4611 mov r1, r2 + 8271c: 46d4 mov ip, sl + 8271e: dced bgt.n 826fc <_vfiprintf_r+0x898> + 82720: 4663 mov r3, ip + 82722: 46a4 mov ip, r4 + 82724: 461c mov r4, r3 + 82726: 443a add r2, r7 + 82728: f1be 0f07 cmp.w lr, #7 + 8272c: 920f str r2, [sp, #60] ; 0x3c + 8272e: e884 00a0 stmia.w r4, {r5, r7} + 82732: f8cd e038 str.w lr, [sp, #56] ; 0x38 + 82736: f300 80ee bgt.w 82916 <_vfiprintf_r+0xab2> + 8273a: 3408 adds r4, #8 + 8273c: f10e 0001 add.w r0, lr, #1 + 82740: 4671 mov r1, lr + 82742: e6f1 b.n 82528 <_vfiprintf_r+0x6c4> + 82744: 9801 ldr r0, [sp, #4] + 82746: 9900 ldr r1, [sp, #0] + 82748: aa0d add r2, sp, #52 ; 0x34 + 8274a: 9305 str r3, [sp, #20] + 8274c: f7ff fb4e bl 81dec <__sprint_r.part.0> + 82750: 2800 cmp r0, #0 + 82752: f47f af4a bne.w 825ea <_vfiprintf_r+0x786> + 82756: 990e ldr r1, [sp, #56] ; 0x38 + 82758: 46d4 mov ip, sl + 8275a: 9a0f ldr r2, [sp, #60] ; 0x3c + 8275c: f101 0e01 add.w lr, r1, #1 + 82760: 9b05 ldr r3, [sp, #20] + 82762: e7c8 b.n 826f6 <_vfiprintf_r+0x892> + 82764: 2a00 cmp r2, #0 + 82766: f040 80c5 bne.w 828f4 <_vfiprintf_r+0xa90> + 8276a: 9b05 ldr r3, [sp, #20] + 8276c: 2b00 cmp r3, #0 + 8276e: f000 8085 beq.w 8287c <_vfiprintf_r+0xa18> + 82772: aa0c add r2, sp, #48 ; 0x30 + 82774: 2302 movs r3, #2 + 82776: 921a str r2, [sp, #104] ; 0x68 + 82778: 4608 mov r0, r1 + 8277a: 931b str r3, [sp, #108] ; 0x6c + 8277c: 461a mov r2, r3 + 8277e: 4654 mov r4, sl + 82780: e6cb b.n 8251a <_vfiprintf_r+0x6b6> + 82782: 2a00 cmp r2, #0 + 82784: f040 80a5 bne.w 828d2 <_vfiprintf_r+0xa6e> + 82788: 2001 movs r0, #1 + 8278a: 4611 mov r1, r2 + 8278c: 4654 mov r4, sl + 8278e: e6c7 b.n 82520 <_vfiprintf_r+0x6bc> + 82790: bb03 cbnz r3, 827d4 <_vfiprintf_r+0x970> + 82792: f018 0f01 tst.w r8, #1 + 82796: d01d beq.n 827d4 <_vfiprintf_r+0x970> + 82798: ab2a add r3, sp, #168 ; 0xa8 + 8279a: 2230 movs r2, #48 ; 0x30 + 8279c: f803 2d41 strb.w r2, [r3, #-65]! + 827a0: ebc3 090a rsb r9, r3, sl + 827a4: 9307 str r3, [sp, #28] + 827a6: e48f b.n 820c8 <_vfiprintf_r+0x264> + 827a8: 46d1 mov r9, sl + 827aa: 9809 ldr r0, [sp, #36] ; 0x24 + 827ac: 0933 lsrs r3, r6, #4 + 827ae: ea43 7307 orr.w r3, r3, r7, lsl #28 + 827b2: 0939 lsrs r1, r7, #4 + 827b4: f006 020f and.w r2, r6, #15 + 827b8: 460f mov r7, r1 + 827ba: 461e mov r6, r3 + 827bc: 5c83 ldrb r3, [r0, r2] + 827be: f809 3d01 strb.w r3, [r9, #-1]! + 827c2: ea56 0307 orrs.w r3, r6, r7 + 827c6: d1f1 bne.n 827ac <_vfiprintf_r+0x948> + 827c8: 464b mov r3, r9 + 827ca: f8cd 901c str.w r9, [sp, #28] + 827ce: ebc3 090a rsb r9, r3, sl + 827d2: e479 b.n 820c8 <_vfiprintf_r+0x264> + 827d4: f8cd a01c str.w sl, [sp, #28] + 827d8: e476 b.n 820c8 <_vfiprintf_r+0x264> + 827da: 2302 movs r3, #2 + 827dc: e445 b.n 8206a <_vfiprintf_r+0x206> + 827de: bf00 nop + 827e0: 00084cac .word 0x00084cac + 827e4: 00084cec .word 0x00084cec + 827e8: 2a00 cmp r2, #0 + 827ea: f040 80d5 bne.w 82998 <_vfiprintf_r+0xb34> + 827ee: f89d 302f ldrb.w r3, [sp, #47] ; 0x2f + 827f2: 2b00 cmp r3, #0 + 827f4: f000 80ac beq.w 82950 <_vfiprintf_r+0xaec> + 827f8: 2301 movs r3, #1 + 827fa: f10d 012f add.w r1, sp, #47 ; 0x2f + 827fe: 4618 mov r0, r3 + 82800: 931b str r3, [sp, #108] ; 0x6c + 82802: 461a mov r2, r3 + 82804: 911a str r1, [sp, #104] ; 0x68 + 82806: 4654 mov r4, sl + 82808: e678 b.n 824fc <_vfiprintf_r+0x698> + 8280a: 9a03 ldr r2, [sp, #12] + 8280c: 1b95 subs r5, r2, r6 + 8280e: 2d00 cmp r5, #0 + 82810: 4652 mov r2, sl + 82812: f73f af09 bgt.w 82628 <_vfiprintf_r+0x7c4> + 82816: e6c8 b.n 825aa <_vfiprintf_r+0x746> + 82818: 465d mov r5, fp + 8281a: f7ff bb7c b.w 81f16 <_vfiprintf_r+0xb2> + 8281e: 9801 ldr r0, [sp, #4] + 82820: 9900 ldr r1, [sp, #0] + 82822: aa0d add r2, sp, #52 ; 0x34 + 82824: f7ff fae2 bl 81dec <__sprint_r.part.0> + 82828: 2800 cmp r0, #0 + 8282a: f47f aede bne.w 825ea <_vfiprintf_r+0x786> + 8282e: 4652 mov r2, sl + 82830: 9b0f ldr r3, [sp, #60] ; 0x3c + 82832: e6f2 b.n 8261a <_vfiprintf_r+0x7b6> + 82834: 9904 ldr r1, [sp, #16] + 82836: 2700 movs r7, #0 + 82838: 460a mov r2, r1 + 8283a: 3204 adds r2, #4 + 8283c: 680e ldr r6, [r1, #0] + 8283e: 9204 str r2, [sp, #16] + 82840: e413 b.n 8206a <_vfiprintf_r+0x206> + 82842: 3204 adds r2, #4 + 82844: 681e ldr r6, [r3, #0] + 82846: 2700 movs r7, #0 + 82848: 2301 movs r3, #1 + 8284a: 9204 str r2, [sp, #16] + 8284c: e40d b.n 8206a <_vfiprintf_r+0x206> + 8284e: 6816 ldr r6, [r2, #0] + 82850: 3204 adds r2, #4 + 82852: 9204 str r2, [sp, #16] + 82854: 2700 movs r7, #0 + 82856: e52d b.n 822b4 <_vfiprintf_r+0x450> + 82858: 681e ldr r6, [r3, #0] + 8285a: 3304 adds r3, #4 + 8285c: 17f7 asrs r7, r6, #31 + 8285e: 9304 str r3, [sp, #16] + 82860: 4632 mov r2, r6 + 82862: 463b mov r3, r7 + 82864: e4c1 b.n 821ea <_vfiprintf_r+0x386> + 82866: 9801 ldr r0, [sp, #4] + 82868: 9900 ldr r1, [sp, #0] + 8286a: aa0d add r2, sp, #52 ; 0x34 + 8286c: f7ff fabe bl 81dec <__sprint_r.part.0> + 82870: 2800 cmp r0, #0 + 82872: f47f aeba bne.w 825ea <_vfiprintf_r+0x786> + 82876: 4654 mov r4, sl + 82878: f7ff bbc0 b.w 81ffc <_vfiprintf_r+0x198> + 8287c: 4608 mov r0, r1 + 8287e: 4654 mov r4, sl + 82880: 4611 mov r1, r2 + 82882: e64d b.n 82520 <_vfiprintf_r+0x6bc> + 82884: 46d1 mov r9, sl + 82886: f8cd c014 str.w ip, [sp, #20] + 8288a: 4630 mov r0, r6 + 8288c: 4639 mov r1, r7 + 8288e: 220a movs r2, #10 + 82890: 2300 movs r3, #0 + 82892: f001 fdd1 bl 84438 <__aeabi_uldivmod> + 82896: 3230 adds r2, #48 ; 0x30 + 82898: 4630 mov r0, r6 + 8289a: 4639 mov r1, r7 + 8289c: f809 2d01 strb.w r2, [r9, #-1]! + 828a0: 2300 movs r3, #0 + 828a2: 220a movs r2, #10 + 828a4: f001 fdc8 bl 84438 <__aeabi_uldivmod> + 828a8: 4606 mov r6, r0 + 828aa: 460f mov r7, r1 + 828ac: ea56 0307 orrs.w r3, r6, r7 + 828b0: d1eb bne.n 8288a <_vfiprintf_r+0xa26> + 828b2: f8dd c014 ldr.w ip, [sp, #20] + 828b6: e787 b.n 827c8 <_vfiprintf_r+0x964> + 828b8: 2b30 cmp r3, #48 ; 0x30 + 828ba: 9b07 ldr r3, [sp, #28] + 828bc: d087 beq.n 827ce <_vfiprintf_r+0x96a> + 828be: 3b01 subs r3, #1 + 828c0: 461a mov r2, r3 + 828c2: 9307 str r3, [sp, #28] + 828c4: 2330 movs r3, #48 ; 0x30 + 828c6: ebc2 090a rsb r9, r2, sl + 828ca: f801 3c01 strb.w r3, [r1, #-1] + 828ce: f7ff bbfb b.w 820c8 <_vfiprintf_r+0x264> + 828d2: 9801 ldr r0, [sp, #4] + 828d4: 9900 ldr r1, [sp, #0] + 828d6: aa0d add r2, sp, #52 ; 0x34 + 828d8: f8cd c014 str.w ip, [sp, #20] + 828dc: f7ff fa86 bl 81dec <__sprint_r.part.0> + 828e0: 2800 cmp r0, #0 + 828e2: f47f ae82 bne.w 825ea <_vfiprintf_r+0x786> + 828e6: 990e ldr r1, [sp, #56] ; 0x38 + 828e8: 4654 mov r4, sl + 828ea: 9a0f ldr r2, [sp, #60] ; 0x3c + 828ec: 1c48 adds r0, r1, #1 + 828ee: f8dd c014 ldr.w ip, [sp, #20] + 828f2: e615 b.n 82520 <_vfiprintf_r+0x6bc> + 828f4: 9801 ldr r0, [sp, #4] + 828f6: 9900 ldr r1, [sp, #0] + 828f8: aa0d add r2, sp, #52 ; 0x34 + 828fa: f8cd c020 str.w ip, [sp, #32] + 828fe: f7ff fa75 bl 81dec <__sprint_r.part.0> + 82902: 2800 cmp r0, #0 + 82904: f47f ae71 bne.w 825ea <_vfiprintf_r+0x786> + 82908: 990e ldr r1, [sp, #56] ; 0x38 + 8290a: 4654 mov r4, sl + 8290c: 9a0f ldr r2, [sp, #60] ; 0x3c + 8290e: 1c48 adds r0, r1, #1 + 82910: f8dd c020 ldr.w ip, [sp, #32] + 82914: e5f5 b.n 82502 <_vfiprintf_r+0x69e> + 82916: 2a00 cmp r2, #0 + 82918: d167 bne.n 829ea <_vfiprintf_r+0xb86> + 8291a: 2001 movs r0, #1 + 8291c: 4611 mov r1, r2 + 8291e: 4654 mov r4, sl + 82920: e602 b.n 82528 <_vfiprintf_r+0x6c4> + 82922: 9801 ldr r0, [sp, #4] + 82924: 9900 ldr r1, [sp, #0] + 82926: aa0d add r2, sp, #52 ; 0x34 + 82928: f7ff fa60 bl 81dec <__sprint_r.part.0> + 8292c: 2800 cmp r0, #0 + 8292e: f47f ae5c bne.w 825ea <_vfiprintf_r+0x786> + 82932: 980e ldr r0, [sp, #56] ; 0x38 + 82934: 4654 mov r4, sl + 82936: 9a0f ldr r2, [sp, #60] ; 0x3c + 82938: 3001 adds r0, #1 + 8293a: e625 b.n 82588 <_vfiprintf_r+0x724> + 8293c: 252d movs r5, #45 ; 0x2d + 8293e: 4276 negs r6, r6 + 82940: eb67 0747 sbc.w r7, r7, r7, lsl #1 + 82944: f88d 502f strb.w r5, [sp, #47] ; 0x2f + 82948: 46e1 mov r9, ip + 8294a: 2301 movs r3, #1 + 8294c: f7ff bb93 b.w 82076 <_vfiprintf_r+0x212> + 82950: 9b05 ldr r3, [sp, #20] + 82952: 4611 mov r1, r2 + 82954: 2001 movs r0, #1 + 82956: 4654 mov r4, sl + 82958: 2b00 cmp r3, #0 + 8295a: f43f ade5 beq.w 82528 <_vfiprintf_r+0x6c4> + 8295e: aa0c add r2, sp, #48 ; 0x30 + 82960: 2302 movs r3, #2 + 82962: e88a 000c stmia.w sl, {r2, r3} + 82966: 461a mov r2, r3 + 82968: e5d7 b.n 8251a <_vfiprintf_r+0x6b6> + 8296a: f018 0f10 tst.w r8, #16 + 8296e: d10b bne.n 82988 <_vfiprintf_r+0xb24> + 82970: f018 0f40 tst.w r8, #64 ; 0x40 + 82974: d008 beq.n 82988 <_vfiprintf_r+0xb24> + 82976: 9a04 ldr r2, [sp, #16] + 82978: 6813 ldr r3, [r2, #0] + 8297a: 3204 adds r2, #4 + 8297c: 9204 str r2, [sp, #16] + 8297e: f8bd 2008 ldrh.w r2, [sp, #8] + 82982: 801a strh r2, [r3, #0] + 82984: f7ff baa0 b.w 81ec8 <_vfiprintf_r+0x64> + 82988: 9a04 ldr r2, [sp, #16] + 8298a: 6813 ldr r3, [r2, #0] + 8298c: 3204 adds r2, #4 + 8298e: 9204 str r2, [sp, #16] + 82990: 9a02 ldr r2, [sp, #8] + 82992: 601a str r2, [r3, #0] + 82994: f7ff ba98 b.w 81ec8 <_vfiprintf_r+0x64> + 82998: 9801 ldr r0, [sp, #4] + 8299a: 9900 ldr r1, [sp, #0] + 8299c: aa0d add r2, sp, #52 ; 0x34 + 8299e: f8cd c020 str.w ip, [sp, #32] + 829a2: f7ff fa23 bl 81dec <__sprint_r.part.0> + 829a6: 2800 cmp r0, #0 + 829a8: f47f ae1f bne.w 825ea <_vfiprintf_r+0x786> + 829ac: 990e ldr r1, [sp, #56] ; 0x38 + 829ae: 4654 mov r4, sl + 829b0: 9a0f ldr r2, [sp, #60] ; 0x3c + 829b2: 1c48 adds r0, r1, #1 + 829b4: f8dd c020 ldr.w ip, [sp, #32] + 829b8: e592 b.n 824e0 <_vfiprintf_r+0x67c> + 829ba: f048 0820 orr.w r8, r8, #32 + 829be: f10b 0001 add.w r0, fp, #1 + 829c2: f89b 3001 ldrb.w r3, [fp, #1] + 829c6: f7ff bab6 b.w 81f36 <_vfiprintf_r+0xd2> + 829ca: 426d negs r5, r5 + 829cc: 9304 str r3, [sp, #16] + 829ce: 4658 mov r0, fp + 829d0: f7ff bbc8 b.w 82164 <_vfiprintf_r+0x300> + 829d4: 9807 ldr r0, [sp, #28] + 829d6: 9504 str r5, [sp, #16] + 829d8: f7ff f9da bl 81d90 + 829dc: f89d 502f ldrb.w r5, [sp, #47] ; 0x2f + 829e0: 4681 mov r9, r0 + 829e2: f04f 0c00 mov.w ip, #0 + 829e6: f7ff bb6f b.w 820c8 <_vfiprintf_r+0x264> + 829ea: 9801 ldr r0, [sp, #4] + 829ec: 9900 ldr r1, [sp, #0] + 829ee: aa0d add r2, sp, #52 ; 0x34 + 829f0: f8cd c014 str.w ip, [sp, #20] + 829f4: f7ff f9fa bl 81dec <__sprint_r.part.0> + 829f8: 2800 cmp r0, #0 + 829fa: f47f adf6 bne.w 825ea <_vfiprintf_r+0x786> + 829fe: 990e ldr r1, [sp, #56] ; 0x38 + 82a00: 4654 mov r4, sl + 82a02: 9a0f ldr r2, [sp, #60] ; 0x3c + 82a04: 1c48 adds r0, r1, #1 + 82a06: f8dd c014 ldr.w ip, [sp, #20] + 82a0a: e58d b.n 82528 <_vfiprintf_r+0x6c4> + 82a0c: 990e ldr r1, [sp, #56] ; 0x38 + 82a0e: 9a0f ldr r2, [sp, #60] ; 0x3c + 82a10: 3101 adds r1, #1 + 82a12: 4f15 ldr r7, [pc, #84] ; (82a68 <_vfiprintf_r+0xc04>) + 82a14: f7ff bb9a b.w 8214c <_vfiprintf_r+0x2e8> + 82a18: 2e06 cmp r6, #6 + 82a1a: 4b14 ldr r3, [pc, #80] ; (82a6c <_vfiprintf_r+0xc08>) + 82a1c: bf28 it cs + 82a1e: f04f 0c06 movcs.w ip, #6 + 82a22: 46e1 mov r9, ip + 82a24: 9504 str r5, [sp, #16] + 82a26: ea2c 76ec bic.w r6, ip, ip, asr #31 + 82a2a: 9307 str r3, [sp, #28] + 82a2c: e463 b.n 822f6 <_vfiprintf_r+0x492> + 82a2e: 990e ldr r1, [sp, #56] ; 0x38 + 82a30: 4f0d ldr r7, [pc, #52] ; (82a68 <_vfiprintf_r+0xc04>) + 82a32: f101 0e01 add.w lr, r1, #1 + 82a36: e61a b.n 8266e <_vfiprintf_r+0x80a> + 82a38: 46e1 mov r9, ip + 82a3a: 9504 str r5, [sp, #16] + 82a3c: 4684 mov ip, r0 + 82a3e: f89d 502f ldrb.w r5, [sp, #47] ; 0x2f + 82a42: f7ff bb41 b.w 820c8 <_vfiprintf_r+0x264> + 82a46: 4686 mov lr, r0 + 82a48: 4d09 ldr r5, [pc, #36] ; (82a70 <_vfiprintf_r+0xc0c>) + 82a4a: e66c b.n 82726 <_vfiprintf_r+0x8c2> + 82a4c: 9a04 ldr r2, [sp, #16] + 82a4e: f89b 3001 ldrb.w r3, [fp, #1] + 82a52: 6816 ldr r6, [r2, #0] + 82a54: 3204 adds r2, #4 + 82a56: 2e00 cmp r6, #0 + 82a58: 9204 str r2, [sp, #16] + 82a5a: f6bf aa6c bge.w 81f36 <_vfiprintf_r+0xd2> + 82a5e: f04f 36ff mov.w r6, #4294967295 + 82a62: f7ff ba68 b.w 81f36 <_vfiprintf_r+0xd2> + 82a66: bf00 nop + 82a68: 00084cec .word 0x00084cec + 82a6c: 00084ce4 .word 0x00084ce4 + 82a70: 00084cac .word 0x00084cac + +00082a74 <__sbprintf>: + 82a74: e92d 45f0 stmdb sp!, {r4, r5, r6, r7, r8, sl, lr} + 82a78: 4688 mov r8, r1 + 82a7a: 6e4f ldr r7, [r1, #100] ; 0x64 + 82a7c: f2ad 4d6c subw sp, sp, #1132 ; 0x46c + 82a80: 9719 str r7, [sp, #100] ; 0x64 + 82a82: f8d8 701c ldr.w r7, [r8, #28] + 82a86: f8b1 e00c ldrh.w lr, [r1, #12] + 82a8a: f8b1 a00e ldrh.w sl, [r1, #14] + 82a8e: 9707 str r7, [sp, #28] + 82a90: f8d8 7024 ldr.w r7, [r8, #36] ; 0x24 + 82a94: ac1a add r4, sp, #104 ; 0x68 + 82a96: f44f 6580 mov.w r5, #1024 ; 0x400 + 82a9a: f02e 0e02 bic.w lr, lr, #2 + 82a9e: 2600 movs r6, #0 + 82aa0: 4669 mov r1, sp + 82aa2: 9400 str r4, [sp, #0] + 82aa4: 9404 str r4, [sp, #16] + 82aa6: 9502 str r5, [sp, #8] + 82aa8: 9505 str r5, [sp, #20] + 82aaa: f8ad e00c strh.w lr, [sp, #12] + 82aae: f8ad a00e strh.w sl, [sp, #14] + 82ab2: 9709 str r7, [sp, #36] ; 0x24 + 82ab4: 9606 str r6, [sp, #24] + 82ab6: 4605 mov r5, r0 + 82ab8: f7ff f9d4 bl 81e64 <_vfiprintf_r> + 82abc: 1e04 subs r4, r0, #0 + 82abe: db07 blt.n 82ad0 <__sbprintf+0x5c> + 82ac0: 4628 mov r0, r5 + 82ac2: 4669 mov r1, sp + 82ac4: f000 f92a bl 82d1c <_fflush_r> + 82ac8: 42b0 cmp r0, r6 + 82aca: bf18 it ne + 82acc: f04f 34ff movne.w r4, #4294967295 + 82ad0: f8bd 300c ldrh.w r3, [sp, #12] + 82ad4: 065b lsls r3, r3, #25 + 82ad6: d505 bpl.n 82ae4 <__sbprintf+0x70> + 82ad8: f8b8 300c ldrh.w r3, [r8, #12] + 82adc: f043 0340 orr.w r3, r3, #64 ; 0x40 + 82ae0: f8a8 300c strh.w r3, [r8, #12] + 82ae4: 4620 mov r0, r4 + 82ae6: f20d 4d6c addw sp, sp, #1132 ; 0x46c + 82aea: e8bd 85f0 ldmia.w sp!, {r4, r5, r6, r7, r8, sl, pc} + 82aee: bf00 nop + +00082af0 <__swsetup_r>: + 82af0: b538 push {r3, r4, r5, lr} + 82af2: 4b2f ldr r3, [pc, #188] ; (82bb0 <__swsetup_r+0xc0>) + 82af4: 4605 mov r5, r0 + 82af6: 6818 ldr r0, [r3, #0] + 82af8: 460c mov r4, r1 + 82afa: b110 cbz r0, 82b02 <__swsetup_r+0x12> + 82afc: 6b83 ldr r3, [r0, #56] ; 0x38 + 82afe: 2b00 cmp r3, #0 + 82b00: d036 beq.n 82b70 <__swsetup_r+0x80> + 82b02: 89a2 ldrh r2, [r4, #12] + 82b04: b293 uxth r3, r2 + 82b06: 0718 lsls r0, r3, #28 + 82b08: d50c bpl.n 82b24 <__swsetup_r+0x34> + 82b0a: 6920 ldr r0, [r4, #16] + 82b0c: b1a8 cbz r0, 82b3a <__swsetup_r+0x4a> + 82b0e: f013 0201 ands.w r2, r3, #1 + 82b12: d01e beq.n 82b52 <__swsetup_r+0x62> + 82b14: 6963 ldr r3, [r4, #20] + 82b16: 2200 movs r2, #0 + 82b18: 425b negs r3, r3 + 82b1a: 61a3 str r3, [r4, #24] + 82b1c: 60a2 str r2, [r4, #8] + 82b1e: b1f0 cbz r0, 82b5e <__swsetup_r+0x6e> + 82b20: 2000 movs r0, #0 + 82b22: bd38 pop {r3, r4, r5, pc} + 82b24: 06d9 lsls r1, r3, #27 + 82b26: d53a bpl.n 82b9e <__swsetup_r+0xae> + 82b28: 0758 lsls r0, r3, #29 + 82b2a: d424 bmi.n 82b76 <__swsetup_r+0x86> + 82b2c: 6920 ldr r0, [r4, #16] + 82b2e: f042 0308 orr.w r3, r2, #8 + 82b32: 81a3 strh r3, [r4, #12] + 82b34: b29b uxth r3, r3 + 82b36: 2800 cmp r0, #0 + 82b38: d1e9 bne.n 82b0e <__swsetup_r+0x1e> + 82b3a: f403 7220 and.w r2, r3, #640 ; 0x280 + 82b3e: f5b2 7f00 cmp.w r2, #512 ; 0x200 + 82b42: d0e4 beq.n 82b0e <__swsetup_r+0x1e> + 82b44: 4628 mov r0, r5 + 82b46: 4621 mov r1, r4 + 82b48: f000 fcee bl 83528 <__smakebuf_r> + 82b4c: 89a3 ldrh r3, [r4, #12] + 82b4e: 6920 ldr r0, [r4, #16] + 82b50: e7dd b.n 82b0e <__swsetup_r+0x1e> + 82b52: 0799 lsls r1, r3, #30 + 82b54: bf58 it pl + 82b56: 6962 ldrpl r2, [r4, #20] + 82b58: 60a2 str r2, [r4, #8] + 82b5a: 2800 cmp r0, #0 + 82b5c: d1e0 bne.n 82b20 <__swsetup_r+0x30> + 82b5e: 89a3 ldrh r3, [r4, #12] + 82b60: 061a lsls r2, r3, #24 + 82b62: d5de bpl.n 82b22 <__swsetup_r+0x32> + 82b64: f043 0340 orr.w r3, r3, #64 ; 0x40 + 82b68: 81a3 strh r3, [r4, #12] + 82b6a: f04f 30ff mov.w r0, #4294967295 + 82b6e: bd38 pop {r3, r4, r5, pc} + 82b70: f000 f968 bl 82e44 <__sinit> + 82b74: e7c5 b.n 82b02 <__swsetup_r+0x12> + 82b76: 6b21 ldr r1, [r4, #48] ; 0x30 + 82b78: b149 cbz r1, 82b8e <__swsetup_r+0x9e> + 82b7a: f104 0340 add.w r3, r4, #64 ; 0x40 + 82b7e: 4299 cmp r1, r3 + 82b80: d003 beq.n 82b8a <__swsetup_r+0x9a> + 82b82: 4628 mov r0, r5 + 82b84: f000 fa36 bl 82ff4 <_free_r> + 82b88: 89a2 ldrh r2, [r4, #12] + 82b8a: 2300 movs r3, #0 + 82b8c: 6323 str r3, [r4, #48] ; 0x30 + 82b8e: 6920 ldr r0, [r4, #16] + 82b90: f022 0224 bic.w r2, r2, #36 ; 0x24 + 82b94: 2300 movs r3, #0 + 82b96: b292 uxth r2, r2 + 82b98: e884 0009 stmia.w r4, {r0, r3} + 82b9c: e7c7 b.n 82b2e <__swsetup_r+0x3e> + 82b9e: f042 0240 orr.w r2, r2, #64 ; 0x40 + 82ba2: 2309 movs r3, #9 + 82ba4: 602b str r3, [r5, #0] + 82ba6: f04f 30ff mov.w r0, #4294967295 + 82baa: 81a2 strh r2, [r4, #12] + 82bac: bd38 pop {r3, r4, r5, pc} + 82bae: bf00 nop + 82bb0: 20070558 .word 0x20070558 + +00082bb4 : + 82bb4: 4b02 ldr r3, [pc, #8] ; (82bc0 ) + 82bb6: b113 cbz r3, 82bbe + 82bb8: 4802 ldr r0, [pc, #8] ; (82bc4 ) + 82bba: f000 b805 b.w 82bc8 + 82bbe: 4770 bx lr + 82bc0: 00000000 .word 0x00000000 + 82bc4: 00082e59 .word 0x00082e59 + +00082bc8 : + 82bc8: 4601 mov r1, r0 + 82bca: 2000 movs r0, #0 + 82bcc: 4602 mov r2, r0 + 82bce: 4603 mov r3, r0 + 82bd0: f001 bb3e b.w 84250 <__register_exitproc> + +00082bd4 <__sflush_r>: + 82bd4: 898b ldrh r3, [r1, #12] + 82bd6: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 82bda: b29a uxth r2, r3 + 82bdc: 460d mov r5, r1 + 82bde: 0711 lsls r1, r2, #28 + 82be0: 4680 mov r8, r0 + 82be2: d43c bmi.n 82c5e <__sflush_r+0x8a> + 82be4: 686a ldr r2, [r5, #4] + 82be6: f443 6300 orr.w r3, r3, #2048 ; 0x800 + 82bea: 2a00 cmp r2, #0 + 82bec: 81ab strh r3, [r5, #12] + 82bee: dd65 ble.n 82cbc <__sflush_r+0xe8> + 82bf0: 6aae ldr r6, [r5, #40] ; 0x28 + 82bf2: 2e00 cmp r6, #0 + 82bf4: d04b beq.n 82c8e <__sflush_r+0xba> + 82bf6: b29b uxth r3, r3 + 82bf8: f403 5280 and.w r2, r3, #4096 ; 0x1000 + 82bfc: 2100 movs r1, #0 + 82bfe: b292 uxth r2, r2 + 82c00: f8d8 4000 ldr.w r4, [r8] + 82c04: f8c8 1000 str.w r1, [r8] + 82c08: 2a00 cmp r2, #0 + 82c0a: d05b beq.n 82cc4 <__sflush_r+0xf0> + 82c0c: 6d2a ldr r2, [r5, #80] ; 0x50 + 82c0e: 075f lsls r7, r3, #29 + 82c10: d505 bpl.n 82c1e <__sflush_r+0x4a> + 82c12: 6869 ldr r1, [r5, #4] + 82c14: 6b2b ldr r3, [r5, #48] ; 0x30 + 82c16: 1a52 subs r2, r2, r1 + 82c18: b10b cbz r3, 82c1e <__sflush_r+0x4a> + 82c1a: 6beb ldr r3, [r5, #60] ; 0x3c + 82c1c: 1ad2 subs r2, r2, r3 + 82c1e: 4640 mov r0, r8 + 82c20: 69e9 ldr r1, [r5, #28] + 82c22: 2300 movs r3, #0 + 82c24: 47b0 blx r6 + 82c26: 1c46 adds r6, r0, #1 + 82c28: d056 beq.n 82cd8 <__sflush_r+0x104> + 82c2a: 89ab ldrh r3, [r5, #12] + 82c2c: 692a ldr r2, [r5, #16] + 82c2e: f423 6300 bic.w r3, r3, #2048 ; 0x800 + 82c32: b29b uxth r3, r3 + 82c34: 2100 movs r1, #0 + 82c36: 602a str r2, [r5, #0] + 82c38: 04da lsls r2, r3, #19 + 82c3a: 81ab strh r3, [r5, #12] + 82c3c: 6069 str r1, [r5, #4] + 82c3e: d43b bmi.n 82cb8 <__sflush_r+0xe4> + 82c40: 6b29 ldr r1, [r5, #48] ; 0x30 + 82c42: f8c8 4000 str.w r4, [r8] + 82c46: b311 cbz r1, 82c8e <__sflush_r+0xba> + 82c48: f105 0340 add.w r3, r5, #64 ; 0x40 + 82c4c: 4299 cmp r1, r3 + 82c4e: d002 beq.n 82c56 <__sflush_r+0x82> + 82c50: 4640 mov r0, r8 + 82c52: f000 f9cf bl 82ff4 <_free_r> + 82c56: 2000 movs r0, #0 + 82c58: 6328 str r0, [r5, #48] ; 0x30 + 82c5a: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 82c5e: 692e ldr r6, [r5, #16] + 82c60: b1ae cbz r6, 82c8e <__sflush_r+0xba> + 82c62: 0791 lsls r1, r2, #30 + 82c64: 682c ldr r4, [r5, #0] + 82c66: bf0c ite eq + 82c68: 696b ldreq r3, [r5, #20] + 82c6a: 2300 movne r3, #0 + 82c6c: 602e str r6, [r5, #0] + 82c6e: 1ba4 subs r4, r4, r6 + 82c70: 60ab str r3, [r5, #8] + 82c72: e00a b.n 82c8a <__sflush_r+0xb6> + 82c74: 4632 mov r2, r6 + 82c76: 4623 mov r3, r4 + 82c78: 6a6f ldr r7, [r5, #36] ; 0x24 + 82c7a: 4640 mov r0, r8 + 82c7c: 69e9 ldr r1, [r5, #28] + 82c7e: 47b8 blx r7 + 82c80: 2800 cmp r0, #0 + 82c82: eba4 0400 sub.w r4, r4, r0 + 82c86: 4406 add r6, r0 + 82c88: dd04 ble.n 82c94 <__sflush_r+0xc0> + 82c8a: 2c00 cmp r4, #0 + 82c8c: dcf2 bgt.n 82c74 <__sflush_r+0xa0> + 82c8e: 2000 movs r0, #0 + 82c90: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 82c94: 89ab ldrh r3, [r5, #12] + 82c96: f04f 30ff mov.w r0, #4294967295 + 82c9a: f043 0340 orr.w r3, r3, #64 ; 0x40 + 82c9e: 81ab strh r3, [r5, #12] + 82ca0: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 82ca4: 89ab ldrh r3, [r5, #12] + 82ca6: 692a ldr r2, [r5, #16] + 82ca8: f423 6300 bic.w r3, r3, #2048 ; 0x800 + 82cac: b29b uxth r3, r3 + 82cae: 81ab strh r3, [r5, #12] + 82cb0: 04db lsls r3, r3, #19 + 82cb2: 6069 str r1, [r5, #4] + 82cb4: 602a str r2, [r5, #0] + 82cb6: d5c3 bpl.n 82c40 <__sflush_r+0x6c> + 82cb8: 6528 str r0, [r5, #80] ; 0x50 + 82cba: e7c1 b.n 82c40 <__sflush_r+0x6c> + 82cbc: 6bea ldr r2, [r5, #60] ; 0x3c + 82cbe: 2a00 cmp r2, #0 + 82cc0: dc96 bgt.n 82bf0 <__sflush_r+0x1c> + 82cc2: e7e4 b.n 82c8e <__sflush_r+0xba> + 82cc4: 2301 movs r3, #1 + 82cc6: 4640 mov r0, r8 + 82cc8: 69e9 ldr r1, [r5, #28] + 82cca: 47b0 blx r6 + 82ccc: 1c43 adds r3, r0, #1 + 82cce: 4602 mov r2, r0 + 82cd0: d019 beq.n 82d06 <__sflush_r+0x132> + 82cd2: 89ab ldrh r3, [r5, #12] + 82cd4: 6aae ldr r6, [r5, #40] ; 0x28 + 82cd6: e79a b.n 82c0e <__sflush_r+0x3a> + 82cd8: f8d8 1000 ldr.w r1, [r8] + 82cdc: 2900 cmp r1, #0 + 82cde: d0e1 beq.n 82ca4 <__sflush_r+0xd0> + 82ce0: 291d cmp r1, #29 + 82ce2: d007 beq.n 82cf4 <__sflush_r+0x120> + 82ce4: 2916 cmp r1, #22 + 82ce6: d005 beq.n 82cf4 <__sflush_r+0x120> + 82ce8: 89ab ldrh r3, [r5, #12] + 82cea: f043 0340 orr.w r3, r3, #64 ; 0x40 + 82cee: 81ab strh r3, [r5, #12] + 82cf0: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 82cf4: 89ab ldrh r3, [r5, #12] + 82cf6: 6929 ldr r1, [r5, #16] + 82cf8: f423 6300 bic.w r3, r3, #2048 ; 0x800 + 82cfc: 2200 movs r2, #0 + 82cfe: 81ab strh r3, [r5, #12] + 82d00: e885 0006 stmia.w r5, {r1, r2} + 82d04: e79c b.n 82c40 <__sflush_r+0x6c> + 82d06: f8d8 3000 ldr.w r3, [r8] + 82d0a: 2b00 cmp r3, #0 + 82d0c: d0e1 beq.n 82cd2 <__sflush_r+0xfe> + 82d0e: 2b1d cmp r3, #29 + 82d10: d001 beq.n 82d16 <__sflush_r+0x142> + 82d12: 2b16 cmp r3, #22 + 82d14: d1be bne.n 82c94 <__sflush_r+0xc0> + 82d16: f8c8 4000 str.w r4, [r8] + 82d1a: e7b8 b.n 82c8e <__sflush_r+0xba> + +00082d1c <_fflush_r>: + 82d1c: b510 push {r4, lr} + 82d1e: 4604 mov r4, r0 + 82d20: b082 sub sp, #8 + 82d22: b108 cbz r0, 82d28 <_fflush_r+0xc> + 82d24: 6b83 ldr r3, [r0, #56] ; 0x38 + 82d26: b153 cbz r3, 82d3e <_fflush_r+0x22> + 82d28: f9b1 000c ldrsh.w r0, [r1, #12] + 82d2c: b908 cbnz r0, 82d32 <_fflush_r+0x16> + 82d2e: b002 add sp, #8 + 82d30: bd10 pop {r4, pc} + 82d32: 4620 mov r0, r4 + 82d34: b002 add sp, #8 + 82d36: e8bd 4010 ldmia.w sp!, {r4, lr} + 82d3a: f7ff bf4b b.w 82bd4 <__sflush_r> + 82d3e: 9101 str r1, [sp, #4] + 82d40: f000 f880 bl 82e44 <__sinit> + 82d44: 9901 ldr r1, [sp, #4] + 82d46: e7ef b.n 82d28 <_fflush_r+0xc> + +00082d48 <_cleanup_r>: + 82d48: 4901 ldr r1, [pc, #4] ; (82d50 <_cleanup_r+0x8>) + 82d4a: f000 bbbb b.w 834c4 <_fwalk_reent> + 82d4e: bf00 nop + 82d50: 00084319 .word 0x00084319 + +00082d54 <__sinit.part.1>: + 82d54: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 82d58: 4607 mov r7, r0 + 82d5a: 4835 ldr r0, [pc, #212] ; (82e30 <__sinit.part.1+0xdc>) + 82d5c: 687d ldr r5, [r7, #4] + 82d5e: 2400 movs r4, #0 + 82d60: f507 723b add.w r2, r7, #748 ; 0x2ec + 82d64: 2304 movs r3, #4 + 82d66: 2103 movs r1, #3 + 82d68: 63f8 str r0, [r7, #60] ; 0x3c + 82d6a: f8c7 12e4 str.w r1, [r7, #740] ; 0x2e4 + 82d6e: f8c7 22e8 str.w r2, [r7, #744] ; 0x2e8 + 82d72: f8c7 42e0 str.w r4, [r7, #736] ; 0x2e0 + 82d76: b083 sub sp, #12 + 82d78: 602c str r4, [r5, #0] + 82d7a: 606c str r4, [r5, #4] + 82d7c: 60ac str r4, [r5, #8] + 82d7e: 666c str r4, [r5, #100] ; 0x64 + 82d80: 81ec strh r4, [r5, #14] + 82d82: 612c str r4, [r5, #16] + 82d84: 616c str r4, [r5, #20] + 82d86: 61ac str r4, [r5, #24] + 82d88: 81ab strh r3, [r5, #12] + 82d8a: 4621 mov r1, r4 + 82d8c: f105 005c add.w r0, r5, #92 ; 0x5c + 82d90: 2208 movs r2, #8 + 82d92: f7fe fef3 bl 81b7c + 82d96: f8df b09c ldr.w fp, [pc, #156] ; 82e34 <__sinit.part.1+0xe0> + 82d9a: 68be ldr r6, [r7, #8] + 82d9c: f8df a098 ldr.w sl, [pc, #152] ; 82e38 <__sinit.part.1+0xe4> + 82da0: f8df 9098 ldr.w r9, [pc, #152] ; 82e3c <__sinit.part.1+0xe8> + 82da4: f8df 8098 ldr.w r8, [pc, #152] ; 82e40 <__sinit.part.1+0xec> + 82da8: 2301 movs r3, #1 + 82daa: 2209 movs r2, #9 + 82dac: f8c5 b020 str.w fp, [r5, #32] + 82db0: f8c5 a024 str.w sl, [r5, #36] ; 0x24 + 82db4: f8c5 9028 str.w r9, [r5, #40] ; 0x28 + 82db8: f8c5 802c str.w r8, [r5, #44] ; 0x2c + 82dbc: 61ed str r5, [r5, #28] + 82dbe: 4621 mov r1, r4 + 82dc0: 81f3 strh r3, [r6, #14] + 82dc2: 81b2 strh r2, [r6, #12] + 82dc4: f106 005c add.w r0, r6, #92 ; 0x5c + 82dc8: 6034 str r4, [r6, #0] + 82dca: 6074 str r4, [r6, #4] + 82dcc: 60b4 str r4, [r6, #8] + 82dce: 6674 str r4, [r6, #100] ; 0x64 + 82dd0: 6134 str r4, [r6, #16] + 82dd2: 6174 str r4, [r6, #20] + 82dd4: 61b4 str r4, [r6, #24] + 82dd6: 2208 movs r2, #8 + 82dd8: 9301 str r3, [sp, #4] + 82dda: f7fe fecf bl 81b7c + 82dde: 68fd ldr r5, [r7, #12] + 82de0: 2012 movs r0, #18 + 82de2: 2202 movs r2, #2 + 82de4: 61f6 str r6, [r6, #28] + 82de6: f8c6 b020 str.w fp, [r6, #32] + 82dea: f8c6 a024 str.w sl, [r6, #36] ; 0x24 + 82dee: f8c6 9028 str.w r9, [r6, #40] ; 0x28 + 82df2: f8c6 802c str.w r8, [r6, #44] ; 0x2c + 82df6: 4621 mov r1, r4 + 82df8: 81a8 strh r0, [r5, #12] + 82dfa: 81ea strh r2, [r5, #14] + 82dfc: 602c str r4, [r5, #0] + 82dfe: 606c str r4, [r5, #4] + 82e00: 60ac str r4, [r5, #8] + 82e02: 666c str r4, [r5, #100] ; 0x64 + 82e04: 612c str r4, [r5, #16] + 82e06: 616c str r4, [r5, #20] + 82e08: 61ac str r4, [r5, #24] + 82e0a: f105 005c add.w r0, r5, #92 ; 0x5c + 82e0e: 2208 movs r2, #8 + 82e10: f7fe feb4 bl 81b7c + 82e14: 9b01 ldr r3, [sp, #4] + 82e16: 61ed str r5, [r5, #28] + 82e18: f8c5 b020 str.w fp, [r5, #32] + 82e1c: f8c5 a024 str.w sl, [r5, #36] ; 0x24 + 82e20: f8c5 9028 str.w r9, [r5, #40] ; 0x28 + 82e24: f8c5 802c str.w r8, [r5, #44] ; 0x2c + 82e28: 63bb str r3, [r7, #56] ; 0x38 + 82e2a: b003 add sp, #12 + 82e2c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 82e30: 00082d49 .word 0x00082d49 + 82e34: 0008408d .word 0x0008408d + 82e38: 000840b1 .word 0x000840b1 + 82e3c: 000840e9 .word 0x000840e9 + 82e40: 00084109 .word 0x00084109 + +00082e44 <__sinit>: + 82e44: 6b83 ldr r3, [r0, #56] ; 0x38 + 82e46: b103 cbz r3, 82e4a <__sinit+0x6> + 82e48: 4770 bx lr + 82e4a: f7ff bf83 b.w 82d54 <__sinit.part.1> + 82e4e: bf00 nop + +00082e50 <__sfp_lock_acquire>: + 82e50: 4770 bx lr + 82e52: bf00 nop + +00082e54 <__sfp_lock_release>: + 82e54: 4770 bx lr + 82e56: bf00 nop + +00082e58 <__libc_fini_array>: + 82e58: b538 push {r3, r4, r5, lr} + 82e5a: 4b08 ldr r3, [pc, #32] ; (82e7c <__libc_fini_array+0x24>) + 82e5c: 4d08 ldr r5, [pc, #32] ; (82e80 <__libc_fini_array+0x28>) + 82e5e: 1aed subs r5, r5, r3 + 82e60: 10ac asrs r4, r5, #2 + 82e62: bf18 it ne + 82e64: 18ed addne r5, r5, r3 + 82e66: d005 beq.n 82e74 <__libc_fini_array+0x1c> + 82e68: 3c01 subs r4, #1 + 82e6a: f855 3d04 ldr.w r3, [r5, #-4]! + 82e6e: 4798 blx r3 + 82e70: 2c00 cmp r4, #0 + 82e72: d1f9 bne.n 82e68 <__libc_fini_array+0x10> + 82e74: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} + 82e78: f001 bf4a b.w 84d10 <_fini> + 82e7c: 00084d1c .word 0x00084d1c + 82e80: 00084d20 .word 0x00084d20 + +00082e84 <__fputwc>: + 82e84: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 82e88: b082 sub sp, #8 + 82e8a: 4607 mov r7, r0 + 82e8c: 460e mov r6, r1 + 82e8e: 4614 mov r4, r2 + 82e90: f000 fb44 bl 8351c <__locale_mb_cur_max> + 82e94: 2801 cmp r0, #1 + 82e96: d040 beq.n 82f1a <__fputwc+0x96> + 82e98: 4638 mov r0, r7 + 82e9a: a901 add r1, sp, #4 + 82e9c: 4632 mov r2, r6 + 82e9e: f104 035c add.w r3, r4, #92 ; 0x5c + 82ea2: f001 f989 bl 841b8 <_wcrtomb_r> + 82ea6: f1b0 3fff cmp.w r0, #4294967295 + 82eaa: 4680 mov r8, r0 + 82eac: d02e beq.n 82f0c <__fputwc+0x88> + 82eae: 2800 cmp r0, #0 + 82eb0: d03b beq.n 82f2a <__fputwc+0xa6> + 82eb2: f89d 1004 ldrb.w r1, [sp, #4] + 82eb6: 2500 movs r5, #0 + 82eb8: e009 b.n 82ece <__fputwc+0x4a> + 82eba: 6823 ldr r3, [r4, #0] + 82ebc: 7019 strb r1, [r3, #0] + 82ebe: 6823 ldr r3, [r4, #0] + 82ec0: 3301 adds r3, #1 + 82ec2: 6023 str r3, [r4, #0] + 82ec4: 3501 adds r5, #1 + 82ec6: 45a8 cmp r8, r5 + 82ec8: d92f bls.n 82f2a <__fputwc+0xa6> + 82eca: ab01 add r3, sp, #4 + 82ecc: 5d59 ldrb r1, [r3, r5] + 82ece: 68a3 ldr r3, [r4, #8] + 82ed0: 3b01 subs r3, #1 + 82ed2: 2b00 cmp r3, #0 + 82ed4: 60a3 str r3, [r4, #8] + 82ed6: daf0 bge.n 82eba <__fputwc+0x36> + 82ed8: 69a2 ldr r2, [r4, #24] + 82eda: 4293 cmp r3, r2 + 82edc: db06 blt.n 82eec <__fputwc+0x68> + 82ede: 6823 ldr r3, [r4, #0] + 82ee0: 7019 strb r1, [r3, #0] + 82ee2: 6823 ldr r3, [r4, #0] + 82ee4: 7819 ldrb r1, [r3, #0] + 82ee6: 3301 adds r3, #1 + 82ee8: 290a cmp r1, #10 + 82eea: d1ea bne.n 82ec2 <__fputwc+0x3e> + 82eec: 4638 mov r0, r7 + 82eee: 4622 mov r2, r4 + 82ef0: f001 f90e bl 84110 <__swbuf_r> + 82ef4: f1a0 30ff sub.w r0, r0, #4294967295 + 82ef8: fab0 f080 clz r0, r0 + 82efc: 0940 lsrs r0, r0, #5 + 82efe: 2800 cmp r0, #0 + 82f00: d0e0 beq.n 82ec4 <__fputwc+0x40> + 82f02: f04f 30ff mov.w r0, #4294967295 + 82f06: b002 add sp, #8 + 82f08: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 82f0c: 89a3 ldrh r3, [r4, #12] + 82f0e: f043 0340 orr.w r3, r3, #64 ; 0x40 + 82f12: 81a3 strh r3, [r4, #12] + 82f14: b002 add sp, #8 + 82f16: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 82f1a: 1e73 subs r3, r6, #1 + 82f1c: 2bfe cmp r3, #254 ; 0xfe + 82f1e: d8bb bhi.n 82e98 <__fputwc+0x14> + 82f20: b2f1 uxtb r1, r6 + 82f22: 4680 mov r8, r0 + 82f24: f88d 1004 strb.w r1, [sp, #4] + 82f28: e7c5 b.n 82eb6 <__fputwc+0x32> + 82f2a: 4630 mov r0, r6 + 82f2c: b002 add sp, #8 + 82f2e: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 82f32: bf00 nop + +00082f34 <_fputwc_r>: + 82f34: 8993 ldrh r3, [r2, #12] + 82f36: f413 5f00 tst.w r3, #8192 ; 0x2000 + 82f3a: d10b bne.n 82f54 <_fputwc_r+0x20> + 82f3c: b410 push {r4} + 82f3e: 6e54 ldr r4, [r2, #100] ; 0x64 + 82f40: f443 5300 orr.w r3, r3, #8192 ; 0x2000 + 82f44: f444 5400 orr.w r4, r4, #8192 ; 0x2000 + 82f48: 6654 str r4, [r2, #100] ; 0x64 + 82f4a: 8193 strh r3, [r2, #12] + 82f4c: f85d 4b04 ldr.w r4, [sp], #4 + 82f50: f7ff bf98 b.w 82e84 <__fputwc> + 82f54: f7ff bf96 b.w 82e84 <__fputwc> + +00082f58 <_malloc_trim_r>: + 82f58: b5f8 push {r3, r4, r5, r6, r7, lr} + 82f5a: 460c mov r4, r1 + 82f5c: 4f22 ldr r7, [pc, #136] ; (82fe8 <_malloc_trim_r+0x90>) + 82f5e: 4606 mov r6, r0 + 82f60: f000 fe8e bl 83c80 <__malloc_lock> + 82f64: 68bb ldr r3, [r7, #8] + 82f66: 685d ldr r5, [r3, #4] + 82f68: f025 0503 bic.w r5, r5, #3 + 82f6c: 1b29 subs r1, r5, r4 + 82f6e: f601 71ef addw r1, r1, #4079 ; 0xfef + 82f72: f421 617f bic.w r1, r1, #4080 ; 0xff0 + 82f76: f021 010f bic.w r1, r1, #15 + 82f7a: f5a1 5480 sub.w r4, r1, #4096 ; 0x1000 + 82f7e: f5b4 5f80 cmp.w r4, #4096 ; 0x1000 + 82f82: db07 blt.n 82f94 <_malloc_trim_r+0x3c> + 82f84: 4630 mov r0, r6 + 82f86: 2100 movs r1, #0 + 82f88: f001 f86e bl 84068 <_sbrk_r> + 82f8c: 68bb ldr r3, [r7, #8] + 82f8e: 442b add r3, r5 + 82f90: 4298 cmp r0, r3 + 82f92: d004 beq.n 82f9e <_malloc_trim_r+0x46> + 82f94: 4630 mov r0, r6 + 82f96: f000 fe75 bl 83c84 <__malloc_unlock> + 82f9a: 2000 movs r0, #0 + 82f9c: bdf8 pop {r3, r4, r5, r6, r7, pc} + 82f9e: 4630 mov r0, r6 + 82fa0: 4261 negs r1, r4 + 82fa2: f001 f861 bl 84068 <_sbrk_r> + 82fa6: 3001 adds r0, #1 + 82fa8: d00d beq.n 82fc6 <_malloc_trim_r+0x6e> + 82faa: 4b10 ldr r3, [pc, #64] ; (82fec <_malloc_trim_r+0x94>) + 82fac: 68ba ldr r2, [r7, #8] + 82fae: 6819 ldr r1, [r3, #0] + 82fb0: 1b2d subs r5, r5, r4 + 82fb2: f045 0501 orr.w r5, r5, #1 + 82fb6: 4630 mov r0, r6 + 82fb8: 1b09 subs r1, r1, r4 + 82fba: 6055 str r5, [r2, #4] + 82fbc: 6019 str r1, [r3, #0] + 82fbe: f000 fe61 bl 83c84 <__malloc_unlock> + 82fc2: 2001 movs r0, #1 + 82fc4: bdf8 pop {r3, r4, r5, r6, r7, pc} + 82fc6: 4630 mov r0, r6 + 82fc8: 2100 movs r1, #0 + 82fca: f001 f84d bl 84068 <_sbrk_r> + 82fce: 68ba ldr r2, [r7, #8] + 82fd0: 1a83 subs r3, r0, r2 + 82fd2: 2b0f cmp r3, #15 + 82fd4: ddde ble.n 82f94 <_malloc_trim_r+0x3c> + 82fd6: 4c06 ldr r4, [pc, #24] ; (82ff0 <_malloc_trim_r+0x98>) + 82fd8: 4904 ldr r1, [pc, #16] ; (82fec <_malloc_trim_r+0x94>) + 82fda: 6824 ldr r4, [r4, #0] + 82fdc: f043 0301 orr.w r3, r3, #1 + 82fe0: 1b00 subs r0, r0, r4 + 82fe2: 6053 str r3, [r2, #4] + 82fe4: 6008 str r0, [r1, #0] + 82fe6: e7d5 b.n 82f94 <_malloc_trim_r+0x3c> + 82fe8: 20070580 .word 0x20070580 + 82fec: 200748b4 .word 0x200748b4 + 82ff0: 2007098c .word 0x2007098c + +00082ff4 <_free_r>: + 82ff4: 2900 cmp r1, #0 + 82ff6: d04e beq.n 83096 <_free_r+0xa2> + 82ff8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 82ffc: 460c mov r4, r1 + 82ffe: 4680 mov r8, r0 + 83000: f000 fe3e bl 83c80 <__malloc_lock> + 83004: f854 7c04 ldr.w r7, [r4, #-4] + 83008: 4962 ldr r1, [pc, #392] ; (83194 <_free_r+0x1a0>) + 8300a: f1a4 0508 sub.w r5, r4, #8 + 8300e: f027 0201 bic.w r2, r7, #1 + 83012: 18ab adds r3, r5, r2 + 83014: 688e ldr r6, [r1, #8] + 83016: 6858 ldr r0, [r3, #4] + 83018: 429e cmp r6, r3 + 8301a: f020 0003 bic.w r0, r0, #3 + 8301e: d05a beq.n 830d6 <_free_r+0xe2> + 83020: 07fe lsls r6, r7, #31 + 83022: 6058 str r0, [r3, #4] + 83024: d40b bmi.n 8303e <_free_r+0x4a> + 83026: f854 7c08 ldr.w r7, [r4, #-8] + 8302a: f101 0e08 add.w lr, r1, #8 + 8302e: 1bed subs r5, r5, r7 + 83030: 68ac ldr r4, [r5, #8] + 83032: 443a add r2, r7 + 83034: 4574 cmp r4, lr + 83036: d067 beq.n 83108 <_free_r+0x114> + 83038: 68ef ldr r7, [r5, #12] + 8303a: 60e7 str r7, [r4, #12] + 8303c: 60bc str r4, [r7, #8] + 8303e: 181c adds r4, r3, r0 + 83040: 6864 ldr r4, [r4, #4] + 83042: 07e4 lsls r4, r4, #31 + 83044: d40c bmi.n 83060 <_free_r+0x6c> + 83046: 4f54 ldr r7, [pc, #336] ; (83198 <_free_r+0x1a4>) + 83048: 689c ldr r4, [r3, #8] + 8304a: 4402 add r2, r0 + 8304c: 42bc cmp r4, r7 + 8304e: d07c beq.n 8314a <_free_r+0x156> + 83050: 68d8 ldr r0, [r3, #12] + 83052: f042 0301 orr.w r3, r2, #1 + 83056: 60e0 str r0, [r4, #12] + 83058: 6084 str r4, [r0, #8] + 8305a: 606b str r3, [r5, #4] + 8305c: 50aa str r2, [r5, r2] + 8305e: e003 b.n 83068 <_free_r+0x74> + 83060: f042 0301 orr.w r3, r2, #1 + 83064: 606b str r3, [r5, #4] + 83066: 50aa str r2, [r5, r2] + 83068: f5b2 7f00 cmp.w r2, #512 ; 0x200 + 8306c: d214 bcs.n 83098 <_free_r+0xa4> + 8306e: 08d2 lsrs r2, r2, #3 + 83070: eb01 03c2 add.w r3, r1, r2, lsl #3 + 83074: 2401 movs r4, #1 + 83076: 6848 ldr r0, [r1, #4] + 83078: 1092 asrs r2, r2, #2 + 8307a: fa04 f202 lsl.w r2, r4, r2 + 8307e: 689c ldr r4, [r3, #8] + 83080: 4310 orrs r0, r2 + 83082: 60ac str r4, [r5, #8] + 83084: 60eb str r3, [r5, #12] + 83086: 6048 str r0, [r1, #4] + 83088: 609d str r5, [r3, #8] + 8308a: 60e5 str r5, [r4, #12] + 8308c: 4640 mov r0, r8 + 8308e: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} + 83092: f000 bdf7 b.w 83c84 <__malloc_unlock> + 83096: 4770 bx lr + 83098: 0a53 lsrs r3, r2, #9 + 8309a: 2b04 cmp r3, #4 + 8309c: d847 bhi.n 8312e <_free_r+0x13a> + 8309e: 0993 lsrs r3, r2, #6 + 830a0: f103 0438 add.w r4, r3, #56 ; 0x38 + 830a4: 0060 lsls r0, r4, #1 + 830a6: eb01 0080 add.w r0, r1, r0, lsl #2 + 830aa: 6883 ldr r3, [r0, #8] + 830ac: 4939 ldr r1, [pc, #228] ; (83194 <_free_r+0x1a0>) + 830ae: 4283 cmp r3, r0 + 830b0: d043 beq.n 8313a <_free_r+0x146> + 830b2: 6859 ldr r1, [r3, #4] + 830b4: f021 0103 bic.w r1, r1, #3 + 830b8: 4291 cmp r1, r2 + 830ba: d902 bls.n 830c2 <_free_r+0xce> + 830bc: 689b ldr r3, [r3, #8] + 830be: 4298 cmp r0, r3 + 830c0: d1f7 bne.n 830b2 <_free_r+0xbe> + 830c2: 68da ldr r2, [r3, #12] + 830c4: 60ea str r2, [r5, #12] + 830c6: 60ab str r3, [r5, #8] + 830c8: 4640 mov r0, r8 + 830ca: 6095 str r5, [r2, #8] + 830cc: 60dd str r5, [r3, #12] + 830ce: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} + 830d2: f000 bdd7 b.w 83c84 <__malloc_unlock> + 830d6: 07ff lsls r7, r7, #31 + 830d8: 4402 add r2, r0 + 830da: d407 bmi.n 830ec <_free_r+0xf8> + 830dc: f854 4c08 ldr.w r4, [r4, #-8] + 830e0: 1b2d subs r5, r5, r4 + 830e2: 68eb ldr r3, [r5, #12] + 830e4: 68a8 ldr r0, [r5, #8] + 830e6: 4422 add r2, r4 + 830e8: 60c3 str r3, [r0, #12] + 830ea: 6098 str r0, [r3, #8] + 830ec: 4b2b ldr r3, [pc, #172] ; (8319c <_free_r+0x1a8>) + 830ee: f042 0001 orr.w r0, r2, #1 + 830f2: 681b ldr r3, [r3, #0] + 830f4: 6068 str r0, [r5, #4] + 830f6: 429a cmp r2, r3 + 830f8: 608d str r5, [r1, #8] + 830fa: d3c7 bcc.n 8308c <_free_r+0x98> + 830fc: 4b28 ldr r3, [pc, #160] ; (831a0 <_free_r+0x1ac>) + 830fe: 4640 mov r0, r8 + 83100: 6819 ldr r1, [r3, #0] + 83102: f7ff ff29 bl 82f58 <_malloc_trim_r> + 83106: e7c1 b.n 8308c <_free_r+0x98> + 83108: 1819 adds r1, r3, r0 + 8310a: 6849 ldr r1, [r1, #4] + 8310c: 07c9 lsls r1, r1, #31 + 8310e: d409 bmi.n 83124 <_free_r+0x130> + 83110: 68d9 ldr r1, [r3, #12] + 83112: 4402 add r2, r0 + 83114: 689b ldr r3, [r3, #8] + 83116: f042 0001 orr.w r0, r2, #1 + 8311a: 60d9 str r1, [r3, #12] + 8311c: 608b str r3, [r1, #8] + 8311e: 6068 str r0, [r5, #4] + 83120: 50aa str r2, [r5, r2] + 83122: e7b3 b.n 8308c <_free_r+0x98> + 83124: f042 0301 orr.w r3, r2, #1 + 83128: 606b str r3, [r5, #4] + 8312a: 50aa str r2, [r5, r2] + 8312c: e7ae b.n 8308c <_free_r+0x98> + 8312e: 2b14 cmp r3, #20 + 83130: d814 bhi.n 8315c <_free_r+0x168> + 83132: f103 045b add.w r4, r3, #91 ; 0x5b + 83136: 0060 lsls r0, r4, #1 + 83138: e7b5 b.n 830a6 <_free_r+0xb2> + 8313a: 684a ldr r2, [r1, #4] + 8313c: 10a4 asrs r4, r4, #2 + 8313e: 2001 movs r0, #1 + 83140: 40a0 lsls r0, r4 + 83142: 4302 orrs r2, r0 + 83144: 604a str r2, [r1, #4] + 83146: 461a mov r2, r3 + 83148: e7bc b.n 830c4 <_free_r+0xd0> + 8314a: f042 0301 orr.w r3, r2, #1 + 8314e: 614d str r5, [r1, #20] + 83150: 610d str r5, [r1, #16] + 83152: 60ec str r4, [r5, #12] + 83154: 60ac str r4, [r5, #8] + 83156: 606b str r3, [r5, #4] + 83158: 50aa str r2, [r5, r2] + 8315a: e797 b.n 8308c <_free_r+0x98> + 8315c: 2b54 cmp r3, #84 ; 0x54 + 8315e: d804 bhi.n 8316a <_free_r+0x176> + 83160: 0b13 lsrs r3, r2, #12 + 83162: f103 046e add.w r4, r3, #110 ; 0x6e + 83166: 0060 lsls r0, r4, #1 + 83168: e79d b.n 830a6 <_free_r+0xb2> + 8316a: f5b3 7faa cmp.w r3, #340 ; 0x154 + 8316e: d804 bhi.n 8317a <_free_r+0x186> + 83170: 0bd3 lsrs r3, r2, #15 + 83172: f103 0477 add.w r4, r3, #119 ; 0x77 + 83176: 0060 lsls r0, r4, #1 + 83178: e795 b.n 830a6 <_free_r+0xb2> + 8317a: f240 5054 movw r0, #1364 ; 0x554 + 8317e: 4283 cmp r3, r0 + 83180: d804 bhi.n 8318c <_free_r+0x198> + 83182: 0c93 lsrs r3, r2, #18 + 83184: f103 047c add.w r4, r3, #124 ; 0x7c + 83188: 0060 lsls r0, r4, #1 + 8318a: e78c b.n 830a6 <_free_r+0xb2> + 8318c: 20fc movs r0, #252 ; 0xfc + 8318e: 247e movs r4, #126 ; 0x7e + 83190: e789 b.n 830a6 <_free_r+0xb2> + 83192: bf00 nop + 83194: 20070580 .word 0x20070580 + 83198: 20070588 .word 0x20070588 + 8319c: 20070988 .word 0x20070988 + 831a0: 200748b0 .word 0x200748b0 + +000831a4 <__sfvwrite_r>: + 831a4: 6893 ldr r3, [r2, #8] + 831a6: 2b00 cmp r3, #0 + 831a8: f000 80b1 beq.w 8330e <__sfvwrite_r+0x16a> + 831ac: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 831b0: f8b1 e00c ldrh.w lr, [r1, #12] + 831b4: b083 sub sp, #12 + 831b6: f01e 0f08 tst.w lr, #8 + 831ba: 460c mov r4, r1 + 831bc: 4681 mov r9, r0 + 831be: 4616 mov r6, r2 + 831c0: d028 beq.n 83214 <__sfvwrite_r+0x70> + 831c2: 690b ldr r3, [r1, #16] + 831c4: b333 cbz r3, 83214 <__sfvwrite_r+0x70> + 831c6: f00e 0802 and.w r8, lr, #2 + 831ca: fa1f f088 uxth.w r0, r8 + 831ce: 6835 ldr r5, [r6, #0] + 831d0: b380 cbz r0, 83234 <__sfvwrite_r+0x90> + 831d2: f04f 0b00 mov.w fp, #0 + 831d6: 46d8 mov r8, fp + 831d8: f8df a2e4 ldr.w sl, [pc, #740] ; 834c0 <__sfvwrite_r+0x31c> + 831dc: f1b8 0f00 cmp.w r8, #0 + 831e0: f000 808f beq.w 83302 <__sfvwrite_r+0x15e> + 831e4: 45d0 cmp r8, sl + 831e6: 4643 mov r3, r8 + 831e8: 4648 mov r0, r9 + 831ea: bf28 it cs + 831ec: 4653 movcs r3, sl + 831ee: 69e1 ldr r1, [r4, #28] + 831f0: 465a mov r2, fp + 831f2: 6a67 ldr r7, [r4, #36] ; 0x24 + 831f4: 47b8 blx r7 + 831f6: 2800 cmp r0, #0 + 831f8: f340 80a8 ble.w 8334c <__sfvwrite_r+0x1a8> + 831fc: 68b3 ldr r3, [r6, #8] + 831fe: 4483 add fp, r0 + 83200: 1a1b subs r3, r3, r0 + 83202: ebc0 0808 rsb r8, r0, r8 + 83206: 60b3 str r3, [r6, #8] + 83208: 2b00 cmp r3, #0 + 8320a: d1e7 bne.n 831dc <__sfvwrite_r+0x38> + 8320c: 2000 movs r0, #0 + 8320e: b003 add sp, #12 + 83210: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 83214: 4648 mov r0, r9 + 83216: 4621 mov r1, r4 + 83218: f7ff fc6a bl 82af0 <__swsetup_r> + 8321c: 2800 cmp r0, #0 + 8321e: f040 8146 bne.w 834ae <__sfvwrite_r+0x30a> + 83222: f8b4 e00c ldrh.w lr, [r4, #12] + 83226: 6835 ldr r5, [r6, #0] + 83228: f00e 0802 and.w r8, lr, #2 + 8322c: fa1f f088 uxth.w r0, r8 + 83230: 2800 cmp r0, #0 + 83232: d1ce bne.n 831d2 <__sfvwrite_r+0x2e> + 83234: f01e 0b01 ands.w fp, lr, #1 + 83238: f040 8091 bne.w 8335e <__sfvwrite_r+0x1ba> + 8323c: 46d8 mov r8, fp + 8323e: f1b8 0f00 cmp.w r8, #0 + 83242: d058 beq.n 832f6 <__sfvwrite_r+0x152> + 83244: f41e 7f00 tst.w lr, #512 ; 0x200 + 83248: 68a7 ldr r7, [r4, #8] + 8324a: d062 beq.n 83312 <__sfvwrite_r+0x16e> + 8324c: 45b8 cmp r8, r7 + 8324e: 46ba mov sl, r7 + 83250: f0c0 80c2 bcc.w 833d8 <__sfvwrite_r+0x234> + 83254: f41e 6f90 tst.w lr, #1152 ; 0x480 + 83258: f000 80c0 beq.w 833dc <__sfvwrite_r+0x238> + 8325c: 6967 ldr r7, [r4, #20] + 8325e: 6921 ldr r1, [r4, #16] + 83260: 6823 ldr r3, [r4, #0] + 83262: eb07 0747 add.w r7, r7, r7, lsl #1 + 83266: 1a5b subs r3, r3, r1 + 83268: eb07 77d7 add.w r7, r7, r7, lsr #31 + 8326c: 1c58 adds r0, r3, #1 + 8326e: 107f asrs r7, r7, #1 + 83270: 4440 add r0, r8 + 83272: 4287 cmp r7, r0 + 83274: 463a mov r2, r7 + 83276: bf3c itt cc + 83278: 4607 movcc r7, r0 + 8327a: 463a movcc r2, r7 + 8327c: f41e 6f80 tst.w lr, #1024 ; 0x400 + 83280: 9300 str r3, [sp, #0] + 83282: f000 80fb beq.w 8347c <__sfvwrite_r+0x2d8> + 83286: 4611 mov r1, r2 + 83288: 4648 mov r0, r9 + 8328a: f000 f9c5 bl 83618 <_malloc_r> + 8328e: 9b00 ldr r3, [sp, #0] + 83290: 4682 mov sl, r0 + 83292: 2800 cmp r0, #0 + 83294: f000 810e beq.w 834b4 <__sfvwrite_r+0x310> + 83298: 461a mov r2, r3 + 8329a: 6921 ldr r1, [r4, #16] + 8329c: 9300 str r3, [sp, #0] + 8329e: f7fe fbf7 bl 81a90 + 832a2: 89a2 ldrh r2, [r4, #12] + 832a4: 9b00 ldr r3, [sp, #0] + 832a6: f422 6290 bic.w r2, r2, #1152 ; 0x480 + 832aa: f042 0280 orr.w r2, r2, #128 ; 0x80 + 832ae: 81a2 strh r2, [r4, #12] + 832b0: eb0a 0003 add.w r0, sl, r3 + 832b4: f8c4 a010 str.w sl, [r4, #16] + 832b8: 1afb subs r3, r7, r3 + 832ba: 6167 str r7, [r4, #20] + 832bc: 46c2 mov sl, r8 + 832be: 4647 mov r7, r8 + 832c0: 6020 str r0, [r4, #0] + 832c2: 60a3 str r3, [r4, #8] + 832c4: 4652 mov r2, sl + 832c6: 4659 mov r1, fp + 832c8: f000 fc76 bl 83bb8 + 832cc: 68a0 ldr r0, [r4, #8] + 832ce: 6822 ldr r2, [r4, #0] + 832d0: 1bc0 subs r0, r0, r7 + 832d2: 60a0 str r0, [r4, #8] + 832d4: 4640 mov r0, r8 + 832d6: eb02 030a add.w r3, r2, sl + 832da: 6023 str r3, [r4, #0] + 832dc: 68b3 ldr r3, [r6, #8] + 832de: 4483 add fp, r0 + 832e0: 1a1b subs r3, r3, r0 + 832e2: ebc0 0808 rsb r8, r0, r8 + 832e6: 60b3 str r3, [r6, #8] + 832e8: 2b00 cmp r3, #0 + 832ea: d08f beq.n 8320c <__sfvwrite_r+0x68> + 832ec: f8b4 e00c ldrh.w lr, [r4, #12] + 832f0: f1b8 0f00 cmp.w r8, #0 + 832f4: d1a6 bne.n 83244 <__sfvwrite_r+0xa0> + 832f6: f8d5 b000 ldr.w fp, [r5] + 832fa: f8d5 8004 ldr.w r8, [r5, #4] + 832fe: 3508 adds r5, #8 + 83300: e79d b.n 8323e <__sfvwrite_r+0x9a> + 83302: f8d5 b000 ldr.w fp, [r5] + 83306: f8d5 8004 ldr.w r8, [r5, #4] + 8330a: 3508 adds r5, #8 + 8330c: e766 b.n 831dc <__sfvwrite_r+0x38> + 8330e: 2000 movs r0, #0 + 83310: 4770 bx lr + 83312: 6820 ldr r0, [r4, #0] + 83314: 6923 ldr r3, [r4, #16] + 83316: 4298 cmp r0, r3 + 83318: d803 bhi.n 83322 <__sfvwrite_r+0x17e> + 8331a: 6962 ldr r2, [r4, #20] + 8331c: 4590 cmp r8, r2 + 8331e: f080 8085 bcs.w 8342c <__sfvwrite_r+0x288> + 83322: 4547 cmp r7, r8 + 83324: bf28 it cs + 83326: 4647 movcs r7, r8 + 83328: 4659 mov r1, fp + 8332a: 463a mov r2, r7 + 8332c: f000 fc44 bl 83bb8 + 83330: 68a3 ldr r3, [r4, #8] + 83332: 6822 ldr r2, [r4, #0] + 83334: 1bdb subs r3, r3, r7 + 83336: 443a add r2, r7 + 83338: 60a3 str r3, [r4, #8] + 8333a: 6022 str r2, [r4, #0] + 8333c: 2b00 cmp r3, #0 + 8333e: d149 bne.n 833d4 <__sfvwrite_r+0x230> + 83340: 4648 mov r0, r9 + 83342: 4621 mov r1, r4 + 83344: f7ff fcea bl 82d1c <_fflush_r> + 83348: 2800 cmp r0, #0 + 8334a: d043 beq.n 833d4 <__sfvwrite_r+0x230> + 8334c: 89a3 ldrh r3, [r4, #12] + 8334e: f043 0340 orr.w r3, r3, #64 ; 0x40 + 83352: f04f 30ff mov.w r0, #4294967295 + 83356: 81a3 strh r3, [r4, #12] + 83358: b003 add sp, #12 + 8335a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 8335e: 4680 mov r8, r0 + 83360: 4683 mov fp, r0 + 83362: 4682 mov sl, r0 + 83364: 9000 str r0, [sp, #0] + 83366: f1ba 0f00 cmp.w sl, #0 + 8336a: d02b beq.n 833c4 <__sfvwrite_r+0x220> + 8336c: 9b00 ldr r3, [sp, #0] + 8336e: 2b00 cmp r3, #0 + 83370: d04f beq.n 83412 <__sfvwrite_r+0x26e> + 83372: 45d0 cmp r8, sl + 83374: 4643 mov r3, r8 + 83376: bf28 it cs + 83378: 4653 movcs r3, sl + 8337a: 6820 ldr r0, [r4, #0] + 8337c: 6921 ldr r1, [r4, #16] + 8337e: 461f mov r7, r3 + 83380: 4288 cmp r0, r1 + 83382: f8d4 e008 ldr.w lr, [r4, #8] + 83386: 6962 ldr r2, [r4, #20] + 83388: d903 bls.n 83392 <__sfvwrite_r+0x1ee> + 8338a: eb0e 0c02 add.w ip, lr, r2 + 8338e: 4563 cmp r3, ip + 83390: dc5e bgt.n 83450 <__sfvwrite_r+0x2ac> + 83392: 4293 cmp r3, r2 + 83394: db24 blt.n 833e0 <__sfvwrite_r+0x23c> + 83396: 4613 mov r3, r2 + 83398: 6a67 ldr r7, [r4, #36] ; 0x24 + 8339a: 4648 mov r0, r9 + 8339c: 69e1 ldr r1, [r4, #28] + 8339e: 465a mov r2, fp + 833a0: 47b8 blx r7 + 833a2: 1e07 subs r7, r0, #0 + 833a4: ddd2 ble.n 8334c <__sfvwrite_r+0x1a8> + 833a6: ebb8 0807 subs.w r8, r8, r7 + 833aa: d029 beq.n 83400 <__sfvwrite_r+0x25c> + 833ac: 68b3 ldr r3, [r6, #8] + 833ae: 44bb add fp, r7 + 833b0: 1bdb subs r3, r3, r7 + 833b2: ebc7 0a0a rsb sl, r7, sl + 833b6: 60b3 str r3, [r6, #8] + 833b8: 2b00 cmp r3, #0 + 833ba: f43f af27 beq.w 8320c <__sfvwrite_r+0x68> + 833be: f1ba 0f00 cmp.w sl, #0 + 833c2: d1d3 bne.n 8336c <__sfvwrite_r+0x1c8> + 833c4: 2300 movs r3, #0 + 833c6: f8d5 b000 ldr.w fp, [r5] + 833ca: f8d5 a004 ldr.w sl, [r5, #4] + 833ce: 9300 str r3, [sp, #0] + 833d0: 3508 adds r5, #8 + 833d2: e7c8 b.n 83366 <__sfvwrite_r+0x1c2> + 833d4: 4638 mov r0, r7 + 833d6: e781 b.n 832dc <__sfvwrite_r+0x138> + 833d8: 4647 mov r7, r8 + 833da: 46c2 mov sl, r8 + 833dc: 6820 ldr r0, [r4, #0] + 833de: e771 b.n 832c4 <__sfvwrite_r+0x120> + 833e0: 461a mov r2, r3 + 833e2: 4659 mov r1, fp + 833e4: 9301 str r3, [sp, #4] + 833e6: f000 fbe7 bl 83bb8 + 833ea: 68a2 ldr r2, [r4, #8] + 833ec: 6821 ldr r1, [r4, #0] + 833ee: 9b01 ldr r3, [sp, #4] + 833f0: ebb8 0807 subs.w r8, r8, r7 + 833f4: eba2 0203 sub.w r2, r2, r3 + 833f8: 440b add r3, r1 + 833fa: 60a2 str r2, [r4, #8] + 833fc: 6023 str r3, [r4, #0] + 833fe: d1d5 bne.n 833ac <__sfvwrite_r+0x208> + 83400: 4648 mov r0, r9 + 83402: 4621 mov r1, r4 + 83404: f7ff fc8a bl 82d1c <_fflush_r> + 83408: 2800 cmp r0, #0 + 8340a: d19f bne.n 8334c <__sfvwrite_r+0x1a8> + 8340c: f8cd 8000 str.w r8, [sp] + 83410: e7cc b.n 833ac <__sfvwrite_r+0x208> + 83412: 4658 mov r0, fp + 83414: 210a movs r1, #10 + 83416: 4652 mov r2, sl + 83418: f000 fb84 bl 83b24 + 8341c: 2800 cmp r0, #0 + 8341e: d041 beq.n 834a4 <__sfvwrite_r+0x300> + 83420: 3001 adds r0, #1 + 83422: 2301 movs r3, #1 + 83424: ebcb 0800 rsb r8, fp, r0 + 83428: 9300 str r3, [sp, #0] + 8342a: e7a2 b.n 83372 <__sfvwrite_r+0x1ce> + 8342c: f06f 4300 mvn.w r3, #2147483648 ; 0x80000000 + 83430: 4543 cmp r3, r8 + 83432: bf28 it cs + 83434: 4643 movcs r3, r8 + 83436: fb93 f3f2 sdiv r3, r3, r2 + 8343a: 6a67 ldr r7, [r4, #36] ; 0x24 + 8343c: fb03 f302 mul.w r3, r3, r2 + 83440: 4648 mov r0, r9 + 83442: 69e1 ldr r1, [r4, #28] + 83444: 465a mov r2, fp + 83446: 47b8 blx r7 + 83448: 2800 cmp r0, #0 + 8344a: f73f af47 bgt.w 832dc <__sfvwrite_r+0x138> + 8344e: e77d b.n 8334c <__sfvwrite_r+0x1a8> + 83450: 4662 mov r2, ip + 83452: 4659 mov r1, fp + 83454: f8cd c004 str.w ip, [sp, #4] + 83458: f000 fbae bl 83bb8 + 8345c: 6823 ldr r3, [r4, #0] + 8345e: f8dd c004 ldr.w ip, [sp, #4] + 83462: 4648 mov r0, r9 + 83464: 4463 add r3, ip + 83466: 6023 str r3, [r4, #0] + 83468: 4621 mov r1, r4 + 8346a: f7ff fc57 bl 82d1c <_fflush_r> + 8346e: f8dd c004 ldr.w ip, [sp, #4] + 83472: 2800 cmp r0, #0 + 83474: f47f af6a bne.w 8334c <__sfvwrite_r+0x1a8> + 83478: 4667 mov r7, ip + 8347a: e794 b.n 833a6 <__sfvwrite_r+0x202> + 8347c: 4648 mov r0, r9 + 8347e: f000 fc03 bl 83c88 <_realloc_r> + 83482: 9b00 ldr r3, [sp, #0] + 83484: 4682 mov sl, r0 + 83486: 2800 cmp r0, #0 + 83488: f47f af12 bne.w 832b0 <__sfvwrite_r+0x10c> + 8348c: 4648 mov r0, r9 + 8348e: 6921 ldr r1, [r4, #16] + 83490: f7ff fdb0 bl 82ff4 <_free_r> + 83494: 89a3 ldrh r3, [r4, #12] + 83496: 220c movs r2, #12 + 83498: f023 0380 bic.w r3, r3, #128 ; 0x80 + 8349c: b29b uxth r3, r3 + 8349e: f8c9 2000 str.w r2, [r9] + 834a2: e754 b.n 8334e <__sfvwrite_r+0x1aa> + 834a4: 2301 movs r3, #1 + 834a6: f10a 0801 add.w r8, sl, #1 + 834aa: 9300 str r3, [sp, #0] + 834ac: e761 b.n 83372 <__sfvwrite_r+0x1ce> + 834ae: f04f 30ff mov.w r0, #4294967295 + 834b2: e6ac b.n 8320e <__sfvwrite_r+0x6a> + 834b4: 230c movs r3, #12 + 834b6: f8c9 3000 str.w r3, [r9] + 834ba: 89a3 ldrh r3, [r4, #12] + 834bc: e747 b.n 8334e <__sfvwrite_r+0x1aa> + 834be: bf00 nop + 834c0: 7ffffc00 .word 0x7ffffc00 + +000834c4 <_fwalk_reent>: + 834c4: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 834c8: f510 7638 adds.w r6, r0, #736 ; 0x2e0 + 834cc: d01e beq.n 8350c <_fwalk_reent+0x48> + 834ce: 4688 mov r8, r1 + 834d0: 4607 mov r7, r0 + 834d2: f04f 0900 mov.w r9, #0 + 834d6: 6875 ldr r5, [r6, #4] + 834d8: 68b4 ldr r4, [r6, #8] + 834da: 3d01 subs r5, #1 + 834dc: d410 bmi.n 83500 <_fwalk_reent+0x3c> + 834de: 89a3 ldrh r3, [r4, #12] + 834e0: 3d01 subs r5, #1 + 834e2: 2b01 cmp r3, #1 + 834e4: d908 bls.n 834f8 <_fwalk_reent+0x34> + 834e6: f9b4 300e ldrsh.w r3, [r4, #14] + 834ea: 3301 adds r3, #1 + 834ec: d004 beq.n 834f8 <_fwalk_reent+0x34> + 834ee: 4638 mov r0, r7 + 834f0: 4621 mov r1, r4 + 834f2: 47c0 blx r8 + 834f4: ea49 0900 orr.w r9, r9, r0 + 834f8: 1c6b adds r3, r5, #1 + 834fa: f104 0468 add.w r4, r4, #104 ; 0x68 + 834fe: d1ee bne.n 834de <_fwalk_reent+0x1a> + 83500: 6836 ldr r6, [r6, #0] + 83502: 2e00 cmp r6, #0 + 83504: d1e7 bne.n 834d6 <_fwalk_reent+0x12> + 83506: 4648 mov r0, r9 + 83508: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + 8350c: 46b1 mov r9, r6 + 8350e: 4648 mov r0, r9 + 83510: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + +00083514 <__locale_charset>: + 83514: 4800 ldr r0, [pc, #0] ; (83518 <__locale_charset+0x4>) + 83516: 4770 bx lr + 83518: 2007055c .word 0x2007055c + +0008351c <__locale_mb_cur_max>: + 8351c: 4b01 ldr r3, [pc, #4] ; (83524 <__locale_mb_cur_max+0x8>) + 8351e: 6818 ldr r0, [r3, #0] + 83520: 4770 bx lr + 83522: bf00 nop + 83524: 2007057c .word 0x2007057c + +00083528 <__smakebuf_r>: + 83528: 898b ldrh r3, [r1, #12] + 8352a: b29a uxth r2, r3 + 8352c: f012 0f02 tst.w r2, #2 + 83530: d13c bne.n 835ac <__smakebuf_r+0x84> + 83532: b5f0 push {r4, r5, r6, r7, lr} + 83534: 460c mov r4, r1 + 83536: f9b1 100e ldrsh.w r1, [r1, #14] + 8353a: b091 sub sp, #68 ; 0x44 + 8353c: 2900 cmp r1, #0 + 8353e: 4605 mov r5, r0 + 83540: db19 blt.n 83576 <__smakebuf_r+0x4e> + 83542: aa01 add r2, sp, #4 + 83544: f000 ff2a bl 8439c <_fstat_r> + 83548: 2800 cmp r0, #0 + 8354a: db12 blt.n 83572 <__smakebuf_r+0x4a> + 8354c: 9b02 ldr r3, [sp, #8] + 8354e: f403 4370 and.w r3, r3, #61440 ; 0xf000 + 83552: f5a3 5700 sub.w r7, r3, #8192 ; 0x2000 + 83556: fab7 f787 clz r7, r7 + 8355a: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 8355e: ea4f 1757 mov.w r7, r7, lsr #5 + 83562: d02a beq.n 835ba <__smakebuf_r+0x92> + 83564: 89a3 ldrh r3, [r4, #12] + 83566: f44f 6680 mov.w r6, #1024 ; 0x400 + 8356a: f443 6300 orr.w r3, r3, #2048 ; 0x800 + 8356e: 81a3 strh r3, [r4, #12] + 83570: e00b b.n 8358a <__smakebuf_r+0x62> + 83572: 89a3 ldrh r3, [r4, #12] + 83574: b29a uxth r2, r3 + 83576: f012 0f80 tst.w r2, #128 ; 0x80 + 8357a: f443 6300 orr.w r3, r3, #2048 ; 0x800 + 8357e: 81a3 strh r3, [r4, #12] + 83580: bf0c ite eq + 83582: f44f 6680 moveq.w r6, #1024 ; 0x400 + 83586: 2640 movne r6, #64 ; 0x40 + 83588: 2700 movs r7, #0 + 8358a: 4628 mov r0, r5 + 8358c: 4631 mov r1, r6 + 8358e: f000 f843 bl 83618 <_malloc_r> + 83592: 89a3 ldrh r3, [r4, #12] + 83594: b340 cbz r0, 835e8 <__smakebuf_r+0xc0> + 83596: 4a1a ldr r2, [pc, #104] ; (83600 <__smakebuf_r+0xd8>) + 83598: f043 0380 orr.w r3, r3, #128 ; 0x80 + 8359c: 63ea str r2, [r5, #60] ; 0x3c + 8359e: 81a3 strh r3, [r4, #12] + 835a0: 6020 str r0, [r4, #0] + 835a2: 6120 str r0, [r4, #16] + 835a4: 6166 str r6, [r4, #20] + 835a6: b99f cbnz r7, 835d0 <__smakebuf_r+0xa8> + 835a8: b011 add sp, #68 ; 0x44 + 835aa: bdf0 pop {r4, r5, r6, r7, pc} + 835ac: f101 0343 add.w r3, r1, #67 ; 0x43 + 835b0: 2201 movs r2, #1 + 835b2: 600b str r3, [r1, #0] + 835b4: 610b str r3, [r1, #16] + 835b6: 614a str r2, [r1, #20] + 835b8: 4770 bx lr + 835ba: 4b12 ldr r3, [pc, #72] ; (83604 <__smakebuf_r+0xdc>) + 835bc: 6aa2 ldr r2, [r4, #40] ; 0x28 + 835be: 429a cmp r2, r3 + 835c0: d1d0 bne.n 83564 <__smakebuf_r+0x3c> + 835c2: 89a3 ldrh r3, [r4, #12] + 835c4: f44f 6680 mov.w r6, #1024 ; 0x400 + 835c8: 4333 orrs r3, r6 + 835ca: 81a3 strh r3, [r4, #12] + 835cc: 64e6 str r6, [r4, #76] ; 0x4c + 835ce: e7dc b.n 8358a <__smakebuf_r+0x62> + 835d0: 4628 mov r0, r5 + 835d2: f9b4 100e ldrsh.w r1, [r4, #14] + 835d6: f000 fef5 bl 843c4 <_isatty_r> + 835da: 2800 cmp r0, #0 + 835dc: d0e4 beq.n 835a8 <__smakebuf_r+0x80> + 835de: 89a3 ldrh r3, [r4, #12] + 835e0: f043 0301 orr.w r3, r3, #1 + 835e4: 81a3 strh r3, [r4, #12] + 835e6: e7df b.n 835a8 <__smakebuf_r+0x80> + 835e8: 059a lsls r2, r3, #22 + 835ea: d4dd bmi.n 835a8 <__smakebuf_r+0x80> + 835ec: f104 0243 add.w r2, r4, #67 ; 0x43 + 835f0: f043 0302 orr.w r3, r3, #2 + 835f4: 2101 movs r1, #1 + 835f6: 81a3 strh r3, [r4, #12] + 835f8: 6022 str r2, [r4, #0] + 835fa: 6122 str r2, [r4, #16] + 835fc: 6161 str r1, [r4, #20] + 835fe: e7d3 b.n 835a8 <__smakebuf_r+0x80> + 83600: 00082d49 .word 0x00082d49 + 83604: 000840e9 .word 0x000840e9 + +00083608 : + 83608: 4b02 ldr r3, [pc, #8] ; (83614 ) + 8360a: 4601 mov r1, r0 + 8360c: 6818 ldr r0, [r3, #0] + 8360e: f000 b803 b.w 83618 <_malloc_r> + 83612: bf00 nop + 83614: 20070558 .word 0x20070558 + +00083618 <_malloc_r>: + 83618: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8361c: f101 050b add.w r5, r1, #11 + 83620: 2d16 cmp r5, #22 + 83622: b083 sub sp, #12 + 83624: 4606 mov r6, r0 + 83626: d927 bls.n 83678 <_malloc_r+0x60> + 83628: f035 0507 bics.w r5, r5, #7 + 8362c: f100 80b6 bmi.w 8379c <_malloc_r+0x184> + 83630: 42a9 cmp r1, r5 + 83632: f200 80b3 bhi.w 8379c <_malloc_r+0x184> + 83636: f000 fb23 bl 83c80 <__malloc_lock> + 8363a: f5b5 7ffc cmp.w r5, #504 ; 0x1f8 + 8363e: d222 bcs.n 83686 <_malloc_r+0x6e> + 83640: 4fbc ldr r7, [pc, #752] ; (83934 <_malloc_r+0x31c>) + 83642: 08e8 lsrs r0, r5, #3 + 83644: eb07 03c0 add.w r3, r7, r0, lsl #3 + 83648: 68dc ldr r4, [r3, #12] + 8364a: 429c cmp r4, r3 + 8364c: f000 81bc beq.w 839c8 <_malloc_r+0x3b0> + 83650: 6863 ldr r3, [r4, #4] + 83652: 68e1 ldr r1, [r4, #12] + 83654: f023 0303 bic.w r3, r3, #3 + 83658: 4423 add r3, r4 + 8365a: 685a ldr r2, [r3, #4] + 8365c: 68a5 ldr r5, [r4, #8] + 8365e: f042 0201 orr.w r2, r2, #1 + 83662: 60e9 str r1, [r5, #12] + 83664: 4630 mov r0, r6 + 83666: 608d str r5, [r1, #8] + 83668: 605a str r2, [r3, #4] + 8366a: f000 fb0b bl 83c84 <__malloc_unlock> + 8366e: 3408 adds r4, #8 + 83670: 4620 mov r0, r4 + 83672: b003 add sp, #12 + 83674: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 83678: 2910 cmp r1, #16 + 8367a: f200 808f bhi.w 8379c <_malloc_r+0x184> + 8367e: f000 faff bl 83c80 <__malloc_lock> + 83682: 2510 movs r5, #16 + 83684: e7dc b.n 83640 <_malloc_r+0x28> + 83686: 0a68 lsrs r0, r5, #9 + 83688: f000 808f beq.w 837aa <_malloc_r+0x192> + 8368c: 2804 cmp r0, #4 + 8368e: f200 8147 bhi.w 83920 <_malloc_r+0x308> + 83692: 09a8 lsrs r0, r5, #6 + 83694: 3038 adds r0, #56 ; 0x38 + 83696: 0041 lsls r1, r0, #1 + 83698: 4fa6 ldr r7, [pc, #664] ; (83934 <_malloc_r+0x31c>) + 8369a: eb07 0181 add.w r1, r7, r1, lsl #2 + 8369e: 68cc ldr r4, [r1, #12] + 836a0: 42a1 cmp r1, r4 + 836a2: d106 bne.n 836b2 <_malloc_r+0x9a> + 836a4: e00c b.n 836c0 <_malloc_r+0xa8> + 836a6: 2a00 cmp r2, #0 + 836a8: f280 8082 bge.w 837b0 <_malloc_r+0x198> + 836ac: 68e4 ldr r4, [r4, #12] + 836ae: 42a1 cmp r1, r4 + 836b0: d006 beq.n 836c0 <_malloc_r+0xa8> + 836b2: 6863 ldr r3, [r4, #4] + 836b4: f023 0303 bic.w r3, r3, #3 + 836b8: 1b5a subs r2, r3, r5 + 836ba: 2a0f cmp r2, #15 + 836bc: ddf3 ble.n 836a6 <_malloc_r+0x8e> + 836be: 3801 subs r0, #1 + 836c0: 3001 adds r0, #1 + 836c2: 499c ldr r1, [pc, #624] ; (83934 <_malloc_r+0x31c>) + 836c4: 693c ldr r4, [r7, #16] + 836c6: f101 0e08 add.w lr, r1, #8 + 836ca: 4574 cmp r4, lr + 836cc: f000 8171 beq.w 839b2 <_malloc_r+0x39a> + 836d0: 6863 ldr r3, [r4, #4] + 836d2: f023 0303 bic.w r3, r3, #3 + 836d6: 1b5a subs r2, r3, r5 + 836d8: 2a0f cmp r2, #15 + 836da: f300 8157 bgt.w 8398c <_malloc_r+0x374> + 836de: 2a00 cmp r2, #0 + 836e0: f8c1 e014 str.w lr, [r1, #20] + 836e4: f8c1 e010 str.w lr, [r1, #16] + 836e8: da66 bge.n 837b8 <_malloc_r+0x1a0> + 836ea: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 836ee: f080 812d bcs.w 8394c <_malloc_r+0x334> + 836f2: 08db lsrs r3, r3, #3 + 836f4: eb01 08c3 add.w r8, r1, r3, lsl #3 + 836f8: ea4f 0ca3 mov.w ip, r3, asr #2 + 836fc: 684a ldr r2, [r1, #4] + 836fe: 2301 movs r3, #1 + 83700: fa03 f30c lsl.w r3, r3, ip + 83704: f8d8 c008 ldr.w ip, [r8, #8] + 83708: 4313 orrs r3, r2 + 8370a: f8c4 c008 str.w ip, [r4, #8] + 8370e: f8c4 800c str.w r8, [r4, #12] + 83712: 604b str r3, [r1, #4] + 83714: f8c8 4008 str.w r4, [r8, #8] + 83718: f8cc 400c str.w r4, [ip, #12] + 8371c: 1082 asrs r2, r0, #2 + 8371e: 2401 movs r4, #1 + 83720: 4094 lsls r4, r2 + 83722: 429c cmp r4, r3 + 83724: d855 bhi.n 837d2 <_malloc_r+0x1ba> + 83726: 4223 tst r3, r4 + 83728: d106 bne.n 83738 <_malloc_r+0x120> + 8372a: f020 0003 bic.w r0, r0, #3 + 8372e: 0064 lsls r4, r4, #1 + 83730: 4223 tst r3, r4 + 83732: f100 0004 add.w r0, r0, #4 + 83736: d0fa beq.n 8372e <_malloc_r+0x116> + 83738: eb07 08c0 add.w r8, r7, r0, lsl #3 + 8373c: 46c4 mov ip, r8 + 8373e: 4681 mov r9, r0 + 83740: f8dc 300c ldr.w r3, [ip, #12] + 83744: 459c cmp ip, r3 + 83746: d107 bne.n 83758 <_malloc_r+0x140> + 83748: e135 b.n 839b6 <_malloc_r+0x39e> + 8374a: 2900 cmp r1, #0 + 8374c: f280 8145 bge.w 839da <_malloc_r+0x3c2> + 83750: 68db ldr r3, [r3, #12] + 83752: 459c cmp ip, r3 + 83754: f000 812f beq.w 839b6 <_malloc_r+0x39e> + 83758: 685a ldr r2, [r3, #4] + 8375a: f022 0203 bic.w r2, r2, #3 + 8375e: 1b51 subs r1, r2, r5 + 83760: 290f cmp r1, #15 + 83762: ddf2 ble.n 8374a <_malloc_r+0x132> + 83764: 461c mov r4, r3 + 83766: 68da ldr r2, [r3, #12] + 83768: f854 cf08 ldr.w ip, [r4, #8]! + 8376c: f045 0901 orr.w r9, r5, #1 + 83770: f041 0801 orr.w r8, r1, #1 + 83774: 441d add r5, r3 + 83776: f8c3 9004 str.w r9, [r3, #4] + 8377a: 4630 mov r0, r6 + 8377c: f8cc 200c str.w r2, [ip, #12] + 83780: f8c2 c008 str.w ip, [r2, #8] + 83784: 617d str r5, [r7, #20] + 83786: 613d str r5, [r7, #16] + 83788: f8c5 e00c str.w lr, [r5, #12] + 8378c: f8c5 e008 str.w lr, [r5, #8] + 83790: f8c5 8004 str.w r8, [r5, #4] + 83794: 5069 str r1, [r5, r1] + 83796: f000 fa75 bl 83c84 <__malloc_unlock> + 8379a: e769 b.n 83670 <_malloc_r+0x58> + 8379c: 2400 movs r4, #0 + 8379e: 4620 mov r0, r4 + 837a0: 230c movs r3, #12 + 837a2: 6033 str r3, [r6, #0] + 837a4: b003 add sp, #12 + 837a6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 837aa: 217e movs r1, #126 ; 0x7e + 837ac: 203f movs r0, #63 ; 0x3f + 837ae: e773 b.n 83698 <_malloc_r+0x80> + 837b0: 4423 add r3, r4 + 837b2: 685a ldr r2, [r3, #4] + 837b4: 68e1 ldr r1, [r4, #12] + 837b6: e751 b.n 8365c <_malloc_r+0x44> + 837b8: 4423 add r3, r4 + 837ba: 685a ldr r2, [r3, #4] + 837bc: 4630 mov r0, r6 + 837be: f042 0201 orr.w r2, r2, #1 + 837c2: 605a str r2, [r3, #4] + 837c4: 3408 adds r4, #8 + 837c6: f000 fa5d bl 83c84 <__malloc_unlock> + 837ca: 4620 mov r0, r4 + 837cc: b003 add sp, #12 + 837ce: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 837d2: 68bc ldr r4, [r7, #8] + 837d4: 6863 ldr r3, [r4, #4] + 837d6: f023 0803 bic.w r8, r3, #3 + 837da: 4545 cmp r5, r8 + 837dc: d804 bhi.n 837e8 <_malloc_r+0x1d0> + 837de: ebc5 0308 rsb r3, r5, r8 + 837e2: 2b0f cmp r3, #15 + 837e4: f300 808c bgt.w 83900 <_malloc_r+0x2e8> + 837e8: 4b53 ldr r3, [pc, #332] ; (83938 <_malloc_r+0x320>) + 837ea: f8df a15c ldr.w sl, [pc, #348] ; 83948 <_malloc_r+0x330> + 837ee: 681a ldr r2, [r3, #0] + 837f0: f8da 3000 ldr.w r3, [sl] + 837f4: 442a add r2, r5 + 837f6: 3301 adds r3, #1 + 837f8: eb04 0b08 add.w fp, r4, r8 + 837fc: f000 8151 beq.w 83aa2 <_malloc_r+0x48a> + 83800: f502 5280 add.w r2, r2, #4096 ; 0x1000 + 83804: 320f adds r2, #15 + 83806: f422 627f bic.w r2, r2, #4080 ; 0xff0 + 8380a: f022 020f bic.w r2, r2, #15 + 8380e: 4611 mov r1, r2 + 83810: 4630 mov r0, r6 + 83812: 9201 str r2, [sp, #4] + 83814: f000 fc28 bl 84068 <_sbrk_r> + 83818: f1b0 3fff cmp.w r0, #4294967295 + 8381c: 4681 mov r9, r0 + 8381e: 9a01 ldr r2, [sp, #4] + 83820: f000 8148 beq.w 83ab4 <_malloc_r+0x49c> + 83824: 4583 cmp fp, r0 + 83826: f200 80ef bhi.w 83a08 <_malloc_r+0x3f0> + 8382a: 4b44 ldr r3, [pc, #272] ; (8393c <_malloc_r+0x324>) + 8382c: 45cb cmp fp, r9 + 8382e: 6819 ldr r1, [r3, #0] + 83830: 4411 add r1, r2 + 83832: 6019 str r1, [r3, #0] + 83834: f000 8143 beq.w 83abe <_malloc_r+0x4a6> + 83838: f8da 0000 ldr.w r0, [sl] + 8383c: f8df e108 ldr.w lr, [pc, #264] ; 83948 <_malloc_r+0x330> + 83840: 3001 adds r0, #1 + 83842: bf1b ittet ne + 83844: ebcb 0b09 rsbne fp, fp, r9 + 83848: 4459 addne r1, fp + 8384a: f8ce 9000 streq.w r9, [lr] + 8384e: 6019 strne r1, [r3, #0] + 83850: f019 0107 ands.w r1, r9, #7 + 83854: f000 8108 beq.w 83a68 <_malloc_r+0x450> + 83858: f1c1 0008 rsb r0, r1, #8 + 8385c: f5c1 5180 rsb r1, r1, #4096 ; 0x1000 + 83860: 4481 add r9, r0 + 83862: 3108 adds r1, #8 + 83864: 444a add r2, r9 + 83866: f3c2 020b ubfx r2, r2, #0, #12 + 8386a: ebc2 0a01 rsb sl, r2, r1 + 8386e: 4651 mov r1, sl + 83870: 4630 mov r0, r6 + 83872: 9301 str r3, [sp, #4] + 83874: f000 fbf8 bl 84068 <_sbrk_r> + 83878: 1c43 adds r3, r0, #1 + 8387a: 9b01 ldr r3, [sp, #4] + 8387c: f000 812d beq.w 83ada <_malloc_r+0x4c2> + 83880: ebc9 0200 rsb r2, r9, r0 + 83884: 4452 add r2, sl + 83886: f042 0201 orr.w r2, r2, #1 + 8388a: 6819 ldr r1, [r3, #0] + 8388c: 42bc cmp r4, r7 + 8388e: 4451 add r1, sl + 83890: f8c7 9008 str.w r9, [r7, #8] + 83894: 6019 str r1, [r3, #0] + 83896: f8c9 2004 str.w r2, [r9, #4] + 8389a: f8df a0a0 ldr.w sl, [pc, #160] ; 8393c <_malloc_r+0x324> + 8389e: d016 beq.n 838ce <_malloc_r+0x2b6> + 838a0: f1b8 0f0f cmp.w r8, #15 + 838a4: f240 80ef bls.w 83a86 <_malloc_r+0x46e> + 838a8: 6862 ldr r2, [r4, #4] + 838aa: f1a8 030c sub.w r3, r8, #12 + 838ae: f023 0307 bic.w r3, r3, #7 + 838b2: f002 0201 and.w r2, r2, #1 + 838b6: 18e0 adds r0, r4, r3 + 838b8: f04f 0e05 mov.w lr, #5 + 838bc: 431a orrs r2, r3 + 838be: 2b0f cmp r3, #15 + 838c0: 6062 str r2, [r4, #4] + 838c2: f8c0 e004 str.w lr, [r0, #4] + 838c6: f8c0 e008 str.w lr, [r0, #8] + 838ca: f200 810a bhi.w 83ae2 <_malloc_r+0x4ca> + 838ce: 4b1c ldr r3, [pc, #112] ; (83940 <_malloc_r+0x328>) + 838d0: 68bc ldr r4, [r7, #8] + 838d2: 681a ldr r2, [r3, #0] + 838d4: 4291 cmp r1, r2 + 838d6: bf88 it hi + 838d8: 6019 strhi r1, [r3, #0] + 838da: 4b1a ldr r3, [pc, #104] ; (83944 <_malloc_r+0x32c>) + 838dc: 681a ldr r2, [r3, #0] + 838de: 4291 cmp r1, r2 + 838e0: 6862 ldr r2, [r4, #4] + 838e2: bf88 it hi + 838e4: 6019 strhi r1, [r3, #0] + 838e6: f022 0203 bic.w r2, r2, #3 + 838ea: 4295 cmp r5, r2 + 838ec: eba2 0305 sub.w r3, r2, r5 + 838f0: d801 bhi.n 838f6 <_malloc_r+0x2de> + 838f2: 2b0f cmp r3, #15 + 838f4: dc04 bgt.n 83900 <_malloc_r+0x2e8> + 838f6: 4630 mov r0, r6 + 838f8: f000 f9c4 bl 83c84 <__malloc_unlock> + 838fc: 2400 movs r4, #0 + 838fe: e6b7 b.n 83670 <_malloc_r+0x58> + 83900: f045 0201 orr.w r2, r5, #1 + 83904: f043 0301 orr.w r3, r3, #1 + 83908: 4425 add r5, r4 + 8390a: 6062 str r2, [r4, #4] + 8390c: 4630 mov r0, r6 + 8390e: 60bd str r5, [r7, #8] + 83910: 3408 adds r4, #8 + 83912: 606b str r3, [r5, #4] + 83914: f000 f9b6 bl 83c84 <__malloc_unlock> + 83918: 4620 mov r0, r4 + 8391a: b003 add sp, #12 + 8391c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 83920: 2814 cmp r0, #20 + 83922: d969 bls.n 839f8 <_malloc_r+0x3e0> + 83924: 2854 cmp r0, #84 ; 0x54 + 83926: f200 8098 bhi.w 83a5a <_malloc_r+0x442> + 8392a: 0b28 lsrs r0, r5, #12 + 8392c: 306e adds r0, #110 ; 0x6e + 8392e: 0041 lsls r1, r0, #1 + 83930: e6b2 b.n 83698 <_malloc_r+0x80> + 83932: bf00 nop + 83934: 20070580 .word 0x20070580 + 83938: 200748b0 .word 0x200748b0 + 8393c: 200748b4 .word 0x200748b4 + 83940: 200748ac .word 0x200748ac + 83944: 200748a8 .word 0x200748a8 + 83948: 2007098c .word 0x2007098c + 8394c: 0a5a lsrs r2, r3, #9 + 8394e: 2a04 cmp r2, #4 + 83950: d955 bls.n 839fe <_malloc_r+0x3e6> + 83952: 2a14 cmp r2, #20 + 83954: f200 80a7 bhi.w 83aa6 <_malloc_r+0x48e> + 83958: 325b adds r2, #91 ; 0x5b + 8395a: ea4f 0c42 mov.w ip, r2, lsl #1 + 8395e: eb07 0c8c add.w ip, r7, ip, lsl #2 + 83962: f8dc 1008 ldr.w r1, [ip, #8] + 83966: f8df 81b8 ldr.w r8, [pc, #440] ; 83b20 <_malloc_r+0x508> + 8396a: 4561 cmp r1, ip + 8396c: d07f beq.n 83a6e <_malloc_r+0x456> + 8396e: 684a ldr r2, [r1, #4] + 83970: f022 0203 bic.w r2, r2, #3 + 83974: 4293 cmp r3, r2 + 83976: d202 bcs.n 8397e <_malloc_r+0x366> + 83978: 6889 ldr r1, [r1, #8] + 8397a: 458c cmp ip, r1 + 8397c: d1f7 bne.n 8396e <_malloc_r+0x356> + 8397e: 68ca ldr r2, [r1, #12] + 83980: 687b ldr r3, [r7, #4] + 83982: 60e2 str r2, [r4, #12] + 83984: 60a1 str r1, [r4, #8] + 83986: 6094 str r4, [r2, #8] + 83988: 60cc str r4, [r1, #12] + 8398a: e6c7 b.n 8371c <_malloc_r+0x104> + 8398c: f045 0701 orr.w r7, r5, #1 + 83990: f042 0301 orr.w r3, r2, #1 + 83994: 4425 add r5, r4 + 83996: 6067 str r7, [r4, #4] + 83998: 4630 mov r0, r6 + 8399a: 614d str r5, [r1, #20] + 8399c: 610d str r5, [r1, #16] + 8399e: f8c5 e00c str.w lr, [r5, #12] + 839a2: f8c5 e008 str.w lr, [r5, #8] + 839a6: 606b str r3, [r5, #4] + 839a8: 50aa str r2, [r5, r2] + 839aa: 3408 adds r4, #8 + 839ac: f000 f96a bl 83c84 <__malloc_unlock> + 839b0: e65e b.n 83670 <_malloc_r+0x58> + 839b2: 684b ldr r3, [r1, #4] + 839b4: e6b2 b.n 8371c <_malloc_r+0x104> + 839b6: f109 0901 add.w r9, r9, #1 + 839ba: f019 0f03 tst.w r9, #3 + 839be: f10c 0c08 add.w ip, ip, #8 + 839c2: f47f aebd bne.w 83740 <_malloc_r+0x128> + 839c6: e02c b.n 83a22 <_malloc_r+0x40a> + 839c8: f104 0308 add.w r3, r4, #8 + 839cc: 6964 ldr r4, [r4, #20] + 839ce: 42a3 cmp r3, r4 + 839d0: bf08 it eq + 839d2: 3002 addeq r0, #2 + 839d4: f43f ae75 beq.w 836c2 <_malloc_r+0xaa> + 839d8: e63a b.n 83650 <_malloc_r+0x38> + 839da: 461c mov r4, r3 + 839dc: 441a add r2, r3 + 839de: 6851 ldr r1, [r2, #4] + 839e0: 68db ldr r3, [r3, #12] + 839e2: f854 5f08 ldr.w r5, [r4, #8]! + 839e6: f041 0101 orr.w r1, r1, #1 + 839ea: 6051 str r1, [r2, #4] + 839ec: 4630 mov r0, r6 + 839ee: 60eb str r3, [r5, #12] + 839f0: 609d str r5, [r3, #8] + 839f2: f000 f947 bl 83c84 <__malloc_unlock> + 839f6: e63b b.n 83670 <_malloc_r+0x58> + 839f8: 305b adds r0, #91 ; 0x5b + 839fa: 0041 lsls r1, r0, #1 + 839fc: e64c b.n 83698 <_malloc_r+0x80> + 839fe: 099a lsrs r2, r3, #6 + 83a00: 3238 adds r2, #56 ; 0x38 + 83a02: ea4f 0c42 mov.w ip, r2, lsl #1 + 83a06: e7aa b.n 8395e <_malloc_r+0x346> + 83a08: 42bc cmp r4, r7 + 83a0a: 4b45 ldr r3, [pc, #276] ; (83b20 <_malloc_r+0x508>) + 83a0c: f43f af0d beq.w 8382a <_malloc_r+0x212> + 83a10: 689c ldr r4, [r3, #8] + 83a12: 6862 ldr r2, [r4, #4] + 83a14: f022 0203 bic.w r2, r2, #3 + 83a18: e767 b.n 838ea <_malloc_r+0x2d2> + 83a1a: f8d8 8000 ldr.w r8, [r8] + 83a1e: 4598 cmp r8, r3 + 83a20: d17c bne.n 83b1c <_malloc_r+0x504> + 83a22: f010 0f03 tst.w r0, #3 + 83a26: f1a8 0308 sub.w r3, r8, #8 + 83a2a: f100 30ff add.w r0, r0, #4294967295 + 83a2e: d1f4 bne.n 83a1a <_malloc_r+0x402> + 83a30: 687b ldr r3, [r7, #4] + 83a32: ea23 0304 bic.w r3, r3, r4 + 83a36: 607b str r3, [r7, #4] + 83a38: 0064 lsls r4, r4, #1 + 83a3a: 429c cmp r4, r3 + 83a3c: f63f aec9 bhi.w 837d2 <_malloc_r+0x1ba> + 83a40: 2c00 cmp r4, #0 + 83a42: f43f aec6 beq.w 837d2 <_malloc_r+0x1ba> + 83a46: 4223 tst r3, r4 + 83a48: 4648 mov r0, r9 + 83a4a: f47f ae75 bne.w 83738 <_malloc_r+0x120> + 83a4e: 0064 lsls r4, r4, #1 + 83a50: 4223 tst r3, r4 + 83a52: f100 0004 add.w r0, r0, #4 + 83a56: d0fa beq.n 83a4e <_malloc_r+0x436> + 83a58: e66e b.n 83738 <_malloc_r+0x120> + 83a5a: f5b0 7faa cmp.w r0, #340 ; 0x154 + 83a5e: d818 bhi.n 83a92 <_malloc_r+0x47a> + 83a60: 0be8 lsrs r0, r5, #15 + 83a62: 3077 adds r0, #119 ; 0x77 + 83a64: 0041 lsls r1, r0, #1 + 83a66: e617 b.n 83698 <_malloc_r+0x80> + 83a68: f44f 5180 mov.w r1, #4096 ; 0x1000 + 83a6c: e6fa b.n 83864 <_malloc_r+0x24c> + 83a6e: f8d8 3004 ldr.w r3, [r8, #4] + 83a72: 1092 asrs r2, r2, #2 + 83a74: f04f 0c01 mov.w ip, #1 + 83a78: fa0c f202 lsl.w r2, ip, r2 + 83a7c: 4313 orrs r3, r2 + 83a7e: f8c8 3004 str.w r3, [r8, #4] + 83a82: 460a mov r2, r1 + 83a84: e77d b.n 83982 <_malloc_r+0x36a> + 83a86: 2301 movs r3, #1 + 83a88: f8c9 3004 str.w r3, [r9, #4] + 83a8c: 464c mov r4, r9 + 83a8e: 2200 movs r2, #0 + 83a90: e72b b.n 838ea <_malloc_r+0x2d2> + 83a92: f240 5354 movw r3, #1364 ; 0x554 + 83a96: 4298 cmp r0, r3 + 83a98: d81c bhi.n 83ad4 <_malloc_r+0x4bc> + 83a9a: 0ca8 lsrs r0, r5, #18 + 83a9c: 307c adds r0, #124 ; 0x7c + 83a9e: 0041 lsls r1, r0, #1 + 83aa0: e5fa b.n 83698 <_malloc_r+0x80> + 83aa2: 3210 adds r2, #16 + 83aa4: e6b3 b.n 8380e <_malloc_r+0x1f6> + 83aa6: 2a54 cmp r2, #84 ; 0x54 + 83aa8: d823 bhi.n 83af2 <_malloc_r+0x4da> + 83aaa: 0b1a lsrs r2, r3, #12 + 83aac: 326e adds r2, #110 ; 0x6e + 83aae: ea4f 0c42 mov.w ip, r2, lsl #1 + 83ab2: e754 b.n 8395e <_malloc_r+0x346> + 83ab4: 68bc ldr r4, [r7, #8] + 83ab6: 6862 ldr r2, [r4, #4] + 83ab8: f022 0203 bic.w r2, r2, #3 + 83abc: e715 b.n 838ea <_malloc_r+0x2d2> + 83abe: f3cb 000b ubfx r0, fp, #0, #12 + 83ac2: 2800 cmp r0, #0 + 83ac4: f47f aeb8 bne.w 83838 <_malloc_r+0x220> + 83ac8: 4442 add r2, r8 + 83aca: 68bb ldr r3, [r7, #8] + 83acc: f042 0201 orr.w r2, r2, #1 + 83ad0: 605a str r2, [r3, #4] + 83ad2: e6fc b.n 838ce <_malloc_r+0x2b6> + 83ad4: 21fc movs r1, #252 ; 0xfc + 83ad6: 207e movs r0, #126 ; 0x7e + 83ad8: e5de b.n 83698 <_malloc_r+0x80> + 83ada: 2201 movs r2, #1 + 83adc: f04f 0a00 mov.w sl, #0 + 83ae0: e6d3 b.n 8388a <_malloc_r+0x272> + 83ae2: f104 0108 add.w r1, r4, #8 + 83ae6: 4630 mov r0, r6 + 83ae8: f7ff fa84 bl 82ff4 <_free_r> + 83aec: f8da 1000 ldr.w r1, [sl] + 83af0: e6ed b.n 838ce <_malloc_r+0x2b6> + 83af2: f5b2 7faa cmp.w r2, #340 ; 0x154 + 83af6: d804 bhi.n 83b02 <_malloc_r+0x4ea> + 83af8: 0bda lsrs r2, r3, #15 + 83afa: 3277 adds r2, #119 ; 0x77 + 83afc: ea4f 0c42 mov.w ip, r2, lsl #1 + 83b00: e72d b.n 8395e <_malloc_r+0x346> + 83b02: f240 5154 movw r1, #1364 ; 0x554 + 83b06: 428a cmp r2, r1 + 83b08: d804 bhi.n 83b14 <_malloc_r+0x4fc> + 83b0a: 0c9a lsrs r2, r3, #18 + 83b0c: 327c adds r2, #124 ; 0x7c + 83b0e: ea4f 0c42 mov.w ip, r2, lsl #1 + 83b12: e724 b.n 8395e <_malloc_r+0x346> + 83b14: f04f 0cfc mov.w ip, #252 ; 0xfc + 83b18: 227e movs r2, #126 ; 0x7e + 83b1a: e720 b.n 8395e <_malloc_r+0x346> + 83b1c: 687b ldr r3, [r7, #4] + 83b1e: e78b b.n 83a38 <_malloc_r+0x420> + 83b20: 20070580 .word 0x20070580 + +00083b24 : + 83b24: 0783 lsls r3, r0, #30 + 83b26: b470 push {r4, r5, r6} + 83b28: b2c9 uxtb r1, r1 + 83b2a: d040 beq.n 83bae + 83b2c: 1e54 subs r4, r2, #1 + 83b2e: 2a00 cmp r2, #0 + 83b30: d03f beq.n 83bb2 + 83b32: 7803 ldrb r3, [r0, #0] + 83b34: 428b cmp r3, r1 + 83b36: bf18 it ne + 83b38: 1c43 addne r3, r0, #1 + 83b3a: d105 bne.n 83b48 + 83b3c: e01c b.n 83b78 + 83b3e: b1ec cbz r4, 83b7c + 83b40: 7802 ldrb r2, [r0, #0] + 83b42: 3c01 subs r4, #1 + 83b44: 428a cmp r2, r1 + 83b46: d017 beq.n 83b78 + 83b48: f013 0f03 tst.w r3, #3 + 83b4c: 4618 mov r0, r3 + 83b4e: f103 0301 add.w r3, r3, #1 + 83b52: d1f4 bne.n 83b3e + 83b54: 2c03 cmp r4, #3 + 83b56: d814 bhi.n 83b82 + 83b58: b184 cbz r4, 83b7c + 83b5a: 7803 ldrb r3, [r0, #0] + 83b5c: 428b cmp r3, r1 + 83b5e: d00b beq.n 83b78 + 83b60: 1905 adds r5, r0, r4 + 83b62: 1c43 adds r3, r0, #1 + 83b64: e002 b.n 83b6c + 83b66: 7802 ldrb r2, [r0, #0] + 83b68: 428a cmp r2, r1 + 83b6a: d005 beq.n 83b78 + 83b6c: 42ab cmp r3, r5 + 83b6e: 4618 mov r0, r3 + 83b70: f103 0301 add.w r3, r3, #1 + 83b74: d1f7 bne.n 83b66 + 83b76: 2000 movs r0, #0 + 83b78: bc70 pop {r4, r5, r6} + 83b7a: 4770 bx lr + 83b7c: 4620 mov r0, r4 + 83b7e: bc70 pop {r4, r5, r6} + 83b80: 4770 bx lr + 83b82: 4602 mov r2, r0 + 83b84: ea41 2601 orr.w r6, r1, r1, lsl #8 + 83b88: ea46 4606 orr.w r6, r6, r6, lsl #16 + 83b8c: 6813 ldr r3, [r2, #0] + 83b8e: 4610 mov r0, r2 + 83b90: 4073 eors r3, r6 + 83b92: f1a3 3501 sub.w r5, r3, #16843009 ; 0x1010101 + 83b96: ea25 0303 bic.w r3, r5, r3 + 83b9a: f013 3f80 tst.w r3, #2155905152 ; 0x80808080 + 83b9e: f102 0204 add.w r2, r2, #4 + 83ba2: d1d9 bne.n 83b58 + 83ba4: 3c04 subs r4, #4 + 83ba6: 2c03 cmp r4, #3 + 83ba8: 4610 mov r0, r2 + 83baa: d8ef bhi.n 83b8c + 83bac: e7d4 b.n 83b58 + 83bae: 4614 mov r4, r2 + 83bb0: e7d0 b.n 83b54 + 83bb2: 4610 mov r0, r2 + 83bb4: e7e0 b.n 83b78 + 83bb6: bf00 nop + +00083bb8 : + 83bb8: 4288 cmp r0, r1 + 83bba: b5f0 push {r4, r5, r6, r7, lr} + 83bbc: d90d bls.n 83bda + 83bbe: 188b adds r3, r1, r2 + 83bc0: 4298 cmp r0, r3 + 83bc2: d20a bcs.n 83bda + 83bc4: 1881 adds r1, r0, r2 + 83bc6: 2a00 cmp r2, #0 + 83bc8: d054 beq.n 83c74 + 83bca: 1a9a subs r2, r3, r2 + 83bcc: f813 4d01 ldrb.w r4, [r3, #-1]! + 83bd0: 4293 cmp r3, r2 + 83bd2: f801 4d01 strb.w r4, [r1, #-1]! + 83bd6: d1f9 bne.n 83bcc + 83bd8: bdf0 pop {r4, r5, r6, r7, pc} + 83bda: 2a0f cmp r2, #15 + 83bdc: d948 bls.n 83c70 + 83bde: ea40 0301 orr.w r3, r0, r1 + 83be2: 079b lsls r3, r3, #30 + 83be4: d147 bne.n 83c76 + 83be6: 4615 mov r5, r2 + 83be8: f100 0410 add.w r4, r0, #16 + 83bec: f101 0310 add.w r3, r1, #16 + 83bf0: f853 6c10 ldr.w r6, [r3, #-16] + 83bf4: 3d10 subs r5, #16 + 83bf6: f844 6c10 str.w r6, [r4, #-16] + 83bfa: f853 6c0c ldr.w r6, [r3, #-12] + 83bfe: 2d0f cmp r5, #15 + 83c00: f844 6c0c str.w r6, [r4, #-12] + 83c04: f853 6c08 ldr.w r6, [r3, #-8] + 83c08: f104 0410 add.w r4, r4, #16 + 83c0c: f844 6c18 str.w r6, [r4, #-24] + 83c10: f853 6c04 ldr.w r6, [r3, #-4] + 83c14: f103 0310 add.w r3, r3, #16 + 83c18: f844 6c14 str.w r6, [r4, #-20] + 83c1c: d8e8 bhi.n 83bf0 + 83c1e: f1a2 0310 sub.w r3, r2, #16 + 83c22: f023 030f bic.w r3, r3, #15 + 83c26: f002 0e0f and.w lr, r2, #15 + 83c2a: 3310 adds r3, #16 + 83c2c: f1be 0f03 cmp.w lr, #3 + 83c30: 4419 add r1, r3 + 83c32: 4403 add r3, r0 + 83c34: d921 bls.n 83c7a + 83c36: 460e mov r6, r1 + 83c38: 4674 mov r4, lr + 83c3a: 1f1d subs r5, r3, #4 + 83c3c: f856 7b04 ldr.w r7, [r6], #4 + 83c40: 3c04 subs r4, #4 + 83c42: 2c03 cmp r4, #3 + 83c44: f845 7f04 str.w r7, [r5, #4]! + 83c48: d8f8 bhi.n 83c3c + 83c4a: f1ae 0404 sub.w r4, lr, #4 + 83c4e: f024 0403 bic.w r4, r4, #3 + 83c52: 3404 adds r4, #4 + 83c54: 4423 add r3, r4 + 83c56: 4421 add r1, r4 + 83c58: f002 0203 and.w r2, r2, #3 + 83c5c: b152 cbz r2, 83c74 + 83c5e: 3b01 subs r3, #1 + 83c60: 440a add r2, r1 + 83c62: f811 4b01 ldrb.w r4, [r1], #1 + 83c66: 4291 cmp r1, r2 + 83c68: f803 4f01 strb.w r4, [r3, #1]! + 83c6c: d1f9 bne.n 83c62 + 83c6e: bdf0 pop {r4, r5, r6, r7, pc} + 83c70: 4603 mov r3, r0 + 83c72: e7f3 b.n 83c5c + 83c74: bdf0 pop {r4, r5, r6, r7, pc} + 83c76: 4603 mov r3, r0 + 83c78: e7f1 b.n 83c5e + 83c7a: 4672 mov r2, lr + 83c7c: e7ee b.n 83c5c + 83c7e: bf00 nop + +00083c80 <__malloc_lock>: + 83c80: 4770 bx lr + 83c82: bf00 nop + +00083c84 <__malloc_unlock>: + 83c84: 4770 bx lr + 83c86: bf00 nop + +00083c88 <_realloc_r>: + 83c88: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 83c8c: 4617 mov r7, r2 + 83c8e: b083 sub sp, #12 + 83c90: 460d mov r5, r1 + 83c92: 2900 cmp r1, #0 + 83c94: f000 80e2 beq.w 83e5c <_realloc_r+0x1d4> + 83c98: 4681 mov r9, r0 + 83c9a: f107 040b add.w r4, r7, #11 + 83c9e: f7ff ffef bl 83c80 <__malloc_lock> + 83ca2: f855 3c04 ldr.w r3, [r5, #-4] + 83ca6: 2c16 cmp r4, #22 + 83ca8: f023 0603 bic.w r6, r3, #3 + 83cac: f1a5 0808 sub.w r8, r5, #8 + 83cb0: d84b bhi.n 83d4a <_realloc_r+0xc2> + 83cb2: 2210 movs r2, #16 + 83cb4: 4614 mov r4, r2 + 83cb6: 42a7 cmp r7, r4 + 83cb8: d84c bhi.n 83d54 <_realloc_r+0xcc> + 83cba: 4296 cmp r6, r2 + 83cbc: da51 bge.n 83d62 <_realloc_r+0xda> + 83cbe: f8df b3a4 ldr.w fp, [pc, #932] ; 84064 <_realloc_r+0x3dc> + 83cc2: eb08 0106 add.w r1, r8, r6 + 83cc6: f8db 0008 ldr.w r0, [fp, #8] + 83cca: 4288 cmp r0, r1 + 83ccc: f000 80d3 beq.w 83e76 <_realloc_r+0x1ee> + 83cd0: 6848 ldr r0, [r1, #4] + 83cd2: f020 0e01 bic.w lr, r0, #1 + 83cd6: 448e add lr, r1 + 83cd8: f8de e004 ldr.w lr, [lr, #4] + 83cdc: f01e 0f01 tst.w lr, #1 + 83ce0: d154 bne.n 83d8c <_realloc_r+0x104> + 83ce2: f020 0003 bic.w r0, r0, #3 + 83ce6: 4430 add r0, r6 + 83ce8: 4290 cmp r0, r2 + 83cea: f280 80bd bge.w 83e68 <_realloc_r+0x1e0> + 83cee: 07db lsls r3, r3, #31 + 83cf0: f100 8090 bmi.w 83e14 <_realloc_r+0x18c> + 83cf4: f855 3c08 ldr.w r3, [r5, #-8] + 83cf8: ebc3 0a08 rsb sl, r3, r8 + 83cfc: f8da 3004 ldr.w r3, [sl, #4] + 83d00: f023 0303 bic.w r3, r3, #3 + 83d04: eb00 0e03 add.w lr, r0, r3 + 83d08: 4596 cmp lr, r2 + 83d0a: db49 blt.n 83da0 <_realloc_r+0x118> + 83d0c: 4657 mov r7, sl + 83d0e: 68cb ldr r3, [r1, #12] + 83d10: 6889 ldr r1, [r1, #8] + 83d12: 1f32 subs r2, r6, #4 + 83d14: 60cb str r3, [r1, #12] + 83d16: 6099 str r1, [r3, #8] + 83d18: f857 1f08 ldr.w r1, [r7, #8]! + 83d1c: f8da 300c ldr.w r3, [sl, #12] + 83d20: 2a24 cmp r2, #36 ; 0x24 + 83d22: 60cb str r3, [r1, #12] + 83d24: 6099 str r1, [r3, #8] + 83d26: f200 8133 bhi.w 83f90 <_realloc_r+0x308> + 83d2a: 2a13 cmp r2, #19 + 83d2c: f240 80fa bls.w 83f24 <_realloc_r+0x29c> + 83d30: 682b ldr r3, [r5, #0] + 83d32: 2a1b cmp r2, #27 + 83d34: f8ca 3008 str.w r3, [sl, #8] + 83d38: 686b ldr r3, [r5, #4] + 83d3a: f8ca 300c str.w r3, [sl, #12] + 83d3e: f200 813b bhi.w 83fb8 <_realloc_r+0x330> + 83d42: 3508 adds r5, #8 + 83d44: f10a 0310 add.w r3, sl, #16 + 83d48: e0ed b.n 83f26 <_realloc_r+0x29e> + 83d4a: f024 0407 bic.w r4, r4, #7 + 83d4e: 2c00 cmp r4, #0 + 83d50: 4622 mov r2, r4 + 83d52: dab0 bge.n 83cb6 <_realloc_r+0x2e> + 83d54: 230c movs r3, #12 + 83d56: 2000 movs r0, #0 + 83d58: f8c9 3000 str.w r3, [r9] + 83d5c: b003 add sp, #12 + 83d5e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 83d62: 462f mov r7, r5 + 83d64: 1b32 subs r2, r6, r4 + 83d66: 2a0f cmp r2, #15 + 83d68: f003 0301 and.w r3, r3, #1 + 83d6c: d840 bhi.n 83df0 <_realloc_r+0x168> + 83d6e: 4333 orrs r3, r6 + 83d70: f8c8 3004 str.w r3, [r8, #4] + 83d74: 4446 add r6, r8 + 83d76: 6873 ldr r3, [r6, #4] + 83d78: f043 0301 orr.w r3, r3, #1 + 83d7c: 6073 str r3, [r6, #4] + 83d7e: 4648 mov r0, r9 + 83d80: f7ff ff80 bl 83c84 <__malloc_unlock> + 83d84: 4638 mov r0, r7 + 83d86: b003 add sp, #12 + 83d88: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 83d8c: 07d9 lsls r1, r3, #31 + 83d8e: d441 bmi.n 83e14 <_realloc_r+0x18c> + 83d90: f855 3c08 ldr.w r3, [r5, #-8] + 83d94: ebc3 0a08 rsb sl, r3, r8 + 83d98: f8da 3004 ldr.w r3, [sl, #4] + 83d9c: f023 0303 bic.w r3, r3, #3 + 83da0: 4433 add r3, r6 + 83da2: 4293 cmp r3, r2 + 83da4: db36 blt.n 83e14 <_realloc_r+0x18c> + 83da6: 4657 mov r7, sl + 83da8: f8da 100c ldr.w r1, [sl, #12] + 83dac: f857 0f08 ldr.w r0, [r7, #8]! + 83db0: 1f32 subs r2, r6, #4 + 83db2: 2a24 cmp r2, #36 ; 0x24 + 83db4: 60c1 str r1, [r0, #12] + 83db6: 6088 str r0, [r1, #8] + 83db8: f200 80f5 bhi.w 83fa6 <_realloc_r+0x31e> + 83dbc: 2a13 cmp r2, #19 + 83dbe: f240 80f0 bls.w 83fa2 <_realloc_r+0x31a> + 83dc2: 6829 ldr r1, [r5, #0] + 83dc4: 2a1b cmp r2, #27 + 83dc6: f8ca 1008 str.w r1, [sl, #8] + 83dca: 6869 ldr r1, [r5, #4] + 83dcc: f8ca 100c str.w r1, [sl, #12] + 83dd0: f200 8107 bhi.w 83fe2 <_realloc_r+0x35a> + 83dd4: 3508 adds r5, #8 + 83dd6: f10a 0210 add.w r2, sl, #16 + 83dda: 6829 ldr r1, [r5, #0] + 83ddc: 461e mov r6, r3 + 83dde: 6011 str r1, [r2, #0] + 83de0: 6869 ldr r1, [r5, #4] + 83de2: 46d0 mov r8, sl + 83de4: 6051 str r1, [r2, #4] + 83de6: 68ab ldr r3, [r5, #8] + 83de8: 6093 str r3, [r2, #8] + 83dea: f8da 3004 ldr.w r3, [sl, #4] + 83dee: e7b9 b.n 83d64 <_realloc_r+0xdc> + 83df0: eb08 0104 add.w r1, r8, r4 + 83df4: 4323 orrs r3, r4 + 83df6: f042 0001 orr.w r0, r2, #1 + 83dfa: f8c8 3004 str.w r3, [r8, #4] + 83dfe: 440a add r2, r1 + 83e00: 6048 str r0, [r1, #4] + 83e02: 6853 ldr r3, [r2, #4] + 83e04: 3108 adds r1, #8 + 83e06: f043 0301 orr.w r3, r3, #1 + 83e0a: 6053 str r3, [r2, #4] + 83e0c: 4648 mov r0, r9 + 83e0e: f7ff f8f1 bl 82ff4 <_free_r> + 83e12: e7b4 b.n 83d7e <_realloc_r+0xf6> + 83e14: 4639 mov r1, r7 + 83e16: 4648 mov r0, r9 + 83e18: f7ff fbfe bl 83618 <_malloc_r> + 83e1c: 4607 mov r7, r0 + 83e1e: 2800 cmp r0, #0 + 83e20: d0ad beq.n 83d7e <_realloc_r+0xf6> + 83e22: f855 3c04 ldr.w r3, [r5, #-4] + 83e26: f1a0 0108 sub.w r1, r0, #8 + 83e2a: f023 0201 bic.w r2, r3, #1 + 83e2e: 4442 add r2, r8 + 83e30: 4291 cmp r1, r2 + 83e32: f000 80a6 beq.w 83f82 <_realloc_r+0x2fa> + 83e36: 1f32 subs r2, r6, #4 + 83e38: 2a24 cmp r2, #36 ; 0x24 + 83e3a: f200 8093 bhi.w 83f64 <_realloc_r+0x2dc> + 83e3e: 2a13 cmp r2, #19 + 83e40: d865 bhi.n 83f0e <_realloc_r+0x286> + 83e42: 4603 mov r3, r0 + 83e44: 462a mov r2, r5 + 83e46: 6811 ldr r1, [r2, #0] + 83e48: 6019 str r1, [r3, #0] + 83e4a: 6851 ldr r1, [r2, #4] + 83e4c: 6059 str r1, [r3, #4] + 83e4e: 6892 ldr r2, [r2, #8] + 83e50: 609a str r2, [r3, #8] + 83e52: 4629 mov r1, r5 + 83e54: 4648 mov r0, r9 + 83e56: f7ff f8cd bl 82ff4 <_free_r> + 83e5a: e790 b.n 83d7e <_realloc_r+0xf6> + 83e5c: 4611 mov r1, r2 + 83e5e: b003 add sp, #12 + 83e60: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 83e64: f7ff bbd8 b.w 83618 <_malloc_r> + 83e68: 68ca ldr r2, [r1, #12] + 83e6a: 6889 ldr r1, [r1, #8] + 83e6c: 462f mov r7, r5 + 83e6e: 60ca str r2, [r1, #12] + 83e70: 4606 mov r6, r0 + 83e72: 6091 str r1, [r2, #8] + 83e74: e776 b.n 83d64 <_realloc_r+0xdc> + 83e76: 6841 ldr r1, [r0, #4] + 83e78: f104 0010 add.w r0, r4, #16 + 83e7c: f021 0103 bic.w r1, r1, #3 + 83e80: 4431 add r1, r6 + 83e82: 4281 cmp r1, r0 + 83e84: da5a bge.n 83f3c <_realloc_r+0x2b4> + 83e86: 07db lsls r3, r3, #31 + 83e88: d4c4 bmi.n 83e14 <_realloc_r+0x18c> + 83e8a: f855 3c08 ldr.w r3, [r5, #-8] + 83e8e: ebc3 0a08 rsb sl, r3, r8 + 83e92: f8da 3004 ldr.w r3, [sl, #4] + 83e96: f023 0303 bic.w r3, r3, #3 + 83e9a: eb01 0c03 add.w ip, r1, r3 + 83e9e: 4560 cmp r0, ip + 83ea0: f73f af7e bgt.w 83da0 <_realloc_r+0x118> + 83ea4: 4657 mov r7, sl + 83ea6: f8da 300c ldr.w r3, [sl, #12] + 83eaa: f857 1f08 ldr.w r1, [r7, #8]! + 83eae: 1f32 subs r2, r6, #4 + 83eb0: 2a24 cmp r2, #36 ; 0x24 + 83eb2: 60cb str r3, [r1, #12] + 83eb4: 6099 str r1, [r3, #8] + 83eb6: f200 80b6 bhi.w 84026 <_realloc_r+0x39e> + 83eba: 2a13 cmp r2, #19 + 83ebc: f240 80a7 bls.w 8400e <_realloc_r+0x386> + 83ec0: 682b ldr r3, [r5, #0] + 83ec2: 2a1b cmp r2, #27 + 83ec4: f8ca 3008 str.w r3, [sl, #8] + 83ec8: 686b ldr r3, [r5, #4] + 83eca: f8ca 300c str.w r3, [sl, #12] + 83ece: f200 80b3 bhi.w 84038 <_realloc_r+0x3b0> + 83ed2: 3508 adds r5, #8 + 83ed4: f10a 0310 add.w r3, sl, #16 + 83ed8: 682a ldr r2, [r5, #0] + 83eda: 601a str r2, [r3, #0] + 83edc: 686a ldr r2, [r5, #4] + 83ede: 605a str r2, [r3, #4] + 83ee0: 68aa ldr r2, [r5, #8] + 83ee2: 609a str r2, [r3, #8] + 83ee4: ebc4 030c rsb r3, r4, ip + 83ee8: eb0a 0204 add.w r2, sl, r4 + 83eec: f043 0301 orr.w r3, r3, #1 + 83ef0: f8cb 2008 str.w r2, [fp, #8] + 83ef4: 6053 str r3, [r2, #4] + 83ef6: f8da 3004 ldr.w r3, [sl, #4] + 83efa: 4648 mov r0, r9 + 83efc: f003 0301 and.w r3, r3, #1 + 83f00: 431c orrs r4, r3 + 83f02: f8ca 4004 str.w r4, [sl, #4] + 83f06: f7ff febd bl 83c84 <__malloc_unlock> + 83f0a: 4638 mov r0, r7 + 83f0c: e73b b.n 83d86 <_realloc_r+0xfe> + 83f0e: 682b ldr r3, [r5, #0] + 83f10: 2a1b cmp r2, #27 + 83f12: 6003 str r3, [r0, #0] + 83f14: 686b ldr r3, [r5, #4] + 83f16: 6043 str r3, [r0, #4] + 83f18: d828 bhi.n 83f6c <_realloc_r+0x2e4> + 83f1a: f100 0308 add.w r3, r0, #8 + 83f1e: f105 0208 add.w r2, r5, #8 + 83f22: e790 b.n 83e46 <_realloc_r+0x1be> + 83f24: 463b mov r3, r7 + 83f26: 682a ldr r2, [r5, #0] + 83f28: 4676 mov r6, lr + 83f2a: 601a str r2, [r3, #0] + 83f2c: 686a ldr r2, [r5, #4] + 83f2e: 46d0 mov r8, sl + 83f30: 605a str r2, [r3, #4] + 83f32: 68aa ldr r2, [r5, #8] + 83f34: 609a str r2, [r3, #8] + 83f36: f8da 3004 ldr.w r3, [sl, #4] + 83f3a: e713 b.n 83d64 <_realloc_r+0xdc> + 83f3c: 1b0b subs r3, r1, r4 + 83f3e: eb08 0204 add.w r2, r8, r4 + 83f42: f043 0301 orr.w r3, r3, #1 + 83f46: f8cb 2008 str.w r2, [fp, #8] + 83f4a: 6053 str r3, [r2, #4] + 83f4c: f855 3c04 ldr.w r3, [r5, #-4] + 83f50: 4648 mov r0, r9 + 83f52: f003 0301 and.w r3, r3, #1 + 83f56: 431c orrs r4, r3 + 83f58: f845 4c04 str.w r4, [r5, #-4] + 83f5c: f7ff fe92 bl 83c84 <__malloc_unlock> + 83f60: 4628 mov r0, r5 + 83f62: e710 b.n 83d86 <_realloc_r+0xfe> + 83f64: 4629 mov r1, r5 + 83f66: f7ff fe27 bl 83bb8 + 83f6a: e772 b.n 83e52 <_realloc_r+0x1ca> + 83f6c: 68ab ldr r3, [r5, #8] + 83f6e: 2a24 cmp r2, #36 ; 0x24 + 83f70: 6083 str r3, [r0, #8] + 83f72: 68eb ldr r3, [r5, #12] + 83f74: 60c3 str r3, [r0, #12] + 83f76: d02b beq.n 83fd0 <_realloc_r+0x348> + 83f78: f100 0310 add.w r3, r0, #16 + 83f7c: f105 0210 add.w r2, r5, #16 + 83f80: e761 b.n 83e46 <_realloc_r+0x1be> + 83f82: f850 2c04 ldr.w r2, [r0, #-4] + 83f86: 462f mov r7, r5 + 83f88: f022 0203 bic.w r2, r2, #3 + 83f8c: 4416 add r6, r2 + 83f8e: e6e9 b.n 83d64 <_realloc_r+0xdc> + 83f90: 4629 mov r1, r5 + 83f92: 4638 mov r0, r7 + 83f94: 4676 mov r6, lr + 83f96: 46d0 mov r8, sl + 83f98: f7ff fe0e bl 83bb8 + 83f9c: f8da 3004 ldr.w r3, [sl, #4] + 83fa0: e6e0 b.n 83d64 <_realloc_r+0xdc> + 83fa2: 463a mov r2, r7 + 83fa4: e719 b.n 83dda <_realloc_r+0x152> + 83fa6: 4629 mov r1, r5 + 83fa8: 4638 mov r0, r7 + 83faa: 461e mov r6, r3 + 83fac: 46d0 mov r8, sl + 83fae: f7ff fe03 bl 83bb8 + 83fb2: f8da 3004 ldr.w r3, [sl, #4] + 83fb6: e6d5 b.n 83d64 <_realloc_r+0xdc> + 83fb8: 68ab ldr r3, [r5, #8] + 83fba: 2a24 cmp r2, #36 ; 0x24 + 83fbc: f8ca 3010 str.w r3, [sl, #16] + 83fc0: 68eb ldr r3, [r5, #12] + 83fc2: f8ca 3014 str.w r3, [sl, #20] + 83fc6: d018 beq.n 83ffa <_realloc_r+0x372> + 83fc8: 3510 adds r5, #16 + 83fca: f10a 0318 add.w r3, sl, #24 + 83fce: e7aa b.n 83f26 <_realloc_r+0x29e> + 83fd0: 692a ldr r2, [r5, #16] + 83fd2: f100 0318 add.w r3, r0, #24 + 83fd6: 6102 str r2, [r0, #16] + 83fd8: 6969 ldr r1, [r5, #20] + 83fda: f105 0218 add.w r2, r5, #24 + 83fde: 6141 str r1, [r0, #20] + 83fe0: e731 b.n 83e46 <_realloc_r+0x1be> + 83fe2: 68a9 ldr r1, [r5, #8] + 83fe4: 2a24 cmp r2, #36 ; 0x24 + 83fe6: f8ca 1010 str.w r1, [sl, #16] + 83fea: 68e9 ldr r1, [r5, #12] + 83fec: f8ca 1014 str.w r1, [sl, #20] + 83ff0: d00f beq.n 84012 <_realloc_r+0x38a> + 83ff2: 3510 adds r5, #16 + 83ff4: f10a 0218 add.w r2, sl, #24 + 83ff8: e6ef b.n 83dda <_realloc_r+0x152> + 83ffa: 692a ldr r2, [r5, #16] + 83ffc: f10a 0320 add.w r3, sl, #32 + 84000: f8ca 2018 str.w r2, [sl, #24] + 84004: 696a ldr r2, [r5, #20] + 84006: 3518 adds r5, #24 + 84008: f8ca 201c str.w r2, [sl, #28] + 8400c: e78b b.n 83f26 <_realloc_r+0x29e> + 8400e: 463b mov r3, r7 + 84010: e762 b.n 83ed8 <_realloc_r+0x250> + 84012: 6929 ldr r1, [r5, #16] + 84014: f10a 0220 add.w r2, sl, #32 + 84018: f8ca 1018 str.w r1, [sl, #24] + 8401c: 6969 ldr r1, [r5, #20] + 8401e: 3518 adds r5, #24 + 84020: f8ca 101c str.w r1, [sl, #28] + 84024: e6d9 b.n 83dda <_realloc_r+0x152> + 84026: 4629 mov r1, r5 + 84028: 4638 mov r0, r7 + 8402a: f8cd c004 str.w ip, [sp, #4] + 8402e: f7ff fdc3 bl 83bb8 + 84032: f8dd c004 ldr.w ip, [sp, #4] + 84036: e755 b.n 83ee4 <_realloc_r+0x25c> + 84038: 68ab ldr r3, [r5, #8] + 8403a: 2a24 cmp r2, #36 ; 0x24 + 8403c: f8ca 3010 str.w r3, [sl, #16] + 84040: 68eb ldr r3, [r5, #12] + 84042: f8ca 3014 str.w r3, [sl, #20] + 84046: d003 beq.n 84050 <_realloc_r+0x3c8> + 84048: 3510 adds r5, #16 + 8404a: f10a 0318 add.w r3, sl, #24 + 8404e: e743 b.n 83ed8 <_realloc_r+0x250> + 84050: 692a ldr r2, [r5, #16] + 84052: f10a 0320 add.w r3, sl, #32 + 84056: f8ca 2018 str.w r2, [sl, #24] + 8405a: 696a ldr r2, [r5, #20] + 8405c: 3518 adds r5, #24 + 8405e: f8ca 201c str.w r2, [sl, #28] + 84062: e739 b.n 83ed8 <_realloc_r+0x250> + 84064: 20070580 .word 0x20070580 + +00084068 <_sbrk_r>: + 84068: b538 push {r3, r4, r5, lr} + 8406a: 4c07 ldr r4, [pc, #28] ; (84088 <_sbrk_r+0x20>) + 8406c: 2300 movs r3, #0 + 8406e: 4605 mov r5, r0 + 84070: 4608 mov r0, r1 + 84072: 6023 str r3, [r4, #0] + 84074: f7fd f944 bl 81300 <_sbrk> + 84078: 1c43 adds r3, r0, #1 + 8407a: d000 beq.n 8407e <_sbrk_r+0x16> + 8407c: bd38 pop {r3, r4, r5, pc} + 8407e: 6823 ldr r3, [r4, #0] + 84080: 2b00 cmp r3, #0 + 84082: d0fb beq.n 8407c <_sbrk_r+0x14> + 84084: 602b str r3, [r5, #0] + 84086: bd38 pop {r3, r4, r5, pc} + 84088: 200748e8 .word 0x200748e8 + +0008408c <__sread>: + 8408c: b510 push {r4, lr} + 8408e: 460c mov r4, r1 + 84090: f9b1 100e ldrsh.w r1, [r1, #14] + 84094: f000 f9bc bl 84410 <_read_r> + 84098: 2800 cmp r0, #0 + 8409a: db03 blt.n 840a4 <__sread+0x18> + 8409c: 6d23 ldr r3, [r4, #80] ; 0x50 + 8409e: 4403 add r3, r0 + 840a0: 6523 str r3, [r4, #80] ; 0x50 + 840a2: bd10 pop {r4, pc} + 840a4: 89a3 ldrh r3, [r4, #12] + 840a6: f423 5380 bic.w r3, r3, #4096 ; 0x1000 + 840aa: 81a3 strh r3, [r4, #12] + 840ac: bd10 pop {r4, pc} + 840ae: bf00 nop + +000840b0 <__swrite>: + 840b0: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 840b4: 460c mov r4, r1 + 840b6: 8989 ldrh r1, [r1, #12] + 840b8: 461d mov r5, r3 + 840ba: 05cb lsls r3, r1, #23 + 840bc: 4616 mov r6, r2 + 840be: 4607 mov r7, r0 + 840c0: d506 bpl.n 840d0 <__swrite+0x20> + 840c2: f9b4 100e ldrsh.w r1, [r4, #14] + 840c6: 2200 movs r2, #0 + 840c8: 2302 movs r3, #2 + 840ca: f000 f98d bl 843e8 <_lseek_r> + 840ce: 89a1 ldrh r1, [r4, #12] + 840d0: f421 5180 bic.w r1, r1, #4096 ; 0x1000 + 840d4: 81a1 strh r1, [r4, #12] + 840d6: 4638 mov r0, r7 + 840d8: f9b4 100e ldrsh.w r1, [r4, #14] + 840dc: 4632 mov r2, r6 + 840de: 462b mov r3, r5 + 840e0: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} + 840e4: f000 b8a0 b.w 84228 <_write_r> + +000840e8 <__sseek>: + 840e8: b510 push {r4, lr} + 840ea: 460c mov r4, r1 + 840ec: f9b1 100e ldrsh.w r1, [r1, #14] + 840f0: f000 f97a bl 843e8 <_lseek_r> + 840f4: 89a3 ldrh r3, [r4, #12] + 840f6: 1c42 adds r2, r0, #1 + 840f8: bf0e itee eq + 840fa: f423 5380 biceq.w r3, r3, #4096 ; 0x1000 + 840fe: f443 5380 orrne.w r3, r3, #4096 ; 0x1000 + 84102: 6520 strne r0, [r4, #80] ; 0x50 + 84104: 81a3 strh r3, [r4, #12] + 84106: bd10 pop {r4, pc} + +00084108 <__sclose>: + 84108: f9b1 100e ldrsh.w r1, [r1, #14] + 8410c: f000 b8f2 b.w 842f4 <_close_r> + +00084110 <__swbuf_r>: + 84110: b570 push {r4, r5, r6, lr} + 84112: 460d mov r5, r1 + 84114: 4614 mov r4, r2 + 84116: 4606 mov r6, r0 + 84118: b110 cbz r0, 84120 <__swbuf_r+0x10> + 8411a: 6b83 ldr r3, [r0, #56] ; 0x38 + 8411c: 2b00 cmp r3, #0 + 8411e: d048 beq.n 841b2 <__swbuf_r+0xa2> + 84120: 89a2 ldrh r2, [r4, #12] + 84122: 69a3 ldr r3, [r4, #24] + 84124: b291 uxth r1, r2 + 84126: 0708 lsls r0, r1, #28 + 84128: 60a3 str r3, [r4, #8] + 8412a: d538 bpl.n 8419e <__swbuf_r+0x8e> + 8412c: 6923 ldr r3, [r4, #16] + 8412e: 2b00 cmp r3, #0 + 84130: d035 beq.n 8419e <__swbuf_r+0x8e> + 84132: 0489 lsls r1, r1, #18 + 84134: b2ed uxtb r5, r5 + 84136: d515 bpl.n 84164 <__swbuf_r+0x54> + 84138: 6822 ldr r2, [r4, #0] + 8413a: 6961 ldr r1, [r4, #20] + 8413c: 1ad3 subs r3, r2, r3 + 8413e: 428b cmp r3, r1 + 84140: da1c bge.n 8417c <__swbuf_r+0x6c> + 84142: 3301 adds r3, #1 + 84144: 68a1 ldr r1, [r4, #8] + 84146: 1c50 adds r0, r2, #1 + 84148: 3901 subs r1, #1 + 8414a: 60a1 str r1, [r4, #8] + 8414c: 6020 str r0, [r4, #0] + 8414e: 7015 strb r5, [r2, #0] + 84150: 6962 ldr r2, [r4, #20] + 84152: 429a cmp r2, r3 + 84154: d01a beq.n 8418c <__swbuf_r+0x7c> + 84156: 89a3 ldrh r3, [r4, #12] + 84158: 07db lsls r3, r3, #31 + 8415a: d501 bpl.n 84160 <__swbuf_r+0x50> + 8415c: 2d0a cmp r5, #10 + 8415e: d015 beq.n 8418c <__swbuf_r+0x7c> + 84160: 4628 mov r0, r5 + 84162: bd70 pop {r4, r5, r6, pc} + 84164: 6e61 ldr r1, [r4, #100] ; 0x64 + 84166: f442 5200 orr.w r2, r2, #8192 ; 0x2000 + 8416a: f421 5100 bic.w r1, r1, #8192 ; 0x2000 + 8416e: 81a2 strh r2, [r4, #12] + 84170: 6822 ldr r2, [r4, #0] + 84172: 6661 str r1, [r4, #100] ; 0x64 + 84174: 6961 ldr r1, [r4, #20] + 84176: 1ad3 subs r3, r2, r3 + 84178: 428b cmp r3, r1 + 8417a: dbe2 blt.n 84142 <__swbuf_r+0x32> + 8417c: 4630 mov r0, r6 + 8417e: 4621 mov r1, r4 + 84180: f7fe fdcc bl 82d1c <_fflush_r> + 84184: b940 cbnz r0, 84198 <__swbuf_r+0x88> + 84186: 6822 ldr r2, [r4, #0] + 84188: 2301 movs r3, #1 + 8418a: e7db b.n 84144 <__swbuf_r+0x34> + 8418c: 4630 mov r0, r6 + 8418e: 4621 mov r1, r4 + 84190: f7fe fdc4 bl 82d1c <_fflush_r> + 84194: 2800 cmp r0, #0 + 84196: d0e3 beq.n 84160 <__swbuf_r+0x50> + 84198: f04f 30ff mov.w r0, #4294967295 + 8419c: bd70 pop {r4, r5, r6, pc} + 8419e: 4630 mov r0, r6 + 841a0: 4621 mov r1, r4 + 841a2: f7fe fca5 bl 82af0 <__swsetup_r> + 841a6: 2800 cmp r0, #0 + 841a8: d1f6 bne.n 84198 <__swbuf_r+0x88> + 841aa: 89a2 ldrh r2, [r4, #12] + 841ac: 6923 ldr r3, [r4, #16] + 841ae: b291 uxth r1, r2 + 841b0: e7bf b.n 84132 <__swbuf_r+0x22> + 841b2: f7fe fe47 bl 82e44 <__sinit> + 841b6: e7b3 b.n 84120 <__swbuf_r+0x10> + +000841b8 <_wcrtomb_r>: + 841b8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 841bc: 4605 mov r5, r0 + 841be: b086 sub sp, #24 + 841c0: 461e mov r6, r3 + 841c2: 460c mov r4, r1 + 841c4: b1a1 cbz r1, 841f0 <_wcrtomb_r+0x38> + 841c6: 4b10 ldr r3, [pc, #64] ; (84208 <_wcrtomb_r+0x50>) + 841c8: 4617 mov r7, r2 + 841ca: f8d3 8000 ldr.w r8, [r3] + 841ce: f7ff f9a1 bl 83514 <__locale_charset> + 841d2: 9600 str r6, [sp, #0] + 841d4: 4603 mov r3, r0 + 841d6: 4621 mov r1, r4 + 841d8: 463a mov r2, r7 + 841da: 4628 mov r0, r5 + 841dc: 47c0 blx r8 + 841de: 1c43 adds r3, r0, #1 + 841e0: d103 bne.n 841ea <_wcrtomb_r+0x32> + 841e2: 2200 movs r2, #0 + 841e4: 238a movs r3, #138 ; 0x8a + 841e6: 6032 str r2, [r6, #0] + 841e8: 602b str r3, [r5, #0] + 841ea: b006 add sp, #24 + 841ec: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 841f0: 4b05 ldr r3, [pc, #20] ; (84208 <_wcrtomb_r+0x50>) + 841f2: 681f ldr r7, [r3, #0] + 841f4: f7ff f98e bl 83514 <__locale_charset> + 841f8: 9600 str r6, [sp, #0] + 841fa: 4603 mov r3, r0 + 841fc: 4622 mov r2, r4 + 841fe: 4628 mov r0, r5 + 84200: a903 add r1, sp, #12 + 84202: 47b8 blx r7 + 84204: e7eb b.n 841de <_wcrtomb_r+0x26> + 84206: bf00 nop + 84208: 20070990 .word 0x20070990 + +0008420c <__ascii_wctomb>: + 8420c: b121 cbz r1, 84218 <__ascii_wctomb+0xc> + 8420e: 2aff cmp r2, #255 ; 0xff + 84210: d804 bhi.n 8421c <__ascii_wctomb+0x10> + 84212: 700a strb r2, [r1, #0] + 84214: 2001 movs r0, #1 + 84216: 4770 bx lr + 84218: 4608 mov r0, r1 + 8421a: 4770 bx lr + 8421c: 238a movs r3, #138 ; 0x8a + 8421e: 6003 str r3, [r0, #0] + 84220: f04f 30ff mov.w r0, #4294967295 + 84224: 4770 bx lr + 84226: bf00 nop + +00084228 <_write_r>: + 84228: b570 push {r4, r5, r6, lr} + 8422a: 4c08 ldr r4, [pc, #32] ; (8424c <_write_r+0x24>) + 8422c: 4606 mov r6, r0 + 8422e: 2500 movs r5, #0 + 84230: 4608 mov r0, r1 + 84232: 4611 mov r1, r2 + 84234: 461a mov r2, r3 + 84236: 6025 str r5, [r4, #0] + 84238: f7fb ffda bl 801f0 <_write> + 8423c: 1c43 adds r3, r0, #1 + 8423e: d000 beq.n 84242 <_write_r+0x1a> + 84240: bd70 pop {r4, r5, r6, pc} + 84242: 6823 ldr r3, [r4, #0] + 84244: 2b00 cmp r3, #0 + 84246: d0fb beq.n 84240 <_write_r+0x18> + 84248: 6033 str r3, [r6, #0] + 8424a: bd70 pop {r4, r5, r6, pc} + 8424c: 200748e8 .word 0x200748e8 + +00084250 <__register_exitproc>: + 84250: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 84254: 4c25 ldr r4, [pc, #148] ; (842ec <__register_exitproc+0x9c>) + 84256: 4606 mov r6, r0 + 84258: 6825 ldr r5, [r4, #0] + 8425a: 4688 mov r8, r1 + 8425c: f8d5 4148 ldr.w r4, [r5, #328] ; 0x148 + 84260: 4692 mov sl, r2 + 84262: 4699 mov r9, r3 + 84264: b3c4 cbz r4, 842d8 <__register_exitproc+0x88> + 84266: 6860 ldr r0, [r4, #4] + 84268: 281f cmp r0, #31 + 8426a: dc17 bgt.n 8429c <__register_exitproc+0x4c> + 8426c: 1c41 adds r1, r0, #1 + 8426e: b176 cbz r6, 8428e <__register_exitproc+0x3e> + 84270: eb04 0380 add.w r3, r4, r0, lsl #2 + 84274: f8c3 a088 str.w sl, [r3, #136] ; 0x88 + 84278: f8d4 5188 ldr.w r5, [r4, #392] ; 0x188 + 8427c: 2201 movs r2, #1 + 8427e: 4082 lsls r2, r0 + 84280: 4315 orrs r5, r2 + 84282: 2e02 cmp r6, #2 + 84284: f8c4 5188 str.w r5, [r4, #392] ; 0x188 + 84288: f8c3 9108 str.w r9, [r3, #264] ; 0x108 + 8428c: d01e beq.n 842cc <__register_exitproc+0x7c> + 8428e: 1c83 adds r3, r0, #2 + 84290: 6061 str r1, [r4, #4] + 84292: 2000 movs r0, #0 + 84294: f844 8023 str.w r8, [r4, r3, lsl #2] + 84298: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8429c: 4b14 ldr r3, [pc, #80] ; (842f0 <__register_exitproc+0xa0>) + 8429e: b303 cbz r3, 842e2 <__register_exitproc+0x92> + 842a0: f44f 70c8 mov.w r0, #400 ; 0x190 + 842a4: f7ff f9b0 bl 83608 + 842a8: 4604 mov r4, r0 + 842aa: b1d0 cbz r0, 842e2 <__register_exitproc+0x92> + 842ac: f8d5 3148 ldr.w r3, [r5, #328] ; 0x148 + 842b0: 2700 movs r7, #0 + 842b2: e884 0088 stmia.w r4, {r3, r7} + 842b6: 4638 mov r0, r7 + 842b8: f8c5 4148 str.w r4, [r5, #328] ; 0x148 + 842bc: 2101 movs r1, #1 + 842be: f8c4 7188 str.w r7, [r4, #392] ; 0x188 + 842c2: f8c4 718c str.w r7, [r4, #396] ; 0x18c + 842c6: 2e00 cmp r6, #0 + 842c8: d0e1 beq.n 8428e <__register_exitproc+0x3e> + 842ca: e7d1 b.n 84270 <__register_exitproc+0x20> + 842cc: f8d4 318c ldr.w r3, [r4, #396] ; 0x18c + 842d0: 431a orrs r2, r3 + 842d2: f8c4 218c str.w r2, [r4, #396] ; 0x18c + 842d6: e7da b.n 8428e <__register_exitproc+0x3e> + 842d8: f505 74a6 add.w r4, r5, #332 ; 0x14c + 842dc: f8c5 4148 str.w r4, [r5, #328] ; 0x148 + 842e0: e7c1 b.n 84266 <__register_exitproc+0x16> + 842e2: f04f 30ff mov.w r0, #4294967295 + 842e6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 842ea: bf00 nop + 842ec: 00084ca4 .word 0x00084ca4 + 842f0: 00083609 .word 0x00083609 + +000842f4 <_close_r>: + 842f4: b538 push {r3, r4, r5, lr} + 842f6: 4c07 ldr r4, [pc, #28] ; (84314 <_close_r+0x20>) + 842f8: 2300 movs r3, #0 + 842fa: 4605 mov r5, r0 + 842fc: 4608 mov r0, r1 + 842fe: 6023 str r3, [r4, #0] + 84300: f7fd f818 bl 81334 <_close> + 84304: 1c43 adds r3, r0, #1 + 84306: d000 beq.n 8430a <_close_r+0x16> + 84308: bd38 pop {r3, r4, r5, pc} + 8430a: 6823 ldr r3, [r4, #0] + 8430c: 2b00 cmp r3, #0 + 8430e: d0fb beq.n 84308 <_close_r+0x14> + 84310: 602b str r3, [r5, #0] + 84312: bd38 pop {r3, r4, r5, pc} + 84314: 200748e8 .word 0x200748e8 + +00084318 <_fclose_r>: + 84318: 2900 cmp r1, #0 + 8431a: d03d beq.n 84398 <_fclose_r+0x80> + 8431c: b570 push {r4, r5, r6, lr} + 8431e: 4605 mov r5, r0 + 84320: 460c mov r4, r1 + 84322: b108 cbz r0, 84328 <_fclose_r+0x10> + 84324: 6b83 ldr r3, [r0, #56] ; 0x38 + 84326: b37b cbz r3, 84388 <_fclose_r+0x70> + 84328: f9b4 300c ldrsh.w r3, [r4, #12] + 8432c: b90b cbnz r3, 84332 <_fclose_r+0x1a> + 8432e: 2000 movs r0, #0 + 84330: bd70 pop {r4, r5, r6, pc} + 84332: 4628 mov r0, r5 + 84334: 4621 mov r1, r4 + 84336: f7fe fc4d bl 82bd4 <__sflush_r> + 8433a: 6ae3 ldr r3, [r4, #44] ; 0x2c + 8433c: 4606 mov r6, r0 + 8433e: b133 cbz r3, 8434e <_fclose_r+0x36> + 84340: 4628 mov r0, r5 + 84342: 69e1 ldr r1, [r4, #28] + 84344: 4798 blx r3 + 84346: 2800 cmp r0, #0 + 84348: bfb8 it lt + 8434a: f04f 36ff movlt.w r6, #4294967295 + 8434e: 89a3 ldrh r3, [r4, #12] + 84350: 061b lsls r3, r3, #24 + 84352: d41c bmi.n 8438e <_fclose_r+0x76> + 84354: 6b21 ldr r1, [r4, #48] ; 0x30 + 84356: b141 cbz r1, 8436a <_fclose_r+0x52> + 84358: f104 0340 add.w r3, r4, #64 ; 0x40 + 8435c: 4299 cmp r1, r3 + 8435e: d002 beq.n 84366 <_fclose_r+0x4e> + 84360: 4628 mov r0, r5 + 84362: f7fe fe47 bl 82ff4 <_free_r> + 84366: 2300 movs r3, #0 + 84368: 6323 str r3, [r4, #48] ; 0x30 + 8436a: 6c61 ldr r1, [r4, #68] ; 0x44 + 8436c: b121 cbz r1, 84378 <_fclose_r+0x60> + 8436e: 4628 mov r0, r5 + 84370: f7fe fe40 bl 82ff4 <_free_r> + 84374: 2300 movs r3, #0 + 84376: 6463 str r3, [r4, #68] ; 0x44 + 84378: f7fe fd6a bl 82e50 <__sfp_lock_acquire> + 8437c: 2300 movs r3, #0 + 8437e: 81a3 strh r3, [r4, #12] + 84380: f7fe fd68 bl 82e54 <__sfp_lock_release> + 84384: 4630 mov r0, r6 + 84386: bd70 pop {r4, r5, r6, pc} + 84388: f7fe fd5c bl 82e44 <__sinit> + 8438c: e7cc b.n 84328 <_fclose_r+0x10> + 8438e: 4628 mov r0, r5 + 84390: 6921 ldr r1, [r4, #16] + 84392: f7fe fe2f bl 82ff4 <_free_r> + 84396: e7dd b.n 84354 <_fclose_r+0x3c> + 84398: 2000 movs r0, #0 + 8439a: 4770 bx lr + +0008439c <_fstat_r>: + 8439c: b538 push {r3, r4, r5, lr} + 8439e: 4c08 ldr r4, [pc, #32] ; (843c0 <_fstat_r+0x24>) + 843a0: 2300 movs r3, #0 + 843a2: 4605 mov r5, r0 + 843a4: 4608 mov r0, r1 + 843a6: 4611 mov r1, r2 + 843a8: 6023 str r3, [r4, #0] + 843aa: f7fc ffc7 bl 8133c <_fstat> + 843ae: 1c43 adds r3, r0, #1 + 843b0: d000 beq.n 843b4 <_fstat_r+0x18> + 843b2: bd38 pop {r3, r4, r5, pc} + 843b4: 6823 ldr r3, [r4, #0] + 843b6: 2b00 cmp r3, #0 + 843b8: d0fb beq.n 843b2 <_fstat_r+0x16> + 843ba: 602b str r3, [r5, #0] + 843bc: bd38 pop {r3, r4, r5, pc} + 843be: bf00 nop + 843c0: 200748e8 .word 0x200748e8 + +000843c4 <_isatty_r>: + 843c4: b538 push {r3, r4, r5, lr} + 843c6: 4c07 ldr r4, [pc, #28] ; (843e4 <_isatty_r+0x20>) + 843c8: 2300 movs r3, #0 + 843ca: 4605 mov r5, r0 + 843cc: 4608 mov r0, r1 + 843ce: 6023 str r3, [r4, #0] + 843d0: f7fc ffba bl 81348 <_isatty> + 843d4: 1c43 adds r3, r0, #1 + 843d6: d000 beq.n 843da <_isatty_r+0x16> + 843d8: bd38 pop {r3, r4, r5, pc} + 843da: 6823 ldr r3, [r4, #0] + 843dc: 2b00 cmp r3, #0 + 843de: d0fb beq.n 843d8 <_isatty_r+0x14> + 843e0: 602b str r3, [r5, #0] + 843e2: bd38 pop {r3, r4, r5, pc} + 843e4: 200748e8 .word 0x200748e8 + +000843e8 <_lseek_r>: + 843e8: b570 push {r4, r5, r6, lr} + 843ea: 4c08 ldr r4, [pc, #32] ; (8440c <_lseek_r+0x24>) + 843ec: 4606 mov r6, r0 + 843ee: 2500 movs r5, #0 + 843f0: 4608 mov r0, r1 + 843f2: 4611 mov r1, r2 + 843f4: 461a mov r2, r3 + 843f6: 6025 str r5, [r4, #0] + 843f8: f7fc ffa8 bl 8134c <_lseek> + 843fc: 1c43 adds r3, r0, #1 + 843fe: d000 beq.n 84402 <_lseek_r+0x1a> + 84400: bd70 pop {r4, r5, r6, pc} + 84402: 6823 ldr r3, [r4, #0] + 84404: 2b00 cmp r3, #0 + 84406: d0fb beq.n 84400 <_lseek_r+0x18> + 84408: 6033 str r3, [r6, #0] + 8440a: bd70 pop {r4, r5, r6, pc} + 8440c: 200748e8 .word 0x200748e8 + +00084410 <_read_r>: + 84410: b570 push {r4, r5, r6, lr} + 84412: 4c08 ldr r4, [pc, #32] ; (84434 <_read_r+0x24>) + 84414: 4606 mov r6, r0 + 84416: 2500 movs r5, #0 + 84418: 4608 mov r0, r1 + 8441a: 4611 mov r1, r2 + 8441c: 461a mov r2, r3 + 8441e: 6025 str r5, [r4, #0] + 84420: f7fb fec8 bl 801b4 <_read> + 84424: 1c43 adds r3, r0, #1 + 84426: d000 beq.n 8442a <_read_r+0x1a> + 84428: bd70 pop {r4, r5, r6, pc} + 8442a: 6823 ldr r3, [r4, #0] + 8442c: 2b00 cmp r3, #0 + 8442e: d0fb beq.n 84428 <_read_r+0x18> + 84430: 6033 str r3, [r6, #0] + 84432: bd70 pop {r4, r5, r6, pc} + 84434: 200748e8 .word 0x200748e8 + +00084438 <__aeabi_uldivmod>: + 84438: b953 cbnz r3, 84450 <__aeabi_uldivmod+0x18> + 8443a: b94a cbnz r2, 84450 <__aeabi_uldivmod+0x18> + 8443c: 2900 cmp r1, #0 + 8443e: bf08 it eq + 84440: 2800 cmpeq r0, #0 + 84442: bf1c itt ne + 84444: f04f 31ff movne.w r1, #4294967295 + 84448: f04f 30ff movne.w r0, #4294967295 + 8444c: f000 b83c b.w 844c8 <__aeabi_idiv0> + 84450: b082 sub sp, #8 + 84452: 46ec mov ip, sp + 84454: e92d 5000 stmdb sp!, {ip, lr} + 84458: f000 f81e bl 84498 <__gnu_uldivmod_helper> + 8445c: f8dd e004 ldr.w lr, [sp, #4] + 84460: b002 add sp, #8 + 84462: bc0c pop {r2, r3} + 84464: 4770 bx lr + 84466: bf00 nop + +00084468 <__gnu_ldivmod_helper>: + 84468: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 8446c: 9c06 ldr r4, [sp, #24] + 8446e: 4690 mov r8, r2 + 84470: 4606 mov r6, r0 + 84472: 460f mov r7, r1 + 84474: 461d mov r5, r3 + 84476: f000 f829 bl 844cc <__divdi3> + 8447a: fb08 fc01 mul.w ip, r8, r1 + 8447e: fba8 2300 umull r2, r3, r8, r0 + 84482: fb00 c505 mla r5, r0, r5, ip + 84486: 1ab2 subs r2, r6, r2 + 84488: 442b add r3, r5 + 8448a: eb67 0303 sbc.w r3, r7, r3 + 8448e: 4686 mov lr, r0 + 84490: e9c4 2300 strd r2, r3, [r4] + 84494: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + +00084498 <__gnu_uldivmod_helper>: + 84498: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 8449c: 9e08 ldr r6, [sp, #32] + 8449e: 4617 mov r7, r2 + 844a0: 4680 mov r8, r0 + 844a2: 4689 mov r9, r1 + 844a4: 461d mov r5, r3 + 844a6: f000 f967 bl 84778 <__udivdi3> + 844aa: fb00 f305 mul.w r3, r0, r5 + 844ae: fba0 4507 umull r4, r5, r0, r7 + 844b2: fb07 3701 mla r7, r7, r1, r3 + 844b6: ebb8 0404 subs.w r4, r8, r4 + 844ba: 443d add r5, r7 + 844bc: eb69 0505 sbc.w r5, r9, r5 + 844c0: e9c6 4500 strd r4, r5, [r6] + 844c4: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + +000844c8 <__aeabi_idiv0>: + 844c8: 4770 bx lr + 844ca: bf00 nop + +000844cc <__divdi3>: + 844cc: 2900 cmp r1, #0 + 844ce: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} + 844d2: f2c0 80a8 blt.w 84626 <__divdi3+0x15a> + 844d6: 2600 movs r6, #0 + 844d8: 2b00 cmp r3, #0 + 844da: f2c0 809e blt.w 8461a <__divdi3+0x14e> + 844de: 4681 mov r9, r0 + 844e0: 468e mov lr, r1 + 844e2: 4690 mov r8, r2 + 844e4: 469c mov ip, r3 + 844e6: 4617 mov r7, r2 + 844e8: 4604 mov r4, r0 + 844ea: 460d mov r5, r1 + 844ec: 2b00 cmp r3, #0 + 844ee: d13d bne.n 8456c <__divdi3+0xa0> + 844f0: 428a cmp r2, r1 + 844f2: d959 bls.n 845a8 <__divdi3+0xdc> + 844f4: fab2 f382 clz r3, r2 + 844f8: b13b cbz r3, 8450a <__divdi3+0x3e> + 844fa: f1c3 0220 rsb r2, r3, #32 + 844fe: 409d lsls r5, r3 + 84500: fa20 f202 lsr.w r2, r0, r2 + 84504: 409f lsls r7, r3 + 84506: 4315 orrs r5, r2 + 84508: 409c lsls r4, r3 + 8450a: 0c39 lsrs r1, r7, #16 + 8450c: fbb5 f0f1 udiv r0, r5, r1 + 84510: fa1f fe87 uxth.w lr, r7 + 84514: fb01 5510 mls r5, r1, r0, r5 + 84518: fb0e f300 mul.w r3, lr, r0 + 8451c: 0c22 lsrs r2, r4, #16 + 8451e: ea42 4505 orr.w r5, r2, r5, lsl #16 + 84522: 42ab cmp r3, r5 + 84524: d909 bls.n 8453a <__divdi3+0x6e> + 84526: 19ed adds r5, r5, r7 + 84528: f100 32ff add.w r2, r0, #4294967295 + 8452c: f080 810b bcs.w 84746 <__divdi3+0x27a> + 84530: 42ab cmp r3, r5 + 84532: f240 8108 bls.w 84746 <__divdi3+0x27a> + 84536: 3802 subs r0, #2 + 84538: 443d add r5, r7 + 8453a: 1aed subs r5, r5, r3 + 8453c: fbb5 f3f1 udiv r3, r5, r1 + 84540: fb01 5513 mls r5, r1, r3, r5 + 84544: fb0e fe03 mul.w lr, lr, r3 + 84548: b2a4 uxth r4, r4 + 8454a: ea44 4505 orr.w r5, r4, r5, lsl #16 + 8454e: 45ae cmp lr, r5 + 84550: d908 bls.n 84564 <__divdi3+0x98> + 84552: 19ed adds r5, r5, r7 + 84554: f103 32ff add.w r2, r3, #4294967295 + 84558: f080 80f7 bcs.w 8474a <__divdi3+0x27e> + 8455c: 45ae cmp lr, r5 + 8455e: f240 80f4 bls.w 8474a <__divdi3+0x27e> + 84562: 3b02 subs r3, #2 + 84564: ea43 4300 orr.w r3, r3, r0, lsl #16 + 84568: 2200 movs r2, #0 + 8456a: e003 b.n 84574 <__divdi3+0xa8> + 8456c: 428b cmp r3, r1 + 8456e: d90f bls.n 84590 <__divdi3+0xc4> + 84570: 2200 movs r2, #0 + 84572: 4613 mov r3, r2 + 84574: 1c34 adds r4, r6, #0 + 84576: bf18 it ne + 84578: 2401 movne r4, #1 + 8457a: 4260 negs r0, r4 + 8457c: f04f 0500 mov.w r5, #0 + 84580: eb65 0145 sbc.w r1, r5, r5, lsl #1 + 84584: 4058 eors r0, r3 + 84586: 4051 eors r1, r2 + 84588: 1900 adds r0, r0, r4 + 8458a: 4169 adcs r1, r5 + 8458c: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + 84590: fab3 f283 clz r2, r3 + 84594: 2a00 cmp r2, #0 + 84596: f040 8089 bne.w 846ac <__divdi3+0x1e0> + 8459a: 428b cmp r3, r1 + 8459c: d302 bcc.n 845a4 <__divdi3+0xd8> + 8459e: 4580 cmp r8, r0 + 845a0: f200 80e2 bhi.w 84768 <__divdi3+0x29c> + 845a4: 2301 movs r3, #1 + 845a6: e7e5 b.n 84574 <__divdi3+0xa8> + 845a8: b912 cbnz r2, 845b0 <__divdi3+0xe4> + 845aa: 2301 movs r3, #1 + 845ac: fbb3 f7f2 udiv r7, r3, r2 + 845b0: fab7 f887 clz r8, r7 + 845b4: f1b8 0f00 cmp.w r8, #0 + 845b8: d13b bne.n 84632 <__divdi3+0x166> + 845ba: 1bed subs r5, r5, r7 + 845bc: ea4f 4c17 mov.w ip, r7, lsr #16 + 845c0: fa1f fe87 uxth.w lr, r7 + 845c4: 2201 movs r2, #1 + 845c6: fbb5 f0fc udiv r0, r5, ip + 845ca: fb0c 5510 mls r5, ip, r0, r5 + 845ce: fb0e f300 mul.w r3, lr, r0 + 845d2: 0c21 lsrs r1, r4, #16 + 845d4: ea41 4505 orr.w r5, r1, r5, lsl #16 + 845d8: 42ab cmp r3, r5 + 845da: d907 bls.n 845ec <__divdi3+0x120> + 845dc: 19ed adds r5, r5, r7 + 845de: f100 31ff add.w r1, r0, #4294967295 + 845e2: d202 bcs.n 845ea <__divdi3+0x11e> + 845e4: 42ab cmp r3, r5 + 845e6: f200 80c3 bhi.w 84770 <__divdi3+0x2a4> + 845ea: 4608 mov r0, r1 + 845ec: 1aed subs r5, r5, r3 + 845ee: fbb5 f3fc udiv r3, r5, ip + 845f2: fb0c 5513 mls r5, ip, r3, r5 + 845f6: fb0e fe03 mul.w lr, lr, r3 + 845fa: b2a4 uxth r4, r4 + 845fc: ea44 4505 orr.w r5, r4, r5, lsl #16 + 84600: 45ae cmp lr, r5 + 84602: d907 bls.n 84614 <__divdi3+0x148> + 84604: 19ed adds r5, r5, r7 + 84606: f103 31ff add.w r1, r3, #4294967295 + 8460a: d202 bcs.n 84612 <__divdi3+0x146> + 8460c: 45ae cmp lr, r5 + 8460e: f200 80ad bhi.w 8476c <__divdi3+0x2a0> + 84612: 460b mov r3, r1 + 84614: ea43 4300 orr.w r3, r3, r0, lsl #16 + 84618: e7ac b.n 84574 <__divdi3+0xa8> + 8461a: 4252 negs r2, r2 + 8461c: ea6f 0606 mvn.w r6, r6 + 84620: eb63 0343 sbc.w r3, r3, r3, lsl #1 + 84624: e75b b.n 844de <__divdi3+0x12> + 84626: 4240 negs r0, r0 + 84628: eb61 0141 sbc.w r1, r1, r1, lsl #1 + 8462c: f04f 36ff mov.w r6, #4294967295 + 84630: e752 b.n 844d8 <__divdi3+0xc> + 84632: fa07 f708 lsl.w r7, r7, r8 + 84636: f1c8 0220 rsb r2, r8, #32 + 8463a: fa25 f302 lsr.w r3, r5, r2 + 8463e: ea4f 4c17 mov.w ip, r7, lsr #16 + 84642: fbb3 f1fc udiv r1, r3, ip + 84646: fa1f fe87 uxth.w lr, r7 + 8464a: fb0c 3311 mls r3, ip, r1, r3 + 8464e: fa24 f202 lsr.w r2, r4, r2 + 84652: fa05 f508 lsl.w r5, r5, r8 + 84656: fb0e f901 mul.w r9, lr, r1 + 8465a: 432a orrs r2, r5 + 8465c: 0c10 lsrs r0, r2, #16 + 8465e: ea40 4303 orr.w r3, r0, r3, lsl #16 + 84662: 4599 cmp r9, r3 + 84664: fa04 f408 lsl.w r4, r4, r8 + 84668: d907 bls.n 8467a <__divdi3+0x1ae> + 8466a: 19db adds r3, r3, r7 + 8466c: f101 30ff add.w r0, r1, #4294967295 + 84670: d278 bcs.n 84764 <__divdi3+0x298> + 84672: 4599 cmp r9, r3 + 84674: d976 bls.n 84764 <__divdi3+0x298> + 84676: 3902 subs r1, #2 + 84678: 443b add r3, r7 + 8467a: ebc9 0303 rsb r3, r9, r3 + 8467e: fbb3 f0fc udiv r0, r3, ip + 84682: fb0c 3310 mls r3, ip, r0, r3 + 84686: fb0e f500 mul.w r5, lr, r0 + 8468a: b292 uxth r2, r2 + 8468c: ea42 4303 orr.w r3, r2, r3, lsl #16 + 84690: 429d cmp r5, r3 + 84692: d907 bls.n 846a4 <__divdi3+0x1d8> + 84694: 19db adds r3, r3, r7 + 84696: f100 32ff add.w r2, r0, #4294967295 + 8469a: d25f bcs.n 8475c <__divdi3+0x290> + 8469c: 429d cmp r5, r3 + 8469e: d95d bls.n 8475c <__divdi3+0x290> + 846a0: 3802 subs r0, #2 + 846a2: 443b add r3, r7 + 846a4: 1b5d subs r5, r3, r5 + 846a6: ea40 4201 orr.w r2, r0, r1, lsl #16 + 846aa: e78c b.n 845c6 <__divdi3+0xfa> + 846ac: f1c2 0320 rsb r3, r2, #32 + 846b0: fa28 f103 lsr.w r1, r8, r3 + 846b4: fa0c fc02 lsl.w ip, ip, r2 + 846b8: ea41 0c0c orr.w ip, r1, ip + 846bc: ea4f 401c mov.w r0, ip, lsr #16 + 846c0: fa2e f103 lsr.w r1, lr, r3 + 846c4: fbb1 f5f0 udiv r5, r1, r0 + 846c8: fa1f f78c uxth.w r7, ip + 846cc: fb00 1115 mls r1, r0, r5, r1 + 846d0: fa29 f303 lsr.w r3, r9, r3 + 846d4: fa0e fe02 lsl.w lr, lr, r2 + 846d8: fb07 f905 mul.w r9, r7, r5 + 846dc: ea43 0e0e orr.w lr, r3, lr + 846e0: ea4f 431e mov.w r3, lr, lsr #16 + 846e4: ea43 4101 orr.w r1, r3, r1, lsl #16 + 846e8: 4589 cmp r9, r1 + 846ea: fa08 f802 lsl.w r8, r8, r2 + 846ee: d908 bls.n 84702 <__divdi3+0x236> + 846f0: eb11 010c adds.w r1, r1, ip + 846f4: f105 33ff add.w r3, r5, #4294967295 + 846f8: d232 bcs.n 84760 <__divdi3+0x294> + 846fa: 4589 cmp r9, r1 + 846fc: d930 bls.n 84760 <__divdi3+0x294> + 846fe: 3d02 subs r5, #2 + 84700: 4461 add r1, ip + 84702: ebc9 0101 rsb r1, r9, r1 + 84706: fbb1 f3f0 udiv r3, r1, r0 + 8470a: fb00 1113 mls r1, r0, r3, r1 + 8470e: fb07 f703 mul.w r7, r7, r3 + 84712: fa1f fe8e uxth.w lr, lr + 84716: ea4e 4e01 orr.w lr, lr, r1, lsl #16 + 8471a: 4577 cmp r7, lr + 8471c: d908 bls.n 84730 <__divdi3+0x264> + 8471e: eb1e 0e0c adds.w lr, lr, ip + 84722: f103 31ff add.w r1, r3, #4294967295 + 84726: d217 bcs.n 84758 <__divdi3+0x28c> + 84728: 4577 cmp r7, lr + 8472a: d915 bls.n 84758 <__divdi3+0x28c> + 8472c: 3b02 subs r3, #2 + 8472e: 44e6 add lr, ip + 84730: ea43 4305 orr.w r3, r3, r5, lsl #16 + 84734: fba3 8908 umull r8, r9, r3, r8 + 84738: ebc7 0e0e rsb lr, r7, lr + 8473c: 45ce cmp lr, r9 + 8473e: d309 bcc.n 84754 <__divdi3+0x288> + 84740: d005 beq.n 8474e <__divdi3+0x282> + 84742: 2200 movs r2, #0 + 84744: e716 b.n 84574 <__divdi3+0xa8> + 84746: 4610 mov r0, r2 + 84748: e6f7 b.n 8453a <__divdi3+0x6e> + 8474a: 4613 mov r3, r2 + 8474c: e70a b.n 84564 <__divdi3+0x98> + 8474e: 4094 lsls r4, r2 + 84750: 4544 cmp r4, r8 + 84752: d2f6 bcs.n 84742 <__divdi3+0x276> + 84754: 3b01 subs r3, #1 + 84756: e7f4 b.n 84742 <__divdi3+0x276> + 84758: 460b mov r3, r1 + 8475a: e7e9 b.n 84730 <__divdi3+0x264> + 8475c: 4610 mov r0, r2 + 8475e: e7a1 b.n 846a4 <__divdi3+0x1d8> + 84760: 461d mov r5, r3 + 84762: e7ce b.n 84702 <__divdi3+0x236> + 84764: 4601 mov r1, r0 + 84766: e788 b.n 8467a <__divdi3+0x1ae> + 84768: 4613 mov r3, r2 + 8476a: e703 b.n 84574 <__divdi3+0xa8> + 8476c: 3b02 subs r3, #2 + 8476e: e751 b.n 84614 <__divdi3+0x148> + 84770: 3802 subs r0, #2 + 84772: 443d add r5, r7 + 84774: e73a b.n 845ec <__divdi3+0x120> + 84776: bf00 nop + +00084778 <__udivdi3>: + 84778: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} + 8477c: 2b00 cmp r3, #0 + 8477e: d144 bne.n 8480a <__udivdi3+0x92> + 84780: 428a cmp r2, r1 + 84782: 4615 mov r5, r2 + 84784: 4604 mov r4, r0 + 84786: d94f bls.n 84828 <__udivdi3+0xb0> + 84788: fab2 f782 clz r7, r2 + 8478c: 460e mov r6, r1 + 8478e: b14f cbz r7, 847a4 <__udivdi3+0x2c> + 84790: f1c7 0320 rsb r3, r7, #32 + 84794: 40b9 lsls r1, r7 + 84796: fa20 f603 lsr.w r6, r0, r3 + 8479a: fa02 f507 lsl.w r5, r2, r7 + 8479e: 430e orrs r6, r1 + 847a0: fa00 f407 lsl.w r4, r0, r7 + 847a4: 0c2f lsrs r7, r5, #16 + 847a6: fbb6 f0f7 udiv r0, r6, r7 + 847aa: fa1f fe85 uxth.w lr, r5 + 847ae: fb07 6210 mls r2, r7, r0, r6 + 847b2: fb0e f100 mul.w r1, lr, r0 + 847b6: 0c26 lsrs r6, r4, #16 + 847b8: ea46 4302 orr.w r3, r6, r2, lsl #16 + 847bc: 4299 cmp r1, r3 + 847be: d909 bls.n 847d4 <__udivdi3+0x5c> + 847c0: 195b adds r3, r3, r5 + 847c2: f100 32ff add.w r2, r0, #4294967295 + 847c6: f080 80ee bcs.w 849a6 <__udivdi3+0x22e> + 847ca: 4299 cmp r1, r3 + 847cc: f240 80eb bls.w 849a6 <__udivdi3+0x22e> + 847d0: 3802 subs r0, #2 + 847d2: 442b add r3, r5 + 847d4: 1a59 subs r1, r3, r1 + 847d6: fbb1 f3f7 udiv r3, r1, r7 + 847da: fb07 1113 mls r1, r7, r3, r1 + 847de: fb0e fe03 mul.w lr, lr, r3 + 847e2: b2a4 uxth r4, r4 + 847e4: ea44 4101 orr.w r1, r4, r1, lsl #16 + 847e8: 458e cmp lr, r1 + 847ea: d908 bls.n 847fe <__udivdi3+0x86> + 847ec: 1949 adds r1, r1, r5 + 847ee: f103 32ff add.w r2, r3, #4294967295 + 847f2: f080 80da bcs.w 849aa <__udivdi3+0x232> + 847f6: 458e cmp lr, r1 + 847f8: f240 80d7 bls.w 849aa <__udivdi3+0x232> + 847fc: 3b02 subs r3, #2 + 847fe: ea43 4000 orr.w r0, r3, r0, lsl #16 + 84802: 2600 movs r6, #0 + 84804: 4631 mov r1, r6 + 84806: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + 8480a: 428b cmp r3, r1 + 8480c: d847 bhi.n 8489e <__udivdi3+0x126> + 8480e: fab3 f683 clz r6, r3 + 84812: 2e00 cmp r6, #0 + 84814: d148 bne.n 848a8 <__udivdi3+0x130> + 84816: 428b cmp r3, r1 + 84818: d302 bcc.n 84820 <__udivdi3+0xa8> + 8481a: 4282 cmp r2, r0 + 8481c: f200 80cf bhi.w 849be <__udivdi3+0x246> + 84820: 2001 movs r0, #1 + 84822: 4631 mov r1, r6 + 84824: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + 84828: b912 cbnz r2, 84830 <__udivdi3+0xb8> + 8482a: 2501 movs r5, #1 + 8482c: fbb5 f5f2 udiv r5, r5, r2 + 84830: fab5 fc85 clz ip, r5 + 84834: f1bc 0f00 cmp.w ip, #0 + 84838: d178 bne.n 8492c <__udivdi3+0x1b4> + 8483a: 1b49 subs r1, r1, r5 + 8483c: 0c2f lsrs r7, r5, #16 + 8483e: fa1f fe85 uxth.w lr, r5 + 84842: 2601 movs r6, #1 + 84844: fbb1 f0f7 udiv r0, r1, r7 + 84848: fb07 1110 mls r1, r7, r0, r1 + 8484c: fb0e f200 mul.w r2, lr, r0 + 84850: 0c23 lsrs r3, r4, #16 + 84852: ea43 4101 orr.w r1, r3, r1, lsl #16 + 84856: 428a cmp r2, r1 + 84858: d907 bls.n 8486a <__udivdi3+0xf2> + 8485a: 1949 adds r1, r1, r5 + 8485c: f100 33ff add.w r3, r0, #4294967295 + 84860: d202 bcs.n 84868 <__udivdi3+0xf0> + 84862: 428a cmp r2, r1 + 84864: f200 80bc bhi.w 849e0 <__udivdi3+0x268> + 84868: 4618 mov r0, r3 + 8486a: 1a89 subs r1, r1, r2 + 8486c: fbb1 f3f7 udiv r3, r1, r7 + 84870: fb07 1113 mls r1, r7, r3, r1 + 84874: fb0e fe03 mul.w lr, lr, r3 + 84878: b2a4 uxth r4, r4 + 8487a: ea44 4201 orr.w r2, r4, r1, lsl #16 + 8487e: 4596 cmp lr, r2 + 84880: d908 bls.n 84894 <__udivdi3+0x11c> + 84882: 1952 adds r2, r2, r5 + 84884: f103 31ff add.w r1, r3, #4294967295 + 84888: f080 8091 bcs.w 849ae <__udivdi3+0x236> + 8488c: 4596 cmp lr, r2 + 8488e: f240 808e bls.w 849ae <__udivdi3+0x236> + 84892: 3b02 subs r3, #2 + 84894: ea43 4000 orr.w r0, r3, r0, lsl #16 + 84898: 4631 mov r1, r6 + 8489a: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + 8489e: 2600 movs r6, #0 + 848a0: 4630 mov r0, r6 + 848a2: 4631 mov r1, r6 + 848a4: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + 848a8: f1c6 0420 rsb r4, r6, #32 + 848ac: fa22 f504 lsr.w r5, r2, r4 + 848b0: 40b3 lsls r3, r6 + 848b2: 432b orrs r3, r5 + 848b4: fa21 f704 lsr.w r7, r1, r4 + 848b8: ea4f 4813 mov.w r8, r3, lsr #16 + 848bc: fbb7 fcf8 udiv ip, r7, r8 + 848c0: fa1f f983 uxth.w r9, r3 + 848c4: fb08 771c mls r7, r8, ip, r7 + 848c8: fa20 fe04 lsr.w lr, r0, r4 + 848cc: fa01 f506 lsl.w r5, r1, r6 + 848d0: fb09 f40c mul.w r4, r9, ip + 848d4: ea4e 0505 orr.w r5, lr, r5 + 848d8: ea4f 4e15 mov.w lr, r5, lsr #16 + 848dc: ea4e 4707 orr.w r7, lr, r7, lsl #16 + 848e0: 42bc cmp r4, r7 + 848e2: fa02 f206 lsl.w r2, r2, r6 + 848e6: d904 bls.n 848f2 <__udivdi3+0x17a> + 848e8: 18ff adds r7, r7, r3 + 848ea: f10c 31ff add.w r1, ip, #4294967295 + 848ee: d368 bcc.n 849c2 <__udivdi3+0x24a> + 848f0: 468c mov ip, r1 + 848f2: 1b3f subs r7, r7, r4 + 848f4: fbb7 f4f8 udiv r4, r7, r8 + 848f8: fb08 7714 mls r7, r8, r4, r7 + 848fc: fb09 f904 mul.w r9, r9, r4 + 84900: b2ad uxth r5, r5 + 84902: ea45 4107 orr.w r1, r5, r7, lsl #16 + 84906: 4589 cmp r9, r1 + 84908: d904 bls.n 84914 <__udivdi3+0x19c> + 8490a: 18c9 adds r1, r1, r3 + 8490c: f104 35ff add.w r5, r4, #4294967295 + 84910: d35d bcc.n 849ce <__udivdi3+0x256> + 84912: 462c mov r4, r5 + 84914: ea44 440c orr.w r4, r4, ip, lsl #16 + 84918: fba4 2302 umull r2, r3, r4, r2 + 8491c: ebc9 0101 rsb r1, r9, r1 + 84920: 4299 cmp r1, r3 + 84922: d349 bcc.n 849b8 <__udivdi3+0x240> + 84924: d045 beq.n 849b2 <__udivdi3+0x23a> + 84926: 4620 mov r0, r4 + 84928: 2600 movs r6, #0 + 8492a: e76b b.n 84804 <__udivdi3+0x8c> + 8492c: f1cc 0420 rsb r4, ip, #32 + 84930: fa05 f50c lsl.w r5, r5, ip + 84934: fa21 f304 lsr.w r3, r1, r4 + 84938: 0c2a lsrs r2, r5, #16 + 8493a: fbb3 f6f2 udiv r6, r3, r2 + 8493e: fa1f fe85 uxth.w lr, r5 + 84942: fb02 3816 mls r8, r2, r6, r3 + 84946: fa20 f704 lsr.w r7, r0, r4 + 8494a: fa01 f10c lsl.w r1, r1, ip + 8494e: fb0e f906 mul.w r9, lr, r6 + 84952: 430f orrs r7, r1 + 84954: 0c3c lsrs r4, r7, #16 + 84956: ea44 4308 orr.w r3, r4, r8, lsl #16 + 8495a: 4599 cmp r9, r3 + 8495c: fa00 f40c lsl.w r4, r0, ip + 84960: d907 bls.n 84972 <__udivdi3+0x1fa> + 84962: 195b adds r3, r3, r5 + 84964: f106 31ff add.w r1, r6, #4294967295 + 84968: d238 bcs.n 849dc <__udivdi3+0x264> + 8496a: 4599 cmp r9, r3 + 8496c: d936 bls.n 849dc <__udivdi3+0x264> + 8496e: 3e02 subs r6, #2 + 84970: 442b add r3, r5 + 84972: ebc9 0303 rsb r3, r9, r3 + 84976: fbb3 f0f2 udiv r0, r3, r2 + 8497a: fb02 3310 mls r3, r2, r0, r3 + 8497e: fb0e f100 mul.w r1, lr, r0 + 84982: b2bf uxth r7, r7 + 84984: ea47 4303 orr.w r3, r7, r3, lsl #16 + 84988: 4299 cmp r1, r3 + 8498a: d907 bls.n 8499c <__udivdi3+0x224> + 8498c: 195b adds r3, r3, r5 + 8498e: f100 37ff add.w r7, r0, #4294967295 + 84992: d221 bcs.n 849d8 <__udivdi3+0x260> + 84994: 4299 cmp r1, r3 + 84996: d91f bls.n 849d8 <__udivdi3+0x260> + 84998: 3802 subs r0, #2 + 8499a: 442b add r3, r5 + 8499c: 4617 mov r7, r2 + 8499e: 1a59 subs r1, r3, r1 + 849a0: ea40 4606 orr.w r6, r0, r6, lsl #16 + 849a4: e74e b.n 84844 <__udivdi3+0xcc> + 849a6: 4610 mov r0, r2 + 849a8: e714 b.n 847d4 <__udivdi3+0x5c> + 849aa: 4613 mov r3, r2 + 849ac: e727 b.n 847fe <__udivdi3+0x86> + 849ae: 460b mov r3, r1 + 849b0: e770 b.n 84894 <__udivdi3+0x11c> + 849b2: 40b0 lsls r0, r6 + 849b4: 4290 cmp r0, r2 + 849b6: d2b6 bcs.n 84926 <__udivdi3+0x1ae> + 849b8: 1e60 subs r0, r4, #1 + 849ba: 2600 movs r6, #0 + 849bc: e722 b.n 84804 <__udivdi3+0x8c> + 849be: 4630 mov r0, r6 + 849c0: e720 b.n 84804 <__udivdi3+0x8c> + 849c2: 42bc cmp r4, r7 + 849c4: d994 bls.n 848f0 <__udivdi3+0x178> + 849c6: f1ac 0c02 sub.w ip, ip, #2 + 849ca: 441f add r7, r3 + 849cc: e791 b.n 848f2 <__udivdi3+0x17a> + 849ce: 4589 cmp r9, r1 + 849d0: d99f bls.n 84912 <__udivdi3+0x19a> + 849d2: 3c02 subs r4, #2 + 849d4: 4419 add r1, r3 + 849d6: e79d b.n 84914 <__udivdi3+0x19c> + 849d8: 4638 mov r0, r7 + 849da: e7df b.n 8499c <__udivdi3+0x224> + 849dc: 460e mov r6, r1 + 849de: e7c8 b.n 84972 <__udivdi3+0x1fa> + 849e0: 3802 subs r0, #2 + 849e2: 4429 add r1, r5 + 849e4: e741 b.n 8486a <__udivdi3+0xf2> + 849e6: bf00 nop + +000849e8 : + 849e8: 0400 1c25 02a0 0000 2d2d 4520 414d 2043 ..%.....-- EMAC + 849f8: 7845 6d61 6c70 2065 2d2d 2d0d 202d 7241 Example --.-- Ar + 84a08: 7564 6e69 206f 7544 2f65 2058 2d2d 2d0d duino Due/X --.- + 84a18: 202d 6f43 706d 6c69 6465 203a 754a 206c - Compiled: Jul + 84a28: 3831 3220 3130 2036 3332 353a 3a32 3630 18 2016 23:52:06 + 84a38: 2d20 0d2d 0000 0000 2d2d 4d20 4341 2520 --.....-- MAC % + 84a48: 3a78 7825 253a 3a78 7825 253a 3a78 7825 x:%x:%x:%x:%x:%x + 84a58: 0d0a 0000 2d2d 4920 2050 2520 2e64 6425 ....-- IP %d.%d + 84a68: 252e 2e64 6425 0d0a 0000 0000 4850 2059 .%d.%d......PHY + 84a78: 6e49 7469 6169 696c 657a 4520 5252 524f Initialize ERROR + 84a88: 0d21 0000 7541 6f74 4e20 6765 746f 6169 !...Auto Negotia + 84a98: 6574 4520 5252 524f 0d21 0000 6553 2074 te ERROR!...Set + 84aa8: 696c 6b6e 4520 5252 524f 0d21 0000 0000 link ERROR!..... + 84ab8: 694c 6b6e 6420 7465 6365 6574 2e64 0d20 Link detected. . + 84ac8: 0000 0000 3a45 4120 5052 5320 6e65 2064 ....E: ARP Send + 84ad8: 202d 7830 7825 0d0a 0000 0000 3a45 4920 - 0x%x......E: I + 84ae8: 4d43 2050 6553 646e 2d20 3020 2578 0a78 CMP Send - 0x%x. + 84af8: 000d 0000 3d3d 3d3d 3d3d 203d 5049 2520 ....======= IP % + 84b08: 6434 6220 7479 7365 202c 4548 4441 5245 4d bytes, HEADER + 84b18: 3d20 3d3d 3d3d 3d3d 3d3d 0a3d 000d 0000 ==========..... + 84b28: 4920 2050 6556 7372 6f69 206e 2020 2020 IP Version + 84b38: 2020 3d20 7620 252e 0064 0000 0d0a 4820 = v.%d..... H + 84b48: 6165 6564 2072 654c 676e 6874 2020 2020 eader Length + 84b58: 3d20 2520 0064 0000 0d0a 5420 7079 2065 = %d..... Type + 84b68: 666f 7320 7265 6976 6563 2020 3d20 3020 of service = 0 + 84b78: 2578 0078 0d0a 5420 746f 6c61 4920 2050 x%x... Total IP + 84b88: 654c 676e 6874 2020 3d20 3020 2578 0058 Length = 0x%X. + 84b98: 0d0a 4920 2044 2020 2020 2020 2020 2020 .. ID + 84ba8: 2020 2020 3d20 3020 2578 0058 0d0a 4820 = 0x%X... H + 84bb8: 6165 6564 2072 6843 6365 736b 6d75 2020 eader Checksum + 84bc8: 3d20 3020 2578 0058 200d 7250 746f 636f = 0x%X.. Protoc + 84bd8: 6c6f 2020 2020 2020 2020 2020 203d 0000 ol = .. + 84be8: 4349 504d 0000 0000 5049 0000 4354 0050 ICMP....IP..TCP. + 84bf8: 4455 0050 6425 2820 7830 5825 0029 0000 UDP.%d (0x%X)... + 84c08: 0d0a 4920 2050 7253 2063 6441 7264 7365 .. IP Src Addres + 84c18: 2073 2020 3d20 2520 3a64 6425 253a 3a64 s = %d:%d:%d: + 84c28: 6425 0000 0d0a 4920 2050 6544 7473 4120 %d.... IP Dest A + 84c38: 6464 6572 7373 2020 3d20 2520 3a64 6425 ddress = %d:%d + 84c48: 253a 3a64 6425 0000 0d0a 2d2d 2d2d 2d2d :%d:%d....------ + 84c58: 2d2d 2d2d 2d2d 2d2d 2d2d 2d2d 2d2d 2d2d ---------------- + 84c68: 2d2d 2d2d 2d2d 2d2d 2d2d 2d2d 2d2d 2d2d ---------------- + 84c78: 2d2d 000d 3d3d 203d 6544 6166 6c75 2074 --..=== Default + 84c88: 5f77 6b70 5f74 6f66 6d72 7461 203d 7830 w_pkt_format= 0x + 84c98: 5825 3d3d 0a3d 000d 0043 0000 %X===...C... + +00084ca4 <_global_impure_ptr>: + 84ca4: 0130 2007 000a 0000 0.. .... + +00084cac : + 84cac: 3030 3030 3030 3030 3030 3030 3030 3030 0000000000000000 + 84cbc: 3130 3332 3534 3736 3938 4241 4443 4645 0123456789ABCDEF + 84ccc: 0000 0000 3130 3332 3534 3736 3938 6261 ....0123456789ab + 84cdc: 6463 6665 0000 0000 6e28 6c75 296c 0000 cdef....(null).. + +00084cec : + 84cec: 2020 2020 2020 2020 2020 2020 2020 2020 + +00084cfc <_init>: + 84cfc: b5f8 push {r3, r4, r5, r6, r7, lr} + 84cfe: bf00 nop + 84d00: bcf8 pop {r3, r4, r5, r6, r7} + 84d02: bc08 pop {r3} + 84d04: 469e mov lr, r3 + 84d06: 4770 bx lr + +00084d08 <__init_array_start>: + 84d08: 00082bb5 .word 0x00082bb5 + +00084d0c <__frame_dummy_init_array_entry>: + 84d0c: 00080119 .... + +00084d10 <_fini>: + 84d10: b5f8 push {r3, r4, r5, r6, r7, lr} + 84d12: bf00 nop + 84d14: bcf8 pop {r3, r4, r5, r6, r7} + 84d16: bc08 pop {r3} + 84d18: 469e mov lr, r3 + 84d1a: 4770 bx lr + +00084d1c <__fini_array_start>: + 84d1c: 000800f5 .word 0x000800f5 + +Disassembly of section .relocate: + +20070000 : +__no_inline +RAMFUNC +void SystemInit(void) +{ + /* Set FWS according to SYS_BOARD_MCKR configuration */ + EFC0->EEFC_FMR = EEFC_FMR_FWS(4); +20070000: f44f 6380 mov.w r3, #1024 ; 0x400 +20070004: 4a20 ldr r2, [pc, #128] ; (20070088 ) +20070006: 6013 str r3, [r2, #0] + EFC1->EEFC_FMR = EEFC_FMR_FWS(4); +20070008: f502 7200 add.w r2, r2, #512 ; 0x200 +2007000c: 6013 str r3, [r2, #0] + + /* Initialize main oscillator */ + if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) { +2007000e: 4b1f ldr r3, [pc, #124] ; (2007008c ) +20070010: 6a1b ldr r3, [r3, #32] +20070012: f013 7f80 tst.w r3, #16777216 ; 0x1000000 +20070016: d107 bne.n 20070028 + PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT | +20070018: 4a1d ldr r2, [pc, #116] ; (20070090 ) +2007001a: 4b1c ldr r3, [pc, #112] ; (2007008c ) +2007001c: 621a str r2, [r3, #32] + CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN; + while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) { +2007001e: 461a mov r2, r3 +20070020: 6e93 ldr r3, [r2, #104] ; 0x68 +20070022: f013 0f01 tst.w r3, #1 +20070026: d0fb beq.n 20070020 + } + } + + /* Switch to 3-20MHz Xtal oscillator */ + PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT | +20070028: 4a1a ldr r2, [pc, #104] ; (20070094 ) +2007002a: 4b18 ldr r3, [pc, #96] ; (2007008c ) +2007002c: 621a str r2, [r3, #32] + CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL; + + while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) { +2007002e: 461a mov r2, r3 +20070030: 6e93 ldr r3, [r2, #104] ; 0x68 +20070032: f413 3f80 tst.w r3, #65536 ; 0x10000 +20070036: d0fb beq.n 20070030 + } + PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | +20070038: 4a14 ldr r2, [pc, #80] ; (2007008c ) +2007003a: 6b13 ldr r3, [r2, #48] ; 0x30 +2007003c: f023 0303 bic.w r3, r3, #3 +20070040: f043 0301 orr.w r3, r3, #1 +20070044: 6313 str r3, [r2, #48] ; 0x30 + PMC_MCKR_CSS_MAIN_CLK; + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { +20070046: 6e93 ldr r3, [r2, #104] ; 0x68 +20070048: f013 0f08 tst.w r3, #8 +2007004c: d0fb beq.n 20070046 + } + + /* Initialize PLLA */ + PMC->CKGR_PLLAR = SYS_BOARD_PLLAR; +2007004e: 4a12 ldr r2, [pc, #72] ; (20070098 ) +20070050: 4b0e ldr r3, [pc, #56] ; (2007008c ) +20070052: 629a str r2, [r3, #40] ; 0x28 + while (!(PMC->PMC_SR & PMC_SR_LOCKA)) { +20070054: 461a mov r2, r3 +20070056: 6e93 ldr r3, [r2, #104] ; 0x68 +20070058: f013 0f02 tst.w r3, #2 +2007005c: d0fb beq.n 20070056 + } + + /* Switch to main clock */ + PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK; +2007005e: 2211 movs r2, #17 +20070060: 4b0a ldr r3, [pc, #40] ; (2007008c ) +20070062: 631a str r2, [r3, #48] ; 0x30 + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { +20070064: 461a mov r2, r3 +20070066: 6e93 ldr r3, [r2, #104] ; 0x68 +20070068: f013 0f08 tst.w r3, #8 +2007006c: d0fb beq.n 20070066 + } + + /* Switch to PLLA */ + PMC->PMC_MCKR = SYS_BOARD_MCKR; +2007006e: 2212 movs r2, #18 +20070070: 4b06 ldr r3, [pc, #24] ; (2007008c ) +20070072: 631a str r2, [r3, #48] ; 0x30 + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { +20070074: 461a mov r2, r3 +20070076: 6e93 ldr r3, [r2, #104] ; 0x68 +20070078: f013 0f08 tst.w r3, #8 +2007007c: d0fb beq.n 20070076 + } + + SystemCoreClock = CHIP_FREQ_CPU_MAX; +2007007e: 4a07 ldr r2, [pc, #28] ; (2007009c ) +20070080: 4b07 ldr r3, [pc, #28] ; (200700a0 ) +20070082: 601a str r2, [r3, #0] +20070084: 4770 bx lr +20070086: bf00 nop +20070088: 400e0a00 .word 0x400e0a00 +2007008c: 400e0600 .word 0x400e0600 +20070090: 00370809 .word 0x00370809 +20070094: 01370809 .word 0x01370809 +20070098: 200d3f01 .word 0x200d3f01 +2007009c: 0501bd00 .word 0x0501bd00 +200700a0: 2007012c .word 0x2007012c + +200700a4 : +__no_inline +RAMFUNC +void system_init_flash(uint32_t ul_clk) +{ + /* Set FWS for embedded Flash access according to operating frequency */ + if (ul_clk < CHIP_FREQ_FWS_0) { +200700a4: 4b1b ldr r3, [pc, #108] ; (20070114 ) +200700a6: 4298 cmp r0, r3 +200700a8: d806 bhi.n 200700b8 + EFC0->EEFC_FMR = EEFC_FMR_FWS(0); +200700aa: 2300 movs r3, #0 +200700ac: 4a1a ldr r2, [pc, #104] ; (20070118 ) +200700ae: 6013 str r3, [r2, #0] + EFC1->EEFC_FMR = EEFC_FMR_FWS(0); +200700b0: f502 7200 add.w r2, r2, #512 ; 0x200 +200700b4: 6013 str r3, [r2, #0] +200700b6: 4770 bx lr + } else if (ul_clk < CHIP_FREQ_FWS_1) { +200700b8: 4b18 ldr r3, [pc, #96] ; (2007011c ) +200700ba: 4298 cmp r0, r3 +200700bc: d807 bhi.n 200700ce + EFC0->EEFC_FMR = EEFC_FMR_FWS(1); +200700be: f44f 7380 mov.w r3, #256 ; 0x100 +200700c2: 4a15 ldr r2, [pc, #84] ; (20070118 ) +200700c4: 6013 str r3, [r2, #0] + EFC1->EEFC_FMR = EEFC_FMR_FWS(1); +200700c6: f502 7200 add.w r2, r2, #512 ; 0x200 +200700ca: 6013 str r3, [r2, #0] +200700cc: 4770 bx lr + } else if (ul_clk < CHIP_FREQ_FWS_2) { +200700ce: 4b14 ldr r3, [pc, #80] ; (20070120 ) +200700d0: 4298 cmp r0, r3 +200700d2: d807 bhi.n 200700e4 + EFC0->EEFC_FMR = EEFC_FMR_FWS(2); +200700d4: f44f 7300 mov.w r3, #512 ; 0x200 +200700d8: 4a0f ldr r2, [pc, #60] ; (20070118 ) +200700da: 6013 str r3, [r2, #0] + EFC1->EEFC_FMR = EEFC_FMR_FWS(2); +200700dc: f502 7200 add.w r2, r2, #512 ; 0x200 +200700e0: 6013 str r3, [r2, #0] +200700e2: 4770 bx lr + } else if (ul_clk < CHIP_FREQ_FWS_3) { +200700e4: 4b0f ldr r3, [pc, #60] ; (20070124 ) +200700e6: 4298 cmp r0, r3 +200700e8: d807 bhi.n 200700fa + EFC0->EEFC_FMR = EEFC_FMR_FWS(3); +200700ea: f44f 7340 mov.w r3, #768 ; 0x300 +200700ee: 4a0a ldr r2, [pc, #40] ; (20070118 ) +200700f0: 6013 str r3, [r2, #0] + EFC1->EEFC_FMR = EEFC_FMR_FWS(3); +200700f2: f502 7200 add.w r2, r2, #512 ; 0x200 +200700f6: 6013 str r3, [r2, #0] +200700f8: 4770 bx lr + } else if (ul_clk < CHIP_FREQ_FWS_4) { +200700fa: 4b0b ldr r3, [pc, #44] ; (20070128 ) +200700fc: 4298 cmp r0, r3 + EFC0->EEFC_FMR = EEFC_FMR_FWS(4); +200700fe: bf94 ite ls +20070100: f44f 6380 movls.w r3, #1024 ; 0x400 + EFC1->EEFC_FMR = EEFC_FMR_FWS(4); + } else { + EFC0->EEFC_FMR = EEFC_FMR_FWS(5); +20070104: f44f 63a0 movhi.w r3, #1280 ; 0x500 +20070108: 4a03 ldr r2, [pc, #12] ; (20070118 ) +2007010a: 6013 str r3, [r2, #0] + EFC1->EEFC_FMR = EEFC_FMR_FWS(5); +2007010c: f502 7200 add.w r2, r2, #512 ; 0x200 +20070110: 6013 str r3, [r2, #0] +20070112: 4770 bx lr +20070114: 0121eabf .word 0x0121eabf +20070118: 400e0a00 .word 0x400e0a00 +2007011c: 02faf07f .word 0x02faf07f +20070120: 03d08fff .word 0x03d08fff +20070124: 04c4b3ff .word 0x04c4b3ff +20070128: 055d4a7f .word 0x055d4a7f + +2007012c : +2007012c: 003d0900 ..=. + +20070130 : +20070130: 00000000 2007041c 20070484 200704ec ....... ... ... + ... +20070164: 00084ca0 00000000 00000000 00000000 .L.............. + ... +200701d8: 00000001 00000000 abcd330e e66d1234 .........3..4.m. +200701e8: 0005deec 0000000b 00000000 00000000 ................ + ... + +20070558 <_impure_ptr>: +20070558: 20070130 0.. + +2007055c : +2007055c: 49435341 00000049 00000000 00000000 ASCII........... + ... + +2007057c <__mb_cur_max>: +2007057c: 00000001 .... + +20070580 <__malloc_av_>: + ... +20070588: 20070580 20070580 20070588 20070588 ... ... ... ... +20070598: 20070590 20070590 20070598 20070598 ... ... ... ... +200705a8: 200705a0 200705a0 200705a8 200705a8 ... ... ... ... +200705b8: 200705b0 200705b0 200705b8 200705b8 ... ... ... ... +200705c8: 200705c0 200705c0 200705c8 200705c8 ... ... ... ... +200705d8: 200705d0 200705d0 200705d8 200705d8 ... ... ... ... +200705e8: 200705e0 200705e0 200705e8 200705e8 ... ... ... ... +200705f8: 200705f0 200705f0 200705f8 200705f8 ... ... ... ... +20070608: 20070600 20070600 20070608 20070608 ... ... ... ... +20070618: 20070610 20070610 20070618 20070618 ... ... ... ... +20070628: 20070620 20070620 20070628 20070628 .. .. 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src/ASF/common/utils/stdio/write.o +LOAD src/ASF/sam/boards/sam3x_ek/init.o +LOAD src/ASF/sam/boards/sam3x_ek/led.o +LOAD src/ASF/sam/components/ethernet_phy/dm9161a/ethernet_phy.o +LOAD src/ASF/sam/drivers/emac/emac.o +LOAD src/ASF/sam/drivers/pio/pio.o +LOAD src/ASF/sam/drivers/pio/pio_handler.o +LOAD src/ASF/sam/drivers/pmc/pmc.o +LOAD src/ASF/sam/drivers/pmc/sleep.o +LOAD src/ASF/sam/drivers/rstc/rstc.o +LOAD src/ASF/sam/drivers/uart/uart.o +LOAD src/ASF/sam/drivers/usart/usart.o +LOAD src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.o +LOAD src/ASF/sam/utils/cmsis/sam3x/source/templates/gcc/startup_sam3x.o +LOAD src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.o +LOAD src/ASF/sam/utils/syscalls/gcc/syscalls.o +LOAD src/emac_example.o +START GROUP +LOAD ..\src\ASF\thirdparty\CMSIS\Lib\GCC\libarm_cortexM3l_math.a +LOAD c:/program files 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+_isatty src/ASF/sam/utils/syscalls/gcc/syscalls.o + c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-isattyr.o) +_isatty_r c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-isattyr.o) + c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-makebuf.o) +_kill src/ASF/sam/utils/syscalls/gcc/syscalls.o +_localeconv_r c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-locale.o) +_lseek src/ASF/sam/utils/syscalls/gcc/syscalls.o + c:/program files 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(x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-mallocr.o) + c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-freer.o) +_setlocale_r c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-locale.o) +_sfixed src/ASF/sam/utils/cmsis/sam3x/source/templates/gcc/startup_sam3x.o +_srelocate src/ASF/sam/utils/cmsis/sam3x/source/templates/gcc/startup_sam3x.o +_start c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m/crt0.o +_szero src/ASF/sam/utils/cmsis/sam3x/source/templates/gcc/startup_sam3x.o +_vfiprintf_r c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-vfiprintf.o) + c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-iprintf.o) +_wcrtomb_r c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-wcrtomb.o) + c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-fputwc.o) +_wctomb_r c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-wctomb_r.o) +_write src/ASF/common/utils/stdio/write.o + c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-writer.o) +_write_r c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-writer.o) + c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-stdio.o) +atexit c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-atexit.o) + c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-__call_atexit.o) + c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m/crt0.o +board_init src/ASF/sam/boards/sam3x_ek/init.o + src/emac_example.o +cleanup_glue c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-reent.o) +cpu_irq_enter_critical src/ASF/common/utils/interrupt/interrupt_sam_nvic.o +cpu_irq_leave_critical src/ASF/common/utils/interrupt/interrupt_sam_nvic.o +emac_dev_get_tx_load src/ASF/sam/drivers/emac/emac.o +emac_dev_init src/ASF/sam/drivers/emac/emac.o + src/emac_example.o +emac_dev_read src/ASF/sam/drivers/emac/emac.o + src/emac_example.o +emac_dev_reset src/ASF/sam/drivers/emac/emac.o +emac_dev_set_rx_callback src/ASF/sam/drivers/emac/emac.o +emac_dev_set_tx_wakeup_callback src/ASF/sam/drivers/emac/emac.o +emac_dev_write src/ASF/sam/drivers/emac/emac.o + src/emac_example.o +emac_handler src/ASF/sam/drivers/emac/emac.o + src/emac_example.o +emac_phy_read src/ASF/sam/drivers/emac/emac.o + src/ASF/sam/components/ethernet_phy/dm9161a/ethernet_phy.o +emac_phy_write src/ASF/sam/drivers/emac/emac.o + src/ASF/sam/components/ethernet_phy/dm9161a/ethernet_phy.o +errno c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-reent.o) + c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-readr.o) + c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-lseekr.o) + c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-isattyr.o) + c:/program files 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src/ASF/sam/components/ethernet_phy/dm9161a/ethernet_phy.o + src/emac_example.o +exception_table src/ASF/sam/utils/cmsis/sam3x/source/templates/gcc/startup_sam3x.o +exit c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-exit.o) + c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m/crt0.o +fclose c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-fclose.o) +fflush c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-fflush.o) +fputwc c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-fputwc.o) +free c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-malloc.o) + c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-__call_atexit.o) +g_interrupt_enabled src/ASF/common/utils/interrupt/interrupt_sam_nvic.o + src/ASF/sam/drivers/pmc/sleep.o +hardware_init_hook c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m/crt0.o +iprintf c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-iprintf.o) + src/emac_example.o + src/ASF/sam/utils/syscalls/gcc/syscalls.o +link src/ASF/sam/utils/syscalls/gcc/syscalls.o +localeconv c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-locale.o) +main src/emac_example.o + src/ASF/sam/utils/cmsis/sam3x/source/templates/gcc/startup_sam3x.o + c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m/crt0.o +malloc c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-malloc.o) + c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-__atexit.o) + c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-setvbuf.o) +memchr c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-memchr.o) + c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-fvwrite.o) + c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-vfiprintf.o) +memcpy c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-memcpy.o) + c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-fvwrite.o) + src/ASF/sam/drivers/emac/emac.o +memmove c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-memmove.o) + c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-reallocr.o) + c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-fvwrite.o) +memset c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-memset.o) + c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-findfp.o) + c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m/crt0.o +pio_clear src/ASF/sam/drivers/pio/pio.o +pio_configure src/ASF/sam/drivers/pio/pio.o +pio_configure_interrupt src/ASF/sam/drivers/pio/pio.o + src/ASF/sam/drivers/pio/pio_handler.o +pio_configure_pin src/ASF/sam/drivers/pio/pio.o + src/ASF/sam/boards/sam3x_ek/init.o +pio_configure_pin_group src/ASF/sam/drivers/pio/pio.o + src/ASF/sam/boards/sam3x_ek/init.o +pio_disable_interrupt src/ASF/sam/drivers/pio/pio.o + src/ASF/sam/drivers/pio/pio_handler.o +pio_disable_output_write src/ASF/sam/drivers/pio/pio.o +pio_disable_pin_interrupt src/ASF/sam/drivers/pio/pio.o +pio_enable_interrupt src/ASF/sam/drivers/pio/pio.o + src/ASF/sam/drivers/pio/pio_handler.o +pio_enable_output_write src/ASF/sam/drivers/pio/pio.o +pio_enable_pin_interrupt src/ASF/sam/drivers/pio/pio.o +pio_get src/ASF/sam/drivers/pio/pio.o +pio_get_interrupt_mask src/ASF/sam/drivers/pio/pio.o + src/ASF/sam/drivers/pio/pio_handler.o +pio_get_interrupt_status src/ASF/sam/drivers/pio/pio.o + src/ASF/sam/drivers/pio/pio_handler.o +pio_get_multi_driver_status src/ASF/sam/drivers/pio/pio.o +pio_get_output_data_status src/ASF/sam/drivers/pio/pio.o +pio_get_output_write_status src/ASF/sam/drivers/pio/pio.o +pio_get_pin_group src/ASF/sam/drivers/pio/pio.o + src/ASF/sam/drivers/pio/pio_handler.o +pio_get_pin_group_id src/ASF/sam/drivers/pio/pio.o + src/ASF/sam/drivers/pio/pio_handler.o +pio_get_pin_group_mask src/ASF/sam/drivers/pio/pio.o + src/ASF/sam/drivers/pio/pio_handler.o +pio_get_pin_value src/ASF/sam/drivers/pio/pio.o +pio_get_writeprotect_status src/ASF/sam/drivers/pio/pio.o +pio_handler_process src/ASF/sam/drivers/pio/pio_handler.o +pio_handler_set src/ASF/sam/drivers/pio/pio_handler.o +pio_handler_set_pin src/ASF/sam/drivers/pio/pio_handler.o +pio_handler_set_priority src/ASF/sam/drivers/pio/pio_handler.o +pio_pull_up src/ASF/sam/drivers/pio/pio.o +pio_set src/ASF/sam/drivers/pio/pio.o +pio_set_additional_interrupt_mode src/ASF/sam/drivers/pio/pio.o +pio_set_debounce_filter src/ASF/sam/drivers/pio/pio.o +pio_set_input src/ASF/sam/drivers/pio/pio.o +pio_set_multi_driver src/ASF/sam/drivers/pio/pio.o +pio_set_output src/ASF/sam/drivers/pio/pio.o +pio_set_peripheral src/ASF/sam/drivers/pio/pio.o +pio_set_pin_group_high src/ASF/sam/drivers/pio/pio.o +pio_set_pin_group_low src/ASF/sam/drivers/pio/pio.o +pio_set_pin_high src/ASF/sam/drivers/pio/pio.o + src/ASF/sam/boards/sam3x_ek/led.o +pio_set_pin_low src/ASF/sam/drivers/pio/pio.o + src/ASF/sam/boards/sam3x_ek/led.o +pio_set_writeprotect src/ASF/sam/drivers/pio/pio.o +pio_sync_output_write src/ASF/sam/drivers/pio/pio.o +pio_toggle_pin src/ASF/sam/drivers/pio/pio.o +pio_toggle_pin_group src/ASF/sam/drivers/pio/pio.o +pmc_clr_fast_startup_input src/ASF/sam/drivers/pmc/pmc.o +pmc_disable_all_pck src/ASF/sam/drivers/pmc/pmc.o +pmc_disable_all_periph_clk src/ASF/sam/drivers/pmc/pmc.o +pmc_disable_clock_failure_detector src/ASF/sam/drivers/pmc/pmc.o +pmc_disable_interrupt src/ASF/sam/drivers/pmc/pmc.o +pmc_disable_pck src/ASF/sam/drivers/pmc/pmc.o +pmc_disable_periph_clk src/ASF/sam/drivers/pmc/pmc.o +pmc_disable_pllack src/ASF/sam/drivers/pmc/pmc.o + src/ASF/sam/drivers/pmc/sleep.o + src/ASF/common/services/clock/sam3x/sysclk.o +pmc_disable_udpck src/ASF/sam/drivers/pmc/pmc.o +pmc_disable_upll_clock src/ASF/sam/drivers/pmc/pmc.o + src/ASF/sam/drivers/pmc/sleep.o +pmc_enable_all_pck src/ASF/sam/drivers/pmc/pmc.o +pmc_enable_all_periph_clk src/ASF/sam/drivers/pmc/pmc.o +pmc_enable_backupmode src/ASF/sam/drivers/pmc/pmc.o +pmc_enable_clock_failure_detector src/ASF/sam/drivers/pmc/pmc.o +pmc_enable_interrupt src/ASF/sam/drivers/pmc/pmc.o +pmc_enable_pck src/ASF/sam/drivers/pmc/pmc.o +pmc_enable_periph_clk src/ASF/sam/drivers/pmc/pmc.o + src/emac_example.o + src/ASF/sam/boards/sam3x_ek/init.o +pmc_enable_pllack src/ASF/sam/drivers/pmc/pmc.o +pmc_enable_sleepmode src/ASF/sam/drivers/pmc/pmc.o +pmc_enable_udpck src/ASF/sam/drivers/pmc/pmc.o +pmc_enable_upll_clock src/ASF/sam/drivers/pmc/pmc.o +pmc_enable_waitmode src/ASF/sam/drivers/pmc/pmc.o + src/ASF/sam/drivers/pmc/sleep.o +pmc_get_interrupt_mask src/ASF/sam/drivers/pmc/pmc.o +pmc_get_status src/ASF/sam/drivers/pmc/pmc.o +pmc_get_writeprotect_status src/ASF/sam/drivers/pmc/pmc.o +pmc_is_locked_pllack src/ASF/sam/drivers/pmc/pmc.o + src/ASF/common/services/clock/sam3x/sysclk.o +pmc_is_locked_upll src/ASF/sam/drivers/pmc/pmc.o +pmc_is_pck_enabled src/ASF/sam/drivers/pmc/pmc.o +pmc_is_periph_clk_enabled src/ASF/sam/drivers/pmc/pmc.o +pmc_is_wakeup_clocks_restored src/ASF/sam/drivers/pmc/sleep.o +pmc_mainck_osc_select src/ASF/sam/drivers/pmc/pmc.o +pmc_mck_set_prescaler src/ASF/sam/drivers/pmc/pmc.o + src/ASF/common/services/clock/sam3x/sysclk.o +pmc_mck_set_source src/ASF/sam/drivers/pmc/pmc.o + src/ASF/common/services/clock/sam3x/sysclk.o +pmc_osc_bypass_main_xtal src/ASF/sam/drivers/pmc/pmc.o +pmc_osc_disable_fastrc src/ASF/sam/drivers/pmc/pmc.o +pmc_osc_disable_main_xtal src/ASF/sam/drivers/pmc/pmc.o +pmc_osc_disable_xtal src/ASF/sam/drivers/pmc/pmc.o +pmc_osc_enable_fastrc src/ASF/sam/drivers/pmc/pmc.o +pmc_osc_enable_main_xtal src/ASF/sam/drivers/pmc/pmc.o +pmc_osc_is_bypassed_main_xtal src/ASF/sam/drivers/pmc/pmc.o +pmc_osc_is_ready_32kxtal src/ASF/sam/drivers/pmc/pmc.o +pmc_osc_is_ready_fastrc src/ASF/sam/drivers/pmc/pmc.o +pmc_osc_is_ready_main_xtal src/ASF/sam/drivers/pmc/pmc.o +pmc_osc_is_ready_mainck src/ASF/sam/drivers/pmc/pmc.o + src/ASF/common/services/clock/sam3x/sysclk.o +pmc_pck_set_prescaler src/ASF/sam/drivers/pmc/pmc.o +pmc_pck_set_source src/ASF/sam/drivers/pmc/pmc.o +pmc_set_fast_startup_input src/ASF/sam/drivers/pmc/pmc.o +pmc_set_writeprotect src/ASF/sam/drivers/pmc/pmc.o +pmc_sleep src/ASF/sam/drivers/pmc/sleep.o +pmc_switch_mainck_to_fastrc src/ASF/sam/drivers/pmc/pmc.o +pmc_switch_mainck_to_xtal src/ASF/sam/drivers/pmc/pmc.o + src/ASF/common/services/clock/sam3x/sysclk.o +pmc_switch_mck_to_mainck src/ASF/sam/drivers/pmc/pmc.o +pmc_switch_mck_to_pllack src/ASF/sam/drivers/pmc/pmc.o + src/ASF/common/services/clock/sam3x/sysclk.o +pmc_switch_mck_to_sclk src/ASF/sam/drivers/pmc/pmc.o +pmc_switch_mck_to_upllck src/ASF/sam/drivers/pmc/pmc.o +pmc_switch_pck_to_mainck src/ASF/sam/drivers/pmc/pmc.o +pmc_switch_pck_to_mck src/ASF/sam/drivers/pmc/pmc.o +pmc_switch_pck_to_pllack src/ASF/sam/drivers/pmc/pmc.o +pmc_switch_pck_to_sclk src/ASF/sam/drivers/pmc/pmc.o +pmc_switch_pck_to_upllck src/ASF/sam/drivers/pmc/pmc.o +pmc_switch_sclk_to_32kxtal src/ASF/sam/drivers/pmc/pmc.o +pmc_switch_udpck_to_pllack src/ASF/sam/drivers/pmc/pmc.o +pmc_switch_udpck_to_upllck src/ASF/sam/drivers/pmc/pmc.o +pmc_wait_wakeup_clocks_restore src/ASF/sam/drivers/pmc/sleep.o +ptr_get src/ASF/common/utils/stdio/read.o + src/emac_example.o +ptr_put src/ASF/common/utils/stdio/write.o + src/emac_example.o +puts c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-puts.o) + src/emac_example.o +rstc_disable_user_reset src/ASF/sam/drivers/rstc/rstc.o +rstc_disable_user_reset_interrupt src/ASF/sam/drivers/rstc/rstc.o +rstc_enable_user_reset src/ASF/sam/drivers/rstc/rstc.o +rstc_enable_user_reset_interrupt src/ASF/sam/drivers/rstc/rstc.o +rstc_get_reset_cause src/ASF/sam/drivers/rstc/rstc.o +rstc_get_status src/ASF/sam/drivers/rstc/rstc.o + src/emac_example.o +rstc_reset_extern src/ASF/sam/drivers/rstc/rstc.o + src/emac_example.o +rstc_set_external_reset src/ASF/sam/drivers/rstc/rstc.o + src/emac_example.o +rstc_start_software_reset src/ASF/sam/drivers/rstc/rstc.o +setbuf c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-setbuf.o) + src/emac_example.o +setlocale c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-locale.o) +setvbuf c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-setvbuf.o) + c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-setbuf.o) +software_init_hook c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m/crt0.o +stdio_base src/ASF/common/utils/stdio/write.o + src/emac_example.o + src/ASF/common/utils/stdio/read.o +strcmp c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-strcmp.o) + c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-locale.o) +strlen c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-strlen.o) + c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-vfiprintf.o) + c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-puts.o) +sysclk_init src/ASF/common/services/clock/sam3x/sysclk.o + src/emac_example.o +sysclk_set_prescalers src/ASF/common/services/clock/sam3x/sysclk.o +sysclk_set_source src/ASF/common/services/clock/sam3x/sysclk.o +system_init_flash src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.o + src/ASF/common/services/clock/sam3x/sysclk.o +uart_disable src/ASF/sam/drivers/uart/uart.o +uart_disable_interrupt src/ASF/sam/drivers/uart/uart.o +uart_disable_rx src/ASF/sam/drivers/uart/uart.o +uart_disable_tx src/ASF/sam/drivers/uart/uart.o +uart_enable src/ASF/sam/drivers/uart/uart.o +uart_enable_interrupt src/ASF/sam/drivers/uart/uart.o +uart_enable_rx src/ASF/sam/drivers/uart/uart.o +uart_enable_tx src/ASF/sam/drivers/uart/uart.o +uart_get_interrupt_mask src/ASF/sam/drivers/uart/uart.o +uart_get_pdc_base src/ASF/sam/drivers/uart/uart.o +uart_get_status src/ASF/sam/drivers/uart/uart.o +uart_init src/ASF/sam/drivers/uart/uart.o + src/emac_example.o +uart_is_rx_buf_end src/ASF/sam/drivers/uart/uart.o +uart_is_rx_buf_full src/ASF/sam/drivers/uart/uart.o +uart_is_rx_ready src/ASF/sam/drivers/uart/uart.o +uart_is_tx_buf_empty src/ASF/sam/drivers/uart/uart.o +uart_is_tx_buf_end src/ASF/sam/drivers/uart/uart.o +uart_is_tx_empty src/ASF/sam/drivers/uart/uart.o +uart_is_tx_ready src/ASF/sam/drivers/uart/uart.o +uart_read src/ASF/sam/drivers/uart/uart.o + src/emac_example.o + src/ASF/common/services/serial/usart_serial.o +uart_reset src/ASF/sam/drivers/uart/uart.o +uart_reset_rx src/ASF/sam/drivers/uart/uart.o +uart_reset_status src/ASF/sam/drivers/uart/uart.o +uart_reset_tx src/ASF/sam/drivers/uart/uart.o +uart_set_clock_divisor src/ASF/sam/drivers/uart/uart.o +uart_write src/ASF/sam/drivers/uart/uart.o + src/emac_example.o + src/ASF/common/services/serial/usart_serial.o +usart_disable_interrupt src/ASF/sam/drivers/usart/usart.o +usart_disable_rx src/ASF/sam/drivers/usart/usart.o +usart_disable_tx src/ASF/sam/drivers/usart/usart.o +usart_disable_writeprotect src/ASF/sam/drivers/usart/usart.o +usart_drive_RTS_pin_high src/ASF/sam/drivers/usart/usart.o +usart_drive_RTS_pin_low src/ASF/sam/drivers/usart/usart.o +usart_enable_interrupt src/ASF/sam/drivers/usart/usart.o +usart_enable_rx src/ASF/sam/drivers/usart/usart.o +usart_enable_tx src/ASF/sam/drivers/usart/usart.o +usart_enable_writeprotect src/ASF/sam/drivers/usart/usart.o +usart_get_error_number src/ASF/sam/drivers/usart/usart.o +usart_get_interrupt_mask src/ASF/sam/drivers/usart/usart.o +usart_get_pdc_base src/ASF/sam/drivers/usart/usart.o +usart_get_rx_access src/ASF/sam/drivers/usart/usart.o +usart_get_status src/ASF/sam/drivers/usart/usart.o +usart_get_tx_access src/ASF/sam/drivers/usart/usart.o +usart_get_writeprotect_status src/ASF/sam/drivers/usart/usart.o +usart_getchar src/ASF/sam/drivers/usart/usart.o +usart_init_hw_handshaking src/ASF/sam/drivers/usart/usart.o +usart_init_irda src/ASF/sam/drivers/usart/usart.o +usart_init_iso7816 src/ASF/sam/drivers/usart/usart.o +usart_init_lin_master src/ASF/sam/drivers/usart/usart.o +usart_init_lin_slave src/ASF/sam/drivers/usart/usart.o +usart_init_rs232 src/ASF/sam/drivers/usart/usart.o +usart_init_rs485 src/ASF/sam/drivers/usart/usart.o +usart_init_spi_master src/ASF/sam/drivers/usart/usart.o +usart_init_spi_slave src/ASF/sam/drivers/usart/usart.o +usart_init_sync_master src/ASF/sam/drivers/usart/usart.o +usart_init_sync_slave src/ASF/sam/drivers/usart/usart.o +usart_is_rx_buf_end src/ASF/sam/drivers/usart/usart.o +usart_is_rx_buf_full src/ASF/sam/drivers/usart/usart.o +usart_is_rx_ready src/ASF/sam/drivers/usart/usart.o +usart_is_tx_buf_empty src/ASF/sam/drivers/usart/usart.o +usart_is_tx_buf_end src/ASF/sam/drivers/usart/usart.o +usart_is_tx_empty src/ASF/sam/drivers/usart/usart.o +usart_is_tx_ready src/ASF/sam/drivers/usart/usart.o +usart_lin_abort_tx src/ASF/sam/drivers/usart/usart.o +usart_lin_disable_checksum src/ASF/sam/drivers/usart/usart.o +usart_lin_disable_frame_slot src/ASF/sam/drivers/usart/usart.o +usart_lin_disable_parity src/ASF/sam/drivers/usart/usart.o +usart_lin_disable_pdc_mode src/ASF/sam/drivers/usart/usart.o +usart_lin_enable_checksum src/ASF/sam/drivers/usart/usart.o +usart_lin_enable_frame_slot src/ASF/sam/drivers/usart/usart.o +usart_lin_enable_parity src/ASF/sam/drivers/usart/usart.o +usart_lin_enable_pdc_mode src/ASF/sam/drivers/usart/usart.o +usart_lin_get_data_length src/ASF/sam/drivers/usart/usart.o +usart_lin_read_identifier src/ASF/sam/drivers/usart/usart.o +usart_lin_send_wakeup_signal src/ASF/sam/drivers/usart/usart.o +usart_lin_set_checksum_type src/ASF/sam/drivers/usart/usart.o +usart_lin_set_data_len_mode src/ASF/sam/drivers/usart/usart.o +usart_lin_set_node_action src/ASF/sam/drivers/usart/usart.o +usart_lin_set_response_data_len src/ASF/sam/drivers/usart/usart.o +usart_lin_set_tx_identifier src/ASF/sam/drivers/usart/usart.o +usart_lin_set_wakeup_signal_type src/ASF/sam/drivers/usart/usart.o +usart_man_disable_drift_compensation src/ASF/sam/drivers/usart/usart.o +usart_man_enable_drift_compensation src/ASF/sam/drivers/usart/usart.o +usart_man_set_rx_polarity src/ASF/sam/drivers/usart/usart.o +usart_man_set_rx_pre_len src/ASF/sam/drivers/usart/usart.o +usart_man_set_rx_pre_pattern src/ASF/sam/drivers/usart/usart.o +usart_man_set_tx_polarity src/ASF/sam/drivers/usart/usart.o +usart_man_set_tx_pre_len src/ASF/sam/drivers/usart/usart.o +usart_man_set_tx_pre_pattern src/ASF/sam/drivers/usart/usart.o +usart_putchar src/ASF/sam/drivers/usart/usart.o +usart_read src/ASF/sam/drivers/usart/usart.o + src/emac_example.o + src/ASF/common/services/serial/usart_serial.o +usart_reset src/ASF/sam/drivers/usart/usart.o +usart_reset_iterations src/ASF/sam/drivers/usart/usart.o +usart_reset_nack src/ASF/sam/drivers/usart/usart.o +usart_reset_rx src/ASF/sam/drivers/usart/usart.o +usart_reset_status src/ASF/sam/drivers/usart/usart.o +usart_reset_tx src/ASF/sam/drivers/usart/usart.o +usart_restart_rx_timeout src/ASF/sam/drivers/usart/usart.o +usart_send_address src/ASF/sam/drivers/usart/usart.o +usart_serial_read_packet src/ASF/common/services/serial/usart_serial.o +usart_serial_write_packet src/ASF/common/services/serial/usart_serial.o +usart_set_async_baudrate src/ASF/sam/drivers/usart/usart.o +usart_set_rx_timeout src/ASF/sam/drivers/usart/usart.o +usart_set_tx_timeguard src/ASF/sam/drivers/usart/usart.o +usart_spi_force_chip_select src/ASF/sam/drivers/usart/usart.o +usart_spi_release_chip_select src/ASF/sam/drivers/usart/usart.o +usart_start_rx_timeout src/ASF/sam/drivers/usart/usart.o +usart_start_tx_break src/ASF/sam/drivers/usart/usart.o +usart_stop_tx_break src/ASF/sam/drivers/usart/usart.o +usart_write src/ASF/sam/drivers/usart/usart.o + src/emac_example.o + src/ASF/common/services/serial/usart_serial.o +usart_write_line src/ASF/sam/drivers/usart/usart.o +vfiprintf c:/program files (x86)/atmel7/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/4.9.3/../../../../arm-none-eabi/lib/armv7-m\libc.a(lib_a-vfiprintf.o) +wcrtomb c:/program files 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+################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL := cmd.exe +RM := rm -rf + +USER_OBJS := + +LIBS := +PROJ := + +O_SRCS := +C_SRCS := +S_SRCS := +S_UPPER_SRCS := +OBJ_SRCS := +ASM_SRCS := +PREPROCESSING_SRCS := +OBJS := +OBJS_AS_ARGS := +C_DEPS := +C_DEPS_AS_ARGS := +EXECUTABLES := +OUTPUT_FILE_PATH := +OUTPUT_FILE_PATH_AS_ARGS := +AVR_APP_PATH :=$$$AVR_APP_PATH$$$ +QUOTE := " +ADDITIONAL_DEPENDENCIES:= +OUTPUT_FILE_DEP:= +LIB_DEP:= +LINKER_SCRIPT_DEP:= + +# Every subdirectory with source files must be described here +SUBDIRS := \ +../src/ \ +../src/ASF/ \ +../src/ASF/common/ \ +../src/ASF/common/boards/ \ +../src/ASF/common/services/ \ +../src/ASF/common/services/clock/ \ +../src/ASF/common/services/clock/sam3x/ \ +../src/ASF/common/services/gpio/ \ +../src/ASF/common/services/gpio/sam_gpio/ \ +../src/ASF/common/services/ioport/ \ +../src/ASF/common/services/ioport/sam/ \ +../src/ASF/common/services/serial/ \ +../src/ASF/common/services/serial/sam_uart/ \ +../src/ASF/common/utils/ \ +../src/ASF/common/utils/interrupt/ \ +../src/ASF/common/utils/stdio/ \ +../src/ASF/common/utils/stdio/stdio_serial/ \ +../src/ASF/sam/ \ +../src/ASF/sam/boards/ \ +../src/ASF/sam/boards/sam3x_ek/ \ +../src/ASF/sam/components/ \ +../src/ASF/sam/components/ethernet_phy/ \ +../src/ASF/sam/components/ethernet_phy/dm9161a/ \ +../src/ASF/sam/drivers/ \ +../src/ASF/sam/drivers/emac/ \ +../src/ASF/sam/drivers/pio/ \ +../src/ASF/sam/drivers/pmc/ \ +../src/ASF/sam/drivers/rstc/ \ +../src/ASF/sam/drivers/rstc/example1/ \ +../src/ASF/sam/drivers/uart/ \ +../src/ASF/sam/drivers/usart/ \ +../src/ASF/sam/utils/ \ +../src/ASF/sam/utils/cmsis/ \ +../src/ASF/sam/utils/cmsis/sam3x/ \ +../src/ASF/sam/utils/cmsis/sam3x/include/ \ +../src/ASF/sam/utils/cmsis/sam3x/include/component/ \ +../src/ASF/sam/utils/cmsis/sam3x/include/instance/ \ +../src/ASF/sam/utils/cmsis/sam3x/include/pio/ \ +../src/ASF/sam/utils/cmsis/sam3x/source/ \ +../src/ASF/sam/utils/cmsis/sam3x/source/templates/ \ +../src/ASF/sam/utils/cmsis/sam3x/source/templates/gcc/ \ +../src/ASF/sam/utils/header_files/ \ +../src/ASF/sam/utils/linker_scripts/ \ +../src/ASF/sam/utils/linker_scripts/sam3x/ \ +../src/ASF/sam/utils/linker_scripts/sam3x/sam3x8/ \ +../src/ASF/sam/utils/linker_scripts/sam3x/sam3x8/gcc/ \ +../src/ASF/sam/utils/make/ \ +../src/ASF/sam/utils/preprocessor/ \ +../src/ASF/sam/utils/syscalls/ \ +../src/ASF/sam/utils/syscalls/gcc/ \ +../src/ASF/thirdparty/ \ +../src/ASF/thirdparty/CMSIS/ \ +../src/ASF/thirdparty/CMSIS/Include/ \ +../src/ASF/thirdparty/CMSIS/Lib/ \ +../src/ASF/thirdparty/CMSIS/Lib/GCC/ \ +../src/config/ + + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../src/ASF/common/services/clock/sam3x/sysclk.c \ +../src/ASF/common/services/serial/usart_serial.c \ +../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c \ +../src/ASF/common/utils/stdio/read.c \ +../src/ASF/common/utils/stdio/write.c \ +../src/ASF/sam/boards/sam3x_ek/init.c \ +../src/ASF/sam/boards/sam3x_ek/led.c \ +../src/ASF/sam/components/ethernet_phy/dm9161a/ethernet_phy.c \ +../src/ASF/sam/drivers/emac/emac.c \ +../src/ASF/sam/drivers/pio/pio.c \ +../src/ASF/sam/drivers/pio/pio_handler.c \ +../src/ASF/sam/drivers/pmc/pmc.c \ +../src/ASF/sam/drivers/pmc/sleep.c \ +../src/ASF/sam/drivers/rstc/rstc.c \ +../src/ASF/sam/drivers/uart/uart.c \ +../src/ASF/sam/drivers/usart/usart.c \ +../src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.c \ +../src/ASF/sam/utils/cmsis/sam3x/source/templates/gcc/startup_sam3x.c \ +../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.c \ +../src/ASF/sam/utils/syscalls/gcc/syscalls.c \ +../src/emac_example.c + + +PREPROCESSING_SRCS += + + +ASM_SRCS += + + +OBJS += \ +src/ASF/common/services/clock/sam3x/sysclk.o \ +src/ASF/common/services/serial/usart_serial.o \ +src/ASF/common/utils/interrupt/interrupt_sam_nvic.o \ +src/ASF/common/utils/stdio/read.o \ +src/ASF/common/utils/stdio/write.o \ +src/ASF/sam/boards/sam3x_ek/init.o \ +src/ASF/sam/boards/sam3x_ek/led.o \ +src/ASF/sam/components/ethernet_phy/dm9161a/ethernet_phy.o \ +src/ASF/sam/drivers/emac/emac.o \ +src/ASF/sam/drivers/pio/pio.o \ +src/ASF/sam/drivers/pio/pio_handler.o \ +src/ASF/sam/drivers/pmc/pmc.o \ +src/ASF/sam/drivers/pmc/sleep.o \ +src/ASF/sam/drivers/rstc/rstc.o \ +src/ASF/sam/drivers/uart/uart.o \ +src/ASF/sam/drivers/usart/usart.o \ +src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.o \ +src/ASF/sam/utils/cmsis/sam3x/source/templates/gcc/startup_sam3x.o \ +src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.o \ +src/ASF/sam/utils/syscalls/gcc/syscalls.o \ +src/emac_example.o + +OBJS_AS_ARGS += \ +src/ASF/common/services/clock/sam3x/sysclk.o \ +src/ASF/common/services/serial/usart_serial.o \ +src/ASF/common/utils/interrupt/interrupt_sam_nvic.o \ +src/ASF/common/utils/stdio/read.o \ +src/ASF/common/utils/stdio/write.o \ +src/ASF/sam/boards/sam3x_ek/init.o \ +src/ASF/sam/boards/sam3x_ek/led.o \ +src/ASF/sam/components/ethernet_phy/dm9161a/ethernet_phy.o \ +src/ASF/sam/drivers/emac/emac.o \ +src/ASF/sam/drivers/pio/pio.o \ +src/ASF/sam/drivers/pio/pio_handler.o \ +src/ASF/sam/drivers/pmc/pmc.o \ +src/ASF/sam/drivers/pmc/sleep.o \ +src/ASF/sam/drivers/rstc/rstc.o \ +src/ASF/sam/drivers/uart/uart.o \ +src/ASF/sam/drivers/usart/usart.o \ +src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.o \ +src/ASF/sam/utils/cmsis/sam3x/source/templates/gcc/startup_sam3x.o \ +src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.o \ +src/ASF/sam/utils/syscalls/gcc/syscalls.o \ +src/emac_example.o + +C_DEPS += \ +src/ASF/common/services/clock/sam3x/sysclk.d \ +src/ASF/common/services/serial/usart_serial.d \ +src/ASF/common/utils/interrupt/interrupt_sam_nvic.d \ +src/ASF/common/utils/stdio/read.d \ +src/ASF/common/utils/stdio/write.d \ +src/ASF/sam/boards/sam3x_ek/init.d \ +src/ASF/sam/boards/sam3x_ek/led.d \ +src/ASF/sam/components/ethernet_phy/dm9161a/ethernet_phy.d \ +src/ASF/sam/drivers/emac/emac.d \ +src/ASF/sam/drivers/pio/pio.d \ +src/ASF/sam/drivers/pio/pio_handler.d \ +src/ASF/sam/drivers/pmc/pmc.d \ +src/ASF/sam/drivers/pmc/sleep.d \ +src/ASF/sam/drivers/rstc/rstc.d \ +src/ASF/sam/drivers/uart/uart.d \ +src/ASF/sam/drivers/usart/usart.d \ +src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.d \ +src/ASF/sam/utils/cmsis/sam3x/source/templates/gcc/startup_sam3x.d \ +src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.d \ +src/ASF/sam/utils/syscalls/gcc/syscalls.d \ +src/emac_example.d + +C_DEPS_AS_ARGS += \ +src/ASF/common/services/clock/sam3x/sysclk.d \ +src/ASF/common/services/serial/usart_serial.d \ +src/ASF/common/utils/interrupt/interrupt_sam_nvic.d \ +src/ASF/common/utils/stdio/read.d \ +src/ASF/common/utils/stdio/write.d \ +src/ASF/sam/boards/sam3x_ek/init.d \ +src/ASF/sam/boards/sam3x_ek/led.d \ +src/ASF/sam/components/ethernet_phy/dm9161a/ethernet_phy.d \ +src/ASF/sam/drivers/emac/emac.d \ +src/ASF/sam/drivers/pio/pio.d \ +src/ASF/sam/drivers/pio/pio_handler.d \ +src/ASF/sam/drivers/pmc/pmc.d \ +src/ASF/sam/drivers/pmc/sleep.d \ +src/ASF/sam/drivers/rstc/rstc.d \ +src/ASF/sam/drivers/uart/uart.d \ +src/ASF/sam/drivers/usart/usart.d \ +src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.d \ +src/ASF/sam/utils/cmsis/sam3x/source/templates/gcc/startup_sam3x.d \ +src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.d \ +src/ASF/sam/utils/syscalls/gcc/syscalls.d \ +src/emac_example.d + +OUTPUT_FILE_PATH +=EMAC_EMAC_EXAMPLE_TAIJI_DUE.elf + +OUTPUT_FILE_PATH_AS_ARGS +=EMAC_EMAC_EXAMPLE_TAIJI_DUE.elf + +ADDITIONAL_DEPENDENCIES:= + +OUTPUT_FILE_DEP:= ./makedep.mk + +LIB_DEP+= + +LINKER_SCRIPT_DEP+= \ +../src/ASF/sam/utils/linker_scripts/sam3x/sam3x8/gcc/flash.ld + + +# AVR32/GNU C Compiler + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +src/ASF/common/services/clock/sam3x/%.o: ../src/ASF/common/services/clock/sam3x/%.c + @echo Building file: $< + @echo Invoking: ARM/GNU C Compiler : 4.9.3 + $(QUOTE)C:\Program Files (x86)\Atmel7\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAM3X8E__ -DDEBUG -DBOARD=SAM3X_EK -D__SAM3X8H__ -Dscanf=iscanf -DARM_MATH_CM3=true -Dprintf=iprintf -I"../sam/drivers/emac/emac_example/sam3x8h_sam3x_ek" -I"../src/ASF/sam/components/ethernet_phy/dm9161a" -I"../src/ASF/common/utils" -I"../src/ASF/common/services/serial/sam_uart" -I"../src/ASF/sam/drivers/pmc" -I"../src/ASF/common/services/gpio" -I"../src/ASF/sam/boards" -I"../src/ASF/sam/drivers/pio" -I"../src/ASF/common/boards" -I"../src/ASF/sam/utils/cmsis/sam3x/source/templates" -I"../src/ASF/sam/drivers/emac" -I"../src/ASF/sam/utils/header_files" -I"../src/ASF/sam/drivers/rstc" -I"../src/ASF/common/services/ioport" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/sam/utils/cmsis/sam3x/include" -I"../src/config" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src" -I"../src/ASF/common/services/clock" -I"../src/ASF/common/utils/stdio/stdio_serial" -I"../src/ASF/sam/utils" -I"../src/ASF/sam/utils/preprocessor" -I"../src/ASF/common/services/serial" -I"../src/ASF/sam/drivers/usart" -I"../src/ASF/sam/drivers/uart" -I"../src/ASF/sam/boards/sam3x_ek" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m3 -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + + +src/ASF/common/services/serial/%.o: ../src/ASF/common/services/serial/%.c + @echo Building file: $< + @echo Invoking: ARM/GNU C Compiler : 4.9.3 + $(QUOTE)C:\Program Files (x86)\Atmel7\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAM3X8E__ -DDEBUG -DBOARD=SAM3X_EK -D__SAM3X8H__ -Dscanf=iscanf -DARM_MATH_CM3=true -Dprintf=iprintf -I"../sam/drivers/emac/emac_example/sam3x8h_sam3x_ek" -I"../src/ASF/sam/components/ethernet_phy/dm9161a" -I"../src/ASF/common/utils" -I"../src/ASF/common/services/serial/sam_uart" -I"../src/ASF/sam/drivers/pmc" -I"../src/ASF/common/services/gpio" -I"../src/ASF/sam/boards" -I"../src/ASF/sam/drivers/pio" -I"../src/ASF/common/boards" -I"../src/ASF/sam/utils/cmsis/sam3x/source/templates" -I"../src/ASF/sam/drivers/emac" -I"../src/ASF/sam/utils/header_files" -I"../src/ASF/sam/drivers/rstc" -I"../src/ASF/common/services/ioport" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/sam/utils/cmsis/sam3x/include" -I"../src/config" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src" -I"../src/ASF/common/services/clock" -I"../src/ASF/common/utils/stdio/stdio_serial" -I"../src/ASF/sam/utils" -I"../src/ASF/sam/utils/preprocessor" -I"../src/ASF/common/services/serial" -I"../src/ASF/sam/drivers/usart" -I"../src/ASF/sam/drivers/uart" -I"../src/ASF/sam/boards/sam3x_ek" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m3 -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + + +src/ASF/common/utils/interrupt/%.o: ../src/ASF/common/utils/interrupt/%.c + @echo Building file: $< + @echo Invoking: ARM/GNU C Compiler : 4.9.3 + $(QUOTE)C:\Program Files (x86)\Atmel7\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAM3X8E__ -DDEBUG -DBOARD=SAM3X_EK -D__SAM3X8H__ -Dscanf=iscanf -DARM_MATH_CM3=true -Dprintf=iprintf -I"../sam/drivers/emac/emac_example/sam3x8h_sam3x_ek" -I"../src/ASF/sam/components/ethernet_phy/dm9161a" -I"../src/ASF/common/utils" -I"../src/ASF/common/services/serial/sam_uart" -I"../src/ASF/sam/drivers/pmc" -I"../src/ASF/common/services/gpio" -I"../src/ASF/sam/boards" -I"../src/ASF/sam/drivers/pio" -I"../src/ASF/common/boards" -I"../src/ASF/sam/utils/cmsis/sam3x/source/templates" -I"../src/ASF/sam/drivers/emac" -I"../src/ASF/sam/utils/header_files" -I"../src/ASF/sam/drivers/rstc" -I"../src/ASF/common/services/ioport" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/sam/utils/cmsis/sam3x/include" -I"../src/config" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src" -I"../src/ASF/common/services/clock" -I"../src/ASF/common/utils/stdio/stdio_serial" -I"../src/ASF/sam/utils" -I"../src/ASF/sam/utils/preprocessor" -I"../src/ASF/common/services/serial" -I"../src/ASF/sam/drivers/usart" -I"../src/ASF/sam/drivers/uart" -I"../src/ASF/sam/boards/sam3x_ek" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m3 -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + + +src/ASF/common/utils/stdio/%.o: ../src/ASF/common/utils/stdio/%.c + @echo Building file: $< + @echo Invoking: ARM/GNU C Compiler : 4.9.3 + $(QUOTE)C:\Program Files (x86)\Atmel7\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAM3X8E__ -DDEBUG -DBOARD=SAM3X_EK -D__SAM3X8H__ -Dscanf=iscanf -DARM_MATH_CM3=true -Dprintf=iprintf -I"../sam/drivers/emac/emac_example/sam3x8h_sam3x_ek" -I"../src/ASF/sam/components/ethernet_phy/dm9161a" -I"../src/ASF/common/utils" -I"../src/ASF/common/services/serial/sam_uart" -I"../src/ASF/sam/drivers/pmc" -I"../src/ASF/common/services/gpio" -I"../src/ASF/sam/boards" -I"../src/ASF/sam/drivers/pio" -I"../src/ASF/common/boards" -I"../src/ASF/sam/utils/cmsis/sam3x/source/templates" -I"../src/ASF/sam/drivers/emac" -I"../src/ASF/sam/utils/header_files" -I"../src/ASF/sam/drivers/rstc" -I"../src/ASF/common/services/ioport" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/sam/utils/cmsis/sam3x/include" -I"../src/config" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src" -I"../src/ASF/common/services/clock" -I"../src/ASF/common/utils/stdio/stdio_serial" -I"../src/ASF/sam/utils" -I"../src/ASF/sam/utils/preprocessor" -I"../src/ASF/common/services/serial" -I"../src/ASF/sam/drivers/usart" -I"../src/ASF/sam/drivers/uart" -I"../src/ASF/sam/boards/sam3x_ek" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m3 -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + + +src/ASF/sam/boards/sam3x_ek/%.o: ../src/ASF/sam/boards/sam3x_ek/%.c + @echo Building file: $< + @echo Invoking: ARM/GNU C Compiler : 4.9.3 + $(QUOTE)C:\Program Files (x86)\Atmel7\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAM3X8E__ -DDEBUG -DBOARD=SAM3X_EK -D__SAM3X8H__ -Dscanf=iscanf -DARM_MATH_CM3=true -Dprintf=iprintf -I"../sam/drivers/emac/emac_example/sam3x8h_sam3x_ek" -I"../src/ASF/sam/components/ethernet_phy/dm9161a" -I"../src/ASF/common/utils" -I"../src/ASF/common/services/serial/sam_uart" -I"../src/ASF/sam/drivers/pmc" -I"../src/ASF/common/services/gpio" -I"../src/ASF/sam/boards" -I"../src/ASF/sam/drivers/pio" -I"../src/ASF/common/boards" -I"../src/ASF/sam/utils/cmsis/sam3x/source/templates" -I"../src/ASF/sam/drivers/emac" -I"../src/ASF/sam/utils/header_files" -I"../src/ASF/sam/drivers/rstc" -I"../src/ASF/common/services/ioport" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/sam/utils/cmsis/sam3x/include" -I"../src/config" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src" -I"../src/ASF/common/services/clock" -I"../src/ASF/common/utils/stdio/stdio_serial" -I"../src/ASF/sam/utils" -I"../src/ASF/sam/utils/preprocessor" -I"../src/ASF/common/services/serial" -I"../src/ASF/sam/drivers/usart" -I"../src/ASF/sam/drivers/uart" -I"../src/ASF/sam/boards/sam3x_ek" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m3 -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + + +src/ASF/sam/components/ethernet_phy/dm9161a/%.o: ../src/ASF/sam/components/ethernet_phy/dm9161a/%.c + @echo Building file: $< + @echo Invoking: ARM/GNU C Compiler : 4.9.3 + $(QUOTE)C:\Program Files (x86)\Atmel7\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAM3X8E__ -DDEBUG -DBOARD=SAM3X_EK -D__SAM3X8H__ -Dscanf=iscanf -DARM_MATH_CM3=true -Dprintf=iprintf -I"../sam/drivers/emac/emac_example/sam3x8h_sam3x_ek" -I"../src/ASF/sam/components/ethernet_phy/dm9161a" -I"../src/ASF/common/utils" -I"../src/ASF/common/services/serial/sam_uart" -I"../src/ASF/sam/drivers/pmc" -I"../src/ASF/common/services/gpio" -I"../src/ASF/sam/boards" -I"../src/ASF/sam/drivers/pio" -I"../src/ASF/common/boards" -I"../src/ASF/sam/utils/cmsis/sam3x/source/templates" -I"../src/ASF/sam/drivers/emac" -I"../src/ASF/sam/utils/header_files" -I"../src/ASF/sam/drivers/rstc" -I"../src/ASF/common/services/ioport" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/sam/utils/cmsis/sam3x/include" -I"../src/config" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src" -I"../src/ASF/common/services/clock" -I"../src/ASF/common/utils/stdio/stdio_serial" -I"../src/ASF/sam/utils" -I"../src/ASF/sam/utils/preprocessor" -I"../src/ASF/common/services/serial" -I"../src/ASF/sam/drivers/usart" -I"../src/ASF/sam/drivers/uart" -I"../src/ASF/sam/boards/sam3x_ek" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m3 -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare 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-I"../src/ASF/sam/drivers/pio" -I"../src/ASF/common/boards" -I"../src/ASF/sam/utils/cmsis/sam3x/source/templates" -I"../src/ASF/sam/drivers/emac" -I"../src/ASF/sam/utils/header_files" -I"../src/ASF/sam/drivers/rstc" -I"../src/ASF/common/services/ioport" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/sam/utils/cmsis/sam3x/include" -I"../src/config" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src" -I"../src/ASF/common/services/clock" -I"../src/ASF/common/utils/stdio/stdio_serial" -I"../src/ASF/sam/utils" -I"../src/ASF/sam/utils/preprocessor" -I"../src/ASF/common/services/serial" -I"../src/ASF/sam/drivers/usart" -I"../src/ASF/sam/drivers/uart" -I"../src/ASF/sam/boards/sam3x_ek" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m3 -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 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-I"../src/ASF/sam/components/ethernet_phy/dm9161a" -I"../src/ASF/common/utils" -I"../src/ASF/common/services/serial/sam_uart" -I"../src/ASF/sam/drivers/pmc" -I"../src/ASF/common/services/gpio" -I"../src/ASF/sam/boards" -I"../src/ASF/sam/drivers/pio" -I"../src/ASF/common/boards" -I"../src/ASF/sam/utils/cmsis/sam3x/source/templates" -I"../src/ASF/sam/drivers/emac" -I"../src/ASF/sam/utils/header_files" -I"../src/ASF/sam/drivers/rstc" -I"../src/ASF/common/services/ioport" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/sam/utils/cmsis/sam3x/include" -I"../src/config" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src" -I"../src/ASF/common/services/clock" -I"../src/ASF/common/utils/stdio/stdio_serial" -I"../src/ASF/sam/utils" -I"../src/ASF/sam/utils/preprocessor" -I"../src/ASF/common/services/serial" -I"../src/ASF/sam/drivers/usart" -I"../src/ASF/sam/drivers/uart" -I"../src/ASF/sam/boards/sam3x_ek" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m3 -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + + +src/ASF/sam/drivers/pmc/%.o: ../src/ASF/sam/drivers/pmc/%.c + @echo Building file: $< + @echo Invoking: ARM/GNU C Compiler : 4.9.3 + $(QUOTE)C:\Program Files (x86)\Atmel7\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAM3X8E__ -DDEBUG -DBOARD=SAM3X_EK -D__SAM3X8H__ -Dscanf=iscanf -DARM_MATH_CM3=true -Dprintf=iprintf -I"../sam/drivers/emac/emac_example/sam3x8h_sam3x_ek" -I"../src/ASF/sam/components/ethernet_phy/dm9161a" -I"../src/ASF/common/utils" -I"../src/ASF/common/services/serial/sam_uart" -I"../src/ASF/sam/drivers/pmc" -I"../src/ASF/common/services/gpio" -I"../src/ASF/sam/boards" -I"../src/ASF/sam/drivers/pio" -I"../src/ASF/common/boards" -I"../src/ASF/sam/utils/cmsis/sam3x/source/templates" -I"../src/ASF/sam/drivers/emac" -I"../src/ASF/sam/utils/header_files" -I"../src/ASF/sam/drivers/rstc" -I"../src/ASF/common/services/ioport" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/sam/utils/cmsis/sam3x/include" -I"../src/config" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src" -I"../src/ASF/common/services/clock" -I"../src/ASF/common/utils/stdio/stdio_serial" -I"../src/ASF/sam/utils" -I"../src/ASF/sam/utils/preprocessor" -I"../src/ASF/common/services/serial" -I"../src/ASF/sam/drivers/usart" -I"../src/ASF/sam/drivers/uart" -I"../src/ASF/sam/boards/sam3x_ek" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m3 -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + + +src/ASF/sam/drivers/rstc/%.o: ../src/ASF/sam/drivers/rstc/%.c + @echo Building file: $< + @echo Invoking: ARM/GNU C Compiler : 4.9.3 + $(QUOTE)C:\Program Files (x86)\Atmel7\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAM3X8E__ -DDEBUG -DBOARD=SAM3X_EK -D__SAM3X8H__ -Dscanf=iscanf -DARM_MATH_CM3=true -Dprintf=iprintf -I"../sam/drivers/emac/emac_example/sam3x8h_sam3x_ek" -I"../src/ASF/sam/components/ethernet_phy/dm9161a" -I"../src/ASF/common/utils" -I"../src/ASF/common/services/serial/sam_uart" -I"../src/ASF/sam/drivers/pmc" -I"../src/ASF/common/services/gpio" -I"../src/ASF/sam/boards" -I"../src/ASF/sam/drivers/pio" -I"../src/ASF/common/boards" -I"../src/ASF/sam/utils/cmsis/sam3x/source/templates" -I"../src/ASF/sam/drivers/emac" -I"../src/ASF/sam/utils/header_files" -I"../src/ASF/sam/drivers/rstc" -I"../src/ASF/common/services/ioport" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/sam/utils/cmsis/sam3x/include" -I"../src/config" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src" -I"../src/ASF/common/services/clock" -I"../src/ASF/common/utils/stdio/stdio_serial" -I"../src/ASF/sam/utils" -I"../src/ASF/sam/utils/preprocessor" -I"../src/ASF/common/services/serial" -I"../src/ASF/sam/drivers/usart" -I"../src/ASF/sam/drivers/uart" -I"../src/ASF/sam/boards/sam3x_ek" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m3 -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + + +src/ASF/sam/drivers/uart/%.o: ../src/ASF/sam/drivers/uart/%.c + @echo Building file: $< + @echo Invoking: ARM/GNU C Compiler : 4.9.3 + $(QUOTE)C:\Program Files (x86)\Atmel7\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAM3X8E__ -DDEBUG -DBOARD=SAM3X_EK -D__SAM3X8H__ -Dscanf=iscanf -DARM_MATH_CM3=true -Dprintf=iprintf -I"../sam/drivers/emac/emac_example/sam3x8h_sam3x_ek" -I"../src/ASF/sam/components/ethernet_phy/dm9161a" -I"../src/ASF/common/utils" -I"../src/ASF/common/services/serial/sam_uart" -I"../src/ASF/sam/drivers/pmc" -I"../src/ASF/common/services/gpio" -I"../src/ASF/sam/boards" -I"../src/ASF/sam/drivers/pio" -I"../src/ASF/common/boards" -I"../src/ASF/sam/utils/cmsis/sam3x/source/templates" -I"../src/ASF/sam/drivers/emac" -I"../src/ASF/sam/utils/header_files" -I"../src/ASF/sam/drivers/rstc" -I"../src/ASF/common/services/ioport" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/sam/utils/cmsis/sam3x/include" -I"../src/config" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src" -I"../src/ASF/common/services/clock" -I"../src/ASF/common/utils/stdio/stdio_serial" -I"../src/ASF/sam/utils" -I"../src/ASF/sam/utils/preprocessor" -I"../src/ASF/common/services/serial" -I"../src/ASF/sam/drivers/usart" -I"../src/ASF/sam/drivers/uart" -I"../src/ASF/sam/boards/sam3x_ek" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m3 -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + + +src/ASF/sam/drivers/usart/%.o: ../src/ASF/sam/drivers/usart/%.c + @echo Building file: $< + @echo Invoking: ARM/GNU C Compiler : 4.9.3 + $(QUOTE)C:\Program Files (x86)\Atmel7\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAM3X8E__ -DDEBUG -DBOARD=SAM3X_EK -D__SAM3X8H__ -Dscanf=iscanf -DARM_MATH_CM3=true -Dprintf=iprintf -I"../sam/drivers/emac/emac_example/sam3x8h_sam3x_ek" -I"../src/ASF/sam/components/ethernet_phy/dm9161a" -I"../src/ASF/common/utils" -I"../src/ASF/common/services/serial/sam_uart" -I"../src/ASF/sam/drivers/pmc" -I"../src/ASF/common/services/gpio" -I"../src/ASF/sam/boards" -I"../src/ASF/sam/drivers/pio" -I"../src/ASF/common/boards" -I"../src/ASF/sam/utils/cmsis/sam3x/source/templates" -I"../src/ASF/sam/drivers/emac" -I"../src/ASF/sam/utils/header_files" -I"../src/ASF/sam/drivers/rstc" -I"../src/ASF/common/services/ioport" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/sam/utils/cmsis/sam3x/include" -I"../src/config" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src" -I"../src/ASF/common/services/clock" -I"../src/ASF/common/utils/stdio/stdio_serial" -I"../src/ASF/sam/utils" -I"../src/ASF/sam/utils/preprocessor" -I"../src/ASF/common/services/serial" -I"../src/ASF/sam/drivers/usart" -I"../src/ASF/sam/drivers/uart" -I"../src/ASF/sam/boards/sam3x_ek" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m3 -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + + +src/ASF/sam/utils/cmsis/sam3x/source/templates/%.o: ../src/ASF/sam/utils/cmsis/sam3x/source/templates/%.c + @echo Building file: $< + @echo Invoking: ARM/GNU C Compiler : 4.9.3 + $(QUOTE)C:\Program Files (x86)\Atmel7\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAM3X8E__ -DDEBUG -DBOARD=SAM3X_EK -D__SAM3X8H__ -Dscanf=iscanf -DARM_MATH_CM3=true -Dprintf=iprintf -I"../sam/drivers/emac/emac_example/sam3x8h_sam3x_ek" -I"../src/ASF/sam/components/ethernet_phy/dm9161a" -I"../src/ASF/common/utils" -I"../src/ASF/common/services/serial/sam_uart" -I"../src/ASF/sam/drivers/pmc" -I"../src/ASF/common/services/gpio" -I"../src/ASF/sam/boards" -I"../src/ASF/sam/drivers/pio" -I"../src/ASF/common/boards" -I"../src/ASF/sam/utils/cmsis/sam3x/source/templates" -I"../src/ASF/sam/drivers/emac" -I"../src/ASF/sam/utils/header_files" -I"../src/ASF/sam/drivers/rstc" -I"../src/ASF/common/services/ioport" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/sam/utils/cmsis/sam3x/include" -I"../src/config" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src" -I"../src/ASF/common/services/clock" -I"../src/ASF/common/utils/stdio/stdio_serial" -I"../src/ASF/sam/utils" -I"../src/ASF/sam/utils/preprocessor" -I"../src/ASF/common/services/serial" -I"../src/ASF/sam/drivers/usart" -I"../src/ASF/sam/drivers/uart" -I"../src/ASF/sam/boards/sam3x_ek" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m3 -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + + +src/ASF/sam/utils/cmsis/sam3x/source/templates/gcc/%.o: ../src/ASF/sam/utils/cmsis/sam3x/source/templates/gcc/%.c + @echo Building file: $< + @echo Invoking: ARM/GNU C Compiler : 4.9.3 + $(QUOTE)C:\Program Files (x86)\Atmel7\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAM3X8E__ -DDEBUG -DBOARD=SAM3X_EK -D__SAM3X8H__ -Dscanf=iscanf -DARM_MATH_CM3=true -Dprintf=iprintf -I"../sam/drivers/emac/emac_example/sam3x8h_sam3x_ek" -I"../src/ASF/sam/components/ethernet_phy/dm9161a" -I"../src/ASF/common/utils" -I"../src/ASF/common/services/serial/sam_uart" -I"../src/ASF/sam/drivers/pmc" -I"../src/ASF/common/services/gpio" -I"../src/ASF/sam/boards" -I"../src/ASF/sam/drivers/pio" -I"../src/ASF/common/boards" -I"../src/ASF/sam/utils/cmsis/sam3x/source/templates" -I"../src/ASF/sam/drivers/emac" -I"../src/ASF/sam/utils/header_files" -I"../src/ASF/sam/drivers/rstc" -I"../src/ASF/common/services/ioport" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/sam/utils/cmsis/sam3x/include" -I"../src/config" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src" -I"../src/ASF/common/services/clock" -I"../src/ASF/common/utils/stdio/stdio_serial" -I"../src/ASF/sam/utils" -I"../src/ASF/sam/utils/preprocessor" -I"../src/ASF/common/services/serial" -I"../src/ASF/sam/drivers/usart" -I"../src/ASF/sam/drivers/uart" -I"../src/ASF/sam/boards/sam3x_ek" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m3 -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + + +src/ASF/sam/utils/syscalls/gcc/%.o: ../src/ASF/sam/utils/syscalls/gcc/%.c + @echo Building file: $< + @echo Invoking: ARM/GNU C Compiler : 4.9.3 + $(QUOTE)C:\Program Files (x86)\Atmel7\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAM3X8E__ -DDEBUG -DBOARD=SAM3X_EK -D__SAM3X8H__ -Dscanf=iscanf -DARM_MATH_CM3=true -Dprintf=iprintf -I"../sam/drivers/emac/emac_example/sam3x8h_sam3x_ek" -I"../src/ASF/sam/components/ethernet_phy/dm9161a" -I"../src/ASF/common/utils" -I"../src/ASF/common/services/serial/sam_uart" -I"../src/ASF/sam/drivers/pmc" -I"../src/ASF/common/services/gpio" -I"../src/ASF/sam/boards" -I"../src/ASF/sam/drivers/pio" -I"../src/ASF/common/boards" -I"../src/ASF/sam/utils/cmsis/sam3x/source/templates" -I"../src/ASF/sam/drivers/emac" -I"../src/ASF/sam/utils/header_files" -I"../src/ASF/sam/drivers/rstc" -I"../src/ASF/common/services/ioport" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/sam/utils/cmsis/sam3x/include" -I"../src/config" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src" -I"../src/ASF/common/services/clock" -I"../src/ASF/common/utils/stdio/stdio_serial" -I"../src/ASF/sam/utils" -I"../src/ASF/sam/utils/preprocessor" -I"../src/ASF/common/services/serial" -I"../src/ASF/sam/drivers/usart" -I"../src/ASF/sam/drivers/uart" -I"../src/ASF/sam/boards/sam3x_ek" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m3 -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + + +src/%.o: ../src/%.c + @echo Building file: $< + @echo Invoking: ARM/GNU C Compiler : 4.9.3 + $(QUOTE)C:\Program Files (x86)\Atmel7\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAM3X8E__ -DDEBUG -DBOARD=SAM3X_EK -D__SAM3X8H__ -Dscanf=iscanf -DARM_MATH_CM3=true -Dprintf=iprintf -I"../sam/drivers/emac/emac_example/sam3x8h_sam3x_ek" -I"../src/ASF/sam/components/ethernet_phy/dm9161a" -I"../src/ASF/common/utils" -I"../src/ASF/common/services/serial/sam_uart" -I"../src/ASF/sam/drivers/pmc" -I"../src/ASF/common/services/gpio" -I"../src/ASF/sam/boards" -I"../src/ASF/sam/drivers/pio" -I"../src/ASF/common/boards" -I"../src/ASF/sam/utils/cmsis/sam3x/source/templates" -I"../src/ASF/sam/drivers/emac" -I"../src/ASF/sam/utils/header_files" -I"../src/ASF/sam/drivers/rstc" -I"../src/ASF/common/services/ioport" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/sam/utils/cmsis/sam3x/include" -I"../src/config" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src" -I"../src/ASF/common/services/clock" -I"../src/ASF/common/utils/stdio/stdio_serial" -I"../src/ASF/sam/utils" -I"../src/ASF/sam/utils/preprocessor" -I"../src/ASF/common/services/serial" -I"../src/ASF/sam/drivers/usart" -I"../src/ASF/sam/drivers/uart" -I"../src/ASF/sam/boards/sam3x_ek" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m3 -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + + + + +# AVR32/GNU Preprocessing Assembler + + + +# AVR32/GNU Assembler + + + + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +endif + +# Add inputs and outputs from these tool invocations to the build variables + +# All Target +all: $(OUTPUT_FILE_PATH) $(ADDITIONAL_DEPENDENCIES) + +$(OUTPUT_FILE_PATH): $(OBJS) $(USER_OBJS) $(OUTPUT_FILE_DEP) $(LIB_DEP) $(LINKER_SCRIPT_DEP) + @echo Building target: $@ + @echo Invoking: ARM/GNU Linker : 4.9.3 + $(QUOTE)C:\Program Files (x86)\Atmel7\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -o$(OUTPUT_FILE_PATH_AS_ARGS) $(OBJS_AS_ARGS) $(USER_OBJS) $(LIBS) -mthumb -Wl,-Map="EMAC_EMAC_EXAMPLE_TAIJI_DUE.map" -Wl,--start-group -larm_cortexM3l_math -lm -Wl,--end-group -L"..\src\ASF\thirdparty\CMSIS\Lib\GCC" -Wl,--gc-sections -mcpu=cortex-m3 -Wl,--entry=Reset_Handler -Wl,--cref -mthumb -T../src/ASF/sam/utils/linker_scripts/sam3x/sam3x8/gcc/flash.ld + @echo Finished building target: $@ + "C:\Program Files (x86)\Atmel7\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -O binary "EMAC_EMAC_EXAMPLE_TAIJI_DUE.elf" "EMAC_EMAC_EXAMPLE_TAIJI_DUE.bin" + "C:\Program Files (x86)\Atmel7\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -O ihex -R .eeprom -R .fuse -R .lock -R .signature "EMAC_EMAC_EXAMPLE_TAIJI_DUE.elf" "EMAC_EMAC_EXAMPLE_TAIJI_DUE.hex" + "C:\Program Files (x86)\Atmel7\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -j .eeprom --set-section-flags=.eeprom=alloc,load --change-section-lma .eeprom=0 --no-change-warnings -O binary "EMAC_EMAC_EXAMPLE_TAIJI_DUE.elf" "EMAC_EMAC_EXAMPLE_TAIJI_DUE.eep" || exit 0 + "C:\Program Files (x86)\Atmel7\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objdump.exe" -h -S "EMAC_EMAC_EXAMPLE_TAIJI_DUE.elf" > "EMAC_EMAC_EXAMPLE_TAIJI_DUE.lss" + "C:\Program Files (x86)\Atmel7\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -O srec -R .eeprom -R .fuse -R .lock -R .signature "EMAC_EMAC_EXAMPLE_TAIJI_DUE.elf" "EMAC_EMAC_EXAMPLE_TAIJI_DUE.srec" + "C:\Program Files (x86)\Atmel7\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-size.exe" "EMAC_EMAC_EXAMPLE_TAIJI_DUE.elf" + + + + + + + +# Other Targets +clean: + -$(RM) $(OBJS_AS_ARGS) $(EXECUTABLES) + -$(RM) $(C_DEPS_AS_ARGS) + rm -rf "EMAC_EMAC_EXAMPLE_TAIJI_DUE.elf" "EMAC_EMAC_EXAMPLE_TAIJI_DUE.a" "EMAC_EMAC_EXAMPLE_TAIJI_DUE.hex" "EMAC_EMAC_EXAMPLE_TAIJI_DUE.bin" "EMAC_EMAC_EXAMPLE_TAIJI_DUE.lss" "EMAC_EMAC_EXAMPLE_TAIJI_DUE.eep" "EMAC_EMAC_EXAMPLE_TAIJI_DUE.map" "EMAC_EMAC_EXAMPLE_TAIJI_DUE.srec" + \ No newline at end of file diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/makedep.mk b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/makedep.mk new file mode 100644 index 0000000..fcae254 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/makedep.mk @@ -0,0 +1,46 @@ +################################################################################ +# Automatically-generated file. Do not edit or delete the file +################################################################################ + +src\ASF\common\services\clock\sam3x\sysclk.c + +src\ASF\common\services\serial\usart_serial.c + +src\ASF\common\utils\interrupt\interrupt_sam_nvic.c + +src\ASF\common\utils\stdio\read.c + +src\ASF\common\utils\stdio\write.c + +src\ASF\sam\boards\sam3x_ek\init.c + +src\ASF\sam\boards\sam3x_ek\led.c + +src\ASF\sam\components\ethernet_phy\dm9161a\ethernet_phy.c + +src\ASF\sam\drivers\emac\emac.c + +src\ASF\sam\drivers\pio\pio.c + +src\ASF\sam\drivers\pio\pio_handler.c + +src\ASF\sam\drivers\pmc\pmc.c + +src\ASF\sam\drivers\pmc\sleep.c + +src\ASF\sam\drivers\rstc\rstc.c + +src\ASF\sam\drivers\uart\uart.c + +src\ASF\sam\drivers\usart\usart.c + +src\ASF\sam\utils\cmsis\sam3x\source\templates\exceptions.c + +src\ASF\sam\utils\cmsis\sam3x\source\templates\gcc\startup_sam3x.c + +src\ASF\sam\utils\cmsis\sam3x\source\templates\system_sam3x.c + +src\ASF\sam\utils\syscalls\gcc\syscalls.c + +src\emac_example.c + diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/common/services/clock/sam3x/sysclk.d b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/common/services/clock/sam3x/sysclk.d new file mode 100644 index 0000000..8df81e3 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/common/services/clock/sam3x/sysclk.d @@ -0,0 +1,360 @@ +src/ASF/common/services/clock/sam3x/sysclk.d \ + src/ASF/common/services/clock/sam3x/sysclk.o: \ + ../src/ASF/common/services/clock/sam3x/sysclk.c \ + ../src/ASF/common/services/clock/sysclk.h \ + ../src/ASF/common/utils/parts.h ../src/config/conf_clock.h \ + ../src/ASF/common/services/clock/sam3x/sysclk.h \ + ../src/ASF/common/services/clock/osc.h \ + ../src/ASF/common/services/clock/sam3x/osc.h \ + ../src/ASF/common/boards/board.h ../src/ASF/sam/utils/compiler.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/preprocessor/tpaste.h \ + ../src/ASF/sam/utils/preprocessor/stringz.h \ + ../src/ASF/sam/utils/preprocessor/mrepeat.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/header_files/io.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cm3.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \ + ../src/ASF/common/utils/interrupt.h \ + ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \ + ../src/ASF/sam/boards/sam3x_ek/sam3x_ek.h \ + ../src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.h \ + ../src/ASF/sam/drivers/pmc/pmc.h ../src/ASF/common/services/clock/pll.h \ + ../src/ASF/common/services/clock/sam3x/pll.h + +../src/ASF/common/services/clock/sysclk.h: + +../src/ASF/common/utils/parts.h: + +../src/config/conf_clock.h: + +../src/ASF/common/services/clock/sam3x/sysclk.h: + +../src/ASF/common/services/clock/osc.h: + +../src/ASF/common/services/clock/sam3x/osc.h: + +../src/ASF/common/boards/board.h: + +../src/ASF/sam/utils/compiler.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/preprocessor/tpaste.h: + +../src/ASF/sam/utils/preprocessor/stringz.h: + +../src/ASF/sam/utils/preprocessor/mrepeat.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/header_files/io.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cm3.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h: + +../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h: + +../src/ASF/common/utils/interrupt.h: + +../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h: + +../src/ASF/sam/boards/sam3x_ek/sam3x_ek.h: + +../src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.h: + +../src/ASF/sam/drivers/pmc/pmc.h: + +../src/ASF/common/services/clock/pll.h: + +../src/ASF/common/services/clock/sam3x/pll.h: diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/common/services/clock/sam3x/sysclk.o b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/common/services/clock/sam3x/sysclk.o new file mode 100644 index 0000000..900ca70 Binary files /dev/null and b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/common/services/clock/sam3x/sysclk.o differ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/common/services/serial/usart_serial.d b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/common/services/serial/usart_serial.d new file mode 100644 index 0000000..072fc04 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/common/services/serial/usart_serial.d @@ -0,0 +1,377 @@ +src/ASF/common/services/serial/usart_serial.d \ + src/ASF/common/services/serial/usart_serial.o: \ + ../src/ASF/common/services/serial/usart_serial.c \ + ../src/ASF/common/services/serial/serial.h \ + ../src/ASF/common/utils/parts.h ../src/ASF/sam/utils/status_codes.h \ + ../src/ASF/common/services/serial/sam_uart/uart_serial.h \ + ../src/ASF/sam/utils/compiler.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/preprocessor/tpaste.h \ + ../src/ASF/sam/utils/preprocessor/stringz.h \ + ../src/ASF/sam/utils/preprocessor/mrepeat.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/header_files/io.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cm3.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \ + ../src/ASF/common/utils/interrupt.h \ + ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \ + ../src/ASF/common/services/clock/sysclk.h ../src/config/conf_clock.h \ + ../src/ASF/common/services/clock/sam3x/sysclk.h \ + ../src/ASF/common/services/clock/osc.h \ + ../src/ASF/common/services/clock/sam3x/osc.h \ + ../src/ASF/common/boards/board.h \ + ../src/ASF/sam/boards/sam3x_ek/sam3x_ek.h \ + ../src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.h \ + ../src/ASF/sam/drivers/pmc/pmc.h ../src/ASF/common/services/clock/pll.h \ + ../src/ASF/common/services/clock/sam3x/pll.h \ + ../src/ASF/sam/drivers/uart/uart.h ../src/ASF/sam/drivers/usart/usart.h \ + ../src/config/conf_uart_serial.h + +../src/ASF/common/services/serial/serial.h: + +../src/ASF/common/utils/parts.h: + +../src/ASF/sam/utils/status_codes.h: + +../src/ASF/common/services/serial/sam_uart/uart_serial.h: + +../src/ASF/sam/utils/compiler.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/preprocessor/tpaste.h: + +../src/ASF/sam/utils/preprocessor/stringz.h: + +../src/ASF/sam/utils/preprocessor/mrepeat.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/header_files/io.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cm3.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h: + +../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h: + +../src/ASF/common/utils/interrupt.h: + +../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h: + +../src/ASF/common/services/clock/sysclk.h: + +../src/config/conf_clock.h: + +../src/ASF/common/services/clock/sam3x/sysclk.h: + +../src/ASF/common/services/clock/osc.h: + +../src/ASF/common/services/clock/sam3x/osc.h: + +../src/ASF/common/boards/board.h: + +../src/ASF/sam/boards/sam3x_ek/sam3x_ek.h: + +../src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.h: + +../src/ASF/sam/drivers/pmc/pmc.h: + +../src/ASF/common/services/clock/pll.h: + +../src/ASF/common/services/clock/sam3x/pll.h: + +../src/ASF/sam/drivers/uart/uart.h: + +../src/ASF/sam/drivers/usart/usart.h: + +../src/config/conf_uart_serial.h: diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/common/services/serial/usart_serial.o b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/common/services/serial/usart_serial.o new file mode 100644 index 0000000..e048b64 Binary files /dev/null and b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/common/services/serial/usart_serial.o differ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/common/utils/interrupt/interrupt_sam_nvic.d b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/common/utils/interrupt/interrupt_sam_nvic.d new file mode 100644 index 0000000..c38a841 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/common/utils/interrupt/interrupt_sam_nvic.d @@ -0,0 +1,333 @@ +src/ASF/common/utils/interrupt/interrupt_sam_nvic.d \ + src/ASF/common/utils/interrupt/interrupt_sam_nvic.o: \ + ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c \ + ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \ + ../src/ASF/sam/utils/compiler.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h \ + ../src/ASF/common/utils/parts.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/preprocessor/tpaste.h \ + ../src/ASF/sam/utils/preprocessor/stringz.h \ + ../src/ASF/sam/utils/preprocessor/mrepeat.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/header_files/io.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cm3.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \ + ../src/ASF/common/utils/interrupt.h \ + ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h + +../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h: + +../src/ASF/sam/utils/compiler.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h: + +../src/ASF/common/utils/parts.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/preprocessor/tpaste.h: + +../src/ASF/sam/utils/preprocessor/stringz.h: + +../src/ASF/sam/utils/preprocessor/mrepeat.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/header_files/io.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cm3.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h: + +../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h: + +../src/ASF/common/utils/interrupt.h: + +../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h: diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/common/utils/interrupt/interrupt_sam_nvic.o b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/common/utils/interrupt/interrupt_sam_nvic.o new file mode 100644 index 0000000..2dba391 Binary files /dev/null and b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/common/utils/interrupt/interrupt_sam_nvic.o differ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/common/utils/stdio/read.d b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/common/utils/stdio/read.d new file mode 100644 index 0000000..6a167bf --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/common/utils/stdio/read.d @@ -0,0 +1,328 @@ +src/ASF/common/utils/stdio/read.d src/ASF/common/utils/stdio/read.o: \ + ../src/ASF/common/utils/stdio/read.c ../src/ASF/sam/utils/compiler.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h \ + ../src/ASF/common/utils/parts.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/preprocessor/tpaste.h \ + ../src/ASF/sam/utils/preprocessor/stringz.h \ + ../src/ASF/sam/utils/preprocessor/mrepeat.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/header_files/io.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cm3.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \ + ../src/ASF/common/utils/interrupt.h \ + ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h + +../src/ASF/sam/utils/compiler.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h: + +../src/ASF/common/utils/parts.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/preprocessor/tpaste.h: + +../src/ASF/sam/utils/preprocessor/stringz.h: + +../src/ASF/sam/utils/preprocessor/mrepeat.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/header_files/io.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cm3.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h: + +../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h: + +../src/ASF/common/utils/interrupt.h: + +../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h: diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/common/utils/stdio/read.o b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/common/utils/stdio/read.o new file mode 100644 index 0000000..c728b19 Binary files /dev/null and b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/common/utils/stdio/read.o differ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/common/utils/stdio/write.d b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/common/utils/stdio/write.d new file mode 100644 index 0000000..051026c --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/common/utils/stdio/write.d @@ -0,0 +1,328 @@ +src/ASF/common/utils/stdio/write.d src/ASF/common/utils/stdio/write.o: \ + ../src/ASF/common/utils/stdio/write.c ../src/ASF/sam/utils/compiler.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h \ + ../src/ASF/common/utils/parts.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/preprocessor/tpaste.h \ + ../src/ASF/sam/utils/preprocessor/stringz.h \ + ../src/ASF/sam/utils/preprocessor/mrepeat.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/header_files/io.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cm3.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \ + ../src/ASF/common/utils/interrupt.h \ + ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h + +../src/ASF/sam/utils/compiler.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h: + +../src/ASF/common/utils/parts.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/preprocessor/tpaste.h: + +../src/ASF/sam/utils/preprocessor/stringz.h: + +../src/ASF/sam/utils/preprocessor/mrepeat.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/header_files/io.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cm3.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h: + +../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h: + +../src/ASF/common/utils/interrupt.h: + +../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h: diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/common/utils/stdio/write.o b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/common/utils/stdio/write.o new file mode 100644 index 0000000..2e3932f Binary files /dev/null and b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/common/utils/stdio/write.o differ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/boards/sam3x_ek/init.d b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/boards/sam3x_ek/init.d new file mode 100644 index 0000000..795bc8a --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/boards/sam3x_ek/init.d @@ -0,0 +1,376 @@ +src/ASF/sam/boards/sam3x_ek/init.d src/ASF/sam/boards/sam3x_ek/init.o: \ + ../src/ASF/sam/boards/sam3x_ek/init.c ../src/ASF/sam/utils/compiler.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h \ + ../src/ASF/common/utils/parts.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/preprocessor/tpaste.h \ + ../src/ASF/sam/utils/preprocessor/stringz.h \ + ../src/ASF/sam/utils/preprocessor/mrepeat.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/header_files/io.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cm3.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \ + ../src/ASF/common/utils/interrupt.h \ + ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \ + ../src/ASF/common/boards/board.h \ + ../src/ASF/sam/boards/sam3x_ek/sam3x_ek.h \ + ../src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.h \ + ../src/config/conf_board.h ../src/ASF/common/services/gpio/gpio.h \ + ../src/ASF/common/services/gpio/sam_gpio/sam_gpio.h \ + ../src/ASF/sam/drivers/pio/pio.h \ + ../src/ASF/common/services/ioport/ioport.h \ + ../src/ASF/common/services/ioport/sam/ioport_pio.h \ + ../src/ASF/common/services/clock/sysclk.h ../src/config/conf_clock.h \ + ../src/ASF/common/services/clock/sam3x/sysclk.h \ + ../src/ASF/common/services/clock/osc.h \ + ../src/ASF/common/services/clock/sam3x/osc.h \ + ../src/ASF/sam/drivers/pmc/pmc.h ../src/ASF/common/services/clock/pll.h \ + ../src/ASF/common/services/clock/sam3x/pll.h + +../src/ASF/sam/utils/compiler.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h: + +../src/ASF/common/utils/parts.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/preprocessor/tpaste.h: + +../src/ASF/sam/utils/preprocessor/stringz.h: + +../src/ASF/sam/utils/preprocessor/mrepeat.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/header_files/io.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cm3.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h: + +../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h: + +../src/ASF/common/utils/interrupt.h: + +../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h: + +../src/ASF/common/boards/board.h: + +../src/ASF/sam/boards/sam3x_ek/sam3x_ek.h: + +../src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.h: + +../src/config/conf_board.h: + +../src/ASF/common/services/gpio/gpio.h: + +../src/ASF/common/services/gpio/sam_gpio/sam_gpio.h: + +../src/ASF/sam/drivers/pio/pio.h: + +../src/ASF/common/services/ioport/ioport.h: + +../src/ASF/common/services/ioport/sam/ioport_pio.h: + +../src/ASF/common/services/clock/sysclk.h: + +../src/config/conf_clock.h: + +../src/ASF/common/services/clock/sam3x/sysclk.h: + +../src/ASF/common/services/clock/osc.h: + +../src/ASF/common/services/clock/sam3x/osc.h: + +../src/ASF/sam/drivers/pmc/pmc.h: + +../src/ASF/common/services/clock/pll.h: + +../src/ASF/common/services/clock/sam3x/pll.h: diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/boards/sam3x_ek/init.o b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/boards/sam3x_ek/init.o new file mode 100644 index 0000000..84b31dc Binary files /dev/null and b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/boards/sam3x_ek/init.o differ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/boards/sam3x_ek/led.d b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/boards/sam3x_ek/led.d new file mode 100644 index 0000000..2e9e438 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/boards/sam3x_ek/led.d @@ -0,0 +1,349 @@ +src/ASF/sam/boards/sam3x_ek/led.d src/ASF/sam/boards/sam3x_ek/led.o: \ + ../src/ASF/sam/boards/sam3x_ek/led.c ../src/ASF/common/boards/board.h \ + ../src/ASF/sam/utils/compiler.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h \ + ../src/ASF/common/utils/parts.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/preprocessor/tpaste.h \ + ../src/ASF/sam/utils/preprocessor/stringz.h \ + ../src/ASF/sam/utils/preprocessor/mrepeat.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/header_files/io.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cm3.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \ + ../src/ASF/common/utils/interrupt.h \ + ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \ + ../src/ASF/sam/boards/sam3x_ek/sam3x_ek.h \ + ../src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.h \ + ../src/ASF/sam/boards/sam3x_ek/led.h \ + ../src/ASF/common/services/gpio/gpio.h \ + ../src/ASF/common/services/gpio/sam_gpio/sam_gpio.h \ + ../src/ASF/sam/drivers/pio/pio.h + +../src/ASF/common/boards/board.h: + +../src/ASF/sam/utils/compiler.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h: + +../src/ASF/common/utils/parts.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/preprocessor/tpaste.h: + +../src/ASF/sam/utils/preprocessor/stringz.h: + +../src/ASF/sam/utils/preprocessor/mrepeat.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/header_files/io.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cm3.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h: + +../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h: + +../src/ASF/common/utils/interrupt.h: + +../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h: + +../src/ASF/sam/boards/sam3x_ek/sam3x_ek.h: + +../src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.h: + +../src/ASF/sam/boards/sam3x_ek/led.h: + +../src/ASF/common/services/gpio/gpio.h: + +../src/ASF/common/services/gpio/sam_gpio/sam_gpio.h: + +../src/ASF/sam/drivers/pio/pio.h: diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/boards/sam3x_ek/led.o b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/boards/sam3x_ek/led.o new file mode 100644 index 0000000..015502c Binary files /dev/null and b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/boards/sam3x_ek/led.o differ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/components/ethernet_phy/dm9161a/ethernet_phy.d b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/components/ethernet_phy/dm9161a/ethernet_phy.d new file mode 100644 index 0000000..af67301 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/components/ethernet_phy/dm9161a/ethernet_phy.d @@ -0,0 +1,350 @@ +src/ASF/sam/components/ethernet_phy/dm9161a/ethernet_phy.d \ + src/ASF/sam/components/ethernet_phy/dm9161a/ethernet_phy.o: \ + ../src/ASF/sam/components/ethernet_phy/dm9161a/ethernet_phy.c \ + ../src/ASF/sam/components/ethernet_phy/dm9161a/ethernet_phy.h \ + ../src/ASF/sam/utils/compiler.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h \ + ../src/ASF/common/utils/parts.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/preprocessor/tpaste.h \ + ../src/ASF/sam/utils/preprocessor/stringz.h \ + ../src/ASF/sam/utils/preprocessor/mrepeat.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/header_files/io.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cm3.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \ + ../src/ASF/common/utils/interrupt.h \ + ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \ + ../src/ASF/common/boards/board.h \ + ../src/ASF/sam/boards/sam3x_ek/sam3x_ek.h \ + ../src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.h \ + ../src/ASF/sam/drivers/emac/emac.h ../src/config/conf_eth.h \ + ../src/ASF/sam/components/ethernet_phy/dm9161a/mii.h + +../src/ASF/sam/components/ethernet_phy/dm9161a/ethernet_phy.h: + +../src/ASF/sam/utils/compiler.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h: + +../src/ASF/common/utils/parts.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/preprocessor/tpaste.h: + +../src/ASF/sam/utils/preprocessor/stringz.h: + +../src/ASF/sam/utils/preprocessor/mrepeat.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/header_files/io.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cm3.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h: + +../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h: + +../src/ASF/common/utils/interrupt.h: + +../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h: + +../src/ASF/common/boards/board.h: + +../src/ASF/sam/boards/sam3x_ek/sam3x_ek.h: + +../src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.h: + +../src/ASF/sam/drivers/emac/emac.h: + +../src/config/conf_eth.h: + +../src/ASF/sam/components/ethernet_phy/dm9161a/mii.h: diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/components/ethernet_phy/dm9161a/ethernet_phy.o b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/components/ethernet_phy/dm9161a/ethernet_phy.o new file mode 100644 index 0000000..8c0c382 Binary files /dev/null and b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/components/ethernet_phy/dm9161a/ethernet_phy.o differ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/emac/emac.d b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/emac/emac.d new file mode 100644 index 0000000..7023997 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/emac/emac.d @@ -0,0 +1,339 @@ +src/ASF/sam/drivers/emac/emac.d src/ASF/sam/drivers/emac/emac.o: \ + ../src/ASF/sam/drivers/emac/emac.c ../src/ASF/sam/utils/compiler.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h \ + ../src/ASF/common/utils/parts.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/preprocessor/tpaste.h \ + ../src/ASF/sam/utils/preprocessor/stringz.h \ + ../src/ASF/sam/utils/preprocessor/mrepeat.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/header_files/io.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cm3.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \ + ../src/ASF/common/utils/interrupt.h \ + ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \ + ../src/ASF/sam/drivers/emac/emac.h ../src/config/conf_eth.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h + +../src/ASF/sam/utils/compiler.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h: + +../src/ASF/common/utils/parts.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/preprocessor/tpaste.h: + +../src/ASF/sam/utils/preprocessor/stringz.h: + +../src/ASF/sam/utils/preprocessor/mrepeat.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/header_files/io.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cm3.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h: + +../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h: + +../src/ASF/common/utils/interrupt.h: + +../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h: + +../src/ASF/sam/drivers/emac/emac.h: + +../src/config/conf_eth.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h: diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/emac/emac.o b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/emac/emac.o new file mode 100644 index 0000000..2572631 Binary files /dev/null and b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/emac/emac.o differ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/pio/pio.d b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/pio/pio.d new file mode 100644 index 0000000..6e69609 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/pio/pio.d @@ -0,0 +1,331 @@ +src/ASF/sam/drivers/pio/pio.d src/ASF/sam/drivers/pio/pio.o: \ + ../src/ASF/sam/drivers/pio/pio.c ../src/ASF/sam/drivers/pio/pio.h \ + ../src/ASF/sam/utils/compiler.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h \ + ../src/ASF/common/utils/parts.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/preprocessor/tpaste.h \ + ../src/ASF/sam/utils/preprocessor/stringz.h \ + ../src/ASF/sam/utils/preprocessor/mrepeat.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/header_files/io.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cm3.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \ + ../src/ASF/common/utils/interrupt.h \ + ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h + +../src/ASF/sam/drivers/pio/pio.h: + +../src/ASF/sam/utils/compiler.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h: + +../src/ASF/common/utils/parts.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/preprocessor/tpaste.h: + +../src/ASF/sam/utils/preprocessor/stringz.h: + +../src/ASF/sam/utils/preprocessor/mrepeat.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/header_files/io.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cm3.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h: + +../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h: + +../src/ASF/common/utils/interrupt.h: + +../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h: diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/pio/pio.o b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/pio/pio.o new file mode 100644 index 0000000..bff0c02 Binary files /dev/null and b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/pio/pio.o differ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/pio/pio_handler.d b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/pio/pio_handler.d new file mode 100644 index 0000000..52571a3 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/pio/pio_handler.d @@ -0,0 +1,335 @@ +src/ASF/sam/drivers/pio/pio_handler.d \ + src/ASF/sam/drivers/pio/pio_handler.o: \ + ../src/ASF/sam/drivers/pio/pio_handler.c \ + ../src/ASF/sam/drivers/pio/pio.h ../src/ASF/sam/utils/compiler.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h \ + ../src/ASF/common/utils/parts.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/preprocessor/tpaste.h \ + ../src/ASF/sam/utils/preprocessor/stringz.h \ + ../src/ASF/sam/utils/preprocessor/mrepeat.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/header_files/io.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cm3.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \ + ../src/ASF/common/utils/interrupt.h \ + ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \ + ../src/ASF/sam/drivers/pio/pio_handler.h + +../src/ASF/sam/drivers/pio/pio.h: + +../src/ASF/sam/utils/compiler.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h: + +../src/ASF/common/utils/parts.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/preprocessor/tpaste.h: + +../src/ASF/sam/utils/preprocessor/stringz.h: + +../src/ASF/sam/utils/preprocessor/mrepeat.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/header_files/io.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cm3.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h: + +../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h: + +../src/ASF/common/utils/interrupt.h: + +../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h: + +../src/ASF/sam/drivers/pio/pio_handler.h: diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/pio/pio_handler.o b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/pio/pio_handler.o new file mode 100644 index 0000000..a1fa280 Binary files /dev/null and b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/pio/pio_handler.o differ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/pmc/pmc.d b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/pmc/pmc.d new file mode 100644 index 0000000..ba9b98b --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/pmc/pmc.d @@ -0,0 +1,331 @@ +src/ASF/sam/drivers/pmc/pmc.d src/ASF/sam/drivers/pmc/pmc.o: \ + ../src/ASF/sam/drivers/pmc/pmc.c ../src/ASF/sam/drivers/pmc/pmc.h \ + ../src/ASF/sam/utils/compiler.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h \ + ../src/ASF/common/utils/parts.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/preprocessor/tpaste.h \ + ../src/ASF/sam/utils/preprocessor/stringz.h \ + ../src/ASF/sam/utils/preprocessor/mrepeat.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/header_files/io.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cm3.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \ + ../src/ASF/common/utils/interrupt.h \ + ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h + +../src/ASF/sam/drivers/pmc/pmc.h: + +../src/ASF/sam/utils/compiler.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h: + +../src/ASF/common/utils/parts.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/preprocessor/tpaste.h: + +../src/ASF/sam/utils/preprocessor/stringz.h: + +../src/ASF/sam/utils/preprocessor/mrepeat.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/header_files/io.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cm3.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h: + +../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h: + +../src/ASF/common/utils/interrupt.h: + +../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h: diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/pmc/pmc.o b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/pmc/pmc.o new file mode 100644 index 0000000..9b7a04d Binary files /dev/null and b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/pmc/pmc.o differ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/pmc/sleep.d b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/pmc/sleep.d new file mode 100644 index 0000000..c190e7f --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/pmc/sleep.d @@ -0,0 +1,342 @@ +src/ASF/sam/drivers/pmc/sleep.d src/ASF/sam/drivers/pmc/sleep.o: \ + ../src/ASF/sam/drivers/pmc/sleep.c ../src/ASF/sam/utils/compiler.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h \ + ../src/ASF/common/utils/parts.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/preprocessor/tpaste.h \ + ../src/ASF/sam/utils/preprocessor/stringz.h \ + ../src/ASF/sam/utils/preprocessor/mrepeat.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/header_files/io.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cm3.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \ + ../src/ASF/common/utils/interrupt.h \ + ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \ + ../src/ASF/sam/drivers/pmc/sleep.h ../src/ASF/sam/drivers/pmc/pmc.h \ + ../src/ASF/common/boards/board.h \ + ../src/ASF/sam/boards/sam3x_ek/sam3x_ek.h \ + ../src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.h + +../src/ASF/sam/utils/compiler.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h: + +../src/ASF/common/utils/parts.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/preprocessor/tpaste.h: + +../src/ASF/sam/utils/preprocessor/stringz.h: + +../src/ASF/sam/utils/preprocessor/mrepeat.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/header_files/io.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cm3.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h: + +../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h: + +../src/ASF/common/utils/interrupt.h: + +../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h: + +../src/ASF/sam/drivers/pmc/sleep.h: + +../src/ASF/sam/drivers/pmc/pmc.h: + +../src/ASF/common/boards/board.h: + +../src/ASF/sam/boards/sam3x_ek/sam3x_ek.h: + +../src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.h: diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/pmc/sleep.o b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/pmc/sleep.o new file mode 100644 index 0000000..42332b4 Binary files /dev/null and b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/pmc/sleep.o differ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/rstc/rstc.d b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/rstc/rstc.d new file mode 100644 index 0000000..108709d --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/rstc/rstc.d @@ -0,0 +1,331 @@ +src/ASF/sam/drivers/rstc/rstc.d src/ASF/sam/drivers/rstc/rstc.o: \ + ../src/ASF/sam/drivers/rstc/rstc.c ../src/ASF/sam/drivers/rstc/rstc.h \ + ../src/ASF/sam/utils/compiler.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h \ + ../src/ASF/common/utils/parts.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/preprocessor/tpaste.h \ + ../src/ASF/sam/utils/preprocessor/stringz.h \ + ../src/ASF/sam/utils/preprocessor/mrepeat.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/header_files/io.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cm3.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \ + ../src/ASF/common/utils/interrupt.h \ + ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h + +../src/ASF/sam/drivers/rstc/rstc.h: + +../src/ASF/sam/utils/compiler.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h: + +../src/ASF/common/utils/parts.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/preprocessor/tpaste.h: + +../src/ASF/sam/utils/preprocessor/stringz.h: + +../src/ASF/sam/utils/preprocessor/mrepeat.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/header_files/io.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cm3.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h: + +../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h: + +../src/ASF/common/utils/interrupt.h: + +../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h: diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/rstc/rstc.o b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/rstc/rstc.o new file mode 100644 index 0000000..4433e7f Binary files /dev/null and b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/rstc/rstc.o differ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/uart/uart.d b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/uart/uart.d new file mode 100644 index 0000000..039561d --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/uart/uart.d @@ -0,0 +1,331 @@ +src/ASF/sam/drivers/uart/uart.d src/ASF/sam/drivers/uart/uart.o: \ + ../src/ASF/sam/drivers/uart/uart.c ../src/ASF/sam/drivers/uart/uart.h \ + ../src/ASF/sam/utils/compiler.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h \ + ../src/ASF/common/utils/parts.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/preprocessor/tpaste.h \ + ../src/ASF/sam/utils/preprocessor/stringz.h \ + ../src/ASF/sam/utils/preprocessor/mrepeat.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/header_files/io.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cm3.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \ + ../src/ASF/common/utils/interrupt.h \ + ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h + +../src/ASF/sam/drivers/uart/uart.h: + +../src/ASF/sam/utils/compiler.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h: + +../src/ASF/common/utils/parts.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/preprocessor/tpaste.h: + +../src/ASF/sam/utils/preprocessor/stringz.h: + +../src/ASF/sam/utils/preprocessor/mrepeat.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/header_files/io.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cm3.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h: + +../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h: + +../src/ASF/common/utils/interrupt.h: + +../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h: diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/uart/uart.o b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/uart/uart.o new file mode 100644 index 0000000..da4da71 Binary files /dev/null and b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/uart/uart.o differ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/usart/usart.d b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/usart/usart.d new file mode 100644 index 0000000..ba59f65 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/usart/usart.d @@ -0,0 +1,331 @@ +src/ASF/sam/drivers/usart/usart.d src/ASF/sam/drivers/usart/usart.o: \ + ../src/ASF/sam/drivers/usart/usart.c \ + ../src/ASF/sam/drivers/usart/usart.h ../src/ASF/sam/utils/compiler.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h \ + ../src/ASF/common/utils/parts.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/preprocessor/tpaste.h \ + ../src/ASF/sam/utils/preprocessor/stringz.h \ + ../src/ASF/sam/utils/preprocessor/mrepeat.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/header_files/io.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cm3.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \ + ../src/ASF/common/utils/interrupt.h \ + ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h + +../src/ASF/sam/drivers/usart/usart.h: + +../src/ASF/sam/utils/compiler.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h: + +../src/ASF/common/utils/parts.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/preprocessor/tpaste.h: + +../src/ASF/sam/utils/preprocessor/stringz.h: + +../src/ASF/sam/utils/preprocessor/mrepeat.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/header_files/io.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cm3.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h: + +../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h: + +../src/ASF/common/utils/interrupt.h: + +../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h: diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/usart/usart.o b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/usart/usart.o new file mode 100644 index 0000000..e3ef725 Binary files /dev/null and b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/drivers/usart/usart.o differ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.d b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.d new file mode 100644 index 0000000..425be3a --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.d @@ -0,0 +1,333 @@ +src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.d \ + src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.o: \ + ../src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.c \ + ../src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cm3.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h \ + ../src/ASF/sam/utils/compiler.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h \ + ../src/ASF/common/utils/parts.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/preprocessor/tpaste.h \ + ../src/ASF/sam/utils/preprocessor/stringz.h \ + ../src/ASF/sam/utils/preprocessor/mrepeat.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/header_files/io.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \ + ../src/ASF/common/utils/interrupt.h \ + ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h + +../src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cm3.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h: + +../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h: + +../src/ASF/sam/utils/compiler.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h: + +../src/ASF/common/utils/parts.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/preprocessor/tpaste.h: + +../src/ASF/sam/utils/preprocessor/stringz.h: + +../src/ASF/sam/utils/preprocessor/mrepeat.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/header_files/io.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h: + +../src/ASF/common/utils/interrupt.h: + +../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h: diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.o b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.o new file mode 100644 index 0000000..918fab8 Binary files /dev/null and b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.o differ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/utils/cmsis/sam3x/source/templates/gcc/startup_sam3x.d b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/utils/cmsis/sam3x/source/templates/gcc/startup_sam3x.d new file mode 100644 index 0000000..46ce505 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/utils/cmsis/sam3x/source/templates/gcc/startup_sam3x.d @@ -0,0 +1,333 @@ +src/ASF/sam/utils/cmsis/sam3x/source/templates/gcc/startup_sam3x.d \ + src/ASF/sam/utils/cmsis/sam3x/source/templates/gcc/startup_sam3x.o: \ + ../src/ASF/sam/utils/cmsis/sam3x/source/templates/gcc/startup_sam3x.c \ + ../src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cm3.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h \ + ../src/ASF/sam/utils/compiler.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h \ + ../src/ASF/common/utils/parts.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/preprocessor/tpaste.h \ + ../src/ASF/sam/utils/preprocessor/stringz.h \ + ../src/ASF/sam/utils/preprocessor/mrepeat.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/header_files/io.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \ + ../src/ASF/common/utils/interrupt.h \ + ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h + +../src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cm3.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h: + +../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h: + +../src/ASF/sam/utils/compiler.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h: + +../src/ASF/common/utils/parts.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/preprocessor/tpaste.h: + +../src/ASF/sam/utils/preprocessor/stringz.h: + +../src/ASF/sam/utils/preprocessor/mrepeat.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/header_files/io.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h: + +../src/ASF/common/utils/interrupt.h: + +../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h: diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/utils/cmsis/sam3x/source/templates/gcc/startup_sam3x.o b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/utils/cmsis/sam3x/source/templates/gcc/startup_sam3x.o new file mode 100644 index 0000000..6b4992e Binary files /dev/null and b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/utils/cmsis/sam3x/source/templates/gcc/startup_sam3x.o differ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.d b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.d new file mode 100644 index 0000000..910576a --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.d @@ -0,0 +1,333 @@ +src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.d \ + src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.o: \ + ../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.c \ + ../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \ + ../src/ASF/sam/utils/compiler.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h \ + ../src/ASF/common/utils/parts.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/preprocessor/tpaste.h \ + ../src/ASF/sam/utils/preprocessor/stringz.h \ + ../src/ASF/sam/utils/preprocessor/mrepeat.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/header_files/io.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cm3.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \ + ../src/ASF/common/utils/interrupt.h \ + ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h + +../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h: + +../src/ASF/sam/utils/compiler.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h: + +../src/ASF/common/utils/parts.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/preprocessor/tpaste.h: + +../src/ASF/sam/utils/preprocessor/stringz.h: + +../src/ASF/sam/utils/preprocessor/mrepeat.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/header_files/io.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cm3.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h: + +../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h: + +../src/ASF/common/utils/interrupt.h: + +../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h: diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.o b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.o new file mode 100644 index 0000000..41739da Binary files /dev/null and b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.o differ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/utils/syscalls/gcc/syscalls.d b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/utils/syscalls/gcc/syscalls.d new file mode 100644 index 0000000..1380bd9 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/utils/syscalls/gcc/syscalls.d @@ -0,0 +1,75 @@ +src/ASF/sam/utils/syscalls/gcc/syscalls.d \ + src/ASF/sam/utils/syscalls/gcc/syscalls.o: \ + ../src/ASF/sam/utils/syscalls/gcc/syscalls.c \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stat.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\time.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\time.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stat.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\time.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\time.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h: diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/utils/syscalls/gcc/syscalls.o b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/utils/syscalls/gcc/syscalls.o new file mode 100644 index 0000000..88bd11a Binary files /dev/null and b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/ASF/sam/utils/syscalls/gcc/syscalls.o differ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/emac_example.d b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/emac_example.d new file mode 100644 index 0000000..5e8a87f --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/emac_example.d @@ -0,0 +1,424 @@ +src/emac_example.d src/emac_example.o: ../src/emac_example.c ../src/asf.h \ + ../src/ASF/sam/utils/compiler.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h \ + ../src/ASF/common/utils/parts.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/preprocessor/tpaste.h \ + ../src/ASF/sam/utils/preprocessor/stringz.h \ + ../src/ASF/sam/utils/preprocessor/mrepeat.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/header_files/io.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cm3.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \ + ../src/ASF/common/utils/interrupt.h \ + ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \ + ../src/ASF/sam/utils/status_codes.h ../src/ASF/sam/drivers/emac/emac.h \ + ../src/config/conf_eth.h \ + ../src/ASF/sam/components/ethernet_phy/dm9161a/ethernet_phy.h \ + ../src/ASF/common/boards/board.h \ + ../src/ASF/sam/boards/sam3x_ek/sam3x_ek.h \ + ../src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.h \ + ../src/ASF/common/services/gpio/gpio.h \ + ../src/ASF/common/services/gpio/sam_gpio/sam_gpio.h \ + ../src/ASF/sam/drivers/pio/pio.h \ + ../src/ASF/common/services/ioport/ioport.h \ + ../src/ASF/common/services/ioport/sam/ioport_pio.h \ + ../src/ASF/common/services/clock/sysclk.h ../src/config/conf_clock.h \ + ../src/ASF/common/services/clock/sam3x/sysclk.h \ + ../src/ASF/common/services/clock/osc.h \ + ../src/ASF/common/services/clock/sam3x/osc.h \ + ../src/ASF/sam/drivers/pmc/pmc.h ../src/ASF/common/services/clock/pll.h \ + ../src/ASF/common/services/clock/sam3x/pll.h \ + ../src/ASF/sam/drivers/pmc/sleep.h ../src/ASF/sam/drivers/rstc/rstc.h \ + ../src/ASF/sam/boards/sam3x_ek/led.h \ + ../src/ASF/common/utils/stdio/stdio_serial/stdio_serial.h \ + ../src/ASF/common/services/serial/serial.h \ + ../src/ASF/common/services/serial/sam_uart/uart_serial.h \ + ../src/ASF/sam/drivers/uart/uart.h ../src/ASF/sam/drivers/usart/usart.h \ + ../src/config/conf_uart_serial.h \ + ../src/ASF/sam/drivers/pio/pio_handler.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h \ + c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h \ + ../src/mini_ip.h + +../src/asf.h: + +../src/ASF/sam/utils/compiler.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stddef.h: + +../src/ASF/common/utils/parts.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/preprocessor/tpaste.h: + +../src/ASF/sam/utils/preprocessor/stringz.h: + +../src/ASF/sam/utils/preprocessor/mrepeat.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/header_files/io.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cm3.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h: + +../src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdarg.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\4.9.3\include\stdbool.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h: + +../src/ASF/common/utils/interrupt.h: + +../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h: + +../src/ASF/sam/utils/status_codes.h: + +../src/ASF/sam/drivers/emac/emac.h: + +../src/config/conf_eth.h: + +../src/ASF/sam/components/ethernet_phy/dm9161a/ethernet_phy.h: + +../src/ASF/common/boards/board.h: + +../src/ASF/sam/boards/sam3x_ek/sam3x_ek.h: + +../src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.h: + +../src/ASF/common/services/gpio/gpio.h: + +../src/ASF/common/services/gpio/sam_gpio/sam_gpio.h: + +../src/ASF/sam/drivers/pio/pio.h: + +../src/ASF/common/services/ioport/ioport.h: + +../src/ASF/common/services/ioport/sam/ioport_pio.h: + +../src/ASF/common/services/clock/sysclk.h: + +../src/config/conf_clock.h: + +../src/ASF/common/services/clock/sam3x/sysclk.h: + +../src/ASF/common/services/clock/osc.h: + +../src/ASF/common/services/clock/sam3x/osc.h: + +../src/ASF/sam/drivers/pmc/pmc.h: + +../src/ASF/common/services/clock/pll.h: + +../src/ASF/common/services/clock/sam3x/pll.h: + +../src/ASF/sam/drivers/pmc/sleep.h: + +../src/ASF/sam/drivers/rstc/rstc.h: + +../src/ASF/sam/boards/sam3x_ek/led.h: + +../src/ASF/common/utils/stdio/stdio_serial/stdio_serial.h: + +../src/ASF/common/services/serial/serial.h: + +../src/ASF/common/services/serial/sam_uart/uart_serial.h: + +../src/ASF/sam/drivers/uart/uart.h: + +../src/ASF/sam/drivers/usart/usart.h: + +../src/config/conf_uart_serial.h: + +../src/ASF/sam/drivers/pio/pio_handler.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h: + +c:\program\ files\ (x86)\atmel7\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h: + +../src/mini_ip.h: diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/emac_example.o b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/emac_example.o new file mode 100644 index 0000000..eccc394 Binary files /dev/null and b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/Debug/src/emac_example.o differ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE.componentinfo.xml b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE.componentinfo.xml new file mode 100644 index 0000000..e275755 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE.componentinfo.xml @@ -0,0 +1,4 @@ + + + + \ No newline at end of file diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE.cproj b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE.cproj new file mode 100644 index 0000000..d0336bc --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE.cproj @@ -0,0 +1,1013 @@ + + + + 2.0 + 7.0 + com.Atmel.ARMGCC.C + dce6c7e3-ee26-4d79-826b-08594b9ad897 + ATSAM3X8E + sam3x + Executable + C + $(MSBuildProjectName) + .elf + $(MSBuildProjectDirectory)\$(Configuration) + EMAC_EMAC_EXAMPLE_TAIJI_DUE + EMAC_EMAC_EXAMPLE_TAIJI_DUE + EMAC_EMAC_EXAMPLE_TAIJI_DUE + Native + true + false + true + true + 0x20000000 + + true + exception_table + 2 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + com.atmel.avrdbg.tool.atmelice + J41800027347 + 0x285E0A60 + + + + 7500000 + + JTAG + + com.atmel.avrdbg.tool.atmelice + J41800027347 + Atmel-ICE + + JTAG + 7500000 + + + + + True + True + True + True + True + + + NDEBUG + BOARD=SAM3X_EK + __SAM3X8H__ + scanf=iscanf + ARM_MATH_CM3=true + printf=iprintf + + + + + ../sam/drivers/emac/emac_example/sam3x8h_sam3x_ek + ../src/ASF/sam/components/ethernet_phy/dm9161a + ../src/ASF/common/utils + ../src/ASF/common/services/serial/sam_uart + ../src/ASF/sam/drivers/pmc + ../src/ASF/common/services/gpio + ../src/ASF/sam/boards + ../src/ASF/sam/drivers/pio + ../src/ASF/common/boards + ../src/ASF/sam/utils/cmsis/sam3x/source/templates + ../src/ASF/sam/drivers/emac + ../src/ASF/sam/utils/header_files + ../src/ASF/sam/drivers/rstc + ../src/ASF/common/services/ioport + ../src/ASF/thirdparty/CMSIS/Include + ../src/ASF/sam/utils/cmsis/sam3x/include + ../src/config + ../src/ASF/thirdparty/CMSIS/Lib/GCC + ../src + ../src/ASF/common/services/clock + ../src/ASF/common/utils/stdio/stdio_serial + ../src/ASF/sam/utils + ../src/ASF/sam/utils/preprocessor + ../src/ASF/common/services/serial + ../src/ASF/sam/drivers/usart + ../src/ASF/sam/drivers/uart + ../src/ASF/sam/boards/sam3x_ek + + + Optimize for size (-Os) + -fdata-sections + True + True + -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 + + + libarm_cortexM3l_math + libm + + + + + ..\src\ASF\thirdparty\CMSIS\Lib\GCC + + + True + -Wl,--entry=Reset_Handler -Wl,--cref -mthumb -T../src/ASF/sam/utils/linker_scripts/sam3x/sam3x8/gcc/flash.ld + -DARM_MATH_CM3=true -DBOARD=SAM3X_EK -D__SAM3X8H__ -Dprintf=iprintf -Dscanf=iscanf + + + ../sam/drivers/emac/emac_example/sam3x8h_sam3x_ek + ../src/ASF/sam/components/ethernet_phy/dm9161a + ../src/ASF/common/utils + ../src/ASF/common/services/serial/sam_uart + ../src/ASF/sam/drivers/pmc + ../src/ASF/common/services/gpio + ../src/ASF/sam/boards + ../src/ASF/sam/drivers/pio + ../src/ASF/common/boards + ../src/ASF/sam/utils/cmsis/sam3x/source/templates + ../src/ASF/sam/drivers/emac + ../src/ASF/sam/utils/header_files + ../src/ASF/sam/drivers/rstc + ../src/ASF/common/services/ioport + ../src/ASF/thirdparty/CMSIS/Include + ../src/ASF/sam/utils/cmsis/sam3x/include + ../src/config + ../src/ASF/thirdparty/CMSIS/Lib/GCC + ../src + ../src/ASF/common/services/clock + ../src/ASF/common/utils/stdio/stdio_serial + ../src/ASF/sam/utils + ../src/ASF/sam/utils/preprocessor + ../src/ASF/common/services/serial + ../src/ASF/sam/drivers/usart + ../src/ASF/sam/drivers/uart + ../src/ASF/sam/boards/sam3x_ek + + + + + + + + + True + True + True + True + True + + + DEBUG + BOARD=SAM3X_EK + __SAM3X8H__ + scanf=iscanf + ARM_MATH_CM3=true + printf=iprintf + + + + + ../sam/drivers/emac/emac_example/sam3x8h_sam3x_ek + ../src/ASF/sam/components/ethernet_phy/dm9161a + ../src/ASF/common/utils + ../src/ASF/common/services/serial/sam_uart + ../src/ASF/sam/drivers/pmc + ../src/ASF/common/services/gpio + ../src/ASF/sam/boards + ../src/ASF/sam/drivers/pio + ../src/ASF/common/boards + ../src/ASF/sam/utils/cmsis/sam3x/source/templates + ../src/ASF/sam/drivers/emac + ../src/ASF/sam/utils/header_files + ../src/ASF/sam/drivers/rstc + ../src/ASF/common/services/ioport + ../src/ASF/thirdparty/CMSIS/Include + ../src/ASF/sam/utils/cmsis/sam3x/include + ../src/config + ../src/ASF/thirdparty/CMSIS/Lib/GCC + ../src + ../src/ASF/common/services/clock + ../src/ASF/common/utils/stdio/stdio_serial + ../src/ASF/sam/utils + ../src/ASF/sam/utils/preprocessor + ../src/ASF/common/services/serial + ../src/ASF/sam/drivers/usart + ../src/ASF/sam/drivers/uart + ../src/ASF/sam/boards/sam3x_ek + + + Optimize (-O1) + -fdata-sections + True + Maximum (-g3) + True + -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 + + + libarm_cortexM3l_math + libm + + + + + ..\src\ASF\thirdparty\CMSIS\Lib\GCC + + + True + -Wl,--entry=Reset_Handler -Wl,--cref -mthumb -T../src/ASF/sam/utils/linker_scripts/sam3x/sam3x8/gcc/flash.ld + Default (-g) + -DARM_MATH_CM3=true -DBOARD=SAM3X_EK -D__SAM3X8H__ -Dprintf=iprintf -Dscanf=iscanf + + + ../sam/drivers/emac/emac_example/sam3x8h_sam3x_ek + ../src/ASF/sam/components/ethernet_phy/dm9161a + ../src/ASF/common/utils + ../src/ASF/common/services/serial/sam_uart + ../src/ASF/sam/drivers/pmc + ../src/ASF/common/services/gpio + ../src/ASF/sam/boards + ../src/ASF/sam/drivers/pio + ../src/ASF/common/boards + ../src/ASF/sam/utils/cmsis/sam3x/source/templates + ../src/ASF/sam/drivers/emac + ../src/ASF/sam/utils/header_files + ../src/ASF/sam/drivers/rstc + ../src/ASF/common/services/ioport + ../src/ASF/thirdparty/CMSIS/Include + ../src/ASF/sam/utils/cmsis/sam3x/include + ../src/config + ../src/ASF/thirdparty/CMSIS/Lib/GCC + ../src + ../src/ASF/common/services/clock + ../src/ASF/common/utils/stdio/stdio_serial + ../src/ASF/sam/utils + ../src/ASF/sam/utils/preprocessor + ../src/ASF/common/services/serial + ../src/ASF/sam/drivers/usart + ../src/ASF/sam/drivers/uart + ../src/ASF/sam/boards/sam3x_ek + + + Default (-Wa,-g) + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + + \ No newline at end of file diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/boards/board.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/boards/board.h new file mode 100644 index 0000000..7f995a0 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/boards/board.h @@ -0,0 +1,436 @@ +/** + * \file + * + * \brief Standard board header file. + * + * This file includes the appropriate board header file according to the + * defined board (parameter BOARD). + * + * Copyright (c) 2009-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/** + * \defgroup group_common_boards Generic board support + * + * The generic board support module includes board-specific definitions + * and function prototypes, such as the board initialization function. + * + * \{ + */ + +#include "compiler.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/*! \name Base Boards + */ +//! @{ +#define EVK1100 1 //!< AT32UC3A EVK1100 board. +#define EVK1101 2 //!< AT32UC3B EVK1101 board. +#define UC3C_EK 3 //!< AT32UC3C UC3C-EK board. +#define EVK1104 4 //!< AT32UC3A3 EVK1104 board. +#define EVK1105 5 //!< AT32UC3A EVK1105 board. +#define STK600_RCUC3L0 6 //!< STK600 RCUC3L0 board. +#define UC3L_EK 7 //!< AT32UC3L-EK board. +#define XPLAIN 8 //!< ATxmega128A1 Xplain board. +#define STK600_RC064X 10 //!< ATxmega256A3 STK600 board. +#define STK600_RC100X 11 //!< ATxmega128A1 STK600 board. +#define UC3_A3_XPLAINED 13 //!< ATUC3A3 UC3-A3 Xplained board. +#define UC3_L0_XPLAINED 15 //!< ATUC3L0 UC3-L0 Xplained board. +#define STK600_RCUC3D 16 //!< STK600 RCUC3D board. +#define STK600_RCUC3C0 17 //!< STK600 RCUC3C board. +#define XMEGA_B1_XPLAINED 18 //!< ATxmega128B1 Xplained board. +#define XMEGA_A1_XPLAINED 19 //!< ATxmega128A1 Xplain-A1 board. +#define XMEGA_A1U_XPLAINED_PRO 20 //!< ATxmega128A1U XMEGA-A1U Xplained Pro board. +#define STK600_RCUC3L4 21 //!< ATUCL4 STK600 board. +#define UC3_L0_XPLAINED_BC 22 //!< ATUC3L0 UC3-L0 Xplained board controller board. +#define MEGA1284P_XPLAINED_BC 23 //!< ATmega1284P-Xplained board controller board. +#define STK600_RC044X 24 //!< STK600 with RC044X routing card board. +#define STK600_RCUC3B0 25 //!< STK600 RCUC3B0 board. +#define UC3_L0_QT600 26 //!< QT600 UC3L0 MCU board. +#define XMEGA_A3BU_XPLAINED 27 //!< ATxmega256A3BU Xplained board. +#define STK600_RC064X_LCDX 28 //!< XMEGAB3 STK600 RC064X LCDX board. +#define STK600_RC100X_LCDX 29 //!< XMEGAB1 STK600 RC100X LCDX board. +#define UC3B_BOARD_CONTROLLER 30 //!< AT32UC3B1 board controller for Atmel boards. +#define RZ600 31 //!< AT32UC3A RZ600 MCU board. +#define SAM3S_EK 32 //!< SAM3S-EK board. +#define SAM3U_EK 33 //!< SAM3U-EK board. +#define SAM3X_EK 34 //!< SAM3X-EK board. +#define SAM3N_EK 35 //!< SAM3N-EK board. +#define SAM3S_EK2 36 //!< SAM3S-EK2 board. +#define SAM4S_EK 37 //!< SAM4S-EK board. +#define STK600_RCUC3A0 38 //!< STK600 RCUC3A0 board. +#define STK600_MEGA 39 //!< STK600 MEGA board. +#define MEGA_1284P_XPLAINED 40 //!< ATmega1284P Xplained board. +#define SAM4S_XPLAINED 41 //!< SAM4S Xplained board. +#define ATXMEGA128A1_QT600 42 //!< QT600 ATXMEGA128A1 MCU board. +#define ARDUINO_DUE_X 43 //!< Arduino Due/X board. +#define STK600_RCUC3L3 44 //!< ATUCL3 STK600 board. +#define SAM4L_EK 45 //!< SAM4L-EK board. +#define STK600_MEGA_RF 46 //!< STK600 MEGA RF EVK board. +#define XMEGA_C3_XPLAINED 47 //!< ATxmega384C3 Xplained board. +#define STK600_RC032X 48 //!< STK600 with RC032X routing card board. +#define SAM4S_EK2 49 //!< SAM4S-EK2 board. +#define XMEGA_E5_XPLAINED 50 //!< ATxmega32E5 Xplained board. +#define SAM4E_EK 51 //!< SAM4E-EK board. +#define ATMEGA256RFR2_XPLAINED_PRO 52 //!< ATmega256RFR2 Xplained Pro board. +#define SAM4S_XPLAINED_PRO 53 //!< SAM4S Xplained Pro board. +#define SAM4L_XPLAINED_PRO 54 //!< SAM4L Xplained Pro board. +#define ATMEGA256RFR2_ZIGBIT 55 //!< ATmega256RFR2 zigbit. +#define XMEGA_RF233_ZIGBIT 56 //!< ATxmega256A3U with AT86RF233 Zigbit. +#define XMEGA_RF212B_ZIGBIT 57 //!< ATxmega256A3U with AT86RF212B Zigbit. +#define SAM4S_WPIR_RD 58 //!< SAM4S-WPIR-RD board. +#define SAMD20_XPLAINED_PRO 59 //!< SAM D20 Xplained Pro board. +#define SAM4L8_XPLAINED_PRO 60 //!< SAM4L8 Xplained Pro board. +#define SAM4N_XPLAINED_PRO 61 //!< SAM4N Xplained Pro board. +#define XMEGA_A3_REB_CBB 62 //!< XMEGA REB Controller Base board. +#define ATMEGARFX_RCB 63 //!< RFR2 & RFA1 RCB. +#define SAM4C_EK 64 //!< SAM4C-EK board. +#define RCB256RFR2_XPRO 65 //!< RFR2 RCB Xplained Pro board. +#define SAMG53_XPLAINED_PRO 66 //!< SAMG53 Xplained Pro board. +#define SAM4CP16BMB 67 //!< SAM4CP16BMB board. +#define SAM4E_XPLAINED_PRO 68 //!< SAM4E Xplained Pro board. +#define SAMD21_XPLAINED_PRO 69 //!< SAM D21 Xplained Pro board. +#define SAMR21_XPLAINED_PRO 70 //!< SAM R21 Xplained Pro board. +#define SAM4CMP_DB 71 //!< SAM4CMP demo board. +#define SAM4CMS_DB 72 //!< SAM4CMS demo board. +#define ATPL230AMB 73 //!< ATPL230AMB board. +#define SAMD11_XPLAINED_PRO 74 //!< SAM D11 Xplained Pro board. +#define SAMG55_XPLAINED_PRO 75 //!< SAMG55 Xplained Pro board. +#define SAML21_XPLAINED_PRO 76 //!< SAM L21 Xplained Pro board. +#define SAMD10_XPLAINED_MINI 77 //!< SAM D10 Xplained Mini board. +#define SAMDA1_XPLAINED_PRO 78 //!< SAM DA1 Xplained Pro board. +#define SAMW25_XPLAINED_PRO 79 //!< SAMW25 Xplained Pro board. +#define SAMC21_XPLAINED_PRO 80 //!< SAM C21 Xplained Pro board. +#define SAMV71_XPLAINED_ULTRA 81 //!< SAMV71 Xplained Ultra board. +#define ATMEGA328P_XPLAINED_MINI 82 //!< ATMEGA328P Xplained MINI board. +#define ATMEGA328PB_XPLAINED_MINI 83 //!< ATMEGA328PB Xplained MINI board. +#define SAMB11_XPLAINED_PRO 84 //!< SAM B11 Xplained Pro board. +#define SAME70_XPLAINED 85 //!< SAME70 Xplained board. +#define SAML22_XPLAINED_PRO 86 //!< SAM L22 Xplained Pro board. +#define SAML22_XPLAINED_PRO_B 87 //!< SAM L22 Xplained Pro board. +#define SAMR21ZLL_EK 88 //!< SAMR21ZLL-EK board. +#define ATMEGA168PB_XPLAINED_MINI 89 //!< ATMEGA168PB Xplained MINI board. +#define ATMEGA324PB_XPLAINED_PRO 90 //!< ATMEGA324PB Xplained Pro board. +#define SIMULATOR_XMEGA_A1 97 //!< Simulator for XMEGA A1 devices. +#define AVR_SIMULATOR_UC3 98 //!< Simulator for the AVR UC3 device family. +#define USER_BOARD 99 //!< User-reserved board (if any). +#define DUMMY_BOARD 100 //!< Dummy board to support board-independent applications (e.g. bootloader). +//! @} + +/*! \name Extension Boards + */ +//! @{ +#define EXT1102 1 //!< AT32UC3B EXT1102 board +#define MC300 2 //!< AT32UC3 MC300 board +#define SENSORS_XPLAINED_INERTIAL_1 3 //!< Xplained inertial sensor board 1 +#define SENSORS_XPLAINED_INERTIAL_2 4 //!< Xplained inertial sensor board 2 +#define SENSORS_XPLAINED_PRESSURE_1 5 //!< Xplained pressure sensor board +#define SENSORS_XPLAINED_LIGHTPROX_1 6 //!< Xplained light & proximity sensor board +#define SENSORS_XPLAINED_INERTIAL_A1 7 //!< Xplained inertial sensor board "A" +#define RZ600_AT86RF231 8 //!< AT86RF231 RF board in RZ600 +#define RZ600_AT86RF230B 9 //!< AT86RF230B RF board in RZ600 +#define RZ600_AT86RF212 10 //!< AT86RF212 RF board in RZ600 +#define SENSORS_XPLAINED_BREADBOARD 11 //!< Xplained sensor development breadboard +#define SECURITY_XPLAINED 12 //!< Xplained ATSHA204 board +#define USER_EXT_BOARD 99 //!< User-reserved extension board (if any). +//! @} + +#if BOARD == EVK1100 +# include "evk1100/evk1100.h" +#elif BOARD == EVK1101 +# include "evk1101/evk1101.h" +#elif BOARD == UC3C_EK +# include "uc3c_ek/uc3c_ek.h" +#elif BOARD == EVK1104 +# include "evk1104/evk1104.h" +#elif BOARD == EVK1105 +# include "evk1105/evk1105.h" +#elif BOARD == STK600_RCUC3L0 +# include "stk600/rcuc3l0/stk600_rcuc3l0.h" +#elif BOARD == UC3L_EK +# include "uc3l_ek/uc3l_ek.h" +#elif BOARD == STK600_RCUC3L4 +# include "stk600/rcuc3l4/stk600_rcuc3l4.h" +#elif BOARD == XPLAIN +# include "xplain/xplain.h" +#elif BOARD == STK600_MEGA + /*No header-file to include*/ +#elif BOARD == STK600_MEGA_RF +# include "stk600.h" +#elif BOARD == ATMEGA256RFR2_XPLAINED_PRO +# include "atmega256rfr2_xplained_pro/atmega256rfr2_xplained_pro.h" +#elif BOARD == ATMEGA256RFR2_ZIGBIT +# include "atmega256rfr2_zigbit/atmega256rfr2_zigbit.h" +#elif BOARD == STK600_RC032X +# include "stk600/rc032x/stk600_rc032x.h" +#elif BOARD == STK600_RC044X +# include "stk600/rc044x/stk600_rc044x.h" +#elif BOARD == STK600_RC064X +# include "stk600/rc064x/stk600_rc064x.h" +#elif BOARD == STK600_RC100X +# include "stk600/rc100x/stk600_rc100x.h" +#elif BOARD == UC3_A3_XPLAINED +# include "uc3_a3_xplained/uc3_a3_xplained.h" +#elif BOARD == UC3_L0_XPLAINED +# include "uc3_l0_xplained/uc3_l0_xplained.h" +#elif BOARD == STK600_RCUC3B0 +# include "stk600/rcuc3b0/stk600_rcuc3b0.h" +#elif BOARD == STK600_RCUC3D +# include "stk600/rcuc3d/stk600_rcuc3d.h" +#elif BOARD == STK600_RCUC3C0 +# include "stk600/rcuc3c0/stk600_rcuc3c0.h" +#elif BOARD == SAMG53_XPLAINED_PRO +# include "samg53_xplained_pro/samg53_xplained_pro.h" +#elif BOARD == SAMG55_XPLAINED_PRO +# include "samg55_xplained_pro/samg55_xplained_pro.h" +#elif BOARD == XMEGA_B1_XPLAINED +# include "xmega_b1_xplained/xmega_b1_xplained.h" +#elif BOARD == STK600_RC064X_LCDX +# include "stk600/rc064x_lcdx/stk600_rc064x_lcdx.h" +#elif BOARD == STK600_RC100X_LCDX +# include "stk600/rc100x_lcdx/stk600_rc100x_lcdx.h" +#elif BOARD == XMEGA_A1_XPLAINED +# include "xmega_a1_xplained/xmega_a1_xplained.h" +#elif BOARD == XMEGA_A1U_XPLAINED_PRO +# include "xmega_a1u_xplained_pro/xmega_a1u_xplained_pro.h" +#elif BOARD == UC3_L0_XPLAINED_BC +# include "uc3_l0_xplained_bc/uc3_l0_xplained_bc.h" +#elif BOARD == SAM3S_EK +# include "sam3s_ek/sam3s_ek.h" +# include "system_sam3s.h" +#elif BOARD == SAM3S_EK2 +# include "sam3s_ek2/sam3s_ek2.h" +# include "system_sam3sd8.h" +#elif BOARD == SAM3U_EK +# include "sam3u_ek/sam3u_ek.h" +# include "system_sam3u.h" +#elif BOARD == SAM3X_EK +# include "sam3x_ek/sam3x_ek.h" +# include "system_sam3x.h" +#elif BOARD == SAM3N_EK +# include "sam3n_ek/sam3n_ek.h" +# include "system_sam3n.h" +#elif BOARD == SAM4S_EK +# include "sam4s_ek/sam4s_ek.h" +# include "system_sam4s.h" +#elif BOARD == SAM4S_WPIR_RD +# include "sam4s_wpir_rd/sam4s_wpir_rd.h" +# include "system_sam4s.h" +#elif BOARD == SAM4S_XPLAINED +# include "sam4s_xplained/sam4s_xplained.h" +# include "system_sam4s.h" +#elif BOARD == SAM4S_EK2 +# include "sam4s_ek2/sam4s_ek2.h" +# include "system_sam4s.h" +#elif BOARD == MEGA_1284P_XPLAINED + /*No header-file to include*/ +#elif BOARD == ARDUINO_DUE_X +# include "arduino_due_x/arduino_due_x.h" +# include "system_sam3x.h" +#elif BOARD == SAM4L_EK +# include "sam4l_ek/sam4l_ek.h" +#elif BOARD == SAM4E_EK +# include "sam4e_ek/sam4e_ek.h" +#elif BOARD == SAMD20_XPLAINED_PRO +# include "samd20_xplained_pro/samd20_xplained_pro.h" +#elif BOARD == SAMD21_XPLAINED_PRO +# include "samd21_xplained_pro/samd21_xplained_pro.h" +#elif BOARD == SAMR21_XPLAINED_PRO +# include "samr21_xplained_pro/samr21_xplained_pro.h" +#elif BOARD == SAMR21ZLL_EK +# include "samr21zll_ek/samr21zll_ek.h" +#elif BOARD == SAMD11_XPLAINED_PRO +# include "samd11_xplained_pro/samd11_xplained_pro.h" +#elif BOARD == SAML21_XPLAINED_PRO && defined(__SAML21J18A__) +# include "saml21_xplained_pro/saml21_xplained_pro.h" +#elif BOARD == SAML22_XPLAINED_PRO +# include "saml22_xplained_pro/saml22_xplained_pro.h" +#elif BOARD == SAML22_XPLAINED_PRO_B +# include "saml22_xplained_pro_b/saml22_xplained_pro_b.h" +#elif BOARD == SAML21_XPLAINED_PRO && defined(__SAML21J18B__) +# include "saml21_xplained_pro_b/saml21_xplained_pro.h" +#elif BOARD == SAMD10_XPLAINED_MINI +# include "samd10_xplained_mini/samd10_xplained_mini.h" +#elif BOARD == SAMDA1_XPLAINED_PRO +# include "samda1_xplained_pro/samda1_xplained_pro.h" +#elif BOARD == SAMC21_XPLAINED_PRO +# include "samc21_xplained_pro/samc21_xplained_pro.h" +#elif BOARD == SAM4N_XPLAINED_PRO +# include "sam4n_xplained_pro/sam4n_xplained_pro.h" +#elif BOARD == SAMW25_XPLAINED_PRO +# include "samw25_xplained_pro/samw25_xplained_pro.h" +#elif BOARD == SAMV71_XPLAINED_ULTRA +# include "samv71_xplained_ultra/samv71_xplained_ultra.h" +#elif BOARD == MEGA1284P_XPLAINED_BC +# include "mega1284p_xplained_bc/mega1284p_xplained_bc.h" +#elif BOARD == UC3_L0_QT600 +# include "uc3_l0_qt600/uc3_l0_qt600.h" +#elif BOARD == XMEGA_A3BU_XPLAINED +# include "xmega_a3bu_xplained/xmega_a3bu_xplained.h" +#elif BOARD == XMEGA_E5_XPLAINED +# include "xmega_e5_xplained/xmega_e5_xplained.h" +#elif BOARD == UC3B_BOARD_CONTROLLER +# include "uc3b_board_controller/uc3b_board_controller.h" +#elif BOARD == RZ600 +# include "rz600/rz600.h" +#elif BOARD == STK600_RCUC3A0 +# include "stk600/rcuc3a0/stk600_rcuc3a0.h" +#elif BOARD == ATXMEGA128A1_QT600 +# include "atxmega128a1_qt600/atxmega128a1_qt600.h" +#elif BOARD == STK600_RCUC3L3 +# include "stk600/rcuc3l3/stk600_rcuc3l3.h" +#elif BOARD == SAM4S_XPLAINED_PRO +# include "sam4s_xplained_pro/sam4s_xplained_pro.h" +#elif BOARD == SAM4L_XPLAINED_PRO +# include "sam4l_xplained_pro/sam4l_xplained_pro.h" +#elif BOARD == SAM4L8_XPLAINED_PRO +# include "sam4l8_xplained_pro/sam4l8_xplained_pro.h" +#elif BOARD == SAM4C_EK +# include "sam4c_ek/sam4c_ek.h" +#elif BOARD == SAM4CMP_DB +# include "sam4cmp_db/sam4cmp_db.h" +#elif BOARD == SAM4CMS_DB +# include "sam4cms_db/sam4cms_db.h" +#elif BOARD == SAM4CP16BMB +# include "sam4cp16bmb/sam4cp16bmb.h" +#elif BOARD == ATPL230AMB +# include "atpl230amb/atpl230amb.h" +#elif BOARD == XMEGA_C3_XPLAINED +# include "xmega_c3_xplained/xmega_c3_xplained.h" +#elif BOARD == XMEGA_RF233_ZIGBIT +# include "xmega_rf233_zigbit/xmega_rf233_zigbit.h" +#elif BOARD == XMEGA_A3_REB_CBB +# include "xmega_a3_reb_cbb/xmega_a3_reb_cbb.h" +#elif BOARD == ATMEGARFX_RCB +# include "atmegarfx_rcb/atmegarfx_rcb.h" +#elif BOARD == RCB256RFR2_XPRO +# include "atmega256rfr2_rcb_xpro/atmega256rfr2_rcb_xpro.h" +#elif BOARD == XMEGA_RF212B_ZIGBIT +# include "xmega_rf212b_zigbit/xmega_rf212b_zigbit.h" +#elif BOARD == SAM4E_XPLAINED_PRO +# include "sam4e_xplained_pro/sam4e_xplained_pro.h" +#elif BOARD == ATMEGA328P_XPLAINED_MINI +# include "atmega328p_xplained_mini/atmega328p_xplained_mini.h" +#elif BOARD == ATMEGA328PB_XPLAINED_MINI +# include "atmega328pb_xplained_mini/atmega328pb_xplained_mini.h" +#elif BOARD == SAMB11_XPLAINED_PRO +# include "samb11_xplained_pro/samb11_xplained_pro.h" +#elif BOARD == SAME70_XPLAINED +# include "same70_xplained/same70_xplained.h" +#elif BOARD == ATMEGA168PB_XPLAINED_MINI +# include "atmega168pb_xplained_mini/atmega168pb_xplained_mini.h" +#elif BOARD == ATMEGA324PB_XPLAINED_PRO +# include "atmega324pb_xplained_pro/atmega324pb_xplained_pro.h" +#elif BOARD == SIMULATOR_XMEGA_A1 +# include "simulator/xmega_a1/simulator_xmega_a1.h" +#elif BOARD == AVR_SIMULATOR_UC3 +# include "avr_simulator_uc3/avr_simulator_uc3.h" +#elif BOARD == USER_BOARD + // User-reserved area: #include the header file of your board here (if any). +# include "user_board.h" +#elif BOARD == DUMMY_BOARD +# include "dummy/dummy_board.h" +#else +# error No known Atmel board defined +#endif + +#if (defined EXT_BOARD) +# if EXT_BOARD == MC300 +# include "mc300/mc300.h" +# elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_1) || \ + (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_2) || \ + (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_A1) || \ + (EXT_BOARD == SENSORS_XPLAINED_PRESSURE_1) || \ + (EXT_BOARD == SENSORS_XPLAINED_LIGHTPROX_1) || \ + (EXT_BOARD == SENSORS_XPLAINED_BREADBOARD) +# include "sensors_xplained/sensors_xplained.h" +# elif EXT_BOARD == RZ600_AT86RF231 +# include "at86rf231/at86rf231.h" +# elif EXT_BOARD == RZ600_AT86RF230B +# include "at86rf230b/at86rf230b.h" +# elif EXT_BOARD == RZ600_AT86RF212 +# include "at86rf212/at86rf212.h" +# elif EXT_BOARD == SECURITY_XPLAINED +# include "security_xplained.h" +# elif EXT_BOARD == USER_EXT_BOARD + // User-reserved area: #include the header file of your extension board here + // (if any). +# endif +#endif + + +#if (defined(__GNUC__) && defined(__AVR32__)) || (defined(__ICCAVR32__) || defined(__AAVR32__)) +#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling. + +/*! \brief This function initializes the board target resources + * + * This function should be called to ensure proper initialization of the target + * board hardware connected to the part. + */ +extern void board_init(void); + +#endif // #ifdef __AVR32_ABI_COMPILER__ +#else +/*! \brief This function initializes the board target resources + * + * This function should be called to ensure proper initialization of the target + * board hardware connected to the part. + */ +extern void board_init(void); +#endif + + +#ifdef __cplusplus +} +#endif + +/** + * \} + */ + +#endif // _BOARD_H_ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/clock/genclk.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/clock/genclk.h new file mode 100644 index 0000000..503a50a --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/clock/genclk.h @@ -0,0 +1,199 @@ +/** + * \file + * + * \brief Generic clock management + * + * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#ifndef CLK_GENCLK_H_INCLUDED +#define CLK_GENCLK_H_INCLUDED + +#include "parts.h" + +#if SAM3S +# include "sam3s/genclk.h" +#elif SAM3U +# include "sam3u/genclk.h" +#elif SAM3N +# include "sam3n/genclk.h" +#elif SAM3XA +# include "sam3x/genclk.h" +#elif SAM4S +# include "sam4s/genclk.h" +#elif SAM4L +# include "sam4l/genclk.h" +#elif SAM4E +# include "sam4e/genclk.h" +#elif SAM4N +# include "sam4n/genclk.h" +#elif SAM4C +# include "sam4c/genclk.h" +#elif SAM4CM +# include "sam4cm/genclk.h" +#elif SAM4CP +# include "sam4cp/genclk.h" +#elif SAMG +# include "samg/genclk.h" +#elif SAMV71 +# include "samv71/genclk.h" +#elif SAMV70 +# include "samv70/genclk.h" +#elif SAME70 +# include "same70/genclk.h" +#elif SAMS70 +# include "sams70/genclk.h" +#elif (UC3A0 || UC3A1) +# include "uc3a0_a1/genclk.h" +#elif UC3A3 +# include "uc3a3_a4/genclk.h" +#elif UC3B +# include "uc3b0_b1/genclk.h" +#elif UC3C +# include "uc3c/genclk.h" +#elif UC3D +# include "uc3d/genclk.h" +#elif UC3L +# include "uc3l/genclk.h" +#else +# error Unsupported chip type +#endif + +/** + * \ingroup clk_group + * \defgroup genclk_group Generic Clock Management + * + * Generic clocks are configurable clocks which run outside the system + * clock domain. They are often connected to peripherals which have an + * asynchronous component running independently of the bus clock, e.g. + * USB controllers, low-power timers and RTCs, etc. + * + * Note that not all platforms have support for generic clocks; on such + * platforms, this API will not be available. + * + * @{ + */ + +/** + * \def GENCLK_DIV_MAX + * \brief Maximum divider supported by the generic clock implementation + */ +/** + * \enum genclk_source + * \brief Generic clock source ID + * + * Each generic clock may be generated from a different clock source. + * These are the available alternatives provided by the chip. + */ + +//! \name Generic clock configuration +//@{ +/** + * \struct genclk_config + * \brief Hardware representation of a set of generic clock parameters + */ +/** + * \fn void genclk_config_defaults(struct genclk_config *cfg, + * unsigned int id) + * \brief Initialize \a cfg to the default configuration for the clock + * identified by \a id. + */ +/** + * \fn void genclk_config_read(struct genclk_config *cfg, unsigned int id) + * \brief Read the currently active configuration of the clock + * identified by \a id into \a cfg. + */ +/** + * \fn void genclk_config_write(const struct genclk_config *cfg, + * unsigned int id) + * \brief Activate the configuration \a cfg on the clock identified by + * \a id. + */ +/** + * \fn void genclk_config_set_source(struct genclk_config *cfg, + * enum genclk_source src) + * \brief Select a new source clock \a src in configuration \a cfg. + */ +/** + * \fn void genclk_config_set_divider(struct genclk_config *cfg, + * unsigned int divider) + * \brief Set a new \a divider in configuration \a cfg. + */ +/** + * \fn void genclk_enable_source(enum genclk_source src) + * \brief Enable the source clock \a src used by a generic clock. + */ + //@} + +//! \name Enabling and disabling Generic Clocks +//@{ +/** + * \fn void genclk_enable(const struct genclk_config *cfg, unsigned int id) + * \brief Activate the configuration \a cfg on the clock identified by + * \a id and enable it. + */ +/** + * \fn void genclk_disable(unsigned int id) + * \brief Disable the generic clock identified by \a id. + */ +//@} + +/** + * \brief Enable the configuration defined by \a src and \a divider + * for the generic clock identified by \a id. + * + * \param id The ID of the generic clock. + * \param src The source clock of the generic clock. + * \param divider The divider used to generate the generic clock. + */ +static inline void genclk_enable_config(unsigned int id, enum genclk_source src, unsigned int divider) +{ + struct genclk_config gcfg; + + genclk_config_defaults(&gcfg, id); + genclk_enable_source(src); + genclk_config_set_source(&gcfg, src); + genclk_config_set_divider(&gcfg, divider); + genclk_enable(&gcfg, id); +} + +//! @} + +#endif /* CLK_GENCLK_H_INCLUDED */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/clock/osc.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/clock/osc.h new file mode 100644 index 0000000..e67f01f --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/clock/osc.h @@ -0,0 +1,185 @@ +/** + * \file + * + * \brief Oscillator management + * + * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#ifndef OSC_H_INCLUDED +#define OSC_H_INCLUDED + +#include "parts.h" +#include "conf_clock.h" + +#if SAM3S +# include "sam3s/osc.h" +#elif SAM3XA +# include "sam3x/osc.h" +#elif SAM3U +# include "sam3u/osc.h" +#elif SAM3N +# include "sam3n/osc.h" +#elif SAM4S +# include "sam4s/osc.h" +#elif SAM4E +# include "sam4e/osc.h" +#elif SAM4C +# include "sam4c/osc.h" +#elif SAM4CM +# include "sam4cm/osc.h" +#elif SAM4CP +# include "sam4cp/osc.h" +#elif SAM4L +# include "sam4l/osc.h" +#elif SAM4N +# include "sam4n/osc.h" +#elif SAMG +# include "samg/osc.h" +#elif SAMV71 +# include "samv71/osc.h" +#elif SAMV70 +# include "samv70/osc.h" +#elif SAME70 +# include "same70/osc.h" +#elif SAMS70 +# include "sams70/osc.h" +#elif (UC3A0 || UC3A1) +# include "uc3a0_a1/osc.h" +#elif UC3A3 +# include "uc3a3_a4/osc.h" +#elif UC3B +# include "uc3b0_b1/osc.h" +#elif UC3C +# include "uc3c/osc.h" +#elif UC3D +# include "uc3d/osc.h" +#elif UC3L +# include "uc3l/osc.h" +#elif XMEGA +# include "xmega/osc.h" +#else +# error Unsupported chip type +#endif + +/** + * \ingroup clk_group + * \defgroup osc_group Oscillator Management + * + * This group contains functions and definitions related to configuring + * and enabling/disabling on-chip oscillators. Internal RC-oscillators, + * external crystal oscillators and external clock generators are + * supported by this module. What all of these have in common is that + * they swing at a fixed, nominal frequency which is normally not + * adjustable. + * + * \par Example: Enabling an oscillator + * + * The following example demonstrates how to enable the external + * oscillator on XMEGA A and wait for it to be ready to use. The + * oscillator identifiers are platform-specific, so while the same + * procedure is used on all platforms, the parameter to osc_enable() + * will be different from device to device. + * \code + osc_enable(OSC_ID_XOSC); + osc_wait_ready(OSC_ID_XOSC); \endcode + * + * \section osc_group_board Board-specific Definitions + * If external oscillators are used, the board code must provide the + * following definitions for each of those: + * - \b BOARD__HZ: The nominal frequency of the oscillator. + * - \b BOARD__STARTUP_US: The startup time of the + * oscillator in microseconds. + * - \b BOARD__TYPE: The type of oscillator connected, i.e. + * whether it's a crystal or external clock, and sometimes what kind + * of crystal it is. The meaning of this value is platform-specific. + * + * @{ + */ + +//! \name Oscillator Management +//@{ +/** + * \fn void osc_enable(uint8_t id) + * \brief Enable oscillator \a id + * + * The startup time and mode value is automatically determined based on + * definitions in the board code. + */ +/** + * \fn void osc_disable(uint8_t id) + * \brief Disable oscillator \a id + */ +/** + * \fn osc_is_ready(uint8_t id) + * \brief Determine whether oscillator \a id is ready. + * \retval true Oscillator \a id is running and ready to use as a clock + * source. + * \retval false Oscillator \a id is not running. + */ +/** + * \fn uint32_t osc_get_rate(uint8_t id) + * \brief Return the frequency of oscillator \a id in Hz + */ + +#ifndef __ASSEMBLY__ + +/** + * \brief Wait until the oscillator identified by \a id is ready + * + * This function will busy-wait for the oscillator identified by \a id + * to become stable and ready to use as a clock source. + * + * \param id A number identifying the oscillator to wait for. + */ +static inline void osc_wait_ready(uint8_t id) +{ + while (!osc_is_ready(id)) { + /* Do nothing */ + } +} + +#endif /* __ASSEMBLY__ */ + +//@} + +//! @} + +#endif /* OSC_H_INCLUDED */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/clock/pll.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/clock/pll.h new file mode 100644 index 0000000..23e930c --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/clock/pll.h @@ -0,0 +1,341 @@ +/** + * \file + * + * \brief PLL management + * + * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#ifndef CLK_PLL_H_INCLUDED +#define CLK_PLL_H_INCLUDED + +#include "parts.h" +#include "conf_clock.h" + +#if SAM3S +# include "sam3s/pll.h" +#elif SAM3XA +# include "sam3x/pll.h" +#elif SAM3U +# include "sam3u/pll.h" +#elif SAM3N +# include "sam3n/pll.h" +#elif SAM4S +# include "sam4s/pll.h" +#elif SAM4E +# include "sam4e/pll.h" +#elif SAM4C +# include "sam4c/pll.h" +#elif SAM4CM +# include "sam4cm/pll.h" +#elif SAM4CP +# include "sam4cp/pll.h" +#elif SAM4L +# include "sam4l/pll.h" +#elif SAM4N +# include "sam4n/pll.h" +#elif SAMG +# include "samg/pll.h" +#elif SAMV71 +# include "samv71/pll.h" +#elif SAMV70 +# include "samv70/pll.h" +#elif SAME70 +# include "same70/pll.h" +#elif SAMS70 +# include "sams70/pll.h" +#elif (UC3A0 || UC3A1) +# include "uc3a0_a1/pll.h" +#elif UC3A3 +# include "uc3a3_a4/pll.h" +#elif UC3B +# include "uc3b0_b1/pll.h" +#elif UC3C +# include "uc3c/pll.h" +#elif UC3D +# include "uc3d/pll.h" +#elif (UC3L0128 || UC3L0256 || UC3L3_L4) +# include "uc3l/pll.h" +#elif XMEGA +# include "xmega/pll.h" +#else +# error Unsupported chip type +#endif + +/** + * \ingroup clk_group + * \defgroup pll_group PLL Management + * + * This group contains functions and definitions related to configuring + * and enabling/disabling on-chip PLLs. A PLL will take an input signal + * (the \em source), optionally divide the frequency by a configurable + * \em divider, and then multiply the frequency by a configurable \em + * multiplier. + * + * Some devices don't support input dividers; specifying any other + * divisor than 1 on these devices will result in an assertion failure. + * Other devices may have various restrictions to the frequency range of + * the input and output signals. + * + * \par Example: Setting up PLL0 with default parameters + * + * The following example shows how to configure and enable PLL0 using + * the default parameters specified using the configuration symbols + * listed above. + * \code + pll_enable_config_defaults(0); \endcode + * + * To configure, enable PLL0 using the default parameters and to disable + * a specific feature like Wide Bandwidth Mode (a UC3A3-specific + * PLL option.), you can use this initialization process. + * \code + struct pll_config pllcfg; + if (pll_is_locked(pll_id)) { + return; // Pll already running + } + pll_enable_source(CONFIG_PLL0_SOURCE); + pll_config_defaults(&pllcfg, 0); + pll_config_set_option(&pllcfg, PLL_OPT_WBM_DISABLE); + pll_enable(&pllcfg, 0); + pll_wait_for_lock(0); \endcode + * + * When the last function call returns, PLL0 is ready to be used as the + * main system clock source. + * + * \section pll_group_config Configuration Symbols + * + * Each PLL has a set of default parameters determined by the following + * configuration symbols in the application's configuration file: + * - \b CONFIG_PLLn_SOURCE: The default clock source connected to the + * input of PLL \a n. Must be one of the values defined by the + * #pll_source enum. + * - \b CONFIG_PLLn_MUL: The default multiplier (loop divider) of PLL + * \a n. + * - \b CONFIG_PLLn_DIV: The default input divider of PLL \a n. + * + * These configuration symbols determine the result of calling + * pll_config_defaults() and pll_get_default_rate(). + * + * @{ + */ + +//! \name Chip-specific PLL characteristics +//@{ +/** + * \def PLL_MAX_STARTUP_CYCLES + * \brief Maximum PLL startup time in number of slow clock cycles + */ +/** + * \def NR_PLLS + * \brief Number of on-chip PLLs + */ + +/** + * \def PLL_MIN_HZ + * \brief Minimum frequency that the PLL can generate + */ +/** + * \def PLL_MAX_HZ + * \brief Maximum frequency that the PLL can generate + */ +/** + * \def PLL_NR_OPTIONS + * \brief Number of PLL option bits + */ +//@} + +/** + * \enum pll_source + * \brief PLL clock source + */ + +//! \name PLL configuration +//@{ + +/** + * \struct pll_config + * \brief Hardware-specific representation of PLL configuration. + * + * This structure contains one or more device-specific values + * representing the current PLL configuration. The contents of this + * structure is typically different from platform to platform, and the + * user should not access any fields except through the PLL + * configuration API. + */ + +/** + * \fn void pll_config_init(struct pll_config *cfg, + * enum pll_source src, unsigned int div, unsigned int mul) + * \brief Initialize PLL configuration from standard parameters. + * + * \note This function may be defined inline because it is assumed to be + * called very few times, and usually with constant parameters. Inlining + * it will in such cases reduce the code size significantly. + * + * \param cfg The PLL configuration to be initialized. + * \param src The oscillator to be used as input to the PLL. + * \param div PLL input divider. + * \param mul PLL loop divider (i.e. multiplier). + * + * \return A configuration which will make the PLL run at + * (\a mul / \a div) times the frequency of \a src + */ +/** + * \def pll_config_defaults(cfg, pll_id) + * \brief Initialize PLL configuration using default parameters. + * + * After this function returns, \a cfg will contain a configuration + * which will make the PLL run at (CONFIG_PLLx_MUL / CONFIG_PLLx_DIV) + * times the frequency of CONFIG_PLLx_SOURCE. + * + * \param cfg The PLL configuration to be initialized. + * \param pll_id Use defaults for this PLL. + */ +/** + * \def pll_get_default_rate(pll_id) + * \brief Get the default rate in Hz of \a pll_id + */ +/** + * \fn void pll_config_set_option(struct pll_config *cfg, + * unsigned int option) + * \brief Set the PLL option bit \a option in the configuration \a cfg. + * + * \param cfg The PLL configuration to be changed. + * \param option The PLL option bit to be set. + */ +/** + * \fn void pll_config_clear_option(struct pll_config *cfg, + * unsigned int option) + * \brief Clear the PLL option bit \a option in the configuration \a cfg. + * + * \param cfg The PLL configuration to be changed. + * \param option The PLL option bit to be cleared. + */ +/** + * \fn void pll_config_read(struct pll_config *cfg, unsigned int pll_id) + * \brief Read the currently active configuration of \a pll_id. + * + * \param cfg The configuration object into which to store the currently + * active configuration. + * \param pll_id The ID of the PLL to be accessed. + */ +/** + * \fn void pll_config_write(const struct pll_config *cfg, + * unsigned int pll_id) + * \brief Activate the configuration \a cfg on \a pll_id + * + * \param cfg The configuration object representing the PLL + * configuration to be activated. + * \param pll_id The ID of the PLL to be updated. + */ + +//@} + +//! \name Interaction with the PLL hardware +//@{ +/** + * \fn void pll_enable(const struct pll_config *cfg, + * unsigned int pll_id) + * \brief Activate the configuration \a cfg and enable PLL \a pll_id. + * + * \param cfg The PLL configuration to be activated. + * \param pll_id The ID of the PLL to be enabled. + */ +/** + * \fn void pll_disable(unsigned int pll_id) + * \brief Disable the PLL identified by \a pll_id. + * + * After this function is called, the PLL identified by \a pll_id will + * be disabled. The PLL configuration stored in hardware may be affected + * by this, so if the caller needs to restore the same configuration + * later, it should either do a pll_config_read() before disabling the + * PLL, or remember the last configuration written to the PLL. + * + * \param pll_id The ID of the PLL to be disabled. + */ +/** + * \fn bool pll_is_locked(unsigned int pll_id) + * \brief Determine whether the PLL is locked or not. + * + * \param pll_id The ID of the PLL to check. + * + * \retval true The PLL is locked and ready to use as a clock source + * \retval false The PLL is not yet locked, or has not been enabled. + */ +/** + * \fn void pll_enable_source(enum pll_source src) + * \brief Enable the source of the pll. + * The source is enabled, if the source is not already running. + * + * \param src The ID of the PLL source to enable. + */ +/** + * \fn void pll_enable_config_defaults(unsigned int pll_id) + * \brief Enable the pll with the default configuration. + * PLL is enabled, if the PLL is not already locked. + * + * \param pll_id The ID of the PLL to enable. + */ + +/** + * \brief Wait for PLL \a pll_id to become locked + * + * \todo Use a timeout to avoid waiting forever and hanging the system + * + * \param pll_id The ID of the PLL to wait for. + * + * \retval STATUS_OK The PLL is now locked. + * \retval ERR_TIMEOUT Timed out waiting for PLL to become locked. + */ +static inline int pll_wait_for_lock(unsigned int pll_id) +{ + Assert(pll_id < NR_PLLS); + + while (!pll_is_locked(pll_id)) { + /* Do nothing */ + } + + return 0; +} + +//@} +//! @} + +#endif /* CLK_PLL_H_INCLUDED */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/clock/sam3x/genclk.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/clock/sam3x/genclk.h new file mode 100644 index 0000000..895aba0 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/clock/sam3x/genclk.h @@ -0,0 +1,278 @@ +/** + * \file + * + * \brief Chip-specific generic clock management. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef CHIP_GENCLK_H_INCLUDED +#define CHIP_GENCLK_H_INCLUDED + +#include +#include + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \weakgroup genclk_group + * @{ + */ + +//! \name Programmable Clock Identifiers (PCK) +//@{ +#define GENCLK_PCK_0 0 //!< PCK0 ID +#define GENCLK_PCK_1 1 //!< PCK1 ID +#define GENCLK_PCK_2 2 //!< PCK2 ID +//@} + +//! \name Programmable Clock Sources (PCK) +//@{ + +enum genclk_source { + GENCLK_PCK_SRC_SLCK_RC = 0, //!< Internal 32kHz RC oscillator as PCK source clock + GENCLK_PCK_SRC_SLCK_XTAL = 1, //!< External 32kHz crystal oscillator as PCK source clock + GENCLK_PCK_SRC_SLCK_BYPASS = 2, //!< External 32kHz bypass oscillator as PCK source clock + GENCLK_PCK_SRC_MAINCK_4M_RC = 3, //!< Internal 4MHz RC oscillator as PCK source clock + GENCLK_PCK_SRC_MAINCK_8M_RC = 4, //!< Internal 8MHz RC oscillator as PCK source clock + GENCLK_PCK_SRC_MAINCK_12M_RC = 5, //!< Internal 12MHz RC oscillator as PCK source clock + GENCLK_PCK_SRC_MAINCK_XTAL = 6, //!< External crystal oscillator as PCK source clock + GENCLK_PCK_SRC_MAINCK_BYPASS = 7, //!< External bypass oscillator as PCK source clock + GENCLK_PCK_SRC_PLLACK = 8, //!< Use PLLACK as PCK source clock + GENCLK_PCK_SRC_PLLBCK = 9, //!< Use PLLBCK as PCK source clock + GENCLK_PCK_SRC_MCK = 10, //!< Use Master Clk as PCK source clock +}; + +//@} + +//! \name Programmable Clock Prescalers (PCK) +//@{ + +enum genclk_divider { + GENCLK_PCK_PRES_1 = PMC_PCK_PRES_CLK_1, //!< Set PCK clock prescaler to 1 + GENCLK_PCK_PRES_2 = PMC_PCK_PRES_CLK_2, //!< Set PCK clock prescaler to 2 + GENCLK_PCK_PRES_4 = PMC_PCK_PRES_CLK_4, //!< Set PCK clock prescaler to 4 + GENCLK_PCK_PRES_8 = PMC_PCK_PRES_CLK_8, //!< Set PCK clock prescaler to 8 + GENCLK_PCK_PRES_16 = PMC_PCK_PRES_CLK_16, //!< Set PCK clock prescaler to 16 + GENCLK_PCK_PRES_32 = PMC_PCK_PRES_CLK_32, //!< Set PCK clock prescaler to 32 + GENCLK_PCK_PRES_64 = PMC_PCK_PRES_CLK_64, //!< Set PCK clock prescaler to 64 +}; + +//@} + +struct genclk_config { + uint32_t ctrl; +}; + +static inline void genclk_config_defaults(struct genclk_config *p_cfg, + uint32_t ul_id) +{ + ul_id = ul_id; + p_cfg->ctrl = 0; +} + +static inline void genclk_config_read(struct genclk_config *p_cfg, + uint32_t ul_id) +{ + p_cfg->ctrl = PMC->PMC_PCK[ul_id]; +} + +static inline void genclk_config_write(const struct genclk_config *p_cfg, + uint32_t ul_id) +{ + PMC->PMC_PCK[ul_id] = p_cfg->ctrl; +} + +//! \name Programmable Clock Source and Prescaler configuration +//@{ + +static inline void genclk_config_set_source(struct genclk_config *p_cfg, + enum genclk_source e_src) +{ + p_cfg->ctrl &= (~PMC_PCK_CSS_Msk); + + switch (e_src) { + case GENCLK_PCK_SRC_SLCK_RC: + case GENCLK_PCK_SRC_SLCK_XTAL: + case GENCLK_PCK_SRC_SLCK_BYPASS: + p_cfg->ctrl |= (PMC_PCK_CSS_SLOW_CLK); + break; + + case GENCLK_PCK_SRC_MAINCK_4M_RC: + case GENCLK_PCK_SRC_MAINCK_8M_RC: + case GENCLK_PCK_SRC_MAINCK_12M_RC: + case GENCLK_PCK_SRC_MAINCK_XTAL: + case GENCLK_PCK_SRC_MAINCK_BYPASS: + p_cfg->ctrl |= (PMC_PCK_CSS_MAIN_CLK); + break; + + case GENCLK_PCK_SRC_PLLACK: + p_cfg->ctrl |= (PMC_PCK_CSS_PLLA_CLK); + break; + + case GENCLK_PCK_SRC_PLLBCK: + p_cfg->ctrl |= (PMC_PCK_CSS_UPLL_CLK); + break; + + case GENCLK_PCK_SRC_MCK: + p_cfg->ctrl |= (PMC_PCK_CSS_MCK); + break; + } +} + +static inline void genclk_config_set_divider(struct genclk_config *p_cfg, + uint32_t e_divider) +{ + p_cfg->ctrl &= ~PMC_PCK_PRES_Msk; + p_cfg->ctrl |= e_divider; +} + +//@} + +static inline void genclk_enable(const struct genclk_config *p_cfg, + uint32_t ul_id) +{ + PMC->PMC_PCK[ul_id] = p_cfg->ctrl; + pmc_enable_pck(ul_id); +} + +static inline void genclk_disable(uint32_t ul_id) +{ + pmc_disable_pck(ul_id); +} + +static inline void genclk_enable_source(enum genclk_source e_src) +{ + switch (e_src) { + case GENCLK_PCK_SRC_SLCK_RC: + if (!osc_is_ready(OSC_SLCK_32K_RC)) { + osc_enable(OSC_SLCK_32K_RC); + osc_wait_ready(OSC_SLCK_32K_RC); + } + break; + + case GENCLK_PCK_SRC_SLCK_XTAL: + if (!osc_is_ready(OSC_SLCK_32K_XTAL)) { + osc_enable(OSC_SLCK_32K_XTAL); + osc_wait_ready(OSC_SLCK_32K_XTAL); + } + break; + + case GENCLK_PCK_SRC_SLCK_BYPASS: + if (!osc_is_ready(OSC_SLCK_32K_BYPASS)) { + osc_enable(OSC_SLCK_32K_BYPASS); + osc_wait_ready(OSC_SLCK_32K_BYPASS); + } + break; + + case GENCLK_PCK_SRC_MAINCK_4M_RC: + if (!osc_is_ready(OSC_MAINCK_4M_RC)) { + osc_enable(OSC_MAINCK_4M_RC); + osc_wait_ready(OSC_MAINCK_4M_RC); + } + break; + + case GENCLK_PCK_SRC_MAINCK_8M_RC: + if (!osc_is_ready(OSC_MAINCK_8M_RC)) { + osc_enable(OSC_MAINCK_8M_RC); + osc_wait_ready(OSC_MAINCK_8M_RC); + } + break; + + case GENCLK_PCK_SRC_MAINCK_12M_RC: + if (!osc_is_ready(OSC_MAINCK_12M_RC)) { + osc_enable(OSC_MAINCK_12M_RC); + osc_wait_ready(OSC_MAINCK_12M_RC); + } + break; + + case GENCLK_PCK_SRC_MAINCK_XTAL: + if (!osc_is_ready(OSC_MAINCK_XTAL)) { + osc_enable(OSC_MAINCK_XTAL); + osc_wait_ready(OSC_MAINCK_XTAL); + } + break; + + case GENCLK_PCK_SRC_MAINCK_BYPASS: + if (!osc_is_ready(OSC_MAINCK_BYPASS)) { + osc_enable(OSC_MAINCK_BYPASS); + osc_wait_ready(OSC_MAINCK_BYPASS); + } + break; + +#ifdef CONFIG_PLL0_SOURCE + case GENCLK_PCK_SRC_PLLACK: + pll_enable_config_defaults(0); + break; +#endif + +#ifdef CONFIG_PLL1_SOURCE + case GENCLK_PCK_SRC_PLLBCK: + pll_enable_config_defaults(1); + break; +#endif + + case GENCLK_PCK_SRC_MCK: + break; + + default: + Assert(false); + break; + } +} + +//! @} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +#endif /* CHIP_GENCLK_H_INCLUDED */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/clock/sam3x/osc.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/clock/sam3x/osc.h new file mode 100644 index 0000000..85a8993 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/clock/sam3x/osc.h @@ -0,0 +1,247 @@ +/** + * \file + * + * \brief Chip-specific oscillator management functions. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef CHIP_OSC_H_INCLUDED +#define CHIP_OSC_H_INCLUDED + +#include "board.h" +#include "pmc.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/* + * Below BOARD_XXX macros are related to the specific board, and + * should be defined by the board code, otherwise default value are used. + */ +#if !defined(BOARD_FREQ_SLCK_XTAL) +# warning The board slow clock xtal frequency has not been defined. +# define BOARD_FREQ_SLCK_XTAL (32768UL) +#endif + +#if !defined(BOARD_FREQ_SLCK_BYPASS) +# warning The board slow clock bypass frequency has not been defined. +# define BOARD_FREQ_SLCK_BYPASS (32768UL) +#endif + +#if !defined(BOARD_FREQ_MAINCK_XTAL) +# warning The board main clock xtal frequency has not been defined. +# define BOARD_FREQ_MAINCK_XTAL (12000000UL) +#endif + +#if !defined(BOARD_FREQ_MAINCK_BYPASS) +# warning The board main clock bypass frequency has not been defined. +# define BOARD_FREQ_MAINCK_BYPASS (12000000UL) +#endif + +#if !defined(BOARD_OSC_STARTUP_US) +# warning The board main clock xtal startup time has not been defined. +# define BOARD_OSC_STARTUP_US (15625UL) +#endif + +/** + * \weakgroup osc_group + * @{ + */ + +//! \name Oscillator identifiers +//@{ +#define OSC_SLCK_32K_RC 0 //!< Internal 32kHz RC oscillator. +#define OSC_SLCK_32K_XTAL 1 //!< External 32kHz crystal oscillator. +#define OSC_SLCK_32K_BYPASS 2 //!< External 32kHz bypass oscillator. +#define OSC_MAINCK_4M_RC 3 //!< Internal 4MHz RC oscillator. +#define OSC_MAINCK_8M_RC 4 //!< Internal 8MHz RC oscillator. +#define OSC_MAINCK_12M_RC 5 //!< Internal 12MHz RC oscillator. +#define OSC_MAINCK_XTAL 6 //!< External crystal oscillator. +#define OSC_MAINCK_BYPASS 7 //!< External bypass oscillator. +//@} + +//! \name Oscillator clock speed in hertz +//@{ +#define OSC_SLCK_32K_RC_HZ CHIP_FREQ_SLCK_RC //!< Internal 32kHz RC oscillator. +#define OSC_SLCK_32K_XTAL_HZ BOARD_FREQ_SLCK_XTAL //!< External 32kHz crystal oscillator. +#define OSC_SLCK_32K_BYPASS_HZ BOARD_FREQ_SLCK_BYPASS //!< External 32kHz bypass oscillator. +#define OSC_MAINCK_4M_RC_HZ CHIP_FREQ_MAINCK_RC_4MHZ //!< Internal 4MHz RC oscillator. +#define OSC_MAINCK_8M_RC_HZ CHIP_FREQ_MAINCK_RC_8MHZ //!< Internal 8MHz RC oscillator. +#define OSC_MAINCK_12M_RC_HZ CHIP_FREQ_MAINCK_RC_12MHZ //!< Internal 12MHz RC oscillator. +#define OSC_MAINCK_XTAL_HZ BOARD_FREQ_MAINCK_XTAL //!< External crystal oscillator. +#define OSC_MAINCK_BYPASS_HZ BOARD_FREQ_MAINCK_BYPASS //!< External bypass oscillator. +//@} + +static inline void osc_enable(uint32_t ul_id) +{ + switch (ul_id) { + case OSC_SLCK_32K_RC: + break; + + case OSC_SLCK_32K_XTAL: + pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL); + break; + + case OSC_SLCK_32K_BYPASS: + pmc_switch_sclk_to_32kxtal(PMC_OSC_BYPASS); + break; + + + case OSC_MAINCK_4M_RC: + pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz); + break; + + case OSC_MAINCK_8M_RC: + pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz); + break; + + case OSC_MAINCK_12M_RC: + pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz); + break; + + + case OSC_MAINCK_XTAL: + pmc_switch_mainck_to_xtal(PMC_OSC_XTAL, + pmc_us_to_moscxtst(BOARD_OSC_STARTUP_US, + OSC_SLCK_32K_RC_HZ)); + break; + + case OSC_MAINCK_BYPASS: + pmc_switch_mainck_to_xtal(PMC_OSC_BYPASS, + pmc_us_to_moscxtst(BOARD_OSC_STARTUP_US, + OSC_SLCK_32K_RC_HZ)); + break; + } +} + +static inline void osc_disable(uint32_t ul_id) +{ + switch (ul_id) { + case OSC_SLCK_32K_RC: + case OSC_SLCK_32K_XTAL: + case OSC_SLCK_32K_BYPASS: + break; + + case OSC_MAINCK_4M_RC: + case OSC_MAINCK_8M_RC: + case OSC_MAINCK_12M_RC: + pmc_osc_disable_fastrc(); + break; + + case OSC_MAINCK_XTAL: + pmc_osc_disable_xtal(PMC_OSC_XTAL); + break; + + case OSC_MAINCK_BYPASS: + pmc_osc_disable_xtal(PMC_OSC_BYPASS); + break; + } +} + +static inline bool osc_is_ready(uint32_t ul_id) +{ + switch (ul_id) { + case OSC_SLCK_32K_RC: + return 1; + + case OSC_SLCK_32K_XTAL: + case OSC_SLCK_32K_BYPASS: + return pmc_osc_is_ready_32kxtal(); + + case OSC_MAINCK_4M_RC: + case OSC_MAINCK_8M_RC: + case OSC_MAINCK_12M_RC: + case OSC_MAINCK_XTAL: + case OSC_MAINCK_BYPASS: + return pmc_osc_is_ready_mainck(); + } + + return 0; +} + +static inline uint32_t osc_get_rate(uint32_t ul_id) +{ + switch (ul_id) { + case OSC_SLCK_32K_RC: + return OSC_SLCK_32K_RC_HZ; + + case OSC_SLCK_32K_XTAL: + return BOARD_FREQ_SLCK_XTAL; + + case OSC_SLCK_32K_BYPASS: + return BOARD_FREQ_SLCK_BYPASS; + + case OSC_MAINCK_4M_RC: + return OSC_MAINCK_4M_RC_HZ; + + case OSC_MAINCK_8M_RC: + return OSC_MAINCK_8M_RC_HZ; + + case OSC_MAINCK_12M_RC: + return OSC_MAINCK_12M_RC_HZ; + + case OSC_MAINCK_XTAL: + return BOARD_FREQ_MAINCK_XTAL; + + case OSC_MAINCK_BYPASS: + return BOARD_FREQ_MAINCK_BYPASS; + } + + return 0; +} + +//! @} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +#endif /* CHIP_OSC_H_INCLUDED */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/clock/sam3x/pll.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/clock/sam3x/pll.h new file mode 100644 index 0000000..525b73b --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/clock/sam3x/pll.h @@ -0,0 +1,267 @@ +/** + * \file + * + * \brief Chip-specific PLL definitions. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef CHIP_PLL_H_INCLUDED +#define CHIP_PLL_H_INCLUDED + +#include + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \weakgroup pll_group + * @{ + */ + +#define PLL_OUTPUT_MIN_HZ 84000000 +#define PLL_OUTPUT_MAX_HZ 192000000 + +#define PLL_INPUT_MIN_HZ 8000000 +#define PLL_INPUT_MAX_HZ 16000000 + +#define NR_PLLS 2 +#define PLLA_ID 0 +#define UPLL_ID 1 //!< USB UTMI PLL. + +#define PLL_UPLL_HZ 480000000 + +#define PLL_COUNT 0x3fU + +enum pll_source { + PLL_SRC_MAINCK_4M_RC = OSC_MAINCK_4M_RC, //!< Internal 4MHz RC oscillator. + PLL_SRC_MAINCK_8M_RC = OSC_MAINCK_8M_RC, //!< Internal 8MHz RC oscillator. + PLL_SRC_MAINCK_12M_RC = OSC_MAINCK_12M_RC, //!< Internal 12MHz RC oscillator. + PLL_SRC_MAINCK_XTAL = OSC_MAINCK_XTAL, //!< External crystal oscillator. + PLL_SRC_MAINCK_BYPASS = OSC_MAINCK_BYPASS, //!< External bypass oscillator. + PLL_NR_SOURCES, //!< Number of PLL sources. +}; + +struct pll_config { + uint32_t ctrl; +}; + +#define pll_get_default_rate(pll_id) \ + ((osc_get_rate(CONFIG_PLL##pll_id##_SOURCE) \ + * CONFIG_PLL##pll_id##_MUL) \ + / CONFIG_PLL##pll_id##_DIV) + +/* Force UTMI PLL parameters (Hardware defined) */ +#ifdef CONFIG_PLL1_SOURCE +# undef CONFIG_PLL1_SOURCE +#endif +#ifdef CONFIG_PLL1_MUL +# undef CONFIG_PLL1_MUL +#endif +#ifdef CONFIG_PLL1_DIV +# undef CONFIG_PLL1_DIV +#endif +#define CONFIG_PLL1_SOURCE PLL_SRC_MAINCK_XTAL +#define CONFIG_PLL1_MUL 0 +#define CONFIG_PLL1_DIV 0 + +/** + * \note The SAM3X PLL hardware interprets mul as mul+1. For readability the hardware mul+1 + * is hidden in this implementation. Use mul as mul effective value. + */ +static inline void pll_config_init(struct pll_config *p_cfg, + enum pll_source e_src, uint32_t ul_div, uint32_t ul_mul) +{ + uint32_t vco_hz; + + Assert(e_src < PLL_NR_SOURCES); + + if (ul_div == 0 && ul_mul == 0) { /* Must only be true for UTMI PLL */ + p_cfg->ctrl = CKGR_UCKR_UPLLCOUNT(PLL_COUNT); + } else { /* PLLA */ + /* Calculate internal VCO frequency */ + vco_hz = osc_get_rate(e_src) / ul_div; + Assert(vco_hz >= PLL_INPUT_MIN_HZ); + Assert(vco_hz <= PLL_INPUT_MAX_HZ); + + vco_hz *= ul_mul; + Assert(vco_hz >= PLL_OUTPUT_MIN_HZ); + Assert(vco_hz <= PLL_OUTPUT_MAX_HZ); + + /* PMC hardware will automatically make it mul+1 */ + p_cfg->ctrl = CKGR_PLLAR_MULA(ul_mul - 1) | CKGR_PLLAR_DIVA(ul_div) | CKGR_PLLAR_PLLACOUNT(PLL_COUNT); + } +} + +#define pll_config_defaults(cfg, pll_id) \ + pll_config_init(cfg, \ + CONFIG_PLL##pll_id##_SOURCE, \ + CONFIG_PLL##pll_id##_DIV, \ + CONFIG_PLL##pll_id##_MUL) + +static inline void pll_config_read(struct pll_config *p_cfg, uint32_t ul_pll_id) +{ + Assert(ul_pll_id < NR_PLLS); + + if (ul_pll_id == PLLA_ID) { + p_cfg->ctrl = PMC->CKGR_PLLAR; + } else { + p_cfg->ctrl = PMC->CKGR_UCKR; + } +} + +static inline void pll_config_write(const struct pll_config *p_cfg, uint32_t ul_pll_id) +{ + Assert(ul_pll_id < NR_PLLS); + + if (ul_pll_id == PLLA_ID) { + pmc_disable_pllack(); // Always stop PLL first! + PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | p_cfg->ctrl; + } else { + PMC->CKGR_UCKR = p_cfg->ctrl; + } +} + +static inline void pll_enable(const struct pll_config *p_cfg, uint32_t ul_pll_id) +{ + Assert(ul_pll_id < NR_PLLS); + + if (ul_pll_id == PLLA_ID) { + pmc_disable_pllack(); // Always stop PLL first! + PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | p_cfg->ctrl; + } else { + PMC->CKGR_UCKR = p_cfg->ctrl | CKGR_UCKR_UPLLEN; + } +} + +/** + * \note This will only disable the selected PLL, not the underlying oscillator (mainck). + */ +static inline void pll_disable(uint32_t ul_pll_id) +{ + Assert(ul_pll_id < NR_PLLS); + + if (ul_pll_id == PLLA_ID) { + pmc_disable_pllack(); + } else { + PMC->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN; + } +} + +static inline uint32_t pll_is_locked(uint32_t ul_pll_id) +{ + Assert(ul_pll_id < NR_PLLS); + + if (ul_pll_id == PLLA_ID) { + return pmc_is_locked_pllack(); + } else { + return pmc_is_locked_upll(); + } +} + +static inline void pll_enable_source(enum pll_source e_src) +{ + switch (e_src) { + case PLL_SRC_MAINCK_4M_RC: + case PLL_SRC_MAINCK_8M_RC: + case PLL_SRC_MAINCK_12M_RC: + case PLL_SRC_MAINCK_XTAL: + case PLL_SRC_MAINCK_BYPASS: + osc_enable(e_src); + osc_wait_ready(e_src); + break; + + default: + Assert(false); + break; + } +} + +static inline void pll_enable_config_defaults(unsigned int ul_pll_id) +{ + struct pll_config pllcfg; + + if (pll_is_locked(ul_pll_id)) { + return; // Pll already running + } + switch (ul_pll_id) { +#ifdef CONFIG_PLL0_SOURCE + case 0: + pll_enable_source(CONFIG_PLL0_SOURCE); + pll_config_init(&pllcfg, + CONFIG_PLL0_SOURCE, + CONFIG_PLL0_DIV, + CONFIG_PLL0_MUL); + break; +#endif +#ifdef CONFIG_PLL1_SOURCE + case 1: + pll_enable_source(CONFIG_PLL1_SOURCE); + pll_config_init(&pllcfg, + CONFIG_PLL1_SOURCE, + CONFIG_PLL1_DIV, + CONFIG_PLL1_MUL); + break; +#endif + default: + Assert(false); + break; + } + pll_enable(&pllcfg, ul_pll_id); + while (!pll_is_locked(ul_pll_id)); +} + +//! @} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +#endif /* CHIP_PLL_H_INCLUDED */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/clock/sam3x/sysclk.c b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/clock/sam3x/sysclk.c new file mode 100644 index 0000000..7ffc9dc --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/clock/sam3x/sysclk.c @@ -0,0 +1,260 @@ +/** + * \file + * + * \brief Chip-specific system clock management functions. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#include + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \weakgroup sysclk_group + * @{ + */ + +#if defined(CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC) +/** + * \brief boolean signalling that the sysclk_init is done. + */ +uint32_t sysclk_initialized = 0; +#endif + +/** + * \brief Set system clock prescaler configuration + * + * This function will change the system clock prescaler configuration to + * match the parameters. + * + * \note The parameters to this function are device-specific. + * + * \param cpu_shift The CPU clock will be divided by \f$2^{mck\_pres}\f$ + */ +void sysclk_set_prescalers(uint32_t ul_pres) +{ + pmc_mck_set_prescaler(ul_pres); + SystemCoreClockUpdate(); +} + +/** + * \brief Change the source of the main system clock. + * + * \param src The new system clock source. Must be one of the constants + * from the System Clock Sources section. + */ +void sysclk_set_source(uint32_t ul_src) +{ + switch (ul_src) { + case SYSCLK_SRC_SLCK_RC: + case SYSCLK_SRC_SLCK_XTAL: + case SYSCLK_SRC_SLCK_BYPASS: + pmc_mck_set_source(PMC_MCKR_CSS_SLOW_CLK); + break; + + case SYSCLK_SRC_MAINCK_4M_RC: + case SYSCLK_SRC_MAINCK_8M_RC: + case SYSCLK_SRC_MAINCK_12M_RC: + case SYSCLK_SRC_MAINCK_XTAL: + case SYSCLK_SRC_MAINCK_BYPASS: + pmc_mck_set_source(PMC_MCKR_CSS_MAIN_CLK); + break; + + case SYSCLK_SRC_PLLACK: + pmc_mck_set_source(PMC_MCKR_CSS_PLLA_CLK); + break; + + case SYSCLK_SRC_UPLLCK: + pmc_mck_set_source(PMC_MCKR_CSS_UPLL_CLK); + break; + } + + SystemCoreClockUpdate(); +} + +#if defined(CONFIG_USBCLK_SOURCE) || defined(__DOXYGEN__) +/** + * \brief Enable full speed USB clock. + * + * \note The SAM3X PMC hardware interprets div as div+1. For readability the hardware div+1 + * is hidden in this implementation. Use div as div effective value. + * + * \param pll_id Source of the USB clock. + * \param div Actual clock divisor. Must be superior to 0. + */ +void sysclk_enable_usb(void) +{ + Assert(CONFIG_USBCLK_DIV > 0); + +#ifdef CONFIG_PLL0_SOURCE + if (CONFIG_USBCLK_SOURCE == USBCLK_SRC_PLL0) { + struct pll_config pllcfg; + + pll_enable_source(CONFIG_PLL0_SOURCE); + pll_config_defaults(&pllcfg, 0); + pll_enable(&pllcfg, 0); + pll_wait_for_lock(0); + pmc_switch_udpck_to_pllack(CONFIG_USBCLK_DIV - 1); + pmc_enable_udpck(); + return; + } +#endif + + if (CONFIG_USBCLK_SOURCE == USBCLK_SRC_UPLL) { + + pmc_enable_upll_clock(); + pmc_switch_udpck_to_upllck(CONFIG_USBCLK_DIV - 1); + pmc_enable_udpck(); + return; + } +} + +/** + * \brief Disable full speed USB clock. + * + * \note This implementation does not switch off the PLL, it just turns off the USB clock. + */ +void sysclk_disable_usb(void) +{ + pmc_disable_udpck(); +} +#endif // CONFIG_USBCLK_SOURCE + +void sysclk_init(void) +{ + struct pll_config pllcfg; + + /* Set flash wait state to max in case the below clock switching. */ + system_init_flash(CHIP_FREQ_CPU_MAX); + + /* Config system clock setting */ + if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_RC) { + osc_enable(OSC_SLCK_32K_RC); + osc_wait_ready(OSC_SLCK_32K_RC); + pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES); + } + + else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_XTAL) { + osc_enable(OSC_SLCK_32K_XTAL); + osc_wait_ready(OSC_SLCK_32K_XTAL); + pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES); + } + + else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_BYPASS) { + osc_enable(OSC_SLCK_32K_BYPASS); + osc_wait_ready(OSC_SLCK_32K_BYPASS); + pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES); + } + + else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_4M_RC) { + /* Already running from SYSCLK_SRC_MAINCK_4M_RC */ + } + + else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_8M_RC) { + osc_enable(OSC_MAINCK_8M_RC); + osc_wait_ready(OSC_MAINCK_8M_RC); + pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES); + } + + else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_12M_RC) { + osc_enable(OSC_MAINCK_12M_RC); + osc_wait_ready(OSC_MAINCK_12M_RC); + pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES); + } + + else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_XTAL) { + osc_enable(OSC_MAINCK_XTAL); + osc_wait_ready(OSC_MAINCK_XTAL); + pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES); + } + + else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_BYPASS) { + osc_enable(OSC_MAINCK_BYPASS); + osc_wait_ready(OSC_MAINCK_BYPASS); + pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES); + } + +#ifdef CONFIG_PLL0_SOURCE + else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_PLLACK) { + pll_enable_source(CONFIG_PLL0_SOURCE); + pll_config_defaults(&pllcfg, 0); + pll_enable(&pllcfg, 0); + pll_wait_for_lock(0); + pmc_switch_mck_to_pllack(CONFIG_SYSCLK_PRES); + } +#endif + + else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_UPLLCK) { + pll_enable_source(CONFIG_PLL1_SOURCE); + pll_config_defaults(&pllcfg, 1); + pll_enable(&pllcfg, 1); + pll_wait_for_lock(1); + pmc_switch_mck_to_upllck(CONFIG_SYSCLK_PRES); + } + + /* Update the SystemFrequency variable */ + SystemCoreClockUpdate(); + + /* Set a flash wait state depending on the new cpu frequency */ + system_init_flash(sysclk_get_cpu_hz()); + +#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC) + /* Signal that the internal frequencies are setup */ + sysclk_initialized = 1; +#endif +} + +//! @} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/clock/sam3x/sysclk.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/clock/sam3x/sysclk.h new file mode 100644 index 0000000..f3a6e29 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/clock/sam3x/sysclk.h @@ -0,0 +1,380 @@ +/** + * \file + * + * \brief Chip-specific system clock management functions. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef CHIP_SYSCLK_H_INCLUDED +#define CHIP_SYSCLK_H_INCLUDED + +#include +#include + +/** + * \page sysclk_quickstart Quick Start Guide for the System Clock Management service (SAM3A) + * + * This is the quick start guide for the \ref sysclk_group "System Clock Management" + * service, with step-by-step instructions on how to configure and use the service for + * specific use cases. + * + * \section sysclk_quickstart_usecases System Clock Management use cases + * - \ref sysclk_quickstart_basic + * + * \section sysclk_quickstart_basic Basic usage of the System Clock Management service + * This section will present a basic use case for the System Clock Management service. + * This use case will configure the main system clock to 84MHz, using an internal PLL + * module to multiply the frequency of a crystal attached to the microcontroller. + * + * \subsection sysclk_quickstart_use_case_1_prereq Prerequisites + * - None + * + * \subsection sysclk_quickstart_use_case_1_setup_steps Initialization code + * Add to the application initialization code: + * \code + sysclk_init(); +\endcode + * + * \subsection sysclk_quickstart_use_case_1_setup_steps_workflow Workflow + * -# Configure the system clocks according to the settings in conf_clock.h: + * \code sysclk_init(); \endcode + * + * \subsection sysclk_quickstart_use_case_1_example_code Example code + * Add or uncomment the following in your conf_clock.h header file, commenting out all other + * definitions of the same symbol(s): + * \code + #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK + + // Fpll0 = (Fclk * PLL_mul) / PLL_div + #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL + #define CONFIG_PLL0_MUL (84000000UL / BOARD_FREQ_MAINCK_XTAL) + #define CONFIG_PLL0_DIV 1 + + // Fbus = Fsys / BUS_div + #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1 +\endcode + * + * \subsection sysclk_quickstart_use_case_1_example_workflow Workflow + * -# Configure the main system clock to use the output of the PLL module as its source: + * \code #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK \endcode + * -# Configure the PLL module to use the fast external fast crystal oscillator as its source: + * \code #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL \endcode + * -# Configure the PLL module to multiply the external fast crystal oscillator frequency up to 84MHz: + * \code + #define CONFIG_PLL0_MUL (84000000UL / BOARD_FREQ_MAINCK_XTAL) + #define CONFIG_PLL0_DIV 1 +\endcode + * \note For user boards, \c BOARD_FREQ_MAINCK_XTAL should be defined in the board \c conf_board.h configuration + * file as the frequency of the fast crystal attached to the microcontroller. + * -# Configure the main clock to run at the full 84MHz, disable scaling of the main system clock speed: + * \code + #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1 +\endcode + * \note Some dividers are powers of two, while others are integer division factors. Refer to the + * formulas in the conf_clock.h template commented above each division define. + */ + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \weakgroup sysclk_group + * @{ + */ + +//! \name Configuration Symbols +//@{ +/** + * \def CONFIG_SYSCLK_SOURCE + * \brief Initial/static main system clock source + * + * The main system clock will be configured to use this clock during + * initialization. + */ +#ifndef CONFIG_SYSCLK_SOURCE +# define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC +#endif +/** + * \def CONFIG_SYSCLK_PRES + * \brief Initial CPU clock divider (mck) + * + * The MCK will run at + * \f[ + * f_{MCK} = \frac{f_{sys}}{\mathrm{CONFIG\_SYSCLK\_PRES}}\,\mbox{Hz} + * \f] + * after initialization. + */ +#ifndef CONFIG_SYSCLK_PRES +# define CONFIG_SYSCLK_PRES 0 +#endif + +//@} + +//! \name Master Clock Sources (MCK) +//@{ +#define SYSCLK_SRC_SLCK_RC 0 //!< Internal 32kHz RC oscillator as master source clock +#define SYSCLK_SRC_SLCK_XTAL 1 //!< External 32kHz crystal oscillator as master source clock +#define SYSCLK_SRC_SLCK_BYPASS 2 //!< External 32kHz bypass oscillator as master source clock +#define SYSCLK_SRC_MAINCK_4M_RC 3 //!< Internal 4MHz RC oscillator as master source clock +#define SYSCLK_SRC_MAINCK_8M_RC 4 //!< Internal 8MHz RC oscillator as master source clock +#define SYSCLK_SRC_MAINCK_12M_RC 5 //!< Internal 12MHz RC oscillator as master source clock +#define SYSCLK_SRC_MAINCK_XTAL 6 //!< External crystal oscillator as master source clock +#define SYSCLK_SRC_MAINCK_BYPASS 7 //!< External bypass oscillator as master source clock +#define SYSCLK_SRC_PLLACK 8 //!< Use PLLACK as master source clock +#define SYSCLK_SRC_UPLLCK 9 //!< Use UPLLCK as master source clock +//@} + +//! \name Master Clock Prescalers (MCK) +//@{ +#define SYSCLK_PRES_1 PMC_MCKR_PRES_CLK_1 //!< Set master clock prescaler to 1 +#define SYSCLK_PRES_2 PMC_MCKR_PRES_CLK_2 //!< Set master clock prescaler to 2 +#define SYSCLK_PRES_4 PMC_MCKR_PRES_CLK_4 //!< Set master clock prescaler to 4 +#define SYSCLK_PRES_8 PMC_MCKR_PRES_CLK_8 //!< Set master clock prescaler to 8 +#define SYSCLK_PRES_16 PMC_MCKR_PRES_CLK_16 //!< Set master clock prescaler to 16 +#define SYSCLK_PRES_32 PMC_MCKR_PRES_CLK_32 //!< Set master clock prescaler to 32 +#define SYSCLK_PRES_64 PMC_MCKR_PRES_CLK_64 //!< Set master clock prescaler to 64 +#define SYSCLK_PRES_3 PMC_MCKR_PRES_CLK_3 //!< Set master clock prescaler to 3 +//@} + +//! \name USB Clock Sources +//@{ +#define USBCLK_SRC_PLL0 0 //!< Use PLLA +#define USBCLK_SRC_UPLL 1 //!< Use UPLL +//@} + +/** + * \def CONFIG_USBCLK_SOURCE + * \brief Configuration symbol for the USB generic clock source + * + * Sets the clock source to use for the USB. The source must also be properly + * configured. + * + * Define this to one of the \c USBCLK_SRC_xxx settings. Leave it undefined if + * USB is not required. + */ +#ifdef __DOXYGEN__ +# define CONFIG_USBCLK_SOURCE +#endif + +/** + * \def CONFIG_USBCLK_DIV + * \brief Configuration symbol for the USB generic clock divider setting + * + * Sets the clock division for the USB generic clock. If a USB clock source is + * selected with CONFIG_USBCLK_SOURCE, this configuration symbol must also be + * defined. + */ +#ifdef __DOXYGEN__ +# define CONFIG_USBCLK_DIV +#endif + +/** + * \name Querying the system clock + * + * The following functions may be used to query the current frequency of + * the system clock and the CPU and bus clocks derived from it. + * sysclk_get_main_hz() and sysclk_get_cpu_hz() can be assumed to be + * available on all platforms, although some platforms may define + * additional accessors for various chip-internal bus clocks. These are + * usually not intended to be queried directly by generic code. + */ +//@{ + +/** + * \brief Return the current rate in Hz of the main system clock + * + * \todo This function assumes that the main clock source never changes + * once it's been set up, and that PLL0 always runs at the compile-time + * configured default rate. While this is probably the most common + * configuration, which we want to support as a special case for + * performance reasons, we will at some point need to support more + * dynamic setups as well. + */ +#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC) +extern uint32_t sysclk_initialized; +#endif +static inline uint32_t sysclk_get_main_hz(void) +{ +#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC) + if (!sysclk_initialized ) { + return OSC_MAINCK_4M_RC_HZ; + } +#endif + + /* Config system clock setting */ + if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_RC) { + return OSC_SLCK_32K_RC_HZ; + } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_XTAL) { + return OSC_SLCK_32K_XTAL_HZ; + } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_BYPASS) { + return OSC_SLCK_32K_BYPASS_HZ; + } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_4M_RC) { + return OSC_MAINCK_4M_RC_HZ; + } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_8M_RC) { + return OSC_MAINCK_8M_RC_HZ; + } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_12M_RC) { + return OSC_MAINCK_12M_RC_HZ; + } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_XTAL) { + return OSC_MAINCK_XTAL_HZ; + } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_BYPASS) { + return OSC_MAINCK_BYPASS_HZ; + } +#ifdef CONFIG_PLL0_SOURCE + else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_PLLACK) { + return pll_get_default_rate(0); + } +#endif + +#ifdef CONFIG_PLL1_SOURCE + else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_UPLLCK) { + return PLL_UPLL_HZ; + } +#endif + else { + /* unhandled_case(CONFIG_SYSCLK_SOURCE); */ + return 0; + } +} + +/** + * \brief Return the current rate in Hz of the CPU clock + * + * \todo This function assumes that the CPU always runs at the system + * clock frequency. We want to support at least two more scenarios: + * Fixed CPU/bus clock dividers (config symbols) and dynamic CPU/bus + * clock dividers (which may change at run time). Ditto for all the bus + * clocks. + * + * \return Frequency of the CPU clock, in Hz. + */ +static inline uint32_t sysclk_get_cpu_hz(void) +{ + /* CONFIG_SYSCLK_PRES is the register value for setting the expected */ + /* prescaler, not an immediate value. */ + return sysclk_get_main_hz() / + ((CONFIG_SYSCLK_PRES == SYSCLK_PRES_3) ? 3 : + (1 << (CONFIG_SYSCLK_PRES >> PMC_MCKR_PRES_Pos))); +} + +/** + * \brief Retrieves the current rate in Hz of the peripheral clocks. + * + * \return Frequency of the peripheral clocks, in Hz. + */ +static inline uint32_t sysclk_get_peripheral_hz(void) +{ + /* CONFIG_SYSCLK_PRES is the register value for setting the expected */ + /* prescaler, not an immediate value. */ + return sysclk_get_main_hz() / + ((CONFIG_SYSCLK_PRES == SYSCLK_PRES_3) ? 3 : + (1 << (CONFIG_SYSCLK_PRES >> PMC_MCKR_PRES_Pos))); +} + +/** + * \brief Retrieves the current rate in Hz of the Peripheral Bus clock attached + * to the specified peripheral. + * + * \param module Pointer to the module's base address. + * + * \return Frequency of the bus attached to the specified peripheral, in Hz. + */ +static inline uint32_t sysclk_get_peripheral_bus_hz(const volatile void *module) +{ + UNUSED(module); + return sysclk_get_peripheral_hz(); +} +//@} + +//! \name Enabling and disabling synchronous clocks +//@{ + +/** + * \brief Enable a peripheral's clock. + * + * \param ul_id Id (number) of the peripheral clock. + */ +static inline void sysclk_enable_peripheral_clock(uint32_t ul_id) +{ + pmc_enable_periph_clk(ul_id); +} + +/** + * \brief Disable a peripheral's clock. + * + * \param ul_id Id (number) of the peripheral clock. + */ +static inline void sysclk_disable_peripheral_clock(uint32_t ul_id) +{ + pmc_disable_periph_clk(ul_id); +} + +//@} + +//! \name System Clock Source and Prescaler configuration +//@{ + +extern void sysclk_set_prescalers(uint32_t ul_pres); +extern void sysclk_set_source(uint32_t ul_src); + +//@} + +extern void sysclk_enable_usb(void); +extern void sysclk_disable_usb(void); + +extern void sysclk_init(void); + +//! @} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +#endif /* CHIP_SYSCLK_H_INCLUDED */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/clock/sysclk.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/clock/sysclk.h new file mode 100644 index 0000000..86e4bf7 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/clock/sysclk.h @@ -0,0 +1,194 @@ +/** + * \file + * + * \brief System clock management + * + * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#ifndef SYSCLK_H_INCLUDED +#define SYSCLK_H_INCLUDED + +#include "parts.h" +#include "conf_clock.h" + +#if SAM3S +# include "sam3s/sysclk.h" +#elif SAM3U +# include "sam3u/sysclk.h" +#elif SAM3N +# include "sam3n/sysclk.h" +#elif SAM3XA +# include "sam3x/sysclk.h" +#elif SAM4S +# include "sam4s/sysclk.h" +#elif SAM4E +# include "sam4e/sysclk.h" +#elif SAM4C +# include "sam4c/sysclk.h" +#elif SAM4CM +# include "sam4cm/sysclk.h" +#elif SAM4CP +# include "sam4cp/sysclk.h" +#elif SAM4L +# include "sam4l/sysclk.h" +#elif SAM4N +# include "sam4n/sysclk.h" +#elif SAMG +# include "samg/sysclk.h" +#elif SAMV71 +# include "samv71/sysclk.h" +#elif SAMV70 +# include "samv70/sysclk.h" +#elif SAME70 +# include "same70/sysclk.h" +#elif SAMS70 +# include "sams70/sysclk.h" +#elif (UC3A0 || UC3A1) +# include "uc3a0_a1/sysclk.h" +#elif UC3A3 +# include "uc3a3_a4/sysclk.h" +#elif UC3B +# include "uc3b0_b1/sysclk.h" +#elif UC3C +# include "uc3c/sysclk.h" +#elif UC3D +# include "uc3d/sysclk.h" +#elif UC3L +# include "uc3l/sysclk.h" +#elif XMEGA +# include "xmega/sysclk.h" +#elif MEGA +# include "mega/sysclk.h" +#else +# error Unsupported chip type +#endif + +/** + * \defgroup clk_group Clock Management + */ + +/** + * \ingroup clk_group + * \defgroup sysclk_group System Clock Management + * + * See \ref sysclk_quickstart. + * + * The sysclk API covers the system clock and all + * clocks derived from it. The system clock is a chip-internal clock on + * which all synchronous clocks, i.e. CPU and bus/peripheral + * clocks, are based. The system clock is typically generated from one + * of a variety of sources, which may include crystal and RC oscillators + * as well as PLLs. The clocks derived from the system clock are + * sometimes also known as synchronous clocks, since they + * always run synchronously with respect to each other, as opposed to + * generic clocks which may run from different oscillators or + * PLLs. + * + * Most applications should simply call sysclk_init() to initialize + * everything related to the system clock and its source (oscillator, + * PLL or DFLL), and leave it at that. More advanced applications, and + * platform-specific drivers, may require additional services from the + * clock system, some of which may be platform-specific. + * + * \section sysclk_group_platform Platform Dependencies + * + * The sysclk API is partially chip- or platform-specific. While all + * platforms provide mostly the same functionality, there are some + * variations around how different bus types and clock tree structures + * are handled. + * + * The following functions are available on all platforms with the same + * parameters and functionality. These functions may be called freely by + * portable applications, drivers and services: + * - sysclk_init() + * - sysclk_set_source() + * - sysclk_get_main_hz() + * - sysclk_get_cpu_hz() + * - sysclk_get_peripheral_bus_hz() + * + * The following functions are available on all platforms, but there may + * be variations in the function signature (i.e. parameters) and + * behavior. These functions are typically called by platform-specific + * parts of drivers, and applications that aren't intended to be + * portable: + * - sysclk_enable_peripheral_clock() + * - sysclk_disable_peripheral_clock() + * - sysclk_enable_module() + * - sysclk_disable_module() + * - sysclk_module_is_enabled() + * - sysclk_set_prescalers() + * + * All other functions should be considered platform-specific. + * Enabling/disabling clocks to specific peripherals as well as + * determining the speed of these clocks should be done by calling + * functions provided by the driver for that peripheral. + * + * @{ + */ + +//! \name System Clock Initialization +//@{ +/** + * \fn void sysclk_init(void) + * \brief Initialize the synchronous clock system. + * + * This function will initialize the system clock and its source. This + * includes: + * - Mask all synchronous clocks except for any clocks which are + * essential for normal operation (for example internal memory + * clocks). + * - Set up the system clock prescalers as specified by the + * application's configuration file. + * - Enable the clock source specified by the application's + * configuration file (oscillator or PLL) and wait for it to become + * stable. + * - Set the main system clock source to the clock specified by the + * application's configuration file. + * + * Since all non-essential peripheral clocks are initially disabled, it + * is the responsibility of the peripheral driver to re-enable any + * clocks that are needed for normal operation. + */ +//@} + +//! @} + +#endif /* SYSCLK_H_INCLUDED */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/gpio/gpio.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/gpio/gpio.h new file mode 100644 index 0000000..e062690 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/gpio/gpio.h @@ -0,0 +1,86 @@ +/** + * \file + * + * \brief Common GPIO API. + * + * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#ifndef _GPIO_H_ +#define _GPIO_H_ + +#include + +#if (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) +# include "sam_gpio/sam_gpio.h" +#elif XMEGA +# include "xmega_gpio/xmega_gpio.h" +#elif MEGA || MEGA_RF +# include "mega_gpio/mega_gpio.h" +#else +# error Unsupported chip type +#endif + +/** + * \defgroup gpio_group General Purpose Input/Output + * + * This is the common API for GPIO. Additional features are available + * in the documentation of the specific modules. + * + * \section io_group_platform Platform Dependencies + * + * The following functions are available on all platforms, but there may + * be variations in the function signature (i.e. parameters) and + * behaviour. These functions are typically called by platform-specific + * parts of drivers, and applications that aren't intended to be + * portable: + * - gpio_pin_is_low() + * - gpio_pin_is_high() + * - gpio_set_pin_high() + * - gpio_set_pin_group_high() + * - gpio_set_pin_low() + * - gpio_set_pin_group_low() + * - gpio_toggle_pin() + * - gpio_toggle_pin_group() + * - gpio_configure_pin() + * - gpio_configure_group() + */ + +#endif /* _GPIO_H_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/gpio/sam_gpio/sam_gpio.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/gpio/sam_gpio/sam_gpio.h new file mode 100644 index 0000000..cb5e974 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/gpio/sam_gpio/sam_gpio.h @@ -0,0 +1,83 @@ +/** + * \file + * + * \brief GPIO service for SAM. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef SAM_GPIO_H_INCLUDED +#define SAM_GPIO_H_INCLUDED + +#include "compiler.h" +#include "pio.h" + +#define gpio_pin_is_low(io_id) \ + (pio_get_pin_value(io_id) ? 0 : 1) + +#define gpio_pin_is_high(io_id) \ + (pio_get_pin_value(io_id) ? 1 : 0) + +#define gpio_set_pin_high(io_id) \ + pio_set_pin_high(io_id) + +#define gpio_set_pin_low(io_id) \ + pio_set_pin_low(io_id) + +#define gpio_toggle_pin(io_id) \ + pio_toggle_pin(io_id) + +#define gpio_configure_pin(io_id,io_flags) \ + pio_configure_pin(io_id,io_flags) + +#define gpio_configure_group(port_id,port_mask,io_flags) \ + pio_configure_pin_group(port_id,port_mask,io_flags) + +#define gpio_set_pin_group_high(port_id,mask) \ + pio_set_pin_group_high(port_id,mask) + +#define gpio_set_pin_group_low(port_id,mask) \ + pio_set_pin_group_low(port_id,mask) + +#define gpio_toggle_pin_group(port_id,mask) \ + pio_toggle_pin_group(port_id,mask) + +#endif /* SAM_GPIO_H_INCLUDED */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/ioport/ioport.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/ioport/ioport.h new file mode 100644 index 0000000..5278126 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/ioport/ioport.h @@ -0,0 +1,541 @@ +/** + * \file + * + * \brief Common IOPORT service main header file for AVR, UC3 and ARM + * architectures. + * + * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#ifndef IOPORT_H +#define IOPORT_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/** + * \defgroup ioport_group Common IOPORT API + * + * See \ref ioport_quickstart. + * + * This is common IOPORT service for GPIO pin configuration and control in a + * standardized manner across the MEGA, MEGA_RF, XMEGA, UC3 and ARM devices. + * + * Port pin control code is optimized for each platform, and should produce + * both compact and fast execution times when used with constant values. + * + * \section dependencies Dependencies + * This driver depends on the following modules: + * - \ref sysclk_group for clock speed and functions. + * @{ + */ + +/** + * \def IOPORT_CREATE_PIN(port, pin) + * \brief Create IOPORT pin number + * + * Create a IOPORT pin number for use with the IOPORT functions. + * + * \param port IOPORT port (e.g. PORTA, PA or PIOA depending on chosen + * architecture) + * \param pin IOPORT zero-based index of the I/O pin + */ + +/** \brief IOPORT pin directions */ +enum ioport_direction { + IOPORT_DIR_INPUT, /*!< IOPORT input direction */ + IOPORT_DIR_OUTPUT, /*!< IOPORT output direction */ +}; + +/** \brief IOPORT levels */ +enum ioport_value { + IOPORT_PIN_LEVEL_LOW, /*!< IOPORT pin value low */ + IOPORT_PIN_LEVEL_HIGH, /*!< IOPORT pin value high */ +}; + +#if MEGA_RF +/** \brief IOPORT edge sense modes */ +enum ioport_sense { + IOPORT_SENSE_LEVEL, /*!< IOPORT sense low level */ + IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */ + IOPORT_SENSE_FALLING, /*!< IOPORT sense falling edges */ + IOPORT_SENSE_RISING, /*!< IOPORT sense rising edges */ +}; +#elif SAM && !SAM4L +/** \brief IOPORT edge sense modes */ +enum ioport_sense { + IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */ + IOPORT_SENSE_FALLING, /*!< IOPORT sense falling edges */ + IOPORT_SENSE_RISING, /*!< IOPORT sense rising edges */ + IOPORT_SENSE_LEVEL_LOW, /*!< IOPORT sense low level */ + IOPORT_SENSE_LEVEL_HIGH,/*!< IOPORT sense High level */ +}; +#else +enum ioport_sense { + IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */ + IOPORT_SENSE_RISING, /*!< IOPORT sense rising edges */ + IOPORT_SENSE_FALLING, /*!< IOPORT sense falling edges */ +}; +#endif + + +#if XMEGA +# include "xmega/ioport.h" +# if defined(IOPORT_XMEGA_COMPAT) +# include "xmega/ioport_compat.h" +# endif +#elif MEGA +# include "mega/ioport.h" +#elif UC3 +# include "uc3/ioport.h" +#elif SAM +# if SAM4L +# include "sam/ioport_gpio.h" +# elif (SAMD20 | SAMD21 | SAML21) +# include "sam0/ioport.h" +# else +# include "sam/ioport_pio.h" +# endif +#endif + +/** + * \brief Initializes the IOPORT service, ready for use. + * + * This function must be called before using any other functions in the IOPORT + * service. + */ +static inline void ioport_init(void) +{ + arch_ioport_init(); +} + +/** + * \brief Enable an IOPORT pin, based on a pin created with \ref + * IOPORT_CREATE_PIN(). + * + * \param pin IOPORT pin to enable + */ +static inline void ioport_enable_pin(ioport_pin_t pin) +{ + arch_ioport_enable_pin(pin); +} + +/** + * \brief Enable multiple pins in a single IOPORT port. + * + * \param port IOPORT port to enable + * \param mask Mask of pins within the port to enable + */ +static inline void ioport_enable_port(ioport_port_t port, + ioport_port_mask_t mask) +{ + arch_ioport_enable_port(port, mask); +} + +/** + * \brief Disable IOPORT pin, based on a pin created with \ref + * IOPORT_CREATE_PIN(). + * + * \param pin IOPORT pin to disable + */ +static inline void ioport_disable_pin(ioport_pin_t pin) +{ + arch_ioport_disable_pin(pin); +} + +/** + * \brief Disable multiple pins in a single IOPORT port. + * + * \param port IOPORT port to disable + * \param mask Pin mask of pins to disable + */ +static inline void ioport_disable_port(ioport_port_t port, + ioport_port_mask_t mask) +{ + arch_ioport_disable_port(port, mask); +} + +/** + * \brief Set multiple pin modes in a single IOPORT port, such as pull-up, + * pull-down, etc. configuration. + * + * \param port IOPORT port to configure + * \param mask Pin mask of pins to configure + * \param mode Mode masks to configure for the specified pins (\ref + * ioport_modes) + */ +static inline void ioport_set_port_mode(ioport_port_t port, + ioport_port_mask_t mask, ioport_mode_t mode) +{ + arch_ioport_set_port_mode(port, mask, mode); +} + +/** + * \brief Set pin mode for one single IOPORT pin. + * + * \param pin IOPORT pin to configure + * \param mode Mode masks to configure for the specified pin (\ref ioport_modes) + */ +static inline void ioport_set_pin_mode(ioport_pin_t pin, ioport_mode_t mode) +{ + arch_ioport_set_pin_mode(pin, mode); +} + +/** + * \brief Reset multiple pin modes in a specified IOPORT port to defaults. + * + * \param port IOPORT port to configure + * \param mask Mask of pins whose mode configuration is to be reset + */ +static inline void ioport_reset_port_mode(ioport_port_t port, + ioport_port_mask_t mask) +{ + arch_ioport_set_port_mode(port, mask, 0); +} + +/** + * \brief Reset pin mode configuration for a single IOPORT pin + * + * \param pin IOPORT pin to configure + */ +static inline void ioport_reset_pin_mode(ioport_pin_t pin) +{ + arch_ioport_set_pin_mode(pin, 0); +} + +/** + * \brief Set I/O direction for a group of pins in a single IOPORT. + * + * \param port IOPORT port to configure + * \param mask Pin mask of pins to configure + * \param dir Direction to set for the specified pins (\ref ioport_direction) + */ +static inline void ioport_set_port_dir(ioport_port_t port, + ioport_port_mask_t mask, enum ioport_direction dir) +{ + arch_ioport_set_port_dir(port, mask, dir); +} + +/** + * \brief Set direction for a single IOPORT pin. + * + * \param pin IOPORT pin to configure + * \param dir Direction to set for the specified pin (\ref ioport_direction) + */ +static inline void ioport_set_pin_dir(ioport_pin_t pin, + enum ioport_direction dir) +{ + arch_ioport_set_pin_dir(pin, dir); +} + +/** + * \brief Set an IOPORT pin to a specified logical value. + * + * \param pin IOPORT pin to configure + * \param level Logical value of the pin + */ +static inline void ioport_set_pin_level(ioport_pin_t pin, bool level) +{ + arch_ioport_set_pin_level(pin, level); +} + +/** + * \brief Set a group of IOPORT pins in a single port to a specified logical + * value. + * + * \param port IOPORT port to write to + * \param mask Pin mask of pins to modify + * \param level Level of the pins to be modified + */ +static inline void ioport_set_port_level(ioport_port_t port, + ioport_port_mask_t mask, ioport_port_mask_t level) +{ + arch_ioport_set_port_level(port, mask, level); +} + +/** + * \brief Get current value of an IOPORT pin, which has been configured as an + * input. + * + * \param pin IOPORT pin to read + * \return Current logical value of the specified pin + */ +static inline bool ioport_get_pin_level(ioport_pin_t pin) +{ + return arch_ioport_get_pin_level(pin); +} + +/** + * \brief Get current value of several IOPORT pins in a single port, which have + * been configured as an inputs. + * + * \param port IOPORT port to read + * \param mask Pin mask of pins to read + * \return Logical levels of the specified pins from the read port, returned as + * a mask. + */ +static inline ioport_port_mask_t ioport_get_port_level(ioport_pin_t port, + ioport_port_mask_t mask) +{ + return arch_ioport_get_port_level(port, mask); +} + +/** + * \brief Toggle the value of an IOPORT pin, which has previously configured as + * an output. + * + * \param pin IOPORT pin to toggle + */ +static inline void ioport_toggle_pin_level(ioport_pin_t pin) +{ + arch_ioport_toggle_pin_level(pin); +} + +/** + * \brief Toggle the values of several IOPORT pins located in a single port. + * + * \param port IOPORT port to modify + * \param mask Pin mask of pins to toggle + */ +static inline void ioport_toggle_port_level(ioport_port_t port, + ioport_port_mask_t mask) +{ + arch_ioport_toggle_port_level(port, mask); +} + +/** + * \brief Set the pin sense mode of a single IOPORT pin. + * + * \param pin IOPORT pin to configure + * \param pin_sense Edge to sense for the pin (\ref ioport_sense) + */ +static inline void ioport_set_pin_sense_mode(ioport_pin_t pin, + enum ioport_sense pin_sense) +{ + arch_ioport_set_pin_sense_mode(pin, pin_sense); +} + +/** + * \brief Set the pin sense mode of a multiple IOPORT pins on a single port. + * + * \param port IOPORT port to configure + * \param mask Bitmask if pins whose edge sense is to be configured + * \param pin_sense Edge to sense for the pins (\ref ioport_sense) + */ +static inline void ioport_set_port_sense_mode(ioport_port_t port, + ioport_port_mask_t mask, + enum ioport_sense pin_sense) +{ + arch_ioport_set_port_sense_mode(port, mask, pin_sense); +} + +/** + * \brief Convert a pin ID into a its port ID. + * + * \param pin IOPORT pin ID to convert + * \retval Port ID for the given pin ID + */ +static inline ioport_port_t ioport_pin_to_port_id(ioport_pin_t pin) +{ + return arch_ioport_pin_to_port_id(pin); +} + +/** + * \brief Convert a pin ID into a bitmask mask for the given pin on its port. + * + * \param pin IOPORT pin ID to convert + * \retval Bitmask with a bit set that corresponds to the given pin ID in its port + */ +static inline ioport_port_mask_t ioport_pin_to_mask(ioport_pin_t pin) +{ + return arch_ioport_pin_to_mask(pin); +} + +/** @} */ + +/** + * \page ioport_quickstart Quick start guide for the common IOPORT service + * + * This is the quick start guide for the \ref ioport_group, with + * step-by-step instructions on how to configure and use the service in a + * selection of use cases. + * + * The use cases contain several code fragments. The code fragments in the + * steps for setup can be copied into a custom initialization function, while + * the steps for usage can be copied into, e.g., the main application function. + * + * \section ioport_quickstart_basic Basic use case + * In this use case we will configure one IO pin for button input and one for + * LED control. Then it will read the button state and output it on the LED. + * + * \section ioport_quickstart_basic_setup Setup steps + * + * \subsection ioport_quickstart_basic_setup_code Example code + * \code + #define MY_LED IOPORT_CREATE_PIN(PORTA, 5) + #define MY_BUTTON IOPORT_CREATE_PIN(PORTA, 6) + + ioport_init(); + + ioport_set_pin_dir(MY_LED, IOPORT_DIR_OUTPUT); + ioport_set_pin_dir(MY_BUTTON, IOPORT_DIR_INPUT); + ioport_set_pin_mode(MY_BUTTON, IOPORT_MODE_PULLUP); +\endcode + * + * \subsection ioport_quickstart_basic_setup_flow Workflow + * -# It's useful to give the GPIOs symbolic names and this can be done with + * the \ref IOPORT_CREATE_PIN macro. We define one for a LED and one for a + * button. + * - \code + #define MY_LED IOPORT_CREATE_PIN(PORTA, 5) + #define MY_BUTTON IOPORT_CREATE_PIN(PORTA, 6) +\endcode + * - \note The usefulness of the \ref IOPORT_CREATE_PIN macro and port names + * differ between architectures: + * - MEGA, MEGA_RF and XMEGA: Use \ref IOPORT_CREATE_PIN macro with port definitions + * PORTA, PORTB ... + * - UC3: Most convenient to pick up the device header file pin definition + * and us it directly. E.g.: AVR32_PIN_PB06 + * - SAM: Most convenient to pick up the device header file pin definition + * and us it directly. E.g.: PIO_PA5_IDX
+ * \ref IOPORT_CREATE_PIN can also be used with port definitions + * PIOA, PIOB ... + * -# Initialize the ioport service. This typically enables the IO module if + * needed. + * - \code ioport_init(); \endcode + * -# Set the LED GPIO as output: + * - \code ioport_set_pin_dir(MY_LED, IOPORT_DIR_OUTPUT); \endcode + * -# Set the button GPIO as input: + * - \code ioport_set_pin_dir(MY_BUTTON, IOPORT_DIR_INPUT); \endcode + * -# Enable pull-up for the button GPIO: + * - \code ioport_set_pin_mode(MY_BUTTON, IOPORT_MODE_PULLUP); \endcode + * + * \section ioport_quickstart_basic_usage Usage steps + * + * \subsection ioport_quickstart_basic_usage_code Example code + * \code + bool value; + + value = ioport_get_pin_level(MY_BUTTON); + ioport_set_pin_level(MY_LED, value); +\endcode + * + * \subsection ioport_quickstart_basic_usage_flow Workflow + * -# Define a boolean variable for state storage: + * - \code bool value; \endcode + * -# Read out the button level into variable value: + * - \code value = ioport_get_pin_level(MY_BUTTON); \endcode + * -# Set the LED to read out value from the button: + * - \code ioport_set_pin_level(MY_LED, value); \endcode + * + * \section ioport_quickstart_advanced Advanced use cases + * - \subpage ioport_quickstart_use_case_1 : Port access + */ + +/** + * \page ioport_quickstart_use_case_1 Advanced use case doing port access + * + * In this case we will read out the pins from one whole port and write the + * read value to another port. + * + * \section ioport_quickstart_use_case_1_setup Setup steps + * + * \subsection ioport_quickstart_use_case_1_setup_code Example code + * \code + #define IN_PORT IOPORT_PORTA + #define OUT_PORT IOPORT_PORTB + #define MASK 0x00000060 + + ioport_init(); + + ioport_set_port_dir(IN_PORT, MASK, IOPORT_DIR_INPUT); + ioport_set_port_dir(OUT_PORT, MASK, IOPORT_DIR_OUTPUT); +\endcode + * + * \subsection ioport_quickstart_basic_setup_flow Workflow + * -# It's useful to give the ports symbolic names: + * - \code + #define IN_PORT IOPORT_PORTA + #define OUT_PORT IOPORT_PORTB +\endcode + * - \note The port names differ between architectures: + * - MEGA_RF, MEGA and XMEGA: There are predefined names for ports: IOPORT_PORTA, + * IOPORT_PORTB ... + * - UC3: Use the index value of the different IO blocks: 0, 1 ... + * - SAM: There are predefined names for ports: IOPORT_PIOA, IOPORT_PIOB + * ... + * -# Also useful to define a mask for the bits to work with: + * - \code #define MASK 0x00000060 \endcode + * -# Initialize the ioport service. This typically enables the IO module if + * needed. + * - \code ioport_init(); \endcode + * -# Set one of the ports as input: + * - \code ioport_set_pin_dir(IN_PORT, MASK, IOPORT_DIR_INPUT); \endcode + * -# Set the other port as output: + * - \code ioport_set_pin_dir(OUT_PORT, MASK, IOPORT_DIR_OUTPUT); \endcode + * + * \section ioport_quickstart_basic_usage Usage steps + * + * \subsection ioport_quickstart_basic_usage_code Example code + * \code + ioport_port_mask_t value; + + value = ioport_get_port_level(IN_PORT, MASK); + ioport_set_port_level(OUT_PORT, MASK, value); +\endcode + * + * \subsection ioport_quickstart_basic_usage_flow Workflow + * -# Define a variable for port date storage: + * - \code ioport_port_mask_t value; \endcode + * -# Read out from one port: + * - \code value = ioport_get_port_level(IN_PORT, MASK); \endcode + * -# Put the read data out on the other port: + * - \code ioport_set_port_level(OUT_PORT, MASK, value); \endcode + */ + +#ifdef __cplusplus +} +#endif + +#endif /* IOPORT_H */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/ioport/sam/ioport_pio.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/ioport/sam/ioport_pio.h new file mode 100644 index 0000000..8c003e1 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/ioport/sam/ioport_pio.h @@ -0,0 +1,380 @@ +/** + * \file + * + * \brief SAM architecture specific IOPORT service implementation header file. + * + * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#ifndef IOPORT_SAM_H +#define IOPORT_SAM_H + +#include + +#define IOPORT_CREATE_PIN(port, pin) ((IOPORT_ ## port) * 32 + (pin)) +#define IOPORT_BASE_ADDRESS (uintptr_t)PIOA +#define IOPORT_PIO_OFFSET ((uintptr_t)PIOB - (uintptr_t)PIOA) + +#define IOPORT_PIOA 0 +#define IOPORT_PIOB 1 +#define IOPORT_PIOC 2 +#define IOPORT_PIOD 3 +#define IOPORT_PIOE 4 +#define IOPORT_PIOF 5 + +/** + * \weakgroup ioport_group + * \section ioport_modes IOPORT Modes + * + * For details on these please see the SAM Manual. + * + * @{ + */ + +/** \name IOPORT Mode bit definitions */ +/** @{ */ +#define IOPORT_MODE_MUX_MASK (0x7 << 0) /*!< MUX bits mask */ +#define IOPORT_MODE_MUX_BIT0 ( 1 << 0) /*!< MUX BIT0 mask */ + +#if SAM3N || SAM3S || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70 +#define IOPORT_MODE_MUX_BIT1 ( 1 << 1) /*!< MUX BIT1 mask */ +#endif + +#define IOPORT_MODE_MUX_A ( 0 << 0) /*!< MUX function A */ +#define IOPORT_MODE_MUX_B ( 1 << 0) /*!< MUX function B */ + +#if SAM3N || SAM3S || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70 +#define IOPORT_MODE_MUX_C ( 2 << 0) /*!< MUX function C */ +#define IOPORT_MODE_MUX_D ( 3 << 0) /*!< MUX function D */ +#endif + +#define IOPORT_MODE_PULLUP ( 1 << 3) /*!< Pull-up */ + +#if SAM3N || SAM3S || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70 +#define IOPORT_MODE_PULLDOWN ( 1 << 4) /*!< Pull-down */ +#endif + +#define IOPORT_MODE_OPEN_DRAIN ( 1 << 5) /*!< Open drain */ + +#define IOPORT_MODE_GLITCH_FILTER ( 1 << 6) /*!< Glitch filter */ +#define IOPORT_MODE_DEBOUNCE ( 1 << 7) /*!< Input debounce */ +/** @} */ + +/** @} */ + +typedef uint32_t ioport_mode_t; +typedef uint32_t ioport_pin_t; +typedef uint32_t ioport_port_t; +typedef uint32_t ioport_port_mask_t; + +__always_inline static ioport_port_t arch_ioport_pin_to_port_id(ioport_pin_t pin) +{ + return pin >> 5; +} + +__always_inline static Pio *arch_ioport_port_to_base(ioport_port_t port) +{ +#if (SAM4C || SAM4CM || SAM4CP) + if (port == IOPORT_PIOC) { + return (Pio *)(uintptr_t)PIOC; +# ifdef ID_PIOD + } else if (port == IOPORT_PIOD) { + return (Pio *)(uintptr_t)PIOD; +# endif + } else { + return (Pio *)((uintptr_t)IOPORT_BASE_ADDRESS + + (IOPORT_PIO_OFFSET * port)); + } +#else + return (Pio *)((uintptr_t)IOPORT_BASE_ADDRESS + + (IOPORT_PIO_OFFSET * port)); +#endif +} + +__always_inline static Pio *arch_ioport_pin_to_base(ioport_pin_t pin) +{ + return arch_ioport_port_to_base(arch_ioport_pin_to_port_id(pin)); +} + +__always_inline static ioport_port_mask_t arch_ioport_pin_to_mask(ioport_pin_t pin) +{ + return 1U << (pin & 0x1F); +} + +__always_inline static void arch_ioport_init(void) +{ +#ifdef ID_PIOA + sysclk_enable_peripheral_clock(ID_PIOA); +#endif +#ifdef ID_PIOB + sysclk_enable_peripheral_clock(ID_PIOB); +#endif +#ifdef ID_PIOC + sysclk_enable_peripheral_clock(ID_PIOC); +#endif +#ifdef ID_PIOD + sysclk_enable_peripheral_clock(ID_PIOD); +#endif +#ifdef ID_PIOE + sysclk_enable_peripheral_clock(ID_PIOE); +#endif +#ifdef ID_PIOF + sysclk_enable_peripheral_clock(ID_PIOF); +#endif +} + +__always_inline static void arch_ioport_enable_port(ioport_port_t port, + ioport_port_mask_t mask) +{ + arch_ioport_port_to_base(port)->PIO_PER = mask; +} + +__always_inline static void arch_ioport_disable_port(ioport_port_t port, + ioport_port_mask_t mask) +{ + arch_ioport_port_to_base(port)->PIO_PDR = mask; +} + +__always_inline static void arch_ioport_enable_pin(ioport_pin_t pin) +{ + arch_ioport_enable_port(arch_ioport_pin_to_port_id(pin), + arch_ioport_pin_to_mask(pin)); +} + +__always_inline static void arch_ioport_disable_pin(ioport_pin_t pin) +{ + arch_ioport_disable_port(arch_ioport_pin_to_port_id(pin), + arch_ioport_pin_to_mask(pin)); +} + +__always_inline static void arch_ioport_set_port_mode(ioport_port_t port, + ioport_port_mask_t mask, ioport_mode_t mode) +{ + Pio *base = arch_ioport_port_to_base(port); + + if (mode & IOPORT_MODE_PULLUP) { + base->PIO_PUER = mask; + } else { + base->PIO_PUDR = mask; + } + +#if defined(IOPORT_MODE_PULLDOWN) + if (mode & IOPORT_MODE_PULLDOWN) { + base->PIO_PPDER = mask; + } else { + base->PIO_PPDDR = mask; + } +#endif + + if (mode & IOPORT_MODE_OPEN_DRAIN) { + base->PIO_MDER = mask; + } else { + base->PIO_MDDR = mask; + } + + if (mode & (IOPORT_MODE_GLITCH_FILTER | IOPORT_MODE_DEBOUNCE)) { + base->PIO_IFER = mask; + } else { + base->PIO_IFDR = mask; + } + + if (mode & IOPORT_MODE_DEBOUNCE) { +#if SAM3U || SAM3XA + base->PIO_DIFSR = mask; +#else + base->PIO_IFSCER = mask; +#endif + } else { +#if SAM3U || SAM3XA + base->PIO_SCIFSR = mask; +#else + base->PIO_IFSCDR = mask; +#endif + } + +#if !defined(IOPORT_MODE_MUX_BIT1) + if (mode & IOPORT_MODE_MUX_BIT0) { + base->PIO_ABSR |= mask; + } else { + base->PIO_ABSR &= ~mask; + } +#else + if (mode & IOPORT_MODE_MUX_BIT0) { + base->PIO_ABCDSR[0] |= mask; + } else { + base->PIO_ABCDSR[0] &= ~mask; + } + + if (mode & IOPORT_MODE_MUX_BIT1) { + base->PIO_ABCDSR[1] |= mask; + } else { + base->PIO_ABCDSR[1] &= ~mask; + } +#endif +} + +__always_inline static void arch_ioport_set_pin_mode(ioport_pin_t pin, + ioport_mode_t mode) +{ + arch_ioport_set_port_mode(arch_ioport_pin_to_port_id(pin), + arch_ioport_pin_to_mask(pin), mode); +} + +__always_inline static void arch_ioport_set_port_dir(ioport_port_t port, + ioport_port_mask_t mask, enum ioport_direction group_direction) +{ + Pio *base = arch_ioport_port_to_base(port); + + if (group_direction == IOPORT_DIR_OUTPUT) { + base->PIO_OER = mask; + } else if (group_direction == IOPORT_DIR_INPUT) { + base->PIO_ODR = mask; + } + + base->PIO_OWER = mask; +} + +__always_inline static void arch_ioport_set_pin_dir(ioport_pin_t pin, + enum ioport_direction dir) +{ + Pio *base = arch_ioport_pin_to_base(pin); + + if (dir == IOPORT_DIR_OUTPUT) { + base->PIO_OER = arch_ioport_pin_to_mask(pin); + } else if (dir == IOPORT_DIR_INPUT) { + base->PIO_ODR = arch_ioport_pin_to_mask(pin); + } + + base->PIO_OWER = arch_ioport_pin_to_mask(pin); +} + +__always_inline static void arch_ioport_set_pin_level(ioport_pin_t pin, + bool level) +{ + Pio *base = arch_ioport_pin_to_base(pin); + + if (level) { + base->PIO_SODR = arch_ioport_pin_to_mask(pin); + } else { + base->PIO_CODR = arch_ioport_pin_to_mask(pin); + } +} + +__always_inline static void arch_ioport_set_port_level(ioport_port_t port, + ioport_port_mask_t mask, ioport_port_mask_t level) +{ + Pio *base = arch_ioport_port_to_base(port); + + base->PIO_SODR = mask & level; + base->PIO_CODR = mask & ~level; +} + +__always_inline static bool arch_ioport_get_pin_level(ioport_pin_t pin) +{ + return arch_ioport_pin_to_base(pin)->PIO_PDSR & arch_ioport_pin_to_mask(pin); +} + +__always_inline static ioport_port_mask_t arch_ioport_get_port_level( + ioport_port_t port, ioport_port_mask_t mask) +{ + return arch_ioport_port_to_base(port)->PIO_PDSR & mask; +} + +__always_inline static void arch_ioport_toggle_pin_level(ioport_pin_t pin) +{ + Pio *port = arch_ioport_pin_to_base(pin); + ioport_port_mask_t mask = arch_ioport_pin_to_mask(pin); + + if (port->PIO_PDSR & arch_ioport_pin_to_mask(pin)) { + port->PIO_CODR = mask; + } else { + port->PIO_SODR = mask; + } +} + +__always_inline static void arch_ioport_toggle_port_level(ioport_port_t port, + ioport_port_mask_t mask) +{ + arch_ioport_port_to_base(port)->PIO_ODSR ^= mask; +} + +__always_inline static void arch_ioport_set_port_sense_mode(ioport_port_t port, + ioport_port_mask_t mask, enum ioport_sense pin_sense) +{ + Pio *base = arch_ioport_port_to_base(port); + /* AIMMR ELSR FRLHSR + * 0 X X IOPORT_SENSE_BOTHEDGES (Default) + * 1 0 0 IOPORT_SENSE_FALLING + * 1 0 1 IOPORT_SENSE_RISING + * 1 1 0 IOPORT_SENSE_LEVEL_LOW + * 1 1 1 IOPORT_SENSE_LEVEL_HIGH + */ + switch(pin_sense) { + case IOPORT_SENSE_LEVEL_LOW: + base->PIO_LSR = mask; + base->PIO_FELLSR = mask; + break; + case IOPORT_SENSE_LEVEL_HIGH: + base->PIO_LSR = mask; + base->PIO_REHLSR = mask; + break; + case IOPORT_SENSE_FALLING: + base->PIO_ESR = mask; + base->PIO_FELLSR = mask; + break; + case IOPORT_SENSE_RISING: + base->PIO_ESR = mask; + base->PIO_REHLSR = mask; + break; + default: + base->PIO_AIMDR = mask; + return; + } + base->PIO_AIMER = mask; +} + +__always_inline static void arch_ioport_set_pin_sense_mode(ioport_pin_t pin, + enum ioport_sense pin_sense) +{ + arch_ioport_set_port_sense_mode(arch_ioport_pin_to_port_id(pin), + arch_ioport_pin_to_mask(pin), pin_sense); +} + +#endif /* IOPORT_SAM_H */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/serial/sam_uart/uart_serial.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/serial/sam_uart/uart_serial.h new file mode 100644 index 0000000..e990f0a --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/serial/sam_uart/uart_serial.h @@ -0,0 +1,682 @@ +/** + * \file + * + * \brief Uart Serial for SAM. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#ifndef _UART_SERIAL_H_ +#define _UART_SERIAL_H_ + +#include "compiler.h" +#include "sysclk.h" +#if (SAMG55) +#include "flexcom.h" +#endif +#if ((!SAM4L) && (!SAMG55)) +#include "uart.h" +#endif +#include "usart.h" + +/** + * \name Serial Management Configuration + */ +//! @{ +#include "conf_uart_serial.h" + +//! @} + +/** Input parameters when initializing RS232 and similar modes. */ +typedef struct uart_rs232_options { + /** Set baud rate of the USART (unused in slave modes). */ + uint32_t baudrate; + + /** Number of bits to transmit as a character (5-bit to 9-bit). */ + uint32_t charlength; + + /** + * Parity type: USART_PMODE_DISABLED_gc, USART_PMODE_EVEN_gc, + * USART_PMODE_ODD_gc. + */ + uint32_t paritytype; + + /** 1, 1.5 or 2 stop bits. */ + uint32_t stopbits; + +} usart_rs232_options_t; + +typedef usart_rs232_options_t usart_serial_options_t; + +typedef Usart *usart_if; + +/** + * \brief Initializes the Usart in master mode. + * + * \param p_usart Base address of the USART instance. + * \param opt Options needed to set up RS232 communication (see + * \ref usart_options_t). + */ +static inline void usart_serial_init(usart_if p_usart, + usart_serial_options_t *opt) +{ +#if ((!SAM4L) && (!SAMG55)) + sam_uart_opt_t uart_settings; + uart_settings.ul_mck = sysclk_get_peripheral_hz(); + uart_settings.ul_baudrate = opt->baudrate; + uart_settings.ul_mode = opt->paritytype; +#endif + + sam_usart_opt_t usart_settings; + usart_settings.baudrate = opt->baudrate; + usart_settings.char_length = opt->charlength; + usart_settings.parity_type = opt->paritytype; + usart_settings.stop_bits= opt->stopbits; + usart_settings.channel_mode= US_MR_CHMODE_NORMAL; + +#ifdef UART + if (UART == (Uart*)p_usart) { + sysclk_enable_peripheral_clock(ID_UART); + /* Configure UART */ + uart_init((Uart*)p_usart, &uart_settings); + } +#else +# ifdef UART0 + if (UART0 == (Uart*)p_usart) { + sysclk_enable_peripheral_clock(ID_UART0); + /* Configure UART */ + uart_init((Uart*)p_usart, &uart_settings); + } +# endif +# ifdef UART1 + if (UART1 == (Uart*)p_usart) { + sysclk_enable_peripheral_clock(ID_UART1); + /* Configure UART */ + uart_init((Uart*)p_usart, &uart_settings); + } +# endif +# ifdef UART2 + if (UART2 == (Uart*)p_usart) { + sysclk_enable_peripheral_clock(ID_UART2); + /* Configure UART */ + uart_init((Uart*)p_usart, &uart_settings); + } +# endif +# ifdef UART3 + if (UART3 == (Uart*)p_usart) { + sysclk_enable_peripheral_clock(ID_UART3); + /* Configure UART */ + uart_init((Uart*)p_usart, &uart_settings); + } +# endif +#endif /* ifdef UART */ + + +#ifdef USART + if (USART == p_usart) { +#if (!SAM4L) + sysclk_enable_peripheral_clock(ID_USART); + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_hz()); +#endif +#if (SAM4L) + sysclk_enable_peripheral_clock(p_usart); + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_bus_hz(p_usart)); +#endif + /* Enable the receiver and transmitter. */ + usart_enable_tx(p_usart); + usart_enable_rx(p_usart); + } +#else +# ifdef USART0 + if (USART0 == p_usart) { +#if (!SAM4L) +#if (SAMG55) + flexcom_enable(FLEXCOM0); + flexcom_set_opmode(FLEXCOM0, FLEXCOM_USART); +#else + sysclk_enable_peripheral_clock(ID_USART0); +#endif + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_hz()); +#endif +#if (SAM4L) + sysclk_enable_peripheral_clock(p_usart); + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_bus_hz(p_usart)); +#endif + /* Enable the receiver and transmitter. */ + usart_enable_tx(p_usart); + usart_enable_rx(p_usart); + } +# endif +# ifdef USART1 + if (USART1 == p_usart) { +#if (!SAM4L) +#if (SAMG55) + flexcom_enable(FLEXCOM1); + flexcom_set_opmode(FLEXCOM1, FLEXCOM_USART); +#else + sysclk_enable_peripheral_clock(ID_USART1); +#endif + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_hz()); +#endif +#if (SAM4L) + sysclk_enable_peripheral_clock(p_usart); + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_bus_hz(p_usart)); +#endif + /* Enable the receiver and transmitter. */ + usart_enable_tx(p_usart); + usart_enable_rx(p_usart); + } +# endif +# ifdef USART2 + if (USART2 == p_usart) { +#if (!SAM4L) +#if (SAMG55) + flexcom_enable(FLEXCOM2); + flexcom_set_opmode(FLEXCOM2, FLEXCOM_USART); +#else + sysclk_enable_peripheral_clock(ID_USART2); +#endif + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_hz()); +#endif +#if (SAM4L) + sysclk_enable_peripheral_clock(p_usart); + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_bus_hz(p_usart)); +#endif + /* Enable the receiver and transmitter. */ + usart_enable_tx(p_usart); + usart_enable_rx(p_usart); + } +# endif +# ifdef USART3 + if (USART3 == p_usart) { +#if (!SAM4L) +#if (SAMG55) + flexcom_enable(FLEXCOM3); + flexcom_set_opmode(FLEXCOM3, FLEXCOM_USART); +#else + sysclk_enable_peripheral_clock(ID_USART3); +#endif + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_hz()); +#endif +#if (SAM4L) + sysclk_enable_peripheral_clock(p_usart); + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_bus_hz(p_usart)); +#endif + /* Enable the receiver and transmitter. */ + usart_enable_tx(p_usart); + usart_enable_rx(p_usart); + } +# endif +# ifdef USART4 + if (USART4 == p_usart) { +#if (!SAM4L) +#if (SAMG55) + flexcom_enable(FLEXCOM4); + flexcom_set_opmode(FLEXCOM4, FLEXCOM_USART); +#else + sysclk_enable_peripheral_clock(ID_USART4); +#endif + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_hz()); +#endif +#if (SAM4L) + sysclk_enable_peripheral_clock(p_usart); + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_bus_hz(p_usart)); +#endif + /* Enable the receiver and transmitter. */ + usart_enable_tx(p_usart); + usart_enable_rx(p_usart); + } +# endif +# ifdef USART5 + if (USART5 == p_usart) { +#if (!SAM4L) +#if (SAMG55) + flexcom_enable(FLEXCOM5); + flexcom_set_opmode(FLEXCOM5, FLEXCOM_USART); +#else + sysclk_enable_peripheral_clock(ID_USART5); +#endif + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_hz()); +#endif +#if (SAM4L) + sysclk_enable_peripheral_clock(p_usart); + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_bus_hz(p_usart)); +#endif + /* Enable the receiver and transmitter. */ + usart_enable_tx(p_usart); + usart_enable_rx(p_usart); + } +# endif +# ifdef USART6 + if (USART6 == p_usart) { +#if (!SAM4L) +#if (SAMG55) + flexcom_enable(FLEXCOM6); + flexcom_set_opmode(FLEXCOM6, FLEXCOM_USART); +#else + sysclk_enable_peripheral_clock(ID_USART6); +#endif + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_hz()); +#endif +#if (SAM4L) + sysclk_enable_peripheral_clock(p_usart); + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_bus_hz(p_usart)); +#endif + /* Enable the receiver and transmitter. */ + usart_enable_tx(p_usart); + usart_enable_rx(p_usart); + } +# endif +# ifdef USART7 + if (USART7 == p_usart) { +#if (!SAM4L) +#if (SAMG55) + flexcom_enable(FLEXCOM7); + flexcom_set_opmode(FLEXCOM7, FLEXCOM_USART); +#else + sysclk_enable_peripheral_clock(ID_USART7); +#endif + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_hz()); +#endif +#if (SAM4L) + sysclk_enable_peripheral_clock(p_usart); + /* Configure USART */ + usart_init_rs232(p_usart, &usart_settings, + sysclk_get_peripheral_bus_hz(p_usart)); +#endif + /* Enable the receiver and transmitter. */ + usart_enable_tx(p_usart); + usart_enable_rx(p_usart); + } +# endif + +#endif /* ifdef USART */ + +} + +/** + * \brief Sends a character with the USART. + * + * \param p_usart Base address of the USART instance. + * \param c Character to write. + * + * \return Status. + * \retval 1 The character was written. + * \retval 0 The function timed out before the USART transmitter became + * ready to send. + */ +static inline int usart_serial_putchar(usart_if p_usart, const uint8_t c) +{ +#ifdef UART + if (UART == (Uart*)p_usart) { + while (uart_write((Uart*)p_usart, c)!=0); + return 1; + } +#else +# ifdef UART0 + if (UART0 == (Uart*)p_usart) { + while (uart_write((Uart*)p_usart, c)!=0); + return 1; + } +# endif +# ifdef UART1 + if (UART1 == (Uart*)p_usart) { + while (uart_write((Uart*)p_usart, c)!=0); + return 1; + } +# endif +# ifdef UART2 + if (UART2 == (Uart*)p_usart) { + while (uart_write((Uart*)p_usart, c)!=0); + return 1; + } +# endif +# ifdef UART3 + if (UART3 == (Uart*)p_usart) { + while (uart_write((Uart*)p_usart, c)!=0); + return 1; + } +# endif +#endif /* ifdef UART */ + + +#ifdef USART + if (USART == p_usart) { + while (usart_write(p_usart, c)!=0); + return 1; + } +#else +# ifdef USART0 + if (USART0 == p_usart) { + while (usart_write(p_usart, c)!=0); + return 1; + } +# endif +# ifdef USART1 + if (USART1 == p_usart) { + while (usart_write(p_usart, c)!=0); + return 1; + } +# endif +# ifdef USART2 + if (USART2 == p_usart) { + while (usart_write(p_usart, c)!=0); + return 1; + } +# endif +# ifdef USART3 + if (USART3 == p_usart) { + while (usart_write(p_usart, c)!=0); + return 1; + } +# endif +# ifdef USART4 + if (USART4 == p_usart) { + while (usart_write(p_usart, c)!=0); + return 1; + } +# endif +# ifdef USART5 + if (USART5 == p_usart) { + while (usart_write(p_usart, c)!=0); + return 1; + } +# endif +# ifdef USART6 + if (USART6 == p_usart) { + while (usart_write(p_usart, c)!=0); + return 1; + } +# endif +# ifdef USART7 + if (USART7 == p_usart) { + while (usart_write(p_usart, c)!=0); + return 1; + } +# endif +#endif /* ifdef USART */ + + return 0; +} +/** + * \brief Waits until a character is received, and returns it. + * + * \param p_usart Base address of the USART instance. + * \param data Data to read + * + */ +static inline void usart_serial_getchar(usart_if p_usart, uint8_t *data) +{ + uint32_t val = 0; + + /* Avoid Cppcheck Warning */ + UNUSED(val); + +#ifdef UART + if (UART == (Uart*)p_usart) { + while (uart_read((Uart*)p_usart, data)); + } +#else +# ifdef UART0 + if (UART0 == (Uart*)p_usart) { + while (uart_read((Uart*)p_usart, data)); + } +# endif +# ifdef UART1 + if (UART1 == (Uart*)p_usart) { + while (uart_read((Uart*)p_usart, data)); + } +# endif +# ifdef UART2 + if (UART2 == (Uart*)p_usart) { + while (uart_read((Uart*)p_usart, data)); + } +# endif +# ifdef UART3 + if (UART3 == (Uart*)p_usart) { + while (uart_read((Uart*)p_usart, data)); + } +# endif +#endif /* ifdef UART */ + + +#ifdef USART + if (USART == p_usart) { + while (usart_read(p_usart, &val)); + *data = (uint8_t)(val & 0xFF); + } +#else +# ifdef USART0 + if (USART0 == p_usart) { + while (usart_read(p_usart, &val)); + *data = (uint8_t)(val & 0xFF); + } +# endif +# ifdef USART1 + if (USART1 == p_usart) { + while (usart_read(p_usart, &val)); + *data = (uint8_t)(val & 0xFF); + } +# endif +# ifdef USART2 + if (USART2 == p_usart) { + while (usart_read(p_usart, &val)); + *data = (uint8_t)(val & 0xFF); + } +# endif +# ifdef USART3 + if (USART3 == p_usart) { + while (usart_read(p_usart, &val)); + *data = (uint8_t)(val & 0xFF); + } +# endif +# ifdef USART4 + if (USART4 == p_usart) { + while (usart_read(p_usart, &val)); + *data = (uint8_t)(val & 0xFF); + } +# endif +# ifdef USART5 + if (USART5 == p_usart) { + while (usart_read(p_usart, &val)); + *data = (uint8_t)(val & 0xFF); + } +# endif +# ifdef USART6 + if (USART6 == p_usart) { + while (usart_read(p_usart, &val)); + *data = (uint8_t)(val & 0xFF); + } +# endif +# ifdef USART7 + if (USART7 == p_usart) { + while (usart_read(p_usart, &val)); + *data = (uint8_t)(val & 0xFF); + } +# endif +#endif /* ifdef USART */ + +} + +/** + * \brief Check if Received data is ready. + * + * \param p_usart Base address of the USART instance. + * + * \retval 1 One data has been received. + * \retval 0 No data has been received. + */ +static inline uint32_t usart_serial_is_rx_ready(usart_if p_usart) +{ +#ifdef UART + if (UART == (Uart*)p_usart) { + return uart_is_rx_ready((Uart*)p_usart); + } +#else +# ifdef UART0 + if (UART0 == (Uart*)p_usart) { + return uart_is_rx_ready((Uart*)p_usart); + } +# endif +# ifdef UART1 + if (UART1 == (Uart*)p_usart) { + return uart_is_rx_ready((Uart*)p_usart); + } +# endif +# ifdef UART2 + if (UART2 == (Uart*)p_usart) { + return uart_is_rx_ready((Uart*)p_usart); + } +# endif +# ifdef UART3 + if (UART3 == (Uart*)p_usart) { + return uart_is_rx_ready((Uart*)p_usart); + } +# endif +#endif /* ifdef UART */ + + +#ifdef USART + if (USART == p_usart) { + return usart_is_rx_ready(p_usart); + } +#else +# ifdef USART0 + if (USART0 == p_usart) { + return usart_is_rx_ready(p_usart); + } +# endif +# ifdef USART1 + if (USART1 == p_usart) { + return usart_is_rx_ready(p_usart); + } +# endif +# ifdef USART2 + if (USART2 == p_usart) { + return usart_is_rx_ready(p_usart); + } +# endif +# ifdef USART3 + if (USART3 == p_usart) { + return usart_is_rx_ready(p_usart); + } +# endif +# ifdef USART4 + if (USART4 == p_usart) { + return usart_is_rx_ready(p_usart); + } +# endif +# ifdef USART5 + if (USART5 == p_usart) { + return usart_is_rx_ready(p_usart); + } +# endif +# ifdef USART6 + if (USART6 == p_usart) { + return usart_is_rx_ready(p_usart); + } +# endif +# ifdef USART7 + if (USART7 == p_usart) { + return usart_is_rx_ready(p_usart); + } +# endif +#endif /* ifdef USART */ + + return 0; +} + +/** + * \brief Send a sequence of bytes to a USART device + * + * \param usart Base address of the USART instance. + * \param data data buffer to write + * \param len Length of data + * + */ +status_code_t usart_serial_write_packet(usart_if usart, const uint8_t *data, + size_t len); + +/** + * \brief Receive a sequence of bytes to a USART device + * + * \param usart Base address of the USART instance. + * \param data data buffer to write + * \param len Length of data + * + */ +status_code_t usart_serial_read_packet(usart_if usart, uint8_t *data, + size_t len); + +#endif /* _UART_SERIAL_H_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/serial/serial.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/serial/serial.h new file mode 100644 index 0000000..df0ae23 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/serial/serial.h @@ -0,0 +1,279 @@ +/** + * \file + * + * \brief Serial Mode management + * + * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#ifndef SERIAL_H_INCLUDED +#define SERIAL_H_INCLUDED + +#include +#include "status_codes.h" + +/** + * \typedef usart_if + * + * This type can be used independently to refer to USART module for the + * architecture used. It refers to the correct type definition for the + * architecture, ie. USART_t* for XMEGA or avr32_usart_t* for UC3. + */ + +#if XMEGA +# include "xmega_usart/usart_serial.h" +#elif MEGA_RF +# include "megarf_usart/usart_serial.h" +#elif UC3 +# include "uc3_usart/usart_serial.h" +#elif (SAMB) +#include "samb_uart/uart_serial.h" +#elif (SAM0) +#include "sam0_usart/usart_serial.h" +#elif SAM +# include "sam_uart/uart_serial.h" +#else +# error Unsupported chip type +#endif + +/** + * + * \defgroup serial_group Serial Interface (Serial) + * + * See \ref serial_quickstart. + * + * This is the common API for serial interface. Additional features are available + * in the documentation of the specific modules. + * + * \section serial_group_platform Platform Dependencies + * + * The serial API is partially chip- or platform-specific. While all + * platforms provide mostly the same functionality, there are some + * variations around how different bus types and clock tree structures + * are handled. + * + * The following functions are available on all platforms, but there may + * be variations in the function signature (i.e. parameters) and + * behaviour. These functions are typically called by platform-specific + * parts of drivers, and applications that aren't intended to be + * portable: + * - usart_serial_init() + * - usart_serial_putchar() + * - usart_serial_getchar() + * - usart_serial_write_packet() + * - usart_serial_read_packet() + * + * + * @{ + */ + +//! @} + +/** + * \page serial_quickstart Quick start guide for Serial Interface service + * + * This is the quick start guide for the \ref serial_group "Serial Interface module", with + * step-by-step instructions on how to configure and use the serial in a + * selection of use cases. + * + * The use cases contain several code fragments. The code fragments in the + * steps for setup can be copied into a custom initialization function, while + * the steps for usage can be copied into, e.g., the main application function. + * + * \section serial_use_cases Serial use cases + * - \ref serial_basic_use_case + * - \subpage serial_use_case_1 + * + * \section serial_basic_use_case Basic use case - transmit a character + * In this use case, the serial module is configured for: + * - Using USARTD0 + * - Baudrate: 9600 + * - Character length: 8 bit + * - Parity mode: Disabled + * - Stop bit: None + * - RS232 mode + * + * The use case waits for a received character on the configured USART and + * echoes the character back to the same USART. + * + * \section serial_basic_use_case_setup Setup steps + * + * \subsection serial_basic_use_case_setup_prereq Prerequisites + * -# \ref sysclk_group "System Clock Management (sysclk)" + * + * \subsection serial_basic_use_case_setup_code Example code + * The following configuration must be added to the project (typically to a + * conf_uart_serial.h file, but it can also be added to your main application file.) + * + * \note The following takes SAM3X configuration for example, other devices have similar + * configuration, but their parameters may be different, refer to corresponding header files. + * + * \code + #define USART_SERIAL &USARTD0 + #define USART_SERIAL_BAUDRATE 9600 + #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT + #define USART_SERIAL_PARITY US_MR_PAR_NO + #define USART_SERIAL_STOP_BIT false +\endcode + * + * A variable for the received byte must be added: + * \code uint8_t received_byte; \endcode + * + * Add to application initialization: + * \code + sysclk_init(); + + static usart_serial_options_t usart_options = { + .baudrate = USART_SERIAL_BAUDRATE, + .charlength = USART_SERIAL_CHAR_LENGTH, + .paritytype = USART_SERIAL_PARITY, + .stopbits = USART_SERIAL_STOP_BIT + }; + + usart_serial_init(USART_SERIAL, &usart_options); +\endcode + * + * \subsection serial_basic_use_case_setup_flow Workflow + * -# Initialize system clock: + * - \code sysclk_init(); \endcode + * -# Create serial USART options struct: + * - \code + static usart_serial_options_t usart_options = { + .baudrate = USART_SERIAL_BAUDRATE, + .charlength = USART_SERIAL_CHAR_LENGTH, + .paritytype = USART_SERIAL_PARITY, + .stopbits = USART_SERIAL_STOP_BIT + }; +\endcode + * -# Initialize the serial service: + * - \code usart_serial_init(USART_SERIAL, &usart_options);\endcode + * + * \section serial_basic_use_case_usage Usage steps + * + * \subsection serial_basic_use_case_usage_code Example code + * Add to application C-file: + * \code + usart_serial_getchar(USART_SERIAL, &received_byte); + usart_serial_putchar(USART_SERIAL, received_byte); +\endcode + * + * \subsection serial_basic_use_case_usage_flow Workflow + * -# Wait for reception of a character: + * - \code usart_serial_getchar(USART_SERIAL, &received_byte); \endcode + * -# Echo the character back: + * - \code usart_serial_putchar(USART_SERIAL, received_byte); \endcode + */ + +/** + * \page serial_use_case_1 Advanced use case - Send a packet of serial data + * + * In this use case, the USART module is configured for: + * - Using USARTD0 + * - Baudrate: 9600 + * - Character length: 8 bit + * - Parity mode: Disabled + * - Stop bit: None + * - RS232 mode + * + * The use case sends a string of text through the USART. + * + * \section serial_use_case_1_setup Setup steps + * + * \subsection serial_use_case_1_setup_prereq Prerequisites + * -# \ref sysclk_group "System Clock Management (sysclk)" + * + * \subsection serial_use_case_1_setup_code Example code + * The following configuration must be added to the project (typically to a + * conf_uart_serial.h file, but it can also be added to your main application file.): + * + * \note The following takes SAM3X configuration for example, other devices have similar + * configuration, but their parameters may be different, refer to corresponding header files. + * + * \code + #define USART_SERIAL &USARTD0 + #define USART_SERIAL_BAUDRATE 9600 + #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT + #define USART_SERIAL_PARITY US_MR_PAR_NO + #define USART_SERIAL_STOP_BIT false +\endcode + * + * Add to application initialization: + * \code + sysclk_init(); + + static usart_serial_options_t usart_options = { + .baudrate = USART_SERIAL_BAUDRATE, + .charlength = USART_SERIAL_CHAR_LENGTH, + .paritytype = USART_SERIAL_PARITY, + .stopbits = USART_SERIAL_STOP_BIT + }; + + usart_serial_init(USART_SERIAL, &usart_options); +\endcode + * + * \subsection serial_use_case_1_setup_flow Workflow + * -# Initialize system clock: + * - \code sysclk_init(); \endcode + * -# Create USART options struct: + * - \code + static usart_serial_options_t usart_options = { + .baudrate = USART_SERIAL_BAUDRATE, + .charlength = USART_SERIAL_CHAR_LENGTH, + .paritytype = USART_SERIAL_PARITY, + .stopbits = USART_SERIAL_STOP_BIT + }; +\endcode + * -# Initialize in RS232 mode: + * - \code usart_serial_init(USART_SERIAL_EXAMPLE, &usart_options); \endcode + * + * \section serial_use_case_1_usage Usage steps + * + * \subsection serial_use_case_1_usage_code Example code + * Add to, e.g., main loop in application C-file: + * \code + usart_serial_write_packet(USART_SERIAL, "Test String", strlen("Test String")); +\endcode + * + * \subsection serial_use_case_1_usage_flow Workflow + * -# Write a string of text to the USART: + * - \code usart_serial_write_packet(USART_SERIAL, "Test String", strlen("Test String")); \endcode + */ + +#endif /* SERIAL_H_INCLUDED */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/serial/usart_serial.c b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/serial/usart_serial.c new file mode 100644 index 0000000..c67c256 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/services/serial/usart_serial.c @@ -0,0 +1,87 @@ +/** + * + * \file + * + * \brief USART Serial driver functions. + * + * + * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#include "serial.h" + +/** + * \brief Send a sequence of bytes to USART device + * + * \param usart Base address of the USART instance. + * \param data Data buffer to read + * \param len Length of data + * + */ +status_code_t usart_serial_write_packet(usart_if usart, const uint8_t *data, + size_t len) +{ + while (len) { + usart_serial_putchar(usart, *data); + len--; + data++; + } + return STATUS_OK; +} + + +/** + * \brief Receive a sequence of bytes from USART device + * + * \param usart Base address of the USART instance. + * \param data Data buffer to write + * \param len Length of data + * + */ +status_code_t usart_serial_read_packet(usart_if usart, uint8_t *data, + size_t len) +{ + while (len) { + usart_serial_getchar(usart, data); + len--; + data++; + } + return STATUS_OK; +} diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/utils/interrupt.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/utils/interrupt.h new file mode 100644 index 0000000..288d782 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/utils/interrupt.h @@ -0,0 +1,142 @@ +/** + * \file + * + * \brief Global interrupt management for 8- and 32-bit AVR + * + * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#ifndef UTILS_INTERRUPT_H +#define UTILS_INTERRUPT_H + +#include + +#if XMEGA || MEGA || TINY +# include "interrupt/interrupt_avr8.h" +#elif UC3 +# include "interrupt/interrupt_avr32.h" +#elif SAM || SAMB +# include "interrupt/interrupt_sam_nvic.h" +#else +# error Unsupported device. +#endif + +/** + * \defgroup interrupt_group Global interrupt management + * + * This is a driver for global enabling and disabling of interrupts. + * + * @{ + */ + +#if defined(__DOXYGEN__) +/** + * \def CONFIG_INTERRUPT_FORCE_INTC + * \brief Force usage of the ASF INTC driver + * + * Predefine this symbol when preprocessing to force the use of the ASF INTC driver. + * This is useful to ensure compatibility across compilers and shall be used only when required + * by the application needs. + */ +# define CONFIG_INTERRUPT_FORCE_INTC +#endif + +//! \name Global interrupt flags +//@{ +/** + * \typedef irqflags_t + * \brief Type used for holding state of interrupt flag + */ + +/** + * \def cpu_irq_enable + * \brief Enable interrupts globally + */ + +/** + * \def cpu_irq_disable + * \brief Disable interrupts globally + */ + +/** + * \fn irqflags_t cpu_irq_save(void) + * \brief Get and clear the global interrupt flags + * + * Use in conjunction with \ref cpu_irq_restore. + * + * \return Current state of interrupt flags. + * + * \note This function leaves interrupts disabled. + */ + +/** + * \fn void cpu_irq_restore(irqflags_t flags) + * \brief Restore global interrupt flags + * + * Use in conjunction with \ref cpu_irq_save. + * + * \param flags State to set interrupt flag to. + */ + +/** + * \fn bool cpu_irq_is_enabled_flags(irqflags_t flags) + * \brief Check if interrupts are globally enabled in supplied flags + * + * \param flags Currents state of interrupt flags. + * + * \return True if interrupts are enabled. + */ + +/** + * \def cpu_irq_is_enabled + * \brief Check if interrupts are globally enabled + * + * \return True if interrupts are enabled. + */ +//@} + +//! @} + +/** + * \ingroup interrupt_group + * \defgroup interrupt_deprecated_group Deprecated interrupt definitions + */ + +#endif /* UTILS_INTERRUPT_H */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/utils/interrupt/interrupt_sam_nvic.c b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/utils/interrupt/interrupt_sam_nvic.c new file mode 100644 index 0000000..26dcc91 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/utils/interrupt/interrupt_sam_nvic.c @@ -0,0 +1,86 @@ +/** + * \file + * + * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based) + * + * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#include "interrupt_sam_nvic.h" + +#if !defined(__DOXYGEN__) +/* Deprecated - global flag to determine the global interrupt state. Required by + * QTouch library, however new applications should use cpu_irq_is_enabled() + * which probes the true global interrupt state from the CPU special registers. + */ +volatile bool g_interrupt_enabled = true; +#endif + +void cpu_irq_enter_critical(void) +{ + if (cpu_irq_critical_section_counter == 0) { + if (cpu_irq_is_enabled()) { + cpu_irq_disable(); + cpu_irq_prev_interrupt_state = true; + } else { + /* Make sure the to save the prev state as false */ + cpu_irq_prev_interrupt_state = false; + } + + } + + cpu_irq_critical_section_counter++; +} + +void cpu_irq_leave_critical(void) +{ + /* Check if the user is trying to leave a critical section when not in a critical section */ + Assert(cpu_irq_critical_section_counter > 0); + + cpu_irq_critical_section_counter--; + + /* Only enable global interrupts when the counter reaches 0 and the state of the global interrupt flag + was enabled when entering critical state */ + if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) { + cpu_irq_enable(); + } +} + diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/utils/interrupt/interrupt_sam_nvic.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/utils/interrupt/interrupt_sam_nvic.h new file mode 100644 index 0000000..f996e92 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/utils/interrupt/interrupt_sam_nvic.h @@ -0,0 +1,189 @@ +/** + * \file + * + * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based) + * + * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef UTILS_INTERRUPT_INTERRUPT_H +#define UTILS_INTERRUPT_INTERRUPT_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \weakgroup interrupt_group + * + * @{ + */ + +/** + * \name Interrupt Service Routine definition + * + * @{ + */ + +/** + * \brief Define service routine + * + * \note For NVIC devices the interrupt service routines are predefined to + * add to vector table in binary generation, so there is no service + * register at run time. The routine collections are in exceptions.h. + * + * Usage: + * \code + ISR(foo_irq_handler) + { + // Function definition + ... + } +\endcode + * + * \param func Name for the function. + */ +# define ISR(func) \ + void func (void) + +/** + * \brief Initialize interrupt vectors + * + * For NVIC the interrupt vectors are put in vector table. So nothing + * to do to initialize them, except defined the vector function with + * right name. + * + * This must be called prior to \ref irq_register_handler. + */ +# define irq_initialize_vectors() \ + do { \ + } while(0) + +/** + * \brief Register handler for interrupt + * + * For NVIC the interrupt vectors are put in vector table. So nothing + * to do to register them, except defined the vector function with + * right name. + * + * Usage: + * \code + irq_initialize_vectors(); + irq_register_handler(foo_irq_handler); +\endcode + * + * \note The function \a func must be defined with the \ref ISR macro. + * \note The functions prototypes can be found in the device exception header + * files (exceptions.h). + */ +# define irq_register_handler(int_num, int_prio) \ + NVIC_ClearPendingIRQ( (IRQn_Type)int_num); \ + NVIC_SetPriority( (IRQn_Type)int_num, int_prio); \ + NVIC_EnableIRQ( (IRQn_Type)int_num); \ + +//@} + +# define cpu_irq_enable() \ + do { \ + g_interrupt_enabled = true; \ + __DMB(); \ + __enable_irq(); \ + } while (0) +# define cpu_irq_disable() \ + do { \ + __disable_irq(); \ + __DMB(); \ + g_interrupt_enabled = false; \ + } while (0) + +typedef uint32_t irqflags_t; + +#if !defined(__DOXYGEN__) +extern volatile bool g_interrupt_enabled; +#endif + +#define cpu_irq_is_enabled() (__get_PRIMASK() == 0) + +static volatile uint32_t cpu_irq_critical_section_counter; +static volatile bool cpu_irq_prev_interrupt_state; + +static inline irqflags_t cpu_irq_save(void) +{ + irqflags_t flags = cpu_irq_is_enabled(); + cpu_irq_disable(); + return flags; +} + +static inline bool cpu_irq_is_enabled_flags(irqflags_t flags) +{ + return (flags); +} + +static inline void cpu_irq_restore(irqflags_t flags) +{ + if (cpu_irq_is_enabled_flags(flags)) + cpu_irq_enable(); +} + +void cpu_irq_enter_critical(void); +void cpu_irq_leave_critical(void); + +/** + * \weakgroup interrupt_deprecated_group + * @{ + */ + +#define Enable_global_interrupt() cpu_irq_enable() +#define Disable_global_interrupt() cpu_irq_disable() +#define Is_global_interrupt_enabled() cpu_irq_is_enabled() + +//@} + +//@} + +#ifdef __cplusplus +} +#endif + +#endif /* UTILS_INTERRUPT_INTERRUPT_H */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/utils/parts.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/utils/parts.h new file mode 100644 index 0000000..7f89395 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/utils/parts.h @@ -0,0 +1,1631 @@ +/** + * \file + * + * \brief Atmel part identification macros + * + * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef ATMEL_PARTS_H +#define ATMEL_PARTS_H + +/** + * \defgroup part_macros_group Atmel part identification macros + * + * This collection of macros identify which series and families that the various + * Atmel parts belong to. These can be used to select part-dependent sections of + * code at compile time. + * + * @{ + */ + +/** + * \name Convenience macros for part checking + * @{ + */ +/* ! Check GCC and IAR part definition for 8-bit AVR */ +#define AVR8_PART_IS_DEFINED(part) \ + (defined(__ ## part ## __) || defined(__AVR_ ## part ## __)) + +/* ! Check GCC and IAR part definition for 32-bit AVR */ +#define AVR32_PART_IS_DEFINED(part) \ + (defined(__AT32 ## part ## __) || defined(__AVR32_ ## part ## __)) + +/* ! Check GCC and IAR part definition for SAM */ +#define SAM_PART_IS_DEFINED(part) (defined(__ ## part ## __)) +/** @} */ + +/** + * \defgroup uc3_part_macros_group AVR UC3 parts + * @{ + */ + +/** + * \name AVR UC3 A series + * @{ + */ +#define UC3A0 ( \ + AVR32_PART_IS_DEFINED(UC3A0128) || \ + AVR32_PART_IS_DEFINED(UC3A0256) || \ + AVR32_PART_IS_DEFINED(UC3A0512) \ + ) + +#define UC3A1 ( \ + AVR32_PART_IS_DEFINED(UC3A1128) || \ + AVR32_PART_IS_DEFINED(UC3A1256) || \ + AVR32_PART_IS_DEFINED(UC3A1512) \ + ) + +#define UC3A3 ( \ + AVR32_PART_IS_DEFINED(UC3A364) || \ + AVR32_PART_IS_DEFINED(UC3A364S) || \ + AVR32_PART_IS_DEFINED(UC3A3128) || \ + AVR32_PART_IS_DEFINED(UC3A3128S) || \ + AVR32_PART_IS_DEFINED(UC3A3256) || \ + AVR32_PART_IS_DEFINED(UC3A3256S) \ + ) + +#define UC3A4 ( \ + AVR32_PART_IS_DEFINED(UC3A464) || \ + AVR32_PART_IS_DEFINED(UC3A464S) || \ + AVR32_PART_IS_DEFINED(UC3A4128) || \ + AVR32_PART_IS_DEFINED(UC3A4128S) || \ + AVR32_PART_IS_DEFINED(UC3A4256) || \ + AVR32_PART_IS_DEFINED(UC3A4256S) \ + ) +/** @} */ + +/** + * \name AVR UC3 B series + * @{ + */ +#define UC3B0 ( \ + AVR32_PART_IS_DEFINED(UC3B064) || \ + AVR32_PART_IS_DEFINED(UC3B0128) || \ + AVR32_PART_IS_DEFINED(UC3B0256) || \ + AVR32_PART_IS_DEFINED(UC3B0512) \ + ) + +#define UC3B1 ( \ + AVR32_PART_IS_DEFINED(UC3B164) || \ + AVR32_PART_IS_DEFINED(UC3B1128) || \ + AVR32_PART_IS_DEFINED(UC3B1256) || \ + AVR32_PART_IS_DEFINED(UC3B1512) \ + ) +/** @} */ + +/** + * \name AVR UC3 C series + * @{ + */ +#define UC3C0 ( \ + AVR32_PART_IS_DEFINED(UC3C064C) || \ + AVR32_PART_IS_DEFINED(UC3C0128C) || \ + AVR32_PART_IS_DEFINED(UC3C0256C) || \ + AVR32_PART_IS_DEFINED(UC3C0512C) \ + ) + +#define UC3C1 ( \ + AVR32_PART_IS_DEFINED(UC3C164C) || \ + AVR32_PART_IS_DEFINED(UC3C1128C) || \ + AVR32_PART_IS_DEFINED(UC3C1256C) || \ + AVR32_PART_IS_DEFINED(UC3C1512C) \ + ) + +#define UC3C2 ( \ + AVR32_PART_IS_DEFINED(UC3C264C) || \ + AVR32_PART_IS_DEFINED(UC3C2128C) || \ + AVR32_PART_IS_DEFINED(UC3C2256C) || \ + AVR32_PART_IS_DEFINED(UC3C2512C) \ + ) +/** @} */ + +/** + * \name AVR UC3 D series + * @{ + */ +#define UC3D3 ( \ + AVR32_PART_IS_DEFINED(UC64D3) || \ + AVR32_PART_IS_DEFINED(UC128D3) \ + ) + +#define UC3D4 ( \ + AVR32_PART_IS_DEFINED(UC64D4) || \ + AVR32_PART_IS_DEFINED(UC128D4) \ + ) +/** @} */ + +/** + * \name AVR UC3 L series + * @{ + */ +#define UC3L0 ( \ + AVR32_PART_IS_DEFINED(UC3L016) || \ + AVR32_PART_IS_DEFINED(UC3L032) || \ + AVR32_PART_IS_DEFINED(UC3L064) \ + ) + +#define UC3L0128 ( \ + AVR32_PART_IS_DEFINED(UC3L0128) \ + ) + +#define UC3L0256 ( \ + AVR32_PART_IS_DEFINED(UC3L0256) \ + ) + +#define UC3L3 ( \ + AVR32_PART_IS_DEFINED(UC64L3U) || \ + AVR32_PART_IS_DEFINED(UC128L3U) || \ + AVR32_PART_IS_DEFINED(UC256L3U) \ + ) + +#define UC3L4 ( \ + AVR32_PART_IS_DEFINED(UC64L4U) || \ + AVR32_PART_IS_DEFINED(UC128L4U) || \ + AVR32_PART_IS_DEFINED(UC256L4U) \ + ) + +#define UC3L3_L4 (UC3L3 || UC3L4) +/** @} */ + +/** + * \name AVR UC3 families + * @{ + */ +/** AVR UC3 A family */ +#define UC3A (UC3A0 || UC3A1 || UC3A3 || UC3A4) + +/** AVR UC3 B family */ +#define UC3B (UC3B0 || UC3B1) + +/** AVR UC3 C family */ +#define UC3C (UC3C0 || UC3C1 || UC3C2) + +/** AVR UC3 D family */ +#define UC3D (UC3D3 || UC3D4) + +/** AVR UC3 L family */ +#define UC3L (UC3L0 || UC3L0128 || UC3L0256 || UC3L3_L4) +/** @} */ + +/** AVR UC3 product line */ +#define UC3 (UC3A || UC3B || UC3C || UC3D || UC3L) + +/** @} */ + +/** + * \defgroup xmega_part_macros_group AVR XMEGA parts + * @{ + */ + +/** + * \name AVR XMEGA A series + * @{ + */ +#define XMEGA_A1 ( \ + AVR8_PART_IS_DEFINED(ATxmega64A1) || \ + AVR8_PART_IS_DEFINED(ATxmega128A1) \ + ) + +#define XMEGA_A3 ( \ + AVR8_PART_IS_DEFINED(ATxmega64A3) || \ + AVR8_PART_IS_DEFINED(ATxmega128A3) || \ + AVR8_PART_IS_DEFINED(ATxmega192A3) || \ + AVR8_PART_IS_DEFINED(ATxmega256A3) \ + ) + +#define XMEGA_A3B ( \ + AVR8_PART_IS_DEFINED(ATxmega256A3B) \ + ) + +#define XMEGA_A4 ( \ + AVR8_PART_IS_DEFINED(ATxmega16A4) || \ + AVR8_PART_IS_DEFINED(ATxmega32A4) \ + ) +/** @} */ + +/** + * \name AVR XMEGA AU series + * @{ + */ +#define XMEGA_A1U ( \ + AVR8_PART_IS_DEFINED(ATxmega64A1U) || \ + AVR8_PART_IS_DEFINED(ATxmega128A1U) \ + ) + +#define XMEGA_A3U ( \ + AVR8_PART_IS_DEFINED(ATxmega64A3U) || \ + AVR8_PART_IS_DEFINED(ATxmega128A3U) || \ + AVR8_PART_IS_DEFINED(ATxmega192A3U) || \ + AVR8_PART_IS_DEFINED(ATxmega256A3U) \ + ) + +#define XMEGA_A3BU ( \ + AVR8_PART_IS_DEFINED(ATxmega256A3BU) \ + ) + +#define XMEGA_A4U ( \ + AVR8_PART_IS_DEFINED(ATxmega16A4U) || \ + AVR8_PART_IS_DEFINED(ATxmega32A4U) || \ + AVR8_PART_IS_DEFINED(ATxmega64A4U) || \ + AVR8_PART_IS_DEFINED(ATxmega128A4U) \ + ) +/** @} */ + +/** + * \name AVR XMEGA B series + * @{ + */ +#define XMEGA_B1 ( \ + AVR8_PART_IS_DEFINED(ATxmega64B1) || \ + AVR8_PART_IS_DEFINED(ATxmega128B1) \ + ) + +#define XMEGA_B3 ( \ + AVR8_PART_IS_DEFINED(ATxmega64B3) || \ + AVR8_PART_IS_DEFINED(ATxmega128B3) \ + ) +/** @} */ + +/** + * \name AVR XMEGA C series + * @{ + */ +#define XMEGA_C3 ( \ + AVR8_PART_IS_DEFINED(ATxmega384C3) || \ + AVR8_PART_IS_DEFINED(ATxmega256C3) || \ + AVR8_PART_IS_DEFINED(ATxmega192C3) || \ + AVR8_PART_IS_DEFINED(ATxmega128C3) || \ + AVR8_PART_IS_DEFINED(ATxmega64C3) || \ + AVR8_PART_IS_DEFINED(ATxmega32C3) \ + ) + +#define XMEGA_C4 ( \ + AVR8_PART_IS_DEFINED(ATxmega32C4) || \ + AVR8_PART_IS_DEFINED(ATxmega16C4) \ + ) +/** @} */ + +/** + * \name AVR XMEGA D series + * @{ + */ +#define XMEGA_D3 ( \ + AVR8_PART_IS_DEFINED(ATxmega32D3) || \ + AVR8_PART_IS_DEFINED(ATxmega64D3) || \ + AVR8_PART_IS_DEFINED(ATxmega128D3) || \ + AVR8_PART_IS_DEFINED(ATxmega192D3) || \ + AVR8_PART_IS_DEFINED(ATxmega256D3) || \ + AVR8_PART_IS_DEFINED(ATxmega384D3) \ + ) + +#define XMEGA_D4 ( \ + AVR8_PART_IS_DEFINED(ATxmega16D4) || \ + AVR8_PART_IS_DEFINED(ATxmega32D4) || \ + AVR8_PART_IS_DEFINED(ATxmega64D4) || \ + AVR8_PART_IS_DEFINED(ATxmega128D4) \ + ) +/** @} */ + +/** + * \name AVR XMEGA E series + * @{ + */ +#define XMEGA_E5 ( \ + AVR8_PART_IS_DEFINED(ATxmega8E5) || \ + AVR8_PART_IS_DEFINED(ATxmega16E5) || \ + AVR8_PART_IS_DEFINED(ATxmega32E5) \ + ) +/** @} */ + + +/** + * \name AVR XMEGA families + * @{ + */ +/** AVR XMEGA A family */ +#define XMEGA_A (XMEGA_A1 || XMEGA_A3 || XMEGA_A3B || XMEGA_A4) + +/** AVR XMEGA AU family */ +#define XMEGA_AU (XMEGA_A1U || XMEGA_A3U || XMEGA_A3BU || XMEGA_A4U) + +/** AVR XMEGA B family */ +#define XMEGA_B (XMEGA_B1 || XMEGA_B3) + +/** AVR XMEGA C family */ +#define XMEGA_C (XMEGA_C3 || XMEGA_C4) + +/** AVR XMEGA D family */ +#define XMEGA_D (XMEGA_D3 || XMEGA_D4) + +/** AVR XMEGA E family */ +#define XMEGA_E (XMEGA_E5) +/** @} */ + + +/** AVR XMEGA product line */ +#define XMEGA (XMEGA_A || XMEGA_AU || XMEGA_B || XMEGA_C || XMEGA_D || XMEGA_E) + +/** @} */ + +/** + * \defgroup mega_part_macros_group megaAVR parts + * + * \note These megaAVR groupings are based on the groups in AVR Libc for the + * part header files. They are not names of official megaAVR device series or + * families. + * + * @{ + */ + +/** + * \name ATmegaxx0/xx1 subgroups + * @{ + */ +#define MEGA_XX0 ( \ + AVR8_PART_IS_DEFINED(ATmega640) || \ + AVR8_PART_IS_DEFINED(ATmega1280) || \ + AVR8_PART_IS_DEFINED(ATmega2560) \ + ) + +#define MEGA_XX1 ( \ + AVR8_PART_IS_DEFINED(ATmega1281) || \ + AVR8_PART_IS_DEFINED(ATmega2561) \ + ) +/** @} */ + +/** + * \name megaAVR groups + * @{ + */ +/** ATmegaxx0/xx1 group */ +#define MEGA_XX0_1 (MEGA_XX0 || MEGA_XX1) + +/** ATmegaxx4 group */ +#define MEGA_XX4 ( \ + AVR8_PART_IS_DEFINED(ATmega164A) || \ + AVR8_PART_IS_DEFINED(ATmega164PA) || \ + AVR8_PART_IS_DEFINED(ATmega324A) || \ + AVR8_PART_IS_DEFINED(ATmega324PA) || \ + AVR8_PART_IS_DEFINED(ATmega324PB) || \ + AVR8_PART_IS_DEFINED(ATmega644) || \ + AVR8_PART_IS_DEFINED(ATmega644A) || \ + AVR8_PART_IS_DEFINED(ATmega644PA) || \ + AVR8_PART_IS_DEFINED(ATmega1284P) || \ + AVR8_PART_IS_DEFINED(ATmega128RFA1) \ + ) + +/** ATmegaxx4 group */ +#define MEGA_XX4_A ( \ + AVR8_PART_IS_DEFINED(ATmega164A) || \ + AVR8_PART_IS_DEFINED(ATmega164PA) || \ + AVR8_PART_IS_DEFINED(ATmega324A) || \ + AVR8_PART_IS_DEFINED(ATmega324PA) || \ + AVR8_PART_IS_DEFINED(ATmega644A) || \ + AVR8_PART_IS_DEFINED(ATmega644PA) || \ + AVR8_PART_IS_DEFINED(ATmega1284P) \ + ) + +/** ATmegaxx8 group */ +#define MEGA_XX8 ( \ + AVR8_PART_IS_DEFINED(ATmega48) || \ + AVR8_PART_IS_DEFINED(ATmega48A) || \ + AVR8_PART_IS_DEFINED(ATmega48PA) || \ + AVR8_PART_IS_DEFINED(ATmega48PB) || \ + AVR8_PART_IS_DEFINED(ATmega88) || \ + AVR8_PART_IS_DEFINED(ATmega88A) || \ + AVR8_PART_IS_DEFINED(ATmega88PA) || \ + AVR8_PART_IS_DEFINED(ATmega88PB) || \ + AVR8_PART_IS_DEFINED(ATmega168) || \ + AVR8_PART_IS_DEFINED(ATmega168A) || \ + AVR8_PART_IS_DEFINED(ATmega168PA) || \ + AVR8_PART_IS_DEFINED(ATmega168PB) || \ + AVR8_PART_IS_DEFINED(ATmega328) || \ + AVR8_PART_IS_DEFINED(ATmega328P) || \ + AVR8_PART_IS_DEFINED(ATmega328PB) \ + ) + +/** ATmegaxx8A/P/PA group */ +#define MEGA_XX8_A ( \ + AVR8_PART_IS_DEFINED(ATmega48A) || \ + AVR8_PART_IS_DEFINED(ATmega48PA) || \ + AVR8_PART_IS_DEFINED(ATmega88A) || \ + AVR8_PART_IS_DEFINED(ATmega88PA) || \ + AVR8_PART_IS_DEFINED(ATmega168A) || \ + AVR8_PART_IS_DEFINED(ATmega168PA) || \ + AVR8_PART_IS_DEFINED(ATmega328P) \ + ) + +/** ATmegaxx group */ +#define MEGA_XX ( \ + AVR8_PART_IS_DEFINED(ATmega16) || \ + AVR8_PART_IS_DEFINED(ATmega16A) || \ + AVR8_PART_IS_DEFINED(ATmega32) || \ + AVR8_PART_IS_DEFINED(ATmega32A) || \ + AVR8_PART_IS_DEFINED(ATmega64) || \ + AVR8_PART_IS_DEFINED(ATmega64A) || \ + AVR8_PART_IS_DEFINED(ATmega128) || \ + AVR8_PART_IS_DEFINED(ATmega128A) \ + ) + +/** ATmegaxxA/P/PA group */ +#define MEGA_XX_A ( \ + AVR8_PART_IS_DEFINED(ATmega16A) || \ + AVR8_PART_IS_DEFINED(ATmega32A) || \ + AVR8_PART_IS_DEFINED(ATmega64A) || \ + AVR8_PART_IS_DEFINED(ATmega128A) \ + ) +/** ATmegaxxRFA1 group */ +#define MEGA_RFA1 ( \ + AVR8_PART_IS_DEFINED(ATmega128RFA1) \ + ) + +/** ATmegaxxRFR2 group */ +#define MEGA_RFR2 ( \ + AVR8_PART_IS_DEFINED(ATmega64RFR2) || \ + AVR8_PART_IS_DEFINED(ATmega128RFR2) || \ + AVR8_PART_IS_DEFINED(ATmega256RFR2) || \ + AVR8_PART_IS_DEFINED(ATmega644RFR2) || \ + AVR8_PART_IS_DEFINED(ATmega1284RFR2) || \ + AVR8_PART_IS_DEFINED(ATmega2564RFR2) \ + ) + + +/** ATmegaxxRFxx group */ +#define MEGA_RF (MEGA_RFA1 || MEGA_RFR2) + +/** + * \name ATmegaxx_un0/un1/un2 subgroups + * @{ + */ +#define MEGA_XX_UN0 ( \ + AVR8_PART_IS_DEFINED(ATmega16) || \ + AVR8_PART_IS_DEFINED(ATmega16A) || \ + AVR8_PART_IS_DEFINED(ATmega32) || \ + AVR8_PART_IS_DEFINED(ATmega32A) \ + ) + +/** ATmegaxx group without power reduction and + * And interrupt sense register. + */ +#define MEGA_XX_UN1 ( \ + AVR8_PART_IS_DEFINED(ATmega64) || \ + AVR8_PART_IS_DEFINED(ATmega64A) || \ + AVR8_PART_IS_DEFINED(ATmega128) || \ + AVR8_PART_IS_DEFINED(ATmega128A) \ + ) + +/** ATmegaxx group without power reduction and + * And interrupt sense register. + */ +#define MEGA_XX_UN2 ( \ + AVR8_PART_IS_DEFINED(ATmega169P) || \ + AVR8_PART_IS_DEFINED(ATmega169PA) || \ + AVR8_PART_IS_DEFINED(ATmega329P) || \ + AVR8_PART_IS_DEFINED(ATmega329PA) \ + ) + +/** Devices added to complete megaAVR offering. + * Please do not use this group symbol as it is not intended + * to be permanent: the devices should be regrouped. + */ +#define MEGA_UNCATEGORIZED ( \ + AVR8_PART_IS_DEFINED(AT90CAN128) || \ + AVR8_PART_IS_DEFINED(AT90CAN32) || \ + AVR8_PART_IS_DEFINED(AT90CAN64) || \ + AVR8_PART_IS_DEFINED(AT90PWM1) || \ + AVR8_PART_IS_DEFINED(AT90PWM216) || \ + AVR8_PART_IS_DEFINED(AT90PWM2B) || \ + AVR8_PART_IS_DEFINED(AT90PWM316) || \ + AVR8_PART_IS_DEFINED(AT90PWM3B) || \ + AVR8_PART_IS_DEFINED(AT90PWM81) || \ + AVR8_PART_IS_DEFINED(AT90USB1286) || \ + AVR8_PART_IS_DEFINED(AT90USB1287) || \ + AVR8_PART_IS_DEFINED(AT90USB162) || \ + AVR8_PART_IS_DEFINED(AT90USB646) || \ + AVR8_PART_IS_DEFINED(AT90USB647) || \ + AVR8_PART_IS_DEFINED(AT90USB82) || \ + AVR8_PART_IS_DEFINED(ATmega1284) || \ + AVR8_PART_IS_DEFINED(ATmega162) || \ + AVR8_PART_IS_DEFINED(ATmega164P) || \ + AVR8_PART_IS_DEFINED(ATmega165A) || \ + AVR8_PART_IS_DEFINED(ATmega165P) || \ + AVR8_PART_IS_DEFINED(ATmega165PA) || \ + AVR8_PART_IS_DEFINED(ATmega168P) || \ + AVR8_PART_IS_DEFINED(ATmega169A) || \ + AVR8_PART_IS_DEFINED(ATmega16M1) || \ + AVR8_PART_IS_DEFINED(ATmega16U2) || \ + AVR8_PART_IS_DEFINED(ATmega16U4) || \ + AVR8_PART_IS_DEFINED(ATmega256RFA2) || \ + AVR8_PART_IS_DEFINED(ATmega324P) || \ + AVR8_PART_IS_DEFINED(ATmega325) || \ + AVR8_PART_IS_DEFINED(ATmega3250) || \ + AVR8_PART_IS_DEFINED(ATmega3250A) || \ + AVR8_PART_IS_DEFINED(ATmega3250P) || \ + AVR8_PART_IS_DEFINED(ATmega3250PA) || \ + AVR8_PART_IS_DEFINED(ATmega325A) || \ + AVR8_PART_IS_DEFINED(ATmega325P) || \ + AVR8_PART_IS_DEFINED(ATmega325PA) || \ + AVR8_PART_IS_DEFINED(ATmega329) || \ + AVR8_PART_IS_DEFINED(ATmega3290) || \ + AVR8_PART_IS_DEFINED(ATmega3290A) || \ + AVR8_PART_IS_DEFINED(ATmega3290P) || \ + AVR8_PART_IS_DEFINED(ATmega3290PA) || \ + AVR8_PART_IS_DEFINED(ATmega329A) || \ + AVR8_PART_IS_DEFINED(ATmega32M1) || \ + AVR8_PART_IS_DEFINED(ATmega32U2) || \ + AVR8_PART_IS_DEFINED(ATmega32U4) || \ + AVR8_PART_IS_DEFINED(ATmega48P) || \ + AVR8_PART_IS_DEFINED(ATmega644P) || \ + AVR8_PART_IS_DEFINED(ATmega645) || \ + AVR8_PART_IS_DEFINED(ATmega6450) || \ + AVR8_PART_IS_DEFINED(ATmega6450A) || \ + AVR8_PART_IS_DEFINED(ATmega6450P) || \ + AVR8_PART_IS_DEFINED(ATmega645A) || \ + AVR8_PART_IS_DEFINED(ATmega645P) || \ + AVR8_PART_IS_DEFINED(ATmega649) || \ + AVR8_PART_IS_DEFINED(ATmega6490) || \ + AVR8_PART_IS_DEFINED(ATmega6490A) || \ + AVR8_PART_IS_DEFINED(ATmega6490P) || \ + AVR8_PART_IS_DEFINED(ATmega649A) || \ + AVR8_PART_IS_DEFINED(ATmega649P) || \ + AVR8_PART_IS_DEFINED(ATmega64M1) || \ + AVR8_PART_IS_DEFINED(ATmega64RFA2) || \ + AVR8_PART_IS_DEFINED(ATmega8) || \ + AVR8_PART_IS_DEFINED(ATmega8515) || \ + AVR8_PART_IS_DEFINED(ATmega8535) || \ + AVR8_PART_IS_DEFINED(ATmega88P) || \ + AVR8_PART_IS_DEFINED(ATmega8A) || \ + AVR8_PART_IS_DEFINED(ATmega8U2) \ + ) + +/** Unspecified group */ +#define MEGA_UNSPECIFIED (MEGA_XX_UN0 || MEGA_XX_UN1 || MEGA_XX_UN2 || \ + MEGA_UNCATEGORIZED) + +/** @} */ + +/** megaAVR product line */ +#define MEGA (MEGA_XX0_1 || MEGA_XX4 || MEGA_XX8 || MEGA_XX || MEGA_RF || \ + MEGA_UNSPECIFIED) + +/** @} */ + +/** + * \defgroup tiny_part_macros_group tinyAVR parts + * + * @{ + */ + +/** + * \name tinyAVR groups + * @{ + */ + +/** Devices added to complete tinyAVR offering. + * Please do not use this group symbol as it is not intended + * to be permanent: the devices should be regrouped. + */ +#define TINY_UNCATEGORIZED ( \ + AVR8_PART_IS_DEFINED(ATtiny10) || \ + AVR8_PART_IS_DEFINED(ATtiny13) || \ + AVR8_PART_IS_DEFINED(ATtiny13A) || \ + AVR8_PART_IS_DEFINED(ATtiny1634) || \ + AVR8_PART_IS_DEFINED(ATtiny167) || \ + AVR8_PART_IS_DEFINED(ATtiny20) || \ + AVR8_PART_IS_DEFINED(ATtiny2313) || \ + AVR8_PART_IS_DEFINED(ATtiny2313A) || \ + AVR8_PART_IS_DEFINED(ATtiny24) || \ + AVR8_PART_IS_DEFINED(ATtiny24A) || \ + AVR8_PART_IS_DEFINED(ATtiny25) || \ + AVR8_PART_IS_DEFINED(ATtiny26) || \ + AVR8_PART_IS_DEFINED(ATtiny261) || \ + AVR8_PART_IS_DEFINED(ATtiny261A) || \ + AVR8_PART_IS_DEFINED(ATtiny4) || \ + AVR8_PART_IS_DEFINED(ATtiny40) || \ + AVR8_PART_IS_DEFINED(ATtiny4313) || \ + AVR8_PART_IS_DEFINED(ATtiny43U) || \ + AVR8_PART_IS_DEFINED(ATtiny44) || \ + AVR8_PART_IS_DEFINED(ATtiny44A) || \ + AVR8_PART_IS_DEFINED(ATtiny45) || \ + AVR8_PART_IS_DEFINED(ATtiny461) || \ + AVR8_PART_IS_DEFINED(ATtiny461A) || \ + AVR8_PART_IS_DEFINED(ATtiny48) || \ + AVR8_PART_IS_DEFINED(ATtiny5) || \ + AVR8_PART_IS_DEFINED(ATtiny828) || \ + AVR8_PART_IS_DEFINED(ATtiny84) || \ + AVR8_PART_IS_DEFINED(ATtiny84A) || \ + AVR8_PART_IS_DEFINED(ATtiny85) || \ + AVR8_PART_IS_DEFINED(ATtiny861) || \ + AVR8_PART_IS_DEFINED(ATtiny861A) || \ + AVR8_PART_IS_DEFINED(ATtiny87) || \ + AVR8_PART_IS_DEFINED(ATtiny88) || \ + AVR8_PART_IS_DEFINED(ATtiny9) \ + ) + +/** @} */ + +/** tinyAVR product line */ +#define TINY (TINY_UNCATEGORIZED) + +/** @} */ + +/** + * \defgroup sam_part_macros_group SAM parts + * @{ + */ + +/** + * \name SAM3S series + * @{ + */ +#define SAM3S1 ( \ + SAM_PART_IS_DEFINED(SAM3S1A) || \ + SAM_PART_IS_DEFINED(SAM3S1B) || \ + SAM_PART_IS_DEFINED(SAM3S1C) \ + ) + +#define SAM3S2 ( \ + SAM_PART_IS_DEFINED(SAM3S2A) || \ + SAM_PART_IS_DEFINED(SAM3S2B) || \ + SAM_PART_IS_DEFINED(SAM3S2C) \ + ) + +#define SAM3S4 ( \ + SAM_PART_IS_DEFINED(SAM3S4A) || \ + SAM_PART_IS_DEFINED(SAM3S4B) || \ + SAM_PART_IS_DEFINED(SAM3S4C) \ + ) + +#define SAM3S8 ( \ + SAM_PART_IS_DEFINED(SAM3S8B) || \ + SAM_PART_IS_DEFINED(SAM3S8C) \ + ) + +#define SAM3SD8 ( \ + SAM_PART_IS_DEFINED(SAM3SD8B) || \ + SAM_PART_IS_DEFINED(SAM3SD8C) \ + ) +/** @} */ + +/** + * \name SAM3U series + * @{ + */ +#define SAM3U1 ( \ + SAM_PART_IS_DEFINED(SAM3U1C) || \ + SAM_PART_IS_DEFINED(SAM3U1E) \ + ) + +#define SAM3U2 ( \ + SAM_PART_IS_DEFINED(SAM3U2C) || \ + SAM_PART_IS_DEFINED(SAM3U2E) \ + ) + +#define SAM3U4 ( \ + SAM_PART_IS_DEFINED(SAM3U4C) || \ + SAM_PART_IS_DEFINED(SAM3U4E) \ + ) +/** @} */ + +/** + * \name SAM3N series + * @{ + */ +#define SAM3N00 ( \ + SAM_PART_IS_DEFINED(SAM3N00A) || \ + SAM_PART_IS_DEFINED(SAM3N00B) \ + ) + +#define SAM3N0 ( \ + SAM_PART_IS_DEFINED(SAM3N0A) || \ + SAM_PART_IS_DEFINED(SAM3N0B) || \ + SAM_PART_IS_DEFINED(SAM3N0C) \ + ) + +#define SAM3N1 ( \ + SAM_PART_IS_DEFINED(SAM3N1A) || \ + SAM_PART_IS_DEFINED(SAM3N1B) || \ + SAM_PART_IS_DEFINED(SAM3N1C) \ + ) + +#define SAM3N2 ( \ + SAM_PART_IS_DEFINED(SAM3N2A) || \ + SAM_PART_IS_DEFINED(SAM3N2B) || \ + SAM_PART_IS_DEFINED(SAM3N2C) \ + ) + +#define SAM3N4 ( \ + SAM_PART_IS_DEFINED(SAM3N4A) || \ + SAM_PART_IS_DEFINED(SAM3N4B) || \ + SAM_PART_IS_DEFINED(SAM3N4C) \ + ) +/** @} */ + +/** + * \name SAM3X series + * @{ + */ +#define SAM3X4 ( \ + SAM_PART_IS_DEFINED(SAM3X4C) || \ + SAM_PART_IS_DEFINED(SAM3X4E) \ + ) + +#define SAM3X8 ( \ + SAM_PART_IS_DEFINED(SAM3X8C) || \ + SAM_PART_IS_DEFINED(SAM3X8E) || \ + SAM_PART_IS_DEFINED(SAM3X8H) \ + ) +/** @} */ + +/** + * \name SAM3A series + * @{ + */ +#define SAM3A4 ( \ + SAM_PART_IS_DEFINED(SAM3A4C) \ + ) + +#define SAM3A8 ( \ + SAM_PART_IS_DEFINED(SAM3A8C) \ + ) +/** @} */ + +/** + * \name SAM4S series + * @{ + */ +#define SAM4S2 ( \ + SAM_PART_IS_DEFINED(SAM4S2A) || \ + SAM_PART_IS_DEFINED(SAM4S2B) || \ + SAM_PART_IS_DEFINED(SAM4S2C) \ + ) + +#define SAM4S4 ( \ + SAM_PART_IS_DEFINED(SAM4S4A) || \ + SAM_PART_IS_DEFINED(SAM4S4B) || \ + SAM_PART_IS_DEFINED(SAM4S4C) \ + ) + +#define SAM4S8 ( \ + SAM_PART_IS_DEFINED(SAM4S8B) || \ + SAM_PART_IS_DEFINED(SAM4S8C) \ + ) + +#define SAM4S16 ( \ + SAM_PART_IS_DEFINED(SAM4S16B) || \ + SAM_PART_IS_DEFINED(SAM4S16C) \ + ) + +#define SAM4SA16 ( \ + SAM_PART_IS_DEFINED(SAM4SA16B) || \ + SAM_PART_IS_DEFINED(SAM4SA16C) \ + ) + +#define SAM4SD16 ( \ + SAM_PART_IS_DEFINED(SAM4SD16B) || \ + SAM_PART_IS_DEFINED(SAM4SD16C) \ + ) + +#define SAM4SD32 ( \ + SAM_PART_IS_DEFINED(SAM4SD32B) || \ + SAM_PART_IS_DEFINED(SAM4SD32C) \ + ) +/** @} */ + +/** + * \name SAM4L series + * @{ + */ +#define SAM4LS ( \ + SAM_PART_IS_DEFINED(SAM4LS2A) || \ + SAM_PART_IS_DEFINED(SAM4LS2B) || \ + SAM_PART_IS_DEFINED(SAM4LS2C) || \ + SAM_PART_IS_DEFINED(SAM4LS4A) || \ + SAM_PART_IS_DEFINED(SAM4LS4B) || \ + SAM_PART_IS_DEFINED(SAM4LS4C) || \ + SAM_PART_IS_DEFINED(SAM4LS8A) || \ + SAM_PART_IS_DEFINED(SAM4LS8B) || \ + SAM_PART_IS_DEFINED(SAM4LS8C) \ + ) + +#define SAM4LC ( \ + SAM_PART_IS_DEFINED(SAM4LC2A) || \ + SAM_PART_IS_DEFINED(SAM4LC2B) || \ + SAM_PART_IS_DEFINED(SAM4LC2C) || \ + SAM_PART_IS_DEFINED(SAM4LC4A) || \ + SAM_PART_IS_DEFINED(SAM4LC4B) || \ + SAM_PART_IS_DEFINED(SAM4LC4C) || \ + SAM_PART_IS_DEFINED(SAM4LC8A) || \ + SAM_PART_IS_DEFINED(SAM4LC8B) || \ + SAM_PART_IS_DEFINED(SAM4LC8C) \ + ) +/** @} */ + +/** + * \name SAMD20 series + * @{ + */ +#define SAMD20J ( \ + SAM_PART_IS_DEFINED(SAMD20J14) || \ + SAM_PART_IS_DEFINED(SAMD20J15) || \ + SAM_PART_IS_DEFINED(SAMD20J16) || \ + SAM_PART_IS_DEFINED(SAMD20J17) || \ + SAM_PART_IS_DEFINED(SAMD20J18) \ + ) + +#define SAMD20G ( \ + SAM_PART_IS_DEFINED(SAMD20G14) || \ + SAM_PART_IS_DEFINED(SAMD20G15) || \ + SAM_PART_IS_DEFINED(SAMD20G16) || \ + SAM_PART_IS_DEFINED(SAMD20G17) || \ + SAM_PART_IS_DEFINED(SAMD20G17U) || \ + SAM_PART_IS_DEFINED(SAMD20G18) || \ + SAM_PART_IS_DEFINED(SAMD20G18U) \ + ) + +#define SAMD20E ( \ + SAM_PART_IS_DEFINED(SAMD20E14) || \ + SAM_PART_IS_DEFINED(SAMD20E15) || \ + SAM_PART_IS_DEFINED(SAMD20E16) || \ + SAM_PART_IS_DEFINED(SAMD20E17) || \ + SAM_PART_IS_DEFINED(SAMD20E18) \ + ) +/** @} */ + +/** + * \name SAMD21 series + * @{ + */ +#define SAMD21J ( \ + SAM_PART_IS_DEFINED(SAMD21J15A) || \ + SAM_PART_IS_DEFINED(SAMD21J16A) || \ + SAM_PART_IS_DEFINED(SAMD21J17A) || \ + SAM_PART_IS_DEFINED(SAMD21J18A) || \ + SAM_PART_IS_DEFINED(SAMD21J15B) || \ + SAM_PART_IS_DEFINED(SAMD21J16B) \ + ) + +#define SAMD21G ( \ + SAM_PART_IS_DEFINED(SAMD21G15A) || \ + SAM_PART_IS_DEFINED(SAMD21G16A) || \ + SAM_PART_IS_DEFINED(SAMD21G17A) || \ + SAM_PART_IS_DEFINED(SAMD21G17AU) || \ + SAM_PART_IS_DEFINED(SAMD21G18A) || \ + SAM_PART_IS_DEFINED(SAMD21G18AU) || \ + SAM_PART_IS_DEFINED(SAMD21G15B) || \ + SAM_PART_IS_DEFINED(SAMD21G16B) || \ + SAM_PART_IS_DEFINED(SAMD21G15L) || \ + SAM_PART_IS_DEFINED(SAMD21G16L) \ + ) + +#define SAMD21GXXL ( \ + SAM_PART_IS_DEFINED(SAMD21G15L) || \ + SAM_PART_IS_DEFINED(SAMD21G16L) \ + ) + +#define SAMD21E ( \ + SAM_PART_IS_DEFINED(SAMD21E15A) || \ + SAM_PART_IS_DEFINED(SAMD21E16A) || \ + SAM_PART_IS_DEFINED(SAMD21E17A) || \ + SAM_PART_IS_DEFINED(SAMD21E18A) || \ + SAM_PART_IS_DEFINED(SAMD21E15B) || \ + SAM_PART_IS_DEFINED(SAMD21E15BU) || \ + SAM_PART_IS_DEFINED(SAMD21E16B) || \ + SAM_PART_IS_DEFINED(SAMD21E16BU) || \ + SAM_PART_IS_DEFINED(SAMD21E15L) || \ + SAM_PART_IS_DEFINED(SAMD21E16L) \ + ) + +#define SAMD21EXXL ( \ + SAM_PART_IS_DEFINED(SAMD21E15L) || \ + SAM_PART_IS_DEFINED(SAMD21E16L) \ + ) + +/** @} */ + +/** + * \name SAMR21 series + * @{ + */ +#define SAMR21G ( \ + SAM_PART_IS_DEFINED(SAMR21G16A) || \ + SAM_PART_IS_DEFINED(SAMR21G17A) || \ + SAM_PART_IS_DEFINED(SAMR21G18A) \ + ) + +#define SAMR21E ( \ + SAM_PART_IS_DEFINED(SAMR21E16A) || \ + SAM_PART_IS_DEFINED(SAMR21E17A) || \ + SAM_PART_IS_DEFINED(SAMR21E18A) || \ + SAM_PART_IS_DEFINED(SAMR21E19A) \ + ) +/** @} */ + +/** + * \name SAMB11 series + * @{ + */ +#define SAMB11G ( \ + SAM_PART_IS_DEFINED(SAMB11G18A) \ + ) +/** @} */ + +/** + * \name SAMD09 series + * @{ + */ +#define SAMD09C ( \ + SAM_PART_IS_DEFINED(SAMD09C13A) \ + ) + +#define SAMD09D ( \ + SAM_PART_IS_DEFINED(SAMD09D14A) \ + ) +/** @} */ + +/** + * \name SAMD10 series + * @{ + */ +#define SAMD10C ( \ + SAM_PART_IS_DEFINED(SAMD10C12A) || \ + SAM_PART_IS_DEFINED(SAMD10C13A) || \ + SAM_PART_IS_DEFINED(SAMD10C14A) \ + ) + +#define SAMD10DS ( \ + SAM_PART_IS_DEFINED(SAMD10D12AS) || \ + SAM_PART_IS_DEFINED(SAMD10D13AS) || \ + SAM_PART_IS_DEFINED(SAMD10D14AS) \ + ) + +#define SAMD10DM ( \ + SAM_PART_IS_DEFINED(SAMD10D12AM) || \ + SAM_PART_IS_DEFINED(SAMD10D13AM) || \ + SAM_PART_IS_DEFINED(SAMD10D14AM) \ + ) + +#define SAMD10DU ( \ + SAM_PART_IS_DEFINED(SAMD10D14AU) \ + ) +/** @} */ + +/** + * \name SAMD11 series + * @{ + */ +#define SAMD11C ( \ + SAM_PART_IS_DEFINED(SAMD11C14A) \ + ) + +#define SAMD11DS ( \ + SAM_PART_IS_DEFINED(SAMD11D14AS) \ + ) + +#define SAMD11DM ( \ + SAM_PART_IS_DEFINED(SAMD11D14AM) \ + ) + +#define SAMD11DU ( \ + SAM_PART_IS_DEFINED(SAMD11D14AU) \ + ) +/** @} */ + +/** + * \name SAML21 series + * @{ + */ +#define SAML21E ( \ + SAM_PART_IS_DEFINED(SAML21E18A) || \ + SAM_PART_IS_DEFINED(SAML21E15B) || \ + SAM_PART_IS_DEFINED(SAML21E16B) || \ + SAM_PART_IS_DEFINED(SAML21E17B) || \ + SAM_PART_IS_DEFINED(SAML21E18B) \ + ) + +#define SAML21G ( \ + SAM_PART_IS_DEFINED(SAML21G18A) || \ + SAM_PART_IS_DEFINED(SAML21G16B) || \ + SAM_PART_IS_DEFINED(SAML21G17B) || \ + SAM_PART_IS_DEFINED(SAML21G18B) \ + ) + +#define SAML21J ( \ + SAM_PART_IS_DEFINED(SAML21J18A) || \ + SAM_PART_IS_DEFINED(SAML21J16B) || \ + SAM_PART_IS_DEFINED(SAML21J17B) || \ + SAM_PART_IS_DEFINED(SAML21J18B) \ + ) + +/* Group for SAML21 A variant: SAML21[E/G/J][18]A */ +#define SAML21XXXA ( \ + SAM_PART_IS_DEFINED(SAML21E18A) || \ + SAM_PART_IS_DEFINED(SAML21G18A) || \ + SAM_PART_IS_DEFINED(SAML21J18A) \ + ) + +/* Group for SAML21 B variant: SAML21[E/G/J][15/16/1718]B */ +#define SAML21XXXB ( \ + SAM_PART_IS_DEFINED(SAML21E15B) || \ + SAM_PART_IS_DEFINED(SAML21E16B) || \ + SAM_PART_IS_DEFINED(SAML21E17B) || \ + SAM_PART_IS_DEFINED(SAML21E18B) || \ + SAM_PART_IS_DEFINED(SAML21G16B) || \ + SAM_PART_IS_DEFINED(SAML21G17B) || \ + SAM_PART_IS_DEFINED(SAML21G18B) || \ + SAM_PART_IS_DEFINED(SAML21J16B) || \ + SAM_PART_IS_DEFINED(SAML21J17B) || \ + SAM_PART_IS_DEFINED(SAML21J18B) \ + ) + +/** @} */ + +/** + * \name SAML22 series + * @{ + */ +#define SAML22N ( \ + SAM_PART_IS_DEFINED(SAML22N16A) || \ + SAM_PART_IS_DEFINED(SAML22N17A) || \ + SAM_PART_IS_DEFINED(SAML22N18A) \ + ) + +#define SAML22G ( \ + SAM_PART_IS_DEFINED(SAML22G16A) || \ + SAM_PART_IS_DEFINED(SAML22G17A) || \ + SAM_PART_IS_DEFINED(SAML22G18A) \ + ) + +#define SAML22J ( \ + SAM_PART_IS_DEFINED(SAML22J16A) || \ + SAM_PART_IS_DEFINED(SAML22J17A) || \ + SAM_PART_IS_DEFINED(SAML22J18A) \ + ) +/** @} */ + +/** + * \name SAMDA0 series + * @{ + */ +#define SAMDA0J ( \ + SAM_PART_IS_DEFINED(SAMDA0J14A) || \ + SAM_PART_IS_DEFINED(SAMDA0J15A) || \ + SAM_PART_IS_DEFINED(SAMDA0J16A) \ + ) + +#define SAMDA0G ( \ + SAM_PART_IS_DEFINED(SAMDA0G14A) || \ + SAM_PART_IS_DEFINED(SAMDA0G15A) || \ + SAM_PART_IS_DEFINED(SAMDA0G16A) \ + ) + +#define SAMDA0E ( \ + SAM_PART_IS_DEFINED(SAMDA0E14A) || \ + SAM_PART_IS_DEFINED(SAMDA0E15A) || \ + SAM_PART_IS_DEFINED(SAMDA0E16A) \ + ) +/** @} */ + +/** + * \name SAMDA1 series + * @{ + */ +#define SAMDA1J ( \ + SAM_PART_IS_DEFINED(SAMDA1J14A) || \ + SAM_PART_IS_DEFINED(SAMDA1J15A) || \ + SAM_PART_IS_DEFINED(SAMDA1J16A) \ + ) + +#define SAMDA1G ( \ + SAM_PART_IS_DEFINED(SAMDA1G14A) || \ + SAM_PART_IS_DEFINED(SAMDA1G15A) || \ + SAM_PART_IS_DEFINED(SAMDA1G16A) \ + ) + +#define SAMDA1E ( \ + SAM_PART_IS_DEFINED(SAMDA1E14A) || \ + SAM_PART_IS_DEFINED(SAMDA1E15A) || \ + SAM_PART_IS_DEFINED(SAMDA1E16A) \ + ) +/** @} */ + +/** + * \name SAMC20 series + * @{ + */ +#define SAMC20E ( \ + SAM_PART_IS_DEFINED(SAMC20E15A) || \ + SAM_PART_IS_DEFINED(SAMC20E16A) || \ + SAM_PART_IS_DEFINED(SAMC20E17A) || \ + SAM_PART_IS_DEFINED(SAMC20E18A) \ + ) + +#define SAMC20G ( \ + SAM_PART_IS_DEFINED(SAMC20G15A) || \ + SAM_PART_IS_DEFINED(SAMC20G16A) || \ + SAM_PART_IS_DEFINED(SAMC20G17A) || \ + SAM_PART_IS_DEFINED(SAMC20G18A) \ + ) + +#define SAMC20J ( \ + SAM_PART_IS_DEFINED(SAMC20J15A) || \ + SAM_PART_IS_DEFINED(SAMC20J16A) || \ + SAM_PART_IS_DEFINED(SAMC20J17A) || \ + SAM_PART_IS_DEFINED(SAMC20J18A) \ + ) +/** @} */ + +/** + * \name SAMC21 series + * @{ + */ +#define SAMC21E ( \ + SAM_PART_IS_DEFINED(SAMC21E15A) || \ + SAM_PART_IS_DEFINED(SAMC21E16A) || \ + SAM_PART_IS_DEFINED(SAMC21E17A) || \ + SAM_PART_IS_DEFINED(SAMC21E18A) \ + ) + +#define SAMC21G ( \ + SAM_PART_IS_DEFINED(SAMC21G15A) || \ + SAM_PART_IS_DEFINED(SAMC21G16A) || \ + SAM_PART_IS_DEFINED(SAMC21G17A) || \ + SAM_PART_IS_DEFINED(SAMC21G18A) \ + ) + +#define SAMC21J ( \ + SAM_PART_IS_DEFINED(SAMC21J15A) || \ + SAM_PART_IS_DEFINED(SAMC21J16A) || \ + SAM_PART_IS_DEFINED(SAMC21J17A) || \ + SAM_PART_IS_DEFINED(SAMC21J18A) \ + ) +/** @} */ + +/** + * \name SAM4E series + * @{ + */ +#define SAM4E8 ( \ + SAM_PART_IS_DEFINED(SAM4E8C) || \ + SAM_PART_IS_DEFINED(SAM4E8CB) || \ + SAM_PART_IS_DEFINED(SAM4E8E) \ + ) + +#define SAM4E16 ( \ + SAM_PART_IS_DEFINED(SAM4E16C) || \ + SAM_PART_IS_DEFINED(SAM4E16CB) || \ + SAM_PART_IS_DEFINED(SAM4E16E) \ + ) +/** @} */ + +/** + * \name SAM4N series + * @{ + */ +#define SAM4N8 ( \ + SAM_PART_IS_DEFINED(SAM4N8A) || \ + SAM_PART_IS_DEFINED(SAM4N8B) || \ + SAM_PART_IS_DEFINED(SAM4N8C) \ + ) + +#define SAM4N16 ( \ + SAM_PART_IS_DEFINED(SAM4N16B) || \ + SAM_PART_IS_DEFINED(SAM4N16C) \ + ) +/** @} */ + +/** + * \name SAM4C series + * @{ + */ +#define SAM4C4_0 ( \ + SAM_PART_IS_DEFINED(SAM4C4C_0) \ + ) + +#define SAM4C4_1 ( \ + SAM_PART_IS_DEFINED(SAM4C4C_1) \ + ) + +#define SAM4C4 (SAM4C4_0 || SAM4C4_1) + +#define SAM4C8_0 ( \ + SAM_PART_IS_DEFINED(SAM4C8C_0) \ + ) + +#define SAM4C8_1 ( \ + SAM_PART_IS_DEFINED(SAM4C8C_1) \ + ) + +#define SAM4C8 (SAM4C8_0 || SAM4C8_1) + +#define SAM4C16_0 ( \ + SAM_PART_IS_DEFINED(SAM4C16C_0) \ + ) + +#define SAM4C16_1 ( \ + SAM_PART_IS_DEFINED(SAM4C16C_1) \ + ) + +#define SAM4C16 (SAM4C16_0 || SAM4C16_1) + +#define SAM4C32_0 ( \ + SAM_PART_IS_DEFINED(SAM4C32C_0) ||\ + SAM_PART_IS_DEFINED(SAM4C32E_0) \ + ) + +#define SAM4C32_1 ( \ + SAM_PART_IS_DEFINED(SAM4C32C_1) ||\ + SAM_PART_IS_DEFINED(SAM4C32E_1) \ + ) + + +#define SAM4C32 (SAM4C32_0 || SAM4C32_1) + +/** @} */ + +/** + * \name SAM4CM series + * @{ + */ +#define SAM4CMP8_0 ( \ + SAM_PART_IS_DEFINED(SAM4CMP8C_0) \ + ) + +#define SAM4CMP8_1 ( \ + SAM_PART_IS_DEFINED(SAM4CMP8C_1) \ + ) + +#define SAM4CMP8 (SAM4CMP8_0 || SAM4CMP8_1) + +#define SAM4CMP16_0 ( \ + SAM_PART_IS_DEFINED(SAM4CMP16C_0) \ + ) + +#define SAM4CMP16_1 ( \ + SAM_PART_IS_DEFINED(SAM4CMP16C_1) \ + ) + +#define SAM4CMP16 (SAM4CMP16_0 || SAM4CMP16_1) + +#define SAM4CMP32_0 ( \ + SAM_PART_IS_DEFINED(SAM4CMP32C_0) \ + ) + +#define SAM4CMP32_1 ( \ + SAM_PART_IS_DEFINED(SAM4CMP32C_1) \ + ) + +#define SAM4CMP32 (SAM4CMP32_0 || SAM4CMP32_1) + +#define SAM4CMS4_0 ( \ + SAM_PART_IS_DEFINED(SAM4CMS4C_0) \ + ) + +#define SAM4CMS4_1 ( \ + SAM_PART_IS_DEFINED(SAM4CMS4C_1) \ + ) + +#define SAM4CMS4 (SAM4CMS4_0 || SAM4CMS4_1) + +#define SAM4CMS8_0 ( \ + SAM_PART_IS_DEFINED(SAM4CMS8C_0) \ + ) + +#define SAM4CMS8_1 ( \ + SAM_PART_IS_DEFINED(SAM4CMS8C_1) \ + ) + +#define SAM4CMS8 (SAM4CMS8_0 || SAM4CMS8_1) + +#define SAM4CMS16_0 ( \ + SAM_PART_IS_DEFINED(SAM4CMS16C_0) \ + ) + +#define SAM4CMS16_1 ( \ + SAM_PART_IS_DEFINED(SAM4CMS16C_1) \ + ) + +#define SAM4CMS16 (SAM4CMS16_0 || SAM4CMS16_1) + +#define SAM4CMS32_0 ( \ + SAM_PART_IS_DEFINED(SAM4CMS32C_0) \ + ) + +#define SAM4CMS32_1 ( \ + SAM_PART_IS_DEFINED(SAM4CMS32C_1) \ + ) + +#define SAM4CMS32 (SAM4CMS32_0 || SAM4CMS32_1) + +/** @} */ + +/** + * \name SAM4CP series + * @{ + */ +#define SAM4CP16_0 ( \ + SAM_PART_IS_DEFINED(SAM4CP16B_0) \ + ) + +#define SAM4CP16_1 ( \ + SAM_PART_IS_DEFINED(SAM4CP16B_1) \ + ) + +#define SAM4CP16 (SAM4CP16_0 || SAM4CP16_1) +/** @} */ + +/** + * \name SAMG series + * @{ + */ +#define SAMG51 ( \ + SAM_PART_IS_DEFINED(SAMG51G18) \ + ) + +#define SAMG53 ( \ + SAM_PART_IS_DEFINED(SAMG53G19) ||\ + SAM_PART_IS_DEFINED(SAMG53N19) \ + ) + +#define SAMG54 ( \ + SAM_PART_IS_DEFINED(SAMG54G19) ||\ + SAM_PART_IS_DEFINED(SAMG54J19) ||\ + SAM_PART_IS_DEFINED(SAMG54N19) \ + ) + +#define SAMG55 ( \ + SAM_PART_IS_DEFINED(SAMG55G18) ||\ + SAM_PART_IS_DEFINED(SAMG55G19) ||\ + SAM_PART_IS_DEFINED(SAMG55J18) ||\ + SAM_PART_IS_DEFINED(SAMG55J19) ||\ + SAM_PART_IS_DEFINED(SAMG55N19) \ + ) +/** @} */ + +/** + * \name SAMV71 series + * @{ + */ +#define SAMV71J ( \ + SAM_PART_IS_DEFINED(SAMV71J19) || \ + SAM_PART_IS_DEFINED(SAMV71J20) || \ + SAM_PART_IS_DEFINED(SAMV71J21) \ + ) + +#define SAMV71N ( \ + SAM_PART_IS_DEFINED(SAMV71N19) || \ + SAM_PART_IS_DEFINED(SAMV71N20) || \ + SAM_PART_IS_DEFINED(SAMV71N21) \ + ) + +#define SAMV71Q ( \ + SAM_PART_IS_DEFINED(SAMV71Q19) || \ + SAM_PART_IS_DEFINED(SAMV71Q20) || \ + SAM_PART_IS_DEFINED(SAMV71Q21) \ + ) +/** @} */ + +/** + * \name SAMV70 series + * @{ + */ +#define SAMV70J ( \ + SAM_PART_IS_DEFINED(SAMV70J19) || \ + SAM_PART_IS_DEFINED(SAMV70J20) \ + ) + +#define SAMV70N ( \ + SAM_PART_IS_DEFINED(SAMV70N19) || \ + SAM_PART_IS_DEFINED(SAMV70N20) \ + ) + +#define SAMV70Q ( \ + SAM_PART_IS_DEFINED(SAMV70Q19) || \ + SAM_PART_IS_DEFINED(SAMV70Q20) \ + ) +/** @} */ + +/** + * \name SAMS70 series + * @{ + */ +#define SAMS70J ( \ + SAM_PART_IS_DEFINED(SAMS70J19) || \ + SAM_PART_IS_DEFINED(SAMS70J20) || \ + SAM_PART_IS_DEFINED(SAMS70J21) \ + ) + +#define SAMS70N ( \ + SAM_PART_IS_DEFINED(SAMS70N19) || \ + SAM_PART_IS_DEFINED(SAMS70N20) || \ + SAM_PART_IS_DEFINED(SAMS70N21) \ + ) + +#define SAMS70Q ( \ + SAM_PART_IS_DEFINED(SAMS70Q19) || \ + SAM_PART_IS_DEFINED(SAMS70Q20) || \ + SAM_PART_IS_DEFINED(SAMS70Q21) \ + ) +/** @} */ + +/** + * \name SAME70 series + * @{ + */ +#define SAME70J ( \ + SAM_PART_IS_DEFINED(SAME70J19) || \ + SAM_PART_IS_DEFINED(SAME70J20) || \ + SAM_PART_IS_DEFINED(SAME70J21) \ + ) + +#define SAME70N ( \ + SAM_PART_IS_DEFINED(SAME70N19) || \ + SAM_PART_IS_DEFINED(SAME70N20) || \ + SAM_PART_IS_DEFINED(SAME70N21) \ + ) + +#define SAME70Q ( \ + SAM_PART_IS_DEFINED(SAME70Q19) || \ + SAM_PART_IS_DEFINED(SAME70Q20) || \ + SAM_PART_IS_DEFINED(SAME70Q21) \ + ) +/** @} */ + +/** + * \name SAM families + * @{ + */ +/** SAM3S Family */ +#define SAM3S (SAM3S1 || SAM3S2 || SAM3S4 || SAM3S8 || SAM3SD8) + +/** SAM3U Family */ +#define SAM3U (SAM3U1 || SAM3U2 || SAM3U4) + +/** SAM3N Family */ +#define SAM3N (SAM3N00 || SAM3N0 || SAM3N1 || SAM3N2 || SAM3N4) + +/** SAM3XA Family */ +#define SAM3XA (SAM3X4 || SAM3X8 || SAM3A4 || SAM3A8) + +/** SAM4S Family */ +#define SAM4S (SAM4S2 || SAM4S4 || SAM4S8 || SAM4S16 || SAM4SA16 || SAM4SD16 || SAM4SD32) + +/** SAM4L Family */ +#define SAM4L (SAM4LS || SAM4LC) + +/** SAMD20 Family */ +#define SAMD20 (SAMD20J || SAMD20G || SAMD20E) + +/** SAMD21 Family */ +#define SAMD21 (SAMD21J || SAMD21G || SAMD21E) + +/** SAMD09 Family */ +#define SAMD09 (SAMD09C || SAMD09D) + +/** SAMD10 Family */ +#define SAMD10 (SAMD10C || SAMD10DS || SAMD10DM || SAMD10DU) + +/** SAMD11 Family */ +#define SAMD11 (SAMD11C || SAMD11DS || SAMD11DM || SAMD11DU) + +/** SAMDA1 Family */ +#define SAMDA1 (SAMDA1J || SAMDA1G || SAMDA1E) + +/** SAMD Family */ +#define SAMD (SAMD20 || SAMD21 || SAMD09 || SAMD10 || SAMD11 || SAMDA1) + +/** SAMR21 Family */ +#define SAMR21 (SAMR21G || SAMR21E) + +/** SAMB11 Family */ +#define SAMB11 (SAMB11G) + +/** SAML21 Family */ +#define SAML21 (SAML21J || SAML21G || SAML21E) + +/** SAML22 Family */ +#define SAML22 (SAML22J || SAML22G || SAML22N) +/** SAMC20 Family */ +#define SAMC20 (SAMC20J || SAMC20G || SAMC20E) + +/** SAMC21 Family */ +#define SAMC21 (SAMC21J || SAMC21G || SAMC21E) + +/** SAM4E Family */ +#define SAM4E (SAM4E8 || SAM4E16) + +/** SAM4N Family */ +#define SAM4N (SAM4N8 || SAM4N16) + +/** SAM4C Family */ +#define SAM4C_0 (SAM4C4_0 || SAM4C8_0 || SAM4C16_0 || SAM4C32_0) +#define SAM4C_1 (SAM4C4_1 || SAM4C8_1 || SAM4C16_1 || SAM4C32_1) +#define SAM4C (SAM4C4 || SAM4C8 || SAM4C16 || SAM4C32) + +/** SAM4CM Family */ +#define SAM4CM_0 (SAM4CMP8_0 || SAM4CMP16_0 || SAM4CMP32_0 || \ + SAM4CMS4_0 || SAM4CMS8_0 || SAM4CMS16_0 || SAM4CMS32_0) +#define SAM4CM_1 (SAM4CMP8_1 || SAM4CMP16_1 || SAM4CMP32_1 || \ + SAM4CMS4_1 || SAM4CMS8_1 || SAM4CMS16_1 || SAM4CMS32_1) +#define SAM4CM (SAM4CMP8 || SAM4CMP16 || SAM4CMP32 || \ + SAM4CMS4 || SAM4CMS8 || SAM4CMS16 || SAM4CMS32) + +/** SAM4CP Family */ +#define SAM4CP_0 (SAM4CP16_0) +#define SAM4CP_1 (SAM4CP16_1) +#define SAM4CP (SAM4CP16) + +/** SAMG Family */ +#define SAMG (SAMG51 || SAMG53 || SAMG54 || SAMG55) + +/** SAMB Family */ +#define SAMB (SAMB11) + +/** SAMV71 Family */ +#define SAMV71 (SAMV71J || SAMV71N || SAMV71Q) + +/** SAMV70 Family */ +#define SAMV70 (SAMV70J || SAMV70N || SAMV70Q) + +/** SAME70 Family */ +#define SAME70 (SAME70J || SAME70N || SAME70Q) + +/** SAMS70 Family */ +#define SAMS70 (SAMS70J || SAMS70N || SAMS70Q) + +/** SAM0 product line (cortex-m0+) */ +#define SAM0 (SAMD20 || SAMD21 || SAMR21 || SAMD10 || SAMD11 || SAML21 ||\ + SAMDA1 || SAMC20 || SAMC21 || SAML22 || SAMD09) + +/** @} */ + +/** SAM product line */ +#define SAM (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4L || SAM4E || \ + SAM0 || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG || SAMV71 || SAMV70 || SAME70 || SAMS70) + +/** @} */ + +/** @} */ + +/** @} */ + +#endif /* ATMEL_PARTS_H */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/utils/stdio/read.c b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/utils/stdio/read.c new file mode 100644 index 0000000..1326308 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/utils/stdio/read.c @@ -0,0 +1,167 @@ +/** + * \file + * + * \brief System-specific implementation of the \ref _read function used by + * the standard library. + * + * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#include "compiler.h" + +/** + * \defgroup group_common_utils_stdio Standard I/O (stdio) + * + * Common standard I/O driver that implements the stdio + * read and write functions on AVR and SAM devices. + * + * \{ + */ + +extern volatile void *volatile stdio_base; +void (*ptr_get)(void volatile*, char*); + + +// IAR common implementation +#if ( defined(__ICCAVR32__) || defined(__ICCAVR__) || defined(__ICCARM__) ) + +#include + +_STD_BEGIN + +#pragma module_name = "?__read" + +/*! \brief Reads a number of bytes, at most \a size, into the memory area + * pointed to by \a buffer. + * + * \param handle File handle to read from. + * \param buffer Pointer to buffer to write read bytes to. + * \param size Number of bytes to read. + * + * \return The number of bytes read, \c 0 at the end of the file, or + * \c _LLIO_ERROR on failure. + */ +size_t __read(int handle, unsigned char *buffer, size_t size) +{ + int nChars = 0; + // This implementation only reads from stdin. + // For all other file handles, it returns failure. + if (handle != _LLIO_STDIN) { + return _LLIO_ERROR; + } + for (; size > 0; --size) { + ptr_get(stdio_base, (char*)buffer); + buffer++; + nChars++; + } + return nChars; +} + +/*! \brief This routine is required by IAR DLIB library since EWAVR V6.10 + * the implementation is empty to be compatible with old IAR version. + */ +int __close(int handle) +{ + UNUSED(handle); + return 0; +} + +/*! \brief This routine is required by IAR DLIB library since EWAVR V6.10 + * the implementation is empty to be compatible with old IAR version. + */ +int remove(const char* val) +{ + UNUSED(val); + return 0; +} + +/*! \brief This routine is required by IAR DLIB library since EWAVR V6.10 + * the implementation is empty to be compatible with old IAR version. + */ +long __lseek(int handle, long val, int val2) +{ + UNUSED(handle); + UNUSED(val2); + return val; +} + +_STD_END + +// GCC AVR32 and SAM implementation +#elif (defined(__GNUC__) && !XMEGA && !MEGA) + +int __attribute__((weak)) +_read (int file, char * ptr, int len); // Remove GCC compiler warning + +int __attribute__((weak)) +_read (int file, char * ptr, int len) +{ + int nChars = 0; + + if (file != 0) { + return -1; + } + + for (; len > 0; --len) { + ptr_get(stdio_base, ptr); + ptr++; + nChars++; + } + return nChars; +} + +// GCC AVR implementation +#elif (defined(__GNUC__) && (XMEGA || MEGA) ) + +int _read (int *f); // Remove GCC compiler warning + +int _read (int *f) +{ + char c; + ptr_get(stdio_base,&c); + return c; +} +#endif + +/** + * \} + */ + diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/utils/stdio/stdio_serial/stdio_serial.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/utils/stdio/stdio_serial/stdio_serial.h new file mode 100644 index 0000000..4315d3f --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/utils/stdio/stdio_serial/stdio_serial.h @@ -0,0 +1,129 @@ +/** + * + * \file + * + * \brief Common Standard I/O Serial Management. + * + * This file defines a useful set of functions for the Stdio Serial interface on AVR + * and SAM devices. + * + * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + ******************************************************************************/ +/* + * Support and FAQ: visit Atmel Support + */ + + +#ifndef _STDIO_SERIAL_H_ +#define _STDIO_SERIAL_H_ + +/** + * \defgroup group_common_utils_stdio_stdio_serial Standard serial I/O (stdio) + * \ingroup group_common_utils_stdio + * + * Common standard serial I/O management driver that + * implements a stdio serial interface on AVR and SAM devices. + * + * \{ + */ + +#include +#include "compiler.h" +#ifndef SAMD20 +# include "sysclk.h" +#endif +#include "serial.h" + +#if (XMEGA || MEGA_RF) && defined(__GNUC__) + extern int _write (char c, int *f); + extern int _read (int *f); +#endif + + +//! Pointer to the base of the USART module instance to use for stdio. +extern volatile void *volatile stdio_base; +//! Pointer to the external low level write function. +extern int (*ptr_put)(void volatile*, char); + +//! Pointer to the external low level read function. +extern void (*ptr_get)(void volatile*, char*); + +/*! \brief Initializes the stdio in Serial Mode. + * + * \param usart Base address of the USART instance. + * \param opt Options needed to set up RS232 communication (see \ref usart_options_t). + * + */ +static inline void stdio_serial_init(volatile void *usart, const usart_serial_options_t *opt) +{ + stdio_base = (void *)usart; + ptr_put = (int (*)(void volatile*,char))&usart_serial_putchar; + ptr_get = (void (*)(void volatile*,char*))&usart_serial_getchar; +# if (XMEGA || MEGA_RF) + usart_serial_init((USART_t *)usart,opt); +# elif UC3 + usart_serial_init(usart,(usart_serial_options_t *)opt); +# elif SAM + usart_serial_init((Usart *)usart,(usart_serial_options_t *)opt); +# else +# error Unsupported chip type +# endif + +# if defined(__GNUC__) +# if (XMEGA || MEGA_RF) + // For AVR GCC libc print redirection uses fdevopen. + fdevopen((int (*)(char, FILE*))(_write),(int (*)(FILE*))(_read)); +# endif +# if UC3 || SAM + // For AVR32 and SAM GCC + // Specify that stdout and stdin should not be buffered. + setbuf(stdout, NULL); + setbuf(stdin, NULL); + // Note: Already the case in IAR's Normal DLIB default configuration + // and AVR GCC library: + // - printf() emits one character at a time. + // - getchar() requests only 1 byte to exit. +# endif +# endif +} + +/** + * \} + */ + +#endif // _STDIO_SERIAL_H_ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/utils/stdio/write.c b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/utils/stdio/write.c new file mode 100644 index 0000000..1e8f459 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/common/utils/stdio/write.c @@ -0,0 +1,147 @@ +/** + * \file + * + * \brief System-specific implementation of the \ref _write function used by + * the standard library. + * + * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#include "compiler.h" + +/** + * \addtogroup group_common_utils_stdio + * + * \{ + */ + +volatile void *volatile stdio_base; +int (*ptr_put)(void volatile*, char); + + +#if ( defined(__ICCAVR32__) || defined(__ICCAVR__) || defined(__ICCARM__)) + +#include + +_STD_BEGIN + +#pragma module_name = "?__write" + +/*! \brief Writes a number of bytes, at most \a size, from the memory area + * pointed to by \a buffer. + * + * If \a buffer is zero then \ref __write performs flushing of internal buffers, + * if any. In this case, \a handle can be \c -1 to indicate that all handles + * should be flushed. + * + * \param handle File handle to write to. + * \param buffer Pointer to buffer to read bytes to write from. + * \param size Number of bytes to write. + * + * \return The number of bytes written, or \c _LLIO_ERROR on failure. + */ +size_t __write(int handle, const unsigned char *buffer, size_t size) +{ + size_t nChars = 0; + + if (buffer == 0) { + // This means that we should flush internal buffers. + return 0; + } + + // This implementation only writes to stdout and stderr. + // For all other file handles, it returns failure. + if (handle != _LLIO_STDOUT && handle != _LLIO_STDERR) { + return _LLIO_ERROR; + } + + for (; size != 0; --size) { + if (ptr_put(stdio_base, *buffer++) < 0) { + return _LLIO_ERROR; + } + ++nChars; + } + return nChars; +} + +_STD_END + + +#elif (defined(__GNUC__) && !XMEGA && !MEGA) + +int __attribute__((weak)) +_write (int file, const char *ptr, int len); + +int __attribute__((weak)) +_write (int file, const char *ptr, int len) +{ + int nChars = 0; + + if ((file != 1) && (file != 2) && (file!=3)) { + return -1; + } + + for (; len != 0; --len) { + if (ptr_put(stdio_base, *ptr++) < 0) { + return -1; + } + ++nChars; + } + return nChars; +} + +#elif (defined(__GNUC__) && (XMEGA || MEGA)) + +int _write (char c, int *f); + +int _write (char c, int *f) +{ + if (ptr_put(stdio_base, c) < 0) { + return -1; + } + return 1; +} +#endif + +/** + * \} + */ + diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/boards/sam3x_ek/init.c b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/boards/sam3x_ek/init.c new file mode 100644 index 0000000..41b0546 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/boards/sam3x_ek/init.c @@ -0,0 +1,213 @@ +/** + * \file + * + * \brief Arduino Due/X board init. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#include "compiler.h" +#include "board.h" +#include "conf_board.h" +#include "gpio.h" +#include "ioport.h" + +void board_init(void) +{ +#ifndef CONF_BOARD_KEEP_WATCHDOG_AT_INIT + /* Disable the watchdog */ + WDT->WDT_MR = WDT_MR_WDDIS; +#endif + + /* GPIO has been deprecated, the old code just keeps it for compatibility. + * In new designs IOPORT is used instead. + * Here IOPORT must be initialized for others to use before setting up IO. + */ + ioport_init(); + /* Configure LED pins */ + gpio_configure_pin(LED0_GPIO, LED0_FLAGS); + gpio_configure_pin(LED1_GPIO, LED1_FLAGS); + gpio_configure_pin(LED2_GPIO, LED2_FLAGS); + + /* Configure Push Button pins */ + gpio_configure_pin(GPIO_PUSH_BUTTON_1, GPIO_PUSH_BUTTON_1_FLAGS); + gpio_configure_pin(GPIO_PUSH_BUTTON_2, GPIO_PUSH_BUTTON_2_FLAGS); + +#ifdef CONF_BOARD_UART_CONSOLE + /* Configure UART pins */ + gpio_configure_group(PINS_UART_PIO, PINS_UART, PINS_UART_FLAGS); +#endif + + /* Configure ADC example pins */ +#ifdef CONF_BOARD_ADC + /* TC TIOA configuration */ + gpio_configure_pin(PIN_TC0_TIOA0,PIN_TC0_TIOA0_FLAGS); + + /* ADC Trigger configuration */ + gpio_configure_pin(PINS_ADC_TRIG, PINS_ADC_TRIG_FLAG); + + /* PWMH0 configuration */ + gpio_configure_pin(PIN_PWMC_PWMH0_TRIG, PIN_PWMC_PWMH0_TRIG_FLAG); +#endif + +#ifdef CONF_BOARD_PWM_LED0 + /* Configure PWM LED0 pin */ + gpio_configure_pin(PIN_PWM_LED0_GPIO, PIN_PWM_LED0_FLAGS); +#endif + +#ifdef CONF_BOARD_PWM_LED1 + /* Configure PWM LED1 pin */ + gpio_configure_pin(PIN_PWM_LED1_GPIO, PIN_PWM_LED1_FLAGS); +#endif + +#ifdef CONF_BOARD_PWM_LED2 + /* Configure PWM LED2 pin */ + gpio_configure_pin(PIN_PWM_LED2_GPIO, PIN_PWM_LED2_FLAGS); +#endif + + /* Configure SPI0 pins */ +#ifdef CONF_BOARD_SPI0 + gpio_configure_pin(SPI0_MISO_GPIO, SPI0_MISO_FLAGS); + gpio_configure_pin(SPI0_MOSI_GPIO, SPI0_MOSI_FLAGS); + gpio_configure_pin(SPI0_SPCK_GPIO, SPI0_SPCK_FLAGS); + + /** + * For NPCS 1, 2, and 3, different PINs can be used to access the same + * NPCS line. + * Depending on the application requirements, the default PIN may not be + * available. + * Hence a different PIN should be selected using the + * CONF_BOARD_SPI_NPCS_GPIO and + * CONF_BOARD_SPI_NPCS_FLAGS macros. + */ + +# ifdef CONF_BOARD_SPI0_NPCS0 + gpio_configure_pin(SPI0_NPCS0_GPIO, SPI0_NPCS0_FLAGS); +# endif + +# ifdef CONF_BOARD_SPI0_NPCS1 + gpio_configure_pin(SPI0_NPCS1_PA29_GPIO,SPI0_NPCS1_PA29_FLAGS); +# endif +#endif // #ifdef CONF_BOARD_SPI0 + + /* Configure SPI1 pins */ +#ifdef CONF_BOARD_SPI1 + gpio_configure_pin(SPI1_MISO_GPIO, SPI1_MISO_FLAGS); + gpio_configure_pin(SPI1_MOSI_GPIO, SPI1_MOSI_FLAGS); + gpio_configure_pin(SPI1_SPCK_GPIO, SPI1_SPCK_FLAGS); + +# ifdef CONF_BOARD_SPI1_NPCS0 + gpio_configure_pin(SPI1_NPCS0_GPIO, SPI1_NPCS0_FLAGS); +# endif + +# ifdef CONF_BOARD_SPI1_NPCS1 + gpio_configure_pin(SPI1_NPCS1_GPIO, SPI1_NPCS1_FLAGS); +# endif + +# ifdef CONF_BOARD_SPI1_NPCS2 + gpio_configure_pin(SPI1_NPCS2_GPIO, SPI1_NPCS2_FLAGS); +# endif + +# ifdef CONF_BOARD_SPI1_NPCS3 + gpio_configure_pin(SPI1_NPCS3_GPIO, SPI1_NPCS3_FLAGS); +# endif +#endif + +#ifdef CONF_BOARD_TWI0 + gpio_configure_pin(TWI0_DATA_GPIO, TWI0_DATA_FLAGS); + gpio_configure_pin(TWI0_CLK_GPIO, TWI0_CLK_FLAGS); +#endif + +#ifdef CONF_BOARD_TWI1 + gpio_configure_pin(TWI1_DATA_GPIO, TWI1_DATA_FLAGS); + gpio_configure_pin(TWI1_CLK_GPIO, TWI1_CLK_FLAGS); +#endif + +#ifdef CONF_BOARD_USART_RXD + /* Configure USART RXD pin */ + gpio_configure_pin(PIN_USART0_RXD_IDX, PIN_USART0_RXD_FLAGS); +#endif + +#ifdef CONF_BOARD_USART_TXD + /* Configure USART TXD pin */ + gpio_configure_pin(PIN_USART0_TXD_IDX, PIN_USART0_TXD_FLAGS); +#endif + +#ifdef CONF_BOARD_USB_PORT + /* Configure USB_ID (UOTGID) pin */ + gpio_configure_pin(USB_ID_GPIO, USB_ID_FLAGS); + /* Configure USB_VBOF (UOTGVBOF) pin */ + gpio_configure_pin(USB_VBOF_GPIO, USB_VBOF_FLAGS); +#endif + +#ifdef CONF_BOARD_MMA7341L + /* Configure MMA7341L mode set control pin */ + gpio_configure_pin(PIN_MMA7341L_MODE, PIN_MMA7341L_MODE_FLAG); + /* Configure MMA7341L x,y,z axis output voltage pin */ + gpio_configure_pin(PIN_MMA7341L_X_AXIS, PIN_MMA7341L_X_AXIS_FLAG); + gpio_configure_pin(PIN_MMA7341L_Y_AXIS, PIN_MMA7341L_Y_AXIS_FLAG); + gpio_configure_pin(PIN_MMA7341L_Z_AXIS, PIN_MMA7341L_Z_AXIS_FLAG); +#endif + +#ifdef CONF_BOARD_ADS7843 + /* Configure Touchscreen SPI pins */ + gpio_configure_pin(BOARD_ADS7843_IRQ_GPIO,BOARD_ADS7843_IRQ_FLAGS); + gpio_configure_pin(BOARD_ADS7843_BUSY_GPIO, BOARD_ADS7843_BUSY_FLAGS); + gpio_configure_pin(SPI0_MISO_GPIO, SPI0_MISO_FLAGS); + gpio_configure_pin(SPI0_MOSI_GPIO, SPI0_MOSI_FLAGS); + gpio_configure_pin(SPI0_SPCK_GPIO, SPI0_SPCK_FLAGS); + gpio_configure_pin(SPI0_NPCS0_GPIO, SPI0_NPCS0_FLAGS); +#endif + +#ifdef CONF_BOARD_EMAC + gpio_configure_pin(PIN_EEMAC_EREFCK, PIN_EMAC_FLAGS); + gpio_configure_pin(PIN_EMAC_ETX0, PIN_EMAC_FLAGS); + gpio_configure_pin(PIN_EMAC_ETX1, PIN_EMAC_FLAGS); + gpio_configure_pin(PIN_EMAC_ETXEN, PIN_EMAC_FLAGS); + gpio_configure_pin(PIN_EMAC_ECRSDV, PIN_EMAC_FLAGS); + gpio_configure_pin(PIN_EMAC_ERX0, PIN_EMAC_FLAGS); + gpio_configure_pin(PIN_EMAC_ERX1, PIN_EMAC_FLAGS); + gpio_configure_pin(PIN_EMAC_ERXER, PIN_EMAC_FLAGS); + gpio_configure_pin(PIN_EMAC_EMDC, PIN_EMAC_FLAGS); + gpio_configure_pin(PIN_EMAC_EMDIO, PIN_EMAC_FLAGS); +#endif + +} diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/boards/sam3x_ek/led.c b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/boards/sam3x_ek/led.c new file mode 100644 index 0000000..cdd8c2d --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/boards/sam3x_ek/led.c @@ -0,0 +1,109 @@ +/** + * \file + * + * \brief SAM3X-EK LEDs support package. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#include "board.h" +#include "led.h" +#include "gpio.h" + +#define ACTIVE_LEVEL_IS_HIGH 1 + +typedef const struct +{ + uint32_t ul_port_id; //!< LED GPIO port. + uint32_t ul_active_level; //!< Active level of the LED. +} tLED_DESCRIPTOR; + +//! Hardware descriptors of all LEDs. +static tLED_DESCRIPTOR LED_DESCRIPTOR[BOARD_NUM_OF_LED] = +{ +#define INSERT_LED_DESCRIPTOR(LED_NO, unused) \ + { \ + LED##LED_NO##_GPIO, LED##LED_NO##_ACTIVE_LEVEL \ + }, + MREPEAT(BOARD_NUM_OF_LED, INSERT_LED_DESCRIPTOR, ~) +#undef INSERT_LED_DESCRIPTOR +}; + +/*! \brief Turns off the specified LEDs. + * + * \param led_gpio LED to turn off (LEDx_GPIO). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +void LED_Off(uint32_t led_gpio) +{ + uint32_t i; + for (i = 0; i < BOARD_NUM_OF_LED; i++) { + if (led_gpio == LED_DESCRIPTOR[i].ul_port_id) { + if (LED_DESCRIPTOR[i].ul_active_level == ACTIVE_LEVEL_IS_HIGH) { + gpio_set_pin_low(led_gpio); + } else { + gpio_set_pin_high(led_gpio); + } + } + } +} + +/*! \brief Turns on the specified LEDs. + * + * \param led_gpio LED to turn on (LEDx_GPIO). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +void LED_On(uint32_t led_gpio) +{ + uint32_t i; + for (i = 0; i < BOARD_NUM_OF_LED; i++) { + if (led_gpio == LED_DESCRIPTOR[i].ul_port_id) { + if (LED_DESCRIPTOR[i].ul_active_level == ACTIVE_LEVEL_IS_HIGH) { + gpio_set_pin_high(led_gpio); + } else { + gpio_set_pin_low(led_gpio); + } + } + } +} + diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/boards/sam3x_ek/led.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/boards/sam3x_ek/led.h new file mode 100644 index 0000000..aee452d --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/boards/sam3x_ek/led.h @@ -0,0 +1,76 @@ +/** + * \file + * + * \brief SAM3X-EK LEDs support package. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _LED_H_ +#define _LED_H_ + +#include "gpio.h" + +/*! \brief Turns off the specified LEDs. + * + * \param led_gpio LED to turn off (LEDx_GPIO). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +void LED_Off(uint32_t led_gpio); + +/*! \brief Turns on the specified LEDs. + * + * \param led_gpio LED to turn on (LEDx_GPIO). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +void LED_On(uint32_t led_gpio); + +/*! \brief Toggles the specified LEDs. + * + * \param led_gpio LED to toggle (LEDx_GPIO). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +#define LED_Toggle(led_gpio) gpio_toggle_pin(led_gpio) + +#endif // _LED_H_ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/boards/sam3x_ek/sam3x_ek.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/boards/sam3x_ek/sam3x_ek.h new file mode 100644 index 0000000..a3a2551 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/boards/sam3x_ek/sam3x_ek.h @@ -0,0 +1,818 @@ +/** + * \file + * + * \brief Arduino Due/X Board Definition. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef ARDUINO_DUE_X_H_INCLUDED +#define ARDUINO_DUE_X_H_INCLUDED + +#include "compiler.h" +#include "system_sam3x.h" +#include "exceptions.h" + +/* ------------------------------------------------------------------------ */ + +/** + * \page arduino_due_x_opfreq "Arduino Due/X - Operating frequencies" + * This page lists several definition related to the board operating frequency + * + * \section Definitions + * - \ref BOARD_FREQ_* + * - \ref BOARD_MCK + */ + +/*! Board oscillator settings */ +#define BOARD_FREQ_SLCK_XTAL (32768U) +#define BOARD_FREQ_SLCK_BYPASS (32768U) +#define BOARD_FREQ_MAINCK_XTAL (12000000U) +#define BOARD_FREQ_MAINCK_BYPASS (12000000U) + +/*! Master clock frequency */ +#define BOARD_MCK CHIP_FREQ_CPU_MAX +#define BOARD_NO_32K_XTAL + +/** board main clock xtal startup time */ +#define BOARD_OSC_STARTUP_US 15625 + +/* ------------------------------------------------------------------------ */ + +/** + * \page arduino_due_x_board_info "Arduino Due/X - Board informations" + * This page lists several definition related to the board description. + * + * \section Definitions + * - \ref BOARD_NAME + */ + +/*! Name of the board */ +#define BOARD_NAME "Arduino Due/X" +/*! Board definition */ +#define arduinoduex +/*! Family definition (already defined) */ +#define sam3x +/*! Core definition */ +#define cortexm3 + +/* ------------------------------------------------------------------------ */ + +/** + * \page arduino_due_x_piodef "Arduino Due/X - PIO definitions" + * This pages lists all the pio definitions. The constants + * are named using the following convention: PIN_* for a constant which defines + * a single Pin instance (but may include several PIOs sharing the same + * controller), and PINS_* for a list of Pin instances. + * + */ + +/** + * \file + * ADC + * - \ref PIN_ADC0_AD1 + * - \ref PINS_ADC + * + */ + +/** + * \note ADC pins are automatically configured by the ADC peripheral as soon as + * the corresponding channel is enabled. + * + * \note On Arduino Due/X, Channel 1 is labelled A6 on the PCB. + */ + +/*! ADC_AD1 pin definition. */ +#define PIN_ADC0_AD1 {PIO_PA3X1_AD1, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT} +#define PINS_ADC_TRIG PIO_PA11_IDX +#define PINS_ADC_TRIG_FLAG (PIO_PERIPH_B | PIO_DEFAULT) +/*! Pins ADC */ +#define PINS_ADC PIN_ADC0_AD1 + +/** + * \file + * DAC + * + */ + +/** + * \note DAC pins are automatically configured by the DAC peripheral as soon + * as the corresponding channel is enabled. + * + * \note On Arduino Due/X, channel 0 is labelled A12 and channel 1 is labelled + * A13 on the PCB. + */ + + +/** + * \file + * LEDs + * + */ + +/* ------------------------------------------------------------------------ */ +/* LEDS */ +/* ------------------------------------------------------------------------ */ +/*! Power LED pin definition (ORANGE). L */ +#define PIN_POWER_LED {PIO_PB27, PIOB, ID_PIOB, PIO_OUTPUT_1, PIO_DEFAULT} +/*! LED #1 pin definition */ +#define PIN_USER_LED1 {PIO_PC21, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} +/*! LED #2 pin definition */ +#define PIN_USER_LED2 {PIO_PC22, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} +/*! LED #3 pin definition */ +#define PIN_USER_LED3 {PIO_PC23, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} + +/*! List of all LEDs definitions. */ +#define PINS_LEDS PIN_USER_LED1, PIN_USER_LED2, PIN_USER_LED3, PIN_POWER_LED + +/*! LED #0 "L" pin definition (ORANGE).*/ +#define LED_0_NAME "Orange_LED" +#define LED0_GPIO (PIO_PB27_IDX) +#define LED0_FLAGS (PIO_TYPE_PIO_OUTPUT_1 | PIO_DEFAULT) +#define LED0_ACTIVE_LEVEL 0 + +#define PIN_LED_0 {1 << 27, PIOB, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT} +#define PIN_LED_0_MASK (1 << 27) +#define PIN_LED_0_PIO PIOB +#define PIN_LED_0_ID ID_PIOB +#define PIN_LED_0_TYPE PIO_OUTPUT_0 +#define PIN_LED_0_ATTR PIO_DEFAULT + +/*! LED #1 pin definition */ +#define LED_1_NAME "External_LED_on_PWM9_connector_output" +#define LED1_GPIO (PIO_PC21_IDX) +#define LED1_FLAGS (PIO_TYPE_PIO_OUTPUT_1 | PIO_DEFAULT) +#define LED1_ACTIVE_LEVEL 0 + +#define PIN_LED_1 {1 << 21, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} +#define PIN_LED_1_MASK (1 << 21) +#define PIN_LED_1_PIO PIOC +#define PIN_LED_1_ID ID_PIOC +#define PIN_LED_1_TYPE PIO_OUTPUT_1 +#define PIN_LED_1_ATTR PIO_DEFAULT + +/*! LED #2 pin detection */ +#define LED2_GPIO (PIO_PC22_IDX) +#define LED2_FLAGS (PIO_TYPE_PIO_OUTPUT_1 | PIO_DEFAULT) +#define LED2_ACTIVE_LEVEL 0 + +#define PIN_LED_2 {1 << 22, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} +#define PIN_LED_2_MASK (1 << 22) +#define PIN_LED_2_PIO PIOC +#define PIN_LED_2_ID ID_PIOC +#define PIN_LED_2_TYPE PIO_OUTPUT_1 +#define PIN_LED_2_ATTR PIO_DEFAULT + +/*! LED #3 pin detection */ +#define LED3_GPIO (PIO_PC23_IDX) +#define LED3_FLAGS (PIO_TYPE_PIO_OUTPUT_1 | PIO_DEFAULT) +#define LED3_ACTIVE_LEVEL 1 + +#define BOARD_NUM_OF_LED 4 +#define PIN_LED_3 {1 << 23, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} +#define PIN_LED_3_MASK (1 << 23) +#define PIN_LED_3_PIO PIOC +#define PIN_LED_3_ID ID_PIOC +#define PIN_LED_3_TYPE PIO_OUTPUT_1 +#define PIN_LED_3_ATTR PIO_DEFAULT + +/** + * \file + * Push buttons + * - \ref PIN_PB_LEFT_CLICK + * - \ref PIN_PB_RIGHT_CLICK + * - \ref PINS_PUSHBUTTONS + * - \ref PUSHBUTTON_BP1 + * - \ref PUSHBUTTON_BP2 + * + */ + +/* ------------------------------------------------------------------------ */ +/* PUSHBUTTONS */ +/* ------------------------------------------------------------------------ */ + +/**************************changing**********************************/ + +/** Push button LEFT CLICK definition. + * Attributes = pull-up + debounce + interrupt on falling edge. */ +#define PIN_PB_LEFT_CLICK {PIO_PD8, PIOD, ID_PIOD, PIO_INPUT,\ + PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE} + +/** Push button RIGHT CLICK definition. + * Attributes = pull-up + debounce + interrupt on falling edge. */ +#define PIN_PB_RIGHT_CLICK {PIO_PC28, PIOC, ID_PIOC, PIO_INPUT,\ + PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE} + +/*! List of all push button definitions. */ +#define PINS_PUSHBUTTONS PIN_PB_LEFT_CLICK, PIN_PB_RIGHT_CLICK + +/*! Push button #1 index. */ +#define PUSHBUTTON_BP1 0 +/*! Push button #2 index. */ +#define PUSHBUTTON_BP2 1 + +/*! Push button LEFT CLICK index. */ +#define PUSHBUTTON_LEFT 0 +/*! Push button RIGHT CLICK index. */ +#define PUSHBUTTON_RIGHT 1 + +/** Push button #0 definition. + * Attributes = pull-up + debounce + interrupt on rising edge. */ +#define PUSHBUTTON_1_NAME "External_PB1_on_PWM12_connector_output" + +#define GPIO_PUSH_BUTTON_1 (PIO_PD8_IDX) +#define GPIO_PUSH_BUTTON_1_FLAGS\ + (PIO_INPUT | PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE) + +#define PIN_PUSHBUTTON_1 {PIO_PD8, PIOD, ID_PIOD, PIO_INPUT,\ + PIO_PULLUP } +#define PIN_PUSHBUTTON_1_MASK PIO_PD8 +#define PIN_PUSHBUTTON_1_PIO PIOD +#define PIN_PUSHBUTTON_1_ID ID_PIOD +#define PIN_PUSHBUTTON_1_TYPE PIO_INPUT +#define PIN_PUSHBUTTON_1_ATTR (PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE) + +/** Push button #1 definition. + * Attributes = pull-up + debounce + interrupt on falling edge. */ +#define PUSHBUTTON_2_NAME "External_PB2_on_PWM3_connector_output" +#define GPIO_PUSH_BUTTON_2 (PIO_PC28_IDX) +#define GPIO_PUSH_BUTTON_2_FLAGS\ + (PIO_INPUT | PIO_PULLUP) + +#define PIN_PUSHBUTTON_2 {PIO_PC28, PIOC, ID_PIOC, PIO_INPUT,\ + PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE} +#define PIN_PUSHBUTTON_2_MASK PIO_PC28 +#define PIN_PUSHBUTTON_2_PIO PIOC +#define PIN_PUSHBUTTON_2_ID ID_PIOC +#define PIN_PUSHBUTTON_2_TYPE PIO_INPUT +#define PIN_PUSHBUTTON_2_ATTR (PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE) + + +#define PIN_TC0_TIOA1 (PIO_PA2_IDX) +#define PIN_TC0_TIOA1_MUX (IOPORT_MODE_MUX_A) +#define PIN_TC0_TIOA1_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) + +#define PIN_TC0_TIOA1_PIO PIOA +#define PIN_TC0_TIOA1_MASK PIO_PA2 +#define PIN_TC0_TIOA1_ID ID_PIOA +#define PIN_TC0_TIOA1_TYPE PIO_PERIPH_A +#define PIN_TC0_TIOA1_ATTR PIO_DEFAULT + + +#define PIN_TC0_TIOA0 (PIO_PB25_IDX) +#define PIN_TC0_TIOA0_MUX (IOPORT_MODE_MUX_B) +#define PIN_TC0_TIOA0_FLAGS (PIO_INPUT | PIO_DEFAULT) + +#define PIN_TC0_TIOA0_PIO PIOB +#define PIN_TC0_TIOA0_MASK PIO_PB25 +#define PIN_TC0_TIOA0_ID ID_PIOB +#define PIN_TC0_TIOA0_TYPE PIO_INPUT +#define PIN_TC0_TIOA0_ATTR PIO_DEFAULT + +/** + * \file + * PWMC + * - \ref PIN_PWMC_PWMH0 + * - \ref PIN_PWMC_PWML4 + * - \ref PIN_PWMC_PWML5 + * - \ref PIN_PWMC_PWML6 + * - \ref PIN_PWM_LED0 + * - \ref PIN_PWM_LED1 + * - \ref PIN_PWM_LED2 + * + */ + +/* ------------------------------------------------------------------------ */ +/* PWM */ +/* ------------------------------------------------------------------------ */ +/*! PWMC PWM0 TRIG pin definition: Output High. */ +#define PIN_PWMC_PWMH0_TRIG PIO_PB12_IDX +#define PIN_PWMC_PWMH0_TRIG_FLAG PIO_PERIPH_B | PIO_DEFAULT + +/*! PWMC PWM4 pin definition: Output Low. */ +#define PIN_PWMC_PWML4\ + {PIO_PC21B_PWML4, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} +/*! PWMC PWM5 pin definition: Output Low. */ +#define PIN_PWMC_PWML5\ + {PIO_PC22B_PWML5, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} +/*! PWMC PWM6 pin definition: Output High. */ +#define PIN_PWMC_PWML6\ + {PIO_PC23B_PWML6, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} + +/*! PWM pins definition for LED0 */ +#define PIN_PWM_LED0 PIN_PWMC_PWML4 +/*! PWM pins definition for LED1 */ +#define PIN_PWM_LED1 PIN_PWMC_PWML5 +/*! PWM pins definition for LED2 */ +#define PIN_PWM_LED2 PIN_PWMC_PWML6 + + +/*! PWM channel for LED0 */ +#define CHANNEL_PWM_LED0 PWM_CHANNEL_4 +/*! PWM channel for LED1 */ +#define CHANNEL_PWM_LED1 PWM_CHANNEL_5 +/*! PWM channel for LED2 */ +#define CHANNEL_PWM_LED2 PWM_CHANNEL_6 + +/*! PWM "PWM7" LED0 pin definitions.*/ +#define PIN_PWM_LED0_GPIO PIO_PC21_IDX +#define PIN_PWM_LED0_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) +#define PIN_PWM_LED0_CHANNEL PWM_CHANNEL_4 + +/*! PWM "PWM8" LED1 pin definitions.*/ +#define PIN_PWM_LED1_GPIO PIO_PC22_IDX +#define PIN_PWM_LED1_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) +#define PIN_PWM_LED1_CHANNEL PWM_CHANNEL_5 + +/*! PWM "PWM9" LED2 pin definitions.*/ +#define PIN_PWM_LED2_GPIO PIO_PC23_IDX +#define PIN_PWM_LED2_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) +#define PIN_PWM_LED2_CHANNEL PWM_CHANNEL_6 + +/** + * \file + * SPI + * + */ + +/* ------------------------------------------------------------------------ */ +/* SPI */ +/* ------------------------------------------------------------------------ */ +/*! SPI0 MISO pin definition. */ +#define SPI0_MISO_GPIO (PIO_PA25_IDX) +#define SPI0_MISO_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +/*! SPI0 MOSI pin definition. */ +#define SPI0_MOSI_GPIO (PIO_PA26_IDX) +#define SPI0_MOSI_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +/*! SPI0 SPCK pin definition. */ +#define SPI0_SPCK_GPIO (PIO_PA27_IDX) +#define SPI0_SPCK_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) + +/*! SPI0 chip select 0 pin definition. (Only one configuration is possible) */ +#define SPI0_NPCS0_GPIO (PIO_PA28_IDX) +#define SPI0_NPCS0_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +/*! SPI0 chip select 1 pin definition. (multiple configurations are possible) */ +#define SPI0_NPCS1_PA29_GPIO (PIO_PA29_IDX) +#define SPI0_NPCS1_PA29_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +#define SPI0_NPCS1_PB20_GPIO (PIO_PB20_IDX) +#define SPI0_NPCS1_PB20_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) +/*! SPI0 chip select 2 pin definition. (multiple configurations are possible) */ +#define SPI0_NPCS2_PA30_GPIO (PIO_PA30_IDX) +#define SPI0_NPCS2_PA30_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +#define SPI0_NPCS2_PB21_GPIO (PIO_PB21_IDX) +#define SPI0_NPCS2_PB21_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) +/*! SPI0 chip select 3 pin definition. (multiple configurations are possible) */ +#define SPI0_NPCS3_PA31_GPIO (PIO_PA31_IDX) +#define SPI0_NPCS3_PA31_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +#define SPI0_NPCS3_PB23_GPIO (PIO_PB23_IDX) +#define SPI0_NPCS3_PB23_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) + +/*! SPI1 MISO pin definition. */ +#define SPI1_MISO_GPIO (PIO_PE28_IDX) +#define SPI1_MISO_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +/*! SPI1 MOSI pin definition. */ +#define SPI1_MOSI_GPIO (PIO_PE29_IDX) +#define SPI1_MOSI_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +/*! SPI1 SPCK pin definition. */ +#define SPI1_SPCK_GPIO (PIO_PE30_IDX) +#define SPI1_SPCK_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +/*! SPI1 chip select 0 pin definition. (Only one configuration is possible) */ +#define SPI1_NPCS0_GPIO (PIO_PE31_IDX) +#define SPI1_NPCS0_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +/*! SPI1 chip select 1 pin definition. (Only one configuration is possible) */ +#define SPI1_NPCS1_GPIO (PIO_PF0_IDX) +#define SPI1_NPCS1_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +/*! SPI1 chip select 2 pin definition. (Only one configuration is possible) */ +#define SPI1_NPCS2_GPIO (PIO_PF1_IDX) +#define SPI1_NPCS2_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +/*! SPI1 chip select 3 pin definition. (Only one configuration is possible) */ +#define SPI1_NPCS3_GPIO (PIO_PF2_IDX) +#define SPI1_NPCS3_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) + +/** + * \file + * SSC + * - \ref PIN_SSC_TD + * - \ref PIN_SSC_TK + * - \ref PIN_SSC_TF + * - \ref PIN_SSC_RD + * - \ref PIN_SSC_RK + * - \ref PIN_SSC_RF + * + */ +/* ------------------------------------------------------------------------ */ +/* SSC */ +/* ------------------------------------------------------------------------ */ +/** SSC pin Transmitter Data (TD) */ +#define PIN_SSC_TD (PIO_PA16_IDX) +#define PIN_SSC_TD_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) +/** SSC pin Transmitter Clock (TK) */ +#define PIN_SSC_TK (PIO_PA14_IDX) +#define PIN_SSC_TK_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) +/** SSC pin Transmitter FrameSync (TF) */ +#define PIN_SSC_TF (PIO_PA15_IDX) +#define PIN_SSC_TF_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) +/** SSC pin Receiver Data (RD) */ +#define PIN_SSC_RD (PIO_PB18_IDX) +#define PIN_SSC_RD_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +/** SSC pin Receiver Clock (RK) */ +#define PIN_SSC_RK (PIO_PB19_IDX) +#define PIN_SSC_RK_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +/** SSC pin Receiver FrameSync (RF) */ +#define PIN_SSC_RF (PIO_PB17_IDX) +#define PIN_SSC_RF_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) + +/** + * \file + * PCK0 + * - \ref PIN_PCK0 + * + */ + +/* ------------------------------------------------------------------------ */ +/* PCK */ +/* ------------------------------------------------------------------------ */ +/*! PCK0 */ +#define PIN_PCK0 (PIO_PA1_IDX) +#define PIN_PCK0_MUX (IOPORT_MODE_MUX_B) +#define PIN_PCK0_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) + +#define PIN_PCK_0_MASK PIO_PA1 +#define PIN_PCK_0_PIO PIOA +#define PIN_PCK_0_ID ID_PIOA +#define PIN_PCK_0_TYPE PIO_PERIPH_B +#define PIN_PCK_0_ATTR PIO_DEFAULT +/** + * \file + * UART + * - \ref PINS_UART + * + */ + +/* ------------------------------------------------------------------------ */ +/* UART */ +/* ------------------------------------------------------------------------ */ +/*! UART pins (UTXD0 and URXD0) definitions, PA8,9. (labeled RX0->0 and TX0->1)*/ +#define PINS_UART (PIO_PA8A_URXD | PIO_PA9A_UTXD) +#define PINS_UART_FLAGS (PIO_PERIPH_A | PIO_DEFAULT | PIO_PULLUP) + +#define PINS_UART_MASK (PIO_PA8A_URXD | PIO_PA9A_UTXD) +#define PINS_UART_PIO PIOA +#define PINS_UART_ID ID_PIOA +#define PINS_UART_TYPE PIO_PERIPH_A +#define PINS_UART_ATTR PIO_DEFAULT + +/** + * \file + * USART0 + * - \ref PIN_USART0_RXD + * - \ref PIN_USART0_TXD + */ +/* ------------------------------------------------------------------------ */ +/* USART0 */ +/* ------------------------------------------------------------------------ */ +#define PINS_USART0_MASK (PIO_PA10A_RXD0 | PIO_PA11A_TXD0) +#define PINS_USART0_PIO PIOA +#define PINS_USART0_ID ID_PIOA +#define PINS_USART0_TYPE PIO_PERIPH_A +#define PINS_USART0_ATTR PIO_DEFAULT +/*! USART0 pin RX (labeled RX1 19)*/ +#define PIN_USART0_RXD\ + {PIO_PA10A_RXD0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_USART0_RXD_IDX (PIO_PA10_IDX) +#define PIN_USART0_RXD_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) + +/*! USART0 pin TX (labeled TX1 18) */ +#define PIN_USART0_TXD\ + {PIO_PA11A_TXD0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_USART0_TXD_IDX (PIO_PA11_IDX) +#define PIN_USART0_TXD_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) + +/** + * \file + * USART1 + * - \ref PIN_USART1_RXD + * - \ref PIN_USART1_TXD + */ +/* ------------------------------------------------------------------------ */ +/* USART1 */ +/* ------------------------------------------------------------------------ */ +#define PINS_USART1_MASK (PIO_PA12A_RXD1 | PIO_PA13A_TXD1) +#define PINS_USART1_PIO PIOA +#define PINS_USART1_ID ID_PIOA +#define PINS_USART1_TYPE PIO_PERIPH_A +#define PINS_USART1_ATTR PIO_DEFAULT +/*! USART1 pin RX (labeled RX2 17) */ +#define PIN_USART1_RXD\ + {PIO_PA12A_RXD1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_USART1_RXD_IDX (PIO_PA12_IDX) +#define PIN_USART1_RXD_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +/*! USART1 pin TX (labeled TX2 16) */ +#define PIN_USART1_TXD\ + {PIO_PA13A_TXD1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_USART1_TXD_IDX (PIO_PA13_IDX) +#define PIN_USART1_TXD_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +/** + * \file + * USART3 + * - \ref PIN_USART3_RXD + * - \ref PIN_USART3_TXD + */ + +/* ------------------------------------------------------------------------ */ +/* USART3 */ +/* ------------------------------------------------------------------------ */ +#define PINS_USART3_MASK (PIO_PD5B_RXD3 | PIO_PD4B_TXD3) +#define PINS_USART3_PIO PIOD +#define PINS_USART3_ID ID_PIOD +#define PINS_USART3_TYPE PIO_PERIPH_B +#define PINS_USART3_ATTR PIO_DEFAULT +/*! USART3 pin RX (labeled RX3 15) */ +#define PIN_USART3_RXD\ + {PIO_PD5B_RXD3, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +#define PIN_USART3_RXD_IDX (PIO_PD5_IDX) +#define PIN_USART3_RXD_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) +/*! USART3 pin TX (labeled RX3 14) */ +#define PIN_USART3_TXD\ + {PIO_PD4B_TXD3, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +#define PIN_USART3_TXD_IDX (PIO_PD4_IDX) +#define PIN_USART3_TXD_FLAGS (PIO_PERIPH_B | PIO_DEFAULT) +/** + * \file + * USB + * - \ref PIN_USBOTG_VBOF + * - \ref PIN_USB_FAULT + * + */ + +/* ------------------------------------------------------------------------ */ +/* USB */ +/* ------------------------------------------------------------------------ */ +/*! USB OTG VBus On/Off: Bus Power Control Port. */ +#define PIN_UOTGHS_VBOF { PIO_PB10, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_PULLUP } +/*! USB OTG Identification: Mini Connector Identification Port. */ +#define PIN_UOTGHS_ID { PIO_PB11, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_PULLUP } + +/*! Multiplexed pin used for USB_ID: */ +#define USB_ID PIO_PB11_IDX +#define USB_ID_GPIO (PIO_PB11_IDX) +#define USB_ID_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +/*! Multiplexed pin used for USB_VBOF: */ +#define USB_VBOF PIO_PB10_IDX +#define USB_VBOF_GPIO (PIO_PB10_IDX) +#define USB_VBOF_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +/*! Active level of the USB_VBOF output pin. */ +#define USB_VBOF_ACTIVE_LEVEL LOW +/* ------------------------------------------------------------------------ */ +/** + * \file + * TWI + */ +/* ------------------------------------------------------------------------ */ +/* TWI */ +/* ------------------------------------------------------------------------ */ +/*! TWI0 pins definition */ +#define TWI0_DATA_GPIO PIO_PA17_IDX +#define TWI0_DATA_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +#define TWI0_CLK_GPIO PIO_PA18_IDX +#define TWI0_CLK_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) + +/*! TWI1 pins definition */ +#define TWI1_DATA_GPIO PIO_PB12_IDX +#define TWI1_DATA_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) +#define TWI1_CLK_GPIO PIO_PB13_IDX +#define TWI1_CLK_FLAGS (PIO_PERIPH_A | PIO_DEFAULT) + +/* ------------------------------------------------------------------------ */ +/** + * \file + * NMA7341 + * - \NMA7341L_CHANNEL + * - \PIN_NMA7341L + */ + + +/* ------------------------------------------------------------------------ */ +/** + * \file + * TouchScreen + * + * - \ref PIN_TSC_IRQ + * - \ref PIN_TSC_BUSY + * - \ref BOARD_TSC_SPI_BASE + * - \ref BOARD_TSC_SPI_ID + * - \ref BOARD_TSC_SPI_PINS + * - \ref BOARD_TSC_NPCS + * - \ref BOARD_TSC_NPCS_PIN + * + */ + +/* ------------------------------------------------------------------------ */ +/* Touchscreen */ +/* ------------------------------------------------------------------------ */ +/*! Touchscreen controller IRQ pin definition. */ +#define PIN_TSC_IRQ {PIO_PA31, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP} +/*! Touchscreen controller Busy pin definition. */ +#define PIN_TSC_BUSY {PIO_PA30, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP} + +/*! Chip select pin connected to the touchscreen controller. */ +/* We use PIO mode for chip select to meet ADS7843's timing specification */ +#define BOARD_TSC_NPCS_PIN\ + {PIO_PA28A_SPI0_NPCS0, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_PULLUP} + +/** + * \file + * EMAC + * - BOARD_EMAC_PHY_ADDR: Phy MAC address + * - BOARD_EMAC_MODE_RMII: Enable RMII connection with the PHY + */ +/*! EMAC pins */ + + +#define PIN_EEMAC_EREFCK PIO_PB0_IDX +#define PIN_EMAC_ETXEN PIO_PB1_IDX +#define PIN_EMAC_ETX0 PIO_PB2_IDX +#define PIN_EMAC_ETX1 PIO_PB3_IDX +#define PIN_EMAC_ECRSDV PIO_PB4_IDX +#define PIN_EMAC_ERX0 PIO_PB5_IDX +#define PIN_EMAC_ERX1 PIO_PB6_IDX +#define PIN_EMAC_ERXER PIO_PB7_IDX +#define PIN_EMAC_EMDC PIO_PB8_IDX +#define PIN_EMAC_EMDIO PIO_PB9_IDX +#define PIN_EMAC_FLAGS PIO_PERIPH_A | PIO_DEFAULT + +/*! EMAC PHY address */ +#define BOARD_EMAC_PHY_ADDR 0 +/*! EMAC RMII mode */ +#define BOARD_EMAC_MODE_RMII 1 + + +/* ------------------------------------------------------------------------ */ +/* NAND FLASH */ +/* ------------------------------------------------------------------------ */ +/* Chip select number for nand */ +#define BOARD_NAND_CS 0 + +/*! Address for transferring command bytes to the nandflash. */ +#define BOARD_NF_COMMAND_ADDR 0x60400000 +/*! Address for transferring address bytes to the nandflash. */ +#define BOARD_NF_ADDRESS_ADDR 0x60200000 +/*! Address for transferring data bytes to the nandflash. */ +#define BOARD_NF_DATA_ADDR 0x60000000 +/* Bus width for NAND */ +#define CONF_NF_BUSWIDTH 8 +/* SMC NFC using five address cycle */ +#define CONF_NF_NEED_FIVE_ADDRESS_CYCLES 1 +/* Access timing for NAND */ +#define CONF_NF_SETUP_TIMING (SMC_SETUP_NWE_SETUP(0) \ + | SMC_SETUP_NCS_WR_SETUP(0) \ + | SMC_SETUP_NRD_SETUP(0) \ + | SMC_SETUP_NCS_RD_SETUP(0)) +#define CONF_NF_PULSE_TIMING (SMC_PULSE_NWE_PULSE(2) \ + | SMC_PULSE_NCS_WR_PULSE(3) \ + | SMC_PULSE_NRD_PULSE(2) \ + | SMC_PULSE_NCS_RD_PULSE(3)) +#define CONF_NF_CYCLE_TIMING (SMC_CYCLE_NWE_CYCLE(3) \ + | SMC_CYCLE_NRD_CYCLE(3)) +#define CONF_NF_TIMING (SMC_TIMINGS_TCLR(1) \ + | SMC_TIMINGS_TADL(6) \ + | SMC_TIMINGS_TAR(4) \ + | SMC_TIMINGS_TRR(2) \ + | SMC_TIMINGS_TWB(9) \ + | SMC_TIMINGS_RBNSEL(7) \ + | (SMC_TIMINGS_NFSEL)) +/* Support DMA */ +#define CONF_NF_USE_DMA +#ifdef CONF_NF_USE_DMA +/* DMA channel used for NF */ +#define CONF_NF_DMA_CHANNEL 0 +#endif + +/* ------------------------------------------------------------------------ */ +/* SDRAM */ +/* ------------------------------------------------------------------------ */ +/*! Board SDRAM size for MT48LC16M16A2 */ +#define BOARD_SDRAM_SIZE (32 * 1024 * 1024) /* 32 MB */ + +/*! List of all SDRAM pins definitions */ +#define PIO_SDRAM_SDCKE PIO_PD13 +#define PIO_SDRAM_SDCS PIO_PD12 +#define PIO_SDRAM_RAS PIO_PD15 +#define PIO_SDRAM_CAS PIO_PD16 +#define PIO_SDRAM_BA0 PIO_PD6 +#define PIO_SDRAM_BA1 PIO_PD7 +#define PIO_SDRAM_SDWE PIO_PD14 +//#define PIO_SDRAM_NBS0 PIO_PC21 +#define PIO_SDRAM_NBS1 PIO_PD10 +#define PIO_SDRAM_DATA (0xffff << 2) /*PIO_PC2--PIO_PC17 */ +//#define PIO_SDRAM_SDA0_A7 (0xff << 23) /*PIO_PC23--PIO_PC30 */ +#define PIO_SDRAM_SDA8 PIO_PD22 +#define PIO_SDRAM_SDA9 PIO_PD23 +#define PIO_SDRAM_SDA11 PIO_PD25 +#define PIO_SDRAM_SDA12 PIO_PD4 +#define PIO_SDRAM_SDA10 PIO_PD11 + +/*! List of all SDRAM pins definitions */ +#define PINS_SDRAM_PIOC\ + { PIO_SDRAM_DATA | PIO_SDRAM_NBS0 | PIO_SDRAM_SDA0_A7,\ + PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP } + +#define PINS_SDRAM_PIOD\ + { PIO_SDRAM_SDCKE | PIO_SDRAM_SDCS |\ + PIO_SDRAM_RAS | PIO_SDRAM_CAS |\ + PIO_SDRAM_BA0 | PIO_SDRAM_BA1 |\ + PIO_SDRAM_SDWE | PIO_SDRAM_NBS1 |\ + PIO_SDRAM_SDA10 |\ + PIO_SDRAM_SDA8 | PIO_SDRAM_SDA9 |\ + PIO_SDRAM_SDA11 | PIO_SDRAM_SDA12,\ + PIOD, ID_PIOD, PIO_PERIPH_A, PIO_PULLUP } + +/* PIO18 is used as SDRAM Enable on EK-REVB board */ +#define PINS_SDRAM_EN\ + { (1 << 18), PIOD, ID_PIOD, PIO_OUTPUT_1, PIO_DEFAULT } + +#define PINS_SDRAM PINS_SDRAM_PIOC, PINS_SDRAM_PIOD, PINS_SDRAM_EN + +/*! SDRAM bus width */ +#define BOARD_SDRAM_BUSWIDTH 16 + +/* SDRAMC clock speed */ +#define SDRAMC_CLK (BOARD_MCK) + +/** + * \file + * \section NorFlash + * - \ref BOARD_NORFLASH_ADDR + * + */ + +/* ------------------------------------------------------------------------ */ +/* NOR FLASH */ +/* ------------------------------------------------------------------------ */ +/*! Address for transferring command bytes to the norflash. */ +#define BOARD_NORFLASH_ADDR 0x60000000 + +/*! TWI ID for EEPROM application to use */ +#define BOARD_ID_TWI_EEPROM ID_TWI0 +/*! TWI Base for TWI EEPROM application to use */ +#define BOARD_BASE_TWI_EEPROM TWI0 + +/*! USART RX pin for application */ +#define BOARD_PIN_USART_RXD PIN_USART0_RXD +/*! USART TX pin for application */ +#define BOARD_PIN_USART_TXD PIN_USART0_TXD +/*! USART Base for application */ +#define BOARD_USART_BASE USART0 +/*! USART ID for application */ +#define BOARD_ID_USART ID_USART0 +/*! USART1 Base for application */ +#define BOARD_USART1_BASE USART1 +/*! USART1 ID for application */ +#define BOARD_ID_USART1 ID_USART1 +/*! USART3 Base for application */ +#define BOARD_USART3_BASE USART3 +/*! USART3 ID for application */ +#define BOARD_ID_USART3 ID_USART3 + +#define CONSOLE_UART UART +#define CONSOLE_UART_ID ID_UART + +#endif /* ARDUINO_DUE_X_H_INCLUDED */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/components/ethernet_phy/dm9161a/ethernet_phy.c b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/components/ethernet_phy/dm9161a/ethernet_phy.c new file mode 100644 index 0000000..1f13fc9 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/components/ethernet_phy/dm9161a/ethernet_phy.c @@ -0,0 +1,427 @@ + /** + * \file + * + * \brief API driver for DM9161A PHY component. + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#include "ethernet_phy.h" +#include "emac.h" +#include "mii.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \defgroup dm9161a_ethernet_phy_group PHY component (DM9161A) + * + * Driver for the dm9161a component. This driver provides access to the main + * features of the PHY. + * + * \section dependencies Dependencies + * This driver depends on the following modules: + * - \ref emac_group Ethernet Media Access Controller (EMAC) module. + * + * @{ + */ + +/* Max PHY number */ +#define ETH_PHY_MAX_ADDR 31 + +/* Ethernet PHY operation max retry count */ +#define ETH_PHY_RETRY_MAX 1000000 + +/* Ethernet PHY operation timeout */ +#define ETH_PHY_TIMEOUT 10 + +/** + * \brief Find a valid PHY Address ( from addrStart to 31 ). + * + * \param p_emac Pointer to the EMAC instance. + * \param uc_phy_addr PHY address. + * \param uc_start_addr Start address of the PHY to be searched. + * + * \return 0xFF when no valid PHY address is found. + */ +static uint8_t ethernet_phy_find_valid(Emac *p_emac, uint8_t uc_phy_addr, + uint8_t addrStart) +{ + uint32_t ul_value = 0; + uint8_t uc_rc; + uint8_t uc_cnt; + uint8_t uc_phy_address = uc_phy_addr; + + emac_enable_management(p_emac, true); + + /* Check the current PHY address */ + uc_rc = uc_phy_address; + if (emac_phy_read(p_emac, uc_phy_addr, MII_PHYID1, &ul_value) != EMAC_OK) { + } + + /* Find another one */ + if (ul_value != MII_OUI_MSB) { + uc_rc = 0xFF; + for (uc_cnt = addrStart; uc_cnt <= ETH_PHY_MAX_ADDR; uc_cnt++) { + uc_phy_address = (uc_phy_address + 1) & 0x1F; + emac_phy_read(p_emac, uc_phy_address, MII_PHYID1, &ul_value); + if (ul_value == MII_OUI_MSB) { + uc_rc = uc_phy_address; + break; + } + } + } + + emac_enable_management(p_emac, false); + + if (uc_rc != 0xFF) { + emac_phy_read(p_emac, uc_phy_address, MII_DSCSR, &ul_value); + } + return uc_rc; +} + + +/** + * \brief Perform a HW initialization to the PHY ( via RSTC ) and set up clocks. + * + * This should be called only once to initialize the PHY pre-settings. + * The PHY address is the reset status of CRS, RXD[3:0] (the emacPins' pullups). + * The COL pin is used to select MII mode on reset (pulled up for Reduced MII). + * The RXDV pin is used to select test mode on reset (pulled up for test mode). + * The above pins should be predefined for corresponding settings in resetPins. + * The EMAC peripheral pins are configured after the reset is done. + * + * \param p_emac Pointer to the EMAC instance. + * \param uc_phy_addr PHY address. + * \param ul_mck EMAC MCK. + * + * Return EMAC_OK if successfully, EMAC_TIMEOUT if timeout. + */ +uint8_t ethernet_phy_init(Emac *p_emac, uint8_t uc_phy_addr, uint32_t mck) +{ + uint8_t uc_rc = EMAC_TIMEOUT; + uint8_t uc_phy; + + /* Configure EMAC runtime clock */ + uc_rc = emac_set_clock(p_emac, mck); + if (uc_rc != EMAC_OK) { + return 0; + } + + /* Check PHY Address */ + uc_phy = ethernet_phy_find_valid(p_emac, uc_phy_addr, 0); + if (uc_phy == 0xFF) { + return 0; + } + if (uc_phy != uc_phy_addr) { + ethernet_phy_reset(p_emac, uc_phy_addr); + } + + return uc_rc; +} + + +/** + * \brief Get the Link & speed settings, and automatically set up the EMAC with the + * settings. + * + * \param p_emac Pointer to the EMAC instance. + * \param uc_phy_addr PHY address. + * \param uc_apply_setting_flag Set to 0 to not apply the PHY configurations, else to apply. + * + * Return EMAC_OK if successfully, EMAC_TIMEOUT if timeout. + */ +uint8_t ethernet_phy_set_link(Emac *p_emac, uint8_t uc_phy_addr, + uint8_t uc_apply_setting_flag) +{ + uint32_t ul_stat1; + uint32_t ul_stat2; + uint8_t uc_phy_address, uc_speed, uc_fd; + uint8_t uc_rc = EMAC_TIMEOUT; + + emac_enable_management(p_emac, true); + + uc_phy_address = uc_phy_addr; + + uc_rc = emac_phy_read(p_emac, uc_phy_address, MII_BMSR, &ul_stat1); + if (uc_rc != EMAC_OK) { + /* Disable PHY management and start the EMAC transfer */ + emac_enable_management(p_emac, false); + + return uc_rc; + } + + if ((ul_stat1 & MII_LINK_STATUS) == 0) { + /* Disable PHY management and start the EMAC transfer */ + emac_enable_management(p_emac, false); + + return EMAC_INVALID; + } + + if (uc_apply_setting_flag == 0) { + /* Disable PHY management and start the EMAC transfer */ + emac_enable_management(p_emac, false); + + return uc_rc; + } + + /* Re-configure Link speed */ + uc_rc = emac_phy_read(p_emac, uc_phy_address, MII_DSCSR, &ul_stat2); + if (uc_rc != EMAC_OK) { + /* Disable PHY management and start the EMAC transfer */ + emac_enable_management(p_emac, false); + + return uc_rc; + } + + if ((ul_stat1 & MII_100BASE_TX_FD) && (ul_stat2 & MII_100FDX)) { + /* Set EMAC for 100BaseTX and Full Duplex */ + uc_speed = true; + uc_fd = true; + } + + if ((ul_stat1 & MII_10BASE_T_FD) && (ul_stat2 & MII_10FDX)) { + /* Set MII for 10BaseT and Full Duplex */ + uc_speed = false; + uc_fd = true; + } + + if ((ul_stat1 & MII_100BASE_T4_HD) && (ul_stat2 & MII_100HDX)) { + /* Set MII for 100BaseTX and Half Duplex */ + uc_speed = true; + uc_fd = false; + } + + if ((ul_stat1 & MII_10BASE_T_HD) && (ul_stat2 & MII_10HDX)) { + /* Set MII for 10BaseT and Half Duplex */ + uc_speed = false; + uc_fd = false; + } + + emac_set_speed(p_emac, uc_speed); + emac_enable_full_duplex(p_emac, uc_fd); + + /* Start the EMAC transfers */ + emac_enable_management(p_emac, false); + return uc_rc; +} + + +/** + * \brief Issue an auto negotiation of the PHY. + * + * \param p_emac Pointer to the EMAC instance. + * \param uc_phy_addr PHY address. + * + * Return EMAC_OK if successfully, EMAC_TIMEOUT if timeout. + */ +uint8_t ethernet_phy_auto_negotiate(Emac *p_emac, uint8_t uc_phy_addr) +{ + uint32_t ul_retry_max = ETH_PHY_RETRY_MAX; + uint32_t ul_value; + uint32_t ul_phy_anar; + uint32_t ul_phy_analpar; + uint32_t ul_retry_count = 0; + uint8_t uc_fd = 0; + uint8_t uc_speed = 0; + uint8_t uc_rc = EMAC_TIMEOUT; + + emac_enable_management(p_emac, true); + + /* Set up control register */ + uc_rc = emac_phy_read(p_emac, uc_phy_addr, MII_BMCR, &ul_value); + if (uc_rc != EMAC_OK) { + emac_enable_management(p_emac, false); + return uc_rc; + } + + ul_value &= ~MII_AUTONEG; /* Remove auto-negotiation enable */ + ul_value &= ~(MII_LOOPBACK | MII_POWER_DOWN); + ul_value |= MII_ISOLATE; /* Electrically isolate PHY */ + uc_rc = emac_phy_write(p_emac, uc_phy_addr, MII_BMCR, ul_value); + if (uc_rc != EMAC_OK) { + emac_enable_management(p_emac, false); + return uc_rc; + } + + /* + * Set the Auto_negotiation Advertisement Register. + * MII advertising for Next page. + * 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3. + */ + ul_phy_anar = MII_TX_FDX | MII_TX_HDX | MII_10_FDX | MII_10_HDX | + MII_AN_IEEE_802_3; + uc_rc = emac_phy_write(p_emac, uc_phy_addr, MII_ANAR, ul_phy_anar); + if (uc_rc != EMAC_OK) { + emac_enable_management(p_emac, false); + return uc_rc; + } + + /* Read & modify control register */ + uc_rc = emac_phy_read(p_emac, uc_phy_addr, MII_BMCR, &ul_value); + if (uc_rc != EMAC_OK) { + emac_enable_management(p_emac, false); + return uc_rc; + } + + ul_value |= MII_SPEED_SELECT | MII_AUTONEG | MII_DUPLEX_MODE; + uc_rc = emac_phy_write(p_emac, uc_phy_addr, MII_BMCR, ul_value); + if (uc_rc != EMAC_OK) { + emac_enable_management(p_emac, false); + return uc_rc; + } + + /* Restart auto negotiation */ + ul_value |= MII_RESTART_AUTONEG; + ul_value &= ~MII_ISOLATE; + uc_rc = emac_phy_write(p_emac, uc_phy_addr, MII_BMCR, ul_value); + if (uc_rc != EMAC_OK) { + emac_enable_management(p_emac, false); + return uc_rc; + } + + /* Check if auto negotiation is completed */ + while (1) { + uc_rc = emac_phy_read(p_emac, uc_phy_addr, MII_BMSR, &ul_value); + if (uc_rc != EMAC_OK) { + emac_enable_management(p_emac, false); + return uc_rc; + } + /* Done successfully */ + if (ul_value & MII_AUTONEG_COMP) { + break; + } + + /* Timeout check */ + if (ul_retry_max) { + if (++ul_retry_count >= ul_retry_max) { + emac_enable_management(p_emac, false); + return EMAC_TIMEOUT; + } + } + } + + /* Get the auto negotiate link partner base page */ + uc_rc = emac_phy_read(p_emac, uc_phy_addr, MII_ANLPAR, &ul_phy_analpar); + if (uc_rc != EMAC_OK) { + emac_enable_management(p_emac, false); + return uc_rc; + } + + /* Set up the EMAC link speed */ + if ((ul_phy_anar & ul_phy_analpar) & MII_TX_FDX) { + /* Set MII for 100BaseTX and Full Duplex */ + uc_speed = true; + uc_fd = true; + } else if ((ul_phy_anar & ul_phy_analpar) & MII_10_FDX) { + /* Set MII for 10BaseT and Full Duplex */ + uc_speed = false; + uc_fd = true; + } else if ((ul_phy_anar & ul_phy_analpar) & MII_TX_HDX) { + /* Set MII for 100BaseTX and half Duplex */ + uc_speed = true; + uc_fd = false; + } else if ((ul_phy_anar & ul_phy_analpar) & MII_10_HDX) { + /* Set MII for 10BaseT and half Duplex */ + uc_speed = false; + uc_fd = false; + } + + emac_set_speed(p_emac, uc_speed); + emac_enable_full_duplex(p_emac, uc_fd); + + emac_enable_rmii(p_emac, ETH_PHY_MODE); + emac_enable_transceiver_clock(p_emac, true); + + emac_enable_management(p_emac, false); + return uc_rc; +} + +/** + * \brief Issue a SW reset to reset all registers of the PHY. + * + * \param p_emac Pointer to the EMAC instance. + * \param uc_phy_addr PHY address. + * + * \Return EMAC_OK if successfully, EMAC_TIMEOUT if timeout. + */ +uint8_t ethernet_phy_reset(Emac *p_emac, uint8_t uc_phy_addr) +{ + uint32_t ul_bmcr = MII_RESET; + uint8_t uc_phy_address = uc_phy_addr; + uint32_t ul_timeout = ETH_PHY_TIMEOUT; + uint8_t uc_rc = EMAC_TIMEOUT; + + emac_enable_management(p_emac, true); + + ul_bmcr = MII_RESET; + emac_phy_write(p_emac, uc_phy_address, MII_BMCR, ul_bmcr); + + do { + emac_phy_read(p_emac, uc_phy_address, MII_BMCR, &ul_bmcr); + ul_timeout--; + } while ((ul_bmcr & MII_RESET) && ul_timeout); + + emac_enable_management(p_emac, false); + + if (!ul_timeout) { + uc_rc = EMAC_OK; + } + + return (uc_rc); +} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \} + */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/components/ethernet_phy/dm9161a/ethernet_phy.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/components/ethernet_phy/dm9161a/ethernet_phy.h new file mode 100644 index 0000000..b3064d2 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/components/ethernet_phy/dm9161a/ethernet_phy.h @@ -0,0 +1,123 @@ + /** + * \file + * + * \brief API driver for DM9161A PHY component. + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef DM9161A_H_INCLUDED +#define DM9161A_H_INCLUDED + +#include "compiler.h" +#include "board.h" +#include "emac.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus + extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \brief Perform a HW initialization to the PHY ( via RSTC ) and set up clocks. + * + * This should be called only once to initialize the PHY pre-settings. + * The PHY address is the reset status of CRS, RXD[3:0] (the emacPins' pullups). + * The COL pin is used to select MII mode on reset (pulled up for Reduced MII). + * The RXDV pin is used to select test mode on reset (pulled up for test mode). + * The above pins should be predefined for corresponding settings in resetPins. + * The EMAC peripheral pins are configured after the reset is done. + * + * \param p_emac Pointer to the EMAC instance. + * \param uc_phy_addr PHY address. + * \param ul_mck EMAC MCK. + * + * Return EMAC_OK if successfully, EMAC_TIMEOUT if timeout. + */ +uint8_t ethernet_phy_init(Emac *p_emac, uint8_t uc_phy_addr, uint32_t ul_mck); + + +/** + * \brief Get the Link & speed settings, and automatically set up the EMAC with the + * settings. + * + * \param p_emac Pointer to the EMAC instance. + * \param uc_phy_addr PHY address. + * \param uc_apply_setting_flag Set to 0 to not apply the PHY configurations, else to apply. + * + * Return EMAC_OK if successfully, EMAC_TIMEOUT if timeout. + */ +uint8_t ethernet_phy_set_link(Emac *p_emac, uint8_t uc_phy_addr, + uint8_t uc_apply_setting_flag); + + +/** + * \brief Issue an auto negotiation of the PHY. + * + * \param p_emac Pointer to the EMAC instance. + * \param uc_phy_addr PHY address. + * + * Return EMAC_OK if successfully, EMAC_TIMEOUT if timeout. + */ +uint8_t ethernet_phy_auto_negotiate(Emac *p_emac, uint8_t uc_phy_addr); + +/** + * \brief Issue a SW reset to reset all registers of the PHY. + * + * \param p_emac Pointer to the EMAC instance. + * \param uc_phy_addr PHY address. + * + * \Return EMAC_OK if successfully, EMAC_TIMEOUT if timeout. + */ +uint8_t ethernet_phy_reset(Emac *p_emac, uint8_t uc_phy_addr); + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +#endif /* DM9161A_H_INCLUDED */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/components/ethernet_phy/dm9161a/mii.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/components/ethernet_phy/dm9161a/mii.h new file mode 100644 index 0000000..beb09c1 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/components/ethernet_phy/dm9161a/mii.h @@ -0,0 +1,207 @@ +/** + * \file + * + * \brief Include definitions for the MII. + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef MII_H_INCLUDED +#define MII_H_INCLUDED + +/** \addtogroup eth_phy_mii + @{*/ + +/** \addtogroup mii_registers PHY registers Addresses + @{*/ +#define MII_BMCR 0 /**< Basic Mode Control Register */ +#define MII_BMSR 1 /**< Basic Mode Status Register */ +#define MII_PHYID1 2 /**< PHY Identifier Register 1 */ +#define MII_PHYID2 3 /**< PHY Identifier Register 2 */ +#define MII_ANAR 4 /**< Auto_negotiation Advertisement Register */ +#define MII_ANLPAR 5 /**< Auto_negotiation Link Partner Ability Register */ +#define MII_ANER 6 /**< Auto-negotiation Expansion Register */ +#define MII_DSCR 16 /**< Specified Configuration Register */ +#define MII_DSCSR 17 /**< Specified Configuration and Status Register */ +#define MII_10BTCSR 18 /**< 10BASE-T Configuration and Status Register */ +#define MII_PWDOR 19 /**< Power Down Control Register */ +#define MII_CONFIGR 20 /**< Specified configure Register */ +#define MII_MDINTR 21 /**< Specified Interrupt Register */ +#define MII_RECR 22 /**< Specified Receive Error Counter Register */ +#define MII_DISCR 23 /**< Specified Disconnect Counter Register */ +#define MII_RLSR 24 /**< Hardware Reset Latch State Register */ +/** @}*/ + +/** \addtogroup phy_bmcr Basic Mode Control Register (BMCR, 0) + List Bit definitions: \ref MII_BMCR + @{*/ +#define MII_RESET (1u << 15) /**< 1= Software Reset; 0=Normal Operation */ +#define MII_LOOPBACK (1u << 14) /**< 1=loopback Enabled; 0=Normal Operation */ +#define MII_SPEED_SELECT (1u << 13) /**< 1=100Mbps; 0=10Mbps */ +#define MII_AUTONEG (1u << 12) /**< Auto-negotiation Enable */ +#define MII_POWER_DOWN (1u << 11) /**< 1=Power down 0=Normal operation */ +#define MII_ISOLATE (1u << 10) /**< 1 = Isolate 0 = Normal operation */ +#define MII_RESTART_AUTONEG (1u << 9) /**< 1 = Restart auto-negotiation 0 = Normal operation */ +#define MII_DUPLEX_MODE (1u << 8) /**< 1 = Full duplex operation 0 = Normal operation */ +#define MII_COLLISION_TEST (1u << 7) /**< 1 = Collision test enabled 0 = Normal operation */ +/** Reserved bits: 6 to 0, Read as 0, ignore on write */ +/** @}*/ + +/** \addtogroup phy_bmsr Basic Mode Status Register (BMSR, 1) + List Bit definitions: \ref MII_BMSR + @{*/ +#define MII_100BASE_T4 (1u << 15) /**< 100BASE-T4 Capable */ +#define MII_100BASE_TX_FD (1u << 14) /**< 100BASE-TX Full Duplex Capable */ +#define MII_100BASE_T4_HD (1u << 13) /**< 100BASE-TX Half Duplex Capable */ +#define MII_10BASE_T_FD (1u << 12) /**< 10BASE-T Full Duplex Capable */ +#define MII_10BASE_T_HD (1u << 11) /**< 10BASE-T Half Duplex Capable */ +/** Reserved bits: 10 to 7, Read as 0, ignore on write */ +#define MII_MF_PREAMB_SUPPR (1u << 6) /**< MII Frame Preamble Suppression */ +#define MII_AUTONEG_COMP (1u << 5) /**< Auto-negotiation is completed */ +#define MII_REMOTE_FAULT (1u << 4) /**< Remote Fault */ +#define MII_AUTONEG_ABILITY (1u << 3) /**< Auto Configuration Ability */ +#define MII_LINK_STATUS (1u << 2) /**< Link Status */ +#define MII_JABBER_DETECT (1u << 1) /**< Jabber Detect */ +#define MII_EXTEND_CAPAB (1u << 0) /**< Extended Capability */ +/** @}*/ + +/** \addtogroup phy_id PHY ID Identifier Register (PHYID, 2,3) + List definitions: \ref MII_PHYID1, \ref MII_PHYID2 + @{*/ +#define MII_LSB_MASK 0x3F /**< Mask for PHY ID LSB */ + + +#define MII_OUI_MSB 0x0181 /** Davicom PHY OUI MSB */ +#define MII_OUI_LSB 0x2E /** Davicom PHY OUI LSB */ +/** @}*/ + +/** \addtogroup phy_neg Auto-negotiation (ANAR, 4; ANLPAR, 5) + - Auto-negotiation Advertisement Register (ANAR) + - Auto-negotiation Link Partner Ability Register (ANLPAR) + List Bit definitions: \ref MII_ANAR, \ref MII_ANLPAR + @{*/ +#define MII_NP (1u << 15) /**< Next page Indication */ +#define MII_ACK (1u << 14) /**< Acknowledge */ +#define MII_RF (1u << 13) /**< Remote Fault */ +/** Reserved: 12 to 11, Write as 0, ignore on read */ +#define MII_FCS (1u << 10) /**< Flow Control Support */ +#define MII_T4 (1u << 9) /**< 100BASE-T4 Support */ +#define MII_TX_FDX (1u << 8) /**< 100BASE-TX Full Duplex Support */ +#define MII_TX_HDX (1u << 7) /**< 100BASE-TX Support */ +#define MII_10_FDX (1u << 6) /**< 10BASE-T Full Duplex Support */ +#define MII_10_HDX (1u << 5) /**< 10BASE-T Support */ +/** Selector: 4 to 0, Protocol Selection Bits */ +#define MII_AN_IEEE_802_3 0x0001 +/** @}*/ + +/** \addtogroup phy_neg_exp Auto-negotiation Expansion Register (ANER, 6) + List Bit definitions: \ref MII_ANER + @{*/ +/** Reserved: 15 to 5, Read as 0, ignore on write */ +#define MII_PDF (1u << 4) /**< Local Device Parallel Detection Fault */ +#define MII_LP_NP_ABLE (1u << 3) /**< Link Partner Next Page Able */ +#define MII_NP_ABLE (1u << 2) /**< Local Device Next Page Able */ +#define MII_PAGE_RX (1u << 1) /**< New Page Received */ +#define MII_LP_AN_ABLE (1u << 0) /**< Link Partner Auto-negotiation Able */ +/** @}*/ + +/** \addtogroup phy_dscr Specified Configuration Register (DSCR, 16) + List Bit definitions: \ref MII_DSCR + @{*/ +#define MII_BP4B5B (1u << 15) /**< Bypass 4B5B Encoding and 5B4B Decoding */ +#define MII_BP_SCR (1u << 14) /**< Bypass Scrambler/Descrambler Function */ +#define MII_BP_ALIGN (1u << 13) /**< Bypass Symbol Alignment Function */ +#define MII_BP_ADPOK (1u << 12) /**< Bypass ADPOK */ +#define MII_REPEATER (1u << 11) /**< Repeater/Node Mode */ +#define MII_TX (1u << 10) /**< 100BASE-TX Mode Control */ +#define MII_FEF (1u << 9) /**< Far end Fault Enable */ +#define MII_RMII_ENABLE (1u << 8) /**< Reduced MII Enable */ +#define MII_F_LINK_100 (1u << 7) /**< Force Good Link in 100Mbps */ +#define MII_SPLED_CTL (1u << 6) /**< Speed LED Disable */ +#define MII_COLLED_CTL (1u << 5) /**< Collision LED Enable */ +#define MII_RPDCTR_EN (1u << 4) /**< Reduced Power Down Control Enable */ +#define MII_SM_RST (1u << 3) /**< Reset State Machine */ +#define MII_MFP_SC (1u << 2) /**< MF Preamble Suppression Control */ +#define MII_SLEEP (1u << 1) /**< Sleep Mode */ +#define MII_RLOUT (1u << 0) /**< Remote Loopout Control */ +/** @}*/ + +/** \addtogroup phy_dscsr Specified Configuration and Status Register (DSCSR, 17) + List Bit definitions: \ref MII_DSCSR + @{*/ +#define MII_100FDX (1u << 15) /**< 100M Full Duplex Operation Mode */ +#define MII_100HDX (1u << 14) /**< 100M Half Duplex Operation Mode */ +#define MII_10FDX (1u << 13) /**< 10M Full Duplex Operation Mode */ +#define MII_10HDX (1u << 12) /**< 10M Half Duplex Operation Mode */ +/** @}*/ + +/** \addtogroup phy_10btcsr 10BASE-T Configuration/Status (10BTCSR, 18) + List Bit definitions: \ref MII_10BTCSR + @{*/ +/** Reserved: 18 to 15, Read as 0, ignore on write */ +#define MII_LP_EN (1u << 14) /**< Link Pulse Enable */ +#define MII_HBE (1u << 13) /**< Heartbeat Enable */ +#define MII_SQUELCH (1u << 12) /**< Squelch Enable */ +#define MII_JABEN (1u << 11) /**< Jabber Enable */ +#define MII_10BT_SER (1u << 10) /**< 10BASE-T GPSI Mode */ +/** Reserved: 9 to 1, Read as 0, ignore on write */ +#define MII_POLR (1u << 0) /**< Polarity Reversed */ +/** @}*/ + +/** \addtogroup phy_mdintr Specified Interrupt Register (MDINTR, 21) + List Bit definitions: \ref MII_MDINTR + @{*/ +#define MII_INTR_PEND (1u << 15) /**< Interrupt Pending */ +/** Reserved: 14 to 12, Reserved */ +#define MII_FDX_MASK (1u << 11) /**< Full duplex Interrupt Mask */ +#define MII_SPD_MASK (1u << 10) /**< Speed Interrupt Mask */ +#define MII_LINK_MASK (1u << 9) /**< Link Interrupt Mask */ +#define MII_INTR_MASK (1u << 8) /**< Master Interrupt Mask */ +/** Reserved: 7 to 5, Reserved */ +#define MII_FDX_CHANGE (1u << 4) /**< Duplex Status Change Interrupt */ +#define MII_SPD_CHANGE (1u << 3) /**< Speed Status Change Interrupt */ +#define MII_LINK_CHANGE (1u << 2) /**< Link Status Change Interrupt */ +/** Reserved: 1, Reserved */ +#define MII_INTR_STATUS (1u << 0) /**< Interrupt Status */ +/** @}*/ + +/**@}*/ +#endif /* MII_H_INCLUDED */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/components/ethernet_phy/documentation.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/components/ethernet_phy/documentation.h new file mode 100644 index 0000000..6081641 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/components/ethernet_phy/documentation.h @@ -0,0 +1,75 @@ +/** + * \file + * + * \brief Ethernet Phy management + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/** + * + * \defgroup ethernet_phy_group Ethernet Phy + * + * This is the common API for Ethernet Phy on ARMs. Additional features are available + * in the documentation of the specific modules. + * + * \section ethernet_phy_group_platform Platform Dependencies + * + * The ethernet_phy API is partially chip- or platform-specific. While all + * platforms provide mostly the same functionality, there are some + * variations around how different bus types and clock tree structures + * are handled. + * + * The following functions are available on all platforms, but there may + * be variations in the function signature (i.e. parameters) and + * behaviour. These functions are typically called by platform-specific + * parts of drivers, and applications that aren't intended to be + * portable: + * - ethernet_phy_init() + * - ethernet_phy_set_link() + * - ethernet_phy_auto_negotiate() + * - ethernet_phy_reset() + * + * @{ + */ +/* + * Support and FAQ: visit Atmel Support + */ + +//! @} + diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/emac/emac.c b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/emac/emac.c new file mode 100644 index 0000000..d16f63e --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/emac/emac.c @@ -0,0 +1,787 @@ + /** + * \file + * + * \brief EMAC (Ethernet MAC) driver for SAM. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#include "compiler.h" +#include "emac.h" +#include + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \defgroup emac_group Ethernet Media Access Controller + * + * See \ref emac_quickstart. + * + * Driver for the EMAC (Ethernet Media Access Controller). + * This file contains basic functions for the EMAC, with support for all modes, settings + * and clock speeds. + * + * \section dependencies Dependencies + * This driver does not depend on other modules. + * + * @{ + */ + +/** TX descriptor lists */ +COMPILER_ALIGNED(8) +static emac_tx_descriptor_t gs_tx_desc[EMAC_TX_BUFFERS]; +/** TX callback lists */ +static emac_dev_tx_cb_t gs_tx_callback[EMAC_TX_BUFFERS]; +/** RX descriptors lists */ +COMPILER_ALIGNED(8) +static emac_rx_descriptor_t gs_rx_desc[EMAC_RX_BUFFERS]; +/** Send Buffer. Section 3.6 of AMBA 2.0 spec states that burst should not cross the + * 1K Boundaries. Receive buffer manager write operations are burst of 2 words => 3 lsb bits + * of the address shall be set to 0. + */ +COMPILER_ALIGNED(8) +static uint8_t gs_uc_tx_buffer[EMAC_TX_BUFFERS * EMAC_TX_UNITSIZE]; + +/** Receive Buffer */ +COMPILER_ALIGNED(8) +static uint8_t gs_uc_rx_buffer[EMAC_RX_BUFFERS * EMAC_RX_UNITSIZE]; + +/** + * EMAC device memory management struct. + */ +typedef struct emac_dev_mem { + /* Pointer to allocated buffer for RX. The address should be 8-byte aligned + and the size should be EMAC_RX_UNITSIZE * wRxSize. */ + uint8_t *p_rx_buffer; + /* Pointer to allocated RX descriptor list. */ + emac_rx_descriptor_t *p_rx_dscr; + /* RX size, in number of registered units (RX descriptors). */ + uint16_t us_rx_size; + /* Pointer to allocated buffer for TX. The address should be 8-byte aligned + and the size should be EMAC_TX_UNITSIZE * wTxSize. */ + uint8_t *p_tx_buffer; + /* Pointer to allocated TX descriptor list. */ + emac_tx_descriptor_t *p_tx_dscr; + /* TX size, in number of registered units (TX descriptors). */ + uint16_t us_tx_size; +} emac_dev_mem_t; + +/** Return count in buffer */ +#define CIRC_CNT(head,tail,size) (((head) - (tail)) % (size)) + +/* + * Return space available, from 0 to size-1. + * Always leave one free char as a completely full buffer that has (head == tail), + * which is the same as empty. + */ +#define CIRC_SPACE(head,tail,size) CIRC_CNT((tail),((head)+1),(size)) + +/** Circular buffer is empty ? */ +#define CIRC_EMPTY(head, tail) (head == tail) +/** Clear circular buffer */ +#define CIRC_CLEAR(head, tail) (head = tail = 0) + +/** Increment head or tail */ +static void circ_inc(uint16_t *headortail, uint32_t size) +{ + (*headortail)++; + if((*headortail) >= size) { + (*headortail) = 0; + } +} + +/** + * \brief Wait PHY operation to be completed. + * + * \param p_emac HW controller address. + * \param ul_retry The retry times, 0 to wait forever until completeness. + * + * Return EMAC_OK if the operation is completed successfully. + */ +static uint8_t emac_wait_phy(Emac* p_emac, const uint32_t ul_retry) +{ + volatile uint32_t ul_retry_count = 0; + + while (!emac_is_phy_idle(p_emac)) { + if (ul_retry == 0) { + continue; + } + + ul_retry_count++; + + if (ul_retry_count >= ul_retry) { + return EMAC_TIMEOUT; + } + } + return EMAC_OK; +} + +/** + * \brief Disable transfer, reset registers and descriptor lists. + * + * \param p_dev Pointer to EMAC driver instance. + * + */ +static void emac_reset_tx_mem(emac_device_t* p_dev) +{ + Emac *p_hw = p_dev->p_hw; + uint8_t *p_tx_buff = p_dev->p_tx_buffer; + emac_tx_descriptor_t *p_td = p_dev->p_tx_dscr; + + uint32_t ul_index; + uint32_t ul_address; + + /* Disable TX */ + emac_enable_transmit(p_hw, 0); + + /* Set up the TX descriptors */ + CIRC_CLEAR(p_dev->us_tx_head, p_dev->us_tx_tail); + for (ul_index = 0; ul_index < p_dev->us_tx_list_size; ul_index++) { + ul_address = (uint32_t) (&(p_tx_buff[ul_index * EMAC_TX_UNITSIZE])); + p_td[ul_index].addr = ul_address; + p_td[ul_index].status.val = EMAC_TXD_USED; + } + p_td[p_dev->us_tx_list_size - 1].status.val = + EMAC_TXD_USED | EMAC_TXD_WRAP; + + /* Set transmit buffer queue */ + emac_set_tx_queue(p_hw, (uint32_t) p_td); +} + +/** + * \brief Disable receiver, reset registers and descriptor list. + * + * \param p_drv Pointer to EMAC Driver instance. + */ +static void emac_reset_rx_mem(emac_device_t* p_dev) +{ + Emac *p_hw = p_dev->p_hw; + uint8_t *p_rx_buff = p_dev->p_rx_buffer; + emac_rx_descriptor_t *pRd = p_dev->p_rx_dscr; + + uint32_t ul_index; + uint32_t ul_address; + + /* Disable RX */ + emac_enable_receive(p_hw, 0); + + /* Set up the RX descriptors */ + p_dev->us_rx_idx = 0; + for (ul_index = 0; ul_index < p_dev->us_rx_list_size; ul_index++) { + ul_address = (uint32_t) (&(p_rx_buff[ul_index * EMAC_RX_UNITSIZE])); + pRd[ul_index].addr.val = ul_address & EMAC_RXD_ADDR_MASK; + pRd[ul_index].status.val = 0; + } + pRd[p_dev->us_rx_list_size - 1].addr.val |= EMAC_RXD_WRAP; + + /* Set receive buffer queue */ + emac_set_rx_queue(p_hw, (uint32_t) pRd); +} + + +/** + * \brief Initialize the allocated buffer lists for EMAC driver to transfer data. + * Must be invoked after emac_dev_init() but before RX/TX starts. + * + * \note If input address is not 8-byte aligned, the address is automatically + * adjusted and the list size is reduced by one. + * + * \param p_emac Pointer to EMAC instance. + * \param p_emac_dev Pointer to EMAC device instance. + * \param p_dev_mm Pointer to the EMAC memory management control block. + * \param p_tx_cb Pointer to allocated TX callback list. + * + * \return EMAC_OK or EMAC_PARAM. + */ +static uint8_t emac_init_mem(Emac* p_emac, emac_device_t* p_emac_dev, + emac_dev_mem_t* p_dev_mm, + emac_dev_tx_cb_t* p_tx_cb) +{ + if (p_dev_mm->us_rx_size <= 1 || p_dev_mm->us_tx_size <= 1 || p_tx_cb == NULL) { + return EMAC_PARAM; + } + + /* Assign RX buffers */ + if (((uint32_t) p_dev_mm->p_rx_buffer & 0x7) + || ((uint32_t) p_dev_mm->p_rx_dscr & 0x7)) { + p_dev_mm->us_rx_size--; + } + p_emac_dev->p_rx_buffer = + (uint8_t *) ((uint32_t) p_dev_mm->p_rx_buffer & 0xFFFFFFF8); + p_emac_dev->p_rx_dscr = + (emac_rx_descriptor_t *) ((uint32_t) p_dev_mm->p_rx_dscr + & 0xFFFFFFF8); + p_emac_dev->us_rx_list_size = p_dev_mm->us_rx_size; + + /* Assign TX buffers */ + if (((uint32_t) p_dev_mm->p_tx_buffer & 0x7) + || ((uint32_t) p_dev_mm->p_tx_dscr & 0x7)) { + p_dev_mm->us_tx_size--; + } + p_emac_dev->p_tx_buffer = + (uint8_t *) ((uint32_t) p_dev_mm->p_tx_buffer & 0xFFFFFFF8); + p_emac_dev->p_tx_dscr = + (emac_tx_descriptor_t *) ((uint32_t) p_dev_mm->p_tx_dscr + & 0xFFFFFFF8); + p_emac_dev->us_tx_list_size = p_dev_mm->us_tx_size; + p_emac_dev->func_tx_cb_list = p_tx_cb; + + /* Reset TX & RX */ + emac_reset_rx_mem(p_emac_dev); + emac_reset_tx_mem(p_emac_dev); + + /* Enable Rx and Tx, plus the statistics register */ + emac_enable_transmit(p_emac, true); + emac_enable_receive(p_emac, true); + emac_enable_statistics_write(p_emac, true); + + /* Set up the interrupts for transmission and errors */ + emac_enable_interrupt(p_emac, + EMAC_IER_RXUBR | /* Enable receive used bit read interrupt. */ + EMAC_IER_TUND | /* Enable transmit underrun interrupt. */ + EMAC_IER_RLE | /* Enable retry limit exceeded interrupt. */ + EMAC_IER_TXERR | /* Enable transmit buffers exhausted in mid-frame interrupt. */ + EMAC_IER_TCOMP | /* Enable transmit complete interrupt. */ + EMAC_IER_ROVR | /* Enable receive overrun interrupt. */ + EMAC_IER_HRESP | /* Enable Hresp not OK interrupt. */ + EMAC_IER_PFR | /* Enable pause frame received interrupt. */ + EMAC_IER_PTZ); /* Enable pause time zero interrupt. */ + + return EMAC_OK; +} + +/** + * \brief Read the PHY register. + * + * \param p_emac Pointer to the EMAC instance. + * \param uc_phy_address PHY address. + * \param uc_address Register address. + * \param p_value Pointer to a 32-bit location to store read data. + * + * \Return EMAC_OK if successfully, EMAC_TIMEOUT if timeout. + */ +uint8_t emac_phy_read(Emac* p_emac, uint8_t uc_phy_address, uint8_t uc_address, + uint32_t* p_value) +{ + emac_maintain_phy(p_emac, uc_phy_address, uc_address, 1, 0); + + if (emac_wait_phy(p_emac, MAC_PHY_RETRY_MAX) == EMAC_TIMEOUT) { + return EMAC_TIMEOUT; + } + *p_value = emac_get_phy_data(p_emac); + return EMAC_OK; +} + +/** + * \brief Write the PHY register. + * + * \param p_emac Pointer to the EMAC instance. + * \param uc_phy_address PHY Address. + * \param uc_address Register Address. + * \param ul_value Data to write, actually 16-bit data. + * + * \Return EMAC_OK if successfully, EMAC_TIMEOUT if timeout. + */ +uint8_t emac_phy_write(Emac* p_emac, uint8_t uc_phy_address, + uint8_t uc_address, uint32_t ul_value) +{ + emac_maintain_phy(p_emac, uc_phy_address, uc_address, 0, ul_value); + + if (emac_wait_phy(p_emac, MAC_PHY_RETRY_MAX) == EMAC_TIMEOUT) { + return EMAC_TIMEOUT; + } + return EMAC_OK; +} + +/** + * \brief Initialize the EMAC driver. + * + * \param p_emac Pointer to the EMAC instance. + * \param p_emac_dev Pointer to the EMAC device instance. + * \param p_opt EMAC configure options. + */ +void emac_dev_init(Emac* p_emac, emac_device_t* p_emac_dev, + emac_options_t* p_opt) +{ + emac_dev_mem_t emac_dev_mm; + + /* Disable TX & RX and more */ + emac_network_control(p_emac, 0); + emac_disable_interrupt(p_emac, ~0u); + + emac_clear_statistics(p_emac); + + /* Clear all status bits in the receive status register. */ + emac_clear_rx_status(p_emac, EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA); + + /* Clear all status bits in the transmit status register */ + emac_clear_tx_status(p_emac, EMAC_TSR_UBR | EMAC_TSR_COL | EMAC_TSR_RLES + | EMAC_TSR_BEX | EMAC_TSR_COMP | EMAC_TSR_UND); + + /* Clear interrupts */ + emac_get_interrupt_status(p_emac); + + /* Enable the copy of data into the buffers + ignore broadcasts, and not copy FCS. */ + emac_set_configure(p_emac, + emac_get_configure(p_emac) | EMAC_NCFGR_DRFCS | EMAC_NCFGR_PAE); + + emac_enable_copy_all(p_emac, p_opt->uc_copy_all_frame); + emac_disable_broadcast(p_emac, p_opt->uc_no_boardcast); + + /* Fill in EMAC device memory management */ + emac_dev_mm.p_rx_buffer = gs_uc_rx_buffer; + emac_dev_mm.p_rx_dscr = gs_rx_desc; + emac_dev_mm.us_rx_size = EMAC_RX_BUFFERS; + + emac_dev_mm.p_tx_buffer = gs_uc_tx_buffer; + emac_dev_mm.p_tx_dscr = gs_tx_desc; + emac_dev_mm.us_tx_size = EMAC_TX_BUFFERS; + + emac_init_mem(p_emac, p_emac_dev, &emac_dev_mm, gs_tx_callback); + + emac_set_address(p_emac, 0, p_opt->uc_mac_addr); + +} + +/** + * \brief Frames can be read from the EMAC in multiple sections. + * Read ul_frame_size bytes from the EMAC receive buffers to pcTo. + * p_rcv_size is the size of the entire frame. Generally emac_read + * will be repeatedly called until the sum of all the ul_frame_size equals + * the value of p_rcv_size. + * + * \param p_emac_dev Pointer to the EMAC device instance. + * \param p_frame Address of the frame buffer. + * \param ul_frame_size Length of the frame. + * \param p_rcv_size Received frame size. + * + * \return EMAC_OK if receiving frame successfully, otherwise failed. + */ +uint32_t emac_dev_read(emac_device_t* p_emac_dev, uint8_t* p_frame, + uint32_t ul_frame_size, uint32_t* p_rcv_size) +{ + uint16_t us_buffer_length; + uint32_t tmp_ul_frame_size = 0; + uint8_t *p_tmp_frame = 0; + uint16_t us_tmp_idx = p_emac_dev->us_rx_idx; + emac_rx_descriptor_t *p_rx_td = + &p_emac_dev->p_rx_dscr[p_emac_dev->us_rx_idx]; + int8_t c_is_frame = 0; + + if (p_frame == NULL) + return EMAC_PARAM; + + /* Set the default return value */ + *p_rcv_size = 0; + + /* Process received RX descriptor */ + while ((p_rx_td->addr.val & EMAC_RXD_OWNERSHIP) == EMAC_RXD_OWNERSHIP) { + /* A start of frame has been received, discard previous fragments */ + if ((p_rx_td->status.val & EMAC_RXD_SOF) == EMAC_RXD_SOF) { + /* Skip previous fragment */ + while (us_tmp_idx != p_emac_dev->us_rx_idx) { + p_rx_td = &p_emac_dev->p_rx_dscr[p_emac_dev->us_rx_idx]; + p_rx_td->addr.val &= ~(EMAC_RXD_OWNERSHIP); + + circ_inc(&p_emac_dev->us_rx_idx, p_emac_dev->us_rx_list_size); + } + /* Reset the temporary frame pointer */ + p_tmp_frame = p_frame; + tmp_ul_frame_size = 0; + /* Start to gather buffers in a frame */ + c_is_frame = 1; + } + + /* Increment the pointer */ + circ_inc(&us_tmp_idx, p_emac_dev->us_rx_list_size); + + /* Copy data in the frame buffer */ + if (c_is_frame) { + if (us_tmp_idx == p_emac_dev->us_rx_idx) { + do { + p_rx_td = &p_emac_dev->p_rx_dscr[p_emac_dev->us_rx_idx]; + p_rx_td->addr.val &= ~(EMAC_RXD_OWNERSHIP); + circ_inc(&p_emac_dev->us_rx_idx, p_emac_dev->us_rx_list_size); + + } while (us_tmp_idx != p_emac_dev->us_rx_idx); + + return EMAC_RX_NULL; + } + /* Copy the buffer into the application frame */ + us_buffer_length = EMAC_RX_UNITSIZE; + if ((tmp_ul_frame_size + us_buffer_length) > ul_frame_size) { + us_buffer_length = ul_frame_size - tmp_ul_frame_size; + } + + memcpy(p_tmp_frame, + (void *)(p_rx_td->addr.val & EMAC_RXD_ADDR_MASK), + us_buffer_length); + p_tmp_frame += us_buffer_length; + tmp_ul_frame_size += us_buffer_length; + + /* An end of frame has been received, return the data */ + if ((p_rx_td->status.val & EMAC_RXD_EOF) == EMAC_RXD_EOF) { + /* Frame size from the EMAC */ + *p_rcv_size = (p_rx_td->status.val & EMAC_RXD_LEN_MASK); + + /* All data have been copied in the application frame buffer => release TD */ + while (p_emac_dev->us_rx_idx != us_tmp_idx) { + p_rx_td = &p_emac_dev->p_rx_dscr[p_emac_dev->us_rx_idx]; + p_rx_td->addr.val &= ~(EMAC_RXD_OWNERSHIP); + circ_inc(&p_emac_dev->us_rx_idx, p_emac_dev->us_rx_list_size); + } + + /* Application frame buffer is too small so that all data have not been copied */ + if (tmp_ul_frame_size < *p_rcv_size) { + return EMAC_SIZE_TOO_SMALL; + } + + return EMAC_OK; + } + } + /* SOF has not been detected, skip the fragment */ + else { + p_rx_td->addr.val &= ~(EMAC_RXD_OWNERSHIP); + p_emac_dev->us_rx_idx = us_tmp_idx; + } + + /* Process the next buffer */ + p_rx_td = &p_emac_dev->p_rx_dscr[us_tmp_idx]; + } + + return EMAC_RX_NULL; +} + +/** + * \brief Send ulLength bytes from pcFrom. This copies the buffer to one of the + * EMAC Tx buffers, and then indicates to the EMAC that the buffer is ready. + * If lEndOfFrame is true then the data being copied is the end of the frame + * and the frame can be transmitted. + * + * \param p_emac_dev Pointer to the EMAC device instance. + * \param p_buffer Pointer to the data buffer. + * \param ul_size Length of the frame. + * \param func_tx_cb Transmit callback function. + * + * \return Length sent. + */ +uint32_t emac_dev_write(emac_device_t* p_emac_dev, void *p_buffer, + uint32_t ul_size, emac_dev_tx_cb_t func_tx_cb) +{ + + volatile emac_tx_descriptor_t *p_tx_td; + volatile emac_dev_tx_cb_t *p_func_tx_cb; + + Emac *p_hw = p_emac_dev->p_hw; + + + /* Check parameter */ + if (ul_size > EMAC_TX_UNITSIZE) { + return EMAC_PARAM; + } + + /* Pointers to the current transmit descriptor */ + p_tx_td = &p_emac_dev->p_tx_dscr[p_emac_dev->us_tx_head]; + + /* If no free TxTd, buffer can't be sent, schedule the wakeup callback */ + if (CIRC_SPACE(p_emac_dev->us_tx_head, p_emac_dev->us_tx_tail, + p_emac_dev->us_tx_list_size) == 0) { + return EMAC_TX_BUSY; + } + + /* Pointers to the current Tx callback */ + p_func_tx_cb = &p_emac_dev->func_tx_cb_list[p_emac_dev->us_tx_head]; + + /* Set up/copy data to transmission buffer */ + if (p_buffer && ul_size) { + /* Driver manages the ring buffer */ + memcpy((void *)p_tx_td->addr, p_buffer, ul_size); + } + + /* Tx callback */ + *p_func_tx_cb = func_tx_cb; + + /* Update transmit descriptor status */ + + /* The buffer size defined is the length of ethernet frame, + so it's always the last buffer of the frame. */ + if (p_emac_dev->us_tx_head == p_emac_dev->us_tx_list_size - 1) { + p_tx_td->status.val = + (ul_size & EMAC_TXD_LEN_MASK) | EMAC_TXD_LAST + | EMAC_TXD_WRAP; + } else { + p_tx_td->status.val = + (ul_size & EMAC_TXD_LEN_MASK) | EMAC_TXD_LAST; + } + + circ_inc(&p_emac_dev->us_tx_head, p_emac_dev->us_tx_list_size); + + /* Now start to transmit if it is still not done */ + emac_start_transmission(p_hw); + + return EMAC_OK; +} + +/** + * \brief Get current load of transmit. + * + * \param p_emac_dev Pointer to the EMAC device instance. + * + * \return Current load of transmit. + */ +uint32_t emac_dev_get_tx_load(emac_device_t* p_emac_dev) +{ + uint16_t us_head = p_emac_dev->us_tx_head; + uint16_t us_tail = p_emac_dev->us_tx_tail; + return CIRC_CNT(us_head, us_tail, p_emac_dev->us_tx_list_size); +} + +/** + * \brief Register/Clear RX callback. Callback will be invoked after the next received + * frame. + * + * When emac_dev_read() returns EMAC_RX_NULL, the application task calls + * emac_dev_set_rx_callback() to register func_rx_cb() callback and enters suspend state. + * The callback is in charge to resume the task once a new frame has been + * received. The next time emac_dev_read() is called, it will be successful. + * + * This function is usually invoked from the RX callback itself with NULL + * callback, to unregister. Once the callback has resumed the application task, + * there is no need to invoke the callback again. + * + * \param p_emac_dev Pointer to the EMAC device instance. + * \param func_tx_cb Receive callback function. + */ +void emac_dev_set_rx_callback(emac_device_t* p_emac_dev, + emac_dev_tx_cb_t func_rx_cb) +{ + Emac *p_hw = p_emac_dev->p_hw; + + if (func_rx_cb == NULL) { + emac_disable_interrupt(p_hw, EMAC_IDR_RCOMP); + p_emac_dev->func_rx_cb = NULL; + } else { + p_emac_dev->func_rx_cb = func_rx_cb; + emac_enable_interrupt(p_hw, EMAC_IER_RCOMP); + } +} + +/** + * \brief Register/Clear TX wakeup callback. + * + * When emac_dev_write() returns EMAC_TX_BUSY (all transmit descriptor busy), the application + * task calls emac_dev_set_tx_wakeup_callback() to register func_wakeup() callback and + * enters suspend state. The callback is in charge to resume the task once + * several transmit descriptors have been released. The next time emac_dev_write() will be called, + * it shall be successful. + * + * This function is usually invoked with NULL callback from the TX wakeup + * callback itself, to unregister. Once the callback has resumed the + * application task, there is no need to invoke the callback again. + * + * \param p_emac_dev Pointer to EMAC device instance. + * \param func_wakeup Pointer to wakeup callback function. + * \param uc_threshold Number of free transmit descriptor before wakeup callback invoked. + * + * \return EMAC_OK, EMAC_PARAM on parameter error. + */ +uint8_t emac_dev_set_tx_wakeup_callback(emac_device_t* p_emac_dev, + emac_dev_wakeup_cb_t func_wakeup_cb, uint8_t uc_threshold) +{ + if (func_wakeup_cb == NULL) { + p_emac_dev->func_wakeup_cb = NULL; + } else { + if (uc_threshold <= p_emac_dev->us_tx_list_size) { + p_emac_dev->func_wakeup_cb = func_wakeup_cb; + p_emac_dev->uc_wakeup_threshold = uc_threshold; + } else { + return EMAC_PARAM; + } + } + + return EMAC_OK; +} + + +/** + * \brief Reset TX & RX queue & statistics. + * + * \param p_emac_dev Pointer to EMAC device instance. + */ +void emac_dev_reset(emac_device_t* p_emac_dev) +{ + Emac *p_hw = p_emac_dev->p_hw; + + emac_reset_rx_mem(p_emac_dev); + emac_reset_tx_mem(p_emac_dev); + emac_network_control(p_hw, EMAC_NCR_TE | EMAC_NCR_RE + | EMAC_NCR_WESTAT | EMAC_NCR_CLRSTAT); +} + + +/** + * \brief EMAC Interrupt handler. + * + * \param p_emac_dev Pointer to EMAC device instance. + */ +void emac_handler(emac_device_t* p_emac_dev) +{ + Emac *p_hw = p_emac_dev->p_hw; + + emac_tx_descriptor_t *p_tx_td; + emac_dev_tx_cb_t *p_tx_cb; + volatile uint32_t ul_isr; + volatile uint32_t ul_rsr; + volatile uint32_t ul_tsr; + uint32_t ul_rx_status_flag; + uint32_t ul_tx_status_flag; + + ul_isr = emac_get_interrupt_status(p_hw); + ul_rsr = emac_get_rx_status(p_hw); + ul_tsr = emac_get_tx_status(p_hw); + + ul_isr &= ~(emac_get_interrupt_mask(p_hw) | 0xFFC300); + + /* RX packet */ + if ((ul_isr & EMAC_ISR_RCOMP) || (ul_rsr & EMAC_RSR_REC)) { + ul_rx_status_flag = EMAC_RSR_REC; + + /* Check OVR */ + if (ul_rsr & EMAC_RSR_OVR) { + ul_rx_status_flag |= EMAC_RSR_OVR; + } + /* Check BNA */ + if (ul_rsr & EMAC_RSR_BNA) { + ul_rx_status_flag |= EMAC_RSR_BNA; + } + /* Clear status */ + emac_clear_rx_status(p_hw, ul_rx_status_flag); + + /* Invoke callbacks */ + if (p_emac_dev->func_rx_cb) { + p_emac_dev->func_rx_cb(ul_rx_status_flag); + } + } + + /* TX packet */ + if ((ul_isr & EMAC_ISR_TCOMP) || (ul_tsr & EMAC_TSR_COMP)) { + + ul_tx_status_flag = EMAC_TSR_COMP; + + /* A frame transmitted */ + + /* Check RLE */ + if (ul_tsr & EMAC_TSR_RLES) { + /* Status RLE & Number of discarded buffers */ + ul_tx_status_flag = EMAC_TSR_RLES | CIRC_CNT(p_emac_dev->us_tx_head, + p_emac_dev->us_tx_tail, p_emac_dev->us_tx_list_size); + p_tx_cb = &p_emac_dev->func_tx_cb_list[p_emac_dev->us_tx_tail]; + emac_reset_tx_mem(p_emac_dev); + emac_enable_transmit(p_hw, 1); + } + /* Check COL */ + if (ul_tsr & EMAC_TSR_COL) { + ul_tx_status_flag |= EMAC_TSR_COL; + } + /* Check BEX */ + if (ul_tsr & EMAC_TSR_BEX) { + ul_tx_status_flag |= EMAC_TSR_BEX; + } + /* Check UND */ + if (ul_tsr & EMAC_TSR_UND) { + ul_tx_status_flag |= EMAC_TSR_UND; + } + /* Clear status */ + emac_clear_tx_status(p_hw, ul_tx_status_flag); + + if (!CIRC_EMPTY(p_emac_dev->us_tx_head, p_emac_dev->us_tx_tail)) { + /* Check the buffers */ + do { + p_tx_td = &p_emac_dev->p_tx_dscr[p_emac_dev->us_tx_tail]; + p_tx_cb = &p_emac_dev->func_tx_cb_list[p_emac_dev->us_tx_tail]; + /* Any error? Exit if buffer has not been sent yet */ + if ((p_tx_td->status.val & EMAC_TXD_USED) == 0) { + break; + } + + /* Notify upper layer that a packet has been sent */ + if (*p_tx_cb) { + (*p_tx_cb) (ul_tx_status_flag); + } + + circ_inc(&p_emac_dev->us_tx_tail, p_emac_dev->us_tx_list_size); + } while (CIRC_CNT(p_emac_dev->us_tx_head, p_emac_dev->us_tx_tail, + p_emac_dev->us_tx_list_size)); + } + + if (ul_tsr & EMAC_TSR_RLES) { + /* Notify upper layer RLE */ + if (*p_tx_cb) { + (*p_tx_cb) (ul_tx_status_flag); + } + } + + /* If a wakeup has been scheduled, notify upper layer that it can + send other packets, and the sending will be successful. */ + if ((CIRC_SPACE(p_emac_dev->us_tx_head, p_emac_dev->us_tx_tail, + p_emac_dev->us_tx_list_size) >= p_emac_dev->uc_wakeup_threshold) + && p_emac_dev->func_wakeup_cb) { + p_emac_dev->func_wakeup_cb(); + } + } +} + +//@} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/emac/emac.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/emac/emac.h new file mode 100644 index 0000000..e1e3eb3 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/emac/emac.h @@ -0,0 +1,1248 @@ + /** + * \file + * + * \brief EMAC (Ethernet MAC) driver for SAM. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef EMAC_H_INCLUDED +#define EMAC_H_INCLUDED + +#include "compiler.h" +#include "conf_eth.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** The buffer addresses written into the descriptors must be aligned, so the + last few bits are zero. These bits have special meaning for the EMAC + peripheral and cannot be used as part of the address. */ +#define EMAC_RXD_ADDR_MASK 0xFFFFFFFC +#define EMAC_RXD_WRAP (1ul << 1) /**< Wrap bit */ +#define EMAC_RXD_OWNERSHIP (1ul << 0) /**< Ownership bit */ + +#define EMAC_RXD_BROADCAST (1ul << 31) /**< Broadcast detected */ +#define EMAC_RXD_MULTIHASH (1ul << 30) /**< Multicast hash match */ +#define EMAC_RXD_UNIHASH (1ul << 29) /**< Unicast hash match */ +#define EMAC_RXD_EXTADDR (1ul << 28) /**< External address match */ +#define EMAC_RXD_ADDR1 (1ul << 26) /**< Address 1 match */ +#define EMAC_RXD_ADDR2 (1ul << 25) /**< Address 2 match */ +#define EMAC_RXD_ADDR3 (1ul << 24) /**< Address 3 match */ +#define EMAC_RXD_ADDR4 (1ul << 23) /**< Address 4 match */ +#define EMAC_RXD_TYPE (1ul << 22) /**< Type ID match */ +#define EMAC_RXD_VLAN (1ul << 21) /**< VLAN tag detected */ +#define EMAC_RXD_PRIORITY (1ul << 20) /**< Priority tag detected */ +#define EMAC_RXD_PRIORITY_MASK (3ul << 17) /**< VLAN priority */ +#define EMAC_RXD_CFI (1ul << 16) /**< Concatenation Format Indicator only if bit 21 is set */ +#define EMAC_RXD_EOF (1ul << 15) /**< End of frame */ +#define EMAC_RXD_SOF (1ul << 14) /**< Start of frame */ +#define EMAC_RXD_OFFSET_MASK /**< Receive buffer offset */ +#define EMAC_RXD_LEN_MASK (0xFFF) /**< Length of frame including FCS (if selected) */ +#define EMAC_RXD_LENJUMBO_MASK (0x3FFF) /**< Jumbo frame length */ + +#define EMAC_TXD_USED (1ul << 31) /**< Frame is transmitted */ +#define EMAC_TXD_WRAP (1ul << 30) /**< Last descriptor */ +#define EMAC_TXD_ERROR (1ul << 29) /**< Retry limit exceeded, error */ +#define EMAC_TXD_UNDERRUN (1ul << 28) /**< Transmit underrun */ +#define EMAC_TXD_EXHAUSTED (1ul << 27) /**< Buffer exhausted */ +#define EMAC_TXD_NOCRC (1ul << 16) /**< No CRC */ +#define EMAC_TXD_LAST (1ul << 15) /**< Last buffer in frame */ +#define EMAC_TXD_LEN_MASK (0x7FF) /**< Length of buffer */ + +/** The MAC can support frame lengths up to 1536 bytes */ +#define EMAC_FRAME_LENTGH_MAX 1536 + +#define EMAC_RX_UNITSIZE 128 /**< Fixed size for RX buffer */ +#define EMAC_TX_UNITSIZE 1518 /**< Size for ETH frame length */ + +/** EMAC clock speed */ +#define EMAC_CLOCK_SPEED_160MHZ (160*1000*1000) +#define EMAC_CLOCK_SPEED_80MHZ (80*1000*1000) +#define EMAC_CLOCK_SPEED_40MHZ (40*1000*1000) +#define EMAC_CLOCK_SPEED_20MHZ (20*1000*1000) + +/** EMAC maintain code default value*/ +#define EMAC_MAN_CODE_VALUE (10) + +/** EMAC maintain start of frame default value*/ +#define EMAC_MAN_SOF_VALUE (1) + +/** EMAC maintain read/write*/ +#define EMAC_MAN_RW_TYPE (2) + +/** EMAC maintain read only*/ +#define EMAC_MAN_READ_ONLY (1) + +/** EMAC address length */ +#define EMAC_ADDR_LENGTH (6) + +/** + * \brief Return codes for EMAC APIs. + */ +typedef enum { + EMAC_OK = 0, /** Operation OK */ + EMAC_TIMEOUT = 1, /** EMAC operation timeout */ + EMAC_TX_BUSY, /** TX in progress */ + EMAC_RX_NULL, /** No data received */ + EMAC_SIZE_TOO_SMALL, /** Buffer size not enough */ + EMAC_PARAM, /** Parameter error, TX packet invalid or RX size too small */ + EMAC_INVALID = 0xFF, /* Invalid */ +} emac_status_t; + +/** Receive buffer descriptor struct */ +COMPILER_PACK_SET(8) +typedef struct emac_rx_descriptor { + union emac_rx_addr { + uint32_t val; + struct emac_rx_addr_bm { + uint32_t b_ownership:1, /**< User clear, EMAC sets this to 1 once it has successfully written a frame to memory */ + b_wrap:1, /**< Marks last descriptor in receive buffer */ + addr_dw:30; /**< Address in number of DW */ + } bm; + } addr; /**< Address, Wrap & Ownership */ + union emac_rx_status { + uint32_t val; + struct emac_rx_status_bm { + uint32_t len:12, /** Length of frame including FCS */ + offset:2, /** Receive buffer offset, bits 13:12 of frame length for jumbo frame */ + b_sof:1, /** Start of frame */ + b_eof:1, /** End of frame */ + b_cfi:1, /** Concatenation Format Indicator */ + vlan_priority:3, /** VLAN priority (if VLAN detected) */ + b_priority_detected:1, /** Priority tag detected */ + b_vlan_detected:1, /**< VLAN tag detected */ + b_type_id_match:1, /**< Type ID match */ + b_addr4match:1, /**< Address register 4 match */ + b_addr3match:1, /**< Address register 3 match */ + b_addr2match:1, /**< Address register 2 match */ + b_addr1match:1, /**< Address register 1 match */ + reserved:1, + b_ext_addr_match:1, /**< External address match */ + b_uni_hash_match:1, /**< Unicast hash match */ + b_multi_hash_match:1, /**< Multicast hash match */ + b_boardcast_detect:1; /**< Global broadcast address detected */ + } bm; + } status; +} emac_rx_descriptor_t; + +/** Transmit buffer descriptor struct */ +COMPILER_PACK_SET(8) +typedef struct emac_tx_descriptor { + uint32_t addr; + union emac_tx_status { + uint32_t val; + struct emac_tx_status_bm { + uint32_t len:11, /**< Length of buffer */ + reserved:4, + b_last_buffer:1, /**< Last buffer (in the current frame) */ + b_no_crc:1, /**< No CRC */ + reserved1:10, + b_exhausted:1, /**< Buffer exhausted in mid frame */ + b_underrun:1, /**< Transmit underrun */ + b_error:1, /**< Retry limit exceeded, error detected */ + b_wrap:1, /**< Marks last descriptor in TD list */ + b_used:1; /**< User clear, EMAC sets this to 1 once a frame has been successfully transmitted */ + } bm; + } status; +} emac_tx_descriptor_t; + +COMPILER_PACK_RESET() + +/** + * \brief Input parameters when initializing the emac module mode. + */ +typedef struct emac_options { + /* Enable/Disable CopyAllFrame */ + uint8_t uc_copy_all_frame; + /* Enable/Disable NoBroadCast */ + uint8_t uc_no_boardcast; + /* MAC address */ + uint8_t uc_mac_addr[EMAC_ADDR_LENGTH]; +} emac_options_t; + +/** RX callback */ +typedef void (*emac_dev_tx_cb_t) (uint32_t ul_status); +/** Wakeup callback */ +typedef void (*emac_dev_wakeup_cb_t) (void); + +/** + * EMAC driver structure. + */ +typedef struct emac_device { + + /** Pointer to HW register base */ + Emac *p_hw; + /** + * Pointer to allocated TX buffer. + * Section 3.6 of AMBA 2.0 spec states that burst should not cross + * 1K Boundaries. + * Receive buffer manager writes are burst of 2 words => 3 lsb bits + * of the address shall be set to 0. + */ + uint8_t *p_tx_buffer; + /** Pointer to allocated RX buffer */ + uint8_t *p_rx_buffer; + /** Pointer to Rx TDs (must be 8-byte aligned) */ + emac_rx_descriptor_t *p_rx_dscr; + /** Pointer to Tx TDs (must be 8-byte aligned) */ + emac_tx_descriptor_t *p_tx_dscr; + /** Optional callback to be invoked once a frame has been received */ + emac_dev_tx_cb_t func_rx_cb; + /** Optional callback to be invoked once several TDs have been released */ + emac_dev_wakeup_cb_t func_wakeup_cb; + /** Optional callback list to be invoked once TD has been processed */ + emac_dev_tx_cb_t *func_tx_cb_list; + /** RX TD list size */ + uint16_t us_rx_list_size; + /** RX index for current processing TD */ + uint16_t us_rx_idx; + /** TX TD list size */ + uint16_t us_tx_list_size; + /** Circular buffer head pointer by upper layer (buffer to be sent) */ + uint16_t us_tx_head; + /** Circular buffer tail pointer incremented by handlers (buffer sent) */ + uint16_t us_tx_tail; + + /** Number of free TD before wakeup callback is invoked */ + uint8_t uc_wakeup_threshold; +} emac_device_t; + +/** + * \brief Write network control value. + * + * \param p_emac Pointer to the EMAC instance. + * \param ul_ncr Network control value. + */ +static inline void emac_network_control(Emac* p_emac, uint32_t ul_ncr) +{ + p_emac->EMAC_NCR = ul_ncr; +} + +/** + * \brief Get network control value. + * + * \param p_emac Pointer to the EMAC instance. + */ + +static inline uint32_t emac_get_network_control(Emac* p_emac) +{ + return p_emac->EMAC_NCR; +} + +/** + * \brief Enable/Disable EMAC receive. + * + * \param p_emac Pointer to the EMAC instance. + * \param uc_enable 0 to disable EMAC receiver, else to enable it. + */ +static inline void emac_enable_receive(Emac* p_emac, uint8_t uc_enable) +{ + if (uc_enable) { + p_emac->EMAC_NCR |= EMAC_NCR_RE; + } else { + p_emac->EMAC_NCR &= ~EMAC_NCR_RE; + } +} + +/** + * \brief Enable/Disable EMAC transmit. + * + * \param p_emac Pointer to the EMAC instance. + * \param uc_enable 0 to disable EMAC transmit, else to enable it. + */ +static inline void emac_enable_transmit(Emac* p_emac, uint8_t uc_enable) +{ + if (uc_enable) { + p_emac->EMAC_NCR |= EMAC_NCR_TE; + } else { + p_emac->EMAC_NCR &= ~EMAC_NCR_TE; + } +} + +/** + * \brief Enable/Disable EMAC management. + * + * \param p_emac Pointer to the EMAC instance. + * \param uc_enable 0 to disable EMAC management, else to enable it. + */ +static inline void emac_enable_management(Emac* p_emac, uint8_t uc_enable) +{ + if (uc_enable) { + p_emac->EMAC_NCR |= EMAC_NCR_MPE; + } else { + p_emac->EMAC_NCR &= ~EMAC_NCR_MPE; + } +} + +/** + * \brief Clear all statistics registers. + * + * \param p_emac Pointer to the EMAC instance. + */ +static inline void emac_clear_statistics(Emac* p_emac) +{ + p_emac->EMAC_NCR |= EMAC_NCR_CLRSTAT; +} + +/** + * \brief Increase all statistics registers. + * + * \param p_emac Pointer to the EMAC instance. + */ +static inline void emac_increase_statistics(Emac* p_emac) +{ + p_emac->EMAC_NCR |= EMAC_NCR_INCSTAT; +} + +/** + * \brief Enable/Disable statistics registers writing. + * + * \param p_emac Pointer to the EMAC instance. + * \param uc_enable 0 to disable the statistics registers writing, else to enable it. + */ +static inline void emac_enable_statistics_write(Emac* p_emac, + uint8_t uc_enable) +{ + if (uc_enable) { + p_emac->EMAC_NCR |= EMAC_NCR_WESTAT; + } else { + p_emac->EMAC_NCR &= ~EMAC_NCR_WESTAT; + } +} + +/** + * \brief In half-duplex mode, forces collisions on all received frames. + * + * \param p_emac Pointer to the EMAC instance. + * \param uc_enable 0 to disable the back pressure, else to enable it. + */ +static inline void emac_enable_back_pressure(Emac* p_emac, uint8_t uc_enable) +{ + if (uc_enable) { + p_emac->EMAC_NCR |= EMAC_NCR_BP; + } else { + p_emac->EMAC_NCR &= ~EMAC_NCR_BP; + } +} + +/** + * \brief Start transmission. + * + * \param p_emac Pointer to the EMAC instance. + */ +static inline void emac_start_transmission(Emac* p_emac) +{ + p_emac->EMAC_NCR |= EMAC_NCR_TSTART; +} + +/** + * \brief Halt transmission. + * + * \param p_emac Pointer to the EMAC instance. + */ +static inline void emac_halt_transmission(Emac* p_emac) +{ + p_emac->EMAC_NCR |= EMAC_NCR_THALT; +} + +/** + * \brief Set up network configuration register. + * + * \param p_emac Pointer to the EMAC instance. + * \param ul_cfg Network configuration value. + */ +static inline void emac_set_configure(Emac* p_emac, uint32_t ul_cfg) +{ + p_emac->EMAC_NCFGR = ul_cfg; +} + +/** + * \brief Get network configuration. + * + * \param p_emac Pointer to the EMAC instance. + * + * \return Network configuration. + */ +static inline uint32_t emac_get_configure(Emac* p_emac) +{ + return p_emac->EMAC_NCFGR; +} + +/** + * \brief Set speed. + * + * \param p_emac Pointer to the EMAC instance. + * \param uc_speed 1 to indicate 100Mbps, 0 to 10Mbps. + */ +static inline void emac_set_speed(Emac* p_emac, uint8_t uc_speed) +{ + if (uc_speed) { + p_emac->EMAC_NCFGR |= EMAC_NCFGR_SPD; + } else { + p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_SPD; + } +} + +/** + * \brief Enable/Disable Full-Duplex mode. + * + * \param p_emac Pointer to the EMAC instance. + * \param uc_enable 0 to disable the Full-Duplex mode, else to enable it. + */ +static inline void emac_enable_full_duplex(Emac* p_emac, uint8_t uc_enable) +{ + if (uc_enable) { + p_emac->EMAC_NCFGR |= EMAC_NCFGR_FD; + } else { + p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_FD; + } +} + +/** + * \brief Enable/Disable Copy(Receive) All Valid Frames. + * + * \param p_emac Pointer to the EMAC instance. + * \param uc_enable 0 to disable copying all valid frames, else to enable it. + */ +static inline void emac_enable_copy_all(Emac* p_emac, uint8_t uc_enable) +{ + if (uc_enable) { + p_emac->EMAC_NCFGR |= EMAC_NCFGR_CAF; + } else { + p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_CAF; + } +} + +/** + * \brief Enable/Disable jumbo frames (up to 10240 bytes). + * + * \param p_emac Pointer to the EMAC instance. + * \param uc_enable 0 to disable the jumbo frames, else to enable it. + */ +static inline void emac_enable_jumbo_frames(Emac* p_emac, uint8_t uc_enable) +{ + if (uc_enable) { + p_emac->EMAC_NCFGR |= EMAC_NCFGR_JFRAME; + } else { + p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_JFRAME; + } +} + +/** + * \brief Disable/Enable broadcast receiving. + * + * \param p_emac Pointer to the EMAC instance. + * \param uc_enable 1 to disable the broadcast, else to enable it. + */ +static inline void emac_disable_broadcast(Emac* p_emac, uint8_t uc_enable) +{ + if (uc_enable) { + p_emac->EMAC_NCFGR |= EMAC_NCFGR_NBC; + } else { + p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_NBC; + } +} + +/** + * \brief Enable/Disable multicast hash. + * + * \param p_emac Pointer to the EMAC instance. + * \param uc_enable 0 to disable the multicast hash, else to enable it. + */ +static inline void emac_enable_multicast_hash(Emac* p_emac, uint8_t uc_enable) +{ + if (uc_enable) { + p_emac->EMAC_NCFGR |= EMAC_NCFGR_UNI; + } else { + p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_UNI; + } +} + +/** + * \brief Enable/Disable big frames (over 1518, up to 1536). + * + * \param p_emac Pointer to the EMAC instance. + * \param uc_enable 0 to disable big frames else to enable it. + */ +static inline void emac_enable_big_frame(Emac* p_emac, uint8_t uc_enable) +{ + if (uc_enable) { + p_emac->EMAC_NCFGR |= EMAC_NCFGR_BIG; + } else { + p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_BIG; + } +} + +/** + * \brief Set MDC clock divider. + * + * \param p_emac Pointer to the EMAC instance. + * \param ul_mck EMAC MCK. + * + * \return EMAC_OK if successfully. + */ +static inline uint8_t emac_set_clock(Emac* p_emac, uint32_t ul_mck) +{ + uint32_t ul_clk; + + if (ul_mck > EMAC_CLOCK_SPEED_160MHZ) { + return EMAC_INVALID; + } else if (ul_mck > EMAC_CLOCK_SPEED_80MHZ) { + ul_clk = EMAC_NCFGR_CLK_MCK_64; + } else if (ul_mck > EMAC_CLOCK_SPEED_40MHZ) { + ul_clk = EMAC_NCFGR_CLK_MCK_32; + } else if (ul_mck > EMAC_CLOCK_SPEED_20MHZ) { + ul_clk = EMAC_NCFGR_CLK_MCK_16; + } else { + ul_clk = EMAC_NCFGR_CLK_MCK_8; + } + + p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_CLK_Msk; + p_emac->EMAC_NCFGR |= ul_clk; + + return EMAC_OK; +} + +/** + * \brief Enable/Disable retry test. + * + * \param p_emac Pointer to the EMAC instance. + * \param uc_enable 0 to disable the EMAC receiver, else to enable it. + */ +static inline void emac_enable_retry_test(Emac* p_emac, uint8_t uc_enable) +{ + if (uc_enable) { + p_emac->EMAC_NCFGR |= EMAC_NCFGR_RTY; + } else { + p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_RTY; + } +} + +/** + * \brief Enable/Disable pause (when a valid pause frame is received). + * + * \param p_emac Pointer to the EMAC instance. + * \param uc_enable 0 to disable pause frame, else to enable it. + */ +static inline void emac_enable_pause_frame(Emac* p_emac, uint8_t uc_enable) +{ + if (uc_enable) { + p_emac->EMAC_NCFGR |= EMAC_NCFGR_PAE; + } else { + p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_PAE; + } +} + +/** + * \brief Set receive buffer offset to 0 ~ 3. + * + * \param p_emac Pointer to the EMAC instance. + */ +static inline void emac_set_rx_buffer_offset(Emac* p_emac, uint8_t uc_offset) +{ + p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_RBOF_Msk; + p_emac->EMAC_NCFGR |= + (EMAC_NCFGR_RBOF_Msk & ((uc_offset) << EMAC_NCFGR_RBOF_Pos)); +} + +/** + * \brief Enable/Disable receive length field checking. + * + * \param p_emac Pointer to the EMAC instance. + * \param uc_enable 0 to disable receive length field checking, else to enable it. + */ +static inline void emac_enable_rx_length_check(Emac* p_emac, uint8_t uc_enable) +{ + if (uc_enable) { + p_emac->EMAC_NCFGR |= EMAC_NCFGR_RLCE; + } else { + p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_RLCE; + } +} + +/** + * \brief Enable/Disable discarding FCS field of received frames. + * + * \param p_emac Pointer to the EMAC instance. + * \param uc_enable 0 to disable discarding FCS field of received frames, else to enable it. + */ +static inline void emac_enable_discard_fcs(Emac* p_emac, uint8_t uc_enable) +{ + if (uc_enable) { + p_emac->EMAC_NCFGR |= EMAC_NCFGR_DRFCS; + } else { + p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_DRFCS; + } +} + + +/** + * \brief Enable/Disable frames to be received in half-duplex mode + * while transmitting. + * + * \param p_emac Pointer to the EMAC instance. + * \param uc_enable 0 to disable the received in half-duplex mode, else to enable it. + */ +static inline void emac_enable_efrhd(Emac* p_emac, uint8_t uc_enable) +{ + if (uc_enable) { + p_emac->EMAC_NCFGR |= EMAC_NCFGR_EFRHD; + } else { + p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_EFRHD; + } +} + +/** + * \brief Enable/Disable ignore RX FCS. + * + * \param p_emac Pointer to the EMAC instance. + * \param uc_enable 0 to disable ignore RX FCS, else to enable it. + */ +static inline void emac_enable_ignore_rx_fcs(Emac* p_emac, uint8_t uc_enable) +{ + if (uc_enable) { + p_emac->EMAC_NCFGR |= EMAC_NCFGR_IRXFCS; + } else { + p_emac->EMAC_NCFGR &= ~EMAC_NCFGR_IRXFCS; + } +} + +/** + * \brief Get Network Status. + * + * \param p_emac Pointer to the EMAC instance. + * + * \return Network status. + */ +static inline uint32_t emac_get_status(Emac* p_emac) +{ + return p_emac->EMAC_NSR; +} + +/** + * \brief Get MDIO IN pin status. + * + * \param p_emac Pointer to the EMAC instance. + * + * \return MDIO IN pin status. + */ +static inline uint8_t emac_get_MDIO(Emac* p_emac) +{ + return ((p_emac->EMAC_NSR & EMAC_NSR_MDIO) > 0); +} + +/** + * \brief Check if PHY is idle. + * + * \param p_emac Pointer to the EMAC instance. + * + * \return 1 if PHY is idle. + */ +static inline uint8_t emac_is_phy_idle(Emac* p_emac) +{ + return ((p_emac->EMAC_NSR & EMAC_NSR_IDLE) > 0); +} + +/** + * \brief Return transmit status. + * + * \param p_emac Pointer to the EMAC instance. + * + * \return Transmit status. + */ +static inline uint32_t emac_get_tx_status(Emac* p_emac) +{ + return p_emac->EMAC_TSR; +} + +/** + * \brief Clear transmit status. + * + * \param p_emac Pointer to the EMAC instance. + * \param ul_status Transmit status. + */ +static inline void emac_clear_tx_status(Emac* p_emac, uint32_t ul_status) +{ + p_emac->EMAC_TSR = ul_status; +} + +/** + * \brief Return receive status. + * + * \param p_emac Pointer to the EMAC instance. + */ +static inline uint32_t emac_get_rx_status(Emac* p_emac) +{ + return p_emac->EMAC_RSR; +} + +/** + * \brief Clear receive status. + * + * \param p_emac Pointer to the EMAC instance. + * \param ul_status Receive status. + */ +static inline void emac_clear_rx_status(Emac* p_emac, uint32_t ul_status) +{ + p_emac->EMAC_RSR = ul_status; +} + +/** + * \brief Set Rx Queue. + * + * \param p_emac Pointer to the EMAC instance. + * \param ul_addr Rx queue address. + */ +static inline void emac_set_rx_queue(Emac* p_emac, uint32_t ul_addr) +{ + p_emac->EMAC_RBQP = EMAC_RBQP_ADDR_Msk & ul_addr; +} + +/** + * \brief Get Rx Queue Address. + * + * \param p_emac Pointer to the EMAC instance. + * + * \return Rx queue address. + */ +static inline uint32_t emac_get_rx_queue(Emac* p_emac) +{ + return p_emac->EMAC_RBQP; +} + +/** + * \brief Set Tx Queue. + * + * \param p_emac Pointer to the EMAC instance. + * \param ul_addr Tx queue address. + */ +static inline void emac_set_tx_queue(Emac* p_emac, uint32_t ul_addr) +{ + p_emac->EMAC_TBQP = EMAC_TBQP_ADDR_Msk & ul_addr; +} + +/** + * \brief Get Tx Queue. + * + * \param p_emac Pointer to the EMAC instance. + * + * \return Rx queue address. + */ +static inline uint32_t emac_get_tx_queue(Emac* p_emac) +{ + return p_emac->EMAC_TBQP; +} + +/** + * \brief Enable interrupt(s). + * + * \param p_emac Pointer to the EMAC instance. + * \param ul_source Interrupt source(s) to be enabled. + */ +static inline void emac_enable_interrupt(Emac* p_emac, uint32_t ul_source) +{ + p_emac->EMAC_IER = ul_source; +} + +/** + * \brief Disable interrupt(s). + * + * \param p_emac Pointer to the EMAC instance. + * \param ul_source Interrupt source(s) to be disabled. + */ +static inline void emac_disable_interrupt(Emac* p_emac, uint32_t ul_source) +{ + p_emac->EMAC_IDR = ul_source; +} + +/** + * \brief Return interrupt status. + * + * \param p_emac Pointer to the EMAC instance. + * + * \return Interrupt status. + */ +static inline uint32_t emac_get_interrupt_status(Emac* p_emac) +{ + return p_emac->EMAC_ISR; +} + +/** + * \brief Return interrupt mask. + * + * \param p_emac Pointer to the EMAC instance. + * + * \return Interrupt mask. + */ +static inline uint32_t emac_get_interrupt_mask(Emac* p_emac) +{ + return p_emac->EMAC_IMR; +} + +/** + * \brief Execute PHY maintenance command. + * + * \param p_emac Pointer to the EMAC instance. + * \param uc_phy_addr PHY address. + * \param uc_reg_addr Register address. + * \param uc_rw 1 to Read, 0 to write. + * \param us_data Data to be performed, write only. + */ +static inline void emac_maintain_phy(Emac* p_emac, + uint8_t uc_phy_addr, uint8_t uc_reg_addr, uint8_t uc_rw, + uint16_t us_data) +{ + /* Wait until bus idle */ + while ((p_emac->EMAC_NSR & EMAC_NSR_IDLE) == 0); + /* Write maintain register */ + p_emac->EMAC_MAN = EMAC_MAN_CODE(EMAC_MAN_CODE_VALUE) + | EMAC_MAN_SOF(EMAC_MAN_SOF_VALUE) + | EMAC_MAN_PHYA(uc_phy_addr) + | EMAC_MAN_REGA(uc_reg_addr) + | EMAC_MAN_RW((uc_rw ? EMAC_MAN_RW_TYPE : EMAC_MAN_READ_ONLY)) + | EMAC_MAN_DATA(us_data); +} + +/** + * \brief Get PHY maintenance data returned. + * + * \param p_emac Pointer to the EMAC instance. + * + * \return Get PHY data. + */ +static inline uint16_t emac_get_phy_data(Emac* p_emac) +{ + /* Wait until bus idle */ + while ((p_emac->EMAC_NSR & EMAC_NSR_IDLE) == 0); + /* Return data */ + return (uint16_t) (p_emac->EMAC_MAN & EMAC_MAN_DATA_Msk); +} + +/** + * \brief Set pause time. + * + * \param p_emac Pointer to the EMAC instance. + * \param us_pause_time Pause time. + */ +static inline void emac_set_pause_time(Emac* p_emac, uint16_t us_pause_time) +{ + p_emac->EMAC_PTR = us_pause_time; +} + +/** + * \brief Set Hash. + * + * \param p_emac Pointer to the EMAC instance. + * \param ul_hash_top Hash top. + * \param ul_hash_bottom Hash bottom. + */ +static inline void emac_set_hash(Emac* p_emac, uint32_t ul_hash_top, + uint32_t ul_hash_bottom) +{ + p_emac->EMAC_HRB = ul_hash_bottom; + p_emac->EMAC_HRT = ul_hash_top; +} + +/** + * \brief Set 64 bits Hash. + * + * \param p_emac Pointer to the EMAC instance. + * \param ull_hash 64 bits hash value. + */ +static inline void emac_set_hash64(Emac* p_emac, uint64_t ull_hash) +{ + p_emac->EMAC_HRB = (uint32_t) ull_hash; + p_emac->EMAC_HRT = (uint32_t) (ull_hash >> 32); +} + +/** + * \brief Set MAC Address. + * + * \param p_emac Pointer to the EMAC instance. + * \param uc_index EMAC specific address register index. + * \param p_mac_addr EMAC address. + */ +static inline void emac_set_address(Emac* p_emac, uint8_t uc_index, + uint8_t* p_mac_addr) +{ + p_emac->EMAC_SA[uc_index].EMAC_SAxB = (p_mac_addr[3] << 24) + | (p_mac_addr[2] << 16) + | (p_mac_addr[1] << 8) + | (p_mac_addr[0]); + p_emac->EMAC_SA[uc_index].EMAC_SAxT = (p_mac_addr[5] << 8) + | (p_mac_addr[4]); +} + +/** + * \brief Set MAC Address via 2 dword. + * + * \param p_emac Pointer to the EMAC instance. + * \param uc_index EMAC specific address register index. + * \param ul_mac_top EMAC top address. + * \param ul_mac_bottom EMAC bottom address. + */ +static inline void emac_set_address32(Emac* p_emac, uint8_t uc_index, + uint32_t ul_mac_top, uint32_t ul_mac_bottom) +{ + p_emac->EMAC_SA[uc_index].EMAC_SAxB = ul_mac_bottom; + p_emac->EMAC_SA[uc_index].EMAC_SAxT = ul_mac_top; +} + +/** + * \brief Set MAC Address via int64. + * + * \param p_emac Pointer to the EMAC instance. + * \param uc_index EMAC specific address register index. + * \param ull_mac 64-bit EMAC address. + */ +static inline void emac_set_address64(Emac* p_emac, uint8_t uc_index, + uint64_t ull_mac) +{ + p_emac->EMAC_SA[uc_index].EMAC_SAxB = (uint32_t) ull_mac; + p_emac->EMAC_SA[uc_index].EMAC_SAxT = (uint32_t) (ull_mac >> 32); +} + +/** + * \brief Set type ID. + * + * \param p_emac Pointer to the EMAC instance. + * \param us_type_id Type to be set. + */ +static inline void emac_set_type_id(Emac* p_emac, uint16_t us_type_id) +{ + p_emac->EMAC_TID = EMAC_TID_TID(us_type_id); +} + +/** + * \brief Get type ID. + * + * \param p_emac Pointer to the EMAC instance. + * + * \return Type ID. + */ +static inline uint16_t emac_get_type_id(Emac* p_emac) +{ + return (p_emac->EMAC_TID & EMAC_TID_TID_Msk); +} + +/** + * \brief Enable/Disable RMII. + * + * \param p_emac Pointer to the EMAC instance. + * \param uc_enable 0 to disable the RMII mode, else to enable it. + */ +static inline void emac_enable_rmii(Emac* p_emac, uint8_t uc_enable) +{ + if (uc_enable) { + p_emac->EMAC_USRIO |= EMAC_USRIO_RMII; + } else { + p_emac->EMAC_USRIO &= ~EMAC_USRIO_RMII; + } +} + +/** + * \brief Enable/Disable transceiver input clock. + * + * \param p_emac Pointer to the EMAC instance. + * \param uc_enable 0 to disable transceiver input clock, else to enable it. + */ +static inline void emac_enable_transceiver_clock(Emac* p_emac, + uint8_t uc_enable) +{ + if (uc_enable) { + p_emac->EMAC_USRIO |= EMAC_USRIO_CLKEN; + } else { + p_emac->EMAC_USRIO &= ~EMAC_USRIO_CLKEN; + } +} + +uint8_t emac_phy_read(Emac* p_emac, uint8_t uc_phy_address, uint8_t uc_address, + uint32_t* p_value); +uint8_t emac_phy_write(Emac* p_emac, uint8_t uc_phy_address, + uint8_t uc_address, uint32_t ul_value); +void emac_dev_init(Emac* p_emac, emac_device_t* p_emac_dev, + emac_options_t* p_opt); +uint32_t emac_dev_read(emac_device_t* p_emac_dev, uint8_t* p_frame, + uint32_t ul_frame_size, uint32_t* p_rcv_size); +uint32_t emac_dev_write(emac_device_t* p_emac_dev, void *p_buffer, + uint32_t ul_size, emac_dev_tx_cb_t func_tx_cb); +uint32_t emac_dev_get_tx_load(emac_device_t* p_emac_dev); +void emac_dev_set_rx_callback(emac_device_t* p_emac_dev, + emac_dev_tx_cb_t func_rx_cb); +uint8_t emac_dev_set_tx_wakeup_callback(emac_device_t* p_emac_dev, + emac_dev_wakeup_cb_t func_wakeup, uint8_t uc_threshold); +void emac_dev_reset(emac_device_t* p_emac_dev); +void emac_handler(emac_device_t* p_emac_dev); + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \page emac_quickstart Quickstart guide for EMAC driver. + * + * This is the quickstart guide for the \ref emac_group "Ethernet MAC", + * with step-by-step instructions on how to configure and use the driver in a + * selection of use cases. + * + * The use cases contain several code fragments. The code fragments in the + * steps for setup can be copied into a custom initialization function, while + * the steps for usage can be copied into, e.g., the main application function. + * + * \section emac_basic_use_case Basic use case + * In the basic use case, the EMAC driver are configured for: + * - PHY component DM9161A is used + * - EMAC uses RMII mode + * - The number of receive buffer is 16 + * - The number of transfer buffer is 8 + * - MAC address is set to 00-04-25-1c-a0-02 + * - IP address is set to 192.168.0.2 + * - IP address is set to 192.168.0.2 + * - Gateway is set to 192.168.0.1 + * - Network mask is 255.255.255.0 + * - PHY operation max retry count is 1000000 + * - EMAC is configured to not support copy all frame and support broadcast + * - The reset PIN of DM9161A is connected to the NRST of SAM3X + * - The data will be read from the ethernet + * + * \section emac_basic_use_case_setup Setup steps + * + * \subsection emac_basic_use_case_setup_prereq Prerequisites + * -# \ref sysclk_group "System Clock Management (sysclock)" + * -# \ref pio_group "Parallel Input/Output Controller (pio)" + * -# \ref pmc_group "Power Management Controller (pmc)" + * -# \ref sam_drivers_rstc_group "Reset Controller (RSTC)" + * -# \ref dm9161a_ethernet_phy_group "PHY component (DM9161A)" + * + * \subsection emac_basic_use_case_setup_code Example code + * Content of conf_eth.h + * \code + #define EMAC_RX_BUFFERS 16 + #define EMAC_TX_BUFFERS 8 + #define MAC_PHY_RETRY_MAX 1000000 + #define ETHERNET_CONF_ETHADDR0 0x00 + #define ETHERNET_CONF_ETHADDR0 0x00 + #define ETHERNET_CONF_ETHADDR1 0x04 + #define ETHERNET_CONF_ETHADDR2 0x25 + #define ETHERNET_CONF_ETHADDR3 0x1C + #define ETHERNET_CONF_ETHADDR4 0xA0 + #define ETHERNET_CONF_ETHADDR5 0x02 + #define ETHERNET_CONF_IPADDR0 192 + #define ETHERNET_CONF_IPADDR1 168 + #define ETHERNET_CONF_IPADDR2 0 + #define ETHERNET_CONF_IPADDR3 2 + #define ETHERNET_CONF_GATEWAY_ADDR0 192 + #define ETHERNET_CONF_GATEWAY_ADDR1 168 + #define ETHERNET_CONF_GATEWAY_ADDR2 0 + #define ETHERNET_CONF_GATEWAY_ADDR3 1 + #define ETHERNET_CONF_NET_MASK0 255 + #define ETHERNET_CONF_NET_MASK1 255 + #define ETHERNET_CONF_NET_MASK2 255 + #define ETHERNET_CONF_NET_MASK3 0 + #define ETH_PHY_MODE BOARD_EMAC_MODE_RMII +\endcode + * + * A specific EMAC device and the receive data buffer must be defined; another ul_frm_size should be defined + * to trace the actual size of the data received. + * \code + static emac_device_t gs_emac_dev; + static volatile uint8_t gs_uc_eth_buffer[EMAC_FRAME_LENTGH_MAX]; + + uint32_t ul_frm_size; +\endcode + * + * Add to application C-file: + * \code + void emac_init(void) + { + sysclk_init(); + + board_init(); + + rstc_set_external_reset(RSTC, 13); + rstc_reset_extern(RSTC); + while (rstc_get_status(RSTC) & RSTC_SR_NRSTL) { + }; + + ul_delay = sysclk_get_cpu_hz() / 1000 / 3 * 400; + while (ul_delay--); + + pmc_enable_periph_clk(ID_EMAC); + + emac_option.uc_copy_all_frame = 0; + emac_option.uc_no_boardcast = 0; + memcpy(emac_option.uc_mac_addr, gs_uc_mac_address, sizeof(gs_uc_mac_address)); + gs_emac_dev.p_hw = EMAC; + + emac_dev_init(EMAC, &gs_emac_dev, &emac_option); + + NVIC_EnableIRQ(EMAC_IRQn); + + ethernet_phy_init(EMAC, BOARD_EMAC_PHY_ADDR, sysclk_get_cpu_hz() + + ethernet_phy_auto_negotiate(EMAC, BOARD_EMAC_PHY_ADDR + + ethernet_phy_set_link(EMAC, BOARD_EMAC_PHY_ADDR, 1) +\endcode + * + * \subsection emac_basic_use_case_setup_flow Workflow + * - Ensure that conf_eth.h is present and contains the + * following configuration symbol. This configuration file is used + * by the driver and should not be included by the application. + * -# Define the receiving buffer size used in the internal EMAC driver. + * The buffer size used for RX is EMAC_RX_BUFFERS * 128. + * If it was supposed receiving a large number of frame, the + * EMAC_RX_BUFFERS should be set higher. E.g., the application wants to accept + * a ping echo test of 2048, the EMAC_RX_BUFFERS should be set at least + * (2048/128)=16, but as there are additional frames coming, a preferred + * number is 24 depending on a normal Ethernet throughput. + * - \code + #define EMAC_RX_BUFFERS 16 +\endcode + * -# Define the transmitting buffer size used in the internal EMAC driver. + * The buffer size used for TX is EMAC_TX_BUFFERS * 1518. + * - \code + #define EMAC_TX_BUFFERS 8 +\endcode + * -# Define maximum retry time for a PHY read/write operation. + * - \code + #define MAC_PHY_RETRY_MAX 1000000 +\endcode + * -# Define the MAC address. 00:04:25:1C:A0:02 is the address reserved + * for ATMEL, application should always change this address to its' own. + * - \code + #define ETHERNET_CONF_ETHADDR0 0x00 + #define ETHERNET_CONF_ETHADDR1 0x04 + #define ETHERNET_CONF_ETHADDR2 0x25 + #define ETHERNET_CONF_ETHADDR3 0x1C + #define ETHERNET_CONF_ETHADDR4 0xA0 + #define ETHERNET_CONF_ETHADDR5 0x02 +\endcode + * -# Define the IP address configration used in the application. When DHCP + * is enabled, this configuration is not effected. + * - \code + #define ETHERNET_CONF_IPADDR0 192 + #define ETHERNET_CONF_IPADDR1 168 + #define ETHERNET_CONF_IPADDR2 0 + #define ETHERNET_CONF_IPADDR3 2 + #define ETHERNET_CONF_GATEWAY_ADDR0 192 + #define ETHERNET_CONF_GATEWAY_ADDR1 168 + #define ETHERNET_CONF_GATEWAY_ADDR2 0 + #define ETHERNET_CONF_GATEWAY_ADDR3 1 + #define ETHERNET_CONF_NET_MASK0 255 + #define ETHERNET_CONF_NET_MASK1 255 + #define ETHERNET_CONF_NET_MASK2 255 + #define ETHERNET_CONF_NET_MASK3 0 +\endcode + * -# Configure the PHY maintainance interface. + * - \code + #define ETH_PHY_MODE BOARD_EMAC_MODE_RMII +\endcode + + * -# Enable the system clock: + * - \code sysclk_init(); \endcode + * -# Enable PIO configurations for EMAC: + * - \code board_init(); \endcode + * -# Reset PHY; this is required by the DM9161A component: + * - \code + rstc_set_external_reset(RSTC, 13); + rstc_reset_extern(RSTC); + while (rstc_get_status(RSTC) & RSTC_SR_NRSTL) { + }; +\endcode + * -# Wait for PHY ready: + * - \code + ul_delay = sysclk_get_cpu_hz() / 1000 / 3 * 400; + while (ul_delay--); +\endcode + * -# Enable PMC clock for EMAC: + * - \code pmc_enable_periph_clk(ID_EMAC); \endcode + * -# Set the EMAC options; it's set to copy all frame and support broadcast: + * - \code + emac_option.uc_copy_all_frame = 0; + emac_option.uc_no_boardcast = 0; + memcpy(emac_option.uc_mac_addr, gs_uc_mac_address, sizeof(gs_uc_mac_address)); + gs_emac_dev.p_hw = EMAC; +\endcode + * -# Initialize EMAC device with the filled option: + * - \code + emac_dev_init(EMAC, &gs_emac_dev, &emac_option); +\endcode + * -# Enable the interrupt service for EMAC: + * - \code + NVIC_EnableIRQ(EMAC_IRQn); +\endcode + * -# Initialize the PHY component: + * - \code + ethernet_phy_init(EMAC, BOARD_EMAC_PHY_ADDR, sysclk_get_cpu_hz()); +\endcode + * -# The link will be established based on auto negotiation. + * - \code + ethernet_phy_auto_negotiate(EMAC, BOARD_EMAC_PHY_ADDR); +\endcode + * -# Establish the ethernet link; the network can be worked from now on: + * - \code + ethernet_phy_set_link(EMAC, BOARD_EMAC_PHY_ADDR, 1); +\endcode + * + * \section emac_basic_use_case_usage Usage steps + * \subsection emac_basic_use_case_usage_code Example code + * Add to, e.g., main loop in application C-file: + * \code + emac_dev_read(&gs_emac_dev, (uint8_t *) gs_uc_eth_buffer, sizeof(gs_uc_eth_buffer), &ul_frm_size)); +\endcode + * + * \subsection emac_basic_use_case_usage_flow Workflow + * -# Start reading the data from the ethernet: + * - \code emac_dev_read(&gs_emac_dev, (uint8_t *) gs_uc_eth_buffer, sizeof(gs_uc_eth_buffer), &ul_frm_size)); \endcode + */ + +#endif /* EMAC_H_INCLUDED */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/pio/pio.c b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/pio/pio.c new file mode 100644 index 0000000..c3c7773 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/pio/pio.c @@ -0,0 +1,1470 @@ +/** + * \file + * + * \brief Parallel Input/Output (PIO) Controller driver for SAM. + * + * Copyright (c) 2011-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#include "pio.h" + +#ifndef PIO_WPMR_WPKEY_PASSWD +# define PIO_WPMR_WPKEY_PASSWD PIO_WPMR_WPKEY(0x50494Fu) +#endif + +/** + * \defgroup sam_drivers_pio_group Peripheral Parallel Input/Output (PIO) Controller + * + * \par Purpose + * + * The Parallel Input/Output Controller (PIO) manages up to 32 fully + * programmable input/output lines. Each I/O line may be dedicated as a + * general-purpose I/O or be assigned to a function of an embedded peripheral. + * This assures effective optimization of the pins of a product. + * + * @{ + */ + +#ifndef FREQ_SLOW_CLOCK_EXT +/* External slow clock frequency (hz) */ +#define FREQ_SLOW_CLOCK_EXT 32768 +#endif + +/** + * \brief Configure PIO internal pull-up. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + * \param ul_pull_up_enable Indicates if the pin(s) internal pull-up shall be + * configured. + */ +void pio_pull_up(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_pull_up_enable) +{ + /* Enable the pull-up(s) if necessary */ + if (ul_pull_up_enable) { + p_pio->PIO_PUER = ul_mask; + } else { + p_pio->PIO_PUDR = ul_mask; + } +} + +/** + * \brief Configure Glitch or Debouncing filter for the specified input(s). + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + * \param ul_cut_off Cuts off frequency for debouncing filter. + */ +void pio_set_debounce_filter(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_cut_off) +{ +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) + /* Set Debouncing, 0 bit field no effect */ + p_pio->PIO_IFSCER = ul_mask; +#elif (SAM3XA || SAM3U) + /* Set Debouncing, 0 bit field no effect */ + p_pio->PIO_DIFSR = ul_mask; +#else +#error "Unsupported device" +#endif + + /* + * The debouncing filter can filter a pulse of less than 1/2 Period of a + * programmable Divided Slow Clock: + * Tdiv_slclk = ((DIV+1)*2).Tslow_clock + */ + p_pio->PIO_SCDR = PIO_SCDR_DIV((FREQ_SLOW_CLOCK_EXT / + (2 * (ul_cut_off))) - 1); +} + +/** + * \brief Set a high output level on all the PIOs defined in ul_mask. + * This has no immediate effects on PIOs that are not output, but the PIO + * controller will save the value if they are changed to outputs. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + */ +void pio_set(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_SODR = ul_mask; +} + +/** + * \brief Set a low output level on all the PIOs defined in ul_mask. + * This has no immediate effects on PIOs that are not output, but the PIO + * controller will save the value if they are changed to outputs. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + */ +void pio_clear(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_CODR = ul_mask; +} + +/** + * \brief Return 1 if one or more PIOs of the given Pin instance currently have + * a high level; otherwise returns 0. This method returns the actual value that + * is being read on the pin. To return the supposed output value of a pin, use + * pio_get_output_data_status() instead. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_type PIO type. + * \param ul_mask Bitmask of one or more pin(s) to configure. + * + * \retval 1 at least one PIO currently has a high level. + * \retval 0 all PIOs have a low level. + */ +uint32_t pio_get(Pio *p_pio, const pio_type_t ul_type, + const uint32_t ul_mask) +{ + uint32_t ul_reg; + + if ((ul_type == PIO_OUTPUT_0) || (ul_type == PIO_OUTPUT_1)) { + ul_reg = p_pio->PIO_ODSR; + } else { + ul_reg = p_pio->PIO_PDSR; + } + + if ((ul_reg & ul_mask) == 0) { + return 0; + } else { + return 1; + } +} + +/** + * \brief Configure IO of a PIO controller as being controlled by a specific + * peripheral. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_type PIO type. + * \param ul_mask Bitmask of one or more pin(s) to configure. + */ +void pio_set_peripheral(Pio *p_pio, const pio_type_t ul_type, + const uint32_t ul_mask) +{ + uint32_t ul_sr; + + /* Disable interrupts on the pin(s) */ + p_pio->PIO_IDR = ul_mask; + +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) + switch (ul_type) { + case PIO_PERIPH_A: + ul_sr = p_pio->PIO_ABCDSR[0]; + p_pio->PIO_ABCDSR[0] &= (~ul_mask & ul_sr); + + ul_sr = p_pio->PIO_ABCDSR[1]; + p_pio->PIO_ABCDSR[1] &= (~ul_mask & ul_sr); + break; + case PIO_PERIPH_B: + ul_sr = p_pio->PIO_ABCDSR[0]; + p_pio->PIO_ABCDSR[0] = (ul_mask | ul_sr); + + ul_sr = p_pio->PIO_ABCDSR[1]; + p_pio->PIO_ABCDSR[1] &= (~ul_mask & ul_sr); + break; +#if (!SAMG) + case PIO_PERIPH_C: + ul_sr = p_pio->PIO_ABCDSR[0]; + p_pio->PIO_ABCDSR[0] &= (~ul_mask & ul_sr); + + ul_sr = p_pio->PIO_ABCDSR[1]; + p_pio->PIO_ABCDSR[1] = (ul_mask | ul_sr); + break; + case PIO_PERIPH_D: + ul_sr = p_pio->PIO_ABCDSR[0]; + p_pio->PIO_ABCDSR[0] = (ul_mask | ul_sr); + + ul_sr = p_pio->PIO_ABCDSR[1]; + p_pio->PIO_ABCDSR[1] = (ul_mask | ul_sr); + break; +#endif + /* Other types are invalid in this function */ + case PIO_INPUT: + case PIO_OUTPUT_0: + case PIO_OUTPUT_1: + case PIO_NOT_A_PIN: + return; + } +#elif (SAM3XA|| SAM3U) + switch (ul_type) { + case PIO_PERIPH_A: + ul_sr = p_pio->PIO_ABSR; + p_pio->PIO_ABSR &= (~ul_mask & ul_sr); + break; + + case PIO_PERIPH_B: + ul_sr = p_pio->PIO_ABSR; + p_pio->PIO_ABSR = (ul_mask | ul_sr); + break; + + // other types are invalid in this function + case PIO_INPUT: + case PIO_OUTPUT_0: + case PIO_OUTPUT_1: + case PIO_NOT_A_PIN: + return; + } +#else +#error "Unsupported device" +#endif + + /* Remove the pins from under the control of PIO */ + p_pio->PIO_PDR = ul_mask; +} + +/** + * \brief Configure one or more pin(s) or a PIO controller as inputs. + * Optionally, the corresponding internal pull-up(s) and glitch filter(s) can + * be enabled. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask indicating which pin(s) to configure as input(s). + * \param ul_attribute PIO attribute(s). + */ +void pio_set_input(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_attribute) +{ + pio_disable_interrupt(p_pio, ul_mask); + pio_pull_up(p_pio, ul_mask, ul_attribute & PIO_PULLUP); + + /* Enable Input Filter if necessary */ + if (ul_attribute & (PIO_DEGLITCH | PIO_DEBOUNCE)) { + p_pio->PIO_IFER = ul_mask; + } else { + p_pio->PIO_IFDR = ul_mask; + } + +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) + /* Enable de-glitch or de-bounce if necessary */ + if (ul_attribute & PIO_DEGLITCH) { + p_pio->PIO_IFSCDR = ul_mask; + } else { + if (ul_attribute & PIO_DEBOUNCE) { + p_pio->PIO_IFSCER = ul_mask; + } + } +#elif (SAM3XA|| SAM3U) + /* Enable de-glitch or de-bounce if necessary */ + if (ul_attribute & PIO_DEGLITCH) { + p_pio->PIO_SCIFSR = ul_mask; + } else { + if (ul_attribute & PIO_DEBOUNCE) { + p_pio->PIO_DIFSR = ul_mask; + } + } +#else +#error "Unsupported device" +#endif + + /* Configure pin as input */ + p_pio->PIO_ODR = ul_mask; + p_pio->PIO_PER = ul_mask; +} + +/** + * \brief Configure one or more pin(s) of a PIO controller as outputs, with + * the given default value. Optionally, the multi-drive feature can be enabled + * on the pin(s). + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask indicating which pin(s) to configure. + * \param ul_default_level Default level on the pin(s). + * \param ul_multidrive_enable Indicates if the pin(s) shall be configured as + * open-drain. + * \param ul_pull_up_enable Indicates if the pin shall have its pull-up + * activated. + */ +void pio_set_output(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_default_level, + const uint32_t ul_multidrive_enable, + const uint32_t ul_pull_up_enable) +{ + pio_disable_interrupt(p_pio, ul_mask); + pio_pull_up(p_pio, ul_mask, ul_pull_up_enable); + + /* Enable multi-drive if necessary */ + if (ul_multidrive_enable) { + p_pio->PIO_MDER = ul_mask; + } else { + p_pio->PIO_MDDR = ul_mask; + } + + /* Set default value */ + if (ul_default_level) { + p_pio->PIO_SODR = ul_mask; + } else { + p_pio->PIO_CODR = ul_mask; + } + + /* Configure pin(s) as output(s) */ + p_pio->PIO_OER = ul_mask; + p_pio->PIO_PER = ul_mask; +} + +/** + * \brief Perform complete pin(s) configuration; general attributes and PIO init + * if necessary. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_type PIO type. + * \param ul_mask Bitmask of one or more pin(s) to configure. + * \param ul_attribute Pins attributes. + * + * \return Whether the pin(s) have been configured properly. + */ +uint32_t pio_configure(Pio *p_pio, const pio_type_t ul_type, + const uint32_t ul_mask, const uint32_t ul_attribute) +{ + /* Configure pins */ + switch (ul_type) { + case PIO_PERIPH_A: + case PIO_PERIPH_B: +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) + case PIO_PERIPH_C: + case PIO_PERIPH_D: +#endif + pio_set_peripheral(p_pio, ul_type, ul_mask); + pio_pull_up(p_pio, ul_mask, (ul_attribute & PIO_PULLUP)); + break; + + case PIO_INPUT: + pio_set_input(p_pio, ul_mask, ul_attribute); + break; + + case PIO_OUTPUT_0: + case PIO_OUTPUT_1: + pio_set_output(p_pio, ul_mask, (ul_type == PIO_OUTPUT_1), + (ul_attribute & PIO_OPENDRAIN) ? 1 : 0, + (ul_attribute & PIO_PULLUP) ? 1 : 0); + break; + + default: + return 0; + } + + return 1; +} + +/** + * \brief Return 1 if one or more PIOs of the given Pin are configured to + * output a high level (even if they are not output). + * To get the actual value of the pin, use PIO_Get() instead. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s). + * + * \retval 1 At least one PIO is configured to output a high level. + * \retval 0 All PIOs are configured to output a low level. + */ +uint32_t pio_get_output_data_status(const Pio *p_pio, + const uint32_t ul_mask) +{ + if ((p_pio->PIO_ODSR & ul_mask) == 0) { + return 0; + } else { + return 1; + } +} + +/** + * \brief Configure PIO pin multi-driver. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + * \param ul_multi_driver_enable Indicates if the pin(s) multi-driver shall be + * configured. + */ +void pio_set_multi_driver(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_multi_driver_enable) +{ + /* Enable the multi-driver if necessary */ + if (ul_multi_driver_enable) { + p_pio->PIO_MDER = ul_mask; + } else { + p_pio->PIO_MDDR = ul_mask; + } +} + +/** + * \brief Get multi-driver status. + * + * \param p_pio Pointer to a PIO instance. + * + * \return The multi-driver mask value. + */ +uint32_t pio_get_multi_driver_status(const Pio *p_pio) +{ + return p_pio->PIO_MDSR; +} + + +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Configure PIO pin internal pull-down. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + * \param ul_pull_down_enable Indicates if the pin(s) internal pull-down shall + * be configured. + */ +void pio_pull_down(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_pull_down_enable) +{ + /* Enable the pull-down if necessary */ + if (ul_pull_down_enable) { + p_pio->PIO_PPDER = ul_mask; + } else { + p_pio->PIO_PPDDR = ul_mask; + } +} +#endif + +/** + * \brief Enable PIO output write for synchronous data output. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + */ +void pio_enable_output_write(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_OWER = ul_mask; +} + +/** + * \brief Disable PIO output write. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + */ +void pio_disable_output_write(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_OWDR = ul_mask; +} + +/** + * \brief Read PIO output write status. + * + * \param p_pio Pointer to a PIO instance. + * + * \return The output write mask value. + */ +uint32_t pio_get_output_write_status(const Pio *p_pio) +{ + return p_pio->PIO_OWSR; +} + +/** + * \brief Synchronously write on output pins. + * \note Only bits unmasked by PIO_OWSR (Output Write Status Register) are + * written. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + */ +void pio_sync_output_write(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_ODSR = ul_mask; +} + +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Configure PIO pin schmitt trigger. By default the Schmitt trigger is + * active. + * Disabling the Schmitt Trigger is requested when using the QTouch Library. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + */ +void pio_set_schmitt_trigger(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_SCHMITT = ul_mask; +} + +/** + * \brief Get PIO pin schmitt trigger status. + * + * \param p_pio Pointer to a PIO instance. + * + * \return The schmitt trigger mask value. + */ +uint32_t pio_get_schmitt_trigger(const Pio *p_pio) +{ + return p_pio->PIO_SCHMITT; +} +#endif + +/** + * \brief Configure the given interrupt source. + * Interrupt can be configured to trigger on rising edge, falling edge, + * high level, low level or simply on level change. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Interrupt source bit map. + * \param ul_attr Interrupt source attributes. + */ +void pio_configure_interrupt(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_attr) +{ + /* Configure additional interrupt mode registers. */ + if (ul_attr & PIO_IT_AIME) { + /* Enable additional interrupt mode. */ + p_pio->PIO_AIMER = ul_mask; + + /* If bit field of the selected pin is 1, set as + Rising Edge/High level detection event. */ + if (ul_attr & PIO_IT_RE_OR_HL) { + /* Rising Edge or High Level */ + p_pio->PIO_REHLSR = ul_mask; + } else { + /* Falling Edge or Low Level */ + p_pio->PIO_FELLSR = ul_mask; + } + + /* If bit field of the selected pin is 1, set as + edge detection source. */ + if (ul_attr & PIO_IT_EDGE) { + /* Edge select */ + p_pio->PIO_ESR = ul_mask; + } else { + /* Level select */ + p_pio->PIO_LSR = ul_mask; + } + } else { + /* Disable additional interrupt mode. */ + p_pio->PIO_AIMDR = ul_mask; + } +} + +/** + * \brief Enable the given interrupt source. + * The PIO must be configured as an NVIC interrupt source as well. + * The status register of the corresponding PIO controller is cleared + * prior to enabling the interrupt. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Interrupt sources bit map. + */ +void pio_enable_interrupt(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_ISR; + p_pio->PIO_IER = ul_mask; +} + +/** + * \brief Disable a given interrupt source, with no added side effects. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Interrupt sources bit map. + */ +void pio_disable_interrupt(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_IDR = ul_mask; +} + +/** + * \brief Read PIO interrupt status. + * + * \param p_pio Pointer to a PIO instance. + * + * \return The interrupt status mask value. + */ +uint32_t pio_get_interrupt_status(const Pio *p_pio) +{ + return p_pio->PIO_ISR; +} + +/** + * \brief Read PIO interrupt mask. + * + * \param p_pio Pointer to a PIO instance. + * + * \return The interrupt mask value. + */ +uint32_t pio_get_interrupt_mask(const Pio *p_pio) +{ + return p_pio->PIO_IMR; +} + +/** + * \brief Set additional interrupt mode. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Interrupt sources bit map. + * \param ul_attribute Pin(s) attributes. + */ +void pio_set_additional_interrupt_mode(Pio *p_pio, + const uint32_t ul_mask, const uint32_t ul_attribute) +{ + /* Enables additional interrupt mode if needed */ + if (ul_attribute & PIO_IT_AIME) { + /* Enables additional interrupt mode */ + p_pio->PIO_AIMER = ul_mask; + + /* Configures the Polarity of the event detection */ + /* (Rising/Falling Edge or High/Low Level) */ + if (ul_attribute & PIO_IT_RE_OR_HL) { + /* Rising Edge or High Level */ + p_pio->PIO_REHLSR = ul_mask; + } else { + /* Falling Edge or Low Level */ + p_pio->PIO_FELLSR = ul_mask; + } + + /* Configures the type of event detection (Edge or Level) */ + if (ul_attribute & PIO_IT_EDGE) { + /* Edge select */ + p_pio->PIO_ESR = ul_mask; + } else { + /* Level select */ + p_pio->PIO_LSR = ul_mask; + } + } else { + /* Disable additional interrupt mode */ + p_pio->PIO_AIMDR = ul_mask; + } +} + +#ifndef PIO_WPMR_WPKEY_PASSWD +#define PIO_WPMR_WPKEY_PASSWD PIO_WPMR_WPKEY(0x50494FU) +#endif + +/** + * \brief Enable or disable write protect of PIO registers. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_enable 1 to enable, 0 to disable. + */ +void pio_set_writeprotect(Pio *p_pio, const uint32_t ul_enable) +{ + p_pio->PIO_WPMR = PIO_WPMR_WPKEY_PASSWD | (ul_enable & PIO_WPMR_WPEN); +} + +/** + * \brief Read write protect status. + * + * \param p_pio Pointer to a PIO instance. + * + * \return Return write protect status. + */ +uint32_t pio_get_writeprotect_status(const Pio *p_pio) +{ + return p_pio->PIO_WPSR; +} + +/** + * \brief Return the value of a pin. + * + * \param ul_pin The pin number. + * + * \return The pin value. + * + * \note If pin is output: a pull-up or pull-down could hide the actual value. + * The function \ref pio_get can be called to get the actual pin output + * level. + * \note If pin is input: PIOx must be clocked to sample the signal. + * See PMC driver. + */ +uint32_t pio_get_pin_value(uint32_t ul_pin) +{ + Pio *p_pio = pio_get_pin_group(ul_pin); + + return (p_pio->PIO_PDSR >> (ul_pin & 0x1F)) & 1; +} + +/** + * \brief Drive a GPIO pin to 1. + * + * \param ul_pin The pin index. + * + * \note The function \ref pio_configure_pin must be called beforehand. + */ +void pio_set_pin_high(uint32_t ul_pin) +{ + Pio *p_pio = pio_get_pin_group(ul_pin); + + /* Value to be driven on the I/O line: 1. */ + p_pio->PIO_SODR = 1 << (ul_pin & 0x1F); +} + +/** + * \brief Drive a GPIO pin to 0. + * + * \param ul_pin The pin index. + * + * \note The function \ref pio_configure_pin must be called before. + */ +void pio_set_pin_low(uint32_t ul_pin) +{ + Pio *p_pio = pio_get_pin_group(ul_pin); + + /* Value to be driven on the I/O line: 0. */ + p_pio->PIO_CODR = 1 << (ul_pin & 0x1F); +} + +/** + * \brief Toggle a GPIO pin. + * + * \param ul_pin The pin index. + * + * \note The function \ref pio_configure_pin must be called before. + */ +void pio_toggle_pin(uint32_t ul_pin) +{ + Pio *p_pio = pio_get_pin_group(ul_pin); + + if (p_pio->PIO_ODSR & (1 << (ul_pin & 0x1F))) { + /* Value to be driven on the I/O line: 0. */ + p_pio->PIO_CODR = 1 << (ul_pin & 0x1F); + } else { + /* Value to be driven on the I/O line: 1. */ + p_pio->PIO_SODR = 1 << (ul_pin & 0x1F); + } +} + +/** + * \brief Perform complete pin(s) configuration; general attributes and PIO init + * if necessary. + * + * \param ul_pin The pin index. + * \param ul_flags Pins attributes. + * + * \return Whether the pin(s) have been configured properly. + */ +uint32_t pio_configure_pin(uint32_t ul_pin, const uint32_t ul_flags) +{ + Pio *p_pio = pio_get_pin_group(ul_pin); + + /* Configure pins */ + switch (ul_flags & PIO_TYPE_Msk) { + case PIO_TYPE_PIO_PERIPH_A: + pio_set_peripheral(p_pio, PIO_PERIPH_A, (1 << (ul_pin & 0x1F))); + pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)), + (ul_flags & PIO_PULLUP)); + break; + case PIO_TYPE_PIO_PERIPH_B: + pio_set_peripheral(p_pio, PIO_PERIPH_B, (1 << (ul_pin & 0x1F))); + pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)), + (ul_flags & PIO_PULLUP)); + break; +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) + case PIO_TYPE_PIO_PERIPH_C: + pio_set_peripheral(p_pio, PIO_PERIPH_C, (1 << (ul_pin & 0x1F))); + pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)), + (ul_flags & PIO_PULLUP)); + break; + case PIO_TYPE_PIO_PERIPH_D: + pio_set_peripheral(p_pio, PIO_PERIPH_D, (1 << (ul_pin & 0x1F))); + pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)), + (ul_flags & PIO_PULLUP)); + break; +#endif + + case PIO_TYPE_PIO_INPUT: + pio_set_input(p_pio, (1 << (ul_pin & 0x1F)), ul_flags); + break; + + case PIO_TYPE_PIO_OUTPUT_0: + case PIO_TYPE_PIO_OUTPUT_1: + pio_set_output(p_pio, (1 << (ul_pin & 0x1F)), + ((ul_flags & PIO_TYPE_PIO_OUTPUT_1) + == PIO_TYPE_PIO_OUTPUT_1) ? 1 : 0, + (ul_flags & PIO_OPENDRAIN) ? 1 : 0, + (ul_flags & PIO_PULLUP) ? 1 : 0); + break; + + default: + return 0; + } + + return 1; +} + +/** + * \brief Drive a GPIO port to 1. + * + * \param p_pio Base address of the PIO port. + * \param ul_mask Bitmask of one or more pin(s) to toggle. + */ +void pio_set_pin_group_high(Pio *p_pio, uint32_t ul_mask) +{ + /* Value to be driven on the I/O line: 1. */ + p_pio->PIO_SODR = ul_mask; +} + +/** + * \brief Drive a GPIO port to 0. + * + * \param p_pio Base address of the PIO port. + * \param ul_mask Bitmask of one or more pin(s) to toggle. + */ +void pio_set_pin_group_low(Pio *p_pio, uint32_t ul_mask) +{ + /* Value to be driven on the I/O line: 0. */ + p_pio->PIO_CODR = ul_mask; +} + +/** + * \brief Toggle a GPIO group. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + */ +void pio_toggle_pin_group(Pio *p_pio, uint32_t ul_mask) +{ + if (p_pio->PIO_ODSR & ul_mask) { + /* Value to be driven on the I/O line: 0. */ + p_pio->PIO_CODR = ul_mask; + } else { + /* Value to be driven on the I/O line: 1. */ + p_pio->PIO_SODR = ul_mask; + } +} + +/** + * \brief Perform complete pin(s) configuration; general attributes and PIO init + * if necessary. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + * \param ul_flags Pin(s) attributes. + * + * \return Whether the pin(s) have been configured properly. + */ +uint32_t pio_configure_pin_group(Pio *p_pio, + uint32_t ul_mask, const uint32_t ul_flags) +{ + /* Configure pins */ + switch (ul_flags & PIO_TYPE_Msk) { + case PIO_TYPE_PIO_PERIPH_A: + pio_set_peripheral(p_pio, PIO_PERIPH_A, ul_mask); + pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP)); + break; + case PIO_TYPE_PIO_PERIPH_B: + pio_set_peripheral(p_pio, PIO_PERIPH_B, ul_mask); + pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP)); + break; +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) + case PIO_TYPE_PIO_PERIPH_C: + pio_set_peripheral(p_pio, PIO_PERIPH_C, ul_mask); + pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP)); + break; + case PIO_TYPE_PIO_PERIPH_D: + pio_set_peripheral(p_pio, PIO_PERIPH_D, ul_mask); + pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP)); + break; +#endif + + case PIO_TYPE_PIO_INPUT: + pio_set_input(p_pio, ul_mask, ul_flags); + break; + + case PIO_TYPE_PIO_OUTPUT_0: + case PIO_TYPE_PIO_OUTPUT_1: + pio_set_output(p_pio, ul_mask, + ((ul_flags & PIO_TYPE_PIO_OUTPUT_1) + == PIO_TYPE_PIO_OUTPUT_1) ? 1 : 0, + (ul_flags & PIO_OPENDRAIN) ? 1 : 0, + (ul_flags & PIO_PULLUP) ? 1 : 0); + break; + + default: + return 0; + } + + return 1; +} + +/** + * \brief Enable interrupt for a GPIO pin. + * + * \param ul_pin The pin index. + * + * \note The function \ref gpio_configure_pin must be called before. + */ +void pio_enable_pin_interrupt(uint32_t ul_pin) +{ + Pio *p_pio = pio_get_pin_group(ul_pin); + + p_pio->PIO_IER = 1 << (ul_pin & 0x1F); +} + + +/** + * \brief Disable interrupt for a GPIO pin. + * + * \param ul_pin The pin index. + * + * \note The function \ref gpio_configure_pin must be called before. + */ +void pio_disable_pin_interrupt(uint32_t ul_pin) +{ + Pio *p_pio = pio_get_pin_group(ul_pin); + + p_pio->PIO_IDR = 1 << (ul_pin & 0x1F); +} + + +/** + * \brief Return GPIO port for a GPIO pin. + * + * \param ul_pin The pin index. + * + * \return Pointer to \ref Pio struct for GPIO port. + */ +Pio *pio_get_pin_group(uint32_t ul_pin) +{ + Pio *p_pio; + +#if (SAM4C || SAM4CP) +# ifdef ID_PIOD + if (ul_pin > PIO_PC9_IDX) { + p_pio = PIOD; + } else if (ul_pin > PIO_PB31_IDX) { +# else + if (ul_pin > PIO_PB31_IDX) { +# endif + p_pio = PIOC; + } else { + p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5))); + } +#elif (SAM4CM) + if (ul_pin > PIO_PB21_IDX) { + p_pio = PIOC; + } else { + p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5))); + } +#else + p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5))); +#endif + return p_pio; +} + +/** + * \brief Return GPIO port peripheral ID for a GPIO pin. + * + * \param ul_pin The pin index. + * + * \return GPIO port peripheral ID. + */ +uint32_t pio_get_pin_group_id(uint32_t ul_pin) +{ + uint32_t ul_id; + +#if (SAM4C || SAM4CP) +# ifdef ID_PIOD + if (ul_pin > PIO_PC9_IDX) { + ul_id = ID_PIOD; + } else if (ul_pin > PIO_PB31_IDX) { +# else + if (ul_pin > PIO_PB31_IDX) { +# endif + ul_id = ID_PIOC; + } else { + ul_id = ID_PIOA + (ul_pin >> 5); + } +#elif (SAM4CM) + if (ul_pin > PIO_PB21_IDX) { + ul_id = ID_PIOC; + } else { + ul_id = ID_PIOA + (ul_pin >> 5); + } +#elif (SAMV70 || SAMV71 || SAME70 || SAMS70) + if (ul_pin > PIO_PC31_IDX) { + if(ul_pin > PIO_PD31_IDX){ + ul_id = ID_PIOE; + } else { + ul_id = ID_PIOD; + } + } else { + ul_id = ID_PIOA + (ul_pin >> 5); + } +#else + ul_id = ID_PIOA + (ul_pin >> 5); +#endif + return ul_id; +} + + +/** + * \brief Return GPIO port pin mask for a GPIO pin. + * + * \param ul_pin The pin index. + * + * \return GPIO port pin mask. + */ +uint32_t pio_get_pin_group_mask(uint32_t ul_pin) +{ + uint32_t ul_mask = 1 << (ul_pin & 0x1F); + return ul_mask; +} + +#if (SAM3S || SAM4S || SAM4E || SAMV71 || SAMV70 || SAME70 || SAMS70) +/* Capture mode enable flag */ +uint32_t pio_capture_enable_flag; + +/** + * \brief Configure PIO capture mode. + * \note PIO capture mode will be disabled automatically. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mode Bitmask of one or more modes. + */ +void pio_capture_set_mode(Pio *p_pio, uint32_t ul_mode) +{ + ul_mode &= (~PIO_PCMR_PCEN); /* Disable PIO capture mode */ + p_pio->PIO_PCMR = ul_mode; +} + +/** + * \brief Enable PIO capture mode. + * + * \param p_pio Pointer to a PIO instance. + */ +void pio_capture_enable(Pio *p_pio) +{ + p_pio->PIO_PCMR |= PIO_PCMR_PCEN; + pio_capture_enable_flag = true; +} + +/** + * \brief Disable PIO capture mode. + * + * \param p_pio Pointer to a PIO instance. + */ +void pio_capture_disable(Pio *p_pio) +{ + p_pio->PIO_PCMR &= (~PIO_PCMR_PCEN); + pio_capture_enable_flag = false; +} + +/** + * \brief Read from Capture Reception Holding Register. + * \note Data presence should be tested before any read attempt. + * + * \param p_pio Pointer to a PIO instance. + * \param pul_data Pointer to store the data. + * + * \retval 0 Success. + * \retval 1 I/O Failure, Capture data is not ready. + */ +uint32_t pio_capture_read(const Pio *p_pio, uint32_t *pul_data) +{ + /* Check if the data is ready */ + if ((p_pio->PIO_PCISR & PIO_PCISR_DRDY) == 0) { + return 1; + } + + /* Read data */ + *pul_data = p_pio->PIO_PCRHR; + return 0; +} + +/** + * \brief Enable the given interrupt source of PIO capture. The status + * register of the corresponding PIO capture controller is cleared prior + * to enabling the interrupt. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Interrupt sources bit map. + */ +void pio_capture_enable_interrupt(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_PCISR; + p_pio->PIO_PCIER = ul_mask; +} + +/** + * \brief Disable a given interrupt source of PIO capture. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Interrupt sources bit map. + */ +void pio_capture_disable_interrupt(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_PCIDR = ul_mask; +} + +/** + * \brief Read PIO interrupt status of PIO capture. + * + * \param p_pio Pointer to a PIO instance. + * + * \return The interrupt status mask value. + */ +uint32_t pio_capture_get_interrupt_status(const Pio *p_pio) +{ + return p_pio->PIO_PCISR; +} + +/** + * \brief Read PIO interrupt mask of PIO capture. + * + * \param p_pio Pointer to a PIO instance. + * + * \return The interrupt mask value. + */ +uint32_t pio_capture_get_interrupt_mask(const Pio *p_pio) +{ + return p_pio->PIO_PCIMR; +} +#if !(SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Get PDC registers base address. + * + * \param p_pio Pointer to an PIO peripheral. + * + * \return PIOA PDC register base address. + */ +Pdc *pio_capture_get_pdc_base(const Pio *p_pio) +{ + UNUSED(p_pio); /* Stop warning */ + return PDC_PIOA; +} +#endif +#endif + +#if (SAM4C || SAM4CP || SAM4CM || SAMG55) +/** + * \brief Set PIO IO drive. + * + * \param p_pio Pointer to an PIO peripheral. + * \param ul_line Line index (0..31). + * \param mode IO drive mode. + */ +void pio_set_io_drive(Pio *p_pio, uint32_t ul_line, + enum pio_io_drive_mode mode) +{ + p_pio->PIO_DRIVER &= ~(1 << ul_line); + p_pio->PIO_DRIVER |= mode << ul_line; +} +#endif + +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Enable PIO keypad controller. + * + * \param p_pio Pointer to a PIO instance. + */ +void pio_keypad_enable(Pio *p_pio) +{ + p_pio->PIO_KER |= PIO_KER_KCE; +} + +/** + * \brief Disable PIO keypad controller. + * + * \param p_pio Pointer to a PIO instance. + */ +void pio_keypad_disable(Pio *p_pio) +{ + p_pio->PIO_KER &= (~PIO_KER_KCE); +} + +/** + * \brief Set PIO keypad controller row number. + * + * \param p_pio Pointer to a PIO instance. + * \param num Number of row of the keypad matrix. + */ +void pio_keypad_set_row_num(Pio *p_pio, uint8_t num) +{ + p_pio->PIO_KRCR &= (~PIO_KRCR_NBR_Msk); + p_pio->PIO_KRCR |= PIO_KRCR_NBR(num); +} + +/** + * \brief Get PIO keypad controller row number. + * + * \param p_pio Pointer to a PIO instance. + * + * \return Number of row of the keypad matrix. + */ +uint8_t pio_keypad_get_row_num(const Pio *p_pio) +{ + return ((p_pio->PIO_KRCR & PIO_KRCR_NBR_Msk) >> PIO_KRCR_NBR_Pos); +} + +/** + * \brief Set PIO keypad controller column number. + * + * \param p_pio Pointer to a PIO instance. + * \param num Number of column of the keypad matrix. + */ +void pio_keypad_set_column_num(Pio *p_pio, uint8_t num) +{ + p_pio->PIO_KRCR &= (~PIO_KRCR_NBC_Msk); + p_pio->PIO_KRCR |= PIO_KRCR_NBC(num); +} + +/** + * \brief Get PIO keypad controller column number. + * + * \param p_pio Pointer to a PIO instance. + * + * \return Number of column of the keypad matrix. + */ +uint8_t pio_keypad_get_column_num(const Pio *p_pio) +{ + return ((p_pio->PIO_KRCR & PIO_KRCR_NBC_Msk) >> PIO_KRCR_NBC_Pos); +} + +/** + * \brief Set PIO keypad matrix debouncing value. + * + * \param p_pio Pointer to a PIO instance. + * \param num Number of debouncing value. + */ +void pio_keypad_set_debouncing_value(Pio *p_pio, uint16_t value) +{ + p_pio->PIO_KDR = PIO_KDR_DBC(value); +} + +/** + * \brief Get PIO keypad matrix debouncing value. + * + * \param p_pio Pointer to a PIO instance. + * + * \return The keypad debouncing value. + */ +uint16_t pio_keypad_get_debouncing_value(const Pio *p_pio) +{ + return ((p_pio->PIO_KDR & PIO_KDR_DBC_Msk) >> PIO_KDR_DBC_Pos); +} + +/** + * \brief Enable the interrupt source of PIO keypad. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Interrupt sources bit map. + */ +void pio_keypad_enable_interrupt(Pio *p_pio, uint32_t ul_mask) +{ + p_pio->PIO_KIER = ul_mask; +} + +/** + * \brief Disable the interrupt source of PIO keypad. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Interrupt sources bit map. + */ +void pio_keypad_disable_interrupt(Pio *p_pio, uint32_t ul_mask) +{ + p_pio->PIO_KIDR = ul_mask; +} + +/** + * \brief Get interrupt mask of PIO keypad. + * + * \param p_pio Pointer to a PIO instance. + * + * \return The interrupt mask value. + */ +uint32_t pio_keypad_get_interrupt_mask(const Pio *p_pio) +{ + return p_pio->PIO_KIMR; +} + +/** + * \brief Get key press status of PIO keypad. + * + * \param p_pio Pointer to a PIO instance. + * + * \return The status of key press. + * 0: No key press has been detected. + * 1: At least one key press has been detected. + */ +uint32_t pio_keypad_get_press_status(const Pio *p_pio) +{ + if (p_pio->PIO_KSR & PIO_KSR_KPR) { + return 1; + } else { + return 0; + } +} + +/** + * \brief Get key release status of PIO keypad. + * + * \param p_pio Pointer to a PIO instance. + * + * \return The status of key release. + * 0 No key release has been detected. + * 1 At least one key release has been detected. + */ +uint32_t pio_keypad_get_release_status(const Pio *p_pio) +{ + if (p_pio->PIO_KSR & PIO_KSR_KRL) { + return 1; + } else { + return 0; + } +} + +/** + * \brief Get simultaneous key press number of PIO keypad. + * + * \param p_pio Pointer to a PIO instance. + * + * \return The number of simultaneous key press. + */ +uint8_t pio_keypad_get_simult_press_num(const Pio *p_pio) +{ + return ((p_pio->PIO_KSR & PIO_KSR_NBKPR_Msk) >> PIO_KSR_NBKPR_Pos); +} + +/** + * \brief Get simultaneous key release number of PIO keypad. + * + * \param p_pio Pointer to a PIO instance. + * + * \return The number of simultaneous key release. + */ +uint8_t pio_keypad_get_simult_release_num(const Pio *p_pio) +{ + return ((p_pio->PIO_KSR & PIO_KSR_NBKRL_Msk) >> PIO_KSR_NBKRL_Pos); +} + +/** + * \brief Get detected key press row index of PIO keypad. + * + * \param p_pio Pointer to a PIO instance. + * \param queue The queue of key press row + * + * \return The index of detected key press row. + */ +uint8_t pio_keypad_get_press_row_index(const Pio *p_pio, uint8_t queue) +{ + switch (queue) { + case 0: + return ((p_pio->PIO_KKPR & PIO_KKPR_KEY0ROW_Msk) >> PIO_KKPR_KEY0ROW_Pos); + case 1: + return ((p_pio->PIO_KKPR & PIO_KKPR_KEY1ROW_Msk) >> PIO_KKPR_KEY1ROW_Pos); + case 2: + return ((p_pio->PIO_KKPR & PIO_KKPR_KEY2ROW_Msk) >> PIO_KKPR_KEY2ROW_Pos); + case 3: + return ((p_pio->PIO_KKPR & PIO_KKPR_KEY3ROW_Msk) >> PIO_KKPR_KEY3ROW_Pos); + default: + return 0; + } +} + +/** + * \brief Get detected key press column index of PIO keypad. + * + * \param p_pio Pointer to a PIO instance. + * \param queue The queue of key press column + * + * \return The index of detected key press column. + */ +uint8_t pio_keypad_get_press_column_index(const Pio *p_pio, uint8_t queue) +{ + switch (queue) { + case 0: + return ((p_pio->PIO_KKPR & PIO_KKPR_KEY0COL_Msk) >> PIO_KKPR_KEY0COL_Pos); + case 1: + return ((p_pio->PIO_KKPR & PIO_KKPR_KEY1COL_Msk) >> PIO_KKPR_KEY1COL_Pos); + case 2: + return ((p_pio->PIO_KKPR & PIO_KKPR_KEY2COL_Msk) >> PIO_KKPR_KEY2COL_Pos); + case 3: + return ((p_pio->PIO_KKPR & PIO_KKPR_KEY3COL_Msk) >> PIO_KKPR_KEY3COL_Pos); + default: + return 0; + } +} + +/** + * \brief Get detected key release row index of PIO keypad. + * + * \param p_pio Pointer to a PIO instance. + * \param queue The queue of key release row + * + * \return The index of detected key release row. + */ +uint8_t pio_keypad_get_release_row_index(const Pio *p_pio, uint8_t queue) +{ + switch (queue) { + case 0: + return ((p_pio->PIO_KKRR & PIO_KKRR_KEY0ROW_Msk) >> PIO_KKRR_KEY0ROW_Pos); + case 1: + return ((p_pio->PIO_KKRR & PIO_KKRR_KEY1ROW_Msk) >> PIO_KKRR_KEY1ROW_Pos); + case 2: + return ((p_pio->PIO_KKRR & PIO_KKRR_KEY2ROW_Msk) >> PIO_KKRR_KEY2ROW_Pos); + case 3: + return ((p_pio->PIO_KKRR & PIO_KKRR_KEY3ROW_Msk) >> PIO_KKRR_KEY3ROW_Pos); + default: + return 0; + } +} + +/** + * \brief Get detected key release column index of PIO keypad. + * + * \param p_pio Pointer to a PIO instance. + * \param queue The queue of key release column + * + * \return The index of detected key release column. + */ +uint8_t pio_keypad_get_release_column_index(const Pio *p_pio, uint8_t queue) +{ + switch (queue) { + case 0: + return ((p_pio->PIO_KKRR & PIO_KKRR_KEY0COL_Msk) >> PIO_KKRR_KEY0COL_Pos); + case 1: + return ((p_pio->PIO_KKRR & PIO_KKRR_KEY1COL_Msk) >> PIO_KKRR_KEY1COL_Pos); + case 2: + return ((p_pio->PIO_KKRR & PIO_KKRR_KEY2COL_Msk) >> PIO_KKRR_KEY2COL_Pos); + case 3: + return ((p_pio->PIO_KKRR & PIO_KKRR_KEY3COL_Msk) >> PIO_KKRR_KEY3COL_Pos); + default: + return 0; + } +} + +#endif + +//@} + diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/pio/pio.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/pio/pio.h new file mode 100644 index 0000000..b01d478 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/pio/pio.h @@ -0,0 +1,377 @@ +/** + * \file + * + * \brief Parallel Input/Output (PIO) Controller driver for SAM. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef PIO_H_INCLUDED +#define PIO_H_INCLUDED + +#include "compiler.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Compute PIO register length */ +#define PIO_DELTA ((uint32_t) PIOB - (uint32_t) PIOA) + +/* GPIO Support */ +#define PIO_TYPE_Pos 27 +/* PIO Type Mask */ +#define PIO_TYPE_Msk (0xFu << PIO_TYPE_Pos) +/* The pin is not a function pin. */ +#define PIO_TYPE_NOT_A_PIN (0x0u << PIO_TYPE_Pos) +/* The pin is controlled by the peripheral A. */ +#define PIO_TYPE_PIO_PERIPH_A (0x1u << PIO_TYPE_Pos) +/* The pin is controlled by the peripheral B. */ +#define PIO_TYPE_PIO_PERIPH_B (0x2u << PIO_TYPE_Pos) +/* The pin is controlled by the peripheral C. */ +#define PIO_TYPE_PIO_PERIPH_C (0x3u << PIO_TYPE_Pos) +/* The pin is controlled by the peripheral D. */ +#define PIO_TYPE_PIO_PERIPH_D (0x4u << PIO_TYPE_Pos) +/* The pin is an input. */ +#define PIO_TYPE_PIO_INPUT (0x5u << PIO_TYPE_Pos) +/* The pin is an output and has a default level of 0. */ +#define PIO_TYPE_PIO_OUTPUT_0 (0x6u << PIO_TYPE_Pos) +/* The pin is an output and has a default level of 1. */ +#define PIO_TYPE_PIO_OUTPUT_1 (0x7u << PIO_TYPE_Pos) + +typedef enum _pio_type { + PIO_NOT_A_PIN = PIO_TYPE_NOT_A_PIN, + PIO_PERIPH_A = PIO_TYPE_PIO_PERIPH_A, + PIO_PERIPH_B = PIO_TYPE_PIO_PERIPH_B, +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) + PIO_PERIPH_C = PIO_TYPE_PIO_PERIPH_C, + PIO_PERIPH_D = PIO_TYPE_PIO_PERIPH_D, +#endif + PIO_INPUT = PIO_TYPE_PIO_INPUT, + PIO_OUTPUT_0 = PIO_TYPE_PIO_OUTPUT_0, + PIO_OUTPUT_1 = PIO_TYPE_PIO_OUTPUT_1 +} pio_type_t; + +/* Default pin configuration (no attribute). */ +#define PIO_DEFAULT (0u << 0) +/* The internal pin pull-up is active. */ +#define PIO_PULLUP (1u << 0) +/* The internal glitch filter is active. */ +#define PIO_DEGLITCH (1u << 1) +/* The pin is open-drain. */ +#define PIO_OPENDRAIN (1u << 2) + +/* The internal debouncing filter is active. */ +#define PIO_DEBOUNCE (1u << 3) + +/* Enable additional interrupt modes. */ +#define PIO_IT_AIME (1u << 4) + +/* Interrupt High Level/Rising Edge detection is active. */ +#define PIO_IT_RE_OR_HL (1u << 5) +/* Interrupt Edge detection is active. */ +#define PIO_IT_EDGE (1u << 6) + +/* Low level interrupt is active */ +#define PIO_IT_LOW_LEVEL (0 | 0 | PIO_IT_AIME) +/* High level interrupt is active */ +#define PIO_IT_HIGH_LEVEL (PIO_IT_RE_OR_HL | 0 | PIO_IT_AIME) +/* Falling edge interrupt is active */ +#define PIO_IT_FALL_EDGE (0 | PIO_IT_EDGE | PIO_IT_AIME) +/* Rising edge interrupt is active */ +#define PIO_IT_RISE_EDGE (PIO_IT_RE_OR_HL | PIO_IT_EDGE | PIO_IT_AIME) + +/* + * The #attribute# field is a bitmask that can either be set to PIO_DEFAULT, + * or combine (using bitwise OR '|') any number of the following constants: + * - PIO_PULLUP + * - PIO_DEGLITCH + * - PIO_DEBOUNCE + * - PIO_OPENDRAIN + * - PIO_IT_LOW_LEVEL + * - PIO_IT_HIGH_LEVEL + * - PIO_IT_FALL_EDGE + * - PIO_IT_RISE_EDGE + */ +void pio_pull_up(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_pull_up_enable); +void pio_set_debounce_filter(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_cut_off); +void pio_set(Pio *p_pio, const uint32_t ul_mask); +void pio_clear(Pio *p_pio, const uint32_t ul_mask); +uint32_t pio_get(Pio *p_pio, const pio_type_t ul_type, + const uint32_t ul_mask); +void pio_set_peripheral(Pio *p_pio, const pio_type_t ul_type, + const uint32_t ul_mask); +void pio_set_input(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_attribute); +void pio_set_output(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_default_level, + const uint32_t ul_multidrive_enable, + const uint32_t ul_pull_up_enable); +uint32_t pio_configure(Pio *p_pio, const pio_type_t ul_type, + const uint32_t ul_mask, const uint32_t ul_attribute); +uint32_t pio_get_output_data_status(const Pio *p_pio, + const uint32_t ul_mask); +void pio_set_multi_driver(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_multi_driver_enable); +uint32_t pio_get_multi_driver_status(const Pio *p_pio); + +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) +void pio_pull_down(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_pull_down_enable); +#endif + +void pio_enable_output_write(Pio *p_pio, const uint32_t ul_mask); +void pio_disable_output_write(Pio *p_pio, const uint32_t ul_mask); +uint32_t pio_get_output_write_status(const Pio *p_pio); +void pio_sync_output_write(Pio *p_pio, const uint32_t ul_mask); + +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAME70 || SAMS70) +void pio_set_schmitt_trigger(Pio *p_pio, const uint32_t ul_mask); +uint32_t pio_get_schmitt_trigger(const Pio *p_pio); +#endif + +void pio_configure_interrupt(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_attr); +void pio_enable_interrupt(Pio *p_pio, const uint32_t ul_mask); +void pio_disable_interrupt(Pio *p_pio, const uint32_t ul_mask); +uint32_t pio_get_interrupt_status(const Pio *p_pio); +uint32_t pio_get_interrupt_mask(const Pio *p_pio); +void pio_set_additional_interrupt_mode(Pio *p_pio, + const uint32_t ul_mask, const uint32_t ul_attribute); +void pio_set_writeprotect(Pio *p_pio, const uint32_t ul_enable); +uint32_t pio_get_writeprotect_status(const Pio *p_pio); + +#if (SAM3S || SAM4S || SAM4E || SAMV71 || SAMV70 || SAME70 || SAMS70) +void pio_capture_set_mode(Pio *p_pio, uint32_t ul_mode); +void pio_capture_enable(Pio *p_pio); +void pio_capture_disable(Pio *p_pio); +uint32_t pio_capture_read(const Pio *p_pio, uint32_t * pul_data); +void pio_capture_enable_interrupt(Pio *p_pio, const uint32_t ul_mask); +void pio_capture_disable_interrupt(Pio * p_pio, const uint32_t ul_mask); +uint32_t pio_capture_get_interrupt_status(const Pio *p_pio); +uint32_t pio_capture_get_interrupt_mask(const Pio *p_pio); +#if !(SAMV71 || SAMV70 || SAME70 || SAMS70) +Pdc *pio_capture_get_pdc_base(const Pio *p_pio); +#endif +#endif + +/* GPIO Support */ +uint32_t pio_get_pin_value(uint32_t pin); +void pio_set_pin_high(uint32_t pin); +void pio_set_pin_low(uint32_t pin); +void pio_toggle_pin(uint32_t pin); +void pio_enable_pin_interrupt(uint32_t pin); +void pio_disable_pin_interrupt(uint32_t pin); +Pio *pio_get_pin_group(uint32_t pin); +uint32_t pio_get_pin_group_id(uint32_t pin); +uint32_t pio_get_pin_group_mask(uint32_t pin); +uint32_t pio_configure_pin(uint32_t ul_pin, const uint32_t ul_flags); +void pio_set_pin_group_high(Pio *p_pio, uint32_t ul_mask); +void pio_set_pin_group_low(Pio *p_pio, uint32_t ul_mask); +void pio_toggle_pin_group(Pio *p_pio, uint32_t ul_mask); +uint32_t pio_configure_pin_group(Pio *p_pio, uint32_t ul_mask, + const uint32_t ul_flags); + +#if (SAM4C || SAM4CP || SAM4CM || SAMG55) +enum pio_io_drive_mode { + PIO_IO_DRIVE_LOW = 0, + PIO_IO_DRIVE_HIGH, +}; +void pio_set_io_drive(Pio *p_pio, uint32_t ul_line, + enum pio_io_drive_mode mode); +#endif + +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) +void pio_keypad_enable(Pio *p_pio); +void pio_keypad_disable(Pio *p_pio); +void pio_keypad_set_row_num(Pio *p_pio, uint8_t num); +uint8_t pio_keypad_get_row_num(const Pio *p_pio); +void pio_keypad_set_column_num(Pio *p_pio, uint8_t num); +uint8_t pio_keypad_get_column_num(const Pio *p_pio); +void pio_keypad_set_debouncing_value(Pio *p_pio, uint16_t value); +uint16_t pio_keypad_get_debouncing_value(const Pio *p_pio); +void pio_keypad_enable_interrupt(Pio *p_pio, uint32_t ul_mask); +void pio_keypad_disable_interrupt(Pio *p_pio, uint32_t ul_mask); +uint32_t pio_keypad_get_interrupt_mask(const Pio *p_pio); +uint32_t pio_keypad_get_press_status(const Pio *p_pio); +uint32_t pio_keypad_get_release_status(const Pio *p_pio); +uint8_t pio_keypad_get_simult_press_num(const Pio *p_pio); +uint8_t pio_keypad_get_simult_release_num(const Pio *p_pio); +uint8_t pio_keypad_get_press_row_index(const Pio *p_pio, uint8_t queue); +uint8_t pio_keypad_get_press_column_index(const Pio *p_pio, uint8_t queue); +uint8_t pio_keypad_get_release_row_index(const Pio *p_pio, uint8_t queue); +uint8_t pio_keypad_get_release_column_index(const Pio *p_pio, uint8_t queue); +#endif +/** + * \page sam_pio_quickstart Quick Start Guide for the SAM PIO driver + * + * This is the quick start guide for the \ref sam_drivers_pio_group "PIO Driver", + * with step-by-step instructions on how to configure and use the driver for + * specific use cases. + * + * The section described below can be compiled into e.g. the main application + * loop or any other function that will need to interface with the IO port. + * + * \section sam_pio_usecases PIO use cases + * - \ref sam_pio_quickstart_basic + * - \ref sam_pio_quickstart_use_case_2 + * + * \section sam_pio_quickstart_basic Basic usage of the PIO driver + * This section will present a basic use case for the PIO driver. This use case + * will configure pin 23 on port A as output and pin 16 as an input with pullup, + * and then toggle the output pin's value to match that of the input pin. + * + * \subsection sam_pio_quickstart_use_case_1_prereq Prerequisites + * - \ref group_pmc "Power Management Controller driver" + * + * \subsection sam_pio_quickstart_use_case_1_setup_steps Initialization code + * Add to the application initialization code: + * \code + pmc_enable_periph_clk(ID_PIOA); + + pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE); + pio_set_input(PIOA, PIO_PA16, PIO_PULLUP); +\endcode + * + * \subsection sam_pio_quickstart_use_case_1_setup_steps_workflow Workflow + * -# Enable the module clock to the PIOA peripheral: + * \code pmc_enable_periph_clk(ID_PIOA); \endcode + * -# Set pin 23 direction on PIOA as output, default low level: + * \code pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE); \endcode + * -# Set pin 16 direction on PIOA as input, with pullup: + * \code pio_set_input(PIOA, PIO_PA16, PIO_PULLUP); \endcode + * + * \subsection sam_pio_quickstart_use_case_1_example_code Example code + * Set the state of output pin 23 to match input pin 16: + * \code + if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16)) + pio_clear(PIOA, PIO_PA23); + else + pio_set(PIOA, PIO_PA23); +\endcode + * + * \subsection sam_pio_quickstart_use_case_1_example_workflow Workflow + * -# We check the value of the pin: + * \code + if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16)) +\endcode + * -# Then we set the new output value based on the read pin value: + * \code + pio_clear(PIOA, PIO_PA23); + else + pio_set(PIOA, PIO_PA23); +\endcode + */ + +/** + * \page sam_pio_quickstart_use_case_2 Advanced use case - Interrupt driven edge detection + * + * \section sam_pio_quickstart_use_case_2 Advanced Use Case 1 + * This section will present a more advanced use case for the PIO driver. This use case + * will configure pin 23 on port A as output and pin 16 as an input with pullup, + * and then toggle the output pin's value to match that of the input pin using the interrupt + * controller within the device. + * + * \subsection sam_pio_quickstart_use_case_2_prereq Prerequisites + * - \ref group_pmc "Power Management Controller driver" + * + * \subsection sam_pio_quickstart_use_case_2_setup_steps Initialization code + * Add to the application initialization code: + * \code + pmc_enable_periph_clk(ID_PIOA); + + pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE); + pio_set_input(PIOA, PIO_PA16, PIO_PULLUP); + + pio_handler_set(PIOA, ID_PIOA, PIO_PA16, PIO_IT_EDGE, pin_edge_handler); + pio_enable_interrupt(PIOA, PIO_PA16); + + NVIC_EnableIRQ(PIOA_IRQn); +\endcode + * + * \subsection sam_pio_quickstart_use_case_2_setup_steps_workflow Workflow + * -# Enable the module clock to the PIOA peripheral: + * \code pmc_enable_periph_clk(ID_PIOA); \endcode + * -# Set pin 23 direction on PIOA as output, default low level: + * \code pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE); \endcode + * -# Set pin 16 direction on PIOA as input, with pullup: + * \code pio_set_input(PIOA, PIO_PA16, PIO_PULLUP); \endcode + * -# Configure the input pin 16 interrupt mode and handler: + * \code pio_handler_set(PIOA, ID_PIOA, PIO_PA16, PIO_IT_EDGE, pin_edge_handler); \endcode + * -# Enable the interrupt for the configured input pin: + * \code pio_enable_interrupt(PIOA, PIO_PA16); \endcode + * -# Enable interrupt handling from the PIOA module: + * \code NVIC_EnableIRQ(PIOA_IRQn); \endcode + * + * \subsection sam_pio_quickstart_use_case_2_example_code Example code + * Add the following function to your application: + * \code + void pin_edge_handler(const uint32_t id, const uint32_t index) + { + if ((id == ID_PIOA) && (index == PIO_PA16)){ + if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16)) + pio_clear(PIOA, PIO_PA23); + else + pio_set(PIOA, PIO_PA23); + } + } +\endcode + * + * \subsection sam_pio_quickstart_use_case_2_example_workflow Workflow + * -# We check the value of the pin: + * \code + if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16)) +\endcode + * -# Then we set the new output value based on the read pin value: + * \code + pio_clear(PIOA, PIO_PA23); + else + pio_set(PIOA, PIO_PA23); +\endcode + */ + +#ifdef __cplusplus +} +#endif + +#endif /* PIO_H_INCLUDED */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/pio/pio_handler.c b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/pio/pio_handler.c new file mode 100644 index 0000000..59650d9 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/pio/pio_handler.c @@ -0,0 +1,286 @@ +/** + * \file + * + * \brief Parallel Input/Output (PIO) interrupt handler for SAM. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#include "pio.h" +#include "pio_handler.h" + +/** + * Maximum number of interrupt sources that can be defined. This + * constant can be increased, but the current value is the smallest possible one + * that will be compatible with all existing projects. + */ +#define MAX_INTERRUPT_SOURCES 7 + +/** + * Describes a PIO interrupt source, including the PIO instance triggering the + * interrupt and the associated interrupt handler. + */ +struct s_interrupt_source { + uint32_t id; + uint32_t mask; + uint32_t attr; + + /* Interrupt handler. */ + void (*handler) (const uint32_t, const uint32_t); +}; + + +/* List of interrupt sources. */ +static struct s_interrupt_source gs_interrupt_sources[MAX_INTERRUPT_SOURCES]; + +/* Number of currently defined interrupt sources. */ +static uint32_t gs_ul_nb_sources = 0; + +#if (SAM3S || SAM4S || SAM4E) +/* PIO Capture handler */ +static void (*pio_capture_handler)(Pio *) = NULL; +extern uint32_t pio_capture_enable_flag; +#endif + +/** + * \brief Process an interrupt request on the given PIO controller. + * + * \param p_pio PIO controller base address. + * \param ul_id PIO controller ID. + */ +void pio_handler_process(Pio *p_pio, uint32_t ul_id) +{ + uint32_t status; + uint32_t i; + + /* Read PIO controller status */ + status = pio_get_interrupt_status(p_pio); + status &= pio_get_interrupt_mask(p_pio); + + /* Check pending events */ + if (status != 0) { + /* Find triggering source */ + i = 0; + while (status != 0) { + /* Source is configured on the same controller */ + if (gs_interrupt_sources[i].id == ul_id) { + /* Source has PIOs whose statuses have changed */ + if ((status & gs_interrupt_sources[i].mask) != 0) { + gs_interrupt_sources[i].handler(gs_interrupt_sources[i].id, + gs_interrupt_sources[i].mask); + status &= ~(gs_interrupt_sources[i].mask); + } + } + i++; + if (i >= MAX_INTERRUPT_SOURCES) { + break; + } + } + } + + /* Check capture events */ +#if (SAM3S || SAM4S || SAM4E) + if (pio_capture_enable_flag) { + if (pio_capture_handler) { + pio_capture_handler(p_pio); + } + } +#endif +} + +/** + * \brief Set an interrupt handler for the provided pins. + * The provided handler will be called with the triggering pin as its parameter + * as soon as an interrupt is detected. + * + * \param p_pio PIO controller base address. + * \param ul_id PIO ID. + * \param ul_mask Pins (bit mask) to configure. + * \param ul_attr Pins attribute to configure. + * \param p_handler Interrupt handler function pointer. + * + * \return 0 if successful, 1 if the maximum number of sources has been defined. + */ +uint32_t pio_handler_set(Pio *p_pio, uint32_t ul_id, uint32_t ul_mask, + uint32_t ul_attr, void (*p_handler) (uint32_t, uint32_t)) +{ + struct s_interrupt_source *pSource; + + if (gs_ul_nb_sources >= MAX_INTERRUPT_SOURCES) + return 1; + + /* Define new source */ + pSource = &(gs_interrupt_sources[gs_ul_nb_sources]); + pSource->id = ul_id; + pSource->mask = ul_mask; + pSource->attr = ul_attr; + pSource->handler = p_handler; + gs_ul_nb_sources++; + + /* Configure interrupt mode */ + pio_configure_interrupt(p_pio, ul_mask, ul_attr); + + return 0; +} + +#if (SAM3S || SAM4S || SAM4E) +/** + * \brief Set a capture interrupt handler for all PIO. + * + * The handler will be called with the triggering PIO as its parameter + * as soon as an interrupt is detected. + * + * \param p_handler Interrupt handler function pointer. + * + */ +void pio_capture_handler_set(void (*p_handler)(Pio *)) +{ + pio_capture_handler = p_handler; +} +#endif + +#ifdef ID_PIOA +/** + * \brief Set an interrupt handler for the specified pin. + * The provided handler will be called with the triggering pin as its parameter + * as soon as an interrupt is detected. + * + * \param ul_pin Pin index to configure. + * \param ul_flag Pin flag. + * \param p_handler Interrupt handler function pointer. + * + * \return 0 if successful, 1 if the maximum number of sources has been defined. + */ +uint32_t pio_handler_set_pin(uint32_t ul_pin, uint32_t ul_flag, + void (*p_handler) (uint32_t, uint32_t)) +{ + Pio *p_pio = pio_get_pin_group(ul_pin); + uint32_t group_id = pio_get_pin_group_id(ul_pin); + uint32_t group_mask = pio_get_pin_group_mask(ul_pin); + + return pio_handler_set(p_pio, group_id, group_mask, ul_flag, p_handler); +} + +/** + * \brief Parallel IO Controller A interrupt handler. + * Redefined PIOA interrupt handler for NVIC interrupt table. + */ +void PIOA_Handler(void) +{ + pio_handler_process(PIOA, ID_PIOA); +} +#endif + +#ifdef ID_PIOB +/** + * \brief Parallel IO Controller B interrupt handler + * Redefined PIOB interrupt handler for NVIC interrupt table. + */ +void PIOB_Handler(void) +{ + pio_handler_process(PIOB, ID_PIOB); +} +#endif + +#ifdef ID_PIOC +/** + * \brief Parallel IO Controller C interrupt handler. + * Redefined PIOC interrupt handler for NVIC interrupt table. + */ +void PIOC_Handler(void) +{ + pio_handler_process(PIOC, ID_PIOC); +} +#endif + +#ifdef ID_PIOD +/** + * \brief Parallel IO Controller D interrupt handler. + * Redefined PIOD interrupt handler for NVIC interrupt table. + */ +void PIOD_Handler(void) +{ + pio_handler_process(PIOD, ID_PIOD); +} +#endif + +#ifdef ID_PIOE +/** + * \brief Parallel IO Controller E interrupt handler. + * Redefined PIOE interrupt handler for NVIC interrupt table. + */ +void PIOE_Handler(void) +{ + pio_handler_process(PIOE, ID_PIOE); +} +#endif + +#ifdef ID_PIOF +/** + * \brief Parallel IO Controller F interrupt handler. + * Redefined PIOF interrupt handler for NVIC interrupt table. + */ +void PIOF_Handler(void) +{ + pio_handler_process(PIOF, ID_PIOF); +} +#endif + +/** + * \brief Initialize PIO interrupt management logic. + * + * \param p_pio PIO controller base address. + * \param ul_irqn NVIC line number. + * \param ul_priority PIO controller interrupts priority. + */ +void pio_handler_set_priority(Pio *p_pio, IRQn_Type ul_irqn, uint32_t ul_priority) +{ + uint32_t bitmask = 0; + + bitmask = pio_get_interrupt_mask(p_pio); + pio_disable_interrupt(p_pio, 0xFFFFFFFF); + pio_get_interrupt_status(p_pio); + NVIC_DisableIRQ(ul_irqn); + NVIC_ClearPendingIRQ(ul_irqn); + NVIC_SetPriority(ul_irqn, ul_priority); + NVIC_EnableIRQ(ul_irqn); + pio_enable_interrupt(p_pio, bitmask); +} diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/pio/pio_handler.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/pio/pio_handler.h new file mode 100644 index 0000000..0aa3476 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/pio/pio_handler.h @@ -0,0 +1,69 @@ +/** + * \file + * + * \brief Parallel Input/Output (PIO) interrupt handler for SAM. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef PIO_HANDLER_H_INCLUDED +#define PIO_HANDLER_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +void pio_handler_process(Pio *p_pio, uint32_t ul_id); +void pio_handler_set_priority(Pio *p_pio, IRQn_Type ul_irqn, uint32_t ul_priority); +uint32_t pio_handler_set(Pio *p_pio, uint32_t ul_id, uint32_t ul_mask, + uint32_t ul_attr, void (*p_handler) (uint32_t, uint32_t)); +uint32_t pio_handler_set_pin(uint32_t ul_pin, uint32_t ul_flag, + void (*p_handler) (uint32_t, uint32_t)); + +#if (SAM3S || SAM4S || SAM4E) +void pio_capture_handler_set(void (*p_handler)(Pio *)); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* PIO_HANDLER_H_INCLUDED */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/pmc/pmc.c b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/pmc/pmc.c new file mode 100644 index 0000000..da5c032 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/pmc/pmc.c @@ -0,0 +1,1651 @@ +/** + * \file + * + * \brief Power Management Controller (PMC) driver for SAM. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#include "pmc.h" + +#if (SAM3N) +# define MAX_PERIPH_ID 31 +#elif (SAM3XA) +# define MAX_PERIPH_ID 44 +#elif (SAM3U) +# define MAX_PERIPH_ID 29 +#elif (SAM3S || SAM4S) +# define MAX_PERIPH_ID 34 +#elif (SAM4E) +# define MAX_PERIPH_ID 47 +#elif (SAMV71) +# define MAX_PERIPH_ID 63 +#elif (SAMV70) +# define MAX_PERIPH_ID 63 +#elif (SAME70) +# define MAX_PERIPH_ID 63 +#elif (SAMS70) +# define MAX_PERIPH_ID 63 +#elif (SAM4N) +# define MAX_PERIPH_ID 31 +#elif (SAM4C || SAM4CM || SAM4CP) +# define MAX_PERIPH_ID 43 +#elif (SAMG51) +# define MAX_PERIPH_ID 47 +#elif (SAMG53) +# define MAX_PERIPH_ID 47 +#elif (SAMG54) +# define MAX_PERIPH_ID 47 +#elif (SAMG55) +# define MAX_PERIPH_ID 50 +#endif + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \defgroup sam_drivers_pmc_group Power Management Controller (PMC) + * + * \par Purpose + * + * The Power Management Controller (PMC) optimizes power consumption by + * controlling all system and user peripheral clocks. The PMC enables/disables + * the clock inputs to many of the peripherals and the Cortex-M Processor. + * + * @{ + */ + +/** + * \brief Set the prescaler of the MCK. + * + * \param ul_pres Prescaler value. + */ +void pmc_mck_set_prescaler(uint32_t ul_pres) +{ + PMC->PMC_MCKR = + (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); +} + +#if SAMV71 || SAMV70 || SAME70 || SAMS70 +/** + * \brief Set the division of the MCK. + * + * \param ul_div Division value. + */ +void pmc_mck_set_division(uint32_t ul_div) +{ + switch (ul_div) { + case 1: + ul_div = PMC_MCKR_MDIV_EQ_PCK; + break; + case 2: + ul_div = PMC_MCKR_MDIV_PCK_DIV2; + break; + case 3: + ul_div = PMC_MCKR_MDIV_PCK_DIV3; + break; + case 4: + ul_div = PMC_MCKR_MDIV_PCK_DIV4; + break; + default: + ul_div = PMC_MCKR_MDIV_EQ_PCK; + break; + } + PMC->PMC_MCKR = + (PMC->PMC_MCKR & (~PMC_MCKR_MDIV_Msk)) | ul_div; + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); +} +#endif + +/** + * \brief Set the source of the MCK. + * + * \param ul_source Source selection value. + */ +void pmc_mck_set_source(uint32_t ul_source) +{ + PMC->PMC_MCKR = + (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | ul_source; + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); +} + +/** + * \brief Switch master clock source selection to slow clock. + * + * \param ul_pres Processor clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_mck_to_sclk(uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | + PMC_MCKR_CSS_SLOW_CLK; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} + +/** + * \brief Switch master clock source selection to main clock. + * + * \param ul_pres Processor clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_mck_to_mainck(uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | + PMC_MCKR_CSS_MAIN_CLK; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} + +/** + * \brief Switch master clock source selection to PLLA clock. + * + * \param ul_pres Processor clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | + PMC_MCKR_CSS_PLLA_CLK; + + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} + +#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55) +/** + * \brief Switch master clock source selection to PLLB clock. + * + * \param ul_pres Processor clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_mck_to_pllbck(uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | + PMC_MCKR_CSS_PLLB_CLK; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} +#endif + +#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Switch master clock source selection to UPLL clock. + * + * \param ul_pres Processor clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_mck_to_upllck(uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | + PMC_MCKR_CSS_UPLL_CLK; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} +#endif + +/** + * \brief Switch slow clock source selection to external 32k (Xtal or Bypass). + * + * \note Switching SCLK back to 32krc is only possible by shutting down the + * VDDIO power supply. + * + * \param ul_bypass 0 for Xtal, 1 for bypass. + */ +void pmc_switch_sclk_to_32kxtal(uint32_t ul_bypass) +{ + /* Set Bypass mode if required */ + if (ul_bypass == 1) { + SUPC->SUPC_MR |= SUPC_MR_KEY_PASSWD | + SUPC_MR_OSCBYPASS; + } + + SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL; +} + +/** + * \brief Check if the external 32k Xtal is ready. + * + * \retval 1 External 32k Xtal is ready. + * \retval 0 External 32k Xtal is not ready. + */ +uint32_t pmc_osc_is_ready_32kxtal(void) +{ + return ((SUPC->SUPC_SR & SUPC_SR_OSCSEL) + && (PMC->PMC_SR & PMC_SR_OSCSELS)); +} + +/** + * \brief Switch main clock source selection to internal fast RC. + * + * \param ul_moscrcf Fast RC oscillator(4/8/12Mhz). + * + * \retval 0 Success. + * \retval 1 Timeout error. + * \retval 2 Invalid frequency. + */ +void pmc_switch_mainck_to_fastrc(uint32_t ul_moscrcf) +{ + /* Enable Fast RC oscillator but DO NOT switch to RC now */ + PMC->CKGR_MOR |= (CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN); + + /* Wait the Fast RC to stabilize */ + while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)); + + /* Change Fast RC oscillator frequency */ + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) | + CKGR_MOR_KEY_PASSWD | ul_moscrcf; + + /* Wait the Fast RC to stabilize */ + while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)); + + /* Switch to Fast RC */ + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) | + CKGR_MOR_KEY_PASSWD; +} + +/** + * \brief Enable fast RC oscillator. + * + * \param ul_rc Fast RC oscillator(4/8/12Mhz). + */ +void pmc_osc_enable_fastrc(uint32_t ul_rc) +{ + /* Enable Fast RC oscillator but DO NOT switch to RC */ + PMC->CKGR_MOR |= (CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN); + /* Wait the Fast RC to stabilize */ + while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)); + + /* Change Fast RC oscillator frequency */ + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) | + CKGR_MOR_KEY_PASSWD | ul_rc; + /* Wait the Fast RC to stabilize */ + while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)); +} + +/** + * \brief Disable the internal fast RC. + */ +void pmc_osc_disable_fastrc(void) +{ + /* Disable Fast RC oscillator */ + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN & + ~CKGR_MOR_MOSCRCF_Msk) + | CKGR_MOR_KEY_PASSWD; +} + +/** + * \brief Check if the main fastrc is ready. + * + * \retval 0 Xtal is not ready, otherwise ready. + */ +uint32_t pmc_osc_is_ready_fastrc(void) +{ + return (PMC->PMC_SR & PMC_SR_MOSCRCS); +} + +/** + * \brief Enable main XTAL oscillator. + * + * \param ul_xtal_startup_time Xtal start-up time, in number of slow clocks. + */ +void pmc_osc_enable_main_xtal(uint32_t ul_xtal_startup_time) +{ + uint32_t mor = PMC->CKGR_MOR; + mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN); + mor |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN | + CKGR_MOR_MOSCXTST(ul_xtal_startup_time); + PMC->CKGR_MOR = mor; + /* Wait the main Xtal to stabilize */ + while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)); +} + +/** + * \brief Bypass main XTAL. + */ +void pmc_osc_bypass_main_xtal(void) +{ + uint32_t mor = PMC->CKGR_MOR; + mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN); + mor |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY; + /* Enable Crystal oscillator but DO NOT switch now. Keep MOSCSEL to 0 */ + PMC->CKGR_MOR = mor; + /* The MOSCXTS in PMC_SR is automatically set */ +} + +/** + * \brief Disable the main Xtal. + */ +void pmc_osc_disable_main_xtal(void) +{ + uint32_t mor = PMC->CKGR_MOR; + mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN); + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor; +} + +/** + * \brief Check if the main crystal is bypassed. + * + * \retval 0 Xtal is bypassed, otherwise not. + */ +uint32_t pmc_osc_is_bypassed_main_xtal(void) +{ + return (PMC->CKGR_MOR & CKGR_MOR_MOSCXTBY); +} + +/** + * \brief Check if the main crystal is ready. + * + * \note If main crystal is bypassed, it's always ready. + * + * \retval 0 main crystal is not ready, otherwise ready. + */ +uint32_t pmc_osc_is_ready_main_xtal(void) +{ + return (PMC->PMC_SR & PMC_SR_MOSCXTS); +} + +/** + * \brief Switch main clock source selection to external Xtal/Bypass. + * + * \note The function may switch MCK to SCLK if MCK source is MAINCK to avoid + * any system crash. + * + * \note If used in Xtal mode, the Xtal is automatically enabled. + * + * \param ul_bypass 0 for Xtal, 1 for bypass. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +void pmc_switch_mainck_to_xtal(uint32_t ul_bypass, + uint32_t ul_xtal_startup_time) +{ + /* Enable Main Xtal oscillator */ + if (ul_bypass) { + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) | + CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY | + CKGR_MOR_MOSCSEL; + } else { + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) | + CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN | + CKGR_MOR_MOSCXTST(ul_xtal_startup_time); + /* Wait the Xtal to stabilize */ + while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)); + + PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCSEL; + } +} + +/** + * \brief Disable the external Xtal. + * + * \param ul_bypass 0 for Xtal, 1 for bypass. + */ +void pmc_osc_disable_xtal(uint32_t ul_bypass) +{ + /* Disable xtal oscillator */ + if (ul_bypass) { + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) | + CKGR_MOR_KEY_PASSWD; + } else { + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) | + CKGR_MOR_KEY_PASSWD; + } +} + +/** + * \brief Check if the MAINCK is ready. Depending on MOSCEL, MAINCK can be one + * of Xtal, bypass or internal RC. + * + * \retval 1 Xtal is ready. + * \retval 0 Xtal is not ready. + */ +uint32_t pmc_osc_is_ready_mainck(void) +{ + return PMC->PMC_SR & PMC_SR_MOSCSELS; +} + +/** + * \brief Select Main Crystal or internal RC as main clock source. + * + * \note This function will not enable/disable RC or Main Crystal. + * + * \param ul_xtal_rc 0 internal RC is selected, otherwise Main Crystal. + */ +void pmc_mainck_osc_select(uint32_t ul_xtal_rc) +{ + uint32_t mor = PMC->CKGR_MOR; + if (ul_xtal_rc) { + mor |= CKGR_MOR_MOSCSEL; + } else { + mor &= ~CKGR_MOR_MOSCSEL; + } + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor; +} + +/** + * \brief Enable PLLA clock. + * + * \param mula PLLA multiplier. + * \param pllacount PLLA counter. + * \param diva Divider. + */ +void pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva) +{ + /* first disable the PLL to unlock the lock */ + pmc_disable_pllack(); + +#if (SAM4C || SAM4CM || SAM4CP || SAMG) + PMC->CKGR_PLLAR = CKGR_PLLAR_PLLAEN(diva) | + CKGR_PLLAR_PLLACOUNT(pllacount) | CKGR_PLLAR_MULA(mula); +#else + PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_DIVA(diva) | + CKGR_PLLAR_PLLACOUNT(pllacount) | CKGR_PLLAR_MULA(mula); +#endif + while ((PMC->PMC_SR & PMC_SR_LOCKA) == 0); +} + +/** + * \brief Disable PLLA clock. + */ +void pmc_disable_pllack(void) +{ +#if (SAM4C || SAM4CM || SAM4CP || SAMG) + PMC->CKGR_PLLAR = CKGR_PLLAR_MULA(0); +#else + PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0); +#endif +} + +/** + * \brief Is PLLA locked? + * + * \retval 0 Not locked. + * \retval 1 Locked. + */ +uint32_t pmc_is_locked_pllack(void) +{ + return (PMC->PMC_SR & PMC_SR_LOCKA); +} + +#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55) +/** + * \brief Enable PLLB clock. + * + * \param mulb PLLB multiplier. + * \param pllbcount PLLB counter. + * \param divb Divider. + */ +void pmc_enable_pllbck(uint32_t mulb, uint32_t pllbcount, uint32_t divb) +{ + /* first disable the PLL to unlock the lock */ + pmc_disable_pllbck(); + +#if SAMG55 + PMC->CKGR_PLLAR = CKGR_PLLAR_PLLAEN(divb) | + CKGR_PLLAR_PLLACOUNT(pllbcount) | CKGR_PLLAR_MULA(mulb); +#else + PMC->CKGR_PLLBR = + CKGR_PLLBR_DIVB(divb) | CKGR_PLLBR_PLLBCOUNT(pllbcount) + | CKGR_PLLBR_MULB(mulb); +#endif + while ((PMC->PMC_SR & PMC_SR_LOCKB) == 0); +} + +/** + * \brief Disable PLLB clock. + */ +void pmc_disable_pllbck(void) +{ + PMC->CKGR_PLLBR = CKGR_PLLBR_MULB(0); +} + +/** + * \brief Is PLLB locked? + * + * \retval 0 Not locked. + * \retval 1 Locked. + */ +uint32_t pmc_is_locked_pllbck(void) +{ + return (PMC->PMC_SR & PMC_SR_LOCKB); +} +#endif + +#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Enable UPLL clock. + */ +void pmc_enable_upll_clock(void) +{ + PMC->CKGR_UCKR = CKGR_UCKR_UPLLCOUNT(3) | CKGR_UCKR_UPLLEN; + + /* Wait UTMI PLL Lock Status */ + while (!(PMC->PMC_SR & PMC_SR_LOCKU)); +} + +/** + * \brief Disable UPLL clock. + */ +void pmc_disable_upll_clock(void) +{ + PMC->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN; +} + +/** + * \brief Is UPLL locked? + * + * \retval 0 Not locked. + * \retval 1 Locked. + */ +uint32_t pmc_is_locked_upll(void) +{ + return (PMC->PMC_SR & PMC_SR_LOCKU); +} +#endif + +/** + * \brief Enable the specified peripheral clock. + * + * \note The ID must NOT be shifted (i.e., 1 << ID_xxx). + * + * \param ul_id Peripheral ID (ID_xxx). + * + * \retval 0 Success. + * \retval 1 Invalid parameter. + */ +uint32_t pmc_enable_periph_clk(uint32_t ul_id) +{ + if (ul_id > MAX_PERIPH_ID) { + return 1; + } + + if (ul_id < 32) { + if ((PMC->PMC_PCSR0 & (1u << ul_id)) != (1u << ul_id)) { + PMC->PMC_PCER0 = 1 << ul_id; + } +#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) + } else { + ul_id -= 32; + if ((PMC->PMC_PCSR1 & (1u << ul_id)) != (1u << ul_id)) { + PMC->PMC_PCER1 = 1 << ul_id; + } +#endif + } + + return 0; +} + +/** + * \brief Disable the specified peripheral clock. + * + * \note The ID must NOT be shifted (i.e., 1 << ID_xxx). + * + * \param ul_id Peripheral ID (ID_xxx). + * + * \retval 0 Success. + * \retval 1 Invalid parameter. + */ +uint32_t pmc_disable_periph_clk(uint32_t ul_id) +{ + if (ul_id > MAX_PERIPH_ID) { + return 1; + } + + if (ul_id < 32) { + if ((PMC->PMC_PCSR0 & (1u << ul_id)) == (1u << ul_id)) { + PMC->PMC_PCDR0 = 1 << ul_id; + } +#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 \ + || SAMV70 || SAME70 || SAMS70) + } else { + ul_id -= 32; + if ((PMC->PMC_PCSR1 & (1u << ul_id)) == (1u << ul_id)) { + PMC->PMC_PCDR1 = 1 << ul_id; + } +#endif + } + return 0; +} + +/** + * \brief Enable all peripheral clocks. + */ +void pmc_enable_all_periph_clk(void) +{ + PMC->PMC_PCER0 = PMC_MASK_STATUS0; + while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != PMC_MASK_STATUS0); + +#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \ + || SAMV70 || SAME70 || SAMS70) + PMC->PMC_PCER1 = PMC_MASK_STATUS1; + while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != PMC_MASK_STATUS1); +#endif +} + +/** + * \brief Disable all peripheral clocks. + */ +void pmc_disable_all_periph_clk(void) +{ + PMC->PMC_PCDR0 = PMC_MASK_STATUS0; + while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != 0); + +#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \ + || SAMV70 || SAME70 || SAMS70) + PMC->PMC_PCDR1 = PMC_MASK_STATUS1; + while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != 0); +#endif +} + +/** + * \brief Check if the specified peripheral clock is enabled. + * + * \note The ID must NOT be shifted (i.e., 1 << ID_xxx). + * + * \param ul_id Peripheral ID (ID_xxx). + * + * \retval 0 Peripheral clock is disabled or unknown. + * \retval 1 Peripheral clock is enabled. + */ +uint32_t pmc_is_periph_clk_enabled(uint32_t ul_id) +{ + if (ul_id > MAX_PERIPH_ID) { + return 0; + } + +#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \ + || SAMV70 || SAME70 || SAMS70) + if (ul_id < 32) { +#endif + if ((PMC->PMC_PCSR0 & (1u << ul_id))) { + return 1; + } else { + return 0; + } +#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \ + || SAMV70 || SAME70 || SAMS70) + } else { + ul_id -= 32; + if ((PMC->PMC_PCSR1 & (1u << ul_id))) { + return 1; + } else { + return 0; + } + } +#endif +} + +/** + * \brief Set the prescaler for the specified programmable clock. + * + * \param ul_id Peripheral ID. + * \param ul_pres Prescaler value. + */ +void pmc_pck_set_prescaler(uint32_t ul_id, uint32_t ul_pres) +{ + PMC->PMC_PCK[ul_id] = + (PMC->PMC_PCK[ul_id] & ~PMC_PCK_PRES_Msk) | ul_pres; + while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id)) + && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id))); +} + +/** + * \brief Set the source oscillator for the specified programmable clock. + * + * \param ul_id Peripheral ID. + * \param ul_source Source selection value. + */ +void pmc_pck_set_source(uint32_t ul_id, uint32_t ul_source) +{ + PMC->PMC_PCK[ul_id] = + (PMC->PMC_PCK[ul_id] & ~PMC_PCK_CSS_Msk) | ul_source; + while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id)) + && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id))); +} + +/** + * \brief Switch programmable clock source selection to slow clock. + * + * \param ul_id Id of the programmable clock. + * \param ul_pres Programmable clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_pck_to_sclk(uint32_t ul_id, uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_SLOW_CLK | ul_pres; + for (ul_timeout = PMC_TIMEOUT; + !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} + +/** + * \brief Switch programmable clock source selection to main clock. + * + * \param ul_id Id of the programmable clock. + * \param ul_pres Programmable clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_pck_to_mainck(uint32_t ul_id, uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_MAIN_CLK | ul_pres; + for (ul_timeout = PMC_TIMEOUT; + !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} + +/** + * \brief Switch programmable clock source selection to PLLA clock. + * + * \param ul_id Id of the programmable clock. + * \param ul_pres Programmable clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_pck_to_pllack(uint32_t ul_id, uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLA_CLK | ul_pres; + for (ul_timeout = PMC_TIMEOUT; + !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} + +#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55) +/** + * \brief Switch programmable clock source selection to PLLB clock. + * + * \param ul_id Id of the programmable clock. + * \param ul_pres Programmable clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_pck_to_pllbck(uint32_t ul_id, uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLB_CLK | ul_pres; + for (ul_timeout = PMC_TIMEOUT; + !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} +#endif + +#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Switch programmable clock source selection to UPLL clock. + * + * \param ul_id Id of the programmable clock. + * \param ul_pres Programmable clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_pck_to_upllck(uint32_t ul_id, uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_UPLL_CLK | ul_pres; + for (ul_timeout = PMC_TIMEOUT; + !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} +#endif + +/** + * \brief Switch programmable clock source selection to mck. + * + * \param ul_id Id of the programmable clock. + * \param ul_pres Programmable clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_pck_to_mck(uint32_t ul_id, uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_MCK | ul_pres; + for (ul_timeout = PMC_TIMEOUT; + !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} + +/** + * \brief Enable the specified programmable clock. + * + * \param ul_id Id of the programmable clock. + */ +void pmc_enable_pck(uint32_t ul_id) +{ + PMC->PMC_SCER = PMC_SCER_PCK0 << ul_id; +} + +/** + * \brief Disable the specified programmable clock. + * + * \param ul_id Id of the programmable clock. + */ +void pmc_disable_pck(uint32_t ul_id) +{ + PMC->PMC_SCDR = PMC_SCER_PCK0 << ul_id; +} + +/** + * \brief Enable all programmable clocks. + */ +void pmc_enable_all_pck(void) +{ + PMC->PMC_SCER = PMC_SCER_PCK0 | PMC_SCER_PCK1 | PMC_SCER_PCK2; +} + +/** + * \brief Disable all programmable clocks. + */ +void pmc_disable_all_pck(void) +{ + PMC->PMC_SCDR = PMC_SCDR_PCK0 | PMC_SCDR_PCK1 | PMC_SCDR_PCK2; +} + +/** + * \brief Check if the specified programmable clock is enabled. + * + * \param ul_id Id of the programmable clock. + * + * \retval 0 Programmable clock is disabled or unknown. + * \retval 1 Programmable clock is enabled. + */ +uint32_t pmc_is_pck_enabled(uint32_t ul_id) +{ + if (ul_id > 2) { + return 0; + } + + return (PMC->PMC_SCSR & (PMC_SCSR_PCK0 << ul_id)); +} + +#if (SAM4C || SAM4CM || SAM4CP) +/** + * \brief Enable Coprocessor Clocks. + */ +void pmc_enable_cpck(void) +{ + PMC->PMC_SCER = PMC_SCER_CPCK | PMC_SCER_CPKEY_PASSWD; +} + +/** + * \brief Disable Coprocessor Clocks. + */ +void pmc_disable_cpck(void) +{ + PMC->PMC_SCDR = PMC_SCDR_CPCK | PMC_SCDR_CPKEY_PASSWD; +} + +/** + * \brief Check if the Coprocessor Clocks is enabled. + * + * \retval 0 Coprocessor Clocks is disabled. + * \retval 1 Coprocessor Clocks is enabled. + */ +bool pmc_is_cpck_enabled(void) +{ + if(PMC->PMC_SCSR & PMC_SCSR_CPCK) { + return 1; + } else { + return 0; + } +} + +/** + * \brief Enable Coprocessor Bus Master Clocks. + */ +void pmc_enable_cpbmck(void) +{ + PMC->PMC_SCER = PMC_SCER_CPCK | PMC_SCER_CPKEY_PASSWD; +} + +/** + * \brief Disable Coprocessor Bus Master Clocks. + */ +void pmc_disable_cpbmck(void) +{ + PMC->PMC_SCDR = PMC_SCDR_CPCK | PMC_SCDR_CPKEY_PASSWD; +} + +/** + * \brief Check if the Coprocessor Bus Master Clocks is enabled. + * + * \retval 0 Coprocessor Bus Master Clocks is disabled. + * \retval 1 Coprocessor Bus Master Clocks is enabled. + */ +bool pmc_is_cpbmck_enabled(void) +{ + if(PMC->PMC_SCSR & PMC_SCSR_CPBMCK) { + return 1; + } else { + return 0; + } +} + +/** + * \brief Set the prescaler for the Coprocessor Master Clock. + * + * \param ul_pres Prescaler value. + */ +void pmc_cpck_set_prescaler(uint32_t ul_pres) +{ + PMC->PMC_MCKR = + (PMC->PMC_MCKR & (~PMC_MCKR_CPPRES_Msk)) | PMC_MCKR_CPPRES(ul_pres); +} + +/** + * \brief Set the source for the Coprocessor Master Clock. + * + * \param ul_source Source selection value. + */ +void pmc_cpck_set_source(uint32_t ul_source) +{ + PMC->PMC_MCKR = + (PMC->PMC_MCKR & (~PMC_MCKR_CPCSS_Msk)) | ul_source; +} +#endif + +#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Switch UDP (USB) clock source selection to PLLA clock. + * + * \param ul_usbdiv Clock divisor. + */ +void pmc_switch_udpck_to_pllack(uint32_t ul_usbdiv) +{ + PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv); +} +#endif + +#if (SAM3S || SAM4S || SAMG55) +/** + * \brief Switch UDP (USB) clock source selection to PLLB clock. + * + * \param ul_usbdiv Clock divisor. + */ +void pmc_switch_udpck_to_pllbck(uint32_t ul_usbdiv) +{ + PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv) | PMC_USB_USBS; +} +#endif + +#if (SAM3XA || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Switch UDP (USB) clock source selection to UPLL clock. + * + * \param ul_usbdiv Clock divisor. + */ +void pmc_switch_udpck_to_upllck(uint32_t ul_usbdiv) +{ + PMC->PMC_USB = PMC_USB_USBS | PMC_USB_USBDIV(ul_usbdiv); +} +#endif + +#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Enable UDP (USB) clock. + */ +void pmc_enable_udpck(void) +{ +#if (SAM3S || SAM4S || SAM4E || SAMG55) + PMC->PMC_SCER = PMC_SCER_UDP; +#elif (SAMV71 || SAMV70 || SAME70 || SAMS70) + PMC->PMC_SCER = PMC_SCER_USBCLK; +#else + PMC->PMC_SCER = PMC_SCER_UOTGCLK; +# endif +} + +/** + * \brief Disable UDP (USB) clock. + */ +void pmc_disable_udpck(void) +{ +#if (SAM3S || SAM4S || SAM4E || SAMG55) + PMC->PMC_SCDR = PMC_SCDR_UDP; +#elif (SAMV71 || SAMV70 || SAME70 || SAMS70) + PMC->PMC_SCDR = PMC_SCDR_USBCLK; +#else + PMC->PMC_SCDR = PMC_SCDR_UOTGCLK; +# endif +} +#endif + +#if SAMG55 +/** + * \brief Switch UHP (USB) clock source selection to PLLA clock. + * + * \param ul_usbdiv Clock divisor. + */ +void pmc_switch_uhpck_to_pllack(uint32_t ul_usbdiv) +{ + PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv); +} + +/** + * \brief Switch UHP (USB) clock source selection to PLLB clock. + * + * \param ul_usbdiv Clock divisor. + */ +void pmc_switch_uhpck_to_pllbck(uint32_t ul_usbdiv) +{ + PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv) | PMC_USB_USBS; +} + +/** + * \brief Enable UHP (USB) clock. + */ +void pmc_enable_uhpck(void) +{ + PMC->PMC_SCER = PMC_SCER_UHP; +} +#endif + +/** + * \brief Enable PMC interrupts. + * + * \param ul_sources Interrupt sources bit map. + */ +void pmc_enable_interrupt(uint32_t ul_sources) +{ + PMC->PMC_IER = ul_sources; +} + +/** + * \brief Disable PMC interrupts. + * + * \param ul_sources Interrupt sources bit map. + */ +void pmc_disable_interrupt(uint32_t ul_sources) +{ + PMC->PMC_IDR = ul_sources; +} + +/** + * \brief Get PMC interrupt mask. + * + * \return The interrupt mask value. + */ +uint32_t pmc_get_interrupt_mask(void) +{ + return PMC->PMC_IMR; +} + +/** + * \brief Get current status. + * + * \return The current PMC status. + */ +uint32_t pmc_get_status(void) +{ + return PMC->PMC_SR; +} + +/** + * \brief Set the wake-up inputs for fast startup mode registers + * (event generation). + * + * \param ul_inputs Wake up inputs to enable. + */ +void pmc_set_fast_startup_input(uint32_t ul_inputs) +{ + ul_inputs &= PMC_FAST_STARTUP_Msk; + PMC->PMC_FSMR |= ul_inputs; +} + +/** + * \brief Clear the wake-up inputs for fast startup mode registers + * (remove event generation). + * + * \param ul_inputs Wake up inputs to disable. + */ +void pmc_clr_fast_startup_input(uint32_t ul_inputs) +{ + ul_inputs &= PMC_FAST_STARTUP_Msk; + PMC->PMC_FSMR &= ~ul_inputs; +} + +#if (SAM4C || SAM4CM || SAM4CP) +/** + * \brief Set the wake-up inputs of coprocessor for fast startup mode registers + * (event generation). + * + * \param ul_inputs Wake up inputs to enable. + */ +void pmc_cp_set_fast_startup_input(uint32_t ul_inputs) +{ + ul_inputs &= PMC_FAST_STARTUP_Msk; + PMC->PMC_CPFSMR |= ul_inputs; +} + +/** + * \brief Clear the wake-up inputs of coprocessor for fast startup mode registers + * (remove event generation). + * + * \param ul_inputs Wake up inputs to disable. + */ +void pmc_cp_clr_fast_startup_input(uint32_t ul_inputs) +{ + ul_inputs &= PMC_FAST_STARTUP_Msk; + PMC->PMC_CPFSMR &= ~ul_inputs; +} +#endif + +#if (!(SAMG51 || SAMG53 || SAMG54)) +/** + * \brief Enable Sleep Mode. + * Enter condition: (WFE or WFI) + (SLEEPDEEP bit = 0) + (LPM bit = 0) + * + * \param uc_type 0 for wait for interrupt, 1 for wait for event. + * \note For SAM4S, SAM4C, SAM4CM, SAM4CP, SAMV71 and SAM4E series, + * since only WFI is effective, uc_type = 1 will be treated as uc_type = 0. + */ +void pmc_enable_sleepmode(uint8_t uc_type) +{ +#if !(SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70) + PMC->PMC_FSMR &= (uint32_t) ~ PMC_FSMR_LPM; // Enter Sleep mode +#endif + SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; // Deep sleep + +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70) + UNUSED(uc_type); + __WFI(); +#else + if (uc_type == 0) { + __WFI(); + } else { + __WFE(); + } +#endif +} +#endif + +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70) +static uint32_t ul_flash_in_wait_mode = PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN; +/** + * \brief Set the embedded flash state in wait mode + * + * \param ul_flash_state PMC_WAIT_MODE_FLASH_STANDBY flash in standby mode, + * PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN flash in deep power down mode. + */ +void pmc_set_flash_in_wait_mode(uint32_t ul_flash_state) +{ + ul_flash_in_wait_mode = ul_flash_state; +} + +/** + * \brief Enable Wait Mode. Enter condition: (WAITMODE bit = 1) + FLPM + * + * \note In this function, FLPM will retain, WAITMODE bit will be set, + * Generally, this function will be called by pmc_sleep() in order to + * complete all sequence entering wait mode. + * See \ref pmc_sleep() for entering different sleep modes. + */ +void pmc_enable_waitmode(void) +{ + uint32_t i; + + /* Flash in wait mode */ + i = PMC->PMC_FSMR; + i &= ~PMC_FSMR_FLPM_Msk; +#if !(SAMV71 || SAMV70 || SAME70 || SAMS70) + i |= ul_flash_in_wait_mode; +#else + i |= PMC_WAIT_MODE_FLASH_IDLE; +#endif + PMC->PMC_FSMR = i; + + /* Set the WAITMODE bit = 1 */ + PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_WAITMODE; + + /* Waiting for Master Clock Ready MCKRDY = 1 */ + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); + + /* Waiting for MOSCRCEN bit cleared is strongly recommended + * to ensure that the core will not execute undesired instructions + */ + for (i = 0; i < 500; i++) { + __NOP(); + } + while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN)); + +#if (!SAMG) + /* Restore Flash in idle mode */ + i = PMC->PMC_FSMR; + i &= ~PMC_FSMR_FLPM_Msk; + i |= PMC_WAIT_MODE_FLASH_IDLE; + PMC->PMC_FSMR = i; +#endif +} +#else +/** + * \brief Enable Wait Mode. Enter condition: WFE + (SLEEPDEEP bit = 0) + + * (LPM bit = 1) + */ +void pmc_enable_waitmode(void) +{ + uint32_t i; + + PMC->PMC_FSMR |= PMC_FSMR_LPM; /* Enter Wait mode */ + SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; /* Deep sleep */ + + __WFE(); + + /* Waiting for MOSCRCEN bit cleared is strongly recommended + * to ensure that the core will not execute undesired instructions + */ + for (i = 0; i < 500; i++) { + __NOP(); + } + while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN)); + +} +#endif + +#if (!(SAMG51 || SAMG53 || SAMG54)) +/** + * \brief Enable Backup Mode. Enter condition: WFE/(VROFF bit = 1) + + * (SLEEPDEEP bit = 1) + */ +void pmc_enable_backupmode(void) +{ +#if (SAM4C || SAM4CM || SAM4CP) + uint32_t tmp = SUPC->SUPC_MR & ~(SUPC_MR_BUPPOREN | SUPC_MR_KEY_Msk); + SUPC->SUPC_MR = tmp | SUPC_MR_KEY_PASSWD; + while (SUPC->SUPC_SR & SUPC_SR_BUPPORS); +#endif + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) + SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_VROFF_STOP_VREG; + __WFE(); + __WFI(); +#else + __WFE(); +#endif +} +#endif + +/** + * \brief Enable Clock Failure Detector. + */ +void pmc_enable_clock_failure_detector(void) +{ + uint32_t ul_reg = PMC->CKGR_MOR; + + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | CKGR_MOR_CFDEN | ul_reg; +} + +/** + * \brief Disable Clock Failure Detector. + */ +void pmc_disable_clock_failure_detector(void) +{ + uint32_t ul_reg = PMC->CKGR_MOR & (~CKGR_MOR_CFDEN); + + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | ul_reg; +} + +#if (SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Enable Slow Crystal Oscillator Frequency Monitoring. + */ +void pmc_enable_sclk_osc_freq_monitor(void) +{ + uint32_t ul_reg = PMC->CKGR_MOR; + + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | CKGR_MOR_XT32KFME | ul_reg; +} + +/** + * \brief Disable Slow Crystal Oscillator Frequency Monitoring. + */ +void pmc_disable_sclk_osc_freq_monitor(void) +{ + uint32_t ul_reg = PMC->CKGR_MOR & (~CKGR_MOR_XT32KFME); + + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | ul_reg; +} +#endif + +/** + * \brief Enable or disable write protect of PMC registers. + * + * \param ul_enable 1 to enable, 0 to disable. + */ +void pmc_set_writeprotect(uint32_t ul_enable) +{ + if (ul_enable) { + PMC->PMC_WPMR = PMC_WPMR_WPKEY_PASSWD | PMC_WPMR_WPEN; + } else { + PMC->PMC_WPMR = PMC_WPMR_WPKEY_PASSWD; + } +} + +/** + * \brief Return write protect status. + * + * \return Return write protect status. + */ +uint32_t pmc_get_writeprotect_status(void) +{ + return PMC->PMC_WPSR; +} + +#if (SAMG53 || SAMG54 || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Enable the specified peripheral clock. + * + * \note The ID must NOT be shifted (i.e., 1 << ID_xxx). + * + * \param ul_id Peripheral ID (ID_xxx). + * + * \retval 0 Success. + * \retval 1 Fail. + */ +uint32_t pmc_enable_sleepwalking(uint32_t ul_id) +{ + uint32_t temp; +#if (SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) + if ((7 <= ul_id) && (ul_id<= 29)) { +#else + if ((8 <= ul_id) && (ul_id<= 29)) { +#endif + temp = pmc_get_active_status0(); + if (temp & (1 << ul_id)) { + return 1; + } + PMC->PMC_SLPWK_ER0 = 1 << ul_id; + temp = pmc_get_active_status0(); + if (temp & (1 << ul_id)) { + pmc_disable_sleepwalking(ul_id); + return 1; + } + return 0; + } +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) + else if ((32 <= ul_id) && (ul_id<= 60)) { + ul_id -= 32; + temp = pmc_get_active_status1(); + if (temp & (1 << ul_id)) { + return 1; + } + PMC->PMC_SLPWK_ER1 = 1 << ul_id; + temp = pmc_get_active_status1(); + if (temp & (1 << ul_id)) { + pmc_disable_sleepwalking(ul_id); + return 1; + } + return 0; + } +#endif + else { + return 1; + } +} + +/** + * \brief Disable the sleepwalking of specified peripheral. + * + * \note The ID must NOT be shifted (i.e., 1 << ID_xxx). + * + * \param ul_id Peripheral ID (ID_xxx). + * + * \retval 0 Success. + * \retval 1 Invalid parameter. + */ +uint32_t pmc_disable_sleepwalking(uint32_t ul_id) +{ +#if (SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) + if ((7 <= ul_id) && (ul_id<= 29)) { +#else + if ((8 <= ul_id) && (ul_id<= 29)) { +#endif + PMC->PMC_SLPWK_DR0 = 1 << ul_id; + return 0; + } +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) + else if ((32 <= ul_id) && (ul_id<= 60)) { + ul_id -= 32; + PMC->PMC_SLPWK_DR1 = 1 << ul_id; + return 0; + } +#endif + else { + return 1; + } +} + +/** + * \brief Return peripheral sleepwalking enable status. + * + * \return the status register value. + */ +uint32_t pmc_get_sleepwalking_status0(void) +{ + return PMC->PMC_SLPWK_SR0; +} + +/** + * \brief Return peripheral active status. + * + * \return the status register value. + */ +uint32_t pmc_get_active_status0(void) +{ + return PMC->PMC_SLPWK_ASR0; +} + +#endif + +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Return peripheral sleepwalking enable status. + * + * \return the status register value. + */ +uint32_t pmc_get_sleepwalking_status1(void) +{ + return PMC->PMC_SLPWK_SR1; +} + +/** + * \brief Return peripheral active status. + * + * \return the status register value. + */ +uint32_t pmc_get_active_status1(void) +{ + return PMC->PMC_SLPWK_ASR1; +} +#endif + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/pmc/pmc.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/pmc/pmc.h new file mode 100644 index 0000000..e49506d --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/pmc/pmc.h @@ -0,0 +1,550 @@ +/** + * \file + * + * \brief Power Management Controller (PMC) driver for SAM. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef PMC_H_INCLUDED +#define PMC_H_INCLUDED + +#include "compiler.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** Bit mask for peripheral clocks (PCER0) */ +#define PMC_MASK_STATUS0 (0xFFFFFFFC) + +/** Bit mask for peripheral clocks (PCER1) */ +#define PMC_MASK_STATUS1 (0xFFFFFFFF) + +/** Loop counter timeout value */ +#if !(SAME70) +#define PMC_TIMEOUT (2048) +#else +#define PMC_TIMEOUT (4096) +#endif + +/** Key to unlock CKGR_MOR register */ +#ifndef CKGR_MOR_KEY_PASSWD +#define CKGR_MOR_KEY_PASSWD CKGR_MOR_KEY(0x37U) +#endif + +/** Key used to write SUPC registers */ +#ifndef SUPC_CR_KEY_PASSWD +#define SUPC_CR_KEY_PASSWD SUPC_CR_KEY(0xA5U) +#endif + +#ifndef SUPC_MR_KEY_PASSWD +#define SUPC_MR_KEY_PASSWD SUPC_MR_KEY(0xA5U) +#endif + +/** Mask to access fast startup input */ +#define PMC_FAST_STARTUP_Msk (0x7FFFFu) + +/** PMC_WPMR Write Protect KEY, unlock it */ +#ifndef PMC_WPMR_WPKEY_PASSWD +#define PMC_WPMR_WPKEY_PASSWD PMC_WPMR_WPKEY((uint32_t) 0x504D43) +#endif + +/** Using external oscillator */ +#define PMC_OSC_XTAL 0 + +/** Oscillator in bypass mode */ +#define PMC_OSC_BYPASS 1 + +#define PMC_PCK_0 0 /* PCK0 ID */ +#define PMC_PCK_1 1 /* PCK1 ID */ +#define PMC_PCK_2 2 /* PCK2 ID */ +#if SAMG55 +#define PMC_PCK_3 3 /* PCK3 ID */ +#define PMC_PCK_4 4 /* PCK4 ID */ +#define PMC_PCK_5 5 /* PCK5 ID */ +#define PMC_PCK_6 6 /* PCK6 ID */ +#define PMC_PCK_7 7 /* PCK7 ID */ +#endif + +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** Flash state in Wait Mode */ +#define PMC_WAIT_MODE_FLASH_STANDBY PMC_FSMR_FLPM_FLASH_STANDBY +#define PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN +#define PMC_WAIT_MODE_FLASH_IDLE PMC_FSMR_FLPM_FLASH_IDLE +#endif + +/** Convert startup time from us to MOSCXTST */ +#define pmc_us_to_moscxtst(startup_us, slowck_freq) \ + ((startup_us * slowck_freq / 8 / 1000000) < 0x100 ? \ + (startup_us * slowck_freq / 8 / 1000000) : 0xFF) + +/** + * \name Master clock (MCK) Source and Prescaler configuration + * + * \note The following functions may be used to select the clock source and + * prescaler for the master clock. + */ +//@{ + +void pmc_mck_set_prescaler(uint32_t ul_pres); +#if SAMV71 || SAMV70 || SAME70 || SAMS70 +void pmc_mck_set_division(uint32_t ul_div); +#endif +void pmc_mck_set_source(uint32_t ul_source); +uint32_t pmc_switch_mck_to_sclk(uint32_t ul_pres); +uint32_t pmc_switch_mck_to_mainck(uint32_t ul_pres); +uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres); +#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55) +uint32_t pmc_switch_mck_to_pllbck(uint32_t ul_pres); +#endif +#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70) +uint32_t pmc_switch_mck_to_upllck(uint32_t ul_pres); +#endif +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70) +void pmc_set_flash_in_wait_mode(uint32_t ul_flash_state); +#endif + + +//@} + +/** + * \name Slow clock (SLCK) oscillator and configuration + * + */ +//@{ + +void pmc_switch_sclk_to_32kxtal(uint32_t ul_bypass); +uint32_t pmc_osc_is_ready_32kxtal(void); + +//@} + +/** + * \name Main Clock (MAINCK) oscillator and configuration + * + */ +//@{ + +void pmc_switch_mainck_to_fastrc(uint32_t ul_moscrcf); +void pmc_osc_enable_fastrc(uint32_t ul_rc); +void pmc_osc_disable_fastrc(void); +uint32_t pmc_osc_is_ready_fastrc(void); +void pmc_osc_enable_main_xtal(uint32_t ul_xtal_startup_time); +void pmc_osc_bypass_main_xtal(void); +void pmc_osc_disable_main_xtal(void); +uint32_t pmc_osc_is_bypassed_main_xtal(void); +uint32_t pmc_osc_is_ready_main_xtal(void); +void pmc_switch_mainck_to_xtal(uint32_t ul_bypass, + uint32_t ul_xtal_startup_time); +void pmc_osc_disable_xtal(uint32_t ul_bypass); +uint32_t pmc_osc_is_ready_mainck(void); +void pmc_mainck_osc_select(uint32_t ul_xtal_rc); + +//@} + +/** + * \name PLL oscillator and configuration + * + */ +//@{ + +void pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva); +void pmc_disable_pllack(void); +uint32_t pmc_is_locked_pllack(void); + +#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55) +void pmc_enable_pllbck(uint32_t mulb, uint32_t pllbcount, uint32_t divb); +void pmc_disable_pllbck(void); +uint32_t pmc_is_locked_pllbck(void); +#endif + +#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70) +void pmc_enable_upll_clock(void); +void pmc_disable_upll_clock(void); +uint32_t pmc_is_locked_upll(void); +#endif + +//@} + +/** + * \name Peripherals clock configuration + * + */ +//@{ + +uint32_t pmc_enable_periph_clk(uint32_t ul_id); +uint32_t pmc_disable_periph_clk(uint32_t ul_id); +void pmc_enable_all_periph_clk(void); +void pmc_disable_all_periph_clk(void); +uint32_t pmc_is_periph_clk_enabled(uint32_t ul_id); + +//@} + +/** + * \name Programmable clock Source and Prescaler configuration + * + * The following functions may be used to select the clock source and + * prescaler for the specified programmable clock. + */ +//@{ + +void pmc_pck_set_prescaler(uint32_t ul_id, uint32_t ul_pres); +void pmc_pck_set_source(uint32_t ul_id, uint32_t ul_source); +uint32_t pmc_switch_pck_to_sclk(uint32_t ul_id, uint32_t ul_pres); +uint32_t pmc_switch_pck_to_mainck(uint32_t ul_id, uint32_t ul_pres); +uint32_t pmc_switch_pck_to_pllack(uint32_t ul_id, uint32_t ul_pres); +#if (SAM4C || SAM4CM || SAM4CP) +void pmc_enable_cpck(void); +void pmc_disable_cpck(void); +bool pmc_is_cpck_enabled(void); +void pmc_enable_cpbmck(void); +void pmc_disable_cpbmck(void); +bool pmc_is_cpbmck_enabled(void); +void pmc_cpck_set_prescaler(uint32_t ul_pres); +void pmc_cpck_set_source(uint32_t ul_source); +#endif +#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55) +uint32_t pmc_switch_pck_to_pllbck(uint32_t ul_id, uint32_t ul_pres); +#endif +#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70) +uint32_t pmc_switch_pck_to_upllck(uint32_t ul_id, uint32_t ul_pres); +#endif +uint32_t pmc_switch_pck_to_mck(uint32_t ul_id, uint32_t ul_pres); +void pmc_enable_pck(uint32_t ul_id); +void pmc_disable_pck(uint32_t ul_id); +void pmc_enable_all_pck(void); +void pmc_disable_all_pck(void); +uint32_t pmc_is_pck_enabled(uint32_t ul_id); + +//@} + +/** + * \name USB clock configuration + * + */ +//@{ + +#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) +void pmc_switch_udpck_to_pllack(uint32_t ul_usbdiv); +#endif +#if (SAM3S || SAM4S || SAMG55) +void pmc_switch_udpck_to_pllbck(uint32_t ul_usbdiv); +#endif +#if (SAM3XA || SAMV71 || SAMV70 || SAME70 || SAMS70) +void pmc_switch_udpck_to_upllck(uint32_t ul_usbdiv); +#endif +#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) +void pmc_enable_udpck(void); +void pmc_disable_udpck(void); +#endif +#if SAMG55 +void pmc_switch_uhpck_to_pllack(uint32_t ul_usbdiv); +void pmc_switch_uhpck_to_pllbck(uint32_t ul_usbdiv); +void pmc_enable_uhpck(void); +#endif + +//@} + +/** + * \name Interrupt and status management + * + */ +//@{ + +void pmc_enable_interrupt(uint32_t ul_sources); +void pmc_disable_interrupt(uint32_t ul_sources); +uint32_t pmc_get_interrupt_mask(void); +uint32_t pmc_get_status(void); + +//@} + +/** + * \name Power management + * + * The following functions are used to configure sleep mode and additional + * wake up inputs. + */ +//@{ + +void pmc_set_fast_startup_input(uint32_t ul_inputs); +void pmc_clr_fast_startup_input(uint32_t ul_inputs); +#if (SAM4C || SAM4CM || SAM4CP) +void pmc_cp_set_fast_startup_input(uint32_t ul_inputs); +void pmc_cp_clr_fast_startup_input(uint32_t ul_inputs); +#endif +#if (!(SAMG51 || SAMG53 || SAMG54)) +void pmc_enable_sleepmode(uint8_t uc_type); +#endif +void pmc_enable_waitmode(void); +#if (!(SAMG51 || SAMG53 || SAMG54)) +void pmc_enable_backupmode(void); +#endif +//@} + +/** + * \name Failure detector + * + */ +//@{ + +void pmc_enable_clock_failure_detector(void); +void pmc_disable_clock_failure_detector(void); + +//@} + +#if (SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \name Slow Crystal Oscillator Frequency Monitoring + * + */ +//@{ + +void pmc_enable_sclk_osc_freq_monitor(void); +void pmc_disable_sclk_osc_freq_monitor(void); + +//@} +#endif + +/** + * \name Write protection + * + */ +//@{ + +void pmc_set_writeprotect(uint32_t ul_enable); +uint32_t pmc_get_writeprotect_status(void); + +//@} + +#if (SAMG53 || SAMG54 || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \name Sleepwalking configuration + * + */ +//@{ + +uint32_t pmc_enable_sleepwalking(uint32_t ul_id); +uint32_t pmc_disable_sleepwalking(uint32_t ul_id); +uint32_t pmc_get_sleepwalking_status0(void); +uint32_t pmc_get_active_status0(void); +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) +uint32_t pmc_get_sleepwalking_status1(void); +uint32_t pmc_get_active_status1(void); +#endif +//@} +#endif + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +//! @} + +/** + * \page sam_pmc_quickstart Quick start guide for the SAM PMC module + * + * This is the quick start guide for the \ref sam_drivers_pmc_group "PMC module", + * with step-by-step instructions on how to configure and use the driver in a + * selection of use cases. + * + * The use cases contain several code fragments. The code fragments in the + * steps for setup can be copied into a custom initialization function, while + * the steps for usage can be copied into, e.g., the main application function. + * + * \section pmc_use_cases PMC use cases + * - \ref pmc_basic_use_case Basic use case - Switch Main Clock sources + * - \ref pmc_use_case_2 Advanced use case - Configure Programmable Clocks + * + * \section pmc_basic_use_case Basic use case - Switch Main Clock sources + * In this use case, the PMC module is configured for a variety of system clock + * sources and speeds. A LED is used to visually indicate the current clock + * speed as the source is switched. + * + * \section pmc_basic_use_case_setup Setup + * + * \subsection pmc_basic_use_case_setup_prereq Prerequisites + * -# \ref gpio_group "General Purpose I/O Management (gpio)" + * + * \subsection pmc_basic_use_case_setup_code Code + * The following function needs to be added to the user application, to flash a + * board LED a variable number of times at a rate given in CPU ticks. + * + * \code + #define FLASH_TICK_COUNT 0x00012345 + + void flash_led(uint32_t tick_count, uint8_t flash_count) + { + SysTick->CTRL = SysTick_CTRL_ENABLE_Msk; + SysTick->LOAD = tick_count; + + while (flash_count--) + { + gpio_toggle_pin(LED0_GPIO); + while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)); + gpio_toggle_pin(LED0_GPIO); + while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)); + } + } +\endcode + * + * \section pmc_basic_use_case_usage Use case + * + * \subsection pmc_basic_use_case_usage_code Example code + * Add to application C-file: + * \code + for (;;) + { + pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz); + flash_led(FLASH_TICK_COUNT, 5); + pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz); + flash_led(FLASH_TICK_COUNT, 5); + pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz); + flash_led(FLASH_TICK_COUNT, 5); + pmc_switch_mainck_to_xtal(0); + flash_led(FLASH_TICK_COUNT, 5); + } +\endcode + * + * \subsection pmc_basic_use_case_usage_flow Workflow + * -# Wrap the code in an infinite loop: + * \code + for (;;) +\endcode + * -# Switch the Master CPU frequency to the internal 12MHz RC oscillator, flash + * a LED on the board several times: + * \code + pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz); + flash_led(FLASH_TICK_COUNT, 5); +\endcode + * -# Switch the Master CPU frequency to the internal 8MHz RC oscillator, flash + * a LED on the board several times: + * \code + pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz); + flash_led(FLASH_TICK_COUNT, 5); +\endcode + * -# Switch the Master CPU frequency to the internal 4MHz RC oscillator, flash + * a LED on the board several times: + * \code + pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz); + flash_led(FLASH_TICK_COUNT, 5); +\endcode + * -# Switch the Master CPU frequency to the external crystal oscillator, flash + * a LED on the board several times: + * \code + pmc_switch_mainck_to_xtal(0, BOARD_OSC_STARTUP_US); + flash_led(FLASH_TICK_COUNT, 5); +\endcode + * + * \section pmc_use_case_2 Use case #2 - Configure Programmable Clocks + * In this use case, the PMC module is configured to start the Slow Clock from + * an attached 32KHz crystal, and start one of the Programmable Clock modules + * sourced from the Slow Clock divided down with a prescale factor of 64. + * + * \section pmc_use_case_2_setup Setup + * + * \subsection pmc_use_case_2_setup_prereq Prerequisites + * -# \ref pio_group "Parallel Input/Output Controller (pio)" + * + * \subsection pmc_use_case_2_setup_code Code + * The following code must be added to the user application: + * \code + pio_set_peripheral(PIOA, PIO_PERIPH_B, PIO_PA17); +\endcode + * + * \subsection pmc_use_case_2_setup_code_workflow Workflow + * -# Configure the PCK1 pin to output on a specific port pin (in this case, + * PIOA pin 17) of the microcontroller. + * \code + pio_set_peripheral(PIOA, PIO_PERIPH_B, PIO_PA17); +\endcode + * \note The peripheral selection and pin will vary according to your selected + * SAM device model. Refer to the "Peripheral Signal Multiplexing on I/O + * Lines" of your device's datasheet. + * + * \section pmc_use_case_2_usage Use case + * The generated PCK1 clock output can be viewed on an oscilloscope attached to + * the correct pin of the microcontroller. + * + * \subsection pmc_use_case_2_usage_code Example code + * Add to application C-file: + * \code + pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL); + pmc_switch_pck_to_sclk(PMC_PCK_1, PMC_PCK_PRES_CLK_64); + pmc_enable_pck(PMC_PCK_1); + + for (;;) + { + // Do Nothing + } +\endcode + * + * \subsection pmc_use_case_2_usage_flow Workflow + * -# Switch the Slow Clock source input to an external 32KHz crystal: + * \code + pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL); +\endcode + * -# Switch the Programmable Clock module PCK1 source clock to the Slow Clock, + * with a prescaler of 64: + * \code + pmc_switch_pck_to_sclk(PMC_PCK_1, PMC_PCK_PRES_CLK_64); +\endcode + * -# Enable Programmable Clock module PCK1: + * \code + pmc_enable_pck(PMC_PCK_1); +\endcode + * -# Enter an infinite loop: + * \code + for (;;) + { + // Do Nothing + } +\endcode + */ + +#endif /* PMC_H_INCLUDED */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/pmc/sleep.c b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/pmc/sleep.c new file mode 100644 index 0000000..0a971da --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/pmc/sleep.c @@ -0,0 +1,389 @@ +/** + * \file + * + * \brief Sleep mode access + * + * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#include +#include "sleep.h" + +/* SAM3,SAM4,SAMG,SAMV,SAMS and SAME series */ +#if (SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S || SAM4E || SAM4N || SAM4C || \ + SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAMS70 || SAME70) +# include "pmc.h" +# include "board.h" + +/* Checking board configuration of main clock xtal statup time */ +#if !defined(BOARD_OSC_STARTUP_US) +# warning The board main clock xtal statup time has not been defined. Using default settings. +# define BOARD_OSC_STARTUP_US (15625UL) +#endif + +#if !defined(EFC0) +# define EFC0 EFC +#endif + +/** + * Save clock settings and shutdown PLLs + */ +__always_inline static void pmc_save_clock_settings( + uint32_t *p_osc_setting, + uint32_t *p_pll0_setting, + uint32_t *p_pll1_setting, + uint32_t *p_mck_setting, + uint32_t *p_fmr_setting, +#if defined(EFC1) + uint32_t *p_fmr_setting1, +#endif + const bool disable_xtal) +{ + uint32_t mor = PMC->CKGR_MOR; + uint32_t mckr = PMC->PMC_MCKR; + uint32_t fmr = EFC0->EEFC_FMR; +# if defined(EFC1) + uint32_t fmr1 = EFC1->EEFC_FMR; +# endif + + if (p_osc_setting) { + *p_osc_setting = mor; + } + if (p_pll0_setting) { + *p_pll0_setting = PMC->CKGR_PLLAR; + } + if (p_pll1_setting) { +#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP) + *p_pll1_setting = PMC->CKGR_PLLBR; +#elif (SAM3U || SAM3XA) + *p_pll1_setting = PMC->CKGR_UCKR; +#else + *p_pll1_setting = 0; +#endif + } + if (p_mck_setting) { + *p_mck_setting = mckr; + } + if (p_fmr_setting) { + *p_fmr_setting = fmr; + } +#if defined(EFC1) + if (p_fmr_setting1) { + *p_fmr_setting1 = fmr1; + } +#endif + + /* Enable FAST RC */ + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor | CKGR_MOR_MOSCRCEN; + /* if MCK source is PLL, switch to mainck */ + if ((mckr & PMC_MCKR_CSS_Msk) > PMC_MCKR_CSS_MAIN_CLK) { + /* MCK -> MAINCK */ + mckr = (mckr & (~PMC_MCKR_CSS_Msk)) | PMC_MCKR_CSS_MAIN_CLK; + PMC->PMC_MCKR = mckr; + while(!(PMC->PMC_SR & PMC_SR_MCKRDY)); + } + /* MCK prescale -> 1 */ + if (mckr & PMC_MCKR_PRES_Msk) { + mckr = (mckr & (~PMC_MCKR_PRES_Msk)); + PMC->PMC_MCKR = mckr; + while(!(PMC->PMC_SR & PMC_SR_MCKRDY)); + } + /* Disable PLLs */ + pmc_disable_pllack(); +#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP) + pmc_disable_pllbck(); +#elif (SAM3U || SAM3XA) + pmc_disable_upll_clock(); +#endif + + /* Prepare for entering WAIT mode */ + /* Wait fast RC ready */ + while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)); + + /* Switch mainck to FAST RC */ +#if SAMG + /** + * For the sleepwalking feature, we need an accurate RC clock. Only 24M and + * 16M are trimmed in production. Here we select the 24M. + * And so wait state need to be 1. + */ + EFC0->EEFC_FMR = (fmr & (~EEFC_FMR_FWS_Msk)) | EEFC_FMR_FWS(1); + + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) | CKGR_MOR_MOSCRCF_24_MHz | + CKGR_MOR_KEY_PASSWD; +#else + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) | + CKGR_MOR_KEY_PASSWD; +#endif + while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)); + +#if (!SAMG) + /* FWS update */ + EFC0->EEFC_FMR = fmr & (~EEFC_FMR_FWS_Msk); +#if defined(EFC1) + EFC1->EEFC_FMR = fmr1 & (~EEFC_FMR_FWS_Msk); +#endif +#endif + + /* Disable XTALs */ + if (disable_xtal) { + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) | + CKGR_MOR_KEY_PASSWD; + } +} + +/** + * Restore clock settings + */ +__always_inline static void pmc_restore_clock_setting( + const uint32_t osc_setting, + const uint32_t pll0_setting, + const uint32_t pll1_setting, + const uint32_t mck_setting, + const uint32_t fmr_setting +#if defined(EFC1) + , const uint32_t fmr_setting1 +#endif + ) +{ + uint32_t mckr; + uint32_t pll_sr = 0; + + /* Switch mainck to external xtal */ + if (CKGR_MOR_MOSCXTBY == (osc_setting & CKGR_MOR_MOSCXTBY)) { + /* Bypass mode */ + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) | + CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY | + CKGR_MOR_MOSCSEL; + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN & + ~CKGR_MOR_MOSCRCF_Msk) + | CKGR_MOR_KEY_PASSWD; + } else if (CKGR_MOR_MOSCXTEN == (osc_setting & CKGR_MOR_MOSCXTEN)) { + /* Enable External XTAL */ + if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCXTEN)) { + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) | + CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN; + /* Wait the Xtal to stabilize */ + while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)); + } + /* Select External XTAL */ + if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) { + PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCSEL; + while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)); + } + /* Disable Fast RC */ + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN & + ~CKGR_MOR_MOSCRCF_Msk) + | CKGR_MOR_KEY_PASSWD; + } + + if (pll0_setting & CKGR_PLLAR_MULA_Msk) { +#if (SAM4C || SAM4CM || SAMG || SAM4CP) + PMC->CKGR_PLLAR = pll0_setting; +#else + PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | pll0_setting; +#endif + pll_sr |= PMC_SR_LOCKA; + } +#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP) + if (pll1_setting & CKGR_PLLBR_MULB_Msk) { + PMC->CKGR_PLLBR = pll1_setting; + pll_sr |= PMC_SR_LOCKB; + } +#elif (SAM3U || SAM3XA) + if (pll1_setting & CKGR_UCKR_UPLLEN) { + PMC->CKGR_UCKR = pll1_setting; + pll_sr |= PMC_SR_LOCKU; + } +#else + UNUSED(pll1_setting); +#endif + /* Wait MCK source ready */ + switch(mck_setting & PMC_MCKR_CSS_Msk) { + case PMC_MCKR_CSS_PLLA_CLK: + while (!(PMC->PMC_SR & PMC_SR_LOCKA)); + break; +#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP) + case PMC_MCKR_CSS_PLLB_CLK: + while (!(PMC->PMC_SR & PMC_SR_LOCKB)); + break; +#elif (SAM3U || SAM3XA) + case PMC_MCKR_CSS_UPLL_CLK: + while (!(PMC->PMC_SR & PMC_SR_LOCKU)); + break; +#endif + } + + /* Switch to faster clock */ + mckr = PMC->PMC_MCKR; + + /* Set PRES */ + PMC->PMC_MCKR = (mckr & ~PMC_MCKR_PRES_Msk) + | (mck_setting & PMC_MCKR_PRES_Msk); + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); + + /* Restore flash wait states */ + EFC0->EEFC_FMR = fmr_setting; +#if defined(EFC1) + EFC1->EEFC_FMR = fmr_setting1; +#endif + + /* Set CSS and others */ + PMC->PMC_MCKR = mck_setting; + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); + + /* Waiting all restored PLLs ready */ + while (!(PMC->PMC_SR & pll_sr)); +} + +/** If clocks are switched for some sleep mode */ +static volatile bool b_is_sleep_clock_used = false; +/** Callback invoked once when clocks are restored */ +static pmc_callback_wakeup_clocks_restored_t callback_clocks_restored = NULL; + +void pmc_sleep(int sleep_mode) +{ + switch (sleep_mode) { +#if (!(SAMG51 || SAMG53 || SAMG54)) + case SAM_PM_SMODE_SLEEP_WFI: + case SAM_PM_SMODE_SLEEP_WFE: +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAMS70 || SAME70) + SCB->SCR &= (uint32_t)~SCR_SLEEPDEEP; + cpu_irq_enable(); + __WFI(); + break; +#else + PMC->PMC_FSMR &= (uint32_t)~PMC_FSMR_LPM; + SCB->SCR &= (uint32_t)~SCR_SLEEPDEEP; + cpu_irq_enable(); + if (sleep_mode == SAM_PM_SMODE_SLEEP_WFI) + __WFI(); + else + __WFE(); + break; +#endif +#endif + + case SAM_PM_SMODE_WAIT_FAST: + case SAM_PM_SMODE_WAIT: { + uint32_t mor, pllr0, pllr1, mckr; + uint32_t fmr; +#if defined(EFC1) + uint32_t fmr1; +#endif +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAMS70 || SAME70) + (sleep_mode == SAM_PM_SMODE_WAIT_FAST) ? + pmc_set_flash_in_wait_mode(PMC_FSMR_FLPM_FLASH_STANDBY) : + pmc_set_flash_in_wait_mode(PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN); +#endif + cpu_irq_disable(); + b_is_sleep_clock_used = true; + +#if (SAM4C || SAM4CM || SAM4CP) + /* Backup the sub-system 1 status and stop sub-system 1 */ + uint32_t cpclk_backup = PMC->PMC_SCSR & + (PMC_SCSR_CPCK | PMC_SCSR_CPBMCK); + PMC->PMC_SCDR = cpclk_backup | PMC_SCDR_CPKEY_PASSWD; +#endif + pmc_save_clock_settings(&mor, &pllr0, &pllr1, &mckr, &fmr, +#if defined(EFC1) + &fmr1, +#endif + (sleep_mode == SAM_PM_SMODE_WAIT)); + + /* Enter wait mode */ + cpu_irq_enable(); + + pmc_enable_waitmode(); + + cpu_irq_disable(); + pmc_restore_clock_setting(mor, pllr0, pllr1, mckr, fmr +#if defined(EFC1) + , fmr1 +#endif + ); + +#if (SAM4C || SAM4CM || SAM4CP) + /* Restore the sub-system 1 */ + PMC->PMC_SCER = cpclk_backup | PMC_SCER_CPKEY_PASSWD; +#endif + b_is_sleep_clock_used = false; + if (callback_clocks_restored) { + callback_clocks_restored(); + callback_clocks_restored = NULL; + } + cpu_irq_enable(); + + break; + } +#if (!(SAMG51 || SAMG53 || SAMG54)) + case SAM_PM_SMODE_BACKUP: + SCB->SCR |= SCR_SLEEPDEEP; +#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAMS70 || SAME70) + SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_VROFF_STOP_VREG; + cpu_irq_enable(); + __WFI() ; +#else + cpu_irq_enable(); + __WFE() ; +#endif + break; +#endif + } +} + +bool pmc_is_wakeup_clocks_restored(void) +{ + return !b_is_sleep_clock_used; +} + +void pmc_wait_wakeup_clocks_restore( + pmc_callback_wakeup_clocks_restored_t callback) +{ + if (b_is_sleep_clock_used) { + cpu_irq_disable(); + callback_clocks_restored = callback; + } else if (callback) { + callback(); + } +} + +#endif diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/pmc/sleep.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/pmc/sleep.h new file mode 100644 index 0000000..f798bdd --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/pmc/sleep.h @@ -0,0 +1,133 @@ +/** + * \file + * + * \brief Sleep mode access + * + * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef SLEEP_H +#define SLEEP_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * \defgroup sleep_group Power Manager (PM) + * + * This is a stub on the SAM Power Manager Control (PMC) for the sleepmgr + * service. + * + * \note To minimize the code overhead, these functions do not feature + * interrupt-protected access since they are likely to be called inside + * interrupt handlers or in applications where such protection is not + * necessary. If such protection is needed, it must be ensured by the calling + * code. + * + * @{ + */ + +#if defined(__DOXYGEN__) +/** + * \brief Sets the MCU in the specified sleep mode + * \param sleep_mode Sleep mode to set. + */ +#endif +/* SAM3,SAM4,SAMG,SAMV,SAME and SAMS series */ +#if (SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S || SAM4E || SAM4N || SAM4C || \ + SAM4CM || SAM4CP || SAMG || SAMV71 || SAME70 || SAMS70) + +#if (SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S || SAM4E || SAM4N || SAM4C || \ + SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAME70 || SAMS70) +# define SAM_PM_SMODE_ACTIVE 0 /**< Active */ +# define SAM_PM_SMODE_SLEEP_WFE 1 /**< Wait for Events */ +# define SAM_PM_SMODE_SLEEP_WFI 2 /**< Wait for Interrupts */ +# define SAM_PM_SMODE_WAIT_FAST 3 /**< Wait Mode, startup fast (in 3ms) */ +# define SAM_PM_SMODE_WAIT 4 /**< Wait Mode */ +# define SAM_PM_SMODE_BACKUP 5 /**< Backup Mode */ +#else +# define SAM_PM_SMODE_ACTIVE 0 /**< Active */ +# define SAM_PM_SMODE_WAIT_FAST 1 /**< Wait Mode, startup fast (in 3ms) */ +# define SAM_PM_SMODE_WAIT 2 /**< Wait Mode */ +#endif + +/** (SCR) Sleep deep bit */ +#define SCR_SLEEPDEEP (0x1 << 2) + +/** + * Clocks restored callback function type. + * Registered by routine pmc_wait_wakeup_clocks_restore() + * Callback called when all clocks are restored. + */ +typedef void (*pmc_callback_wakeup_clocks_restored_t) (void); + +/** + * Enter sleep mode + * \param sleep_mode Sleep mode to enter + */ +void pmc_sleep(int sleep_mode); + +/** + * Check if clocks are restored after wakeup + * (For WAIT mode. In WAIT mode, clocks are switched to FASTRC. + * After wakeup clocks should be restored, before that some of the + * ISR should not be served, otherwise there may be timing or clock issue.) + */ +bool pmc_is_wakeup_clocks_restored(void); + +/** + * \return true if start waiting + */ +void pmc_wait_wakeup_clocks_restore( + pmc_callback_wakeup_clocks_restored_t callback); + +#endif + +//! @} + +#ifdef __cplusplus +} +#endif + +#endif /* SLEEP_H */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/rstc/example1/rstc_example1.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/rstc/example1/rstc_example1.h new file mode 100644 index 0000000..c193e39 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/rstc/example1/rstc_example1.h @@ -0,0 +1,160 @@ +/** + * \file + * + * \brief SAM Reset Controller (RSTC) Driver Example + * + * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + + #ifndef RSTC_EXAMPLE1_H_INCLUDED + #define RSTC_EXAMPLE1_H_INCLUDED + +/** + * \page asfdoc_sam_drivers_rstc_example1 Reset Controller (RSTC) Example + * + * \section asfdoc_sam_drivers_rstc_example1_purpose Purpose + * + * This basic example shows how to use the Reset Controller (RSTC) peripheral + * available on SAM devices. The RSTC handles all the resets of the system, + * reports which reset occurred last and also drives independently or + * simultaneously the external reset and the peripheral and processor + * resets. + * + * + * \section asfdoc_sam_drivers_rstc_example1_requirements Requirements + * + * - This example can be used with SAM evaluation kits + * - Optional: An oscilloscope connected to the evaluation kit's NRST signal + * + * + * \section asfdoc_sam_drivers_rstc_example1_description Description + * + * Upon startup, the program displays the reset controller status + * and a menu to perform the following: + * \code + * Menu: + * 0 - Reset Status information. + * 1 - User Reset enable. + * 2 - User Reset disable. + * 3 - User Reset interrupt enable. + * 4 - User Reset interrupt disable. + * 5 - Software Reset. + * 6 - Watchdog Reset. + * 7 - NRST assert. \endcode + * + * The menu can be used to initiate several types of reset and to enable/disable + * the User Reset interrupt. + * + * + * \section asfdoc_sam_drivers_rstc_example1_files Main Files + * + * - rstc.c: Reset Controller driver + * - rstc.h: Reset Controller driver header file + * - rstc_example1.c: Reset Controller example application + * + * + * \section asfdoc_sam_drivers_astc_example1_compilinfo Compilation Information + * + * This software is written for GNU GCC and IAR Embedded Workbench® + * for Atmel®. Other compilers may or may not work. + * + * + * \section asfdoc_sam_drivers_rstc_example1_usage Usage + * + * -# Build the program and download it into the evaluation board. + * -# On the computer, open and configure a terminal application + * (e.g., HyperTerminal on Microsoft® Windows®) with these settings: + * - 115200 baud + * - 8 bits of data + * - No parity + * - 1 stop bit + * - No flow control + * -# Start the application. + * -# In the terminal window, the following text should appear: + * \code + * -- RSTC Reset Controller Example -- + * -- xxxxxx-xx + * -- Compiled: xxx xx xxxx xx:xx:xx -- + * + * Reset info : General Reset, NRST=1, User Reset=0 + * + * Menu: + * 0 - Reset Status information. + * 1 - User Reset enable. + * 2 - User Reset disable. + * 3 - User Reset interrupt enable. + * 4 - User Reset interrupt disable. + * 5 - Software Reset. + * 6 - Watchdog Reset. + * 7 - NRST assert. \endcode + * -# Press one of the keys listed in the menu to perform the corresponding + * action. + * - Press '1': The following message is displayed: + * \verbatim User Reset enabled - Press evaluation kit RESET button to test. \endverbatim + * If the evaluation kit's reset button is pressed the last reset source will be displayed + * and the menu shown again. + * - Press '2': The following message is displayed: + * \verbatim User Reset enabled - Press evaluation kit RESET button to test. \endverbatim + * If the evaluation kit's reset button is pressed it will have no effect on the system. + * - Press '3': The following message is displayed: + * \verbatim User Reset interrupt enabled.. \endverbatim + * If the evaluation kit's reset button is pressed the following message will be displayed. + * \verbatim User Reset IRQ triggered. Press any console key for the menu \endverbatim + * - Press '4': The following message is displayed: + * \verbatim User Reset interrupt disabled. \endverbatim + * If the evaluation kit's reset button is pressed it will have no effect on the system. + * - Press '5': The following message is displayed: + * \verbatim Software Reset activated. \endverbatim + * The evaluation kit will perform a software reset, the last reset source will be + * displayed and the menu shown again. + * - Press '6': The following message is displayed: + * \verbatim Watchdog Reset will trigger in 3 seconds. \endverbatim + * The evaluation kit will perform a watchdog reset, the last reset source will be + * displayed and the menu shown again. + * - Press '7': The following message is displayed: + * \verbatim NRST asserted. \endverbatim + * The evaluation kit will assert the NRST signal for 60µs. + * \note The "NRST assert" menu option requires an oscilloscope connected to the + * evaluation kit's NRST signal. To avoid a hardware conflict during the test do not + * use the evaluation kit's manual RESET button. + * + */ + + #endif /* RSTC_EXAMPLE1_H_INCLUDED */ +/* + * Support and FAQ: visit Atmel Support + */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/rstc/rstc.c b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/rstc/rstc.c new file mode 100644 index 0000000..8996128 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/rstc/rstc.c @@ -0,0 +1,214 @@ +/** + * \file + * + * \brief SAM Reset Controller (RSTC) driver. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#include "rstc.h" + +/// @cond +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +#define RSTC_KEY 0xA5000000 + +/** + * \brief Set the external reset length. + * + * \param[in,out] p_rstc Module hardware register base address pointer + * \param[in] ul_length The length of external reset + */ +void rstc_set_external_reset( + Rstc *p_rstc, + const uint32_t ul_length) +{ + /* Validate the parameters. */ + Assert(p_rstc); + + uint32_t mode = p_rstc->RSTC_MR; + + mode &= ~(RSTC_MR_ERSTL_Msk | RSTC_MR_KEY_Msk); + mode |= (RSTC_MR_ERSTL(ul_length) | RSTC_KEY); + + p_rstc->RSTC_MR = mode; +} + +/** + * \brief Enable User Reset. + * + * \param[in,out] p_rstc Module hardware register base address pointer + */ +void rstc_enable_user_reset( + Rstc *p_rstc) +{ + /* Validate the parameters. */ + Assert(p_rstc); + + uint32_t mode = p_rstc->RSTC_MR; + + mode &= ~RSTC_MR_KEY_Msk; + mode |= (RSTC_MR_URSTEN | RSTC_KEY); + + p_rstc->RSTC_MR = mode; +} + +/** + * \brief Disable User Reset. + * + * \param[in,out] p_rstc Module hardware register base address pointer + */ +void rstc_disable_user_reset( + Rstc *p_rstc) +{ + /* Validate the parameters. */ + Assert(p_rstc); + + uint32_t mode = p_rstc->RSTC_MR; + + mode &= ~(RSTC_MR_URSTEN | RSTC_MR_KEY_Msk); + mode |= RSTC_KEY; + + p_rstc->RSTC_MR = mode; +} + +/** + * \brief Enable the User Reset interrupt. + * + * \param[in,out] p_rstc Module hardware register base address pointer + */ +void rstc_enable_user_reset_interrupt( + Rstc *p_rstc) +{ + /* Validate the parameters. */ + Assert(p_rstc); + + uint32_t mode = p_rstc->RSTC_MR; + + mode &= ~RSTC_MR_KEY_Msk; + mode |= (RSTC_MR_URSTIEN | RSTC_KEY); + + p_rstc->RSTC_MR = mode; +} + +/** + * \brief Disable the User Reset interrupt. + * + * \param[in,out] p_rstc Module hardware register base address pointer + */ +void rstc_disable_user_reset_interrupt( + Rstc *p_rstc) +{ + /* Validate the parameters. */ + Assert(p_rstc); + + uint32_t mode = p_rstc->RSTC_MR; + + mode &= ~(RSTC_MR_URSTIEN | RSTC_MR_KEY_Msk); + mode |= RSTC_KEY; + + p_rstc->RSTC_MR = mode; +} + +/** + * \brief Perform a Software Reset. + * + * \param[out] p_rstc Module hardware register base address pointer + */ +void rstc_start_software_reset( + Rstc *p_rstc) +{ +#if (SAMV71 || SAMV70 || SAMS70 || SAME70) + p_rstc->RSTC_CR = RSTC_KEY | RSTC_CR_PROCRST; +#else + p_rstc->RSTC_CR = RSTC_KEY | RSTC_CR_PROCRST | RSTC_CR_PERRST; +#endif +} + +/** + * \brief Asserts the NRST pin for external resets. + * + * \param[out] p_rstc Module hardware register base address pointer + */ +void rstc_reset_extern( + Rstc *p_rstc) +{ + p_rstc->RSTC_CR = RSTC_KEY | RSTC_CR_EXTRST; +} + +/** + * \brief Get the RSTC status. + * + * \param[in] p_rstc Module hardware register base address pointer + * + * \return RSTC status. + */ +uint32_t rstc_get_status( + Rstc *p_rstc) +{ + return p_rstc->RSTC_SR; +} + +/** + * \brief Get the reset cause. + * + * \param[in] p_rstc Module hardware register base address pointer + * + * \return The last reset cause. + */ +uint32_t rstc_get_reset_cause( + Rstc *p_rstc) +{ + return (p_rstc->RSTC_SR & RSTC_SR_RSTTYP_Msk); +} + +/// @cond +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/rstc/rstc.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/rstc/rstc.h new file mode 100644 index 0000000..557a501 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/rstc/rstc.h @@ -0,0 +1,426 @@ +/** + * \file + * + * \brief SAM Reset Controller (RSTC) driver. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef RSTC_H_INCLUDED +#define RSTC_H_INCLUDED + +/** + * \defgroup asfdoc_sam_drivers_rstc_group SAM3/4C/4CM/4CP/4E/4N/4S/G/V71/V70/S70/E70 Reset Controller (RSTC) Driver + * This driver for Atmel® | SMART ARM®-based microcontrollers + * provides an interface for the configuration and management of the device's + * Reset Controller functionality. + * + * The Reset Controller manages all Resets of the System including; + * external devices (via the NRST pin), Processor Reset and Peripheral Reset. + * It also provides the status of the last reset source. + * + * The following peripheral is used by this module: + * + * - RSTC (Reset Controller) + * + * Devices from the following series can use this module: + * - Atmel | SMART SAM3 + * - Atmel | SMART SAM4C + * - Atmel | SMART SAM4CM + * - Atmel | SMART SAM4CP + * - Atmel | SMART SAM4E + * - Atmel | SMART SAM4N + * - Atmel | SMART SAM4S + * - Atmel | SMART SAM G + * - Atmel | SMART SAMV71 + * - Atmel | SMART SAMV70 + * - Atmel | SMART SAME70 + * - Atmel | SMART SAMS70 + * + * The outline of this documentation is as follows: + * - \ref asfdoc_sam_drivers_rstc_prerequisites + * - \ref asfdoc_sam_drivers_rstc_module_overview + * - \ref asfdoc_sam_drivers_rstc_special_considerations + * - \ref asfdoc_sam_drivers_rstc_extra_info + * - \ref asfdoc_sam_drivers_rstc_examples + * - \ref asfdoc_sam_drivers_rstc_api_overview + * + * + * \section asfdoc_sam_drivers_rstc_prerequisites Prerequisites + * There are no prerequisites for this module. + * + * + * \section asfdoc_sam_drivers_rstc_module_overview Module Overview + * The Reset Controller contains an NRST Manager and a Reset State Manager. It runs at + * Slow Clock (SCLK) and generates the following: + * + * - Processor and Watchdog Timer reset + * - Embedded peripheral reset + * - Co-processor and Co-processor peripheral reset (SAM4C devices only) + * - External device reset (via the NRST pin) + * + * These reset signals are asserted by the Reset Controller acting on external events + * or as the result of an action performed by software. The Reset State Manager controls + * the operation of reset signals and provides a signal to the NRST Manager when an + * assertion of the NRST pin is required. + * + * \subsection asfdoc_sam_drivers_rstc_module_overview_nrst_manager NRST Manager + * To control an external device reset the NRST Manager shapes the NRST assertion period + * using a programmable timer. While asserted, after power-up, NRST is an output and + * driven low. When the programmable time period has elapsed the pin behaves as an input + * and all the system is held in reset if NRST is tied to GND by an external signal. + * + * \subsubsection asfdoc_sam_drivers_rstc_module_overview_nrst_signal NRST Signal or Interrupt + * The NRST Manager samples the NRST pin at Slow Clock (SCLK) speed and drives this pin + * low when required by the Reset State Manager. When the line is detected as being low a + * User Reset is reported to the Reset State Manager. However, the NRST Manager can be + * programmed not to trigger a reset when NRST is asserted. + * + * The Reset controller can also be programmed to generate an interrupt instead of generating + * a reset. + * + * \subsubsection asfdoc_sam_drivers_rstc_module_overview_nrst_external NRST External Reset Control + * The NRST Manager can assert NRST for a programmable time period of between 60µs and 2s + * (approximately). This allows the Reset Controller to shape the NRST pin level and thus to + * guarantee that the NRST line is low for a time that is compliant with any external devices + * also connected to the system reset. + * + * \subsection asfdoc_sam_drivers_rstc_module_overview_reset_state Reset State Manager + * The Reset State Manager handles the different reset sources and generates the internal reset + * signals. + * + * \subsubsection asfdoc_sam_drivers_rstc_module_overview_reset_state_general General Reset + * A general reset occurs when either a Power-on-reset is detected or the Supply Controller + * detects a Brownout or Voltage regulation loss. + * + * \subsubsection asfdoc_sam_drivers_rstc_module_overview_reset_state_backup Backup Reset + * A Backup Reset occurs when the chip returns from Backup Mode. The core_backup_reset signal + * is asserted by the Supply Controller when a Backup Reset occurs. + * + * \subsubsection asfdoc_sam_drivers_rstc_module_overview_reset_state_user User Reset + * If User Reset is enabled then the state is entered when a low level is detected on the + * NRST pin. When User Reset is entered both the Processor Reset and the Peripheral Reset + * are asserted. + * + * The User Reset state is left when NRST rises and the processor clock is re-enabled as + * soon as NRST is confirmed high. + * + * \subsubsection asfdoc_sam_drivers_rstc_module_overview_reset_state_software Software Reset + * The Reset Controller allows software to assert the the following reset signals: + * - Reset the processor and the Watchdog Timer + * - Reset all the embedded peripherals + * - Reset the Co-processor (SAM4C devices only) + * - Reset all the embedded peripherals associated with the Co-processor (SAM4C devices only) + * - Assert NRST for a programmable time period + * + * \note The embedded peripheral reset also includes the memory system and the Remap Command + * and is generally used for debugging purposes. + * + * \note For SAM4C devices the Co-processor peripheral reset only affects the embedded peripherals + * associated with the Co-processor. The processor's peripherals are not reset. + * + * \subsubsection asfdoc_sam_drivers_rstc_module_overview_reset_state_watchdog Watchdog Reset + * The Watchdog Reset is entered when a watchdog fault occurs. + * + * \subsubsection asfdoc_sam_drivers_rstc_module_overview_reset_state_priorities Reset State Priorities + * The Reset State Manager manages the following priorities between the different reset sources, + * given in descending order: + * - General Reset + * - Backup Reset + * - Watchdog Reset + * - Software Reset + * - User Reset + * + * Particular cases are listed below: + * - When in User Reset: + * - A watchdog event is impossible because the Watchdog Timer is being reset + * - A Software Reset is impossible because the processor reset is being activated + * - When in Software Reset: + * - A watchdog event has priority over the current state + * - The NRST has no effect + * - When in Watchdog Reset: + * - The processor reset is active and so a Software Reset cannot be programmed + * - A User Reset cannot be entered + * + * \section asfdoc_sam_drivers_rstc_special_considerations Special Considerations + * System designs using any external devices that require a software controllable + * reset signal assertion longer than two seconds should use a dedicated I/O output + * of the microcontroller. + * + * \section asfdoc_sam_drivers_rstc_extra_info Extra Information + * + * For extra information, see \ref asfdoc_sam_drivers_rstc_extra. This includes: + * - \ref asfdoc_sam_drivers_rstc_extra_acronyms + * - \ref asfdoc_sam_drivers_rstc_extra_dependencies + * - \ref asfdoc_sam_drivers_rstc_extra_errata + * - \ref asfdoc_sam_drivers_rstc_extra_history + * + * + * \section asfdoc_sam_drivers_rstc_examples Examples + * + * For a list of examples related to this driver, see + * \ref asfdoc_sam_drivers_rstc_exqsg. + * + * + * \section asfdoc_sam_drivers_rstc_api_overview API Overview + * + * @{ + */ + +#include + +/// @cond +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/* Definitions of Reset Controller Status. */ +/* Reset cause */ +#define RSTC_GENERAL_RESET (0 << RSTC_SR_RSTTYP_Pos) +#define RSTC_BACKUP_RESET (1 << RSTC_SR_RSTTYP_Pos) +#define RSTC_WATCHDOG_RESET (2 << RSTC_SR_RSTTYP_Pos) +#define RSTC_SOFTWARE_RESET (3 << RSTC_SR_RSTTYP_Pos) +#define RSTC_USER_RESET (4 << RSTC_SR_RSTTYP_Pos) +/* NRST Pin Level. */ +#define RSTC_NRST_LOW (LOW << 16) +#define RSTC_NRST_HIGH (HIGH << 16) + +void rstc_set_external_reset(Rstc* p_rstc, const uint32_t ul_length); +void rstc_enable_user_reset(Rstc* p_rstc); +void rstc_disable_user_reset(Rstc* p_rstc); +void rstc_enable_user_reset_interrupt(Rstc* p_rstc); +void rstc_disable_user_reset_interrupt(Rstc* p_rstc); +void rstc_start_software_reset(Rstc* p_rstc); +void rstc_reset_extern(Rstc *p_rstc); +uint32_t rstc_get_status(Rstc* p_rstc); +uint32_t rstc_get_reset_cause(Rstc* p_rstc); + +#if SAM4C || SAM4CP || defined(__DOXYGEN__) +#ifndef RSTC_CPMR_KEY_PASSWD +/** \internal */ +#define RSTC_CPMR_KEY_PASSWD RSTC_CPMR_CPKEY(0x5AU) +#endif /* RSTC_CPMR_KEY_PASSWD */ + +/** + * \brief Deassert the reset of the Co-processor. + * + * \note This function is for SAM4C devices only. + * + * \param[in,out] p_rstc Module hardware register base address pointer + * \param[in] reset The reset to be deasserted as a bitmask, which could be RSTC_CPMR_CPEREN + * (peripheral reset) and/or RSTC_CPMR_CPROCEN (core reset). + */ +static inline void rstc_deassert_reset_of_coprocessor( + Rstc* p_rstc, + const uint32_t reset) +{ + p_rstc->RSTC_CPMR |= reset | RSTC_CPMR_KEY_PASSWD; +} + +/** + * \brief Assert the reset of the Co-processor. + * + * \note This function is for SAM4C devices only. + * + * \param[in,out] p_rstc Module hardware register base address pointer + * \param[in] reset The reset to be asserted as a bitmask, which could be RSTC_CPMR_CPEREN + * (peripheral reset) and/or RSTC_CPMR_CPROCEN (core reset). + */ +static inline void rstc_assert_reset_of_coprocessor( + Rstc* p_rstc, + const uint32_t reset) +{ + /* Validate parameters. */ + Assert(p_rstc); + + uint32_t tmp = p_rstc->RSTC_CPMR; + tmp &= ~(RSTC_CPMR_CPKEY_Msk | (reset & (RSTC_CPMR_CPEREN | + RSTC_CPMR_CPROCEN))); + tmp |= RSTC_CPMR_KEY_PASSWD; + p_rstc->RSTC_CPMR = tmp; +} +#endif /* SAM4C || SAM4CP || defined(__DOXYGEN__) */ + +/** @} */ + +/** + * \page asfdoc_sam_drivers_rstc_extra Extra Information for Reset Controller Driver + * + * \section asfdoc_sam_drivers_rstc_extra_acronyms Acronyms + * Below is a table listing the acronyms used in this module, along with their + * intended meanings. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
AcronymDefinition
GNDGround
I/OInput Output
NRSTSynchronous Microcontroller Reset
QSGQuick Start Guide
SCLKSlow Clock
+ * + * + * \section asfdoc_sam_drivers_rstc_extra_dependencies Dependencies + * This driver has the following dependencies: + * + * - None + * + * + * \section asfdoc_sam_drivers_rstc_extra_errata Errata + * There are no errata related to this driver. + * + * + * \section asfdoc_sam_drivers_rstc_extra_history Module History + * An overview of the module history is presented in the table below, with + * details on the enhancements and fixes made to the module since its first + * release. The current version of this corresponds to the newest version in + * the table. + * + * + * + * + * + * + * + * + *
Changelog
Initial document release
+ */ + +/** + * \page asfdoc_sam_drivers_rstc_exqsg Examples for Reset Controller Driver + * + * This is a list of the available Quick Start Guides (QSGs) and example + * applications for \ref asfdoc_sam_drivers_rstc_group. QSGs are simple examples with + * step-by-step instructions to configure and use this driver in a selection of + * use cases. Note that a QSG can be compiled as a standalone application or be + * added to the user application. + * + * - \subpage asfdoc_sam_drivers_rstc_quick_start + * - \subpage asfdoc_sam_drivers_rstc_example1 + * + * \page asfdoc_sam_drivers_rstc_document_revision_history Document Revision History + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
Doc. Rev. + * Date + * Comments + *
42279B07/2015Updated title of application note and added list of supported devices
42279A05/2014Initial document release
+ */ + +/** + * \page asfdoc_sam_drivers_rstc_quick_start Quick Start guide for SAM RSTC driver + * + * This is the quick start guide for the + * \ref asfdoc_sam_drivers_rstc_group, + * with step-by-step instructions on how to configure and use the driver + * in a selection of use cases. + * + * The use cases contain several code fragments. The code fragments in the + * steps for setup can be copied into a custom initialization function, while + * the steps for usage can be copied into, e.g., the main application function. + * + * \section asfdoc_sam_drivers_rstc_quick_start_basic_use_case Basic Use Case + * In this basic use case, the User Reset interrupt is enabled and the main + * application notified about NRST signal assertion events. + * + * \subsection asfdoc_sam_drivers_rstc_quick_start_prereq Prerequisites + * - \ref sysclk_group "System Clock Management" + * - \ref asfdoc_sam_drivers_wdt_group "Watchdog Timer" + * + * \section asfdoc_sam_drivers_rstc_quick_start_setup Setup Steps + * \subsection asfdoc_sam_drivers_rstc_quick_start_setup_code Example Code + * Add the following to the application C-file: + * \snippet rstc_example1.c reset_irq_variable + * \snippet rstc_example1.c reset_irq_handler + * + * \subsection asfdoc_sam_drivers_rstc_quick_start_setup_flow Workflow + * + * Enable the User Reset interrupt: + * \snippet rstc_example1.c reset_enable_user_reset_interrupt + * + * \section rtc_basic_use_case_usage Usage Steps + * \subsection rtc_basic_use_case_usage_flow Workflow + * Add to, e.g., main loop in application C-file: + * \snippet rstc_example1.c reset_irq_has_triggered + */ + +/// @cond +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +#endif /* RSTC_H_INCLUDED */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/uart/uart.c b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/uart/uart.c new file mode 100644 index 0000000..c519ed4 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/uart/uart.c @@ -0,0 +1,562 @@ +/** + * \file + * + * \brief Universal Asynchronous Receiver Transceiver (UART) driver for SAM. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#include "uart.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \defgroup sam_drivers_uart_group Universal Asynchronous Receiver Transceiver (UART) + * + * The Universal Asynchronous Receiver Transmitter features a two-pin UART that + * can be used for communication and trace purposes and offers an ideal medium + * for in-situ programming solutions. Moreover, the association with two + * peripheral DMA controller (PDC) channels permits packet handling for these + * tasks with processor time reduced to a minimum. + * + * \par Usage + * + * -# Enable the UART peripheral clock in the PMC. + * -# Enable the required UART PIOs (see pio.h). + * -# Configure the UART by calling uart_init. + * -# Send data through the UART using the uart_write. + * -# Receive data from the UART using the uart_read; the availability of data + * can be polled with uart_is_rx_ready. + * -# Disable the transmitter and/or the receiver of the UART with + * uart_disable_tx and uart_disable_rx. + * + * @{ + */ + +/** + * \brief Configure UART with the specified parameters. + * + * \note The PMC and PIOs must be configured first. + * + * \param p_uart Pointer to a UART instance. + * \param p_uart_opt Pointer to sam_uart_opt_t instance. + * + * \retval 0 Success. + * \retval 1 Bad baud rate generator value. + */ +uint32_t uart_init(Uart *p_uart, const sam_uart_opt_t *p_uart_opt) +{ + uint32_t cd = 0; + + /* Reset and disable receiver & transmitter */ + p_uart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX + | UART_CR_RXDIS | UART_CR_TXDIS; + + /* Check and configure baudrate */ + /* Asynchronous, no oversampling */ + cd = (p_uart_opt->ul_mck / p_uart_opt->ul_baudrate) / UART_MCK_DIV; + if (cd < UART_MCK_DIV_MIN_FACTOR || cd > UART_MCK_DIV_MAX_FACTOR) + return 1; + + p_uart->UART_BRGR = cd; + /* Configure mode */ + p_uart->UART_MR = p_uart_opt->ul_mode; + +#if (!SAMV71 && !SAMV70 && !SAME70 && !SAMS70) + /* Disable PDC channel */ + p_uart->UART_PTCR = UART_PTCR_RXTDIS | UART_PTCR_TXTDIS; +#endif + + /* Enable receiver and transmitter */ + p_uart->UART_CR = UART_CR_RXEN | UART_CR_TXEN; + + return 0; +} + +/** + * \brief Enable UART transmitter. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_enable_tx(Uart *p_uart) +{ + /* Enable transmitter */ + p_uart->UART_CR = UART_CR_TXEN; +} + +/** + * \brief Disable UART transmitter. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_disable_tx(Uart *p_uart) +{ + /* Disable transmitter */ + p_uart->UART_CR = UART_CR_TXDIS; +} + +/** + * \brief Reset UART transmitter. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_reset_tx(Uart *p_uart) +{ + /* Reset transmitter */ + p_uart->UART_CR = UART_CR_RSTTX | UART_CR_TXDIS; +} + +/** + * \brief Enable UART receiver. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_enable_rx(Uart *p_uart) +{ + /* Enable receiver */ + p_uart->UART_CR = UART_CR_RXEN; +} + +/** + * \brief Disable UART receiver. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_disable_rx(Uart *p_uart) +{ + /* Disable receiver */ + p_uart->UART_CR = UART_CR_RXDIS; +} + +/** + * \brief Reset UART receiver. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_reset_rx(Uart *p_uart) +{ + /* Reset receiver */ + p_uart->UART_CR = UART_CR_RSTRX | UART_CR_RXDIS; +} + +/** + * \brief Enable UART receiver and transmitter. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_enable(Uart *p_uart) +{ + /* Enable receiver and transmitter */ + p_uart->UART_CR = UART_CR_RXEN | UART_CR_TXEN; +} + +/** + * \brief Disable UART receiver and transmitter. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_disable(Uart *p_uart) +{ + /* Disable receiver and transmitter */ + p_uart->UART_CR = UART_CR_RXDIS | UART_CR_TXDIS; +} + +/** + * \brief Reset UART receiver and transmitter. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_reset(Uart *p_uart) +{ + /* Reset and disable receiver & transmitter */ + p_uart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX + | UART_CR_RXDIS | UART_CR_TXDIS; +} + +/** \brief Enable UART interrupts. + * + * \param p_uart Pointer to a UART instance. + * \param ul_sources Interrupts to be enabled. + */ +void uart_enable_interrupt(Uart *p_uart, uint32_t ul_sources) +{ + p_uart->UART_IER = ul_sources; +} + +/** \brief Disable UART interrupts. + * + * \param p_uart Pointer to a UART instance. + * \param ul_sources Interrupts to be disabled. + */ +void uart_disable_interrupt(Uart *p_uart, uint32_t ul_sources) +{ + p_uart->UART_IDR = ul_sources; +} + +/** \brief Read UART interrupt mask. + * + * \param p_uart Pointer to a UART instance. + * + * \return The interrupt mask value. + */ +uint32_t uart_get_interrupt_mask(Uart *p_uart) +{ + return p_uart->UART_IMR; +} + +/** + * \brief Get current status. + * + * \param p_uart Pointer to a UART instance. + * + * \return The current UART status. + */ +uint32_t uart_get_status(Uart *p_uart) +{ + return p_uart->UART_SR; +} + +/** + * \brief Reset status bits. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_reset_status(Uart *p_uart) +{ + p_uart->UART_CR = UART_CR_RSTSTA; +} + +/** + * \brief Check if Transmit is Ready. + * Check if data has been loaded in UART_THR and is waiting to be loaded in the + * Transmit Shift Register (TSR). + * + * \param p_uart Pointer to a UART instance. + * + * \retval 1 Data has been transmitted. + * \retval 0 Transmit is not ready, data pending. + */ +uint32_t uart_is_tx_ready(Uart *p_uart) +{ + return (p_uart->UART_SR & UART_SR_TXRDY) > 0; +} + +/** + * \brief Check if Transmit Hold Register is empty. + * Check if the last data written in UART_THR has been loaded in TSR and the + * last data loaded in TSR has been transmitted. + * + * \param p_uart Pointer to a UART instance. + * + * \retval 1 Transmitter is empty. + * \retval 0 Transmitter is not empty. + */ +uint32_t uart_is_tx_empty(Uart *p_uart) +{ + return (p_uart->UART_SR & UART_SR_TXEMPTY) > 0; +} + +/** + * \brief Check if Received data is ready. + * Check if data has been received and loaded in UART_RHR. + * + * \param p_uart Pointer to a UART instance. + * + * \retval 1 One data has been received. + * \retval 0 No data has been received. + */ +uint32_t uart_is_rx_ready(Uart *p_uart) +{ + return (p_uart->UART_SR & UART_SR_RXRDY) > 0; +} + +/** + * \brief Check if both transmit buffers are sent out. + * + * \param p_uart Pointer to a UART instance. + * + * \retval 1 Transmit buffer is empty. + * \retval 0 Transmit buffer is not empty. + */ +uint32_t uart_is_tx_buf_empty(Uart *p_uart) +{ + return (p_uart->UART_SR & UART_SR_TXEMPTY) > 0; +} + +/** + * \brief Set UART clock divisor value + * + * \param p_uart Pointer to a UART instance. + * \param us_divisor Value to be set. + * + */ +void uart_set_clock_divisor(Uart *p_uart, uint16_t us_divisor) +{ + p_uart->UART_BRGR = us_divisor; +} + +/** + * \brief Write to UART Transmit Holding Register + * Before writing user should check if tx is ready (or empty). + * + * \param p_uart Pointer to a UART instance. + * \param data Data to be sent. + * + * \retval 0 Success. + * \retval 1 I/O Failure, UART is not ready. + */ +uint32_t uart_write(Uart *p_uart, const uint8_t uc_data) +{ + /* Check if the transmitter is ready */ + if (!(p_uart->UART_SR & UART_SR_TXRDY)) + return 1; + + /* Send character */ + p_uart->UART_THR = uc_data; + return 0; +} + +/** + * \brief Read from UART Receive Holding Register. + * Before reading user should check if rx is ready. + * + * \param p_uart Pointer to a UART instance. + * + * \retval 0 Success. + * \retval 1 I/O Failure, UART is not ready. + */ +uint32_t uart_read(Uart *p_uart, uint8_t *puc_data) +{ + /* Check if the receiver is ready */ + if ((p_uart->UART_SR & UART_SR_RXRDY) == 0) + return 1; + + /* Read character */ + *puc_data = (uint8_t) p_uart->UART_RHR; + return 0; +} + +#if (!SAMV71 && !SAMV70 && !SAME70 && !SAMS70) +/** + * \brief Check if one receive buffer is filled. + * + * \param p_uart Pointer to a UART instance. + * + * \retval 1 Receive is completed. + * \retval 0 Receive is still pending. + */ +uint32_t uart_is_rx_buf_end(Uart *p_uart) +{ + return (p_uart->UART_SR & UART_SR_ENDRX) > 0; +} + +/** + * \brief Check if one transmit buffer is sent out. + * + * \param p_uart Pointer to a UART instance. + * + * \retval 1 Transmit is completed. + * \retval 0 Transmit is still pending. + */ +uint32_t uart_is_tx_buf_end(Uart *p_uart) +{ + return (p_uart->UART_SR & UART_SR_ENDTX) > 0; +} + +/** + * \brief Check if both receive buffers are full. + * + * \param p_uart Pointer to a UART instance. + * + * \retval 1 Receive buffers are full. + * \retval 0 Receive buffers are not full. + */ +uint32_t uart_is_rx_buf_full(Uart *p_uart) +{ + return (p_uart->UART_SR & UART_SR_RXBUFF) > 0; +} + +/** + * \brief Get UART PDC base address. + * + * \param p_uart Pointer to a UART instance. + * + * \return UART PDC registers base for PDC driver to access. + */ +Pdc *uart_get_pdc_base(Uart *p_uart) +{ + Pdc *p_pdc_base; + +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM) + if (p_uart == UART0) + p_pdc_base = PDC_UART0; +#elif (SAM3XA || SAM3U) + if (p_uart == UART) + p_pdc_base = PDC_UART; +#else +#error "Unsupported device" +#endif + +#if (SAM3S || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM) + if (p_uart == UART1) + p_pdc_base = PDC_UART1; +#endif + +#if (SAM4N) + if (p_uart == UART2) + p_pdc_base = PDC_UART2; +#endif + + return p_pdc_base; +} +#endif + +#if (SAM4C || SAM4CP || SAM4CM) +/** + * \brief Enable UART optical interface. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_enable_optical_interface(Uart *p_uart) +{ + Assert(p_uart == UART1); + p_uart->UART_MR |= UART_MR_OPT_EN; +} + +/** + * \brief Disable UART optical interface. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_disable_optical_interface(Uart *p_uart) +{ + Assert(p_uart == UART1); + p_uart->UART_MR &= ~UART_MR_OPT_EN; +} + +/** + * \brief Enable UART optical interface. + * + * \param p_uart Pointer to a UART instance. + * \param cfg Pointer to a UART optical interface configuration. + */ +void uart_config_optical_interface(Uart *p_uart, + struct uart_config_optical *cfg) +{ + Assert(p_uart == UART1); + uint32_t reg = p_uart->UART_MR; + + reg &= ~(UART_MR_OPT_RXINV | UART_MR_OPT_MDINV | UART_MR_FILTER + | UART_MR_OPT_CLKDIV_Msk | UART_MR_OPT_DUTY_Msk + | UART_MR_OPT_CMPTH_Msk); + reg |= (cfg->rx_inverted ? UART_MR_OPT_RXINV : 0) + | (cfg->tx_inverted ? UART_MR_OPT_MDINV : 0) + | (cfg->rx_filter ? UART_MR_FILTER : 0) + | UART_MR_OPT_CLKDIV(cfg->clk_div) + | cfg->duty | cfg->threshold; + + p_uart->UART_MR = reg; +} +#endif + +#if (SAMG53 || SAMG54 || SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Set sleepwalking match mode. + * + * \param p_uart Pointer to a UART instance. + * \param ul_low_value First comparison value for received character. + * \param ul_high_value Second comparison value for received character. + * \param cmpmode ture for start condition, false for flag only. + * \param cmppar ture for parity check, false for no. + */ +void uart_set_sleepwalking(Uart *p_uart, uint8_t ul_low_value, + bool cmpmode, bool cmppar, uint8_t ul_high_value) +{ + Assert(ul_low_value <= ul_high_value); + + uint32_t temp = 0; + + if (cmpmode) { + temp |= UART_CMPR_CMPMODE_START_CONDITION; + } + + if (cmppar) { + temp |= UART_CMPR_CMPPAR; + } + + temp |= UART_CMPR_VAL1(ul_low_value); + + temp |= UART_CMPR_VAL2(ul_high_value); + + p_uart->UART_CMPR= temp; +} + +/** + * \brief Enables/Disables write protection mode. + * + * \param p_uart Pointer to a UART instance. + * \param flag ture for enable, false for disable. + */ +void uart_set_write_protection(Uart *p_uart, bool flag) +{ + if (flag) { + p_uart->UART_WPMR = UART_WPMR_WPKEY_PASSWD | UART_WPMR_WPEN; + } else { + p_uart->UART_WPMR = UART_WPMR_WPKEY_PASSWD; + } +} +#endif + +//@} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/uart/uart.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/uart/uart.h new file mode 100644 index 0000000..5f6e5f6 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/uart/uart.h @@ -0,0 +1,160 @@ +/** + * \file + * + * \brief Universal Asynchronous Receiver Transceiver (UART) driver for SAM. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef UART_H_INCLUDED +#define UART_H_INCLUDED + +#include "compiler.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/* UART internal div factor for sampling */ +#define UART_MCK_DIV 16 +/* Div factor to get the maximum baud rate */ +#define UART_MCK_DIV_MIN_FACTOR 1 +/* Div factor to get the minimum baud rate */ +#define UART_MCK_DIV_MAX_FACTOR 65535 + +/*! \brief Option list for UART peripheral initialization */ +typedef struct sam_uart_opt { + /** MCK for UART */ + uint32_t ul_mck; + /** Expected baud rate */ + uint32_t ul_baudrate; + /** Initialize value for UART mode register */ + uint32_t ul_mode; +} sam_uart_opt_t; + +uint32_t uart_init(Uart *p_uart, const sam_uart_opt_t *p_uart_opt); +void uart_enable_tx(Uart *p_uart); +void uart_disable_tx(Uart *p_uart); +void uart_reset_tx(Uart *p_uart); +void uart_enable_rx(Uart *p_uart); +void uart_disable_rx(Uart *p_uart); +void uart_reset_rx(Uart *p_uart); +void uart_enable(Uart *p_uart); +void uart_disable(Uart *p_uart); +void uart_reset(Uart *p_uart); +void uart_enable_interrupt(Uart *p_uart, uint32_t ul_sources); +void uart_disable_interrupt(Uart *p_uart, uint32_t ul_sources); +uint32_t uart_get_interrupt_mask(Uart *p_uart); +uint32_t uart_get_status(Uart *p_uart); +void uart_reset_status(Uart *p_uart); +uint32_t uart_is_tx_ready(Uart *p_uart); +uint32_t uart_is_tx_empty(Uart *p_uart); +uint32_t uart_is_rx_ready(Uart *p_uart); +uint32_t uart_is_tx_buf_empty(Uart *p_uart); +void uart_set_clock_divisor(Uart *p_uart, uint16_t us_divisor); +uint32_t uart_write(Uart *p_uart, const uint8_t uc_data); +uint32_t uart_read(Uart *p_uart, uint8_t *puc_data); +#if (!SAMV71 && !SAMV70 && !SAME70 && !SAMS70) +uint32_t uart_is_rx_buf_end(Uart *p_uart); +uint32_t uart_is_tx_buf_end(Uart *p_uart); +uint32_t uart_is_rx_buf_full(Uart *p_uart); +Pdc *uart_get_pdc_base(Uart *p_uart); +#endif +#if (SAMG53 || SAMG54 || SAMV71 || SAMV70 || SAME70 || SAMS70) +void uart_set_sleepwalking(Uart *p_uart, uint8_t ul_low_value, + bool cmpmode, bool cmppar, uint8_t ul_high_value); +void uart_set_write_protection(Uart *p_uart, bool flag); +#endif + +#if (SAM4C || SAM4CP || SAM4CM) +enum uart_optical_duty_cycle { + UART_MOD_CLK_DUTY_50_00 = UART_MR_OPT_DUTY_DUTY_50, + UART_MOD_CLK_DUTY_43_75 = UART_MR_OPT_DUTY_DUTY_43P75, + UART_MOD_CLK_DUTY_37_50 = UART_MR_OPT_DUTY_DUTY_37P5, + UART_MOD_CLK_DUTY_31_25 = UART_MR_OPT_DUTY_DUTY_31P25, + UART_MOD_CLK_DUTY_25_00 = UART_MR_OPT_DUTY_DUTY_25, + UART_MOD_CLK_DUTY_18_75 = UART_MR_OPT_DUTY_DUTY_18P75, + UART_MOD_CLK_DUTY_12_50 = UART_MR_OPT_DUTY_DUTY_12P5, + UART_MOD_CLK_DUTY_06_25 = UART_MR_OPT_DUTY_DUTY_6P25, +}; + +enum uart_optical_cmp_threshold { + UART_RX_CMP_THRESHOLD_VDDIO_DIV_10_0 = UART_MR_OPT_CMPTH_VDDIO_DIV10, + UART_RX_CMP_THRESHOLD_VDDIO_DIV_5_0 = UART_MR_OPT_CMPTH_VDDIO_DIV5, + UART_RX_CMP_THRESHOLD_VDDIO_DIV_3_3 = UART_MR_OPT_CMPTH_VDDIO_DIV3P3, + UART_RX_CMP_THRESHOLD_VDDIO_DIV_2_5 = UART_MR_OPT_CMPTH_VDDIO_DIV2P5, + UART_RX_CMP_THRESHOLD_VDDIO_DIV_2_0 = UART_MR_OPT_CMPTH_VDDIO_DIV2, +}; + +struct uart_config_optical { + /* UART Receive Data Inverted */ + bool rx_inverted; + /* UART Modulated Data Inverted */ + bool tx_inverted; + /* UART Receiver Digital Filter */ + bool rx_filter; + /* Optical Link Clock Divider */ + uint8_t clk_div; + /* Optical Link Modulation Clock Duty Cycle */ + enum uart_optical_duty_cycle duty; + /* Receive Path Comparator Threshold */ + enum uart_optical_cmp_threshold threshold; +}; + +void uart_enable_optical_interface(Uart *p_uart); +void uart_disable_optical_interface(Uart *p_uart); +void uart_config_optical_interface(Uart *p_uart, + struct uart_config_optical *cfg); +#endif + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +#endif /* UART_H_INCLUDED */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/usart/usart.c b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/usart/usart.c new file mode 100644 index 0000000..e7c479b --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/usart/usart.c @@ -0,0 +1,2102 @@ +/** + * \file + * + * \brief Universal Synchronous Asynchronous Receiver Transmitter (USART) driver + * for SAM. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#include "usart.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \defgroup sam_drivers_usart_group Universal Synchronous Asynchronous + * Receiver Transmitter (USART) + * + * The Universal Synchronous Asynchronous Receiver Transceiver (USART) + * provides one full duplex universal synchronous asynchronous serial link. + * Data frame format is widely programmable (data length, parity, number of + * stop bits) to support a maximum of standards. The receiver implements + * parity error, framing error and overrun error detection. The receiver + * time-out enables handling variable-length frames and the transmitter + * timeguard facilitates communications with slow remote devices. Multidrop + * communications are also supported through address bit handling in reception + * and transmission. The driver supports the following modes: + * RS232, RS485, SPI, IrDA, ISO7816, MODEM, Hardware handshaking and LIN. + * + * @{ + */ + +/* The write protect key value. */ +#ifndef US_WPMR_WPKEY_PASSWD +#define US_WPMR_WPKEY_PASSWD US_WPMR_WPKEY(0x555341U) +#endif + +#ifndef US_WPMR_WPKEY_PASSWD +# define US_WPMR_WPKEY_PASSWD US_WPMR_WPKEY(US_WPKEY_VALUE) +#endif + +/* The CD value scope programmed in MR register. */ +#define MIN_CD_VALUE 0x01 +#define MIN_CD_VALUE_SPI 0x04 +#define MAX_CD_VALUE US_BRGR_CD_Msk + +/* The receiver sampling divide of baudrate clock. */ +#define HIGH_FRQ_SAMPLE_DIV 16 +#define LOW_FRQ_SAMPLE_DIV 8 + +/* Max transmitter timeguard. */ +#define MAX_TRAN_GUARD_TIME US_TTGR_TG_Msk + +/* The non-existent parity error number. */ +#define USART_PARITY_ERROR 5 + +/* ISO7816 protocol type. */ +#define ISO7816_T_0 0 +#define ISO7816_T_1 1 + +/** + * \brief Calculate a clock divider(CD) and a fractional part (FP) for the + * USART asynchronous modes to generate a baudrate as close as possible to + * the baudrate set point. + * + * \note Baud rate calculation: Baudrate = ul_mck/(Over * (CD + FP/8)) + * (Over being 16 or 8). The maximal oversampling is selected if it allows to + * generate a baudrate close to the set point. + * + * \param p_usart Pointer to a USART instance. + * \param baudrate Baud rate set point. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 Baud rate is successfully initialized. + * \retval 1 Baud rate set point is out of range for the given input clock + * frequency. + */ +uint32_t usart_set_async_baudrate(Usart *p_usart, + uint32_t baudrate, uint32_t ul_mck) +{ + uint32_t over; + uint32_t cd_fp; + uint32_t cd; + uint32_t fp; + + /* Calculate the receiver sampling divide of baudrate clock. */ + if (ul_mck >= HIGH_FRQ_SAMPLE_DIV * baudrate) { + over = HIGH_FRQ_SAMPLE_DIV; + } else { + over = LOW_FRQ_SAMPLE_DIV; + } + + /* Calculate clock divider according to the fraction calculated formula. */ + cd_fp = (8 * ul_mck + (over * baudrate) / 2) / (over * baudrate); + cd = cd_fp >> 3; + fp = cd_fp & 0x07; + if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) { + return 1; + } + + /* Configure the OVER bit in MR register. */ + if (over == 8) { + p_usart->US_MR |= US_MR_OVER; + } + + /* Configure the baudrate generate register. */ + p_usart->US_BRGR = (cd << US_BRGR_CD_Pos) | (fp << US_BRGR_FP_Pos); + + return 0; +} + +/** + * \brief Calculate a clock divider for the USART synchronous master modes + * to generate a baudrate as close as possible to the baudrate set point. + * + * \note Synchronous baudrate calculation: baudrate = ul_mck / cd + * + * \param p_usart Pointer to a USART instance. + * \param baudrate Baud rate set point. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 Baud rate is successfully initialized. + * \retval 1 Baud rate set point is out of range for the given input clock + * frequency. + */ +static uint32_t usart_set_sync_master_baudrate(Usart *p_usart, + uint32_t baudrate, uint32_t ul_mck) +{ + uint32_t cd; + + /* Calculate clock divider according to the formula in synchronous mode. */ + cd = (ul_mck + baudrate / 2) / baudrate; + + if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) { + return 1; + } + + /* Configure the baudrate generate register. */ + p_usart->US_BRGR = cd << US_BRGR_CD_Pos; + + p_usart->US_MR = (p_usart->US_MR & ~US_MR_USCLKS_Msk) | + US_MR_USCLKS_MCK | US_MR_SYNC; + return 0; +} + +/** + * \brief Select the SCK pin as the source of baud rate for the USART + * synchronous slave modes. + * + * \param p_usart Pointer to a USART instance. + */ +static void usart_set_sync_slave_baudrate(Usart *p_usart) +{ + p_usart->US_MR = (p_usart->US_MR & ~US_MR_USCLKS_Msk) | + US_MR_USCLKS_SCK | US_MR_SYNC; +} + +/** + * \brief Calculate a clock divider (\e CD) for the USART SPI master mode to + * generate a baud rate as close as possible to the baud rate set point. + * + * \note Baud rate calculation: + * \f$ Baudrate = \frac{SelectedClock}{CD} \f$. + * + * \param p_usart Pointer to a USART instance. + * \param baudrate Baud rate set point. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 Baud rate is successfully initialized. + * \retval 1 Baud rate set point is out of range for the given input clock + * frequency. + */ +static uint32_t usart_set_spi_master_baudrate(Usart *p_usart, + uint32_t baudrate, uint32_t ul_mck) +{ + uint32_t cd; + + /* Calculate the clock divider according to the formula in SPI mode. */ + cd = (ul_mck + baudrate / 2) / baudrate; + + if (cd < MIN_CD_VALUE_SPI || cd > MAX_CD_VALUE) { + return 1; + } + + p_usart->US_BRGR = cd << US_BRGR_CD_Pos; + + return 0; +} + +/** + * \brief Select the SCK pin as the source of baudrate for the USART SPI slave + * mode. + * + * \param p_usart Pointer to a USART instance. + */ +static void usart_set_spi_slave_baudrate(Usart *p_usart) +{ + p_usart->US_MR &= ~US_MR_USCLKS_Msk; + p_usart->US_MR |= US_MR_USCLKS_SCK; +} + +/** + * \brief Reset the USART and disable TX and RX. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_reset(Usart *p_usart) +{ + /* Disable the Write Protect. */ + usart_disable_writeprotect(p_usart); + + /* Reset registers that could cause unpredictable behavior after reset. */ + p_usart->US_MR = 0; + p_usart->US_RTOR = 0; + p_usart->US_TTGR = 0; + + /* Disable TX and RX. */ + usart_reset_tx(p_usart); + usart_reset_rx(p_usart); + /* Reset status bits. */ + usart_reset_status(p_usart); + /* Turn off RTS and DTR if exist. */ + usart_drive_RTS_pin_high(p_usart); +#if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E) + usart_drive_DTR_pin_high(p_usart); +#endif +} + +/** + * \brief Configure USART to work in RS232 mode. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_rs232(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) +{ + static uint32_t ul_reg_val; + + /* Reset the USART and shut down TX and RX. */ + usart_reset(p_usart); + + ul_reg_val = 0; + /* Check whether the input values are legal. */ + if (!p_usart_opt || usart_set_async_baudrate(p_usart, + p_usart_opt->baudrate, ul_mck)) { + return 1; + } + + /* Configure the USART option. */ + ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type | + p_usart_opt->channel_mode | p_usart_opt->stop_bits; + + /* Configure the USART mode as normal mode. */ + ul_reg_val |= US_MR_USART_MODE_NORMAL; + + p_usart->US_MR |= ul_reg_val; + + return 0; +} + +/** + * \brief Configure USART to work in hardware handshaking mode. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_hw_handshaking(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) +{ + /* Initialize the USART as standard RS232. */ + if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) { + return 1; + } + + /* Set hardware handshaking mode. */ + p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | + US_MR_USART_MODE_HW_HANDSHAKING; + + return 0; +} + +#if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E) + +/** + * \brief Configure USART to work in modem mode. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_modem(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) +{ + /* + * SAM3S, SAM4S and SAM4E series support MODEM mode only on USART1, + * SAM3U and SAM4L series support MODEM mode only on USART0. + */ +#if (SAM3S || SAM4S || SAM4E) +#ifdef USART1 + if (p_usart != USART1) { + return 1; + } +#endif +#elif (SAM3U || SAM4L) + if (p_usart != USART0) { + return 1; + } +#endif + + /* Initialize the USART as standard RS232. */ + if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) { + return 1; + } + + /* Set MODEM mode. */ + p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | + US_MR_USART_MODE_MODEM; + + return 0; +} +#endif + +/** + * \brief Configure USART to work in SYNC mode and act as a master. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_sync_master(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) +{ + static uint32_t ul_reg_val; + + /* Reset the USART and shut down TX and RX. */ + usart_reset(p_usart); + + ul_reg_val = 0; + /* Check whether the input values are legal. */ + if (!p_usart_opt || usart_set_sync_master_baudrate(p_usart, + p_usart_opt->baudrate, ul_mck)) { + return 1; + } + + /* Configure the USART option. */ + ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type | + p_usart_opt->channel_mode | p_usart_opt->stop_bits; + + /* Set normal mode and output clock as synchronous master. */ + ul_reg_val |= US_MR_USART_MODE_NORMAL | US_MR_CLKO; + p_usart->US_MR |= ul_reg_val; + + return 0; +} + +/** + * \brief Configure USART to work in SYNC mode and act as a slave. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_sync_slave(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt) +{ + static uint32_t ul_reg_val; + + /* Reset the USART and shut down TX and RX. */ + usart_reset(p_usart); + + ul_reg_val = 0; + usart_set_sync_slave_baudrate(p_usart); + + /* Check whether the input values are legal. */ + if (!p_usart_opt) { + return 1; + } + + /* Configure the USART option. */ + ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type | + p_usart_opt->channel_mode | p_usart_opt->stop_bits; + + /* Set normal mode. */ + ul_reg_val |= US_MR_USART_MODE_NORMAL; + p_usart->US_MR |= ul_reg_val; + + return 0; +} + +/** + * \brief Configure USART to work in RS485 mode. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_rs485(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) +{ + /* Initialize the USART as standard RS232. */ + if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) { + return 1; + } + + /* Set RS485 mode. */ + p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | + US_MR_USART_MODE_RS485; + + return 0; +} + +#if (!SAMG55 && !SAMV71 && !SAMV70 && !SAME70 && !SAMS70) +/** + * \brief Configure USART to work in IrDA mode. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_irda(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) +{ + /* Initialize the USART as standard RS232. */ + if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) { + return 1; + } + + /* Set IrDA filter. */ + p_usart->US_IF = p_usart_opt->irda_filter; + + /* Set IrDA mode. */ + p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | + US_MR_USART_MODE_IRDA; + + return 0; +} +#endif + +#if (!SAMV71 && !SAMV70 && !SAME70 && !SAMS70) +/** + * \brief Calculate a clock divider (\e CD) for the USART ISO7816 mode to + * generate an ISO7816 clock as close as possible to the clock set point. + * + * \note ISO7816 clock calculation: Clock = ul_mck / cd + * + * \param p_usart Pointer to a USART instance. + * \param clock ISO7816 clock set point. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 ISO7816 clock is successfully initialized. + * \retval 1 ISO7816 clock set point is out of range for the given input clock + * frequency. + */ +static uint32_t usart_set_iso7816_clock(Usart *p_usart, + uint32_t clock, uint32_t ul_mck) +{ + uint32_t cd; + + /* Calculate clock divider according to the formula in ISO7816 mode. */ + cd = (ul_mck + clock / 2) / clock; + + if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) { + return 1; + } + + p_usart->US_MR = (p_usart->US_MR & ~(US_MR_USCLKS_Msk | US_MR_SYNC | + US_MR_OVER)) | US_MR_USCLKS_MCK | US_MR_CLKO; + + /* Configure the baudrate generate register. */ + p_usart->US_BRGR = cd << US_BRGR_CD_Pos; + + return 0; +} + +/** + * \brief Configure USART to work in ISO7816 mode. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_iso7816(Usart *p_usart, + const usart_iso7816_opt_t *p_usart_opt, uint32_t ul_mck) +{ + static uint32_t ul_reg_val; + + /* Reset the USART and shut down TX and RX. */ + usart_reset(p_usart); + + ul_reg_val = 0; + + /* Check whether the input values are legal. */ + if (!p_usart_opt || ((p_usart_opt->parity_type != US_MR_PAR_EVEN) && + (p_usart_opt->parity_type != US_MR_PAR_ODD))) { + return 1; + } + + if (p_usart_opt->protocol_type == ISO7816_T_0) { + ul_reg_val |= US_MR_USART_MODE_IS07816_T_0 | US_MR_NBSTOP_2_BIT | + (p_usart_opt->max_iterations << US_MR_MAX_ITERATION_Pos); + + if (p_usart_opt->bit_order) { + ul_reg_val |= US_MR_MSBF; + } + } else if (p_usart_opt->protocol_type == ISO7816_T_1) { + /* + * Only LSBF is used in the T=1 protocol, and max_iterations field + * is only used in T=0 mode. + */ + if (p_usart_opt->bit_order || p_usart_opt->max_iterations) { + return 1; + } + + /* Set USART mode to ISO7816, T=1, and always uses 1 stop bit. */ + ul_reg_val |= US_MR_USART_MODE_IS07816_T_1 | US_MR_NBSTOP_1_BIT; + } else { + return 1; + } + + /* Set up the baudrate. */ + if (usart_set_iso7816_clock(p_usart, p_usart_opt->iso7816_hz, ul_mck)) { + return 1; + } + + /* Set FIDI register: bit rate = iso7816_hz / fidi_ratio. */ + p_usart->US_FIDI = p_usart_opt->fidi_ratio; + + /* Set ISO7816 parity type in the MODE register. */ + ul_reg_val |= p_usart_opt->parity_type; + + if (p_usart_opt->inhibit_nack) { + ul_reg_val |= US_MR_INACK; + } + if (p_usart_opt->dis_suc_nack) { + ul_reg_val |= US_MR_DSNACK; + } + + p_usart->US_MR |= ul_reg_val; + + return 0; +} + +/** + * \brief Reset the ITERATION in US_CSR when the ISO7816 mode is enabled. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_reset_iterations(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RSTIT; +} + +/** + * \brief Reset NACK in US_CSR. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_reset_nack(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RSTNACK; +} + +/** + * \brief Check if one receive buffer is filled. + * + * \param p_usart Pointer to a USART instance. + * + * \retval 1 Receive is complete. + * \retval 0 Receive is still pending. + */ +uint32_t usart_is_rx_buf_end(Usart *p_usart) +{ + return (p_usart->US_CSR & US_CSR_ENDRX) > 0; +} + +/** + * \brief Check if one transmit buffer is empty. + * + * \param p_usart Pointer to a USART instance. + * + * \retval 1 Transmit is complete. + * \retval 0 Transmit is still pending. + */ +uint32_t usart_is_tx_buf_end(Usart *p_usart) +{ + return (p_usart->US_CSR & US_CSR_ENDTX) > 0; +} + +/** + * \brief Check if both receive buffers are full. + * + * \param p_usart Pointer to a USART instance. + * + * \retval 1 Receive buffers are full. + * \retval 0 Receive buffers are not full. + */ +uint32_t usart_is_rx_buf_full(Usart *p_usart) +{ + return (p_usart->US_CSR & US_CSR_RXBUFF) > 0; +} + +/** + * \brief Check if both transmit buffers are empty. + * + * \param p_usart Pointer to a USART instance. + * + * \retval 1 Transmit buffers are empty. + * \retval 0 Transmit buffers are not empty. + */ +uint32_t usart_is_tx_buf_empty(Usart *p_usart) +{ + return (p_usart->US_CSR & US_CSR_TXBUFE) > 0; +} + +/** + * \brief Get the total number of errors that occur during an ISO7816 transfer. + * + * \param p_usart Pointer to a USART instance. + * + * \return The number of errors that occurred. + */ +uint8_t usart_get_error_number(Usart *p_usart) +{ + return (p_usart->US_NER & US_NER_NB_ERRORS_Msk); +} + +#endif + +/** + * \brief Configure USART to work in SPI mode and act as a master. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_spi_master(Usart *p_usart, + const usart_spi_opt_t *p_usart_opt, uint32_t ul_mck) +{ + static uint32_t ul_reg_val; + + /* Reset the USART and shut down TX and RX. */ + usart_reset(p_usart); + + ul_reg_val = 0; + /* Check whether the input values are legal. */ + if (!p_usart_opt || (p_usart_opt->spi_mode > SPI_MODE_3) || + usart_set_spi_master_baudrate(p_usart, p_usart_opt->baudrate, + ul_mck)) { + return 1; + } + + /* Configure the character length bit in MR register. */ + ul_reg_val |= p_usart_opt->char_length; + + /* Set SPI master mode and channel mode. */ + ul_reg_val |= US_MR_USART_MODE_SPI_MASTER | US_MR_CLKO | + p_usart_opt->channel_mode; + + switch (p_usart_opt->spi_mode) { + case SPI_MODE_0: + ul_reg_val |= US_MR_CPHA; + ul_reg_val &= ~US_MR_CPOL; + break; + + case SPI_MODE_1: + ul_reg_val &= ~US_MR_CPHA; + ul_reg_val &= ~US_MR_CPOL; + break; + + case SPI_MODE_2: + ul_reg_val |= US_MR_CPHA; + ul_reg_val |= US_MR_CPOL; + break; + + case SPI_MODE_3: + ul_reg_val &= ~US_MR_CPHA; + ul_reg_val |= US_MR_CPOL; + break; + + default: + break; + } + + p_usart->US_MR |= ul_reg_val; + + return 0; +} + +/** + * \brief Configure USART to work in SPI mode and act as a slave. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_spi_slave(Usart *p_usart, + const usart_spi_opt_t *p_usart_opt) +{ + static uint32_t ul_reg_val; + + /* Reset the USART and shut down TX and RX. */ + usart_reset(p_usart); + + ul_reg_val = 0; + usart_set_spi_slave_baudrate(p_usart); + + /* Check whether the input values are legal. */ + if (!p_usart_opt || p_usart_opt->spi_mode > SPI_MODE_3) { + return 1; + } + + /* Configure the character length bit in MR register. */ + ul_reg_val |= p_usart_opt->char_length; + + /* Set SPI slave mode and channel mode. */ + ul_reg_val |= US_MR_USART_MODE_SPI_SLAVE | p_usart_opt->channel_mode; + + switch (p_usart_opt->spi_mode) { + case SPI_MODE_0: + ul_reg_val |= US_MR_CPHA; + ul_reg_val &= ~US_MR_CPOL; + break; + + case SPI_MODE_1: + ul_reg_val &= ~US_MR_CPHA; + ul_reg_val &= ~US_MR_CPOL; + break; + + case SPI_MODE_2: + ul_reg_val |= US_MR_CPHA; + ul_reg_val |= US_MR_CPOL; + break; + + case SPI_MODE_3: + ul_reg_val |= US_MR_CPOL; + ul_reg_val &= ~US_MR_CPHA; + break; + + default: + break; + } + + p_usart->US_MR |= ul_reg_val; + + return 0; +} + +#if (SAM3XA || SAM4L || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) + +/** + * \brief Configure USART to work in LIN mode and act as a LIN master. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param ul_baudrate Baudrate to be used. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_lin_master(Usart *p_usart,uint32_t ul_baudrate, + uint32_t ul_mck) +{ + /* Reset the USART and shut down TX and RX. */ + usart_reset(p_usart); + + /* Set up the baudrate. */ + if (usart_set_async_baudrate(p_usart, ul_baudrate, ul_mck)) { + return 1; + } + + /* Set LIN master mode. */ + p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | + US_MR_USART_MODE_LIN_MASTER; + + usart_enable_rx(p_usart); + usart_enable_tx(p_usart); + + return 0; +} + +/** + * \brief Configure USART to work in LIN mode and act as a LIN slave. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param ul_baudrate Baudrate to be used. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_lin_slave(Usart *p_usart, uint32_t ul_baudrate, + uint32_t ul_mck) +{ + /* Reset the USART and shut down TX and RX. */ + usart_reset(p_usart); + + usart_enable_rx(p_usart); + usart_enable_tx(p_usart); + + /* Set LIN slave mode. */ + p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | + US_MR_USART_MODE_LIN_SLAVE; + + /* Set up the baudrate. */ + if (usart_set_async_baudrate(p_usart, ul_baudrate, ul_mck)) { + return 1; + } + + return 0; +} + +/** + * \brief Abort the current LIN transmission. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_abort_tx(Usart *p_usart) +{ + p_usart->US_CR = US_CR_LINABT; +} + +/** + * \brief Send a wakeup signal on the LIN bus. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_send_wakeup_signal(Usart *p_usart) +{ + p_usart->US_CR = US_CR_LINWKUP; +} + +/** + * \brief Configure the LIN node action, which should be one of PUBLISH, + * SUBSCRIBE or IGNORE. + * + * \param p_usart Pointer to a USART instance. + * \param uc_action 0 for PUBLISH, 1 for SUBSCRIBE, 2 for IGNORE. + */ +void usart_lin_set_node_action(Usart *p_usart, uint8_t uc_action) +{ + p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_NACT_Msk) | + (uc_action << US_LINMR_NACT_Pos); +} + +/** + * \brief Disable the parity check during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_disable_parity(Usart *p_usart) +{ + p_usart->US_LINMR |= US_LINMR_PARDIS; +} + +/** + * \brief Enable the parity check during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_enable_parity(Usart *p_usart) +{ + p_usart->US_LINMR &= ~US_LINMR_PARDIS; +} + +/** + * \brief Disable the checksum during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_disable_checksum(Usart *p_usart) +{ + p_usart->US_LINMR |= US_LINMR_CHKDIS; +} + +/** + * \brief Enable the checksum during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_enable_checksum(Usart *p_usart) +{ + p_usart->US_LINMR &= ~US_LINMR_CHKDIS; +} + +/** + * \brief Configure the checksum type during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + * \param uc_type 0 for LIN 2.0 Enhanced checksum or 1 for LIN 1.3 Classic + * checksum. + */ +void usart_lin_set_checksum_type(Usart *p_usart, uint8_t uc_type) +{ + p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_CHKTYP) | + (uc_type << 4); +} + +/** + * \brief Configure the data length mode during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + * \param uc_mode Indicate the data length type: 0 if the data length is + * defined by the DLC of LIN mode register or 1 if the data length is defined + * by the bit 5 and 6 of the identifier. + */ +void usart_lin_set_data_len_mode(Usart *p_usart, uint8_t uc_mode) +{ + p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_DLM) | + (uc_mode << 5); +} + +/** + * \brief Disable the frame slot mode during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_disable_frame_slot(Usart *p_usart) +{ + p_usart->US_LINMR |= US_LINMR_FSDIS; +} + +/** + * \brief Enable the frame slot mode during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_enable_frame_slot(Usart *p_usart) +{ + p_usart->US_LINMR &= ~US_LINMR_FSDIS; +} + +/** + * \brief Configure the wakeup signal type during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + * \param uc_type Indicate the checksum type: 0 if the wakeup signal is a + * LIN 2.0 wakeup signal; 1 if the wakeup signal is a LIN 1.3 wakeup signal. + */ +void usart_lin_set_wakeup_signal_type(Usart *p_usart, uint8_t uc_type) +{ + p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_WKUPTYP) | + (uc_type << 7); +} + +/** + * \brief Configure the response data length if the data length is defined by + * the DLC field during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + * \param uc_len Indicate the response data length. + */ +void usart_lin_set_response_data_len(Usart *p_usart, uint8_t uc_len) +{ + p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_DLC_Msk) | + ((uc_len - 1) << US_LINMR_DLC_Pos); +} + +/** + * \brief The LIN mode register is not written by the PDC. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_disable_pdc_mode(Usart *p_usart) +{ + p_usart->US_LINMR &= ~US_LINMR_PDCM; +} + +/** + * \brief The LIN mode register (except this flag) is written by the PDC. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_enable_pdc_mode(Usart *p_usart) +{ + p_usart->US_LINMR |= US_LINMR_PDCM; +} + +/** + * \brief Configure the LIN identifier when USART works in LIN master mode. + * + * \param p_usart Pointer to a USART instance. + * \param uc_id The identifier to be transmitted. + */ +void usart_lin_set_tx_identifier(Usart *p_usart, uint8_t uc_id) +{ + p_usart->US_LINIR = (p_usart->US_LINIR & ~US_LINIR_IDCHR_Msk) | + US_LINIR_IDCHR(uc_id); +} + +/** + * \brief Read the identifier when USART works in LIN mode. + * + * \param p_usart Pointer to a USART instance. + * + * \return The last identifier received in LIN slave mode or the last + * identifier transmitted in LIN master mode. + */ +uint8_t usart_lin_read_identifier(Usart *p_usart) +{ + return (p_usart->US_LINIR & US_LINIR_IDCHR_Msk); +} + +/** + * \brief Get data length. + * + * \param p_usart Pointer to a USART instance. + * + * \return Data length. + */ +uint8_t usart_lin_get_data_length(Usart *usart) +{ + if (usart->US_LINMR & US_LINMR_DLM) { + uint8_t data_length = 1 << ((usart->US_LINIR >> + (US_LINIR_IDCHR_Pos + 4)) & 0x03); + return data_length; + } else { + return ((usart->US_LINMR & US_LINMR_DLC_Msk) >> US_LINMR_DLC_Pos) + 1; + } +} + +#endif + +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) +/** + * \brief Get identifier send status. + * + * \param p_usart Pointer to a USART instance. + * + * \return + * 0: No LIN identifier has been sent since the last RSTSTA. + * 1: :At least one LIN identifier has been sent since the last RSTSTA. + */ +uint8_t usart_lin_identifier_send_complete(Usart *usart) +{ + return (usart->US_CSR & US_CSR_LINID) > 0; +} + +/** + * \brief Get identifier received status. + * + * \param p_usart Pointer to a USART instance. + * + * \return + * 0: No LIN identifier has been reveived since the last RSTSTA. + * 1: At least one LIN identifier has been received since the last RSTSTA. + */ +uint8_t usart_lin_identifier_reception_complete(Usart *usart) +{ + return (usart->US_CSR & US_CSR_LINID) > 0; +} + +/** + * \brief Get transmission status. + * + * \param p_usart Pointer to a USART instance. + * + * \return + * 0: The USART is idle or a LIN transfer is ongoing. + * 1: A LIN transfer has been completed since the last RSTSTA. + */ +uint8_t usart_lin_tx_complete(Usart *usart) +{ + return (usart->US_CSR & US_CSR_LINTC) > 0; +} + +/** + * \brief Configure USART to work in LON mode. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param ul_baudrate Baudrate to be used. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_lon(Usart *p_usart,uint32_t ul_baudrate, + uint32_t ul_mck) +{ + /* Reset the USART and shut down TX and RX. */ + usart_reset(p_usart); + + /* Set up the baudrate. */ + if (usart_set_async_baudrate(p_usart, ul_baudrate, ul_mck)) { + return 1; + } + + /* Set LIN master mode. */ + p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | + US_MR_USART_MODE_LON; + + usart_enable_rx(p_usart); + usart_enable_tx(p_usart); + + return 0; +} + +/** + * \brief set LON parameter value. + * + * \param p_usart Pointer to a USART instance. + * \param uc_type 0: LON comm_type = 1 mode, + * 1: LON comm_type = 2 mode + */ +void usart_lon_set_comm_type(Usart *p_usart, uint8_t uc_type) +{ + p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_COMMT) | + (uc_type << 0); +} + +/** + * \brief Disable LON Collision Detection Feature. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lon_disable_coll_detection(Usart *p_usart) +{ + p_usart->US_LONMR |= US_LONMR_COLDET; +} + +/** + * \brief Enable LON Collision Detection Feature. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lon_enable_coll_detection(Usart *p_usart) +{ + p_usart->US_LONMR &= ~US_LONMR_COLDET; +} + +/** + * \brief set Terminate Frame upon Collision Notification. + * + * \param p_usart Pointer to a USART instance. + * \param uc_type 0: Do not terminate the frame in LON comm_type = 1 mode upon collision detection. + * 1:Terminate the frame in LON comm_type = 1 mode upon collision detection if possible. + */ +void usart_lon_set_tcol(Usart *p_usart, uint8_t uc_type) +{ + p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_TCOL) | + (uc_type << 2); +} + +/** + * \brief set LON Collision Detection on Frame Tail. + * + * \param p_usart Pointer to a USART instance. + * \param uc_type 0: Detect collisions after CRC has been sent but prior end of transmission in LON comm_type = 1 mode. + * 1: Ignore collisions after CRC has been sent but prior end of transmission in LON comm_type = 1 mode. + */ +void usart_lon_set_cdtail(Usart *p_usart, uint8_t uc_type) +{ + p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_CDTAIL) | + (uc_type << 3); +} + +/** + * \brief set LON DMA Mode. + * + * \param p_usart Pointer to a USART instance. + * \param uc_type 0: The LON data length register US_LONDL is not written by the DMA. + * 1: The LON data length register US_LONDL is written by the DMA. + */ +void usart_lon_set_dmam(Usart *p_usart, uint8_t uc_type) +{ + p_usart->US_LONMR = (p_usart->US_LONMR & ~US_LONMR_DMAM) | + (uc_type << 4); +} + +/** + * \brief set LON Beta1 Length after Transmission. + * + * \param p_usart Pointer to a USART instance. + * \param ul_len 1-16777215: LON beta1 length after transmission in tbit + */ +void usart_lon_set_beta1_tx_len(Usart *p_usart, uint32_t ul_len) +{ + p_usart->US_LONB1TX = US_LONB1TX_BETA1TX(ul_len); +} + +/** + * \brief set LON Beta1 Length after Reception. + * + * \param p_usart Pointer to a USART instance. + * \param ul_len 1-16777215: LON beta1 length after reception in tbit. + */ +void usart_lon_set_beta1_rx_len(Usart *p_usart, uint32_t ul_len) +{ + p_usart->US_LONB1RX = US_LONB1RX_BETA1RX(ul_len); +} + +/** + * \brief set LON Priority. + * + * \param p_usart Pointer to a USART instance. + * \param uc_psnb 0 -127: LON Priority Slot Number. + * \param uc_nps 0 -127: LON Node Priority Slot. + */ +void usart_lon_set_priority(Usart *p_usart, uint8_t uc_psnb, uint8_t uc_nps) +{ + p_usart->US_LONPRIO = US_LONPRIO_PSNB(uc_psnb) | US_LONPRIO_NPS(uc_nps); +} + +/** + * \brief set LON Indeterminate Time after Transmission. + * + * \param p_usart Pointer to a USART instance. + * \param ul_time 1-16777215: LON Indeterminate Time after Transmission (comm_type = 1 mode only). + */ +void usart_lon_set_tx_idt(Usart *p_usart, uint32_t ul_time) +{ + p_usart->US_IDTTX = US_IDTTX_IDTTX(ul_time); +} + +/** + * \brief set LON Indeterminate Time after Reception. + * + * \param p_usart Pointer to a USART instance. + * \param ul_time 1-16777215: LON Indeterminate Time after Reception (comm_type = 1 mode only). + */ +void usart_lon_set_rx_idt(Usart *p_usart, uint32_t ul_time) +{ + p_usart->US_IDTRX = US_IDTRX_IDTRX(ul_time); +} + +/** + * \brief set LON Preamble Length. + * + * \param p_usart Pointer to a USART instance. + * \param ul_len 1-16383: LON preamble length in tbit(without byte-sync). + */ +void usart_lon_set_pre_len(Usart *p_usart, uint32_t ul_len) +{ + p_usart->US_LONPR = US_LONPR_LONPL(ul_len); +} + +/** + * \brief set LON Data Length. + * + * \param p_usart Pointer to a USART instance. + * \param uc_len 0-255: LON data length is LONDL+1 bytes. + */ +void usart_lon_set_data_len(Usart *p_usart, uint8_t uc_len) +{ + p_usart->US_LONDL = US_LONDL_LONDL(uc_len); +} + +/** + * \brief set LON Priority. + * + * \param p_usart Pointer to a USART instance. + * \param uc_bli LON Backlog Increment. + * \param uc_altp LON Alternate Path Bit. + * \param uc_pb LON Priority Bit. + */ +void usart_lon_set_l2hdr(Usart *p_usart, uint8_t uc_bli, uint8_t uc_altp, uint8_t uc_pb) +{ + p_usart->US_LONL2HDR = US_LONL2HDR_BLI(uc_bli) | (uc_altp << 6) | (uc_pb << 7); +} + +/** + * \brief Check if LON Transmission End. + * + * \param p_usart Pointer to a USART instance. + * + * \retval 1 At least one transmission has been performed since the last RSTSTA. + * \retval 0 Transmission on going or no transmission occurred since the last RSTSTA. + */ +uint32_t usart_lon_is_tx_end(Usart *p_usart) +{ + return (p_usart->US_CSR & US_CSR_LTXD) > 0; +} + +/** + * \brief Check if LON Reception End. + * + * \param p_usart Pointer to a USART instance. + * + * \retval 1 At least one Reception has been performed since the last RSTSTA. + * \retval 0 Reception on going or no Reception occurred since the last RSTSTA. + */ +uint32_t usart_lon_is_rx_end(Usart *p_usart) +{ + return (p_usart->US_CSR & US_CSR_LRXD) > 0; +} +#endif + +/** + * \brief Enable USART transmitter. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_enable_tx(Usart *p_usart) +{ + p_usart->US_CR = US_CR_TXEN; +} + +/** + * \brief Disable USART transmitter. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_disable_tx(Usart *p_usart) +{ + p_usart->US_CR = US_CR_TXDIS; +} + +/** + * \brief Immediately stop and disable USART transmitter. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_reset_tx(Usart *p_usart) +{ + /* Reset transmitter */ + p_usart->US_CR = US_CR_RSTTX | US_CR_TXDIS; +} + +/** + * \brief Configure the transmit timeguard register. + * + * \param p_usart Pointer to a USART instance. + * \param timeguard The value of transmit timeguard. + */ +void usart_set_tx_timeguard(Usart *p_usart, uint32_t timeguard) +{ + p_usart->US_TTGR = timeguard; +} + +/** + * \brief Enable USART receiver. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_enable_rx(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RXEN; +} + +/** + * \brief Disable USART receiver. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_disable_rx(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RXDIS; +} + +/** + * \brief Immediately stop and disable USART receiver. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_reset_rx(Usart *p_usart) +{ + /* Reset Receiver */ + p_usart->US_CR = US_CR_RSTRX | US_CR_RXDIS; +} + +/** + * \brief Configure the receive timeout register. + * + * \param p_usart Pointer to a USART instance. + * \param timeout The value of receive timeout. + */ +void usart_set_rx_timeout(Usart *p_usart, uint32_t timeout) +{ + p_usart->US_RTOR = timeout; +} + +/** + * \brief Enable USART interrupts. + * + * \param p_usart Pointer to a USART peripheral. + * \param ul_sources Interrupt sources bit map. + */ +void usart_enable_interrupt(Usart *p_usart, uint32_t ul_sources) +{ + p_usart->US_IER = ul_sources; +} + +/** + * \brief Disable USART interrupts. + * + * \param p_usart Pointer to a USART peripheral. + * \param ul_sources Interrupt sources bit map. + */ +void usart_disable_interrupt(Usart *p_usart, uint32_t ul_sources) +{ + p_usart->US_IDR = ul_sources; +} + +/** + * \brief Read USART interrupt mask. + * + * \param p_usart Pointer to a USART peripheral. + * + * \return The interrupt mask value. + */ +uint32_t usart_get_interrupt_mask(Usart *p_usart) +{ + return p_usart->US_IMR; +} + +/** + * \brief Get current status. + * + * \param p_usart Pointer to a USART instance. + * + * \return The current USART status. + */ +uint32_t usart_get_status(Usart *p_usart) +{ + return p_usart->US_CSR; +} + +/** + * \brief Reset status bits (PARE, OVER, MANERR, UNRE and PXBRK in US_CSR). + * + * \param p_usart Pointer to a USART instance. + */ +void usart_reset_status(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RSTSTA; +} + +/** + * \brief Start transmission of a break. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_start_tx_break(Usart *p_usart) +{ + p_usart->US_CR = US_CR_STTBRK; +} + +/** + * \brief Stop transmission of a break. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_stop_tx_break(Usart *p_usart) +{ + p_usart->US_CR = US_CR_STPBRK; +} + +/** + * \brief Start waiting for a character before clocking the timeout count. + * Reset the status bit TIMEOUT in US_CSR. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_start_rx_timeout(Usart *p_usart) +{ + p_usart->US_CR = US_CR_STTTO; +} + +/** + * \brief In Multidrop mode only, the next character written to the US_THR + * is sent with the address bit set. + * + * \param p_usart Pointer to a USART instance. + * \param ul_addr The address to be sent out. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_send_address(Usart *p_usart, uint32_t ul_addr) +{ + if ((p_usart->US_MR & US_MR_PAR_MULTIDROP) != US_MR_PAR_MULTIDROP) { + return 1; + } + + p_usart->US_CR = US_CR_SENDA; + + if (usart_write(p_usart, ul_addr)) { + return 1; + } else { + return 0; + } +} + +/** + * \brief Restart the receive timeout. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_restart_rx_timeout(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RETTO; +} + +#if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E) + +/** + * \brief Drive the pin DTR to 0. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_drive_DTR_pin_low(Usart *p_usart) +{ + p_usart->US_CR = US_CR_DTREN; +} + +/** + * \brief Drive the pin DTR to 1. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_drive_DTR_pin_high(Usart *p_usart) +{ + p_usart->US_CR = US_CR_DTRDIS; +} + +#endif + +/** + * \brief Drive the pin RTS to 0. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_drive_RTS_pin_low(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RTSEN; +} + +/** + * \brief Drive the pin RTS to 1. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_drive_RTS_pin_high(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RTSDIS; +} + +/** + * \brief Drive the slave select line NSS (RTS pin) to 0 in SPI master mode. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_spi_force_chip_select(Usart *p_usart) +{ + p_usart->US_CR = US_CR_FCS; +} + +/** + * \brief Drive the slave select line NSS (RTS pin) to 1 in SPI master mode. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_spi_release_chip_select(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RCS; +} + +/** + * \brief Check if Transmit is Ready. + * Check if data have been loaded in USART_THR and are waiting to be loaded + * into the Transmit Shift Register (TSR). + * + * \param p_usart Pointer to a USART instance. + * + * \retval 1 No data is in the Transmit Holding Register. + * \retval 0 There is data in the Transmit Holding Register. + */ +uint32_t usart_is_tx_ready(Usart *p_usart) +{ + return (p_usart->US_CSR & US_CSR_TXRDY) > 0; +} + +/** + * \brief Check if Transmit Holding Register is empty. + * Check if the last data written in USART_THR have been loaded in TSR and the + * last data loaded in TSR have been transmitted. + * + * \param p_usart Pointer to a USART instance. + * + * \retval 1 Transmitter is empty. + * \retval 0 Transmitter is not empty. + */ +uint32_t usart_is_tx_empty(Usart *p_usart) +{ + return (p_usart->US_CSR & US_CSR_TXEMPTY) > 0; +} + +/** + * \brief Check if the received data are ready. + * Check if Data have been received and loaded into USART_RHR. + * + * \param p_usart Pointer to a USART instance. + * + * \retval 1 Some data has been received. + * \retval 0 No data has been received. + */ +uint32_t usart_is_rx_ready(Usart *p_usart) +{ + return (p_usart->US_CSR & US_CSR_RXRDY) > 0; +} + +/** + * \brief Write to USART Transmit Holding Register. + * + * \note Before writing user should check if tx is ready (or empty). + * + * \param p_usart Pointer to a USART instance. + * \param c Data to be sent. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_write(Usart *p_usart, uint32_t c) +{ + if (!(p_usart->US_CSR & US_CSR_TXRDY)) { + return 1; + } + + p_usart->US_THR = US_THR_TXCHR(c); + return 0; +} + +/** + * \brief Write to USART Transmit Holding Register. + * + * \note Before writing user should check if tx is ready (or empty). + * + * \param p_usart Pointer to a USART instance. + * \param c Data to be sent. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_putchar(Usart *p_usart, uint32_t c) +{ + while (!(p_usart->US_CSR & US_CSR_TXRDY)) { + } + + p_usart->US_THR = US_THR_TXCHR(c); + + return 0; +} + +/** + * \brief Write one-line string through USART. + * + * \param p_usart Pointer to a USART instance. + * \param string Pointer to one-line string to be sent. + */ +void usart_write_line(Usart *p_usart, const char *string) +{ + while (*string != '\0') { + usart_putchar(p_usart, *string++); + } +} + +/** + * \brief Read from USART Receive Holding Register. + * + * \note Before reading user should check if rx is ready. + * + * \param p_usart Pointer to a USART instance. + * \param c Pointer where the one-byte received data will be stored. + * + * \retval 0 on success. + * \retval 1 if no data is available or errors. + */ +uint32_t usart_read(Usart *p_usart, uint32_t *c) +{ + if (!(p_usart->US_CSR & US_CSR_RXRDY)) { + return 1; + } + + /* Read character */ + *c = p_usart->US_RHR & US_RHR_RXCHR_Msk; + + return 0; +} + +/** + * \brief Read from USART Receive Holding Register. + * Before reading user should check if rx is ready. + * + * \param p_usart Pointer to a USART instance. + * \param c Pointer where the one-byte received data will be stored. + * + * \retval 0 Data has been received. + * \retval 1 on failure. + */ +uint32_t usart_getchar(Usart *p_usart, uint32_t *c) +{ + /* Wait until it's not empty or timeout has reached. */ + while (!(p_usart->US_CSR & US_CSR_RXRDY)) { + } + + /* Read character */ + *c = p_usart->US_RHR & US_RHR_RXCHR_Msk; + + return 0; +} + +#if (SAM3XA || SAM3U) +/** + * \brief Get Transmit address for DMA operation. + * + * \param p_usart Pointer to a USART instance. + * + * \return Transmit address for DMA access. + */ +uint32_t *usart_get_tx_access(Usart *p_usart) +{ + return (uint32_t *)&(p_usart->US_THR); +} + +/** + * \brief Get Receive address for DMA operation. + * + * \param p_usart Pointer to a USART instance. + * + * \return Receive address for DMA access. + */ +uint32_t *usart_get_rx_access(Usart *p_usart) +{ + return (uint32_t *)&(p_usart->US_RHR); +} +#endif + +#if (!SAM4L && !SAMV71 && !SAMV70 && !SAME70 && !SAMS70) +/** + * \brief Get USART PDC base address. + * + * \param p_usart Pointer to a UART instance. + * + * \return USART PDC registers base for PDC driver to access. + */ +Pdc *usart_get_pdc_base(Usart *p_usart) +{ + Pdc *p_pdc_base; + + p_pdc_base = (Pdc *)NULL; + +#ifdef PDC_USART + if (p_usart == USART) { + p_pdc_base = PDC_USART; + return p_pdc_base; + } +#endif +#ifdef PDC_USART0 + if (p_usart == USART0) { + p_pdc_base = PDC_USART0; + return p_pdc_base; + } +#endif +#ifdef PDC_USART1 + else if (p_usart == USART1) { + p_pdc_base = PDC_USART1; + return p_pdc_base; + } +#endif +#ifdef PDC_USART2 + else if (p_usart == USART2) { + p_pdc_base = PDC_USART2; + return p_pdc_base; + } +#endif +#ifdef PDC_USART3 + else if (p_usart == USART3) { + p_pdc_base = PDC_USART3; + return p_pdc_base; + } +#endif +#ifdef PDC_USART4 + else if (p_usart == USART4) { + p_pdc_base = PDC_USART4; + return p_pdc_base; + } +#endif +#ifdef PDC_USART5 + else if (p_usart == USART5) { + p_pdc_base = PDC_USART5; + return p_pdc_base; + } +#endif +#ifdef PDC_USART6 + else if (p_usart == USART6) { + p_pdc_base = PDC_USART6; + return p_pdc_base; + } +#endif +#ifdef PDC_USART7 + else if (p_usart == USART7) { + p_pdc_base = PDC_USART7; + return p_pdc_base; + } +#endif + + return p_pdc_base; +} +#endif + +/** + * \brief Enable write protect of USART registers. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_enable_writeprotect(Usart *p_usart) +{ + p_usart->US_WPMR = US_WPMR_WPEN | US_WPMR_WPKEY_PASSWD; +} + +/** + * \brief Disable write protect of USART registers. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_disable_writeprotect(Usart *p_usart) +{ + p_usart->US_WPMR = US_WPMR_WPKEY_PASSWD; +} + +/** + * \brief Get write protect status. + * + * \param p_usart Pointer to a USART instance. + * + * \return 0 if no write protect violation occurred, or 16-bit write protect + * violation source. + */ +uint32_t usart_get_writeprotect_status(Usart *p_usart) +{ + uint32_t reg_value; + + reg_value = p_usart->US_WPSR; + if (reg_value & US_WPSR_WPVS) { + return (reg_value & US_WPSR_WPVSRC_Msk) >> US_WPSR_WPVSRC_Pos; + } else { + return 0; + } +} + +#if (SAM3S || SAM4S || SAM3U || SAM3XA || SAM4L || SAM4E || SAM4C || SAM4CP || SAM4CM) + +/** + * \brief Configure the transmitter preamble length when the Manchester + * encode/decode is enabled. + * + * \param p_usart Pointer to a USART instance. + * \param uc_len The transmitter preamble length, which should be 0 ~ 15. + */ +void usart_man_set_tx_pre_len(Usart *p_usart, uint8_t uc_len) +{ + p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_PL_Msk) | + US_MAN_TX_PL(uc_len); +} + +/** + * \brief Configure the transmitter preamble pattern when the Manchester + * encode/decode is enabled, which should be 0 ~ 3. + * + * \param p_usart Pointer to a USART instance. + * \param uc_pattern 0 if the preamble is composed of '1's; + * 1 if the preamble is composed of '0's; + * 2 if the preamble is composed of '01's; + * 3 if the preamble is composed of '10's. + */ +void usart_man_set_tx_pre_pattern(Usart *p_usart, uint8_t uc_pattern) +{ + p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_PP_Msk) | + (uc_pattern << US_MAN_TX_PP_Pos); +} + +/** + * \brief Configure the transmitter Manchester polarity when the Manchester + * encode/decode is enabled. + * + * \param p_usart Pointer to a USART instance. + * \param uc_polarity Indicate the transmitter Manchester polarity, which + * should be 0 or 1. + */ +void usart_man_set_tx_polarity(Usart *p_usart, uint8_t uc_polarity) +{ + p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_MPOL) | + (uc_polarity << 12); +} + +/** + * \brief Configure the detected receiver preamble length when the Manchester + * encode/decode is enabled. + * + * \param p_usart Pointer to a USART instance. + * \param uc_len The detected receiver preamble length, which should be 0 ~ 15. + */ +void usart_man_set_rx_pre_len(Usart *p_usart, uint8_t uc_len) +{ + p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_PL_Msk) | + US_MAN_RX_PL(uc_len); +} + +/** + * \brief Configure the detected receiver preamble pattern when the Manchester + * encode/decode is enabled, which should be 0 ~ 3. + * + * \param p_usart Pointer to a USART instance. + * \param uc_pattern 0 if the preamble is composed of '1's; + * 1 if the preamble is composed of '0's; + * 2 if the preamble is composed of '01's; + * 3 if the preamble is composed of '10's. + */ +void usart_man_set_rx_pre_pattern(Usart *p_usart, uint8_t uc_pattern) +{ + p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_PP_Msk) | + (uc_pattern << US_MAN_RX_PP_Pos); +} + +/** + * \brief Configure the receiver Manchester polarity when the Manchester + * encode/decode is enabled. + * + * \param p_usart Pointer to a USART instance. + * \param uc_polarity Indicate the receiver Manchester polarity, which should + * be 0 or 1. + */ +void usart_man_set_rx_polarity(Usart *p_usart, uint8_t uc_polarity) +{ + p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_MPOL) | + (uc_polarity << 28); +} + +/** + * \brief Enable drift compensation. + * + * \note The 16X clock mode must be enabled. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_man_enable_drift_compensation(Usart *p_usart) +{ + p_usart->US_MAN |= US_MAN_DRIFT; +} + +/** + * \brief Disable drift compensation. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_man_disable_drift_compensation(Usart *p_usart) +{ + p_usart->US_MAN &= ~US_MAN_DRIFT; +} + +#endif + +#if SAM4L + +uint32_t usart_get_version(Usart *p_usart) +{ + return p_usart->US_VERSION; +} + +#endif + +#if SAMG55 +/** + * \brief Set sleepwalking match mode. + * + * \param p_uart Pointer to a USART instance. + * \param ul_low_value First comparison value for received character. + * \param ul_high_value Second comparison value for received character. + * \param cmpmode ture for start condition, false for flag only. + * \param cmppar ture for parity check, false for no. + */ +void usart_set_sleepwalking(Usart *p_uart, uint8_t ul_low_value, + bool cmpmode, bool cmppar, uint8_t ul_high_value) +{ + Assert(ul_low_value <= ul_high_value); + + uint32_t temp = 0; + + if (cmpmode) { + temp |= US_CMPR_CMPMODE_START_CONDITION; + } + + if (cmppar) { + temp |= US_CMPR_CMPPAR; + } + + temp |= US_CMPR_VAL1(ul_low_value); + + temp |= US_CMPR_VAL2(ul_high_value); + + p_uart->US_CMPR= temp; +} +#endif + +//@} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/usart/usart.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/usart/usart.h new file mode 100644 index 0000000..d279f74 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/drivers/usart/usart.h @@ -0,0 +1,779 @@ +/** + * \file + * + * \brief Universal Synchronous Asynchronous Receiver Transmitter (USART) driver + * for SAM. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef USART_H_INCLUDED +#define USART_H_INCLUDED + +#include "compiler.h" + +/** + * \defgroup group_sam_drivers_usart Universal Synchronous Asynchronous Receiver + * Transmitter (USART). + * + * See \ref sam_usart_quickstart. + * + * This is a low-level driver implementation for the SAM Universal + * Synchronous/Asynchronous Receiver/Transmitter. + * + * @{ + */ + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** Clock phase. */ +#define SPI_CPHA (1 << 0) + +/** Clock polarity. */ +#define SPI_CPOL (1 << 1) + +/** SPI mode definition. */ +#define SPI_MODE_0 0 +#define SPI_MODE_1 (SPI_CPHA) +#define SPI_MODE_2 (SPI_CPOL) +#define SPI_MODE_3 (SPI_CPOL | SPI_CPHA) + +/**micro definition for LIN mode of SAMV71*/ +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) +#define US_MR_USART_MODE_LIN_MASTER 0x0A +#define US_MR_USART_MODE_LIN_SLAVE 0x0B +#endif +/* Input parameters when initializing RS232 and similar modes. */ +typedef struct { + /* Set baud rate of the USART (unused in slave modes). */ + uint32_t baudrate; + + /* + * Number of bits, which should be one of the following: US_MR_CHRL_5_BIT, + * US_MR_CHRL_6_BIT, US_MR_CHRL_7_BIT, US_MR_CHRL_8_BIT or + * US_MR_MODE9. + */ + uint32_t char_length; + + /* + * Parity type, which should be one of the following: US_MR_PAR_EVEN, + * US_MR_PAR_ODD, US_MR_PAR_SPACE, US_MR_PAR_MARK, US_MR_PAR_NO + * or US_MR_PAR_MULTIDROP. + */ + uint32_t parity_type; + + /* + * Number of stop bits between two characters: US_MR_NBSTOP_1_BIT, + * US_MR_NBSTOP_1_5_BIT, US_MR_NBSTOP_2_BIT. + * \note US_MR_NBSTOP_1_5_BIT is supported in asynchronous modes only. + */ + uint32_t stop_bits; + + /* + * Run the channel in test mode, which should be one of following: + * US_MR_CHMODE_NORMAL, US_MR_CHMODE_AUTOMATIC, + * US_MR_CHMODE_LOCAL_LOOPBACK, US_MR_CHMODE_REMOTE_LOOPBACK. + */ + uint32_t channel_mode; + + /* Filter of IrDA mode, useless in other modes. */ + uint32_t irda_filter; +} sam_usart_opt_t; + +/* Input parameters when initializing ISO7816 mode. */ +typedef struct { + /* Set the frequency of the ISO7816 clock. */ + uint32_t iso7816_hz; + + /* + * The number of ISO7816 clock ticks in every bit period (1 to 2047, + * 0 = disable clock). Baudrate rate = iso7816_hz / fidi_ratio. + */ + uint32_t fidi_ratio; + + /* + * How to calculate the parity bit: US_MR_PAR_EVEN for normal mode or + * US_MR_PAR_ODD for inverse mode. + */ + uint32_t parity_type; + + /* + * Inhibit Non Acknowledge: + * - 0: the NACK is generated; + * - 1: the NACK is not generated. + * + * \note This bit will be used only in ISO7816 mode, protocol T = 0 + * receiver. + */ + uint32_t inhibit_nack; + + /* + * Disable successive NACKs. + * - 0: NACK is sent on the ISO line as soon as a parity error occurs + * in the received character. Successive parity errors are counted up to + * the value in the max_iterations field. These parity errors generate + * a NACK on the ISO line. As soon as this value is reached, no additional + * NACK is sent on the ISO line. The ITERATION flag is asserted. + */ + uint32_t dis_suc_nack; + + /* Max number of repetitions (0 to 7). */ + uint32_t max_iterations; + + /* + * Bit order in transmitted characters: + * - 0: LSB first; + * - 1: MSB first. + */ + uint32_t bit_order; + + /* + * Which protocol is used: + * - 0: T = 0; + * - 1: T = 1. + */ + uint32_t protocol_type; +} usart_iso7816_opt_t; + +/* Input parameters when initializing SPI mode. */ +typedef struct { + /* Set the frequency of the SPI clock (unused in slave mode). */ + uint32_t baudrate; + + /* + * Number of bits, which should be one of the following: US_MR_CHRL_5_BIT, + * US_MR_CHRL_6_BIT, US_MR_CHRL_7_BIT, US_MR_CHRL_8_BIT or + * US_MR_MODE9. + */ + uint32_t char_length; + + /* + * Which SPI mode to use, which should be one of the following: + * SPI_MODE_0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_3. + */ + uint32_t spi_mode; + + /* + * Run the channel in test mode, which should be one of following: + * US_MR_CHMODE_NORMAL, US_MR_CHMODE_AUTOMATIC, + * US_MR_CHMODE_LOCAL_LOOPBACK, US_MR_CHMODE_REMOTE_LOOPBACK. + */ + uint32_t channel_mode; +} usart_spi_opt_t; + +void usart_reset(Usart *p_usart); +uint32_t usart_set_async_baudrate(Usart *p_usart, + uint32_t baudrate, uint32_t ul_mck); +uint32_t usart_init_rs232(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck); +uint32_t usart_init_hw_handshaking(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck); +#if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E) +uint32_t usart_init_modem(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck); +#endif +uint32_t usart_init_sync_master(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck); +uint32_t usart_init_sync_slave(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt); +uint32_t usart_init_rs485(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck); +#if (!SAMG55 && !SAMV71 && !SAMV70 && !SAME70 && !SAMS70) +uint32_t usart_init_irda(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck); +#endif +#if (!SAMV71 && !SAMV70 && !SAME70 && !SAMS70) +uint32_t usart_init_iso7816(Usart *p_usart, + const usart_iso7816_opt_t *p_usart_opt, uint32_t ul_mck); +void usart_reset_iterations(Usart *p_usart); +void usart_reset_nack(Usart *p_usart); +uint32_t usart_is_rx_buf_end(Usart *p_usart); +uint32_t usart_is_tx_buf_end(Usart *p_usart); +uint32_t usart_is_rx_buf_full(Usart *p_usart); +uint32_t usart_is_tx_buf_empty(Usart *p_usart); +uint8_t usart_get_error_number(Usart *p_usart); +#endif +uint32_t usart_init_spi_master(Usart *p_usart, + const usart_spi_opt_t *p_usart_opt, uint32_t ul_mck); +uint32_t usart_init_spi_slave(Usart *p_usart, + const usart_spi_opt_t *p_usart_opt); +#if (SAM3XA || SAM4L || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70) +uint32_t usart_init_lin_master(Usart *p_usart, uint32_t ul_baudrate, + uint32_t ul_mck); +uint32_t usart_init_lin_slave(Usart *p_usart, uint32_t ul_baudrate, + uint32_t ul_mck); +void usart_lin_abort_tx(Usart *p_usart); +void usart_lin_send_wakeup_signal(Usart *p_usart); +void usart_lin_set_node_action(Usart *p_usart, uint8_t uc_action); +void usart_lin_disable_parity(Usart *p_usart); +void usart_lin_enable_parity(Usart *p_usart); +void usart_lin_disable_checksum(Usart *p_usart); +void usart_lin_enable_checksum(Usart *p_usart); +void usart_lin_set_checksum_type(Usart *p_usart, uint8_t uc_type); +void usart_lin_set_data_len_mode(Usart *p_usart, uint8_t uc_mode); +void usart_lin_disable_frame_slot(Usart *p_usart); +void usart_lin_enable_frame_slot(Usart *p_usart); +void usart_lin_set_wakeup_signal_type(Usart *p_usart, uint8_t uc_type); +void usart_lin_set_response_data_len(Usart *p_usart, uint8_t uc_len); +void usart_lin_disable_pdc_mode(Usart *p_usart); +void usart_lin_enable_pdc_mode(Usart *p_usart); +void usart_lin_set_tx_identifier(Usart *p_usart, uint8_t uc_id); +uint8_t usart_lin_read_identifier(Usart *p_usart); +uint8_t usart_lin_get_data_length(Usart *usart); +#endif +#if (SAMV71 || SAMV70 || SAME70 || SAMS70) +uint8_t usart_lin_identifier_send_complete(Usart *usart); +uint8_t usart_lin_identifier_reception_complete(Usart *usart); +uint8_t usart_lin_tx_complete(Usart *usart); +uint32_t usart_init_lon(Usart *p_usart, uint32_t ul_baudrate, uint32_t ul_mck); +void usart_lon_set_comm_type(Usart *p_usart, uint8_t uc_type); +void usart_lon_disable_coll_detection(Usart *p_usart); +void usart_lon_enable_coll_detection(Usart *p_usart); +void usart_lon_set_tcol(Usart *p_usart, uint8_t uc_type); +void usart_lon_set_cdtail(Usart *p_usart, uint8_t uc_type); +void usart_lon_set_dmam(Usart *p_usart, uint8_t uc_type); +void usart_lon_set_beta1_tx_len(Usart *p_usart, uint32_t ul_len); +void usart_lon_set_beta1_rx_len(Usart *p_usart, uint32_t ul_len); +void usart_lon_set_priority(Usart *p_usart, uint8_t uc_psnb, uint8_t uc_nps); +void usart_lon_set_tx_idt(Usart *p_usart, uint32_t ul_time); +void usart_lon_set_rx_idt(Usart *p_usart, uint32_t ul_time); +void usart_lon_set_pre_len(Usart *p_usart, uint32_t ul_len); +void usart_lon_set_data_len(Usart *p_usart, uint8_t uc_len); +void usart_lon_set_l2hdr(Usart *p_usart, uint8_t uc_bli, uint8_t uc_altp, uint8_t uc_pb); +uint32_t usart_lon_is_tx_end(Usart *p_usart); +uint32_t usart_lon_is_rx_end(Usart *p_usart); +#endif +void usart_enable_tx(Usart *p_usart); +void usart_disable_tx(Usart *p_usart); +void usart_reset_tx(Usart *p_usart); +void usart_set_tx_timeguard(Usart *p_usart, uint32_t timeguard); +void usart_enable_rx(Usart *p_usart); +void usart_disable_rx(Usart *p_usart); +void usart_reset_rx(Usart *p_usart); +void usart_set_rx_timeout(Usart *p_usart, uint32_t timeout); +void usart_enable_interrupt(Usart *p_usart, uint32_t ul_sources); +void usart_disable_interrupt(Usart *p_usart, uint32_t ul_sources); +uint32_t usart_get_interrupt_mask(Usart *p_usart); +uint32_t usart_get_status(Usart *p_usart); +void usart_reset_status(Usart *p_usart); +void usart_start_tx_break(Usart *p_usart); +void usart_stop_tx_break(Usart *p_usart); +void usart_start_rx_timeout(Usart *p_usart); +uint32_t usart_send_address(Usart *p_usart, uint32_t ul_addr); +void usart_restart_rx_timeout(Usart *p_usart); +#if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E) +void usart_drive_DTR_pin_low(Usart *p_usart); +void usart_drive_DTR_pin_high(Usart *p_usart); +#endif +void usart_drive_RTS_pin_low(Usart *p_usart); +void usart_drive_RTS_pin_high(Usart *p_usart); +void usart_spi_force_chip_select(Usart *p_usart); +void usart_spi_release_chip_select(Usart *p_usart); +uint32_t usart_is_tx_ready(Usart *p_usart); +uint32_t usart_is_tx_empty(Usart *p_usart); +uint32_t usart_is_rx_ready(Usart *p_usart); +uint32_t usart_write(Usart *p_usart, uint32_t c); +uint32_t usart_putchar(Usart *p_usart, uint32_t c); +void usart_write_line(Usart *p_usart, const char *string); +uint32_t usart_read(Usart *p_usart, uint32_t *c); +uint32_t usart_getchar(Usart *p_usart, uint32_t *c); +#if (SAM3XA || SAM3U) +uint32_t *usart_get_tx_access(Usart *p_usart); +uint32_t *usart_get_rx_access(Usart *p_usart); +#endif +#if (!SAM4L && !SAMV71 && !SAMV70 && !SAME70 && !SAMS70) +Pdc *usart_get_pdc_base(Usart *p_usart); +#endif +void usart_enable_writeprotect(Usart *p_usart); +void usart_disable_writeprotect(Usart *p_usart); +uint32_t usart_get_writeprotect_status(Usart *p_usart); +#if (SAM3S || SAM4S || SAM3U || SAM3XA || SAM4L || SAM4E || SAM4C || SAM4CP || SAM4CM || SAMV70 || SAMV71 || SAMS70 || SAME70) +void usart_man_set_tx_pre_len(Usart *p_usart, uint8_t uc_len); +void usart_man_set_tx_pre_pattern(Usart *p_usart, uint8_t uc_pattern); +void usart_man_set_tx_polarity(Usart *p_usart, uint8_t uc_polarity); +void usart_man_set_rx_pre_len(Usart *p_usart, uint8_t uc_len); +void usart_man_set_rx_pre_pattern(Usart *p_usart, uint8_t uc_pattern); +void usart_man_set_rx_polarity(Usart *p_usart, uint8_t uc_polarity); +void usart_man_enable_drift_compensation(Usart *p_usart); +void usart_man_disable_drift_compensation(Usart *p_usart); +#endif + +#if SAM4L +uint32_t usart_get_version(Usart *p_usart); +#endif + +#if SAMG55 +void usart_set_sleepwalking(Usart *p_uart, uint8_t ul_low_value, + bool cmpmode, bool cmppar, uint8_t ul_high_value); +#endif + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +//! @} + +/** + * \page sam_usart_quickstart Quick start guide for the SAM USART module + * + * This is the quick start guide for the \ref group_sam_drivers_usart + * "USART module", with step-by-step instructions on how to configure and + * use the driver in a selection of use cases. + * + * The use cases contain several code fragments. The code fragments in the + * steps for setup can be copied into a custom initialization function, while + * the steps for usage can be copied into, e.g., the main application function. + * + * \note Some SAM devices contain both USART and UART modules, with the latter + * being a subset in functionality of the former but physically separate + * peripherals. UART modules are compatible with the USART driver, but + * only for the functions and modes supported by the base UART driver. + * + * \section usart_use_cases USART use cases + * - \ref usart_basic_use_case + * - \subpage usart_use_case_1 + * - \subpage usart_use_case_2 + * + * \note The USART pins configuration are not included here. Please refer + * the related code in board_init() function. + * + * \section usart_basic_use_case Basic use case - transmit a character + * In this use case, the USART module is configured for: + * - Using USART0 + * - Baudrate: 9600 + * - Character length: 8 bit + * - Parity mode: Disabled + * - Stop bit: None + * - RS232 mode + * + * \section usart_basic_use_case_setup Setup steps + * + * \subsection usart_basic_use_case_setup_prereq Prerequisites + * -# \ref sysclk_group "System Clock Management (sysclock)" + * -# \ref ioport_group "Common IOPORT API (ioport)" + * + * \subsection usart_basic_use_case_setup_code Example code + * The following configuration must be added to the project (typically to a + * conf_usart.h file, but it can also be added to your main application file.) + * \code + #define USART_SERIAL USART0 + #define USART_SERIAL_ID ID_USART0 //USART0 for sam4l + #define USART_SERIAL_BAUDRATE 9600 + #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT + #define USART_SERIAL_PARITY US_MR_PAR_NO + #define USART_SERIAL_STOP_BIT US_MR_NBSTOP_1_BIT +\endcode + * + * Add to application initialization: + * \code + sysclk_init(); + + board_init(); + + const sam_usart_opt_t usart_console_settings = { + USART_SERIAL_BAUDRATE, + USART_SERIAL_CHAR_LENGTH, + USART_SERIAL_PARITY, + USART_SERIAL_STOP_BIT, + US_MR_CHMODE_NORMAL + }; + #if SAM4L + sysclk_enable_peripheral_clock(USART_SERIAL); + #else + sysclk_enable_peripheral_clock(USART_SERIAL_ID); + #endif + usart_init_rs232(USART_SERIAL, &usart_console_settings, + sysclk_get_main_hz()); + usart_enable_tx(USART_SERIAL); + usart_enable_rx(USART_SERIAL); +\endcode + * + * \subsection usart_basic_use_case_setup_flow Workflow + * -# Initialize system clock: + * \code + sysclk_init(); +\endcode + * -# Configure the USART Tx and Rx pins by call the board init function: + * \code + board_init(); +\endcode + * \note Set the following define in conf_board.h file to enable COM port,it will be used in + * board_init() function to set up IOPorts for the USART pins. + * For SAM4L: + * \code + #define CONF_BOARD_COM_PORT +\endcode + * For other SAM devices: + * \code + #define CONF_BOARD_UART_CONSOLE +\endcode + * -# Create USART options struct: + * \code + const sam_usart_opt_t usart_console_settings = { + USART_SERIAL_BAUDRATE, + USART_SERIAL_CHAR_LENGTH, + USART_SERIAL_PARITY, + USART_SERIAL_STOP_BIT, + US_MR_CHMODE_NORMAL + }; +\endcode + * -# Enable the clock to the USART module: + * \code + #if SAM4L + sysclk_enable_peripheral_clock(USART_SERIAL); + #else + sysclk_enable_peripheral_clock(USART_SERIAL_ID); + #endif +\endcode + * -# Initialize the USART module in RS232 mode: + * \code + usart_init_rs232(USART_SERIAL, &usart_console_settings, + sysclk_get_main_hz()); +\endcode + * -# Enable the Rx and Tx modes of the USART module: + * \code + usart_enable_tx(USART_SERIAL); + usart_enable_rx(USART_SERIAL); +\endcode + * + * \section usart_basic_use_case_usage Usage steps + * + * \subsection usart_basic_use_case_usage_code Example code + * Add to application C-file: + * \code + usart_putchar(USART_SERIAL, 'a'); +\endcode + * + * \subsection usart_basic_use_case_usage_flow Workflow + * -# Send an 'a' character via USART + * \code usart_putchar(USART_SERIAL, 'a'); \endcode + */ + +/** + * \page usart_use_case_1 USART receive character and echo back + * + * In this use case, the USART module is configured for: + * - Using USART0 + * - Baudrate: 9600 + * - Character length: 8 bit + * - Parity mode: Disabled + * - Stop bit: None + * - RS232 mode + * + * The use case waits for a received character on the configured USART and + * echoes the character back to the same USART. + * + * \section usart_use_case_1_setup Setup steps + * + * \subsection usart_use_case_1_setup_prereq Prerequisites + * -# \ref sysclk_group "System Clock Management (sysclock)" + * -# \ref ioport_group "Common IOPORT API (ioport)" + * + * \subsection usart_use_case_1_setup_code Example code + * The following configuration must be added to the project (typically to a + * conf_usart.h file, but it can also be added to your main application file.): + * \code + #define USART_SERIAL USART0 + #define USART_SERIAL_ID ID_USART0 //USART0 for sam4l + #define USART_SERIAL_BAUDRATE 9600 + #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT + #define USART_SERIAL_PARITY US_MR_PAR_NO + #define USART_SERIAL_STOP_BIT US_MR_NBSTOP_1_BIT +\endcode + * + * A variable for the received byte must be added: + * \code + uint32_t received_byte; +\endcode + * + * Add to application initialization: + * \code + sysclk_init(); + + board_init(); + + const sam_usart_opt_t usart_console_settings = { + USART_SERIAL_BAUDRATE, + USART_SERIAL_CHAR_LENGTH, + USART_SERIAL_PARITY, + USART_SERIAL_STOP_BIT, + US_MR_CHMODE_NORMAL + }; + + #if SAM4L + sysclk_enable_peripheral_clock(USART_SERIAL); + #else + sysclk_enable_peripheral_clock(USART_SERIAL_ID); + #endif + + usart_init_rs232(USART_SERIAL, &usart_console_settings, + sysclk_get_main_hz()); + usart_enable_tx(USART_SERIAL); + usart_enable_rx(USART_SERIAL); +\endcode + * + * \subsection usart_use_case_1_setup_flow Workflow + * -# Initialize system clock: + * \code + sysclk_init(); +\endcode + * -# Configure the USART Tx and Rx pins by call the board init function: + * \code + board_init(); +\endcode + * \note Set the following define in conf_board.h file to enable COM port,it will be used in + * board_init() function to set up IOPorts for the USART pins. + * For SAM4L: + * \code + #define CONF_BOARD_COM_PORT +\endcode + * For other SAM devices: + * \code + #define CONF_BOARD_UART_CONSOLE +\endcode + * -# Create USART options struct: + * \code + const sam_usart_opt_t usart_console_settings = { + USART_SERIAL_BAUDRATE, + USART_SERIAL_CHAR_LENGTH, + USART_SERIAL_PARITY, + USART_SERIAL_STOP_BIT, + US_MR_CHMODE_NORMAL + }; +\endcode + * -# Enable the clock to the USART module: + * \code + #if SAM4L + sysclk_enable_peripheral_clock(USART_SERIAL); + #else + sysclk_enable_peripheral_clock(USART_SERIAL_ID); + #endif +\endcode + * -# Initialize the USART module in RS232 mode: + * \code + usart_init_rs232(USART_SERIAL, &usart_console_settings, + sysclk_get_main_hz()); +\endcode + * -# Enable the Rx and Tx modes of the USART module: + * \code + usart_enable_tx(USART_SERIAL); + usart_enable_rx(USART_SERIAL); +\endcode + * + * \section usart_use_case_1_usage Usage steps + * + * \subsection usart_use_case_1_usage_code Example code + * Add to, e.g., main loop in application C-file: + * \code + received_byte = usart_getchar(USART_SERIAL); + usart_putchar(USART_SERIAL, received_byte); +\endcode + * + * \subsection usart_use_case_1_usage_flow Workflow + * -# Wait for reception of a character: + * \code usart_getchar(USART_SERIAL, &received_byte); \endcode + * -# Echo the character back: + * \code usart_putchar(USART_SERIAL, received_byte); \endcode + */ + +/** + * \page usart_use_case_2 USART receive character and echo back via interrupts + * + * In this use case, the USART module is configured for: + * - Using USART0 + * - Baudrate: 9600 + * - Character length: 8 bit + * - Parity mode: Disabled + * - Stop bit: None + * - RS232 mode + * + * The use case waits for a received character on the configured USART and + * echoes the character back to the same USART. The character reception is + * performed via an interrupt handler, rather than the polling method used + * in \ref usart_use_case_1. + * + * \section usart_use_case_2_setup Setup steps + * + * \subsection usart_use_case_2_setup_prereq Prerequisites + * -# \ref sysclk_group "System Clock Management (sysclock)" + * -# \ref pio_group "Parallel Input/Output Controller (pio)" + * -# \ref pmc_group "Power Management Controller (pmc)" + * + * \subsection usart_use_case_2_setup_code Example code + * The following configuration must be added to the project (typically to a + * conf_usart.h file, but it can also be added to your main application file.): + * \code + #define USART_SERIAL USART0 + #define USART_SERIAL_ID ID_USART0 //USART0 for sam4l + #define USART_SERIAL_ISR_HANDLER USART0_Handler + #define USART_SERIAL_BAUDRATE 9600 + #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT + #define USART_SERIAL_PARITY US_MR_PAR_NO + #define USART_SERIAL_STOP_BIT US_MR_NBSTOP_1_BIT +\endcode + * + * A variable for the received byte must be added: + * \code + uint32_t received_byte; +\endcode + * + * Add to application initialization: + * \code + sysclk_init(); + + board_init(); + + const sam_usart_opt_t usart_console_settings = { + USART_SERIAL_BAUDRATE, + USART_SERIAL_CHAR_LENGTH, + USART_SERIAL_PARITY, + USART_SERIAL_STOP_BIT, + US_MR_CHMODE_NORMAL + }; + + #if SAM4L + sysclk_enable_peripheral_clock(USART_SERIAL); + #else + sysclk_enable_peripheral_clock(USART_SERIAL_ID); + #endif + + usart_init_rs232(USART_SERIAL, &usart_console_settings, + sysclk_get_main_hz()); + usart_enable_tx(USART_SERIAL); + usart_enable_rx(USART_SERIAL); + + usart_enable_interrupt(USART_SERIAL, US_IER_RXRDY); + NVIC_EnableIRQ(USART_SERIAL_IRQ); +\endcode + * + * \subsection usart_use_case_2_setup_flow Workflow + * -# Initialize system clock: + * \code + sysclk_init(); +\endcode + * -# Configure the USART Tx and Rx pins by call the board init function: + * \code + board_init(); +\endcode + * \note Set the following define in conf_board.h file to enable COM port,it will be used in + * board_init() function to set up IOPorts for the USART pins. + * For SAM4L: + * \code + #define CONF_BOARD_COM_PORT +\endcode + * For other SAM devices: + * \code + #define CONF_BOARD_UART_CONSOLE +\endcode + * -# Create USART options struct: + * \code + const sam_usart_opt_t usart_console_settings = { + USART_SERIAL_BAUDRATE, + USART_SERIAL_CHAR_LENGTH, + USART_SERIAL_PARITY, + USART_SERIAL_STOP_BIT, + US_MR_CHMODE_NORMAL + }; +\endcode + * -# Enable the clock to the USART module: + * \code + #if SAM4L + sysclk_enable_peripheral_clock(USART_SERIAL); + #else + sysclk_enable_peripheral_clock(USART_SERIAL_ID); + #endif +\endcode + * -# Initialize the USART module in RS232 mode: + * \code + usart_init_rs232(USART_SERIAL, &usart_console_settings, + sysclk_get_main_hz()); +\endcode + * -# Enable the Rx and Tx modes of the USART module: + * \code + usart_enable_tx(USART_SERIAL); + usart_enable_rx(USART_SERIAL); +\endcode + * -# Enable the USART character reception interrupt, and general interrupts + * for the USART module. + * \code + usart_enable_interrupt(USART_SERIAL, US_IER_RXRDY); + NVIC_EnableIRQ(USART_SERIAL_IRQ); +\endcode + * \section usart_use_case_2_usage Usage steps + * + * \subsection usart_use_case_2_usage_code Example code + * Add to your main application C-file the USART interrupt handler: + * \code + void USART_SERIAL_ISR_HANDLER(void) + { + uint32_t dw_status = usart_get_status(USART_SERIAL); + + if (dw_status & US_CSR_RXRDY) { + uint32_t received_byte; + + usart_read(USART_SERIAL, &received_byte); + usart_write(USART_SERIAL, received_byte); + } + } +\endcode + * + * \subsection usart_use_case_2_usage_flow Workflow + * -# When the USART ISR fires, retrieve the USART module interrupt flags: + * \code uint32_t dw_status = usart_get_status(USART_SERIAL); \endcode + * -# Check if the USART Receive Character interrupt has fired: + * \code if (dw_status & US_CSR_RXRDY) \endcode + * -# If a character has been received, fetch it into a temporary variable: + * \code usart_read(USART_SERIAL, &received_byte); \endcode + * -# Echo the character back: + * \code usart_write(USART_SERIAL, received_byte); \endcode + */ + +#endif /* USART_H_INCLUDED */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h new file mode 100644 index 0000000..f8a2771 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_adc.h @@ -0,0 +1,519 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_ADC_COMPONENT_ +#define _SAM3XA_ADC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Analog-to-digital Converter */ +/* ============================================================================= */ +/** \addtogroup SAM3XA_ADC Analog-to-digital Converter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Adc hardware registers */ +typedef struct { + WoReg ADC_CR; /**< \brief (Adc Offset: 0x00) Control Register */ + RwReg ADC_MR; /**< \brief (Adc Offset: 0x04) Mode Register */ + RwReg ADC_SEQR1; /**< \brief (Adc Offset: 0x08) Channel Sequence Register 1 */ + RwReg ADC_SEQR2; /**< \brief (Adc Offset: 0x0C) Channel Sequence Register 2 */ + WoReg ADC_CHER; /**< \brief (Adc Offset: 0x10) Channel Enable Register */ + WoReg ADC_CHDR; /**< \brief (Adc Offset: 0x14) Channel Disable Register */ + RoReg ADC_CHSR; /**< \brief (Adc Offset: 0x18) Channel Status Register */ + RoReg Reserved1[1]; + RoReg ADC_LCDR; /**< \brief (Adc Offset: 0x20) Last Converted Data Register */ + WoReg ADC_IER; /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */ + WoReg ADC_IDR; /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */ + RoReg ADC_IMR; /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */ + RoReg ADC_ISR; /**< \brief (Adc Offset: 0x30) Interrupt Status Register */ + RoReg Reserved2[2]; + RoReg ADC_OVER; /**< \brief (Adc Offset: 0x3C) Overrun Status Register */ + RwReg ADC_EMR; /**< \brief (Adc Offset: 0x40) Extended Mode Register */ + RwReg ADC_CWR; /**< \brief (Adc Offset: 0x44) Compare Window Register */ + RwReg ADC_CGR; /**< \brief (Adc Offset: 0x48) Channel Gain Register */ + RwReg ADC_COR; /**< \brief (Adc Offset: 0x4C) Channel Offset Register */ + RoReg ADC_CDR[16]; /**< \brief (Adc Offset: 0x50) Channel Data Register */ + RoReg Reserved3[1]; + RwReg ADC_ACR; /**< \brief (Adc Offset: 0x94) Analog Control Register */ + RoReg Reserved4[19]; + RwReg ADC_WPMR; /**< \brief (Adc Offset: 0xE4) Write Protect Mode Register */ + RoReg ADC_WPSR; /**< \brief (Adc Offset: 0xE8) Write Protect Status Register */ + RoReg Reserved5[5]; + RwReg ADC_RPR; /**< \brief (Adc Offset: 0x100) Receive Pointer Register */ + RwReg ADC_RCR; /**< \brief (Adc Offset: 0x104) Receive Counter Register */ + RoReg Reserved6[2]; + RwReg ADC_RNPR; /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */ + RwReg ADC_RNCR; /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */ + RoReg Reserved7[2]; + WoReg ADC_PTCR; /**< \brief (Adc Offset: 0x120) Transfer Control Register */ + RoReg ADC_PTSR; /**< \brief (Adc Offset: 0x124) Transfer Status Register */ +} Adc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */ +#define ADC_CR_SWRST (0x1u << 0) /**< \brief (ADC_CR) Software Reset */ +#define ADC_CR_START (0x1u << 1) /**< \brief (ADC_CR) Start Conversion */ +/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */ +#define ADC_MR_TRGEN (0x1u << 0) /**< \brief (ADC_MR) Trigger Enable */ +#define ADC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */ +#define ADC_MR_TRGEN_EN (0x1u << 0) /**< \brief (ADC_MR) Hardware trigger selected by TRGSEL field is enabled. */ +#define ADC_MR_TRGSEL_Pos 1 +#define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos) /**< \brief (ADC_MR) Trigger Selection */ +#define ADC_MR_TRGSEL_ADC_TRIG0 (0x0u << 1) /**< \brief (ADC_MR) External : ADCTRG */ +#define ADC_MR_TRGSEL_ADC_TRIG1 (0x1u << 1) /**< \brief (ADC_MR) TIOA Output of the Timer Counter Channel 0 */ +#define ADC_MR_TRGSEL_ADC_TRIG2 (0x2u << 1) /**< \brief (ADC_MR) TIOA Output of the Timer Counter Channel 1 */ +#define ADC_MR_TRGSEL_ADC_TRIG3 (0x3u << 1) /**< \brief (ADC_MR) TIOA Output of the Timer Counter Channel 2 */ +#define ADC_MR_TRGSEL_ADC_TRIG4 (0x4u << 1) /**< \brief (ADC_MR) PWM Event Line 0 */ +#define ADC_MR_TRGSEL_ADC_TRIG5 (0x5u << 1) /**< \brief (ADC_MR) PWM Event Line 0 */ +#define ADC_MR_LOWRES (0x1u << 4) /**< \brief (ADC_MR) Resolution */ +#define ADC_MR_LOWRES_BITS_12 (0x0u << 4) /**< \brief (ADC_MR) 12-bit resolution */ +#define ADC_MR_LOWRES_BITS_10 (0x1u << 4) /**< \brief (ADC_MR) 10-bit resolution */ +#define ADC_MR_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode */ +#define ADC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (ADC_MR) Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions */ +#define ADC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions */ +#define ADC_MR_FWUP (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up */ +#define ADC_MR_FWUP_OFF (0x0u << 6) /**< \brief (ADC_MR) Normal Sleep Mode: The sleep mode is defined by the SLEEP bit */ +#define ADC_MR_FWUP_ON (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF */ +#define ADC_MR_FREERUN (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode */ +#define ADC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (ADC_MR) Normal Mode */ +#define ADC_MR_FREERUN_ON (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode: Never wait for any trigger. */ +#define ADC_MR_PRESCAL_Pos 8 +#define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos) /**< \brief (ADC_MR) Prescaler Rate Selection */ +#define ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos))) +#define ADC_MR_STARTUP_Pos 16 +#define ADC_MR_STARTUP_Msk (0xfu << ADC_MR_STARTUP_Pos) /**< \brief (ADC_MR) Start Up Time */ +#define ADC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (ADC_MR) 0 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (ADC_MR) 8 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (ADC_MR) 16 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (ADC_MR) 24 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (ADC_MR) 64 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (ADC_MR) 80 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (ADC_MR) 96 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (ADC_MR) 112 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (ADC_MR) 512 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (ADC_MR) 576 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (ADC_MR) 640 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (ADC_MR) 704 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (ADC_MR) 768 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (ADC_MR) 832 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (ADC_MR) 896 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (ADC_MR) 960 periods of ADCClock */ +#define ADC_MR_SETTLING_Pos 20 +#define ADC_MR_SETTLING_Msk (0x3u << ADC_MR_SETTLING_Pos) /**< \brief (ADC_MR) Analog Settling Time */ +#define ADC_MR_SETTLING_AST3 (0x0u << 20) /**< \brief (ADC_MR) 3 periods of ADCClock */ +#define ADC_MR_SETTLING_AST5 (0x1u << 20) /**< \brief (ADC_MR) 5 periods of ADCClock */ +#define ADC_MR_SETTLING_AST9 (0x2u << 20) /**< \brief (ADC_MR) 9 periods of ADCClock */ +#define ADC_MR_SETTLING_AST17 (0x3u << 20) /**< \brief (ADC_MR) 17 periods of ADCClock */ +#define ADC_MR_ANACH (0x1u << 23) /**< \brief (ADC_MR) Analog Change */ +#define ADC_MR_ANACH_NONE (0x0u << 23) /**< \brief (ADC_MR) No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels */ +#define ADC_MR_ANACH_ALLOWED (0x1u << 23) /**< \brief (ADC_MR) Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers */ +#define ADC_MR_TRACKTIM_Pos 24 +#define ADC_MR_TRACKTIM_Msk (0xfu << ADC_MR_TRACKTIM_Pos) /**< \brief (ADC_MR) Tracking Time */ +#define ADC_MR_TRACKTIM(value) ((ADC_MR_TRACKTIM_Msk & ((value) << ADC_MR_TRACKTIM_Pos))) +#define ADC_MR_TRANSFER_Pos 28 +#define ADC_MR_TRANSFER_Msk (0x3u << ADC_MR_TRANSFER_Pos) /**< \brief (ADC_MR) Transfer Period */ +#define ADC_MR_TRANSFER(value) ((ADC_MR_TRANSFER_Msk & ((value) << ADC_MR_TRANSFER_Pos))) +#define ADC_MR_USEQ (0x1u << 31) /**< \brief (ADC_MR) Use Sequence Enable */ +#define ADC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (ADC_MR) Normal Mode: The controller converts channels in a simple numeric order. */ +#define ADC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (ADC_MR) User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers. */ +/* -------- ADC_SEQR1 : (ADC Offset: 0x08) Channel Sequence Register 1 -------- */ +#define ADC_SEQR1_USCH1_Pos 0 +#define ADC_SEQR1_USCH1_Msk (0xfu << ADC_SEQR1_USCH1_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 1 */ +#define ADC_SEQR1_USCH1(value) ((ADC_SEQR1_USCH1_Msk & ((value) << ADC_SEQR1_USCH1_Pos))) +#define ADC_SEQR1_USCH2_Pos 4 +#define ADC_SEQR1_USCH2_Msk (0xfu << ADC_SEQR1_USCH2_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 2 */ +#define ADC_SEQR1_USCH2(value) ((ADC_SEQR1_USCH2_Msk & ((value) << ADC_SEQR1_USCH2_Pos))) +#define ADC_SEQR1_USCH3_Pos 8 +#define ADC_SEQR1_USCH3_Msk (0xfu << ADC_SEQR1_USCH3_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 3 */ +#define ADC_SEQR1_USCH3(value) ((ADC_SEQR1_USCH3_Msk & ((value) << ADC_SEQR1_USCH3_Pos))) +#define ADC_SEQR1_USCH4_Pos 12 +#define ADC_SEQR1_USCH4_Msk (0xfu << ADC_SEQR1_USCH4_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 4 */ +#define ADC_SEQR1_USCH4(value) ((ADC_SEQR1_USCH4_Msk & ((value) << ADC_SEQR1_USCH4_Pos))) +#define ADC_SEQR1_USCH5_Pos 16 +#define ADC_SEQR1_USCH5_Msk (0xfu << ADC_SEQR1_USCH5_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 5 */ +#define ADC_SEQR1_USCH5(value) ((ADC_SEQR1_USCH5_Msk & ((value) << ADC_SEQR1_USCH5_Pos))) +#define ADC_SEQR1_USCH6_Pos 20 +#define ADC_SEQR1_USCH6_Msk (0xfu << ADC_SEQR1_USCH6_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 6 */ +#define ADC_SEQR1_USCH6(value) ((ADC_SEQR1_USCH6_Msk & ((value) << ADC_SEQR1_USCH6_Pos))) +#define ADC_SEQR1_USCH7_Pos 24 +#define ADC_SEQR1_USCH7_Msk (0xfu << ADC_SEQR1_USCH7_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 7 */ +#define ADC_SEQR1_USCH7(value) ((ADC_SEQR1_USCH7_Msk & ((value) << ADC_SEQR1_USCH7_Pos))) +#define ADC_SEQR1_USCH8_Pos 28 +#define ADC_SEQR1_USCH8_Msk (0xfu << ADC_SEQR1_USCH8_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 8 */ +#define ADC_SEQR1_USCH8(value) ((ADC_SEQR1_USCH8_Msk & ((value) << ADC_SEQR1_USCH8_Pos))) +/* -------- ADC_SEQR2 : (ADC Offset: 0x0C) Channel Sequence Register 2 -------- */ +#define ADC_SEQR2_USCH9_Pos 0 +#define ADC_SEQR2_USCH9_Msk (0xfu << ADC_SEQR2_USCH9_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 9 */ +#define ADC_SEQR2_USCH9(value) ((ADC_SEQR2_USCH9_Msk & ((value) << ADC_SEQR2_USCH9_Pos))) +#define ADC_SEQR2_USCH10_Pos 4 +#define ADC_SEQR2_USCH10_Msk (0xfu << ADC_SEQR2_USCH10_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 10 */ +#define ADC_SEQR2_USCH10(value) ((ADC_SEQR2_USCH10_Msk & ((value) << ADC_SEQR2_USCH10_Pos))) +#define ADC_SEQR2_USCH11_Pos 8 +#define ADC_SEQR2_USCH11_Msk (0xfu << ADC_SEQR2_USCH11_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 11 */ +#define ADC_SEQR2_USCH11(value) ((ADC_SEQR2_USCH11_Msk & ((value) << ADC_SEQR2_USCH11_Pos))) +#define ADC_SEQR2_USCH12_Pos 12 +#define ADC_SEQR2_USCH12_Msk (0xfu << ADC_SEQR2_USCH12_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 12 */ +#define ADC_SEQR2_USCH12(value) ((ADC_SEQR2_USCH12_Msk & ((value) << ADC_SEQR2_USCH12_Pos))) +#define ADC_SEQR2_USCH13_Pos 16 +#define ADC_SEQR2_USCH13_Msk (0xfu << ADC_SEQR2_USCH13_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 13 */ +#define ADC_SEQR2_USCH13(value) ((ADC_SEQR2_USCH13_Msk & ((value) << ADC_SEQR2_USCH13_Pos))) +#define ADC_SEQR2_USCH14_Pos 20 +#define ADC_SEQR2_USCH14_Msk (0xfu << ADC_SEQR2_USCH14_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 14 */ +#define ADC_SEQR2_USCH14(value) ((ADC_SEQR2_USCH14_Msk & ((value) << ADC_SEQR2_USCH14_Pos))) +#define ADC_SEQR2_USCH15_Pos 24 +#define ADC_SEQR2_USCH15_Msk (0xfu << ADC_SEQR2_USCH15_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 15 */ +#define ADC_SEQR2_USCH15(value) ((ADC_SEQR2_USCH15_Msk & ((value) << ADC_SEQR2_USCH15_Pos))) +#define ADC_SEQR2_USCH16_Pos 28 +#define ADC_SEQR2_USCH16_Msk (0xfu << ADC_SEQR2_USCH16_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 16 */ +#define ADC_SEQR2_USCH16(value) ((ADC_SEQR2_USCH16_Msk & ((value) << ADC_SEQR2_USCH16_Pos))) +/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */ +#define ADC_CHER_CH0 (0x1u << 0) /**< \brief (ADC_CHER) Channel 0 Enable */ +#define ADC_CHER_CH1 (0x1u << 1) /**< \brief (ADC_CHER) Channel 1 Enable */ +#define ADC_CHER_CH2 (0x1u << 2) /**< \brief (ADC_CHER) Channel 2 Enable */ +#define ADC_CHER_CH3 (0x1u << 3) /**< \brief (ADC_CHER) Channel 3 Enable */ +#define ADC_CHER_CH4 (0x1u << 4) /**< \brief (ADC_CHER) Channel 4 Enable */ +#define ADC_CHER_CH5 (0x1u << 5) /**< \brief (ADC_CHER) Channel 5 Enable */ +#define ADC_CHER_CH6 (0x1u << 6) /**< \brief (ADC_CHER) Channel 6 Enable */ +#define ADC_CHER_CH7 (0x1u << 7) /**< \brief (ADC_CHER) Channel 7 Enable */ +#define ADC_CHER_CH8 (0x1u << 8) /**< \brief (ADC_CHER) Channel 8 Enable */ +#define ADC_CHER_CH9 (0x1u << 9) /**< \brief (ADC_CHER) Channel 9 Enable */ +#define ADC_CHER_CH10 (0x1u << 10) /**< \brief (ADC_CHER) Channel 10 Enable */ +#define ADC_CHER_CH11 (0x1u << 11) /**< \brief (ADC_CHER) Channel 11 Enable */ +#define ADC_CHER_CH12 (0x1u << 12) /**< \brief (ADC_CHER) Channel 12 Enable */ +#define ADC_CHER_CH13 (0x1u << 13) /**< \brief (ADC_CHER) Channel 13 Enable */ +#define ADC_CHER_CH14 (0x1u << 14) /**< \brief (ADC_CHER) Channel 14 Enable */ +#define ADC_CHER_CH15 (0x1u << 15) /**< \brief (ADC_CHER) Channel 15 Enable */ +/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */ +#define ADC_CHDR_CH0 (0x1u << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */ +#define ADC_CHDR_CH1 (0x1u << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */ +#define ADC_CHDR_CH2 (0x1u << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */ +#define ADC_CHDR_CH3 (0x1u << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */ +#define ADC_CHDR_CH4 (0x1u << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */ +#define ADC_CHDR_CH5 (0x1u << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */ +#define ADC_CHDR_CH6 (0x1u << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */ +#define ADC_CHDR_CH7 (0x1u << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */ +#define ADC_CHDR_CH8 (0x1u << 8) /**< \brief (ADC_CHDR) Channel 8 Disable */ +#define ADC_CHDR_CH9 (0x1u << 9) /**< \brief (ADC_CHDR) Channel 9 Disable */ +#define ADC_CHDR_CH10 (0x1u << 10) /**< \brief (ADC_CHDR) Channel 10 Disable */ +#define ADC_CHDR_CH11 (0x1u << 11) /**< \brief (ADC_CHDR) Channel 11 Disable */ +#define ADC_CHDR_CH12 (0x1u << 12) /**< \brief (ADC_CHDR) Channel 12 Disable */ +#define ADC_CHDR_CH13 (0x1u << 13) /**< \brief (ADC_CHDR) Channel 13 Disable */ +#define ADC_CHDR_CH14 (0x1u << 14) /**< \brief (ADC_CHDR) Channel 14 Disable */ +#define ADC_CHDR_CH15 (0x1u << 15) /**< \brief (ADC_CHDR) Channel 15 Disable */ +/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */ +#define ADC_CHSR_CH0 (0x1u << 0) /**< \brief (ADC_CHSR) Channel 0 Status */ +#define ADC_CHSR_CH1 (0x1u << 1) /**< \brief (ADC_CHSR) Channel 1 Status */ +#define ADC_CHSR_CH2 (0x1u << 2) /**< \brief (ADC_CHSR) Channel 2 Status */ +#define ADC_CHSR_CH3 (0x1u << 3) /**< \brief (ADC_CHSR) Channel 3 Status */ +#define ADC_CHSR_CH4 (0x1u << 4) /**< \brief (ADC_CHSR) Channel 4 Status */ +#define ADC_CHSR_CH5 (0x1u << 5) /**< \brief (ADC_CHSR) Channel 5 Status */ +#define ADC_CHSR_CH6 (0x1u << 6) /**< \brief (ADC_CHSR) Channel 6 Status */ +#define ADC_CHSR_CH7 (0x1u << 7) /**< \brief (ADC_CHSR) Channel 7 Status */ +#define ADC_CHSR_CH8 (0x1u << 8) /**< \brief (ADC_CHSR) Channel 8 Status */ +#define ADC_CHSR_CH9 (0x1u << 9) /**< \brief (ADC_CHSR) Channel 9 Status */ +#define ADC_CHSR_CH10 (0x1u << 10) /**< \brief (ADC_CHSR) Channel 10 Status */ +#define ADC_CHSR_CH11 (0x1u << 11) /**< \brief (ADC_CHSR) Channel 11 Status */ +#define ADC_CHSR_CH12 (0x1u << 12) /**< \brief (ADC_CHSR) Channel 12 Status */ +#define ADC_CHSR_CH13 (0x1u << 13) /**< \brief (ADC_CHSR) Channel 13 Status */ +#define ADC_CHSR_CH14 (0x1u << 14) /**< \brief (ADC_CHSR) Channel 14 Status */ +#define ADC_CHSR_CH15 (0x1u << 15) /**< \brief (ADC_CHSR) Channel 15 Status */ +/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */ +#define ADC_LCDR_LDATA_Pos 0 +#define ADC_LCDR_LDATA_Msk (0xfffu << ADC_LCDR_LDATA_Pos) /**< \brief (ADC_LCDR) Last Data Converted */ +#define ADC_LCDR_CHNB_Pos 12 +#define ADC_LCDR_CHNB_Msk (0xfu << ADC_LCDR_CHNB_Pos) /**< \brief (ADC_LCDR) Channel Number */ +/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */ +#define ADC_IER_EOC0 (0x1u << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */ +#define ADC_IER_EOC1 (0x1u << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */ +#define ADC_IER_EOC2 (0x1u << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */ +#define ADC_IER_EOC3 (0x1u << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */ +#define ADC_IER_EOC4 (0x1u << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */ +#define ADC_IER_EOC5 (0x1u << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */ +#define ADC_IER_EOC6 (0x1u << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */ +#define ADC_IER_EOC7 (0x1u << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */ +#define ADC_IER_EOC8 (0x1u << 8) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 8 */ +#define ADC_IER_EOC9 (0x1u << 9) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 9 */ +#define ADC_IER_EOC10 (0x1u << 10) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 10 */ +#define ADC_IER_EOC11 (0x1u << 11) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 11 */ +#define ADC_IER_EOC12 (0x1u << 12) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 12 */ +#define ADC_IER_EOC13 (0x1u << 13) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 13 */ +#define ADC_IER_EOC14 (0x1u << 14) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 14 */ +#define ADC_IER_EOC15 (0x1u << 15) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 15 */ +#define ADC_IER_DRDY (0x1u << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */ +#define ADC_IER_GOVRE (0x1u << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */ +#define ADC_IER_COMPE (0x1u << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */ +#define ADC_IER_ENDRX (0x1u << 27) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */ +#define ADC_IER_RXBUFF (0x1u << 28) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */ +/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */ +#define ADC_IDR_EOC0 (0x1u << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */ +#define ADC_IDR_EOC1 (0x1u << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */ +#define ADC_IDR_EOC2 (0x1u << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */ +#define ADC_IDR_EOC3 (0x1u << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */ +#define ADC_IDR_EOC4 (0x1u << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */ +#define ADC_IDR_EOC5 (0x1u << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */ +#define ADC_IDR_EOC6 (0x1u << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */ +#define ADC_IDR_EOC7 (0x1u << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */ +#define ADC_IDR_EOC8 (0x1u << 8) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 8 */ +#define ADC_IDR_EOC9 (0x1u << 9) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 9 */ +#define ADC_IDR_EOC10 (0x1u << 10) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 10 */ +#define ADC_IDR_EOC11 (0x1u << 11) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 11 */ +#define ADC_IDR_EOC12 (0x1u << 12) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 12 */ +#define ADC_IDR_EOC13 (0x1u << 13) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 13 */ +#define ADC_IDR_EOC14 (0x1u << 14) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 14 */ +#define ADC_IDR_EOC15 (0x1u << 15) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 15 */ +#define ADC_IDR_DRDY (0x1u << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */ +#define ADC_IDR_GOVRE (0x1u << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */ +#define ADC_IDR_COMPE (0x1u << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */ +#define ADC_IDR_ENDRX (0x1u << 27) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */ +#define ADC_IDR_RXBUFF (0x1u << 28) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */ +/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */ +#define ADC_IMR_EOC0 (0x1u << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */ +#define ADC_IMR_EOC1 (0x1u << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */ +#define ADC_IMR_EOC2 (0x1u << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */ +#define ADC_IMR_EOC3 (0x1u << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */ +#define ADC_IMR_EOC4 (0x1u << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */ +#define ADC_IMR_EOC5 (0x1u << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */ +#define ADC_IMR_EOC6 (0x1u << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */ +#define ADC_IMR_EOC7 (0x1u << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */ +#define ADC_IMR_EOC8 (0x1u << 8) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 8 */ +#define ADC_IMR_EOC9 (0x1u << 9) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 9 */ +#define ADC_IMR_EOC10 (0x1u << 10) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 10 */ +#define ADC_IMR_EOC11 (0x1u << 11) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 11 */ +#define ADC_IMR_EOC12 (0x1u << 12) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 12 */ +#define ADC_IMR_EOC13 (0x1u << 13) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 13 */ +#define ADC_IMR_EOC14 (0x1u << 14) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 14 */ +#define ADC_IMR_EOC15 (0x1u << 15) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 15 */ +#define ADC_IMR_DRDY (0x1u << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */ +#define ADC_IMR_GOVRE (0x1u << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */ +#define ADC_IMR_COMPE (0x1u << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */ +#define ADC_IMR_ENDRX (0x1u << 27) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */ +#define ADC_IMR_RXBUFF (0x1u << 28) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */ +/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */ +#define ADC_ISR_EOC0 (0x1u << 0) /**< \brief (ADC_ISR) End of Conversion 0 */ +#define ADC_ISR_EOC1 (0x1u << 1) /**< \brief (ADC_ISR) End of Conversion 1 */ +#define ADC_ISR_EOC2 (0x1u << 2) /**< \brief (ADC_ISR) End of Conversion 2 */ +#define ADC_ISR_EOC3 (0x1u << 3) /**< \brief (ADC_ISR) End of Conversion 3 */ +#define ADC_ISR_EOC4 (0x1u << 4) /**< \brief (ADC_ISR) End of Conversion 4 */ +#define ADC_ISR_EOC5 (0x1u << 5) /**< \brief (ADC_ISR) End of Conversion 5 */ +#define ADC_ISR_EOC6 (0x1u << 6) /**< \brief (ADC_ISR) End of Conversion 6 */ +#define ADC_ISR_EOC7 (0x1u << 7) /**< \brief (ADC_ISR) End of Conversion 7 */ +#define ADC_ISR_EOC8 (0x1u << 8) /**< \brief (ADC_ISR) End of Conversion 8 */ +#define ADC_ISR_EOC9 (0x1u << 9) /**< \brief (ADC_ISR) End of Conversion 9 */ +#define ADC_ISR_EOC10 (0x1u << 10) /**< \brief (ADC_ISR) End of Conversion 10 */ +#define ADC_ISR_EOC11 (0x1u << 11) /**< \brief (ADC_ISR) End of Conversion 11 */ +#define ADC_ISR_EOC12 (0x1u << 12) /**< \brief (ADC_ISR) End of Conversion 12 */ +#define ADC_ISR_EOC13 (0x1u << 13) /**< \brief (ADC_ISR) End of Conversion 13 */ +#define ADC_ISR_EOC14 (0x1u << 14) /**< \brief (ADC_ISR) End of Conversion 14 */ +#define ADC_ISR_EOC15 (0x1u << 15) /**< \brief (ADC_ISR) End of Conversion 15 */ +#define ADC_ISR_DRDY (0x1u << 24) /**< \brief (ADC_ISR) Data Ready */ +#define ADC_ISR_GOVRE (0x1u << 25) /**< \brief (ADC_ISR) General Overrun Error */ +#define ADC_ISR_COMPE (0x1u << 26) /**< \brief (ADC_ISR) Comparison Error */ +#define ADC_ISR_ENDRX (0x1u << 27) /**< \brief (ADC_ISR) End of RX Buffer */ +#define ADC_ISR_RXBUFF (0x1u << 28) /**< \brief (ADC_ISR) RX Buffer Full */ +/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */ +#define ADC_OVER_OVRE0 (0x1u << 0) /**< \brief (ADC_OVER) Overrun Error 0 */ +#define ADC_OVER_OVRE1 (0x1u << 1) /**< \brief (ADC_OVER) Overrun Error 1 */ +#define ADC_OVER_OVRE2 (0x1u << 2) /**< \brief (ADC_OVER) Overrun Error 2 */ +#define ADC_OVER_OVRE3 (0x1u << 3) /**< \brief (ADC_OVER) Overrun Error 3 */ +#define ADC_OVER_OVRE4 (0x1u << 4) /**< \brief (ADC_OVER) Overrun Error 4 */ +#define ADC_OVER_OVRE5 (0x1u << 5) /**< \brief (ADC_OVER) Overrun Error 5 */ +#define ADC_OVER_OVRE6 (0x1u << 6) /**< \brief (ADC_OVER) Overrun Error 6 */ +#define ADC_OVER_OVRE7 (0x1u << 7) /**< \brief (ADC_OVER) Overrun Error 7 */ +#define ADC_OVER_OVRE8 (0x1u << 8) /**< \brief (ADC_OVER) Overrun Error 8 */ +#define ADC_OVER_OVRE9 (0x1u << 9) /**< \brief (ADC_OVER) Overrun Error 9 */ +#define ADC_OVER_OVRE10 (0x1u << 10) /**< \brief (ADC_OVER) Overrun Error 10 */ +#define ADC_OVER_OVRE11 (0x1u << 11) /**< \brief (ADC_OVER) Overrun Error 11 */ +#define ADC_OVER_OVRE12 (0x1u << 12) /**< \brief (ADC_OVER) Overrun Error 12 */ +#define ADC_OVER_OVRE13 (0x1u << 13) /**< \brief (ADC_OVER) Overrun Error 13 */ +#define ADC_OVER_OVRE14 (0x1u << 14) /**< \brief (ADC_OVER) Overrun Error 14 */ +#define ADC_OVER_OVRE15 (0x1u << 15) /**< \brief (ADC_OVER) Overrun Error 15 */ +/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */ +#define ADC_EMR_CMPMODE_Pos 0 +#define ADC_EMR_CMPMODE_Msk (0x3u << ADC_EMR_CMPMODE_Pos) /**< \brief (ADC_EMR) Comparison Mode */ +#define ADC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */ +#define ADC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */ +#define ADC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is in the comparison window. */ +#define ADC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is out of the comparison window. */ +#define ADC_EMR_CMPSEL_Pos 4 +#define ADC_EMR_CMPSEL_Msk (0xfu << ADC_EMR_CMPSEL_Pos) /**< \brief (ADC_EMR) Comparison Selected Channel */ +#define ADC_EMR_CMPSEL(value) ((ADC_EMR_CMPSEL_Msk & ((value) << ADC_EMR_CMPSEL_Pos))) +#define ADC_EMR_CMPALL (0x1u << 9) /**< \brief (ADC_EMR) Compare All Channels */ +#define ADC_EMR_CMPFILTER_Pos 12 +#define ADC_EMR_CMPFILTER_Msk (0x3u << ADC_EMR_CMPFILTER_Pos) /**< \brief (ADC_EMR) Compare Event Filtering */ +#define ADC_EMR_CMPFILTER(value) ((ADC_EMR_CMPFILTER_Msk & ((value) << ADC_EMR_CMPFILTER_Pos))) +#define ADC_EMR_TAG (0x1u << 24) /**< \brief (ADC_EMR) TAG of ADC_LDCR register */ +/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */ +#define ADC_CWR_LOWTHRES_Pos 0 +#define ADC_CWR_LOWTHRES_Msk (0xfffu << ADC_CWR_LOWTHRES_Pos) /**< \brief (ADC_CWR) Low Threshold */ +#define ADC_CWR_LOWTHRES(value) ((ADC_CWR_LOWTHRES_Msk & ((value) << ADC_CWR_LOWTHRES_Pos))) +#define ADC_CWR_HIGHTHRES_Pos 16 +#define ADC_CWR_HIGHTHRES_Msk (0xfffu << ADC_CWR_HIGHTHRES_Pos) /**< \brief (ADC_CWR) High Threshold */ +#define ADC_CWR_HIGHTHRES(value) ((ADC_CWR_HIGHTHRES_Msk & ((value) << ADC_CWR_HIGHTHRES_Pos))) +/* -------- ADC_CGR : (ADC Offset: 0x48) Channel Gain Register -------- */ +#define ADC_CGR_GAIN0_Pos 0 +#define ADC_CGR_GAIN0_Msk (0x3u << ADC_CGR_GAIN0_Pos) /**< \brief (ADC_CGR) Gain for channel 0 */ +#define ADC_CGR_GAIN0(value) ((ADC_CGR_GAIN0_Msk & ((value) << ADC_CGR_GAIN0_Pos))) +#define ADC_CGR_GAIN1_Pos 2 +#define ADC_CGR_GAIN1_Msk (0x3u << ADC_CGR_GAIN1_Pos) /**< \brief (ADC_CGR) Gain for channel 1 */ +#define ADC_CGR_GAIN1(value) ((ADC_CGR_GAIN1_Msk & ((value) << ADC_CGR_GAIN1_Pos))) +#define ADC_CGR_GAIN2_Pos 4 +#define ADC_CGR_GAIN2_Msk (0x3u << ADC_CGR_GAIN2_Pos) /**< \brief (ADC_CGR) Gain for channel 2 */ +#define ADC_CGR_GAIN2(value) ((ADC_CGR_GAIN2_Msk & ((value) << ADC_CGR_GAIN2_Pos))) +#define ADC_CGR_GAIN3_Pos 6 +#define ADC_CGR_GAIN3_Msk (0x3u << ADC_CGR_GAIN3_Pos) /**< \brief (ADC_CGR) Gain for channel 3 */ +#define ADC_CGR_GAIN3(value) ((ADC_CGR_GAIN3_Msk & ((value) << ADC_CGR_GAIN3_Pos))) +#define ADC_CGR_GAIN4_Pos 8 +#define ADC_CGR_GAIN4_Msk (0x3u << ADC_CGR_GAIN4_Pos) /**< \brief (ADC_CGR) Gain for channel 4 */ +#define ADC_CGR_GAIN4(value) ((ADC_CGR_GAIN4_Msk & ((value) << ADC_CGR_GAIN4_Pos))) +#define ADC_CGR_GAIN5_Pos 10 +#define ADC_CGR_GAIN5_Msk (0x3u << ADC_CGR_GAIN5_Pos) /**< \brief (ADC_CGR) Gain for channel 5 */ +#define ADC_CGR_GAIN5(value) ((ADC_CGR_GAIN5_Msk & ((value) << ADC_CGR_GAIN5_Pos))) +#define ADC_CGR_GAIN6_Pos 12 +#define ADC_CGR_GAIN6_Msk (0x3u << ADC_CGR_GAIN6_Pos) /**< \brief (ADC_CGR) Gain for channel 6 */ +#define ADC_CGR_GAIN6(value) ((ADC_CGR_GAIN6_Msk & ((value) << ADC_CGR_GAIN6_Pos))) +#define ADC_CGR_GAIN7_Pos 14 +#define ADC_CGR_GAIN7_Msk (0x3u << ADC_CGR_GAIN7_Pos) /**< \brief (ADC_CGR) Gain for channel 7 */ +#define ADC_CGR_GAIN7(value) ((ADC_CGR_GAIN7_Msk & ((value) << ADC_CGR_GAIN7_Pos))) +#define ADC_CGR_GAIN8_Pos 16 +#define ADC_CGR_GAIN8_Msk (0x3u << ADC_CGR_GAIN8_Pos) /**< \brief (ADC_CGR) Gain for channel 8 */ +#define ADC_CGR_GAIN8(value) ((ADC_CGR_GAIN8_Msk & ((value) << ADC_CGR_GAIN8_Pos))) +#define ADC_CGR_GAIN9_Pos 18 +#define ADC_CGR_GAIN9_Msk (0x3u << ADC_CGR_GAIN9_Pos) /**< \brief (ADC_CGR) Gain for channel 9 */ +#define ADC_CGR_GAIN9(value) ((ADC_CGR_GAIN9_Msk & ((value) << ADC_CGR_GAIN9_Pos))) +#define ADC_CGR_GAIN10_Pos 20 +#define ADC_CGR_GAIN10_Msk (0x3u << ADC_CGR_GAIN10_Pos) /**< \brief (ADC_CGR) Gain for channel 10 */ +#define ADC_CGR_GAIN10(value) ((ADC_CGR_GAIN10_Msk & ((value) << ADC_CGR_GAIN10_Pos))) +#define ADC_CGR_GAIN11_Pos 22 +#define ADC_CGR_GAIN11_Msk (0x3u << ADC_CGR_GAIN11_Pos) /**< \brief (ADC_CGR) Gain for channel 11 */ +#define ADC_CGR_GAIN11(value) ((ADC_CGR_GAIN11_Msk & ((value) << ADC_CGR_GAIN11_Pos))) +#define ADC_CGR_GAIN12_Pos 24 +#define ADC_CGR_GAIN12_Msk (0x3u << ADC_CGR_GAIN12_Pos) /**< \brief (ADC_CGR) Gain for channel 12 */ +#define ADC_CGR_GAIN12(value) ((ADC_CGR_GAIN12_Msk & ((value) << ADC_CGR_GAIN12_Pos))) +#define ADC_CGR_GAIN13_Pos 26 +#define ADC_CGR_GAIN13_Msk (0x3u << ADC_CGR_GAIN13_Pos) /**< \brief (ADC_CGR) Gain for channel 13 */ +#define ADC_CGR_GAIN13(value) ((ADC_CGR_GAIN13_Msk & ((value) << ADC_CGR_GAIN13_Pos))) +#define ADC_CGR_GAIN14_Pos 28 +#define ADC_CGR_GAIN14_Msk (0x3u << ADC_CGR_GAIN14_Pos) /**< \brief (ADC_CGR) Gain for channel 14 */ +#define ADC_CGR_GAIN14(value) ((ADC_CGR_GAIN14_Msk & ((value) << ADC_CGR_GAIN14_Pos))) +#define ADC_CGR_GAIN15_Pos 30 +#define ADC_CGR_GAIN15_Msk (0x3u << ADC_CGR_GAIN15_Pos) /**< \brief (ADC_CGR) Gain for channel 15 */ +#define ADC_CGR_GAIN15(value) ((ADC_CGR_GAIN15_Msk & ((value) << ADC_CGR_GAIN15_Pos))) +/* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */ +#define ADC_COR_OFF0 (0x1u << 0) /**< \brief (ADC_COR) Offset for channel 0 */ +#define ADC_COR_OFF1 (0x1u << 1) /**< \brief (ADC_COR) Offset for channel 1 */ +#define ADC_COR_OFF2 (0x1u << 2) /**< \brief (ADC_COR) Offset for channel 2 */ +#define ADC_COR_OFF3 (0x1u << 3) /**< \brief (ADC_COR) Offset for channel 3 */ +#define ADC_COR_OFF4 (0x1u << 4) /**< \brief (ADC_COR) Offset for channel 4 */ +#define ADC_COR_OFF5 (0x1u << 5) /**< \brief (ADC_COR) Offset for channel 5 */ +#define ADC_COR_OFF6 (0x1u << 6) /**< \brief (ADC_COR) Offset for channel 6 */ +#define ADC_COR_OFF7 (0x1u << 7) /**< \brief (ADC_COR) Offset for channel 7 */ +#define ADC_COR_OFF8 (0x1u << 8) /**< \brief (ADC_COR) Offset for channel 8 */ +#define ADC_COR_OFF9 (0x1u << 9) /**< \brief (ADC_COR) Offset for channel 9 */ +#define ADC_COR_OFF10 (0x1u << 10) /**< \brief (ADC_COR) Offset for channel 10 */ +#define ADC_COR_OFF11 (0x1u << 11) /**< \brief (ADC_COR) Offset for channel 11 */ +#define ADC_COR_OFF12 (0x1u << 12) /**< \brief (ADC_COR) Offset for channel 12 */ +#define ADC_COR_OFF13 (0x1u << 13) /**< \brief (ADC_COR) Offset for channel 13 */ +#define ADC_COR_OFF14 (0x1u << 14) /**< \brief (ADC_COR) Offset for channel 14 */ +#define ADC_COR_OFF15 (0x1u << 15) /**< \brief (ADC_COR) Offset for channel 15 */ +#define ADC_COR_DIFF0 (0x1u << 16) /**< \brief (ADC_COR) Differential inputs for channel 0 */ +#define ADC_COR_DIFF1 (0x1u << 17) /**< \brief (ADC_COR) Differential inputs for channel 1 */ +#define ADC_COR_DIFF2 (0x1u << 18) /**< \brief (ADC_COR) Differential inputs for channel 2 */ +#define ADC_COR_DIFF3 (0x1u << 19) /**< \brief (ADC_COR) Differential inputs for channel 3 */ +#define ADC_COR_DIFF4 (0x1u << 20) /**< \brief (ADC_COR) Differential inputs for channel 4 */ +#define ADC_COR_DIFF5 (0x1u << 21) /**< \brief (ADC_COR) Differential inputs for channel 5 */ +#define ADC_COR_DIFF6 (0x1u << 22) /**< \brief (ADC_COR) Differential inputs for channel 6 */ +#define ADC_COR_DIFF7 (0x1u << 23) /**< \brief (ADC_COR) Differential inputs for channel 7 */ +#define ADC_COR_DIFF8 (0x1u << 24) /**< \brief (ADC_COR) Differential inputs for channel 8 */ +#define ADC_COR_DIFF9 (0x1u << 25) /**< \brief (ADC_COR) Differential inputs for channel 9 */ +#define ADC_COR_DIFF10 (0x1u << 26) /**< \brief (ADC_COR) Differential inputs for channel 10 */ +#define ADC_COR_DIFF11 (0x1u << 27) /**< \brief (ADC_COR) Differential inputs for channel 11 */ +#define ADC_COR_DIFF12 (0x1u << 28) /**< \brief (ADC_COR) Differential inputs for channel 12 */ +#define ADC_COR_DIFF13 (0x1u << 29) /**< \brief (ADC_COR) Differential inputs for channel 13 */ +#define ADC_COR_DIFF14 (0x1u << 30) /**< \brief (ADC_COR) Differential inputs for channel 14 */ +#define ADC_COR_DIFF15 (0x1u << 31) /**< \brief (ADC_COR) Differential inputs for channel 15 */ +/* -------- ADC_CDR[16] : (ADC Offset: 0x50) Channel Data Register -------- */ +#define ADC_CDR_DATA_Pos 0 +#define ADC_CDR_DATA_Msk (0xfffu << ADC_CDR_DATA_Pos) /**< \brief (ADC_CDR[16]) Converted Data */ +/* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */ +#define ADC_ACR_TSON (0x1u << 4) /**< \brief (ADC_ACR) Temperature Sensor On */ +#define ADC_ACR_IBCTL_Pos 8 +#define ADC_ACR_IBCTL_Msk (0x3u << ADC_ACR_IBCTL_Pos) /**< \brief (ADC_ACR) ADC Bias Current Control */ +#define ADC_ACR_IBCTL(value) ((ADC_ACR_IBCTL_Msk & ((value) << ADC_ACR_IBCTL_Pos))) +/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */ +#define ADC_WPMR_WPEN (0x1u << 0) /**< \brief (ADC_WPMR) Write Protect Enable */ +#define ADC_WPMR_WPKEY_Pos 8 +#define ADC_WPMR_WPKEY_Msk (0xffffffu << ADC_WPMR_WPKEY_Pos) /**< \brief (ADC_WPMR) Write Protect KEY */ +#define ADC_WPMR_WPKEY(value) ((ADC_WPMR_WPKEY_Msk & ((value) << ADC_WPMR_WPKEY_Pos))) +/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */ +#define ADC_WPSR_WPVS (0x1u << 0) /**< \brief (ADC_WPSR) Write Protect Violation Status */ +#define ADC_WPSR_WPVSRC_Pos 8 +#define ADC_WPSR_WPVSRC_Msk (0xffffu << ADC_WPSR_WPVSRC_Pos) /**< \brief (ADC_WPSR) Write Protect Violation Source */ +/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */ +#define ADC_RPR_RXPTR_Pos 0 +#define ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos) /**< \brief (ADC_RPR) Receive Pointer Register */ +#define ADC_RPR_RXPTR(value) ((ADC_RPR_RXPTR_Msk & ((value) << ADC_RPR_RXPTR_Pos))) +/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */ +#define ADC_RCR_RXCTR_Pos 0 +#define ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos) /**< \brief (ADC_RCR) Receive Counter Register */ +#define ADC_RCR_RXCTR(value) ((ADC_RCR_RXCTR_Msk & ((value) << ADC_RCR_RXCTR_Pos))) +/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */ +#define ADC_RNPR_RXNPTR_Pos 0 +#define ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos) /**< \brief (ADC_RNPR) Receive Next Pointer */ +#define ADC_RNPR_RXNPTR(value) ((ADC_RNPR_RXNPTR_Msk & ((value) << ADC_RNPR_RXNPTR_Pos))) +/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */ +#define ADC_RNCR_RXNCTR_Pos 0 +#define ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos) /**< \brief (ADC_RNCR) Receive Next Counter */ +#define ADC_RNCR_RXNCTR(value) ((ADC_RNCR_RXNCTR_Msk & ((value) << ADC_RNCR_RXNCTR_Pos))) +/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */ +#define ADC_PTCR_RXTEN (0x1u << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */ +#define ADC_PTCR_RXTDIS (0x1u << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */ +#define ADC_PTCR_TXTEN (0x1u << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */ +#define ADC_PTCR_TXTDIS (0x1u << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */ +/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */ +#define ADC_PTSR_RXTEN (0x1u << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */ +#define ADC_PTSR_TXTEN (0x1u << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + + +#endif /* _SAM3XA_ADC_COMPONENT_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h new file mode 100644 index 0000000..c309f3f --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_can.h @@ -0,0 +1,313 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_CAN_COMPONENT_ +#define _SAM3XA_CAN_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Controller Area Network */ +/* ============================================================================= */ +/** \addtogroup SAM3XA_CAN Controller Area Network */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief CanMb hardware registers */ +typedef struct { + RwReg CAN_MMR; /**< \brief (CanMb Offset: 0x0) Mailbox Mode Register */ + RwReg CAN_MAM; /**< \brief (CanMb Offset: 0x4) Mailbox Acceptance Mask Register */ + RwReg CAN_MID; /**< \brief (CanMb Offset: 0x8) Mailbox ID Register */ + RwReg CAN_MFID; /**< \brief (CanMb Offset: 0xC) Mailbox Family ID Register */ + RwReg CAN_MSR; /**< \brief (CanMb Offset: 0x10) Mailbox Status Register */ + RwReg CAN_MDL; /**< \brief (CanMb Offset: 0x14) Mailbox Data Low Register */ + RwReg CAN_MDH; /**< \brief (CanMb Offset: 0x18) Mailbox Data High Register */ + RwReg CAN_MCR; /**< \brief (CanMb Offset: 0x1C) Mailbox Control Register */ +} CanMb; +/** \brief Can hardware registers */ +#define CANMB_NUMBER 8 +typedef struct { + RwReg CAN_MR; /**< \brief (Can Offset: 0x0000) Mode Register */ + WoReg CAN_IER; /**< \brief (Can Offset: 0x0004) Interrupt Enable Register */ + WoReg CAN_IDR; /**< \brief (Can Offset: 0x0008) Interrupt Disable Register */ + RoReg CAN_IMR; /**< \brief (Can Offset: 0x000C) Interrupt Mask Register */ + RoReg CAN_SR; /**< \brief (Can Offset: 0x0010) Status Register */ + RwReg CAN_BR; /**< \brief (Can Offset: 0x0014) Baudrate Register */ + RoReg CAN_TIM; /**< \brief (Can Offset: 0x0018) Timer Register */ + RoReg CAN_TIMESTP; /**< \brief (Can Offset: 0x001C) Timestamp Register */ + RoReg CAN_ECR; /**< \brief (Can Offset: 0x0020) Error Counter Register */ + WoReg CAN_TCR; /**< \brief (Can Offset: 0x0024) Transfer Command Register */ + WoReg CAN_ACR; /**< \brief (Can Offset: 0x0028) Abort Command Register */ + RoReg Reserved1[46]; + RwReg CAN_WPMR; /**< \brief (Can Offset: 0x00E4) Write Protect Mode Register */ + RoReg CAN_WPSR; /**< \brief (Can Offset: 0x00E8) Write Protect Status Register */ + RoReg Reserved2[69]; + CanMb CAN_MB[CANMB_NUMBER]; /**< \brief (Can Offset: 0x200) MB = 0 .. 7 */ +} Can; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- CAN_MR : (CAN Offset: 0x0000) Mode Register -------- */ +#define CAN_MR_CANEN (0x1u << 0) /**< \brief (CAN_MR) CAN Controller Enable */ +#define CAN_MR_LPM (0x1u << 1) /**< \brief (CAN_MR) Disable/Enable Low Power Mode */ +#define CAN_MR_ABM (0x1u << 2) /**< \brief (CAN_MR) Disable/Enable Autobaud/Listen mode */ +#define CAN_MR_OVL (0x1u << 3) /**< \brief (CAN_MR) Disable/Enable Overload Frame */ +#define CAN_MR_TEOF (0x1u << 4) /**< \brief (CAN_MR) Timestamp messages at each end of Frame */ +#define CAN_MR_TTM (0x1u << 5) /**< \brief (CAN_MR) Disable/Enable Time Triggered Mode */ +#define CAN_MR_TIMFRZ (0x1u << 6) /**< \brief (CAN_MR) Enable Timer Freeze */ +#define CAN_MR_DRPT (0x1u << 7) /**< \brief (CAN_MR) Disable Repeat */ +#define CAN_MR_RXSYNC_Pos 24 +#define CAN_MR_RXSYNC_Msk (0x7u << CAN_MR_RXSYNC_Pos) /**< \brief (CAN_MR) Reception Synchronization Stage (not readable) */ +#define CAN_MR_RXSYNC_DOUBLE_PP (0x0u << 24) /**< \brief (CAN_MR) Rx Signal with Double Synchro Stages (2 Positive Edges) */ +#define CAN_MR_RXSYNC_DOUBLE_PN (0x1u << 24) /**< \brief (CAN_MR) Rx Signal with Double Synchro Stages (One Positive Edge and One Negative Edge) */ +#define CAN_MR_RXSYNC_SINGLE_P (0x2u << 24) /**< \brief (CAN_MR) Rx Signal with Single Synchro Stage (Positive Edge) */ +#define CAN_MR_RXSYNC_NONE (0x3u << 24) /**< \brief (CAN_MR) Rx Signal with No Synchro Stage */ +/* -------- CAN_IER : (CAN Offset: 0x0004) Interrupt Enable Register -------- */ +#define CAN_IER_MB0 (0x1u << 0) /**< \brief (CAN_IER) Mailbox 0 Interrupt Enable */ +#define CAN_IER_MB1 (0x1u << 1) /**< \brief (CAN_IER) Mailbox 1 Interrupt Enable */ +#define CAN_IER_MB2 (0x1u << 2) /**< \brief (CAN_IER) Mailbox 2 Interrupt Enable */ +#define CAN_IER_MB3 (0x1u << 3) /**< \brief (CAN_IER) Mailbox 3 Interrupt Enable */ +#define CAN_IER_MB4 (0x1u << 4) /**< \brief (CAN_IER) Mailbox 4 Interrupt Enable */ +#define CAN_IER_MB5 (0x1u << 5) /**< \brief (CAN_IER) Mailbox 5 Interrupt Enable */ +#define CAN_IER_MB6 (0x1u << 6) /**< \brief (CAN_IER) Mailbox 6 Interrupt Enable */ +#define CAN_IER_MB7 (0x1u << 7) /**< \brief (CAN_IER) Mailbox 7 Interrupt Enable */ +#define CAN_IER_ERRA (0x1u << 16) /**< \brief (CAN_IER) Error Active Mode Interrupt Enable */ +#define CAN_IER_WARN (0x1u << 17) /**< \brief (CAN_IER) Warning Limit Interrupt Enable */ +#define CAN_IER_ERRP (0x1u << 18) /**< \brief (CAN_IER) Error Passive Mode Interrupt Enable */ +#define CAN_IER_BOFF (0x1u << 19) /**< \brief (CAN_IER) Bus Off Mode Interrupt Enable */ +#define CAN_IER_SLEEP (0x1u << 20) /**< \brief (CAN_IER) Sleep Interrupt Enable */ +#define CAN_IER_WAKEUP (0x1u << 21) /**< \brief (CAN_IER) Wakeup Interrupt Enable */ +#define CAN_IER_TOVF (0x1u << 22) /**< \brief (CAN_IER) Timer Overflow Interrupt Enable */ +#define CAN_IER_TSTP (0x1u << 23) /**< \brief (CAN_IER) TimeStamp Interrupt Enable */ +#define CAN_IER_CERR (0x1u << 24) /**< \brief (CAN_IER) CRC Error Interrupt Enable */ +#define CAN_IER_SERR (0x1u << 25) /**< \brief (CAN_IER) Stuffing Error Interrupt Enable */ +#define CAN_IER_AERR (0x1u << 26) /**< \brief (CAN_IER) Acknowledgment Error Interrupt Enable */ +#define CAN_IER_FERR (0x1u << 27) /**< \brief (CAN_IER) Form Error Interrupt Enable */ +#define CAN_IER_BERR (0x1u << 28) /**< \brief (CAN_IER) Bit Error Interrupt Enable */ +/* -------- CAN_IDR : (CAN Offset: 0x0008) Interrupt Disable Register -------- */ +#define CAN_IDR_MB0 (0x1u << 0) /**< \brief (CAN_IDR) Mailbox 0 Interrupt Disable */ +#define CAN_IDR_MB1 (0x1u << 1) /**< \brief (CAN_IDR) Mailbox 1 Interrupt Disable */ +#define CAN_IDR_MB2 (0x1u << 2) /**< \brief (CAN_IDR) Mailbox 2 Interrupt Disable */ +#define CAN_IDR_MB3 (0x1u << 3) /**< \brief (CAN_IDR) Mailbox 3 Interrupt Disable */ +#define CAN_IDR_MB4 (0x1u << 4) /**< \brief (CAN_IDR) Mailbox 4 Interrupt Disable */ +#define CAN_IDR_MB5 (0x1u << 5) /**< \brief (CAN_IDR) Mailbox 5 Interrupt Disable */ +#define CAN_IDR_MB6 (0x1u << 6) /**< \brief (CAN_IDR) Mailbox 6 Interrupt Disable */ +#define CAN_IDR_MB7 (0x1u << 7) /**< \brief (CAN_IDR) Mailbox 7 Interrupt Disable */ +#define CAN_IDR_ERRA (0x1u << 16) /**< \brief (CAN_IDR) Error Active Mode Interrupt Disable */ +#define CAN_IDR_WARN (0x1u << 17) /**< \brief (CAN_IDR) Warning Limit Interrupt Disable */ +#define CAN_IDR_ERRP (0x1u << 18) /**< \brief (CAN_IDR) Error Passive Mode Interrupt Disable */ +#define CAN_IDR_BOFF (0x1u << 19) /**< \brief (CAN_IDR) Bus Off Mode Interrupt Disable */ +#define CAN_IDR_SLEEP (0x1u << 20) /**< \brief (CAN_IDR) Sleep Interrupt Disable */ +#define CAN_IDR_WAKEUP (0x1u << 21) /**< \brief (CAN_IDR) Wakeup Interrupt Disable */ +#define CAN_IDR_TOVF (0x1u << 22) /**< \brief (CAN_IDR) Timer Overflow Interrupt */ +#define CAN_IDR_TSTP (0x1u << 23) /**< \brief (CAN_IDR) TimeStamp Interrupt Disable */ +#define CAN_IDR_CERR (0x1u << 24) /**< \brief (CAN_IDR) CRC Error Interrupt Disable */ +#define CAN_IDR_SERR (0x1u << 25) /**< \brief (CAN_IDR) Stuffing Error Interrupt Disable */ +#define CAN_IDR_AERR (0x1u << 26) /**< \brief (CAN_IDR) Acknowledgment Error Interrupt Disable */ +#define CAN_IDR_FERR (0x1u << 27) /**< \brief (CAN_IDR) Form Error Interrupt Disable */ +#define CAN_IDR_BERR (0x1u << 28) /**< \brief (CAN_IDR) Bit Error Interrupt Disable */ +/* -------- CAN_IMR : (CAN Offset: 0x000C) Interrupt Mask Register -------- */ +#define CAN_IMR_MB0 (0x1u << 0) /**< \brief (CAN_IMR) Mailbox 0 Interrupt Mask */ +#define CAN_IMR_MB1 (0x1u << 1) /**< \brief (CAN_IMR) Mailbox 1 Interrupt Mask */ +#define CAN_IMR_MB2 (0x1u << 2) /**< \brief (CAN_IMR) Mailbox 2 Interrupt Mask */ +#define CAN_IMR_MB3 (0x1u << 3) /**< \brief (CAN_IMR) Mailbox 3 Interrupt Mask */ +#define CAN_IMR_MB4 (0x1u << 4) /**< \brief (CAN_IMR) Mailbox 4 Interrupt Mask */ +#define CAN_IMR_MB5 (0x1u << 5) /**< \brief (CAN_IMR) Mailbox 5 Interrupt Mask */ +#define CAN_IMR_MB6 (0x1u << 6) /**< \brief (CAN_IMR) Mailbox 6 Interrupt Mask */ +#define CAN_IMR_MB7 (0x1u << 7) /**< \brief (CAN_IMR) Mailbox 7 Interrupt Mask */ +#define CAN_IMR_ERRA (0x1u << 16) /**< \brief (CAN_IMR) Error Active Mode Interrupt Mask */ +#define CAN_IMR_WARN (0x1u << 17) /**< \brief (CAN_IMR) Warning Limit Interrupt Mask */ +#define CAN_IMR_ERRP (0x1u << 18) /**< \brief (CAN_IMR) Error Passive Mode Interrupt Mask */ +#define CAN_IMR_BOFF (0x1u << 19) /**< \brief (CAN_IMR) Bus Off Mode Interrupt Mask */ +#define CAN_IMR_SLEEP (0x1u << 20) /**< \brief (CAN_IMR) Sleep Interrupt Mask */ +#define CAN_IMR_WAKEUP (0x1u << 21) /**< \brief (CAN_IMR) Wakeup Interrupt Mask */ +#define CAN_IMR_TOVF (0x1u << 22) /**< \brief (CAN_IMR) Timer Overflow Interrupt Mask */ +#define CAN_IMR_TSTP (0x1u << 23) /**< \brief (CAN_IMR) Timestamp Interrupt Mask */ +#define CAN_IMR_CERR (0x1u << 24) /**< \brief (CAN_IMR) CRC Error Interrupt Mask */ +#define CAN_IMR_SERR (0x1u << 25) /**< \brief (CAN_IMR) Stuffing Error Interrupt Mask */ +#define CAN_IMR_AERR (0x1u << 26) /**< \brief (CAN_IMR) Acknowledgment Error Interrupt Mask */ +#define CAN_IMR_FERR (0x1u << 27) /**< \brief (CAN_IMR) Form Error Interrupt Mask */ +#define CAN_IMR_BERR (0x1u << 28) /**< \brief (CAN_IMR) Bit Error Interrupt Mask */ +/* -------- CAN_SR : (CAN Offset: 0x0010) Status Register -------- */ +#define CAN_SR_MB0 (0x1u << 0) /**< \brief (CAN_SR) Mailbox 0 Event */ +#define CAN_SR_MB1 (0x1u << 1) /**< \brief (CAN_SR) Mailbox 1 Event */ +#define CAN_SR_MB2 (0x1u << 2) /**< \brief (CAN_SR) Mailbox 2 Event */ +#define CAN_SR_MB3 (0x1u << 3) /**< \brief (CAN_SR) Mailbox 3 Event */ +#define CAN_SR_MB4 (0x1u << 4) /**< \brief (CAN_SR) Mailbox 4 Event */ +#define CAN_SR_MB5 (0x1u << 5) /**< \brief (CAN_SR) Mailbox 5 Event */ +#define CAN_SR_MB6 (0x1u << 6) /**< \brief (CAN_SR) Mailbox 6 Event */ +#define CAN_SR_MB7 (0x1u << 7) /**< \brief (CAN_SR) Mailbox 7 Event */ +#define CAN_SR_ERRA (0x1u << 16) /**< \brief (CAN_SR) Error Active Mode */ +#define CAN_SR_WARN (0x1u << 17) /**< \brief (CAN_SR) Warning Limit */ +#define CAN_SR_ERRP (0x1u << 18) /**< \brief (CAN_SR) Error Passive Mode */ +#define CAN_SR_BOFF (0x1u << 19) /**< \brief (CAN_SR) Bus Off Mode */ +#define CAN_SR_SLEEP (0x1u << 20) /**< \brief (CAN_SR) CAN controller in Low power Mode */ +#define CAN_SR_WAKEUP (0x1u << 21) /**< \brief (CAN_SR) CAN controller is not in Low power Mode */ +#define CAN_SR_TOVF (0x1u << 22) /**< \brief (CAN_SR) Timer Overflow */ +#define CAN_SR_TSTP (0x1u << 23) /**< \brief (CAN_SR) */ +#define CAN_SR_CERR (0x1u << 24) /**< \brief (CAN_SR) Mailbox CRC Error */ +#define CAN_SR_SERR (0x1u << 25) /**< \brief (CAN_SR) Mailbox Stuffing Error */ +#define CAN_SR_AERR (0x1u << 26) /**< \brief (CAN_SR) Acknowledgment Error */ +#define CAN_SR_FERR (0x1u << 27) /**< \brief (CAN_SR) Form Error */ +#define CAN_SR_BERR (0x1u << 28) /**< \brief (CAN_SR) Bit Error */ +#define CAN_SR_RBSY (0x1u << 29) /**< \brief (CAN_SR) Receiver busy */ +#define CAN_SR_TBSY (0x1u << 30) /**< \brief (CAN_SR) Transmitter busy */ +#define CAN_SR_OVLSY (0x1u << 31) /**< \brief (CAN_SR) Overload busy */ +/* -------- CAN_BR : (CAN Offset: 0x0014) Baudrate Register -------- */ +#define CAN_BR_PHASE2_Pos 0 +#define CAN_BR_PHASE2_Msk (0x7u << CAN_BR_PHASE2_Pos) /**< \brief (CAN_BR) Phase 2 segment */ +#define CAN_BR_PHASE2(value) ((CAN_BR_PHASE2_Msk & ((value) << CAN_BR_PHASE2_Pos))) +#define CAN_BR_PHASE1_Pos 4 +#define CAN_BR_PHASE1_Msk (0x7u << CAN_BR_PHASE1_Pos) /**< \brief (CAN_BR) Phase 1 segment */ +#define CAN_BR_PHASE1(value) ((CAN_BR_PHASE1_Msk & ((value) << CAN_BR_PHASE1_Pos))) +#define CAN_BR_PROPAG_Pos 8 +#define CAN_BR_PROPAG_Msk (0x7u << CAN_BR_PROPAG_Pos) /**< \brief (CAN_BR) Programming time segment */ +#define CAN_BR_PROPAG(value) ((CAN_BR_PROPAG_Msk & ((value) << CAN_BR_PROPAG_Pos))) +#define CAN_BR_SJW_Pos 12 +#define CAN_BR_SJW_Msk (0x3u << CAN_BR_SJW_Pos) /**< \brief (CAN_BR) Re-synchronization jump width */ +#define CAN_BR_SJW(value) ((CAN_BR_SJW_Msk & ((value) << CAN_BR_SJW_Pos))) +#define CAN_BR_BRP_Pos 16 +#define CAN_BR_BRP_Msk (0x7fu << CAN_BR_BRP_Pos) /**< \brief (CAN_BR) Baudrate Prescaler. */ +#define CAN_BR_BRP(value) ((CAN_BR_BRP_Msk & ((value) << CAN_BR_BRP_Pos))) +#define CAN_BR_SMP (0x1u << 24) /**< \brief (CAN_BR) Sampling Mode */ +#define CAN_BR_SMP_ONCE (0x0u << 24) /**< \brief (CAN_BR) The incoming bit stream is sampled once at sample point. */ +#define CAN_BR_SMP_THREE (0x1u << 24) /**< \brief (CAN_BR) The incoming bit stream is sampled three times with a period of a MCK clock period, centered on sample point. */ +/* -------- CAN_TIM : (CAN Offset: 0x0018) Timer Register -------- */ +#define CAN_TIM_TIMER_Pos 0 +#define CAN_TIM_TIMER_Msk (0xffffu << CAN_TIM_TIMER_Pos) /**< \brief (CAN_TIM) Timer */ +/* -------- CAN_TIMESTP : (CAN Offset: 0x001C) Timestamp Register -------- */ +#define CAN_TIMESTP_MTIMESTAMP_Pos 0 +#define CAN_TIMESTP_MTIMESTAMP_Msk (0xffffu << CAN_TIMESTP_MTIMESTAMP_Pos) /**< \brief (CAN_TIMESTP) Timestamp */ +/* -------- CAN_ECR : (CAN Offset: 0x0020) Error Counter Register -------- */ +#define CAN_ECR_REC_Pos 0 +#define CAN_ECR_REC_Msk (0xffu << CAN_ECR_REC_Pos) /**< \brief (CAN_ECR) Receive Error Counter */ +#define CAN_ECR_TEC_Pos 16 +#define CAN_ECR_TEC_Msk (0xffu << CAN_ECR_TEC_Pos) /**< \brief (CAN_ECR) Transmit Error Counter */ +/* -------- CAN_TCR : (CAN Offset: 0x0024) Transfer Command Register -------- */ +#define CAN_TCR_MB0 (0x1u << 0) /**< \brief (CAN_TCR) Transfer Request for Mailbox 0 */ +#define CAN_TCR_MB1 (0x1u << 1) /**< \brief (CAN_TCR) Transfer Request for Mailbox 1 */ +#define CAN_TCR_MB2 (0x1u << 2) /**< \brief (CAN_TCR) Transfer Request for Mailbox 2 */ +#define CAN_TCR_MB3 (0x1u << 3) /**< \brief (CAN_TCR) Transfer Request for Mailbox 3 */ +#define CAN_TCR_MB4 (0x1u << 4) /**< \brief (CAN_TCR) Transfer Request for Mailbox 4 */ +#define CAN_TCR_MB5 (0x1u << 5) /**< \brief (CAN_TCR) Transfer Request for Mailbox 5 */ +#define CAN_TCR_MB6 (0x1u << 6) /**< \brief (CAN_TCR) Transfer Request for Mailbox 6 */ +#define CAN_TCR_MB7 (0x1u << 7) /**< \brief (CAN_TCR) Transfer Request for Mailbox 7 */ +#define CAN_TCR_TIMRST (0x1u << 31) /**< \brief (CAN_TCR) Timer Reset */ +/* -------- CAN_ACR : (CAN Offset: 0x0028) Abort Command Register -------- */ +#define CAN_ACR_MB0 (0x1u << 0) /**< \brief (CAN_ACR) Abort Request for Mailbox 0 */ +#define CAN_ACR_MB1 (0x1u << 1) /**< \brief (CAN_ACR) Abort Request for Mailbox 1 */ +#define CAN_ACR_MB2 (0x1u << 2) /**< \brief (CAN_ACR) Abort Request for Mailbox 2 */ +#define CAN_ACR_MB3 (0x1u << 3) /**< \brief (CAN_ACR) Abort Request for Mailbox 3 */ +#define CAN_ACR_MB4 (0x1u << 4) /**< \brief (CAN_ACR) Abort Request for Mailbox 4 */ +#define CAN_ACR_MB5 (0x1u << 5) /**< \brief (CAN_ACR) Abort Request for Mailbox 5 */ +#define CAN_ACR_MB6 (0x1u << 6) /**< \brief (CAN_ACR) Abort Request for Mailbox 6 */ +#define CAN_ACR_MB7 (0x1u << 7) /**< \brief (CAN_ACR) Abort Request for Mailbox 7 */ +/* -------- CAN_WPMR : (CAN Offset: 0x00E4) Write Protect Mode Register -------- */ +#define CAN_WPMR_WPEN (0x1u << 0) /**< \brief (CAN_WPMR) Write Protection Enable */ +#define CAN_WPMR_WPKEY_Pos 8 +#define CAN_WPMR_WPKEY_Msk (0xffffffu << CAN_WPMR_WPKEY_Pos) /**< \brief (CAN_WPMR) SPI Write Protection Key Password */ +#define CAN_WPMR_WPKEY(value) ((CAN_WPMR_WPKEY_Msk & ((value) << CAN_WPMR_WPKEY_Pos))) +/* -------- CAN_WPSR : (CAN Offset: 0x00E8) Write Protect Status Register -------- */ +#define CAN_WPSR_WPVS (0x1u << 0) /**< \brief (CAN_WPSR) Write Protection Violation Status */ +#define CAN_WPSR_WPVSRC_Pos 8 +#define CAN_WPSR_WPVSRC_Msk (0xffu << CAN_WPSR_WPVSRC_Pos) /**< \brief (CAN_WPSR) Write Protection Violation Source */ +/* -------- CAN_MMR : (CAN Offset: N/A) Mailbox Mode Register -------- */ +#define CAN_MMR_MTIMEMARK_Pos 0 +#define CAN_MMR_MTIMEMARK_Msk (0xffffu << CAN_MMR_MTIMEMARK_Pos) /**< \brief (CAN_MMR) Mailbox Timemark */ +#define CAN_MMR_MTIMEMARK(value) ((CAN_MMR_MTIMEMARK_Msk & ((value) << CAN_MMR_MTIMEMARK_Pos))) +#define CAN_MMR_PRIOR_Pos 16 +#define CAN_MMR_PRIOR_Msk (0xfu << CAN_MMR_PRIOR_Pos) /**< \brief (CAN_MMR) Mailbox Priority */ +#define CAN_MMR_PRIOR(value) ((CAN_MMR_PRIOR_Msk & ((value) << CAN_MMR_PRIOR_Pos))) +#define CAN_MMR_MOT_Pos 24 +#define CAN_MMR_MOT_Msk (0x7u << CAN_MMR_MOT_Pos) /**< \brief (CAN_MMR) Mailbox Object Type */ +#define CAN_MMR_MOT_MB_DISABLED (0x0u << 24) /**< \brief (CAN_MMR) Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. */ +#define CAN_MMR_MOT_MB_RX (0x1u << 24) /**< \brief (CAN_MMR) Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. */ +#define CAN_MMR_MOT_MB_RX_OVERWRITE (0x2u << 24) /**< \brief (CAN_MMR) Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. */ +#define CAN_MMR_MOT_MB_TX (0x3u << 24) /**< \brief (CAN_MMR) Transmit mailbox. Mailbox is configured for transmission. */ +#define CAN_MMR_MOT_MB_CONSUMER (0x4u << 24) /**< \brief (CAN_MMR) Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. */ +#define CAN_MMR_MOT_MB_PRODUCER (0x5u << 24) /**< \brief (CAN_MMR) Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. */ +/* -------- CAN_MAM : (CAN Offset: N/A) Mailbox Acceptance Mask Register -------- */ +#define CAN_MAM_MIDvB_Pos 0 +#define CAN_MAM_MIDvB_Msk (0x3ffffu << CAN_MAM_MIDvB_Pos) /**< \brief (CAN_MAM) Complementary bits for identifier in extended frame mode */ +#define CAN_MAM_MIDvB(value) ((CAN_MAM_MIDvB_Msk & ((value) << CAN_MAM_MIDvB_Pos))) +#define CAN_MAM_MIDvA_Pos 18 +#define CAN_MAM_MIDvA_Msk (0x7ffu << CAN_MAM_MIDvA_Pos) /**< \brief (CAN_MAM) Identifier for standard frame mode */ +#define CAN_MAM_MIDvA(value) ((CAN_MAM_MIDvA_Msk & ((value) << CAN_MAM_MIDvA_Pos))) +#define CAN_MAM_MIDE (0x1u << 29) /**< \brief (CAN_MAM) Identifier Version */ +/* -------- CAN_MID : (CAN Offset: N/A) Mailbox ID Register -------- */ +#define CAN_MID_MIDvB_Pos 0 +#define CAN_MID_MIDvB_Msk (0x3ffffu << CAN_MID_MIDvB_Pos) /**< \brief (CAN_MID) Complementary bits for identifier in extended frame mode */ +#define CAN_MID_MIDvB(value) ((CAN_MID_MIDvB_Msk & ((value) << CAN_MID_MIDvB_Pos))) +#define CAN_MID_MIDvA_Pos 18 +#define CAN_MID_MIDvA_Msk (0x7ffu << CAN_MID_MIDvA_Pos) /**< \brief (CAN_MID) Identifier for standard frame mode */ +#define CAN_MID_MIDvA(value) ((CAN_MID_MIDvA_Msk & ((value) << CAN_MID_MIDvA_Pos))) +#define CAN_MID_MIDE (0x1u << 29) /**< \brief (CAN_MID) Identifier Version */ +/* -------- CAN_MFID : (CAN Offset: N/A) Mailbox Family ID Register -------- */ +#define CAN_MFID_MFID_Pos 0 +#define CAN_MFID_MFID_Msk (0x1fffffffu << CAN_MFID_MFID_Pos) /**< \brief (CAN_MFID) Family ID */ +/* -------- CAN_MSR : (CAN Offset: N/A) Mailbox Status Register -------- */ +#define CAN_MSR_MTIMESTAMP_Pos 0 +#define CAN_MSR_MTIMESTAMP_Msk (0xffffu << CAN_MSR_MTIMESTAMP_Pos) /**< \brief (CAN_MSR) Timer value */ +#define CAN_MSR_MDLC_Pos 16 +#define CAN_MSR_MDLC_Msk (0xfu << CAN_MSR_MDLC_Pos) /**< \brief (CAN_MSR) Mailbox Data Length Code */ +#define CAN_MSR_MRTR (0x1u << 20) /**< \brief (CAN_MSR) Mailbox Remote Transmission Request */ +#define CAN_MSR_MABT (0x1u << 22) /**< \brief (CAN_MSR) Mailbox Message Abort */ +#define CAN_MSR_MRDY (0x1u << 23) /**< \brief (CAN_MSR) Mailbox Ready */ +#define CAN_MSR_MMI (0x1u << 24) /**< \brief (CAN_MSR) Mailbox Message Ignored */ +/* -------- CAN_MDL : (CAN Offset: N/A) Mailbox Data Low Register -------- */ +#define CAN_MDL_MDL_Pos 0 +#define CAN_MDL_MDL_Msk (0xffffffffu << CAN_MDL_MDL_Pos) /**< \brief (CAN_MDL) Message Data Low Value */ +#define CAN_MDL_MDL(value) ((CAN_MDL_MDL_Msk & ((value) << CAN_MDL_MDL_Pos))) +/* -------- CAN_MDH : (CAN Offset: N/A) Mailbox Data High Register -------- */ +#define CAN_MDH_MDH_Pos 0 +#define CAN_MDH_MDH_Msk (0xffffffffu << CAN_MDH_MDH_Pos) /**< \brief (CAN_MDH) Message Data High Value */ +#define CAN_MDH_MDH(value) ((CAN_MDH_MDH_Msk & ((value) << CAN_MDH_MDH_Pos))) +/* -------- CAN_MCR : (CAN Offset: N/A) Mailbox Control Register -------- */ +#define CAN_MCR_MDLC_Pos 16 +#define CAN_MCR_MDLC_Msk (0xfu << CAN_MCR_MDLC_Pos) /**< \brief (CAN_MCR) Mailbox Data Length Code */ +#define CAN_MCR_MDLC(value) ((CAN_MCR_MDLC_Msk & ((value) << CAN_MCR_MDLC_Pos))) +#define CAN_MCR_MRTR (0x1u << 20) /**< \brief (CAN_MCR) Mailbox Remote Transmission Request */ +#define CAN_MCR_MACR (0x1u << 22) /**< \brief (CAN_MCR) Abort Request for Mailbox x */ +#define CAN_MCR_MTCR (0x1u << 23) /**< \brief (CAN_MCR) Mailbox Transfer Command */ + +/*@}*/ + + +#endif /* _SAM3XA_CAN_COMPONENT_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h new file mode 100644 index 0000000..8ffe440 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_chipid.h @@ -0,0 +1,174 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_CHIPID_COMPONENT_ +#define _SAM3XA_CHIPID_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Chip Identifier */ +/* ============================================================================= */ +/** \addtogroup SAM3XA_CHIPID Chip Identifier */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Chipid hardware registers */ +typedef struct { + RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */ + RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */ +} Chipid; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */ +#define CHIPID_CIDR_VERSION_Pos 0 +#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */ +#define CHIPID_CIDR_EPROC_Pos 5 +#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */ +#define CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */ +#define CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */ +#define CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */ +#define CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */ +#define CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */ +#define CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */ +#define CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */ +#define CHIPID_CIDR_NVPSIZ_Pos 8 +#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */ +#define CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */ +#define CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8K bytes */ +#define CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16K bytes */ +#define CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32K bytes */ +#define CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64K bytes */ +#define CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128K bytes */ +#define CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256K bytes */ +#define CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512K bytes */ +#define CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024K bytes */ +#define CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048K bytes */ +#define CHIPID_CIDR_NVPSIZ2_Pos 12 +#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */ +#define CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */ +#define CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8K bytes */ +#define CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16K bytes */ +#define CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32K bytes */ +#define CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64K bytes */ +#define CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128K bytes */ +#define CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256K bytes */ +#define CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512K bytes */ +#define CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024K bytes */ +#define CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048K bytes */ +#define CHIPID_CIDR_SRAMSIZ_Pos 16 +#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */ +#define CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48K bytes */ +#define CHIPID_CIDR_SRAMSIZ_1K (0x1u << 16) /**< \brief (CHIPID_CIDR) 1K bytes */ +#define CHIPID_CIDR_SRAMSIZ_2K (0x2u << 16) /**< \brief (CHIPID_CIDR) 2K bytes */ +#define CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6K bytes */ +#define CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24K bytes */ +#define CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4K bytes */ +#define CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80K bytes */ +#define CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160K bytes */ +#define CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8K bytes */ +#define CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16K bytes */ +#define CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32K bytes */ +#define CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64K bytes */ +#define CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128K bytes */ +#define CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256K bytes */ +#define CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96K bytes */ +#define CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512K bytes */ +#define CHIPID_CIDR_ARCH_Pos 20 +#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */ +#define CHIPID_CIDR_ARCH_AT91SAM9xx (0x19u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9xx Series */ +#define CHIPID_CIDR_ARCH_AT91SAM9XExx (0x29u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9XExx Series */ +#define CHIPID_CIDR_ARCH_AT91x34 (0x34u << 20) /**< \brief (CHIPID_CIDR) AT91x34 Series */ +#define CHIPID_CIDR_ARCH_CAP7 (0x37u << 20) /**< \brief (CHIPID_CIDR) CAP7 Series */ +#define CHIPID_CIDR_ARCH_CAP9 (0x39u << 20) /**< \brief (CHIPID_CIDR) CAP9 Series */ +#define CHIPID_CIDR_ARCH_CAP11 (0x3Bu << 20) /**< \brief (CHIPID_CIDR) CAP11 Series */ +#define CHIPID_CIDR_ARCH_AT91x40 (0x40u << 20) /**< \brief (CHIPID_CIDR) AT91x40 Series */ +#define CHIPID_CIDR_ARCH_AT91x42 (0x42u << 20) /**< \brief (CHIPID_CIDR) AT91x42 Series */ +#define CHIPID_CIDR_ARCH_AT91x55 (0x55u << 20) /**< \brief (CHIPID_CIDR) AT91x55 Series */ +#define CHIPID_CIDR_ARCH_AT91SAM7Axx (0x60u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Axx Series */ +#define CHIPID_CIDR_ARCH_AT91SAM7AQxx (0x61u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7AQxx Series */ +#define CHIPID_CIDR_ARCH_AT91x63 (0x63u << 20) /**< \brief (CHIPID_CIDR) AT91x63 Series */ +#define CHIPID_CIDR_ARCH_AT91SAM7Sxx (0x70u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Sxx Series */ +#define CHIPID_CIDR_ARCH_AT91SAM7XCxx (0x71u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7XCxx Series */ +#define CHIPID_CIDR_ARCH_AT91SAM7SExx (0x72u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SExx Series */ +#define CHIPID_CIDR_ARCH_AT91SAM7Lxx (0x73u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Lxx Series */ +#define CHIPID_CIDR_ARCH_AT91SAM7Xxx (0x75u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Xxx Series */ +#define CHIPID_CIDR_ARCH_AT91SAM7SLxx (0x76u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SLxx Series */ +#define CHIPID_CIDR_ARCH_SAM3UxC (0x80u << 20) /**< \brief (CHIPID_CIDR) SAM3UxC Series (100-pin version) */ +#define CHIPID_CIDR_ARCH_SAM3UxE (0x81u << 20) /**< \brief (CHIPID_CIDR) SAM3UxE Series (144-pin version) */ +#define CHIPID_CIDR_ARCH_SAM3AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM3AxC Series (100-pin version) */ +#define CHIPID_CIDR_ARCH_SAM4AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM4AxC Series (100-pin version) */ +#define CHIPID_CIDR_ARCH_SAM3XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM3XxC Series (100-pin version) */ +#define CHIPID_CIDR_ARCH_SAM4XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM4XxC Series (100-pin version) */ +#define CHIPID_CIDR_ARCH_SAM3XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM3XxE Series (144-pin version) */ +#define CHIPID_CIDR_ARCH_SAM4XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM4XxE Series (144-pin version) */ +#define CHIPID_CIDR_ARCH_SAM3XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM3XxG Series (208/217-pin version) */ +#define CHIPID_CIDR_ARCH_SAM4XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM4XxG Series (208/217-pin version) */ +#define CHIPID_CIDR_ARCH_SAM3SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM3SxASeries (48-pin version) */ +#define CHIPID_CIDR_ARCH_SAM4SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM4SxA Series (48-pin version) */ +#define CHIPID_CIDR_ARCH_SAM3SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM3SxB Series (64-pin version) */ +#define CHIPID_CIDR_ARCH_SAM4SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM4SxB Series (64-pin version) */ +#define CHIPID_CIDR_ARCH_SAM3SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM3SxC Series (100-pin version) */ +#define CHIPID_CIDR_ARCH_SAM4SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM4SxC Series (100-pin version) */ +#define CHIPID_CIDR_ARCH_AT91x92 (0x92u << 20) /**< \brief (CHIPID_CIDR) AT91x92 Series */ +#define CHIPID_CIDR_ARCH_SAM3NxA (0x93u << 20) /**< \brief (CHIPID_CIDR) SAM3NxA Series (48-pin version) */ +#define CHIPID_CIDR_ARCH_SAM3NxB (0x94u << 20) /**< \brief (CHIPID_CIDR) SAM3NxB Series (64-pin version) */ +#define CHIPID_CIDR_ARCH_SAM3NxC (0x95u << 20) /**< \brief (CHIPID_CIDR) SAM3NxC Series (100-pin version) */ +#define CHIPID_CIDR_ARCH_SAM3SDxB (0x99u << 20) /**< \brief (CHIPID_CIDR) SAM3SDxB Series (64-pin version) */ +#define CHIPID_CIDR_ARCH_SAM3SDxC (0x9Au << 20) /**< \brief (CHIPID_CIDR) SAM3SDxC Series (100-pin version) */ +#define CHIPID_CIDR_ARCH_SAM5A (0xA5u << 20) /**< \brief (CHIPID_CIDR) SAM5A */ +#define CHIPID_CIDR_ARCH_AT75Cxx (0xF0u << 20) /**< \brief (CHIPID_CIDR) AT75Cxx Series */ +#define CHIPID_CIDR_NVPTYP_Pos 28 +#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */ +#define CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */ +#define CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */ +#define CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */ +#define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash MemoryNVPSIZ is ROM size NVPSIZ2 is Flash size */ +#define CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */ +#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */ +/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */ +#define CHIPID_EXID_EXID_Pos 0 +#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */ + +/*@}*/ + + +#endif /* _SAM3XA_CHIPID_COMPONENT_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h new file mode 100644 index 0000000..b35b43c --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_dacc.h @@ -0,0 +1,225 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_DACC_COMPONENT_ +#define _SAM3XA_DACC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */ +/* ============================================================================= */ +/** \addtogroup SAM3XA_DACC Digital-to-Analog Converter Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Dacc hardware registers */ +typedef struct { + WoReg DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */ + RwReg DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */ + RoReg Reserved1[2]; + WoReg DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */ + WoReg DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */ + RoReg DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */ + RoReg Reserved2[1]; + WoReg DACC_CDR; /**< \brief (Dacc Offset: 0x20) Conversion Data Register */ + WoReg DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */ + WoReg DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */ + RoReg DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */ + RoReg DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */ + RoReg Reserved3[24]; + RwReg DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */ + RoReg Reserved4[19]; + RwReg DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protect Mode register */ + RoReg DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protect Status register */ + RoReg Reserved5[7]; + RwReg DACC_TPR; /**< \brief (Dacc Offset: 0x108) Transmit Pointer Register */ + RwReg DACC_TCR; /**< \brief (Dacc Offset: 0x10C) Transmit Counter Register */ + RoReg Reserved6[2]; + RwReg DACC_TNPR; /**< \brief (Dacc Offset: 0x118) Transmit Next Pointer Register */ + RwReg DACC_TNCR; /**< \brief (Dacc Offset: 0x11C) Transmit Next Counter Register */ + WoReg DACC_PTCR; /**< \brief (Dacc Offset: 0x120) Transfer Control Register */ + RoReg DACC_PTSR; /**< \brief (Dacc Offset: 0x124) Transfer Status Register */ +} Dacc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */ +#define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */ +/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */ +#define DACC_MR_TRGEN (0x1u << 0) /**< \brief (DACC_MR) Trigger Enable */ +#define DACC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (DACC_MR) External trigger mode disabled. DACC in free running mode. */ +#define DACC_MR_TRGEN_EN (0x1u << 0) /**< \brief (DACC_MR) External trigger mode enabled. */ +#define DACC_MR_TRGSEL_Pos 1 +#define DACC_MR_TRGSEL_Msk (0x7u << DACC_MR_TRGSEL_Pos) /**< \brief (DACC_MR) Trigger Selection */ +#define DACC_MR_TRGSEL(value) ((DACC_MR_TRGSEL_Msk & ((value) << DACC_MR_TRGSEL_Pos))) +#define DACC_MR_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */ +#define DACC_MR_WORD_HALF (0x0u << 4) /**< \brief (DACC_MR) Half-Word transfer */ +#define DACC_MR_WORD_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */ +#define DACC_MR_SLEEP (0x1u << 5) /**< \brief (DACC_MR) Sleep Mode */ +#define DACC_MR_FASTWKUP (0x1u << 6) /**< \brief (DACC_MR) Fast Wake up Mode */ +#define DACC_MR_REFRESH_Pos 8 +#define DACC_MR_REFRESH_Msk (0xffu << DACC_MR_REFRESH_Pos) /**< \brief (DACC_MR) Refresh Period */ +#define DACC_MR_REFRESH(value) ((DACC_MR_REFRESH_Msk & ((value) << DACC_MR_REFRESH_Pos))) +#define DACC_MR_USER_SEL_Pos 16 +#define DACC_MR_USER_SEL_Msk (0x3u << DACC_MR_USER_SEL_Pos) /**< \brief (DACC_MR) User Channel Selection */ +#define DACC_MR_USER_SEL_CHANNEL0 (0x0u << 16) /**< \brief (DACC_MR) Channel 0 */ +#define DACC_MR_USER_SEL_CHANNEL1 (0x1u << 16) /**< \brief (DACC_MR) Channel 1 */ +#define DACC_MR_TAG (0x1u << 20) /**< \brief (DACC_MR) Tag Selection Mode */ +#define DACC_MR_TAG_DIS (0x0u << 20) /**< \brief (DACC_MR) Tag selection mode disabled. Using USER_SEL to select the channel for the conversion. */ +#define DACC_MR_TAG_EN (0x1u << 20) /**< \brief (DACC_MR) Tag selection mode enabled */ +#define DACC_MR_MAXS (0x1u << 21) /**< \brief (DACC_MR) Max Speed Mode */ +#define DACC_MR_MAXS_NORMAL (0x0u << 21) /**< \brief (DACC_MR) Normal Mode */ +#define DACC_MR_MAXS_MAXIMUM (0x1u << 21) /**< \brief (DACC_MR) Max Speed Mode enabled */ +#define DACC_MR_STARTUP_Pos 24 +#define DACC_MR_STARTUP_Msk (0x3fu << DACC_MR_STARTUP_Pos) /**< \brief (DACC_MR) Startup Time Selection */ +#define DACC_MR_STARTUP_0 (0x0u << 24) /**< \brief (DACC_MR) 0 periods of DACClock */ +#define DACC_MR_STARTUP_8 (0x1u << 24) /**< \brief (DACC_MR) 8 periods of DACClock */ +#define DACC_MR_STARTUP_16 (0x2u << 24) /**< \brief (DACC_MR) 16 periods of DACClock */ +#define DACC_MR_STARTUP_24 (0x3u << 24) /**< \brief (DACC_MR) 24 periods of DACClock */ +#define DACC_MR_STARTUP_64 (0x4u << 24) /**< \brief (DACC_MR) 64 periods of DACClock */ +#define DACC_MR_STARTUP_80 (0x5u << 24) /**< \brief (DACC_MR) 80 periods of DACClock */ +#define DACC_MR_STARTUP_96 (0x6u << 24) /**< \brief (DACC_MR) 96 periods of DACClock */ +#define DACC_MR_STARTUP_112 (0x7u << 24) /**< \brief (DACC_MR) 112 periods of DACClock */ +#define DACC_MR_STARTUP_512 (0x8u << 24) /**< \brief (DACC_MR) 512 periods of DACClock */ +#define DACC_MR_STARTUP_576 (0x9u << 24) /**< \brief (DACC_MR) 576 periods of DACClock */ +#define DACC_MR_STARTUP_640 (0xAu << 24) /**< \brief (DACC_MR) 640 periods of DACClock */ +#define DACC_MR_STARTUP_704 (0xBu << 24) /**< \brief (DACC_MR) 704 periods of DACClock */ +#define DACC_MR_STARTUP_768 (0xCu << 24) /**< \brief (DACC_MR) 768 periods of DACClock */ +#define DACC_MR_STARTUP_832 (0xDu << 24) /**< \brief (DACC_MR) 832 periods of DACClock */ +#define DACC_MR_STARTUP_896 (0xEu << 24) /**< \brief (DACC_MR) 896 periods of DACClock */ +#define DACC_MR_STARTUP_960 (0xFu << 24) /**< \brief (DACC_MR) 960 periods of DACClock */ +#define DACC_MR_STARTUP_1024 (0x10u << 24) /**< \brief (DACC_MR) 1024 periods of DACClock */ +#define DACC_MR_STARTUP_1088 (0x11u << 24) /**< \brief (DACC_MR) 1088 periods of DACClock */ +#define DACC_MR_STARTUP_1152 (0x12u << 24) /**< \brief (DACC_MR) 1152 periods of DACClock */ +#define DACC_MR_STARTUP_1216 (0x13u << 24) /**< \brief (DACC_MR) 1216 periods of DACClock */ +#define DACC_MR_STARTUP_1280 (0x14u << 24) /**< \brief (DACC_MR) 1280 periods of DACClock */ +#define DACC_MR_STARTUP_1344 (0x15u << 24) /**< \brief (DACC_MR) 1344 periods of DACClock */ +#define DACC_MR_STARTUP_1408 (0x16u << 24) /**< \brief (DACC_MR) 1408 periods of DACClock */ +#define DACC_MR_STARTUP_1472 (0x17u << 24) /**< \brief (DACC_MR) 1472 periods of DACClock */ +#define DACC_MR_STARTUP_1536 (0x18u << 24) /**< \brief (DACC_MR) 1536 periods of DACClock */ +#define DACC_MR_STARTUP_1600 (0x19u << 24) /**< \brief (DACC_MR) 1600 periods of DACClock */ +#define DACC_MR_STARTUP_1664 (0x1Au << 24) /**< \brief (DACC_MR) 1664 periods of DACClock */ +#define DACC_MR_STARTUP_1728 (0x1Bu << 24) /**< \brief (DACC_MR) 1728 periods of DACClock */ +#define DACC_MR_STARTUP_1792 (0x1Cu << 24) /**< \brief (DACC_MR) 1792 periods of DACClock */ +#define DACC_MR_STARTUP_1856 (0x1Du << 24) /**< \brief (DACC_MR) 1856 periods of DACClock */ +#define DACC_MR_STARTUP_1920 (0x1Eu << 24) /**< \brief (DACC_MR) 1920 periods of DACClock */ +#define DACC_MR_STARTUP_1984 (0x1Fu << 24) /**< \brief (DACC_MR) 1984 periods of DACClock */ +/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */ +#define DACC_CHER_CH0 (0x1u << 0) /**< \brief (DACC_CHER) Channel 0 Enable */ +#define DACC_CHER_CH1 (0x1u << 1) /**< \brief (DACC_CHER) Channel 1 Enable */ +/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */ +#define DACC_CHDR_CH0 (0x1u << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */ +#define DACC_CHDR_CH1 (0x1u << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */ +/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */ +#define DACC_CHSR_CH0 (0x1u << 0) /**< \brief (DACC_CHSR) Channel 0 Status */ +#define DACC_CHSR_CH1 (0x1u << 1) /**< \brief (DACC_CHSR) Channel 1 Status */ +/* -------- DACC_CDR : (DACC Offset: 0x20) Conversion Data Register -------- */ +#define DACC_CDR_DATA_Pos 0 +#define DACC_CDR_DATA_Msk (0xffffffffu << DACC_CDR_DATA_Pos) /**< \brief (DACC_CDR) Data to Convert */ +#define DACC_CDR_DATA(value) ((DACC_CDR_DATA_Msk & ((value) << DACC_CDR_DATA_Pos))) +/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */ +#define DACC_IER_TXRDY (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable */ +#define DACC_IER_EOC (0x1u << 1) /**< \brief (DACC_IER) End of Conversion Interrupt Enable */ +#define DACC_IER_ENDTX (0x1u << 2) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable */ +#define DACC_IER_TXBUFE (0x1u << 3) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable */ +/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */ +#define DACC_IDR_TXRDY (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable. */ +#define DACC_IDR_EOC (0x1u << 1) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable */ +#define DACC_IDR_ENDTX (0x1u << 2) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable */ +#define DACC_IDR_TXBUFE (0x1u << 3) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable */ +/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */ +#define DACC_IMR_TXRDY (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask */ +#define DACC_IMR_EOC (0x1u << 1) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask */ +#define DACC_IMR_ENDTX (0x1u << 2) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask */ +#define DACC_IMR_TXBUFE (0x1u << 3) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask */ +/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */ +#define DACC_ISR_TXRDY (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag */ +#define DACC_ISR_EOC (0x1u << 1) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag */ +#define DACC_ISR_ENDTX (0x1u << 2) /**< \brief (DACC_ISR) End of DMA Interrupt Flag */ +#define DACC_ISR_TXBUFE (0x1u << 3) /**< \brief (DACC_ISR) Transmit Buffer Empty */ +/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */ +#define DACC_ACR_IBCTLCH0_Pos 0 +#define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */ +#define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos))) +#define DACC_ACR_IBCTLCH1_Pos 2 +#define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */ +#define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos))) +#define DACC_ACR_IBCTLDACCORE_Pos 8 +#define DACC_ACR_IBCTLDACCORE_Msk (0x3u << DACC_ACR_IBCTLDACCORE_Pos) /**< \brief (DACC_ACR) Bias Current Control for DAC Core */ +#define DACC_ACR_IBCTLDACCORE(value) ((DACC_ACR_IBCTLDACCORE_Msk & ((value) << DACC_ACR_IBCTLDACCORE_Pos))) +/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode register -------- */ +#define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protect Enable */ +#define DACC_WPMR_WPKEY_Pos 8 +#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect KEY */ +#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos))) +/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status register -------- */ +#define DACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (DACC_WPSR) Write protection error */ +#define DACC_WPSR_WPROTADDR_Pos 8 +#define DACC_WPSR_WPROTADDR_Msk (0xffu << DACC_WPSR_WPROTADDR_Pos) /**< \brief (DACC_WPSR) Write protection error address */ +/* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */ +#define DACC_TPR_TXPTR_Pos 0 +#define DACC_TPR_TXPTR_Msk (0xffffffffu << DACC_TPR_TXPTR_Pos) /**< \brief (DACC_TPR) Transmit Counter Register */ +#define DACC_TPR_TXPTR(value) ((DACC_TPR_TXPTR_Msk & ((value) << DACC_TPR_TXPTR_Pos))) +/* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */ +#define DACC_TCR_TXCTR_Pos 0 +#define DACC_TCR_TXCTR_Msk (0xffffu << DACC_TCR_TXCTR_Pos) /**< \brief (DACC_TCR) Transmit Counter Register */ +#define DACC_TCR_TXCTR(value) ((DACC_TCR_TXCTR_Msk & ((value) << DACC_TCR_TXCTR_Pos))) +/* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */ +#define DACC_TNPR_TXNPTR_Pos 0 +#define DACC_TNPR_TXNPTR_Msk (0xffffffffu << DACC_TNPR_TXNPTR_Pos) /**< \brief (DACC_TNPR) Transmit Next Pointer */ +#define DACC_TNPR_TXNPTR(value) ((DACC_TNPR_TXNPTR_Msk & ((value) << DACC_TNPR_TXNPTR_Pos))) +/* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */ +#define DACC_TNCR_TXNCTR_Pos 0 +#define DACC_TNCR_TXNCTR_Msk (0xffffu << DACC_TNCR_TXNCTR_Pos) /**< \brief (DACC_TNCR) Transmit Counter Next */ +#define DACC_TNCR_TXNCTR(value) ((DACC_TNCR_TXNCTR_Msk & ((value) << DACC_TNCR_TXNCTR_Pos))) +/* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */ +#define DACC_PTCR_RXTEN (0x1u << 0) /**< \brief (DACC_PTCR) Receiver Transfer Enable */ +#define DACC_PTCR_RXTDIS (0x1u << 1) /**< \brief (DACC_PTCR) Receiver Transfer Disable */ +#define DACC_PTCR_TXTEN (0x1u << 8) /**< \brief (DACC_PTCR) Transmitter Transfer Enable */ +#define DACC_PTCR_TXTDIS (0x1u << 9) /**< \brief (DACC_PTCR) Transmitter Transfer Disable */ +/* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */ +#define DACC_PTSR_RXTEN (0x1u << 0) /**< \brief (DACC_PTSR) Receiver Transfer Enable */ +#define DACC_PTSR_TXTEN (0x1u << 8) /**< \brief (DACC_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + + +#endif /* _SAM3XA_DACC_COMPONENT_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h new file mode 100644 index 0000000..783ea9e --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_dmac.h @@ -0,0 +1,382 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_DMAC_COMPONENT_ +#define _SAM3XA_DMAC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR DMA Controller */ +/* ============================================================================= */ +/** \addtogroup SAM3XA_DMAC DMA Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief DmacCh_num hardware registers */ +typedef struct { + RwReg DMAC_SADDR; /**< \brief (DmacCh_num Offset: 0x0) DMAC Channel Source Address Register */ + RwReg DMAC_DADDR; /**< \brief (DmacCh_num Offset: 0x4) DMAC Channel Destination Address Register */ + RwReg DMAC_DSCR; /**< \brief (DmacCh_num Offset: 0x8) DMAC Channel Descriptor Address Register */ + RwReg DMAC_CTRLA; /**< \brief (DmacCh_num Offset: 0xC) DMAC Channel Control A Register */ + RwReg DMAC_CTRLB; /**< \brief (DmacCh_num Offset: 0x10) DMAC Channel Control B Register */ + RwReg DMAC_CFG; /**< \brief (DmacCh_num Offset: 0x14) DMAC Channel Configuration Register */ + RoReg Reserved1[4]; +} DmacCh_num; +/** \brief Dmac hardware registers */ +#define DMACCH_NUM_NUMBER 6 +typedef struct { + RwReg DMAC_GCFG; /**< \brief (Dmac Offset: 0x000) DMAC Global Configuration Register */ + RwReg DMAC_EN; /**< \brief (Dmac Offset: 0x004) DMAC Enable Register */ + RwReg DMAC_SREQ; /**< \brief (Dmac Offset: 0x008) DMAC Software Single Request Register */ + RwReg DMAC_CREQ; /**< \brief (Dmac Offset: 0x00C) DMAC Software Chunk Transfer Request Register */ + RwReg DMAC_LAST; /**< \brief (Dmac Offset: 0x010) DMAC Software Last Transfer Flag Register */ + RoReg Reserved1[1]; + WoReg DMAC_EBCIER; /**< \brief (Dmac Offset: 0x018) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */ + WoReg DMAC_EBCIDR; /**< \brief (Dmac Offset: 0x01C) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */ + RoReg DMAC_EBCIMR; /**< \brief (Dmac Offset: 0x020) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */ + RoReg DMAC_EBCISR; /**< \brief (Dmac Offset: 0x024) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */ + WoReg DMAC_CHER; /**< \brief (Dmac Offset: 0x028) DMAC Channel Handler Enable Register */ + WoReg DMAC_CHDR; /**< \brief (Dmac Offset: 0x02C) DMAC Channel Handler Disable Register */ + RoReg DMAC_CHSR; /**< \brief (Dmac Offset: 0x030) DMAC Channel Handler Status Register */ + RoReg Reserved2[2]; + DmacCh_num DMAC_CH_NUM[DMACCH_NUM_NUMBER]; /**< \brief (Dmac Offset: 0x3C) ch_num = 0 .. 5 */ + RoReg Reserved3[46]; + RwReg DMAC_WPMR; /**< \brief (Dmac Offset: 0x1E4) DMAC Write Protect Mode Register */ + RoReg DMAC_WPSR; /**< \brief (Dmac Offset: 0x1E8) DMAC Write Protect Status Register */ +} Dmac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- DMAC_GCFG : (DMAC Offset: 0x000) DMAC Global Configuration Register -------- */ +#define DMAC_GCFG_ARB_CFG (0x1u << 4) /**< \brief (DMAC_GCFG) Arbiter Configuration */ +#define DMAC_GCFG_ARB_CFG_FIXED (0x0u << 4) /**< \brief (DMAC_GCFG) Fixed priority arbiter. */ +#define DMAC_GCFG_ARB_CFG_ROUND_ROBIN (0x1u << 4) /**< \brief (DMAC_GCFG) Modified round robin arbiter. */ +/* -------- DMAC_EN : (DMAC Offset: 0x004) DMAC Enable Register -------- */ +#define DMAC_EN_ENABLE (0x1u << 0) /**< \brief (DMAC_EN) */ +/* -------- DMAC_SREQ : (DMAC Offset: 0x008) DMAC Software Single Request Register -------- */ +#define DMAC_SREQ_SSREQ0 (0x1u << 0) /**< \brief (DMAC_SREQ) Source Request */ +#define DMAC_SREQ_DSREQ0 (0x1u << 1) /**< \brief (DMAC_SREQ) Destination Request */ +#define DMAC_SREQ_SSREQ1 (0x1u << 2) /**< \brief (DMAC_SREQ) Source Request */ +#define DMAC_SREQ_DSREQ1 (0x1u << 3) /**< \brief (DMAC_SREQ) Destination Request */ +#define DMAC_SREQ_SSREQ2 (0x1u << 4) /**< \brief (DMAC_SREQ) Source Request */ +#define DMAC_SREQ_DSREQ2 (0x1u << 5) /**< \brief (DMAC_SREQ) Destination Request */ +#define DMAC_SREQ_SSREQ3 (0x1u << 6) /**< \brief (DMAC_SREQ) Source Request */ +#define DMAC_SREQ_DSREQ3 (0x1u << 7) /**< \brief (DMAC_SREQ) Destination Request */ +#define DMAC_SREQ_SSREQ4 (0x1u << 8) /**< \brief (DMAC_SREQ) Source Request */ +#define DMAC_SREQ_DSREQ4 (0x1u << 9) /**< \brief (DMAC_SREQ) Destination Request */ +#define DMAC_SREQ_SSREQ5 (0x1u << 10) /**< \brief (DMAC_SREQ) Source Request */ +#define DMAC_SREQ_DSREQ5 (0x1u << 11) /**< \brief (DMAC_SREQ) Destination Request */ +/* -------- DMAC_CREQ : (DMAC Offset: 0x00C) DMAC Software Chunk Transfer Request Register -------- */ +#define DMAC_CREQ_SCREQ0 (0x1u << 0) /**< \brief (DMAC_CREQ) Source Chunk Request */ +#define DMAC_CREQ_DCREQ0 (0x1u << 1) /**< \brief (DMAC_CREQ) Destination Chunk Request */ +#define DMAC_CREQ_SCREQ1 (0x1u << 2) /**< \brief (DMAC_CREQ) Source Chunk Request */ +#define DMAC_CREQ_DCREQ1 (0x1u << 3) /**< \brief (DMAC_CREQ) Destination Chunk Request */ +#define DMAC_CREQ_SCREQ2 (0x1u << 4) /**< \brief (DMAC_CREQ) Source Chunk Request */ +#define DMAC_CREQ_DCREQ2 (0x1u << 5) /**< \brief (DMAC_CREQ) Destination Chunk Request */ +#define DMAC_CREQ_SCREQ3 (0x1u << 6) /**< \brief (DMAC_CREQ) Source Chunk Request */ +#define DMAC_CREQ_DCREQ3 (0x1u << 7) /**< \brief (DMAC_CREQ) Destination Chunk Request */ +#define DMAC_CREQ_SCREQ4 (0x1u << 8) /**< \brief (DMAC_CREQ) Source Chunk Request */ +#define DMAC_CREQ_DCREQ4 (0x1u << 9) /**< \brief (DMAC_CREQ) Destination Chunk Request */ +#define DMAC_CREQ_SCREQ5 (0x1u << 10) /**< \brief (DMAC_CREQ) Source Chunk Request */ +#define DMAC_CREQ_DCREQ5 (0x1u << 11) /**< \brief (DMAC_CREQ) Destination Chunk Request */ +/* -------- DMAC_LAST : (DMAC Offset: 0x010) DMAC Software Last Transfer Flag Register -------- */ +#define DMAC_LAST_SLAST0 (0x1u << 0) /**< \brief (DMAC_LAST) Source Last */ +#define DMAC_LAST_DLAST0 (0x1u << 1) /**< \brief (DMAC_LAST) Destination Last */ +#define DMAC_LAST_SLAST1 (0x1u << 2) /**< \brief (DMAC_LAST) Source Last */ +#define DMAC_LAST_DLAST1 (0x1u << 3) /**< \brief (DMAC_LAST) Destination Last */ +#define DMAC_LAST_SLAST2 (0x1u << 4) /**< \brief (DMAC_LAST) Source Last */ +#define DMAC_LAST_DLAST2 (0x1u << 5) /**< \brief (DMAC_LAST) Destination Last */ +#define DMAC_LAST_SLAST3 (0x1u << 6) /**< \brief (DMAC_LAST) Source Last */ +#define DMAC_LAST_DLAST3 (0x1u << 7) /**< \brief (DMAC_LAST) Destination Last */ +#define DMAC_LAST_SLAST4 (0x1u << 8) /**< \brief (DMAC_LAST) Source Last */ +#define DMAC_LAST_DLAST4 (0x1u << 9) /**< \brief (DMAC_LAST) Destination Last */ +#define DMAC_LAST_SLAST5 (0x1u << 10) /**< \brief (DMAC_LAST) Source Last */ +#define DMAC_LAST_DLAST5 (0x1u << 11) /**< \brief (DMAC_LAST) Destination Last */ +/* -------- DMAC_EBCIER : (DMAC Offset: 0x018) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. -------- */ +#define DMAC_EBCIER_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIER_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIER_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIER_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIER_BTC4 (0x1u << 4) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIER_BTC5 (0x1u << 5) /**< \brief (DMAC_EBCIER) Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIER_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIER_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIER_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIER_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIER_CBTC4 (0x1u << 12) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIER_CBTC5 (0x1u << 13) /**< \brief (DMAC_EBCIER) Chained Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIER_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIER) Access Error [5:0] */ +#define DMAC_EBCIER_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIER) Access Error [5:0] */ +#define DMAC_EBCIER_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIER) Access Error [5:0] */ +#define DMAC_EBCIER_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIER) Access Error [5:0] */ +#define DMAC_EBCIER_ERR4 (0x1u << 20) /**< \brief (DMAC_EBCIER) Access Error [5:0] */ +#define DMAC_EBCIER_ERR5 (0x1u << 21) /**< \brief (DMAC_EBCIER) Access Error [5:0] */ +/* -------- DMAC_EBCIDR : (DMAC Offset: 0x01C) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. -------- */ +#define DMAC_EBCIDR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIDR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIDR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIDR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIDR_BTC4 (0x1u << 4) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIDR_BTC5 (0x1u << 5) /**< \brief (DMAC_EBCIDR) Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIDR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIDR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIDR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIDR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIDR_CBTC4 (0x1u << 12) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIDR_CBTC5 (0x1u << 13) /**< \brief (DMAC_EBCIDR) Chained Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIDR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */ +#define DMAC_EBCIDR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */ +#define DMAC_EBCIDR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */ +#define DMAC_EBCIDR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */ +#define DMAC_EBCIDR_ERR4 (0x1u << 20) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */ +#define DMAC_EBCIDR_ERR5 (0x1u << 21) /**< \brief (DMAC_EBCIDR) Access Error [5:0] */ +/* -------- DMAC_EBCIMR : (DMAC Offset: 0x020) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. -------- */ +#define DMAC_EBCIMR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIMR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIMR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIMR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIMR_BTC4 (0x1u << 4) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIMR_BTC5 (0x1u << 5) /**< \brief (DMAC_EBCIMR) Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIMR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIMR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIMR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIMR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIMR_CBTC4 (0x1u << 12) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIMR_CBTC5 (0x1u << 13) /**< \brief (DMAC_EBCIMR) Chained Buffer Transfer Completed [5:0] */ +#define DMAC_EBCIMR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */ +#define DMAC_EBCIMR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */ +#define DMAC_EBCIMR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */ +#define DMAC_EBCIMR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */ +#define DMAC_EBCIMR_ERR4 (0x1u << 20) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */ +#define DMAC_EBCIMR_ERR5 (0x1u << 21) /**< \brief (DMAC_EBCIMR) Access Error [5:0] */ +/* -------- DMAC_EBCISR : (DMAC Offset: 0x024) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. -------- */ +#define DMAC_EBCISR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */ +#define DMAC_EBCISR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */ +#define DMAC_EBCISR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */ +#define DMAC_EBCISR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */ +#define DMAC_EBCISR_BTC4 (0x1u << 4) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */ +#define DMAC_EBCISR_BTC5 (0x1u << 5) /**< \brief (DMAC_EBCISR) Buffer Transfer Completed [5:0] */ +#define DMAC_EBCISR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */ +#define DMAC_EBCISR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */ +#define DMAC_EBCISR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */ +#define DMAC_EBCISR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */ +#define DMAC_EBCISR_CBTC4 (0x1u << 12) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */ +#define DMAC_EBCISR_CBTC5 (0x1u << 13) /**< \brief (DMAC_EBCISR) Chained Buffer Transfer Completed [5:0] */ +#define DMAC_EBCISR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCISR) Access Error [5:0] */ +#define DMAC_EBCISR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCISR) Access Error [5:0] */ +#define DMAC_EBCISR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCISR) Access Error [5:0] */ +#define DMAC_EBCISR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCISR) Access Error [5:0] */ +#define DMAC_EBCISR_ERR4 (0x1u << 20) /**< \brief (DMAC_EBCISR) Access Error [5:0] */ +#define DMAC_EBCISR_ERR5 (0x1u << 21) /**< \brief (DMAC_EBCISR) Access Error [5:0] */ +/* -------- DMAC_CHER : (DMAC Offset: 0x028) DMAC Channel Handler Enable Register -------- */ +#define DMAC_CHER_ENA0 (0x1u << 0) /**< \brief (DMAC_CHER) Enable [5:0] */ +#define DMAC_CHER_ENA1 (0x1u << 1) /**< \brief (DMAC_CHER) Enable [5:0] */ +#define DMAC_CHER_ENA2 (0x1u << 2) /**< \brief (DMAC_CHER) Enable [5:0] */ +#define DMAC_CHER_ENA3 (0x1u << 3) /**< \brief (DMAC_CHER) Enable [5:0] */ +#define DMAC_CHER_ENA4 (0x1u << 4) /**< \brief (DMAC_CHER) Enable [5:0] */ +#define DMAC_CHER_ENA5 (0x1u << 5) /**< \brief (DMAC_CHER) Enable [5:0] */ +#define DMAC_CHER_SUSP0 (0x1u << 8) /**< \brief (DMAC_CHER) Suspend [5:0] */ +#define DMAC_CHER_SUSP1 (0x1u << 9) /**< \brief (DMAC_CHER) Suspend [5:0] */ +#define DMAC_CHER_SUSP2 (0x1u << 10) /**< \brief (DMAC_CHER) Suspend [5:0] */ +#define DMAC_CHER_SUSP3 (0x1u << 11) /**< \brief (DMAC_CHER) Suspend [5:0] */ +#define DMAC_CHER_SUSP4 (0x1u << 12) /**< \brief (DMAC_CHER) Suspend [5:0] */ +#define DMAC_CHER_SUSP5 (0x1u << 13) /**< \brief (DMAC_CHER) Suspend [5:0] */ +#define DMAC_CHER_KEEP0 (0x1u << 24) /**< \brief (DMAC_CHER) Keep on [5:0] */ +#define DMAC_CHER_KEEP1 (0x1u << 25) /**< \brief (DMAC_CHER) Keep on [5:0] */ +#define DMAC_CHER_KEEP2 (0x1u << 26) /**< \brief (DMAC_CHER) Keep on [5:0] */ +#define DMAC_CHER_KEEP3 (0x1u << 27) /**< \brief (DMAC_CHER) Keep on [5:0] */ +#define DMAC_CHER_KEEP4 (0x1u << 28) /**< \brief (DMAC_CHER) Keep on [5:0] */ +#define DMAC_CHER_KEEP5 (0x1u << 29) /**< \brief (DMAC_CHER) Keep on [5:0] */ +/* -------- DMAC_CHDR : (DMAC Offset: 0x02C) DMAC Channel Handler Disable Register -------- */ +#define DMAC_CHDR_DIS0 (0x1u << 0) /**< \brief (DMAC_CHDR) Disable [5:0] */ +#define DMAC_CHDR_DIS1 (0x1u << 1) /**< \brief (DMAC_CHDR) Disable [5:0] */ +#define DMAC_CHDR_DIS2 (0x1u << 2) /**< \brief (DMAC_CHDR) Disable [5:0] */ +#define DMAC_CHDR_DIS3 (0x1u << 3) /**< \brief (DMAC_CHDR) Disable [5:0] */ +#define DMAC_CHDR_DIS4 (0x1u << 4) /**< \brief (DMAC_CHDR) Disable [5:0] */ +#define DMAC_CHDR_DIS5 (0x1u << 5) /**< \brief (DMAC_CHDR) Disable [5:0] */ +#define DMAC_CHDR_RES0 (0x1u << 8) /**< \brief (DMAC_CHDR) Resume [5:0] */ +#define DMAC_CHDR_RES1 (0x1u << 9) /**< \brief (DMAC_CHDR) Resume [5:0] */ +#define DMAC_CHDR_RES2 (0x1u << 10) /**< \brief (DMAC_CHDR) Resume [5:0] */ +#define DMAC_CHDR_RES3 (0x1u << 11) /**< \brief (DMAC_CHDR) Resume [5:0] */ +#define DMAC_CHDR_RES4 (0x1u << 12) /**< \brief (DMAC_CHDR) Resume [5:0] */ +#define DMAC_CHDR_RES5 (0x1u << 13) /**< \brief (DMAC_CHDR) Resume [5:0] */ +/* -------- DMAC_CHSR : (DMAC Offset: 0x030) DMAC Channel Handler Status Register -------- */ +#define DMAC_CHSR_ENA0 (0x1u << 0) /**< \brief (DMAC_CHSR) Enable [5:0] */ +#define DMAC_CHSR_ENA1 (0x1u << 1) /**< \brief (DMAC_CHSR) Enable [5:0] */ +#define DMAC_CHSR_ENA2 (0x1u << 2) /**< \brief (DMAC_CHSR) Enable [5:0] */ +#define DMAC_CHSR_ENA3 (0x1u << 3) /**< \brief (DMAC_CHSR) Enable [5:0] */ +#define DMAC_CHSR_ENA4 (0x1u << 4) /**< \brief (DMAC_CHSR) Enable [5:0] */ +#define DMAC_CHSR_ENA5 (0x1u << 5) /**< \brief (DMAC_CHSR) Enable [5:0] */ +#define DMAC_CHSR_SUSP0 (0x1u << 8) /**< \brief (DMAC_CHSR) Suspend [5:0] */ +#define DMAC_CHSR_SUSP1 (0x1u << 9) /**< \brief (DMAC_CHSR) Suspend [5:0] */ +#define DMAC_CHSR_SUSP2 (0x1u << 10) /**< \brief (DMAC_CHSR) Suspend [5:0] */ +#define DMAC_CHSR_SUSP3 (0x1u << 11) /**< \brief (DMAC_CHSR) Suspend [5:0] */ +#define DMAC_CHSR_SUSP4 (0x1u << 12) /**< \brief (DMAC_CHSR) Suspend [5:0] */ +#define DMAC_CHSR_SUSP5 (0x1u << 13) /**< \brief (DMAC_CHSR) Suspend [5:0] */ +#define DMAC_CHSR_EMPT0 (0x1u << 16) /**< \brief (DMAC_CHSR) Empty [5:0] */ +#define DMAC_CHSR_EMPT1 (0x1u << 17) /**< \brief (DMAC_CHSR) Empty [5:0] */ +#define DMAC_CHSR_EMPT2 (0x1u << 18) /**< \brief (DMAC_CHSR) Empty [5:0] */ +#define DMAC_CHSR_EMPT3 (0x1u << 19) /**< \brief (DMAC_CHSR) Empty [5:0] */ +#define DMAC_CHSR_EMPT4 (0x1u << 20) /**< \brief (DMAC_CHSR) Empty [5:0] */ +#define DMAC_CHSR_EMPT5 (0x1u << 21) /**< \brief (DMAC_CHSR) Empty [5:0] */ +#define DMAC_CHSR_STAL0 (0x1u << 24) /**< \brief (DMAC_CHSR) Stalled [5:0] */ +#define DMAC_CHSR_STAL1 (0x1u << 25) /**< \brief (DMAC_CHSR) Stalled [5:0] */ +#define DMAC_CHSR_STAL2 (0x1u << 26) /**< \brief (DMAC_CHSR) Stalled [5:0] */ +#define DMAC_CHSR_STAL3 (0x1u << 27) /**< \brief (DMAC_CHSR) Stalled [5:0] */ +#define DMAC_CHSR_STAL4 (0x1u << 28) /**< \brief (DMAC_CHSR) Stalled [5:0] */ +#define DMAC_CHSR_STAL5 (0x1u << 29) /**< \brief (DMAC_CHSR) Stalled [5:0] */ +/* -------- DMAC_SADDR : (DMAC Offset: N/A) DMAC Channel Source Address Register -------- */ +#define DMAC_SADDR_SADDR_Pos 0 +#define DMAC_SADDR_SADDR_Msk (0xffffffffu << DMAC_SADDR_SADDR_Pos) /**< \brief (DMAC_SADDR) Channel x Source Address */ +#define DMAC_SADDR_SADDR(value) ((DMAC_SADDR_SADDR_Msk & ((value) << DMAC_SADDR_SADDR_Pos))) +/* -------- DMAC_DADDR : (DMAC Offset: N/A) DMAC Channel Destination Address Register -------- */ +#define DMAC_DADDR_DADDR_Pos 0 +#define DMAC_DADDR_DADDR_Msk (0xffffffffu << DMAC_DADDR_DADDR_Pos) /**< \brief (DMAC_DADDR) Channel x Destination Address */ +#define DMAC_DADDR_DADDR(value) ((DMAC_DADDR_DADDR_Msk & ((value) << DMAC_DADDR_DADDR_Pos))) +/* -------- DMAC_DSCR : (DMAC Offset: N/A) DMAC Channel Descriptor Address Register -------- */ +#define DMAC_DSCR_DSCR_Pos 2 +#define DMAC_DSCR_DSCR_Msk (0x3fffffffu << DMAC_DSCR_DSCR_Pos) /**< \brief (DMAC_DSCR) Buffer Transfer Descriptor Address */ +#define DMAC_DSCR_DSCR(value) ((DMAC_DSCR_DSCR_Msk & ((value) << DMAC_DSCR_DSCR_Pos))) +/* -------- DMAC_CTRLA : (DMAC Offset: N/A) DMAC Channel Control A Register -------- */ +#define DMAC_CTRLA_BTSIZE_Pos 0 +#define DMAC_CTRLA_BTSIZE_Msk (0xffffu << DMAC_CTRLA_BTSIZE_Pos) /**< \brief (DMAC_CTRLA) Buffer Transfer Size */ +#define DMAC_CTRLA_BTSIZE(value) ((DMAC_CTRLA_BTSIZE_Msk & ((value) << DMAC_CTRLA_BTSIZE_Pos))) +#define DMAC_CTRLA_SCSIZE_Pos 16 +#define DMAC_CTRLA_SCSIZE_Msk (0x7u << DMAC_CTRLA_SCSIZE_Pos) /**< \brief (DMAC_CTRLA) Source Chunk Transfer Size. */ +#define DMAC_CTRLA_SCSIZE_CHK_1 (0x0u << 16) /**< \brief (DMAC_CTRLA) 1 data transferred */ +#define DMAC_CTRLA_SCSIZE_CHK_4 (0x1u << 16) /**< \brief (DMAC_CTRLA) 4 data transferred */ +#define DMAC_CTRLA_SCSIZE_CHK_8 (0x2u << 16) /**< \brief (DMAC_CTRLA) 8 data transferred */ +#define DMAC_CTRLA_SCSIZE_CHK_16 (0x3u << 16) /**< \brief (DMAC_CTRLA) 16 data transferred */ +#define DMAC_CTRLA_SCSIZE_CHK_32 (0x4u << 16) /**< \brief (DMAC_CTRLA) 32 data transferred */ +#define DMAC_CTRLA_SCSIZE_CHK_64 (0x5u << 16) /**< \brief (DMAC_CTRLA) 64 data transferred */ +#define DMAC_CTRLA_SCSIZE_CHK_128 (0x6u << 16) /**< \brief (DMAC_CTRLA) 128 data transferred */ +#define DMAC_CTRLA_SCSIZE_CHK_256 (0x7u << 16) /**< \brief (DMAC_CTRLA) 256 data transferred */ +#define DMAC_CTRLA_DCSIZE_Pos 20 +#define DMAC_CTRLA_DCSIZE_Msk (0x7u << DMAC_CTRLA_DCSIZE_Pos) /**< \brief (DMAC_CTRLA) Destination Chunk Transfer Size */ +#define DMAC_CTRLA_DCSIZE_CHK_1 (0x0u << 20) /**< \brief (DMAC_CTRLA) 1 data transferred */ +#define DMAC_CTRLA_DCSIZE_CHK_4 (0x1u << 20) /**< \brief (DMAC_CTRLA) 4 data transferred */ +#define DMAC_CTRLA_DCSIZE_CHK_8 (0x2u << 20) /**< \brief (DMAC_CTRLA) 8 data transferred */ +#define DMAC_CTRLA_DCSIZE_CHK_16 (0x3u << 20) /**< \brief (DMAC_CTRLA) 16 data transferred */ +#define DMAC_CTRLA_DCSIZE_CHK_32 (0x4u << 20) /**< \brief (DMAC_CTRLA) 32 data transferred */ +#define DMAC_CTRLA_DCSIZE_CHK_64 (0x5u << 20) /**< \brief (DMAC_CTRLA) 64 data transferred */ +#define DMAC_CTRLA_DCSIZE_CHK_128 (0x6u << 20) /**< \brief (DMAC_CTRLA) 128 data transferred */ +#define DMAC_CTRLA_DCSIZE_CHK_256 (0x7u << 20) /**< \brief (DMAC_CTRLA) 256 data transferred */ +#define DMAC_CTRLA_SRC_WIDTH_Pos 24 +#define DMAC_CTRLA_SRC_WIDTH_Msk (0x3u << DMAC_CTRLA_SRC_WIDTH_Pos) /**< \brief (DMAC_CTRLA) Transfer Width for the Source */ +#define DMAC_CTRLA_SRC_WIDTH_BYTE (0x0u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 8-bit width */ +#define DMAC_CTRLA_SRC_WIDTH_HALF_WORD (0x1u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 16-bit width */ +#define DMAC_CTRLA_SRC_WIDTH_WORD (0x2u << 24) /**< \brief (DMAC_CTRLA) the transfer size is set to 32-bit width */ +#define DMAC_CTRLA_DST_WIDTH_Pos 28 +#define DMAC_CTRLA_DST_WIDTH_Msk (0x3u << DMAC_CTRLA_DST_WIDTH_Pos) /**< \brief (DMAC_CTRLA) Transfer Width for the Destination */ +#define DMAC_CTRLA_DST_WIDTH_BYTE (0x0u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 8-bit width */ +#define DMAC_CTRLA_DST_WIDTH_HALF_WORD (0x1u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 16-bit width */ +#define DMAC_CTRLA_DST_WIDTH_WORD (0x2u << 28) /**< \brief (DMAC_CTRLA) the transfer size is set to 32-bit width */ +#define DMAC_CTRLA_DONE (0x1u << 31) /**< \brief (DMAC_CTRLA) */ +/* -------- DMAC_CTRLB : (DMAC Offset: N/A) DMAC Channel Control B Register -------- */ +#define DMAC_CTRLB_SRC_DSCR (0x1u << 16) /**< \brief (DMAC_CTRLB) Source Address Descriptor */ +#define DMAC_CTRLB_SRC_DSCR_FETCH_FROM_MEM (0x0u << 16) /**< \brief (DMAC_CTRLB) Source address is updated when the descriptor is fetched from the memory. */ +#define DMAC_CTRLB_SRC_DSCR_FETCH_DISABLE (0x1u << 16) /**< \brief (DMAC_CTRLB) Buffer Descriptor Fetch operation is disabled for the source. */ +#define DMAC_CTRLB_DST_DSCR (0x1u << 20) /**< \brief (DMAC_CTRLB) Destination Address Descriptor */ +#define DMAC_CTRLB_DST_DSCR_FETCH_FROM_MEM (0x0u << 20) /**< \brief (DMAC_CTRLB) Destination address is updated when the descriptor is fetched from the memory. */ +#define DMAC_CTRLB_DST_DSCR_FETCH_DISABLE (0x1u << 20) /**< \brief (DMAC_CTRLB) Buffer Descriptor Fetch operation is disabled for the destination. */ +#define DMAC_CTRLB_FC_Pos 21 +#define DMAC_CTRLB_FC_Msk (0x7u << DMAC_CTRLB_FC_Pos) /**< \brief (DMAC_CTRLB) Flow Control */ +#define DMAC_CTRLB_FC_MEM2MEM_DMA_FC (0x0u << 21) /**< \brief (DMAC_CTRLB) Memory-to-Memory Transfer DMAC is flow controller */ +#define DMAC_CTRLB_FC_MEM2PER_DMA_FC (0x1u << 21) /**< \brief (DMAC_CTRLB) Memory-to-Peripheral Transfer DMAC is flow controller */ +#define DMAC_CTRLB_FC_PER2MEM_DMA_FC (0x2u << 21) /**< \brief (DMAC_CTRLB) Peripheral-to-Memory Transfer DMAC is flow controller */ +#define DMAC_CTRLB_FC_PER2PER_DMA_FC (0x3u << 21) /**< \brief (DMAC_CTRLB) Peripheral-to-Peripheral Transfer DMAC is flow controller */ +#define DMAC_CTRLB_SRC_INCR_Pos 24 +#define DMAC_CTRLB_SRC_INCR_Msk (0x3u << DMAC_CTRLB_SRC_INCR_Pos) /**< \brief (DMAC_CTRLB) Incrementing, Decrementing or Fixed Address for the Source */ +#define DMAC_CTRLB_SRC_INCR_INCREMENTING (0x0u << 24) /**< \brief (DMAC_CTRLB) The source address is incremented */ +#define DMAC_CTRLB_SRC_INCR_DECREMENTING (0x1u << 24) /**< \brief (DMAC_CTRLB) The source address is decremented */ +#define DMAC_CTRLB_SRC_INCR_FIXED (0x2u << 24) /**< \brief (DMAC_CTRLB) The source address remains unchanged */ +#define DMAC_CTRLB_DST_INCR_Pos 28 +#define DMAC_CTRLB_DST_INCR_Msk (0x3u << DMAC_CTRLB_DST_INCR_Pos) /**< \brief (DMAC_CTRLB) Incrementing, Decrementing or Fixed Address for the Destination */ +#define DMAC_CTRLB_DST_INCR_INCREMENTING (0x0u << 28) /**< \brief (DMAC_CTRLB) The destination address is incremented */ +#define DMAC_CTRLB_DST_INCR_DECREMENTING (0x1u << 28) /**< \brief (DMAC_CTRLB) The destination address is decremented */ +#define DMAC_CTRLB_DST_INCR_FIXED (0x2u << 28) /**< \brief (DMAC_CTRLB) The destination address remains unchanged */ +#define DMAC_CTRLB_IEN (0x1u << 30) /**< \brief (DMAC_CTRLB) */ +/* -------- DMAC_CFG : (DMAC Offset: N/A) DMAC Channel Configuration Register -------- */ +#define DMAC_CFG_SRC_PER_Pos 0 +#define DMAC_CFG_SRC_PER_Msk (0xfu << DMAC_CFG_SRC_PER_Pos) /**< \brief (DMAC_CFG) Source with Peripheral identifier */ +#define DMAC_CFG_SRC_PER(value) ((DMAC_CFG_SRC_PER_Msk & ((value) << DMAC_CFG_SRC_PER_Pos))) +#define DMAC_CFG_DST_PER_Pos 4 +#define DMAC_CFG_DST_PER_Msk (0xfu << DMAC_CFG_DST_PER_Pos) /**< \brief (DMAC_CFG) Destination with Peripheral identifier */ +#define DMAC_CFG_DST_PER(value) ((DMAC_CFG_DST_PER_Msk & ((value) << DMAC_CFG_DST_PER_Pos))) +#define DMAC_CFG_SRC_H2SEL (0x1u << 9) /**< \brief (DMAC_CFG) Software or Hardware Selection for the Source */ +#define DMAC_CFG_SRC_H2SEL_SW (0x0u << 9) /**< \brief (DMAC_CFG) Software handshaking interface is used to trigger a transfer request. */ +#define DMAC_CFG_SRC_H2SEL_HW (0x1u << 9) /**< \brief (DMAC_CFG) Hardware handshaking interface is used to trigger a transfer request. */ +#define DMAC_CFG_DST_H2SEL (0x1u << 13) /**< \brief (DMAC_CFG) Software or Hardware Selection for the Destination */ +#define DMAC_CFG_DST_H2SEL_SW (0x0u << 13) /**< \brief (DMAC_CFG) Software handshaking interface is used to trigger a transfer request. */ +#define DMAC_CFG_DST_H2SEL_HW (0x1u << 13) /**< \brief (DMAC_CFG) Hardware handshaking interface is used to trigger a transfer request. */ +#define DMAC_CFG_SOD (0x1u << 16) /**< \brief (DMAC_CFG) Stop On Done */ +#define DMAC_CFG_SOD_DISABLE (0x0u << 16) /**< \brief (DMAC_CFG) STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. */ +#define DMAC_CFG_SOD_ENABLE (0x1u << 16) /**< \brief (DMAC_CFG) STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. */ +#define DMAC_CFG_LOCK_IF (0x1u << 20) /**< \brief (DMAC_CFG) Interface Lock */ +#define DMAC_CFG_LOCK_IF_DISABLE (0x0u << 20) /**< \brief (DMAC_CFG) Interface Lock capability is disabled */ +#define DMAC_CFG_LOCK_IF_ENABLE (0x1u << 20) /**< \brief (DMAC_CFG) Interface Lock capability is enabled */ +#define DMAC_CFG_LOCK_B (0x1u << 21) /**< \brief (DMAC_CFG) Bus Lock */ +#define DMAC_CFG_LOCK_B_DISABLE (0x0u << 21) /**< \brief (DMAC_CFG) AHB Bus Locking capability is disabled. */ +#define DMAC_CFG_LOCK_IF_L (0x1u << 22) /**< \brief (DMAC_CFG) Master Interface Arbiter Lock */ +#define DMAC_CFG_LOCK_IF_L_CHUNK (0x0u << 22) /**< \brief (DMAC_CFG) The Master Interface Arbiter is locked by the channel x for a chunk transfer. */ +#define DMAC_CFG_LOCK_IF_L_BUFFER (0x1u << 22) /**< \brief (DMAC_CFG) The Master Interface Arbiter is locked by the channel x for a buffer transfer. */ +#define DMAC_CFG_AHB_PROT_Pos 24 +#define DMAC_CFG_AHB_PROT_Msk (0x7u << DMAC_CFG_AHB_PROT_Pos) /**< \brief (DMAC_CFG) AHB Protection */ +#define DMAC_CFG_AHB_PROT(value) ((DMAC_CFG_AHB_PROT_Msk & ((value) << DMAC_CFG_AHB_PROT_Pos))) +#define DMAC_CFG_FIFOCFG_Pos 28 +#define DMAC_CFG_FIFOCFG_Msk (0x3u << DMAC_CFG_FIFOCFG_Pos) /**< \brief (DMAC_CFG) FIFO Configuration */ +#define DMAC_CFG_FIFOCFG_ALAP_CFG (0x0u << 28) /**< \brief (DMAC_CFG) The largest defined length AHB burst is performed on the destination AHB interface. */ +#define DMAC_CFG_FIFOCFG_HALF_CFG (0x1u << 28) /**< \brief (DMAC_CFG) When half FIFO size is available/filled, a source/destination request is serviced. */ +#define DMAC_CFG_FIFOCFG_ASAP_CFG (0x2u << 28) /**< \brief (DMAC_CFG) When there is enough space/data available to perform a single AHB access, then the request is serviced. */ +/* -------- DMAC_WPMR : (DMAC Offset: 0x1E4) DMAC Write Protect Mode Register -------- */ +#define DMAC_WPMR_WPEN (0x1u << 0) /**< \brief (DMAC_WPMR) Write Protect Enable */ +#define DMAC_WPMR_WPKEY_Pos 8 +#define DMAC_WPMR_WPKEY_Msk (0xffffffu << DMAC_WPMR_WPKEY_Pos) /**< \brief (DMAC_WPMR) Write Protect KEY */ +#define DMAC_WPMR_WPKEY(value) ((DMAC_WPMR_WPKEY_Msk & ((value) << DMAC_WPMR_WPKEY_Pos))) +/* -------- DMAC_WPSR : (DMAC Offset: 0x1E8) DMAC Write Protect Status Register -------- */ +#define DMAC_WPSR_WPVS (0x1u << 0) /**< \brief (DMAC_WPSR) Write Protect Violation Status */ +#define DMAC_WPSR_WPVSRC_Pos 8 +#define DMAC_WPSR_WPVSRC_Msk (0xffffu << DMAC_WPSR_WPVSRC_Pos) /**< \brief (DMAC_WPSR) Write Protect Violation Source */ + +/*@}*/ + + +#endif /* _SAM3XA_DMAC_COMPONENT_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h new file mode 100644 index 0000000..d500e9d --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_efc.h @@ -0,0 +1,91 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_EFC_COMPONENT_ +#define _SAM3XA_EFC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */ +/* ============================================================================= */ +/** \addtogroup SAM3XA_EFC Embedded Flash Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Efc hardware registers */ +typedef struct { + RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */ + WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */ + RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */ + RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */ +} Efc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */ +#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */ +#define EEFC_FMR_FWS_Pos 8 +#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */ +#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos))) +#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */ +#define EEFC_FMR_FAM (0x1u << 24) /**< \brief (EEFC_FMR) Flash Access Mode */ +/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */ +#define EEFC_FCR_FCMD_Pos 0 +#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */ +#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos))) +#define EEFC_FCR_FARG_Pos 8 +#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */ +#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos))) +#define EEFC_FCR_FKEY_Pos 24 +#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */ +#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos))) +/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */ +#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status */ +#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */ +#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */ +/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */ +#define EEFC_FRR_FVALUE_Pos 0 +#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */ + +/*@}*/ + + +#endif /* _SAM3XA_EFC_COMPONENT_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h new file mode 100644 index 0000000..f400e31 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_emac.h @@ -0,0 +1,350 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_EMAC_COMPONENT_ +#define _SAM3XA_EMAC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 */ +/* ============================================================================= */ +/** \addtogroup SAM3XA_EMAC Ethernet MAC 10/100 */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief EmacSa hardware registers */ +typedef struct { + RwReg EMAC_SAxB; /**< \brief (EmacSa Offset: 0x0) Specific Address 1 Bottom Register */ + RwReg EMAC_SAxT; /**< \brief (EmacSa Offset: 0x4) Specific Address 1 Top Register */ +} EmacSa; +/** \brief Emac hardware registers */ +#define EMACSA_NUMBER 4 +typedef struct { + RwReg EMAC_NCR; /**< \brief (Emac Offset: 0x00) Network Control Register */ + RwReg EMAC_NCFGR; /**< \brief (Emac Offset: 0x04) Network Configuration Register */ + RoReg EMAC_NSR; /**< \brief (Emac Offset: 0x08) Network Status Register */ + RoReg Reserved1[2]; + RwReg EMAC_TSR; /**< \brief (Emac Offset: 0x14) Transmit Status Register */ + RwReg EMAC_RBQP; /**< \brief (Emac Offset: 0x18) Receive Buffer Queue Pointer Register */ + RwReg EMAC_TBQP; /**< \brief (Emac Offset: 0x1C) Transmit Buffer Queue Pointer Register */ + RwReg EMAC_RSR; /**< \brief (Emac Offset: 0x20) Receive Status Register */ + RwReg EMAC_ISR; /**< \brief (Emac Offset: 0x24) Interrupt Status Register */ + WoReg EMAC_IER; /**< \brief (Emac Offset: 0x28) Interrupt Enable Register */ + WoReg EMAC_IDR; /**< \brief (Emac Offset: 0x2C) Interrupt Disable Register */ + RoReg EMAC_IMR; /**< \brief (Emac Offset: 0x30) Interrupt Mask Register */ + RwReg EMAC_MAN; /**< \brief (Emac Offset: 0x34) Phy Maintenance Register */ + RwReg EMAC_PTR; /**< \brief (Emac Offset: 0x38) Pause Time Register */ + RwReg EMAC_PFR; /**< \brief (Emac Offset: 0x3C) Pause Frames Received Register */ + RwReg EMAC_FTO; /**< \brief (Emac Offset: 0x40) Frames Transmitted Ok Register */ + RwReg EMAC_SCF; /**< \brief (Emac Offset: 0x44) Single Collision Frames Register */ + RwReg EMAC_MCF; /**< \brief (Emac Offset: 0x48) Multiple Collision Frames Register */ + RwReg EMAC_FRO; /**< \brief (Emac Offset: 0x4C) Frames Received Ok Register */ + RwReg EMAC_FCSE; /**< \brief (Emac Offset: 0x50) Frame Check Sequence Errors Register */ + RwReg EMAC_ALE; /**< \brief (Emac Offset: 0x54) Alignment Errors Register */ + RwReg EMAC_DTF; /**< \brief (Emac Offset: 0x58) Deferred Transmission Frames Register */ + RwReg EMAC_LCOL; /**< \brief (Emac Offset: 0x5C) Late Collisions Register */ + RwReg EMAC_ECOL; /**< \brief (Emac Offset: 0x60) Excessive Collisions Register */ + RwReg EMAC_TUND; /**< \brief (Emac Offset: 0x64) Transmit Underrun Errors Register */ + RwReg EMAC_CSE; /**< \brief (Emac Offset: 0x68) Carrier Sense Errors Register */ + RwReg EMAC_RRE; /**< \brief (Emac Offset: 0x6C) Receive Resource Errors Register */ + RwReg EMAC_ROV; /**< \brief (Emac Offset: 0x70) Receive Overrun Errors Register */ + RwReg EMAC_RSE; /**< \brief (Emac Offset: 0x74) Receive Symbol Errors Register */ + RwReg EMAC_ELE; /**< \brief (Emac Offset: 0x78) Excessive Length Errors Register */ + RwReg EMAC_RJA; /**< \brief (Emac Offset: 0x7C) Receive Jabbers Register */ + RwReg EMAC_USF; /**< \brief (Emac Offset: 0x80) Undersize Frames Register */ + RwReg EMAC_STE; /**< \brief (Emac Offset: 0x84) SQE Test Errors Register */ + RwReg EMAC_RLE; /**< \brief (Emac Offset: 0x88) Received Length Field Mismatch Register */ + RoReg Reserved2[1]; + RwReg EMAC_HRB; /**< \brief (Emac Offset: 0x90) Hash Register Bottom [31:0] Register */ + RwReg EMAC_HRT; /**< \brief (Emac Offset: 0x94) Hash Register Top [63:32] Register */ + EmacSa EMAC_SA[EMACSA_NUMBER]; /**< \brief (Emac Offset: 0x98) sa = 1 .. 4 */ + RwReg EMAC_TID; /**< \brief (Emac Offset: 0xB8) Type ID Checking Register */ + RoReg Reserved3[1]; + RwReg EMAC_USRIO; /**< \brief (Emac Offset: 0xC0) User Input/Output Register */ +} Emac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- EMAC_NCR : (EMAC Offset: 0x00) Network Control Register -------- */ +#define EMAC_NCR_LB (0x1u << 0) /**< \brief (EMAC_NCR) LoopBack */ +#define EMAC_NCR_LLB (0x1u << 1) /**< \brief (EMAC_NCR) Loopback local */ +#define EMAC_NCR_RE (0x1u << 2) /**< \brief (EMAC_NCR) Receive enable */ +#define EMAC_NCR_TE (0x1u << 3) /**< \brief (EMAC_NCR) Transmit enable */ +#define EMAC_NCR_MPE (0x1u << 4) /**< \brief (EMAC_NCR) Management port enable */ +#define EMAC_NCR_CLRSTAT (0x1u << 5) /**< \brief (EMAC_NCR) Clear statistics registers */ +#define EMAC_NCR_INCSTAT (0x1u << 6) /**< \brief (EMAC_NCR) Increment statistics registers */ +#define EMAC_NCR_WESTAT (0x1u << 7) /**< \brief (EMAC_NCR) Write enable for statistics registers */ +#define EMAC_NCR_BP (0x1u << 8) /**< \brief (EMAC_NCR) Back pressure */ +#define EMAC_NCR_TSTART (0x1u << 9) /**< \brief (EMAC_NCR) Start transmission */ +#define EMAC_NCR_THALT (0x1u << 10) /**< \brief (EMAC_NCR) Transmit halt */ +/* -------- EMAC_NCFGR : (EMAC Offset: 0x04) Network Configuration Register -------- */ +#define EMAC_NCFGR_SPD (0x1u << 0) /**< \brief (EMAC_NCFGR) Speed */ +#define EMAC_NCFGR_FD (0x1u << 1) /**< \brief (EMAC_NCFGR) Full Duplex */ +#define EMAC_NCFGR_JFRAME (0x1u << 3) /**< \brief (EMAC_NCFGR) Jumbo Frames */ +#define EMAC_NCFGR_CAF (0x1u << 4) /**< \brief (EMAC_NCFGR) Copy All Frames */ +#define EMAC_NCFGR_NBC (0x1u << 5) /**< \brief (EMAC_NCFGR) No Broadcast */ +#define EMAC_NCFGR_MTI (0x1u << 6) /**< \brief (EMAC_NCFGR) Multicast Hash Enable */ +#define EMAC_NCFGR_UNI (0x1u << 7) /**< \brief (EMAC_NCFGR) Unicast Hash Enable */ +#define EMAC_NCFGR_BIG (0x1u << 8) /**< \brief (EMAC_NCFGR) Receive 1536 bytes frames */ +#define EMAC_NCFGR_CLK_Pos 10 +#define EMAC_NCFGR_CLK_Msk (0x3u << EMAC_NCFGR_CLK_Pos) /**< \brief (EMAC_NCFGR) MDC clock divider */ +#define EMAC_NCFGR_CLK_MCK_8 (0x0u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz). */ +#define EMAC_NCFGR_CLK_MCK_16 (0x1u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz). */ +#define EMAC_NCFGR_CLK_MCK_32 (0x2u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz). */ +#define EMAC_NCFGR_CLK_MCK_64 (0x3u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz). */ +#define EMAC_NCFGR_RTY (0x1u << 12) /**< \brief (EMAC_NCFGR) Retry test */ +#define EMAC_NCFGR_PAE (0x1u << 13) /**< \brief (EMAC_NCFGR) Pause Enable */ +#define EMAC_NCFGR_RBOF_Pos 14 +#define EMAC_NCFGR_RBOF_Msk (0x3u << EMAC_NCFGR_RBOF_Pos) /**< \brief (EMAC_NCFGR) Receive Buffer Offset */ +#define EMAC_NCFGR_RBOF_OFFSET_0 (0x0u << 14) /**< \brief (EMAC_NCFGR) No offset from start of receive buffer. */ +#define EMAC_NCFGR_RBOF_OFFSET_1 (0x1u << 14) /**< \brief (EMAC_NCFGR) One-byte offset from start of receive buffer. */ +#define EMAC_NCFGR_RBOF_OFFSET_2 (0x2u << 14) /**< \brief (EMAC_NCFGR) Two-byte offset from start of receive buffer. */ +#define EMAC_NCFGR_RBOF_OFFSET_3 (0x3u << 14) /**< \brief (EMAC_NCFGR) Three-byte offset from start of receive buffer. */ +#define EMAC_NCFGR_RLCE (0x1u << 16) /**< \brief (EMAC_NCFGR) Receive Length field Checking Enable */ +#define EMAC_NCFGR_DRFCS (0x1u << 17) /**< \brief (EMAC_NCFGR) Discard Receive FCS */ +#define EMAC_NCFGR_EFRHD (0x1u << 18) /**< \brief (EMAC_NCFGR) */ +#define EMAC_NCFGR_IRXFCS (0x1u << 19) /**< \brief (EMAC_NCFGR) Ignore RX FCS */ +/* -------- EMAC_NSR : (EMAC Offset: 0x08) Network Status Register -------- */ +#define EMAC_NSR_MDIO (0x1u << 1) /**< \brief (EMAC_NSR) */ +#define EMAC_NSR_IDLE (0x1u << 2) /**< \brief (EMAC_NSR) */ +/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */ +#define EMAC_TSR_UBR (0x1u << 0) /**< \brief (EMAC_TSR) Used Bit Read */ +#define EMAC_TSR_COL (0x1u << 1) /**< \brief (EMAC_TSR) Collision Occurred */ +#define EMAC_TSR_RLES (0x1u << 2) /**< \brief (EMAC_TSR) Retry Limit exceeded */ +#define EMAC_TSR_TGO (0x1u << 3) /**< \brief (EMAC_TSR) Transmit Go */ +#define EMAC_TSR_BEX (0x1u << 4) /**< \brief (EMAC_TSR) Buffers exhausted mid frame */ +#define EMAC_TSR_COMP (0x1u << 5) /**< \brief (EMAC_TSR) Transmit Complete */ +#define EMAC_TSR_UND (0x1u << 6) /**< \brief (EMAC_TSR) Transmit Underrun */ +/* -------- EMAC_RBQP : (EMAC Offset: 0x18) Receive Buffer Queue Pointer Register -------- */ +#define EMAC_RBQP_ADDR_Pos 2 +#define EMAC_RBQP_ADDR_Msk (0x3fffffffu << EMAC_RBQP_ADDR_Pos) /**< \brief (EMAC_RBQP) Receive buffer queue pointer address */ +#define EMAC_RBQP_ADDR(value) ((EMAC_RBQP_ADDR_Msk & ((value) << EMAC_RBQP_ADDR_Pos))) +/* -------- EMAC_TBQP : (EMAC Offset: 0x1C) Transmit Buffer Queue Pointer Register -------- */ +#define EMAC_TBQP_ADDR_Pos 2 +#define EMAC_TBQP_ADDR_Msk (0x3fffffffu << EMAC_TBQP_ADDR_Pos) /**< \brief (EMAC_TBQP) Transmit buffer queue pointer address */ +#define EMAC_TBQP_ADDR(value) ((EMAC_TBQP_ADDR_Msk & ((value) << EMAC_TBQP_ADDR_Pos))) +/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */ +#define EMAC_RSR_BNA (0x1u << 0) /**< \brief (EMAC_RSR) Buffer Not Available */ +#define EMAC_RSR_REC (0x1u << 1) /**< \brief (EMAC_RSR) Frame Received */ +#define EMAC_RSR_OVR (0x1u << 2) /**< \brief (EMAC_RSR) Receive Overrun */ +/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */ +#define EMAC_ISR_MFD (0x1u << 0) /**< \brief (EMAC_ISR) Management Frame Done */ +#define EMAC_ISR_RCOMP (0x1u << 1) /**< \brief (EMAC_ISR) Receive Complete */ +#define EMAC_ISR_RXUBR (0x1u << 2) /**< \brief (EMAC_ISR) Receive Used Bit Read */ +#define EMAC_ISR_TXUBR (0x1u << 3) /**< \brief (EMAC_ISR) Transmit Used Bit Read */ +#define EMAC_ISR_TUND (0x1u << 4) /**< \brief (EMAC_ISR) Ethernet Transmit Buffer Underrun */ +#define EMAC_ISR_RLEX (0x1u << 5) /**< \brief (EMAC_ISR) Retry Limit Exceeded */ +#define EMAC_ISR_TXERR (0x1u << 6) /**< \brief (EMAC_ISR) Transmit Error */ +#define EMAC_ISR_TCOMP (0x1u << 7) /**< \brief (EMAC_ISR) Transmit Complete */ +#define EMAC_ISR_ROVR (0x1u << 10) /**< \brief (EMAC_ISR) Receive Overrun */ +#define EMAC_ISR_HRESP (0x1u << 11) /**< \brief (EMAC_ISR) Hresp not OK */ +#define EMAC_ISR_PFRE (0x1u << 12) /**< \brief (EMAC_ISR) Pause Frame Received */ +#define EMAC_ISR_PTZ (0x1u << 13) /**< \brief (EMAC_ISR) Pause Time Zero */ +/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */ +#define EMAC_IER_MFD (0x1u << 0) /**< \brief (EMAC_IER) Management Frame sent */ +#define EMAC_IER_RCOMP (0x1u << 1) /**< \brief (EMAC_IER) Receive Complete */ +#define EMAC_IER_RXUBR (0x1u << 2) /**< \brief (EMAC_IER) Receive Used Bit Read */ +#define EMAC_IER_TXUBR (0x1u << 3) /**< \brief (EMAC_IER) Transmit Used Bit Read */ +#define EMAC_IER_TUND (0x1u << 4) /**< \brief (EMAC_IER) Ethernet Transmit Buffer Underrun */ +#define EMAC_IER_RLE (0x1u << 5) /**< \brief (EMAC_IER) Retry Limit Exceeded */ +#define EMAC_IER_TXERR (0x1u << 6) /**< \brief (EMAC_IER) */ +#define EMAC_IER_TCOMP (0x1u << 7) /**< \brief (EMAC_IER) Transmit Complete */ +#define EMAC_IER_ROVR (0x1u << 10) /**< \brief (EMAC_IER) Receive Overrun */ +#define EMAC_IER_HRESP (0x1u << 11) /**< \brief (EMAC_IER) Hresp not OK */ +#define EMAC_IER_PFR (0x1u << 12) /**< \brief (EMAC_IER) Pause Frame Received */ +#define EMAC_IER_PTZ (0x1u << 13) /**< \brief (EMAC_IER) Pause Time Zero */ +/* -------- EMAC_IDR : (EMAC Offset: 0x2C) Interrupt Disable Register -------- */ +#define EMAC_IDR_MFD (0x1u << 0) /**< \brief (EMAC_IDR) Management Frame sent */ +#define EMAC_IDR_RCOMP (0x1u << 1) /**< \brief (EMAC_IDR) Receive Complete */ +#define EMAC_IDR_RXUBR (0x1u << 2) /**< \brief (EMAC_IDR) Receive Used Bit Read */ +#define EMAC_IDR_TXUBR (0x1u << 3) /**< \brief (EMAC_IDR) Transmit Used Bit Read */ +#define EMAC_IDR_TUND (0x1u << 4) /**< \brief (EMAC_IDR) Ethernet Transmit Buffer Underrun */ +#define EMAC_IDR_RLE (0x1u << 5) /**< \brief (EMAC_IDR) Retry Limit Exceeded */ +#define EMAC_IDR_TXERR (0x1u << 6) /**< \brief (EMAC_IDR) */ +#define EMAC_IDR_TCOMP (0x1u << 7) /**< \brief (EMAC_IDR) Transmit Complete */ +#define EMAC_IDR_ROVR (0x1u << 10) /**< \brief (EMAC_IDR) Receive Overrun */ +#define EMAC_IDR_HRESP (0x1u << 11) /**< \brief (EMAC_IDR) Hresp not OK */ +#define EMAC_IDR_PFR (0x1u << 12) /**< \brief (EMAC_IDR) Pause Frame Received */ +#define EMAC_IDR_PTZ (0x1u << 13) /**< \brief (EMAC_IDR) Pause Time Zero */ +/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */ +#define EMAC_IMR_MFD (0x1u << 0) /**< \brief (EMAC_IMR) Management Frame sent */ +#define EMAC_IMR_RCOMP (0x1u << 1) /**< \brief (EMAC_IMR) Receive Complete */ +#define EMAC_IMR_RXUBR (0x1u << 2) /**< \brief (EMAC_IMR) Receive Used Bit Read */ +#define EMAC_IMR_TXUBR (0x1u << 3) /**< \brief (EMAC_IMR) Transmit Used Bit Read */ +#define EMAC_IMR_TUND (0x1u << 4) /**< \brief (EMAC_IMR) Ethernet Transmit Buffer Underrun */ +#define EMAC_IMR_RLE (0x1u << 5) /**< \brief (EMAC_IMR) Retry Limit Exceeded */ +#define EMAC_IMR_TXERR (0x1u << 6) /**< \brief (EMAC_IMR) */ +#define EMAC_IMR_TCOMP (0x1u << 7) /**< \brief (EMAC_IMR) Transmit Complete */ +#define EMAC_IMR_ROVR (0x1u << 10) /**< \brief (EMAC_IMR) Receive Overrun */ +#define EMAC_IMR_HRESP (0x1u << 11) /**< \brief (EMAC_IMR) Hresp not OK */ +#define EMAC_IMR_PFR (0x1u << 12) /**< \brief (EMAC_IMR) Pause Frame Received */ +#define EMAC_IMR_PTZ (0x1u << 13) /**< \brief (EMAC_IMR) Pause Time Zero */ +/* -------- EMAC_MAN : (EMAC Offset: 0x34) Phy Maintenance Register -------- */ +#define EMAC_MAN_DATA_Pos 0 +#define EMAC_MAN_DATA_Msk (0xffffu << EMAC_MAN_DATA_Pos) /**< \brief (EMAC_MAN) */ +#define EMAC_MAN_DATA(value) ((EMAC_MAN_DATA_Msk & ((value) << EMAC_MAN_DATA_Pos))) +#define EMAC_MAN_CODE_Pos 16 +#define EMAC_MAN_CODE_Msk (0x3u << EMAC_MAN_CODE_Pos) /**< \brief (EMAC_MAN) */ +#define EMAC_MAN_CODE(value) ((EMAC_MAN_CODE_Msk & ((value) << EMAC_MAN_CODE_Pos))) +#define EMAC_MAN_REGA_Pos 18 +#define EMAC_MAN_REGA_Msk (0x1fu << EMAC_MAN_REGA_Pos) /**< \brief (EMAC_MAN) Register Address */ +#define EMAC_MAN_REGA(value) ((EMAC_MAN_REGA_Msk & ((value) << EMAC_MAN_REGA_Pos))) +#define EMAC_MAN_PHYA_Pos 23 +#define EMAC_MAN_PHYA_Msk (0x1fu << EMAC_MAN_PHYA_Pos) /**< \brief (EMAC_MAN) PHY Address */ +#define EMAC_MAN_PHYA(value) ((EMAC_MAN_PHYA_Msk & ((value) << EMAC_MAN_PHYA_Pos))) +#define EMAC_MAN_RW_Pos 28 +#define EMAC_MAN_RW_Msk (0x3u << EMAC_MAN_RW_Pos) /**< \brief (EMAC_MAN) Read-write */ +#define EMAC_MAN_RW(value) ((EMAC_MAN_RW_Msk & ((value) << EMAC_MAN_RW_Pos))) +#define EMAC_MAN_SOF_Pos 30 +#define EMAC_MAN_SOF_Msk (0x3u << EMAC_MAN_SOF_Pos) /**< \brief (EMAC_MAN) Start of frame */ +#define EMAC_MAN_SOF(value) ((EMAC_MAN_SOF_Msk & ((value) << EMAC_MAN_SOF_Pos))) +/* -------- EMAC_PTR : (EMAC Offset: 0x38) Pause Time Register -------- */ +#define EMAC_PTR_PTIME_Pos 0 +#define EMAC_PTR_PTIME_Msk (0xffffu << EMAC_PTR_PTIME_Pos) /**< \brief (EMAC_PTR) Pause Time */ +#define EMAC_PTR_PTIME(value) ((EMAC_PTR_PTIME_Msk & ((value) << EMAC_PTR_PTIME_Pos))) +/* -------- EMAC_PFR : (EMAC Offset: 0x3C) Pause Frames Received Register -------- */ +#define EMAC_PFR_FROK_Pos 0 +#define EMAC_PFR_FROK_Msk (0xffffu << EMAC_PFR_FROK_Pos) /**< \brief (EMAC_PFR) Pause Frames received OK */ +#define EMAC_PFR_FROK(value) ((EMAC_PFR_FROK_Msk & ((value) << EMAC_PFR_FROK_Pos))) +/* -------- EMAC_FTO : (EMAC Offset: 0x40) Frames Transmitted Ok Register -------- */ +#define EMAC_FTO_FTOK_Pos 0 +#define EMAC_FTO_FTOK_Msk (0xffffffu << EMAC_FTO_FTOK_Pos) /**< \brief (EMAC_FTO) Frames Transmitted OK */ +#define EMAC_FTO_FTOK(value) ((EMAC_FTO_FTOK_Msk & ((value) << EMAC_FTO_FTOK_Pos))) +/* -------- EMAC_SCF : (EMAC Offset: 0x44) Single Collision Frames Register -------- */ +#define EMAC_SCF_SCF_Pos 0 +#define EMAC_SCF_SCF_Msk (0xffffu << EMAC_SCF_SCF_Pos) /**< \brief (EMAC_SCF) Single Collision Frames */ +#define EMAC_SCF_SCF(value) ((EMAC_SCF_SCF_Msk & ((value) << EMAC_SCF_SCF_Pos))) +/* -------- EMAC_MCF : (EMAC Offset: 0x48) Multiple Collision Frames Register -------- */ +#define EMAC_MCF_MCF_Pos 0 +#define EMAC_MCF_MCF_Msk (0xffffu << EMAC_MCF_MCF_Pos) /**< \brief (EMAC_MCF) Multicollision Frames */ +#define EMAC_MCF_MCF(value) ((EMAC_MCF_MCF_Msk & ((value) << EMAC_MCF_MCF_Pos))) +/* -------- EMAC_FRO : (EMAC Offset: 0x4C) Frames Received Ok Register -------- */ +#define EMAC_FRO_FROK_Pos 0 +#define EMAC_FRO_FROK_Msk (0xffffffu << EMAC_FRO_FROK_Pos) /**< \brief (EMAC_FRO) Frames Received OK */ +#define EMAC_FRO_FROK(value) ((EMAC_FRO_FROK_Msk & ((value) << EMAC_FRO_FROK_Pos))) +/* -------- EMAC_FCSE : (EMAC Offset: 0x50) Frame Check Sequence Errors Register -------- */ +#define EMAC_FCSE_FCSE_Pos 0 +#define EMAC_FCSE_FCSE_Msk (0xffu << EMAC_FCSE_FCSE_Pos) /**< \brief (EMAC_FCSE) Frame Check Sequence Errors */ +#define EMAC_FCSE_FCSE(value) ((EMAC_FCSE_FCSE_Msk & ((value) << EMAC_FCSE_FCSE_Pos))) +/* -------- EMAC_ALE : (EMAC Offset: 0x54) Alignment Errors Register -------- */ +#define EMAC_ALE_ALE_Pos 0 +#define EMAC_ALE_ALE_Msk (0xffu << EMAC_ALE_ALE_Pos) /**< \brief (EMAC_ALE) Alignment Errors */ +#define EMAC_ALE_ALE(value) ((EMAC_ALE_ALE_Msk & ((value) << EMAC_ALE_ALE_Pos))) +/* -------- EMAC_DTF : (EMAC Offset: 0x58) Deferred Transmission Frames Register -------- */ +#define EMAC_DTF_DTF_Pos 0 +#define EMAC_DTF_DTF_Msk (0xffffu << EMAC_DTF_DTF_Pos) /**< \brief (EMAC_DTF) Deferred Transmission Frames */ +#define EMAC_DTF_DTF(value) ((EMAC_DTF_DTF_Msk & ((value) << EMAC_DTF_DTF_Pos))) +/* -------- EMAC_LCOL : (EMAC Offset: 0x5C) Late Collisions Register -------- */ +#define EMAC_LCOL_LCOL_Pos 0 +#define EMAC_LCOL_LCOL_Msk (0xffu << EMAC_LCOL_LCOL_Pos) /**< \brief (EMAC_LCOL) Late Collisions */ +#define EMAC_LCOL_LCOL(value) ((EMAC_LCOL_LCOL_Msk & ((value) << EMAC_LCOL_LCOL_Pos))) +/* -------- EMAC_ECOL : (EMAC Offset: 0x60) Excessive Collisions Register -------- */ +#define EMAC_ECOL_EXCOL_Pos 0 +#define EMAC_ECOL_EXCOL_Msk (0xffu << EMAC_ECOL_EXCOL_Pos) /**< \brief (EMAC_ECOL) Excessive Collisions */ +#define EMAC_ECOL_EXCOL(value) ((EMAC_ECOL_EXCOL_Msk & ((value) << EMAC_ECOL_EXCOL_Pos))) +/* -------- EMAC_TUND : (EMAC Offset: 0x64) Transmit Underrun Errors Register -------- */ +#define EMAC_TUND_TUND_Pos 0 +#define EMAC_TUND_TUND_Msk (0xffu << EMAC_TUND_TUND_Pos) /**< \brief (EMAC_TUND) Transmit Underruns */ +#define EMAC_TUND_TUND(value) ((EMAC_TUND_TUND_Msk & ((value) << EMAC_TUND_TUND_Pos))) +/* -------- EMAC_CSE : (EMAC Offset: 0x68) Carrier Sense Errors Register -------- */ +#define EMAC_CSE_CSE_Pos 0 +#define EMAC_CSE_CSE_Msk (0xffu << EMAC_CSE_CSE_Pos) /**< \brief (EMAC_CSE) Carrier Sense Errors */ +#define EMAC_CSE_CSE(value) ((EMAC_CSE_CSE_Msk & ((value) << EMAC_CSE_CSE_Pos))) +/* -------- EMAC_RRE : (EMAC Offset: 0x6C) Receive Resource Errors Register -------- */ +#define EMAC_RRE_RRE_Pos 0 +#define EMAC_RRE_RRE_Msk (0xffffu << EMAC_RRE_RRE_Pos) /**< \brief (EMAC_RRE) Receive Resource Errors */ +#define EMAC_RRE_RRE(value) ((EMAC_RRE_RRE_Msk & ((value) << EMAC_RRE_RRE_Pos))) +/* -------- EMAC_ROV : (EMAC Offset: 0x70) Receive Overrun Errors Register -------- */ +#define EMAC_ROV_ROVR_Pos 0 +#define EMAC_ROV_ROVR_Msk (0xffu << EMAC_ROV_ROVR_Pos) /**< \brief (EMAC_ROV) Receive Overrun */ +#define EMAC_ROV_ROVR(value) ((EMAC_ROV_ROVR_Msk & ((value) << EMAC_ROV_ROVR_Pos))) +/* -------- EMAC_RSE : (EMAC Offset: 0x74) Receive Symbol Errors Register -------- */ +#define EMAC_RSE_RSE_Pos 0 +#define EMAC_RSE_RSE_Msk (0xffu << EMAC_RSE_RSE_Pos) /**< \brief (EMAC_RSE) Receive Symbol Errors */ +#define EMAC_RSE_RSE(value) ((EMAC_RSE_RSE_Msk & ((value) << EMAC_RSE_RSE_Pos))) +/* -------- EMAC_ELE : (EMAC Offset: 0x78) Excessive Length Errors Register -------- */ +#define EMAC_ELE_EXL_Pos 0 +#define EMAC_ELE_EXL_Msk (0xffu << EMAC_ELE_EXL_Pos) /**< \brief (EMAC_ELE) Excessive Length Errors */ +#define EMAC_ELE_EXL(value) ((EMAC_ELE_EXL_Msk & ((value) << EMAC_ELE_EXL_Pos))) +/* -------- EMAC_RJA : (EMAC Offset: 0x7C) Receive Jabbers Register -------- */ +#define EMAC_RJA_RJB_Pos 0 +#define EMAC_RJA_RJB_Msk (0xffu << EMAC_RJA_RJB_Pos) /**< \brief (EMAC_RJA) Receive Jabbers */ +#define EMAC_RJA_RJB(value) ((EMAC_RJA_RJB_Msk & ((value) << EMAC_RJA_RJB_Pos))) +/* -------- EMAC_USF : (EMAC Offset: 0x80) Undersize Frames Register -------- */ +#define EMAC_USF_USF_Pos 0 +#define EMAC_USF_USF_Msk (0xffu << EMAC_USF_USF_Pos) /**< \brief (EMAC_USF) Undersize frames */ +#define EMAC_USF_USF(value) ((EMAC_USF_USF_Msk & ((value) << EMAC_USF_USF_Pos))) +/* -------- EMAC_STE : (EMAC Offset: 0x84) SQE Test Errors Register -------- */ +#define EMAC_STE_SQER_Pos 0 +#define EMAC_STE_SQER_Msk (0xffu << EMAC_STE_SQER_Pos) /**< \brief (EMAC_STE) SQE test errors */ +#define EMAC_STE_SQER(value) ((EMAC_STE_SQER_Msk & ((value) << EMAC_STE_SQER_Pos))) +/* -------- EMAC_RLE : (EMAC Offset: 0x88) Received Length Field Mismatch Register -------- */ +#define EMAC_RLE_RLFM_Pos 0 +#define EMAC_RLE_RLFM_Msk (0xffu << EMAC_RLE_RLFM_Pos) /**< \brief (EMAC_RLE) Receive Length Field Mismatch */ +#define EMAC_RLE_RLFM(value) ((EMAC_RLE_RLFM_Msk & ((value) << EMAC_RLE_RLFM_Pos))) +/* -------- EMAC_HRB : (EMAC Offset: 0x90) Hash Register Bottom [31:0] Register -------- */ +#define EMAC_HRB_ADDR_Pos 0 +#define EMAC_HRB_ADDR_Msk (0xffffffffu << EMAC_HRB_ADDR_Pos) /**< \brief (EMAC_HRB) */ +#define EMAC_HRB_ADDR(value) ((EMAC_HRB_ADDR_Msk & ((value) << EMAC_HRB_ADDR_Pos))) +/* -------- EMAC_HRT : (EMAC Offset: 0x94) Hash Register Top [63:32] Register -------- */ +#define EMAC_HRT_ADDR_Pos 0 +#define EMAC_HRT_ADDR_Msk (0xffffffffu << EMAC_HRT_ADDR_Pos) /**< \brief (EMAC_HRT) */ +#define EMAC_HRT_ADDR(value) ((EMAC_HRT_ADDR_Msk & ((value) << EMAC_HRT_ADDR_Pos))) +/* -------- EMAC_SAxB : (EMAC Offset: N/A) Specific Address 1 Bottom Register -------- */ +#define EMAC_SAxB_ADDR_Pos 0 +#define EMAC_SAxB_ADDR_Msk (0xffffffffu << EMAC_SAxB_ADDR_Pos) /**< \brief (EMAC_SAxB) */ +#define EMAC_SAxB_ADDR(value) ((EMAC_SAxB_ADDR_Msk & ((value) << EMAC_SAxB_ADDR_Pos))) +/* -------- EMAC_SAxT : (EMAC Offset: N/A) Specific Address 1 Top Register -------- */ +#define EMAC_SAxT_ADDR_Pos 0 +#define EMAC_SAxT_ADDR_Msk (0xffffu << EMAC_SAxT_ADDR_Pos) /**< \brief (EMAC_SAxT) */ +#define EMAC_SAxT_ADDR(value) ((EMAC_SAxT_ADDR_Msk & ((value) << EMAC_SAxT_ADDR_Pos))) +/* -------- EMAC_TID : (EMAC Offset: 0xB8) Type ID Checking Register -------- */ +#define EMAC_TID_TID_Pos 0 +#define EMAC_TID_TID_Msk (0xffffu << EMAC_TID_TID_Pos) /**< \brief (EMAC_TID) Type ID checking */ +#define EMAC_TID_TID(value) ((EMAC_TID_TID_Msk & ((value) << EMAC_TID_TID_Pos))) +/* -------- EMAC_USRIO : (EMAC Offset: 0xC0) User Input/Output Register -------- */ +#define EMAC_USRIO_RMII (0x1u << 0) /**< \brief (EMAC_USRIO) Reduce MII */ +#define EMAC_USRIO_CLKEN (0x1u << 1) /**< \brief (EMAC_USRIO) Clock Enable */ + +/*@}*/ + + +#endif /* _SAM3XA_EMAC_COMPONENT_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h new file mode 100644 index 0000000..ca32d92 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_gpbr.h @@ -0,0 +1,68 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_GPBR_COMPONENT_ +#define _SAM3XA_GPBR_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR General Purpose Backup Register */ +/* ============================================================================= */ +/** \addtogroup SAM3XA_GPBR General Purpose Backup Register */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Gpbr hardware registers */ +typedef struct { + RwReg SYS_GPBR[8]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */ +} Gpbr; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SYS_GPBR[8] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */ +#define SYS_GPBR_GPBR_VALUE_Pos 0 +#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[8]) Value of GPBR x */ +#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos))) + +/*@}*/ + + +#endif /* _SAM3XA_GPBR_COMPONENT_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h new file mode 100644 index 0000000..449a588 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_hsmci.h @@ -0,0 +1,356 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_HSMCI_COMPONENT_ +#define _SAM3XA_HSMCI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */ +/* ============================================================================= */ +/** \addtogroup SAM3XA_HSMCI High Speed MultiMedia Card Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Hsmci hardware registers */ +typedef struct { + WoReg HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */ + RwReg HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */ + RwReg HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */ + RwReg HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */ + RwReg HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */ + WoReg HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */ + RwReg HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */ + RwReg HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */ + RoReg HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */ + RoReg HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */ + WoReg HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */ + RoReg Reserved1[2]; + RoReg HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */ + WoReg HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */ + WoReg HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */ + RoReg HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */ + RwReg HSMCI_DMA; /**< \brief (Hsmci Offset: 0x50) DMA Configuration Register */ + RwReg HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */ + RoReg Reserved2[35]; + RwReg HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */ + RoReg HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */ + RoReg Reserved3[69]; + RwReg HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */ +} Hsmci; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */ +#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */ +#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */ +#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */ +#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */ +#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */ +/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */ +#define HSMCI_MR_CLKDIV_Pos 0 +#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */ +#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos))) +#define HSMCI_MR_PWSDIV_Pos 8 +#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */ +#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos))) +#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR) */ +#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR) */ +#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */ +#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */ +/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */ +#define HSMCI_DTOR_DTOCYC_Pos 0 +#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */ +#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos))) +#define HSMCI_DTOR_DTOMUL_Pos 4 +#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */ +#define HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */ +#define HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */ +#define HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */ +#define HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */ +#define HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */ +#define HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */ +#define HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */ +#define HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */ +/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */ +#define HSMCI_SDCR_SDCSEL_Pos 0 +#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */ +#define HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */ +#define HSMCI_SDCR_SDCSEL_SLOTB (0x1u << 0) /**< \brief (HSMCI_SDCR) SDCARD/SDIO Slot B selected */ +#define HSMCI_SDCR_SDCSEL_SLOTC (0x2u << 0) /**< \brief (HSMCI_SDCR) - */ +#define HSMCI_SDCR_SDCSEL_SLOTD (0x3u << 0) /**< \brief (HSMCI_SDCR) - */ +#define HSMCI_SDCR_SDCBUS_Pos 6 +#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */ +#define HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */ +#define HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bit */ +#define HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bit */ +/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */ +#define HSMCI_ARGR_ARG_Pos 0 +#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */ +#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos))) +/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */ +#define HSMCI_CMDR_CMDNB_Pos 0 +#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */ +#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos))) +#define HSMCI_CMDR_RSPTYP_Pos 6 +#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */ +#define HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response. */ +#define HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response. */ +#define HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response. */ +#define HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */ +#define HSMCI_CMDR_SPCMD_Pos 8 +#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */ +#define HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */ +#define HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */ +#define HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */ +#define HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */ +#define HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */ +#define HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */ +#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */ +#define HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */ +#define HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */ +#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */ +#define HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */ +#define HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */ +#define HSMCI_CMDR_TRCMD_Pos 16 +#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */ +#define HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */ +#define HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */ +#define HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */ +#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */ +#define HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */ +#define HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */ +#define HSMCI_CMDR_TRTYP_Pos 19 +#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */ +#define HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Single Block */ +#define HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Multiple Block */ +#define HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */ +#define HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */ +#define HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */ +#define HSMCI_CMDR_IOSPCMD_Pos 24 +#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */ +#define HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */ +#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */ +#define HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */ +#define HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */ +#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */ +/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */ +#define HSMCI_BLKR_BCNT_Pos 0 +#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */ +#define HSMCI_BLKR_BCNT_MULTIPLE (0x0u << 0) /**< \brief (HSMCI_BLKR) MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer. */ +#define HSMCI_BLKR_BCNT_BYTE (0x4u << 0) /**< \brief (HSMCI_BLKR) SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden. */ +#define HSMCI_BLKR_BCNT_BLOCK (0x5u << 0) /**< \brief (HSMCI_BLKR) SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden. */ +#define HSMCI_BLKR_BLKLEN_Pos 16 +#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */ +#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos))) +/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */ +#define HSMCI_CSTOR_CSTOCYC_Pos 0 +#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */ +#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos))) +#define HSMCI_CSTOR_CSTOMUL_Pos 4 +#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */ +#define HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */ +#define HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */ +#define HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */ +#define HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */ +#define HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */ +#define HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */ +#define HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */ +#define HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */ +/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */ +#define HSMCI_RSPR_RSP_Pos 0 +#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */ +/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */ +#define HSMCI_RDR_DATA_Pos 0 +#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */ +/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */ +#define HSMCI_TDR_DATA_Pos 0 +#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */ +#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos))) +/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */ +#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready */ +#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready */ +#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready */ +#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended */ +#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */ +#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */ +#define HSMCI_SR_SDIOIRQforSlotA (0x1u << 8) /**< \brief (HSMCI_SR) */ +#define HSMCI_SR_SDIOIRQforSlotB (0x1u << 9) /**< \brief (HSMCI_SR) */ +#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */ +#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */ +#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error */ +#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error */ +#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error */ +#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error */ +#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error */ +#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error */ +#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error */ +#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */ +#define HSMCI_SR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_SR) DMA Block Overrun Error */ +#define HSMCI_SR_DMADONE (0x1u << 25) /**< \brief (HSMCI_SR) DMA Transfer done */ +#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */ +#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */ +#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */ +#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */ +#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun */ +#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun */ +/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */ +#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */ +#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */ +#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */ +#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */ +#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */ +#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */ +#define HSMCI_IER_SDIOIRQforSlotA (0x1u << 8) /**< \brief (HSMCI_IER) */ +#define HSMCI_IER_SDIOIRQforSlotB (0x1u << 9) /**< \brief (HSMCI_IER) */ +#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */ +#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */ +#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */ +#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */ +#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */ +#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */ +#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */ +#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */ +#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */ +#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */ +#define HSMCI_IER_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IER) DMA Block Overrun Error Interrupt Enable */ +#define HSMCI_IER_DMADONE (0x1u << 25) /**< \brief (HSMCI_IER) DMA Transfer completed Interrupt Enable */ +#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */ +#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */ +#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */ +#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */ +#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */ +#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */ +/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */ +#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */ +#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */ +#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */ +#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */ +#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */ +#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */ +#define HSMCI_IDR_SDIOIRQforSlotA (0x1u << 8) /**< \brief (HSMCI_IDR) */ +#define HSMCI_IDR_SDIOIRQforSlotB (0x1u << 9) /**< \brief (HSMCI_IDR) */ +#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */ +#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */ +#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */ +#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */ +#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */ +#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */ +#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */ +#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */ +#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */ +#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */ +#define HSMCI_IDR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable */ +#define HSMCI_IDR_DMADONE (0x1u << 25) /**< \brief (HSMCI_IDR) DMA Transfer completed Interrupt Disable */ +#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */ +#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */ +#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */ +#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */ +#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */ +#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */ +/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */ +#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */ +#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */ +#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */ +#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */ +#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */ +#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */ +#define HSMCI_IMR_SDIOIRQforSlotA (0x1u << 8) /**< \brief (HSMCI_IMR) */ +#define HSMCI_IMR_SDIOIRQforSlotB (0x1u << 9) /**< \brief (HSMCI_IMR) */ +#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */ +#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */ +#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */ +#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */ +#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */ +#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */ +#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */ +#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */ +#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */ +#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */ +#define HSMCI_IMR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask */ +#define HSMCI_IMR_DMADONE (0x1u << 25) /**< \brief (HSMCI_IMR) DMA Transfer Completed Interrupt Mask */ +#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */ +#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */ +#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */ +#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */ +#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */ +#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */ +/* -------- HSMCI_DMA : (HSMCI Offset: 0x50) DMA Configuration Register -------- */ +#define HSMCI_DMA_OFFSET_Pos 0 +#define HSMCI_DMA_OFFSET_Msk (0x3u << HSMCI_DMA_OFFSET_Pos) /**< \brief (HSMCI_DMA) DMA Write Buffer Offset */ +#define HSMCI_DMA_OFFSET(value) ((HSMCI_DMA_OFFSET_Msk & ((value) << HSMCI_DMA_OFFSET_Pos))) +#define HSMCI_DMA_CHKSIZE (0x1u << 4) /**< \brief (HSMCI_DMA) DMA Channel Read and Write Chunk Size */ +#define HSMCI_DMA_CHKSIZE_1 (0x0u << 4) /**< \brief (HSMCI_DMA) 1 data available */ +#define HSMCI_DMA_CHKSIZE_4 (0x1u << 4) /**< \brief (HSMCI_DMA) 4 data available */ +#define HSMCI_DMA_DMAEN (0x1u << 8) /**< \brief (HSMCI_DMA) DMA Hardware Handshaking Enable */ +#define HSMCI_DMA_ROPT (0x1u << 12) /**< \brief (HSMCI_DMA) Read Optimization with padding */ +/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */ +#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */ +#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */ +#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */ +#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */ +/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */ +#define HSMCI_WPMR_WP_EN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */ +#define HSMCI_WPMR_WP_KEY_Pos 8 +#define HSMCI_WPMR_WP_KEY_Msk (0xffffffu << HSMCI_WPMR_WP_KEY_Pos) /**< \brief (HSMCI_WPMR) Write Protection Key password */ +#define HSMCI_WPMR_WP_KEY(value) ((HSMCI_WPMR_WP_KEY_Msk & ((value) << HSMCI_WPMR_WP_KEY_Pos))) +/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */ +#define HSMCI_WPSR_WP_VS_Pos 0 +#define HSMCI_WPSR_WP_VS_Msk (0xfu << HSMCI_WPSR_WP_VS_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */ +#define HSMCI_WPSR_WP_VS_NONE (0x0u << 0) /**< \brief (HSMCI_WPSR) No Write Protection Violation occurred since the last read of this register (WP_SR) */ +#define HSMCI_WPSR_WP_VS_WRITE (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) */ +#define HSMCI_WPSR_WP_VS_RESET (0x2u << 0) /**< \brief (HSMCI_WPSR) Software reset had been performed while Write Protection was enabled (since the last read). */ +#define HSMCI_WPSR_WP_VS_BOTH (0x3u << 0) /**< \brief (HSMCI_WPSR) Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. */ +#define HSMCI_WPSR_WP_VSRC_Pos 8 +#define HSMCI_WPSR_WP_VSRC_Msk (0xffffu << HSMCI_WPSR_WP_VSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */ +/* -------- HSMCI_FIFO[256] : (HSMCI Offset: 0x200) FIFO Memory Aperture0 -------- */ +#define HSMCI_FIFO_DATA_Pos 0 +#define HSMCI_FIFO_DATA_Msk (0xffffffffu << HSMCI_FIFO_DATA_Pos) /**< \brief (HSMCI_FIFO[256]) Data to Read or Data to Write */ +#define HSMCI_FIFO_DATA(value) ((HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos))) + +/*@}*/ + + +#endif /* _SAM3XA_HSMCI_COMPONENT_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h new file mode 100644 index 0000000..8d3e31b --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_matrix.h @@ -0,0 +1,300 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_MATRIX_COMPONENT_ +#define _SAM3XA_MATRIX_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */ +/* ============================================================================= */ +/** \addtogroup SAM3XA_MATRIX AHB Bus Matrix */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Matrix hardware registers */ +typedef struct { + RwReg MATRIX_MCFG[6]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */ + RoReg Reserved1[10]; + RwReg MATRIX_SCFG[9]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */ + RoReg Reserved2[7]; + RwReg MATRIX_PRAS0; /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */ + RoReg Reserved3[1]; + RwReg MATRIX_PRAS1; /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */ + RoReg Reserved4[1]; + RwReg MATRIX_PRAS2; /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */ + RoReg Reserved5[1]; + RwReg MATRIX_PRAS3; /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */ + RoReg Reserved6[1]; + RwReg MATRIX_PRAS4; /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */ + RoReg Reserved7[1]; + RwReg MATRIX_PRAS5; /**< \brief (Matrix Offset: 0x00A8) Priority Register A for Slave 5 */ + RoReg Reserved8[1]; + RwReg MATRIX_PRAS6; /**< \brief (Matrix Offset: 0x00B0) Priority Register A for Slave 6 */ + RoReg Reserved9[1]; + RwReg MATRIX_PRAS7; /**< \brief (Matrix Offset: 0x00B8) Priority Register A for Slave 7 */ + RoReg Reserved10[1]; + RwReg MATRIX_PRAS8; /**< \brief (Matrix Offset: 0x00C0) Priority Register A for Slave 8 */ + RoReg Reserved11[1]; + RoReg Reserved12[14]; + RwReg MATRIX_MRCR; /**< \brief (Matrix Offset: 0x0100) Master Remap Control Register */ + RoReg Reserved13[4]; + RwReg CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System I/O Configuration register */ + RoReg Reserved14[51]; + RwReg MATRIX_WPMR; /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */ + RoReg MATRIX_WPSR; /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */ +} Matrix; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- MATRIX_MCFG[6] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */ +#define MATRIX_MCFG_ULBT_Pos 0 +#define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[6]) Undefined Length Burst Type */ +#define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos))) +/* -------- MATRIX_SCFG[9] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */ +#define MATRIX_SCFG_SLOT_CYCLE_Pos 0 +#define MATRIX_SCFG_SLOT_CYCLE_Msk (0xffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[9]) Maximum Number of Allowed Cycles for a Burst */ +#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos))) +#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16 +#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[9]) Default Master Type */ +#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos))) +#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18 +#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0x7u << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[9]) Fixed Default Master */ +#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos))) +#define MATRIX_SCFG_ARBT_Pos 24 +#define MATRIX_SCFG_ARBT_Msk (0x3u << MATRIX_SCFG_ARBT_Pos) /**< \brief (MATRIX_SCFG[9]) Arbitration Type */ +#define MATRIX_SCFG_ARBT(value) ((MATRIX_SCFG_ARBT_Msk & ((value) << MATRIX_SCFG_ARBT_Pos))) +/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */ +#define MATRIX_PRAS0_M0PR_Pos 0 +#define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) /**< \brief (MATRIX_PRAS0) Master 0 Priority */ +#define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos))) +#define MATRIX_PRAS0_M1PR_Pos 4 +#define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) /**< \brief (MATRIX_PRAS0) Master 1 Priority */ +#define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos))) +#define MATRIX_PRAS0_M2PR_Pos 8 +#define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) /**< \brief (MATRIX_PRAS0) Master 2 Priority */ +#define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos))) +#define MATRIX_PRAS0_M3PR_Pos 12 +#define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) /**< \brief (MATRIX_PRAS0) Master 3 Priority */ +#define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos))) +#define MATRIX_PRAS0_M4PR_Pos 16 +#define MATRIX_PRAS0_M4PR_Msk (0x3u << MATRIX_PRAS0_M4PR_Pos) /**< \brief (MATRIX_PRAS0) Master 4 Priority */ +#define MATRIX_PRAS0_M4PR(value) ((MATRIX_PRAS0_M4PR_Msk & ((value) << MATRIX_PRAS0_M4PR_Pos))) +#define MATRIX_PRAS0_M5PR_Pos 20 +#define MATRIX_PRAS0_M5PR_Msk (0x3u << MATRIX_PRAS0_M5PR_Pos) /**< \brief (MATRIX_PRAS0) Master 5 Priority */ +#define MATRIX_PRAS0_M5PR(value) ((MATRIX_PRAS0_M5PR_Msk & ((value) << MATRIX_PRAS0_M5PR_Pos))) +/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */ +#define MATRIX_PRAS1_M0PR_Pos 0 +#define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) /**< \brief (MATRIX_PRAS1) Master 0 Priority */ +#define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos))) +#define MATRIX_PRAS1_M1PR_Pos 4 +#define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) /**< \brief (MATRIX_PRAS1) Master 1 Priority */ +#define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos))) +#define MATRIX_PRAS1_M2PR_Pos 8 +#define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) /**< \brief (MATRIX_PRAS1) Master 2 Priority */ +#define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos))) +#define MATRIX_PRAS1_M3PR_Pos 12 +#define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) /**< \brief (MATRIX_PRAS1) Master 3 Priority */ +#define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos))) +#define MATRIX_PRAS1_M4PR_Pos 16 +#define MATRIX_PRAS1_M4PR_Msk (0x3u << MATRIX_PRAS1_M4PR_Pos) /**< \brief (MATRIX_PRAS1) Master 4 Priority */ +#define MATRIX_PRAS1_M4PR(value) ((MATRIX_PRAS1_M4PR_Msk & ((value) << MATRIX_PRAS1_M4PR_Pos))) +#define MATRIX_PRAS1_M5PR_Pos 20 +#define MATRIX_PRAS1_M5PR_Msk (0x3u << MATRIX_PRAS1_M5PR_Pos) /**< \brief (MATRIX_PRAS1) Master 5 Priority */ +#define MATRIX_PRAS1_M5PR(value) ((MATRIX_PRAS1_M5PR_Msk & ((value) << MATRIX_PRAS1_M5PR_Pos))) +/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */ +#define MATRIX_PRAS2_M0PR_Pos 0 +#define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) /**< \brief (MATRIX_PRAS2) Master 0 Priority */ +#define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos))) +#define MATRIX_PRAS2_M1PR_Pos 4 +#define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) /**< \brief (MATRIX_PRAS2) Master 1 Priority */ +#define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos))) +#define MATRIX_PRAS2_M2PR_Pos 8 +#define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) /**< \brief (MATRIX_PRAS2) Master 2 Priority */ +#define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos))) +#define MATRIX_PRAS2_M3PR_Pos 12 +#define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) /**< \brief (MATRIX_PRAS2) Master 3 Priority */ +#define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos))) +#define MATRIX_PRAS2_M4PR_Pos 16 +#define MATRIX_PRAS2_M4PR_Msk (0x3u << MATRIX_PRAS2_M4PR_Pos) /**< \brief (MATRIX_PRAS2) Master 4 Priority */ +#define MATRIX_PRAS2_M4PR(value) ((MATRIX_PRAS2_M4PR_Msk & ((value) << MATRIX_PRAS2_M4PR_Pos))) +#define MATRIX_PRAS2_M5PR_Pos 20 +#define MATRIX_PRAS2_M5PR_Msk (0x3u << MATRIX_PRAS2_M5PR_Pos) /**< \brief (MATRIX_PRAS2) Master 5 Priority */ +#define MATRIX_PRAS2_M5PR(value) ((MATRIX_PRAS2_M5PR_Msk & ((value) << MATRIX_PRAS2_M5PR_Pos))) +/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */ +#define MATRIX_PRAS3_M0PR_Pos 0 +#define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) /**< \brief (MATRIX_PRAS3) Master 0 Priority */ +#define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos))) +#define MATRIX_PRAS3_M1PR_Pos 4 +#define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) /**< \brief (MATRIX_PRAS3) Master 1 Priority */ +#define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos))) +#define MATRIX_PRAS3_M2PR_Pos 8 +#define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) /**< \brief (MATRIX_PRAS3) Master 2 Priority */ +#define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos))) +#define MATRIX_PRAS3_M3PR_Pos 12 +#define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) /**< \brief (MATRIX_PRAS3) Master 3 Priority */ +#define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos))) +#define MATRIX_PRAS3_M4PR_Pos 16 +#define MATRIX_PRAS3_M4PR_Msk (0x3u << MATRIX_PRAS3_M4PR_Pos) /**< \brief (MATRIX_PRAS3) Master 4 Priority */ +#define MATRIX_PRAS3_M4PR(value) ((MATRIX_PRAS3_M4PR_Msk & ((value) << MATRIX_PRAS3_M4PR_Pos))) +#define MATRIX_PRAS3_M5PR_Pos 20 +#define MATRIX_PRAS3_M5PR_Msk (0x3u << MATRIX_PRAS3_M5PR_Pos) /**< \brief (MATRIX_PRAS3) Master 5 Priority */ +#define MATRIX_PRAS3_M5PR(value) ((MATRIX_PRAS3_M5PR_Msk & ((value) << MATRIX_PRAS3_M5PR_Pos))) +/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */ +#define MATRIX_PRAS4_M0PR_Pos 0 +#define MATRIX_PRAS4_M0PR_Msk (0x3u << MATRIX_PRAS4_M0PR_Pos) /**< \brief (MATRIX_PRAS4) Master 0 Priority */ +#define MATRIX_PRAS4_M0PR(value) ((MATRIX_PRAS4_M0PR_Msk & ((value) << MATRIX_PRAS4_M0PR_Pos))) +#define MATRIX_PRAS4_M1PR_Pos 4 +#define MATRIX_PRAS4_M1PR_Msk (0x3u << MATRIX_PRAS4_M1PR_Pos) /**< \brief (MATRIX_PRAS4) Master 1 Priority */ +#define MATRIX_PRAS4_M1PR(value) ((MATRIX_PRAS4_M1PR_Msk & ((value) << MATRIX_PRAS4_M1PR_Pos))) +#define MATRIX_PRAS4_M2PR_Pos 8 +#define MATRIX_PRAS4_M2PR_Msk (0x3u << MATRIX_PRAS4_M2PR_Pos) /**< \brief (MATRIX_PRAS4) Master 2 Priority */ +#define MATRIX_PRAS4_M2PR(value) ((MATRIX_PRAS4_M2PR_Msk & ((value) << MATRIX_PRAS4_M2PR_Pos))) +#define MATRIX_PRAS4_M3PR_Pos 12 +#define MATRIX_PRAS4_M3PR_Msk (0x3u << MATRIX_PRAS4_M3PR_Pos) /**< \brief (MATRIX_PRAS4) Master 3 Priority */ +#define MATRIX_PRAS4_M3PR(value) ((MATRIX_PRAS4_M3PR_Msk & ((value) << MATRIX_PRAS4_M3PR_Pos))) +#define MATRIX_PRAS4_M4PR_Pos 16 +#define MATRIX_PRAS4_M4PR_Msk (0x3u << MATRIX_PRAS4_M4PR_Pos) /**< \brief (MATRIX_PRAS4) Master 4 Priority */ +#define MATRIX_PRAS4_M4PR(value) ((MATRIX_PRAS4_M4PR_Msk & ((value) << MATRIX_PRAS4_M4PR_Pos))) +#define MATRIX_PRAS4_M5PR_Pos 20 +#define MATRIX_PRAS4_M5PR_Msk (0x3u << MATRIX_PRAS4_M5PR_Pos) /**< \brief (MATRIX_PRAS4) Master 5 Priority */ +#define MATRIX_PRAS4_M5PR(value) ((MATRIX_PRAS4_M5PR_Msk & ((value) << MATRIX_PRAS4_M5PR_Pos))) +/* -------- MATRIX_PRAS5 : (MATRIX Offset: 0x00A8) Priority Register A for Slave 5 -------- */ +#define MATRIX_PRAS5_M0PR_Pos 0 +#define MATRIX_PRAS5_M0PR_Msk (0x3u << MATRIX_PRAS5_M0PR_Pos) /**< \brief (MATRIX_PRAS5) Master 0 Priority */ +#define MATRIX_PRAS5_M0PR(value) ((MATRIX_PRAS5_M0PR_Msk & ((value) << MATRIX_PRAS5_M0PR_Pos))) +#define MATRIX_PRAS5_M1PR_Pos 4 +#define MATRIX_PRAS5_M1PR_Msk (0x3u << MATRIX_PRAS5_M1PR_Pos) /**< \brief (MATRIX_PRAS5) Master 1 Priority */ +#define MATRIX_PRAS5_M1PR(value) ((MATRIX_PRAS5_M1PR_Msk & ((value) << MATRIX_PRAS5_M1PR_Pos))) +#define MATRIX_PRAS5_M2PR_Pos 8 +#define MATRIX_PRAS5_M2PR_Msk (0x3u << MATRIX_PRAS5_M2PR_Pos) /**< \brief (MATRIX_PRAS5) Master 2 Priority */ +#define MATRIX_PRAS5_M2PR(value) ((MATRIX_PRAS5_M2PR_Msk & ((value) << MATRIX_PRAS5_M2PR_Pos))) +#define MATRIX_PRAS5_M3PR_Pos 12 +#define MATRIX_PRAS5_M3PR_Msk (0x3u << MATRIX_PRAS5_M3PR_Pos) /**< \brief (MATRIX_PRAS5) Master 3 Priority */ +#define MATRIX_PRAS5_M3PR(value) ((MATRIX_PRAS5_M3PR_Msk & ((value) << MATRIX_PRAS5_M3PR_Pos))) +#define MATRIX_PRAS5_M4PR_Pos 16 +#define MATRIX_PRAS5_M4PR_Msk (0x3u << MATRIX_PRAS5_M4PR_Pos) /**< \brief (MATRIX_PRAS5) Master 4 Priority */ +#define MATRIX_PRAS5_M4PR(value) ((MATRIX_PRAS5_M4PR_Msk & ((value) << MATRIX_PRAS5_M4PR_Pos))) +#define MATRIX_PRAS5_M5PR_Pos 20 +#define MATRIX_PRAS5_M5PR_Msk (0x3u << MATRIX_PRAS5_M5PR_Pos) /**< \brief (MATRIX_PRAS5) Master 5 Priority */ +#define MATRIX_PRAS5_M5PR(value) ((MATRIX_PRAS5_M5PR_Msk & ((value) << MATRIX_PRAS5_M5PR_Pos))) +/* -------- MATRIX_PRAS6 : (MATRIX Offset: 0x00B0) Priority Register A for Slave 6 -------- */ +#define MATRIX_PRAS6_M0PR_Pos 0 +#define MATRIX_PRAS6_M0PR_Msk (0x3u << MATRIX_PRAS6_M0PR_Pos) /**< \brief (MATRIX_PRAS6) Master 0 Priority */ +#define MATRIX_PRAS6_M0PR(value) ((MATRIX_PRAS6_M0PR_Msk & ((value) << MATRIX_PRAS6_M0PR_Pos))) +#define MATRIX_PRAS6_M1PR_Pos 4 +#define MATRIX_PRAS6_M1PR_Msk (0x3u << MATRIX_PRAS6_M1PR_Pos) /**< \brief (MATRIX_PRAS6) Master 1 Priority */ +#define MATRIX_PRAS6_M1PR(value) ((MATRIX_PRAS6_M1PR_Msk & ((value) << MATRIX_PRAS6_M1PR_Pos))) +#define MATRIX_PRAS6_M2PR_Pos 8 +#define MATRIX_PRAS6_M2PR_Msk (0x3u << MATRIX_PRAS6_M2PR_Pos) /**< \brief (MATRIX_PRAS6) Master 2 Priority */ +#define MATRIX_PRAS6_M2PR(value) ((MATRIX_PRAS6_M2PR_Msk & ((value) << MATRIX_PRAS6_M2PR_Pos))) +#define MATRIX_PRAS6_M3PR_Pos 12 +#define MATRIX_PRAS6_M3PR_Msk (0x3u << MATRIX_PRAS6_M3PR_Pos) /**< \brief (MATRIX_PRAS6) Master 3 Priority */ +#define MATRIX_PRAS6_M3PR(value) ((MATRIX_PRAS6_M3PR_Msk & ((value) << MATRIX_PRAS6_M3PR_Pos))) +#define MATRIX_PRAS6_M4PR_Pos 16 +#define MATRIX_PRAS6_M4PR_Msk (0x3u << MATRIX_PRAS6_M4PR_Pos) /**< \brief (MATRIX_PRAS6) Master 4 Priority */ +#define MATRIX_PRAS6_M4PR(value) ((MATRIX_PRAS6_M4PR_Msk & ((value) << MATRIX_PRAS6_M4PR_Pos))) +#define MATRIX_PRAS6_M5PR_Pos 20 +#define MATRIX_PRAS6_M5PR_Msk (0x3u << MATRIX_PRAS6_M5PR_Pos) /**< \brief (MATRIX_PRAS6) Master 5 Priority */ +#define MATRIX_PRAS6_M5PR(value) ((MATRIX_PRAS6_M5PR_Msk & ((value) << MATRIX_PRAS6_M5PR_Pos))) +/* -------- MATRIX_PRAS7 : (MATRIX Offset: 0x00B8) Priority Register A for Slave 7 -------- */ +#define MATRIX_PRAS7_M0PR_Pos 0 +#define MATRIX_PRAS7_M0PR_Msk (0x3u << MATRIX_PRAS7_M0PR_Pos) /**< \brief (MATRIX_PRAS7) Master 0 Priority */ +#define MATRIX_PRAS7_M0PR(value) ((MATRIX_PRAS7_M0PR_Msk & ((value) << MATRIX_PRAS7_M0PR_Pos))) +#define MATRIX_PRAS7_M1PR_Pos 4 +#define MATRIX_PRAS7_M1PR_Msk (0x3u << MATRIX_PRAS7_M1PR_Pos) /**< \brief (MATRIX_PRAS7) Master 1 Priority */ +#define MATRIX_PRAS7_M1PR(value) ((MATRIX_PRAS7_M1PR_Msk & ((value) << MATRIX_PRAS7_M1PR_Pos))) +#define MATRIX_PRAS7_M2PR_Pos 8 +#define MATRIX_PRAS7_M2PR_Msk (0x3u << MATRIX_PRAS7_M2PR_Pos) /**< \brief (MATRIX_PRAS7) Master 2 Priority */ +#define MATRIX_PRAS7_M2PR(value) ((MATRIX_PRAS7_M2PR_Msk & ((value) << MATRIX_PRAS7_M2PR_Pos))) +#define MATRIX_PRAS7_M3PR_Pos 12 +#define MATRIX_PRAS7_M3PR_Msk (0x3u << MATRIX_PRAS7_M3PR_Pos) /**< \brief (MATRIX_PRAS7) Master 3 Priority */ +#define MATRIX_PRAS7_M3PR(value) ((MATRIX_PRAS7_M3PR_Msk & ((value) << MATRIX_PRAS7_M3PR_Pos))) +#define MATRIX_PRAS7_M4PR_Pos 16 +#define MATRIX_PRAS7_M4PR_Msk (0x3u << MATRIX_PRAS7_M4PR_Pos) /**< \brief (MATRIX_PRAS7) Master 4 Priority */ +#define MATRIX_PRAS7_M4PR(value) ((MATRIX_PRAS7_M4PR_Msk & ((value) << MATRIX_PRAS7_M4PR_Pos))) +#define MATRIX_PRAS7_M5PR_Pos 20 +#define MATRIX_PRAS7_M5PR_Msk (0x3u << MATRIX_PRAS7_M5PR_Pos) /**< \brief (MATRIX_PRAS7) Master 5 Priority */ +#define MATRIX_PRAS7_M5PR(value) ((MATRIX_PRAS7_M5PR_Msk & ((value) << MATRIX_PRAS7_M5PR_Pos))) +/* -------- MATRIX_PRAS8 : (MATRIX Offset: 0x00C0) Priority Register A for Slave 8 -------- */ +#define MATRIX_PRAS8_M0PR_Pos 0 +#define MATRIX_PRAS8_M0PR_Msk (0x3u << MATRIX_PRAS8_M0PR_Pos) /**< \brief (MATRIX_PRAS8) Master 0 Priority */ +#define MATRIX_PRAS8_M0PR(value) ((MATRIX_PRAS8_M0PR_Msk & ((value) << MATRIX_PRAS8_M0PR_Pos))) +#define MATRIX_PRAS8_M1PR_Pos 4 +#define MATRIX_PRAS8_M1PR_Msk (0x3u << MATRIX_PRAS8_M1PR_Pos) /**< \brief (MATRIX_PRAS8) Master 1 Priority */ +#define MATRIX_PRAS8_M1PR(value) ((MATRIX_PRAS8_M1PR_Msk & ((value) << MATRIX_PRAS8_M1PR_Pos))) +#define MATRIX_PRAS8_M2PR_Pos 8 +#define MATRIX_PRAS8_M2PR_Msk (0x3u << MATRIX_PRAS8_M2PR_Pos) /**< \brief (MATRIX_PRAS8) Master 2 Priority */ +#define MATRIX_PRAS8_M2PR(value) ((MATRIX_PRAS8_M2PR_Msk & ((value) << MATRIX_PRAS8_M2PR_Pos))) +#define MATRIX_PRAS8_M3PR_Pos 12 +#define MATRIX_PRAS8_M3PR_Msk (0x3u << MATRIX_PRAS8_M3PR_Pos) /**< \brief (MATRIX_PRAS8) Master 3 Priority */ +#define MATRIX_PRAS8_M3PR(value) ((MATRIX_PRAS8_M3PR_Msk & ((value) << MATRIX_PRAS8_M3PR_Pos))) +#define MATRIX_PRAS8_M4PR_Pos 16 +#define MATRIX_PRAS8_M4PR_Msk (0x3u << MATRIX_PRAS8_M4PR_Pos) /**< \brief (MATRIX_PRAS8) Master 4 Priority */ +#define MATRIX_PRAS8_M4PR(value) ((MATRIX_PRAS8_M4PR_Msk & ((value) << MATRIX_PRAS8_M4PR_Pos))) +#define MATRIX_PRAS8_M5PR_Pos 20 +#define MATRIX_PRAS8_M5PR_Msk (0x3u << MATRIX_PRAS8_M5PR_Pos) /**< \brief (MATRIX_PRAS8) Master 5 Priority */ +#define MATRIX_PRAS8_M5PR(value) ((MATRIX_PRAS8_M5PR_Msk & ((value) << MATRIX_PRAS8_M5PR_Pos))) +/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */ +#define MATRIX_MRCR_RCB0 (0x1u << 0) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 0 */ +#define MATRIX_MRCR_RCB1 (0x1u << 1) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 1 */ +#define MATRIX_MRCR_RCB2 (0x1u << 2) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 2 */ +#define MATRIX_MRCR_RCB3 (0x1u << 3) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 3 */ +#define MATRIX_MRCR_RCB4_Pos 4 +#define MATRIX_MRCR_RCB4_Msk (0x3u << MATRIX_MRCR_RCB4_Pos) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 4 */ +#define MATRIX_MRCR_RCB4(value) ((MATRIX_MRCR_RCB4_Msk & ((value) << MATRIX_MRCR_RCB4_Pos))) +#define MATRIX_MRCR_RCB5 (0x1u << 6) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 5 */ +/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O Configuration register -------- */ +#define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PC0 or ERASE Assignment */ +/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */ +#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */ +#define MATRIX_WPMR_WPKEY_Pos 8 +#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */ +#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos))) +/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */ +#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */ +#define MATRIX_WPSR_WPVSRC_Pos 8 +#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */ + +/*@}*/ + + +#endif /* _SAM3XA_MATRIX_COMPONENT_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h new file mode 100644 index 0000000..383091a --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_pdc.h @@ -0,0 +1,113 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_PDC_COMPONENT_ +#define _SAM3XA_PDC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Peripheral DMA Controller */ +/* ============================================================================= */ +/** \addtogroup SAM3XA_PDC Peripheral DMA Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Pdc hardware registers */ +typedef struct { + RwReg PERIPH_RPR; /**< \brief (Pdc Offset: 0x0) Receive Pointer Register */ + RwReg PERIPH_RCR; /**< \brief (Pdc Offset: 0x4) Receive Counter Register */ + RwReg PERIPH_TPR; /**< \brief (Pdc Offset: 0x8) Transmit Pointer Register */ + RwReg PERIPH_TCR; /**< \brief (Pdc Offset: 0xC) Transmit Counter Register */ + RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x10) Receive Next Pointer Register */ + RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x14) Receive Next Counter Register */ + RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x18) Transmit Next Pointer Register */ + RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x1C) Transmit Next Counter Register */ + WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x20) Transfer Control Register */ + RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x24) Transfer Status Register */ +} Pdc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PERIPH_RPR : (PDC Offset: 0x0) Receive Pointer Register -------- */ +#define PERIPH_RPR_RXPTR_Pos 0 +#define PERIPH_RPR_RXPTR_Msk (0xffffffffu << PERIPH_RPR_RXPTR_Pos) /**< \brief (PERIPH_RPR) Receive Pointer Register */ +#define PERIPH_RPR_RXPTR(value) ((PERIPH_RPR_RXPTR_Msk & ((value) << PERIPH_RPR_RXPTR_Pos))) +/* -------- PERIPH_RCR : (PDC Offset: 0x4) Receive Counter Register -------- */ +#define PERIPH_RCR_RXCTR_Pos 0 +#define PERIPH_RCR_RXCTR_Msk (0xffffu << PERIPH_RCR_RXCTR_Pos) /**< \brief (PERIPH_RCR) Receive Counter Register */ +#define PERIPH_RCR_RXCTR(value) ((PERIPH_RCR_RXCTR_Msk & ((value) << PERIPH_RCR_RXCTR_Pos))) +/* -------- PERIPH_TPR : (PDC Offset: 0x8) Transmit Pointer Register -------- */ +#define PERIPH_TPR_TXPTR_Pos 0 +#define PERIPH_TPR_TXPTR_Msk (0xffffffffu << PERIPH_TPR_TXPTR_Pos) /**< \brief (PERIPH_TPR) Transmit Counter Register */ +#define PERIPH_TPR_TXPTR(value) ((PERIPH_TPR_TXPTR_Msk & ((value) << PERIPH_TPR_TXPTR_Pos))) +/* -------- PERIPH_TCR : (PDC Offset: 0xC) Transmit Counter Register -------- */ +#define PERIPH_TCR_TXCTR_Pos 0 +#define PERIPH_TCR_TXCTR_Msk (0xffffu << PERIPH_TCR_TXCTR_Pos) /**< \brief (PERIPH_TCR) Transmit Counter Register */ +#define PERIPH_TCR_TXCTR(value) ((PERIPH_TCR_TXCTR_Msk & ((value) << PERIPH_TCR_TXCTR_Pos))) +/* -------- PERIPH_RNPR : (PDC Offset: 0x10) Receive Next Pointer Register -------- */ +#define PERIPH_RNPR_RXNPTR_Pos 0 +#define PERIPH_RNPR_RXNPTR_Msk (0xffffffffu << PERIPH_RNPR_RXNPTR_Pos) /**< \brief (PERIPH_RNPR) Receive Next Pointer */ +#define PERIPH_RNPR_RXNPTR(value) ((PERIPH_RNPR_RXNPTR_Msk & ((value) << PERIPH_RNPR_RXNPTR_Pos))) +/* -------- PERIPH_RNCR : (PDC Offset: 0x14) Receive Next Counter Register -------- */ +#define PERIPH_RNCR_RXNCTR_Pos 0 +#define PERIPH_RNCR_RXNCTR_Msk (0xffffu << PERIPH_RNCR_RXNCTR_Pos) /**< \brief (PERIPH_RNCR) Receive Next Counter */ +#define PERIPH_RNCR_RXNCTR(value) ((PERIPH_RNCR_RXNCTR_Msk & ((value) << PERIPH_RNCR_RXNCTR_Pos))) +/* -------- PERIPH_TNPR : (PDC Offset: 0x18) Transmit Next Pointer Register -------- */ +#define PERIPH_TNPR_TXNPTR_Pos 0 +#define PERIPH_TNPR_TXNPTR_Msk (0xffffffffu << PERIPH_TNPR_TXNPTR_Pos) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */ +#define PERIPH_TNPR_TXNPTR(value) ((PERIPH_TNPR_TXNPTR_Msk & ((value) << PERIPH_TNPR_TXNPTR_Pos))) +/* -------- PERIPH_TNCR : (PDC Offset: 0x1C) Transmit Next Counter Register -------- */ +#define PERIPH_TNCR_TXNCTR_Pos 0 +#define PERIPH_TNCR_TXNCTR_Msk (0xffffu << PERIPH_TNCR_TXNCTR_Pos) /**< \brief (PERIPH_TNCR) Transmit Counter Next */ +#define PERIPH_TNCR_TXNCTR(value) ((PERIPH_TNCR_TXNCTR_Msk & ((value) << PERIPH_TNCR_TXNCTR_Pos))) +/* -------- PERIPH_PTCR : (PDC Offset: 0x20) Transfer Control Register -------- */ +#define PERIPH_PTCR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */ +#define PERIPH_PTCR_RXTDIS (0x1u << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */ +#define PERIPH_PTCR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */ +#define PERIPH_PTCR_TXTDIS (0x1u << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */ +/* -------- PERIPH_PTSR : (PDC Offset: 0x24) Transfer Status Register -------- */ +#define PERIPH_PTSR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */ +#define PERIPH_PTSR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + + +#endif /* _SAM3XA_PDC_COMPONENT_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h new file mode 100644 index 0000000..d1049f0 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_pio.h @@ -0,0 +1,1450 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_PIO_COMPONENT_ +#define _SAM3XA_PIO_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */ +/* ============================================================================= */ +/** \addtogroup SAM3XA_PIO Parallel Input/Output Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Pio hardware registers */ +typedef struct { + WoReg PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */ + WoReg PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */ + RoReg PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */ + RoReg Reserved1[1]; + WoReg PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */ + WoReg PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */ + RoReg PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */ + RoReg Reserved2[1]; + WoReg PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */ + WoReg PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */ + RoReg PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */ + RoReg Reserved3[1]; + WoReg PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */ + WoReg PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */ + RwReg PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */ + RoReg PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */ + WoReg PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */ + WoReg PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */ + RoReg PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */ + RoReg PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */ + WoReg PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */ + WoReg PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */ + RoReg PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */ + RoReg Reserved4[1]; + WoReg PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */ + WoReg PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */ + RoReg PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */ + RoReg Reserved5[1]; + RwReg PIO_ABSR; /**< \brief (Pio Offset: 0x0070) Peripheral AB Select Register */ + RoReg Reserved6[3]; + WoReg PIO_SCIFSR; /**< \brief (Pio Offset: 0x0080) System Clock Glitch Input Filter Select Register */ + WoReg PIO_DIFSR; /**< \brief (Pio Offset: 0x0084) Debouncing Input Filter Select Register */ + RoReg PIO_IFDGSR; /**< \brief (Pio Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register */ + RwReg PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */ + RoReg Reserved7[4]; + WoReg PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */ + WoReg PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */ + RoReg PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */ + RoReg Reserved8[1]; + WoReg PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */ + WoReg PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */ + RoReg PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */ + RoReg Reserved9[1]; + WoReg PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */ + WoReg PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */ + RoReg PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */ + RoReg Reserved10[1]; + WoReg PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */ + WoReg PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */ + RoReg PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */ + RoReg Reserved11[1]; + RoReg PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */ + RwReg PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */ + RoReg PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */ +} Pio; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */ +#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */ +/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */ +#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */ +/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */ +#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */ +/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */ +#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */ +/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */ +#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */ +/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */ +#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */ +/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */ +#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */ +/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */ +#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */ +/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */ +#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filer Status */ +/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */ +#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */ +/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */ +#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */ +/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */ +#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */ +/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */ +#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */ +/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */ +#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */ +#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */ +#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */ +#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */ +#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */ +/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */ +#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */ +#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */ +/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */ +#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */ +/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */ +#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull Up Enable. */ +/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */ +#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull Up Status. */ +/* -------- PIO_ABSR : (PIO Offset: 0x0070) Peripheral AB Select Register -------- */ +#define PIO_ABSR_P0 (0x1u << 0) /**< \brief (PIO_ABSR) Peripheral A Select. */ +#define PIO_ABSR_P1 (0x1u << 1) /**< \brief (PIO_ABSR) Peripheral A Select. */ +#define PIO_ABSR_P2 (0x1u << 2) /**< \brief (PIO_ABSR) Peripheral A Select. */ +#define PIO_ABSR_P3 (0x1u << 3) /**< \brief (PIO_ABSR) Peripheral A Select. */ +#define PIO_ABSR_P4 (0x1u << 4) /**< \brief (PIO_ABSR) Peripheral A Select. */ +#define PIO_ABSR_P5 (0x1u << 5) /**< \brief (PIO_ABSR) Peripheral A Select. */ +#define PIO_ABSR_P6 (0x1u << 6) /**< \brief (PIO_ABSR) Peripheral A Select. */ +#define PIO_ABSR_P7 (0x1u << 7) /**< \brief (PIO_ABSR) Peripheral A Select. */ +#define PIO_ABSR_P8 (0x1u << 8) /**< \brief (PIO_ABSR) Peripheral A Select. */ +#define PIO_ABSR_P9 (0x1u << 9) /**< \brief (PIO_ABSR) Peripheral A Select. */ +#define PIO_ABSR_P10 (0x1u << 10) /**< \brief (PIO_ABSR) Peripheral A Select. */ +#define PIO_ABSR_P11 (0x1u << 11) /**< \brief (PIO_ABSR) Peripheral A Select. */ +#define PIO_ABSR_P12 (0x1u << 12) /**< \brief (PIO_ABSR) Peripheral A Select. */ +#define PIO_ABSR_P13 (0x1u << 13) /**< \brief (PIO_ABSR) Peripheral A Select. */ +#define PIO_ABSR_P14 (0x1u << 14) /**< \brief (PIO_ABSR) Peripheral A Select. */ +#define PIO_ABSR_P15 (0x1u << 15) /**< \brief (PIO_ABSR) Peripheral A Select. */ +#define PIO_ABSR_P16 (0x1u << 16) /**< \brief (PIO_ABSR) Peripheral A Select. */ +#define PIO_ABSR_P17 (0x1u << 17) /**< \brief (PIO_ABSR) Peripheral A Select. */ +#define PIO_ABSR_P18 (0x1u << 18) /**< \brief (PIO_ABSR) Peripheral A Select. */ +#define PIO_ABSR_P19 (0x1u << 19) /**< \brief (PIO_ABSR) Peripheral A Select. */ +#define PIO_ABSR_P20 (0x1u << 20) /**< \brief (PIO_ABSR) Peripheral A Select. */ +#define PIO_ABSR_P21 (0x1u << 21) /**< \brief (PIO_ABSR) Peripheral A Select. */ +#define PIO_ABSR_P22 (0x1u << 22) /**< \brief (PIO_ABSR) Peripheral A Select. */ +#define PIO_ABSR_P23 (0x1u << 23) /**< \brief (PIO_ABSR) Peripheral A Select. */ +#define PIO_ABSR_P24 (0x1u << 24) /**< \brief (PIO_ABSR) Peripheral A Select. */ +#define PIO_ABSR_P25 (0x1u << 25) /**< \brief (PIO_ABSR) Peripheral A Select. */ +#define PIO_ABSR_P26 (0x1u << 26) /**< \brief (PIO_ABSR) Peripheral A Select. */ +#define PIO_ABSR_P27 (0x1u << 27) /**< \brief (PIO_ABSR) Peripheral A Select. */ +#define PIO_ABSR_P28 (0x1u << 28) /**< \brief (PIO_ABSR) Peripheral A Select. */ +#define PIO_ABSR_P29 (0x1u << 29) /**< \brief (PIO_ABSR) Peripheral A Select. */ +#define PIO_ABSR_P30 (0x1u << 30) /**< \brief (PIO_ABSR) Peripheral A Select. */ +#define PIO_ABSR_P31 (0x1u << 31) /**< \brief (PIO_ABSR) Peripheral A Select. */ +/* -------- PIO_SCIFSR : (PIO Offset: 0x0080) System Clock Glitch Input Filter Select Register -------- */ +#define PIO_SCIFSR_P0 (0x1u << 0) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P1 (0x1u << 1) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P2 (0x1u << 2) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P3 (0x1u << 3) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P4 (0x1u << 4) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P5 (0x1u << 5) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P6 (0x1u << 6) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P7 (0x1u << 7) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P8 (0x1u << 8) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P9 (0x1u << 9) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P10 (0x1u << 10) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P11 (0x1u << 11) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P12 (0x1u << 12) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P13 (0x1u << 13) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P14 (0x1u << 14) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P15 (0x1u << 15) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P16 (0x1u << 16) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P17 (0x1u << 17) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P18 (0x1u << 18) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P19 (0x1u << 19) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P20 (0x1u << 20) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P21 (0x1u << 21) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P22 (0x1u << 22) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P23 (0x1u << 23) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P24 (0x1u << 24) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P25 (0x1u << 25) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P26 (0x1u << 26) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P27 (0x1u << 27) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P28 (0x1u << 28) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P29 (0x1u << 29) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P30 (0x1u << 30) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +#define PIO_SCIFSR_P31 (0x1u << 31) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ +/* -------- PIO_DIFSR : (PIO Offset: 0x0084) Debouncing Input Filter Select Register -------- */ +#define PIO_DIFSR_P0 (0x1u << 0) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P1 (0x1u << 1) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P2 (0x1u << 2) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P3 (0x1u << 3) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P4 (0x1u << 4) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P5 (0x1u << 5) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P6 (0x1u << 6) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P7 (0x1u << 7) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P8 (0x1u << 8) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P9 (0x1u << 9) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P10 (0x1u << 10) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P11 (0x1u << 11) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P12 (0x1u << 12) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P13 (0x1u << 13) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P14 (0x1u << 14) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P15 (0x1u << 15) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P16 (0x1u << 16) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P17 (0x1u << 17) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P18 (0x1u << 18) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P19 (0x1u << 19) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P20 (0x1u << 20) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P21 (0x1u << 21) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P22 (0x1u << 22) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P23 (0x1u << 23) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P24 (0x1u << 24) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P25 (0x1u << 25) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P26 (0x1u << 26) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P27 (0x1u << 27) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P28 (0x1u << 28) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P29 (0x1u << 29) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P30 (0x1u << 30) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +#define PIO_DIFSR_P31 (0x1u << 31) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ +/* -------- PIO_IFDGSR : (PIO Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register -------- */ +#define PIO_IFDGSR_P0 (0x1u << 0) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P1 (0x1u << 1) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P2 (0x1u << 2) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P3 (0x1u << 3) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P4 (0x1u << 4) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P5 (0x1u << 5) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P6 (0x1u << 6) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P7 (0x1u << 7) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P8 (0x1u << 8) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P9 (0x1u << 9) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P10 (0x1u << 10) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P11 (0x1u << 11) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P12 (0x1u << 12) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P13 (0x1u << 13) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P14 (0x1u << 14) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P15 (0x1u << 15) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P16 (0x1u << 16) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P17 (0x1u << 17) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P18 (0x1u << 18) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P19 (0x1u << 19) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P20 (0x1u << 20) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P21 (0x1u << 21) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P22 (0x1u << 22) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P23 (0x1u << 23) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P24 (0x1u << 24) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P25 (0x1u << 25) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P26 (0x1u << 26) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P27 (0x1u << 27) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P28 (0x1u << 28) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P29 (0x1u << 29) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P30 (0x1u << 30) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFDGSR_P31 (0x1u << 31) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ +/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */ +#define PIO_SCDR_DIV_Pos 0 +#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos))) +/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */ +#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable. */ +/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */ +#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable. */ +/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */ +#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status. */ +/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */ +#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */ +#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */ +#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */ +#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */ +#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */ +#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */ +#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */ +#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */ +#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */ +#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status. */ +/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */ +#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protect Enable */ +#define PIO_WPMR_WPKEY_Pos 8 +#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protect KEY */ +#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos))) +/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */ +#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */ +#define PIO_WPSR_WPVSRC_Pos 8 +#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protect Violation Source */ + +/*@}*/ + + +#endif /* _SAM3XA_PIO_COMPONENT_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h new file mode 100644 index 0000000..8846696 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_pmc.h @@ -0,0 +1,431 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_PMC_COMPONENT_ +#define _SAM3XA_PMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Power Management Controller */ +/* ============================================================================= */ +/** \addtogroup SAM3XA_PMC Power Management Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Pmc hardware registers */ +typedef struct { + WoReg PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */ + WoReg PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */ + RoReg PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */ + RoReg Reserved1[1]; + WoReg PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */ + WoReg PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */ + RoReg PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */ + RwReg CKGR_UCKR; /**< \brief (Pmc Offset: 0x001C) UTMI Clock Register */ + RwReg CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */ + RoReg CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */ + RwReg CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */ + RoReg Reserved2[1]; + RwReg PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */ + RoReg Reserved3[1]; + RwReg PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */ + RoReg Reserved4[1]; + RwReg PMC_PCK[3]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */ + RoReg Reserved5[5]; + WoReg PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */ + WoReg PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */ + RoReg PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */ + RoReg PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */ + RwReg PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */ + RwReg PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */ + WoReg PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */ + RoReg Reserved6[26]; + RwReg PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */ + RoReg PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */ + RoReg Reserved7[5]; + WoReg PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */ + WoReg PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */ + RoReg PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */ + RwReg PMC_PCR; /**< \brief (Pmc Offset: 0x010C) Peripheral Control Register */ +} Pmc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */ +#define PMC_SCER_UOTGCLK (0x1u << 5) /**< \brief (PMC_SCER) Enable USB OTG Clock (48 MHz, USB_48M) for UTMI */ +#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */ +#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */ +#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */ +/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */ +#define PMC_SCDR_UOTGCLK (0x1u << 5) /**< \brief (PMC_SCDR) Disable USB OTG Clock (48 MHz, USB_48M) for UTMI */ +#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */ +#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */ +#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */ +/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */ +#define PMC_SCSR_UOTGCLK (0x1u << 5) /**< \brief (PMC_SCSR) USB OTG Clock (48 MHz, USB_48M) Clock Status */ +#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */ +#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */ +#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */ +/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */ +#define PMC_PCER0_PID2 (0x1u << 2) /**< \brief (PMC_PCER0) Peripheral Clock 2 Enable */ +#define PMC_PCER0_PID3 (0x1u << 3) /**< \brief (PMC_PCER0) Peripheral Clock 3 Enable */ +#define PMC_PCER0_PID4 (0x1u << 4) /**< \brief (PMC_PCER0) Peripheral Clock 4 Enable */ +#define PMC_PCER0_PID5 (0x1u << 5) /**< \brief (PMC_PCER0) Peripheral Clock 5 Enable */ +#define PMC_PCER0_PID6 (0x1u << 6) /**< \brief (PMC_PCER0) Peripheral Clock 6 Enable */ +#define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */ +#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */ +#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */ +#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */ +#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */ +#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */ +#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */ +#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */ +#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */ +#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */ +#define PMC_PCER0_PID17 (0x1u << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */ +#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */ +#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */ +#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */ +#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */ +#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */ +#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */ +#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */ +#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */ +#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */ +#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */ +#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */ +#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */ +#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */ +#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */ +/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */ +#define PMC_PCDR0_PID2 (0x1u << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */ +#define PMC_PCDR0_PID3 (0x1u << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */ +#define PMC_PCDR0_PID4 (0x1u << 4) /**< \brief (PMC_PCDR0) Peripheral Clock 4 Disable */ +#define PMC_PCDR0_PID5 (0x1u << 5) /**< \brief (PMC_PCDR0) Peripheral Clock 5 Disable */ +#define PMC_PCDR0_PID6 (0x1u << 6) /**< \brief (PMC_PCDR0) Peripheral Clock 6 Disable */ +#define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */ +#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */ +#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */ +#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */ +#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */ +#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */ +#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */ +#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */ +#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */ +#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */ +#define PMC_PCDR0_PID17 (0x1u << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */ +#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */ +#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */ +#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */ +#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */ +#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */ +#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */ +#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */ +#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */ +#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */ +#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */ +#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */ +#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */ +#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */ +#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */ +/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */ +#define PMC_PCSR0_PID2 (0x1u << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */ +#define PMC_PCSR0_PID3 (0x1u << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */ +#define PMC_PCSR0_PID4 (0x1u << 4) /**< \brief (PMC_PCSR0) Peripheral Clock 4 Status */ +#define PMC_PCSR0_PID5 (0x1u << 5) /**< \brief (PMC_PCSR0) Peripheral Clock 5 Status */ +#define PMC_PCSR0_PID6 (0x1u << 6) /**< \brief (PMC_PCSR0) Peripheral Clock 6 Status */ +#define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */ +#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */ +#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */ +#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */ +#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */ +#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */ +#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */ +#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */ +#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */ +#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */ +#define PMC_PCSR0_PID17 (0x1u << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */ +#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */ +#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */ +#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */ +#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */ +#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */ +#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */ +#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */ +#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */ +#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */ +#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */ +#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */ +#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */ +#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */ +#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */ +/* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */ +#define CKGR_UCKR_UPLLEN (0x1u << 16) /**< \brief (CKGR_UCKR) UTMI PLL Enable */ +#define CKGR_UCKR_UPLLCOUNT_Pos 20 +#define CKGR_UCKR_UPLLCOUNT_Msk (0xfu << CKGR_UCKR_UPLLCOUNT_Pos) /**< \brief (CKGR_UCKR) UTMI PLL Start-up Time */ +#define CKGR_UCKR_UPLLCOUNT(value) ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos))) +/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */ +#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */ +#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */ +#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */ +#define CKGR_MOR_MOSCRCF_Pos 4 +#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */ +#define CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 4 MHz (default) */ +#define CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 8 MHz */ +#define CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 12 MHz */ +#define CKGR_MOR_MOSCXTST_Pos 8 +#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */ +#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos))) +#define CKGR_MOR_KEY_Pos 16 +#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Password */ +#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos))) +#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */ +#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */ +/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */ +#define CKGR_MCFR_MAINF_Pos 0 +#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */ +#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */ +/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */ +#define CKGR_PLLAR_DIVA_Pos 0 +#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) Divider */ +#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos))) +#define CKGR_PLLAR_PLLACOUNT_Pos 8 +#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */ +#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos))) +#define CKGR_PLLAR_MULA_Pos 16 +#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */ +#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos))) +#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */ +/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */ +#define PMC_MCKR_CSS_Pos 0 +#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */ +#define PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */ +#define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */ +#define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */ +#define PMC_MCKR_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_MCKR) UPLL Clock is selected */ +#define PMC_MCKR_PRES_Pos 4 +#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */ +#define PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */ +#define PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */ +#define PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */ +#define PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */ +#define PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */ +#define PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */ +#define PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */ +#define PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */ +#define PMC_MCKR_PLLADIV2 (0x1u << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */ +#define PMC_MCKR_UPLLDIV2 (0x1u << 13) /**< \brief (PMC_MCKR) */ +/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */ +#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB Input Clock Selection */ +#define PMC_USB_USBDIV_Pos 8 +#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock. */ +#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos))) +/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */ +#define PMC_PCK_CSS_Pos 0 +#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */ +#define PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[3]) Slow Clock is selected */ +#define PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[3]) Main Clock is selected */ +#define PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[3]) PLLA Clock is selected */ +#define PMC_PCK_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK[3]) UPLL Clock is selected */ +#define PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[3]) Master Clock is selected */ +#define PMC_PCK_PRES_Pos 4 +#define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */ +#define PMC_PCK_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_PCK[3]) Selected clock */ +#define PMC_PCK_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 2 */ +#define PMC_PCK_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 4 */ +#define PMC_PCK_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 8 */ +#define PMC_PCK_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 16 */ +#define PMC_PCK_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 32 */ +#define PMC_PCK_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 64 */ +/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */ +#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */ +#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */ +#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */ +#define PMC_IER_LOCKU (0x1u << 6) /**< \brief (PMC_IER) UTMI PLL Lock Interrupt Enable */ +#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */ +#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */ +#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */ +#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */ +#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */ +#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */ +/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */ +#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */ +#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */ +#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */ +#define PMC_IDR_LOCKU (0x1u << 6) /**< \brief (PMC_IDR) UTMI PLL Lock Interrupt Disable */ +#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */ +#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */ +#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */ +#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */ +#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */ +#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */ +/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */ +#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */ +#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */ +#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */ +#define PMC_SR_LOCKU (0x1u << 6) /**< \brief (PMC_SR) UTMI PLL Lock Status */ +#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */ +#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */ +#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */ +#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */ +#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */ +#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */ +/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */ +#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */ +#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */ +#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */ +#define PMC_IMR_LOCKU (0x1u << 6) /**< \brief (PMC_IMR) UTMI PLL Lock Interrupt Mask */ +#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */ +#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */ +#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */ +#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */ +#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */ +#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */ +/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */ +#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */ +#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */ +#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */ +#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */ +#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */ +#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */ +#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */ +#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */ +#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */ +#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */ +#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */ +#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */ +#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */ +#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */ +#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */ +#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */ +#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */ +#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */ +#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */ +#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low Power Mode */ +/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */ +#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */ +#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */ +/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */ +#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protect Enable */ +#define PMC_WPMR_WPKEY_Pos 8 +#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protect KEY */ +#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos))) +/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */ +#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */ +#define PMC_WPSR_WPVSRC_Pos 8 +#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protect Violation Source */ +/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */ +#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */ +#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */ +#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */ +#define PMC_PCER1_PID35 (0x1u << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */ +#define PMC_PCER1_PID36 (0x1u << 4) /**< \brief (PMC_PCER1) Peripheral Clock 36 Enable */ +#define PMC_PCER1_PID37 (0x1u << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */ +#define PMC_PCER1_PID38 (0x1u << 6) /**< \brief (PMC_PCER1) Peripheral Clock 38 Enable */ +#define PMC_PCER1_PID39 (0x1u << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */ +#define PMC_PCER1_PID40 (0x1u << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */ +#define PMC_PCER1_PID41 (0x1u << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */ +#define PMC_PCER1_PID42 (0x1u << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */ +#define PMC_PCER1_PID43 (0x1u << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */ +#define PMC_PCER1_PID44 (0x1u << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */ +/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */ +#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */ +#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */ +#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */ +#define PMC_PCDR1_PID35 (0x1u << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */ +#define PMC_PCDR1_PID36 (0x1u << 4) /**< \brief (PMC_PCDR1) Peripheral Clock 36 Disable */ +#define PMC_PCDR1_PID37 (0x1u << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */ +#define PMC_PCDR1_PID38 (0x1u << 6) /**< \brief (PMC_PCDR1) Peripheral Clock 38 Disable */ +#define PMC_PCDR1_PID39 (0x1u << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */ +#define PMC_PCDR1_PID40 (0x1u << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */ +#define PMC_PCDR1_PID41 (0x1u << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */ +#define PMC_PCDR1_PID42 (0x1u << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */ +#define PMC_PCDR1_PID43 (0x1u << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */ +#define PMC_PCDR1_PID44 (0x1u << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */ +/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */ +#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */ +#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */ +#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */ +#define PMC_PCSR1_PID35 (0x1u << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */ +#define PMC_PCSR1_PID36 (0x1u << 4) /**< \brief (PMC_PCSR1) Peripheral Clock 36 Status */ +#define PMC_PCSR1_PID37 (0x1u << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */ +#define PMC_PCSR1_PID38 (0x1u << 6) /**< \brief (PMC_PCSR1) Peripheral Clock 38 Status */ +#define PMC_PCSR1_PID39 (0x1u << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */ +#define PMC_PCSR1_PID40 (0x1u << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */ +#define PMC_PCSR1_PID41 (0x1u << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */ +#define PMC_PCSR1_PID42 (0x1u << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */ +#define PMC_PCSR1_PID43 (0x1u << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */ +#define PMC_PCSR1_PID44 (0x1u << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */ +/* -------- PMC_PCR : (PMC Offset: 0x010C) Peripheral Control Register -------- */ +#define PMC_PCR_PID_Pos 0 +#define PMC_PCR_PID_Msk (0x3fu << PMC_PCR_PID_Pos) /**< \brief (PMC_PCR) Peripheral ID */ +#define PMC_PCR_PID(value) ((PMC_PCR_PID_Msk & ((value) << PMC_PCR_PID_Pos))) +#define PMC_PCR_CMD (0x1u << 12) /**< \brief (PMC_PCR) Command */ +#define PMC_PCR_DIV_Pos 16 +#define PMC_PCR_DIV_Msk (0x3u << PMC_PCR_DIV_Pos) /**< \brief (PMC_PCR) Divisor Value */ +#define PMC_PCR_DIV_PERIPH_DIV_MCK (0x0u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK */ +#define PMC_PCR_DIV_PERIPH_DIV2_MCK (0x1u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/2 */ +#define PMC_PCR_DIV_PERIPH_DIV4_MCK (0x2u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/4 */ +#define PMC_PCR_EN (0x1u << 28) /**< \brief (PMC_PCR) Enable */ + +/*@}*/ + + +#endif /* _SAM3XA_PMC_COMPONENT_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h new file mode 100644 index 0000000..4180a13 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_pwm.h @@ -0,0 +1,682 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_PWM_COMPONENT_ +#define _SAM3XA_PWM_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */ +/* ============================================================================= */ +/** \addtogroup SAM3XA_PWM Pulse Width Modulation Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief PwmCh_num hardware registers */ +typedef struct { + RwReg PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */ + RwReg PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */ + RwReg PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */ + RwReg PWM_CPRD; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */ + RwReg PWM_CPRDUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */ + RwReg PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */ + RwReg PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */ + RwReg PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */ +} PwmCh_num; +/** \brief PwmCmp hardware registers */ +typedef struct { + RwReg PWM_CMPV; /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */ + RwReg PWM_CMPVUPD; /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */ + RwReg PWM_CMPM; /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */ + RwReg PWM_CMPMUPD; /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */ +} PwmCmp; +/** \brief Pwm hardware registers */ +#define PWMCMP_NUMBER 8 +#define PWMCH_NUM_NUMBER 8 +typedef struct { + RwReg PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */ + WoReg PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */ + WoReg PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */ + RoReg PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */ + WoReg PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */ + WoReg PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */ + RoReg PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */ + RoReg PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */ + RwReg PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */ + RoReg Reserved1[1]; + RwReg PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */ + RwReg PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */ + WoReg PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */ + WoReg PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */ + WoReg PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */ + RoReg PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */ + RoReg PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */ + RwReg PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */ + RwReg PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */ + WoReg PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */ + WoReg PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */ + WoReg PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */ + WoReg PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */ + RwReg PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */ + RoReg PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */ + WoReg PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */ + RwReg PWM_FPV; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */ + RwReg PWM_FPE1; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register 1 */ + RwReg PWM_FPE2; /**< \brief (Pwm Offset: 0x70) PWM Fault Protection Enable Register 2 */ + RoReg Reserved2[2]; + RwReg PWM_ELMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */ + RoReg Reserved3[11]; + RwReg PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */ + RoReg Reserved4[12]; + WoReg PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */ + RoReg PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */ + RoReg Reserved5[7]; + RwReg PWM_TPR; /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */ + RwReg PWM_TCR; /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */ + RoReg Reserved6[2]; + RwReg PWM_TNPR; /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */ + RwReg PWM_TNCR; /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */ + WoReg PWM_PTCR; /**< \brief (Pwm Offset: 0x120) Transfer Control Register */ + RoReg PWM_PTSR; /**< \brief (Pwm Offset: 0x124) Transfer Status Register */ + RoReg Reserved7[2]; + PwmCmp PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */ + RoReg Reserved8[20]; + PwmCh_num PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 7 */ +} Pwm; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */ +#define PWM_CLK_DIVA_Pos 0 +#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ +#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos))) +#define PWM_CLK_PREA_Pos 8 +#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ +#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos))) +#define PWM_CLK_DIVB_Pos 16 +#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ +#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos))) +#define PWM_CLK_PREB_Pos 24 +#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ +#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos))) +/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */ +#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID4 (0x1u << 4) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID5 (0x1u << 5) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID6 (0x1u << 6) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID7 (0x1u << 7) /**< \brief (PWM_ENA) Channel ID */ +/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */ +#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID4 (0x1u << 4) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID5 (0x1u << 5) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID6 (0x1u << 6) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID7 (0x1u << 7) /**< \brief (PWM_DIS) Channel ID */ +/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */ +#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID4 (0x1u << 4) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID5 (0x1u << 5) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID6 (0x1u << 6) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID7 (0x1u << 7) /**< \brief (PWM_SR) Channel ID */ +/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */ +#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */ +#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */ +#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */ +#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */ +#define PWM_IER1_CHID4 (0x1u << 4) /**< \brief (PWM_IER1) Counter Event on Channel 4 Interrupt Enable */ +#define PWM_IER1_CHID5 (0x1u << 5) /**< \brief (PWM_IER1) Counter Event on Channel 5 Interrupt Enable */ +#define PWM_IER1_CHID6 (0x1u << 6) /**< \brief (PWM_IER1) Counter Event on Channel 6 Interrupt Enable */ +#define PWM_IER1_CHID7 (0x1u << 7) /**< \brief (PWM_IER1) Counter Event on Channel 7 Interrupt Enable */ +#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */ +#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */ +#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */ +#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */ +#define PWM_IER1_FCHID4 (0x1u << 20) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 4 Interrupt Enable */ +#define PWM_IER1_FCHID5 (0x1u << 21) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 5 Interrupt Enable */ +#define PWM_IER1_FCHID6 (0x1u << 22) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 6 Interrupt Enable */ +#define PWM_IER1_FCHID7 (0x1u << 23) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 7 Interrupt Enable */ +/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */ +#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */ +#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */ +#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */ +#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */ +#define PWM_IDR1_CHID4 (0x1u << 4) /**< \brief (PWM_IDR1) Counter Event on Channel 4 Interrupt Disable */ +#define PWM_IDR1_CHID5 (0x1u << 5) /**< \brief (PWM_IDR1) Counter Event on Channel 5 Interrupt Disable */ +#define PWM_IDR1_CHID6 (0x1u << 6) /**< \brief (PWM_IDR1) Counter Event on Channel 6 Interrupt Disable */ +#define PWM_IDR1_CHID7 (0x1u << 7) /**< \brief (PWM_IDR1) Counter Event on Channel 7 Interrupt Disable */ +#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */ +#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */ +#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */ +#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */ +#define PWM_IDR1_FCHID4 (0x1u << 20) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 4 Interrupt Disable */ +#define PWM_IDR1_FCHID5 (0x1u << 21) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 5 Interrupt Disable */ +#define PWM_IDR1_FCHID6 (0x1u << 22) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 6 Interrupt Disable */ +#define PWM_IDR1_FCHID7 (0x1u << 23) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 7 Interrupt Disable */ +/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */ +#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */ +#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */ +#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */ +#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */ +#define PWM_IMR1_CHID4 (0x1u << 4) /**< \brief (PWM_IMR1) Counter Event on Channel 4 Interrupt Mask */ +#define PWM_IMR1_CHID5 (0x1u << 5) /**< \brief (PWM_IMR1) Counter Event on Channel 5 Interrupt Mask */ +#define PWM_IMR1_CHID6 (0x1u << 6) /**< \brief (PWM_IMR1) Counter Event on Channel 6 Interrupt Mask */ +#define PWM_IMR1_CHID7 (0x1u << 7) /**< \brief (PWM_IMR1) Counter Event on Channel 7 Interrupt Mask */ +#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */ +#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */ +#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */ +#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */ +#define PWM_IMR1_FCHID4 (0x1u << 20) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 4 Interrupt Mask */ +#define PWM_IMR1_FCHID5 (0x1u << 21) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 5 Interrupt Mask */ +#define PWM_IMR1_FCHID6 (0x1u << 22) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 6 Interrupt Mask */ +#define PWM_IMR1_FCHID7 (0x1u << 23) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 7 Interrupt Mask */ +/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */ +#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */ +#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */ +#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */ +#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */ +#define PWM_ISR1_CHID4 (0x1u << 4) /**< \brief (PWM_ISR1) Counter Event on Channel 4 */ +#define PWM_ISR1_CHID5 (0x1u << 5) /**< \brief (PWM_ISR1) Counter Event on Channel 5 */ +#define PWM_ISR1_CHID6 (0x1u << 6) /**< \brief (PWM_ISR1) Counter Event on Channel 6 */ +#define PWM_ISR1_CHID7 (0x1u << 7) /**< \brief (PWM_ISR1) Counter Event on Channel 7 */ +#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */ +#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */ +#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */ +#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */ +#define PWM_ISR1_FCHID4 (0x1u << 20) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 4 */ +#define PWM_ISR1_FCHID5 (0x1u << 21) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 5 */ +#define PWM_ISR1_FCHID6 (0x1u << 22) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 6 */ +#define PWM_ISR1_FCHID7 (0x1u << 23) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 7 */ +/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */ +#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */ +#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */ +#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */ +#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */ +#define PWM_SCM_SYNC4 (0x1u << 4) /**< \brief (PWM_SCM) Synchronous Channel 4 */ +#define PWM_SCM_SYNC5 (0x1u << 5) /**< \brief (PWM_SCM) Synchronous Channel 5 */ +#define PWM_SCM_SYNC6 (0x1u << 6) /**< \brief (PWM_SCM) Synchronous Channel 6 */ +#define PWM_SCM_SYNC7 (0x1u << 7) /**< \brief (PWM_SCM) Synchronous Channel 7 */ +#define PWM_SCM_UPDM_Pos 16 +#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */ +#define PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */ +#define PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */ +#define PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels */ +#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */ +#define PWM_SCM_PTRCS_Pos 21 +#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */ +#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos))) +/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */ +#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */ +/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */ +#define PWM_SCUP_UPR_Pos 0 +#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */ +#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos))) +#define PWM_SCUP_UPRCNT_Pos 4 +#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */ +#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos))) +/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */ +#define PWM_SCUPUPD_UPRUPD_Pos 0 +#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */ +#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos))) +/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */ +#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */ +#define PWM_IER2_ENDTX (0x1u << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */ +#define PWM_IER2_TXBUFE (0x1u << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */ +#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */ +#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */ +#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */ +#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */ +#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */ +#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */ +#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */ +#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */ +#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */ +#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */ +#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */ +#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */ +#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */ +#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */ +#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */ +#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */ +#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */ +/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */ +#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */ +#define PWM_IDR2_ENDTX (0x1u << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */ +#define PWM_IDR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */ +#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */ +#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */ +#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */ +#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */ +#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */ +#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */ +#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */ +#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */ +#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */ +#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */ +#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */ +#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */ +#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */ +#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */ +#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */ +#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */ +#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */ +/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */ +#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */ +#define PWM_IMR2_ENDTX (0x1u << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */ +#define PWM_IMR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */ +#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */ +#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */ +#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */ +#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */ +#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */ +#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */ +#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */ +#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */ +#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */ +#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */ +#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */ +#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */ +#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */ +#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */ +#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */ +#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */ +#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */ +/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */ +#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */ +#define PWM_ISR2_ENDTX (0x1u << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */ +#define PWM_ISR2_TXBUFE (0x1u << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */ +#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */ +#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */ +#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */ +#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */ +#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */ +#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */ +#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */ +#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */ +#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */ +#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */ +#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */ +#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */ +#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */ +#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */ +#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */ +#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */ +#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */ +/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */ +#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */ +#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */ +#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */ +#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */ +#define PWM_OOV_OOVH4 (0x1u << 4) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 4 */ +#define PWM_OOV_OOVH5 (0x1u << 5) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 5 */ +#define PWM_OOV_OOVH6 (0x1u << 6) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 6 */ +#define PWM_OOV_OOVH7 (0x1u << 7) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 7 */ +#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */ +#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */ +#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */ +#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */ +#define PWM_OOV_OOVL4 (0x1u << 20) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 4 */ +#define PWM_OOV_OOVL5 (0x1u << 21) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 5 */ +#define PWM_OOV_OOVL6 (0x1u << 22) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 6 */ +#define PWM_OOV_OOVL7 (0x1u << 23) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 7 */ +/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */ +#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */ +#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */ +#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */ +#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */ +#define PWM_OS_OSH4 (0x1u << 4) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 4 */ +#define PWM_OS_OSH5 (0x1u << 5) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 5 */ +#define PWM_OS_OSH6 (0x1u << 6) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 6 */ +#define PWM_OS_OSH7 (0x1u << 7) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 7 */ +#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */ +#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */ +#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */ +#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */ +#define PWM_OS_OSL4 (0x1u << 20) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 4 */ +#define PWM_OS_OSL5 (0x1u << 21) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 5 */ +#define PWM_OS_OSL6 (0x1u << 22) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 6 */ +#define PWM_OS_OSL7 (0x1u << 23) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 7 */ +/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */ +#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */ +#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */ +#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */ +#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */ +#define PWM_OSS_OSSH4 (0x1u << 4) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 4 */ +#define PWM_OSS_OSSH5 (0x1u << 5) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 5 */ +#define PWM_OSS_OSSH6 (0x1u << 6) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 6 */ +#define PWM_OSS_OSSH7 (0x1u << 7) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 7 */ +#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */ +#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */ +#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */ +#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */ +#define PWM_OSS_OSSL4 (0x1u << 20) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 4 */ +#define PWM_OSS_OSSL5 (0x1u << 21) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 5 */ +#define PWM_OSS_OSSL6 (0x1u << 22) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 6 */ +#define PWM_OSS_OSSL7 (0x1u << 23) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 7 */ +/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */ +#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */ +#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */ +#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */ +#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */ +#define PWM_OSC_OSCH4 (0x1u << 4) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 4 */ +#define PWM_OSC_OSCH5 (0x1u << 5) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 5 */ +#define PWM_OSC_OSCH6 (0x1u << 6) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 6 */ +#define PWM_OSC_OSCH7 (0x1u << 7) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 7 */ +#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */ +#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */ +#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */ +#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */ +#define PWM_OSC_OSCL4 (0x1u << 20) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 4 */ +#define PWM_OSC_OSCL5 (0x1u << 21) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 5 */ +#define PWM_OSC_OSCL6 (0x1u << 22) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 6 */ +#define PWM_OSC_OSCL7 (0x1u << 23) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 7 */ +/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */ +#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */ +#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */ +#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */ +#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */ +#define PWM_OSSUPD_OSSUPH4 (0x1u << 4) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 4 */ +#define PWM_OSSUPD_OSSUPH5 (0x1u << 5) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 5 */ +#define PWM_OSSUPD_OSSUPH6 (0x1u << 6) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 6 */ +#define PWM_OSSUPD_OSSUPH7 (0x1u << 7) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 7 */ +#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */ +#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */ +#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */ +#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */ +#define PWM_OSSUPD_OSSUPL4 (0x1u << 20) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 4 */ +#define PWM_OSSUPD_OSSUPL5 (0x1u << 21) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 5 */ +#define PWM_OSSUPD_OSSUPL6 (0x1u << 22) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 6 */ +#define PWM_OSSUPD_OSSUPL7 (0x1u << 23) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 7 */ +/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */ +#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */ +#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */ +#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */ +#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */ +#define PWM_OSCUPD_OSCUPH4 (0x1u << 4) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 4 */ +#define PWM_OSCUPD_OSCUPH5 (0x1u << 5) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 5 */ +#define PWM_OSCUPD_OSCUPH6 (0x1u << 6) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 6 */ +#define PWM_OSCUPD_OSCUPH7 (0x1u << 7) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 7 */ +#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */ +#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */ +#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */ +#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */ +#define PWM_OSCUPD_OSCUPL4 (0x1u << 20) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 4 */ +#define PWM_OSCUPD_OSCUPL5 (0x1u << 21) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 5 */ +#define PWM_OSCUPD_OSCUPDL6 (0x1u << 22) /**< \brief (PWM_OSCUPD) */ +#define PWM_OSCUPD_OSCUPL7 (0x1u << 23) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 7 */ +/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */ +#define PWM_FMR_FPOL_Pos 0 +#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity (fault input bit varies from 0 to 5) */ +#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos))) +#define PWM_FMR_FMOD_Pos 8 +#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode (fault input bit varies from 0 to 5) */ +#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos))) +#define PWM_FMR_FFIL_Pos 16 +#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering (fault input bit varies from 0 to 5) */ +#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos))) +/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */ +#define PWM_FSR_FIV_Pos 0 +#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value (fault input bit varies from 0 to 5) */ +#define PWM_FSR_FS_Pos 8 +#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status (fault input bit varies from 0 to 5) */ +/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */ +#define PWM_FCR_FCLR_Pos 0 +#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear (fault input bit varies from 0 to 5) */ +#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos))) +/* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */ +#define PWM_FPV_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */ +#define PWM_FPV_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */ +#define PWM_FPV_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */ +#define PWM_FPV_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */ +#define PWM_FPV_FPVH4 (0x1u << 4) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 4 */ +#define PWM_FPV_FPVH5 (0x1u << 5) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 5 */ +#define PWM_FPV_FPVH6 (0x1u << 6) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 6 */ +#define PWM_FPV_FPVH7 (0x1u << 7) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 7 */ +#define PWM_FPV_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */ +#define PWM_FPV_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */ +#define PWM_FPV_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */ +#define PWM_FPV_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */ +#define PWM_FPV_FPVL4 (0x1u << 20) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 4 */ +#define PWM_FPV_FPVL5 (0x1u << 21) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 5 */ +#define PWM_FPV_FPVL6 (0x1u << 22) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 6 */ +#define PWM_FPV_FPVL7 (0x1u << 23) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 7 */ +/* -------- PWM_FPE1 : (PWM Offset: 0x6C) PWM Fault Protection Enable Register 1 -------- */ +#define PWM_FPE1_FPE0_Pos 0 +#define PWM_FPE1_FPE0_Msk (0xffu << PWM_FPE1_FPE0_Pos) /**< \brief (PWM_FPE1) Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5) */ +#define PWM_FPE1_FPE0(value) ((PWM_FPE1_FPE0_Msk & ((value) << PWM_FPE1_FPE0_Pos))) +#define PWM_FPE1_FPE1_Pos 8 +#define PWM_FPE1_FPE1_Msk (0xffu << PWM_FPE1_FPE1_Pos) /**< \brief (PWM_FPE1) Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5) */ +#define PWM_FPE1_FPE1(value) ((PWM_FPE1_FPE1_Msk & ((value) << PWM_FPE1_FPE1_Pos))) +#define PWM_FPE1_FPE2_Pos 16 +#define PWM_FPE1_FPE2_Msk (0xffu << PWM_FPE1_FPE2_Pos) /**< \brief (PWM_FPE1) Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5) */ +#define PWM_FPE1_FPE2(value) ((PWM_FPE1_FPE2_Msk & ((value) << PWM_FPE1_FPE2_Pos))) +#define PWM_FPE1_FPE3_Pos 24 +#define PWM_FPE1_FPE3_Msk (0xffu << PWM_FPE1_FPE3_Pos) /**< \brief (PWM_FPE1) Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5) */ +#define PWM_FPE1_FPE3(value) ((PWM_FPE1_FPE3_Msk & ((value) << PWM_FPE1_FPE3_Pos))) +/* -------- PWM_FPE2 : (PWM Offset: 0x70) PWM Fault Protection Enable Register 2 -------- */ +#define PWM_FPE2_FPE4_Pos 0 +#define PWM_FPE2_FPE4_Msk (0xffu << PWM_FPE2_FPE4_Pos) /**< \brief (PWM_FPE2) Fault Protection Enable for channel 4 (fault input bit varies from 0 to 5) */ +#define PWM_FPE2_FPE4(value) ((PWM_FPE2_FPE4_Msk & ((value) << PWM_FPE2_FPE4_Pos))) +#define PWM_FPE2_FPE5_Pos 8 +#define PWM_FPE2_FPE5_Msk (0xffu << PWM_FPE2_FPE5_Pos) /**< \brief (PWM_FPE2) Fault Protection Enable for channel 5 (fault input bit varies from 0 to 5) */ +#define PWM_FPE2_FPE5(value) ((PWM_FPE2_FPE5_Msk & ((value) << PWM_FPE2_FPE5_Pos))) +#define PWM_FPE2_FPE6_Pos 16 +#define PWM_FPE2_FPE6_Msk (0xffu << PWM_FPE2_FPE6_Pos) /**< \brief (PWM_FPE2) Fault Protection Enable for channel 6 (fault input bit varies from 0 to 5) */ +#define PWM_FPE2_FPE6(value) ((PWM_FPE2_FPE6_Msk & ((value) << PWM_FPE2_FPE6_Pos))) +#define PWM_FPE2_FPE7_Pos 24 +#define PWM_FPE2_FPE7_Msk (0xffu << PWM_FPE2_FPE7_Pos) /**< \brief (PWM_FPE2) Fault Protection Enable for channel 7 (fault input bit varies from 0 to 5) */ +#define PWM_FPE2_FPE7(value) ((PWM_FPE2_FPE7_Msk & ((value) << PWM_FPE2_FPE7_Pos))) +/* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */ +#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[2]) Comparison 0 Selection */ +#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[2]) Comparison 1 Selection */ +#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[2]) Comparison 2 Selection */ +#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[2]) Comparison 3 Selection */ +#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[2]) Comparison 4 Selection */ +#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[2]) Comparison 5 Selection */ +#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[2]) Comparison 6 Selection */ +#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[2]) Comparison 7 Selection */ +/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */ +#define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */ +#define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */ +#define PWM_SMMR_GCEN2 (0x1u << 2) /**< \brief (PWM_SMMR) Gray Count ENable */ +#define PWM_SMMR_GCEN3 (0x1u << 3) /**< \brief (PWM_SMMR) Gray Count ENable */ +#define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */ +#define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */ +#define PWM_SMMR_DOWN2 (0x1u << 18) /**< \brief (PWM_SMMR) DOWN Count */ +#define PWM_SMMR_DOWN3 (0x1u << 19) /**< \brief (PWM_SMMR) DOWN Count */ +/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */ +#define PWM_WPCR_WPCMD_Pos 0 +#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protect Command */ +#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos))) +#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */ +#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */ +#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */ +#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */ +#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */ +#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */ +#define PWM_WPCR_WPKEY_Pos 8 +#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protect Key */ +#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos))) +/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */ +#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */ +#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPVSRC_Pos 16 +#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */ +/* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */ +#define PWM_TPR_TXPTR_Pos 0 +#define PWM_TPR_TXPTR_Msk (0xffffffffu << PWM_TPR_TXPTR_Pos) /**< \brief (PWM_TPR) Transmit Counter Register */ +#define PWM_TPR_TXPTR(value) ((PWM_TPR_TXPTR_Msk & ((value) << PWM_TPR_TXPTR_Pos))) +/* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */ +#define PWM_TCR_TXCTR_Pos 0 +#define PWM_TCR_TXCTR_Msk (0xffffu << PWM_TCR_TXCTR_Pos) /**< \brief (PWM_TCR) Transmit Counter Register */ +#define PWM_TCR_TXCTR(value) ((PWM_TCR_TXCTR_Msk & ((value) << PWM_TCR_TXCTR_Pos))) +/* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */ +#define PWM_TNPR_TXNPTR_Pos 0 +#define PWM_TNPR_TXNPTR_Msk (0xffffffffu << PWM_TNPR_TXNPTR_Pos) /**< \brief (PWM_TNPR) Transmit Next Pointer */ +#define PWM_TNPR_TXNPTR(value) ((PWM_TNPR_TXNPTR_Msk & ((value) << PWM_TNPR_TXNPTR_Pos))) +/* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */ +#define PWM_TNCR_TXNCTR_Pos 0 +#define PWM_TNCR_TXNCTR_Msk (0xffffu << PWM_TNCR_TXNCTR_Pos) /**< \brief (PWM_TNCR) Transmit Counter Next */ +#define PWM_TNCR_TXNCTR(value) ((PWM_TNCR_TXNCTR_Msk & ((value) << PWM_TNCR_TXNCTR_Pos))) +/* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */ +#define PWM_PTCR_RXTEN (0x1u << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */ +#define PWM_PTCR_RXTDIS (0x1u << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */ +#define PWM_PTCR_TXTEN (0x1u << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */ +#define PWM_PTCR_TXTDIS (0x1u << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */ +/* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */ +#define PWM_PTSR_RXTEN (0x1u << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */ +#define PWM_PTSR_TXTEN (0x1u << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */ +/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */ +#define PWM_CMPV_CV_Pos 0 +#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */ +#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos))) +#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */ +/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */ +#define PWM_CMPVUPD_CVUPD_Pos 0 +#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */ +#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos))) +#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */ +#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */ +#define PWM_CMPM_CTR_Pos 4 +#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */ +#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos))) +#define PWM_CMPM_CPR_Pos 8 +#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */ +#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos))) +#define PWM_CMPM_CPRCNT_Pos 12 +#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */ +#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos))) +#define PWM_CMPM_CUPR_Pos 16 +#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */ +#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos))) +#define PWM_CMPM_CUPRCNT_Pos 20 +#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */ +#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos))) +/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */ +#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */ +#define PWM_CMPMUPD_CTRUPD_Pos 4 +#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */ +#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos))) +#define PWM_CMPMUPD_CPRUPD_Pos 8 +#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */ +#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos))) +#define PWM_CMPMUPD_CUPRUPD_Pos 16 +#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */ +#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos))) +/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */ +#define PWM_CMR_CPRE_Pos 0 +#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */ +#define PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Master clock */ +#define PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Master clock/2 */ +#define PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Master clock/4 */ +#define PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Master clock/8 */ +#define PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Master clock/16 */ +#define PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Master clock/32 */ +#define PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Master clock/64 */ +#define PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Master clock/128 */ +#define PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Master clock/256 */ +#define PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Master clock/512 */ +#define PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Master clock/1024 */ +#define PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */ +#define PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */ +#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */ +#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */ +#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */ +#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */ +#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */ +#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */ +/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */ +#define PWM_CDTY_CDTY_Pos 0 +#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */ +#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos))) +/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */ +#define PWM_CDTYUPD_CDTYUPD_Pos 0 +#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */ +#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos))) +/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */ +#define PWM_CPRD_CPRD_Pos 0 +#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */ +#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos))) +/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */ +#define PWM_CPRDUPD_CPRDUPD_Pos 0 +#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */ +#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos))) +/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */ +#define PWM_CCNT_CNT_Pos 0 +#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */ +/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */ +#define PWM_DT_DTH_Pos 0 +#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */ +#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos))) +#define PWM_DT_DTL_Pos 16 +#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */ +#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos))) +/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */ +#define PWM_DTUPD_DTHUPD_Pos 0 +#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */ +#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos))) +#define PWM_DTUPD_DTLUPD_Pos 16 +#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */ +#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos))) + +/*@}*/ + + +#endif /* _SAM3XA_PWM_COMPONENT_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h new file mode 100644 index 0000000..759c55a --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_rstc.h @@ -0,0 +1,88 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_RSTC_COMPONENT_ +#define _SAM3XA_RSTC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Reset Controller */ +/* ============================================================================= */ +/** \addtogroup SAM3XA_RSTC Reset Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rstc hardware registers */ +typedef struct { + WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */ + RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */ + RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */ +} Rstc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */ +#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */ +#define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */ +#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */ +#define RSTC_CR_KEY_Pos 24 +#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) Password */ +#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos))) +/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */ +#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */ +#define RSTC_SR_RSTTYP_Pos 8 +#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */ +#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */ +#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */ +/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */ +#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */ +#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */ +#define RSTC_MR_ERSTL_Pos 8 +#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */ +#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos))) +#define RSTC_MR_KEY_Pos 24 +#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Password */ +#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos))) + +/*@}*/ + + +#endif /* _SAM3XA_RSTC_COMPONENT_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h new file mode 100644 index 0000000..59e7f75 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtc.h @@ -0,0 +1,183 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_RTC_COMPONENT_ +#define _SAM3XA_RTC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Real-time Clock */ +/* ============================================================================= */ +/** \addtogroup SAM3XA_RTC Real-time Clock */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rtc hardware registers */ +typedef struct { + RwReg RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */ + RwReg RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */ + RwReg RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */ + RwReg RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */ + RwReg RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */ + RwReg RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */ + RoReg RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */ + WoReg RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */ + WoReg RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */ + WoReg RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */ + RoReg RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */ + RoReg RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */ + RoReg Reserved1[45]; + RwReg RTC_WPMR; /**< \brief (Rtc Offset: 0xE4) Write Protect Mode Register */ +} Rtc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */ +#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */ +#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */ +#define RTC_CR_TIMEVSEL_Pos 8 +#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */ +#define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */ +#define RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */ +#define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */ +#define RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */ +#define RTC_CR_CALEVSEL_Pos 16 +#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */ +#define RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */ +#define RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */ +#define RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */ +/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */ +#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */ +/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */ +#define RTC_TIMR_SEC_Pos 0 +#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */ +#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos))) +#define RTC_TIMR_MIN_Pos 8 +#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */ +#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos))) +#define RTC_TIMR_HOUR_Pos 16 +#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */ +#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos))) +#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */ +/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */ +#define RTC_CALR_CENT_Pos 0 +#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */ +#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos))) +#define RTC_CALR_YEAR_Pos 8 +#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */ +#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos))) +#define RTC_CALR_MONTH_Pos 16 +#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */ +#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos))) +#define RTC_CALR_DAY_Pos 21 +#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */ +#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos))) +#define RTC_CALR_DATE_Pos 24 +#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */ +#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos))) +/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */ +#define RTC_TIMALR_SEC_Pos 0 +#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */ +#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos))) +#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */ +#define RTC_TIMALR_MIN_Pos 8 +#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */ +#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos))) +#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */ +#define RTC_TIMALR_HOUR_Pos 16 +#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */ +#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos))) +#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */ +#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */ +/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */ +#define RTC_CALALR_MONTH_Pos 16 +#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */ +#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos))) +#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */ +#define RTC_CALALR_DATE_Pos 24 +#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */ +#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos))) +#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */ +/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */ +#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */ +#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */ +#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */ +#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */ +#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */ +/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */ +#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */ +#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */ +#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */ +#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */ +#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */ +/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */ +#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */ +#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */ +#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */ +#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */ +#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */ +/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */ +#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */ +#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */ +#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */ +#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */ +#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */ +/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */ +#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */ +#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */ +#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */ +#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */ +#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */ +/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */ +#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */ +#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */ +#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */ +#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */ +/* -------- RTC_WPMR : (RTC Offset: 0xE4) Write Protect Mode Register -------- */ +#define RTC_WPMR_WPEN (0x1u << 0) /**< \brief (RTC_WPMR) Write Protect Enable */ +#define RTC_WPMR_WPKEY_Pos 8 +#define RTC_WPMR_WPKEY_Msk (0xffffffu << RTC_WPMR_WPKEY_Pos) /**< \brief (RTC_WPMR) */ +#define RTC_WPMR_WPKEY(value) ((RTC_WPMR_WPKEY_Msk & ((value) << RTC_WPMR_WPKEY_Pos))) + +/*@}*/ + + +#endif /* _SAM3XA_RTC_COMPONENT_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h new file mode 100644 index 0000000..9cf7756 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_rtt.h @@ -0,0 +1,84 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_RTT_COMPONENT_ +#define _SAM3XA_RTT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Real-time Timer */ +/* ============================================================================= */ +/** \addtogroup SAM3XA_RTT Real-time Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rtt hardware registers */ +typedef struct { + RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */ + RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */ + RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */ + RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */ +} Rtt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */ +#define RTT_MR_RTPRES_Pos 0 +#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */ +#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos))) +#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */ +#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */ +#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */ +/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */ +#define RTT_AR_ALMV_Pos 0 +#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */ +#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos))) +/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */ +#define RTT_VR_CRTV_Pos 0 +#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */ +/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */ +#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status */ +#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Real-time Timer Increment */ + +/*@}*/ + + +#endif /* _SAM3XA_RTT_COMPONENT_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_sdramc.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_sdramc.h new file mode 100644 index 0000000..0c49363 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_sdramc.h @@ -0,0 +1,203 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_SDRAMC_COMPONENT_ +#define _SAM3XA_SDRAMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR SDRAM Controller */ +/* ============================================================================= */ +/** \addtogroup SAM3XA_SDRAMC SDRAM Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Sdramc hardware registers */ +typedef struct { + RwReg SDRAMC_MR; /**< \brief (Sdramc Offset: 0x00) SDRAMC Mode Register */ + RwReg SDRAMC_TR; /**< \brief (Sdramc Offset: 0x04) SDRAMC Refresh Timer Register */ + RwReg SDRAMC_CR; /**< \brief (Sdramc Offset: 0x08) SDRAMC Configuration Register */ + RoReg Reserved1[1]; + RwReg SDRAMC_LPR; /**< \brief (Sdramc Offset: 0x10) SDRAMC Low Power Register */ + WoReg SDRAMC_IER; /**< \brief (Sdramc Offset: 0x14) SDRAMC Interrupt Enable Register */ + WoReg SDRAMC_IDR; /**< \brief (Sdramc Offset: 0x18) SDRAMC Interrupt Disable Register */ + RoReg SDRAMC_IMR; /**< \brief (Sdramc Offset: 0x1C) SDRAMC Interrupt Mask Register */ + RoReg SDRAMC_ISR; /**< \brief (Sdramc Offset: 0x20) SDRAMC Interrupt Status Register */ + RwReg SDRAMC_MDR; /**< \brief (Sdramc Offset: 0x24) SDRAMC Memory Device Register */ + RwReg SDRAMC_CR1; /**< \brief (Sdramc Offset: 0x28) SDRAMC Configuration Register 1 */ + RwReg SDRAMC_OCMS; /**< \brief (Sdramc Offset: 0x2C) SDRAMC OCMS Register 1 */ +} Sdramc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SDRAMC_MR : (SDRAMC Offset: 0x00) SDRAMC Mode Register -------- */ +#define SDRAMC_MR_MODE_Pos 0 +#define SDRAMC_MR_MODE_Msk (0x7u << SDRAMC_MR_MODE_Pos) /**< \brief (SDRAMC_MR) SDRAMC Command Mode */ +#define SDRAMC_MR_MODE_NORMAL (0x0u << 0) /**< \brief (SDRAMC_MR) Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_NOP (0x1u << 0) /**< \brief (SDRAMC_MR) The SDRAM Controller issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_ALLBANKS_PRECHARGE (0x2u << 0) /**< \brief (SDRAMC_MR) The SDRAM Controller issues an "All Banks Precharge" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_LOAD_MODEREG (0x3u << 0) /**< \brief (SDRAMC_MR) The SDRAM Controller issues a "Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_AUTO_REFRESH (0x4u << 0) /**< \brief (SDRAMC_MR) The SDRAM Controller issues an "Auto-Refresh" Command when the SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_EXT_LOAD_MODEREG (0x5u << 0) /**< \brief (SDRAMC_MR) The SDRAM Controller issues an "Extended Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the "Extended Load Mode Register" command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low-power SDRAM devices use the bank 1. */ +#define SDRAMC_MR_MODE_DEEP_POWERDOWN (0x6u << 0) /**< \brief (SDRAMC_MR) Deep power-down mode. Enters deep power-down mode. */ +/* -------- SDRAMC_TR : (SDRAMC Offset: 0x04) SDRAMC Refresh Timer Register -------- */ +#define SDRAMC_TR_COUNT_Pos 0 +#define SDRAMC_TR_COUNT_Msk (0xfffu << SDRAMC_TR_COUNT_Pos) /**< \brief (SDRAMC_TR) SDRAMC Refresh Timer Count */ +#define SDRAMC_TR_COUNT(value) ((SDRAMC_TR_COUNT_Msk & ((value) << SDRAMC_TR_COUNT_Pos))) +/* -------- SDRAMC_CR : (SDRAMC Offset: 0x08) SDRAMC Configuration Register -------- */ +#define SDRAMC_CR_NC_Pos 0 +#define SDRAMC_CR_NC_Msk (0x3u << SDRAMC_CR_NC_Pos) /**< \brief (SDRAMC_CR) Number of Column Bits */ +#define SDRAMC_CR_NC_COL8 (0x0u << 0) /**< \brief (SDRAMC_CR) 8 column bits */ +#define SDRAMC_CR_NC_COL9 (0x1u << 0) /**< \brief (SDRAMC_CR) 9 column bits */ +#define SDRAMC_CR_NC_COL10 (0x2u << 0) /**< \brief (SDRAMC_CR) 10 column bits */ +#define SDRAMC_CR_NC_COL11 (0x3u << 0) /**< \brief (SDRAMC_CR) 11 column bits */ +#define SDRAMC_CR_NR_Pos 2 +#define SDRAMC_CR_NR_Msk (0x3u << SDRAMC_CR_NR_Pos) /**< \brief (SDRAMC_CR) Number of Row Bits */ +#define SDRAMC_CR_NR_ROW11 (0x0u << 2) /**< \brief (SDRAMC_CR) 11 row bits */ +#define SDRAMC_CR_NR_ROW12 (0x1u << 2) /**< \brief (SDRAMC_CR) 12 row bits */ +#define SDRAMC_CR_NR_ROW13 (0x2u << 2) /**< \brief (SDRAMC_CR) 13 row bits */ +#define SDRAMC_CR_NB (0x1u << 4) /**< \brief (SDRAMC_CR) Number of Banks */ +#define SDRAMC_CR_NB_BANK2 (0x0u << 4) /**< \brief (SDRAMC_CR) 2 banks */ +#define SDRAMC_CR_NB_BANK4 (0x1u << 4) /**< \brief (SDRAMC_CR) 4 banks */ +#define SDRAMC_CR_CAS_Pos 5 +#define SDRAMC_CR_CAS_Msk (0x3u << SDRAMC_CR_CAS_Pos) /**< \brief (SDRAMC_CR) CAS Latency */ +#define SDRAMC_CR_CAS_LATENCY1 (0x1u << 5) /**< \brief (SDRAMC_CR) 1 cycle CAS latency */ +#define SDRAMC_CR_CAS_LATENCY2 (0x2u << 5) /**< \brief (SDRAMC_CR) 2 cycle CAS latency */ +#define SDRAMC_CR_CAS_LATENCY3 (0x3u << 5) /**< \brief (SDRAMC_CR) 3 cycle CAS latency */ +#define SDRAMC_CR_DBW (0x1u << 7) /**< \brief (SDRAMC_CR) Data Bus Width */ +#define SDRAMC_CR_TWR_Pos 8 +#define SDRAMC_CR_TWR_Msk (0xfu << SDRAMC_CR_TWR_Pos) /**< \brief (SDRAMC_CR) Write Recovery Delay */ +#define SDRAMC_CR_TWR(value) ((SDRAMC_CR_TWR_Msk & ((value) << SDRAMC_CR_TWR_Pos))) +#define SDRAMC_CR_TRC_TRFC_Pos 12 +#define SDRAMC_CR_TRC_TRFC_Msk (0xfu << SDRAMC_CR_TRC_TRFC_Pos) /**< \brief (SDRAMC_CR) Row Cycle Delay and Row Refresh Cycle */ +#define SDRAMC_CR_TRC_TRFC(value) ((SDRAMC_CR_TRC_TRFC_Msk & ((value) << SDRAMC_CR_TRC_TRFC_Pos))) +#define SDRAMC_CR_TRP_Pos 16 +#define SDRAMC_CR_TRP_Msk (0xfu << SDRAMC_CR_TRP_Pos) /**< \brief (SDRAMC_CR) Row Precharge Delay */ +#define SDRAMC_CR_TRP(value) ((SDRAMC_CR_TRP_Msk & ((value) << SDRAMC_CR_TRP_Pos))) +#define SDRAMC_CR_TRCD_Pos 20 +#define SDRAMC_CR_TRCD_Msk (0xfu << SDRAMC_CR_TRCD_Pos) /**< \brief (SDRAMC_CR) Row to Column Delay */ +#define SDRAMC_CR_TRCD(value) ((SDRAMC_CR_TRCD_Msk & ((value) << SDRAMC_CR_TRCD_Pos))) +#define SDRAMC_CR_TRAS_Pos 24 +#define SDRAMC_CR_TRAS_Msk (0xfu << SDRAMC_CR_TRAS_Pos) /**< \brief (SDRAMC_CR) Active to Precharge Delay */ +#define SDRAMC_CR_TRAS(value) ((SDRAMC_CR_TRAS_Msk & ((value) << SDRAMC_CR_TRAS_Pos))) +#define SDRAMC_CR_TXSR_Pos 28 +#define SDRAMC_CR_TXSR_Msk (0xfu << SDRAMC_CR_TXSR_Pos) /**< \brief (SDRAMC_CR) Exit Self Refresh to Active Delay */ +#define SDRAMC_CR_TXSR(value) ((SDRAMC_CR_TXSR_Msk & ((value) << SDRAMC_CR_TXSR_Pos))) +/* -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAMC Low Power Register -------- */ +#define SDRAMC_LPR_LPCB_Pos 0 +#define SDRAMC_LPR_LPCB_Msk (0x3u << SDRAMC_LPR_LPCB_Pos) /**< \brief (SDRAMC_LPR) Low-power Configuration Bits */ +#define SDRAMC_LPR_LPCB_DISABLED (0x0u << 0) /**< \brief (SDRAMC_LPR) Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device. */ +#define SDRAMC_LPR_LPCB_SELF_REFRESH (0x1u << 0) /**< \brief (SDRAMC_LPR) The SDRAM Controller issues a Self-refresh command to the SDRAM device, the SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self Refresh Mode when accessed and enters it after the access. */ +#define SDRAMC_LPR_LPCB_POWER_DOWN (0x2u << 0) /**< \brief (SDRAMC_LPR) The SDRAM Controller issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-down Mode when accessed and enters it after the access. */ +#define SDRAMC_LPR_LPCB_DEEP_POWER_DOWN (0x3u << 0) /**< \brief (SDRAMC_LPR) The SDRAM Controller issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power SDRAM. */ +#define SDRAMC_LPR_PASR_Pos 4 +#define SDRAMC_LPR_PASR_Msk (0x7u << SDRAMC_LPR_PASR_Pos) /**< \brief (SDRAMC_LPR) Partial Array Self-refresh (only for low-power SDRAM) */ +#define SDRAMC_LPR_PASR(value) ((SDRAMC_LPR_PASR_Msk & ((value) << SDRAMC_LPR_PASR_Pos))) +#define SDRAMC_LPR_TCSR_Pos 8 +#define SDRAMC_LPR_TCSR_Msk (0x3u << SDRAMC_LPR_TCSR_Pos) /**< \brief (SDRAMC_LPR) Temperature Compensated Self-Refresh (only for low-power SDRAM) */ +#define SDRAMC_LPR_TCSR(value) ((SDRAMC_LPR_TCSR_Msk & ((value) << SDRAMC_LPR_TCSR_Pos))) +#define SDRAMC_LPR_DS_Pos 10 +#define SDRAMC_LPR_DS_Msk (0x3u << SDRAMC_LPR_DS_Pos) /**< \brief (SDRAMC_LPR) Drive Strength (only for low-power SDRAM) */ +#define SDRAMC_LPR_DS(value) ((SDRAMC_LPR_DS_Msk & ((value) << SDRAMC_LPR_DS_Pos))) +#define SDRAMC_LPR_TIMEOUT_Pos 12 +#define SDRAMC_LPR_TIMEOUT_Msk (0x3u << SDRAMC_LPR_TIMEOUT_Pos) /**< \brief (SDRAMC_LPR) Time to define when low-power mode is enable */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER (0x0u << 12) /**< \brief (SDRAMC_LPR) The SDRAM controller activates the SDRAM low-power mode immediately after the end of the last transfer. */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_64 (0x1u << 12) /**< \brief (SDRAMC_LPR) The SDRAM controller activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer. */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_128 (0x2u << 12) /**< \brief (SDRAMC_LPR) The SDRAM controller activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer. */ +/* -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAMC Interrupt Enable Register -------- */ +#define SDRAMC_IER_RES (0x1u << 0) /**< \brief (SDRAMC_IER) Refresh Error Status */ +/* -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAMC Interrupt Disable Register -------- */ +#define SDRAMC_IDR_RES (0x1u << 0) /**< \brief (SDRAMC_IDR) Refresh Error Status */ +/* -------- SDRAMC_IMR : (SDRAMC Offset: 0x1C) SDRAMC Interrupt Mask Register -------- */ +#define SDRAMC_IMR_RES (0x1u << 0) /**< \brief (SDRAMC_IMR) Refresh Error Status */ +/* -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAMC Interrupt Status Register -------- */ +#define SDRAMC_ISR_RES (0x1u << 0) /**< \brief (SDRAMC_ISR) Refresh Error Status */ +/* -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAMC Memory Device Register -------- */ +#define SDRAMC_MDR_MD_Pos 0 +#define SDRAMC_MDR_MD_Msk (0x3u << SDRAMC_MDR_MD_Pos) /**< \brief (SDRAMC_MDR) Memory Device Type */ +#define SDRAMC_MDR_MD_SDRAM (0x0u << 0) /**< \brief (SDRAMC_MDR) SDRAM */ +#define SDRAMC_MDR_MD_LPSDRAM (0x1u << 0) /**< \brief (SDRAMC_MDR) Low-power SDRAM */ +/* -------- SDRAMC_CR1 : (SDRAMC Offset: 0x28) SDRAMC Configuration Register 1 -------- */ +#define SDRAMC_CR1_NC_Pos 0 +#define SDRAMC_CR1_NC_Msk (0x3u << SDRAMC_CR1_NC_Pos) /**< \brief (SDRAMC_CR1) Number of Column Bits */ +#define SDRAMC_CR1_NC_COL8 (0x0u << 0) /**< \brief (SDRAMC_CR1) 8 column bits */ +#define SDRAMC_CR1_NC_COL9 (0x1u << 0) /**< \brief (SDRAMC_CR1) 9 column bits */ +#define SDRAMC_CR1_NC_COL10 (0x2u << 0) /**< \brief (SDRAMC_CR1) 10 column bits */ +#define SDRAMC_CR1_NC_COL11 (0x3u << 0) /**< \brief (SDRAMC_CR1) 11 column bits */ +#define SDRAMC_CR1_NR_Pos 2 +#define SDRAMC_CR1_NR_Msk (0x3u << SDRAMC_CR1_NR_Pos) /**< \brief (SDRAMC_CR1) Number of Row Bits */ +#define SDRAMC_CR1_NR_ROW11 (0x0u << 2) /**< \brief (SDRAMC_CR1) 11 row bits */ +#define SDRAMC_CR1_NR_ROW12 (0x1u << 2) /**< \brief (SDRAMC_CR1) 12 row bits */ +#define SDRAMC_CR1_NR_ROW13 (0x2u << 2) /**< \brief (SDRAMC_CR1) 13 row bits */ +#define SDRAMC_CR1_NB (0x1u << 4) /**< \brief (SDRAMC_CR1) Number of Banks */ +#define SDRAMC_CR1_NB_BANK2 (0x0u << 4) /**< \brief (SDRAMC_CR1) 2 banks */ +#define SDRAMC_CR1_NB_BANK4 (0x1u << 4) /**< \brief (SDRAMC_CR1) 4 banks */ +#define SDRAMC_CR1_CAS_Pos 5 +#define SDRAMC_CR1_CAS_Msk (0x3u << SDRAMC_CR1_CAS_Pos) /**< \brief (SDRAMC_CR1) CAS Latency */ +#define SDRAMC_CR1_CAS_LATENCY1 (0x1u << 5) /**< \brief (SDRAMC_CR1) 1 cycle CAS latency */ +#define SDRAMC_CR1_CAS_LATENCY2 (0x2u << 5) /**< \brief (SDRAMC_CR1) 2 cycle CAS latency */ +#define SDRAMC_CR1_CAS_LATENCY3 (0x3u << 5) /**< \brief (SDRAMC_CR1) 3 cycle CAS latency */ +#define SDRAMC_CR1_DBW (0x1u << 7) /**< \brief (SDRAMC_CR1) Data Bus Width */ +#define SDRAMC_CR1_TWR_Pos 8 +#define SDRAMC_CR1_TWR_Msk (0xfu << SDRAMC_CR1_TWR_Pos) /**< \brief (SDRAMC_CR1) Write Recovery Delay */ +#define SDRAMC_CR1_TWR(value) ((SDRAMC_CR1_TWR_Msk & ((value) << SDRAMC_CR1_TWR_Pos))) +#define SDRAMC_CR1_TRC_TRFC_Pos 12 +#define SDRAMC_CR1_TRC_TRFC_Msk (0xfu << SDRAMC_CR1_TRC_TRFC_Pos) /**< \brief (SDRAMC_CR1) Row Cycle Delay and Row Refresh Cycle */ +#define SDRAMC_CR1_TRC_TRFC(value) ((SDRAMC_CR1_TRC_TRFC_Msk & ((value) << SDRAMC_CR1_TRC_TRFC_Pos))) +#define SDRAMC_CR1_TRP_Pos 16 +#define SDRAMC_CR1_TRP_Msk (0xfu << SDRAMC_CR1_TRP_Pos) /**< \brief (SDRAMC_CR1) Row Precharge Delay */ +#define SDRAMC_CR1_TRP(value) ((SDRAMC_CR1_TRP_Msk & ((value) << SDRAMC_CR1_TRP_Pos))) +#define SDRAMC_CR1_TRCD_Pos 20 +#define SDRAMC_CR1_TRCD_Msk (0xfu << SDRAMC_CR1_TRCD_Pos) /**< \brief (SDRAMC_CR1) Row to Column Delay */ +#define SDRAMC_CR1_TRCD(value) ((SDRAMC_CR1_TRCD_Msk & ((value) << SDRAMC_CR1_TRCD_Pos))) +#define SDRAMC_CR1_TRAS_Pos 24 +#define SDRAMC_CR1_TRAS_Msk (0xfu << SDRAMC_CR1_TRAS_Pos) /**< \brief (SDRAMC_CR1) Active to Precharge Delay */ +#define SDRAMC_CR1_TRAS(value) ((SDRAMC_CR1_TRAS_Msk & ((value) << SDRAMC_CR1_TRAS_Pos))) +#define SDRAMC_CR1_TXSR_Pos 28 +#define SDRAMC_CR1_TXSR_Msk (0xfu << SDRAMC_CR1_TXSR_Pos) /**< \brief (SDRAMC_CR1) Exit Self Refresh to Active Delay */ +#define SDRAMC_CR1_TXSR(value) ((SDRAMC_CR1_TXSR_Msk & ((value) << SDRAMC_CR1_TXSR_Pos))) +/* -------- SDRAMC_OCMS : (SDRAMC Offset: 0x2C) SDRAMC OCMS Register 1 -------- */ +#define SDRAMC_OCMS_SDR_SE (0x1u << 0) /**< \brief (SDRAMC_OCMS) SDRAM Memory Controller Scrambling Enable */ + +/*@}*/ + + +#endif /* _SAM3XA_SDRAMC_COMPONENT_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h new file mode 100644 index 0000000..2c00f17 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_smc.h @@ -0,0 +1,499 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_SMC_COMPONENT_ +#define _SAM3XA_SMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Static Memory Controller */ +/* ============================================================================= */ +/** \addtogroup SAM3XA_SMC Static Memory Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief SmcCs_number hardware registers */ +typedef struct { + RwReg SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */ + RwReg SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */ + RwReg SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */ + RwReg SMC_TIMINGS; /**< \brief (SmcCs_number Offset: 0xC) SMC Timings Register */ + RwReg SMC_MODE; /**< \brief (SmcCs_number Offset: 0x10) SMC Mode Register */ +} SmcCs_number; +/** \brief Smc hardware registers */ +#define SMCCS_NUMBER_NUMBER 8 +typedef struct { + RwReg SMC_CFG; /**< \brief (Smc Offset: 0x000) SMC NFC Configuration Register */ + WoReg SMC_CTRL; /**< \brief (Smc Offset: 0x004) SMC NFC Control Register */ + RoReg SMC_SR; /**< \brief (Smc Offset: 0x008) SMC NFC Status Register */ + WoReg SMC_IER; /**< \brief (Smc Offset: 0x00C) SMC NFC Interrupt Enable Register */ + WoReg SMC_IDR; /**< \brief (Smc Offset: 0x010) SMC NFC Interrupt Disable Register */ + RoReg SMC_IMR; /**< \brief (Smc Offset: 0x014) SMC NFC Interrupt Mask Register */ + RwReg SMC_ADDR; /**< \brief (Smc Offset: 0x018) SMC NFC Address Cycle Zero Register */ + RwReg SMC_BANK; /**< \brief (Smc Offset: 0x01C) SMC Bank Address Register */ + WoReg SMC_ECC_CTRL; /**< \brief (Smc Offset: 0x020) SMC ECC Control Register */ + RwReg SMC_ECC_MD; /**< \brief (Smc Offset: 0x024) SMC ECC Mode Register */ + RoReg SMC_ECC_SR1; /**< \brief (Smc Offset: 0x028) SMC ECC Status 1 Register */ + RoReg SMC_ECC_PR0; /**< \brief (Smc Offset: 0x02C) SMC ECC Parity 0 Register */ + RoReg SMC_ECC_PR1; /**< \brief (Smc Offset: 0x030) SMC ECC parity 1 Register */ + RoReg SMC_ECC_SR2; /**< \brief (Smc Offset: 0x034) SMC ECC status 2 Register */ + RoReg SMC_ECC_PR2; /**< \brief (Smc Offset: 0x038) SMC ECC parity 2 Register */ + RoReg SMC_ECC_PR3; /**< \brief (Smc Offset: 0x03C) SMC ECC parity 3 Register */ + RoReg SMC_ECC_PR4; /**< \brief (Smc Offset: 0x040) SMC ECC parity 4 Register */ + RoReg SMC_ECC_PR5; /**< \brief (Smc Offset: 0x044) SMC ECC parity 5 Register */ + RoReg SMC_ECC_PR6; /**< \brief (Smc Offset: 0x048) SMC ECC parity 6 Register */ + RoReg SMC_ECC_PR7; /**< \brief (Smc Offset: 0x04C) SMC ECC parity 7 Register */ + RoReg SMC_ECC_PR8; /**< \brief (Smc Offset: 0x050) SMC ECC parity 8 Register */ + RoReg SMC_ECC_PR9; /**< \brief (Smc Offset: 0x054) SMC ECC parity 9 Register */ + RoReg SMC_ECC_PR10; /**< \brief (Smc Offset: 0x058) SMC ECC parity 10 Register */ + RoReg SMC_ECC_PR11; /**< \brief (Smc Offset: 0x05C) SMC ECC parity 11 Register */ + RoReg SMC_ECC_PR12; /**< \brief (Smc Offset: 0x060) SMC ECC parity 12 Register */ + RoReg SMC_ECC_PR13; /**< \brief (Smc Offset: 0x064) SMC ECC parity 13 Register */ + RoReg SMC_ECC_PR14; /**< \brief (Smc Offset: 0x068) SMC ECC parity 14 Register */ + RoReg SMC_ECC_PR15; /**< \brief (Smc Offset: 0x06C) SMC ECC parity 15 Register */ + SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x70) CS_number = 0 .. 7 */ + RwReg SMC_OCMS; /**< \brief (Smc Offset: 0x110) SMC OCMS Register */ + WoReg SMC_KEY1; /**< \brief (Smc Offset: 0x114) SMC OCMS KEY1 Register */ + WoReg SMC_KEY2; /**< \brief (Smc Offset: 0x118) SMC OCMS KEY2 Register */ + RoReg Reserved1[50]; + WoReg SMC_WPCR; /**< \brief (Smc Offset: 0x1E4) Write Protection Control Register */ + RoReg SMC_WPSR; /**< \brief (Smc Offset: 0x1E8) Write Protection Status Register */ +} Smc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SMC_CFG : (SMC Offset: 0x000) SMC NFC Configuration Register -------- */ +#define SMC_CFG_PAGESIZE_Pos 0 +#define SMC_CFG_PAGESIZE_Msk (0x3u << SMC_CFG_PAGESIZE_Pos) /**< \brief (SMC_CFG) */ +#define SMC_CFG_PAGESIZE_PS512_16 (0x0u << 0) /**< \brief (SMC_CFG) Main area 512 Bytes + Spare area 16 Bytes = 528 Bytes */ +#define SMC_CFG_PAGESIZE_PS1024_32 (0x1u << 0) /**< \brief (SMC_CFG) Main area 1024 Bytes + Spare area 32 Bytes = 1056 Bytes */ +#define SMC_CFG_PAGESIZE_PS2048_64 (0x2u << 0) /**< \brief (SMC_CFG) Main area 2048 Bytes + Spare area 64 Bytes = 2112 Bytes */ +#define SMC_CFG_PAGESIZE_PS4096_128 (0x3u << 0) /**< \brief (SMC_CFG) Main area 4096 Bytes + Spare area 128 Bytes = 4224 Bytes */ +#define SMC_CFG_WSPARE (0x1u << 8) /**< \brief (SMC_CFG) Write Spare Area */ +#define SMC_CFG_RSPARE (0x1u << 9) /**< \brief (SMC_CFG) Read Spare Area */ +#define SMC_CFG_EDGECTRL (0x1u << 12) /**< \brief (SMC_CFG) Rising/Falling Edge Detection Control */ +#define SMC_CFG_RBEDGE (0x1u << 13) /**< \brief (SMC_CFG) Ready/Busy Signal Edge Detection */ +#define SMC_CFG_DTOCYC_Pos 16 +#define SMC_CFG_DTOCYC_Msk (0xfu << SMC_CFG_DTOCYC_Pos) /**< \brief (SMC_CFG) Data Timeout Cycle Number */ +#define SMC_CFG_DTOCYC(value) ((SMC_CFG_DTOCYC_Msk & ((value) << SMC_CFG_DTOCYC_Pos))) +#define SMC_CFG_DTOMUL_Pos 20 +#define SMC_CFG_DTOMUL_Msk (0x7u << SMC_CFG_DTOMUL_Pos) /**< \brief (SMC_CFG) Data Timeout Multiplier */ +#define SMC_CFG_DTOMUL_X1 (0x0u << 20) /**< \brief (SMC_CFG) DTOCYC */ +#define SMC_CFG_DTOMUL_X16 (0x1u << 20) /**< \brief (SMC_CFG) DTOCYC x 16 */ +#define SMC_CFG_DTOMUL_X128 (0x2u << 20) /**< \brief (SMC_CFG) DTOCYC x 128 */ +#define SMC_CFG_DTOMUL_X256 (0x3u << 20) /**< \brief (SMC_CFG) DTOCYC x 256 */ +#define SMC_CFG_DTOMUL_X1024 (0x4u << 20) /**< \brief (SMC_CFG) DTOCYC x 1024 */ +#define SMC_CFG_DTOMUL_X4096 (0x5u << 20) /**< \brief (SMC_CFG) DTOCYC x 4096 */ +#define SMC_CFG_DTOMUL_X65536 (0x6u << 20) /**< \brief (SMC_CFG) DTOCYC x 65536 */ +#define SMC_CFG_DTOMUL_X1048576 (0x7u << 20) /**< \brief (SMC_CFG) DTOCYC x 1048576 */ +/* -------- SMC_CTRL : (SMC Offset: 0x004) SMC NFC Control Register -------- */ +#define SMC_CTRL_NFCEN (0x1u << 0) /**< \brief (SMC_CTRL) NAND Flash Controller Enable */ +#define SMC_CTRL_NFCDIS (0x1u << 1) /**< \brief (SMC_CTRL) NAND Flash Controller Disable */ +/* -------- SMC_SR : (SMC Offset: 0x008) SMC NFC Status Register -------- */ +#define SMC_SR_SMCSTS (0x1u << 0) /**< \brief (SMC_SR) NAND Flash Controller status (this field cannot be reset) */ +#define SMC_SR_RB_RISE (0x1u << 4) /**< \brief (SMC_SR) Selected Ready Busy Rising Edge Detected */ +#define SMC_SR_RB_FALL (0x1u << 5) /**< \brief (SMC_SR) Selected Ready Busy Falling Edge Detected */ +#define SMC_SR_NFCBUSY (0x1u << 8) /**< \brief (SMC_SR) NFC Busy (this field cannot be reset) */ +#define SMC_SR_NFCWR (0x1u << 11) /**< \brief (SMC_SR) NFC Write/Read Operation (this field cannot be reset) */ +#define SMC_SR_NFCSID_Pos 12 +#define SMC_SR_NFCSID_Msk (0x7u << SMC_SR_NFCSID_Pos) /**< \brief (SMC_SR) NFC Chip Select ID (this field cannot be reset) */ +#define SMC_SR_XFRDONE (0x1u << 16) /**< \brief (SMC_SR) NFC Data Transfer Terminated */ +#define SMC_SR_CMDDONE (0x1u << 17) /**< \brief (SMC_SR) Command Done */ +#define SMC_SR_DTOE (0x1u << 20) /**< \brief (SMC_SR) Data Timeout Error */ +#define SMC_SR_UNDEF (0x1u << 21) /**< \brief (SMC_SR) Undefined Area Error */ +#define SMC_SR_AWB (0x1u << 22) /**< \brief (SMC_SR) Accessing While Busy */ +#define SMC_SR_NFCASE (0x1u << 23) /**< \brief (SMC_SR) NFC Access Size Error */ +#define SMC_SR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_SR) Ready/Busy Line 0 Edge Detected */ +/* -------- SMC_IER : (SMC Offset: 0x00C) SMC NFC Interrupt Enable Register -------- */ +#define SMC_IER_RB_RISE (0x1u << 4) /**< \brief (SMC_IER) Ready Busy Rising Edge Detection Interrupt Enable */ +#define SMC_IER_RB_FALL (0x1u << 5) /**< \brief (SMC_IER) Ready Busy Falling Edge Detection Interrupt Enable */ +#define SMC_IER_XFRDONE (0x1u << 16) /**< \brief (SMC_IER) Transfer Done Interrupt Enable */ +#define SMC_IER_CMDDONE (0x1u << 17) /**< \brief (SMC_IER) Command Done Interrupt Enable */ +#define SMC_IER_DTOE (0x1u << 20) /**< \brief (SMC_IER) Data Timeout Error Interrupt Enable */ +#define SMC_IER_UNDEF (0x1u << 21) /**< \brief (SMC_IER) Undefined Area Access Interrupt Enable */ +#define SMC_IER_AWB (0x1u << 22) /**< \brief (SMC_IER) Accessing While Busy Interrupt Enable */ +#define SMC_IER_NFCASE (0x1u << 23) /**< \brief (SMC_IER) NFC Access Size Error Interrupt Enable */ +#define SMC_IER_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IER) Ready/Busy Line 0 Interrupt Enable */ +/* -------- SMC_IDR : (SMC Offset: 0x010) SMC NFC Interrupt Disable Register -------- */ +#define SMC_IDR_RB_RISE (0x1u << 4) /**< \brief (SMC_IDR) Ready Busy Rising Edge Detection Interrupt Disable */ +#define SMC_IDR_RB_FALL (0x1u << 5) /**< \brief (SMC_IDR) Ready Busy Falling Edge Detection Interrupt Disable */ +#define SMC_IDR_XFRDONE (0x1u << 16) /**< \brief (SMC_IDR) Transfer Done Interrupt Disable */ +#define SMC_IDR_CMDDONE (0x1u << 17) /**< \brief (SMC_IDR) Command Done Interrupt Disable */ +#define SMC_IDR_DTOE (0x1u << 20) /**< \brief (SMC_IDR) Data Timeout Error Interrupt Disable */ +#define SMC_IDR_UNDEF (0x1u << 21) /**< \brief (SMC_IDR) Undefined Area Access Interrupt Disable */ +#define SMC_IDR_AWB (0x1u << 22) /**< \brief (SMC_IDR) Accessing While Busy Interrupt Disable */ +#define SMC_IDR_NFCASE (0x1u << 23) /**< \brief (SMC_IDR) NFC Access Size Error Interrupt Disable */ +#define SMC_IDR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IDR) Ready/Busy Line 0 Interrupt Disable */ +/* -------- SMC_IMR : (SMC Offset: 0x014) SMC NFC Interrupt Mask Register -------- */ +#define SMC_IMR_RB_RISE (0x1u << 4) /**< \brief (SMC_IMR) Ready Busy Rising Edge Detection Interrupt Mask */ +#define SMC_IMR_RB_FALL (0x1u << 5) /**< \brief (SMC_IMR) Ready Busy Falling Edge Detection Interrupt Mask */ +#define SMC_IMR_XFRDONE (0x1u << 16) /**< \brief (SMC_IMR) Transfer Done Interrupt Mask */ +#define SMC_IMR_CMDDONE (0x1u << 17) /**< \brief (SMC_IMR) Command Done Interrupt Mask */ +#define SMC_IMR_DTOE (0x1u << 20) /**< \brief (SMC_IMR) Data Timeout Error Interrupt Mask */ +#define SMC_IMR_UNDEF (0x1u << 21) /**< \brief (SMC_IMR) Undefined Area Access Interrupt Mask5 */ +#define SMC_IMR_AWB (0x1u << 22) /**< \brief (SMC_IMR) Accessing While Busy Interrupt Mask */ +#define SMC_IMR_NFCASE (0x1u << 23) /**< \brief (SMC_IMR) NFC Access Size Error Interrupt Mask */ +#define SMC_IMR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IMR) Ready/Busy Line 0 Interrupt Mask */ +/* -------- SMC_ADDR : (SMC Offset: 0x018) SMC NFC Address Cycle Zero Register -------- */ +#define SMC_ADDR_ADDR_CYCLE0_Pos 0 +#define SMC_ADDR_ADDR_CYCLE0_Msk (0xffu << SMC_ADDR_ADDR_CYCLE0_Pos) /**< \brief (SMC_ADDR) NAND Flash Array Address cycle 0 */ +#define SMC_ADDR_ADDR_CYCLE0(value) ((SMC_ADDR_ADDR_CYCLE0_Msk & ((value) << SMC_ADDR_ADDR_CYCLE0_Pos))) +/* -------- SMC_BANK : (SMC Offset: 0x01C) SMC Bank Address Register -------- */ +#define SMC_BANK_BANK_Pos 0 +#define SMC_BANK_BANK_Msk (0x7u << SMC_BANK_BANK_Pos) /**< \brief (SMC_BANK) Bank Identifier */ +#define SMC_BANK_BANK(value) ((SMC_BANK_BANK_Msk & ((value) << SMC_BANK_BANK_Pos))) +/* -------- SMC_ECC_CTRL : (SMC Offset: 0x020) SMC ECC Control Register -------- */ +#define SMC_ECC_CTRL_RST (0x1u << 0) /**< \brief (SMC_ECC_CTRL) Reset ECC */ +#define SMC_ECC_CTRL_SWRST (0x1u << 1) /**< \brief (SMC_ECC_CTRL) Software Reset */ +/* -------- SMC_ECC_MD : (SMC Offset: 0x024) SMC ECC Mode Register -------- */ +#define SMC_ECC_MD_ECC_PAGESIZE_Pos 0 +#define SMC_ECC_MD_ECC_PAGESIZE_Msk (0x3u << SMC_ECC_MD_ECC_PAGESIZE_Pos) /**< \brief (SMC_ECC_MD) ECC Page Size */ +#define SMC_ECC_MD_ECC_PAGESIZE_PS512_16 (0x0u << 0) /**< \brief (SMC_ECC_MD) Main area 512 Bytes + Spare area 16 Bytes = 528 Bytes */ +#define SMC_ECC_MD_ECC_PAGESIZE_PS1024_32 (0x1u << 0) /**< \brief (SMC_ECC_MD) Main area 1024 Bytes + Spare area 32 Bytes = 1056 Bytes */ +#define SMC_ECC_MD_ECC_PAGESIZE_PS2048_64 (0x2u << 0) /**< \brief (SMC_ECC_MD) Main area 2048 Bytes + Spare area 64 Bytes = 2112 Bytes */ +#define SMC_ECC_MD_ECC_PAGESIZE_PS4096_128 (0x3u << 0) /**< \brief (SMC_ECC_MD) Main area 4096 Bytes + Spare area 128 Bytes = 4224 Bytes */ +#define SMC_ECC_MD_TYPCORREC_Pos 4 +#define SMC_ECC_MD_TYPCORREC_Msk (0x3u << SMC_ECC_MD_TYPCORREC_Pos) /**< \brief (SMC_ECC_MD) Type of Correction */ +#define SMC_ECC_MD_TYPCORREC_CPAGE (0x0u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for a page of 512/1024/2048/4096 Bytes (for 8 or 16-bit NAND Flash) */ +#define SMC_ECC_MD_TYPCORREC_C256B (0x1u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for 256 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only) */ +#define SMC_ECC_MD_TYPCORREC_C512B (0x2u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for 512 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only) */ +/* -------- SMC_ECC_SR1 : (SMC Offset: 0x028) SMC ECC Status 1 Register -------- */ +#define SMC_ECC_SR1_RECERR0 (0x1u << 0) /**< \brief (SMC_ECC_SR1) Recoverable Error */ +#define SMC_ECC_SR1_ECCERR0_Pos 1 +#define SMC_ECC_SR1_ECCERR0_Msk (0x3u << SMC_ECC_SR1_ECCERR0_Pos) /**< \brief (SMC_ECC_SR1) ECC Error */ +#define SMC_ECC_SR1_RECERR1 (0x1u << 4) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 256th and the 511th bytes or the 512nd and the 1023rd bytes */ +#define SMC_ECC_SR1_ECCERR1 (0x1u << 5) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes */ +#define SMC_ECC_SR1_MULERR1 (0x1u << 6) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes */ +#define SMC_ECC_SR1_RECERR2 (0x1u << 8) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */ +#define SMC_ECC_SR1_ECCERR2 (0x1u << 9) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */ +#define SMC_ECC_SR1_MULERR2 (0x1u << 10) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */ +#define SMC_ECC_SR1_RECERR3 (0x1u << 12) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */ +#define SMC_ECC_SR1_ECCERR3 (0x1u << 13) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */ +#define SMC_ECC_SR1_MULERR3 (0x1u << 14) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */ +#define SMC_ECC_SR1_RECERR4 (0x1u << 16) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes */ +#define SMC_ECC_SR1_ECCERR4_Pos 17 +#define SMC_ECC_SR1_ECCERR4_Msk (0x3u << SMC_ECC_SR1_ECCERR4_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes */ +#define SMC_ECC_SR1_RECERR5 (0x1u << 20) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes */ +#define SMC_ECC_SR1_ECCERR5_Pos 21 +#define SMC_ECC_SR1_ECCERR5_Msk (0x3u << SMC_ECC_SR1_ECCERR5_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes */ +#define SMC_ECC_SR1_RECERR6 (0x1u << 24) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes */ +#define SMC_ECC_SR1_ECCERR6_Pos 25 +#define SMC_ECC_SR1_ECCERR6_Msk (0x3u << SMC_ECC_SR1_ECCERR6_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes */ +#define SMC_ECC_SR1_RECERR7 (0x1u << 28) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes */ +#define SMC_ECC_SR1_ECCERR7_Pos 29 +#define SMC_ECC_SR1_ECCERR7_Msk (0x3u << SMC_ECC_SR1_ECCERR7_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes */ +/* -------- SMC_ECC_PR0 : (SMC Offset: 0x02C) SMC ECC Parity 0 Register -------- */ +#define SMC_ECC_PR0_BITADDR_Pos 0 +#define SMC_ECC_PR0_BITADDR_Msk (0xfu << SMC_ECC_PR0_BITADDR_Pos) /**< \brief (SMC_ECC_PR0) Bit Address */ +#define SMC_ECC_PR0_WORDADDR_Pos 4 +#define SMC_ECC_PR0_WORDADDR_Msk (0xfffu << SMC_ECC_PR0_WORDADDR_Pos) /**< \brief (SMC_ECC_PR0) Word Address */ +#define SMC_ECC_PR0_BITADDR_W9BIT_Pos 0 +#define SMC_ECC_PR0_BITADDR_W9BIT_Msk (0x7u << SMC_ECC_PR0_BITADDR_W9BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR0_WORDADDR_W9BIT_Pos 3 +#define SMC_ECC_PR0_WORDADDR_W9BIT_Msk (0x1ffu << SMC_ECC_PR0_WORDADDR_W9BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR0_NPARITY_Pos 12 +#define SMC_ECC_PR0_NPARITY_Msk (0xfffu << SMC_ECC_PR0_NPARITY_Pos) /**< \brief (SMC_ECC_PR0) Parity N */ +#define SMC_ECC_PR0_BITADDR_W8BIT_Pos 0 +#define SMC_ECC_PR0_BITADDR_W8BIT_Msk (0x7u << SMC_ECC_PR0_BITADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR0_WORDADDR_W8BIT_Pos 3 +#define SMC_ECC_PR0_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR0_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR0_NPARITY_W8BIT_Pos 12 +#define SMC_ECC_PR0_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR0_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Parity N */ +/* -------- SMC_ECC_PR1 : (SMC Offset: 0x030) SMC ECC parity 1 Register -------- */ +#define SMC_ECC_PR1_NPARITY_Pos 0 +#define SMC_ECC_PR1_NPARITY_Msk (0xffffu << SMC_ECC_PR1_NPARITY_Pos) /**< \brief (SMC_ECC_PR1) Parity N */ +#define SMC_ECC_PR1_BITADDR_Pos 0 +#define SMC_ECC_PR1_BITADDR_Msk (0x7u << SMC_ECC_PR1_BITADDR_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR1_WORDADDR_Pos 3 +#define SMC_ECC_PR1_WORDADDR_Msk (0x1ffu << SMC_ECC_PR1_WORDADDR_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR1_NPARITY_W9BIT_Pos 12 +#define SMC_ECC_PR1_NPARITY_W9BIT_Msk (0xfffu << SMC_ECC_PR1_NPARITY_W9BIT_Pos) /**< \brief (SMC_ECC_PR1) Parity N */ +#define SMC_ECC_PR1_WORDADDR_W8BIT_Pos 3 +#define SMC_ECC_PR1_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR1_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR1_NPARITY_W8BIT_Pos 12 +#define SMC_ECC_PR1_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR1_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR1) Parity N */ +/* -------- SMC_ECC_SR2 : (SMC Offset: 0x034) SMC ECC status 2 Register -------- */ +#define SMC_ECC_SR2_RECERR8 (0x1u << 0) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2048th and the 2303rd bytes */ +#define SMC_ECC_SR2_ECCERR8_Pos 1 +#define SMC_ECC_SR2_ECCERR8_Msk (0x3u << SMC_ECC_SR2_ECCERR8_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2048th and the 2303rd bytes */ +#define SMC_ECC_SR2_RECERR9 (0x1u << 4) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2304th and the 2559th bytes */ +#define SMC_ECC_SR2_ECCERR9 (0x1u << 5) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2304th and the 2559th bytes */ +#define SMC_ECC_SR2_MULERR9 (0x1u << 6) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2304th and the 2559th bytes */ +#define SMC_ECC_SR2_RECERR10 (0x1u << 8) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2560th and the 2815th bytes */ +#define SMC_ECC_SR2_ECCERR10 (0x1u << 9) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2560th and the 2815th bytes */ +#define SMC_ECC_SR2_MULERR10 (0x1u << 10) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2560th and the 2815th bytes */ +#define SMC_ECC_SR2_RECERR11 (0x1u << 12) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2816th and the 3071st bytes */ +#define SMC_ECC_SR2_ECCERR11 (0x1u << 13) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2816th and the 3071st bytes */ +#define SMC_ECC_SR2_MULERR11 (0x1u << 14) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2816th and the 3071st bytes */ +#define SMC_ECC_SR2_RECERR12 (0x1u << 16) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3072nd and the 3327th bytes */ +#define SMC_ECC_SR2_ECCERR12_Pos 17 +#define SMC_ECC_SR2_ECCERR12_Msk (0x3u << SMC_ECC_SR2_ECCERR12_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3072nd and the 3327th bytes */ +#define SMC_ECC_SR2_RECERR13 (0x1u << 20) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3328th and the 3583rd bytes */ +#define SMC_ECC_SR2_ECCERR13_Pos 21 +#define SMC_ECC_SR2_ECCERR13_Msk (0x3u << SMC_ECC_SR2_ECCERR13_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3328th and the 3583rd bytes */ +#define SMC_ECC_SR2_RECERR14 (0x1u << 24) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3584th and the 3839th bytes */ +#define SMC_ECC_SR2_ECCERR14_Pos 25 +#define SMC_ECC_SR2_ECCERR14_Msk (0x3u << SMC_ECC_SR2_ECCERR14_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3584th and the 3839th bytes */ +#define SMC_ECC_SR2_RECERR15 (0x1u << 28) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3840th and the 4095th bytes */ +#define SMC_ECC_SR2_ECCERR15_Pos 29 +#define SMC_ECC_SR2_ECCERR15_Msk (0x3u << SMC_ECC_SR2_ECCERR15_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3840th and the 4095th bytes */ +/* -------- SMC_ECC_PR2 : (SMC Offset: 0x038) SMC ECC parity 2 Register -------- */ +#define SMC_ECC_PR2_BITADDR_Pos 0 +#define SMC_ECC_PR2_BITADDR_Msk (0x7u << SMC_ECC_PR2_BITADDR_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR2_WORDADDR_Pos 3 +#define SMC_ECC_PR2_WORDADDR_Msk (0x1ffu << SMC_ECC_PR2_WORDADDR_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR2_NPARITY_Pos 12 +#define SMC_ECC_PR2_NPARITY_Msk (0xfffu << SMC_ECC_PR2_NPARITY_Pos) /**< \brief (SMC_ECC_PR2) Parity N */ +#define SMC_ECC_PR2_WORDADDR_W8BIT_Pos 3 +#define SMC_ECC_PR2_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR2_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR2_NPARITY_W8BIT_Pos 12 +#define SMC_ECC_PR2_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR2_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR2) Parity N */ +/* -------- SMC_ECC_PR3 : (SMC Offset: 0x03C) SMC ECC parity 3 Register -------- */ +#define SMC_ECC_PR3_BITADDR_Pos 0 +#define SMC_ECC_PR3_BITADDR_Msk (0x7u << SMC_ECC_PR3_BITADDR_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR3_WORDADDR_Pos 3 +#define SMC_ECC_PR3_WORDADDR_Msk (0x1ffu << SMC_ECC_PR3_WORDADDR_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR3_NPARITY_Pos 12 +#define SMC_ECC_PR3_NPARITY_Msk (0xfffu << SMC_ECC_PR3_NPARITY_Pos) /**< \brief (SMC_ECC_PR3) Parity N */ +#define SMC_ECC_PR3_WORDADDR_W8BIT_Pos 3 +#define SMC_ECC_PR3_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR3_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR3_NPARITY_W8BIT_Pos 12 +#define SMC_ECC_PR3_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR3_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR3) Parity N */ +/* -------- SMC_ECC_PR4 : (SMC Offset: 0x040) SMC ECC parity 4 Register -------- */ +#define SMC_ECC_PR4_BITADDR_Pos 0 +#define SMC_ECC_PR4_BITADDR_Msk (0x7u << SMC_ECC_PR4_BITADDR_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR4_WORDADDR_Pos 3 +#define SMC_ECC_PR4_WORDADDR_Msk (0x1ffu << SMC_ECC_PR4_WORDADDR_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR4_NPARITY_Pos 12 +#define SMC_ECC_PR4_NPARITY_Msk (0xfffu << SMC_ECC_PR4_NPARITY_Pos) /**< \brief (SMC_ECC_PR4) Parity N */ +#define SMC_ECC_PR4_WORDADDR_W8BIT_Pos 3 +#define SMC_ECC_PR4_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR4_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR4_NPARITY_W8BIT_Pos 12 +#define SMC_ECC_PR4_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR4_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR4) Parity N */ +/* -------- SMC_ECC_PR5 : (SMC Offset: 0x044) SMC ECC parity 5 Register -------- */ +#define SMC_ECC_PR5_BITADDR_Pos 0 +#define SMC_ECC_PR5_BITADDR_Msk (0x7u << SMC_ECC_PR5_BITADDR_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR5_WORDADDR_Pos 3 +#define SMC_ECC_PR5_WORDADDR_Msk (0x1ffu << SMC_ECC_PR5_WORDADDR_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR5_NPARITY_Pos 12 +#define SMC_ECC_PR5_NPARITY_Msk (0xfffu << SMC_ECC_PR5_NPARITY_Pos) /**< \brief (SMC_ECC_PR5) Parity N */ +#define SMC_ECC_PR5_WORDADDR_W8BIT_Pos 3 +#define SMC_ECC_PR5_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR5_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR5_NPARITY_W8BIT_Pos 12 +#define SMC_ECC_PR5_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR5_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR5) Parity N */ +/* -------- SMC_ECC_PR6 : (SMC Offset: 0x048) SMC ECC parity 6 Register -------- */ +#define SMC_ECC_PR6_BITADDR_Pos 0 +#define SMC_ECC_PR6_BITADDR_Msk (0x7u << SMC_ECC_PR6_BITADDR_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR6_WORDADDR_Pos 3 +#define SMC_ECC_PR6_WORDADDR_Msk (0x1ffu << SMC_ECC_PR6_WORDADDR_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR6_NPARITY_Pos 12 +#define SMC_ECC_PR6_NPARITY_Msk (0xfffu << SMC_ECC_PR6_NPARITY_Pos) /**< \brief (SMC_ECC_PR6) Parity N */ +#define SMC_ECC_PR6_WORDADDR_W8BIT_Pos 3 +#define SMC_ECC_PR6_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR6_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR6_NPARITY_W8BIT_Pos 12 +#define SMC_ECC_PR6_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR6_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR6) Parity N */ +/* -------- SMC_ECC_PR7 : (SMC Offset: 0x04C) SMC ECC parity 7 Register -------- */ +#define SMC_ECC_PR7_BITADDR_Pos 0 +#define SMC_ECC_PR7_BITADDR_Msk (0x7u << SMC_ECC_PR7_BITADDR_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR7_WORDADDR_Pos 3 +#define SMC_ECC_PR7_WORDADDR_Msk (0x1ffu << SMC_ECC_PR7_WORDADDR_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR7_NPARITY_Pos 12 +#define SMC_ECC_PR7_NPARITY_Msk (0xfffu << SMC_ECC_PR7_NPARITY_Pos) /**< \brief (SMC_ECC_PR7) Parity N */ +#define SMC_ECC_PR7_WORDADDR_W8BIT_Pos 3 +#define SMC_ECC_PR7_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR7_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR7_NPARITY_W8BIT_Pos 12 +#define SMC_ECC_PR7_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR7_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR7) Parity N */ +/* -------- SMC_ECC_PR8 : (SMC Offset: 0x050) SMC ECC parity 8 Register -------- */ +#define SMC_ECC_PR8_BITADDR_Pos 0 +#define SMC_ECC_PR8_BITADDR_Msk (0x7u << SMC_ECC_PR8_BITADDR_Pos) /**< \brief (SMC_ECC_PR8) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR8_WORDADDR_Pos 3 +#define SMC_ECC_PR8_WORDADDR_Msk (0xffu << SMC_ECC_PR8_WORDADDR_Pos) /**< \brief (SMC_ECC_PR8) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR8_NPARITY_Pos 12 +#define SMC_ECC_PR8_NPARITY_Msk (0x7ffu << SMC_ECC_PR8_NPARITY_Pos) /**< \brief (SMC_ECC_PR8) Parity N */ +/* -------- SMC_ECC_PR9 : (SMC Offset: 0x054) SMC ECC parity 9 Register -------- */ +#define SMC_ECC_PR9_BITADDR_Pos 0 +#define SMC_ECC_PR9_BITADDR_Msk (0x7u << SMC_ECC_PR9_BITADDR_Pos) /**< \brief (SMC_ECC_PR9) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR9_WORDADDR_Pos 3 +#define SMC_ECC_PR9_WORDADDR_Msk (0xffu << SMC_ECC_PR9_WORDADDR_Pos) /**< \brief (SMC_ECC_PR9) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR9_NPARITY_Pos 12 +#define SMC_ECC_PR9_NPARITY_Msk (0x7ffu << SMC_ECC_PR9_NPARITY_Pos) /**< \brief (SMC_ECC_PR9) Parity N */ +/* -------- SMC_ECC_PR10 : (SMC Offset: 0x058) SMC ECC parity 10 Register -------- */ +#define SMC_ECC_PR10_BITADDR_Pos 0 +#define SMC_ECC_PR10_BITADDR_Msk (0x7u << SMC_ECC_PR10_BITADDR_Pos) /**< \brief (SMC_ECC_PR10) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR10_WORDADDR_Pos 3 +#define SMC_ECC_PR10_WORDADDR_Msk (0xffu << SMC_ECC_PR10_WORDADDR_Pos) /**< \brief (SMC_ECC_PR10) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR10_NPARITY_Pos 12 +#define SMC_ECC_PR10_NPARITY_Msk (0x7ffu << SMC_ECC_PR10_NPARITY_Pos) /**< \brief (SMC_ECC_PR10) Parity N */ +/* -------- SMC_ECC_PR11 : (SMC Offset: 0x05C) SMC ECC parity 11 Register -------- */ +#define SMC_ECC_PR11_BITADDR_Pos 0 +#define SMC_ECC_PR11_BITADDR_Msk (0x7u << SMC_ECC_PR11_BITADDR_Pos) /**< \brief (SMC_ECC_PR11) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR11_WORDADDR_Pos 3 +#define SMC_ECC_PR11_WORDADDR_Msk (0xffu << SMC_ECC_PR11_WORDADDR_Pos) /**< \brief (SMC_ECC_PR11) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR11_NPARITY_Pos 12 +#define SMC_ECC_PR11_NPARITY_Msk (0x7ffu << SMC_ECC_PR11_NPARITY_Pos) /**< \brief (SMC_ECC_PR11) Parity N */ +/* -------- SMC_ECC_PR12 : (SMC Offset: 0x060) SMC ECC parity 12 Register -------- */ +#define SMC_ECC_PR12_BITADDR_Pos 0 +#define SMC_ECC_PR12_BITADDR_Msk (0x7u << SMC_ECC_PR12_BITADDR_Pos) /**< \brief (SMC_ECC_PR12) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR12_WORDADDR_Pos 3 +#define SMC_ECC_PR12_WORDADDR_Msk (0xffu << SMC_ECC_PR12_WORDADDR_Pos) /**< \brief (SMC_ECC_PR12) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR12_NPARITY_Pos 12 +#define SMC_ECC_PR12_NPARITY_Msk (0x7ffu << SMC_ECC_PR12_NPARITY_Pos) /**< \brief (SMC_ECC_PR12) Parity N */ +/* -------- SMC_ECC_PR13 : (SMC Offset: 0x064) SMC ECC parity 13 Register -------- */ +#define SMC_ECC_PR13_BITADDR_Pos 0 +#define SMC_ECC_PR13_BITADDR_Msk (0x7u << SMC_ECC_PR13_BITADDR_Pos) /**< \brief (SMC_ECC_PR13) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR13_WORDADDR_Pos 3 +#define SMC_ECC_PR13_WORDADDR_Msk (0xffu << SMC_ECC_PR13_WORDADDR_Pos) /**< \brief (SMC_ECC_PR13) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR13_NPARITY_Pos 12 +#define SMC_ECC_PR13_NPARITY_Msk (0x7ffu << SMC_ECC_PR13_NPARITY_Pos) /**< \brief (SMC_ECC_PR13) Parity N */ +/* -------- SMC_ECC_PR14 : (SMC Offset: 0x068) SMC ECC parity 14 Register -------- */ +#define SMC_ECC_PR14_BITADDR_Pos 0 +#define SMC_ECC_PR14_BITADDR_Msk (0x7u << SMC_ECC_PR14_BITADDR_Pos) /**< \brief (SMC_ECC_PR14) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR14_WORDADDR_Pos 3 +#define SMC_ECC_PR14_WORDADDR_Msk (0xffu << SMC_ECC_PR14_WORDADDR_Pos) /**< \brief (SMC_ECC_PR14) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR14_NPARITY_Pos 12 +#define SMC_ECC_PR14_NPARITY_Msk (0x7ffu << SMC_ECC_PR14_NPARITY_Pos) /**< \brief (SMC_ECC_PR14) Parity N */ +/* -------- SMC_ECC_PR15 : (SMC Offset: 0x06C) SMC ECC parity 15 Register -------- */ +#define SMC_ECC_PR15_BITADDR_Pos 0 +#define SMC_ECC_PR15_BITADDR_Msk (0x7u << SMC_ECC_PR15_BITADDR_Pos) /**< \brief (SMC_ECC_PR15) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR15_WORDADDR_Pos 3 +#define SMC_ECC_PR15_WORDADDR_Msk (0xffu << SMC_ECC_PR15_WORDADDR_Pos) /**< \brief (SMC_ECC_PR15) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */ +#define SMC_ECC_PR15_NPARITY_Pos 12 +#define SMC_ECC_PR15_NPARITY_Msk (0x7ffu << SMC_ECC_PR15_NPARITY_Pos) /**< \brief (SMC_ECC_PR15) Parity N */ +/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */ +#define SMC_SETUP_NWE_SETUP_Pos 0 +#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */ +#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos))) +#define SMC_SETUP_NCS_WR_SETUP_Pos 8 +#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in Write Access */ +#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos))) +#define SMC_SETUP_NRD_SETUP_Pos 16 +#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */ +#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos))) +#define SMC_SETUP_NCS_RD_SETUP_Pos 24 +#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in Read Access */ +#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos))) +/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */ +#define SMC_PULSE_NWE_PULSE_Pos 0 +#define SMC_PULSE_NWE_PULSE_Msk (0x3fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */ +#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos))) +#define SMC_PULSE_NCS_WR_PULSE_Pos 8 +#define SMC_PULSE_NCS_WR_PULSE_Msk (0x3fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */ +#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos))) +#define SMC_PULSE_NRD_PULSE_Pos 16 +#define SMC_PULSE_NRD_PULSE_Msk (0x3fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */ +#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos))) +#define SMC_PULSE_NCS_RD_PULSE_Pos 24 +#define SMC_PULSE_NCS_RD_PULSE_Msk (0x3fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */ +#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos))) +/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */ +#define SMC_CYCLE_NWE_CYCLE_Pos 0 +#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */ +#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos))) +#define SMC_CYCLE_NRD_CYCLE_Pos 16 +#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */ +#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos))) +/* -------- SMC_TIMINGS : (SMC Offset: N/A) SMC Timings Register -------- */ +#define SMC_TIMINGS_TCLR_Pos 0 +#define SMC_TIMINGS_TCLR_Msk (0xfu << SMC_TIMINGS_TCLR_Pos) /**< \brief (SMC_TIMINGS) CLE to REN Low Delay */ +#define SMC_TIMINGS_TCLR(value) ((SMC_TIMINGS_TCLR_Msk & ((value) << SMC_TIMINGS_TCLR_Pos))) +#define SMC_TIMINGS_TADL_Pos 4 +#define SMC_TIMINGS_TADL_Msk (0xfu << SMC_TIMINGS_TADL_Pos) /**< \brief (SMC_TIMINGS) ALE to Data Start */ +#define SMC_TIMINGS_TADL(value) ((SMC_TIMINGS_TADL_Msk & ((value) << SMC_TIMINGS_TADL_Pos))) +#define SMC_TIMINGS_TAR_Pos 8 +#define SMC_TIMINGS_TAR_Msk (0xfu << SMC_TIMINGS_TAR_Pos) /**< \brief (SMC_TIMINGS) ALE to REN Low Delay */ +#define SMC_TIMINGS_TAR(value) ((SMC_TIMINGS_TAR_Msk & ((value) << SMC_TIMINGS_TAR_Pos))) +#define SMC_TIMINGS_OCMS (0x1u << 12) /**< \brief (SMC_TIMINGS) Off Chip Memory Scrambling Enable */ +#define SMC_TIMINGS_TRR_Pos 16 +#define SMC_TIMINGS_TRR_Msk (0xfu << SMC_TIMINGS_TRR_Pos) /**< \brief (SMC_TIMINGS) Ready to REN Low Delay */ +#define SMC_TIMINGS_TRR(value) ((SMC_TIMINGS_TRR_Msk & ((value) << SMC_TIMINGS_TRR_Pos))) +#define SMC_TIMINGS_TWB_Pos 24 +#define SMC_TIMINGS_TWB_Msk (0xfu << SMC_TIMINGS_TWB_Pos) /**< \brief (SMC_TIMINGS) WEN High to REN to Busy */ +#define SMC_TIMINGS_TWB(value) ((SMC_TIMINGS_TWB_Msk & ((value) << SMC_TIMINGS_TWB_Pos))) +#define SMC_TIMINGS_RBNSEL_Pos 28 +#define SMC_TIMINGS_RBNSEL_Msk (0x7u << SMC_TIMINGS_RBNSEL_Pos) /**< \brief (SMC_TIMINGS) Ready/Busy Line Selection */ +#define SMC_TIMINGS_RBNSEL(value) ((SMC_TIMINGS_RBNSEL_Msk & ((value) << SMC_TIMINGS_RBNSEL_Pos))) +#define SMC_TIMINGS_NFSEL (0x1u << 31) /**< \brief (SMC_TIMINGS) NAND Flash Selection */ +/* -------- SMC_MODE : (SMC Offset: N/A) SMC Mode Register -------- */ +#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE) */ +#define SMC_MODE_READ_MODE_NCS_CTRL (0x0u << 0) /**< \brief (SMC_MODE) The Read operation is controlled by the NCS signal. */ +#define SMC_MODE_READ_MODE_NRD_CTRL (0x1u << 0) /**< \brief (SMC_MODE) The Read operation is controlled by the NRD signal. */ +#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE) */ +#define SMC_MODE_WRITE_MODE_NCS_CTRL (0x0u << 1) /**< \brief (SMC_MODE) The Write operation is controller by the NCS signal. */ +#define SMC_MODE_WRITE_MODE_NWE_CTRL (0x1u << 1) /**< \brief (SMC_MODE) The Write operation is controlled by the NWE signal. */ +#define SMC_MODE_EXNW_MODE_Pos 4 +#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */ +#define SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */ +#define SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */ +#define SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */ +#define SMC_MODE_BAT (0x1u << 8) /**< \brief (SMC_MODE) Byte Access Type */ +#define SMC_MODE_DBW (0x1u << 12) /**< \brief (SMC_MODE) Data Bus Width */ +#define SMC_MODE_DBW_BIT_8 (0x0u << 12) /**< \brief (SMC_MODE) 8-bit bus */ +#define SMC_MODE_DBW_BIT_16 (0x1u << 12) /**< \brief (SMC_MODE) 16-bit bus */ +#define SMC_MODE_TDF_CYCLES_Pos 16 +#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */ +#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos))) +#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */ +/* -------- SMC_OCMS : (SMC Offset: 0x110) SMC OCMS Register -------- */ +#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */ +#define SMC_OCMS_SRSE (0x1u << 1) /**< \brief (SMC_OCMS) SRAM Scrambling Enable */ +/* -------- SMC_KEY1 : (SMC Offset: 0x114) SMC OCMS KEY1 Register -------- */ +#define SMC_KEY1_KEY1_Pos 0 +#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */ +#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos))) +/* -------- SMC_KEY2 : (SMC Offset: 0x118) SMC OCMS KEY2 Register -------- */ +#define SMC_KEY2_KEY2_Pos 0 +#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */ +#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos))) +/* -------- SMC_WPCR : (SMC Offset: 0x1E4) Write Protection Control Register -------- */ +#define SMC_WPCR_WP_EN (0x1u << 0) /**< \brief (SMC_WPCR) Write Protection Enable */ +#define SMC_WPCR_WP_KEY_Pos 8 +#define SMC_WPCR_WP_KEY_Msk (0xffffffu << SMC_WPCR_WP_KEY_Pos) /**< \brief (SMC_WPCR) Write Protection KEY password */ +#define SMC_WPCR_WP_KEY(value) ((SMC_WPCR_WP_KEY_Msk & ((value) << SMC_WPCR_WP_KEY_Pos))) +/* -------- SMC_WPSR : (SMC Offset: 0x1E8) Write Protection Status Register -------- */ +#define SMC_WPSR_WP_VS_Pos 0 +#define SMC_WPSR_WP_VS_Msk (0xfu << SMC_WPSR_WP_VS_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Status */ +#define SMC_WPSR_WP_VSRC_Pos 8 +#define SMC_WPSR_WP_VSRC_Msk (0xffffu << SMC_WPSR_WP_VSRC_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAM3XA_SMC_COMPONENT_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h new file mode 100644 index 0000000..252a8ed --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_spi.h @@ -0,0 +1,176 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_SPI_COMPONENT_ +#define _SAM3XA_SPI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */ +/* ============================================================================= */ +/** \addtogroup SAM3XA_SPI Serial Peripheral Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Spi hardware registers */ +typedef struct { + WoReg SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */ + RwReg SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */ + RoReg SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */ + WoReg SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */ + RoReg SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */ + WoReg SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */ + WoReg SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */ + RoReg SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */ + RoReg Reserved1[4]; + RwReg SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */ + RoReg Reserved2[41]; + RwReg SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */ + RoReg SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */ +} Spi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */ +#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */ +#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */ +#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */ +#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */ +/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */ +#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */ +#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */ +#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */ +#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */ +#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */ +#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */ +#define SPI_MR_PCS_Pos 16 +#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */ +#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos))) +#define SPI_MR_DLYBCS_Pos 24 +#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */ +#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos))) +/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */ +#define SPI_RDR_RD_Pos 0 +#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */ +#define SPI_RDR_PCS_Pos 16 +#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */ +/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */ +#define SPI_TDR_TD_Pos 0 +#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */ +#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos))) +#define SPI_TDR_PCS_Pos 16 +#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */ +#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos))) +#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */ +/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full */ +#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */ +#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error */ +#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status */ +#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising */ +#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty */ +#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */ +#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */ +/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */ +#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */ +#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */ +#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */ +#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */ +#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */ +#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */ +#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */ +#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */ +#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */ +#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */ +#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */ +#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */ +/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */ +#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */ +#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */ +#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */ +#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */ +#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */ +#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */ +#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */ +/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */ +#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */ +#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */ +#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ +#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ +#define SPI_CSR_BITS_Pos 4 +#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */ +#define SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */ +#define SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */ +#define SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */ +#define SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */ +#define SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */ +#define SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */ +#define SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */ +#define SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */ +#define SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */ +#define SPI_CSR_SCBR_Pos 8 +#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */ +#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos))) +#define SPI_CSR_DLYBS_Pos 16 +#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */ +#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos))) +#define SPI_CSR_DLYBCT_Pos 24 +#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */ +#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos))) +/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */ +#define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protection Enable */ +#define SPI_WPMR_WPKEY_Pos 8 +#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protection Key Password */ +#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos))) +/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */ +#define SPI_WPSR_WPVS (0x7u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */ +#define SPI_WPSR_WPVS_Pos 0 +#define SPI_WPSR_WPVS_Msk (0x1u << SPI_WPSR_WPVS_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Status */ +#define SPI_WPSR_WPVSRC_Pos 8 +#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAM3XA_SPI_COMPONENT_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h new file mode 100644 index 0000000..8349032 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_ssc.h @@ -0,0 +1,285 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_SSC_COMPONENT_ +#define _SAM3XA_SSC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */ +/* ============================================================================= */ +/** \addtogroup SAM3XA_SSC Synchronous Serial Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Ssc hardware registers */ +typedef struct { + WoReg SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */ + RwReg SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */ + RoReg Reserved1[2]; + RwReg SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */ + RwReg SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */ + RwReg SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */ + RwReg SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */ + RoReg SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */ + WoReg SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */ + RoReg Reserved2[2]; + RoReg SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */ + RwReg SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */ + RwReg SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */ + RwReg SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */ + RoReg SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */ + WoReg SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */ + WoReg SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */ + RoReg SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */ + RoReg Reserved3[37]; + RwReg SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */ + RoReg SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */ +} Ssc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */ +#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */ +#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */ +#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */ +#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */ +#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */ +/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */ +#define SSC_CMR_DIV_Pos 0 +#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */ +#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos))) +/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */ +#define SSC_RCMR_CKS_Pos 0 +#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */ +#define SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */ +#define SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */ +#define SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */ +#define SSC_RCMR_CKO_Pos 2 +#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */ +#define SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None */ +#define SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock */ +#define SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */ +#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */ +#define SSC_RCMR_CKG_Pos 6 +#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */ +#define SSC_RCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_RCMR) None */ +#define SSC_RCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_RCMR) Continuous Receive Clock */ +#define SSC_RCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */ +#define SSC_RCMR_START_Pos 8 +#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */ +#define SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ +#define SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */ +#define SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */ +#define SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */ +#define SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */ +#define SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */ +#define SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */ +#define SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */ +#define SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */ +#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */ +#define SSC_RCMR_STTDLY_Pos 16 +#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */ +#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos))) +#define SSC_RCMR_PERIOD_Pos 24 +#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */ +#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos))) +/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */ +#define SSC_RFMR_DATLEN_Pos 0 +#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */ +#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos))) +#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */ +#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */ +#define SSC_RFMR_DATNB_Pos 8 +#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */ +#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos))) +#define SSC_RFMR_FSLEN_Pos 16 +#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */ +#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos))) +#define SSC_RFMR_FSOS_Pos 20 +#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */ +#define SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None */ +#define SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse */ +#define SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse */ +#define SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer */ +#define SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer */ +#define SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer */ +#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */ +#define SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */ +#define SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */ +#define SSC_RFMR_FSLEN_EXT_Pos 28 +#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */ +#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos))) +/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */ +#define SSC_TCMR_CKS_Pos 0 +#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */ +#define SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */ +#define SSC_TCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_TCMR) TK Clock signal */ +#define SSC_TCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_TCMR) RK pin */ +#define SSC_TCMR_CKO_Pos 2 +#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */ +#define SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None */ +#define SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Receive Clock */ +#define SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers */ +#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */ +#define SSC_TCMR_CKG_Pos 6 +#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */ +#define SSC_TCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_TCMR) None */ +#define SSC_TCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */ +#define SSC_TCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */ +#define SSC_TCMR_START_Pos 8 +#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */ +#define SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. */ +#define SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */ +#define SSC_TCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */ +#define SSC_TCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */ +#define SSC_TCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */ +#define SSC_TCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */ +#define SSC_TCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */ +#define SSC_TCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */ +#define SSC_TCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_TCMR) Compare 0 */ +#define SSC_TCMR_STTDLY_Pos 16 +#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */ +#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos))) +#define SSC_TCMR_PERIOD_Pos 24 +#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */ +#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos))) +/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */ +#define SSC_TFMR_DATLEN_Pos 0 +#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */ +#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos))) +#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */ +#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */ +#define SSC_TFMR_DATNB_Pos 8 +#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per frame */ +#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos))) +#define SSC_TFMR_FSLEN_Pos 16 +#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */ +#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos))) +#define SSC_TFMR_FSOS_Pos 20 +#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */ +#define SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None */ +#define SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse */ +#define SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse */ +#define SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */ +#define SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */ +#define SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */ +#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */ +#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */ +#define SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */ +#define SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */ +#define SSC_TFMR_FSLEN_EXT_Pos 28 +#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */ +#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos))) +/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */ +#define SSC_RHR_RDAT_Pos 0 +#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */ +/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */ +#define SSC_THR_TDAT_Pos 0 +#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */ +#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos))) +/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */ +#define SSC_RSHR_RSDAT_Pos 0 +#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */ +/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */ +#define SSC_TSHR_TSDAT_Pos 0 +#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */ +#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos))) +/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */ +#define SSC_RC0R_CP0_Pos 0 +#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */ +#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos))) +/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */ +#define SSC_RC1R_CP1_Pos 0 +#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */ +#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos))) +/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */ +#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */ +#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */ +#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */ +#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */ +#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */ +#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */ +#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */ +#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */ +#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */ +#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */ +/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */ +#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */ +#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */ +#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */ +#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */ +#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */ +#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */ +#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */ +#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */ +/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */ +#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */ +#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */ +#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */ +#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */ +#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */ +#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */ +#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */ +#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */ +/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */ +#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */ +#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */ +#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */ +#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */ +#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */ +#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */ +#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */ +#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */ +/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */ +#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protect Enable */ +#define SSC_WPMR_WPKEY_Pos 8 +#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protect KEY */ +#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos))) +/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */ +#define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */ +#define SSC_WPSR_WPVSRC_Pos 8 +#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */ + +/*@}*/ + + +#endif /* _SAM3XA_SSC_COMPONENT_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h new file mode 100644 index 0000000..92e9739 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_supc.h @@ -0,0 +1,327 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_SUPC_COMPONENT_ +#define _SAM3XA_SUPC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Supply Controller */ +/* ============================================================================= */ +/** \addtogroup SAM3XA_SUPC Supply Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Supc hardware registers */ +typedef struct { + WoReg SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */ + RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */ + RwReg SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */ + RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */ + RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */ + RoReg SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */ +} Supc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */ +#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */ +#define SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) no effect. */ +#define SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */ +#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */ +#define SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) no effect. */ +#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */ +#define SUPC_CR_KEY_Pos 24 +#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */ +#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos))) +/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */ +#define SUPC_SMMR_SMTH_Pos 0 +#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */ +#define SUPC_SMMR_SMTH_1_9V (0x0u << 0) /**< \brief (SUPC_SMMR) 1.9 V */ +#define SUPC_SMMR_SMTH_2_0V (0x1u << 0) /**< \brief (SUPC_SMMR) 2.0 V */ +#define SUPC_SMMR_SMTH_2_1V (0x2u << 0) /**< \brief (SUPC_SMMR) 2.1 V */ +#define SUPC_SMMR_SMTH_2_2V (0x3u << 0) /**< \brief (SUPC_SMMR) 2.2 V */ +#define SUPC_SMMR_SMTH_2_3V (0x4u << 0) /**< \brief (SUPC_SMMR) 2.3 V */ +#define SUPC_SMMR_SMTH_2_4V (0x5u << 0) /**< \brief (SUPC_SMMR) 2.4 V */ +#define SUPC_SMMR_SMTH_2_5V (0x6u << 0) /**< \brief (SUPC_SMMR) 2.5 V */ +#define SUPC_SMMR_SMTH_2_6V (0x7u << 0) /**< \brief (SUPC_SMMR) 2.6 V */ +#define SUPC_SMMR_SMTH_2_7V (0x8u << 0) /**< \brief (SUPC_SMMR) 2.7 V */ +#define SUPC_SMMR_SMTH_2_8V (0x9u << 0) /**< \brief (SUPC_SMMR) 2.8 V */ +#define SUPC_SMMR_SMTH_2_9V (0xAu << 0) /**< \brief (SUPC_SMMR) 2.9 V */ +#define SUPC_SMMR_SMTH_3_0V (0xBu << 0) /**< \brief (SUPC_SMMR) 3.0 V */ +#define SUPC_SMMR_SMTH_3_1V (0xCu << 0) /**< \brief (SUPC_SMMR) 3.1 V */ +#define SUPC_SMMR_SMTH_3_2V (0xDu << 0) /**< \brief (SUPC_SMMR) 3.2 V */ +#define SUPC_SMMR_SMTH_3_3V (0xEu << 0) /**< \brief (SUPC_SMMR) 3.3 V */ +#define SUPC_SMMR_SMTH_3_4V (0xFu << 0) /**< \brief (SUPC_SMMR) 3.4 V */ +#define SUPC_SMMR_SMSMPL_Pos 8 +#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */ +#define SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */ +#define SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */ +#define SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */ +#define SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */ +#define SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */ +#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */ +#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */ +#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */ +/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */ +#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */ +#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */ +#define SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */ +#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */ +#define SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */ +#define SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */ +#define SUPC_MR_VDDIORDYONREG (0x1u << 14) /**< \brief (SUPC_MR) */ +#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */ +#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */ +#define SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */ +#define SUPC_MR_KEY_Pos 24 +#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */ +#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos))) +/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */ +#define SUPC_WUMR_FWUPEN (0x1u << 0) /**< \brief (SUPC_WUMR) Force Wake Up Enable */ +#define SUPC_WUMR_FWUPEN_NOT_ENABLE (0x0u << 0) /**< \brief (SUPC_WUMR) the Force Wake Up pin has no wake up effect. */ +#define SUPC_WUMR_FWUPEN_ENABLE (0x1u << 0) /**< \brief (SUPC_WUMR) the Force Wake Up pin low forces the wake up of the core power supply. */ +#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */ +#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */ +#define SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */ +#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */ +#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */ +#define SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */ +#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */ +#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */ +#define SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */ +#define SUPC_WUMR_FWUPDBC_Pos 8 +#define SUPC_WUMR_FWUPDBC_Msk (0x7u << SUPC_WUMR_FWUPDBC_Pos) /**< \brief (SUPC_WUMR) Force Wake Up Debouncer Period */ +#define SUPC_WUMR_FWUPDBC_IMMEDIATE (0x0u << 8) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ +#define SUPC_WUMR_FWUPDBC_3_SCLK (0x1u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 3 SLCK periods */ +#define SUPC_WUMR_FWUPDBC_32_SCLK (0x2u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 32 SLCK periods */ +#define SUPC_WUMR_FWUPDBC_512_SCLK (0x3u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 512 SLCK periods */ +#define SUPC_WUMR_FWUPDBC_4096_SCLK (0x4u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 4,096 SLCK periods */ +#define SUPC_WUMR_FWUPDBC_32768_SCLK (0x5u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 32,768 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_Pos 12 +#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer Period */ +#define SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ +#define SUPC_WUMR_WKUPDBC_3_SCLK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32_SCLK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_512_SCLK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_4096_SCLK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32768_SCLK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */ +/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */ +#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */ +#define SUPC_WUIR_WKUPEN0_NOT_ENABLE (0x0u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */ +#define SUPC_WUIR_WKUPEN1_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */ +#define SUPC_WUIR_WKUPEN2_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */ +#define SUPC_WUIR_WKUPEN3_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */ +#define SUPC_WUIR_WKUPEN4_NOT_ENABLE (0x0u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */ +#define SUPC_WUIR_WKUPEN5_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */ +#define SUPC_WUIR_WKUPEN6_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */ +#define SUPC_WUIR_WKUPEN7_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */ +#define SUPC_WUIR_WKUPEN8_NOT_ENABLE (0x0u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */ +#define SUPC_WUIR_WKUPEN9_NOT_ENABLE (0x0u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */ +#define SUPC_WUIR_WKUPEN10_NOT_ENABLE (0x0u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */ +#define SUPC_WUIR_WKUPEN11_NOT_ENABLE (0x0u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */ +#define SUPC_WUIR_WKUPEN12_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */ +#define SUPC_WUIR_WKUPEN13_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN14 (0x1u << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */ +#define SUPC_WUIR_WKUPEN14_NOT_ENABLE (0x0u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN14_ENABLE (0x1u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN15 (0x1u << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */ +#define SUPC_WUIR_WKUPEN15_NOT_ENABLE (0x0u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN15_ENABLE (0x1u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake Up Input Transition 0 */ +#define SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake Up Input Transition 1 */ +#define SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake Up Input Transition 2 */ +#define SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake Up Input Transition 3 */ +#define SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake Up Input Transition 4 */ +#define SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake Up Input Transition 5 */ +#define SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake Up Input Transition 6 */ +#define SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake Up Input Transition 7 */ +#define SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake Up Input Transition 8 */ +#define SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake Up Input Transition 9 */ +#define SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake Up Input Transition 10 */ +#define SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake Up Input Transition 11 */ +#define SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake Up Input Transition 12 */ +#define SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake Up Input Transition 13 */ +#define SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT14 (0x1u << 30) /**< \brief (SUPC_WUIR) Wake Up Input Transition 14 */ +#define SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0u << 30) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1u << 30) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT15 (0x1u << 31) /**< \brief (SUPC_WUIR) Wake Up Input Transition 15 */ +#define SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0u << 31) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1u << 31) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ +/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */ +#define SUPC_SR_FWUPS (0x1u << 0) /**< \brief (SUPC_SR) FWUP Wake Up Status */ +#define SUPC_SR_FWUPS_NO (0x0u << 0) /**< \brief (SUPC_SR) no wake up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_FWUPS_PRESENT (0x1u << 0) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */ +#define SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */ +#define SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */ +#define SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */ +#define SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status */ +#define SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */ +#define SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDUTMI higher than its threshold at its last measurement. */ +#define SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDUTMI lower than its threshold at its last measurement. */ +#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */ +#define SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */ +#define SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */ +#define SUPC_SR_FWUPIS (0x1u << 12) /**< \brief (SUPC_SR) FWUP Input Status */ +#define SUPC_SR_FWUPIS_LOW (0x0u << 12) /**< \brief (SUPC_SR) FWUP input is tied low. */ +#define SUPC_SR_FWUPIS_HIGH (0x1u << 12) /**< \brief (SUPC_SR) FWUP input is tied high. */ +#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */ +#define SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */ +#define SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */ +#define SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */ +#define SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */ +#define SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */ +#define SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */ +#define SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */ +#define SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */ +#define SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */ +#define SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */ +#define SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */ +#define SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */ +#define SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */ +#define SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS14 (0x1u << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */ +#define SUPC_SR_WKUPIS14_DIS (0x0u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS14_EN (0x1u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS15 (0x1u << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */ +#define SUPC_SR_WKUPIS15_DIS (0x0u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS15_EN (0x1u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ + +/*@}*/ + + +#endif /* _SAM3XA_SUPC_COMPONENT_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h new file mode 100644 index 0000000..de3530f --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_tc.h @@ -0,0 +1,318 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_TC_COMPONENT_ +#define _SAM3XA_TC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Timer Counter */ +/* ============================================================================= */ +/** \addtogroup SAM3XA_TC Timer Counter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief TcChannel hardware registers */ +typedef struct { + RwReg TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */ + RwReg TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */ + RwReg TC_SMMR; /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */ + RoReg Reserved1[1]; + RwReg TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */ + RwReg TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */ + RwReg TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */ + RwReg TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */ + RwReg TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */ + RwReg TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */ + RwReg TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */ + RwReg TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */ + RoReg Reserved2[4]; +} TcChannel; +/** \brief Tc hardware registers */ +#define TCCHANNEL_NUMBER 3 +typedef struct { + TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */ + WoReg TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */ + RwReg TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */ + WoReg TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */ + WoReg TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */ + RoReg TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */ + RoReg TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */ + RwReg TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */ + RoReg Reserved1[2]; + RwReg TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protect Mode Register */ +} Tc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */ +#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */ +#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */ +#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */ +/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */ +#define TC_CMR_TCCLKS_Pos 0 +#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */ +#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: TCLK1 */ +#define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: TCLK2 */ +#define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: TCLK3 */ +#define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: TCLK4 */ +#define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: TCLK5 */ +#define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */ +#define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */ +#define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */ +#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */ +#define TC_CMR_BURST_Pos 4 +#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */ +#define TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ +#define TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */ +#define TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */ +#define TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */ +#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */ +#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */ +#define TC_CMR_ETRGEDG_Pos 8 +#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */ +#define TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ +#define TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ +#define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ +#define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ +#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */ +#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */ +#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */ +#define TC_CMR_LDRA_Pos 16 +#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */ +#define TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ +#define TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */ +#define TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */ +#define TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */ +#define TC_CMR_LDRB_Pos 18 +#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */ +#define TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ +#define TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */ +#define TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */ +#define TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */ +#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */ +#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */ +#define TC_CMR_EEVTEDG_Pos 8 +#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */ +#define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */ +#define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ +#define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ +#define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ +#define TC_CMR_EEVT_Pos 10 +#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */ +#define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */ +#define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */ +#define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */ +#define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */ +#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */ +#define TC_CMR_WAVSEL_Pos 13 +#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */ +#define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */ +#define TC_CMR_ACPA_Pos 16 +#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */ +#define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ +#define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_ACPC_Pos 18 +#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */ +#define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ +#define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_AEEVT_Pos 20 +#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */ +#define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */ +#define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */ +#define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_ASWTRG_Pos 22 +#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */ +#define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */ +#define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BCPB_Pos 24 +#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */ +#define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */ +#define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BCPC_Pos 26 +#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */ +#define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */ +#define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BEEVT_Pos 28 +#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */ +#define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */ +#define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BSWTRG_Pos 30 +#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */ +#define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */ +#define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */ +/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */ +#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */ +#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) DOWN Count */ +/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */ +#define TC_CV_CV_Pos 0 +#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */ +/* -------- TC_RA : (TC Offset: N/A) Register A -------- */ +#define TC_RA_RA_Pos 0 +#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */ +#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos))) +/* -------- TC_RB : (TC Offset: N/A) Register B -------- */ +#define TC_RB_RB_Pos 0 +#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */ +#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos))) +/* -------- TC_RC : (TC Offset: N/A) Register C -------- */ +#define TC_RC_RC_Pos 0 +#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */ +#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos))) +/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */ +#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status */ +#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status */ +#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status */ +#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status */ +#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status */ +#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status */ +#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status */ +#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status */ +#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */ +#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */ +#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */ +/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */ +#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */ +#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */ +#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */ +#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */ +#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */ +#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */ +#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */ +#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */ +/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */ +#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */ +#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */ +#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */ +#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */ +#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */ +#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */ +#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */ +#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */ +/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */ +#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */ +#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */ +#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */ +#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */ +#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */ +#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */ +#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */ +#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */ +/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */ +#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */ +/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */ +#define TC_BMR_TC0XC0S_Pos 0 +#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */ +#define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */ +#define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */ +#define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */ +#define TC_BMR_TC1XC1S_Pos 2 +#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */ +#define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */ +#define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */ +#define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */ +#define TC_BMR_TC2XC2S_Pos 4 +#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */ +#define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */ +#define TC_BMR_TC2XC2S_TIOA1 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */ +#define TC_BMR_TC2XC2S_TIOA2 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA2 */ +#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */ +#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) POSition ENabled */ +#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) SPEED ENabled */ +#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */ +#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */ +#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) INVerted phA */ +#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) INVerted phB */ +#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) INVerted InDeX */ +#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */ +#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */ +#define TC_BMR_FILTER (0x1u << 19) /**< \brief (TC_BMR) */ +#define TC_BMR_MAXFILT_Pos 20 +#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) MAXimum FILTer */ +#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos))) +/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */ +#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) InDeX */ +#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) DIRection CHanGe */ +#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature ERRor */ +/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */ +#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) InDeX */ +#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) DIRection CHanGe */ +#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature ERRor */ +/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */ +#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) InDeX */ +#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) DIRection CHanGe */ +#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature ERRor */ +/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */ +#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) InDeX */ +#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) DIRection CHanGe */ +#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature ERRor */ +#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */ +/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */ +#define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) ENable Compare Fault Channel 0 */ +#define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) ENable Compare Fault Channel 1 */ +/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */ +#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protect Enable */ +#define TC_WPMR_WPKEY_Pos 8 +#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protect KEY */ +#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos))) + +/*@}*/ + + +#endif /* _SAM3XA_TC_COMPONENT_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h new file mode 100644 index 0000000..2c984dc --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_trng.h @@ -0,0 +1,87 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_TRNG_COMPONENT_ +#define _SAM3XA_TRNG_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR True Random Number Generator */ +/* ============================================================================= */ +/** \addtogroup SAM3XA_TRNG True Random Number Generator */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Trng hardware registers */ +typedef struct { + WoReg TRNG_CR; /**< \brief (Trng Offset: 0x00) Control Register */ + RoReg Reserved1[3]; + WoReg TRNG_IER; /**< \brief (Trng Offset: 0x10) Interrupt Enable Register */ + WoReg TRNG_IDR; /**< \brief (Trng Offset: 0x14) Interrupt Disable Register */ + RoReg TRNG_IMR; /**< \brief (Trng Offset: 0x18) Interrupt Mask Register */ + RoReg TRNG_ISR; /**< \brief (Trng Offset: 0x1C) Interrupt Status Register */ + RoReg Reserved2[12]; + RoReg TRNG_ODATA; /**< \brief (Trng Offset: 0x50) Output Data Register */ +} Trng; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TRNG_CR : (TRNG Offset: 0x00) Control Register -------- */ +#define TRNG_CR_ENABLE (0x1u << 0) /**< \brief (TRNG_CR) Enables the TRNG to provide random values */ +#define TRNG_CR_KEY_Pos 8 +#define TRNG_CR_KEY_Msk (0xffffffu << TRNG_CR_KEY_Pos) /**< \brief (TRNG_CR) Security Key */ +#define TRNG_CR_KEY(value) ((TRNG_CR_KEY_Msk & ((value) << TRNG_CR_KEY_Pos))) +/* -------- TRNG_IER : (TRNG Offset: 0x10) Interrupt Enable Register -------- */ +#define TRNG_IER_DATRDY (0x1u << 0) /**< \brief (TRNG_IER) Data Ready Interrupt Enable */ +/* -------- TRNG_IDR : (TRNG Offset: 0x14) Interrupt Disable Register -------- */ +#define TRNG_IDR_DATRDY (0x1u << 0) /**< \brief (TRNG_IDR) Data Ready Interrupt Disable */ +/* -------- TRNG_IMR : (TRNG Offset: 0x18) Interrupt Mask Register -------- */ +#define TRNG_IMR_DATRDY (0x1u << 0) /**< \brief (TRNG_IMR) Data Ready Interrupt Mask */ +/* -------- TRNG_ISR : (TRNG Offset: 0x1C) Interrupt Status Register -------- */ +#define TRNG_ISR_DATRDY (0x1u << 0) /**< \brief (TRNG_ISR) Data Ready */ +/* -------- TRNG_ODATA : (TRNG Offset: 0x50) Output Data Register -------- */ +#define TRNG_ODATA_ODATA_Pos 0 +#define TRNG_ODATA_ODATA_Msk (0xffffffffu << TRNG_ODATA_ODATA_Pos) /**< \brief (TRNG_ODATA) Output Data */ + +/*@}*/ + + +#endif /* _SAM3XA_TRNG_COMPONENT_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h new file mode 100644 index 0000000..eca92be --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_twi.h @@ -0,0 +1,232 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_TWI_COMPONENT_ +#define _SAM3XA_TWI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Two-wire Interface */ +/* ============================================================================= */ +/** \addtogroup SAM3XA_TWI Two-wire Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Twi hardware registers */ +typedef struct { + WoReg TWI_CR; /**< \brief (Twi Offset: 0x00) Control Register */ + RwReg TWI_MMR; /**< \brief (Twi Offset: 0x04) Master Mode Register */ + RwReg TWI_SMR; /**< \brief (Twi Offset: 0x08) Slave Mode Register */ + RwReg TWI_IADR; /**< \brief (Twi Offset: 0x0C) Internal Address Register */ + RwReg TWI_CWGR; /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */ + RoReg Reserved1[3]; + RoReg TWI_SR; /**< \brief (Twi Offset: 0x20) Status Register */ + WoReg TWI_IER; /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */ + WoReg TWI_IDR; /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */ + RoReg TWI_IMR; /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */ + RoReg TWI_RHR; /**< \brief (Twi Offset: 0x30) Receive Holding Register */ + WoReg TWI_THR; /**< \brief (Twi Offset: 0x34) Transmit Holding Register */ + RoReg Reserved2[50]; + RwReg TWI_RPR; /**< \brief (Twi Offset: 0x100) Receive Pointer Register */ + RwReg TWI_RCR; /**< \brief (Twi Offset: 0x104) Receive Counter Register */ + RwReg TWI_TPR; /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */ + RwReg TWI_TCR; /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */ + RwReg TWI_RNPR; /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */ + RwReg TWI_RNCR; /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */ + RwReg TWI_TNPR; /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */ + RwReg TWI_TNCR; /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */ + WoReg TWI_PTCR; /**< \brief (Twi Offset: 0x120) Transfer Control Register */ + RoReg TWI_PTSR; /**< \brief (Twi Offset: 0x124) Transfer Status Register */ +} Twi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */ +#define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */ +#define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */ +#define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */ +#define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */ +#define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */ +#define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */ +#define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBUS Quick Command */ +#define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */ +/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */ +#define TWI_MMR_IADRSZ_Pos 8 +#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */ +#define TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */ +#define TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */ +#define TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */ +#define TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */ +#define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */ +#define TWI_MMR_DADR_Pos 16 +#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */ +#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos))) +/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */ +#define TWI_SMR_SADR_Pos 16 +#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */ +#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos))) +/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */ +#define TWI_IADR_IADR_Pos 0 +#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */ +#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos))) +/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */ +#define TWI_CWGR_CLDIV_Pos 0 +#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */ +#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos))) +#define TWI_CWGR_CHDIV_Pos 8 +#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */ +#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos))) +#define TWI_CWGR_CKDIV_Pos 16 +#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */ +#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos))) +/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */ +#define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */ +#define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */ +#define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */ +#define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */ +#define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */ +#define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */ +#define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */ +#define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */ +#define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */ +#define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */ +#define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */ +#define TWI_SR_ENDRX (0x1u << 12) /**< \brief (TWI_SR) End of RX buffer */ +#define TWI_SR_ENDTX (0x1u << 13) /**< \brief (TWI_SR) End of TX buffer */ +#define TWI_SR_RXBUFF (0x1u << 14) /**< \brief (TWI_SR) RX Buffer Full */ +#define TWI_SR_TXBUFE (0x1u << 15) /**< \brief (TWI_SR) TX Buffer Empty */ +/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */ +#define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */ +#define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */ +#define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */ +#define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */ +#define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */ +#define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */ +#define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */ +#define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */ +#define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */ +#define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */ +#define TWI_IER_ENDRX (0x1u << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */ +#define TWI_IER_ENDTX (0x1u << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */ +#define TWI_IER_RXBUFF (0x1u << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */ +#define TWI_IER_TXBUFE (0x1u << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */ +/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */ +#define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */ +#define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */ +#define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */ +#define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */ +#define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */ +#define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */ +#define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */ +#define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */ +#define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */ +#define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */ +#define TWI_IDR_ENDRX (0x1u << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */ +#define TWI_IDR_ENDTX (0x1u << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */ +#define TWI_IDR_RXBUFF (0x1u << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */ +#define TWI_IDR_TXBUFE (0x1u << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */ +/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */ +#define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */ +#define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */ +#define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */ +#define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */ +#define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */ +#define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */ +#define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */ +#define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */ +#define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */ +#define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */ +#define TWI_IMR_ENDRX (0x1u << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */ +#define TWI_IMR_ENDTX (0x1u << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */ +#define TWI_IMR_RXBUFF (0x1u << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */ +#define TWI_IMR_TXBUFE (0x1u << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */ +/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */ +#define TWI_RHR_RXDATA_Pos 0 +#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */ +/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */ +#define TWI_THR_TXDATA_Pos 0 +#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */ +#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos))) +/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */ +#define TWI_RPR_RXPTR_Pos 0 +#define TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos) /**< \brief (TWI_RPR) Receive Pointer Register */ +#define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_Msk & ((value) << TWI_RPR_RXPTR_Pos))) +/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */ +#define TWI_RCR_RXCTR_Pos 0 +#define TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos) /**< \brief (TWI_RCR) Receive Counter Register */ +#define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_Msk & ((value) << TWI_RCR_RXCTR_Pos))) +/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */ +#define TWI_TPR_TXPTR_Pos 0 +#define TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos) /**< \brief (TWI_TPR) Transmit Counter Register */ +#define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_Msk & ((value) << TWI_TPR_TXPTR_Pos))) +/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */ +#define TWI_TCR_TXCTR_Pos 0 +#define TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos) /**< \brief (TWI_TCR) Transmit Counter Register */ +#define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_Msk & ((value) << TWI_TCR_TXCTR_Pos))) +/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */ +#define TWI_RNPR_RXNPTR_Pos 0 +#define TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos) /**< \brief (TWI_RNPR) Receive Next Pointer */ +#define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_Msk & ((value) << TWI_RNPR_RXNPTR_Pos))) +/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */ +#define TWI_RNCR_RXNCTR_Pos 0 +#define TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos) /**< \brief (TWI_RNCR) Receive Next Counter */ +#define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_Msk & ((value) << TWI_RNCR_RXNCTR_Pos))) +/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */ +#define TWI_TNPR_TXNPTR_Pos 0 +#define TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos) /**< \brief (TWI_TNPR) Transmit Next Pointer */ +#define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_Msk & ((value) << TWI_TNPR_TXNPTR_Pos))) +/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */ +#define TWI_TNCR_TXNCTR_Pos 0 +#define TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos) /**< \brief (TWI_TNCR) Transmit Counter Next */ +#define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_Msk & ((value) << TWI_TNCR_TXNCTR_Pos))) +/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */ +#define TWI_PTCR_RXTEN (0x1u << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */ +#define TWI_PTCR_RXTDIS (0x1u << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */ +#define TWI_PTCR_TXTEN (0x1u << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */ +#define TWI_PTCR_TXTDIS (0x1u << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */ +/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */ +#define TWI_PTSR_RXTEN (0x1u << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */ +#define TWI_PTSR_TXTEN (0x1u << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + + +#endif /* _SAM3XA_TWI_COMPONENT_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h new file mode 100644 index 0000000..8186912 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_uart.h @@ -0,0 +1,200 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_UART_COMPONENT_ +#define _SAM3XA_UART_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */ +/* ============================================================================= */ +/** \addtogroup SAM3XA_UART Universal Asynchronous Receiver Transmitter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Uart hardware registers */ +typedef struct { + WoReg UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */ + RwReg UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */ + WoReg UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */ + WoReg UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */ + RoReg UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */ + RoReg UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */ + RoReg UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */ + WoReg UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */ + RwReg UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */ + RoReg Reserved1[55]; + RwReg UART_RPR; /**< \brief (Uart Offset: 0x100) Receive Pointer Register */ + RwReg UART_RCR; /**< \brief (Uart Offset: 0x104) Receive Counter Register */ + RwReg UART_TPR; /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */ + RwReg UART_TCR; /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */ + RwReg UART_RNPR; /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */ + RwReg UART_RNCR; /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */ + RwReg UART_TNPR; /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */ + RwReg UART_TNCR; /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */ + WoReg UART_PTCR; /**< \brief (Uart Offset: 0x120) Transfer Control Register */ + RoReg UART_PTSR; /**< \brief (Uart Offset: 0x124) Transfer Status Register */ +} Uart; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */ +#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */ +#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */ +#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */ +#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */ +#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */ +#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */ +#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status Bits */ +/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */ +#define UART_MR_PAR_Pos 9 +#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */ +#define UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even parity */ +#define UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd parity */ +#define UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */ +#define UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */ +#define UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */ +#define UART_MR_CHMODE_Pos 14 +#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */ +#define UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal Mode */ +#define UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic Echo */ +#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local Loopback */ +#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote Loopback */ +/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */ +#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */ +#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */ +#define UART_IER_ENDRX (0x1u << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */ +#define UART_IER_ENDTX (0x1u << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */ +#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */ +#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */ +#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */ +#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */ +#define UART_IER_TXBUFE (0x1u << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */ +#define UART_IER_RXBUFF (0x1u << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */ +/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */ +#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */ +#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */ +#define UART_IDR_ENDRX (0x1u << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */ +#define UART_IDR_ENDTX (0x1u << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */ +#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */ +#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */ +#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */ +#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */ +#define UART_IDR_TXBUFE (0x1u << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */ +#define UART_IDR_RXBUFF (0x1u << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */ +/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */ +#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */ +#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */ +#define UART_IMR_ENDRX (0x1u << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */ +#define UART_IMR_ENDTX (0x1u << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */ +#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */ +#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */ +#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */ +#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */ +#define UART_IMR_TXBUFE (0x1u << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */ +#define UART_IMR_RXBUFF (0x1u << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */ +/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */ +#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */ +#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */ +#define UART_SR_ENDRX (0x1u << 3) /**< \brief (UART_SR) End of Receiver Transfer */ +#define UART_SR_ENDTX (0x1u << 4) /**< \brief (UART_SR) End of Transmitter Transfer */ +#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */ +#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */ +#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */ +#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */ +#define UART_SR_TXBUFE (0x1u << 11) /**< \brief (UART_SR) Transmission Buffer Empty */ +#define UART_SR_RXBUFF (0x1u << 12) /**< \brief (UART_SR) Receive Buffer Full */ +/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */ +#define UART_RHR_RXCHR_Pos 0 +#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */ +/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */ +#define UART_THR_TXCHR_Pos 0 +#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */ +#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos))) +/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */ +#define UART_BRGR_CD_Pos 0 +#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */ +#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos))) +/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */ +#define UART_RPR_RXPTR_Pos 0 +#define UART_RPR_RXPTR_Msk (0xffffffffu << UART_RPR_RXPTR_Pos) /**< \brief (UART_RPR) Receive Pointer Register */ +#define UART_RPR_RXPTR(value) ((UART_RPR_RXPTR_Msk & ((value) << UART_RPR_RXPTR_Pos))) +/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */ +#define UART_RCR_RXCTR_Pos 0 +#define UART_RCR_RXCTR_Msk (0xffffu << UART_RCR_RXCTR_Pos) /**< \brief (UART_RCR) Receive Counter Register */ +#define UART_RCR_RXCTR(value) ((UART_RCR_RXCTR_Msk & ((value) << UART_RCR_RXCTR_Pos))) +/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */ +#define UART_TPR_TXPTR_Pos 0 +#define UART_TPR_TXPTR_Msk (0xffffffffu << UART_TPR_TXPTR_Pos) /**< \brief (UART_TPR) Transmit Counter Register */ +#define UART_TPR_TXPTR(value) ((UART_TPR_TXPTR_Msk & ((value) << UART_TPR_TXPTR_Pos))) +/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */ +#define UART_TCR_TXCTR_Pos 0 +#define UART_TCR_TXCTR_Msk (0xffffu << UART_TCR_TXCTR_Pos) /**< \brief (UART_TCR) Transmit Counter Register */ +#define UART_TCR_TXCTR(value) ((UART_TCR_TXCTR_Msk & ((value) << UART_TCR_TXCTR_Pos))) +/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */ +#define UART_RNPR_RXNPTR_Pos 0 +#define UART_RNPR_RXNPTR_Msk (0xffffffffu << UART_RNPR_RXNPTR_Pos) /**< \brief (UART_RNPR) Receive Next Pointer */ +#define UART_RNPR_RXNPTR(value) ((UART_RNPR_RXNPTR_Msk & ((value) << UART_RNPR_RXNPTR_Pos))) +/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */ +#define UART_RNCR_RXNCTR_Pos 0 +#define UART_RNCR_RXNCTR_Msk (0xffffu << UART_RNCR_RXNCTR_Pos) /**< \brief (UART_RNCR) Receive Next Counter */ +#define UART_RNCR_RXNCTR(value) ((UART_RNCR_RXNCTR_Msk & ((value) << UART_RNCR_RXNCTR_Pos))) +/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */ +#define UART_TNPR_TXNPTR_Pos 0 +#define UART_TNPR_TXNPTR_Msk (0xffffffffu << UART_TNPR_TXNPTR_Pos) /**< \brief (UART_TNPR) Transmit Next Pointer */ +#define UART_TNPR_TXNPTR(value) ((UART_TNPR_TXNPTR_Msk & ((value) << UART_TNPR_TXNPTR_Pos))) +/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */ +#define UART_TNCR_TXNCTR_Pos 0 +#define UART_TNCR_TXNCTR_Msk (0xffffu << UART_TNCR_TXNCTR_Pos) /**< \brief (UART_TNCR) Transmit Counter Next */ +#define UART_TNCR_TXNCTR(value) ((UART_TNCR_TXNCTR_Msk & ((value) << UART_TNCR_TXNCTR_Pos))) +/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */ +#define UART_PTCR_RXTEN (0x1u << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */ +#define UART_PTCR_RXTDIS (0x1u << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */ +#define UART_PTCR_TXTEN (0x1u << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */ +#define UART_PTCR_TXTDIS (0x1u << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */ +/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */ +#define UART_PTSR_RXTEN (0x1u << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */ +#define UART_PTSR_TXTEN (0x1u << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + + +#endif /* _SAM3XA_UART_COMPONENT_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h new file mode 100644 index 0000000..51b5fbd --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_uotghs.h @@ -0,0 +1,953 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_UOTGHS_COMPONENT_ +#define _SAM3XA_UOTGHS_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR USB On-The-Go Interface */ +/* ============================================================================= */ +/** \addtogroup SAM3XA_UOTGHS USB On-The-Go Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief UotghsDevdma hardware registers */ +typedef struct { + RwReg UOTGHS_DEVDMANXTDSC; /**< \brief (UotghsDevdma Offset: 0x0) Device DMA Channel Next Descriptor Address Register */ + RwReg UOTGHS_DEVDMAADDRESS; /**< \brief (UotghsDevdma Offset: 0x4) Device DMA Channel Address Register */ + RwReg UOTGHS_DEVDMACONTROL; /**< \brief (UotghsDevdma Offset: 0x8) Device DMA Channel Control Register */ + RwReg UOTGHS_DEVDMASTATUS; /**< \brief (UotghsDevdma Offset: 0xC) Device DMA Channel Status Register */ +} UotghsDevdma; +/** \brief UotghsHstdma hardware registers */ +typedef struct { + RwReg UOTGHS_HSTDMANXTDSC; /**< \brief (UotghsHstdma Offset: 0x0) Host DMA Channel Next Descriptor Address Register */ + RwReg UOTGHS_HSTDMAADDRESS; /**< \brief (UotghsHstdma Offset: 0x4) Host DMA Channel Address Register */ + RwReg UOTGHS_HSTDMACONTROL; /**< \brief (UotghsHstdma Offset: 0x8) Host DMA Channel Control Register */ + RwReg UOTGHS_HSTDMASTATUS; /**< \brief (UotghsHstdma Offset: 0xC) Host DMA Channel Status Register */ +} UotghsHstdma; +/** \brief Uotghs hardware registers */ +#define UOTGHSDEVDMA_NUMBER 7 +#define UOTGHSHSTDMA_NUMBER 7 +typedef struct { + RwReg UOTGHS_DEVCTRL; /**< \brief (Uotghs Offset: 0x0000) Device General Control Register */ + RoReg UOTGHS_DEVISR; /**< \brief (Uotghs Offset: 0x0004) Device Global Interrupt Status Register */ + WoReg UOTGHS_DEVICR; /**< \brief (Uotghs Offset: 0x0008) Device Global Interrupt Clear Register */ + WoReg UOTGHS_DEVIFR; /**< \brief (Uotghs Offset: 0x000C) Device Global Interrupt Set Register */ + RoReg UOTGHS_DEVIMR; /**< \brief (Uotghs Offset: 0x0010) Device Global Interrupt Mask Register */ + WoReg UOTGHS_DEVIDR; /**< \brief (Uotghs Offset: 0x0014) Device Global Interrupt Disable Register */ + WoReg UOTGHS_DEVIER; /**< \brief (Uotghs Offset: 0x0018) Device Global Interrupt Enable Register */ + RwReg UOTGHS_DEVEPT; /**< \brief (Uotghs Offset: 0x001C) Device Endpoint Register */ + RoReg UOTGHS_DEVFNUM; /**< \brief (Uotghs Offset: 0x0020) Device Frame Number Register */ + RoReg Reserved1[55]; + RwReg UOTGHS_DEVEPTCFG[10]; /**< \brief (Uotghs Offset: 0x100) Device Endpoint Configuration Register (n = 0) */ + RoReg Reserved2[2]; + RoReg UOTGHS_DEVEPTISR[10]; /**< \brief (Uotghs Offset: 0x130) Device Endpoint Status Register (n = 0) */ + RoReg Reserved3[2]; + WoReg UOTGHS_DEVEPTICR[10]; /**< \brief (Uotghs Offset: 0x160) Device Endpoint Clear Register (n = 0) */ + RoReg Reserved4[2]; + WoReg UOTGHS_DEVEPTIFR[10]; /**< \brief (Uotghs Offset: 0x190) Device Endpoint Set Register (n = 0) */ + RoReg Reserved5[2]; + RoReg UOTGHS_DEVEPTIMR[10]; /**< \brief (Uotghs Offset: 0x1C0) Device Endpoint Mask Register (n = 0) */ + RoReg Reserved6[2]; + WoReg UOTGHS_DEVEPTIER[10]; /**< \brief (Uotghs Offset: 0x1F0) Device Endpoint Enable Register (n = 0) */ + RoReg Reserved7[2]; + WoReg UOTGHS_DEVEPTIDR[10]; /**< \brief (Uotghs Offset: 0x220) Device Endpoint Disable Register (n = 0) */ + RoReg Reserved8[50]; + UotghsDevdma UOTGHS_DEVDMA[UOTGHSDEVDMA_NUMBER]; /**< \brief (Uotghs Offset: 0x310) n = 1 .. 7 */ + RoReg Reserved9[32]; + RwReg UOTGHS_HSTCTRL; /**< \brief (Uotghs Offset: 0x0400) Host General Control Register */ + RoReg UOTGHS_HSTISR; /**< \brief (Uotghs Offset: 0x0404) Host Global Interrupt Status Register */ + WoReg UOTGHS_HSTICR; /**< \brief (Uotghs Offset: 0x0408) Host Global Interrupt Clear Register */ + WoReg UOTGHS_HSTIFR; /**< \brief (Uotghs Offset: 0x040C) Host Global Interrupt Set Register */ + RoReg UOTGHS_HSTIMR; /**< \brief (Uotghs Offset: 0x0410) Host Global Interrupt Mask Register */ + WoReg UOTGHS_HSTIDR; /**< \brief (Uotghs Offset: 0x0414) Host Global Interrupt Disable Register */ + WoReg UOTGHS_HSTIER; /**< \brief (Uotghs Offset: 0x0418) Host Global Interrupt Enable Register */ + RwReg UOTGHS_HSTPIP; /**< \brief (Uotghs Offset: 0x0041C) Host Pipe Register */ + RwReg UOTGHS_HSTFNUM; /**< \brief (Uotghs Offset: 0x0420) Host Frame Number Register */ + RwReg UOTGHS_HSTADDR1; /**< \brief (Uotghs Offset: 0x0424) Host Address 1 Register */ + RwReg UOTGHS_HSTADDR2; /**< \brief (Uotghs Offset: 0x0428) Host Address 2 Register */ + RwReg UOTGHS_HSTADDR3; /**< \brief (Uotghs Offset: 0x042C) Host Address 3 Register */ + RoReg Reserved10[52]; + RwReg UOTGHS_HSTPIPCFG[10]; /**< \brief (Uotghs Offset: 0x500) Host Pipe Configuration Register (n = 0) */ + RoReg Reserved11[2]; + RoReg UOTGHS_HSTPIPISR[10]; /**< \brief (Uotghs Offset: 0x530) Host Pipe Status Register (n = 0) */ + RoReg Reserved12[2]; + WoReg UOTGHS_HSTPIPICR[10]; /**< \brief (Uotghs Offset: 0x560) Host Pipe Clear Register (n = 0) */ + RoReg Reserved13[2]; + WoReg UOTGHS_HSTPIPIFR[10]; /**< \brief (Uotghs Offset: 0x590) Host Pipe Set Register (n = 0) */ + RoReg Reserved14[2]; + RoReg UOTGHS_HSTPIPIMR[10]; /**< \brief (Uotghs Offset: 0x5C0) Host Pipe Mask Register (n = 0) */ + RoReg Reserved15[2]; + WoReg UOTGHS_HSTPIPIER[10]; /**< \brief (Uotghs Offset: 0x5F0) Host Pipe Enable Register (n = 0) */ + RoReg Reserved16[2]; + WoReg UOTGHS_HSTPIPIDR[10]; /**< \brief (Uotghs Offset: 0x620) Host Pipe Disable Register (n = 0) */ + RoReg Reserved17[2]; + RwReg UOTGHS_HSTPIPINRQ[10]; /**< \brief (Uotghs Offset: 0x650) Host Pipe IN Request Register (n = 0) */ + RoReg Reserved18[2]; + RwReg UOTGHS_HSTPIPERR[10]; /**< \brief (Uotghs Offset: 0x680) Host Pipe Error Register (n = 0) */ + RoReg Reserved19[26]; + UotghsHstdma UOTGHS_HSTDMA[UOTGHSHSTDMA_NUMBER]; /**< \brief (Uotghs Offset: 0x710) n = 1 .. 7 */ + RoReg Reserved20[32]; + RwReg UOTGHS_CTRL; /**< \brief (Uotghs Offset: 0x0800) General Control Register */ + RoReg UOTGHS_SR; /**< \brief (Uotghs Offset: 0x0804) General Status Register */ + WoReg UOTGHS_SCR; /**< \brief (Uotghs Offset: 0x0808) General Status Clear Register */ + WoReg UOTGHS_SFR; /**< \brief (Uotghs Offset: 0x080C) General Status Set Register */ + RoReg Reserved21[7]; + RoReg UOTGHS_FSM; /**< \brief (Uotghs Offset: 0x082C) General Finite State Machine Register */ +} Uotghs; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- UOTGHS_DEVCTRL : (UOTGHS Offset: 0x0000) Device General Control Register -------- */ +#define UOTGHS_DEVCTRL_UADD_Pos 0 +#define UOTGHS_DEVCTRL_UADD_Msk (0x7fu << UOTGHS_DEVCTRL_UADD_Pos) /**< \brief (UOTGHS_DEVCTRL) USB Address */ +#define UOTGHS_DEVCTRL_UADD(value) ((UOTGHS_DEVCTRL_UADD_Msk & ((value) << UOTGHS_DEVCTRL_UADD_Pos))) +#define UOTGHS_DEVCTRL_ADDEN (0x1u << 7) /**< \brief (UOTGHS_DEVCTRL) Address Enable */ +#define UOTGHS_DEVCTRL_DETACH (0x1u << 8) /**< \brief (UOTGHS_DEVCTRL) Detach */ +#define UOTGHS_DEVCTRL_RMWKUP (0x1u << 9) /**< \brief (UOTGHS_DEVCTRL) Remote Wake-Up */ +#define UOTGHS_DEVCTRL_SPDCONF_Pos 10 +#define UOTGHS_DEVCTRL_SPDCONF_Msk (0x3u << UOTGHS_DEVCTRL_SPDCONF_Pos) /**< \brief (UOTGHS_DEVCTRL) Mode Configuration */ +#define UOTGHS_DEVCTRL_SPDCONF_NORMAL (0x0u << 10) /**< \brief (UOTGHS_DEVCTRL) The peripheral starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the host is high-speed capable. */ +#define UOTGHS_DEVCTRL_SPDCONF_LOW_POWER (0x1u << 10) /**< \brief (UOTGHS_DEVCTRL) For a better consumption, if high-speed is not needed. */ +#define UOTGHS_DEVCTRL_SPDCONF_HIGH_SPEED (0x2u << 10) /**< \brief (UOTGHS_DEVCTRL) Forced high speed. */ +#define UOTGHS_DEVCTRL_SPDCONF_FORCED_FS (0x3u << 10) /**< \brief (UOTGHS_DEVCTRL) The peripheral remains in full-speed mode whatever the host speed capability. */ +#define UOTGHS_DEVCTRL_LS (0x1u << 12) /**< \brief (UOTGHS_DEVCTRL) Low-Speed Mode Force */ +#define UOTGHS_DEVCTRL_TSTJ (0x1u << 13) /**< \brief (UOTGHS_DEVCTRL) Test mode J */ +#define UOTGHS_DEVCTRL_TSTK (0x1u << 14) /**< \brief (UOTGHS_DEVCTRL) Test mode K */ +#define UOTGHS_DEVCTRL_TSTPCKT (0x1u << 15) /**< \brief (UOTGHS_DEVCTRL) Test packet mode */ +#define UOTGHS_DEVCTRL_OPMODE2 (0x1u << 16) /**< \brief (UOTGHS_DEVCTRL) Specific Operational mode */ +/* -------- UOTGHS_DEVISR : (UOTGHS Offset: 0x0004) Device Global Interrupt Status Register -------- */ +#define UOTGHS_DEVISR_SUSP (0x1u << 0) /**< \brief (UOTGHS_DEVISR) Suspend Interrupt */ +#define UOTGHS_DEVISR_MSOF (0x1u << 1) /**< \brief (UOTGHS_DEVISR) Micro Start of Frame Interrupt */ +#define UOTGHS_DEVISR_SOF (0x1u << 2) /**< \brief (UOTGHS_DEVISR) Start of Frame Interrupt */ +#define UOTGHS_DEVISR_EORST (0x1u << 3) /**< \brief (UOTGHS_DEVISR) End of Reset Interrupt */ +#define UOTGHS_DEVISR_WAKEUP (0x1u << 4) /**< \brief (UOTGHS_DEVISR) Wake-Up Interrupt */ +#define UOTGHS_DEVISR_EORSM (0x1u << 5) /**< \brief (UOTGHS_DEVISR) End of Resume Interrupt */ +#define UOTGHS_DEVISR_UPRSM (0x1u << 6) /**< \brief (UOTGHS_DEVISR) Upstream Resume Interrupt */ +#define UOTGHS_DEVISR_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVISR) Endpoint 0 Interrupt */ +#define UOTGHS_DEVISR_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVISR) Endpoint 1 Interrupt */ +#define UOTGHS_DEVISR_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVISR) Endpoint 2 Interrupt */ +#define UOTGHS_DEVISR_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVISR) Endpoint 3 Interrupt */ +#define UOTGHS_DEVISR_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVISR) Endpoint 4 Interrupt */ +#define UOTGHS_DEVISR_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVISR) Endpoint 5 Interrupt */ +#define UOTGHS_DEVISR_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVISR) Endpoint 6 Interrupt */ +#define UOTGHS_DEVISR_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVISR) Endpoint 7 Interrupt */ +#define UOTGHS_DEVISR_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVISR) Endpoint 8 Interrupt */ +#define UOTGHS_DEVISR_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVISR) Endpoint 9 Interrupt */ +#define UOTGHS_DEVISR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVISR) DMA Channel 1 Interrupt */ +#define UOTGHS_DEVISR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVISR) DMA Channel 2 Interrupt */ +#define UOTGHS_DEVISR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVISR) DMA Channel 3 Interrupt */ +#define UOTGHS_DEVISR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVISR) DMA Channel 4 Interrupt */ +#define UOTGHS_DEVISR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVISR) DMA Channel 5 Interrupt */ +#define UOTGHS_DEVISR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVISR) DMA Channel 6 Interrupt */ +/* -------- UOTGHS_DEVICR : (UOTGHS Offset: 0x0008) Device Global Interrupt Clear Register -------- */ +#define UOTGHS_DEVICR_SUSPC (0x1u << 0) /**< \brief (UOTGHS_DEVICR) Suspend Interrupt Clear */ +#define UOTGHS_DEVICR_MSOFC (0x1u << 1) /**< \brief (UOTGHS_DEVICR) Micro Start of Frame Interrupt Clear */ +#define UOTGHS_DEVICR_SOFC (0x1u << 2) /**< \brief (UOTGHS_DEVICR) Start of Frame Interrupt Clear */ +#define UOTGHS_DEVICR_EORSTC (0x1u << 3) /**< \brief (UOTGHS_DEVICR) End of Reset Interrupt Clear */ +#define UOTGHS_DEVICR_WAKEUPC (0x1u << 4) /**< \brief (UOTGHS_DEVICR) Wake-Up Interrupt Clear */ +#define UOTGHS_DEVICR_EORSMC (0x1u << 5) /**< \brief (UOTGHS_DEVICR) End of Resume Interrupt Clear */ +#define UOTGHS_DEVICR_UPRSMC (0x1u << 6) /**< \brief (UOTGHS_DEVICR) Upstream Resume Interrupt Clear */ +/* -------- UOTGHS_DEVIFR : (UOTGHS Offset: 0x000C) Device Global Interrupt Set Register -------- */ +#define UOTGHS_DEVIFR_SUSPS (0x1u << 0) /**< \brief (UOTGHS_DEVIFR) Suspend Interrupt Set */ +#define UOTGHS_DEVIFR_MSOFS (0x1u << 1) /**< \brief (UOTGHS_DEVIFR) Micro Start of Frame Interrupt Set */ +#define UOTGHS_DEVIFR_SOFS (0x1u << 2) /**< \brief (UOTGHS_DEVIFR) Start of Frame Interrupt Set */ +#define UOTGHS_DEVIFR_EORSTS (0x1u << 3) /**< \brief (UOTGHS_DEVIFR) End of Reset Interrupt Set */ +#define UOTGHS_DEVIFR_WAKEUPS (0x1u << 4) /**< \brief (UOTGHS_DEVIFR) Wake-Up Interrupt Set */ +#define UOTGHS_DEVIFR_EORSMS (0x1u << 5) /**< \brief (UOTGHS_DEVIFR) End of Resume Interrupt Set */ +#define UOTGHS_DEVIFR_UPRSMS (0x1u << 6) /**< \brief (UOTGHS_DEVIFR) Upstream Resume Interrupt Set */ +#define UOTGHS_DEVIFR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIFR) DMA Channel 1 Interrupt Set */ +#define UOTGHS_DEVIFR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIFR) DMA Channel 2 Interrupt Set */ +#define UOTGHS_DEVIFR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIFR) DMA Channel 3 Interrupt Set */ +#define UOTGHS_DEVIFR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIFR) DMA Channel 4 Interrupt Set */ +#define UOTGHS_DEVIFR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIFR) DMA Channel 5 Interrupt Set */ +#define UOTGHS_DEVIFR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIFR) DMA Channel 6 Interrupt Set */ +/* -------- UOTGHS_DEVIMR : (UOTGHS Offset: 0x0010) Device Global Interrupt Mask Register -------- */ +#define UOTGHS_DEVIMR_SUSPE (0x1u << 0) /**< \brief (UOTGHS_DEVIMR) Suspend Interrupt Mask */ +#define UOTGHS_DEVIMR_MSOFE (0x1u << 1) /**< \brief (UOTGHS_DEVIMR) Micro Start of Frame Interrupt Mask */ +#define UOTGHS_DEVIMR_SOFE (0x1u << 2) /**< \brief (UOTGHS_DEVIMR) Start of Frame Interrupt Mask */ +#define UOTGHS_DEVIMR_EORSTE (0x1u << 3) /**< \brief (UOTGHS_DEVIMR) End of Reset Interrupt Mask */ +#define UOTGHS_DEVIMR_WAKEUPE (0x1u << 4) /**< \brief (UOTGHS_DEVIMR) Wake-Up Interrupt Mask */ +#define UOTGHS_DEVIMR_EORSME (0x1u << 5) /**< \brief (UOTGHS_DEVIMR) End of Resume Interrupt Mask */ +#define UOTGHS_DEVIMR_UPRSME (0x1u << 6) /**< \brief (UOTGHS_DEVIMR) Upstream Resume Interrupt Mask */ +#define UOTGHS_DEVIMR_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVIMR) Endpoint 0 Interrupt Mask */ +#define UOTGHS_DEVIMR_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVIMR) Endpoint 1 Interrupt Mask */ +#define UOTGHS_DEVIMR_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVIMR) Endpoint 2 Interrupt Mask */ +#define UOTGHS_DEVIMR_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVIMR) Endpoint 3 Interrupt Mask */ +#define UOTGHS_DEVIMR_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVIMR) Endpoint 4 Interrupt Mask */ +#define UOTGHS_DEVIMR_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVIMR) Endpoint 5 Interrupt Mask */ +#define UOTGHS_DEVIMR_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVIMR) Endpoint 6 Interrupt Mask */ +#define UOTGHS_DEVIMR_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVIMR) Endpoint 7 Interrupt Mask */ +#define UOTGHS_DEVIMR_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVIMR) Endpoint 8 Interrupt Mask */ +#define UOTGHS_DEVIMR_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVIMR) Endpoint 9 Interrupt Mask */ +#define UOTGHS_DEVIMR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIMR) DMA Channel 1 Interrupt Mask */ +#define UOTGHS_DEVIMR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIMR) DMA Channel 2 Interrupt Mask */ +#define UOTGHS_DEVIMR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIMR) DMA Channel 3 Interrupt Mask */ +#define UOTGHS_DEVIMR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIMR) DMA Channel 4 Interrupt Mask */ +#define UOTGHS_DEVIMR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIMR) DMA Channel 5 Interrupt Mask */ +#define UOTGHS_DEVIMR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIMR) DMA Channel 6 Interrupt Mask */ +/* -------- UOTGHS_DEVIDR : (UOTGHS Offset: 0x0014) Device Global Interrupt Disable Register -------- */ +#define UOTGHS_DEVIDR_SUSPEC (0x1u << 0) /**< \brief (UOTGHS_DEVIDR) Suspend Interrupt Disable */ +#define UOTGHS_DEVIDR_MSOFEC (0x1u << 1) /**< \brief (UOTGHS_DEVIDR) Micro Start of Frame Interrupt Disable */ +#define UOTGHS_DEVIDR_SOFEC (0x1u << 2) /**< \brief (UOTGHS_DEVIDR) Start of Frame Interrupt Disable */ +#define UOTGHS_DEVIDR_EORSTEC (0x1u << 3) /**< \brief (UOTGHS_DEVIDR) End of Reset Interrupt Disable */ +#define UOTGHS_DEVIDR_WAKEUPEC (0x1u << 4) /**< \brief (UOTGHS_DEVIDR) Wake-Up Interrupt Disable */ +#define UOTGHS_DEVIDR_EORSMEC (0x1u << 5) /**< \brief (UOTGHS_DEVIDR) End of Resume Interrupt Disable */ +#define UOTGHS_DEVIDR_UPRSMEC (0x1u << 6) /**< \brief (UOTGHS_DEVIDR) Upstream Resume Interrupt Disable */ +#define UOTGHS_DEVIDR_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVIDR) Endpoint 0 Interrupt Disable */ +#define UOTGHS_DEVIDR_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVIDR) Endpoint 1 Interrupt Disable */ +#define UOTGHS_DEVIDR_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVIDR) Endpoint 2 Interrupt Disable */ +#define UOTGHS_DEVIDR_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVIDR) Endpoint 3 Interrupt Disable */ +#define UOTGHS_DEVIDR_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVIDR) Endpoint 4 Interrupt Disable */ +#define UOTGHS_DEVIDR_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVIDR) Endpoint 5 Interrupt Disable */ +#define UOTGHS_DEVIDR_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVIDR) Endpoint 6 Interrupt Disable */ +#define UOTGHS_DEVIDR_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVIDR) Endpoint 7 Interrupt Disable */ +#define UOTGHS_DEVIDR_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVIDR) Endpoint 8 Interrupt Disable */ +#define UOTGHS_DEVIDR_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVIDR) Endpoint 9 Interrupt Disable */ +#define UOTGHS_DEVIDR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIDR) DMA Channel 1 Interrupt Disable */ +#define UOTGHS_DEVIDR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIDR) DMA Channel 2 Interrupt Disable */ +#define UOTGHS_DEVIDR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIDR) DMA Channel 3 Interrupt Disable */ +#define UOTGHS_DEVIDR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIDR) DMA Channel 4 Interrupt Disable */ +#define UOTGHS_DEVIDR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIDR) DMA Channel 5 Interrupt Disable */ +#define UOTGHS_DEVIDR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIDR) DMA Channel 6 Interrupt Disable */ +/* -------- UOTGHS_DEVIER : (UOTGHS Offset: 0x0018) Device Global Interrupt Enable Register -------- */ +#define UOTGHS_DEVIER_SUSPES (0x1u << 0) /**< \brief (UOTGHS_DEVIER) Suspend Interrupt Enable */ +#define UOTGHS_DEVIER_MSOFES (0x1u << 1) /**< \brief (UOTGHS_DEVIER) Micro Start of Frame Interrupt Enable */ +#define UOTGHS_DEVIER_SOFES (0x1u << 2) /**< \brief (UOTGHS_DEVIER) Start of Frame Interrupt Enable */ +#define UOTGHS_DEVIER_EORSTES (0x1u << 3) /**< \brief (UOTGHS_DEVIER) End of Reset Interrupt Enable */ +#define UOTGHS_DEVIER_WAKEUPES (0x1u << 4) /**< \brief (UOTGHS_DEVIER) Wake-Up Interrupt Enable */ +#define UOTGHS_DEVIER_EORSMES (0x1u << 5) /**< \brief (UOTGHS_DEVIER) End of Resume Interrupt Enable */ +#define UOTGHS_DEVIER_UPRSMES (0x1u << 6) /**< \brief (UOTGHS_DEVIER) Upstream Resume Interrupt Enable */ +#define UOTGHS_DEVIER_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVIER) Endpoint 0 Interrupt Enable */ +#define UOTGHS_DEVIER_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVIER) Endpoint 1 Interrupt Enable */ +#define UOTGHS_DEVIER_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVIER) Endpoint 2 Interrupt Enable */ +#define UOTGHS_DEVIER_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVIER) Endpoint 3 Interrupt Enable */ +#define UOTGHS_DEVIER_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVIER) Endpoint 4 Interrupt Enable */ +#define UOTGHS_DEVIER_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVIER) Endpoint 5 Interrupt Enable */ +#define UOTGHS_DEVIER_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVIER) Endpoint 6 Interrupt Enable */ +#define UOTGHS_DEVIER_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVIER) Endpoint 7 Interrupt Enable */ +#define UOTGHS_DEVIER_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVIER) Endpoint 8 Interrupt Enable */ +#define UOTGHS_DEVIER_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVIER) Endpoint 9 Interrupt Enable */ +#define UOTGHS_DEVIER_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIER) DMA Channel 1 Interrupt Enable */ +#define UOTGHS_DEVIER_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIER) DMA Channel 2 Interrupt Enable */ +#define UOTGHS_DEVIER_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIER) DMA Channel 3 Interrupt Enable */ +#define UOTGHS_DEVIER_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIER) DMA Channel 4 Interrupt Enable */ +#define UOTGHS_DEVIER_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIER) DMA Channel 5 Interrupt Enable */ +#define UOTGHS_DEVIER_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIER) DMA Channel 6 Interrupt Enable */ +/* -------- UOTGHS_DEVEPT : (UOTGHS Offset: 0x001C) Device Endpoint Register -------- */ +#define UOTGHS_DEVEPT_EPEN0 (0x1u << 0) /**< \brief (UOTGHS_DEVEPT) Endpoint 0 Enable */ +#define UOTGHS_DEVEPT_EPEN1 (0x1u << 1) /**< \brief (UOTGHS_DEVEPT) Endpoint 1 Enable */ +#define UOTGHS_DEVEPT_EPEN2 (0x1u << 2) /**< \brief (UOTGHS_DEVEPT) Endpoint 2 Enable */ +#define UOTGHS_DEVEPT_EPEN3 (0x1u << 3) /**< \brief (UOTGHS_DEVEPT) Endpoint 3 Enable */ +#define UOTGHS_DEVEPT_EPEN4 (0x1u << 4) /**< \brief (UOTGHS_DEVEPT) Endpoint 4 Enable */ +#define UOTGHS_DEVEPT_EPEN5 (0x1u << 5) /**< \brief (UOTGHS_DEVEPT) Endpoint 5 Enable */ +#define UOTGHS_DEVEPT_EPEN6 (0x1u << 6) /**< \brief (UOTGHS_DEVEPT) Endpoint 6 Enable */ +#define UOTGHS_DEVEPT_EPEN7 (0x1u << 7) /**< \brief (UOTGHS_DEVEPT) Endpoint 7 Enable */ +#define UOTGHS_DEVEPT_EPEN8 (0x1u << 8) /**< \brief (UOTGHS_DEVEPT) Endpoint 8 Enable */ +#define UOTGHS_DEVEPT_EPRST0 (0x1u << 16) /**< \brief (UOTGHS_DEVEPT) Endpoint 0 Reset */ +#define UOTGHS_DEVEPT_EPRST1 (0x1u << 17) /**< \brief (UOTGHS_DEVEPT) Endpoint 1 Reset */ +#define UOTGHS_DEVEPT_EPRST2 (0x1u << 18) /**< \brief (UOTGHS_DEVEPT) Endpoint 2 Reset */ +#define UOTGHS_DEVEPT_EPRST3 (0x1u << 19) /**< \brief (UOTGHS_DEVEPT) Endpoint 3 Reset */ +#define UOTGHS_DEVEPT_EPRST4 (0x1u << 20) /**< \brief (UOTGHS_DEVEPT) Endpoint 4 Reset */ +#define UOTGHS_DEVEPT_EPRST5 (0x1u << 21) /**< \brief (UOTGHS_DEVEPT) Endpoint 5 Reset */ +#define UOTGHS_DEVEPT_EPRST6 (0x1u << 22) /**< \brief (UOTGHS_DEVEPT) Endpoint 6 Reset */ +#define UOTGHS_DEVEPT_EPRST7 (0x1u << 23) /**< \brief (UOTGHS_DEVEPT) Endpoint 7 Reset */ +#define UOTGHS_DEVEPT_EPRST8 (0x1u << 24) /**< \brief (UOTGHS_DEVEPT) Endpoint 8 Reset */ +/* -------- UOTGHS_DEVFNUM : (UOTGHS Offset: 0x0020) Device Frame Number Register -------- */ +#define UOTGHS_DEVFNUM_MFNUM_Pos 0 +#define UOTGHS_DEVFNUM_MFNUM_Msk (0x7u << UOTGHS_DEVFNUM_MFNUM_Pos) /**< \brief (UOTGHS_DEVFNUM) Micro Frame Number */ +#define UOTGHS_DEVFNUM_FNUM_Pos 3 +#define UOTGHS_DEVFNUM_FNUM_Msk (0x7ffu << UOTGHS_DEVFNUM_FNUM_Pos) /**< \brief (UOTGHS_DEVFNUM) Frame Number */ +#define UOTGHS_DEVFNUM_FNCERR (0x1u << 15) /**< \brief (UOTGHS_DEVFNUM) Frame Number CRC Error */ +/* -------- UOTGHS_DEVEPTCFG[10] : (UOTGHS Offset: 0x100) Device Endpoint Configuration Register (n = 0) -------- */ +#define UOTGHS_DEVEPTCFG_ALLOC (0x1u << 1) /**< \brief (UOTGHS_DEVEPTCFG[10]) Endpoint Memory Allocate */ +#define UOTGHS_DEVEPTCFG_EPBK_Pos 2 +#define UOTGHS_DEVEPTCFG_EPBK_Msk (0x3u << UOTGHS_DEVEPTCFG_EPBK_Pos) /**< \brief (UOTGHS_DEVEPTCFG[10]) Endpoint Banks */ +#define UOTGHS_DEVEPTCFG_EPBK_1_BANK (0x0u << 2) /**< \brief (UOTGHS_DEVEPTCFG[10]) Single-bank endpoint */ +#define UOTGHS_DEVEPTCFG_EPBK_2_BANK (0x1u << 2) /**< \brief (UOTGHS_DEVEPTCFG[10]) Double-bank endpoint */ +#define UOTGHS_DEVEPTCFG_EPBK_3_BANK (0x2u << 2) /**< \brief (UOTGHS_DEVEPTCFG[10]) Triple-bank endpoint */ +#define UOTGHS_DEVEPTCFG_EPSIZE_Pos 4 +#define UOTGHS_DEVEPTCFG_EPSIZE_Msk (0x7u << UOTGHS_DEVEPTCFG_EPSIZE_Pos) /**< \brief (UOTGHS_DEVEPTCFG[10]) Endpoint Size */ +#define UOTGHS_DEVEPTCFG_EPSIZE_8_BYTE (0x0u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 8 bytes */ +#define UOTGHS_DEVEPTCFG_EPSIZE_16_BYTE (0x1u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 16 bytes */ +#define UOTGHS_DEVEPTCFG_EPSIZE_32_BYTE (0x2u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 32 bytes */ +#define UOTGHS_DEVEPTCFG_EPSIZE_64_BYTE (0x3u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 64 bytes */ +#define UOTGHS_DEVEPTCFG_EPSIZE_128_BYTE (0x4u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 128 bytes */ +#define UOTGHS_DEVEPTCFG_EPSIZE_256_BYTE (0x5u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 256 bytes */ +#define UOTGHS_DEVEPTCFG_EPSIZE_512_BYTE (0x6u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 512 bytes */ +#define UOTGHS_DEVEPTCFG_EPSIZE_1024_BYTE (0x7u << 4) /**< \brief (UOTGHS_DEVEPTCFG[10]) 1024 bytes */ +#define UOTGHS_DEVEPTCFG_EPDIR (0x1u << 8) /**< \brief (UOTGHS_DEVEPTCFG[10]) Endpoint Direction */ +#define UOTGHS_DEVEPTCFG_EPDIR_OUT (0x0u << 8) /**< \brief (UOTGHS_DEVEPTCFG[10]) The endpoint direction is OUT. */ +#define UOTGHS_DEVEPTCFG_EPDIR_IN (0x1u << 8) /**< \brief (UOTGHS_DEVEPTCFG[10]) The endpoint direction is IN (nor for control endpoints). */ +#define UOTGHS_DEVEPTCFG_AUTOSW (0x1u << 9) /**< \brief (UOTGHS_DEVEPTCFG[10]) Automatic Switch */ +#define UOTGHS_DEVEPTCFG_EPTYPE_Pos 11 +#define UOTGHS_DEVEPTCFG_EPTYPE_Msk (0x3u << UOTGHS_DEVEPTCFG_EPTYPE_Pos) /**< \brief (UOTGHS_DEVEPTCFG[10]) Endpoint Type */ +#define UOTGHS_DEVEPTCFG_EPTYPE_CTRL (0x0u << 11) /**< \brief (UOTGHS_DEVEPTCFG[10]) Control */ +#define UOTGHS_DEVEPTCFG_EPTYPE_ISO (0x1u << 11) /**< \brief (UOTGHS_DEVEPTCFG[10]) Isochronous */ +#define UOTGHS_DEVEPTCFG_EPTYPE_BLK (0x2u << 11) /**< \brief (UOTGHS_DEVEPTCFG[10]) Bulk */ +#define UOTGHS_DEVEPTCFG_EPTYPE_INTRPT (0x3u << 11) /**< \brief (UOTGHS_DEVEPTCFG[10]) Interrupt */ +#define UOTGHS_DEVEPTCFG_NBTRANS_Pos 13 +#define UOTGHS_DEVEPTCFG_NBTRANS_Msk (0x3u << UOTGHS_DEVEPTCFG_NBTRANS_Pos) /**< \brief (UOTGHS_DEVEPTCFG[10]) Number of transaction per microframe for isochronous endpoint */ +#define UOTGHS_DEVEPTCFG_NBTRANS_0_TRANS (0x0u << 13) /**< \brief (UOTGHS_DEVEPTCFG[10]) reserved to endpoint that does not have the high-bandwidth isochronous capability. */ +#define UOTGHS_DEVEPTCFG_NBTRANS_1_TRANS (0x1u << 13) /**< \brief (UOTGHS_DEVEPTCFG[10]) default value: one transaction per micro-frame. */ +#define UOTGHS_DEVEPTCFG_NBTRANS_2_TRANS (0x2u << 13) /**< \brief (UOTGHS_DEVEPTCFG[10]) 2 transactions per micro-frame. This endpoint should be configured as double-bank. */ +#define UOTGHS_DEVEPTCFG_NBTRANS_3_TRANS (0x3u << 13) /**< \brief (UOTGHS_DEVEPTCFG[10]) 3 transactions per micro-frame. This endpoint should be configured as triple-bank. */ +/* -------- UOTGHS_DEVEPTISR[10] : (UOTGHS Offset: 0x130) Device Endpoint Status Register (n = 0) -------- */ +#define UOTGHS_DEVEPTISR_TXINI (0x1u << 0) /**< \brief (UOTGHS_DEVEPTISR[10]) Transmitted IN Data Interrupt */ +#define UOTGHS_DEVEPTISR_RXOUTI (0x1u << 1) /**< \brief (UOTGHS_DEVEPTISR[10]) Received OUT Data Interrupt */ +#define UOTGHS_DEVEPTISR_RXSTPI (0x1u << 2) /**< \brief (UOTGHS_DEVEPTISR[10]) Received SETUP Interrupt */ +#define UOTGHS_DEVEPTISR_UNDERFI (0x1u << 2) /**< \brief (UOTGHS_DEVEPTISR[10]) Underflow Interrupt */ +#define UOTGHS_DEVEPTISR_NAKOUTI (0x1u << 3) /**< \brief (UOTGHS_DEVEPTISR[10]) NAKed OUT Interrupt */ +#define UOTGHS_DEVEPTISR_HBISOINERRI (0x1u << 3) /**< \brief (UOTGHS_DEVEPTISR[10]) High bandwidth isochronous IN Underflow Error Interrupt */ +#define UOTGHS_DEVEPTISR_NAKINI (0x1u << 4) /**< \brief (UOTGHS_DEVEPTISR[10]) NAKed IN Interrupt */ +#define UOTGHS_DEVEPTISR_HBISOFLUSHI (0x1u << 4) /**< \brief (UOTGHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Flush Interrupt */ +#define UOTGHS_DEVEPTISR_OVERFI (0x1u << 5) /**< \brief (UOTGHS_DEVEPTISR[10]) Overflow Interrupt */ +#define UOTGHS_DEVEPTISR_STALLEDI (0x1u << 6) /**< \brief (UOTGHS_DEVEPTISR[10]) STALLed Interrupt */ +#define UOTGHS_DEVEPTISR_CRCERRI (0x1u << 6) /**< \brief (UOTGHS_DEVEPTISR[10]) CRC Error Interrupt */ +#define UOTGHS_DEVEPTISR_SHORTPACKET (0x1u << 7) /**< \brief (UOTGHS_DEVEPTISR[10]) Short Packet Interrupt */ +#define UOTGHS_DEVEPTISR_DTSEQ_Pos 8 +#define UOTGHS_DEVEPTISR_DTSEQ_Msk (0x3u << UOTGHS_DEVEPTISR_DTSEQ_Pos) /**< \brief (UOTGHS_DEVEPTISR[10]) Data Toggle Sequence */ +#define UOTGHS_DEVEPTISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (UOTGHS_DEVEPTISR[10]) Data0 toggle sequence */ +#define UOTGHS_DEVEPTISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (UOTGHS_DEVEPTISR[10]) Data1 toggle sequence */ +#define UOTGHS_DEVEPTISR_DTSEQ_DATA2 (0x2u << 8) /**< \brief (UOTGHS_DEVEPTISR[10]) Data2 toggle sequence (for high-bandwidth isochronous endpoint) */ +#define UOTGHS_DEVEPTISR_DTSEQ_MDATA (0x3u << 8) /**< \brief (UOTGHS_DEVEPTISR[10]) MData toggle sequence (for high-bandwidth isochronous endpoint) */ +#define UOTGHS_DEVEPTISR_ERRORTRANS (0x1u << 10) /**< \brief (UOTGHS_DEVEPTISR[10]) High-bandwidth isochronous OUT endpoint transaction error Interrupt */ +#define UOTGHS_DEVEPTISR_NBUSYBK_Pos 12 +#define UOTGHS_DEVEPTISR_NBUSYBK_Msk (0x3u << UOTGHS_DEVEPTISR_NBUSYBK_Pos) /**< \brief (UOTGHS_DEVEPTISR[10]) Number of Busy Banks */ +#define UOTGHS_DEVEPTISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (UOTGHS_DEVEPTISR[10]) 0 busy bank (all banks free) */ +#define UOTGHS_DEVEPTISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (UOTGHS_DEVEPTISR[10]) 1 busy bank */ +#define UOTGHS_DEVEPTISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (UOTGHS_DEVEPTISR[10]) 2 busy banks */ +#define UOTGHS_DEVEPTISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (UOTGHS_DEVEPTISR[10]) 3 busy banks */ +#define UOTGHS_DEVEPTISR_CURRBK_Pos 14 +#define UOTGHS_DEVEPTISR_CURRBK_Msk (0x3u << UOTGHS_DEVEPTISR_CURRBK_Pos) /**< \brief (UOTGHS_DEVEPTISR[10]) Current Bank */ +#define UOTGHS_DEVEPTISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (UOTGHS_DEVEPTISR[10]) Current bank is bank0 */ +#define UOTGHS_DEVEPTISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (UOTGHS_DEVEPTISR[10]) Current bank is bank1 */ +#define UOTGHS_DEVEPTISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (UOTGHS_DEVEPTISR[10]) Current bank is bank2 */ +#define UOTGHS_DEVEPTISR_RWALL (0x1u << 16) /**< \brief (UOTGHS_DEVEPTISR[10]) Read-write Allowed */ +#define UOTGHS_DEVEPTISR_CTRLDIR (0x1u << 17) /**< \brief (UOTGHS_DEVEPTISR[10]) Control Direction */ +#define UOTGHS_DEVEPTISR_CFGOK (0x1u << 18) /**< \brief (UOTGHS_DEVEPTISR[10]) Configuration OK Status */ +#define UOTGHS_DEVEPTISR_BYCT_Pos 20 +#define UOTGHS_DEVEPTISR_BYCT_Msk (0x7ffu << UOTGHS_DEVEPTISR_BYCT_Pos) /**< \brief (UOTGHS_DEVEPTISR[10]) Byte Count */ +/* -------- UOTGHS_DEVEPTICR[10] : (UOTGHS Offset: 0x160) Device Endpoint Clear Register (n = 0) -------- */ +#define UOTGHS_DEVEPTICR_TXINIC (0x1u << 0) /**< \brief (UOTGHS_DEVEPTICR[10]) Transmitted IN Data Interrupt Clear */ +#define UOTGHS_DEVEPTICR_RXOUTIC (0x1u << 1) /**< \brief (UOTGHS_DEVEPTICR[10]) Received OUT Data Interrupt Clear */ +#define UOTGHS_DEVEPTICR_RXSTPIC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTICR[10]) Received SETUP Interrupt Clear */ +#define UOTGHS_DEVEPTICR_UNDERFIC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTICR[10]) Underflow Interrupt Clear */ +#define UOTGHS_DEVEPTICR_NAKOUTIC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTICR[10]) NAKed OUT Interrupt Clear */ +#define UOTGHS_DEVEPTICR_HBISOINERRIC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTICR[10]) High bandwidth isochronous IN Underflow Error Interrupt Clear */ +#define UOTGHS_DEVEPTICR_NAKINIC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTICR[10]) NAKed IN Interrupt Clear */ +#define UOTGHS_DEVEPTICR_HBISOFLUSHIC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */ +#define UOTGHS_DEVEPTICR_OVERFIC (0x1u << 5) /**< \brief (UOTGHS_DEVEPTICR[10]) Overflow Interrupt Clear */ +#define UOTGHS_DEVEPTICR_STALLEDIC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTICR[10]) STALLed Interrupt Clear */ +#define UOTGHS_DEVEPTICR_CRCERRIC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTICR[10]) CRC Error Interrupt Clear */ +#define UOTGHS_DEVEPTICR_SHORTPACKETC (0x1u << 7) /**< \brief (UOTGHS_DEVEPTICR[10]) Short Packet Interrupt Clear */ +/* -------- UOTGHS_DEVEPTIFR[10] : (UOTGHS Offset: 0x190) Device Endpoint Set Register (n = 0) -------- */ +#define UOTGHS_DEVEPTIFR_TXINIS (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIFR[10]) Transmitted IN Data Interrupt Set */ +#define UOTGHS_DEVEPTIFR_RXOUTIS (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIFR[10]) Received OUT Data Interrupt Set */ +#define UOTGHS_DEVEPTIFR_RXSTPIS (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIFR[10]) Received SETUP Interrupt Set */ +#define UOTGHS_DEVEPTIFR_UNDERFIS (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIFR[10]) Underflow Interrupt Set */ +#define UOTGHS_DEVEPTIFR_NAKOUTIS (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIFR[10]) NAKed OUT Interrupt Set */ +#define UOTGHS_DEVEPTIFR_HBISOINERRIS (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIFR[10]) High bandwidth isochronous IN Underflow Error Interrupt Set */ +#define UOTGHS_DEVEPTIFR_NAKINIS (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIFR[10]) NAKed IN Interrupt Set */ +#define UOTGHS_DEVEPTIFR_HBISOFLUSHIS (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Flush Interrupt Set */ +#define UOTGHS_DEVEPTIFR_OVERFIS (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIFR[10]) Overflow Interrupt Set */ +#define UOTGHS_DEVEPTIFR_STALLEDIS (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIFR[10]) STALLed Interrupt Set */ +#define UOTGHS_DEVEPTIFR_CRCERRIS (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIFR[10]) CRC Error Interrupt Set */ +#define UOTGHS_DEVEPTIFR_SHORTPACKETS (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIFR[10]) Short Packet Interrupt Set */ +#define UOTGHS_DEVEPTIFR_NBUSYBKS (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIFR[10]) Number of Busy Banks Interrupt Set */ +/* -------- UOTGHS_DEVEPTIMR[10] : (UOTGHS Offset: 0x1C0) Device Endpoint Mask Register (n = 0) -------- */ +#define UOTGHS_DEVEPTIMR_TXINE (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIMR[10]) Transmitted IN Data Interrupt */ +#define UOTGHS_DEVEPTIMR_RXOUTE (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIMR[10]) Received OUT Data Interrupt */ +#define UOTGHS_DEVEPTIMR_RXSTPE (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIMR[10]) Received SETUP Interrupt */ +#define UOTGHS_DEVEPTIMR_UNDERFE (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIMR[10]) Underflow Interrupt */ +#define UOTGHS_DEVEPTIMR_NAKOUTE (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIMR[10]) NAKed OUT Interrupt */ +#define UOTGHS_DEVEPTIMR_HBISOINERRE (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Error Interrupt */ +#define UOTGHS_DEVEPTIMR_NAKINE (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIMR[10]) NAKed IN Interrupt */ +#define UOTGHS_DEVEPTIMR_HBISOFLUSHE (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Flush Interrupt */ +#define UOTGHS_DEVEPTIMR_OVERFE (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIMR[10]) Overflow Interrupt */ +#define UOTGHS_DEVEPTIMR_STALLEDE (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIMR[10]) STALLed Interrupt */ +#define UOTGHS_DEVEPTIMR_CRCERRE (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIMR[10]) CRC Error Interrupt */ +#define UOTGHS_DEVEPTIMR_SHORTPACKETE (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIMR[10]) Short Packet Interrupt */ +#define UOTGHS_DEVEPTIMR_MDATAE (0x1u << 8) /**< \brief (UOTGHS_DEVEPTIMR[10]) MData Interrupt */ +#define UOTGHS_DEVEPTIMR_DATAXE (0x1u << 9) /**< \brief (UOTGHS_DEVEPTIMR[10]) DataX Interrupt */ +#define UOTGHS_DEVEPTIMR_ERRORTRANSE (0x1u << 10) /**< \brief (UOTGHS_DEVEPTIMR[10]) Transaction Error Interrupt */ +#define UOTGHS_DEVEPTIMR_NBUSYBKE (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIMR[10]) Number of Busy Banks Interrupt */ +#define UOTGHS_DEVEPTIMR_KILLBK (0x1u << 13) /**< \brief (UOTGHS_DEVEPTIMR[10]) Kill IN Bank */ +#define UOTGHS_DEVEPTIMR_FIFOCON (0x1u << 14) /**< \brief (UOTGHS_DEVEPTIMR[10]) FIFO Control */ +#define UOTGHS_DEVEPTIMR_EPDISHDMA (0x1u << 16) /**< \brief (UOTGHS_DEVEPTIMR[10]) Endpoint Interrupts Disable HDMA Request */ +#define UOTGHS_DEVEPTIMR_NYETDIS (0x1u << 17) /**< \brief (UOTGHS_DEVEPTIMR[10]) NYET Token Disable */ +#define UOTGHS_DEVEPTIMR_RSTDT (0x1u << 18) /**< \brief (UOTGHS_DEVEPTIMR[10]) Reset Data Toggle */ +#define UOTGHS_DEVEPTIMR_STALLRQ (0x1u << 19) /**< \brief (UOTGHS_DEVEPTIMR[10]) STALL Request */ +/* -------- UOTGHS_DEVEPTIER[10] : (UOTGHS Offset: 0x1F0) Device Endpoint Enable Register (n = 0) -------- */ +#define UOTGHS_DEVEPTIER_TXINES (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIER[10]) Transmitted IN Data Interrupt Enable */ +#define UOTGHS_DEVEPTIER_RXOUTES (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIER[10]) Received OUT Data Interrupt Enable */ +#define UOTGHS_DEVEPTIER_RXSTPES (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIER[10]) Received SETUP Interrupt Enable */ +#define UOTGHS_DEVEPTIER_UNDERFES (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIER[10]) Underflow Interrupt Enable */ +#define UOTGHS_DEVEPTIER_NAKOUTES (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIER[10]) NAKed OUT Interrupt Enable */ +#define UOTGHS_DEVEPTIER_HBISOINERRES (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Error Interrupt Enable */ +#define UOTGHS_DEVEPTIER_NAKINES (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIER[10]) NAKed IN Interrupt Enable */ +#define UOTGHS_DEVEPTIER_HBISOFLUSHES (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Flush Interrupt Enable */ +#define UOTGHS_DEVEPTIER_OVERFES (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIER[10]) Overflow Interrupt Enable */ +#define UOTGHS_DEVEPTIER_STALLEDES (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIER[10]) STALLed Interrupt Enable */ +#define UOTGHS_DEVEPTIER_CRCERRES (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIER[10]) CRC Error Interrupt Enable */ +#define UOTGHS_DEVEPTIER_SHORTPACKETES (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIER[10]) Short Packet Interrupt Enable */ +#define UOTGHS_DEVEPTIER_MDATAES (0x1u << 8) /**< \brief (UOTGHS_DEVEPTIER[10]) MData Interrupt Enable */ +#define UOTGHS_DEVEPTIER_DATAXES (0x1u << 9) /**< \brief (UOTGHS_DEVEPTIER[10]) DataX Interrupt Enable */ +#define UOTGHS_DEVEPTIER_ERRORTRANSES (0x1u << 10) /**< \brief (UOTGHS_DEVEPTIER[10]) Transaction Error Interrupt Enable */ +#define UOTGHS_DEVEPTIER_NBUSYBKES (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIER[10]) Number of Busy Banks Interrupt Enable */ +#define UOTGHS_DEVEPTIER_KILLBKS (0x1u << 13) /**< \brief (UOTGHS_DEVEPTIER[10]) Kill IN Bank */ +#define UOTGHS_DEVEPTIER_EPDISHDMAS (0x1u << 16) /**< \brief (UOTGHS_DEVEPTIER[10]) Endpoint Interrupts Disable HDMA Request Enable */ +#define UOTGHS_DEVEPTIER_NYETDISS (0x1u << 17) /**< \brief (UOTGHS_DEVEPTIER[10]) NYET Token Disable Enable */ +#define UOTGHS_DEVEPTIER_RSTDTS (0x1u << 18) /**< \brief (UOTGHS_DEVEPTIER[10]) Reset Data Toggle Enable */ +#define UOTGHS_DEVEPTIER_STALLRQS (0x1u << 19) /**< \brief (UOTGHS_DEVEPTIER[10]) STALL Request Enable */ +/* -------- UOTGHS_DEVEPTIDR[10] : (UOTGHS Offset: 0x220) Device Endpoint Disable Register (n = 0) -------- */ +#define UOTGHS_DEVEPTIDR_TXINEC (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIDR[10]) Transmitted IN Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_RXOUTEC (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIDR[10]) Received OUT Data Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_RXSTPEC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIDR[10]) Received SETUP Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_UNDERFEC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIDR[10]) Underflow Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_NAKOUTEC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIDR[10]) NAKed OUT Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_HBISOINERREC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Error Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_NAKINEC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIDR[10]) NAKed IN Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_HBISOFLUSHEC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_OVERFEC (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIDR[10]) Overflow Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_STALLEDEC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIDR[10]) STALLed Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_CRCERREC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIDR[10]) CRC Error Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_SHORTPACKETEC (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIDR[10]) Shortpacket Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_MDATEC (0x1u << 8) /**< \brief (UOTGHS_DEVEPTIDR[10]) MData Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_DATAXEC (0x1u << 9) /**< \brief (UOTGHS_DEVEPTIDR[10]) DataX Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_ERRORTRANSEC (0x1u << 10) /**< \brief (UOTGHS_DEVEPTIDR[10]) Transaction Error Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_NBUSYBKEC (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIDR[10]) Number of Busy Banks Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_FIFOCONC (0x1u << 14) /**< \brief (UOTGHS_DEVEPTIDR[10]) FIFO Control Clear */ +#define UOTGHS_DEVEPTIDR_EPDISHDMAC (0x1u << 16) /**< \brief (UOTGHS_DEVEPTIDR[10]) Endpoint Interrupts Disable HDMA Request Clear */ +#define UOTGHS_DEVEPTIDR_NYETDISC (0x1u << 17) /**< \brief (UOTGHS_DEVEPTIDR[10]) NYET Token Disable Clear */ +#define UOTGHS_DEVEPTIDR_STALLRQC (0x1u << 19) /**< \brief (UOTGHS_DEVEPTIDR[10]) STALL Request Clear */ +/* -------- UOTGHS_DEVDMANXTDSC : (UOTGHS Offset: N/A) Device DMA Channel Next Descriptor Address Register -------- */ +#define UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos 0 +#define UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (UOTGHS_DEVDMANXTDSC) Next Descriptor Address */ +#define UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD(value) ((UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos))) +/* -------- UOTGHS_DEVDMAADDRESS : (UOTGHS Offset: N/A) Device DMA Channel Address Register -------- */ +#define UOTGHS_DEVDMAADDRESS_BUFF_ADD_Pos 0 +#define UOTGHS_DEVDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << UOTGHS_DEVDMAADDRESS_BUFF_ADD_Pos) /**< \brief (UOTGHS_DEVDMAADDRESS) Buffer Address */ +#define UOTGHS_DEVDMAADDRESS_BUFF_ADD(value) ((UOTGHS_DEVDMAADDRESS_BUFF_ADD_Msk & ((value) << UOTGHS_DEVDMAADDRESS_BUFF_ADD_Pos))) +/* -------- UOTGHS_DEVDMACONTROL : (UOTGHS Offset: N/A) Device DMA Channel Control Register -------- */ +#define UOTGHS_DEVDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_DEVDMACONTROL) Channel Enable Command */ +#define UOTGHS_DEVDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (UOTGHS_DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */ +#define UOTGHS_DEVDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (UOTGHS_DEVDMACONTROL) End of Transfer Enable Control */ +#define UOTGHS_DEVDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (UOTGHS_DEVDMACONTROL) End of Buffer Enable Control */ +#define UOTGHS_DEVDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (UOTGHS_DEVDMACONTROL) End of Transfer Interrupt Enable */ +#define UOTGHS_DEVDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (UOTGHS_DEVDMACONTROL) End of Buffer Interrupt Enable */ +#define UOTGHS_DEVDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (UOTGHS_DEVDMACONTROL) Descriptor Loaded Interrupt Enable */ +#define UOTGHS_DEVDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (UOTGHS_DEVDMACONTROL) Burst Lock Enable */ +#define UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Pos 16 +#define UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Msk (0xffffu << UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (UOTGHS_DEVDMACONTROL) Buffer Byte Length (Write-only) */ +#define UOTGHS_DEVDMACONTROL_BUFF_LENGTH(value) ((UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Msk & ((value) << UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Pos))) +/* -------- UOTGHS_DEVDMASTATUS : (UOTGHS Offset: N/A) Device DMA Channel Status Register -------- */ +#define UOTGHS_DEVDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_DEVDMASTATUS) Channel Enable Status */ +#define UOTGHS_DEVDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (UOTGHS_DEVDMASTATUS) Channel Active Status */ +#define UOTGHS_DEVDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (UOTGHS_DEVDMASTATUS) End of Channel Transfer Status */ +#define UOTGHS_DEVDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (UOTGHS_DEVDMASTATUS) End of Channel Buffer Status */ +#define UOTGHS_DEVDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (UOTGHS_DEVDMASTATUS) Descriptor Loaded Status */ +#define UOTGHS_DEVDMASTATUS_BUFF_COUNT_Pos 16 +#define UOTGHS_DEVDMASTATUS_BUFF_COUNT_Msk (0xffffu << UOTGHS_DEVDMASTATUS_BUFF_COUNT_Pos) /**< \brief (UOTGHS_DEVDMASTATUS) Buffer Byte Count */ +#define UOTGHS_DEVDMASTATUS_BUFF_COUNT(value) ((UOTGHS_DEVDMASTATUS_BUFF_COUNT_Msk & ((value) << UOTGHS_DEVDMASTATUS_BUFF_COUNT_Pos))) +/* -------- UOTGHS_HSTCTRL : (UOTGHS Offset: 0x0400) Host General Control Register -------- */ +#define UOTGHS_HSTCTRL_SOFE (0x1u << 8) /**< \brief (UOTGHS_HSTCTRL) Start of Frame Generation Enable */ +#define UOTGHS_HSTCTRL_RESET (0x1u << 9) /**< \brief (UOTGHS_HSTCTRL) Send USB Reset */ +#define UOTGHS_HSTCTRL_RESUME (0x1u << 10) /**< \brief (UOTGHS_HSTCTRL) Send USB Resume */ +#define UOTGHS_HSTCTRL_SPDCONF_Pos 12 +#define UOTGHS_HSTCTRL_SPDCONF_Msk (0x3u << UOTGHS_HSTCTRL_SPDCONF_Pos) /**< \brief (UOTGHS_HSTCTRL) Mode Configuration */ +#define UOTGHS_HSTCTRL_SPDCONF_NORMAL (0x0u << 12) /**< \brief (UOTGHS_HSTCTRL) The host starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the downstream peripheral is high-speed capable. */ +#define UOTGHS_HSTCTRL_SPDCONF_LOW_POWER (0x1u << 12) /**< \brief (UOTGHS_HSTCTRL) For a better consumption, if high-speed is not needed. */ +#define UOTGHS_HSTCTRL_SPDCONF_HIGH_SPEED (0x2u << 12) /**< \brief (UOTGHS_HSTCTRL) Forced high speed. */ +#define UOTGHS_HSTCTRL_SPDCONF_FORCED_FS (0x3u << 12) /**< \brief (UOTGHS_HSTCTRL) The host remains to full-speed mode whatever the peripheral speed capability. */ +/* -------- UOTGHS_HSTISR : (UOTGHS Offset: 0x0404) Host Global Interrupt Status Register -------- */ +#define UOTGHS_HSTISR_DCONNI (0x1u << 0) /**< \brief (UOTGHS_HSTISR) Device Connection Interrupt */ +#define UOTGHS_HSTISR_DDISCI (0x1u << 1) /**< \brief (UOTGHS_HSTISR) Device Disconnection Interrupt */ +#define UOTGHS_HSTISR_RSTI (0x1u << 2) /**< \brief (UOTGHS_HSTISR) USB Reset Sent Interrupt */ +#define UOTGHS_HSTISR_RSMEDI (0x1u << 3) /**< \brief (UOTGHS_HSTISR) Downstream Resume Sent Interrupt */ +#define UOTGHS_HSTISR_RXRSMI (0x1u << 4) /**< \brief (UOTGHS_HSTISR) Upstream Resume Received Interrupt */ +#define UOTGHS_HSTISR_HSOFI (0x1u << 5) /**< \brief (UOTGHS_HSTISR) Host Start of Frame Interrupt */ +#define UOTGHS_HSTISR_HWUPI (0x1u << 6) /**< \brief (UOTGHS_HSTISR) Host Wake-Up Interrupt */ +#define UOTGHS_HSTISR_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTISR) Pipe 0 Interrupt */ +#define UOTGHS_HSTISR_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTISR) Pipe 1 Interrupt */ +#define UOTGHS_HSTISR_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTISR) Pipe 2 Interrupt */ +#define UOTGHS_HSTISR_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTISR) Pipe 3 Interrupt */ +#define UOTGHS_HSTISR_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTISR) Pipe 4 Interrupt */ +#define UOTGHS_HSTISR_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTISR) Pipe 5 Interrupt */ +#define UOTGHS_HSTISR_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTISR) Pipe 6 Interrupt */ +#define UOTGHS_HSTISR_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTISR) Pipe 7 Interrupt */ +#define UOTGHS_HSTISR_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTISR) Pipe 8 Interrupt */ +#define UOTGHS_HSTISR_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTISR) Pipe 9 Interrupt */ +#define UOTGHS_HSTISR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTISR) DMA Channel 1 Interrupt */ +#define UOTGHS_HSTISR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTISR) DMA Channel 2 Interrupt */ +#define UOTGHS_HSTISR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTISR) DMA Channel 3 Interrupt */ +#define UOTGHS_HSTISR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTISR) DMA Channel 4 Interrupt */ +#define UOTGHS_HSTISR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTISR) DMA Channel 5 Interrupt */ +#define UOTGHS_HSTISR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTISR) DMA Channel 6 Interrupt */ +/* -------- UOTGHS_HSTICR : (UOTGHS Offset: 0x0408) Host Global Interrupt Clear Register -------- */ +#define UOTGHS_HSTICR_DCONNIC (0x1u << 0) /**< \brief (UOTGHS_HSTICR) Device Connection Interrupt Clear */ +#define UOTGHS_HSTICR_DDISCIC (0x1u << 1) /**< \brief (UOTGHS_HSTICR) Device Disconnection Interrupt Clear */ +#define UOTGHS_HSTICR_RSTIC (0x1u << 2) /**< \brief (UOTGHS_HSTICR) USB Reset Sent Interrupt Clear */ +#define UOTGHS_HSTICR_RSMEDIC (0x1u << 3) /**< \brief (UOTGHS_HSTICR) Downstream Resume Sent Interrupt Clear */ +#define UOTGHS_HSTICR_RXRSMIC (0x1u << 4) /**< \brief (UOTGHS_HSTICR) Upstream Resume Received Interrupt Clear */ +#define UOTGHS_HSTICR_HSOFIC (0x1u << 5) /**< \brief (UOTGHS_HSTICR) Host Start of Frame Interrupt Clear */ +#define UOTGHS_HSTICR_HWUPIC (0x1u << 6) /**< \brief (UOTGHS_HSTICR) Host Wake-Up Interrupt Clear */ +/* -------- UOTGHS_HSTIFR : (UOTGHS Offset: 0x040C) Host Global Interrupt Set Register -------- */ +#define UOTGHS_HSTIFR_DCONNIS (0x1u << 0) /**< \brief (UOTGHS_HSTIFR) Device Connection Interrupt Set */ +#define UOTGHS_HSTIFR_DDISCIS (0x1u << 1) /**< \brief (UOTGHS_HSTIFR) Device Disconnection Interrupt Set */ +#define UOTGHS_HSTIFR_RSTIS (0x1u << 2) /**< \brief (UOTGHS_HSTIFR) USB Reset Sent Interrupt Set */ +#define UOTGHS_HSTIFR_RSMEDIS (0x1u << 3) /**< \brief (UOTGHS_HSTIFR) Downstream Resume Sent Interrupt Set */ +#define UOTGHS_HSTIFR_RXRSMIS (0x1u << 4) /**< \brief (UOTGHS_HSTIFR) Upstream Resume Received Interrupt Set */ +#define UOTGHS_HSTIFR_HSOFIS (0x1u << 5) /**< \brief (UOTGHS_HSTIFR) Host Start of Frame Interrupt Set */ +#define UOTGHS_HSTIFR_HWUPIS (0x1u << 6) /**< \brief (UOTGHS_HSTIFR) Host Wake-Up Interrupt Set */ +#define UOTGHS_HSTIFR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIFR) DMA Channel 1 Interrupt Set */ +#define UOTGHS_HSTIFR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIFR) DMA Channel 2 Interrupt Set */ +#define UOTGHS_HSTIFR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIFR) DMA Channel 3 Interrupt Set */ +#define UOTGHS_HSTIFR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIFR) DMA Channel 4 Interrupt Set */ +#define UOTGHS_HSTIFR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIFR) DMA Channel 5 Interrupt Set */ +#define UOTGHS_HSTIFR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIFR) DMA Channel 6 Interrupt Set */ +/* -------- UOTGHS_HSTIMR : (UOTGHS Offset: 0x0410) Host Global Interrupt Mask Register -------- */ +#define UOTGHS_HSTIMR_DCONNIE (0x1u << 0) /**< \brief (UOTGHS_HSTIMR) Device Connection Interrupt Enable */ +#define UOTGHS_HSTIMR_DDISCIE (0x1u << 1) /**< \brief (UOTGHS_HSTIMR) Device Disconnection Interrupt Enable */ +#define UOTGHS_HSTIMR_RSTIE (0x1u << 2) /**< \brief (UOTGHS_HSTIMR) USB Reset Sent Interrupt Enable */ +#define UOTGHS_HSTIMR_RSMEDIE (0x1u << 3) /**< \brief (UOTGHS_HSTIMR) Downstream Resume Sent Interrupt Enable */ +#define UOTGHS_HSTIMR_RXRSMIE (0x1u << 4) /**< \brief (UOTGHS_HSTIMR) Upstream Resume Received Interrupt Enable */ +#define UOTGHS_HSTIMR_HSOFIE (0x1u << 5) /**< \brief (UOTGHS_HSTIMR) Host Start of Frame Interrupt Enable */ +#define UOTGHS_HSTIMR_HWUPIE (0x1u << 6) /**< \brief (UOTGHS_HSTIMR) Host Wake-Up Interrupt Enable */ +#define UOTGHS_HSTIMR_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTIMR) Pipe 0 Interrupt Enable */ +#define UOTGHS_HSTIMR_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTIMR) Pipe 1 Interrupt Enable */ +#define UOTGHS_HSTIMR_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTIMR) Pipe 2 Interrupt Enable */ +#define UOTGHS_HSTIMR_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTIMR) Pipe 3 Interrupt Enable */ +#define UOTGHS_HSTIMR_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTIMR) Pipe 4 Interrupt Enable */ +#define UOTGHS_HSTIMR_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTIMR) Pipe 5 Interrupt Enable */ +#define UOTGHS_HSTIMR_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTIMR) Pipe 6 Interrupt Enable */ +#define UOTGHS_HSTIMR_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTIMR) Pipe 7 Interrupt Enable */ +#define UOTGHS_HSTIMR_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTIMR) Pipe 8 Interrupt Enable */ +#define UOTGHS_HSTIMR_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTIMR) Pipe 9 Interrupt Enable */ +#define UOTGHS_HSTIMR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIMR) DMA Channel 1 Interrupt Enable */ +#define UOTGHS_HSTIMR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIMR) DMA Channel 2 Interrupt Enable */ +#define UOTGHS_HSTIMR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIMR) DMA Channel 3 Interrupt Enable */ +#define UOTGHS_HSTIMR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIMR) DMA Channel 4 Interrupt Enable */ +#define UOTGHS_HSTIMR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIMR) DMA Channel 5 Interrupt Enable */ +#define UOTGHS_HSTIMR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIMR) DMA Channel 6 Interrupt Enable */ +/* -------- UOTGHS_HSTIDR : (UOTGHS Offset: 0x0414) Host Global Interrupt Disable Register -------- */ +#define UOTGHS_HSTIDR_DCONNIEC (0x1u << 0) /**< \brief (UOTGHS_HSTIDR) Device Connection Interrupt Disable */ +#define UOTGHS_HSTIDR_DDISCIEC (0x1u << 1) /**< \brief (UOTGHS_HSTIDR) Device Disconnection Interrupt Disable */ +#define UOTGHS_HSTIDR_RSTIEC (0x1u << 2) /**< \brief (UOTGHS_HSTIDR) USB Reset Sent Interrupt Disable */ +#define UOTGHS_HSTIDR_RSMEDIEC (0x1u << 3) /**< \brief (UOTGHS_HSTIDR) Downstream Resume Sent Interrupt Disable */ +#define UOTGHS_HSTIDR_RXRSMIEC (0x1u << 4) /**< \brief (UOTGHS_HSTIDR) Upstream Resume Received Interrupt Disable */ +#define UOTGHS_HSTIDR_HSOFIEC (0x1u << 5) /**< \brief (UOTGHS_HSTIDR) Host Start of Frame Interrupt Disable */ +#define UOTGHS_HSTIDR_HWUPIEC (0x1u << 6) /**< \brief (UOTGHS_HSTIDR) Host Wake-Up Interrupt Disable */ +#define UOTGHS_HSTIDR_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTIDR) Pipe 0 Interrupt Disable */ +#define UOTGHS_HSTIDR_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTIDR) Pipe 1 Interrupt Disable */ +#define UOTGHS_HSTIDR_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTIDR) Pipe 2 Interrupt Disable */ +#define UOTGHS_HSTIDR_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTIDR) Pipe 3 Interrupt Disable */ +#define UOTGHS_HSTIDR_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTIDR) Pipe 4 Interrupt Disable */ +#define UOTGHS_HSTIDR_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTIDR) Pipe 5 Interrupt Disable */ +#define UOTGHS_HSTIDR_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTIDR) Pipe 6 Interrupt Disable */ +#define UOTGHS_HSTIDR_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTIDR) Pipe 7 Interrupt Disable */ +#define UOTGHS_HSTIDR_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTIDR) Pipe 8 Interrupt Disable */ +#define UOTGHS_HSTIDR_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTIDR) Pipe 9 Interrupt Disable */ +#define UOTGHS_HSTIDR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIDR) DMA Channel 1 Interrupt Disable */ +#define UOTGHS_HSTIDR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIDR) DMA Channel 2 Interrupt Disable */ +#define UOTGHS_HSTIDR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIDR) DMA Channel 3 Interrupt Disable */ +#define UOTGHS_HSTIDR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIDR) DMA Channel 4 Interrupt Disable */ +#define UOTGHS_HSTIDR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIDR) DMA Channel 5 Interrupt Disable */ +#define UOTGHS_HSTIDR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIDR) DMA Channel 6 Interrupt Disable */ +/* -------- UOTGHS_HSTIER : (UOTGHS Offset: 0x0418) Host Global Interrupt Enable Register -------- */ +#define UOTGHS_HSTIER_DCONNIES (0x1u << 0) /**< \brief (UOTGHS_HSTIER) Device Connection Interrupt Enable */ +#define UOTGHS_HSTIER_DDISCIES (0x1u << 1) /**< \brief (UOTGHS_HSTIER) Device Disconnection Interrupt Enable */ +#define UOTGHS_HSTIER_RSTIES (0x1u << 2) /**< \brief (UOTGHS_HSTIER) USB Reset Sent Interrupt Enable */ +#define UOTGHS_HSTIER_RSMEDIES (0x1u << 3) /**< \brief (UOTGHS_HSTIER) Downstream Resume Sent Interrupt Enable */ +#define UOTGHS_HSTIER_RXRSMIES (0x1u << 4) /**< \brief (UOTGHS_HSTIER) Upstream Resume Received Interrupt Enable */ +#define UOTGHS_HSTIER_HSOFIES (0x1u << 5) /**< \brief (UOTGHS_HSTIER) Host Start of Frame Interrupt Enable */ +#define UOTGHS_HSTIER_HWUPIES (0x1u << 6) /**< \brief (UOTGHS_HSTIER) Host Wake-Up Interrupt Enable */ +#define UOTGHS_HSTIER_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTIER) Pipe 0 Interrupt Enable */ +#define UOTGHS_HSTIER_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTIER) Pipe 1 Interrupt Enable */ +#define UOTGHS_HSTIER_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTIER) Pipe 2 Interrupt Enable */ +#define UOTGHS_HSTIER_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTIER) Pipe 3 Interrupt Enable */ +#define UOTGHS_HSTIER_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTIER) Pipe 4 Interrupt Enable */ +#define UOTGHS_HSTIER_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTIER) Pipe 5 Interrupt Enable */ +#define UOTGHS_HSTIER_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTIER) Pipe 6 Interrupt Enable */ +#define UOTGHS_HSTIER_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTIER) Pipe 7 Interrupt Enable */ +#define UOTGHS_HSTIER_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTIER) Pipe 8 Interrupt Enable */ +#define UOTGHS_HSTIER_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTIER) Pipe 9 Interrupt Enable */ +#define UOTGHS_HSTIER_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIER) DMA Channel 1 Interrupt Enable */ +#define UOTGHS_HSTIER_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIER) DMA Channel 2 Interrupt Enable */ +#define UOTGHS_HSTIER_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIER) DMA Channel 3 Interrupt Enable */ +#define UOTGHS_HSTIER_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIER) DMA Channel 4 Interrupt Enable */ +#define UOTGHS_HSTIER_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIER) DMA Channel 5 Interrupt Enable */ +#define UOTGHS_HSTIER_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIER) DMA Channel 6 Interrupt Enable */ +/* -------- UOTGHS_HSTPIP : (UOTGHS Offset: 0x0041C) Host Pipe Register -------- */ +#define UOTGHS_HSTPIP_PEN0 (0x1u << 0) /**< \brief (UOTGHS_HSTPIP) Pipe 0 Enable */ +#define UOTGHS_HSTPIP_PEN1 (0x1u << 1) /**< \brief (UOTGHS_HSTPIP) Pipe 1 Enable */ +#define UOTGHS_HSTPIP_PEN2 (0x1u << 2) /**< \brief (UOTGHS_HSTPIP) Pipe 2 Enable */ +#define UOTGHS_HSTPIP_PEN3 (0x1u << 3) /**< \brief (UOTGHS_HSTPIP) Pipe 3 Enable */ +#define UOTGHS_HSTPIP_PEN4 (0x1u << 4) /**< \brief (UOTGHS_HSTPIP) Pipe 4 Enable */ +#define UOTGHS_HSTPIP_PEN5 (0x1u << 5) /**< \brief (UOTGHS_HSTPIP) Pipe 5 Enable */ +#define UOTGHS_HSTPIP_PEN6 (0x1u << 6) /**< \brief (UOTGHS_HSTPIP) Pipe 6 Enable */ +#define UOTGHS_HSTPIP_PEN7 (0x1u << 7) /**< \brief (UOTGHS_HSTPIP) Pipe 7 Enable */ +#define UOTGHS_HSTPIP_PEN8 (0x1u << 8) /**< \brief (UOTGHS_HSTPIP) Pipe 8 Enable */ +#define UOTGHS_HSTPIP_PRST0 (0x1u << 16) /**< \brief (UOTGHS_HSTPIP) Pipe 0 Reset */ +#define UOTGHS_HSTPIP_PRST1 (0x1u << 17) /**< \brief (UOTGHS_HSTPIP) Pipe 1 Reset */ +#define UOTGHS_HSTPIP_PRST2 (0x1u << 18) /**< \brief (UOTGHS_HSTPIP) Pipe 2 Reset */ +#define UOTGHS_HSTPIP_PRST3 (0x1u << 19) /**< \brief (UOTGHS_HSTPIP) Pipe 3 Reset */ +#define UOTGHS_HSTPIP_PRST4 (0x1u << 20) /**< \brief (UOTGHS_HSTPIP) Pipe 4 Reset */ +#define UOTGHS_HSTPIP_PRST5 (0x1u << 21) /**< \brief (UOTGHS_HSTPIP) Pipe 5 Reset */ +#define UOTGHS_HSTPIP_PRST6 (0x1u << 22) /**< \brief (UOTGHS_HSTPIP) Pipe 6 Reset */ +#define UOTGHS_HSTPIP_PRST7 (0x1u << 23) /**< \brief (UOTGHS_HSTPIP) Pipe 7 Reset */ +#define UOTGHS_HSTPIP_PRST8 (0x1u << 24) /**< \brief (UOTGHS_HSTPIP) Pipe 8 Reset */ +/* -------- UOTGHS_HSTFNUM : (UOTGHS Offset: 0x0420) Host Frame Number Register -------- */ +#define UOTGHS_HSTFNUM_MFNUM_Pos 0 +#define UOTGHS_HSTFNUM_MFNUM_Msk (0x7u << UOTGHS_HSTFNUM_MFNUM_Pos) /**< \brief (UOTGHS_HSTFNUM) Micro Frame Number */ +#define UOTGHS_HSTFNUM_MFNUM(value) ((UOTGHS_HSTFNUM_MFNUM_Msk & ((value) << UOTGHS_HSTFNUM_MFNUM_Pos))) +#define UOTGHS_HSTFNUM_FNUM_Pos 3 +#define UOTGHS_HSTFNUM_FNUM_Msk (0x7ffu << UOTGHS_HSTFNUM_FNUM_Pos) /**< \brief (UOTGHS_HSTFNUM) Frame Number */ +#define UOTGHS_HSTFNUM_FNUM(value) ((UOTGHS_HSTFNUM_FNUM_Msk & ((value) << UOTGHS_HSTFNUM_FNUM_Pos))) +#define UOTGHS_HSTFNUM_FLENHIGH_Pos 16 +#define UOTGHS_HSTFNUM_FLENHIGH_Msk (0xffu << UOTGHS_HSTFNUM_FLENHIGH_Pos) /**< \brief (UOTGHS_HSTFNUM) Frame Length */ +#define UOTGHS_HSTFNUM_FLENHIGH(value) ((UOTGHS_HSTFNUM_FLENHIGH_Msk & ((value) << UOTGHS_HSTFNUM_FLENHIGH_Pos))) +/* -------- UOTGHS_HSTADDR1 : (UOTGHS Offset: 0x0424) Host Address 1 Register -------- */ +#define UOTGHS_HSTADDR1_HSTADDRP0_Pos 0 +#define UOTGHS_HSTADDR1_HSTADDRP0_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP0_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */ +#define UOTGHS_HSTADDR1_HSTADDRP0(value) ((UOTGHS_HSTADDR1_HSTADDRP0_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP0_Pos))) +#define UOTGHS_HSTADDR1_HSTADDRP1_Pos 8 +#define UOTGHS_HSTADDR1_HSTADDRP1_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP1_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */ +#define UOTGHS_HSTADDR1_HSTADDRP1(value) ((UOTGHS_HSTADDR1_HSTADDRP1_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP1_Pos))) +#define UOTGHS_HSTADDR1_HSTADDRP2_Pos 16 +#define UOTGHS_HSTADDR1_HSTADDRP2_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP2_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */ +#define UOTGHS_HSTADDR1_HSTADDRP2(value) ((UOTGHS_HSTADDR1_HSTADDRP2_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP2_Pos))) +#define UOTGHS_HSTADDR1_HSTADDRP3_Pos 24 +#define UOTGHS_HSTADDR1_HSTADDRP3_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP3_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */ +#define UOTGHS_HSTADDR1_HSTADDRP3(value) ((UOTGHS_HSTADDR1_HSTADDRP3_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP3_Pos))) +/* -------- UOTGHS_HSTADDR2 : (UOTGHS Offset: 0x0428) Host Address 2 Register -------- */ +#define UOTGHS_HSTADDR2_HSTADDRP4_Pos 0 +#define UOTGHS_HSTADDR2_HSTADDRP4_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP4_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */ +#define UOTGHS_HSTADDR2_HSTADDRP4(value) ((UOTGHS_HSTADDR2_HSTADDRP4_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP4_Pos))) +#define UOTGHS_HSTADDR2_HSTADDRP5_Pos 8 +#define UOTGHS_HSTADDR2_HSTADDRP5_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP5_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */ +#define UOTGHS_HSTADDR2_HSTADDRP5(value) ((UOTGHS_HSTADDR2_HSTADDRP5_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP5_Pos))) +#define UOTGHS_HSTADDR2_HSTADDRP6_Pos 16 +#define UOTGHS_HSTADDR2_HSTADDRP6_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP6_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */ +#define UOTGHS_HSTADDR2_HSTADDRP6(value) ((UOTGHS_HSTADDR2_HSTADDRP6_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP6_Pos))) +#define UOTGHS_HSTADDR2_HSTADDRP7_Pos 24 +#define UOTGHS_HSTADDR2_HSTADDRP7_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP7_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */ +#define UOTGHS_HSTADDR2_HSTADDRP7(value) ((UOTGHS_HSTADDR2_HSTADDRP7_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP7_Pos))) +/* -------- UOTGHS_HSTADDR3 : (UOTGHS Offset: 0x042C) Host Address 3 Register -------- */ +#define UOTGHS_HSTADDR3_HSTADDRP8_Pos 0 +#define UOTGHS_HSTADDR3_HSTADDRP8_Msk (0x7fu << UOTGHS_HSTADDR3_HSTADDRP8_Pos) /**< \brief (UOTGHS_HSTADDR3) USB Host Address */ +#define UOTGHS_HSTADDR3_HSTADDRP8(value) ((UOTGHS_HSTADDR3_HSTADDRP8_Msk & ((value) << UOTGHS_HSTADDR3_HSTADDRP8_Pos))) +#define UOTGHS_HSTADDR3_HSTADDRP9_Pos 8 +#define UOTGHS_HSTADDR3_HSTADDRP9_Msk (0x7fu << UOTGHS_HSTADDR3_HSTADDRP9_Pos) /**< \brief (UOTGHS_HSTADDR3) USB Host Address */ +#define UOTGHS_HSTADDR3_HSTADDRP9(value) ((UOTGHS_HSTADDR3_HSTADDRP9_Msk & ((value) << UOTGHS_HSTADDR3_HSTADDRP9_Pos))) +/* -------- UOTGHS_HSTPIPCFG[10] : (UOTGHS Offset: 0x500) Host Pipe Configuration Register (n = 0) -------- */ +#define UOTGHS_HSTPIPCFG_ALLOC (0x1u << 1) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Memory Allocate */ +#define UOTGHS_HSTPIPCFG_PBK_Pos 2 +#define UOTGHS_HSTPIPCFG_PBK_Msk (0x3u << UOTGHS_HSTPIPCFG_PBK_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Banks */ +#define UOTGHS_HSTPIPCFG_PBK_1_BANK (0x0u << 2) /**< \brief (UOTGHS_HSTPIPCFG[10]) Single-bank pipe */ +#define UOTGHS_HSTPIPCFG_PBK_2_BANK (0x1u << 2) /**< \brief (UOTGHS_HSTPIPCFG[10]) Double-bank pipe */ +#define UOTGHS_HSTPIPCFG_PBK_3_BANK (0x2u << 2) /**< \brief (UOTGHS_HSTPIPCFG[10]) Triple-bank pipe */ +#define UOTGHS_HSTPIPCFG_PSIZE_Pos 4 +#define UOTGHS_HSTPIPCFG_PSIZE_Msk (0x7u << UOTGHS_HSTPIPCFG_PSIZE_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Size */ +#define UOTGHS_HSTPIPCFG_PSIZE_8_BYTE (0x0u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 8 bytes */ +#define UOTGHS_HSTPIPCFG_PSIZE_16_BYTE (0x1u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 16 bytes */ +#define UOTGHS_HSTPIPCFG_PSIZE_32_BYTE (0x2u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 32 bytes */ +#define UOTGHS_HSTPIPCFG_PSIZE_64_BYTE (0x3u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 64 bytes */ +#define UOTGHS_HSTPIPCFG_PSIZE_128_BYTE (0x4u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 128 bytes */ +#define UOTGHS_HSTPIPCFG_PSIZE_256_BYTE (0x5u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 256 bytes */ +#define UOTGHS_HSTPIPCFG_PSIZE_512_BYTE (0x6u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 512 bytes */ +#define UOTGHS_HSTPIPCFG_PSIZE_1024_BYTE (0x7u << 4) /**< \brief (UOTGHS_HSTPIPCFG[10]) 1024 bytes */ +#define UOTGHS_HSTPIPCFG_PTOKEN_Pos 8 +#define UOTGHS_HSTPIPCFG_PTOKEN_Msk (0x3u << UOTGHS_HSTPIPCFG_PTOKEN_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Token */ +#define UOTGHS_HSTPIPCFG_PTOKEN_SETUP (0x0u << 8) /**< \brief (UOTGHS_HSTPIPCFG[10]) SETUP */ +#define UOTGHS_HSTPIPCFG_PTOKEN_IN (0x1u << 8) /**< \brief (UOTGHS_HSTPIPCFG[10]) IN */ +#define UOTGHS_HSTPIPCFG_PTOKEN_OUT (0x2u << 8) /**< \brief (UOTGHS_HSTPIPCFG[10]) OUT */ +#define UOTGHS_HSTPIPCFG_AUTOSW (0x1u << 10) /**< \brief (UOTGHS_HSTPIPCFG[10]) Automatic Switch */ +#define UOTGHS_HSTPIPCFG_PTYPE_Pos 12 +#define UOTGHS_HSTPIPCFG_PTYPE_Msk (0x3u << UOTGHS_HSTPIPCFG_PTYPE_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Type */ +#define UOTGHS_HSTPIPCFG_PTYPE_CTRL (0x0u << 12) /**< \brief (UOTGHS_HSTPIPCFG[10]) Control */ +#define UOTGHS_HSTPIPCFG_PTYPE_ISO (0x1u << 12) /**< \brief (UOTGHS_HSTPIPCFG[10]) Isochronous */ +#define UOTGHS_HSTPIPCFG_PTYPE_BLK (0x2u << 12) /**< \brief (UOTGHS_HSTPIPCFG[10]) Bulk */ +#define UOTGHS_HSTPIPCFG_PTYPE_INTRPT (0x3u << 12) /**< \brief (UOTGHS_HSTPIPCFG[10]) Interrupt */ +#define UOTGHS_HSTPIPCFG_PEPNUM_Pos 16 +#define UOTGHS_HSTPIPCFG_PEPNUM_Msk (0xfu << UOTGHS_HSTPIPCFG_PEPNUM_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Endpoint Number */ +#define UOTGHS_HSTPIPCFG_PEPNUM(value) ((UOTGHS_HSTPIPCFG_PEPNUM_Msk & ((value) << UOTGHS_HSTPIPCFG_PEPNUM_Pos))) +#define UOTGHS_HSTPIPCFG_PINGEN (0x1u << 20) /**< \brief (UOTGHS_HSTPIPCFG[10]) Ping Enable */ +#define UOTGHS_HSTPIPCFG_INTFRQ_Pos 24 +#define UOTGHS_HSTPIPCFG_INTFRQ_Msk (0xffu << UOTGHS_HSTPIPCFG_INTFRQ_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) Pipe Interrupt Request Frequency */ +#define UOTGHS_HSTPIPCFG_INTFRQ(value) ((UOTGHS_HSTPIPCFG_INTFRQ_Msk & ((value) << UOTGHS_HSTPIPCFG_INTFRQ_Pos))) +#define UOTGHS_HSTPIPCFG_BINTERVAL_Pos 24 +#define UOTGHS_HSTPIPCFG_BINTERVAL_Msk (0xffu << UOTGHS_HSTPIPCFG_BINTERVAL_Pos) /**< \brief (UOTGHS_HSTPIPCFG[10]) bInterval parameter for the Bulk-Out/Ping transaction */ +#define UOTGHS_HSTPIPCFG_BINTERVAL(value) ((UOTGHS_HSTPIPCFG_BINTERVAL_Msk & ((value) << UOTGHS_HSTPIPCFG_BINTERVAL_Pos))) +/* -------- UOTGHS_HSTPIPISR[10] : (UOTGHS Offset: 0x530) Host Pipe Status Register (n = 0) -------- */ +#define UOTGHS_HSTPIPISR_RXINI (0x1u << 0) /**< \brief (UOTGHS_HSTPIPISR[10]) Received IN Data Interrupt */ +#define UOTGHS_HSTPIPISR_TXOUTI (0x1u << 1) /**< \brief (UOTGHS_HSTPIPISR[10]) Transmitted OUT Data Interrupt */ +#define UOTGHS_HSTPIPISR_TXSTPI (0x1u << 2) /**< \brief (UOTGHS_HSTPIPISR[10]) Transmitted SETUP Interrupt */ +#define UOTGHS_HSTPIPISR_UNDERFI (0x1u << 2) /**< \brief (UOTGHS_HSTPIPISR[10]) Underflow Interrupt */ +#define UOTGHS_HSTPIPISR_PERRI (0x1u << 3) /**< \brief (UOTGHS_HSTPIPISR[10]) Pipe Error Interrupt */ +#define UOTGHS_HSTPIPISR_NAKEDI (0x1u << 4) /**< \brief (UOTGHS_HSTPIPISR[10]) NAKed Interrupt */ +#define UOTGHS_HSTPIPISR_OVERFI (0x1u << 5) /**< \brief (UOTGHS_HSTPIPISR[10]) Overflow Interrupt */ +#define UOTGHS_HSTPIPISR_RXSTALLDI (0x1u << 6) /**< \brief (UOTGHS_HSTPIPISR[10]) Received STALLed Interrupt */ +#define UOTGHS_HSTPIPISR_CRCERRI (0x1u << 6) /**< \brief (UOTGHS_HSTPIPISR[10]) CRC Error Interrupt */ +#define UOTGHS_HSTPIPISR_SHORTPACKETI (0x1u << 7) /**< \brief (UOTGHS_HSTPIPISR[10]) Short Packet Interrupt */ +#define UOTGHS_HSTPIPISR_DTSEQ_Pos 8 +#define UOTGHS_HSTPIPISR_DTSEQ_Msk (0x3u << UOTGHS_HSTPIPISR_DTSEQ_Pos) /**< \brief (UOTGHS_HSTPIPISR[10]) Data Toggle Sequence */ +#define UOTGHS_HSTPIPISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (UOTGHS_HSTPIPISR[10]) Data0 toggle sequence */ +#define UOTGHS_HSTPIPISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (UOTGHS_HSTPIPISR[10]) Data1 toggle sequence */ +#define UOTGHS_HSTPIPISR_NBUSYBK_Pos 12 +#define UOTGHS_HSTPIPISR_NBUSYBK_Msk (0x3u << UOTGHS_HSTPIPISR_NBUSYBK_Pos) /**< \brief (UOTGHS_HSTPIPISR[10]) Number of Busy Banks */ +#define UOTGHS_HSTPIPISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (UOTGHS_HSTPIPISR[10]) 0 busy bank (all banks free) */ +#define UOTGHS_HSTPIPISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (UOTGHS_HSTPIPISR[10]) 1 busy bank */ +#define UOTGHS_HSTPIPISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (UOTGHS_HSTPIPISR[10]) 2 busy banks */ +#define UOTGHS_HSTPIPISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (UOTGHS_HSTPIPISR[10]) 3 busy banks */ +#define UOTGHS_HSTPIPISR_CURRBK_Pos 14 +#define UOTGHS_HSTPIPISR_CURRBK_Msk (0x3u << UOTGHS_HSTPIPISR_CURRBK_Pos) /**< \brief (UOTGHS_HSTPIPISR[10]) Current Bank */ +#define UOTGHS_HSTPIPISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (UOTGHS_HSTPIPISR[10]) Current bank is bank0 */ +#define UOTGHS_HSTPIPISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (UOTGHS_HSTPIPISR[10]) Current bank is bank1 */ +#define UOTGHS_HSTPIPISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (UOTGHS_HSTPIPISR[10]) Current bank is bank2 */ +#define UOTGHS_HSTPIPISR_RWALL (0x1u << 16) /**< \brief (UOTGHS_HSTPIPISR[10]) Read-write Allowed */ +#define UOTGHS_HSTPIPISR_CFGOK (0x1u << 18) /**< \brief (UOTGHS_HSTPIPISR[10]) Configuration OK Status */ +#define UOTGHS_HSTPIPISR_PBYCT_Pos 20 +#define UOTGHS_HSTPIPISR_PBYCT_Msk (0x7ffu << UOTGHS_HSTPIPISR_PBYCT_Pos) /**< \brief (UOTGHS_HSTPIPISR[10]) Pipe Byte Count */ +/* -------- UOTGHS_HSTPIPICR[10] : (UOTGHS Offset: 0x560) Host Pipe Clear Register (n = 0) -------- */ +#define UOTGHS_HSTPIPICR_RXINIC (0x1u << 0) /**< \brief (UOTGHS_HSTPIPICR[10]) Received IN Data Interrupt Clear */ +#define UOTGHS_HSTPIPICR_TXOUTIC (0x1u << 1) /**< \brief (UOTGHS_HSTPIPICR[10]) Transmitted OUT Data Interrupt Clear */ +#define UOTGHS_HSTPIPICR_TXSTPIC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPICR[10]) Transmitted SETUP Interrupt Clear */ +#define UOTGHS_HSTPIPICR_UNDERFIC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPICR[10]) Underflow Interrupt Clear */ +#define UOTGHS_HSTPIPICR_NAKEDIC (0x1u << 4) /**< \brief (UOTGHS_HSTPIPICR[10]) NAKed Interrupt Clear */ +#define UOTGHS_HSTPIPICR_OVERFIC (0x1u << 5) /**< \brief (UOTGHS_HSTPIPICR[10]) Overflow Interrupt Clear */ +#define UOTGHS_HSTPIPICR_RXSTALLDIC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPICR[10]) Received STALLed Interrupt Clear */ +#define UOTGHS_HSTPIPICR_CRCERRIC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPICR[10]) CRC Error Interrupt Clear */ +#define UOTGHS_HSTPIPICR_SHORTPACKETIC (0x1u << 7) /**< \brief (UOTGHS_HSTPIPICR[10]) Short Packet Interrupt Clear */ +/* -------- UOTGHS_HSTPIPIFR[10] : (UOTGHS Offset: 0x590) Host Pipe Set Register (n = 0) -------- */ +#define UOTGHS_HSTPIPIFR_RXINIS (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIFR[10]) Received IN Data Interrupt Set */ +#define UOTGHS_HSTPIPIFR_TXOUTIS (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIFR[10]) Transmitted OUT Data Interrupt Set */ +#define UOTGHS_HSTPIPIFR_TXSTPIS (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIFR[10]) Transmitted SETUP Interrupt Set */ +#define UOTGHS_HSTPIPIFR_UNDERFIS (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIFR[10]) Underflow Interrupt Set */ +#define UOTGHS_HSTPIPIFR_PERRIS (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIFR[10]) Pipe Error Interrupt Set */ +#define UOTGHS_HSTPIPIFR_NAKEDIS (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIFR[10]) NAKed Interrupt Set */ +#define UOTGHS_HSTPIPIFR_OVERFIS (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIFR[10]) Overflow Interrupt Set */ +#define UOTGHS_HSTPIPIFR_RXSTALLDIS (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIFR[10]) Received STALLed Interrupt Set */ +#define UOTGHS_HSTPIPIFR_CRCERRIS (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIFR[10]) CRC Error Interrupt Set */ +#define UOTGHS_HSTPIPIFR_SHORTPACKETIS (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIFR[10]) Short Packet Interrupt Set */ +#define UOTGHS_HSTPIPIFR_NBUSYBKS (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIFR[10]) Number of Busy Banks Set */ +/* -------- UOTGHS_HSTPIPIMR[10] : (UOTGHS Offset: 0x5C0) Host Pipe Mask Register (n = 0) -------- */ +#define UOTGHS_HSTPIPIMR_RXINE (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIMR[10]) Received IN Data Interrupt Enable */ +#define UOTGHS_HSTPIPIMR_TXOUTE (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIMR[10]) Transmitted OUT Data Interrupt Enable */ +#define UOTGHS_HSTPIPIMR_TXSTPE (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIMR[10]) Transmitted SETUP Interrupt Enable */ +#define UOTGHS_HSTPIPIMR_UNDERFIE (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIMR[10]) Underflow Interrupt Enable */ +#define UOTGHS_HSTPIPIMR_PERRE (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIMR[10]) Pipe Error Interrupt Enable */ +#define UOTGHS_HSTPIPIMR_NAKEDE (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIMR[10]) NAKed Interrupt Enable */ +#define UOTGHS_HSTPIPIMR_OVERFIE (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIMR[10]) Overflow Interrupt Enable */ +#define UOTGHS_HSTPIPIMR_RXSTALLDE (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIMR[10]) Received STALLed Interrupt Enable */ +#define UOTGHS_HSTPIPIMR_CRCERRE (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIMR[10]) CRC Error Interrupt Enable */ +#define UOTGHS_HSTPIPIMR_SHORTPACKETIE (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIMR[10]) Short Packet Interrupt Enable */ +#define UOTGHS_HSTPIPIMR_NBUSYBKE (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIMR[10]) Number of Busy Banks Interrupt Enable */ +#define UOTGHS_HSTPIPIMR_FIFOCON (0x1u << 14) /**< \brief (UOTGHS_HSTPIPIMR[10]) FIFO Control */ +#define UOTGHS_HSTPIPIMR_PDISHDMA (0x1u << 16) /**< \brief (UOTGHS_HSTPIPIMR[10]) Pipe Interrupts Disable HDMA Request Enable */ +#define UOTGHS_HSTPIPIMR_PFREEZE (0x1u << 17) /**< \brief (UOTGHS_HSTPIPIMR[10]) Pipe Freeze */ +#define UOTGHS_HSTPIPIMR_RSTDT (0x1u << 18) /**< \brief (UOTGHS_HSTPIPIMR[10]) Reset Data Toggle */ +/* -------- UOTGHS_HSTPIPIER[10] : (UOTGHS Offset: 0x5F0) Host Pipe Enable Register (n = 0) -------- */ +#define UOTGHS_HSTPIPIER_RXINES (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIER[10]) Received IN Data Interrupt Enable */ +#define UOTGHS_HSTPIPIER_TXOUTES (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIER[10]) Transmitted OUT Data Interrupt Enable */ +#define UOTGHS_HSTPIPIER_TXSTPES (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIER[10]) Transmitted SETUP Interrupt Enable */ +#define UOTGHS_HSTPIPIER_UNDERFIES (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIER[10]) Underflow Interrupt Enable */ +#define UOTGHS_HSTPIPIER_PERRES (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIER[10]) Pipe Error Interrupt Enable */ +#define UOTGHS_HSTPIPIER_NAKEDES (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIER[10]) NAKed Interrupt Enable */ +#define UOTGHS_HSTPIPIER_OVERFIES (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIER[10]) Overflow Interrupt Enable */ +#define UOTGHS_HSTPIPIER_RXSTALLDES (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIER[10]) Received STALLed Interrupt Enable */ +#define UOTGHS_HSTPIPIER_CRCERRES (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIER[10]) CRC Error Interrupt Enable */ +#define UOTGHS_HSTPIPIER_SHORTPACKETIES (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIER[10]) Short Packet Interrupt Enable */ +#define UOTGHS_HSTPIPIER_NBUSYBKES (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIER[10]) Number of Busy Banks Enable */ +#define UOTGHS_HSTPIPIER_PDISHDMAS (0x1u << 16) /**< \brief (UOTGHS_HSTPIPIER[10]) Pipe Interrupts Disable HDMA Request Enable */ +#define UOTGHS_HSTPIPIER_PFREEZES (0x1u << 17) /**< \brief (UOTGHS_HSTPIPIER[10]) Pipe Freeze Enable */ +#define UOTGHS_HSTPIPIER_RSTDTS (0x1u << 18) /**< \brief (UOTGHS_HSTPIPIER[10]) Reset Data Toggle Enable */ +/* -------- UOTGHS_HSTPIPIDR[10] : (UOTGHS Offset: 0x620) Host Pipe Disable Register (n = 0) -------- */ +#define UOTGHS_HSTPIPIDR_RXINEC (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIDR[10]) Received IN Data Interrupt Disable */ +#define UOTGHS_HSTPIPIDR_TXOUTEC (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIDR[10]) Transmitted OUT Data Interrupt Disable */ +#define UOTGHS_HSTPIPIDR_TXSTPEC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIDR[10]) Transmitted SETUP Interrupt Disable */ +#define UOTGHS_HSTPIPIDR_UNDERFIEC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIDR[10]) Underflow Interrupt Disable */ +#define UOTGHS_HSTPIPIDR_PERREC (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIDR[10]) Pipe Error Interrupt Disable */ +#define UOTGHS_HSTPIPIDR_NAKEDEC (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIDR[10]) NAKed Interrupt Disable */ +#define UOTGHS_HSTPIPIDR_OVERFIEC (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIDR[10]) Overflow Interrupt Disable */ +#define UOTGHS_HSTPIPIDR_RXSTALLDEC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIDR[10]) Received STALLed Interrupt Disable */ +#define UOTGHS_HSTPIPIDR_CRCERREC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIDR[10]) CRC Error Interrupt Disable */ +#define UOTGHS_HSTPIPIDR_SHORTPACKETIEC (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIDR[10]) Short Packet Interrupt Disable */ +#define UOTGHS_HSTPIPIDR_NBUSYBKEC (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIDR[10]) Number of Busy Banks Disable */ +#define UOTGHS_HSTPIPIDR_FIFOCONC (0x1u << 14) /**< \brief (UOTGHS_HSTPIPIDR[10]) FIFO Control Disable */ +#define UOTGHS_HSTPIPIDR_PDISHDMAC (0x1u << 16) /**< \brief (UOTGHS_HSTPIPIDR[10]) Pipe Interrupts Disable HDMA Request Disable */ +#define UOTGHS_HSTPIPIDR_PFREEZEC (0x1u << 17) /**< \brief (UOTGHS_HSTPIPIDR[10]) Pipe Freeze Disable */ +/* -------- UOTGHS_HSTPIPINRQ[10] : (UOTGHS Offset: 0x650) Host Pipe IN Request Register (n = 0) -------- */ +#define UOTGHS_HSTPIPINRQ_INRQ_Pos 0 +#define UOTGHS_HSTPIPINRQ_INRQ_Msk (0xffu << UOTGHS_HSTPIPINRQ_INRQ_Pos) /**< \brief (UOTGHS_HSTPIPINRQ[10]) IN Request Number before Freeze */ +#define UOTGHS_HSTPIPINRQ_INRQ(value) ((UOTGHS_HSTPIPINRQ_INRQ_Msk & ((value) << UOTGHS_HSTPIPINRQ_INRQ_Pos))) +#define UOTGHS_HSTPIPINRQ_INMODE (0x1u << 8) /**< \brief (UOTGHS_HSTPIPINRQ[10]) IN Request Mode */ +/* -------- UOTGHS_HSTPIPERR[10] : (UOTGHS Offset: 0x680) Host Pipe Error Register (n = 0) -------- */ +#define UOTGHS_HSTPIPERR_DATATGL (0x1u << 0) /**< \brief (UOTGHS_HSTPIPERR[10]) Data Toggle Error */ +#define UOTGHS_HSTPIPERR_DATAPID (0x1u << 1) /**< \brief (UOTGHS_HSTPIPERR[10]) Data PID Error */ +#define UOTGHS_HSTPIPERR_PID (0x1u << 2) /**< \brief (UOTGHS_HSTPIPERR[10]) PID Error */ +#define UOTGHS_HSTPIPERR_TIMEOUT (0x1u << 3) /**< \brief (UOTGHS_HSTPIPERR[10]) Time-Out Error */ +#define UOTGHS_HSTPIPERR_CRC16 (0x1u << 4) /**< \brief (UOTGHS_HSTPIPERR[10]) CRC16 Error */ +#define UOTGHS_HSTPIPERR_COUNTER_Pos 5 +#define UOTGHS_HSTPIPERR_COUNTER_Msk (0x3u << UOTGHS_HSTPIPERR_COUNTER_Pos) /**< \brief (UOTGHS_HSTPIPERR[10]) Error Counter */ +#define UOTGHS_HSTPIPERR_COUNTER(value) ((UOTGHS_HSTPIPERR_COUNTER_Msk & ((value) << UOTGHS_HSTPIPERR_COUNTER_Pos))) +/* -------- UOTGHS_HSTDMANXTDSC : (UOTGHS Offset: N/A) Host DMA Channel Next Descriptor Address Register -------- */ +#define UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos 0 +#define UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (UOTGHS_HSTDMANXTDSC) Next Descriptor Address */ +#define UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD(value) ((UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos))) +/* -------- UOTGHS_HSTDMAADDRESS : (UOTGHS Offset: N/A) Host DMA Channel Address Register -------- */ +#define UOTGHS_HSTDMAADDRESS_BUFF_ADD_Pos 0 +#define UOTGHS_HSTDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << UOTGHS_HSTDMAADDRESS_BUFF_ADD_Pos) /**< \brief (UOTGHS_HSTDMAADDRESS) Buffer Address */ +#define UOTGHS_HSTDMAADDRESS_BUFF_ADD(value) ((UOTGHS_HSTDMAADDRESS_BUFF_ADD_Msk & ((value) << UOTGHS_HSTDMAADDRESS_BUFF_ADD_Pos))) +/* -------- UOTGHS_HSTDMACONTROL : (UOTGHS Offset: N/A) Host DMA Channel Control Register -------- */ +#define UOTGHS_HSTDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_HSTDMACONTROL) Channel Enable Command */ +#define UOTGHS_HSTDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (UOTGHS_HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */ +#define UOTGHS_HSTDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (UOTGHS_HSTDMACONTROL) End of Transfer Enable (Control) */ +#define UOTGHS_HSTDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (UOTGHS_HSTDMACONTROL) End of Buffer Enable Control */ +#define UOTGHS_HSTDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (UOTGHS_HSTDMACONTROL) End of Transfer Interrupt Enable */ +#define UOTGHS_HSTDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (UOTGHS_HSTDMACONTROL) End of Buffer Interrupt Enable */ +#define UOTGHS_HSTDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (UOTGHS_HSTDMACONTROL) Descriptor Loaded Interrupt Enable */ +#define UOTGHS_HSTDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (UOTGHS_HSTDMACONTROL) Burst Lock Enable */ +#define UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Pos 16 +#define UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Msk (0xffffu << UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (UOTGHS_HSTDMACONTROL) Buffer Byte Length (Write-only) */ +#define UOTGHS_HSTDMACONTROL_BUFF_LENGTH(value) ((UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Msk & ((value) << UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Pos))) +/* -------- UOTGHS_HSTDMASTATUS : (UOTGHS Offset: N/A) Host DMA Channel Status Register -------- */ +#define UOTGHS_HSTDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_HSTDMASTATUS) Channel Enable Status */ +#define UOTGHS_HSTDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (UOTGHS_HSTDMASTATUS) Channel Active Status */ +#define UOTGHS_HSTDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (UOTGHS_HSTDMASTATUS) End of Channel Transfer Status */ +#define UOTGHS_HSTDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (UOTGHS_HSTDMASTATUS) End of Channel Buffer Status */ +#define UOTGHS_HSTDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (UOTGHS_HSTDMASTATUS) Descriptor Loaded Status */ +#define UOTGHS_HSTDMASTATUS_BUFF_COUNT_Pos 16 +#define UOTGHS_HSTDMASTATUS_BUFF_COUNT_Msk (0xffffu << UOTGHS_HSTDMASTATUS_BUFF_COUNT_Pos) /**< \brief (UOTGHS_HSTDMASTATUS) Buffer Byte Count */ +#define UOTGHS_HSTDMASTATUS_BUFF_COUNT(value) ((UOTGHS_HSTDMASTATUS_BUFF_COUNT_Msk & ((value) << UOTGHS_HSTDMASTATUS_BUFF_COUNT_Pos))) +/* -------- UOTGHS_CTRL : (UOTGHS Offset: 0x0800) General Control Register -------- */ +#define UOTGHS_CTRL_IDTE (0x1u << 0) /**< \brief (UOTGHS_CTRL) ID Transition Interrupt Enable */ +#define UOTGHS_CTRL_VBUSTE (0x1u << 1) /**< \brief (UOTGHS_CTRL) VBus Transition Interrupt Enable */ +#define UOTGHS_CTRL_SRPE (0x1u << 2) /**< \brief (UOTGHS_CTRL) SRP Interrupt Enable */ +#define UOTGHS_CTRL_VBERRE (0x1u << 3) /**< \brief (UOTGHS_CTRL) VBus Error Interrupt Enable */ +#define UOTGHS_CTRL_BCERRE (0x1u << 4) /**< \brief (UOTGHS_CTRL) B-Connection Error Interrupt Enable */ +#define UOTGHS_CTRL_ROLEEXE (0x1u << 5) /**< \brief (UOTGHS_CTRL) Role Exchange Interrupt Enable */ +#define UOTGHS_CTRL_HNPERRE (0x1u << 6) /**< \brief (UOTGHS_CTRL) HNP Error Interrupt Enable */ +#define UOTGHS_CTRL_STOE (0x1u << 7) /**< \brief (UOTGHS_CTRL) Suspend Time-Out Interrupt Enable */ +#define UOTGHS_CTRL_VBUSHWC (0x1u << 8) /**< \brief (UOTGHS_CTRL) VBus Hardware Control */ +#define UOTGHS_CTRL_SRPSEL (0x1u << 9) /**< \brief (UOTGHS_CTRL) SRP Selection */ +#define UOTGHS_CTRL_SRPREQ (0x1u << 10) /**< \brief (UOTGHS_CTRL) SRP Request */ +#define UOTGHS_CTRL_HNPREQ (0x1u << 11) /**< \brief (UOTGHS_CTRL) HNP Request */ +#define UOTGHS_CTRL_OTGPADE (0x1u << 12) /**< \brief (UOTGHS_CTRL) OTG Pad Enable */ +#define UOTGHS_CTRL_VBUSPO (0x1u << 13) /**< \brief (UOTGHS_CTRL) VBus Polarity Off */ +#define UOTGHS_CTRL_FRZCLK (0x1u << 14) /**< \brief (UOTGHS_CTRL) Freeze USB Clock */ +#define UOTGHS_CTRL_USBE (0x1u << 15) /**< \brief (UOTGHS_CTRL) UOTGHS Enable */ +#define UOTGHS_CTRL_TIMVALUE_Pos 16 +#define UOTGHS_CTRL_TIMVALUE_Msk (0x3u << UOTGHS_CTRL_TIMVALUE_Pos) /**< \brief (UOTGHS_CTRL) Timer Value */ +#define UOTGHS_CTRL_TIMVALUE(value) ((UOTGHS_CTRL_TIMVALUE_Msk & ((value) << UOTGHS_CTRL_TIMVALUE_Pos))) +#define UOTGHS_CTRL_TIMPAGE_Pos 20 +#define UOTGHS_CTRL_TIMPAGE_Msk (0x3u << UOTGHS_CTRL_TIMPAGE_Pos) /**< \brief (UOTGHS_CTRL) Timer Page */ +#define UOTGHS_CTRL_TIMPAGE(value) ((UOTGHS_CTRL_TIMPAGE_Msk & ((value) << UOTGHS_CTRL_TIMPAGE_Pos))) +#define UOTGHS_CTRL_UNLOCK (0x1u << 22) /**< \brief (UOTGHS_CTRL) Timer Access Unlock */ +#define UOTGHS_CTRL_UIDE (0x1u << 24) /**< \brief (UOTGHS_CTRL) UOTGID Pin Enable */ +#define UOTGHS_CTRL_UIDE_UIMOD (0x0u << 24) /**< \brief (UOTGHS_CTRL) The USB mode (device/host) is selected from the UIMOD bit. */ +#define UOTGHS_CTRL_UIDE_UOTGID (0x1u << 24) /**< \brief (UOTGHS_CTRL) The USB mode (device/host) is selected from the UOTGID input pin. */ +#define UOTGHS_CTRL_UIMOD (0x1u << 25) /**< \brief (UOTGHS_CTRL) UOTGHS Mode */ +#define UOTGHS_CTRL_UIMOD_Host (0x0u << 25) /**< \brief (UOTGHS_CTRL) The module is in USB host mode. */ +#define UOTGHS_CTRL_UIMOD_Device (0x1u << 25) /**< \brief (UOTGHS_CTRL) The module is in USB device mode. */ +/* -------- UOTGHS_SR : (UOTGHS Offset: 0x0804) General Status Register -------- */ +#define UOTGHS_SR_IDTI (0x1u << 0) /**< \brief (UOTGHS_SR) ID Transition Interrupt */ +#define UOTGHS_SR_VBUSTI (0x1u << 1) /**< \brief (UOTGHS_SR) VBus Transition Interrupt */ +#define UOTGHS_SR_SRPI (0x1u << 2) /**< \brief (UOTGHS_SR) SRP Interrupt */ +#define UOTGHS_SR_VBERRI (0x1u << 3) /**< \brief (UOTGHS_SR) VBus Error Interrupt */ +#define UOTGHS_SR_BCERRI (0x1u << 4) /**< \brief (UOTGHS_SR) B-Connection Error Interrupt */ +#define UOTGHS_SR_ROLEEXI (0x1u << 5) /**< \brief (UOTGHS_SR) Role Exchange Interrupt */ +#define UOTGHS_SR_HNPERRI (0x1u << 6) /**< \brief (UOTGHS_SR) HNP Error Interrupt */ +#define UOTGHS_SR_STOI (0x1u << 7) /**< \brief (UOTGHS_SR) Suspend Time-Out Interrupt */ +#define UOTGHS_SR_VBUSRQ (0x1u << 9) /**< \brief (UOTGHS_SR) VBus Request */ +#define UOTGHS_SR_ID (0x1u << 10) /**< \brief (UOTGHS_SR) UOTGID Pin State */ +#define UOTGHS_SR_VBUS (0x1u << 11) /**< \brief (UOTGHS_SR) VBus Level */ +#define UOTGHS_SR_SPEED_Pos 12 +#define UOTGHS_SR_SPEED_Msk (0x3u << UOTGHS_SR_SPEED_Pos) /**< \brief (UOTGHS_SR) Speed Status */ +#define UOTGHS_SR_SPEED_FULL_SPEED (0x0u << 12) /**< \brief (UOTGHS_SR) Full-Speed mode */ +#define UOTGHS_SR_SPEED_HIGH_SPEED (0x1u << 12) /**< \brief (UOTGHS_SR) High-Speed mode */ +#define UOTGHS_SR_SPEED_LOW_SPEED (0x2u << 12) /**< \brief (UOTGHS_SR) Low-Speed mode */ +#define UOTGHS_SR_CLKUSABLE (0x1u << 14) /**< \brief (UOTGHS_SR) UTMI Clock Usable */ +/* -------- UOTGHS_SCR : (UOTGHS Offset: 0x0808) General Status Clear Register -------- */ +#define UOTGHS_SCR_IDTIC (0x1u << 0) /**< \brief (UOTGHS_SCR) ID Transition Interrupt Clear */ +#define UOTGHS_SCR_VBUSTIC (0x1u << 1) /**< \brief (UOTGHS_SCR) VBus Transition Interrupt Clear */ +#define UOTGHS_SCR_SRPIC (0x1u << 2) /**< \brief (UOTGHS_SCR) SRP Interrupt Clear */ +#define UOTGHS_SCR_VBERRIC (0x1u << 3) /**< \brief (UOTGHS_SCR) VBus Error Interrupt Clear */ +#define UOTGHS_SCR_BCERRIC (0x1u << 4) /**< \brief (UOTGHS_SCR) B-Connection Error Interrupt Clear */ +#define UOTGHS_SCR_ROLEEXIC (0x1u << 5) /**< \brief (UOTGHS_SCR) Role Exchange Interrupt Clear */ +#define UOTGHS_SCR_HNPERRIC (0x1u << 6) /**< \brief (UOTGHS_SCR) HNP Error Interrupt Clear */ +#define UOTGHS_SCR_STOIC (0x1u << 7) /**< \brief (UOTGHS_SCR) Suspend Time-Out Interrupt Clear */ +#define UOTGHS_SCR_VBUSRQC (0x1u << 9) /**< \brief (UOTGHS_SCR) VBus Request Clear */ +/* -------- UOTGHS_SFR : (UOTGHS Offset: 0x080C) General Status Set Register -------- */ +#define UOTGHS_SFR_IDTIS (0x1u << 0) /**< \brief (UOTGHS_SFR) ID Transition Interrupt Set */ +#define UOTGHS_SFR_VBUSTIS (0x1u << 1) /**< \brief (UOTGHS_SFR) VBus Transition Interrupt Set */ +#define UOTGHS_SFR_SRPIS (0x1u << 2) /**< \brief (UOTGHS_SFR) SRP Interrupt Set */ +#define UOTGHS_SFR_VBERRIS (0x1u << 3) /**< \brief (UOTGHS_SFR) VBus Error Interrupt Set */ +#define UOTGHS_SFR_BCERRIS (0x1u << 4) /**< \brief (UOTGHS_SFR) B-Connection Error Interrupt Set */ +#define UOTGHS_SFR_ROLEEXIS (0x1u << 5) /**< \brief (UOTGHS_SFR) Role Exchange Interrupt Set */ +#define UOTGHS_SFR_HNPERRIS (0x1u << 6) /**< \brief (UOTGHS_SFR) HNP Error Interrupt Set */ +#define UOTGHS_SFR_STOIS (0x1u << 7) /**< \brief (UOTGHS_SFR) Suspend Time-Out Interrupt Set */ +#define UOTGHS_SFR_VBUSRQS (0x1u << 9) /**< \brief (UOTGHS_SFR) VBus Request Set */ +/* -------- UOTGHS_FSM : (UOTGHS Offset: 0x082C) General Finite State Machine Register -------- */ +#define UOTGHS_FSM_DRDSTATE_Pos 0 +#define UOTGHS_FSM_DRDSTATE_Msk (0xfu << UOTGHS_FSM_DRDSTATE_Pos) /**< \brief (UOTGHS_FSM) */ +#define UOTGHS_FSM_DRDSTATE_A_IDLESTATE (0x0u << 0) /**< \brief (UOTGHS_FSM) This is the start state for A-devices (when the ID pin is 0) */ +#define UOTGHS_FSM_DRDSTATE_A_WAIT_VRISE (0x1u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the voltage on VBus to rise above the A-device VBus Valid threshold (4.4 V). */ +#define UOTGHS_FSM_DRDSTATE_A_WAIT_BCON (0x2u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the B-device to signal a connection. */ +#define UOTGHS_FSM_DRDSTATE_A_HOST (0x3u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device that operates in Host mode is operational. */ +#define UOTGHS_FSM_DRDSTATE_A_SUSPEND (0x4u << 0) /**< \brief (UOTGHS_FSM) The A-device operating as a host is in the suspend mode. */ +#define UOTGHS_FSM_DRDSTATE_A_PERIPHERAL (0x5u << 0) /**< \brief (UOTGHS_FSM) The A-device operates as a peripheral. */ +#define UOTGHS_FSM_DRDSTATE_A_WAIT_VFALL (0x6u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the voltage on VBus to drop below the A-device Session Valid threshold (1.4 V). */ +#define UOTGHS_FSM_DRDSTATE_A_VBUS_ERR (0x7u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for recovery of the over-current condition that caused it to enter this state. */ +#define UOTGHS_FSM_DRDSTATE_A_WAIT_DISCHARGE (0x8u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the data USB line to discharge (100 us). */ +#define UOTGHS_FSM_DRDSTATE_B_IDLE (0x9u << 0) /**< \brief (UOTGHS_FSM) This is the start state for B-device (when the ID pin is 1). */ +#define UOTGHS_FSM_DRDSTATE_B_PERIPHERAL (0xAu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device acts as the peripheral. */ +#define UOTGHS_FSM_DRDSTATE_B_WAIT_BEGIN_HNP (0xBu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device is in suspend mode and waits until 3 ms before initiating the HNP protocol if requested. */ +#define UOTGHS_FSM_DRDSTATE_B_WAIT_DISCHARGE (0xCu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device waits for the data USB line to discharge (100 us) before becoming Host. */ +#define UOTGHS_FSM_DRDSTATE_B_WAIT_ACON (0xDu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device waits for the A-device to signal a connect before becoming B-Host. */ +#define UOTGHS_FSM_DRDSTATE_B_HOST (0xEu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device acts as the Host. */ +#define UOTGHS_FSM_DRDSTATE_B_SRP_INIT (0xFu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device attempts to start a session using the SRP protocol. */ + +/*@}*/ + + +#endif /* _SAM3XA_UOTGHS_COMPONENT_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h new file mode 100644 index 0000000..e9e7b7d --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_usart.h @@ -0,0 +1,411 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_USART_COMPONENT_ +#define _SAM3XA_USART_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */ +/* ============================================================================= */ +/** \addtogroup SAM3XA_USART Universal Synchronous Asynchronous Receiver Transmitter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Usart hardware registers */ +typedef struct { + WoReg US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */ + RwReg US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */ + WoReg US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */ + WoReg US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */ + RoReg US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */ + RoReg US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */ + RoReg US_RHR; /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */ + WoReg US_THR; /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */ + RwReg US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */ + RwReg US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */ + RwReg US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */ + RoReg Reserved1[5]; + RwReg US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */ + RoReg US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */ + RoReg Reserved2[1]; + RwReg US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */ + RwReg US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */ + RwReg US_LINMR; /**< \brief (Usart Offset: 0x0054) LIN Mode Register */ + RwReg US_LINIR; /**< \brief (Usart Offset: 0x0058) LIN Identifier Register */ + RoReg Reserved3[34]; + RwReg US_WPMR; /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */ + RoReg US_WPSR; /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */ + RoReg Reserved4[5]; + RwReg US_RPR; /**< \brief (Usart Offset: 0x100) Receive Pointer Register */ + RwReg US_RCR; /**< \brief (Usart Offset: 0x104) Receive Counter Register */ + RwReg US_TPR; /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */ + RwReg US_TCR; /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */ + RwReg US_RNPR; /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */ + RwReg US_RNCR; /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */ + RwReg US_TNPR; /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */ + RwReg US_TNCR; /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */ + WoReg US_PTCR; /**< \brief (Usart Offset: 0x120) Transfer Control Register */ + RoReg US_PTSR; /**< \brief (Usart Offset: 0x124) Transfer Status Register */ +} Usart; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */ +#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */ +#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */ +#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */ +#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */ +#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */ +#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */ +#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */ +#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */ +#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */ +#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Start Time-out */ +#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */ +#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */ +#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */ +#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Rearm Time-out */ +#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */ +#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */ +#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */ +#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */ +#define US_CR_LINABT (0x1u << 20) /**< \brief (US_CR) Abort LIN Transmission */ +#define US_CR_LINWKUP (0x1u << 21) /**< \brief (US_CR) Send LIN Wakeup Signal */ +/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */ +#define US_MR_USART_MODE_Pos 0 +#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR) */ +#define US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */ +#define US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */ +#define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */ +#define US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */ +#define US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */ +#define US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */ +#define US_MR_USART_MODE_LIN_MASTER (0xAu << 0) /**< \brief (US_MR) LIN Master */ +#define US_MR_USART_MODE_LIN_SLAVE (0xBu << 0) /**< \brief (US_MR) LIN Slave */ +#define US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI Master */ +#define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */ +#define US_MR_USCLKS_Pos 4 +#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */ +#define US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Master Clock MCK is selected */ +#define US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Internal Clock Divided MCK/DIV (DIV=8) is selected */ +#define US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial Clock SLK is selected */ +#define US_MR_CHRL_Pos 6 +#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length. */ +#define US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */ +#define US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */ +#define US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */ +#define US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */ +#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */ +#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */ +#define US_MR_PAR_Pos 9 +#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */ +#define US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */ +#define US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */ +#define US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */ +#define US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */ +#define US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */ +#define US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */ +#define US_MR_NBSTOP_Pos 12 +#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */ +#define US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */ +#define US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */ +#define US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */ +#define US_MR_CHMODE_Pos 14 +#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */ +#define US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal Mode */ +#define US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */ +#define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */ +#define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */ +#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */ +#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */ +#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */ +#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */ +#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */ +#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */ +#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */ +#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */ +#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) INverted Data */ +#define US_MR_MAX_ITERATION_Pos 24 +#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR) */ +#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos))) +#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Infrared Receive Line Filter */ +#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */ +#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */ +#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */ +/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */ +#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */ +#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */ +#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */ +#define US_IER_ENDRX (0x1u << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */ +#define US_IER_ENDTX (0x1u << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */ +#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */ +#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */ +#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */ +#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */ +#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */ +#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached */ +#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error */ +#define US_IER_TXBUFE (0x1u << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */ +#define US_IER_RXBUFF (0x1u << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */ +#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non Acknowledge Interrupt Enable */ +#define US_IER_LINBK (0x1u << 13) /**< \brief (US_IER) LIN Break Sent or LIN Break Received Interrupt Enable */ +#define US_IER_LINID (0x1u << 14) /**< \brief (US_IER) LIN Identifier Sent or LIN Identifier Received Interrupt Enable */ +#define US_IER_LINTC (0x1u << 15) /**< \brief (US_IER) LIN Transfer Completed Interrupt Enable */ +#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */ +#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */ +#define US_IER_LINBE (0x1u << 25) /**< \brief (US_IER) LIN Bus Error Interrupt Enable */ +#define US_IER_LINISFE (0x1u << 26) /**< \brief (US_IER) LIN Inconsistent Synch Field Error Interrupt Enable */ +#define US_IER_LINIPE (0x1u << 27) /**< \brief (US_IER) LIN Identifier Parity Interrupt Enable */ +#define US_IER_LINCE (0x1u << 28) /**< \brief (US_IER) LIN Checksum Error Interrupt Enable */ +#define US_IER_LINSNRE (0x1u << 29) /**< \brief (US_IER) LIN Slave Not Responding Error Interrupt Enable */ +/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */ +#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */ +#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */ +#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */ +#define US_IDR_ENDRX (0x1u << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */ +#define US_IDR_ENDTX (0x1u << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */ +#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */ +#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */ +#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */ +#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */ +#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */ +#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max number of Repetitions Reached Disable */ +#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Disable */ +#define US_IDR_TXBUFE (0x1u << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */ +#define US_IDR_RXBUFF (0x1u << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */ +#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non Acknowledge Interrupt Disable */ +#define US_IDR_LINBK (0x1u << 13) /**< \brief (US_IDR) LIN Break Sent or LIN Break Received Interrupt Disable */ +#define US_IDR_LINID (0x1u << 14) /**< \brief (US_IDR) LIN Identifier Sent or LIN Identifier Received Interrupt Disable */ +#define US_IDR_LINTC (0x1u << 15) /**< \brief (US_IDR) LIN Transfer Completed Interrupt Disable */ +#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */ +#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */ +#define US_IDR_LINBE (0x1u << 25) /**< \brief (US_IDR) LIN Bus Error Interrupt Disable */ +#define US_IDR_LINISFE (0x1u << 26) /**< \brief (US_IDR) LIN Inconsistent Synch Field Error Interrupt Disable */ +#define US_IDR_LINIPE (0x1u << 27) /**< \brief (US_IDR) LIN Identifier Parity Interrupt Disable */ +#define US_IDR_LINCE (0x1u << 28) /**< \brief (US_IDR) LIN Checksum Error Interrupt Disable */ +#define US_IDR_LINSNRE (0x1u << 29) /**< \brief (US_IDR) LIN Slave Not Responding Error Interrupt Disable */ +/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */ +#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */ +#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */ +#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */ +#define US_IMR_ENDRX (0x1u << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */ +#define US_IMR_ENDTX (0x1u << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */ +#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */ +#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */ +#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */ +#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */ +#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */ +#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max number of Repetitions Reached Mask */ +#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Mask */ +#define US_IMR_TXBUFE (0x1u << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */ +#define US_IMR_RXBUFF (0x1u << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */ +#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non Acknowledge Interrupt Mask */ +#define US_IMR_LINBK (0x1u << 13) /**< \brief (US_IMR) LIN Break Sent or LIN Break Received Interrupt Mask */ +#define US_IMR_LINID (0x1u << 14) /**< \brief (US_IMR) LIN Identifier Sent or LIN Identifier Received Interrupt Mask */ +#define US_IMR_LINTC (0x1u << 15) /**< \brief (US_IMR) LIN Transfer Completed Interrupt Mask */ +#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */ +#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */ +#define US_IMR_LINBE (0x1u << 25) /**< \brief (US_IMR) LIN Bus Error Interrupt Mask */ +#define US_IMR_LINISFE (0x1u << 26) /**< \brief (US_IMR) LIN Inconsistent Synch Field Error Interrupt Mask */ +#define US_IMR_LINIPE (0x1u << 27) /**< \brief (US_IMR) LIN Identifier Parity Interrupt Mask */ +#define US_IMR_LINCE (0x1u << 28) /**< \brief (US_IMR) LIN Checksum Error Interrupt Mask */ +#define US_IMR_LINSNRE (0x1u << 29) /**< \brief (US_IMR) LIN Slave Not Responding Error Interrupt Mask */ +/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */ +#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready */ +#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready */ +#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break */ +#define US_CSR_ENDRX (0x1u << 3) /**< \brief (US_CSR) End of Receiver Transfer */ +#define US_CSR_ENDTX (0x1u << 4) /**< \brief (US_CSR) End of Transmitter Transfer */ +#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error */ +#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error */ +#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error */ +#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out */ +#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty */ +#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max number of Repetitions Reached */ +#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) SPI Underrun Error */ +#define US_CSR_TXBUFE (0x1u << 11) /**< \brief (US_CSR) Transmission Buffer Empty */ +#define US_CSR_RXBUFF (0x1u << 12) /**< \brief (US_CSR) Reception Buffer Full */ +#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non Acknowledge Interrupt */ +#define US_CSR_LINBK (0x1u << 13) /**< \brief (US_CSR) LIN Break Sent or LIN Break Received */ +#define US_CSR_LINID (0x1u << 14) /**< \brief (US_CSR) LIN Identifier Sent or LIN Identifier Received */ +#define US_CSR_LINTC (0x1u << 15) /**< \brief (US_CSR) LIN Transfer Completed */ +#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */ +#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */ +#define US_CSR_LINBLS (0x1u << 23) /**< \brief (US_CSR) LIN Bus Line Status */ +#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error */ +#define US_CSR_LINBE (0x1u << 25) /**< \brief (US_CSR) LIN Bit Error */ +#define US_CSR_LINISFE (0x1u << 26) /**< \brief (US_CSR) LIN Inconsistent Synch Field Error */ +#define US_CSR_LINIPE (0x1u << 27) /**< \brief (US_CSR) LIN Identifier Parity Error */ +#define US_CSR_LINCE (0x1u << 28) /**< \brief (US_CSR) LIN Checksum Error */ +#define US_CSR_LINSNRE (0x1u << 29) /**< \brief (US_CSR) LIN Slave Not Responding Error */ +/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */ +#define US_RHR_RXCHR_Pos 0 +#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */ +#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */ +/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */ +#define US_THR_TXCHR_Pos 0 +#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */ +#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos))) +#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be transmitted */ +/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */ +#define US_BRGR_CD_Pos 0 +#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */ +#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos))) +#define US_BRGR_FP_Pos 16 +#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */ +#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos))) +/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */ +#define US_RTOR_TO_Pos 0 +#define US_RTOR_TO_Msk (0x1ffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */ +#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos))) +/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */ +#define US_TTGR_TG_Pos 0 +#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */ +#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos))) +/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */ +#define US_FIDI_FI_DI_RATIO_Pos 0 +#define US_FIDI_FI_DI_RATIO_Msk (0x7ffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */ +#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos))) +/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */ +#define US_NER_NB_ERRORS_Pos 0 +#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */ +/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */ +#define US_IF_IRDA_FILTER_Pos 0 +#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */ +#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos))) +/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */ +#define US_MAN_TX_PL_Pos 0 +#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */ +#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos))) +#define US_MAN_TX_PP_Pos 8 +#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */ +#define US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */ +#define US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */ +#define US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */ +#define US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */ +#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */ +#define US_MAN_RX_PL_Pos 16 +#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */ +#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos))) +#define US_MAN_RX_PP_Pos 24 +#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */ +#define US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */ +#define US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */ +#define US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */ +#define US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */ +#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */ +#define US_MAN_STUCKTO1 (0x1u << 29) /**< \brief (US_MAN) */ +#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift compensation */ +/* -------- US_LINMR : (USART Offset: 0x0054) LIN Mode Register -------- */ +#define US_LINMR_NACT_Pos 0 +#define US_LINMR_NACT_Msk (0x3u << US_LINMR_NACT_Pos) /**< \brief (US_LINMR) LIN Node Action */ +#define US_LINMR_NACT_PUBLISH (0x0u << 0) /**< \brief (US_LINMR) The USART transmits the response. */ +#define US_LINMR_NACT_SUBSCRIBE (0x1u << 0) /**< \brief (US_LINMR) The USART receives the response. */ +#define US_LINMR_NACT_IGNORE (0x2u << 0) /**< \brief (US_LINMR) The USART does not transmit and does not receive the response. */ +#define US_LINMR_PARDIS (0x1u << 2) /**< \brief (US_LINMR) Parity Disable */ +#define US_LINMR_CHKDIS (0x1u << 3) /**< \brief (US_LINMR) Checksum Disable */ +#define US_LINMR_CHKTYP (0x1u << 4) /**< \brief (US_LINMR) Checksum Type */ +#define US_LINMR_DLM (0x1u << 5) /**< \brief (US_LINMR) Data Length Mode */ +#define US_LINMR_FSDIS (0x1u << 6) /**< \brief (US_LINMR) Frame Slot Mode Disable */ +#define US_LINMR_WKUPTYP (0x1u << 7) /**< \brief (US_LINMR) Wakeup Signal Type */ +#define US_LINMR_DLC_Pos 8 +#define US_LINMR_DLC_Msk (0xffu << US_LINMR_DLC_Pos) /**< \brief (US_LINMR) Data Length Control */ +#define US_LINMR_DLC(value) ((US_LINMR_DLC_Msk & ((value) << US_LINMR_DLC_Pos))) +#define US_LINMR_PDCM (0x1u << 16) /**< \brief (US_LINMR) PDC Mode */ +/* -------- US_LINIR : (USART Offset: 0x0058) LIN Identifier Register -------- */ +#define US_LINIR_IDCHR_Pos 0 +#define US_LINIR_IDCHR_Msk (0xffu << US_LINIR_IDCHR_Pos) /**< \brief (US_LINIR) Identifier Character */ +#define US_LINIR_IDCHR(value) ((US_LINIR_IDCHR_Msk & ((value) << US_LINIR_IDCHR_Pos))) +/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */ +#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protect Enable */ +#define US_WPMR_WPKEY_Pos 8 +#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protect KEY */ +#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos))) +/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */ +#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protect Violation Status */ +#define US_WPSR_WPVSRC_Pos 8 +#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protect Violation Source */ +/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */ +#define US_RPR_RXPTR_Pos 0 +#define US_RPR_RXPTR_Msk (0xffffffffu << US_RPR_RXPTR_Pos) /**< \brief (US_RPR) Receive Pointer Register */ +#define US_RPR_RXPTR(value) ((US_RPR_RXPTR_Msk & ((value) << US_RPR_RXPTR_Pos))) +/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */ +#define US_RCR_RXCTR_Pos 0 +#define US_RCR_RXCTR_Msk (0xffffu << US_RCR_RXCTR_Pos) /**< \brief (US_RCR) Receive Counter Register */ +#define US_RCR_RXCTR(value) ((US_RCR_RXCTR_Msk & ((value) << US_RCR_RXCTR_Pos))) +/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */ +#define US_TPR_TXPTR_Pos 0 +#define US_TPR_TXPTR_Msk (0xffffffffu << US_TPR_TXPTR_Pos) /**< \brief (US_TPR) Transmit Counter Register */ +#define US_TPR_TXPTR(value) ((US_TPR_TXPTR_Msk & ((value) << US_TPR_TXPTR_Pos))) +/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */ +#define US_TCR_TXCTR_Pos 0 +#define US_TCR_TXCTR_Msk (0xffffu << US_TCR_TXCTR_Pos) /**< \brief (US_TCR) Transmit Counter Register */ +#define US_TCR_TXCTR(value) ((US_TCR_TXCTR_Msk & ((value) << US_TCR_TXCTR_Pos))) +/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */ +#define US_RNPR_RXNPTR_Pos 0 +#define US_RNPR_RXNPTR_Msk (0xffffffffu << US_RNPR_RXNPTR_Pos) /**< \brief (US_RNPR) Receive Next Pointer */ +#define US_RNPR_RXNPTR(value) ((US_RNPR_RXNPTR_Msk & ((value) << US_RNPR_RXNPTR_Pos))) +/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */ +#define US_RNCR_RXNCTR_Pos 0 +#define US_RNCR_RXNCTR_Msk (0xffffu << US_RNCR_RXNCTR_Pos) /**< \brief (US_RNCR) Receive Next Counter */ +#define US_RNCR_RXNCTR(value) ((US_RNCR_RXNCTR_Msk & ((value) << US_RNCR_RXNCTR_Pos))) +/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */ +#define US_TNPR_TXNPTR_Pos 0 +#define US_TNPR_TXNPTR_Msk (0xffffffffu << US_TNPR_TXNPTR_Pos) /**< \brief (US_TNPR) Transmit Next Pointer */ +#define US_TNPR_TXNPTR(value) ((US_TNPR_TXNPTR_Msk & ((value) << US_TNPR_TXNPTR_Pos))) +/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */ +#define US_TNCR_TXNCTR_Pos 0 +#define US_TNCR_TXNCTR_Msk (0xffffu << US_TNCR_TXNCTR_Pos) /**< \brief (US_TNCR) Transmit Counter Next */ +#define US_TNCR_TXNCTR(value) ((US_TNCR_TXNCTR_Msk & ((value) << US_TNCR_TXNCTR_Pos))) +/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */ +#define US_PTCR_RXTEN (0x1u << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */ +#define US_PTCR_RXTDIS (0x1u << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */ +#define US_PTCR_TXTEN (0x1u << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */ +#define US_PTCR_TXTDIS (0x1u << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */ +/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */ +#define US_PTSR_RXTEN (0x1u << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */ +#define US_PTSR_TXTEN (0x1u << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + + +#endif /* _SAM3XA_USART_COMPONENT_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h new file mode 100644 index 0000000..0b0b323 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/component/component_wdt.h @@ -0,0 +1,87 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_WDT_COMPONENT_ +#define _SAM3XA_WDT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Watchdog Timer */ +/* ============================================================================= */ +/** \addtogroup SAM3XA_WDT Watchdog Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Wdt hardware registers */ +typedef struct { + WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */ + RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */ + RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */ +} Wdt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */ +#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */ +#define WDT_CR_KEY_Pos 24 +#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */ +#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos))) +/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */ +#define WDT_MR_WDV_Pos 0 +#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */ +#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos))) +#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */ +#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */ +#define WDT_MR_WDRPROC (0x1u << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */ +#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */ +#define WDT_MR_WDD_Pos 16 +#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */ +#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos))) +#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */ +#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */ +/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */ +#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow */ +#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error */ + +/*@}*/ + + +#endif /* _SAM3XA_WDT_COMPONENT_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h new file mode 100644 index 0000000..f609ee6 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_adc.h @@ -0,0 +1,107 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_ADC_INSTANCE_ +#define _SAM3XA_ADC_INSTANCE_ + +/* ========== Register definition for ADC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_ADC_CR (0x400C0000U) /**< \brief (ADC) Control Register */ +#define REG_ADC_MR (0x400C0004U) /**< \brief (ADC) Mode Register */ +#define REG_ADC_SEQR1 (0x400C0008U) /**< \brief (ADC) Channel Sequence Register 1 */ +#define REG_ADC_SEQR2 (0x400C000CU) /**< \brief (ADC) Channel Sequence Register 2 */ +#define REG_ADC_CHER (0x400C0010U) /**< \brief (ADC) Channel Enable Register */ +#define REG_ADC_CHDR (0x400C0014U) /**< \brief (ADC) Channel Disable Register */ +#define REG_ADC_CHSR (0x400C0018U) /**< \brief (ADC) Channel Status Register */ +#define REG_ADC_LCDR (0x400C0020U) /**< \brief (ADC) Last Converted Data Register */ +#define REG_ADC_IER (0x400C0024U) /**< \brief (ADC) Interrupt Enable Register */ +#define REG_ADC_IDR (0x400C0028U) /**< \brief (ADC) Interrupt Disable Register */ +#define REG_ADC_IMR (0x400C002CU) /**< \brief (ADC) Interrupt Mask Register */ +#define REG_ADC_ISR (0x400C0030U) /**< \brief (ADC) Interrupt Status Register */ +#define REG_ADC_OVER (0x400C003CU) /**< \brief (ADC) Overrun Status Register */ +#define REG_ADC_EMR (0x400C0040U) /**< \brief (ADC) Extended Mode Register */ +#define REG_ADC_CWR (0x400C0044U) /**< \brief (ADC) Compare Window Register */ +#define REG_ADC_CGR (0x400C0048U) /**< \brief (ADC) Channel Gain Register */ +#define REG_ADC_COR (0x400C004CU) /**< \brief (ADC) Channel Offset Register */ +#define REG_ADC_CDR (0x400C0050U) /**< \brief (ADC) Channel Data Register */ +#define REG_ADC_ACR (0x400C0094U) /**< \brief (ADC) Analog Control Register */ +#define REG_ADC_WPMR (0x400C00E4U) /**< \brief (ADC) Write Protect Mode Register */ +#define REG_ADC_WPSR (0x400C00E8U) /**< \brief (ADC) Write Protect Status Register */ +#define REG_ADC_RPR (0x400C0100U) /**< \brief (ADC) Receive Pointer Register */ +#define REG_ADC_RCR (0x400C0104U) /**< \brief (ADC) Receive Counter Register */ +#define REG_ADC_RNPR (0x400C0110U) /**< \brief (ADC) Receive Next Pointer Register */ +#define REG_ADC_RNCR (0x400C0114U) /**< \brief (ADC) Receive Next Counter Register */ +#define REG_ADC_PTCR (0x400C0120U) /**< \brief (ADC) Transfer Control Register */ +#define REG_ADC_PTSR (0x400C0124U) /**< \brief (ADC) Transfer Status Register */ +#else +#define REG_ADC_CR (*(WoReg*)0x400C0000U) /**< \brief (ADC) Control Register */ +#define REG_ADC_MR (*(RwReg*)0x400C0004U) /**< \brief (ADC) Mode Register */ +#define REG_ADC_SEQR1 (*(RwReg*)0x400C0008U) /**< \brief (ADC) Channel Sequence Register 1 */ +#define REG_ADC_SEQR2 (*(RwReg*)0x400C000CU) /**< \brief (ADC) Channel Sequence Register 2 */ +#define REG_ADC_CHER (*(WoReg*)0x400C0010U) /**< \brief (ADC) Channel Enable Register */ +#define REG_ADC_CHDR (*(WoReg*)0x400C0014U) /**< \brief (ADC) Channel Disable Register */ +#define REG_ADC_CHSR (*(RoReg*)0x400C0018U) /**< \brief (ADC) Channel Status Register */ +#define REG_ADC_LCDR (*(RoReg*)0x400C0020U) /**< \brief (ADC) Last Converted Data Register */ +#define REG_ADC_IER (*(WoReg*)0x400C0024U) /**< \brief (ADC) Interrupt Enable Register */ +#define REG_ADC_IDR (*(WoReg*)0x400C0028U) /**< \brief (ADC) Interrupt Disable Register */ +#define REG_ADC_IMR (*(RoReg*)0x400C002CU) /**< \brief (ADC) Interrupt Mask Register */ +#define REG_ADC_ISR (*(RoReg*)0x400C0030U) /**< \brief (ADC) Interrupt Status Register */ +#define REG_ADC_OVER (*(RoReg*)0x400C003CU) /**< \brief (ADC) Overrun Status Register */ +#define REG_ADC_EMR (*(RwReg*)0x400C0040U) /**< \brief (ADC) Extended Mode Register */ +#define REG_ADC_CWR (*(RwReg*)0x400C0044U) /**< \brief (ADC) Compare Window Register */ +#define REG_ADC_CGR (*(RwReg*)0x400C0048U) /**< \brief (ADC) Channel Gain Register */ +#define REG_ADC_COR (*(RwReg*)0x400C004CU) /**< \brief (ADC) Channel Offset Register */ +#define REG_ADC_CDR (*(RoReg*)0x400C0050U) /**< \brief (ADC) Channel Data Register */ +#define REG_ADC_ACR (*(RwReg*)0x400C0094U) /**< \brief (ADC) Analog Control Register */ +#define REG_ADC_WPMR (*(RwReg*)0x400C00E4U) /**< \brief (ADC) Write Protect Mode Register */ +#define REG_ADC_WPSR (*(RoReg*)0x400C00E8U) /**< \brief (ADC) Write Protect Status Register */ +#define REG_ADC_RPR (*(RwReg*)0x400C0100U) /**< \brief (ADC) Receive Pointer Register */ +#define REG_ADC_RCR (*(RwReg*)0x400C0104U) /**< \brief (ADC) Receive Counter Register */ +#define REG_ADC_RNPR (*(RwReg*)0x400C0110U) /**< \brief (ADC) Receive Next Pointer Register */ +#define REG_ADC_RNCR (*(RwReg*)0x400C0114U) /**< \brief (ADC) Receive Next Counter Register */ +#define REG_ADC_PTCR (*(WoReg*)0x400C0120U) /**< \brief (ADC) Transfer Control Register */ +#define REG_ADC_PTSR (*(RoReg*)0x400C0124U) /**< \brief (ADC) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_ADC_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h new file mode 100644 index 0000000..a7aa2cc --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can0.h @@ -0,0 +1,207 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_CAN0_INSTANCE_ +#define _SAM3XA_CAN0_INSTANCE_ + +/* ========== Register definition for CAN0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_CAN0_MR (0x400B4000U) /**< \brief (CAN0) Mode Register */ +#define REG_CAN0_IER (0x400B4004U) /**< \brief (CAN0) Interrupt Enable Register */ +#define REG_CAN0_IDR (0x400B4008U) /**< \brief (CAN0) Interrupt Disable Register */ +#define REG_CAN0_IMR (0x400B400CU) /**< \brief (CAN0) Interrupt Mask Register */ +#define REG_CAN0_SR (0x400B4010U) /**< \brief (CAN0) Status Register */ +#define REG_CAN0_BR (0x400B4014U) /**< \brief (CAN0) Baudrate Register */ +#define REG_CAN0_TIM (0x400B4018U) /**< \brief (CAN0) Timer Register */ +#define REG_CAN0_TIMESTP (0x400B401CU) /**< \brief (CAN0) Timestamp Register */ +#define REG_CAN0_ECR (0x400B4020U) /**< \brief (CAN0) Error Counter Register */ +#define REG_CAN0_TCR (0x400B4024U) /**< \brief (CAN0) Transfer Command Register */ +#define REG_CAN0_ACR (0x400B4028U) /**< \brief (CAN0) Abort Command Register */ +#define REG_CAN0_WPMR (0x400B40E4U) /**< \brief (CAN0) Write Protect Mode Register */ +#define REG_CAN0_WPSR (0x400B40E8U) /**< \brief (CAN0) Write Protect Status Register */ +#define REG_CAN0_MMR0 (0x400B4200U) /**< \brief (CAN0) Mailbox Mode Register (MB = 0) */ +#define REG_CAN0_MAM0 (0x400B4204U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 0) */ +#define REG_CAN0_MID0 (0x400B4208U) /**< \brief (CAN0) Mailbox ID Register (MB = 0) */ +#define REG_CAN0_MFID0 (0x400B420CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 0) */ +#define REG_CAN0_MSR0 (0x400B4210U) /**< \brief (CAN0) Mailbox Status Register (MB = 0) */ +#define REG_CAN0_MDL0 (0x400B4214U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 0) */ +#define REG_CAN0_MDH0 (0x400B4218U) /**< \brief (CAN0) Mailbox Data High Register (MB = 0) */ +#define REG_CAN0_MCR0 (0x400B421CU) /**< \brief (CAN0) Mailbox Control Register (MB = 0) */ +#define REG_CAN0_MMR1 (0x400B4220U) /**< \brief (CAN0) Mailbox Mode Register (MB = 1) */ +#define REG_CAN0_MAM1 (0x400B4224U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 1) */ +#define REG_CAN0_MID1 (0x400B4228U) /**< \brief (CAN0) Mailbox ID Register (MB = 1) */ +#define REG_CAN0_MFID1 (0x400B422CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 1) */ +#define REG_CAN0_MSR1 (0x400B4230U) /**< \brief (CAN0) Mailbox Status Register (MB = 1) */ +#define REG_CAN0_MDL1 (0x400B4234U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 1) */ +#define REG_CAN0_MDH1 (0x400B4238U) /**< \brief (CAN0) Mailbox Data High Register (MB = 1) */ +#define REG_CAN0_MCR1 (0x400B423CU) /**< \brief (CAN0) Mailbox Control Register (MB = 1) */ +#define REG_CAN0_MMR2 (0x400B4240U) /**< \brief (CAN0) Mailbox Mode Register (MB = 2) */ +#define REG_CAN0_MAM2 (0x400B4244U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 2) */ +#define REG_CAN0_MID2 (0x400B4248U) /**< \brief (CAN0) Mailbox ID Register (MB = 2) */ +#define REG_CAN0_MFID2 (0x400B424CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 2) */ +#define REG_CAN0_MSR2 (0x400B4250U) /**< \brief (CAN0) Mailbox Status Register (MB = 2) */ +#define REG_CAN0_MDL2 (0x400B4254U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 2) */ +#define REG_CAN0_MDH2 (0x400B4258U) /**< \brief (CAN0) Mailbox Data High Register (MB = 2) */ +#define REG_CAN0_MCR2 (0x400B425CU) /**< \brief (CAN0) Mailbox Control Register (MB = 2) */ +#define REG_CAN0_MMR3 (0x400B4260U) /**< \brief (CAN0) Mailbox Mode Register (MB = 3) */ +#define REG_CAN0_MAM3 (0x400B4264U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 3) */ +#define REG_CAN0_MID3 (0x400B4268U) /**< \brief (CAN0) Mailbox ID Register (MB = 3) */ +#define REG_CAN0_MFID3 (0x400B426CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 3) */ +#define REG_CAN0_MSR3 (0x400B4270U) /**< \brief (CAN0) Mailbox Status Register (MB = 3) */ +#define REG_CAN0_MDL3 (0x400B4274U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 3) */ +#define REG_CAN0_MDH3 (0x400B4278U) /**< \brief (CAN0) Mailbox Data High Register (MB = 3) */ +#define REG_CAN0_MCR3 (0x400B427CU) /**< \brief (CAN0) Mailbox Control Register (MB = 3) */ +#define REG_CAN0_MMR4 (0x400B4280U) /**< \brief (CAN0) Mailbox Mode Register (MB = 4) */ +#define REG_CAN0_MAM4 (0x400B4284U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 4) */ +#define REG_CAN0_MID4 (0x400B4288U) /**< \brief (CAN0) Mailbox ID Register (MB = 4) */ +#define REG_CAN0_MFID4 (0x400B428CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 4) */ +#define REG_CAN0_MSR4 (0x400B4290U) /**< \brief (CAN0) Mailbox Status Register (MB = 4) */ +#define REG_CAN0_MDL4 (0x400B4294U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 4) */ +#define REG_CAN0_MDH4 (0x400B4298U) /**< \brief (CAN0) Mailbox Data High Register (MB = 4) */ +#define REG_CAN0_MCR4 (0x400B429CU) /**< \brief (CAN0) Mailbox Control Register (MB = 4) */ +#define REG_CAN0_MMR5 (0x400B42A0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 5) */ +#define REG_CAN0_MAM5 (0x400B42A4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 5) */ +#define REG_CAN0_MID5 (0x400B42A8U) /**< \brief (CAN0) Mailbox ID Register (MB = 5) */ +#define REG_CAN0_MFID5 (0x400B42ACU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 5) */ +#define REG_CAN0_MSR5 (0x400B42B0U) /**< \brief (CAN0) Mailbox Status Register (MB = 5) */ +#define REG_CAN0_MDL5 (0x400B42B4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 5) */ +#define REG_CAN0_MDH5 (0x400B42B8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 5) */ +#define REG_CAN0_MCR5 (0x400B42BCU) /**< \brief (CAN0) Mailbox Control Register (MB = 5) */ +#define REG_CAN0_MMR6 (0x400B42C0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 6) */ +#define REG_CAN0_MAM6 (0x400B42C4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 6) */ +#define REG_CAN0_MID6 (0x400B42C8U) /**< \brief (CAN0) Mailbox ID Register (MB = 6) */ +#define REG_CAN0_MFID6 (0x400B42CCU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 6) */ +#define REG_CAN0_MSR6 (0x400B42D0U) /**< \brief (CAN0) Mailbox Status Register (MB = 6) */ +#define REG_CAN0_MDL6 (0x400B42D4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 6) */ +#define REG_CAN0_MDH6 (0x400B42D8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 6) */ +#define REG_CAN0_MCR6 (0x400B42DCU) /**< \brief (CAN0) Mailbox Control Register (MB = 6) */ +#define REG_CAN0_MMR7 (0x400B42E0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 7) */ +#define REG_CAN0_MAM7 (0x400B42E4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 7) */ +#define REG_CAN0_MID7 (0x400B42E8U) /**< \brief (CAN0) Mailbox ID Register (MB = 7) */ +#define REG_CAN0_MFID7 (0x400B42ECU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 7) */ +#define REG_CAN0_MSR7 (0x400B42F0U) /**< \brief (CAN0) Mailbox Status Register (MB = 7) */ +#define REG_CAN0_MDL7 (0x400B42F4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 7) */ +#define REG_CAN0_MDH7 (0x400B42F8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 7) */ +#define REG_CAN0_MCR7 (0x400B42FCU) /**< \brief (CAN0) Mailbox Control Register (MB = 7) */ +#else +#define REG_CAN0_MR (*(RwReg*)0x400B4000U) /**< \brief (CAN0) Mode Register */ +#define REG_CAN0_IER (*(WoReg*)0x400B4004U) /**< \brief (CAN0) Interrupt Enable Register */ +#define REG_CAN0_IDR (*(WoReg*)0x400B4008U) /**< \brief (CAN0) Interrupt Disable Register */ +#define REG_CAN0_IMR (*(RoReg*)0x400B400CU) /**< \brief (CAN0) Interrupt Mask Register */ +#define REG_CAN0_SR (*(RoReg*)0x400B4010U) /**< \brief (CAN0) Status Register */ +#define REG_CAN0_BR (*(RwReg*)0x400B4014U) /**< \brief (CAN0) Baudrate Register */ +#define REG_CAN0_TIM (*(RoReg*)0x400B4018U) /**< \brief (CAN0) Timer Register */ +#define REG_CAN0_TIMESTP (*(RoReg*)0x400B401CU) /**< \brief (CAN0) Timestamp Register */ +#define REG_CAN0_ECR (*(RoReg*)0x400B4020U) /**< \brief (CAN0) Error Counter Register */ +#define REG_CAN0_TCR (*(WoReg*)0x400B4024U) /**< \brief (CAN0) Transfer Command Register */ +#define REG_CAN0_ACR (*(WoReg*)0x400B4028U) /**< \brief (CAN0) Abort Command Register */ +#define REG_CAN0_WPMR (*(RwReg*)0x400B40E4U) /**< \brief (CAN0) Write Protect Mode Register */ +#define REG_CAN0_WPSR (*(RoReg*)0x400B40E8U) /**< \brief (CAN0) Write Protect Status Register */ +#define REG_CAN0_MMR0 (*(RwReg*)0x400B4200U) /**< \brief (CAN0) Mailbox Mode Register (MB = 0) */ +#define REG_CAN0_MAM0 (*(RwReg*)0x400B4204U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 0) */ +#define REG_CAN0_MID0 (*(RwReg*)0x400B4208U) /**< \brief (CAN0) Mailbox ID Register (MB = 0) */ +#define REG_CAN0_MFID0 (*(RoReg*)0x400B420CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 0) */ +#define REG_CAN0_MSR0 (*(RoReg*)0x400B4210U) /**< \brief (CAN0) Mailbox Status Register (MB = 0) */ +#define REG_CAN0_MDL0 (*(RwReg*)0x400B4214U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 0) */ +#define REG_CAN0_MDH0 (*(RwReg*)0x400B4218U) /**< \brief (CAN0) Mailbox Data High Register (MB = 0) */ +#define REG_CAN0_MCR0 (*(WoReg*)0x400B421CU) /**< \brief (CAN0) Mailbox Control Register (MB = 0) */ +#define REG_CAN0_MMR1 (*(RwReg*)0x400B4220U) /**< \brief (CAN0) Mailbox Mode Register (MB = 1) */ +#define REG_CAN0_MAM1 (*(RwReg*)0x400B4224U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 1) */ +#define REG_CAN0_MID1 (*(RwReg*)0x400B4228U) /**< \brief (CAN0) Mailbox ID Register (MB = 1) */ +#define REG_CAN0_MFID1 (*(RoReg*)0x400B422CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 1) */ +#define REG_CAN0_MSR1 (*(RoReg*)0x400B4230U) /**< \brief (CAN0) Mailbox Status Register (MB = 1) */ +#define REG_CAN0_MDL1 (*(RwReg*)0x400B4234U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 1) */ +#define REG_CAN0_MDH1 (*(RwReg*)0x400B4238U) /**< \brief (CAN0) Mailbox Data High Register (MB = 1) */ +#define REG_CAN0_MCR1 (*(WoReg*)0x400B423CU) /**< \brief (CAN0) Mailbox Control Register (MB = 1) */ +#define REG_CAN0_MMR2 (*(RwReg*)0x400B4240U) /**< \brief (CAN0) Mailbox Mode Register (MB = 2) */ +#define REG_CAN0_MAM2 (*(RwReg*)0x400B4244U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 2) */ +#define REG_CAN0_MID2 (*(RwReg*)0x400B4248U) /**< \brief (CAN0) Mailbox ID Register (MB = 2) */ +#define REG_CAN0_MFID2 (*(RoReg*)0x400B424CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 2) */ +#define REG_CAN0_MSR2 (*(RoReg*)0x400B4250U) /**< \brief (CAN0) Mailbox Status Register (MB = 2) */ +#define REG_CAN0_MDL2 (*(RwReg*)0x400B4254U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 2) */ +#define REG_CAN0_MDH2 (*(RwReg*)0x400B4258U) /**< \brief (CAN0) Mailbox Data High Register (MB = 2) */ +#define REG_CAN0_MCR2 (*(WoReg*)0x400B425CU) /**< \brief (CAN0) Mailbox Control Register (MB = 2) */ +#define REG_CAN0_MMR3 (*(RwReg*)0x400B4260U) /**< \brief (CAN0) Mailbox Mode Register (MB = 3) */ +#define REG_CAN0_MAM3 (*(RwReg*)0x400B4264U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 3) */ +#define REG_CAN0_MID3 (*(RwReg*)0x400B4268U) /**< \brief (CAN0) Mailbox ID Register (MB = 3) */ +#define REG_CAN0_MFID3 (*(RoReg*)0x400B426CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 3) */ +#define REG_CAN0_MSR3 (*(RoReg*)0x400B4270U) /**< \brief (CAN0) Mailbox Status Register (MB = 3) */ +#define REG_CAN0_MDL3 (*(RwReg*)0x400B4274U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 3) */ +#define REG_CAN0_MDH3 (*(RwReg*)0x400B4278U) /**< \brief (CAN0) Mailbox Data High Register (MB = 3) */ +#define REG_CAN0_MCR3 (*(WoReg*)0x400B427CU) /**< \brief (CAN0) Mailbox Control Register (MB = 3) */ +#define REG_CAN0_MMR4 (*(RwReg*)0x400B4280U) /**< \brief (CAN0) Mailbox Mode Register (MB = 4) */ +#define REG_CAN0_MAM4 (*(RwReg*)0x400B4284U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 4) */ +#define REG_CAN0_MID4 (*(RwReg*)0x400B4288U) /**< \brief (CAN0) Mailbox ID Register (MB = 4) */ +#define REG_CAN0_MFID4 (*(RoReg*)0x400B428CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 4) */ +#define REG_CAN0_MSR4 (*(RoReg*)0x400B4290U) /**< \brief (CAN0) Mailbox Status Register (MB = 4) */ +#define REG_CAN0_MDL4 (*(RwReg*)0x400B4294U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 4) */ +#define REG_CAN0_MDH4 (*(RwReg*)0x400B4298U) /**< \brief (CAN0) Mailbox Data High Register (MB = 4) */ +#define REG_CAN0_MCR4 (*(WoReg*)0x400B429CU) /**< \brief (CAN0) Mailbox Control Register (MB = 4) */ +#define REG_CAN0_MMR5 (*(RwReg*)0x400B42A0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 5) */ +#define REG_CAN0_MAM5 (*(RwReg*)0x400B42A4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 5) */ +#define REG_CAN0_MID5 (*(RwReg*)0x400B42A8U) /**< \brief (CAN0) Mailbox ID Register (MB = 5) */ +#define REG_CAN0_MFID5 (*(RoReg*)0x400B42ACU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 5) */ +#define REG_CAN0_MSR5 (*(RoReg*)0x400B42B0U) /**< \brief (CAN0) Mailbox Status Register (MB = 5) */ +#define REG_CAN0_MDL5 (*(RwReg*)0x400B42B4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 5) */ +#define REG_CAN0_MDH5 (*(RwReg*)0x400B42B8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 5) */ +#define REG_CAN0_MCR5 (*(WoReg*)0x400B42BCU) /**< \brief (CAN0) Mailbox Control Register (MB = 5) */ +#define REG_CAN0_MMR6 (*(RwReg*)0x400B42C0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 6) */ +#define REG_CAN0_MAM6 (*(RwReg*)0x400B42C4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 6) */ +#define REG_CAN0_MID6 (*(RwReg*)0x400B42C8U) /**< \brief (CAN0) Mailbox ID Register (MB = 6) */ +#define REG_CAN0_MFID6 (*(RoReg*)0x400B42CCU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 6) */ +#define REG_CAN0_MSR6 (*(RoReg*)0x400B42D0U) /**< \brief (CAN0) Mailbox Status Register (MB = 6) */ +#define REG_CAN0_MDL6 (*(RwReg*)0x400B42D4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 6) */ +#define REG_CAN0_MDH6 (*(RwReg*)0x400B42D8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 6) */ +#define REG_CAN0_MCR6 (*(WoReg*)0x400B42DCU) /**< \brief (CAN0) Mailbox Control Register (MB = 6) */ +#define REG_CAN0_MMR7 (*(RwReg*)0x400B42E0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 7) */ +#define REG_CAN0_MAM7 (*(RwReg*)0x400B42E4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 7) */ +#define REG_CAN0_MID7 (*(RwReg*)0x400B42E8U) /**< \brief (CAN0) Mailbox ID Register (MB = 7) */ +#define REG_CAN0_MFID7 (*(RoReg*)0x400B42ECU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 7) */ +#define REG_CAN0_MSR7 (*(RoReg*)0x400B42F0U) /**< \brief (CAN0) Mailbox Status Register (MB = 7) */ +#define REG_CAN0_MDL7 (*(RwReg*)0x400B42F4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 7) */ +#define REG_CAN0_MDH7 (*(RwReg*)0x400B42F8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 7) */ +#define REG_CAN0_MCR7 (*(WoReg*)0x400B42FCU) /**< \brief (CAN0) Mailbox Control Register (MB = 7) */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_CAN0_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h new file mode 100644 index 0000000..bad70b4 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_can1.h @@ -0,0 +1,207 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_CAN1_INSTANCE_ +#define _SAM3XA_CAN1_INSTANCE_ + +/* ========== Register definition for CAN1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_CAN1_MR (0x400B8000U) /**< \brief (CAN1) Mode Register */ +#define REG_CAN1_IER (0x400B8004U) /**< \brief (CAN1) Interrupt Enable Register */ +#define REG_CAN1_IDR (0x400B8008U) /**< \brief (CAN1) Interrupt Disable Register */ +#define REG_CAN1_IMR (0x400B800CU) /**< \brief (CAN1) Interrupt Mask Register */ +#define REG_CAN1_SR (0x400B8010U) /**< \brief (CAN1) Status Register */ +#define REG_CAN1_BR (0x400B8014U) /**< \brief (CAN1) Baudrate Register */ +#define REG_CAN1_TIM (0x400B8018U) /**< \brief (CAN1) Timer Register */ +#define REG_CAN1_TIMESTP (0x400B801CU) /**< \brief (CAN1) Timestamp Register */ +#define REG_CAN1_ECR (0x400B8020U) /**< \brief (CAN1) Error Counter Register */ +#define REG_CAN1_TCR (0x400B8024U) /**< \brief (CAN1) Transfer Command Register */ +#define REG_CAN1_ACR (0x400B8028U) /**< \brief (CAN1) Abort Command Register */ +#define REG_CAN1_WPMR (0x400B80E4U) /**< \brief (CAN1) Write Protect Mode Register */ +#define REG_CAN1_WPSR (0x400B80E8U) /**< \brief (CAN1) Write Protect Status Register */ +#define REG_CAN1_MMR0 (0x400B8200U) /**< \brief (CAN1) Mailbox Mode Register (MB = 0) */ +#define REG_CAN1_MAM0 (0x400B8204U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 0) */ +#define REG_CAN1_MID0 (0x400B8208U) /**< \brief (CAN1) Mailbox ID Register (MB = 0) */ +#define REG_CAN1_MFID0 (0x400B820CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 0) */ +#define REG_CAN1_MSR0 (0x400B8210U) /**< \brief (CAN1) Mailbox Status Register (MB = 0) */ +#define REG_CAN1_MDL0 (0x400B8214U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 0) */ +#define REG_CAN1_MDH0 (0x400B8218U) /**< \brief (CAN1) Mailbox Data High Register (MB = 0) */ +#define REG_CAN1_MCR0 (0x400B821CU) /**< \brief (CAN1) Mailbox Control Register (MB = 0) */ +#define REG_CAN1_MMR1 (0x400B8220U) /**< \brief (CAN1) Mailbox Mode Register (MB = 1) */ +#define REG_CAN1_MAM1 (0x400B8224U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 1) */ +#define REG_CAN1_MID1 (0x400B8228U) /**< \brief (CAN1) Mailbox ID Register (MB = 1) */ +#define REG_CAN1_MFID1 (0x400B822CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 1) */ +#define REG_CAN1_MSR1 (0x400B8230U) /**< \brief (CAN1) Mailbox Status Register (MB = 1) */ +#define REG_CAN1_MDL1 (0x400B8234U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 1) */ +#define REG_CAN1_MDH1 (0x400B8238U) /**< \brief (CAN1) Mailbox Data High Register (MB = 1) */ +#define REG_CAN1_MCR1 (0x400B823CU) /**< \brief (CAN1) Mailbox Control Register (MB = 1) */ +#define REG_CAN1_MMR2 (0x400B8240U) /**< \brief (CAN1) Mailbox Mode Register (MB = 2) */ +#define REG_CAN1_MAM2 (0x400B8244U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 2) */ +#define REG_CAN1_MID2 (0x400B8248U) /**< \brief (CAN1) Mailbox ID Register (MB = 2) */ +#define REG_CAN1_MFID2 (0x400B824CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 2) */ +#define REG_CAN1_MSR2 (0x400B8250U) /**< \brief (CAN1) Mailbox Status Register (MB = 2) */ +#define REG_CAN1_MDL2 (0x400B8254U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 2) */ +#define REG_CAN1_MDH2 (0x400B8258U) /**< \brief (CAN1) Mailbox Data High Register (MB = 2) */ +#define REG_CAN1_MCR2 (0x400B825CU) /**< \brief (CAN1) Mailbox Control Register (MB = 2) */ +#define REG_CAN1_MMR3 (0x400B8260U) /**< \brief (CAN1) Mailbox Mode Register (MB = 3) */ +#define REG_CAN1_MAM3 (0x400B8264U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 3) */ +#define REG_CAN1_MID3 (0x400B8268U) /**< \brief (CAN1) Mailbox ID Register (MB = 3) */ +#define REG_CAN1_MFID3 (0x400B826CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 3) */ +#define REG_CAN1_MSR3 (0x400B8270U) /**< \brief (CAN1) Mailbox Status Register (MB = 3) */ +#define REG_CAN1_MDL3 (0x400B8274U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 3) */ +#define REG_CAN1_MDH3 (0x400B8278U) /**< \brief (CAN1) Mailbox Data High Register (MB = 3) */ +#define REG_CAN1_MCR3 (0x400B827CU) /**< \brief (CAN1) Mailbox Control Register (MB = 3) */ +#define REG_CAN1_MMR4 (0x400B8280U) /**< \brief (CAN1) Mailbox Mode Register (MB = 4) */ +#define REG_CAN1_MAM4 (0x400B8284U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 4) */ +#define REG_CAN1_MID4 (0x400B8288U) /**< \brief (CAN1) Mailbox ID Register (MB = 4) */ +#define REG_CAN1_MFID4 (0x400B828CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 4) */ +#define REG_CAN1_MSR4 (0x400B8290U) /**< \brief (CAN1) Mailbox Status Register (MB = 4) */ +#define REG_CAN1_MDL4 (0x400B8294U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 4) */ +#define REG_CAN1_MDH4 (0x400B8298U) /**< \brief (CAN1) Mailbox Data High Register (MB = 4) */ +#define REG_CAN1_MCR4 (0x400B829CU) /**< \brief (CAN1) Mailbox Control Register (MB = 4) */ +#define REG_CAN1_MMR5 (0x400B82A0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 5) */ +#define REG_CAN1_MAM5 (0x400B82A4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 5) */ +#define REG_CAN1_MID5 (0x400B82A8U) /**< \brief (CAN1) Mailbox ID Register (MB = 5) */ +#define REG_CAN1_MFID5 (0x400B82ACU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 5) */ +#define REG_CAN1_MSR5 (0x400B82B0U) /**< \brief (CAN1) Mailbox Status Register (MB = 5) */ +#define REG_CAN1_MDL5 (0x400B82B4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 5) */ +#define REG_CAN1_MDH5 (0x400B82B8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 5) */ +#define REG_CAN1_MCR5 (0x400B82BCU) /**< \brief (CAN1) Mailbox Control Register (MB = 5) */ +#define REG_CAN1_MMR6 (0x400B82C0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 6) */ +#define REG_CAN1_MAM6 (0x400B82C4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 6) */ +#define REG_CAN1_MID6 (0x400B82C8U) /**< \brief (CAN1) Mailbox ID Register (MB = 6) */ +#define REG_CAN1_MFID6 (0x400B82CCU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 6) */ +#define REG_CAN1_MSR6 (0x400B82D0U) /**< \brief (CAN1) Mailbox Status Register (MB = 6) */ +#define REG_CAN1_MDL6 (0x400B82D4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 6) */ +#define REG_CAN1_MDH6 (0x400B82D8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 6) */ +#define REG_CAN1_MCR6 (0x400B82DCU) /**< \brief (CAN1) Mailbox Control Register (MB = 6) */ +#define REG_CAN1_MMR7 (0x400B82E0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 7) */ +#define REG_CAN1_MAM7 (0x400B82E4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 7) */ +#define REG_CAN1_MID7 (0x400B82E8U) /**< \brief (CAN1) Mailbox ID Register (MB = 7) */ +#define REG_CAN1_MFID7 (0x400B82ECU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 7) */ +#define REG_CAN1_MSR7 (0x400B82F0U) /**< \brief (CAN1) Mailbox Status Register (MB = 7) */ +#define REG_CAN1_MDL7 (0x400B82F4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 7) */ +#define REG_CAN1_MDH7 (0x400B82F8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 7) */ +#define REG_CAN1_MCR7 (0x400B82FCU) /**< \brief (CAN1) Mailbox Control Register (MB = 7) */ +#else +#define REG_CAN1_MR (*(RwReg*)0x400B8000U) /**< \brief (CAN1) Mode Register */ +#define REG_CAN1_IER (*(WoReg*)0x400B8004U) /**< \brief (CAN1) Interrupt Enable Register */ +#define REG_CAN1_IDR (*(WoReg*)0x400B8008U) /**< \brief (CAN1) Interrupt Disable Register */ +#define REG_CAN1_IMR (*(RoReg*)0x400B800CU) /**< \brief (CAN1) Interrupt Mask Register */ +#define REG_CAN1_SR (*(RoReg*)0x400B8010U) /**< \brief (CAN1) Status Register */ +#define REG_CAN1_BR (*(RwReg*)0x400B8014U) /**< \brief (CAN1) Baudrate Register */ +#define REG_CAN1_TIM (*(RoReg*)0x400B8018U) /**< \brief (CAN1) Timer Register */ +#define REG_CAN1_TIMESTP (*(RoReg*)0x400B801CU) /**< \brief (CAN1) Timestamp Register */ +#define REG_CAN1_ECR (*(RoReg*)0x400B8020U) /**< \brief (CAN1) Error Counter Register */ +#define REG_CAN1_TCR (*(WoReg*)0x400B8024U) /**< \brief (CAN1) Transfer Command Register */ +#define REG_CAN1_ACR (*(WoReg*)0x400B8028U) /**< \brief (CAN1) Abort Command Register */ +#define REG_CAN1_WPMR (*(RwReg*)0x400B80E4U) /**< \brief (CAN1) Write Protect Mode Register */ +#define REG_CAN1_WPSR (*(RoReg*)0x400B80E8U) /**< \brief (CAN1) Write Protect Status Register */ +#define REG_CAN1_MMR0 (*(RwReg*)0x400B8200U) /**< \brief (CAN1) Mailbox Mode Register (MB = 0) */ +#define REG_CAN1_MAM0 (*(RwReg*)0x400B8204U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 0) */ +#define REG_CAN1_MID0 (*(RwReg*)0x400B8208U) /**< \brief (CAN1) Mailbox ID Register (MB = 0) */ +#define REG_CAN1_MFID0 (*(RoReg*)0x400B820CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 0) */ +#define REG_CAN1_MSR0 (*(RoReg*)0x400B8210U) /**< \brief (CAN1) Mailbox Status Register (MB = 0) */ +#define REG_CAN1_MDL0 (*(RwReg*)0x400B8214U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 0) */ +#define REG_CAN1_MDH0 (*(RwReg*)0x400B8218U) /**< \brief (CAN1) Mailbox Data High Register (MB = 0) */ +#define REG_CAN1_MCR0 (*(WoReg*)0x400B821CU) /**< \brief (CAN1) Mailbox Control Register (MB = 0) */ +#define REG_CAN1_MMR1 (*(RwReg*)0x400B8220U) /**< \brief (CAN1) Mailbox Mode Register (MB = 1) */ +#define REG_CAN1_MAM1 (*(RwReg*)0x400B8224U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 1) */ +#define REG_CAN1_MID1 (*(RwReg*)0x400B8228U) /**< \brief (CAN1) Mailbox ID Register (MB = 1) */ +#define REG_CAN1_MFID1 (*(RoReg*)0x400B822CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 1) */ +#define REG_CAN1_MSR1 (*(RoReg*)0x400B8230U) /**< \brief (CAN1) Mailbox Status Register (MB = 1) */ +#define REG_CAN1_MDL1 (*(RwReg*)0x400B8234U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 1) */ +#define REG_CAN1_MDH1 (*(RwReg*)0x400B8238U) /**< \brief (CAN1) Mailbox Data High Register (MB = 1) */ +#define REG_CAN1_MCR1 (*(WoReg*)0x400B823CU) /**< \brief (CAN1) Mailbox Control Register (MB = 1) */ +#define REG_CAN1_MMR2 (*(RwReg*)0x400B8240U) /**< \brief (CAN1) Mailbox Mode Register (MB = 2) */ +#define REG_CAN1_MAM2 (*(RwReg*)0x400B8244U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 2) */ +#define REG_CAN1_MID2 (*(RwReg*)0x400B8248U) /**< \brief (CAN1) Mailbox ID Register (MB = 2) */ +#define REG_CAN1_MFID2 (*(RoReg*)0x400B824CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 2) */ +#define REG_CAN1_MSR2 (*(RoReg*)0x400B8250U) /**< \brief (CAN1) Mailbox Status Register (MB = 2) */ +#define REG_CAN1_MDL2 (*(RwReg*)0x400B8254U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 2) */ +#define REG_CAN1_MDH2 (*(RwReg*)0x400B8258U) /**< \brief (CAN1) Mailbox Data High Register (MB = 2) */ +#define REG_CAN1_MCR2 (*(WoReg*)0x400B825CU) /**< \brief (CAN1) Mailbox Control Register (MB = 2) */ +#define REG_CAN1_MMR3 (*(RwReg*)0x400B8260U) /**< \brief (CAN1) Mailbox Mode Register (MB = 3) */ +#define REG_CAN1_MAM3 (*(RwReg*)0x400B8264U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 3) */ +#define REG_CAN1_MID3 (*(RwReg*)0x400B8268U) /**< \brief (CAN1) Mailbox ID Register (MB = 3) */ +#define REG_CAN1_MFID3 (*(RoReg*)0x400B826CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 3) */ +#define REG_CAN1_MSR3 (*(RoReg*)0x400B8270U) /**< \brief (CAN1) Mailbox Status Register (MB = 3) */ +#define REG_CAN1_MDL3 (*(RwReg*)0x400B8274U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 3) */ +#define REG_CAN1_MDH3 (*(RwReg*)0x400B8278U) /**< \brief (CAN1) Mailbox Data High Register (MB = 3) */ +#define REG_CAN1_MCR3 (*(WoReg*)0x400B827CU) /**< \brief (CAN1) Mailbox Control Register (MB = 3) */ +#define REG_CAN1_MMR4 (*(RwReg*)0x400B8280U) /**< \brief (CAN1) Mailbox Mode Register (MB = 4) */ +#define REG_CAN1_MAM4 (*(RwReg*)0x400B8284U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 4) */ +#define REG_CAN1_MID4 (*(RwReg*)0x400B8288U) /**< \brief (CAN1) Mailbox ID Register (MB = 4) */ +#define REG_CAN1_MFID4 (*(RoReg*)0x400B828CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 4) */ +#define REG_CAN1_MSR4 (*(RoReg*)0x400B8290U) /**< \brief (CAN1) Mailbox Status Register (MB = 4) */ +#define REG_CAN1_MDL4 (*(RwReg*)0x400B8294U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 4) */ +#define REG_CAN1_MDH4 (*(RwReg*)0x400B8298U) /**< \brief (CAN1) Mailbox Data High Register (MB = 4) */ +#define REG_CAN1_MCR4 (*(WoReg*)0x400B829CU) /**< \brief (CAN1) Mailbox Control Register (MB = 4) */ +#define REG_CAN1_MMR5 (*(RwReg*)0x400B82A0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 5) */ +#define REG_CAN1_MAM5 (*(RwReg*)0x400B82A4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 5) */ +#define REG_CAN1_MID5 (*(RwReg*)0x400B82A8U) /**< \brief (CAN1) Mailbox ID Register (MB = 5) */ +#define REG_CAN1_MFID5 (*(RoReg*)0x400B82ACU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 5) */ +#define REG_CAN1_MSR5 (*(RoReg*)0x400B82B0U) /**< \brief (CAN1) Mailbox Status Register (MB = 5) */ +#define REG_CAN1_MDL5 (*(RwReg*)0x400B82B4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 5) */ +#define REG_CAN1_MDH5 (*(RwReg*)0x400B82B8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 5) */ +#define REG_CAN1_MCR5 (*(WoReg*)0x400B82BCU) /**< \brief (CAN1) Mailbox Control Register (MB = 5) */ +#define REG_CAN1_MMR6 (*(RwReg*)0x400B82C0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 6) */ +#define REG_CAN1_MAM6 (*(RwReg*)0x400B82C4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 6) */ +#define REG_CAN1_MID6 (*(RwReg*)0x400B82C8U) /**< \brief (CAN1) Mailbox ID Register (MB = 6) */ +#define REG_CAN1_MFID6 (*(RoReg*)0x400B82CCU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 6) */ +#define REG_CAN1_MSR6 (*(RoReg*)0x400B82D0U) /**< \brief (CAN1) Mailbox Status Register (MB = 6) */ +#define REG_CAN1_MDL6 (*(RwReg*)0x400B82D4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 6) */ +#define REG_CAN1_MDH6 (*(RwReg*)0x400B82D8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 6) */ +#define REG_CAN1_MCR6 (*(WoReg*)0x400B82DCU) /**< \brief (CAN1) Mailbox Control Register (MB = 6) */ +#define REG_CAN1_MMR7 (*(RwReg*)0x400B82E0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 7) */ +#define REG_CAN1_MAM7 (*(RwReg*)0x400B82E4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 7) */ +#define REG_CAN1_MID7 (*(RwReg*)0x400B82E8U) /**< \brief (CAN1) Mailbox ID Register (MB = 7) */ +#define REG_CAN1_MFID7 (*(RoReg*)0x400B82ECU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 7) */ +#define REG_CAN1_MSR7 (*(RoReg*)0x400B82F0U) /**< \brief (CAN1) Mailbox Status Register (MB = 7) */ +#define REG_CAN1_MDL7 (*(RwReg*)0x400B82F4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 7) */ +#define REG_CAN1_MDH7 (*(RwReg*)0x400B82F8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 7) */ +#define REG_CAN1_MCR7 (*(WoReg*)0x400B82FCU) /**< \brief (CAN1) Mailbox Control Register (MB = 7) */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_CAN1_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h new file mode 100644 index 0000000..380e710 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_chipid.h @@ -0,0 +1,57 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_CHIPID_INSTANCE_ +#define _SAM3XA_CHIPID_INSTANCE_ + +/* ========== Register definition for CHIPID peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_CHIPID_CIDR (0x400E0940U) /**< \brief (CHIPID) Chip ID Register */ +#define REG_CHIPID_EXID (0x400E0944U) /**< \brief (CHIPID) Chip ID Extension Register */ +#else +#define REG_CHIPID_CIDR (*(RoReg*)0x400E0940U) /**< \brief (CHIPID) Chip ID Register */ +#define REG_CHIPID_EXID (*(RoReg*)0x400E0944U) /**< \brief (CHIPID) Chip ID Extension Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_CHIPID_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h new file mode 100644 index 0000000..dd00251 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dacc.h @@ -0,0 +1,91 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_DACC_INSTANCE_ +#define _SAM3XA_DACC_INSTANCE_ + +/* ========== Register definition for DACC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_DACC_CR (0x400C8000U) /**< \brief (DACC) Control Register */ +#define REG_DACC_MR (0x400C8004U) /**< \brief (DACC) Mode Register */ +#define REG_DACC_CHER (0x400C8010U) /**< \brief (DACC) Channel Enable Register */ +#define REG_DACC_CHDR (0x400C8014U) /**< \brief (DACC) Channel Disable Register */ +#define REG_DACC_CHSR (0x400C8018U) /**< \brief (DACC) Channel Status Register */ +#define REG_DACC_CDR (0x400C8020U) /**< \brief (DACC) Conversion Data Register */ +#define REG_DACC_IER (0x400C8024U) /**< \brief (DACC) Interrupt Enable Register */ +#define REG_DACC_IDR (0x400C8028U) /**< \brief (DACC) Interrupt Disable Register */ +#define REG_DACC_IMR (0x400C802CU) /**< \brief (DACC) Interrupt Mask Register */ +#define REG_DACC_ISR (0x400C8030U) /**< \brief (DACC) Interrupt Status Register */ +#define REG_DACC_ACR (0x400C8094U) /**< \brief (DACC) Analog Current Register */ +#define REG_DACC_WPMR (0x400C80E4U) /**< \brief (DACC) Write Protect Mode register */ +#define REG_DACC_WPSR (0x400C80E8U) /**< \brief (DACC) Write Protect Status register */ +#define REG_DACC_TPR (0x400C8108U) /**< \brief (DACC) Transmit Pointer Register */ +#define REG_DACC_TCR (0x400C810CU) /**< \brief (DACC) Transmit Counter Register */ +#define REG_DACC_TNPR (0x400C8118U) /**< \brief (DACC) Transmit Next Pointer Register */ +#define REG_DACC_TNCR (0x400C811CU) /**< \brief (DACC) Transmit Next Counter Register */ +#define REG_DACC_PTCR (0x400C8120U) /**< \brief (DACC) Transfer Control Register */ +#define REG_DACC_PTSR (0x400C8124U) /**< \brief (DACC) Transfer Status Register */ +#else +#define REG_DACC_CR (*(WoReg*)0x400C8000U) /**< \brief (DACC) Control Register */ +#define REG_DACC_MR (*(RwReg*)0x400C8004U) /**< \brief (DACC) Mode Register */ +#define REG_DACC_CHER (*(WoReg*)0x400C8010U) /**< \brief (DACC) Channel Enable Register */ +#define REG_DACC_CHDR (*(WoReg*)0x400C8014U) /**< \brief (DACC) Channel Disable Register */ +#define REG_DACC_CHSR (*(RoReg*)0x400C8018U) /**< \brief (DACC) Channel Status Register */ +#define REG_DACC_CDR (*(WoReg*)0x400C8020U) /**< \brief (DACC) Conversion Data Register */ +#define REG_DACC_IER (*(WoReg*)0x400C8024U) /**< \brief (DACC) Interrupt Enable Register */ +#define REG_DACC_IDR (*(WoReg*)0x400C8028U) /**< \brief (DACC) Interrupt Disable Register */ +#define REG_DACC_IMR (*(RoReg*)0x400C802CU) /**< \brief (DACC) Interrupt Mask Register */ +#define REG_DACC_ISR (*(RoReg*)0x400C8030U) /**< \brief (DACC) Interrupt Status Register */ +#define REG_DACC_ACR (*(RwReg*)0x400C8094U) /**< \brief (DACC) Analog Current Register */ +#define REG_DACC_WPMR (*(RwReg*)0x400C80E4U) /**< \brief (DACC) Write Protect Mode register */ +#define REG_DACC_WPSR (*(RoReg*)0x400C80E8U) /**< \brief (DACC) Write Protect Status register */ +#define REG_DACC_TPR (*(RwReg*)0x400C8108U) /**< \brief (DACC) Transmit Pointer Register */ +#define REG_DACC_TCR (*(RwReg*)0x400C810CU) /**< \brief (DACC) Transmit Counter Register */ +#define REG_DACC_TNPR (*(RwReg*)0x400C8118U) /**< \brief (DACC) Transmit Next Pointer Register */ +#define REG_DACC_TNCR (*(RwReg*)0x400C811CU) /**< \brief (DACC) Transmit Next Counter Register */ +#define REG_DACC_PTCR (*(WoReg*)0x400C8120U) /**< \brief (DACC) Transfer Control Register */ +#define REG_DACC_PTSR (*(RoReg*)0x400C8124U) /**< \brief (DACC) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_DACC_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h new file mode 100644 index 0000000..45389d5 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_dmac.h @@ -0,0 +1,153 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_DMAC_INSTANCE_ +#define _SAM3XA_DMAC_INSTANCE_ + +/* ========== Register definition for DMAC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_DMAC_GCFG (0x400C4000U) /**< \brief (DMAC) DMAC Global Configuration Register */ +#define REG_DMAC_EN (0x400C4004U) /**< \brief (DMAC) DMAC Enable Register */ +#define REG_DMAC_SREQ (0x400C4008U) /**< \brief (DMAC) DMAC Software Single Request Register */ +#define REG_DMAC_CREQ (0x400C400CU) /**< \brief (DMAC) DMAC Software Chunk Transfer Request Register */ +#define REG_DMAC_LAST (0x400C4010U) /**< \brief (DMAC) DMAC Software Last Transfer Flag Register */ +#define REG_DMAC_EBCIER (0x400C4018U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */ +#define REG_DMAC_EBCIDR (0x400C401CU) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */ +#define REG_DMAC_EBCIMR (0x400C4020U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */ +#define REG_DMAC_EBCISR (0x400C4024U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */ +#define REG_DMAC_CHER (0x400C4028U) /**< \brief (DMAC) DMAC Channel Handler Enable Register */ +#define REG_DMAC_CHDR (0x400C402CU) /**< \brief (DMAC) DMAC Channel Handler Disable Register */ +#define REG_DMAC_CHSR (0x400C4030U) /**< \brief (DMAC) DMAC Channel Handler Status Register */ +#define REG_DMAC_SADDR0 (0x400C403CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 0) */ +#define REG_DMAC_DADDR0 (0x400C4040U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 0) */ +#define REG_DMAC_DSCR0 (0x400C4044U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 0) */ +#define REG_DMAC_CTRLA0 (0x400C4048U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 0) */ +#define REG_DMAC_CTRLB0 (0x400C404CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 0) */ +#define REG_DMAC_CFG0 (0x400C4050U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 0) */ +#define REG_DMAC_SADDR1 (0x400C4064U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 1) */ +#define REG_DMAC_DADDR1 (0x400C4068U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 1) */ +#define REG_DMAC_DSCR1 (0x400C406CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 1) */ +#define REG_DMAC_CTRLA1 (0x400C4070U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 1) */ +#define REG_DMAC_CTRLB1 (0x400C4074U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 1) */ +#define REG_DMAC_CFG1 (0x400C4078U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 1) */ +#define REG_DMAC_SADDR2 (0x400C408CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 2) */ +#define REG_DMAC_DADDR2 (0x400C4090U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 2) */ +#define REG_DMAC_DSCR2 (0x400C4094U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 2) */ +#define REG_DMAC_CTRLA2 (0x400C4098U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 2) */ +#define REG_DMAC_CTRLB2 (0x400C409CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 2) */ +#define REG_DMAC_CFG2 (0x400C40A0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 2) */ +#define REG_DMAC_SADDR3 (0x400C40B4U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 3) */ +#define REG_DMAC_DADDR3 (0x400C40B8U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 3) */ +#define REG_DMAC_DSCR3 (0x400C40BCU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 3) */ +#define REG_DMAC_CTRLA3 (0x400C40C0U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 3) */ +#define REG_DMAC_CTRLB3 (0x400C40C4U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 3) */ +#define REG_DMAC_CFG3 (0x400C40C8U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 3) */ +#define REG_DMAC_SADDR4 (0x400C40DCU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 4) */ +#define REG_DMAC_DADDR4 (0x400C40E0U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 4) */ +#define REG_DMAC_DSCR4 (0x400C40E4U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 4) */ +#define REG_DMAC_CTRLA4 (0x400C40E8U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 4) */ +#define REG_DMAC_CTRLB4 (0x400C40ECU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 4) */ +#define REG_DMAC_CFG4 (0x400C40F0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 4) */ +#define REG_DMAC_SADDR5 (0x400C4104U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 5) */ +#define REG_DMAC_DADDR5 (0x400C4108U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 5) */ +#define REG_DMAC_DSCR5 (0x400C410CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 5) */ +#define REG_DMAC_CTRLA5 (0x400C4110U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 5) */ +#define REG_DMAC_CTRLB5 (0x400C4114U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 5) */ +#define REG_DMAC_CFG5 (0x400C4118U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 5) */ +#define REG_DMAC_WPMR (0x400C41E4U) /**< \brief (DMAC) DMAC Write Protect Mode Register */ +#define REG_DMAC_WPSR (0x400C41E8U) /**< \brief (DMAC) DMAC Write Protect Status Register */ +#else +#define REG_DMAC_GCFG (*(RwReg*)0x400C4000U) /**< \brief (DMAC) DMAC Global Configuration Register */ +#define REG_DMAC_EN (*(RwReg*)0x400C4004U) /**< \brief (DMAC) DMAC Enable Register */ +#define REG_DMAC_SREQ (*(RwReg*)0x400C4008U) /**< \brief (DMAC) DMAC Software Single Request Register */ +#define REG_DMAC_CREQ (*(RwReg*)0x400C400CU) /**< \brief (DMAC) DMAC Software Chunk Transfer Request Register */ +#define REG_DMAC_LAST (*(RwReg*)0x400C4010U) /**< \brief (DMAC) DMAC Software Last Transfer Flag Register */ +#define REG_DMAC_EBCIER (*(WoReg*)0x400C4018U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */ +#define REG_DMAC_EBCIDR (*(WoReg*)0x400C401CU) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */ +#define REG_DMAC_EBCIMR (*(RoReg*)0x400C4020U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */ +#define REG_DMAC_EBCISR (*(RoReg*)0x400C4024U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */ +#define REG_DMAC_CHER (*(WoReg*)0x400C4028U) /**< \brief (DMAC) DMAC Channel Handler Enable Register */ +#define REG_DMAC_CHDR (*(WoReg*)0x400C402CU) /**< \brief (DMAC) DMAC Channel Handler Disable Register */ +#define REG_DMAC_CHSR (*(RoReg*)0x400C4030U) /**< \brief (DMAC) DMAC Channel Handler Status Register */ +#define REG_DMAC_SADDR0 (*(RwReg*)0x400C403CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 0) */ +#define REG_DMAC_DADDR0 (*(RwReg*)0x400C4040U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 0) */ +#define REG_DMAC_DSCR0 (*(RwReg*)0x400C4044U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 0) */ +#define REG_DMAC_CTRLA0 (*(RwReg*)0x400C4048U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 0) */ +#define REG_DMAC_CTRLB0 (*(RwReg*)0x400C404CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 0) */ +#define REG_DMAC_CFG0 (*(RwReg*)0x400C4050U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 0) */ +#define REG_DMAC_SADDR1 (*(RwReg*)0x400C4064U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 1) */ +#define REG_DMAC_DADDR1 (*(RwReg*)0x400C4068U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 1) */ +#define REG_DMAC_DSCR1 (*(RwReg*)0x400C406CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 1) */ +#define REG_DMAC_CTRLA1 (*(RwReg*)0x400C4070U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 1) */ +#define REG_DMAC_CTRLB1 (*(RwReg*)0x400C4074U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 1) */ +#define REG_DMAC_CFG1 (*(RwReg*)0x400C4078U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 1) */ +#define REG_DMAC_SADDR2 (*(RwReg*)0x400C408CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 2) */ +#define REG_DMAC_DADDR2 (*(RwReg*)0x400C4090U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 2) */ +#define REG_DMAC_DSCR2 (*(RwReg*)0x400C4094U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 2) */ +#define REG_DMAC_CTRLA2 (*(RwReg*)0x400C4098U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 2) */ +#define REG_DMAC_CTRLB2 (*(RwReg*)0x400C409CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 2) */ +#define REG_DMAC_CFG2 (*(RwReg*)0x400C40A0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 2) */ +#define REG_DMAC_SADDR3 (*(RwReg*)0x400C40B4U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 3) */ +#define REG_DMAC_DADDR3 (*(RwReg*)0x400C40B8U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 3) */ +#define REG_DMAC_DSCR3 (*(RwReg*)0x400C40BCU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 3) */ +#define REG_DMAC_CTRLA3 (*(RwReg*)0x400C40C0U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 3) */ +#define REG_DMAC_CTRLB3 (*(RwReg*)0x400C40C4U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 3) */ +#define REG_DMAC_CFG3 (*(RwReg*)0x400C40C8U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 3) */ +#define REG_DMAC_SADDR4 (*(RwReg*)0x400C40DCU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 4) */ +#define REG_DMAC_DADDR4 (*(RwReg*)0x400C40E0U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 4) */ +#define REG_DMAC_DSCR4 (*(RwReg*)0x400C40E4U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 4) */ +#define REG_DMAC_CTRLA4 (*(RwReg*)0x400C40E8U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 4) */ +#define REG_DMAC_CTRLB4 (*(RwReg*)0x400C40ECU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 4) */ +#define REG_DMAC_CFG4 (*(RwReg*)0x400C40F0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 4) */ +#define REG_DMAC_SADDR5 (*(RwReg*)0x400C4104U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 5) */ +#define REG_DMAC_DADDR5 (*(RwReg*)0x400C4108U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 5) */ +#define REG_DMAC_DSCR5 (*(RwReg*)0x400C410CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 5) */ +#define REG_DMAC_CTRLA5 (*(RwReg*)0x400C4110U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 5) */ +#define REG_DMAC_CTRLB5 (*(RwReg*)0x400C4114U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 5) */ +#define REG_DMAC_CFG5 (*(RwReg*)0x400C4118U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 5) */ +#define REG_DMAC_WPMR (*(RwReg*)0x400C41E4U) /**< \brief (DMAC) DMAC Write Protect Mode Register */ +#define REG_DMAC_WPSR (*(RoReg*)0x400C41E8U) /**< \brief (DMAC) DMAC Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_DMAC_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h new file mode 100644 index 0000000..7741bb5 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc0.h @@ -0,0 +1,61 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_EFC0_INSTANCE_ +#define _SAM3XA_EFC0_INSTANCE_ + +/* ========== Register definition for EFC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_EFC0_FMR (0x400E0A00U) /**< \brief (EFC0) EEFC Flash Mode Register */ +#define REG_EFC0_FCR (0x400E0A04U) /**< \brief (EFC0) EEFC Flash Command Register */ +#define REG_EFC0_FSR (0x400E0A08U) /**< \brief (EFC0) EEFC Flash Status Register */ +#define REG_EFC0_FRR (0x400E0A0CU) /**< \brief (EFC0) EEFC Flash Result Register */ +#else +#define REG_EFC0_FMR (*(RwReg*)0x400E0A00U) /**< \brief (EFC0) EEFC Flash Mode Register */ +#define REG_EFC0_FCR (*(WoReg*)0x400E0A04U) /**< \brief (EFC0) EEFC Flash Command Register */ +#define REG_EFC0_FSR (*(RoReg*)0x400E0A08U) /**< \brief (EFC0) EEFC Flash Status Register */ +#define REG_EFC0_FRR (*(RoReg*)0x400E0A0CU) /**< \brief (EFC0) EEFC Flash Result Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_EFC0_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h new file mode 100644 index 0000000..03b2447 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_efc1.h @@ -0,0 +1,61 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_EFC1_INSTANCE_ +#define _SAM3XA_EFC1_INSTANCE_ + +/* ========== Register definition for EFC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_EFC1_FMR (0x400E0C00U) /**< \brief (EFC1) EEFC Flash Mode Register */ +#define REG_EFC1_FCR (0x400E0C04U) /**< \brief (EFC1) EEFC Flash Command Register */ +#define REG_EFC1_FSR (0x400E0C08U) /**< \brief (EFC1) EEFC Flash Status Register */ +#define REG_EFC1_FRR (0x400E0C0CU) /**< \brief (EFC1) EEFC Flash Result Register */ +#else +#define REG_EFC1_FMR (*(RwReg*)0x400E0C00U) /**< \brief (EFC1) EEFC Flash Mode Register */ +#define REG_EFC1_FCR (*(WoReg*)0x400E0C04U) /**< \brief (EFC1) EEFC Flash Command Register */ +#define REG_EFC1_FSR (*(RoReg*)0x400E0C08U) /**< \brief (EFC1) EEFC Flash Status Register */ +#define REG_EFC1_FRR (*(RoReg*)0x400E0C0CU) /**< \brief (EFC1) EEFC Flash Result Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_EFC1_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h new file mode 100644 index 0000000..55695e7 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_emac.h @@ -0,0 +1,143 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_EMAC_INSTANCE_ +#define _SAM3XA_EMAC_INSTANCE_ + +/* ========== Register definition for EMAC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_EMAC_NCR (0x400B0000U) /**< \brief (EMAC) Network Control Register */ +#define REG_EMAC_NCFGR (0x400B0004U) /**< \brief (EMAC) Network Configuration Register */ +#define REG_EMAC_NSR (0x400B0008U) /**< \brief (EMAC) Network Status Register */ +#define REG_EMAC_TSR (0x400B0014U) /**< \brief (EMAC) Transmit Status Register */ +#define REG_EMAC_RBQP (0x400B0018U) /**< \brief (EMAC) Receive Buffer Queue Pointer Register */ +#define REG_EMAC_TBQP (0x400B001CU) /**< \brief (EMAC) Transmit Buffer Queue Pointer Register */ +#define REG_EMAC_RSR (0x400B0020U) /**< \brief (EMAC) Receive Status Register */ +#define REG_EMAC_ISR (0x400B0024U) /**< \brief (EMAC) Interrupt Status Register */ +#define REG_EMAC_IER (0x400B0028U) /**< \brief (EMAC) Interrupt Enable Register */ +#define REG_EMAC_IDR (0x400B002CU) /**< \brief (EMAC) Interrupt Disable Register */ +#define REG_EMAC_IMR (0x400B0030U) /**< \brief (EMAC) Interrupt Mask Register */ +#define REG_EMAC_MAN (0x400B0034U) /**< \brief (EMAC) Phy Maintenance Register */ +#define REG_EMAC_PTR (0x400B0038U) /**< \brief (EMAC) Pause Time Register */ +#define REG_EMAC_PFR (0x400B003CU) /**< \brief (EMAC) Pause Frames Received Register */ +#define REG_EMAC_FTO (0x400B0040U) /**< \brief (EMAC) Frames Transmitted Ok Register */ +#define REG_EMAC_SCF (0x400B0044U) /**< \brief (EMAC) Single Collision Frames Register */ +#define REG_EMAC_MCF (0x400B0048U) /**< \brief (EMAC) Multiple Collision Frames Register */ +#define REG_EMAC_FRO (0x400B004CU) /**< \brief (EMAC) Frames Received Ok Register */ +#define REG_EMAC_FCSE (0x400B0050U) /**< \brief (EMAC) Frame Check Sequence Errors Register */ +#define REG_EMAC_ALE (0x400B0054U) /**< \brief (EMAC) Alignment Errors Register */ +#define REG_EMAC_DTF (0x400B0058U) /**< \brief (EMAC) Deferred Transmission Frames Register */ +#define REG_EMAC_LCOL (0x400B005CU) /**< \brief (EMAC) Late Collisions Register */ +#define REG_EMAC_ECOL (0x400B0060U) /**< \brief (EMAC) Excessive Collisions Register */ +#define REG_EMAC_TUND (0x400B0064U) /**< \brief (EMAC) Transmit Underrun Errors Register */ +#define REG_EMAC_CSE (0x400B0068U) /**< \brief (EMAC) Carrier Sense Errors Register */ +#define REG_EMAC_RRE (0x400B006CU) /**< \brief (EMAC) Receive Resource Errors Register */ +#define REG_EMAC_ROV (0x400B0070U) /**< \brief (EMAC) Receive Overrun Errors Register */ +#define REG_EMAC_RSE (0x400B0074U) /**< \brief (EMAC) Receive Symbol Errors Register */ +#define REG_EMAC_ELE (0x400B0078U) /**< \brief (EMAC) Excessive Length Errors Register */ +#define REG_EMAC_RJA (0x400B007CU) /**< \brief (EMAC) Receive Jabbers Register */ +#define REG_EMAC_USF (0x400B0080U) /**< \brief (EMAC) Undersize Frames Register */ +#define REG_EMAC_STE (0x400B0084U) /**< \brief (EMAC) SQE Test Errors Register */ +#define REG_EMAC_RLE (0x400B0088U) /**< \brief (EMAC) Received Length Field Mismatch Register */ +#define REG_EMAC_HRB (0x400B0090U) /**< \brief (EMAC) Hash Register Bottom [31:0] Register */ +#define REG_EMAC_HRT (0x400B0094U) /**< \brief (EMAC) Hash Register Top [63:32] Register */ +#define REG_EMAC_SA1B (0x400B0098U) /**< \brief (EMAC) Specific Address 1 Bottom Register */ +#define REG_EMAC_SA1T (0x400B009CU) /**< \brief (EMAC) Specific Address 1 Top Register */ +#define REG_EMAC_SA2B (0x400B00A0U) /**< \brief (EMAC) Specific Address 2 Bottom Register */ +#define REG_EMAC_SA2T (0x400B00A4U) /**< \brief (EMAC) Specific Address 2 Top Register */ +#define REG_EMAC_SA3B (0x400B00A8U) /**< \brief (EMAC) Specific Address 3 Bottom Register */ +#define REG_EMAC_SA3T (0x400B00ACU) /**< \brief (EMAC) Specific Address 3 Top Register */ +#define REG_EMAC_SA4B (0x400B00B0U) /**< \brief (EMAC) Specific Address 4 Bottom Register */ +#define REG_EMAC_SA4T (0x400B00B4U) /**< \brief (EMAC) Specific Address 4 Top Register */ +#define REG_EMAC_TID (0x400B00B8U) /**< \brief (EMAC) Type ID Checking Register */ +#define REG_EMAC_USRIO (0x400B00C0U) /**< \brief (EMAC) User Input/Output Register */ +#else +#define REG_EMAC_NCR (*(RwReg*)0x400B0000U) /**< \brief (EMAC) Network Control Register */ +#define REG_EMAC_NCFGR (*(RwReg*)0x400B0004U) /**< \brief (EMAC) Network Configuration Register */ +#define REG_EMAC_NSR (*(RoReg*)0x400B0008U) /**< \brief (EMAC) Network Status Register */ +#define REG_EMAC_TSR (*(RwReg*)0x400B0014U) /**< \brief (EMAC) Transmit Status Register */ +#define REG_EMAC_RBQP (*(RwReg*)0x400B0018U) /**< \brief (EMAC) Receive Buffer Queue Pointer Register */ +#define REG_EMAC_TBQP (*(RwReg*)0x400B001CU) /**< \brief (EMAC) Transmit Buffer Queue Pointer Register */ +#define REG_EMAC_RSR (*(RwReg*)0x400B0020U) /**< \brief (EMAC) Receive Status Register */ +#define REG_EMAC_ISR (*(RwReg*)0x400B0024U) /**< \brief (EMAC) Interrupt Status Register */ +#define REG_EMAC_IER (*(WoReg*)0x400B0028U) /**< \brief (EMAC) Interrupt Enable Register */ +#define REG_EMAC_IDR (*(WoReg*)0x400B002CU) /**< \brief (EMAC) Interrupt Disable Register */ +#define REG_EMAC_IMR (*(RoReg*)0x400B0030U) /**< \brief (EMAC) Interrupt Mask Register */ +#define REG_EMAC_MAN (*(RwReg*)0x400B0034U) /**< \brief (EMAC) Phy Maintenance Register */ +#define REG_EMAC_PTR (*(RwReg*)0x400B0038U) /**< \brief (EMAC) Pause Time Register */ +#define REG_EMAC_PFR (*(RwReg*)0x400B003CU) /**< \brief (EMAC) Pause Frames Received Register */ +#define REG_EMAC_FTO (*(RwReg*)0x400B0040U) /**< \brief (EMAC) Frames Transmitted Ok Register */ +#define REG_EMAC_SCF (*(RwReg*)0x400B0044U) /**< \brief (EMAC) Single Collision Frames Register */ +#define REG_EMAC_MCF (*(RwReg*)0x400B0048U) /**< \brief (EMAC) Multiple Collision Frames Register */ +#define REG_EMAC_FRO (*(RwReg*)0x400B004CU) /**< \brief (EMAC) Frames Received Ok Register */ +#define REG_EMAC_FCSE (*(RwReg*)0x400B0050U) /**< \brief (EMAC) Frame Check Sequence Errors Register */ +#define REG_EMAC_ALE (*(RwReg*)0x400B0054U) /**< \brief (EMAC) Alignment Errors Register */ +#define REG_EMAC_DTF (*(RwReg*)0x400B0058U) /**< \brief (EMAC) Deferred Transmission Frames Register */ +#define REG_EMAC_LCOL (*(RwReg*)0x400B005CU) /**< \brief (EMAC) Late Collisions Register */ +#define REG_EMAC_ECOL (*(RwReg*)0x400B0060U) /**< \brief (EMAC) Excessive Collisions Register */ +#define REG_EMAC_TUND (*(RwReg*)0x400B0064U) /**< \brief (EMAC) Transmit Underrun Errors Register */ +#define REG_EMAC_CSE (*(RwReg*)0x400B0068U) /**< \brief (EMAC) Carrier Sense Errors Register */ +#define REG_EMAC_RRE (*(RwReg*)0x400B006CU) /**< \brief (EMAC) Receive Resource Errors Register */ +#define REG_EMAC_ROV (*(RwReg*)0x400B0070U) /**< \brief (EMAC) Receive Overrun Errors Register */ +#define REG_EMAC_RSE (*(RwReg*)0x400B0074U) /**< \brief (EMAC) Receive Symbol Errors Register */ +#define REG_EMAC_ELE (*(RwReg*)0x400B0078U) /**< \brief (EMAC) Excessive Length Errors Register */ +#define REG_EMAC_RJA (*(RwReg*)0x400B007CU) /**< \brief (EMAC) Receive Jabbers Register */ +#define REG_EMAC_USF (*(RwReg*)0x400B0080U) /**< \brief (EMAC) Undersize Frames Register */ +#define REG_EMAC_STE (*(RwReg*)0x400B0084U) /**< \brief (EMAC) SQE Test Errors Register */ +#define REG_EMAC_RLE (*(RwReg*)0x400B0088U) /**< \brief (EMAC) Received Length Field Mismatch Register */ +#define REG_EMAC_HRB (*(RwReg*)0x400B0090U) /**< \brief (EMAC) Hash Register Bottom [31:0] Register */ +#define REG_EMAC_HRT (*(RwReg*)0x400B0094U) /**< \brief (EMAC) Hash Register Top [63:32] Register */ +#define REG_EMAC_SA1B (*(RwReg*)0x400B0098U) /**< \brief (EMAC) Specific Address 1 Bottom Register */ +#define REG_EMAC_SA1T (*(RwReg*)0x400B009CU) /**< \brief (EMAC) Specific Address 1 Top Register */ +#define REG_EMAC_SA2B (*(RwReg*)0x400B00A0U) /**< \brief (EMAC) Specific Address 2 Bottom Register */ +#define REG_EMAC_SA2T (*(RwReg*)0x400B00A4U) /**< \brief (EMAC) Specific Address 2 Top Register */ +#define REG_EMAC_SA3B (*(RwReg*)0x400B00A8U) /**< \brief (EMAC) Specific Address 3 Bottom Register */ +#define REG_EMAC_SA3T (*(RwReg*)0x400B00ACU) /**< \brief (EMAC) Specific Address 3 Top Register */ +#define REG_EMAC_SA4B (*(RwReg*)0x400B00B0U) /**< \brief (EMAC) Specific Address 4 Bottom Register */ +#define REG_EMAC_SA4T (*(RwReg*)0x400B00B4U) /**< \brief (EMAC) Specific Address 4 Top Register */ +#define REG_EMAC_TID (*(RwReg*)0x400B00B8U) /**< \brief (EMAC) Type ID Checking Register */ +#define REG_EMAC_USRIO (*(RwReg*)0x400B00C0U) /**< \brief (EMAC) User Input/Output Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_EMAC_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h new file mode 100644 index 0000000..9f9a06b --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_gpbr.h @@ -0,0 +1,55 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_GPBR_INSTANCE_ +#define _SAM3XA_GPBR_INSTANCE_ + +/* ========== Register definition for GPBR peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_GPBR_GPBR (0x400E1A90U) /**< \brief (GPBR) General Purpose Backup Register */ +#else +#define REG_GPBR_GPBR (*(RwReg*)0x400E1A90U) /**< \brief (GPBR) General Purpose Backup Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_GPBR_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h new file mode 100644 index 0000000..b8c4322 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_hsmci.h @@ -0,0 +1,93 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_HSMCI_INSTANCE_ +#define _SAM3XA_HSMCI_INSTANCE_ + +/* ========== Register definition for HSMCI peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_HSMCI_CR (0x40000000U) /**< \brief (HSMCI) Control Register */ +#define REG_HSMCI_MR (0x40000004U) /**< \brief (HSMCI) Mode Register */ +#define REG_HSMCI_DTOR (0x40000008U) /**< \brief (HSMCI) Data Timeout Register */ +#define REG_HSMCI_SDCR (0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ +#define REG_HSMCI_ARGR (0x40000010U) /**< \brief (HSMCI) Argument Register */ +#define REG_HSMCI_CMDR (0x40000014U) /**< \brief (HSMCI) Command Register */ +#define REG_HSMCI_BLKR (0x40000018U) /**< \brief (HSMCI) Block Register */ +#define REG_HSMCI_CSTOR (0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ +#define REG_HSMCI_RSPR (0x40000020U) /**< \brief (HSMCI) Response Register */ +#define REG_HSMCI_RDR (0x40000030U) /**< \brief (HSMCI) Receive Data Register */ +#define REG_HSMCI_TDR (0x40000034U) /**< \brief (HSMCI) Transmit Data Register */ +#define REG_HSMCI_SR (0x40000040U) /**< \brief (HSMCI) Status Register */ +#define REG_HSMCI_IER (0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */ +#define REG_HSMCI_IDR (0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */ +#define REG_HSMCI_IMR (0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */ +#define REG_HSMCI_DMA (0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */ +#define REG_HSMCI_CFG (0x40000054U) /**< \brief (HSMCI) Configuration Register */ +#define REG_HSMCI_WPMR (0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */ +#define REG_HSMCI_WPSR (0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */ +#define REG_HSMCI_FIFO (0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */ +#else +#define REG_HSMCI_CR (*(WoReg*)0x40000000U) /**< \brief (HSMCI) Control Register */ +#define REG_HSMCI_MR (*(RwReg*)0x40000004U) /**< \brief (HSMCI) Mode Register */ +#define REG_HSMCI_DTOR (*(RwReg*)0x40000008U) /**< \brief (HSMCI) Data Timeout Register */ +#define REG_HSMCI_SDCR (*(RwReg*)0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ +#define REG_HSMCI_ARGR (*(RwReg*)0x40000010U) /**< \brief (HSMCI) Argument Register */ +#define REG_HSMCI_CMDR (*(WoReg*)0x40000014U) /**< \brief (HSMCI) Command Register */ +#define REG_HSMCI_BLKR (*(RwReg*)0x40000018U) /**< \brief (HSMCI) Block Register */ +#define REG_HSMCI_CSTOR (*(RwReg*)0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ +#define REG_HSMCI_RSPR (*(RoReg*)0x40000020U) /**< \brief (HSMCI) Response Register */ +#define REG_HSMCI_RDR (*(RoReg*)0x40000030U) /**< \brief (HSMCI) Receive Data Register */ +#define REG_HSMCI_TDR (*(WoReg*)0x40000034U) /**< \brief (HSMCI) Transmit Data Register */ +#define REG_HSMCI_SR (*(RoReg*)0x40000040U) /**< \brief (HSMCI) Status Register */ +#define REG_HSMCI_IER (*(WoReg*)0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */ +#define REG_HSMCI_IDR (*(WoReg*)0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */ +#define REG_HSMCI_IMR (*(RoReg*)0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */ +#define REG_HSMCI_DMA (*(RwReg*)0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */ +#define REG_HSMCI_CFG (*(RwReg*)0x40000054U) /**< \brief (HSMCI) Configuration Register */ +#define REG_HSMCI_WPMR (*(RwReg*)0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */ +#define REG_HSMCI_WPSR (*(RoReg*)0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */ +#define REG_HSMCI_FIFO (*(RwReg*)0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_HSMCI_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h new file mode 100644 index 0000000..713aab1 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_matrix.h @@ -0,0 +1,83 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_MATRIX_INSTANCE_ +#define _SAM3XA_MATRIX_INSTANCE_ + +/* ========== Register definition for MATRIX peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_MATRIX_MCFG (0x400E0400U) /**< \brief (MATRIX) Master Configuration Register */ +#define REG_MATRIX_SCFG (0x400E0440U) /**< \brief (MATRIX) Slave Configuration Register */ +#define REG_MATRIX_PRAS0 (0x400E0480U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ +#define REG_MATRIX_PRAS1 (0x400E0488U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ +#define REG_MATRIX_PRAS2 (0x400E0490U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ +#define REG_MATRIX_PRAS3 (0x400E0498U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ +#define REG_MATRIX_PRAS4 (0x400E04A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ +#define REG_MATRIX_PRAS5 (0x400E04A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */ +#define REG_MATRIX_PRAS6 (0x400E04B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */ +#define REG_MATRIX_PRAS7 (0x400E04B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */ +#define REG_MATRIX_PRAS8 (0x400E04C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */ +#define REG_MATRIX_MRCR (0x400E0500U) /**< \brief (MATRIX) Master Remap Control Register */ +#define REG_CCFG_SYSIO (0x400E0514U) /**< \brief (MATRIX) System I/O Configuration register */ +#define REG_MATRIX_WPMR (0x400E05E4U) /**< \brief (MATRIX) Write Protect Mode Register */ +#define REG_MATRIX_WPSR (0x400E05E8U) /**< \brief (MATRIX) Write Protect Status Register */ +#else +#define REG_MATRIX_MCFG (*(RwReg*)0x400E0400U) /**< \brief (MATRIX) Master Configuration Register */ +#define REG_MATRIX_SCFG (*(RwReg*)0x400E0440U) /**< \brief (MATRIX) Slave Configuration Register */ +#define REG_MATRIX_PRAS0 (*(RwReg*)0x400E0480U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ +#define REG_MATRIX_PRAS1 (*(RwReg*)0x400E0488U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ +#define REG_MATRIX_PRAS2 (*(RwReg*)0x400E0490U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ +#define REG_MATRIX_PRAS3 (*(RwReg*)0x400E0498U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ +#define REG_MATRIX_PRAS4 (*(RwReg*)0x400E04A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ +#define REG_MATRIX_PRAS5 (*(RwReg*)0x400E04A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */ +#define REG_MATRIX_PRAS6 (*(RwReg*)0x400E04B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */ +#define REG_MATRIX_PRAS7 (*(RwReg*)0x400E04B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */ +#define REG_MATRIX_PRAS8 (*(RwReg*)0x400E04C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */ +#define REG_MATRIX_MRCR (*(RwReg*)0x400E0500U) /**< \brief (MATRIX) Master Remap Control Register */ +#define REG_CCFG_SYSIO (*(RwReg*)0x400E0514U) /**< \brief (MATRIX) System I/O Configuration register */ +#define REG_MATRIX_WPMR (*(RwReg*)0x400E05E4U) /**< \brief (MATRIX) Write Protect Mode Register */ +#define REG_MATRIX_WPSR (*(RoReg*)0x400E05E8U) /**< \brief (MATRIX) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_MATRIX_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h new file mode 100644 index 0000000..d40edfa --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioa.h @@ -0,0 +1,139 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_PIOA_INSTANCE_ +#define _SAM3XA_PIOA_INSTANCE_ + +/* ========== Register definition for PIOA peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PIOA_PER (0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */ +#define REG_PIOA_PDR (0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */ +#define REG_PIOA_PSR (0x400E0E08U) /**< \brief (PIOA) PIO Status Register */ +#define REG_PIOA_OER (0x400E0E10U) /**< \brief (PIOA) Output Enable Register */ +#define REG_PIOA_ODR (0x400E0E14U) /**< \brief (PIOA) Output Disable Register */ +#define REG_PIOA_OSR (0x400E0E18U) /**< \brief (PIOA) Output Status Register */ +#define REG_PIOA_IFER (0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ +#define REG_PIOA_IFDR (0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ +#define REG_PIOA_IFSR (0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ +#define REG_PIOA_SODR (0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */ +#define REG_PIOA_CODR (0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */ +#define REG_PIOA_ODSR (0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */ +#define REG_PIOA_PDSR (0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */ +#define REG_PIOA_IER (0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */ +#define REG_PIOA_IDR (0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */ +#define REG_PIOA_IMR (0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */ +#define REG_PIOA_ISR (0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */ +#define REG_PIOA_MDER (0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */ +#define REG_PIOA_MDDR (0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */ +#define REG_PIOA_MDSR (0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */ +#define REG_PIOA_PUDR (0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */ +#define REG_PIOA_PUER (0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */ +#define REG_PIOA_PUSR (0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */ +#define REG_PIOA_ABSR (0x400E0E70U) /**< \brief (PIOA) Peripheral AB Select Register */ +#define REG_PIOA_SCIFSR (0x400E0E80U) /**< \brief (PIOA) System Clock Glitch Input Filter Select Register */ +#define REG_PIOA_DIFSR (0x400E0E84U) /**< \brief (PIOA) Debouncing Input Filter Select Register */ +#define REG_PIOA_IFDGSR (0x400E0E88U) /**< \brief (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOA_SCDR (0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ +#define REG_PIOA_OWER (0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */ +#define REG_PIOA_OWDR (0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */ +#define REG_PIOA_OWSR (0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */ +#define REG_PIOA_AIMER (0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ +#define REG_PIOA_AIMDR (0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */ +#define REG_PIOA_AIMMR (0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ +#define REG_PIOA_ESR (0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */ +#define REG_PIOA_LSR (0x400E0EC4U) /**< \brief (PIOA) Level Select Register */ +#define REG_PIOA_ELSR (0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */ +#define REG_PIOA_FELLSR (0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */ +#define REG_PIOA_REHLSR (0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */ +#define REG_PIOA_FRLHSR (0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ +#define REG_PIOA_LOCKSR (0x400E0EE0U) /**< \brief (PIOA) Lock Status */ +#define REG_PIOA_WPMR (0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */ +#define REG_PIOA_WPSR (0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */ +#else +#define REG_PIOA_PER (*(WoReg*)0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */ +#define REG_PIOA_PDR (*(WoReg*)0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */ +#define REG_PIOA_PSR (*(RoReg*)0x400E0E08U) /**< \brief (PIOA) PIO Status Register */ +#define REG_PIOA_OER (*(WoReg*)0x400E0E10U) /**< \brief (PIOA) Output Enable Register */ +#define REG_PIOA_ODR (*(WoReg*)0x400E0E14U) /**< \brief (PIOA) Output Disable Register */ +#define REG_PIOA_OSR (*(RoReg*)0x400E0E18U) /**< \brief (PIOA) Output Status Register */ +#define REG_PIOA_IFER (*(WoReg*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ +#define REG_PIOA_IFDR (*(WoReg*)0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ +#define REG_PIOA_IFSR (*(RoReg*)0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ +#define REG_PIOA_SODR (*(WoReg*)0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */ +#define REG_PIOA_CODR (*(WoReg*)0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */ +#define REG_PIOA_ODSR (*(RwReg*)0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */ +#define REG_PIOA_PDSR (*(RoReg*)0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */ +#define REG_PIOA_IER (*(WoReg*)0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */ +#define REG_PIOA_IDR (*(WoReg*)0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */ +#define REG_PIOA_IMR (*(RoReg*)0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */ +#define REG_PIOA_ISR (*(RoReg*)0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */ +#define REG_PIOA_MDER (*(WoReg*)0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */ +#define REG_PIOA_MDDR (*(WoReg*)0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */ +#define REG_PIOA_MDSR (*(RoReg*)0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */ +#define REG_PIOA_PUDR (*(WoReg*)0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */ +#define REG_PIOA_PUER (*(WoReg*)0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */ +#define REG_PIOA_PUSR (*(RoReg*)0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */ +#define REG_PIOA_ABSR (*(RwReg*)0x400E0E70U) /**< \brief (PIOA) Peripheral AB Select Register */ +#define REG_PIOA_SCIFSR (*(WoReg*)0x400E0E80U) /**< \brief (PIOA) System Clock Glitch Input Filter Select Register */ +#define REG_PIOA_DIFSR (*(WoReg*)0x400E0E84U) /**< \brief (PIOA) Debouncing Input Filter Select Register */ +#define REG_PIOA_IFDGSR (*(RoReg*)0x400E0E88U) /**< \brief (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOA_SCDR (*(RwReg*)0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ +#define REG_PIOA_OWER (*(WoReg*)0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */ +#define REG_PIOA_OWDR (*(WoReg*)0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */ +#define REG_PIOA_OWSR (*(RoReg*)0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */ +#define REG_PIOA_AIMER (*(WoReg*)0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ +#define REG_PIOA_AIMDR (*(WoReg*)0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */ +#define REG_PIOA_AIMMR (*(RoReg*)0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ +#define REG_PIOA_ESR (*(WoReg*)0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */ +#define REG_PIOA_LSR (*(WoReg*)0x400E0EC4U) /**< \brief (PIOA) Level Select Register */ +#define REG_PIOA_ELSR (*(RoReg*)0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */ +#define REG_PIOA_FELLSR (*(WoReg*)0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */ +#define REG_PIOA_REHLSR (*(WoReg*)0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */ +#define REG_PIOA_FRLHSR (*(RoReg*)0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ +#define REG_PIOA_LOCKSR (*(RoReg*)0x400E0EE0U) /**< \brief (PIOA) Lock Status */ +#define REG_PIOA_WPMR (*(RwReg*)0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */ +#define REG_PIOA_WPSR (*(RoReg*)0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_PIOA_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h new file mode 100644 index 0000000..056e048 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piob.h @@ -0,0 +1,139 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_PIOB_INSTANCE_ +#define _SAM3XA_PIOB_INSTANCE_ + +/* ========== Register definition for PIOB peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PIOB_PER (0x400E1000U) /**< \brief (PIOB) PIO Enable Register */ +#define REG_PIOB_PDR (0x400E1004U) /**< \brief (PIOB) PIO Disable Register */ +#define REG_PIOB_PSR (0x400E1008U) /**< \brief (PIOB) PIO Status Register */ +#define REG_PIOB_OER (0x400E1010U) /**< \brief (PIOB) Output Enable Register */ +#define REG_PIOB_ODR (0x400E1014U) /**< \brief (PIOB) Output Disable Register */ +#define REG_PIOB_OSR (0x400E1018U) /**< \brief (PIOB) Output Status Register */ +#define REG_PIOB_IFER (0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ +#define REG_PIOB_IFDR (0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ +#define REG_PIOB_IFSR (0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */ +#define REG_PIOB_SODR (0x400E1030U) /**< \brief (PIOB) Set Output Data Register */ +#define REG_PIOB_CODR (0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */ +#define REG_PIOB_ODSR (0x400E1038U) /**< \brief (PIOB) Output Data Status Register */ +#define REG_PIOB_PDSR (0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */ +#define REG_PIOB_IER (0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */ +#define REG_PIOB_IDR (0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */ +#define REG_PIOB_IMR (0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */ +#define REG_PIOB_ISR (0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */ +#define REG_PIOB_MDER (0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */ +#define REG_PIOB_MDDR (0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */ +#define REG_PIOB_MDSR (0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */ +#define REG_PIOB_PUDR (0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */ +#define REG_PIOB_PUER (0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */ +#define REG_PIOB_PUSR (0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */ +#define REG_PIOB_ABSR (0x400E1070U) /**< \brief (PIOB) Peripheral AB Select Register */ +#define REG_PIOB_SCIFSR (0x400E1080U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */ +#define REG_PIOB_DIFSR (0x400E1084U) /**< \brief (PIOB) Debouncing Input Filter Select Register */ +#define REG_PIOB_IFDGSR (0x400E1088U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOB_SCDR (0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ +#define REG_PIOB_OWER (0x400E10A0U) /**< \brief (PIOB) Output Write Enable */ +#define REG_PIOB_OWDR (0x400E10A4U) /**< \brief (PIOB) Output Write Disable */ +#define REG_PIOB_OWSR (0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */ +#define REG_PIOB_AIMER (0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ +#define REG_PIOB_AIMDR (0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */ +#define REG_PIOB_AIMMR (0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ +#define REG_PIOB_ESR (0x400E10C0U) /**< \brief (PIOB) Edge Select Register */ +#define REG_PIOB_LSR (0x400E10C4U) /**< \brief (PIOB) Level Select Register */ +#define REG_PIOB_ELSR (0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */ +#define REG_PIOB_FELLSR (0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */ +#define REG_PIOB_REHLSR (0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */ +#define REG_PIOB_FRLHSR (0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ +#define REG_PIOB_LOCKSR (0x400E10E0U) /**< \brief (PIOB) Lock Status */ +#define REG_PIOB_WPMR (0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */ +#define REG_PIOB_WPSR (0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */ +#else +#define REG_PIOB_PER (*(WoReg*)0x400E1000U) /**< \brief (PIOB) PIO Enable Register */ +#define REG_PIOB_PDR (*(WoReg*)0x400E1004U) /**< \brief (PIOB) PIO Disable Register */ +#define REG_PIOB_PSR (*(RoReg*)0x400E1008U) /**< \brief (PIOB) PIO Status Register */ +#define REG_PIOB_OER (*(WoReg*)0x400E1010U) /**< \brief (PIOB) Output Enable Register */ +#define REG_PIOB_ODR (*(WoReg*)0x400E1014U) /**< \brief (PIOB) Output Disable Register */ +#define REG_PIOB_OSR (*(RoReg*)0x400E1018U) /**< \brief (PIOB) Output Status Register */ +#define REG_PIOB_IFER (*(WoReg*)0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ +#define REG_PIOB_IFDR (*(WoReg*)0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ +#define REG_PIOB_IFSR (*(RoReg*)0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */ +#define REG_PIOB_SODR (*(WoReg*)0x400E1030U) /**< \brief (PIOB) Set Output Data Register */ +#define REG_PIOB_CODR (*(WoReg*)0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */ +#define REG_PIOB_ODSR (*(RwReg*)0x400E1038U) /**< \brief (PIOB) Output Data Status Register */ +#define REG_PIOB_PDSR (*(RoReg*)0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */ +#define REG_PIOB_IER (*(WoReg*)0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */ +#define REG_PIOB_IDR (*(WoReg*)0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */ +#define REG_PIOB_IMR (*(RoReg*)0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */ +#define REG_PIOB_ISR (*(RoReg*)0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */ +#define REG_PIOB_MDER (*(WoReg*)0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */ +#define REG_PIOB_MDDR (*(WoReg*)0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */ +#define REG_PIOB_MDSR (*(RoReg*)0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */ +#define REG_PIOB_PUDR (*(WoReg*)0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */ +#define REG_PIOB_PUER (*(WoReg*)0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */ +#define REG_PIOB_PUSR (*(RoReg*)0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */ +#define REG_PIOB_ABSR (*(RwReg*)0x400E1070U) /**< \brief (PIOB) Peripheral AB Select Register */ +#define REG_PIOB_SCIFSR (*(WoReg*)0x400E1080U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */ +#define REG_PIOB_DIFSR (*(WoReg*)0x400E1084U) /**< \brief (PIOB) Debouncing Input Filter Select Register */ +#define REG_PIOB_IFDGSR (*(RoReg*)0x400E1088U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOB_SCDR (*(RwReg*)0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ +#define REG_PIOB_OWER (*(WoReg*)0x400E10A0U) /**< \brief (PIOB) Output Write Enable */ +#define REG_PIOB_OWDR (*(WoReg*)0x400E10A4U) /**< \brief (PIOB) Output Write Disable */ +#define REG_PIOB_OWSR (*(RoReg*)0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */ +#define REG_PIOB_AIMER (*(WoReg*)0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ +#define REG_PIOB_AIMDR (*(WoReg*)0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */ +#define REG_PIOB_AIMMR (*(RoReg*)0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ +#define REG_PIOB_ESR (*(WoReg*)0x400E10C0U) /**< \brief (PIOB) Edge Select Register */ +#define REG_PIOB_LSR (*(WoReg*)0x400E10C4U) /**< \brief (PIOB) Level Select Register */ +#define REG_PIOB_ELSR (*(RoReg*)0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */ +#define REG_PIOB_FELLSR (*(WoReg*)0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */ +#define REG_PIOB_REHLSR (*(WoReg*)0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */ +#define REG_PIOB_FRLHSR (*(RoReg*)0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ +#define REG_PIOB_LOCKSR (*(RoReg*)0x400E10E0U) /**< \brief (PIOB) Lock Status */ +#define REG_PIOB_WPMR (*(RwReg*)0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */ +#define REG_PIOB_WPSR (*(RoReg*)0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_PIOB_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h new file mode 100644 index 0000000..01e0977 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioc.h @@ -0,0 +1,139 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_PIOC_INSTANCE_ +#define _SAM3XA_PIOC_INSTANCE_ + +/* ========== Register definition for PIOC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PIOC_PER (0x400E1200U) /**< \brief (PIOC) PIO Enable Register */ +#define REG_PIOC_PDR (0x400E1204U) /**< \brief (PIOC) PIO Disable Register */ +#define REG_PIOC_PSR (0x400E1208U) /**< \brief (PIOC) PIO Status Register */ +#define REG_PIOC_OER (0x400E1210U) /**< \brief (PIOC) Output Enable Register */ +#define REG_PIOC_ODR (0x400E1214U) /**< \brief (PIOC) Output Disable Register */ +#define REG_PIOC_OSR (0x400E1218U) /**< \brief (PIOC) Output Status Register */ +#define REG_PIOC_IFER (0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ +#define REG_PIOC_IFDR (0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ +#define REG_PIOC_IFSR (0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */ +#define REG_PIOC_SODR (0x400E1230U) /**< \brief (PIOC) Set Output Data Register */ +#define REG_PIOC_CODR (0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */ +#define REG_PIOC_ODSR (0x400E1238U) /**< \brief (PIOC) Output Data Status Register */ +#define REG_PIOC_PDSR (0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */ +#define REG_PIOC_IER (0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */ +#define REG_PIOC_IDR (0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */ +#define REG_PIOC_IMR (0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */ +#define REG_PIOC_ISR (0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */ +#define REG_PIOC_MDER (0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */ +#define REG_PIOC_MDDR (0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */ +#define REG_PIOC_MDSR (0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */ +#define REG_PIOC_PUDR (0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */ +#define REG_PIOC_PUER (0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */ +#define REG_PIOC_PUSR (0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */ +#define REG_PIOC_ABSR (0x400E1270U) /**< \brief (PIOC) Peripheral AB Select Register */ +#define REG_PIOC_SCIFSR (0x400E1280U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */ +#define REG_PIOC_DIFSR (0x400E1284U) /**< \brief (PIOC) Debouncing Input Filter Select Register */ +#define REG_PIOC_IFDGSR (0x400E1288U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOC_SCDR (0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ +#define REG_PIOC_OWER (0x400E12A0U) /**< \brief (PIOC) Output Write Enable */ +#define REG_PIOC_OWDR (0x400E12A4U) /**< \brief (PIOC) Output Write Disable */ +#define REG_PIOC_OWSR (0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */ +#define REG_PIOC_AIMER (0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ +#define REG_PIOC_AIMDR (0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */ +#define REG_PIOC_AIMMR (0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ +#define REG_PIOC_ESR (0x400E12C0U) /**< \brief (PIOC) Edge Select Register */ +#define REG_PIOC_LSR (0x400E12C4U) /**< \brief (PIOC) Level Select Register */ +#define REG_PIOC_ELSR (0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */ +#define REG_PIOC_FELLSR (0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */ +#define REG_PIOC_REHLSR (0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */ +#define REG_PIOC_FRLHSR (0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ +#define REG_PIOC_LOCKSR (0x400E12E0U) /**< \brief (PIOC) Lock Status */ +#define REG_PIOC_WPMR (0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */ +#define REG_PIOC_WPSR (0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */ +#else +#define REG_PIOC_PER (*(WoReg*)0x400E1200U) /**< \brief (PIOC) PIO Enable Register */ +#define REG_PIOC_PDR (*(WoReg*)0x400E1204U) /**< \brief (PIOC) PIO Disable Register */ +#define REG_PIOC_PSR (*(RoReg*)0x400E1208U) /**< \brief (PIOC) PIO Status Register */ +#define REG_PIOC_OER (*(WoReg*)0x400E1210U) /**< \brief (PIOC) Output Enable Register */ +#define REG_PIOC_ODR (*(WoReg*)0x400E1214U) /**< \brief (PIOC) Output Disable Register */ +#define REG_PIOC_OSR (*(RoReg*)0x400E1218U) /**< \brief (PIOC) Output Status Register */ +#define REG_PIOC_IFER (*(WoReg*)0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ +#define REG_PIOC_IFDR (*(WoReg*)0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ +#define REG_PIOC_IFSR (*(RoReg*)0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */ +#define REG_PIOC_SODR (*(WoReg*)0x400E1230U) /**< \brief (PIOC) Set Output Data Register */ +#define REG_PIOC_CODR (*(WoReg*)0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */ +#define REG_PIOC_ODSR (*(RwReg*)0x400E1238U) /**< \brief (PIOC) Output Data Status Register */ +#define REG_PIOC_PDSR (*(RoReg*)0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */ +#define REG_PIOC_IER (*(WoReg*)0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */ +#define REG_PIOC_IDR (*(WoReg*)0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */ +#define REG_PIOC_IMR (*(RoReg*)0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */ +#define REG_PIOC_ISR (*(RoReg*)0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */ +#define REG_PIOC_MDER (*(WoReg*)0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */ +#define REG_PIOC_MDDR (*(WoReg*)0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */ +#define REG_PIOC_MDSR (*(RoReg*)0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */ +#define REG_PIOC_PUDR (*(WoReg*)0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */ +#define REG_PIOC_PUER (*(WoReg*)0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */ +#define REG_PIOC_PUSR (*(RoReg*)0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */ +#define REG_PIOC_ABSR (*(RwReg*)0x400E1270U) /**< \brief (PIOC) Peripheral AB Select Register */ +#define REG_PIOC_SCIFSR (*(WoReg*)0x400E1280U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */ +#define REG_PIOC_DIFSR (*(WoReg*)0x400E1284U) /**< \brief (PIOC) Debouncing Input Filter Select Register */ +#define REG_PIOC_IFDGSR (*(RoReg*)0x400E1288U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOC_SCDR (*(RwReg*)0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ +#define REG_PIOC_OWER (*(WoReg*)0x400E12A0U) /**< \brief (PIOC) Output Write Enable */ +#define REG_PIOC_OWDR (*(WoReg*)0x400E12A4U) /**< \brief (PIOC) Output Write Disable */ +#define REG_PIOC_OWSR (*(RoReg*)0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */ +#define REG_PIOC_AIMER (*(WoReg*)0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ +#define REG_PIOC_AIMDR (*(WoReg*)0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */ +#define REG_PIOC_AIMMR (*(RoReg*)0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ +#define REG_PIOC_ESR (*(WoReg*)0x400E12C0U) /**< \brief (PIOC) Edge Select Register */ +#define REG_PIOC_LSR (*(WoReg*)0x400E12C4U) /**< \brief (PIOC) Level Select Register */ +#define REG_PIOC_ELSR (*(RoReg*)0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */ +#define REG_PIOC_FELLSR (*(WoReg*)0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */ +#define REG_PIOC_REHLSR (*(WoReg*)0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */ +#define REG_PIOC_FRLHSR (*(RoReg*)0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ +#define REG_PIOC_LOCKSR (*(RoReg*)0x400E12E0U) /**< \brief (PIOC) Lock Status */ +#define REG_PIOC_WPMR (*(RwReg*)0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */ +#define REG_PIOC_WPSR (*(RoReg*)0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_PIOC_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h new file mode 100644 index 0000000..8c92a45 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piod.h @@ -0,0 +1,139 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_PIOD_INSTANCE_ +#define _SAM3XA_PIOD_INSTANCE_ + +/* ========== Register definition for PIOD peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PIOD_PER (0x400E1400U) /**< \brief (PIOD) PIO Enable Register */ +#define REG_PIOD_PDR (0x400E1404U) /**< \brief (PIOD) PIO Disable Register */ +#define REG_PIOD_PSR (0x400E1408U) /**< \brief (PIOD) PIO Status Register */ +#define REG_PIOD_OER (0x400E1410U) /**< \brief (PIOD) Output Enable Register */ +#define REG_PIOD_ODR (0x400E1414U) /**< \brief (PIOD) Output Disable Register */ +#define REG_PIOD_OSR (0x400E1418U) /**< \brief (PIOD) Output Status Register */ +#define REG_PIOD_IFER (0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */ +#define REG_PIOD_IFDR (0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */ +#define REG_PIOD_IFSR (0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */ +#define REG_PIOD_SODR (0x400E1430U) /**< \brief (PIOD) Set Output Data Register */ +#define REG_PIOD_CODR (0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */ +#define REG_PIOD_ODSR (0x400E1438U) /**< \brief (PIOD) Output Data Status Register */ +#define REG_PIOD_PDSR (0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */ +#define REG_PIOD_IER (0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */ +#define REG_PIOD_IDR (0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */ +#define REG_PIOD_IMR (0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */ +#define REG_PIOD_ISR (0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */ +#define REG_PIOD_MDER (0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */ +#define REG_PIOD_MDDR (0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */ +#define REG_PIOD_MDSR (0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */ +#define REG_PIOD_PUDR (0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */ +#define REG_PIOD_PUER (0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */ +#define REG_PIOD_PUSR (0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */ +#define REG_PIOD_ABSR (0x400E1470U) /**< \brief (PIOD) Peripheral AB Select Register */ +#define REG_PIOD_SCIFSR (0x400E1480U) /**< \brief (PIOD) System Clock Glitch Input Filter Select Register */ +#define REG_PIOD_DIFSR (0x400E1484U) /**< \brief (PIOD) Debouncing Input Filter Select Register */ +#define REG_PIOD_IFDGSR (0x400E1488U) /**< \brief (PIOD) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOD_SCDR (0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */ +#define REG_PIOD_OWER (0x400E14A0U) /**< \brief (PIOD) Output Write Enable */ +#define REG_PIOD_OWDR (0x400E14A4U) /**< \brief (PIOD) Output Write Disable */ +#define REG_PIOD_OWSR (0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */ +#define REG_PIOD_AIMER (0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */ +#define REG_PIOD_AIMDR (0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disables Register */ +#define REG_PIOD_AIMMR (0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */ +#define REG_PIOD_ESR (0x400E14C0U) /**< \brief (PIOD) Edge Select Register */ +#define REG_PIOD_LSR (0x400E14C4U) /**< \brief (PIOD) Level Select Register */ +#define REG_PIOD_ELSR (0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */ +#define REG_PIOD_FELLSR (0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low Level Select Register */ +#define REG_PIOD_REHLSR (0x400E14D4U) /**< \brief (PIOD) Rising Edge/ High Level Select Register */ +#define REG_PIOD_FRLHSR (0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */ +#define REG_PIOD_LOCKSR (0x400E14E0U) /**< \brief (PIOD) Lock Status */ +#define REG_PIOD_WPMR (0x400E14E4U) /**< \brief (PIOD) Write Protect Mode Register */ +#define REG_PIOD_WPSR (0x400E14E8U) /**< \brief (PIOD) Write Protect Status Register */ +#else +#define REG_PIOD_PER (*(WoReg*)0x400E1400U) /**< \brief (PIOD) PIO Enable Register */ +#define REG_PIOD_PDR (*(WoReg*)0x400E1404U) /**< \brief (PIOD) PIO Disable Register */ +#define REG_PIOD_PSR (*(RoReg*)0x400E1408U) /**< \brief (PIOD) PIO Status Register */ +#define REG_PIOD_OER (*(WoReg*)0x400E1410U) /**< \brief (PIOD) Output Enable Register */ +#define REG_PIOD_ODR (*(WoReg*)0x400E1414U) /**< \brief (PIOD) Output Disable Register */ +#define REG_PIOD_OSR (*(RoReg*)0x400E1418U) /**< \brief (PIOD) Output Status Register */ +#define REG_PIOD_IFER (*(WoReg*)0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */ +#define REG_PIOD_IFDR (*(WoReg*)0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */ +#define REG_PIOD_IFSR (*(RoReg*)0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */ +#define REG_PIOD_SODR (*(WoReg*)0x400E1430U) /**< \brief (PIOD) Set Output Data Register */ +#define REG_PIOD_CODR (*(WoReg*)0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */ +#define REG_PIOD_ODSR (*(RwReg*)0x400E1438U) /**< \brief (PIOD) Output Data Status Register */ +#define REG_PIOD_PDSR (*(RoReg*)0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */ +#define REG_PIOD_IER (*(WoReg*)0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */ +#define REG_PIOD_IDR (*(WoReg*)0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */ +#define REG_PIOD_IMR (*(RoReg*)0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */ +#define REG_PIOD_ISR (*(RoReg*)0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */ +#define REG_PIOD_MDER (*(WoReg*)0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */ +#define REG_PIOD_MDDR (*(WoReg*)0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */ +#define REG_PIOD_MDSR (*(RoReg*)0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */ +#define REG_PIOD_PUDR (*(WoReg*)0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */ +#define REG_PIOD_PUER (*(WoReg*)0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */ +#define REG_PIOD_PUSR (*(RoReg*)0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */ +#define REG_PIOD_ABSR (*(RwReg*)0x400E1470U) /**< \brief (PIOD) Peripheral AB Select Register */ +#define REG_PIOD_SCIFSR (*(WoReg*)0x400E1480U) /**< \brief (PIOD) System Clock Glitch Input Filter Select Register */ +#define REG_PIOD_DIFSR (*(WoReg*)0x400E1484U) /**< \brief (PIOD) Debouncing Input Filter Select Register */ +#define REG_PIOD_IFDGSR (*(RoReg*)0x400E1488U) /**< \brief (PIOD) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOD_SCDR (*(RwReg*)0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */ +#define REG_PIOD_OWER (*(WoReg*)0x400E14A0U) /**< \brief (PIOD) Output Write Enable */ +#define REG_PIOD_OWDR (*(WoReg*)0x400E14A4U) /**< \brief (PIOD) Output Write Disable */ +#define REG_PIOD_OWSR (*(RoReg*)0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */ +#define REG_PIOD_AIMER (*(WoReg*)0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */ +#define REG_PIOD_AIMDR (*(WoReg*)0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disables Register */ +#define REG_PIOD_AIMMR (*(RoReg*)0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */ +#define REG_PIOD_ESR (*(WoReg*)0x400E14C0U) /**< \brief (PIOD) Edge Select Register */ +#define REG_PIOD_LSR (*(WoReg*)0x400E14C4U) /**< \brief (PIOD) Level Select Register */ +#define REG_PIOD_ELSR (*(RoReg*)0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */ +#define REG_PIOD_FELLSR (*(WoReg*)0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low Level Select Register */ +#define REG_PIOD_REHLSR (*(WoReg*)0x400E14D4U) /**< \brief (PIOD) Rising Edge/ High Level Select Register */ +#define REG_PIOD_FRLHSR (*(RoReg*)0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */ +#define REG_PIOD_LOCKSR (*(RoReg*)0x400E14E0U) /**< \brief (PIOD) Lock Status */ +#define REG_PIOD_WPMR (*(RwReg*)0x400E14E4U) /**< \brief (PIOD) Write Protect Mode Register */ +#define REG_PIOD_WPSR (*(RoReg*)0x400E14E8U) /**< \brief (PIOD) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_PIOD_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioe.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioe.h new file mode 100644 index 0000000..a51d30c --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pioe.h @@ -0,0 +1,139 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_PIOE_INSTANCE_ +#define _SAM3XA_PIOE_INSTANCE_ + +/* ========== Register definition for PIOE peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PIOE_PER (0x400E1600U) /**< \brief (PIOE) PIO Enable Register */ +#define REG_PIOE_PDR (0x400E1604U) /**< \brief (PIOE) PIO Disable Register */ +#define REG_PIOE_PSR (0x400E1608U) /**< \brief (PIOE) PIO Status Register */ +#define REG_PIOE_OER (0x400E1610U) /**< \brief (PIOE) Output Enable Register */ +#define REG_PIOE_ODR (0x400E1614U) /**< \brief (PIOE) Output Disable Register */ +#define REG_PIOE_OSR (0x400E1618U) /**< \brief (PIOE) Output Status Register */ +#define REG_PIOE_IFER (0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */ +#define REG_PIOE_IFDR (0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */ +#define REG_PIOE_IFSR (0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */ +#define REG_PIOE_SODR (0x400E1630U) /**< \brief (PIOE) Set Output Data Register */ +#define REG_PIOE_CODR (0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */ +#define REG_PIOE_ODSR (0x400E1638U) /**< \brief (PIOE) Output Data Status Register */ +#define REG_PIOE_PDSR (0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */ +#define REG_PIOE_IER (0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */ +#define REG_PIOE_IDR (0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */ +#define REG_PIOE_IMR (0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */ +#define REG_PIOE_ISR (0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */ +#define REG_PIOE_MDER (0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */ +#define REG_PIOE_MDDR (0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */ +#define REG_PIOE_MDSR (0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */ +#define REG_PIOE_PUDR (0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */ +#define REG_PIOE_PUER (0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */ +#define REG_PIOE_PUSR (0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */ +#define REG_PIOE_ABSR (0x400E1670U) /**< \brief (PIOE) Peripheral AB Select Register */ +#define REG_PIOE_SCIFSR (0x400E1680U) /**< \brief (PIOE) System Clock Glitch Input Filter Select Register */ +#define REG_PIOE_DIFSR (0x400E1684U) /**< \brief (PIOE) Debouncing Input Filter Select Register */ +#define REG_PIOE_IFDGSR (0x400E1688U) /**< \brief (PIOE) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOE_SCDR (0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */ +#define REG_PIOE_OWER (0x400E16A0U) /**< \brief (PIOE) Output Write Enable */ +#define REG_PIOE_OWDR (0x400E16A4U) /**< \brief (PIOE) Output Write Disable */ +#define REG_PIOE_OWSR (0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */ +#define REG_PIOE_AIMER (0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */ +#define REG_PIOE_AIMDR (0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disables Register */ +#define REG_PIOE_AIMMR (0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */ +#define REG_PIOE_ESR (0x400E16C0U) /**< \brief (PIOE) Edge Select Register */ +#define REG_PIOE_LSR (0x400E16C4U) /**< \brief (PIOE) Level Select Register */ +#define REG_PIOE_ELSR (0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */ +#define REG_PIOE_FELLSR (0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low Level Select Register */ +#define REG_PIOE_REHLSR (0x400E16D4U) /**< \brief (PIOE) Rising Edge/ High Level Select Register */ +#define REG_PIOE_FRLHSR (0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */ +#define REG_PIOE_LOCKSR (0x400E16E0U) /**< \brief (PIOE) Lock Status */ +#define REG_PIOE_WPMR (0x400E16E4U) /**< \brief (PIOE) Write Protect Mode Register */ +#define REG_PIOE_WPSR (0x400E16E8U) /**< \brief (PIOE) Write Protect Status Register */ +#else +#define REG_PIOE_PER (*(WoReg*)0x400E1600U) /**< \brief (PIOE) PIO Enable Register */ +#define REG_PIOE_PDR (*(WoReg*)0x400E1604U) /**< \brief (PIOE) PIO Disable Register */ +#define REG_PIOE_PSR (*(RoReg*)0x400E1608U) /**< \brief (PIOE) PIO Status Register */ +#define REG_PIOE_OER (*(WoReg*)0x400E1610U) /**< \brief (PIOE) Output Enable Register */ +#define REG_PIOE_ODR (*(WoReg*)0x400E1614U) /**< \brief (PIOE) Output Disable Register */ +#define REG_PIOE_OSR (*(RoReg*)0x400E1618U) /**< \brief (PIOE) Output Status Register */ +#define REG_PIOE_IFER (*(WoReg*)0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */ +#define REG_PIOE_IFDR (*(WoReg*)0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */ +#define REG_PIOE_IFSR (*(RoReg*)0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */ +#define REG_PIOE_SODR (*(WoReg*)0x400E1630U) /**< \brief (PIOE) Set Output Data Register */ +#define REG_PIOE_CODR (*(WoReg*)0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */ +#define REG_PIOE_ODSR (*(RwReg*)0x400E1638U) /**< \brief (PIOE) Output Data Status Register */ +#define REG_PIOE_PDSR (*(RoReg*)0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */ +#define REG_PIOE_IER (*(WoReg*)0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */ +#define REG_PIOE_IDR (*(WoReg*)0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */ +#define REG_PIOE_IMR (*(RoReg*)0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */ +#define REG_PIOE_ISR (*(RoReg*)0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */ +#define REG_PIOE_MDER (*(WoReg*)0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */ +#define REG_PIOE_MDDR (*(WoReg*)0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */ +#define REG_PIOE_MDSR (*(RoReg*)0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */ +#define REG_PIOE_PUDR (*(WoReg*)0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */ +#define REG_PIOE_PUER (*(WoReg*)0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */ +#define REG_PIOE_PUSR (*(RoReg*)0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */ +#define REG_PIOE_ABSR (*(RwReg*)0x400E1670U) /**< \brief (PIOE) Peripheral AB Select Register */ +#define REG_PIOE_SCIFSR (*(WoReg*)0x400E1680U) /**< \brief (PIOE) System Clock Glitch Input Filter Select Register */ +#define REG_PIOE_DIFSR (*(WoReg*)0x400E1684U) /**< \brief (PIOE) Debouncing Input Filter Select Register */ +#define REG_PIOE_IFDGSR (*(RoReg*)0x400E1688U) /**< \brief (PIOE) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOE_SCDR (*(RwReg*)0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */ +#define REG_PIOE_OWER (*(WoReg*)0x400E16A0U) /**< \brief (PIOE) Output Write Enable */ +#define REG_PIOE_OWDR (*(WoReg*)0x400E16A4U) /**< \brief (PIOE) Output Write Disable */ +#define REG_PIOE_OWSR (*(RoReg*)0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */ +#define REG_PIOE_AIMER (*(WoReg*)0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */ +#define REG_PIOE_AIMDR (*(WoReg*)0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disables Register */ +#define REG_PIOE_AIMMR (*(RoReg*)0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */ +#define REG_PIOE_ESR (*(WoReg*)0x400E16C0U) /**< \brief (PIOE) Edge Select Register */ +#define REG_PIOE_LSR (*(WoReg*)0x400E16C4U) /**< \brief (PIOE) Level Select Register */ +#define REG_PIOE_ELSR (*(RoReg*)0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */ +#define REG_PIOE_FELLSR (*(WoReg*)0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low Level Select Register */ +#define REG_PIOE_REHLSR (*(WoReg*)0x400E16D4U) /**< \brief (PIOE) Rising Edge/ High Level Select Register */ +#define REG_PIOE_FRLHSR (*(RoReg*)0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */ +#define REG_PIOE_LOCKSR (*(RoReg*)0x400E16E0U) /**< \brief (PIOE) Lock Status */ +#define REG_PIOE_WPMR (*(RwReg*)0x400E16E4U) /**< \brief (PIOE) Write Protect Mode Register */ +#define REG_PIOE_WPSR (*(RoReg*)0x400E16E8U) /**< \brief (PIOE) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_PIOE_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piof.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piof.h new file mode 100644 index 0000000..14c0053 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_piof.h @@ -0,0 +1,139 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_PIOF_INSTANCE_ +#define _SAM3XA_PIOF_INSTANCE_ + +/* ========== Register definition for PIOF peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PIOF_PER (0x400E1800U) /**< \brief (PIOF) PIO Enable Register */ +#define REG_PIOF_PDR (0x400E1804U) /**< \brief (PIOF) PIO Disable Register */ +#define REG_PIOF_PSR (0x400E1808U) /**< \brief (PIOF) PIO Status Register */ +#define REG_PIOF_OER (0x400E1810U) /**< \brief (PIOF) Output Enable Register */ +#define REG_PIOF_ODR (0x400E1814U) /**< \brief (PIOF) Output Disable Register */ +#define REG_PIOF_OSR (0x400E1818U) /**< \brief (PIOF) Output Status Register */ +#define REG_PIOF_IFER (0x400E1820U) /**< \brief (PIOF) Glitch Input Filter Enable Register */ +#define REG_PIOF_IFDR (0x400E1824U) /**< \brief (PIOF) Glitch Input Filter Disable Register */ +#define REG_PIOF_IFSR (0x400E1828U) /**< \brief (PIOF) Glitch Input Filter Status Register */ +#define REG_PIOF_SODR (0x400E1830U) /**< \brief (PIOF) Set Output Data Register */ +#define REG_PIOF_CODR (0x400E1834U) /**< \brief (PIOF) Clear Output Data Register */ +#define REG_PIOF_ODSR (0x400E1838U) /**< \brief (PIOF) Output Data Status Register */ +#define REG_PIOF_PDSR (0x400E183CU) /**< \brief (PIOF) Pin Data Status Register */ +#define REG_PIOF_IER (0x400E1840U) /**< \brief (PIOF) Interrupt Enable Register */ +#define REG_PIOF_IDR (0x400E1844U) /**< \brief (PIOF) Interrupt Disable Register */ +#define REG_PIOF_IMR (0x400E1848U) /**< \brief (PIOF) Interrupt Mask Register */ +#define REG_PIOF_ISR (0x400E184CU) /**< \brief (PIOF) Interrupt Status Register */ +#define REG_PIOF_MDER (0x400E1850U) /**< \brief (PIOF) Multi-driver Enable Register */ +#define REG_PIOF_MDDR (0x400E1854U) /**< \brief (PIOF) Multi-driver Disable Register */ +#define REG_PIOF_MDSR (0x400E1858U) /**< \brief (PIOF) Multi-driver Status Register */ +#define REG_PIOF_PUDR (0x400E1860U) /**< \brief (PIOF) Pull-up Disable Register */ +#define REG_PIOF_PUER (0x400E1864U) /**< \brief (PIOF) Pull-up Enable Register */ +#define REG_PIOF_PUSR (0x400E1868U) /**< \brief (PIOF) Pad Pull-up Status Register */ +#define REG_PIOF_ABSR (0x400E1870U) /**< \brief (PIOF) Peripheral AB Select Register */ +#define REG_PIOF_SCIFSR (0x400E1880U) /**< \brief (PIOF) System Clock Glitch Input Filter Select Register */ +#define REG_PIOF_DIFSR (0x400E1884U) /**< \brief (PIOF) Debouncing Input Filter Select Register */ +#define REG_PIOF_IFDGSR (0x400E1888U) /**< \brief (PIOF) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOF_SCDR (0x400E188CU) /**< \brief (PIOF) Slow Clock Divider Debouncing Register */ +#define REG_PIOF_OWER (0x400E18A0U) /**< \brief (PIOF) Output Write Enable */ +#define REG_PIOF_OWDR (0x400E18A4U) /**< \brief (PIOF) Output Write Disable */ +#define REG_PIOF_OWSR (0x400E18A8U) /**< \brief (PIOF) Output Write Status Register */ +#define REG_PIOF_AIMER (0x400E18B0U) /**< \brief (PIOF) Additional Interrupt Modes Enable Register */ +#define REG_PIOF_AIMDR (0x400E18B4U) /**< \brief (PIOF) Additional Interrupt Modes Disables Register */ +#define REG_PIOF_AIMMR (0x400E18B8U) /**< \brief (PIOF) Additional Interrupt Modes Mask Register */ +#define REG_PIOF_ESR (0x400E18C0U) /**< \brief (PIOF) Edge Select Register */ +#define REG_PIOF_LSR (0x400E18C4U) /**< \brief (PIOF) Level Select Register */ +#define REG_PIOF_ELSR (0x400E18C8U) /**< \brief (PIOF) Edge/Level Status Register */ +#define REG_PIOF_FELLSR (0x400E18D0U) /**< \brief (PIOF) Falling Edge/Low Level Select Register */ +#define REG_PIOF_REHLSR (0x400E18D4U) /**< \brief (PIOF) Rising Edge/ High Level Select Register */ +#define REG_PIOF_FRLHSR (0x400E18D8U) /**< \brief (PIOF) Fall/Rise - Low/High Status Register */ +#define REG_PIOF_LOCKSR (0x400E18E0U) /**< \brief (PIOF) Lock Status */ +#define REG_PIOF_WPMR (0x400E18E4U) /**< \brief (PIOF) Write Protect Mode Register */ +#define REG_PIOF_WPSR (0x400E18E8U) /**< \brief (PIOF) Write Protect Status Register */ +#else +#define REG_PIOF_PER (*(WoReg*)0x400E1800U) /**< \brief (PIOF) PIO Enable Register */ +#define REG_PIOF_PDR (*(WoReg*)0x400E1804U) /**< \brief (PIOF) PIO Disable Register */ +#define REG_PIOF_PSR (*(RoReg*)0x400E1808U) /**< \brief (PIOF) PIO Status Register */ +#define REG_PIOF_OER (*(WoReg*)0x400E1810U) /**< \brief (PIOF) Output Enable Register */ +#define REG_PIOF_ODR (*(WoReg*)0x400E1814U) /**< \brief (PIOF) Output Disable Register */ +#define REG_PIOF_OSR (*(RoReg*)0x400E1818U) /**< \brief (PIOF) Output Status Register */ +#define REG_PIOF_IFER (*(WoReg*)0x400E1820U) /**< \brief (PIOF) Glitch Input Filter Enable Register */ +#define REG_PIOF_IFDR (*(WoReg*)0x400E1824U) /**< \brief (PIOF) Glitch Input Filter Disable Register */ +#define REG_PIOF_IFSR (*(RoReg*)0x400E1828U) /**< \brief (PIOF) Glitch Input Filter Status Register */ +#define REG_PIOF_SODR (*(WoReg*)0x400E1830U) /**< \brief (PIOF) Set Output Data Register */ +#define REG_PIOF_CODR (*(WoReg*)0x400E1834U) /**< \brief (PIOF) Clear Output Data Register */ +#define REG_PIOF_ODSR (*(RwReg*)0x400E1838U) /**< \brief (PIOF) Output Data Status Register */ +#define REG_PIOF_PDSR (*(RoReg*)0x400E183CU) /**< \brief (PIOF) Pin Data Status Register */ +#define REG_PIOF_IER (*(WoReg*)0x400E1840U) /**< \brief (PIOF) Interrupt Enable Register */ +#define REG_PIOF_IDR (*(WoReg*)0x400E1844U) /**< \brief (PIOF) Interrupt Disable Register */ +#define REG_PIOF_IMR (*(RoReg*)0x400E1848U) /**< \brief (PIOF) Interrupt Mask Register */ +#define REG_PIOF_ISR (*(RoReg*)0x400E184CU) /**< \brief (PIOF) Interrupt Status Register */ +#define REG_PIOF_MDER (*(WoReg*)0x400E1850U) /**< \brief (PIOF) Multi-driver Enable Register */ +#define REG_PIOF_MDDR (*(WoReg*)0x400E1854U) /**< \brief (PIOF) Multi-driver Disable Register */ +#define REG_PIOF_MDSR (*(RoReg*)0x400E1858U) /**< \brief (PIOF) Multi-driver Status Register */ +#define REG_PIOF_PUDR (*(WoReg*)0x400E1860U) /**< \brief (PIOF) Pull-up Disable Register */ +#define REG_PIOF_PUER (*(WoReg*)0x400E1864U) /**< \brief (PIOF) Pull-up Enable Register */ +#define REG_PIOF_PUSR (*(RoReg*)0x400E1868U) /**< \brief (PIOF) Pad Pull-up Status Register */ +#define REG_PIOF_ABSR (*(RwReg*)0x400E1870U) /**< \brief (PIOF) Peripheral AB Select Register */ +#define REG_PIOF_SCIFSR (*(WoReg*)0x400E1880U) /**< \brief (PIOF) System Clock Glitch Input Filter Select Register */ +#define REG_PIOF_DIFSR (*(WoReg*)0x400E1884U) /**< \brief (PIOF) Debouncing Input Filter Select Register */ +#define REG_PIOF_IFDGSR (*(RoReg*)0x400E1888U) /**< \brief (PIOF) Glitch or Debouncing Input Filter Clock Selection Status Register */ +#define REG_PIOF_SCDR (*(RwReg*)0x400E188CU) /**< \brief (PIOF) Slow Clock Divider Debouncing Register */ +#define REG_PIOF_OWER (*(WoReg*)0x400E18A0U) /**< \brief (PIOF) Output Write Enable */ +#define REG_PIOF_OWDR (*(WoReg*)0x400E18A4U) /**< \brief (PIOF) Output Write Disable */ +#define REG_PIOF_OWSR (*(RoReg*)0x400E18A8U) /**< \brief (PIOF) Output Write Status Register */ +#define REG_PIOF_AIMER (*(WoReg*)0x400E18B0U) /**< \brief (PIOF) Additional Interrupt Modes Enable Register */ +#define REG_PIOF_AIMDR (*(WoReg*)0x400E18B4U) /**< \brief (PIOF) Additional Interrupt Modes Disables Register */ +#define REG_PIOF_AIMMR (*(RoReg*)0x400E18B8U) /**< \brief (PIOF) Additional Interrupt Modes Mask Register */ +#define REG_PIOF_ESR (*(WoReg*)0x400E18C0U) /**< \brief (PIOF) Edge Select Register */ +#define REG_PIOF_LSR (*(WoReg*)0x400E18C4U) /**< \brief (PIOF) Level Select Register */ +#define REG_PIOF_ELSR (*(RoReg*)0x400E18C8U) /**< \brief (PIOF) Edge/Level Status Register */ +#define REG_PIOF_FELLSR (*(WoReg*)0x400E18D0U) /**< \brief (PIOF) Falling Edge/Low Level Select Register */ +#define REG_PIOF_REHLSR (*(WoReg*)0x400E18D4U) /**< \brief (PIOF) Rising Edge/ High Level Select Register */ +#define REG_PIOF_FRLHSR (*(RoReg*)0x400E18D8U) /**< \brief (PIOF) Fall/Rise - Low/High Status Register */ +#define REG_PIOF_LOCKSR (*(RoReg*)0x400E18E0U) /**< \brief (PIOF) Lock Status */ +#define REG_PIOF_WPMR (*(RwReg*)0x400E18E4U) /**< \brief (PIOF) Write Protect Mode Register */ +#define REG_PIOF_WPSR (*(RoReg*)0x400E18E8U) /**< \brief (PIOF) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_PIOF_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h new file mode 100644 index 0000000..7cfa537 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pmc.h @@ -0,0 +1,105 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_PMC_INSTANCE_ +#define _SAM3XA_PMC_INSTANCE_ + +/* ========== Register definition for PMC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PMC_SCER (0x400E0600U) /**< \brief (PMC) System Clock Enable Register */ +#define REG_PMC_SCDR (0x400E0604U) /**< \brief (PMC) System Clock Disable Register */ +#define REG_PMC_SCSR (0x400E0608U) /**< \brief (PMC) System Clock Status Register */ +#define REG_PMC_PCER0 (0x400E0610U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ +#define REG_PMC_PCDR0 (0x400E0614U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ +#define REG_PMC_PCSR0 (0x400E0618U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ +#define REG_CKGR_UCKR (0x400E061CU) /**< \brief (PMC) UTMI Clock Register */ +#define REG_CKGR_MOR (0x400E0620U) /**< \brief (PMC) Main Oscillator Register */ +#define REG_CKGR_MCFR (0x400E0624U) /**< \brief (PMC) Main Clock Frequency Register */ +#define REG_CKGR_PLLAR (0x400E0628U) /**< \brief (PMC) PLLA Register */ +#define REG_PMC_MCKR (0x400E0630U) /**< \brief (PMC) Master Clock Register */ +#define REG_PMC_USB (0x400E0638U) /**< \brief (PMC) USB Clock Register */ +#define REG_PMC_PCK (0x400E0640U) /**< \brief (PMC) Programmable Clock 0 Register */ +#define REG_PMC_IER (0x400E0660U) /**< \brief (PMC) Interrupt Enable Register */ +#define REG_PMC_IDR (0x400E0664U) /**< \brief (PMC) Interrupt Disable Register */ +#define REG_PMC_SR (0x400E0668U) /**< \brief (PMC) Status Register */ +#define REG_PMC_IMR (0x400E066CU) /**< \brief (PMC) Interrupt Mask Register */ +#define REG_PMC_FSMR (0x400E0670U) /**< \brief (PMC) Fast Startup Mode Register */ +#define REG_PMC_FSPR (0x400E0674U) /**< \brief (PMC) Fast Startup Polarity Register */ +#define REG_PMC_FOCR (0x400E0678U) /**< \brief (PMC) Fault Output Clear Register */ +#define REG_PMC_WPMR (0x400E06E4U) /**< \brief (PMC) Write Protect Mode Register */ +#define REG_PMC_WPSR (0x400E06E8U) /**< \brief (PMC) Write Protect Status Register */ +#define REG_PMC_PCER1 (0x400E0700U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ +#define REG_PMC_PCDR1 (0x400E0704U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ +#define REG_PMC_PCSR1 (0x400E0708U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ +#define REG_PMC_PCR (0x400E070CU) /**< \brief (PMC) Peripheral Control Register */ +#else +#define REG_PMC_SCER (*(WoReg*)0x400E0600U) /**< \brief (PMC) System Clock Enable Register */ +#define REG_PMC_SCDR (*(WoReg*)0x400E0604U) /**< \brief (PMC) System Clock Disable Register */ +#define REG_PMC_SCSR (*(RoReg*)0x400E0608U) /**< \brief (PMC) System Clock Status Register */ +#define REG_PMC_PCER0 (*(WoReg*)0x400E0610U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ +#define REG_PMC_PCDR0 (*(WoReg*)0x400E0614U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ +#define REG_PMC_PCSR0 (*(RoReg*)0x400E0618U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ +#define REG_CKGR_UCKR (*(RwReg*)0x400E061CU) /**< \brief (PMC) UTMI Clock Register */ +#define REG_CKGR_MOR (*(RwReg*)0x400E0620U) /**< \brief (PMC) Main Oscillator Register */ +#define REG_CKGR_MCFR (*(RoReg*)0x400E0624U) /**< \brief (PMC) Main Clock Frequency Register */ +#define REG_CKGR_PLLAR (*(RwReg*)0x400E0628U) /**< \brief (PMC) PLLA Register */ +#define REG_PMC_MCKR (*(RwReg*)0x400E0630U) /**< \brief (PMC) Master Clock Register */ +#define REG_PMC_USB (*(RwReg*)0x400E0638U) /**< \brief (PMC) USB Clock Register */ +#define REG_PMC_PCK (*(RwReg*)0x400E0640U) /**< \brief (PMC) Programmable Clock 0 Register */ +#define REG_PMC_IER (*(WoReg*)0x400E0660U) /**< \brief (PMC) Interrupt Enable Register */ +#define REG_PMC_IDR (*(WoReg*)0x400E0664U) /**< \brief (PMC) Interrupt Disable Register */ +#define REG_PMC_SR (*(RoReg*)0x400E0668U) /**< \brief (PMC) Status Register */ +#define REG_PMC_IMR (*(RoReg*)0x400E066CU) /**< \brief (PMC) Interrupt Mask Register */ +#define REG_PMC_FSMR (*(RwReg*)0x400E0670U) /**< \brief (PMC) Fast Startup Mode Register */ +#define REG_PMC_FSPR (*(RwReg*)0x400E0674U) /**< \brief (PMC) Fast Startup Polarity Register */ +#define REG_PMC_FOCR (*(WoReg*)0x400E0678U) /**< \brief (PMC) Fault Output Clear Register */ +#define REG_PMC_WPMR (*(RwReg*)0x400E06E4U) /**< \brief (PMC) Write Protect Mode Register */ +#define REG_PMC_WPSR (*(RoReg*)0x400E06E8U) /**< \brief (PMC) Write Protect Status Register */ +#define REG_PMC_PCER1 (*(WoReg*)0x400E0700U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ +#define REG_PMC_PCDR1 (*(WoReg*)0x400E0704U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ +#define REG_PMC_PCSR1 (*(RoReg*)0x400E0708U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ +#define REG_PMC_PCR (*(RwReg*)0x400E070CU) /**< \brief (PMC) Peripheral Control Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_PMC_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h new file mode 100644 index 0000000..e8d5f85 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_pwm.h @@ -0,0 +1,321 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_PWM_INSTANCE_ +#define _SAM3XA_PWM_INSTANCE_ + +/* ========== Register definition for PWM peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PWM_CLK (0x40094000U) /**< \brief (PWM) PWM Clock Register */ +#define REG_PWM_ENA (0x40094004U) /**< \brief (PWM) PWM Enable Register */ +#define REG_PWM_DIS (0x40094008U) /**< \brief (PWM) PWM Disable Register */ +#define REG_PWM_SR (0x4009400CU) /**< \brief (PWM) PWM Status Register */ +#define REG_PWM_IER1 (0x40094010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */ +#define REG_PWM_IDR1 (0x40094014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */ +#define REG_PWM_IMR1 (0x40094018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */ +#define REG_PWM_ISR1 (0x4009401CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */ +#define REG_PWM_SCM (0x40094020U) /**< \brief (PWM) PWM Sync Channels Mode Register */ +#define REG_PWM_SCUC (0x40094028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */ +#define REG_PWM_SCUP (0x4009402CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */ +#define REG_PWM_SCUPUPD (0x40094030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */ +#define REG_PWM_IER2 (0x40094034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */ +#define REG_PWM_IDR2 (0x40094038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */ +#define REG_PWM_IMR2 (0x4009403CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */ +#define REG_PWM_ISR2 (0x40094040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */ +#define REG_PWM_OOV (0x40094044U) /**< \brief (PWM) PWM Output Override Value Register */ +#define REG_PWM_OS (0x40094048U) /**< \brief (PWM) PWM Output Selection Register */ +#define REG_PWM_OSS (0x4009404CU) /**< \brief (PWM) PWM Output Selection Set Register */ +#define REG_PWM_OSC (0x40094050U) /**< \brief (PWM) PWM Output Selection Clear Register */ +#define REG_PWM_OSSUPD (0x40094054U) /**< \brief (PWM) PWM Output Selection Set Update Register */ +#define REG_PWM_OSCUPD (0x40094058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */ +#define REG_PWM_FMR (0x4009405CU) /**< \brief (PWM) PWM Fault Mode Register */ +#define REG_PWM_FSR (0x40094060U) /**< \brief (PWM) PWM Fault Status Register */ +#define REG_PWM_FCR (0x40094064U) /**< \brief (PWM) PWM Fault Clear Register */ +#define REG_PWM_FPV (0x40094068U) /**< \brief (PWM) PWM Fault Protection Value Register */ +#define REG_PWM_FPE1 (0x4009406CU) /**< \brief (PWM) PWM Fault Protection Enable Register 1 */ +#define REG_PWM_FPE2 (0x40094070U) /**< \brief (PWM) PWM Fault Protection Enable Register 2 */ +#define REG_PWM_ELMR (0x4009407CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */ +#define REG_PWM_SMMR (0x400940B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */ +#define REG_PWM_WPCR (0x400940E4U) /**< \brief (PWM) PWM Write Protect Control Register */ +#define REG_PWM_WPSR (0x400940E8U) /**< \brief (PWM) PWM Write Protect Status Register */ +#define REG_PWM_TPR (0x40094108U) /**< \brief (PWM) Transmit Pointer Register */ +#define REG_PWM_TCR (0x4009410CU) /**< \brief (PWM) Transmit Counter Register */ +#define REG_PWM_TNPR (0x40094118U) /**< \brief (PWM) Transmit Next Pointer Register */ +#define REG_PWM_TNCR (0x4009411CU) /**< \brief (PWM) Transmit Next Counter Register */ +#define REG_PWM_PTCR (0x40094120U) /**< \brief (PWM) Transfer Control Register */ +#define REG_PWM_PTSR (0x40094124U) /**< \brief (PWM) Transfer Status Register */ +#define REG_PWM_CMPV0 (0x40094130U) /**< \brief (PWM) PWM Comparison 0 Value Register */ +#define REG_PWM_CMPVUPD0 (0x40094134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */ +#define REG_PWM_CMPM0 (0x40094138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */ +#define REG_PWM_CMPMUPD0 (0x4009413CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */ +#define REG_PWM_CMPV1 (0x40094140U) /**< \brief (PWM) PWM Comparison 1 Value Register */ +#define REG_PWM_CMPVUPD1 (0x40094144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */ +#define REG_PWM_CMPM1 (0x40094148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */ +#define REG_PWM_CMPMUPD1 (0x4009414CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */ +#define REG_PWM_CMPV2 (0x40094150U) /**< \brief (PWM) PWM Comparison 2 Value Register */ +#define REG_PWM_CMPVUPD2 (0x40094154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */ +#define REG_PWM_CMPM2 (0x40094158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */ +#define REG_PWM_CMPMUPD2 (0x4009415CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */ +#define REG_PWM_CMPV3 (0x40094160U) /**< \brief (PWM) PWM Comparison 3 Value Register */ +#define REG_PWM_CMPVUPD3 (0x40094164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */ +#define REG_PWM_CMPM3 (0x40094168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */ +#define REG_PWM_CMPMUPD3 (0x4009416CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */ +#define REG_PWM_CMPV4 (0x40094170U) /**< \brief (PWM) PWM Comparison 4 Value Register */ +#define REG_PWM_CMPVUPD4 (0x40094174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */ +#define REG_PWM_CMPM4 (0x40094178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */ +#define REG_PWM_CMPMUPD4 (0x4009417CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */ +#define REG_PWM_CMPV5 (0x40094180U) /**< \brief (PWM) PWM Comparison 5 Value Register */ +#define REG_PWM_CMPVUPD5 (0x40094184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */ +#define REG_PWM_CMPM5 (0x40094188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */ +#define REG_PWM_CMPMUPD5 (0x4009418CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */ +#define REG_PWM_CMPV6 (0x40094190U) /**< \brief (PWM) PWM Comparison 6 Value Register */ +#define REG_PWM_CMPVUPD6 (0x40094194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */ +#define REG_PWM_CMPM6 (0x40094198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */ +#define REG_PWM_CMPMUPD6 (0x4009419CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */ +#define REG_PWM_CMPV7 (0x400941A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */ +#define REG_PWM_CMPVUPD7 (0x400941A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */ +#define REG_PWM_CMPM7 (0x400941A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */ +#define REG_PWM_CMPMUPD7 (0x400941ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */ +#define REG_PWM_CMR0 (0x40094200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */ +#define REG_PWM_CDTY0 (0x40094204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */ +#define REG_PWM_CDTYUPD0 (0x40094208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */ +#define REG_PWM_CPRD0 (0x4009420CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */ +#define REG_PWM_CPRDUPD0 (0x40094210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */ +#define REG_PWM_CCNT0 (0x40094214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */ +#define REG_PWM_DT0 (0x40094218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */ +#define REG_PWM_DTUPD0 (0x4009421CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */ +#define REG_PWM_CMR1 (0x40094220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */ +#define REG_PWM_CDTY1 (0x40094224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */ +#define REG_PWM_CDTYUPD1 (0x40094228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */ +#define REG_PWM_CPRD1 (0x4009422CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */ +#define REG_PWM_CPRDUPD1 (0x40094230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */ +#define REG_PWM_CCNT1 (0x40094234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */ +#define REG_PWM_DT1 (0x40094238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */ +#define REG_PWM_DTUPD1 (0x4009423CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */ +#define REG_PWM_CMR2 (0x40094240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */ +#define REG_PWM_CDTY2 (0x40094244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */ +#define REG_PWM_CDTYUPD2 (0x40094248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */ +#define REG_PWM_CPRD2 (0x4009424CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */ +#define REG_PWM_CPRDUPD2 (0x40094250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */ +#define REG_PWM_CCNT2 (0x40094254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */ +#define REG_PWM_DT2 (0x40094258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */ +#define REG_PWM_DTUPD2 (0x4009425CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */ +#define REG_PWM_CMR3 (0x40094260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */ +#define REG_PWM_CDTY3 (0x40094264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */ +#define REG_PWM_CDTYUPD3 (0x40094268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */ +#define REG_PWM_CPRD3 (0x4009426CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */ +#define REG_PWM_CPRDUPD3 (0x40094270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */ +#define REG_PWM_CCNT3 (0x40094274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */ +#define REG_PWM_DT3 (0x40094278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */ +#define REG_PWM_DTUPD3 (0x4009427CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */ +#define REG_PWM_CMR4 (0x40094280U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 4) */ +#define REG_PWM_CDTY4 (0x40094284U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 4) */ +#define REG_PWM_CDTYUPD4 (0x40094288U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 4) */ +#define REG_PWM_CPRD4 (0x4009428CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 4) */ +#define REG_PWM_CPRDUPD4 (0x40094290U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 4) */ +#define REG_PWM_CCNT4 (0x40094294U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 4) */ +#define REG_PWM_DT4 (0x40094298U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 4) */ +#define REG_PWM_DTUPD4 (0x4009429CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 4) */ +#define REG_PWM_CMR5 (0x400942A0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 5) */ +#define REG_PWM_CDTY5 (0x400942A4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 5) */ +#define REG_PWM_CDTYUPD5 (0x400942A8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 5) */ +#define REG_PWM_CPRD5 (0x400942ACU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 5) */ +#define REG_PWM_CPRDUPD5 (0x400942B0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 5) */ +#define REG_PWM_CCNT5 (0x400942B4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 5) */ +#define REG_PWM_DT5 (0x400942B8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 5) */ +#define REG_PWM_DTUPD5 (0x400942BCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 5) */ +#define REG_PWM_CMR6 (0x400942C0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 6) */ +#define REG_PWM_CDTY6 (0x400942C4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 6) */ +#define REG_PWM_CDTYUPD6 (0x400942C8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 6) */ +#define REG_PWM_CPRD6 (0x400942CCU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 6) */ +#define REG_PWM_CPRDUPD6 (0x400942D0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 6) */ +#define REG_PWM_CCNT6 (0x400942D4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 6) */ +#define REG_PWM_DT6 (0x400942D8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 6) */ +#define REG_PWM_DTUPD6 (0x400942DCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 6) */ +#define REG_PWM_CMR7 (0x400942E0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 7) */ +#define REG_PWM_CDTY7 (0x400942E4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 7) */ +#define REG_PWM_CDTYUPD7 (0x400942E8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 7) */ +#define REG_PWM_CPRD7 (0x400942ECU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 7) */ +#define REG_PWM_CPRDUPD7 (0x400942F0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 7) */ +#define REG_PWM_CCNT7 (0x400942F4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 7) */ +#define REG_PWM_DT7 (0x400942F8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 7) */ +#define REG_PWM_DTUPD7 (0x400942FCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 7) */ +#else +#define REG_PWM_CLK (*(RwReg*)0x40094000U) /**< \brief (PWM) PWM Clock Register */ +#define REG_PWM_ENA (*(WoReg*)0x40094004U) /**< \brief (PWM) PWM Enable Register */ +#define REG_PWM_DIS (*(WoReg*)0x40094008U) /**< \brief (PWM) PWM Disable Register */ +#define REG_PWM_SR (*(RoReg*)0x4009400CU) /**< \brief (PWM) PWM Status Register */ +#define REG_PWM_IER1 (*(WoReg*)0x40094010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */ +#define REG_PWM_IDR1 (*(WoReg*)0x40094014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */ +#define REG_PWM_IMR1 (*(RoReg*)0x40094018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */ +#define REG_PWM_ISR1 (*(RoReg*)0x4009401CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */ +#define REG_PWM_SCM (*(RwReg*)0x40094020U) /**< \brief (PWM) PWM Sync Channels Mode Register */ +#define REG_PWM_SCUC (*(RwReg*)0x40094028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */ +#define REG_PWM_SCUP (*(RwReg*)0x4009402CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */ +#define REG_PWM_SCUPUPD (*(WoReg*)0x40094030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */ +#define REG_PWM_IER2 (*(WoReg*)0x40094034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */ +#define REG_PWM_IDR2 (*(WoReg*)0x40094038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */ +#define REG_PWM_IMR2 (*(RoReg*)0x4009403CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */ +#define REG_PWM_ISR2 (*(RoReg*)0x40094040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */ +#define REG_PWM_OOV (*(RwReg*)0x40094044U) /**< \brief (PWM) PWM Output Override Value Register */ +#define REG_PWM_OS (*(RwReg*)0x40094048U) /**< \brief (PWM) PWM Output Selection Register */ +#define REG_PWM_OSS (*(WoReg*)0x4009404CU) /**< \brief (PWM) PWM Output Selection Set Register */ +#define REG_PWM_OSC (*(WoReg*)0x40094050U) /**< \brief (PWM) PWM Output Selection Clear Register */ +#define REG_PWM_OSSUPD (*(WoReg*)0x40094054U) /**< \brief (PWM) PWM Output Selection Set Update Register */ +#define REG_PWM_OSCUPD (*(WoReg*)0x40094058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */ +#define REG_PWM_FMR (*(RwReg*)0x4009405CU) /**< \brief (PWM) PWM Fault Mode Register */ +#define REG_PWM_FSR (*(RoReg*)0x40094060U) /**< \brief (PWM) PWM Fault Status Register */ +#define REG_PWM_FCR (*(WoReg*)0x40094064U) /**< \brief (PWM) PWM Fault Clear Register */ +#define REG_PWM_FPV (*(RwReg*)0x40094068U) /**< \brief (PWM) PWM Fault Protection Value Register */ +#define REG_PWM_FPE1 (*(RwReg*)0x4009406CU) /**< \brief (PWM) PWM Fault Protection Enable Register 1 */ +#define REG_PWM_FPE2 (*(RwReg*)0x40094070U) /**< \brief (PWM) PWM Fault Protection Enable Register 2 */ +#define REG_PWM_ELMR (*(RwReg*)0x4009407CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */ +#define REG_PWM_SMMR (*(RwReg*)0x400940B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */ +#define REG_PWM_WPCR (*(WoReg*)0x400940E4U) /**< \brief (PWM) PWM Write Protect Control Register */ +#define REG_PWM_WPSR (*(RoReg*)0x400940E8U) /**< \brief (PWM) PWM Write Protect Status Register */ +#define REG_PWM_TPR (*(RwReg*)0x40094108U) /**< \brief (PWM) Transmit Pointer Register */ +#define REG_PWM_TCR (*(RwReg*)0x4009410CU) /**< \brief (PWM) Transmit Counter Register */ +#define REG_PWM_TNPR (*(RwReg*)0x40094118U) /**< \brief (PWM) Transmit Next Pointer Register */ +#define REG_PWM_TNCR (*(RwReg*)0x4009411CU) /**< \brief (PWM) Transmit Next Counter Register */ +#define REG_PWM_PTCR (*(WoReg*)0x40094120U) /**< \brief (PWM) Transfer Control Register */ +#define REG_PWM_PTSR (*(RoReg*)0x40094124U) /**< \brief (PWM) Transfer Status Register */ +#define REG_PWM_CMPV0 (*(RwReg*)0x40094130U) /**< \brief (PWM) PWM Comparison 0 Value Register */ +#define REG_PWM_CMPVUPD0 (*(WoReg*)0x40094134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */ +#define REG_PWM_CMPM0 (*(RwReg*)0x40094138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */ +#define REG_PWM_CMPMUPD0 (*(WoReg*)0x4009413CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */ +#define REG_PWM_CMPV1 (*(RwReg*)0x40094140U) /**< \brief (PWM) PWM Comparison 1 Value Register */ +#define REG_PWM_CMPVUPD1 (*(WoReg*)0x40094144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */ +#define REG_PWM_CMPM1 (*(RwReg*)0x40094148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */ +#define REG_PWM_CMPMUPD1 (*(WoReg*)0x4009414CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */ +#define REG_PWM_CMPV2 (*(RwReg*)0x40094150U) /**< \brief (PWM) PWM Comparison 2 Value Register */ +#define REG_PWM_CMPVUPD2 (*(WoReg*)0x40094154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */ +#define REG_PWM_CMPM2 (*(RwReg*)0x40094158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */ +#define REG_PWM_CMPMUPD2 (*(WoReg*)0x4009415CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */ +#define REG_PWM_CMPV3 (*(RwReg*)0x40094160U) /**< \brief (PWM) PWM Comparison 3 Value Register */ +#define REG_PWM_CMPVUPD3 (*(WoReg*)0x40094164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */ +#define REG_PWM_CMPM3 (*(RwReg*)0x40094168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */ +#define REG_PWM_CMPMUPD3 (*(WoReg*)0x4009416CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */ +#define REG_PWM_CMPV4 (*(RwReg*)0x40094170U) /**< \brief (PWM) PWM Comparison 4 Value Register */ +#define REG_PWM_CMPVUPD4 (*(WoReg*)0x40094174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */ +#define REG_PWM_CMPM4 (*(RwReg*)0x40094178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */ +#define REG_PWM_CMPMUPD4 (*(WoReg*)0x4009417CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */ +#define REG_PWM_CMPV5 (*(RwReg*)0x40094180U) /**< \brief (PWM) PWM Comparison 5 Value Register */ +#define REG_PWM_CMPVUPD5 (*(WoReg*)0x40094184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */ +#define REG_PWM_CMPM5 (*(RwReg*)0x40094188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */ +#define REG_PWM_CMPMUPD5 (*(WoReg*)0x4009418CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */ +#define REG_PWM_CMPV6 (*(RwReg*)0x40094190U) /**< \brief (PWM) PWM Comparison 6 Value Register */ +#define REG_PWM_CMPVUPD6 (*(WoReg*)0x40094194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */ +#define REG_PWM_CMPM6 (*(RwReg*)0x40094198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */ +#define REG_PWM_CMPMUPD6 (*(WoReg*)0x4009419CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */ +#define REG_PWM_CMPV7 (*(RwReg*)0x400941A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */ +#define REG_PWM_CMPVUPD7 (*(WoReg*)0x400941A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */ +#define REG_PWM_CMPM7 (*(RwReg*)0x400941A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */ +#define REG_PWM_CMPMUPD7 (*(WoReg*)0x400941ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */ +#define REG_PWM_CMR0 (*(RwReg*)0x40094200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */ +#define REG_PWM_CDTY0 (*(RwReg*)0x40094204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */ +#define REG_PWM_CDTYUPD0 (*(WoReg*)0x40094208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */ +#define REG_PWM_CPRD0 (*(RwReg*)0x4009420CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */ +#define REG_PWM_CPRDUPD0 (*(WoReg*)0x40094210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */ +#define REG_PWM_CCNT0 (*(RoReg*)0x40094214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */ +#define REG_PWM_DT0 (*(RwReg*)0x40094218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */ +#define REG_PWM_DTUPD0 (*(WoReg*)0x4009421CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */ +#define REG_PWM_CMR1 (*(RwReg*)0x40094220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */ +#define REG_PWM_CDTY1 (*(RwReg*)0x40094224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */ +#define REG_PWM_CDTYUPD1 (*(WoReg*)0x40094228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */ +#define REG_PWM_CPRD1 (*(RwReg*)0x4009422CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */ +#define REG_PWM_CPRDUPD1 (*(WoReg*)0x40094230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */ +#define REG_PWM_CCNT1 (*(RoReg*)0x40094234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */ +#define REG_PWM_DT1 (*(RwReg*)0x40094238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */ +#define REG_PWM_DTUPD1 (*(WoReg*)0x4009423CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */ +#define REG_PWM_CMR2 (*(RwReg*)0x40094240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */ +#define REG_PWM_CDTY2 (*(RwReg*)0x40094244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */ +#define REG_PWM_CDTYUPD2 (*(WoReg*)0x40094248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */ +#define REG_PWM_CPRD2 (*(RwReg*)0x4009424CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */ +#define REG_PWM_CPRDUPD2 (*(WoReg*)0x40094250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */ +#define REG_PWM_CCNT2 (*(RoReg*)0x40094254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */ +#define REG_PWM_DT2 (*(RwReg*)0x40094258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */ +#define REG_PWM_DTUPD2 (*(WoReg*)0x4009425CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */ +#define REG_PWM_CMR3 (*(RwReg*)0x40094260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */ +#define REG_PWM_CDTY3 (*(RwReg*)0x40094264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */ +#define REG_PWM_CDTYUPD3 (*(WoReg*)0x40094268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */ +#define REG_PWM_CPRD3 (*(RwReg*)0x4009426CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */ +#define REG_PWM_CPRDUPD3 (*(WoReg*)0x40094270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */ +#define REG_PWM_CCNT3 (*(RoReg*)0x40094274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */ +#define REG_PWM_DT3 (*(RwReg*)0x40094278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */ +#define REG_PWM_DTUPD3 (*(WoReg*)0x4009427CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */ +#define REG_PWM_CMR4 (*(RwReg*)0x40094280U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 4) */ +#define REG_PWM_CDTY4 (*(RwReg*)0x40094284U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 4) */ +#define REG_PWM_CDTYUPD4 (*(WoReg*)0x40094288U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 4) */ +#define REG_PWM_CPRD4 (*(RwReg*)0x4009428CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 4) */ +#define REG_PWM_CPRDUPD4 (*(WoReg*)0x40094290U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 4) */ +#define REG_PWM_CCNT4 (*(RoReg*)0x40094294U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 4) */ +#define REG_PWM_DT4 (*(RwReg*)0x40094298U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 4) */ +#define REG_PWM_DTUPD4 (*(WoReg*)0x4009429CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 4) */ +#define REG_PWM_CMR5 (*(RwReg*)0x400942A0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 5) */ +#define REG_PWM_CDTY5 (*(RwReg*)0x400942A4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 5) */ +#define REG_PWM_CDTYUPD5 (*(WoReg*)0x400942A8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 5) */ +#define REG_PWM_CPRD5 (*(RwReg*)0x400942ACU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 5) */ +#define REG_PWM_CPRDUPD5 (*(WoReg*)0x400942B0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 5) */ +#define REG_PWM_CCNT5 (*(RoReg*)0x400942B4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 5) */ +#define REG_PWM_DT5 (*(RwReg*)0x400942B8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 5) */ +#define REG_PWM_DTUPD5 (*(WoReg*)0x400942BCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 5) */ +#define REG_PWM_CMR6 (*(RwReg*)0x400942C0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 6) */ +#define REG_PWM_CDTY6 (*(RwReg*)0x400942C4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 6) */ +#define REG_PWM_CDTYUPD6 (*(WoReg*)0x400942C8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 6) */ +#define REG_PWM_CPRD6 (*(RwReg*)0x400942CCU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 6) */ +#define REG_PWM_CPRDUPD6 (*(WoReg*)0x400942D0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 6) */ +#define REG_PWM_CCNT6 (*(RoReg*)0x400942D4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 6) */ +#define REG_PWM_DT6 (*(RwReg*)0x400942D8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 6) */ +#define REG_PWM_DTUPD6 (*(WoReg*)0x400942DCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 6) */ +#define REG_PWM_CMR7 (*(RwReg*)0x400942E0U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 7) */ +#define REG_PWM_CDTY7 (*(RwReg*)0x400942E4U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 7) */ +#define REG_PWM_CDTYUPD7 (*(WoReg*)0x400942E8U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 7) */ +#define REG_PWM_CPRD7 (*(RwReg*)0x400942ECU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 7) */ +#define REG_PWM_CPRDUPD7 (*(WoReg*)0x400942F0U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 7) */ +#define REG_PWM_CCNT7 (*(RoReg*)0x400942F4U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 7) */ +#define REG_PWM_DT7 (*(RwReg*)0x400942F8U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 7) */ +#define REG_PWM_DTUPD7 (*(WoReg*)0x400942FCU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 7) */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_PWM_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h new file mode 100644 index 0000000..f2cc332 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rstc.h @@ -0,0 +1,59 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_RSTC_INSTANCE_ +#define _SAM3XA_RSTC_INSTANCE_ + +/* ========== Register definition for RSTC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_RSTC_CR (0x400E1A00U) /**< \brief (RSTC) Control Register */ +#define REG_RSTC_SR (0x400E1A04U) /**< \brief (RSTC) Status Register */ +#define REG_RSTC_MR (0x400E1A08U) /**< \brief (RSTC) Mode Register */ +#else +#define REG_RSTC_CR (*(WoReg*)0x400E1A00U) /**< \brief (RSTC) Control Register */ +#define REG_RSTC_SR (*(RoReg*)0x400E1A04U) /**< \brief (RSTC) Status Register */ +#define REG_RSTC_MR (*(RwReg*)0x400E1A08U) /**< \brief (RSTC) Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_RSTC_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h new file mode 100644 index 0000000..df16e69 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtc.h @@ -0,0 +1,79 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_RTC_INSTANCE_ +#define _SAM3XA_RTC_INSTANCE_ + +/* ========== Register definition for RTC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_RTC_CR (0x400E1A60U) /**< \brief (RTC) Control Register */ +#define REG_RTC_MR (0x400E1A64U) /**< \brief (RTC) Mode Register */ +#define REG_RTC_TIMR (0x400E1A68U) /**< \brief (RTC) Time Register */ +#define REG_RTC_CALR (0x400E1A6CU) /**< \brief (RTC) Calendar Register */ +#define REG_RTC_TIMALR (0x400E1A70U) /**< \brief (RTC) Time Alarm Register */ +#define REG_RTC_CALALR (0x400E1A74U) /**< \brief (RTC) Calendar Alarm Register */ +#define REG_RTC_SR (0x400E1A78U) /**< \brief (RTC) Status Register */ +#define REG_RTC_SCCR (0x400E1A7CU) /**< \brief (RTC) Status Clear Command Register */ +#define REG_RTC_IER (0x400E1A80U) /**< \brief (RTC) Interrupt Enable Register */ +#define REG_RTC_IDR (0x400E1A84U) /**< \brief (RTC) Interrupt Disable Register */ +#define REG_RTC_IMR (0x400E1A88U) /**< \brief (RTC) Interrupt Mask Register */ +#define REG_RTC_VER (0x400E1A8CU) /**< \brief (RTC) Valid Entry Register */ +#define REG_RTC_WPMR (0x400E1B44U) /**< \brief (RTC) Write Protect Mode Register */ +#else +#define REG_RTC_CR (*(RwReg*)0x400E1A60U) /**< \brief (RTC) Control Register */ +#define REG_RTC_MR (*(RwReg*)0x400E1A64U) /**< \brief (RTC) Mode Register */ +#define REG_RTC_TIMR (*(RwReg*)0x400E1A68U) /**< \brief (RTC) Time Register */ +#define REG_RTC_CALR (*(RwReg*)0x400E1A6CU) /**< \brief (RTC) Calendar Register */ +#define REG_RTC_TIMALR (*(RwReg*)0x400E1A70U) /**< \brief (RTC) Time Alarm Register */ +#define REG_RTC_CALALR (*(RwReg*)0x400E1A74U) /**< \brief (RTC) Calendar Alarm Register */ +#define REG_RTC_SR (*(RoReg*)0x400E1A78U) /**< \brief (RTC) Status Register */ +#define REG_RTC_SCCR (*(WoReg*)0x400E1A7CU) /**< \brief (RTC) Status Clear Command Register */ +#define REG_RTC_IER (*(WoReg*)0x400E1A80U) /**< \brief (RTC) Interrupt Enable Register */ +#define REG_RTC_IDR (*(WoReg*)0x400E1A84U) /**< \brief (RTC) Interrupt Disable Register */ +#define REG_RTC_IMR (*(RoReg*)0x400E1A88U) /**< \brief (RTC) Interrupt Mask Register */ +#define REG_RTC_VER (*(RoReg*)0x400E1A8CU) /**< \brief (RTC) Valid Entry Register */ +#define REG_RTC_WPMR (*(RwReg*)0x400E1B44U) /**< \brief (RTC) Write Protect Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_RTC_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h new file mode 100644 index 0000000..07e08b1 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_rtt.h @@ -0,0 +1,61 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_RTT_INSTANCE_ +#define _SAM3XA_RTT_INSTANCE_ + +/* ========== Register definition for RTT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_RTT_MR (0x400E1A30U) /**< \brief (RTT) Mode Register */ +#define REG_RTT_AR (0x400E1A34U) /**< \brief (RTT) Alarm Register */ +#define REG_RTT_VR (0x400E1A38U) /**< \brief (RTT) Value Register */ +#define REG_RTT_SR (0x400E1A3CU) /**< \brief (RTT) Status Register */ +#else +#define REG_RTT_MR (*(RwReg*)0x400E1A30U) /**< \brief (RTT) Mode Register */ +#define REG_RTT_AR (*(RwReg*)0x400E1A34U) /**< \brief (RTT) Alarm Register */ +#define REG_RTT_VR (*(RoReg*)0x400E1A38U) /**< \brief (RTT) Value Register */ +#define REG_RTT_SR (*(RoReg*)0x400E1A3CU) /**< \brief (RTT) Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_RTT_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_sdramc.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_sdramc.h new file mode 100644 index 0000000..e28efb2 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_sdramc.h @@ -0,0 +1,75 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_SDRAMC_INSTANCE_ +#define _SAM3XA_SDRAMC_INSTANCE_ + +/* ========== Register definition for SDRAMC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SDRAMC_MR (0x400E0200U) /**< \brief (SDRAMC) SDRAMC Mode Register */ +#define REG_SDRAMC_TR (0x400E0204U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */ +#define REG_SDRAMC_CR (0x400E0208U) /**< \brief (SDRAMC) SDRAMC Configuration Register */ +#define REG_SDRAMC_LPR (0x400E0210U) /**< \brief (SDRAMC) SDRAMC Low Power Register */ +#define REG_SDRAMC_IER (0x400E0214U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */ +#define REG_SDRAMC_IDR (0x400E0218U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */ +#define REG_SDRAMC_IMR (0x400E021CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */ +#define REG_SDRAMC_ISR (0x400E0220U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */ +#define REG_SDRAMC_MDR (0x400E0224U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */ +#define REG_SDRAMC_CR1 (0x400E0228U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */ +#define REG_SDRAMC_OCMS (0x400E022CU) /**< \brief (SDRAMC) SDRAMC OCMS Register 1 */ +#else +#define REG_SDRAMC_MR (*(RwReg*)0x400E0200U) /**< \brief (SDRAMC) SDRAMC Mode Register */ +#define REG_SDRAMC_TR (*(RwReg*)0x400E0204U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */ +#define REG_SDRAMC_CR (*(RwReg*)0x400E0208U) /**< \brief (SDRAMC) SDRAMC Configuration Register */ +#define REG_SDRAMC_LPR (*(RwReg*)0x400E0210U) /**< \brief (SDRAMC) SDRAMC Low Power Register */ +#define REG_SDRAMC_IER (*(WoReg*)0x400E0214U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */ +#define REG_SDRAMC_IDR (*(WoReg*)0x400E0218U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */ +#define REG_SDRAMC_IMR (*(RoReg*)0x400E021CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */ +#define REG_SDRAMC_ISR (*(RoReg*)0x400E0220U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */ +#define REG_SDRAMC_MDR (*(RwReg*)0x400E0224U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */ +#define REG_SDRAMC_CR1 (*(RwReg*)0x400E0228U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */ +#define REG_SDRAMC_OCMS (*(RwReg*)0x400E022CU) /**< \brief (SDRAMC) SDRAMC OCMS Register 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_SDRAMC_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h new file mode 100644 index 0000000..3a4632b --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_smc.h @@ -0,0 +1,199 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_SMC_INSTANCE_ +#define _SAM3XA_SMC_INSTANCE_ + +/* ========== Register definition for SMC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SMC_CFG (0x400E0000U) /**< \brief (SMC) SMC NFC Configuration Register */ +#define REG_SMC_CTRL (0x400E0004U) /**< \brief (SMC) SMC NFC Control Register */ +#define REG_SMC_SR (0x400E0008U) /**< \brief (SMC) SMC NFC Status Register */ +#define REG_SMC_IER (0x400E000CU) /**< \brief (SMC) SMC NFC Interrupt Enable Register */ +#define REG_SMC_IDR (0x400E0010U) /**< \brief (SMC) SMC NFC Interrupt Disable Register */ +#define REG_SMC_IMR (0x400E0014U) /**< \brief (SMC) SMC NFC Interrupt Mask Register */ +#define REG_SMC_ADDR (0x400E0018U) /**< \brief (SMC) SMC NFC Address Cycle Zero Register */ +#define REG_SMC_BANK (0x400E001CU) /**< \brief (SMC) SMC Bank Address Register */ +#define REG_SMC_ECC_CTRL (0x400E0020U) /**< \brief (SMC) SMC ECC Control Register */ +#define REG_SMC_ECC_MD (0x400E0024U) /**< \brief (SMC) SMC ECC Mode Register */ +#define REG_SMC_ECC_SR1 (0x400E0028U) /**< \brief (SMC) SMC ECC Status 1 Register */ +#define REG_SMC_ECC_PR0 (0x400E002CU) /**< \brief (SMC) SMC ECC Parity 0 Register */ +#define REG_SMC_ECC_PR1 (0x400E0030U) /**< \brief (SMC) SMC ECC parity 1 Register */ +#define REG_SMC_ECC_SR2 (0x400E0034U) /**< \brief (SMC) SMC ECC status 2 Register */ +#define REG_SMC_ECC_PR2 (0x400E0038U) /**< \brief (SMC) SMC ECC parity 2 Register */ +#define REG_SMC_ECC_PR3 (0x400E003CU) /**< \brief (SMC) SMC ECC parity 3 Register */ +#define REG_SMC_ECC_PR4 (0x400E0040U) /**< \brief (SMC) SMC ECC parity 4 Register */ +#define REG_SMC_ECC_PR5 (0x400E0044U) /**< \brief (SMC) SMC ECC parity 5 Register */ +#define REG_SMC_ECC_PR6 (0x400E0048U) /**< \brief (SMC) SMC ECC parity 6 Register */ +#define REG_SMC_ECC_PR7 (0x400E004CU) /**< \brief (SMC) SMC ECC parity 7 Register */ +#define REG_SMC_ECC_PR8 (0x400E0050U) /**< \brief (SMC) SMC ECC parity 8 Register */ +#define REG_SMC_ECC_PR9 (0x400E0054U) /**< \brief (SMC) SMC ECC parity 9 Register */ +#define REG_SMC_ECC_PR10 (0x400E0058U) /**< \brief (SMC) SMC ECC parity 10 Register */ +#define REG_SMC_ECC_PR11 (0x400E005CU) /**< \brief (SMC) SMC ECC parity 11 Register */ +#define REG_SMC_ECC_PR12 (0x400E0060U) /**< \brief (SMC) SMC ECC parity 12 Register */ +#define REG_SMC_ECC_PR13 (0x400E0064U) /**< \brief (SMC) SMC ECC parity 13 Register */ +#define REG_SMC_ECC_PR14 (0x400E0068U) /**< \brief (SMC) SMC ECC parity 14 Register */ +#define REG_SMC_ECC_PR15 (0x400E006CU) /**< \brief (SMC) SMC ECC parity 15 Register */ +#define REG_SMC_SETUP0 (0x400E0070U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ +#define REG_SMC_PULSE0 (0x400E0074U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ +#define REG_SMC_CYCLE0 (0x400E0078U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ +#define REG_SMC_TIMINGS0 (0x400E007CU) /**< \brief (SMC) SMC Timings Register (CS_number = 0) */ +#define REG_SMC_MODE0 (0x400E0080U) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */ +#define REG_SMC_SETUP1 (0x400E0084U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ +#define REG_SMC_PULSE1 (0x400E0088U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ +#define REG_SMC_CYCLE1 (0x400E008CU) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ +#define REG_SMC_TIMINGS1 (0x400E0090U) /**< \brief (SMC) SMC Timings Register (CS_number = 1) */ +#define REG_SMC_MODE1 (0x400E0094U) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */ +#define REG_SMC_SETUP2 (0x400E0098U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ +#define REG_SMC_PULSE2 (0x400E009CU) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ +#define REG_SMC_CYCLE2 (0x400E00A0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ +#define REG_SMC_TIMINGS2 (0x400E00A4U) /**< \brief (SMC) SMC Timings Register (CS_number = 2) */ +#define REG_SMC_MODE2 (0x400E00A8U) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */ +#define REG_SMC_SETUP3 (0x400E00ACU) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ +#define REG_SMC_PULSE3 (0x400E00B0U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ +#define REG_SMC_CYCLE3 (0x400E00B4U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ +#define REG_SMC_TIMINGS3 (0x400E00B8U) /**< \brief (SMC) SMC Timings Register (CS_number = 3) */ +#define REG_SMC_MODE3 (0x400E00BCU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */ +#define REG_SMC_SETUP4 (0x400E00C0U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */ +#define REG_SMC_PULSE4 (0x400E00C4U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */ +#define REG_SMC_CYCLE4 (0x400E00C8U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */ +#define REG_SMC_TIMINGS4 (0x400E00CCU) /**< \brief (SMC) SMC Timings Register (CS_number = 4) */ +#define REG_SMC_MODE4 (0x400E00D0U) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */ +#define REG_SMC_SETUP5 (0x400E00D4U) /**< \brief (SMC) SMC Setup Register (CS_number = 5) */ +#define REG_SMC_PULSE5 (0x400E00D8U) /**< \brief (SMC) SMC Pulse Register (CS_number = 5) */ +#define REG_SMC_CYCLE5 (0x400E00DCU) /**< \brief (SMC) SMC Cycle Register (CS_number = 5) */ +#define REG_SMC_TIMINGS5 (0x400E00E0U) /**< \brief (SMC) SMC Timings Register (CS_number = 5) */ +#define REG_SMC_MODE5 (0x400E00E4U) /**< \brief (SMC) SMC Mode Register (CS_number = 5) */ +#define REG_SMC_SETUP6 (0x400E00E8U) /**< \brief (SMC) SMC Setup Register (CS_number = 6) */ +#define REG_SMC_PULSE6 (0x400E00ECU) /**< \brief (SMC) SMC Pulse Register (CS_number = 6) */ +#define REG_SMC_CYCLE6 (0x400E00F0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 6) */ +#define REG_SMC_TIMINGS6 (0x400E00F4U) /**< \brief (SMC) SMC Timings Register (CS_number = 6) */ +#define REG_SMC_MODE6 (0x400E00F8U) /**< \brief (SMC) SMC Mode Register (CS_number = 6) */ +#define REG_SMC_SETUP7 (0x400E00FCU) /**< \brief (SMC) SMC Setup Register (CS_number = 7) */ +#define REG_SMC_PULSE7 (0x400E0100U) /**< \brief (SMC) SMC Pulse Register (CS_number = 7) */ +#define REG_SMC_CYCLE7 (0x400E0104U) /**< \brief (SMC) SMC Cycle Register (CS_number = 7) */ +#define REG_SMC_TIMINGS7 (0x400E0108U) /**< \brief (SMC) SMC Timings Register (CS_number = 7) */ +#define REG_SMC_MODE7 (0x400E010CU) /**< \brief (SMC) SMC Mode Register (CS_number = 7) */ +#define REG_SMC_OCMS (0x400E0110U) /**< \brief (SMC) SMC OCMS Register */ +#define REG_SMC_KEY1 (0x400E0114U) /**< \brief (SMC) SMC OCMS KEY1 Register */ +#define REG_SMC_KEY2 (0x400E0118U) /**< \brief (SMC) SMC OCMS KEY2 Register */ +#define REG_SMC_WPCR (0x400E01E4U) /**< \brief (SMC) Write Protection Control Register */ +#define REG_SMC_WPSR (0x400E01E8U) /**< \brief (SMC) Write Protection Status Register */ +#else +#define REG_SMC_CFG (*(RwReg*)0x400E0000U) /**< \brief (SMC) SMC NFC Configuration Register */ +#define REG_SMC_CTRL (*(WoReg*)0x400E0004U) /**< \brief (SMC) SMC NFC Control Register */ +#define REG_SMC_SR (*(RoReg*)0x400E0008U) /**< \brief (SMC) SMC NFC Status Register */ +#define REG_SMC_IER (*(WoReg*)0x400E000CU) /**< \brief (SMC) SMC NFC Interrupt Enable Register */ +#define REG_SMC_IDR (*(WoReg*)0x400E0010U) /**< \brief (SMC) SMC NFC Interrupt Disable Register */ +#define REG_SMC_IMR (*(RoReg*)0x400E0014U) /**< \brief (SMC) SMC NFC Interrupt Mask Register */ +#define REG_SMC_ADDR (*(RwReg*)0x400E0018U) /**< \brief (SMC) SMC NFC Address Cycle Zero Register */ +#define REG_SMC_BANK (*(RwReg*)0x400E001CU) /**< \brief (SMC) SMC Bank Address Register */ +#define REG_SMC_ECC_CTRL (*(WoReg*)0x400E0020U) /**< \brief (SMC) SMC ECC Control Register */ +#define REG_SMC_ECC_MD (*(RwReg*)0x400E0024U) /**< \brief (SMC) SMC ECC Mode Register */ +#define REG_SMC_ECC_SR1 (*(RoReg*)0x400E0028U) /**< \brief (SMC) SMC ECC Status 1 Register */ +#define REG_SMC_ECC_PR0 (*(RoReg*)0x400E002CU) /**< \brief (SMC) SMC ECC Parity 0 Register */ +#define REG_SMC_ECC_PR1 (*(RoReg*)0x400E0030U) /**< \brief (SMC) SMC ECC parity 1 Register */ +#define REG_SMC_ECC_SR2 (*(RoReg*)0x400E0034U) /**< \brief (SMC) SMC ECC status 2 Register */ +#define REG_SMC_ECC_PR2 (*(RoReg*)0x400E0038U) /**< \brief (SMC) SMC ECC parity 2 Register */ +#define REG_SMC_ECC_PR3 (*(RoReg*)0x400E003CU) /**< \brief (SMC) SMC ECC parity 3 Register */ +#define REG_SMC_ECC_PR4 (*(RoReg*)0x400E0040U) /**< \brief (SMC) SMC ECC parity 4 Register */ +#define REG_SMC_ECC_PR5 (*(RoReg*)0x400E0044U) /**< \brief (SMC) SMC ECC parity 5 Register */ +#define REG_SMC_ECC_PR6 (*(RoReg*)0x400E0048U) /**< \brief (SMC) SMC ECC parity 6 Register */ +#define REG_SMC_ECC_PR7 (*(RoReg*)0x400E004CU) /**< \brief (SMC) SMC ECC parity 7 Register */ +#define REG_SMC_ECC_PR8 (*(RoReg*)0x400E0050U) /**< \brief (SMC) SMC ECC parity 8 Register */ +#define REG_SMC_ECC_PR9 (*(RoReg*)0x400E0054U) /**< \brief (SMC) SMC ECC parity 9 Register */ +#define REG_SMC_ECC_PR10 (*(RoReg*)0x400E0058U) /**< \brief (SMC) SMC ECC parity 10 Register */ +#define REG_SMC_ECC_PR11 (*(RoReg*)0x400E005CU) /**< \brief (SMC) SMC ECC parity 11 Register */ +#define REG_SMC_ECC_PR12 (*(RoReg*)0x400E0060U) /**< \brief (SMC) SMC ECC parity 12 Register */ +#define REG_SMC_ECC_PR13 (*(RoReg*)0x400E0064U) /**< \brief (SMC) SMC ECC parity 13 Register */ +#define REG_SMC_ECC_PR14 (*(RoReg*)0x400E0068U) /**< \brief (SMC) SMC ECC parity 14 Register */ +#define REG_SMC_ECC_PR15 (*(RoReg*)0x400E006CU) /**< \brief (SMC) SMC ECC parity 15 Register */ +#define REG_SMC_SETUP0 (*(RwReg*)0x400E0070U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ +#define REG_SMC_PULSE0 (*(RwReg*)0x400E0074U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ +#define REG_SMC_CYCLE0 (*(RwReg*)0x400E0078U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ +#define REG_SMC_TIMINGS0 (*(RwReg*)0x400E007CU) /**< \brief (SMC) SMC Timings Register (CS_number = 0) */ +#define REG_SMC_MODE0 (*(RwReg*)0x400E0080U) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */ +#define REG_SMC_SETUP1 (*(RwReg*)0x400E0084U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ +#define REG_SMC_PULSE1 (*(RwReg*)0x400E0088U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ +#define REG_SMC_CYCLE1 (*(RwReg*)0x400E008CU) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ +#define REG_SMC_TIMINGS1 (*(RwReg*)0x400E0090U) /**< \brief (SMC) SMC Timings Register (CS_number = 1) */ +#define REG_SMC_MODE1 (*(RwReg*)0x400E0094U) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */ +#define REG_SMC_SETUP2 (*(RwReg*)0x400E0098U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ +#define REG_SMC_PULSE2 (*(RwReg*)0x400E009CU) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ +#define REG_SMC_CYCLE2 (*(RwReg*)0x400E00A0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ +#define REG_SMC_TIMINGS2 (*(RwReg*)0x400E00A4U) /**< \brief (SMC) SMC Timings Register (CS_number = 2) */ +#define REG_SMC_MODE2 (*(RwReg*)0x400E00A8U) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */ +#define REG_SMC_SETUP3 (*(RwReg*)0x400E00ACU) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ +#define REG_SMC_PULSE3 (*(RwReg*)0x400E00B0U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ +#define REG_SMC_CYCLE3 (*(RwReg*)0x400E00B4U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ +#define REG_SMC_TIMINGS3 (*(RwReg*)0x400E00B8U) /**< \brief (SMC) SMC Timings Register (CS_number = 3) */ +#define REG_SMC_MODE3 (*(RwReg*)0x400E00BCU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */ +#define REG_SMC_SETUP4 (*(RwReg*)0x400E00C0U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */ +#define REG_SMC_PULSE4 (*(RwReg*)0x400E00C4U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */ +#define REG_SMC_CYCLE4 (*(RwReg*)0x400E00C8U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */ +#define REG_SMC_TIMINGS4 (*(RwReg*)0x400E00CCU) /**< \brief (SMC) SMC Timings Register (CS_number = 4) */ +#define REG_SMC_MODE4 (*(RwReg*)0x400E00D0U) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */ +#define REG_SMC_SETUP5 (*(RwReg*)0x400E00D4U) /**< \brief (SMC) SMC Setup Register (CS_number = 5) */ +#define REG_SMC_PULSE5 (*(RwReg*)0x400E00D8U) /**< \brief (SMC) SMC Pulse Register (CS_number = 5) */ +#define REG_SMC_CYCLE5 (*(RwReg*)0x400E00DCU) /**< \brief (SMC) SMC Cycle Register (CS_number = 5) */ +#define REG_SMC_TIMINGS5 (*(RwReg*)0x400E00E0U) /**< \brief (SMC) SMC Timings Register (CS_number = 5) */ +#define REG_SMC_MODE5 (*(RwReg*)0x400E00E4U) /**< \brief (SMC) SMC Mode Register (CS_number = 5) */ +#define REG_SMC_SETUP6 (*(RwReg*)0x400E00E8U) /**< \brief (SMC) SMC Setup Register (CS_number = 6) */ +#define REG_SMC_PULSE6 (*(RwReg*)0x400E00ECU) /**< \brief (SMC) SMC Pulse Register (CS_number = 6) */ +#define REG_SMC_CYCLE6 (*(RwReg*)0x400E00F0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 6) */ +#define REG_SMC_TIMINGS6 (*(RwReg*)0x400E00F4U) /**< \brief (SMC) SMC Timings Register (CS_number = 6) */ +#define REG_SMC_MODE6 (*(RwReg*)0x400E00F8U) /**< \brief (SMC) SMC Mode Register (CS_number = 6) */ +#define REG_SMC_SETUP7 (*(RwReg*)0x400E00FCU) /**< \brief (SMC) SMC Setup Register (CS_number = 7) */ +#define REG_SMC_PULSE7 (*(RwReg*)0x400E0100U) /**< \brief (SMC) SMC Pulse Register (CS_number = 7) */ +#define REG_SMC_CYCLE7 (*(RwReg*)0x400E0104U) /**< \brief (SMC) SMC Cycle Register (CS_number = 7) */ +#define REG_SMC_TIMINGS7 (*(RwReg*)0x400E0108U) /**< \brief (SMC) SMC Timings Register (CS_number = 7) */ +#define REG_SMC_MODE7 (*(RwReg*)0x400E010CU) /**< \brief (SMC) SMC Mode Register (CS_number = 7) */ +#define REG_SMC_OCMS (*(RwReg*)0x400E0110U) /**< \brief (SMC) SMC OCMS Register */ +#define REG_SMC_KEY1 (*(WoReg*)0x400E0114U) /**< \brief (SMC) SMC OCMS KEY1 Register */ +#define REG_SMC_KEY2 (*(WoReg*)0x400E0118U) /**< \brief (SMC) SMC OCMS KEY2 Register */ +#define REG_SMC_WPCR (*(WoReg*)0x400E01E4U) /**< \brief (SMC) Write Protection Control Register */ +#define REG_SMC_WPSR (*(RoReg*)0x400E01E8U) /**< \brief (SMC) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_SMC_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h new file mode 100644 index 0000000..d0aa815 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi0.h @@ -0,0 +1,75 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_SPI0_INSTANCE_ +#define _SAM3XA_SPI0_INSTANCE_ + +/* ========== Register definition for SPI0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SPI0_CR (0x40008000U) /**< \brief (SPI0) Control Register */ +#define REG_SPI0_MR (0x40008004U) /**< \brief (SPI0) Mode Register */ +#define REG_SPI0_RDR (0x40008008U) /**< \brief (SPI0) Receive Data Register */ +#define REG_SPI0_TDR (0x4000800CU) /**< \brief (SPI0) Transmit Data Register */ +#define REG_SPI0_SR (0x40008010U) /**< \brief (SPI0) Status Register */ +#define REG_SPI0_IER (0x40008014U) /**< \brief (SPI0) Interrupt Enable Register */ +#define REG_SPI0_IDR (0x40008018U) /**< \brief (SPI0) Interrupt Disable Register */ +#define REG_SPI0_IMR (0x4000801CU) /**< \brief (SPI0) Interrupt Mask Register */ +#define REG_SPI0_CSR (0x40008030U) /**< \brief (SPI0) Chip Select Register */ +#define REG_SPI0_WPMR (0x400080E4U) /**< \brief (SPI0) Write Protection Control Register */ +#define REG_SPI0_WPSR (0x400080E8U) /**< \brief (SPI0) Write Protection Status Register */ +#else +#define REG_SPI0_CR (*(WoReg*)0x40008000U) /**< \brief (SPI0) Control Register */ +#define REG_SPI0_MR (*(RwReg*)0x40008004U) /**< \brief (SPI0) Mode Register */ +#define REG_SPI0_RDR (*(RoReg*)0x40008008U) /**< \brief (SPI0) Receive Data Register */ +#define REG_SPI0_TDR (*(WoReg*)0x4000800CU) /**< \brief (SPI0) Transmit Data Register */ +#define REG_SPI0_SR (*(RoReg*)0x40008010U) /**< \brief (SPI0) Status Register */ +#define REG_SPI0_IER (*(WoReg*)0x40008014U) /**< \brief (SPI0) Interrupt Enable Register */ +#define REG_SPI0_IDR (*(WoReg*)0x40008018U) /**< \brief (SPI0) Interrupt Disable Register */ +#define REG_SPI0_IMR (*(RoReg*)0x4000801CU) /**< \brief (SPI0) Interrupt Mask Register */ +#define REG_SPI0_CSR (*(RwReg*)0x40008030U) /**< \brief (SPI0) Chip Select Register */ +#define REG_SPI0_WPMR (*(RwReg*)0x400080E4U) /**< \brief (SPI0) Write Protection Control Register */ +#define REG_SPI0_WPSR (*(RoReg*)0x400080E8U) /**< \brief (SPI0) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_SPI0_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi1.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi1.h new file mode 100644 index 0000000..2915fe5 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_spi1.h @@ -0,0 +1,75 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_SPI1_INSTANCE_ +#define _SAM3XA_SPI1_INSTANCE_ + +/* ========== Register definition for SPI1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SPI1_CR (0x4000C000U) /**< \brief (SPI1) Control Register */ +#define REG_SPI1_MR (0x4000C004U) /**< \brief (SPI1) Mode Register */ +#define REG_SPI1_RDR (0x4000C008U) /**< \brief (SPI1) Receive Data Register */ +#define REG_SPI1_TDR (0x4000C00CU) /**< \brief (SPI1) Transmit Data Register */ +#define REG_SPI1_SR (0x4000C010U) /**< \brief (SPI1) Status Register */ +#define REG_SPI1_IER (0x4000C014U) /**< \brief (SPI1) Interrupt Enable Register */ +#define REG_SPI1_IDR (0x4000C018U) /**< \brief (SPI1) Interrupt Disable Register */ +#define REG_SPI1_IMR (0x4000C01CU) /**< \brief (SPI1) Interrupt Mask Register */ +#define REG_SPI1_CSR (0x4000C030U) /**< \brief (SPI1) Chip Select Register */ +#define REG_SPI1_WPMR (0x4000C0E4U) /**< \brief (SPI1) Write Protection Control Register */ +#define REG_SPI1_WPSR (0x4000C0E8U) /**< \brief (SPI1) Write Protection Status Register */ +#else +#define REG_SPI1_CR (*(WoReg*)0x4000C000U) /**< \brief (SPI1) Control Register */ +#define REG_SPI1_MR (*(RwReg*)0x4000C004U) /**< \brief (SPI1) Mode Register */ +#define REG_SPI1_RDR (*(RoReg*)0x4000C008U) /**< \brief (SPI1) Receive Data Register */ +#define REG_SPI1_TDR (*(WoReg*)0x4000C00CU) /**< \brief (SPI1) Transmit Data Register */ +#define REG_SPI1_SR (*(RoReg*)0x4000C010U) /**< \brief (SPI1) Status Register */ +#define REG_SPI1_IER (*(WoReg*)0x4000C014U) /**< \brief (SPI1) Interrupt Enable Register */ +#define REG_SPI1_IDR (*(WoReg*)0x4000C018U) /**< \brief (SPI1) Interrupt Disable Register */ +#define REG_SPI1_IMR (*(RoReg*)0x4000C01CU) /**< \brief (SPI1) Interrupt Mask Register */ +#define REG_SPI1_CSR (*(RwReg*)0x4000C030U) /**< \brief (SPI1) Chip Select Register */ +#define REG_SPI1_WPMR (*(RwReg*)0x4000C0E4U) /**< \brief (SPI1) Write Protection Control Register */ +#define REG_SPI1_WPSR (*(RoReg*)0x4000C0E8U) /**< \brief (SPI1) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_SPI1_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h new file mode 100644 index 0000000..41843fc --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_ssc.h @@ -0,0 +1,89 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_SSC_INSTANCE_ +#define _SAM3XA_SSC_INSTANCE_ + +/* ========== Register definition for SSC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SSC_CR (0x40004000U) /**< \brief (SSC) Control Register */ +#define REG_SSC_CMR (0x40004004U) /**< \brief (SSC) Clock Mode Register */ +#define REG_SSC_RCMR (0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */ +#define REG_SSC_RFMR (0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */ +#define REG_SSC_TCMR (0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */ +#define REG_SSC_TFMR (0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */ +#define REG_SSC_RHR (0x40004020U) /**< \brief (SSC) Receive Holding Register */ +#define REG_SSC_THR (0x40004024U) /**< \brief (SSC) Transmit Holding Register */ +#define REG_SSC_RSHR (0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */ +#define REG_SSC_TSHR (0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */ +#define REG_SSC_RC0R (0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */ +#define REG_SSC_RC1R (0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */ +#define REG_SSC_SR (0x40004040U) /**< \brief (SSC) Status Register */ +#define REG_SSC_IER (0x40004044U) /**< \brief (SSC) Interrupt Enable Register */ +#define REG_SSC_IDR (0x40004048U) /**< \brief (SSC) Interrupt Disable Register */ +#define REG_SSC_IMR (0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */ +#define REG_SSC_WPMR (0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */ +#define REG_SSC_WPSR (0x400040E8U) /**< \brief (SSC) Write Protect Status Register */ +#else +#define REG_SSC_CR (*(WoReg*)0x40004000U) /**< \brief (SSC) Control Register */ +#define REG_SSC_CMR (*(RwReg*)0x40004004U) /**< \brief (SSC) Clock Mode Register */ +#define REG_SSC_RCMR (*(RwReg*)0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */ +#define REG_SSC_RFMR (*(RwReg*)0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */ +#define REG_SSC_TCMR (*(RwReg*)0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */ +#define REG_SSC_TFMR (*(RwReg*)0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */ +#define REG_SSC_RHR (*(RoReg*)0x40004020U) /**< \brief (SSC) Receive Holding Register */ +#define REG_SSC_THR (*(WoReg*)0x40004024U) /**< \brief (SSC) Transmit Holding Register */ +#define REG_SSC_RSHR (*(RoReg*)0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */ +#define REG_SSC_TSHR (*(RwReg*)0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */ +#define REG_SSC_RC0R (*(RwReg*)0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */ +#define REG_SSC_RC1R (*(RwReg*)0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */ +#define REG_SSC_SR (*(RoReg*)0x40004040U) /**< \brief (SSC) Status Register */ +#define REG_SSC_IER (*(WoReg*)0x40004044U) /**< \brief (SSC) Interrupt Enable Register */ +#define REG_SSC_IDR (*(WoReg*)0x40004048U) /**< \brief (SSC) Interrupt Disable Register */ +#define REG_SSC_IMR (*(RoReg*)0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */ +#define REG_SSC_WPMR (*(RwReg*)0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */ +#define REG_SSC_WPSR (*(RoReg*)0x400040E8U) /**< \brief (SSC) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_SSC_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h new file mode 100644 index 0000000..2acee39 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_supc.h @@ -0,0 +1,65 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_SUPC_INSTANCE_ +#define _SAM3XA_SUPC_INSTANCE_ + +/* ========== Register definition for SUPC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SUPC_CR (0x400E1A10U) /**< \brief (SUPC) Supply Controller Control Register */ +#define REG_SUPC_SMMR (0x400E1A14U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ +#define REG_SUPC_MR (0x400E1A18U) /**< \brief (SUPC) Supply Controller Mode Register */ +#define REG_SUPC_WUMR (0x400E1A1CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */ +#define REG_SUPC_WUIR (0x400E1A20U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */ +#define REG_SUPC_SR (0x400E1A24U) /**< \brief (SUPC) Supply Controller Status Register */ +#else +#define REG_SUPC_CR (*(WoReg*)0x400E1A10U) /**< \brief (SUPC) Supply Controller Control Register */ +#define REG_SUPC_SMMR (*(RwReg*)0x400E1A14U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ +#define REG_SUPC_MR (*(RwReg*)0x400E1A18U) /**< \brief (SUPC) Supply Controller Mode Register */ +#define REG_SUPC_WUMR (*(RwReg*)0x400E1A1CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */ +#define REG_SUPC_WUIR (*(RwReg*)0x400E1A20U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */ +#define REG_SUPC_SR (*(RoReg*)0x400E1A24U) /**< \brief (SUPC) Supply Controller Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_SUPC_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h new file mode 100644 index 0000000..114d297 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc0.h @@ -0,0 +1,135 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_TC0_INSTANCE_ +#define _SAM3XA_TC0_INSTANCE_ + +/* ========== Register definition for TC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC0_CCR0 (0x40080000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ +#define REG_TC0_CMR0 (0x40080004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ +#define REG_TC0_SMMR0 (0x40080008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */ +#define REG_TC0_CV0 (0x40080010U) /**< \brief (TC0) Counter Value (channel = 0) */ +#define REG_TC0_RA0 (0x40080014U) /**< \brief (TC0) Register A (channel = 0) */ +#define REG_TC0_RB0 (0x40080018U) /**< \brief (TC0) Register B (channel = 0) */ +#define REG_TC0_RC0 (0x4008001CU) /**< \brief (TC0) Register C (channel = 0) */ +#define REG_TC0_SR0 (0x40080020U) /**< \brief (TC0) Status Register (channel = 0) */ +#define REG_TC0_IER0 (0x40080024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ +#define REG_TC0_IDR0 (0x40080028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ +#define REG_TC0_IMR0 (0x4008002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ +#define REG_TC0_CCR1 (0x40080040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ +#define REG_TC0_CMR1 (0x40080044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ +#define REG_TC0_SMMR1 (0x40080048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */ +#define REG_TC0_CV1 (0x40080050U) /**< \brief (TC0) Counter Value (channel = 1) */ +#define REG_TC0_RA1 (0x40080054U) /**< \brief (TC0) Register A (channel = 1) */ +#define REG_TC0_RB1 (0x40080058U) /**< \brief (TC0) Register B (channel = 1) */ +#define REG_TC0_RC1 (0x4008005CU) /**< \brief (TC0) Register C (channel = 1) */ +#define REG_TC0_SR1 (0x40080060U) /**< \brief (TC0) Status Register (channel = 1) */ +#define REG_TC0_IER1 (0x40080064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ +#define REG_TC0_IDR1 (0x40080068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ +#define REG_TC0_IMR1 (0x4008006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ +#define REG_TC0_CCR2 (0x40080080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ +#define REG_TC0_CMR2 (0x40080084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ +#define REG_TC0_SMMR2 (0x40080088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */ +#define REG_TC0_CV2 (0x40080090U) /**< \brief (TC0) Counter Value (channel = 2) */ +#define REG_TC0_RA2 (0x40080094U) /**< \brief (TC0) Register A (channel = 2) */ +#define REG_TC0_RB2 (0x40080098U) /**< \brief (TC0) Register B (channel = 2) */ +#define REG_TC0_RC2 (0x4008009CU) /**< \brief (TC0) Register C (channel = 2) */ +#define REG_TC0_SR2 (0x400800A0U) /**< \brief (TC0) Status Register (channel = 2) */ +#define REG_TC0_IER2 (0x400800A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ +#define REG_TC0_IDR2 (0x400800A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ +#define REG_TC0_IMR2 (0x400800ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ +#define REG_TC0_BCR (0x400800C0U) /**< \brief (TC0) Block Control Register */ +#define REG_TC0_BMR (0x400800C4U) /**< \brief (TC0) Block Mode Register */ +#define REG_TC0_QIER (0x400800C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */ +#define REG_TC0_QIDR (0x400800CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */ +#define REG_TC0_QIMR (0x400800D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */ +#define REG_TC0_QISR (0x400800D4U) /**< \brief (TC0) QDEC Interrupt Status Register */ +#define REG_TC0_FMR (0x400800D8U) /**< \brief (TC0) Fault Mode Register */ +#define REG_TC0_WPMR (0x400800E4U) /**< \brief (TC0) Write Protect Mode Register */ +#else +#define REG_TC0_CCR0 (*(WoReg*)0x40080000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ +#define REG_TC0_CMR0 (*(RwReg*)0x40080004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ +#define REG_TC0_SMMR0 (*(RwReg*)0x40080008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */ +#define REG_TC0_CV0 (*(RoReg*)0x40080010U) /**< \brief (TC0) Counter Value (channel = 0) */ +#define REG_TC0_RA0 (*(RwReg*)0x40080014U) /**< \brief (TC0) Register A (channel = 0) */ +#define REG_TC0_RB0 (*(RwReg*)0x40080018U) /**< \brief (TC0) Register B (channel = 0) */ +#define REG_TC0_RC0 (*(RwReg*)0x4008001CU) /**< \brief (TC0) Register C (channel = 0) */ +#define REG_TC0_SR0 (*(RoReg*)0x40080020U) /**< \brief (TC0) Status Register (channel = 0) */ +#define REG_TC0_IER0 (*(WoReg*)0x40080024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ +#define REG_TC0_IDR0 (*(WoReg*)0x40080028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ +#define REG_TC0_IMR0 (*(RoReg*)0x4008002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ +#define REG_TC0_CCR1 (*(WoReg*)0x40080040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ +#define REG_TC0_CMR1 (*(RwReg*)0x40080044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ +#define REG_TC0_SMMR1 (*(RwReg*)0x40080048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */ +#define REG_TC0_CV1 (*(RoReg*)0x40080050U) /**< \brief (TC0) Counter Value (channel = 1) */ +#define REG_TC0_RA1 (*(RwReg*)0x40080054U) /**< \brief (TC0) Register A (channel = 1) */ +#define REG_TC0_RB1 (*(RwReg*)0x40080058U) /**< \brief (TC0) Register B (channel = 1) */ +#define REG_TC0_RC1 (*(RwReg*)0x4008005CU) /**< \brief (TC0) Register C (channel = 1) */ +#define REG_TC0_SR1 (*(RoReg*)0x40080060U) /**< \brief (TC0) Status Register (channel = 1) */ +#define REG_TC0_IER1 (*(WoReg*)0x40080064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ +#define REG_TC0_IDR1 (*(WoReg*)0x40080068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ +#define REG_TC0_IMR1 (*(RoReg*)0x4008006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ +#define REG_TC0_CCR2 (*(WoReg*)0x40080080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ +#define REG_TC0_CMR2 (*(RwReg*)0x40080084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ +#define REG_TC0_SMMR2 (*(RwReg*)0x40080088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */ +#define REG_TC0_CV2 (*(RoReg*)0x40080090U) /**< \brief (TC0) Counter Value (channel = 2) */ +#define REG_TC0_RA2 (*(RwReg*)0x40080094U) /**< \brief (TC0) Register A (channel = 2) */ +#define REG_TC0_RB2 (*(RwReg*)0x40080098U) /**< \brief (TC0) Register B (channel = 2) */ +#define REG_TC0_RC2 (*(RwReg*)0x4008009CU) /**< \brief (TC0) Register C (channel = 2) */ +#define REG_TC0_SR2 (*(RoReg*)0x400800A0U) /**< \brief (TC0) Status Register (channel = 2) */ +#define REG_TC0_IER2 (*(WoReg*)0x400800A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ +#define REG_TC0_IDR2 (*(WoReg*)0x400800A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ +#define REG_TC0_IMR2 (*(RoReg*)0x400800ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ +#define REG_TC0_BCR (*(WoReg*)0x400800C0U) /**< \brief (TC0) Block Control Register */ +#define REG_TC0_BMR (*(RwReg*)0x400800C4U) /**< \brief (TC0) Block Mode Register */ +#define REG_TC0_QIER (*(WoReg*)0x400800C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */ +#define REG_TC0_QIDR (*(WoReg*)0x400800CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */ +#define REG_TC0_QIMR (*(RoReg*)0x400800D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */ +#define REG_TC0_QISR (*(RoReg*)0x400800D4U) /**< \brief (TC0) QDEC Interrupt Status Register */ +#define REG_TC0_FMR (*(RwReg*)0x400800D8U) /**< \brief (TC0) Fault Mode Register */ +#define REG_TC0_WPMR (*(RwReg*)0x400800E4U) /**< \brief (TC0) Write Protect Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_TC0_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h new file mode 100644 index 0000000..b5a1804 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc1.h @@ -0,0 +1,135 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_TC1_INSTANCE_ +#define _SAM3XA_TC1_INSTANCE_ + +/* ========== Register definition for TC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC1_CCR0 (0x40084000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ +#define REG_TC1_CMR0 (0x40084004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ +#define REG_TC1_SMMR0 (0x40084008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */ +#define REG_TC1_CV0 (0x40084010U) /**< \brief (TC1) Counter Value (channel = 0) */ +#define REG_TC1_RA0 (0x40084014U) /**< \brief (TC1) Register A (channel = 0) */ +#define REG_TC1_RB0 (0x40084018U) /**< \brief (TC1) Register B (channel = 0) */ +#define REG_TC1_RC0 (0x4008401CU) /**< \brief (TC1) Register C (channel = 0) */ +#define REG_TC1_SR0 (0x40084020U) /**< \brief (TC1) Status Register (channel = 0) */ +#define REG_TC1_IER0 (0x40084024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ +#define REG_TC1_IDR0 (0x40084028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ +#define REG_TC1_IMR0 (0x4008402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ +#define REG_TC1_CCR1 (0x40084040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ +#define REG_TC1_CMR1 (0x40084044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ +#define REG_TC1_SMMR1 (0x40084048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */ +#define REG_TC1_CV1 (0x40084050U) /**< \brief (TC1) Counter Value (channel = 1) */ +#define REG_TC1_RA1 (0x40084054U) /**< \brief (TC1) Register A (channel = 1) */ +#define REG_TC1_RB1 (0x40084058U) /**< \brief (TC1) Register B (channel = 1) */ +#define REG_TC1_RC1 (0x4008405CU) /**< \brief (TC1) Register C (channel = 1) */ +#define REG_TC1_SR1 (0x40084060U) /**< \brief (TC1) Status Register (channel = 1) */ +#define REG_TC1_IER1 (0x40084064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ +#define REG_TC1_IDR1 (0x40084068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ +#define REG_TC1_IMR1 (0x4008406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ +#define REG_TC1_CCR2 (0x40084080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ +#define REG_TC1_CMR2 (0x40084084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ +#define REG_TC1_SMMR2 (0x40084088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */ +#define REG_TC1_CV2 (0x40084090U) /**< \brief (TC1) Counter Value (channel = 2) */ +#define REG_TC1_RA2 (0x40084094U) /**< \brief (TC1) Register A (channel = 2) */ +#define REG_TC1_RB2 (0x40084098U) /**< \brief (TC1) Register B (channel = 2) */ +#define REG_TC1_RC2 (0x4008409CU) /**< \brief (TC1) Register C (channel = 2) */ +#define REG_TC1_SR2 (0x400840A0U) /**< \brief (TC1) Status Register (channel = 2) */ +#define REG_TC1_IER2 (0x400840A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ +#define REG_TC1_IDR2 (0x400840A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ +#define REG_TC1_IMR2 (0x400840ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ +#define REG_TC1_BCR (0x400840C0U) /**< \brief (TC1) Block Control Register */ +#define REG_TC1_BMR (0x400840C4U) /**< \brief (TC1) Block Mode Register */ +#define REG_TC1_QIER (0x400840C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */ +#define REG_TC1_QIDR (0x400840CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */ +#define REG_TC1_QIMR (0x400840D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */ +#define REG_TC1_QISR (0x400840D4U) /**< \brief (TC1) QDEC Interrupt Status Register */ +#define REG_TC1_FMR (0x400840D8U) /**< \brief (TC1) Fault Mode Register */ +#define REG_TC1_WPMR (0x400840E4U) /**< \brief (TC1) Write Protect Mode Register */ +#else +#define REG_TC1_CCR0 (*(WoReg*)0x40084000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ +#define REG_TC1_CMR0 (*(RwReg*)0x40084004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ +#define REG_TC1_SMMR0 (*(RwReg*)0x40084008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */ +#define REG_TC1_CV0 (*(RoReg*)0x40084010U) /**< \brief (TC1) Counter Value (channel = 0) */ +#define REG_TC1_RA0 (*(RwReg*)0x40084014U) /**< \brief (TC1) Register A (channel = 0) */ +#define REG_TC1_RB0 (*(RwReg*)0x40084018U) /**< \brief (TC1) Register B (channel = 0) */ +#define REG_TC1_RC0 (*(RwReg*)0x4008401CU) /**< \brief (TC1) Register C (channel = 0) */ +#define REG_TC1_SR0 (*(RoReg*)0x40084020U) /**< \brief (TC1) Status Register (channel = 0) */ +#define REG_TC1_IER0 (*(WoReg*)0x40084024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ +#define REG_TC1_IDR0 (*(WoReg*)0x40084028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ +#define REG_TC1_IMR0 (*(RoReg*)0x4008402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ +#define REG_TC1_CCR1 (*(WoReg*)0x40084040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ +#define REG_TC1_CMR1 (*(RwReg*)0x40084044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ +#define REG_TC1_SMMR1 (*(RwReg*)0x40084048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */ +#define REG_TC1_CV1 (*(RoReg*)0x40084050U) /**< \brief (TC1) Counter Value (channel = 1) */ +#define REG_TC1_RA1 (*(RwReg*)0x40084054U) /**< \brief (TC1) Register A (channel = 1) */ +#define REG_TC1_RB1 (*(RwReg*)0x40084058U) /**< \brief (TC1) Register B (channel = 1) */ +#define REG_TC1_RC1 (*(RwReg*)0x4008405CU) /**< \brief (TC1) Register C (channel = 1) */ +#define REG_TC1_SR1 (*(RoReg*)0x40084060U) /**< \brief (TC1) Status Register (channel = 1) */ +#define REG_TC1_IER1 (*(WoReg*)0x40084064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ +#define REG_TC1_IDR1 (*(WoReg*)0x40084068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ +#define REG_TC1_IMR1 (*(RoReg*)0x4008406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ +#define REG_TC1_CCR2 (*(WoReg*)0x40084080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ +#define REG_TC1_CMR2 (*(RwReg*)0x40084084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ +#define REG_TC1_SMMR2 (*(RwReg*)0x40084088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */ +#define REG_TC1_CV2 (*(RoReg*)0x40084090U) /**< \brief (TC1) Counter Value (channel = 2) */ +#define REG_TC1_RA2 (*(RwReg*)0x40084094U) /**< \brief (TC1) Register A (channel = 2) */ +#define REG_TC1_RB2 (*(RwReg*)0x40084098U) /**< \brief (TC1) Register B (channel = 2) */ +#define REG_TC1_RC2 (*(RwReg*)0x4008409CU) /**< \brief (TC1) Register C (channel = 2) */ +#define REG_TC1_SR2 (*(RoReg*)0x400840A0U) /**< \brief (TC1) Status Register (channel = 2) */ +#define REG_TC1_IER2 (*(WoReg*)0x400840A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ +#define REG_TC1_IDR2 (*(WoReg*)0x400840A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ +#define REG_TC1_IMR2 (*(RoReg*)0x400840ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ +#define REG_TC1_BCR (*(WoReg*)0x400840C0U) /**< \brief (TC1) Block Control Register */ +#define REG_TC1_BMR (*(RwReg*)0x400840C4U) /**< \brief (TC1) Block Mode Register */ +#define REG_TC1_QIER (*(WoReg*)0x400840C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */ +#define REG_TC1_QIDR (*(WoReg*)0x400840CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */ +#define REG_TC1_QIMR (*(RoReg*)0x400840D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */ +#define REG_TC1_QISR (*(RoReg*)0x400840D4U) /**< \brief (TC1) QDEC Interrupt Status Register */ +#define REG_TC1_FMR (*(RwReg*)0x400840D8U) /**< \brief (TC1) Fault Mode Register */ +#define REG_TC1_WPMR (*(RwReg*)0x400840E4U) /**< \brief (TC1) Write Protect Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_TC1_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h new file mode 100644 index 0000000..5524344 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_tc2.h @@ -0,0 +1,135 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_TC2_INSTANCE_ +#define _SAM3XA_TC2_INSTANCE_ + +/* ========== Register definition for TC2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC2_CCR0 (0x40088000U) /**< \brief (TC2) Channel Control Register (channel = 0) */ +#define REG_TC2_CMR0 (0x40088004U) /**< \brief (TC2) Channel Mode Register (channel = 0) */ +#define REG_TC2_SMMR0 (0x40088008U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 0) */ +#define REG_TC2_CV0 (0x40088010U) /**< \brief (TC2) Counter Value (channel = 0) */ +#define REG_TC2_RA0 (0x40088014U) /**< \brief (TC2) Register A (channel = 0) */ +#define REG_TC2_RB0 (0x40088018U) /**< \brief (TC2) Register B (channel = 0) */ +#define REG_TC2_RC0 (0x4008801CU) /**< \brief (TC2) Register C (channel = 0) */ +#define REG_TC2_SR0 (0x40088020U) /**< \brief (TC2) Status Register (channel = 0) */ +#define REG_TC2_IER0 (0x40088024U) /**< \brief (TC2) Interrupt Enable Register (channel = 0) */ +#define REG_TC2_IDR0 (0x40088028U) /**< \brief (TC2) Interrupt Disable Register (channel = 0) */ +#define REG_TC2_IMR0 (0x4008802CU) /**< \brief (TC2) Interrupt Mask Register (channel = 0) */ +#define REG_TC2_CCR1 (0x40088040U) /**< \brief (TC2) Channel Control Register (channel = 1) */ +#define REG_TC2_CMR1 (0x40088044U) /**< \brief (TC2) Channel Mode Register (channel = 1) */ +#define REG_TC2_SMMR1 (0x40088048U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 1) */ +#define REG_TC2_CV1 (0x40088050U) /**< \brief (TC2) Counter Value (channel = 1) */ +#define REG_TC2_RA1 (0x40088054U) /**< \brief (TC2) Register A (channel = 1) */ +#define REG_TC2_RB1 (0x40088058U) /**< \brief (TC2) Register B (channel = 1) */ +#define REG_TC2_RC1 (0x4008805CU) /**< \brief (TC2) Register C (channel = 1) */ +#define REG_TC2_SR1 (0x40088060U) /**< \brief (TC2) Status Register (channel = 1) */ +#define REG_TC2_IER1 (0x40088064U) /**< \brief (TC2) Interrupt Enable Register (channel = 1) */ +#define REG_TC2_IDR1 (0x40088068U) /**< \brief (TC2) Interrupt Disable Register (channel = 1) */ +#define REG_TC2_IMR1 (0x4008806CU) /**< \brief (TC2) Interrupt Mask Register (channel = 1) */ +#define REG_TC2_CCR2 (0x40088080U) /**< \brief (TC2) Channel Control Register (channel = 2) */ +#define REG_TC2_CMR2 (0x40088084U) /**< \brief (TC2) Channel Mode Register (channel = 2) */ +#define REG_TC2_SMMR2 (0x40088088U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 2) */ +#define REG_TC2_CV2 (0x40088090U) /**< \brief (TC2) Counter Value (channel = 2) */ +#define REG_TC2_RA2 (0x40088094U) /**< \brief (TC2) Register A (channel = 2) */ +#define REG_TC2_RB2 (0x40088098U) /**< \brief (TC2) Register B (channel = 2) */ +#define REG_TC2_RC2 (0x4008809CU) /**< \brief (TC2) Register C (channel = 2) */ +#define REG_TC2_SR2 (0x400880A0U) /**< \brief (TC2) Status Register (channel = 2) */ +#define REG_TC2_IER2 (0x400880A4U) /**< \brief (TC2) Interrupt Enable Register (channel = 2) */ +#define REG_TC2_IDR2 (0x400880A8U) /**< \brief (TC2) Interrupt Disable Register (channel = 2) */ +#define REG_TC2_IMR2 (0x400880ACU) /**< \brief (TC2) Interrupt Mask Register (channel = 2) */ +#define REG_TC2_BCR (0x400880C0U) /**< \brief (TC2) Block Control Register */ +#define REG_TC2_BMR (0x400880C4U) /**< \brief (TC2) Block Mode Register */ +#define REG_TC2_QIER (0x400880C8U) /**< \brief (TC2) QDEC Interrupt Enable Register */ +#define REG_TC2_QIDR (0x400880CCU) /**< \brief (TC2) QDEC Interrupt Disable Register */ +#define REG_TC2_QIMR (0x400880D0U) /**< \brief (TC2) QDEC Interrupt Mask Register */ +#define REG_TC2_QISR (0x400880D4U) /**< \brief (TC2) QDEC Interrupt Status Register */ +#define REG_TC2_FMR (0x400880D8U) /**< \brief (TC2) Fault Mode Register */ +#define REG_TC2_WPMR (0x400880E4U) /**< \brief (TC2) Write Protect Mode Register */ +#else +#define REG_TC2_CCR0 (*(WoReg*)0x40088000U) /**< \brief (TC2) Channel Control Register (channel = 0) */ +#define REG_TC2_CMR0 (*(RwReg*)0x40088004U) /**< \brief (TC2) Channel Mode Register (channel = 0) */ +#define REG_TC2_SMMR0 (*(RwReg*)0x40088008U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 0) */ +#define REG_TC2_CV0 (*(RoReg*)0x40088010U) /**< \brief (TC2) Counter Value (channel = 0) */ +#define REG_TC2_RA0 (*(RwReg*)0x40088014U) /**< \brief (TC2) Register A (channel = 0) */ +#define REG_TC2_RB0 (*(RwReg*)0x40088018U) /**< \brief (TC2) Register B (channel = 0) */ +#define REG_TC2_RC0 (*(RwReg*)0x4008801CU) /**< \brief (TC2) Register C (channel = 0) */ +#define REG_TC2_SR0 (*(RoReg*)0x40088020U) /**< \brief (TC2) Status Register (channel = 0) */ +#define REG_TC2_IER0 (*(WoReg*)0x40088024U) /**< \brief (TC2) Interrupt Enable Register (channel = 0) */ +#define REG_TC2_IDR0 (*(WoReg*)0x40088028U) /**< \brief (TC2) Interrupt Disable Register (channel = 0) */ +#define REG_TC2_IMR0 (*(RoReg*)0x4008802CU) /**< \brief (TC2) Interrupt Mask Register (channel = 0) */ +#define REG_TC2_CCR1 (*(WoReg*)0x40088040U) /**< \brief (TC2) Channel Control Register (channel = 1) */ +#define REG_TC2_CMR1 (*(RwReg*)0x40088044U) /**< \brief (TC2) Channel Mode Register (channel = 1) */ +#define REG_TC2_SMMR1 (*(RwReg*)0x40088048U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 1) */ +#define REG_TC2_CV1 (*(RoReg*)0x40088050U) /**< \brief (TC2) Counter Value (channel = 1) */ +#define REG_TC2_RA1 (*(RwReg*)0x40088054U) /**< \brief (TC2) Register A (channel = 1) */ +#define REG_TC2_RB1 (*(RwReg*)0x40088058U) /**< \brief (TC2) Register B (channel = 1) */ +#define REG_TC2_RC1 (*(RwReg*)0x4008805CU) /**< \brief (TC2) Register C (channel = 1) */ +#define REG_TC2_SR1 (*(RoReg*)0x40088060U) /**< \brief (TC2) Status Register (channel = 1) */ +#define REG_TC2_IER1 (*(WoReg*)0x40088064U) /**< \brief (TC2) Interrupt Enable Register (channel = 1) */ +#define REG_TC2_IDR1 (*(WoReg*)0x40088068U) /**< \brief (TC2) Interrupt Disable Register (channel = 1) */ +#define REG_TC2_IMR1 (*(RoReg*)0x4008806CU) /**< \brief (TC2) Interrupt Mask Register (channel = 1) */ +#define REG_TC2_CCR2 (*(WoReg*)0x40088080U) /**< \brief (TC2) Channel Control Register (channel = 2) */ +#define REG_TC2_CMR2 (*(RwReg*)0x40088084U) /**< \brief (TC2) Channel Mode Register (channel = 2) */ +#define REG_TC2_SMMR2 (*(RwReg*)0x40088088U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 2) */ +#define REG_TC2_CV2 (*(RoReg*)0x40088090U) /**< \brief (TC2) Counter Value (channel = 2) */ +#define REG_TC2_RA2 (*(RwReg*)0x40088094U) /**< \brief (TC2) Register A (channel = 2) */ +#define REG_TC2_RB2 (*(RwReg*)0x40088098U) /**< \brief (TC2) Register B (channel = 2) */ +#define REG_TC2_RC2 (*(RwReg*)0x4008809CU) /**< \brief (TC2) Register C (channel = 2) */ +#define REG_TC2_SR2 (*(RoReg*)0x400880A0U) /**< \brief (TC2) Status Register (channel = 2) */ +#define REG_TC2_IER2 (*(WoReg*)0x400880A4U) /**< \brief (TC2) Interrupt Enable Register (channel = 2) */ +#define REG_TC2_IDR2 (*(WoReg*)0x400880A8U) /**< \brief (TC2) Interrupt Disable Register (channel = 2) */ +#define REG_TC2_IMR2 (*(RoReg*)0x400880ACU) /**< \brief (TC2) Interrupt Mask Register (channel = 2) */ +#define REG_TC2_BCR (*(WoReg*)0x400880C0U) /**< \brief (TC2) Block Control Register */ +#define REG_TC2_BMR (*(RwReg*)0x400880C4U) /**< \brief (TC2) Block Mode Register */ +#define REG_TC2_QIER (*(WoReg*)0x400880C8U) /**< \brief (TC2) QDEC Interrupt Enable Register */ +#define REG_TC2_QIDR (*(WoReg*)0x400880CCU) /**< \brief (TC2) QDEC Interrupt Disable Register */ +#define REG_TC2_QIMR (*(RoReg*)0x400880D0U) /**< \brief (TC2) QDEC Interrupt Mask Register */ +#define REG_TC2_QISR (*(RoReg*)0x400880D4U) /**< \brief (TC2) QDEC Interrupt Status Register */ +#define REG_TC2_FMR (*(RwReg*)0x400880D8U) /**< \brief (TC2) Fault Mode Register */ +#define REG_TC2_WPMR (*(RwReg*)0x400880E4U) /**< \brief (TC2) Write Protect Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_TC2_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h new file mode 100644 index 0000000..d09c769 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_trng.h @@ -0,0 +1,65 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_TRNG_INSTANCE_ +#define _SAM3XA_TRNG_INSTANCE_ + +/* ========== Register definition for TRNG peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TRNG_CR (0x400BC000U) /**< \brief (TRNG) Control Register */ +#define REG_TRNG_IER (0x400BC010U) /**< \brief (TRNG) Interrupt Enable Register */ +#define REG_TRNG_IDR (0x400BC014U) /**< \brief (TRNG) Interrupt Disable Register */ +#define REG_TRNG_IMR (0x400BC018U) /**< \brief (TRNG) Interrupt Mask Register */ +#define REG_TRNG_ISR (0x400BC01CU) /**< \brief (TRNG) Interrupt Status Register */ +#define REG_TRNG_ODATA (0x400BC050U) /**< \brief (TRNG) Output Data Register */ +#else +#define REG_TRNG_CR (*(WoReg*)0x400BC000U) /**< \brief (TRNG) Control Register */ +#define REG_TRNG_IER (*(WoReg*)0x400BC010U) /**< \brief (TRNG) Interrupt Enable Register */ +#define REG_TRNG_IDR (*(WoReg*)0x400BC014U) /**< \brief (TRNG) Interrupt Disable Register */ +#define REG_TRNG_IMR (*(RoReg*)0x400BC018U) /**< \brief (TRNG) Interrupt Mask Register */ +#define REG_TRNG_ISR (*(RoReg*)0x400BC01CU) /**< \brief (TRNG) Interrupt Status Register */ +#define REG_TRNG_ODATA (*(RoReg*)0x400BC050U) /**< \brief (TRNG) Output Data Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_TRNG_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h new file mode 100644 index 0000000..34b1fc5 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi0.h @@ -0,0 +1,95 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_TWI0_INSTANCE_ +#define _SAM3XA_TWI0_INSTANCE_ + +/* ========== Register definition for TWI0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TWI0_CR (0x4008C000U) /**< \brief (TWI0) Control Register */ +#define REG_TWI0_MMR (0x4008C004U) /**< \brief (TWI0) Master Mode Register */ +#define REG_TWI0_SMR (0x4008C008U) /**< \brief (TWI0) Slave Mode Register */ +#define REG_TWI0_IADR (0x4008C00CU) /**< \brief (TWI0) Internal Address Register */ +#define REG_TWI0_CWGR (0x4008C010U) /**< \brief (TWI0) Clock Waveform Generator Register */ +#define REG_TWI0_SR (0x4008C020U) /**< \brief (TWI0) Status Register */ +#define REG_TWI0_IER (0x4008C024U) /**< \brief (TWI0) Interrupt Enable Register */ +#define REG_TWI0_IDR (0x4008C028U) /**< \brief (TWI0) Interrupt Disable Register */ +#define REG_TWI0_IMR (0x4008C02CU) /**< \brief (TWI0) Interrupt Mask Register */ +#define REG_TWI0_RHR (0x4008C030U) /**< \brief (TWI0) Receive Holding Register */ +#define REG_TWI0_THR (0x4008C034U) /**< \brief (TWI0) Transmit Holding Register */ +#define REG_TWI0_RPR (0x4008C100U) /**< \brief (TWI0) Receive Pointer Register */ +#define REG_TWI0_RCR (0x4008C104U) /**< \brief (TWI0) Receive Counter Register */ +#define REG_TWI0_TPR (0x4008C108U) /**< \brief (TWI0) Transmit Pointer Register */ +#define REG_TWI0_TCR (0x4008C10CU) /**< \brief (TWI0) Transmit Counter Register */ +#define REG_TWI0_RNPR (0x4008C110U) /**< \brief (TWI0) Receive Next Pointer Register */ +#define REG_TWI0_RNCR (0x4008C114U) /**< \brief (TWI0) Receive Next Counter Register */ +#define REG_TWI0_TNPR (0x4008C118U) /**< \brief (TWI0) Transmit Next Pointer Register */ +#define REG_TWI0_TNCR (0x4008C11CU) /**< \brief (TWI0) Transmit Next Counter Register */ +#define REG_TWI0_PTCR (0x4008C120U) /**< \brief (TWI0) Transfer Control Register */ +#define REG_TWI0_PTSR (0x4008C124U) /**< \brief (TWI0) Transfer Status Register */ +#else +#define REG_TWI0_CR (*(WoReg*)0x4008C000U) /**< \brief (TWI0) Control Register */ +#define REG_TWI0_MMR (*(RwReg*)0x4008C004U) /**< \brief (TWI0) Master Mode Register */ +#define REG_TWI0_SMR (*(RwReg*)0x4008C008U) /**< \brief (TWI0) Slave Mode Register */ +#define REG_TWI0_IADR (*(RwReg*)0x4008C00CU) /**< \brief (TWI0) Internal Address Register */ +#define REG_TWI0_CWGR (*(RwReg*)0x4008C010U) /**< \brief (TWI0) Clock Waveform Generator Register */ +#define REG_TWI0_SR (*(RoReg*)0x4008C020U) /**< \brief (TWI0) Status Register */ +#define REG_TWI0_IER (*(WoReg*)0x4008C024U) /**< \brief (TWI0) Interrupt Enable Register */ +#define REG_TWI0_IDR (*(WoReg*)0x4008C028U) /**< \brief (TWI0) Interrupt Disable Register */ +#define REG_TWI0_IMR (*(RoReg*)0x4008C02CU) /**< \brief (TWI0) Interrupt Mask Register */ +#define REG_TWI0_RHR (*(RoReg*)0x4008C030U) /**< \brief (TWI0) Receive Holding Register */ +#define REG_TWI0_THR (*(WoReg*)0x4008C034U) /**< \brief (TWI0) Transmit Holding Register */ +#define REG_TWI0_RPR (*(RwReg*)0x4008C100U) /**< \brief (TWI0) Receive Pointer Register */ +#define REG_TWI0_RCR (*(RwReg*)0x4008C104U) /**< \brief (TWI0) Receive Counter Register */ +#define REG_TWI0_TPR (*(RwReg*)0x4008C108U) /**< \brief (TWI0) Transmit Pointer Register */ +#define REG_TWI0_TCR (*(RwReg*)0x4008C10CU) /**< \brief (TWI0) Transmit Counter Register */ +#define REG_TWI0_RNPR (*(RwReg*)0x4008C110U) /**< \brief (TWI0) Receive Next Pointer Register */ +#define REG_TWI0_RNCR (*(RwReg*)0x4008C114U) /**< \brief (TWI0) Receive Next Counter Register */ +#define REG_TWI0_TNPR (*(RwReg*)0x4008C118U) /**< \brief (TWI0) Transmit Next Pointer Register */ +#define REG_TWI0_TNCR (*(RwReg*)0x4008C11CU) /**< \brief (TWI0) Transmit Next Counter Register */ +#define REG_TWI0_PTCR (*(WoReg*)0x4008C120U) /**< \brief (TWI0) Transfer Control Register */ +#define REG_TWI0_PTSR (*(RoReg*)0x4008C124U) /**< \brief (TWI0) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_TWI0_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h new file mode 100644 index 0000000..591b248 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_twi1.h @@ -0,0 +1,95 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_TWI1_INSTANCE_ +#define _SAM3XA_TWI1_INSTANCE_ + +/* ========== Register definition for TWI1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TWI1_CR (0x40090000U) /**< \brief (TWI1) Control Register */ +#define REG_TWI1_MMR (0x40090004U) /**< \brief (TWI1) Master Mode Register */ +#define REG_TWI1_SMR (0x40090008U) /**< \brief (TWI1) Slave Mode Register */ +#define REG_TWI1_IADR (0x4009000CU) /**< \brief (TWI1) Internal Address Register */ +#define REG_TWI1_CWGR (0x40090010U) /**< \brief (TWI1) Clock Waveform Generator Register */ +#define REG_TWI1_SR (0x40090020U) /**< \brief (TWI1) Status Register */ +#define REG_TWI1_IER (0x40090024U) /**< \brief (TWI1) Interrupt Enable Register */ +#define REG_TWI1_IDR (0x40090028U) /**< \brief (TWI1) Interrupt Disable Register */ +#define REG_TWI1_IMR (0x4009002CU) /**< \brief (TWI1) Interrupt Mask Register */ +#define REG_TWI1_RHR (0x40090030U) /**< \brief (TWI1) Receive Holding Register */ +#define REG_TWI1_THR (0x40090034U) /**< \brief (TWI1) Transmit Holding Register */ +#define REG_TWI1_RPR (0x40090100U) /**< \brief (TWI1) Receive Pointer Register */ +#define REG_TWI1_RCR (0x40090104U) /**< \brief (TWI1) Receive Counter Register */ +#define REG_TWI1_TPR (0x40090108U) /**< \brief (TWI1) Transmit Pointer Register */ +#define REG_TWI1_TCR (0x4009010CU) /**< \brief (TWI1) Transmit Counter Register */ +#define REG_TWI1_RNPR (0x40090110U) /**< \brief (TWI1) Receive Next Pointer Register */ +#define REG_TWI1_RNCR (0x40090114U) /**< \brief (TWI1) Receive Next Counter Register */ +#define REG_TWI1_TNPR (0x40090118U) /**< \brief (TWI1) Transmit Next Pointer Register */ +#define REG_TWI1_TNCR (0x4009011CU) /**< \brief (TWI1) Transmit Next Counter Register */ +#define REG_TWI1_PTCR (0x40090120U) /**< \brief (TWI1) Transfer Control Register */ +#define REG_TWI1_PTSR (0x40090124U) /**< \brief (TWI1) Transfer Status Register */ +#else +#define REG_TWI1_CR (*(WoReg*)0x40090000U) /**< \brief (TWI1) Control Register */ +#define REG_TWI1_MMR (*(RwReg*)0x40090004U) /**< \brief (TWI1) Master Mode Register */ +#define REG_TWI1_SMR (*(RwReg*)0x40090008U) /**< \brief (TWI1) Slave Mode Register */ +#define REG_TWI1_IADR (*(RwReg*)0x4009000CU) /**< \brief (TWI1) Internal Address Register */ +#define REG_TWI1_CWGR (*(RwReg*)0x40090010U) /**< \brief (TWI1) Clock Waveform Generator Register */ +#define REG_TWI1_SR (*(RoReg*)0x40090020U) /**< \brief (TWI1) Status Register */ +#define REG_TWI1_IER (*(WoReg*)0x40090024U) /**< \brief (TWI1) Interrupt Enable Register */ +#define REG_TWI1_IDR (*(WoReg*)0x40090028U) /**< \brief (TWI1) Interrupt Disable Register */ +#define REG_TWI1_IMR (*(RoReg*)0x4009002CU) /**< \brief (TWI1) Interrupt Mask Register */ +#define REG_TWI1_RHR (*(RoReg*)0x40090030U) /**< \brief (TWI1) Receive Holding Register */ +#define REG_TWI1_THR (*(WoReg*)0x40090034U) /**< \brief (TWI1) Transmit Holding Register */ +#define REG_TWI1_RPR (*(RwReg*)0x40090100U) /**< \brief (TWI1) Receive Pointer Register */ +#define REG_TWI1_RCR (*(RwReg*)0x40090104U) /**< \brief (TWI1) Receive Counter Register */ +#define REG_TWI1_TPR (*(RwReg*)0x40090108U) /**< \brief (TWI1) Transmit Pointer Register */ +#define REG_TWI1_TCR (*(RwReg*)0x4009010CU) /**< \brief (TWI1) Transmit Counter Register */ +#define REG_TWI1_RNPR (*(RwReg*)0x40090110U) /**< \brief (TWI1) Receive Next Pointer Register */ +#define REG_TWI1_RNCR (*(RwReg*)0x40090114U) /**< \brief (TWI1) Receive Next Counter Register */ +#define REG_TWI1_TNPR (*(RwReg*)0x40090118U) /**< \brief (TWI1) Transmit Next Pointer Register */ +#define REG_TWI1_TNCR (*(RwReg*)0x4009011CU) /**< \brief (TWI1) Transmit Next Counter Register */ +#define REG_TWI1_PTCR (*(WoReg*)0x40090120U) /**< \brief (TWI1) Transfer Control Register */ +#define REG_TWI1_PTSR (*(RoReg*)0x40090124U) /**< \brief (TWI1) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_TWI1_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h new file mode 100644 index 0000000..c598450 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uart.h @@ -0,0 +1,91 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_UART_INSTANCE_ +#define _SAM3XA_UART_INSTANCE_ + +/* ========== Register definition for UART peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_UART_CR (0x400E0800U) /**< \brief (UART) Control Register */ +#define REG_UART_MR (0x400E0804U) /**< \brief (UART) Mode Register */ +#define REG_UART_IER (0x400E0808U) /**< \brief (UART) Interrupt Enable Register */ +#define REG_UART_IDR (0x400E080CU) /**< \brief (UART) Interrupt Disable Register */ +#define REG_UART_IMR (0x400E0810U) /**< \brief (UART) Interrupt Mask Register */ +#define REG_UART_SR (0x400E0814U) /**< \brief (UART) Status Register */ +#define REG_UART_RHR (0x400E0818U) /**< \brief (UART) Receive Holding Register */ +#define REG_UART_THR (0x400E081CU) /**< \brief (UART) Transmit Holding Register */ +#define REG_UART_BRGR (0x400E0820U) /**< \brief (UART) Baud Rate Generator Register */ +#define REG_UART_RPR (0x400E0900U) /**< \brief (UART) Receive Pointer Register */ +#define REG_UART_RCR (0x400E0904U) /**< \brief (UART) Receive Counter Register */ +#define REG_UART_TPR (0x400E0908U) /**< \brief (UART) Transmit Pointer Register */ +#define REG_UART_TCR (0x400E090CU) /**< \brief (UART) Transmit Counter Register */ +#define REG_UART_RNPR (0x400E0910U) /**< \brief (UART) Receive Next Pointer Register */ +#define REG_UART_RNCR (0x400E0914U) /**< \brief (UART) Receive Next Counter Register */ +#define REG_UART_TNPR (0x400E0918U) /**< \brief (UART) Transmit Next Pointer Register */ +#define REG_UART_TNCR (0x400E091CU) /**< \brief (UART) Transmit Next Counter Register */ +#define REG_UART_PTCR (0x400E0920U) /**< \brief (UART) Transfer Control Register */ +#define REG_UART_PTSR (0x400E0924U) /**< \brief (UART) Transfer Status Register */ +#else +#define REG_UART_CR (*(WoReg*)0x400E0800U) /**< \brief (UART) Control Register */ +#define REG_UART_MR (*(RwReg*)0x400E0804U) /**< \brief (UART) Mode Register */ +#define REG_UART_IER (*(WoReg*)0x400E0808U) /**< \brief (UART) Interrupt Enable Register */ +#define REG_UART_IDR (*(WoReg*)0x400E080CU) /**< \brief (UART) Interrupt Disable Register */ +#define REG_UART_IMR (*(RoReg*)0x400E0810U) /**< \brief (UART) Interrupt Mask Register */ +#define REG_UART_SR (*(RoReg*)0x400E0814U) /**< \brief (UART) Status Register */ +#define REG_UART_RHR (*(RoReg*)0x400E0818U) /**< \brief (UART) Receive Holding Register */ +#define REG_UART_THR (*(WoReg*)0x400E081CU) /**< \brief (UART) Transmit Holding Register */ +#define REG_UART_BRGR (*(RwReg*)0x400E0820U) /**< \brief (UART) Baud Rate Generator Register */ +#define REG_UART_RPR (*(RwReg*)0x400E0900U) /**< \brief (UART) Receive Pointer Register */ +#define REG_UART_RCR (*(RwReg*)0x400E0904U) /**< \brief (UART) Receive Counter Register */ +#define REG_UART_TPR (*(RwReg*)0x400E0908U) /**< \brief (UART) Transmit Pointer Register */ +#define REG_UART_TCR (*(RwReg*)0x400E090CU) /**< \brief (UART) Transmit Counter Register */ +#define REG_UART_RNPR (*(RwReg*)0x400E0910U) /**< \brief (UART) Receive Next Pointer Register */ +#define REG_UART_RNCR (*(RwReg*)0x400E0914U) /**< \brief (UART) Receive Next Counter Register */ +#define REG_UART_TNPR (*(RwReg*)0x400E0918U) /**< \brief (UART) Transmit Next Pointer Register */ +#define REG_UART_TNCR (*(RwReg*)0x400E091CU) /**< \brief (UART) Transmit Next Counter Register */ +#define REG_UART_PTCR (*(WoReg*)0x400E0920U) /**< \brief (UART) Transfer Control Register */ +#define REG_UART_PTSR (*(RoReg*)0x400E0924U) /**< \brief (UART) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_UART_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h new file mode 100644 index 0000000..145ddfb --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_uotghs.h @@ -0,0 +1,249 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_UOTGHS_INSTANCE_ +#define _SAM3XA_UOTGHS_INSTANCE_ + +/* ========== Register definition for UOTGHS peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_UOTGHS_DEVCTRL (0x400AC000U) /**< \brief (UOTGHS) Device General Control Register */ +#define REG_UOTGHS_DEVISR (0x400AC004U) /**< \brief (UOTGHS) Device Global Interrupt Status Register */ +#define REG_UOTGHS_DEVICR (0x400AC008U) /**< \brief (UOTGHS) Device Global Interrupt Clear Register */ +#define REG_UOTGHS_DEVIFR (0x400AC00CU) /**< \brief (UOTGHS) Device Global Interrupt Set Register */ +#define REG_UOTGHS_DEVIMR (0x400AC010U) /**< \brief (UOTGHS) Device Global Interrupt Mask Register */ +#define REG_UOTGHS_DEVIDR (0x400AC014U) /**< \brief (UOTGHS) Device Global Interrupt Disable Register */ +#define REG_UOTGHS_DEVIER (0x400AC018U) /**< \brief (UOTGHS) Device Global Interrupt Enable Register */ +#define REG_UOTGHS_DEVEPT (0x400AC01CU) /**< \brief (UOTGHS) Device Endpoint Register */ +#define REG_UOTGHS_DEVFNUM (0x400AC020U) /**< \brief (UOTGHS) Device Frame Number Register */ +#define REG_UOTGHS_DEVEPTCFG (0x400AC100U) /**< \brief (UOTGHS) Device Endpoint Configuration Register (n = 0) */ +#define REG_UOTGHS_DEVEPTISR (0x400AC130U) /**< \brief (UOTGHS) Device Endpoint Status Register (n = 0) */ +#define REG_UOTGHS_DEVEPTICR (0x400AC160U) /**< \brief (UOTGHS) Device Endpoint Clear Register (n = 0) */ +#define REG_UOTGHS_DEVEPTIFR (0x400AC190U) /**< \brief (UOTGHS) Device Endpoint Set Register (n = 0) */ +#define REG_UOTGHS_DEVEPTIMR (0x400AC1C0U) /**< \brief (UOTGHS) Device Endpoint Mask Register (n = 0) */ +#define REG_UOTGHS_DEVEPTIER (0x400AC1F0U) /**< \brief (UOTGHS) Device Endpoint Enable Register (n = 0) */ +#define REG_UOTGHS_DEVEPTIDR (0x400AC220U) /**< \brief (UOTGHS) Device Endpoint Disable Register (n = 0) */ +#define REG_UOTGHS_DEVDMANXTDSC1 (0x400AC310U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 1) */ +#define REG_UOTGHS_DEVDMAADDRESS1 (0x400AC314U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 1) */ +#define REG_UOTGHS_DEVDMACONTROL1 (0x400AC318U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 1) */ +#define REG_UOTGHS_DEVDMASTATUS1 (0x400AC31CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 1) */ +#define REG_UOTGHS_DEVDMANXTDSC2 (0x400AC320U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 2) */ +#define REG_UOTGHS_DEVDMAADDRESS2 (0x400AC324U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 2) */ +#define REG_UOTGHS_DEVDMACONTROL2 (0x400AC328U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 2) */ +#define REG_UOTGHS_DEVDMASTATUS2 (0x400AC32CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 2) */ +#define REG_UOTGHS_DEVDMANXTDSC3 (0x400AC330U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 3) */ +#define REG_UOTGHS_DEVDMAADDRESS3 (0x400AC334U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 3) */ +#define REG_UOTGHS_DEVDMACONTROL3 (0x400AC338U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 3) */ +#define REG_UOTGHS_DEVDMASTATUS3 (0x400AC33CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 3) */ +#define REG_UOTGHS_DEVDMANXTDSC4 (0x400AC340U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 4) */ +#define REG_UOTGHS_DEVDMAADDRESS4 (0x400AC344U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 4) */ +#define REG_UOTGHS_DEVDMACONTROL4 (0x400AC348U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 4) */ +#define REG_UOTGHS_DEVDMASTATUS4 (0x400AC34CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 4) */ +#define REG_UOTGHS_DEVDMANXTDSC5 (0x400AC350U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 5) */ +#define REG_UOTGHS_DEVDMAADDRESS5 (0x400AC354U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 5) */ +#define REG_UOTGHS_DEVDMACONTROL5 (0x400AC358U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 5) */ +#define REG_UOTGHS_DEVDMASTATUS5 (0x400AC35CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 5) */ +#define REG_UOTGHS_DEVDMANXTDSC6 (0x400AC360U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 6) */ +#define REG_UOTGHS_DEVDMAADDRESS6 (0x400AC364U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 6) */ +#define REG_UOTGHS_DEVDMACONTROL6 (0x400AC368U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 6) */ +#define REG_UOTGHS_DEVDMASTATUS6 (0x400AC36CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 6) */ +#define REG_UOTGHS_DEVDMANXTDSC7 (0x400AC370U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 7) */ +#define REG_UOTGHS_DEVDMAADDRESS7 (0x400AC374U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 7) */ +#define REG_UOTGHS_DEVDMACONTROL7 (0x400AC378U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 7) */ +#define REG_UOTGHS_DEVDMASTATUS7 (0x400AC37CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 7) */ +#define REG_UOTGHS_HSTCTRL (0x400AC400U) /**< \brief (UOTGHS) Host General Control Register */ +#define REG_UOTGHS_HSTISR (0x400AC404U) /**< \brief (UOTGHS) Host Global Interrupt Status Register */ +#define REG_UOTGHS_HSTICR (0x400AC408U) /**< \brief (UOTGHS) Host Global Interrupt Clear Register */ +#define REG_UOTGHS_HSTIFR (0x400AC40CU) /**< \brief (UOTGHS) Host Global Interrupt Set Register */ +#define REG_UOTGHS_HSTIMR (0x400AC410U) /**< \brief (UOTGHS) Host Global Interrupt Mask Register */ +#define REG_UOTGHS_HSTIDR (0x400AC414U) /**< \brief (UOTGHS) Host Global Interrupt Disable Register */ +#define REG_UOTGHS_HSTIER (0x400AC418U) /**< \brief (UOTGHS) Host Global Interrupt Enable Register */ +#define REG_UOTGHS_HSTPIP (0x400AC41CU) /**< \brief (UOTGHS) Host Pipe Register */ +#define REG_UOTGHS_HSTFNUM (0x400AC420U) /**< \brief (UOTGHS) Host Frame Number Register */ +#define REG_UOTGHS_HSTADDR1 (0x400AC424U) /**< \brief (UOTGHS) Host Address 1 Register */ +#define REG_UOTGHS_HSTADDR2 (0x400AC428U) /**< \brief (UOTGHS) Host Address 2 Register */ +#define REG_UOTGHS_HSTADDR3 (0x400AC42CU) /**< \brief (UOTGHS) Host Address 3 Register */ +#define REG_UOTGHS_HSTPIPCFG (0x400AC500U) /**< \brief (UOTGHS) Host Pipe Configuration Register (n = 0) */ +#define REG_UOTGHS_HSTPIPISR (0x400AC530U) /**< \brief (UOTGHS) Host Pipe Status Register (n = 0) */ +#define REG_UOTGHS_HSTPIPICR (0x400AC560U) /**< \brief (UOTGHS) Host Pipe Clear Register (n = 0) */ +#define REG_UOTGHS_HSTPIPIFR (0x400AC590U) /**< \brief (UOTGHS) Host Pipe Set Register (n = 0) */ +#define REG_UOTGHS_HSTPIPIMR (0x400AC5C0U) /**< \brief (UOTGHS) Host Pipe Mask Register (n = 0) */ +#define REG_UOTGHS_HSTPIPIER (0x400AC5F0U) /**< \brief (UOTGHS) Host Pipe Enable Register (n = 0) */ +#define REG_UOTGHS_HSTPIPIDR (0x400AC620U) /**< \brief (UOTGHS) Host Pipe Disable Register (n = 0) */ +#define REG_UOTGHS_HSTPIPINRQ (0x400AC650U) /**< \brief (UOTGHS) Host Pipe IN Request Register (n = 0) */ +#define REG_UOTGHS_HSTPIPERR (0x400AC680U) /**< \brief (UOTGHS) Host Pipe Error Register (n = 0) */ +#define REG_UOTGHS_HSTDMANXTDSC1 (0x400AC710U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 1) */ +#define REG_UOTGHS_HSTDMAADDRESS1 (0x400AC714U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 1) */ +#define REG_UOTGHS_HSTDMACONTROL1 (0x400AC718U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 1) */ +#define REG_UOTGHS_HSTDMASTATUS1 (0x400AC71CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 1) */ +#define REG_UOTGHS_HSTDMANXTDSC2 (0x400AC720U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 2) */ +#define REG_UOTGHS_HSTDMAADDRESS2 (0x400AC724U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 2) */ +#define REG_UOTGHS_HSTDMACONTROL2 (0x400AC728U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 2) */ +#define REG_UOTGHS_HSTDMASTATUS2 (0x400AC72CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 2) */ +#define REG_UOTGHS_HSTDMANXTDSC3 (0x400AC730U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 3) */ +#define REG_UOTGHS_HSTDMAADDRESS3 (0x400AC734U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 3) */ +#define REG_UOTGHS_HSTDMACONTROL3 (0x400AC738U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 3) */ +#define REG_UOTGHS_HSTDMASTATUS3 (0x400AC73CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 3) */ +#define REG_UOTGHS_HSTDMANXTDSC4 (0x400AC740U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 4) */ +#define REG_UOTGHS_HSTDMAADDRESS4 (0x400AC744U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 4) */ +#define REG_UOTGHS_HSTDMACONTROL4 (0x400AC748U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 4) */ +#define REG_UOTGHS_HSTDMASTATUS4 (0x400AC74CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 4) */ +#define REG_UOTGHS_HSTDMANXTDSC5 (0x400AC750U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 5) */ +#define REG_UOTGHS_HSTDMAADDRESS5 (0x400AC754U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 5) */ +#define REG_UOTGHS_HSTDMACONTROL5 (0x400AC758U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 5) */ +#define REG_UOTGHS_HSTDMASTATUS5 (0x400AC75CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 5) */ +#define REG_UOTGHS_HSTDMANXTDSC6 (0x400AC760U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 6) */ +#define REG_UOTGHS_HSTDMAADDRESS6 (0x400AC764U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 6) */ +#define REG_UOTGHS_HSTDMACONTROL6 (0x400AC768U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 6) */ +#define REG_UOTGHS_HSTDMASTATUS6 (0x400AC76CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 6) */ +#define REG_UOTGHS_HSTDMANXTDSC7 (0x400AC770U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 7) */ +#define REG_UOTGHS_HSTDMAADDRESS7 (0x400AC774U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 7) */ +#define REG_UOTGHS_HSTDMACONTROL7 (0x400AC778U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 7) */ +#define REG_UOTGHS_HSTDMASTATUS7 (0x400AC77CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 7) */ +#define REG_UOTGHS_CTRL (0x400AC800U) /**< \brief (UOTGHS) General Control Register */ +#define REG_UOTGHS_SR (0x400AC804U) /**< \brief (UOTGHS) General Status Register */ +#define REG_UOTGHS_SCR (0x400AC808U) /**< \brief (UOTGHS) General Status Clear Register */ +#define REG_UOTGHS_SFR (0x400AC80CU) /**< \brief (UOTGHS) General Status Set Register */ +#define REG_UOTGHS_FSM (0x400AC82CU) /**< \brief (UOTGHS) General Finite State Machine Register */ +#else +#define REG_UOTGHS_DEVCTRL (*(RwReg*)0x400AC000U) /**< \brief (UOTGHS) Device General Control Register */ +#define REG_UOTGHS_DEVISR (*(RoReg*)0x400AC004U) /**< \brief (UOTGHS) Device Global Interrupt Status Register */ +#define REG_UOTGHS_DEVICR (*(WoReg*)0x400AC008U) /**< \brief (UOTGHS) Device Global Interrupt Clear Register */ +#define REG_UOTGHS_DEVIFR (*(WoReg*)0x400AC00CU) /**< \brief (UOTGHS) Device Global Interrupt Set Register */ +#define REG_UOTGHS_DEVIMR (*(RoReg*)0x400AC010U) /**< \brief (UOTGHS) Device Global Interrupt Mask Register */ +#define REG_UOTGHS_DEVIDR (*(WoReg*)0x400AC014U) /**< \brief (UOTGHS) Device Global Interrupt Disable Register */ +#define REG_UOTGHS_DEVIER (*(WoReg*)0x400AC018U) /**< \brief (UOTGHS) Device Global Interrupt Enable Register */ +#define REG_UOTGHS_DEVEPT (*(RwReg*)0x400AC01CU) /**< \brief (UOTGHS) Device Endpoint Register */ +#define REG_UOTGHS_DEVFNUM (*(RoReg*)0x400AC020U) /**< \brief (UOTGHS) Device Frame Number Register */ +#define REG_UOTGHS_DEVEPTCFG (*(RwReg*)0x400AC100U) /**< \brief (UOTGHS) Device Endpoint Configuration Register (n = 0) */ +#define REG_UOTGHS_DEVEPTISR (*(RoReg*)0x400AC130U) /**< \brief (UOTGHS) Device Endpoint Status Register (n = 0) */ +#define REG_UOTGHS_DEVEPTICR (*(WoReg*)0x400AC160U) /**< \brief (UOTGHS) Device Endpoint Clear Register (n = 0) */ +#define REG_UOTGHS_DEVEPTIFR (*(WoReg*)0x400AC190U) /**< \brief (UOTGHS) Device Endpoint Set Register (n = 0) */ +#define REG_UOTGHS_DEVEPTIMR (*(RoReg*)0x400AC1C0U) /**< \brief (UOTGHS) Device Endpoint Mask Register (n = 0) */ +#define REG_UOTGHS_DEVEPTIER (*(WoReg*)0x400AC1F0U) /**< \brief (UOTGHS) Device Endpoint Enable Register (n = 0) */ +#define REG_UOTGHS_DEVEPTIDR (*(WoReg*)0x400AC220U) /**< \brief (UOTGHS) Device Endpoint Disable Register (n = 0) */ +#define REG_UOTGHS_DEVDMANXTDSC1 (*(RwReg*)0x400AC310U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 1) */ +#define REG_UOTGHS_DEVDMAADDRESS1 (*(RwReg*)0x400AC314U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 1) */ +#define REG_UOTGHS_DEVDMACONTROL1 (*(RwReg*)0x400AC318U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 1) */ +#define REG_UOTGHS_DEVDMASTATUS1 (*(RwReg*)0x400AC31CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 1) */ +#define REG_UOTGHS_DEVDMANXTDSC2 (*(RwReg*)0x400AC320U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 2) */ +#define REG_UOTGHS_DEVDMAADDRESS2 (*(RwReg*)0x400AC324U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 2) */ +#define REG_UOTGHS_DEVDMACONTROL2 (*(RwReg*)0x400AC328U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 2) */ +#define REG_UOTGHS_DEVDMASTATUS2 (*(RwReg*)0x400AC32CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 2) */ +#define REG_UOTGHS_DEVDMANXTDSC3 (*(RwReg*)0x400AC330U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 3) */ +#define REG_UOTGHS_DEVDMAADDRESS3 (*(RwReg*)0x400AC334U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 3) */ +#define REG_UOTGHS_DEVDMACONTROL3 (*(RwReg*)0x400AC338U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 3) */ +#define REG_UOTGHS_DEVDMASTATUS3 (*(RwReg*)0x400AC33CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 3) */ +#define REG_UOTGHS_DEVDMANXTDSC4 (*(RwReg*)0x400AC340U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 4) */ +#define REG_UOTGHS_DEVDMAADDRESS4 (*(RwReg*)0x400AC344U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 4) */ +#define REG_UOTGHS_DEVDMACONTROL4 (*(RwReg*)0x400AC348U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 4) */ +#define REG_UOTGHS_DEVDMASTATUS4 (*(RwReg*)0x400AC34CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 4) */ +#define REG_UOTGHS_DEVDMANXTDSC5 (*(RwReg*)0x400AC350U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 5) */ +#define REG_UOTGHS_DEVDMAADDRESS5 (*(RwReg*)0x400AC354U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 5) */ +#define REG_UOTGHS_DEVDMACONTROL5 (*(RwReg*)0x400AC358U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 5) */ +#define REG_UOTGHS_DEVDMASTATUS5 (*(RwReg*)0x400AC35CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 5) */ +#define REG_UOTGHS_DEVDMANXTDSC6 (*(RwReg*)0x400AC360U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 6) */ +#define REG_UOTGHS_DEVDMAADDRESS6 (*(RwReg*)0x400AC364U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 6) */ +#define REG_UOTGHS_DEVDMACONTROL6 (*(RwReg*)0x400AC368U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 6) */ +#define REG_UOTGHS_DEVDMASTATUS6 (*(RwReg*)0x400AC36CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 6) */ +#define REG_UOTGHS_DEVDMANXTDSC7 (*(RwReg*)0x400AC370U) /**< \brief (UOTGHS) Device DMA Channel Next Descriptor Address Register (n = 7) */ +#define REG_UOTGHS_DEVDMAADDRESS7 (*(RwReg*)0x400AC374U) /**< \brief (UOTGHS) Device DMA Channel Address Register (n = 7) */ +#define REG_UOTGHS_DEVDMACONTROL7 (*(RwReg*)0x400AC378U) /**< \brief (UOTGHS) Device DMA Channel Control Register (n = 7) */ +#define REG_UOTGHS_DEVDMASTATUS7 (*(RwReg*)0x400AC37CU) /**< \brief (UOTGHS) Device DMA Channel Status Register (n = 7) */ +#define REG_UOTGHS_HSTCTRL (*(RwReg*)0x400AC400U) /**< \brief (UOTGHS) Host General Control Register */ +#define REG_UOTGHS_HSTISR (*(RoReg*)0x400AC404U) /**< \brief (UOTGHS) Host Global Interrupt Status Register */ +#define REG_UOTGHS_HSTICR (*(WoReg*)0x400AC408U) /**< \brief (UOTGHS) Host Global Interrupt Clear Register */ +#define REG_UOTGHS_HSTIFR (*(WoReg*)0x400AC40CU) /**< \brief (UOTGHS) Host Global Interrupt Set Register */ +#define REG_UOTGHS_HSTIMR (*(RoReg*)0x400AC410U) /**< \brief (UOTGHS) Host Global Interrupt Mask Register */ +#define REG_UOTGHS_HSTIDR (*(WoReg*)0x400AC414U) /**< \brief (UOTGHS) Host Global Interrupt Disable Register */ +#define REG_UOTGHS_HSTIER (*(WoReg*)0x400AC418U) /**< \brief (UOTGHS) Host Global Interrupt Enable Register */ +#define REG_UOTGHS_HSTPIP (*(RwReg*)0x400AC41CU) /**< \brief (UOTGHS) Host Pipe Register */ +#define REG_UOTGHS_HSTFNUM (*(RwReg*)0x400AC420U) /**< \brief (UOTGHS) Host Frame Number Register */ +#define REG_UOTGHS_HSTADDR1 (*(RwReg*)0x400AC424U) /**< \brief (UOTGHS) Host Address 1 Register */ +#define REG_UOTGHS_HSTADDR2 (*(RwReg*)0x400AC428U) /**< \brief (UOTGHS) Host Address 2 Register */ +#define REG_UOTGHS_HSTADDR3 (*(RwReg*)0x400AC42CU) /**< \brief (UOTGHS) Host Address 3 Register */ +#define REG_UOTGHS_HSTPIPCFG (*(RwReg*)0x400AC500U) /**< \brief (UOTGHS) Host Pipe Configuration Register (n = 0) */ +#define REG_UOTGHS_HSTPIPISR (*(RoReg*)0x400AC530U) /**< \brief (UOTGHS) Host Pipe Status Register (n = 0) */ +#define REG_UOTGHS_HSTPIPICR (*(WoReg*)0x400AC560U) /**< \brief (UOTGHS) Host Pipe Clear Register (n = 0) */ +#define REG_UOTGHS_HSTPIPIFR (*(WoReg*)0x400AC590U) /**< \brief (UOTGHS) Host Pipe Set Register (n = 0) */ +#define REG_UOTGHS_HSTPIPIMR (*(RoReg*)0x400AC5C0U) /**< \brief (UOTGHS) Host Pipe Mask Register (n = 0) */ +#define REG_UOTGHS_HSTPIPIER (*(WoReg*)0x400AC5F0U) /**< \brief (UOTGHS) Host Pipe Enable Register (n = 0) */ +#define REG_UOTGHS_HSTPIPIDR (*(WoReg*)0x400AC620U) /**< \brief (UOTGHS) Host Pipe Disable Register (n = 0) */ +#define REG_UOTGHS_HSTPIPINRQ (*(RwReg*)0x400AC650U) /**< \brief (UOTGHS) Host Pipe IN Request Register (n = 0) */ +#define REG_UOTGHS_HSTPIPERR (*(RwReg*)0x400AC680U) /**< \brief (UOTGHS) Host Pipe Error Register (n = 0) */ +#define REG_UOTGHS_HSTDMANXTDSC1 (*(RwReg*)0x400AC710U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 1) */ +#define REG_UOTGHS_HSTDMAADDRESS1 (*(RwReg*)0x400AC714U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 1) */ +#define REG_UOTGHS_HSTDMACONTROL1 (*(RwReg*)0x400AC718U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 1) */ +#define REG_UOTGHS_HSTDMASTATUS1 (*(RwReg*)0x400AC71CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 1) */ +#define REG_UOTGHS_HSTDMANXTDSC2 (*(RwReg*)0x400AC720U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 2) */ +#define REG_UOTGHS_HSTDMAADDRESS2 (*(RwReg*)0x400AC724U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 2) */ +#define REG_UOTGHS_HSTDMACONTROL2 (*(RwReg*)0x400AC728U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 2) */ +#define REG_UOTGHS_HSTDMASTATUS2 (*(RwReg*)0x400AC72CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 2) */ +#define REG_UOTGHS_HSTDMANXTDSC3 (*(RwReg*)0x400AC730U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 3) */ +#define REG_UOTGHS_HSTDMAADDRESS3 (*(RwReg*)0x400AC734U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 3) */ +#define REG_UOTGHS_HSTDMACONTROL3 (*(RwReg*)0x400AC738U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 3) */ +#define REG_UOTGHS_HSTDMASTATUS3 (*(RwReg*)0x400AC73CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 3) */ +#define REG_UOTGHS_HSTDMANXTDSC4 (*(RwReg*)0x400AC740U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 4) */ +#define REG_UOTGHS_HSTDMAADDRESS4 (*(RwReg*)0x400AC744U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 4) */ +#define REG_UOTGHS_HSTDMACONTROL4 (*(RwReg*)0x400AC748U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 4) */ +#define REG_UOTGHS_HSTDMASTATUS4 (*(RwReg*)0x400AC74CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 4) */ +#define REG_UOTGHS_HSTDMANXTDSC5 (*(RwReg*)0x400AC750U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 5) */ +#define REG_UOTGHS_HSTDMAADDRESS5 (*(RwReg*)0x400AC754U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 5) */ +#define REG_UOTGHS_HSTDMACONTROL5 (*(RwReg*)0x400AC758U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 5) */ +#define REG_UOTGHS_HSTDMASTATUS5 (*(RwReg*)0x400AC75CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 5) */ +#define REG_UOTGHS_HSTDMANXTDSC6 (*(RwReg*)0x400AC760U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 6) */ +#define REG_UOTGHS_HSTDMAADDRESS6 (*(RwReg*)0x400AC764U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 6) */ +#define REG_UOTGHS_HSTDMACONTROL6 (*(RwReg*)0x400AC768U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 6) */ +#define REG_UOTGHS_HSTDMASTATUS6 (*(RwReg*)0x400AC76CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 6) */ +#define REG_UOTGHS_HSTDMANXTDSC7 (*(RwReg*)0x400AC770U) /**< \brief (UOTGHS) Host DMA Channel Next Descriptor Address Register (n = 7) */ +#define REG_UOTGHS_HSTDMAADDRESS7 (*(RwReg*)0x400AC774U) /**< \brief (UOTGHS) Host DMA Channel Address Register (n = 7) */ +#define REG_UOTGHS_HSTDMACONTROL7 (*(RwReg*)0x400AC778U) /**< \brief (UOTGHS) Host DMA Channel Control Register (n = 7) */ +#define REG_UOTGHS_HSTDMASTATUS7 (*(RwReg*)0x400AC77CU) /**< \brief (UOTGHS) Host DMA Channel Status Register (n = 7) */ +#define REG_UOTGHS_CTRL (*(RwReg*)0x400AC800U) /**< \brief (UOTGHS) General Control Register */ +#define REG_UOTGHS_SR (*(RoReg*)0x400AC804U) /**< \brief (UOTGHS) General Status Register */ +#define REG_UOTGHS_SCR (*(WoReg*)0x400AC808U) /**< \brief (UOTGHS) General Status Clear Register */ +#define REG_UOTGHS_SFR (*(WoReg*)0x400AC80CU) /**< \brief (UOTGHS) General Status Set Register */ +#define REG_UOTGHS_FSM (*(RoReg*)0x400AC82CU) /**< \brief (UOTGHS) General Finite State Machine Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_UOTGHS_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h new file mode 100644 index 0000000..ab4dc5a --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart0.h @@ -0,0 +1,111 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_USART0_INSTANCE_ +#define _SAM3XA_USART0_INSTANCE_ + +/* ========== Register definition for USART0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_USART0_CR (0x40098000U) /**< \brief (USART0) Control Register */ +#define REG_USART0_MR (0x40098004U) /**< \brief (USART0) Mode Register */ +#define REG_USART0_IER (0x40098008U) /**< \brief (USART0) Interrupt Enable Register */ +#define REG_USART0_IDR (0x4009800CU) /**< \brief (USART0) Interrupt Disable Register */ +#define REG_USART0_IMR (0x40098010U) /**< \brief (USART0) Interrupt Mask Register */ +#define REG_USART0_CSR (0x40098014U) /**< \brief (USART0) Channel Status Register */ +#define REG_USART0_RHR (0x40098018U) /**< \brief (USART0) Receiver Holding Register */ +#define REG_USART0_THR (0x4009801CU) /**< \brief (USART0) Transmitter Holding Register */ +#define REG_USART0_BRGR (0x40098020U) /**< \brief (USART0) Baud Rate Generator Register */ +#define REG_USART0_RTOR (0x40098024U) /**< \brief (USART0) Receiver Time-out Register */ +#define REG_USART0_TTGR (0x40098028U) /**< \brief (USART0) Transmitter Timeguard Register */ +#define REG_USART0_FIDI (0x40098040U) /**< \brief (USART0) FI DI Ratio Register */ +#define REG_USART0_NER (0x40098044U) /**< \brief (USART0) Number of Errors Register */ +#define REG_USART0_IF (0x4009804CU) /**< \brief (USART0) IrDA Filter Register */ +#define REG_USART0_MAN (0x40098050U) /**< \brief (USART0) Manchester Encoder Decoder Register */ +#define REG_USART0_LINMR (0x40098054U) /**< \brief (USART0) LIN Mode Register */ +#define REG_USART0_LINIR (0x40098058U) /**< \brief (USART0) LIN Identifier Register */ +#define REG_USART0_WPMR (0x400980E4U) /**< \brief (USART0) Write Protect Mode Register */ +#define REG_USART0_WPSR (0x400980E8U) /**< \brief (USART0) Write Protect Status Register */ +#define REG_USART0_RPR (0x40098100U) /**< \brief (USART0) Receive Pointer Register */ +#define REG_USART0_RCR (0x40098104U) /**< \brief (USART0) Receive Counter Register */ +#define REG_USART0_TPR (0x40098108U) /**< \brief (USART0) Transmit Pointer Register */ +#define REG_USART0_TCR (0x4009810CU) /**< \brief (USART0) Transmit Counter Register */ +#define REG_USART0_RNPR (0x40098110U) /**< \brief (USART0) Receive Next Pointer Register */ +#define REG_USART0_RNCR (0x40098114U) /**< \brief (USART0) Receive Next Counter Register */ +#define REG_USART0_TNPR (0x40098118U) /**< \brief (USART0) Transmit Next Pointer Register */ +#define REG_USART0_TNCR (0x4009811CU) /**< \brief (USART0) Transmit Next Counter Register */ +#define REG_USART0_PTCR (0x40098120U) /**< \brief (USART0) Transfer Control Register */ +#define REG_USART0_PTSR (0x40098124U) /**< \brief (USART0) Transfer Status Register */ +#else +#define REG_USART0_CR (*(WoReg*)0x40098000U) /**< \brief (USART0) Control Register */ +#define REG_USART0_MR (*(RwReg*)0x40098004U) /**< \brief (USART0) Mode Register */ +#define REG_USART0_IER (*(WoReg*)0x40098008U) /**< \brief (USART0) Interrupt Enable Register */ +#define REG_USART0_IDR (*(WoReg*)0x4009800CU) /**< \brief (USART0) Interrupt Disable Register */ +#define REG_USART0_IMR (*(RoReg*)0x40098010U) /**< \brief (USART0) Interrupt Mask Register */ +#define REG_USART0_CSR (*(RoReg*)0x40098014U) /**< \brief (USART0) Channel Status Register */ +#define REG_USART0_RHR (*(RoReg*)0x40098018U) /**< \brief (USART0) Receiver Holding Register */ +#define REG_USART0_THR (*(WoReg*)0x4009801CU) /**< \brief (USART0) Transmitter Holding Register */ +#define REG_USART0_BRGR (*(RwReg*)0x40098020U) /**< \brief (USART0) Baud Rate Generator Register */ +#define REG_USART0_RTOR (*(RwReg*)0x40098024U) /**< \brief (USART0) Receiver Time-out Register */ +#define REG_USART0_TTGR (*(RwReg*)0x40098028U) /**< \brief (USART0) Transmitter Timeguard Register */ +#define REG_USART0_FIDI (*(RwReg*)0x40098040U) /**< \brief (USART0) FI DI Ratio Register */ +#define REG_USART0_NER (*(RoReg*)0x40098044U) /**< \brief (USART0) Number of Errors Register */ +#define REG_USART0_IF (*(RwReg*)0x4009804CU) /**< \brief (USART0) IrDA Filter Register */ +#define REG_USART0_MAN (*(RwReg*)0x40098050U) /**< \brief (USART0) Manchester Encoder Decoder Register */ +#define REG_USART0_LINMR (*(RwReg*)0x40098054U) /**< \brief (USART0) LIN Mode Register */ +#define REG_USART0_LINIR (*(RwReg*)0x40098058U) /**< \brief (USART0) LIN Identifier Register */ +#define REG_USART0_WPMR (*(RwReg*)0x400980E4U) /**< \brief (USART0) Write Protect Mode Register */ +#define REG_USART0_WPSR (*(RoReg*)0x400980E8U) /**< \brief (USART0) Write Protect Status Register */ +#define REG_USART0_RPR (*(RwReg*)0x40098100U) /**< \brief (USART0) Receive Pointer Register */ +#define REG_USART0_RCR (*(RwReg*)0x40098104U) /**< \brief (USART0) Receive Counter Register */ +#define REG_USART0_TPR (*(RwReg*)0x40098108U) /**< \brief (USART0) Transmit Pointer Register */ +#define REG_USART0_TCR (*(RwReg*)0x4009810CU) /**< \brief (USART0) Transmit Counter Register */ +#define REG_USART0_RNPR (*(RwReg*)0x40098110U) /**< \brief (USART0) Receive Next Pointer Register */ +#define REG_USART0_RNCR (*(RwReg*)0x40098114U) /**< \brief (USART0) Receive Next Counter Register */ +#define REG_USART0_TNPR (*(RwReg*)0x40098118U) /**< \brief (USART0) Transmit Next Pointer Register */ +#define REG_USART0_TNCR (*(RwReg*)0x4009811CU) /**< \brief (USART0) Transmit Next Counter Register */ +#define REG_USART0_PTCR (*(WoReg*)0x40098120U) /**< \brief (USART0) Transfer Control Register */ +#define REG_USART0_PTSR (*(RoReg*)0x40098124U) /**< \brief (USART0) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_USART0_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h new file mode 100644 index 0000000..f4bae1b --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart1.h @@ -0,0 +1,111 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_USART1_INSTANCE_ +#define _SAM3XA_USART1_INSTANCE_ + +/* ========== Register definition for USART1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_USART1_CR (0x4009C000U) /**< \brief (USART1) Control Register */ +#define REG_USART1_MR (0x4009C004U) /**< \brief (USART1) Mode Register */ +#define REG_USART1_IER (0x4009C008U) /**< \brief (USART1) Interrupt Enable Register */ +#define REG_USART1_IDR (0x4009C00CU) /**< \brief (USART1) Interrupt Disable Register */ +#define REG_USART1_IMR (0x4009C010U) /**< \brief (USART1) Interrupt Mask Register */ +#define REG_USART1_CSR (0x4009C014U) /**< \brief (USART1) Channel Status Register */ +#define REG_USART1_RHR (0x4009C018U) /**< \brief (USART1) Receiver Holding Register */ +#define REG_USART1_THR (0x4009C01CU) /**< \brief (USART1) Transmitter Holding Register */ +#define REG_USART1_BRGR (0x4009C020U) /**< \brief (USART1) Baud Rate Generator Register */ +#define REG_USART1_RTOR (0x4009C024U) /**< \brief (USART1) Receiver Time-out Register */ +#define REG_USART1_TTGR (0x4009C028U) /**< \brief (USART1) Transmitter Timeguard Register */ +#define REG_USART1_FIDI (0x4009C040U) /**< \brief (USART1) FI DI Ratio Register */ +#define REG_USART1_NER (0x4009C044U) /**< \brief (USART1) Number of Errors Register */ +#define REG_USART1_IF (0x4009C04CU) /**< \brief (USART1) IrDA Filter Register */ +#define REG_USART1_MAN (0x4009C050U) /**< \brief (USART1) Manchester Encoder Decoder Register */ +#define REG_USART1_LINMR (0x4009C054U) /**< \brief (USART1) LIN Mode Register */ +#define REG_USART1_LINIR (0x4009C058U) /**< \brief (USART1) LIN Identifier Register */ +#define REG_USART1_WPMR (0x4009C0E4U) /**< \brief (USART1) Write Protect Mode Register */ +#define REG_USART1_WPSR (0x4009C0E8U) /**< \brief (USART1) Write Protect Status Register */ +#define REG_USART1_RPR (0x4009C100U) /**< \brief (USART1) Receive Pointer Register */ +#define REG_USART1_RCR (0x4009C104U) /**< \brief (USART1) Receive Counter Register */ +#define REG_USART1_TPR (0x4009C108U) /**< \brief (USART1) Transmit Pointer Register */ +#define REG_USART1_TCR (0x4009C10CU) /**< \brief (USART1) Transmit Counter Register */ +#define REG_USART1_RNPR (0x4009C110U) /**< \brief (USART1) Receive Next Pointer Register */ +#define REG_USART1_RNCR (0x4009C114U) /**< \brief (USART1) Receive Next Counter Register */ +#define REG_USART1_TNPR (0x4009C118U) /**< \brief (USART1) Transmit Next Pointer Register */ +#define REG_USART1_TNCR (0x4009C11CU) /**< \brief (USART1) Transmit Next Counter Register */ +#define REG_USART1_PTCR (0x4009C120U) /**< \brief (USART1) Transfer Control Register */ +#define REG_USART1_PTSR (0x4009C124U) /**< \brief (USART1) Transfer Status Register */ +#else +#define REG_USART1_CR (*(WoReg*)0x4009C000U) /**< \brief (USART1) Control Register */ +#define REG_USART1_MR (*(RwReg*)0x4009C004U) /**< \brief (USART1) Mode Register */ +#define REG_USART1_IER (*(WoReg*)0x4009C008U) /**< \brief (USART1) Interrupt Enable Register */ +#define REG_USART1_IDR (*(WoReg*)0x4009C00CU) /**< \brief (USART1) Interrupt Disable Register */ +#define REG_USART1_IMR (*(RoReg*)0x4009C010U) /**< \brief (USART1) Interrupt Mask Register */ +#define REG_USART1_CSR (*(RoReg*)0x4009C014U) /**< \brief (USART1) Channel Status Register */ +#define REG_USART1_RHR (*(RoReg*)0x4009C018U) /**< \brief (USART1) Receiver Holding Register */ +#define REG_USART1_THR (*(WoReg*)0x4009C01CU) /**< \brief (USART1) Transmitter Holding Register */ +#define REG_USART1_BRGR (*(RwReg*)0x4009C020U) /**< \brief (USART1) Baud Rate Generator Register */ +#define REG_USART1_RTOR (*(RwReg*)0x4009C024U) /**< \brief (USART1) Receiver Time-out Register */ +#define REG_USART1_TTGR (*(RwReg*)0x4009C028U) /**< \brief (USART1) Transmitter Timeguard Register */ +#define REG_USART1_FIDI (*(RwReg*)0x4009C040U) /**< \brief (USART1) FI DI Ratio Register */ +#define REG_USART1_NER (*(RoReg*)0x4009C044U) /**< \brief (USART1) Number of Errors Register */ +#define REG_USART1_IF (*(RwReg*)0x4009C04CU) /**< \brief (USART1) IrDA Filter Register */ +#define REG_USART1_MAN (*(RwReg*)0x4009C050U) /**< \brief (USART1) Manchester Encoder Decoder Register */ +#define REG_USART1_LINMR (*(RwReg*)0x4009C054U) /**< \brief (USART1) LIN Mode Register */ +#define REG_USART1_LINIR (*(RwReg*)0x4009C058U) /**< \brief (USART1) LIN Identifier Register */ +#define REG_USART1_WPMR (*(RwReg*)0x4009C0E4U) /**< \brief (USART1) Write Protect Mode Register */ +#define REG_USART1_WPSR (*(RoReg*)0x4009C0E8U) /**< \brief (USART1) Write Protect Status Register */ +#define REG_USART1_RPR (*(RwReg*)0x4009C100U) /**< \brief (USART1) Receive Pointer Register */ +#define REG_USART1_RCR (*(RwReg*)0x4009C104U) /**< \brief (USART1) Receive Counter Register */ +#define REG_USART1_TPR (*(RwReg*)0x4009C108U) /**< \brief (USART1) Transmit Pointer Register */ +#define REG_USART1_TCR (*(RwReg*)0x4009C10CU) /**< \brief (USART1) Transmit Counter Register */ +#define REG_USART1_RNPR (*(RwReg*)0x4009C110U) /**< \brief (USART1) Receive Next Pointer Register */ +#define REG_USART1_RNCR (*(RwReg*)0x4009C114U) /**< \brief (USART1) Receive Next Counter Register */ +#define REG_USART1_TNPR (*(RwReg*)0x4009C118U) /**< \brief (USART1) Transmit Next Pointer Register */ +#define REG_USART1_TNCR (*(RwReg*)0x4009C11CU) /**< \brief (USART1) Transmit Next Counter Register */ +#define REG_USART1_PTCR (*(WoReg*)0x4009C120U) /**< \brief (USART1) Transfer Control Register */ +#define REG_USART1_PTSR (*(RoReg*)0x4009C124U) /**< \brief (USART1) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_USART1_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h new file mode 100644 index 0000000..3653d8d --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart2.h @@ -0,0 +1,111 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_USART2_INSTANCE_ +#define _SAM3XA_USART2_INSTANCE_ + +/* ========== Register definition for USART2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_USART2_CR (0x400A0000U) /**< \brief (USART2) Control Register */ +#define REG_USART2_MR (0x400A0004U) /**< \brief (USART2) Mode Register */ +#define REG_USART2_IER (0x400A0008U) /**< \brief (USART2) Interrupt Enable Register */ +#define REG_USART2_IDR (0x400A000CU) /**< \brief (USART2) Interrupt Disable Register */ +#define REG_USART2_IMR (0x400A0010U) /**< \brief (USART2) Interrupt Mask Register */ +#define REG_USART2_CSR (0x400A0014U) /**< \brief (USART2) Channel Status Register */ +#define REG_USART2_RHR (0x400A0018U) /**< \brief (USART2) Receiver Holding Register */ +#define REG_USART2_THR (0x400A001CU) /**< \brief (USART2) Transmitter Holding Register */ +#define REG_USART2_BRGR (0x400A0020U) /**< \brief (USART2) Baud Rate Generator Register */ +#define REG_USART2_RTOR (0x400A0024U) /**< \brief (USART2) Receiver Time-out Register */ +#define REG_USART2_TTGR (0x400A0028U) /**< \brief (USART2) Transmitter Timeguard Register */ +#define REG_USART2_FIDI (0x400A0040U) /**< \brief (USART2) FI DI Ratio Register */ +#define REG_USART2_NER (0x400A0044U) /**< \brief (USART2) Number of Errors Register */ +#define REG_USART2_IF (0x400A004CU) /**< \brief (USART2) IrDA Filter Register */ +#define REG_USART2_MAN (0x400A0050U) /**< \brief (USART2) Manchester Encoder Decoder Register */ +#define REG_USART2_LINMR (0x400A0054U) /**< \brief (USART2) LIN Mode Register */ +#define REG_USART2_LINIR (0x400A0058U) /**< \brief (USART2) LIN Identifier Register */ +#define REG_USART2_WPMR (0x400A00E4U) /**< \brief (USART2) Write Protect Mode Register */ +#define REG_USART2_WPSR (0x400A00E8U) /**< \brief (USART2) Write Protect Status Register */ +#define REG_USART2_RPR (0x400A0100U) /**< \brief (USART2) Receive Pointer Register */ +#define REG_USART2_RCR (0x400A0104U) /**< \brief (USART2) Receive Counter Register */ +#define REG_USART2_TPR (0x400A0108U) /**< \brief (USART2) Transmit Pointer Register */ +#define REG_USART2_TCR (0x400A010CU) /**< \brief (USART2) Transmit Counter Register */ +#define REG_USART2_RNPR (0x400A0110U) /**< \brief (USART2) Receive Next Pointer Register */ +#define REG_USART2_RNCR (0x400A0114U) /**< \brief (USART2) Receive Next Counter Register */ +#define REG_USART2_TNPR (0x400A0118U) /**< \brief (USART2) Transmit Next Pointer Register */ +#define REG_USART2_TNCR (0x400A011CU) /**< \brief (USART2) Transmit Next Counter Register */ +#define REG_USART2_PTCR (0x400A0120U) /**< \brief (USART2) Transfer Control Register */ +#define REG_USART2_PTSR (0x400A0124U) /**< \brief (USART2) Transfer Status Register */ +#else +#define REG_USART2_CR (*(WoReg*)0x400A0000U) /**< \brief (USART2) Control Register */ +#define REG_USART2_MR (*(RwReg*)0x400A0004U) /**< \brief (USART2) Mode Register */ +#define REG_USART2_IER (*(WoReg*)0x400A0008U) /**< \brief (USART2) Interrupt Enable Register */ +#define REG_USART2_IDR (*(WoReg*)0x400A000CU) /**< \brief (USART2) Interrupt Disable Register */ +#define REG_USART2_IMR (*(RoReg*)0x400A0010U) /**< \brief (USART2) Interrupt Mask Register */ +#define REG_USART2_CSR (*(RoReg*)0x400A0014U) /**< \brief (USART2) Channel Status Register */ +#define REG_USART2_RHR (*(RoReg*)0x400A0018U) /**< \brief (USART2) Receiver Holding Register */ +#define REG_USART2_THR (*(WoReg*)0x400A001CU) /**< \brief (USART2) Transmitter Holding Register */ +#define REG_USART2_BRGR (*(RwReg*)0x400A0020U) /**< \brief (USART2) Baud Rate Generator Register */ +#define REG_USART2_RTOR (*(RwReg*)0x400A0024U) /**< \brief (USART2) Receiver Time-out Register */ +#define REG_USART2_TTGR (*(RwReg*)0x400A0028U) /**< \brief (USART2) Transmitter Timeguard Register */ +#define REG_USART2_FIDI (*(RwReg*)0x400A0040U) /**< \brief (USART2) FI DI Ratio Register */ +#define REG_USART2_NER (*(RoReg*)0x400A0044U) /**< \brief (USART2) Number of Errors Register */ +#define REG_USART2_IF (*(RwReg*)0x400A004CU) /**< \brief (USART2) IrDA Filter Register */ +#define REG_USART2_MAN (*(RwReg*)0x400A0050U) /**< \brief (USART2) Manchester Encoder Decoder Register */ +#define REG_USART2_LINMR (*(RwReg*)0x400A0054U) /**< \brief (USART2) LIN Mode Register */ +#define REG_USART2_LINIR (*(RwReg*)0x400A0058U) /**< \brief (USART2) LIN Identifier Register */ +#define REG_USART2_WPMR (*(RwReg*)0x400A00E4U) /**< \brief (USART2) Write Protect Mode Register */ +#define REG_USART2_WPSR (*(RoReg*)0x400A00E8U) /**< \brief (USART2) Write Protect Status Register */ +#define REG_USART2_RPR (*(RwReg*)0x400A0100U) /**< \brief (USART2) Receive Pointer Register */ +#define REG_USART2_RCR (*(RwReg*)0x400A0104U) /**< \brief (USART2) Receive Counter Register */ +#define REG_USART2_TPR (*(RwReg*)0x400A0108U) /**< \brief (USART2) Transmit Pointer Register */ +#define REG_USART2_TCR (*(RwReg*)0x400A010CU) /**< \brief (USART2) Transmit Counter Register */ +#define REG_USART2_RNPR (*(RwReg*)0x400A0110U) /**< \brief (USART2) Receive Next Pointer Register */ +#define REG_USART2_RNCR (*(RwReg*)0x400A0114U) /**< \brief (USART2) Receive Next Counter Register */ +#define REG_USART2_TNPR (*(RwReg*)0x400A0118U) /**< \brief (USART2) Transmit Next Pointer Register */ +#define REG_USART2_TNCR (*(RwReg*)0x400A011CU) /**< \brief (USART2) Transmit Next Counter Register */ +#define REG_USART2_PTCR (*(WoReg*)0x400A0120U) /**< \brief (USART2) Transfer Control Register */ +#define REG_USART2_PTSR (*(RoReg*)0x400A0124U) /**< \brief (USART2) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_USART2_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h new file mode 100644 index 0000000..e8a86be --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_usart3.h @@ -0,0 +1,111 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_USART3_INSTANCE_ +#define _SAM3XA_USART3_INSTANCE_ + +/* ========== Register definition for USART3 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_USART3_CR (0x400A4000U) /**< \brief (USART3) Control Register */ +#define REG_USART3_MR (0x400A4004U) /**< \brief (USART3) Mode Register */ +#define REG_USART3_IER (0x400A4008U) /**< \brief (USART3) Interrupt Enable Register */ +#define REG_USART3_IDR (0x400A400CU) /**< \brief (USART3) Interrupt Disable Register */ +#define REG_USART3_IMR (0x400A4010U) /**< \brief (USART3) Interrupt Mask Register */ +#define REG_USART3_CSR (0x400A4014U) /**< \brief (USART3) Channel Status Register */ +#define REG_USART3_RHR (0x400A4018U) /**< \brief (USART3) Receiver Holding Register */ +#define REG_USART3_THR (0x400A401CU) /**< \brief (USART3) Transmitter Holding Register */ +#define REG_USART3_BRGR (0x400A4020U) /**< \brief (USART3) Baud Rate Generator Register */ +#define REG_USART3_RTOR (0x400A4024U) /**< \brief (USART3) Receiver Time-out Register */ +#define REG_USART3_TTGR (0x400A4028U) /**< \brief (USART3) Transmitter Timeguard Register */ +#define REG_USART3_FIDI (0x400A4040U) /**< \brief (USART3) FI DI Ratio Register */ +#define REG_USART3_NER (0x400A4044U) /**< \brief (USART3) Number of Errors Register */ +#define REG_USART3_IF (0x400A404CU) /**< \brief (USART3) IrDA Filter Register */ +#define REG_USART3_MAN (0x400A4050U) /**< \brief (USART3) Manchester Encoder Decoder Register */ +#define REG_USART3_LINMR (0x400A4054U) /**< \brief (USART3) LIN Mode Register */ +#define REG_USART3_LINIR (0x400A4058U) /**< \brief (USART3) LIN Identifier Register */ +#define REG_USART3_WPMR (0x400A40E4U) /**< \brief (USART3) Write Protect Mode Register */ +#define REG_USART3_WPSR (0x400A40E8U) /**< \brief (USART3) Write Protect Status Register */ +#define REG_USART3_RPR (0x400A4100U) /**< \brief (USART3) Receive Pointer Register */ +#define REG_USART3_RCR (0x400A4104U) /**< \brief (USART3) Receive Counter Register */ +#define REG_USART3_TPR (0x400A4108U) /**< \brief (USART3) Transmit Pointer Register */ +#define REG_USART3_TCR (0x400A410CU) /**< \brief (USART3) Transmit Counter Register */ +#define REG_USART3_RNPR (0x400A4110U) /**< \brief (USART3) Receive Next Pointer Register */ +#define REG_USART3_RNCR (0x400A4114U) /**< \brief (USART3) Receive Next Counter Register */ +#define REG_USART3_TNPR (0x400A4118U) /**< \brief (USART3) Transmit Next Pointer Register */ +#define REG_USART3_TNCR (0x400A411CU) /**< \brief (USART3) Transmit Next Counter Register */ +#define REG_USART3_PTCR (0x400A4120U) /**< \brief (USART3) Transfer Control Register */ +#define REG_USART3_PTSR (0x400A4124U) /**< \brief (USART3) Transfer Status Register */ +#else +#define REG_USART3_CR (*(WoReg*)0x400A4000U) /**< \brief (USART3) Control Register */ +#define REG_USART3_MR (*(RwReg*)0x400A4004U) /**< \brief (USART3) Mode Register */ +#define REG_USART3_IER (*(WoReg*)0x400A4008U) /**< \brief (USART3) Interrupt Enable Register */ +#define REG_USART3_IDR (*(WoReg*)0x400A400CU) /**< \brief (USART3) Interrupt Disable Register */ +#define REG_USART3_IMR (*(RoReg*)0x400A4010U) /**< \brief (USART3) Interrupt Mask Register */ +#define REG_USART3_CSR (*(RoReg*)0x400A4014U) /**< \brief (USART3) Channel Status Register */ +#define REG_USART3_RHR (*(RoReg*)0x400A4018U) /**< \brief (USART3) Receiver Holding Register */ +#define REG_USART3_THR (*(WoReg*)0x400A401CU) /**< \brief (USART3) Transmitter Holding Register */ +#define REG_USART3_BRGR (*(RwReg*)0x400A4020U) /**< \brief (USART3) Baud Rate Generator Register */ +#define REG_USART3_RTOR (*(RwReg*)0x400A4024U) /**< \brief (USART3) Receiver Time-out Register */ +#define REG_USART3_TTGR (*(RwReg*)0x400A4028U) /**< \brief (USART3) Transmitter Timeguard Register */ +#define REG_USART3_FIDI (*(RwReg*)0x400A4040U) /**< \brief (USART3) FI DI Ratio Register */ +#define REG_USART3_NER (*(RoReg*)0x400A4044U) /**< \brief (USART3) Number of Errors Register */ +#define REG_USART3_IF (*(RwReg*)0x400A404CU) /**< \brief (USART3) IrDA Filter Register */ +#define REG_USART3_MAN (*(RwReg*)0x400A4050U) /**< \brief (USART3) Manchester Encoder Decoder Register */ +#define REG_USART3_LINMR (*(RwReg*)0x400A4054U) /**< \brief (USART3) LIN Mode Register */ +#define REG_USART3_LINIR (*(RwReg*)0x400A4058U) /**< \brief (USART3) LIN Identifier Register */ +#define REG_USART3_WPMR (*(RwReg*)0x400A40E4U) /**< \brief (USART3) Write Protect Mode Register */ +#define REG_USART3_WPSR (*(RoReg*)0x400A40E8U) /**< \brief (USART3) Write Protect Status Register */ +#define REG_USART3_RPR (*(RwReg*)0x400A4100U) /**< \brief (USART3) Receive Pointer Register */ +#define REG_USART3_RCR (*(RwReg*)0x400A4104U) /**< \brief (USART3) Receive Counter Register */ +#define REG_USART3_TPR (*(RwReg*)0x400A4108U) /**< \brief (USART3) Transmit Pointer Register */ +#define REG_USART3_TCR (*(RwReg*)0x400A410CU) /**< \brief (USART3) Transmit Counter Register */ +#define REG_USART3_RNPR (*(RwReg*)0x400A4110U) /**< \brief (USART3) Receive Next Pointer Register */ +#define REG_USART3_RNCR (*(RwReg*)0x400A4114U) /**< \brief (USART3) Receive Next Counter Register */ +#define REG_USART3_TNPR (*(RwReg*)0x400A4118U) /**< \brief (USART3) Transmit Next Pointer Register */ +#define REG_USART3_TNCR (*(RwReg*)0x400A411CU) /**< \brief (USART3) Transmit Next Counter Register */ +#define REG_USART3_PTCR (*(WoReg*)0x400A4120U) /**< \brief (USART3) Transfer Control Register */ +#define REG_USART3_PTSR (*(RoReg*)0x400A4124U) /**< \brief (USART3) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_USART3_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h new file mode 100644 index 0000000..43dd829 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/instance/instance_wdt.h @@ -0,0 +1,59 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_WDT_INSTANCE_ +#define _SAM3XA_WDT_INSTANCE_ + +/* ========== Register definition for WDT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_WDT_CR (0x400E1A50U) /**< \brief (WDT) Control Register */ +#define REG_WDT_MR (0x400E1A54U) /**< \brief (WDT) Mode Register */ +#define REG_WDT_SR (0x400E1A58U) /**< \brief (WDT) Status Register */ +#else +#define REG_WDT_CR (*(WoReg*)0x400E1A50U) /**< \brief (WDT) Control Register */ +#define REG_WDT_MR (*(RwReg*)0x400E1A54U) /**< \brief (WDT) Mode Register */ +#define REG_WDT_SR (*(RoReg*)0x400E1A58U) /**< \brief (WDT) Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3XA_WDT_INSTANCE_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3a4c.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3a4c.h new file mode 100644 index 0000000..7753e15 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3a4c.h @@ -0,0 +1,353 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3A4C_PIO_ +#define _SAM3A4C_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ +#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ +#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */ +#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */ +#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */ +#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */ +#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */ +#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */ +#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */ +#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */ +#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */ +#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */ +#define PIO_PB25 (1u << 25) /**< \brief Pin Controlled by PB25 */ +#define PIO_PB26 (1u << 26) /**< \brief Pin Controlled by PB26 */ +#define PIO_PB27 (1u << 27) /**< \brief Pin Controlled by PB27 */ +#define PIO_PB28 (1u << 28) /**< \brief Pin Controlled by PB28 */ +#define PIO_PB29 (1u << 29) /**< \brief Pin Controlled by PB29 */ +#define PIO_PB30 (1u << 30) /**< \brief Pin Controlled by PB30 */ +#define PIO_PB31 (1u << 31) /**< \brief Pin Controlled by PB31 */ +/* ========== Pio definition for ADC peripheral ========== */ +#define PIO_PA2X1_AD0 (1u << 2) /**< \brief Adc signal: AD0 */ +#define PIO_PA3X1_AD1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */ +#define PIO_PA3X1_WKUP1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */ +#define PIO_PB17X1_AD10 (1u << 17) /**< \brief Adc signal: AD10 */ +#define PIO_PB18X1_AD11 (1u << 18) /**< \brief Adc signal: AD11 */ +#define PIO_PB19X1_AD12 (1u << 19) /**< \brief Adc signal: AD12 */ +#define PIO_PB20X1_AD13 (1u << 20) /**< \brief Adc signal: AD13 */ +#define PIO_PB21X1_AD14 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */ +#define PIO_PB21X1_WKUP13 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */ +#define PIO_PA4X1_AD2 (1u << 4) /**< \brief Adc signal: AD2 */ +#define PIO_PA6X1_AD3 (1u << 6) /**< \brief Adc signal: AD3 */ +#define PIO_PA22X1_AD4 (1u << 22) /**< \brief Adc signal: AD4 */ +#define PIO_PA23X1_AD5 (1u << 23) /**< \brief Adc signal: AD5 */ +#define PIO_PA24X1_AD6 (1u << 24) /**< \brief Adc signal: AD6 */ +#define PIO_PA16X1_AD7 (1u << 16) /**< \brief Adc signal: AD7 */ +#define PIO_PB12X1_AD8 (1u << 12) /**< \brief Adc signal: AD8 */ +#define PIO_PB13X1_AD9 (1u << 13) /**< \brief Adc signal: AD9 */ +#define PIO_PA11B_ADTRG (1u << 11) /**< \brief Adc signal: ADTRG */ +/* ========== Pio definition for CAN0 peripheral ========== */ +#define PIO_PA1A_CANRX0 (1u << 1) /**< \brief Can0 signal: CANRX0 */ +#define PIO_PA0A_CANTX0 (1u << 0) /**< \brief Can0 signal: CANTX0 */ +/* ========== Pio definition for CAN1 peripheral ========== */ +#define PIO_PB15A_CANRX1 (1u << 15) /**< \brief Can1 signal: CANRX1 */ +#define PIO_PB14A_CANTX1 (1u << 14) /**< \brief Can1 signal: CANTX1 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB15X1_DAC0 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */ +#define PIO_PB15X1_WKUP12 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */ +#define PIO_PB16X1_DAC1 (1u << 16) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA10B_DATRG (1u << 10) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA20A_MCCDA (1u << 20) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PE20B_MCCDB (1u << 20) /**< \brief Hsmci signal: MCCDB */ +#define PIO_PA19A_MCCK (1u << 19) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA21A_MCDA0 (1u << 21) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA22A_MCDA1 (1u << 22) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA23A_MCDA2 (1u << 23) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA24A_MCDA3 (1u << 24) /**< \brief Hsmci signal: MCDA3 */ +#define PIO_PD0B_MCDA4 (1u << 0) /**< \brief Hsmci signal: MCDA4 */ +#define PIO_PD1B_MCDA5 (1u << 1) /**< \brief Hsmci signal: MCDA5 */ +#define PIO_PD2B_MCDA6 (1u << 2) /**< \brief Hsmci signal: MCDA6 */ +#define PIO_PD3B_MCDA7 (1u << 3) /**< \brief Hsmci signal: MCDA7 */ +#define PIO_PE22B_MCDB0 (1u << 22) /**< \brief Hsmci signal: MCDB0 */ +#define PIO_PE24B_MCDB1 (1u << 24) /**< \brief Hsmci signal: MCDB1 */ +#define PIO_PE26B_MCDB2 (1u << 26) /**< \brief Hsmci signal: MCDB2 */ +#define PIO_PE27B_MCDB3 (1u << 27) /**< \brief Hsmci signal: MCDB3 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA1B_PCK0 (1u << 1) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB22B_PCK0 (1u << 22) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA24B_PCK1 (1u << 24) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA30B_PCK1 (1u << 30) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA28B_PCK2 (1u << 28) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM peripheral ========== */ +#define PIO_PA5B_PWMFI0 (1u << 5) /**< \brief Pwm signal: PWMFI0 */ +#define PIO_PA3B_PWMFI1 (1u << 3) /**< \brief Pwm signal: PWMFI1 */ +#define PIO_PD6B_PWMFI2 (1u << 6) /**< \brief Pwm signal: PWMFI2 */ +#define PIO_PA8B_PWMH0 (1u << 8) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PB12B_PWMH0 (1u << 12) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PC3B_PWMH0 (1u << 3) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PE15A_PWMH0 (1u << 15) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PB13B_PWMH1 (1u << 13) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PC5B_PWMH1 (1u << 5) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PE16A_PWMH1 (1u << 16) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PB14B_PWMH2 (1u << 14) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PC7B_PWMH2 (1u << 7) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PB15B_PWMH3 (1u << 15) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PC9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PF3A_PWMH3 (1u << 3) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PC20B_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */ +#define PIO_PE20A_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */ +#define PIO_PC19B_PWMH5 (1u << 19) /**< \brief Pwm signal: PWMH5 */ +#define PIO_PE22A_PWMH5 (1u << 22) /**< \brief Pwm signal: PWMH5 */ +#define PIO_PC18B_PWMH6 (1u << 18) /**< \brief Pwm signal: PWMH6 */ +#define PIO_PE24A_PWMH6 (1u << 24) /**< \brief Pwm signal: PWMH6 */ +#define PIO_PE26A_PWMH7 (1u << 26) /**< \brief Pwm signal: PWMH7 */ +#define PIO_PA21B_PWML0 (1u << 21) /**< \brief Pwm signal: PWML0 */ +#define PIO_PB16B_PWML0 (1u << 16) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC2B_PWML0 (1u << 2) /**< \brief Pwm signal: PWML0 */ +#define PIO_PE18A_PWML0 (1u << 18) /**< \brief Pwm signal: PWML0 */ +#define PIO_PA12B_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */ +#define PIO_PB17B_PWML1 (1u << 17) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC4B_PWML1 (1u << 4) /**< \brief Pwm signal: PWML1 */ +#define PIO_PA20B_PWML2 (1u << 20) /**< \brief Pwm signal: PWML2 */ +#define PIO_PB18B_PWML2 (1u << 18) /**< \brief Pwm signal: PWML2 */ +#define PIO_PC6B_PWML2 (1u << 6) /**< \brief Pwm signal: PWML2 */ +#define PIO_PE17A_PWML2 (1u << 17) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA0B_PWML3 (1u << 0) /**< \brief Pwm signal: PWML3 */ +#define PIO_PB19B_PWML3 (1u << 19) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC8B_PWML3 (1u << 8) /**< \brief Pwm signal: PWML3 */ +#define PIO_PB6B_PWML4 (1u << 6) /**< \brief Pwm signal: PWML4 */ +#define PIO_PC21B_PWML4 (1u << 21) /**< \brief Pwm signal: PWML4 */ +#define PIO_PE19A_PWML4 (1u << 19) /**< \brief Pwm signal: PWML4 */ +#define PIO_PB7B_PWML5 (1u << 7) /**< \brief Pwm signal: PWML5 */ +#define PIO_PC22B_PWML5 (1u << 22) /**< \brief Pwm signal: PWML5 */ +#define PIO_PE21A_PWML5 (1u << 21) /**< \brief Pwm signal: PWML5 */ +#define PIO_PB8B_PWML6 (1u << 8) /**< \brief Pwm signal: PWML6 */ +#define PIO_PC23B_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */ +#define PIO_PE23A_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */ +#define PIO_PB9B_PWML7 (1u << 9) /**< \brief Pwm signal: PWML7 */ +#define PIO_PC24B_PWML7 (1u << 24) /**< \brief Pwm signal: PWML7 */ +#define PIO_PE25A_PWML7 (1u << 25) /**< \brief Pwm signal: PWML7 */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PA25A_SPI0_MISO (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PA26A_SPI0_MOSI (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PA27A_SPI0_SPCK (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PB18A_RD (1u << 18) /**< \brief Ssc signal: RD */ +#define PIO_PB17A_RF (1u << 17) /**< \brief Ssc signal: RF */ +#define PIO_PB19A_RK (1u << 19) /**< \brief Ssc signal: RK */ +#define PIO_PA16B_TD (1u << 16) /**< \brief Ssc signal: TD */ +#define PIO_PA15B_TF (1u << 15) /**< \brief Ssc signal: TF */ +#define PIO_PA14B_TK (1u << 14) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PB26B_TCLK0 (1u << 26) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA4A_TCLK1 (1u << 4) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA7A_TCLK2 (1u << 7) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PB25B_TIOA0 (1u << 25) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA2A_TIOA1 (1u << 2) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA5A_TIOA2 (1u << 5) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PB27B_TIOB0 (1u << 27) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA3A_TIOB1 (1u << 3) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA6A_TIOB2 (1u << 6) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PA22B_TCLK3 (1u << 22) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PA23B_TCLK4 (1u << 23) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PB16A_TCLK5 (1u << 16) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PB0B_TIOA3 (1u << 0) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PE9A_TIOA3 (1u << 9) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PB2B_TIOA4 (1u << 2) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PE11A_TIOA4 (1u << 11) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PB4B_TIOA5 (1u << 4) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PE13A_TIOA5 (1u << 13) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PB1B_TIOB3 (1u << 1) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PE10A_TIOB3 (1u << 10) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PB3B_TIOB4 (1u << 3) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PE12A_TIOB4 (1u << 12) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PB5B_TIOB5 (1u << 5) /**< \brief Tc1 signal: TIOB5 */ +#define PIO_PE14A_TIOB5 (1u << 14) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TWI0 peripheral ========== */ +#define PIO_PA18A_TWCK0 (1u << 18) /**< \brief Twi0 signal: TWCK0 */ +#define PIO_PA17A_TWD0 (1u << 17) /**< \brief Twi0 signal: TWD0 */ +/* ========== Pio definition for TWI1 peripheral ========== */ +#define PIO_PB13A_TWCK1 (1u << 13) /**< \brief Twi1 signal: TWCK1 */ +#define PIO_PB12A_TWD1 (1u << 12) /**< \brief Twi1 signal: TWD1 */ +/* ========== Pio definition for UART peripheral ========== */ +#define PIO_PA8A_URXD (1u << 8) /**< \brief Uart signal: URXD */ +#define PIO_PA9A_UTXD (1u << 9) /**< \brief Uart signal: UTXD */ +/* ========== Pio definition for UOTGHS peripheral ========== */ +#define PIO_PB11A_UOTGID (1u << 11) /**< \brief Uotghs signal: UOTGID */ +#define PIO_PB10A_UOTGVBOF (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB26A_CTS0 (1u << 26) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PB25A_RTS0 (1u << 25) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PA10A_RXD0 (1u << 10) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PA17B_SCK0 (1u << 17) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PA11A_TXD0 (1u << 11) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA15A_CTS1 (1u << 15) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA14A_RTS1 (1u << 14) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA12A_RXD1 (1u << 12) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA16A_SCK1 (1u << 16) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PA13A_TXD1 (1u << 13) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PB23A_CTS2 (1u << 23) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PB22A_RTS2 (1u << 22) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PB21A_RXD2 (1u << 21) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PB24A_SCK2 (1u << 24) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PB20A_TXD2 (1u << 20) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB10_IDX 42 +#define PIO_PB11_IDX 43 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PB14_IDX 46 +#define PIO_PB15_IDX 47 +#define PIO_PB16_IDX 48 +#define PIO_PB17_IDX 49 +#define PIO_PB18_IDX 50 +#define PIO_PB19_IDX 51 +#define PIO_PB20_IDX 52 +#define PIO_PB21_IDX 53 +#define PIO_PB22_IDX 54 +#define PIO_PB23_IDX 55 +#define PIO_PB24_IDX 56 +#define PIO_PB25_IDX 57 +#define PIO_PB26_IDX 58 +#define PIO_PB27_IDX 59 +#define PIO_PB28_IDX 60 +#define PIO_PB29_IDX 61 +#define PIO_PB30_IDX 62 +#define PIO_PB31_IDX 63 + +#endif /* _SAM3A4C_PIO_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3a8c.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3a8c.h new file mode 100644 index 0000000..1fff046 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3a8c.h @@ -0,0 +1,353 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3A8C_PIO_ +#define _SAM3A8C_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ +#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ +#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */ +#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */ +#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */ +#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */ +#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */ +#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */ +#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */ +#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */ +#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */ +#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */ +#define PIO_PB25 (1u << 25) /**< \brief Pin Controlled by PB25 */ +#define PIO_PB26 (1u << 26) /**< \brief Pin Controlled by PB26 */ +#define PIO_PB27 (1u << 27) /**< \brief Pin Controlled by PB27 */ +#define PIO_PB28 (1u << 28) /**< \brief Pin Controlled by PB28 */ +#define PIO_PB29 (1u << 29) /**< \brief Pin Controlled by PB29 */ +#define PIO_PB30 (1u << 30) /**< \brief Pin Controlled by PB30 */ +#define PIO_PB31 (1u << 31) /**< \brief Pin Controlled by PB31 */ +/* ========== Pio definition for ADC peripheral ========== */ +#define PIO_PA2X1_AD0 (1u << 2) /**< \brief Adc signal: AD0 */ +#define PIO_PA3X1_AD1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */ +#define PIO_PA3X1_WKUP1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */ +#define PIO_PB17X1_AD10 (1u << 17) /**< \brief Adc signal: AD10 */ +#define PIO_PB18X1_AD11 (1u << 18) /**< \brief Adc signal: AD11 */ +#define PIO_PB19X1_AD12 (1u << 19) /**< \brief Adc signal: AD12 */ +#define PIO_PB20X1_AD13 (1u << 20) /**< \brief Adc signal: AD13 */ +#define PIO_PB21X1_AD14 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */ +#define PIO_PB21X1_WKUP13 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */ +#define PIO_PA4X1_AD2 (1u << 4) /**< \brief Adc signal: AD2 */ +#define PIO_PA6X1_AD3 (1u << 6) /**< \brief Adc signal: AD3 */ +#define PIO_PA22X1_AD4 (1u << 22) /**< \brief Adc signal: AD4 */ +#define PIO_PA23X1_AD5 (1u << 23) /**< \brief Adc signal: AD5 */ +#define PIO_PA24X1_AD6 (1u << 24) /**< \brief Adc signal: AD6 */ +#define PIO_PA16X1_AD7 (1u << 16) /**< \brief Adc signal: AD7 */ +#define PIO_PB12X1_AD8 (1u << 12) /**< \brief Adc signal: AD8 */ +#define PIO_PB13X1_AD9 (1u << 13) /**< \brief Adc signal: AD9 */ +#define PIO_PA11B_ADTRG (1u << 11) /**< \brief Adc signal: ADTRG */ +/* ========== Pio definition for CAN0 peripheral ========== */ +#define PIO_PA1A_CANRX0 (1u << 1) /**< \brief Can0 signal: CANRX0 */ +#define PIO_PA0A_CANTX0 (1u << 0) /**< \brief Can0 signal: CANTX0 */ +/* ========== Pio definition for CAN1 peripheral ========== */ +#define PIO_PB15A_CANRX1 (1u << 15) /**< \brief Can1 signal: CANRX1 */ +#define PIO_PB14A_CANTX1 (1u << 14) /**< \brief Can1 signal: CANTX1 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB15X1_DAC0 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */ +#define PIO_PB15X1_WKUP12 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */ +#define PIO_PB16X1_DAC1 (1u << 16) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA10B_DATRG (1u << 10) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA20A_MCCDA (1u << 20) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PE20B_MCCDB (1u << 20) /**< \brief Hsmci signal: MCCDB */ +#define PIO_PA19A_MCCK (1u << 19) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA21A_MCDA0 (1u << 21) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA22A_MCDA1 (1u << 22) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA23A_MCDA2 (1u << 23) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA24A_MCDA3 (1u << 24) /**< \brief Hsmci signal: MCDA3 */ +#define PIO_PD0B_MCDA4 (1u << 0) /**< \brief Hsmci signal: MCDA4 */ +#define PIO_PD1B_MCDA5 (1u << 1) /**< \brief Hsmci signal: MCDA5 */ +#define PIO_PD2B_MCDA6 (1u << 2) /**< \brief Hsmci signal: MCDA6 */ +#define PIO_PD3B_MCDA7 (1u << 3) /**< \brief Hsmci signal: MCDA7 */ +#define PIO_PE22B_MCDB0 (1u << 22) /**< \brief Hsmci signal: MCDB0 */ +#define PIO_PE24B_MCDB1 (1u << 24) /**< \brief Hsmci signal: MCDB1 */ +#define PIO_PE26B_MCDB2 (1u << 26) /**< \brief Hsmci signal: MCDB2 */ +#define PIO_PE27B_MCDB3 (1u << 27) /**< \brief Hsmci signal: MCDB3 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA1B_PCK0 (1u << 1) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB22B_PCK0 (1u << 22) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA24B_PCK1 (1u << 24) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA30B_PCK1 (1u << 30) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA28B_PCK2 (1u << 28) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM peripheral ========== */ +#define PIO_PA5B_PWMFI0 (1u << 5) /**< \brief Pwm signal: PWMFI0 */ +#define PIO_PA3B_PWMFI1 (1u << 3) /**< \brief Pwm signal: PWMFI1 */ +#define PIO_PD6B_PWMFI2 (1u << 6) /**< \brief Pwm signal: PWMFI2 */ +#define PIO_PA8B_PWMH0 (1u << 8) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PB12B_PWMH0 (1u << 12) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PC3B_PWMH0 (1u << 3) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PE15A_PWMH0 (1u << 15) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PB13B_PWMH1 (1u << 13) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PC5B_PWMH1 (1u << 5) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PE16A_PWMH1 (1u << 16) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PB14B_PWMH2 (1u << 14) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PC7B_PWMH2 (1u << 7) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PB15B_PWMH3 (1u << 15) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PC9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PF3A_PWMH3 (1u << 3) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PC20B_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */ +#define PIO_PE20A_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */ +#define PIO_PC19B_PWMH5 (1u << 19) /**< \brief Pwm signal: PWMH5 */ +#define PIO_PE22A_PWMH5 (1u << 22) /**< \brief Pwm signal: PWMH5 */ +#define PIO_PC18B_PWMH6 (1u << 18) /**< \brief Pwm signal: PWMH6 */ +#define PIO_PE24A_PWMH6 (1u << 24) /**< \brief Pwm signal: PWMH6 */ +#define PIO_PE26A_PWMH7 (1u << 26) /**< \brief Pwm signal: PWMH7 */ +#define PIO_PA21B_PWML0 (1u << 21) /**< \brief Pwm signal: PWML0 */ +#define PIO_PB16B_PWML0 (1u << 16) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC2B_PWML0 (1u << 2) /**< \brief Pwm signal: PWML0 */ +#define PIO_PE18A_PWML0 (1u << 18) /**< \brief Pwm signal: PWML0 */ +#define PIO_PA12B_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */ +#define PIO_PB17B_PWML1 (1u << 17) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC4B_PWML1 (1u << 4) /**< \brief Pwm signal: PWML1 */ +#define PIO_PA20B_PWML2 (1u << 20) /**< \brief Pwm signal: PWML2 */ +#define PIO_PB18B_PWML2 (1u << 18) /**< \brief Pwm signal: PWML2 */ +#define PIO_PC6B_PWML2 (1u << 6) /**< \brief Pwm signal: PWML2 */ +#define PIO_PE17A_PWML2 (1u << 17) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA0B_PWML3 (1u << 0) /**< \brief Pwm signal: PWML3 */ +#define PIO_PB19B_PWML3 (1u << 19) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC8B_PWML3 (1u << 8) /**< \brief Pwm signal: PWML3 */ +#define PIO_PB6B_PWML4 (1u << 6) /**< \brief Pwm signal: PWML4 */ +#define PIO_PC21B_PWML4 (1u << 21) /**< \brief Pwm signal: PWML4 */ +#define PIO_PE19A_PWML4 (1u << 19) /**< \brief Pwm signal: PWML4 */ +#define PIO_PB7B_PWML5 (1u << 7) /**< \brief Pwm signal: PWML5 */ +#define PIO_PC22B_PWML5 (1u << 22) /**< \brief Pwm signal: PWML5 */ +#define PIO_PE21A_PWML5 (1u << 21) /**< \brief Pwm signal: PWML5 */ +#define PIO_PB8B_PWML6 (1u << 8) /**< \brief Pwm signal: PWML6 */ +#define PIO_PC23B_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */ +#define PIO_PE23A_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */ +#define PIO_PB9B_PWML7 (1u << 9) /**< \brief Pwm signal: PWML7 */ +#define PIO_PC24B_PWML7 (1u << 24) /**< \brief Pwm signal: PWML7 */ +#define PIO_PE25A_PWML7 (1u << 25) /**< \brief Pwm signal: PWML7 */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PA25A_SPI0_MISO (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PA26A_SPI0_MOSI (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PA27A_SPI0_SPCK (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PB18A_RD (1u << 18) /**< \brief Ssc signal: RD */ +#define PIO_PB17A_RF (1u << 17) /**< \brief Ssc signal: RF */ +#define PIO_PB19A_RK (1u << 19) /**< \brief Ssc signal: RK */ +#define PIO_PA16B_TD (1u << 16) /**< \brief Ssc signal: TD */ +#define PIO_PA15B_TF (1u << 15) /**< \brief Ssc signal: TF */ +#define PIO_PA14B_TK (1u << 14) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PB26B_TCLK0 (1u << 26) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA4A_TCLK1 (1u << 4) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA7A_TCLK2 (1u << 7) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PB25B_TIOA0 (1u << 25) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA2A_TIOA1 (1u << 2) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA5A_TIOA2 (1u << 5) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PB27B_TIOB0 (1u << 27) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA3A_TIOB1 (1u << 3) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA6A_TIOB2 (1u << 6) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PA22B_TCLK3 (1u << 22) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PA23B_TCLK4 (1u << 23) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PB16A_TCLK5 (1u << 16) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PB0B_TIOA3 (1u << 0) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PE9A_TIOA3 (1u << 9) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PB2B_TIOA4 (1u << 2) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PE11A_TIOA4 (1u << 11) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PB4B_TIOA5 (1u << 4) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PE13A_TIOA5 (1u << 13) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PB1B_TIOB3 (1u << 1) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PE10A_TIOB3 (1u << 10) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PB3B_TIOB4 (1u << 3) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PE12A_TIOB4 (1u << 12) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PB5B_TIOB5 (1u << 5) /**< \brief Tc1 signal: TIOB5 */ +#define PIO_PE14A_TIOB5 (1u << 14) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TWI0 peripheral ========== */ +#define PIO_PA18A_TWCK0 (1u << 18) /**< \brief Twi0 signal: TWCK0 */ +#define PIO_PA17A_TWD0 (1u << 17) /**< \brief Twi0 signal: TWD0 */ +/* ========== Pio definition for TWI1 peripheral ========== */ +#define PIO_PB13A_TWCK1 (1u << 13) /**< \brief Twi1 signal: TWCK1 */ +#define PIO_PB12A_TWD1 (1u << 12) /**< \brief Twi1 signal: TWD1 */ +/* ========== Pio definition for UART peripheral ========== */ +#define PIO_PA8A_URXD (1u << 8) /**< \brief Uart signal: URXD */ +#define PIO_PA9A_UTXD (1u << 9) /**< \brief Uart signal: UTXD */ +/* ========== Pio definition for UOTGHS peripheral ========== */ +#define PIO_PB11A_UOTGID (1u << 11) /**< \brief Uotghs signal: UOTGID */ +#define PIO_PB10A_UOTGVBOF (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB26A_CTS0 (1u << 26) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PB25A_RTS0 (1u << 25) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PA10A_RXD0 (1u << 10) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PA17B_SCK0 (1u << 17) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PA11A_TXD0 (1u << 11) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA15A_CTS1 (1u << 15) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA14A_RTS1 (1u << 14) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA12A_RXD1 (1u << 12) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA16A_SCK1 (1u << 16) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PA13A_TXD1 (1u << 13) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PB23A_CTS2 (1u << 23) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PB22A_RTS2 (1u << 22) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PB21A_RXD2 (1u << 21) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PB24A_SCK2 (1u << 24) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PB20A_TXD2 (1u << 20) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB10_IDX 42 +#define PIO_PB11_IDX 43 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PB14_IDX 46 +#define PIO_PB15_IDX 47 +#define PIO_PB16_IDX 48 +#define PIO_PB17_IDX 49 +#define PIO_PB18_IDX 50 +#define PIO_PB19_IDX 51 +#define PIO_PB20_IDX 52 +#define PIO_PB21_IDX 53 +#define PIO_PB22_IDX 54 +#define PIO_PB23_IDX 55 +#define PIO_PB24_IDX 56 +#define PIO_PB25_IDX 57 +#define PIO_PB26_IDX 58 +#define PIO_PB27_IDX 59 +#define PIO_PB28_IDX 60 +#define PIO_PB29_IDX 61 +#define PIO_PB30_IDX 62 +#define PIO_PB31_IDX 63 + +#endif /* _SAM3A8C_PIO_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x4c.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x4c.h new file mode 100644 index 0000000..ed2dc37 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x4c.h @@ -0,0 +1,373 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3X4C_PIO_ +#define _SAM3X4C_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ +#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ +#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */ +#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */ +#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */ +#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */ +#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */ +#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */ +#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */ +#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */ +#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */ +#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */ +#define PIO_PB25 (1u << 25) /**< \brief Pin Controlled by PB25 */ +#define PIO_PB26 (1u << 26) /**< \brief Pin Controlled by PB26 */ +#define PIO_PB27 (1u << 27) /**< \brief Pin Controlled by PB27 */ +#define PIO_PB28 (1u << 28) /**< \brief Pin Controlled by PB28 */ +#define PIO_PB29 (1u << 29) /**< \brief Pin Controlled by PB29 */ +#define PIO_PB30 (1u << 30) /**< \brief Pin Controlled by PB30 */ +#define PIO_PB31 (1u << 31) /**< \brief Pin Controlled by PB31 */ +/* ========== Pio definition for ADC peripheral ========== */ +#define PIO_PA2X1_AD0 (1u << 2) /**< \brief Adc signal: AD0 */ +#define PIO_PA3X1_AD1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */ +#define PIO_PA3X1_WKUP1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */ +#define PIO_PB17X1_AD10 (1u << 17) /**< \brief Adc signal: AD10 */ +#define PIO_PB18X1_AD11 (1u << 18) /**< \brief Adc signal: AD11 */ +#define PIO_PB19X1_AD12 (1u << 19) /**< \brief Adc signal: AD12 */ +#define PIO_PB20X1_AD13 (1u << 20) /**< \brief Adc signal: AD13 */ +#define PIO_PB21X1_AD14 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */ +#define PIO_PB21X1_WKUP13 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */ +#define PIO_PA4X1_AD2 (1u << 4) /**< \brief Adc signal: AD2 */ +#define PIO_PA6X1_AD3 (1u << 6) /**< \brief Adc signal: AD3 */ +#define PIO_PA22X1_AD4 (1u << 22) /**< \brief Adc signal: AD4 */ +#define PIO_PA23X1_AD5 (1u << 23) /**< \brief Adc signal: AD5 */ +#define PIO_PA24X1_AD6 (1u << 24) /**< \brief Adc signal: AD6 */ +#define PIO_PA16X1_AD7 (1u << 16) /**< \brief Adc signal: AD7 */ +#define PIO_PB12X1_AD8 (1u << 12) /**< \brief Adc signal: AD8 */ +#define PIO_PB13X1_AD9 (1u << 13) /**< \brief Adc signal: AD9 */ +#define PIO_PA11B_ADTRG (1u << 11) /**< \brief Adc signal: ADTRG */ +/* ========== Pio definition for CAN0 peripheral ========== */ +#define PIO_PA1A_CANRX0 (1u << 1) /**< \brief Can0 signal: CANRX0 */ +#define PIO_PA0A_CANTX0 (1u << 0) /**< \brief Can0 signal: CANTX0 */ +/* ========== Pio definition for CAN1 peripheral ========== */ +#define PIO_PB15A_CANRX1 (1u << 15) /**< \brief Can1 signal: CANRX1 */ +#define PIO_PB14A_CANTX1 (1u << 14) /**< \brief Can1 signal: CANTX1 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB15X1_DAC0 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */ +#define PIO_PB15X1_WKUP12 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */ +#define PIO_PB16X1_DAC1 (1u << 16) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA10B_DATRG (1u << 10) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EMAC peripheral ========== */ +#define PIO_PC13B_ECOL (1u << 13) /**< \brief Emac signal: ECOL */ +#define PIO_PC10B_ECRS (1u << 10) /**< \brief Emac signal: ECRS */ +#define PIO_PB4A_ECRSDV (1u << 4) /**< \brief Emac signal: ECRSDV/ERXDV */ +#define PIO_PB4A_ERXDV (1u << 4) /**< \brief Emac signal: ECRSDV/ERXDV */ +#define PIO_PB8A_EMDC (1u << 8) /**< \brief Emac signal: EMDC */ +#define PIO_PB9A_EMDIO (1u << 9) /**< \brief Emac signal: EMDIO */ +#define PIO_PB5A_ERX0 (1u << 5) /**< \brief Emac signal: ERX0 */ +#define PIO_PB6A_ERX1 (1u << 6) /**< \brief Emac signal: ERX1 */ +#define PIO_PC11B_ERX2 (1u << 11) /**< \brief Emac signal: ERX2 */ +#define PIO_PC12B_ERX3 (1u << 12) /**< \brief Emac signal: ERX3 */ +#define PIO_PC14B_ERXCK (1u << 14) /**< \brief Emac signal: ERXCK */ +#define PIO_PB7A_ERXER (1u << 7) /**< \brief Emac signal: ERXER */ +#define PIO_PB2A_ETX0 (1u << 2) /**< \brief Emac signal: ETX0 */ +#define PIO_PB3A_ETX1 (1u << 3) /**< \brief Emac signal: ETX1 */ +#define PIO_PC15B_ETX2 (1u << 15) /**< \brief Emac signal: ETX2 */ +#define PIO_PC16B_ETX3 (1u << 16) /**< \brief Emac signal: ETX3 */ +#define PIO_PB0A_ETXCK (1u << 0) /**< \brief Emac signal: ETXCK */ +#define PIO_PB1A_ETXEN (1u << 1) /**< \brief Emac signal: ETXEN */ +#define PIO_PC17B_ETXER (1u << 17) /**< \brief Emac signal: ETXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA20A_MCCDA (1u << 20) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PE20B_MCCDB (1u << 20) /**< \brief Hsmci signal: MCCDB */ +#define PIO_PA19A_MCCK (1u << 19) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA21A_MCDA0 (1u << 21) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA22A_MCDA1 (1u << 22) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA23A_MCDA2 (1u << 23) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA24A_MCDA3 (1u << 24) /**< \brief Hsmci signal: MCDA3 */ +#define PIO_PD0B_MCDA4 (1u << 0) /**< \brief Hsmci signal: MCDA4 */ +#define PIO_PD1B_MCDA5 (1u << 1) /**< \brief Hsmci signal: MCDA5 */ +#define PIO_PD2B_MCDA6 (1u << 2) /**< \brief Hsmci signal: MCDA6 */ +#define PIO_PD3B_MCDA7 (1u << 3) /**< \brief Hsmci signal: MCDA7 */ +#define PIO_PE22B_MCDB0 (1u << 22) /**< \brief Hsmci signal: MCDB0 */ +#define PIO_PE24B_MCDB1 (1u << 24) /**< \brief Hsmci signal: MCDB1 */ +#define PIO_PE26B_MCDB2 (1u << 26) /**< \brief Hsmci signal: MCDB2 */ +#define PIO_PE27B_MCDB3 (1u << 27) /**< \brief Hsmci signal: MCDB3 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA1B_PCK0 (1u << 1) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB22B_PCK0 (1u << 22) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA24B_PCK1 (1u << 24) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA30B_PCK1 (1u << 30) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA28B_PCK2 (1u << 28) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM peripheral ========== */ +#define PIO_PA5B_PWMFI0 (1u << 5) /**< \brief Pwm signal: PWMFI0 */ +#define PIO_PA3B_PWMFI1 (1u << 3) /**< \brief Pwm signal: PWMFI1 */ +#define PIO_PD6B_PWMFI2 (1u << 6) /**< \brief Pwm signal: PWMFI2 */ +#define PIO_PA8B_PWMH0 (1u << 8) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PB12B_PWMH0 (1u << 12) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PC3B_PWMH0 (1u << 3) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PE15A_PWMH0 (1u << 15) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PB13B_PWMH1 (1u << 13) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PC5B_PWMH1 (1u << 5) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PE16A_PWMH1 (1u << 16) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PB14B_PWMH2 (1u << 14) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PC7B_PWMH2 (1u << 7) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PB15B_PWMH3 (1u << 15) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PC9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PF3A_PWMH3 (1u << 3) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PC20B_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */ +#define PIO_PE20A_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */ +#define PIO_PC19B_PWMH5 (1u << 19) /**< \brief Pwm signal: PWMH5 */ +#define PIO_PE22A_PWMH5 (1u << 22) /**< \brief Pwm signal: PWMH5 */ +#define PIO_PC18B_PWMH6 (1u << 18) /**< \brief Pwm signal: PWMH6 */ +#define PIO_PE24A_PWMH6 (1u << 24) /**< \brief Pwm signal: PWMH6 */ +#define PIO_PE26A_PWMH7 (1u << 26) /**< \brief Pwm signal: PWMH7 */ +#define PIO_PA21B_PWML0 (1u << 21) /**< \brief Pwm signal: PWML0 */ +#define PIO_PB16B_PWML0 (1u << 16) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC2B_PWML0 (1u << 2) /**< \brief Pwm signal: PWML0 */ +#define PIO_PE18A_PWML0 (1u << 18) /**< \brief Pwm signal: PWML0 */ +#define PIO_PA12B_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */ +#define PIO_PB17B_PWML1 (1u << 17) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC4B_PWML1 (1u << 4) /**< \brief Pwm signal: PWML1 */ +#define PIO_PA20B_PWML2 (1u << 20) /**< \brief Pwm signal: PWML2 */ +#define PIO_PB18B_PWML2 (1u << 18) /**< \brief Pwm signal: PWML2 */ +#define PIO_PC6B_PWML2 (1u << 6) /**< \brief Pwm signal: PWML2 */ +#define PIO_PE17A_PWML2 (1u << 17) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA0B_PWML3 (1u << 0) /**< \brief Pwm signal: PWML3 */ +#define PIO_PB19B_PWML3 (1u << 19) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC8B_PWML3 (1u << 8) /**< \brief Pwm signal: PWML3 */ +#define PIO_PB6B_PWML4 (1u << 6) /**< \brief Pwm signal: PWML4 */ +#define PIO_PC21B_PWML4 (1u << 21) /**< \brief Pwm signal: PWML4 */ +#define PIO_PE19A_PWML4 (1u << 19) /**< \brief Pwm signal: PWML4 */ +#define PIO_PB7B_PWML5 (1u << 7) /**< \brief Pwm signal: PWML5 */ +#define PIO_PC22B_PWML5 (1u << 22) /**< \brief Pwm signal: PWML5 */ +#define PIO_PE21A_PWML5 (1u << 21) /**< \brief Pwm signal: PWML5 */ +#define PIO_PB8B_PWML6 (1u << 8) /**< \brief Pwm signal: PWML6 */ +#define PIO_PC23B_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */ +#define PIO_PE23A_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */ +#define PIO_PB9B_PWML7 (1u << 9) /**< \brief Pwm signal: PWML7 */ +#define PIO_PC24B_PWML7 (1u << 24) /**< \brief Pwm signal: PWML7 */ +#define PIO_PE25A_PWML7 (1u << 25) /**< \brief Pwm signal: PWML7 */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PA25A_SPI0_MISO (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PA26A_SPI0_MOSI (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PA27A_SPI0_SPCK (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PB18A_RD (1u << 18) /**< \brief Ssc signal: RD */ +#define PIO_PB17A_RF (1u << 17) /**< \brief Ssc signal: RF */ +#define PIO_PB19A_RK (1u << 19) /**< \brief Ssc signal: RK */ +#define PIO_PA16B_TD (1u << 16) /**< \brief Ssc signal: TD */ +#define PIO_PA15B_TF (1u << 15) /**< \brief Ssc signal: TF */ +#define PIO_PA14B_TK (1u << 14) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PB26B_TCLK0 (1u << 26) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA4A_TCLK1 (1u << 4) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA7A_TCLK2 (1u << 7) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PB25B_TIOA0 (1u << 25) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA2A_TIOA1 (1u << 2) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA5A_TIOA2 (1u << 5) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PB27B_TIOB0 (1u << 27) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA3A_TIOB1 (1u << 3) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA6A_TIOB2 (1u << 6) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PA22B_TCLK3 (1u << 22) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PA23B_TCLK4 (1u << 23) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PB16A_TCLK5 (1u << 16) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PB0B_TIOA3 (1u << 0) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PE9A_TIOA3 (1u << 9) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PB2B_TIOA4 (1u << 2) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PE11A_TIOA4 (1u << 11) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PB4B_TIOA5 (1u << 4) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PE13A_TIOA5 (1u << 13) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PB1B_TIOB3 (1u << 1) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PE10A_TIOB3 (1u << 10) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PB3B_TIOB4 (1u << 3) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PE12A_TIOB4 (1u << 12) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PB5B_TIOB5 (1u << 5) /**< \brief Tc1 signal: TIOB5 */ +#define PIO_PE14A_TIOB5 (1u << 14) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TWI0 peripheral ========== */ +#define PIO_PA18A_TWCK0 (1u << 18) /**< \brief Twi0 signal: TWCK0 */ +#define PIO_PA17A_TWD0 (1u << 17) /**< \brief Twi0 signal: TWD0 */ +/* ========== Pio definition for TWI1 peripheral ========== */ +#define PIO_PB13A_TWCK1 (1u << 13) /**< \brief Twi1 signal: TWCK1 */ +#define PIO_PB12A_TWD1 (1u << 12) /**< \brief Twi1 signal: TWD1 */ +/* ========== Pio definition for UART peripheral ========== */ +#define PIO_PA8A_URXD (1u << 8) /**< \brief Uart signal: URXD */ +#define PIO_PA9A_UTXD (1u << 9) /**< \brief Uart signal: UTXD */ +/* ========== Pio definition for UOTGHS peripheral ========== */ +#define PIO_PB11A_UOTGID (1u << 11) /**< \brief Uotghs signal: UOTGID */ +#define PIO_PB10A_UOTGVBOF (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB26A_CTS0 (1u << 26) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PB25A_RTS0 (1u << 25) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PA10A_RXD0 (1u << 10) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PA17B_SCK0 (1u << 17) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PA11A_TXD0 (1u << 11) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA15A_CTS1 (1u << 15) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA14A_RTS1 (1u << 14) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA12A_RXD1 (1u << 12) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA16A_SCK1 (1u << 16) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PA13A_TXD1 (1u << 13) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PB23A_CTS2 (1u << 23) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PB22A_RTS2 (1u << 22) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PB21A_RXD2 (1u << 21) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PB24A_SCK2 (1u << 24) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PB20A_TXD2 (1u << 20) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB10_IDX 42 +#define PIO_PB11_IDX 43 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PB14_IDX 46 +#define PIO_PB15_IDX 47 +#define PIO_PB16_IDX 48 +#define PIO_PB17_IDX 49 +#define PIO_PB18_IDX 50 +#define PIO_PB19_IDX 51 +#define PIO_PB20_IDX 52 +#define PIO_PB21_IDX 53 +#define PIO_PB22_IDX 54 +#define PIO_PB23_IDX 55 +#define PIO_PB24_IDX 56 +#define PIO_PB25_IDX 57 +#define PIO_PB26_IDX 58 +#define PIO_PB27_IDX 59 +#define PIO_PB28_IDX 60 +#define PIO_PB29_IDX 61 +#define PIO_PB30_IDX 62 +#define PIO_PB31_IDX 63 + +#endif /* _SAM3X4C_PIO_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x4e.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x4e.h new file mode 100644 index 0000000..f1fbbb9 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x4e.h @@ -0,0 +1,567 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3X4E_PIO_ +#define _SAM3X4E_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ +#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ +#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */ +#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */ +#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */ +#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */ +#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */ +#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */ +#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */ +#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */ +#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */ +#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */ +#define PIO_PB25 (1u << 25) /**< \brief Pin Controlled by PB25 */ +#define PIO_PB26 (1u << 26) /**< \brief Pin Controlled by PB26 */ +#define PIO_PB27 (1u << 27) /**< \brief Pin Controlled by PB27 */ +#define PIO_PB28 (1u << 28) /**< \brief Pin Controlled by PB28 */ +#define PIO_PB29 (1u << 29) /**< \brief Pin Controlled by PB29 */ +#define PIO_PB30 (1u << 30) /**< \brief Pin Controlled by PB30 */ +#define PIO_PB31 (1u << 31) /**< \brief Pin Controlled by PB31 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +/* ========== Pio definition for ADC peripheral ========== */ +#define PIO_PA2X1_AD0 (1u << 2) /**< \brief Adc signal: AD0 */ +#define PIO_PA3X1_AD1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */ +#define PIO_PA3X1_WKUP1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */ +#define PIO_PB17X1_AD10 (1u << 17) /**< \brief Adc signal: AD10 */ +#define PIO_PB18X1_AD11 (1u << 18) /**< \brief Adc signal: AD11 */ +#define PIO_PB19X1_AD12 (1u << 19) /**< \brief Adc signal: AD12 */ +#define PIO_PB20X1_AD13 (1u << 20) /**< \brief Adc signal: AD13 */ +#define PIO_PB21X1_AD14 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */ +#define PIO_PB21X1_WKUP13 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */ +#define PIO_PA4X1_AD2 (1u << 4) /**< \brief Adc signal: AD2 */ +#define PIO_PA6X1_AD3 (1u << 6) /**< \brief Adc signal: AD3 */ +#define PIO_PA22X1_AD4 (1u << 22) /**< \brief Adc signal: AD4 */ +#define PIO_PA23X1_AD5 (1u << 23) /**< \brief Adc signal: AD5 */ +#define PIO_PA24X1_AD6 (1u << 24) /**< \brief Adc signal: AD6 */ +#define PIO_PA16X1_AD7 (1u << 16) /**< \brief Adc signal: AD7 */ +#define PIO_PB12X1_AD8 (1u << 12) /**< \brief Adc signal: AD8 */ +#define PIO_PB13X1_AD9 (1u << 13) /**< \brief Adc signal: AD9 */ +#define PIO_PA11B_ADTRG (1u << 11) /**< \brief Adc signal: ADTRG */ +/* ========== Pio definition for CAN0 peripheral ========== */ +#define PIO_PA1A_CANRX0 (1u << 1) /**< \brief Can0 signal: CANRX0 */ +#define PIO_PA0A_CANTX0 (1u << 0) /**< \brief Can0 signal: CANTX0 */ +/* ========== Pio definition for CAN1 peripheral ========== */ +#define PIO_PB15A_CANRX1 (1u << 15) /**< \brief Can1 signal: CANRX1 */ +#define PIO_PB14A_CANTX1 (1u << 14) /**< \brief Can1 signal: CANTX1 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB15X1_DAC0 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */ +#define PIO_PB15X1_WKUP12 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */ +#define PIO_PB16X1_DAC1 (1u << 16) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA10B_DATRG (1u << 10) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC21A_A0 (1u << 21) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC21A_NBS0 (1u << 21) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC22A_A1 (1u << 22) /**< \brief Ebi signal: A1 */ +#define PIO_PD0A_A10 (1u << 0) /**< \brief Ebi signal: A10 */ +#define PIO_PD22A_A10 (1u << 22) /**< \brief Ebi signal: A10 */ +#define PIO_PD1A_A11 (1u << 1) /**< \brief Ebi signal: A11 */ +#define PIO_PD23A_A11 (1u << 23) /**< \brief Ebi signal: A11 */ +#define PIO_PD2A_A12 (1u << 2) /**< \brief Ebi signal: A12 */ +#define PIO_PD24A_A12 (1u << 24) /**< \brief Ebi signal: A12 */ +#define PIO_PD3A_A13 (1u << 3) /**< \brief Ebi signal: A13 */ +#define PIO_PD25A_A13 (1u << 25) /**< \brief Ebi signal: A13 */ +#define PIO_PD4A_A14 (1u << 4) /**< \brief Ebi signal: A14 */ +#define PIO_PD26A_A14 (1u << 26) /**< \brief Ebi signal: A14 */ +#define PIO_PD5A_A15 (1u << 5) /**< \brief Ebi signal: A15 */ +#define PIO_PD27A_A15 (1u << 27) /**< \brief Ebi signal: A15 */ +#define PIO_PD6A_A16 (1u << 6) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PD6A_BA0 (1u << 6) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PD28A_A16 (1u << 28) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PD28A_BA0 (1u << 28) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PD7A_A17 (1u << 7) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PD7A_BA1 (1u << 7) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PD29A_A17 (1u << 29) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PD29A_BA1 (1u << 29) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA25B_A18 (1u << 25) /**< \brief Ebi signal: A18 */ +#define PIO_PB10B_A18 (1u << 10) /**< \brief Ebi signal: A18 */ +#define PIO_PD30A_A18 (1u << 30) /**< \brief Ebi signal: A18 */ +#define PIO_PA26B_A19 (1u << 26) /**< \brief Ebi signal: A19 */ +#define PIO_PB11B_A19 (1u << 11) /**< \brief Ebi signal: A19 */ +#define PIO_PE0A_A19 (1u << 0) /**< \brief Ebi signal: A19 */ +#define PIO_PC23A_A2 (1u << 23) /**< \brief Ebi signal: A2 */ +#define PIO_PA18B_A20 (1u << 18) /**< \brief Ebi signal: A20 */ +#define PIO_PA27B_A20 (1u << 27) /**< \brief Ebi signal: A20 */ +#define PIO_PE1A_A20 (1u << 1) /**< \brief Ebi signal: A20 */ +#define PIO_PD8A_A21 (1u << 8) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PD8A_NANDALE (1u << 8) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PE2A_A21 (1u << 2) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PE2A_NANDALE (1u << 2) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PD9A_A22 (1u << 9) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PD9A_NANDCLE (1u << 9) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PE3A_A22 (1u << 3) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PE3A_NANDCLE (1u << 3) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PE4A_A23 (1u << 4) /**< \brief Ebi signal: A23 */ +#define PIO_PC24A_A3 (1u << 24) /**< \brief Ebi signal: A3 */ +#define PIO_PC25A_A4 (1u << 25) /**< \brief Ebi signal: A4 */ +#define PIO_PC26A_A5 (1u << 26) /**< \brief Ebi signal: A5 */ +#define PIO_PD17A_A5 (1u << 17) /**< \brief Ebi signal: A5 */ +#define PIO_PC27A_A6 (1u << 27) /**< \brief Ebi signal: A6 */ +#define PIO_PD18A_A6 (1u << 18) /**< \brief Ebi signal: A6 */ +#define PIO_PC28A_A7 (1u << 28) /**< \brief Ebi signal: A7 */ +#define PIO_PD19A_A7 (1u << 19) /**< \brief Ebi signal: A7 */ +#define PIO_PC29A_A8 (1u << 29) /**< \brief Ebi signal: A8 */ +#define PIO_PD20A_A8 (1u << 20) /**< \brief Ebi signal: A8 */ +#define PIO_PC30A_A9 (1u << 30) /**< \brief Ebi signal: A9 */ +#define PIO_PD21A_A9 (1u << 21) /**< \brief Ebi signal: A9 */ +#define PIO_PD16A_CAS (1u << 16) /**< \brief Ebi signal: CAS */ +#define PIO_PC2A_D0 (1u << 2) /**< \brief Ebi signal: D0 */ +#define PIO_PC3A_D1 (1u << 3) /**< \brief Ebi signal: D1 */ +#define PIO_PC12A_D10 (1u << 12) /**< \brief Ebi signal: D10 */ +#define PIO_PC13A_D11 (1u << 13) /**< \brief Ebi signal: D11 */ +#define PIO_PC14A_D12 (1u << 14) /**< \brief Ebi signal: D12 */ +#define PIO_PC15A_D13 (1u << 15) /**< \brief Ebi signal: D13 */ +#define PIO_PC16A_D14 (1u << 16) /**< \brief Ebi signal: D14 */ +#define PIO_PC17A_D15 (1u << 17) /**< \brief Ebi signal: D15 */ +#define PIO_PC4A_D2 (1u << 4) /**< \brief Ebi signal: D2 */ +#define PIO_PC5A_D3 (1u << 5) /**< \brief Ebi signal: D3 */ +#define PIO_PC6A_D4 (1u << 6) /**< \brief Ebi signal: D4 */ +#define PIO_PC7A_D5 (1u << 7) /**< \brief Ebi signal: D5 */ +#define PIO_PC8A_D6 (1u << 8) /**< \brief Ebi signal: D6 */ +#define PIO_PC9A_D7 (1u << 9) /**< \brief Ebi signal: D7 */ +#define PIO_PC10A_D8 (1u << 10) /**< \brief Ebi signal: D8 */ +#define PIO_PC11A_D9 (1u << 11) /**< \brief Ebi signal: D9 */ +#define PIO_PC19A_NANDOE (1u << 19) /**< \brief Ebi signal: NANDOE */ +#define PIO_PA2B_NANDRDY (1u << 2) /**< \brief Ebi signal: NANDRDY */ +#define PIO_PC20A_NANDWE (1u << 20) /**< \brief Ebi signal: NANDWE */ +#define PIO_PA6B_NCS0 (1u << 6) /**< \brief Ebi signal: NCS0 */ +#define PIO_PA7B_NCS1 (1u << 7) /**< \brief Ebi signal: NCS1 */ +#define PIO_PB24B_NCS2 (1u << 24) /**< \brief Ebi signal: NCS2 */ +#define PIO_PB27A_NCS3 (1u << 27) /**< \brief Ebi signal: NCS3 */ +#define PIO_PE5A_NCS4 (1u << 5) /**< \brief Ebi signal: NCS4 */ +#define PIO_PE6A_NCS5 (1u << 6) /**< \brief Ebi signal: NCS5 */ +#define PIO_PE18B_NCS6 (1u << 18) /**< \brief Ebi signal: NCS6 */ +#define PIO_PE27A_NCS7 (1u << 27) /**< \brief Ebi signal: NCS7 */ +#define PIO_PA29B_NRD (1u << 29) /**< \brief Ebi signal: NRD */ +#define PIO_PA4B_NWAIT (1u << 4) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC18A_NWR0 (1u << 18) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC18A_NWE (1u << 18) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD10A_NWR1 (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD10A_NBS1 (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15A_RAS (1u << 15) /**< \brief Ebi signal: RAS */ +#define PIO_PD11A_SDA10 (1u << 11) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13A_SDCKE (1u << 13) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD12A_SDCS (1u << 12) /**< \brief Ebi signal: SDCS */ +#define PIO_PD14A_SDWE (1u << 14) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for EMAC peripheral ========== */ +#define PIO_PC13B_ECOL (1u << 13) /**< \brief Emac signal: ECOL */ +#define PIO_PC10B_ECRS (1u << 10) /**< \brief Emac signal: ECRS */ +#define PIO_PB4A_ECRSDV (1u << 4) /**< \brief Emac signal: ECRSDV/ERXDV */ +#define PIO_PB4A_ERXDV (1u << 4) /**< \brief Emac signal: ECRSDV/ERXDV */ +#define PIO_PB8A_EMDC (1u << 8) /**< \brief Emac signal: EMDC */ +#define PIO_PB9A_EMDIO (1u << 9) /**< \brief Emac signal: EMDIO */ +#define PIO_PB5A_ERX0 (1u << 5) /**< \brief Emac signal: ERX0 */ +#define PIO_PB6A_ERX1 (1u << 6) /**< \brief Emac signal: ERX1 */ +#define PIO_PC11B_ERX2 (1u << 11) /**< \brief Emac signal: ERX2 */ +#define PIO_PC12B_ERX3 (1u << 12) /**< \brief Emac signal: ERX3 */ +#define PIO_PC14B_ERXCK (1u << 14) /**< \brief Emac signal: ERXCK */ +#define PIO_PB7A_ERXER (1u << 7) /**< \brief Emac signal: ERXER */ +#define PIO_PB2A_ETX0 (1u << 2) /**< \brief Emac signal: ETX0 */ +#define PIO_PB3A_ETX1 (1u << 3) /**< \brief Emac signal: ETX1 */ +#define PIO_PC15B_ETX2 (1u << 15) /**< \brief Emac signal: ETX2 */ +#define PIO_PC16B_ETX3 (1u << 16) /**< \brief Emac signal: ETX3 */ +#define PIO_PB0A_ETXCK (1u << 0) /**< \brief Emac signal: ETXCK */ +#define PIO_PB1A_ETXEN (1u << 1) /**< \brief Emac signal: ETXEN */ +#define PIO_PC17B_ETXER (1u << 17) /**< \brief Emac signal: ETXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA20A_MCCDA (1u << 20) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PE20B_MCCDB (1u << 20) /**< \brief Hsmci signal: MCCDB */ +#define PIO_PA19A_MCCK (1u << 19) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA21A_MCDA0 (1u << 21) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA22A_MCDA1 (1u << 22) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA23A_MCDA2 (1u << 23) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA24A_MCDA3 (1u << 24) /**< \brief Hsmci signal: MCDA3 */ +#define PIO_PD0B_MCDA4 (1u << 0) /**< \brief Hsmci signal: MCDA4 */ +#define PIO_PD1B_MCDA5 (1u << 1) /**< \brief Hsmci signal: MCDA5 */ +#define PIO_PD2B_MCDA6 (1u << 2) /**< \brief Hsmci signal: MCDA6 */ +#define PIO_PD3B_MCDA7 (1u << 3) /**< \brief Hsmci signal: MCDA7 */ +#define PIO_PE22B_MCDB0 (1u << 22) /**< \brief Hsmci signal: MCDB0 */ +#define PIO_PE24B_MCDB1 (1u << 24) /**< \brief Hsmci signal: MCDB1 */ +#define PIO_PE26B_MCDB2 (1u << 26) /**< \brief Hsmci signal: MCDB2 */ +#define PIO_PE27B_MCDB3 (1u << 27) /**< \brief Hsmci signal: MCDB3 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA1B_PCK0 (1u << 1) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB22B_PCK0 (1u << 22) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA24B_PCK1 (1u << 24) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA30B_PCK1 (1u << 30) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA28B_PCK2 (1u << 28) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM peripheral ========== */ +#define PIO_PA5B_PWMFI0 (1u << 5) /**< \brief Pwm signal: PWMFI0 */ +#define PIO_PA3B_PWMFI1 (1u << 3) /**< \brief Pwm signal: PWMFI1 */ +#define PIO_PD6B_PWMFI2 (1u << 6) /**< \brief Pwm signal: PWMFI2 */ +#define PIO_PA8B_PWMH0 (1u << 8) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PB12B_PWMH0 (1u << 12) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PC3B_PWMH0 (1u << 3) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PE15A_PWMH0 (1u << 15) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PB13B_PWMH1 (1u << 13) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PC5B_PWMH1 (1u << 5) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PE16A_PWMH1 (1u << 16) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PB14B_PWMH2 (1u << 14) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PC7B_PWMH2 (1u << 7) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PB15B_PWMH3 (1u << 15) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PC9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PF3A_PWMH3 (1u << 3) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PC20B_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */ +#define PIO_PE20A_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */ +#define PIO_PC19B_PWMH5 (1u << 19) /**< \brief Pwm signal: PWMH5 */ +#define PIO_PE22A_PWMH5 (1u << 22) /**< \brief Pwm signal: PWMH5 */ +#define PIO_PC18B_PWMH6 (1u << 18) /**< \brief Pwm signal: PWMH6 */ +#define PIO_PE24A_PWMH6 (1u << 24) /**< \brief Pwm signal: PWMH6 */ +#define PIO_PE26A_PWMH7 (1u << 26) /**< \brief Pwm signal: PWMH7 */ +#define PIO_PA21B_PWML0 (1u << 21) /**< \brief Pwm signal: PWML0 */ +#define PIO_PB16B_PWML0 (1u << 16) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC2B_PWML0 (1u << 2) /**< \brief Pwm signal: PWML0 */ +#define PIO_PE18A_PWML0 (1u << 18) /**< \brief Pwm signal: PWML0 */ +#define PIO_PA12B_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */ +#define PIO_PB17B_PWML1 (1u << 17) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC4B_PWML1 (1u << 4) /**< \brief Pwm signal: PWML1 */ +#define PIO_PA20B_PWML2 (1u << 20) /**< \brief Pwm signal: PWML2 */ +#define PIO_PB18B_PWML2 (1u << 18) /**< \brief Pwm signal: PWML2 */ +#define PIO_PC6B_PWML2 (1u << 6) /**< \brief Pwm signal: PWML2 */ +#define PIO_PE17A_PWML2 (1u << 17) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA0B_PWML3 (1u << 0) /**< \brief Pwm signal: PWML3 */ +#define PIO_PB19B_PWML3 (1u << 19) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC8B_PWML3 (1u << 8) /**< \brief Pwm signal: PWML3 */ +#define PIO_PB6B_PWML4 (1u << 6) /**< \brief Pwm signal: PWML4 */ +#define PIO_PC21B_PWML4 (1u << 21) /**< \brief Pwm signal: PWML4 */ +#define PIO_PE19A_PWML4 (1u << 19) /**< \brief Pwm signal: PWML4 */ +#define PIO_PB7B_PWML5 (1u << 7) /**< \brief Pwm signal: PWML5 */ +#define PIO_PC22B_PWML5 (1u << 22) /**< \brief Pwm signal: PWML5 */ +#define PIO_PE21A_PWML5 (1u << 21) /**< \brief Pwm signal: PWML5 */ +#define PIO_PB8B_PWML6 (1u << 8) /**< \brief Pwm signal: PWML6 */ +#define PIO_PC23B_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */ +#define PIO_PE23A_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */ +#define PIO_PB9B_PWML7 (1u << 9) /**< \brief Pwm signal: PWML7 */ +#define PIO_PC24B_PWML7 (1u << 24) /**< \brief Pwm signal: PWML7 */ +#define PIO_PE25A_PWML7 (1u << 25) /**< \brief Pwm signal: PWML7 */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PA25A_SPI0_MISO (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PA26A_SPI0_MOSI (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PA27A_SPI0_SPCK (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PB18A_RD (1u << 18) /**< \brief Ssc signal: RD */ +#define PIO_PB17A_RF (1u << 17) /**< \brief Ssc signal: RF */ +#define PIO_PB19A_RK (1u << 19) /**< \brief Ssc signal: RK */ +#define PIO_PA16B_TD (1u << 16) /**< \brief Ssc signal: TD */ +#define PIO_PA15B_TF (1u << 15) /**< \brief Ssc signal: TF */ +#define PIO_PA14B_TK (1u << 14) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PB26B_TCLK0 (1u << 26) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA4A_TCLK1 (1u << 4) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA7A_TCLK2 (1u << 7) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PB25B_TIOA0 (1u << 25) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA2A_TIOA1 (1u << 2) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA5A_TIOA2 (1u << 5) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PB27B_TIOB0 (1u << 27) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA3A_TIOB1 (1u << 3) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA6A_TIOB2 (1u << 6) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PA22B_TCLK3 (1u << 22) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PA23B_TCLK4 (1u << 23) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PB16A_TCLK5 (1u << 16) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PB0B_TIOA3 (1u << 0) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PE9A_TIOA3 (1u << 9) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PB2B_TIOA4 (1u << 2) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PE11A_TIOA4 (1u << 11) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PB4B_TIOA5 (1u << 4) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PE13A_TIOA5 (1u << 13) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PB1B_TIOB3 (1u << 1) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PE10A_TIOB3 (1u << 10) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PB3B_TIOB4 (1u << 3) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PE12A_TIOB4 (1u << 12) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PB5B_TIOB5 (1u << 5) /**< \brief Tc1 signal: TIOB5 */ +#define PIO_PE14A_TIOB5 (1u << 14) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC27B_TCLK6 (1u << 27) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC30B_TCLK7 (1u << 30) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PD9B_TCLK8 (1u << 9) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC25B_TIOA6 (1u << 25) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC28B_TIOA7 (1u << 28) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PD7B_TIOA8 (1u << 7) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC26B_TIOB6 (1u << 26) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC29B_TIOB7 (1u << 29) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PD8B_TIOB8 (1u << 8) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TWI0 peripheral ========== */ +#define PIO_PA18A_TWCK0 (1u << 18) /**< \brief Twi0 signal: TWCK0 */ +#define PIO_PA17A_TWD0 (1u << 17) /**< \brief Twi0 signal: TWD0 */ +/* ========== Pio definition for TWI1 peripheral ========== */ +#define PIO_PB13A_TWCK1 (1u << 13) /**< \brief Twi1 signal: TWCK1 */ +#define PIO_PB12A_TWD1 (1u << 12) /**< \brief Twi1 signal: TWD1 */ +/* ========== Pio definition for UART peripheral ========== */ +#define PIO_PA8A_URXD (1u << 8) /**< \brief Uart signal: URXD */ +#define PIO_PA9A_UTXD (1u << 9) /**< \brief Uart signal: UTXD */ +/* ========== Pio definition for UOTGHS peripheral ========== */ +#define PIO_PB11A_UOTGID (1u << 11) /**< \brief Uotghs signal: UOTGID */ +#define PIO_PB10A_UOTGVBOF (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB26A_CTS0 (1u << 26) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PB25A_RTS0 (1u << 25) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PA10A_RXD0 (1u << 10) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PA17B_SCK0 (1u << 17) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PA11A_TXD0 (1u << 11) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA15A_CTS1 (1u << 15) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA14A_RTS1 (1u << 14) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA12A_RXD1 (1u << 12) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA16A_SCK1 (1u << 16) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PA13A_TXD1 (1u << 13) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PB23A_CTS2 (1u << 23) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PB22A_RTS2 (1u << 22) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PB21A_RXD2 (1u << 21) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PB24A_SCK2 (1u << 24) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PB20A_TXD2 (1u << 20) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio definition for USART3 peripheral ========== */ +#define PIO_PF4A_CTS3 (1u << 4) /**< \brief Usart3 signal: CTS3 */ +#define PIO_PF5A_RTS3 (1u << 5) /**< \brief Usart3 signal: RTS3 */ +#define PIO_PD5B_RXD3 (1u << 5) /**< \brief Usart3 signal: RXD3 */ +#define PIO_PE16B_SCK3 (1u << 16) /**< \brief Usart3 signal: SCK3 */ +#define PIO_PD4B_TXD3 (1u << 4) /**< \brief Usart3 signal: TXD3 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB10_IDX 42 +#define PIO_PB11_IDX 43 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PB14_IDX 46 +#define PIO_PB15_IDX 47 +#define PIO_PB16_IDX 48 +#define PIO_PB17_IDX 49 +#define PIO_PB18_IDX 50 +#define PIO_PB19_IDX 51 +#define PIO_PB20_IDX 52 +#define PIO_PB21_IDX 53 +#define PIO_PB22_IDX 54 +#define PIO_PB23_IDX 55 +#define PIO_PB24_IDX 56 +#define PIO_PB25_IDX 57 +#define PIO_PB26_IDX 58 +#define PIO_PB27_IDX 59 +#define PIO_PB28_IDX 60 +#define PIO_PB29_IDX 61 +#define PIO_PB30_IDX 62 +#define PIO_PB31_IDX 63 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 + +#endif /* _SAM3X4E_PIO_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8c.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8c.h new file mode 100644 index 0000000..a8f2ed1 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8c.h @@ -0,0 +1,373 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3X8C_PIO_ +#define _SAM3X8C_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ +#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ +#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */ +#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */ +#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */ +#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */ +#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */ +#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */ +#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */ +#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */ +#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */ +#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */ +#define PIO_PB25 (1u << 25) /**< \brief Pin Controlled by PB25 */ +#define PIO_PB26 (1u << 26) /**< \brief Pin Controlled by PB26 */ +#define PIO_PB27 (1u << 27) /**< \brief Pin Controlled by PB27 */ +#define PIO_PB28 (1u << 28) /**< \brief Pin Controlled by PB28 */ +#define PIO_PB29 (1u << 29) /**< \brief Pin Controlled by PB29 */ +#define PIO_PB30 (1u << 30) /**< \brief Pin Controlled by PB30 */ +#define PIO_PB31 (1u << 31) /**< \brief Pin Controlled by PB31 */ +/* ========== Pio definition for ADC peripheral ========== */ +#define PIO_PA2X1_AD0 (1u << 2) /**< \brief Adc signal: AD0 */ +#define PIO_PA3X1_AD1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */ +#define PIO_PA3X1_WKUP1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */ +#define PIO_PB17X1_AD10 (1u << 17) /**< \brief Adc signal: AD10 */ +#define PIO_PB18X1_AD11 (1u << 18) /**< \brief Adc signal: AD11 */ +#define PIO_PB19X1_AD12 (1u << 19) /**< \brief Adc signal: AD12 */ +#define PIO_PB20X1_AD13 (1u << 20) /**< \brief Adc signal: AD13 */ +#define PIO_PB21X1_AD14 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */ +#define PIO_PB21X1_WKUP13 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */ +#define PIO_PA4X1_AD2 (1u << 4) /**< \brief Adc signal: AD2 */ +#define PIO_PA6X1_AD3 (1u << 6) /**< \brief Adc signal: AD3 */ +#define PIO_PA22X1_AD4 (1u << 22) /**< \brief Adc signal: AD4 */ +#define PIO_PA23X1_AD5 (1u << 23) /**< \brief Adc signal: AD5 */ +#define PIO_PA24X1_AD6 (1u << 24) /**< \brief Adc signal: AD6 */ +#define PIO_PA16X1_AD7 (1u << 16) /**< \brief Adc signal: AD7 */ +#define PIO_PB12X1_AD8 (1u << 12) /**< \brief Adc signal: AD8 */ +#define PIO_PB13X1_AD9 (1u << 13) /**< \brief Adc signal: AD9 */ +#define PIO_PA11B_ADTRG (1u << 11) /**< \brief Adc signal: ADTRG */ +/* ========== Pio definition for CAN0 peripheral ========== */ +#define PIO_PA1A_CANRX0 (1u << 1) /**< \brief Can0 signal: CANRX0 */ +#define PIO_PA0A_CANTX0 (1u << 0) /**< \brief Can0 signal: CANTX0 */ +/* ========== Pio definition for CAN1 peripheral ========== */ +#define PIO_PB15A_CANRX1 (1u << 15) /**< \brief Can1 signal: CANRX1 */ +#define PIO_PB14A_CANTX1 (1u << 14) /**< \brief Can1 signal: CANTX1 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB15X1_DAC0 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */ +#define PIO_PB15X1_WKUP12 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */ +#define PIO_PB16X1_DAC1 (1u << 16) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA10B_DATRG (1u << 10) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EMAC peripheral ========== */ +#define PIO_PC13B_ECOL (1u << 13) /**< \brief Emac signal: ECOL */ +#define PIO_PC10B_ECRS (1u << 10) /**< \brief Emac signal: ECRS */ +#define PIO_PB4A_ECRSDV (1u << 4) /**< \brief Emac signal: ECRSDV/ERXDV */ +#define PIO_PB4A_ERXDV (1u << 4) /**< \brief Emac signal: ECRSDV/ERXDV */ +#define PIO_PB8A_EMDC (1u << 8) /**< \brief Emac signal: EMDC */ +#define PIO_PB9A_EMDIO (1u << 9) /**< \brief Emac signal: EMDIO */ +#define PIO_PB5A_ERX0 (1u << 5) /**< \brief Emac signal: ERX0 */ +#define PIO_PB6A_ERX1 (1u << 6) /**< \brief Emac signal: ERX1 */ +#define PIO_PC11B_ERX2 (1u << 11) /**< \brief Emac signal: ERX2 */ +#define PIO_PC12B_ERX3 (1u << 12) /**< \brief Emac signal: ERX3 */ +#define PIO_PC14B_ERXCK (1u << 14) /**< \brief Emac signal: ERXCK */ +#define PIO_PB7A_ERXER (1u << 7) /**< \brief Emac signal: ERXER */ +#define PIO_PB2A_ETX0 (1u << 2) /**< \brief Emac signal: ETX0 */ +#define PIO_PB3A_ETX1 (1u << 3) /**< \brief Emac signal: ETX1 */ +#define PIO_PC15B_ETX2 (1u << 15) /**< \brief Emac signal: ETX2 */ +#define PIO_PC16B_ETX3 (1u << 16) /**< \brief Emac signal: ETX3 */ +#define PIO_PB0A_ETXCK (1u << 0) /**< \brief Emac signal: ETXCK */ +#define PIO_PB1A_ETXEN (1u << 1) /**< \brief Emac signal: ETXEN */ +#define PIO_PC17B_ETXER (1u << 17) /**< \brief Emac signal: ETXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA20A_MCCDA (1u << 20) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PE20B_MCCDB (1u << 20) /**< \brief Hsmci signal: MCCDB */ +#define PIO_PA19A_MCCK (1u << 19) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA21A_MCDA0 (1u << 21) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA22A_MCDA1 (1u << 22) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA23A_MCDA2 (1u << 23) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA24A_MCDA3 (1u << 24) /**< \brief Hsmci signal: MCDA3 */ +#define PIO_PD0B_MCDA4 (1u << 0) /**< \brief Hsmci signal: MCDA4 */ +#define PIO_PD1B_MCDA5 (1u << 1) /**< \brief Hsmci signal: MCDA5 */ +#define PIO_PD2B_MCDA6 (1u << 2) /**< \brief Hsmci signal: MCDA6 */ +#define PIO_PD3B_MCDA7 (1u << 3) /**< \brief Hsmci signal: MCDA7 */ +#define PIO_PE22B_MCDB0 (1u << 22) /**< \brief Hsmci signal: MCDB0 */ +#define PIO_PE24B_MCDB1 (1u << 24) /**< \brief Hsmci signal: MCDB1 */ +#define PIO_PE26B_MCDB2 (1u << 26) /**< \brief Hsmci signal: MCDB2 */ +#define PIO_PE27B_MCDB3 (1u << 27) /**< \brief Hsmci signal: MCDB3 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA1B_PCK0 (1u << 1) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB22B_PCK0 (1u << 22) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA24B_PCK1 (1u << 24) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA30B_PCK1 (1u << 30) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA28B_PCK2 (1u << 28) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM peripheral ========== */ +#define PIO_PA5B_PWMFI0 (1u << 5) /**< \brief Pwm signal: PWMFI0 */ +#define PIO_PA3B_PWMFI1 (1u << 3) /**< \brief Pwm signal: PWMFI1 */ +#define PIO_PD6B_PWMFI2 (1u << 6) /**< \brief Pwm signal: PWMFI2 */ +#define PIO_PA8B_PWMH0 (1u << 8) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PB12B_PWMH0 (1u << 12) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PC3B_PWMH0 (1u << 3) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PE15A_PWMH0 (1u << 15) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PB13B_PWMH1 (1u << 13) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PC5B_PWMH1 (1u << 5) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PE16A_PWMH1 (1u << 16) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PB14B_PWMH2 (1u << 14) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PC7B_PWMH2 (1u << 7) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PB15B_PWMH3 (1u << 15) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PC9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PF3A_PWMH3 (1u << 3) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PC20B_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */ +#define PIO_PE20A_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */ +#define PIO_PC19B_PWMH5 (1u << 19) /**< \brief Pwm signal: PWMH5 */ +#define PIO_PE22A_PWMH5 (1u << 22) /**< \brief Pwm signal: PWMH5 */ +#define PIO_PC18B_PWMH6 (1u << 18) /**< \brief Pwm signal: PWMH6 */ +#define PIO_PE24A_PWMH6 (1u << 24) /**< \brief Pwm signal: PWMH6 */ +#define PIO_PE26A_PWMH7 (1u << 26) /**< \brief Pwm signal: PWMH7 */ +#define PIO_PA21B_PWML0 (1u << 21) /**< \brief Pwm signal: PWML0 */ +#define PIO_PB16B_PWML0 (1u << 16) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC2B_PWML0 (1u << 2) /**< \brief Pwm signal: PWML0 */ +#define PIO_PE18A_PWML0 (1u << 18) /**< \brief Pwm signal: PWML0 */ +#define PIO_PA12B_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */ +#define PIO_PB17B_PWML1 (1u << 17) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC4B_PWML1 (1u << 4) /**< \brief Pwm signal: PWML1 */ +#define PIO_PA20B_PWML2 (1u << 20) /**< \brief Pwm signal: PWML2 */ +#define PIO_PB18B_PWML2 (1u << 18) /**< \brief Pwm signal: PWML2 */ +#define PIO_PC6B_PWML2 (1u << 6) /**< \brief Pwm signal: PWML2 */ +#define PIO_PE17A_PWML2 (1u << 17) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA0B_PWML3 (1u << 0) /**< \brief Pwm signal: PWML3 */ +#define PIO_PB19B_PWML3 (1u << 19) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC8B_PWML3 (1u << 8) /**< \brief Pwm signal: PWML3 */ +#define PIO_PB6B_PWML4 (1u << 6) /**< \brief Pwm signal: PWML4 */ +#define PIO_PC21B_PWML4 (1u << 21) /**< \brief Pwm signal: PWML4 */ +#define PIO_PE19A_PWML4 (1u << 19) /**< \brief Pwm signal: PWML4 */ +#define PIO_PB7B_PWML5 (1u << 7) /**< \brief Pwm signal: PWML5 */ +#define PIO_PC22B_PWML5 (1u << 22) /**< \brief Pwm signal: PWML5 */ +#define PIO_PE21A_PWML5 (1u << 21) /**< \brief Pwm signal: PWML5 */ +#define PIO_PB8B_PWML6 (1u << 8) /**< \brief Pwm signal: PWML6 */ +#define PIO_PC23B_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */ +#define PIO_PE23A_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */ +#define PIO_PB9B_PWML7 (1u << 9) /**< \brief Pwm signal: PWML7 */ +#define PIO_PC24B_PWML7 (1u << 24) /**< \brief Pwm signal: PWML7 */ +#define PIO_PE25A_PWML7 (1u << 25) /**< \brief Pwm signal: PWML7 */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PA25A_SPI0_MISO (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PA26A_SPI0_MOSI (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PA27A_SPI0_SPCK (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PB18A_RD (1u << 18) /**< \brief Ssc signal: RD */ +#define PIO_PB17A_RF (1u << 17) /**< \brief Ssc signal: RF */ +#define PIO_PB19A_RK (1u << 19) /**< \brief Ssc signal: RK */ +#define PIO_PA16B_TD (1u << 16) /**< \brief Ssc signal: TD */ +#define PIO_PA15B_TF (1u << 15) /**< \brief Ssc signal: TF */ +#define PIO_PA14B_TK (1u << 14) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PB26B_TCLK0 (1u << 26) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA4A_TCLK1 (1u << 4) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA7A_TCLK2 (1u << 7) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PB25B_TIOA0 (1u << 25) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA2A_TIOA1 (1u << 2) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA5A_TIOA2 (1u << 5) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PB27B_TIOB0 (1u << 27) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA3A_TIOB1 (1u << 3) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA6A_TIOB2 (1u << 6) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PA22B_TCLK3 (1u << 22) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PA23B_TCLK4 (1u << 23) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PB16A_TCLK5 (1u << 16) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PB0B_TIOA3 (1u << 0) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PE9A_TIOA3 (1u << 9) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PB2B_TIOA4 (1u << 2) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PE11A_TIOA4 (1u << 11) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PB4B_TIOA5 (1u << 4) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PE13A_TIOA5 (1u << 13) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PB1B_TIOB3 (1u << 1) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PE10A_TIOB3 (1u << 10) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PB3B_TIOB4 (1u << 3) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PE12A_TIOB4 (1u << 12) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PB5B_TIOB5 (1u << 5) /**< \brief Tc1 signal: TIOB5 */ +#define PIO_PE14A_TIOB5 (1u << 14) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TWI0 peripheral ========== */ +#define PIO_PA18A_TWCK0 (1u << 18) /**< \brief Twi0 signal: TWCK0 */ +#define PIO_PA17A_TWD0 (1u << 17) /**< \brief Twi0 signal: TWD0 */ +/* ========== Pio definition for TWI1 peripheral ========== */ +#define PIO_PB13A_TWCK1 (1u << 13) /**< \brief Twi1 signal: TWCK1 */ +#define PIO_PB12A_TWD1 (1u << 12) /**< \brief Twi1 signal: TWD1 */ +/* ========== Pio definition for UART peripheral ========== */ +#define PIO_PA8A_URXD (1u << 8) /**< \brief Uart signal: URXD */ +#define PIO_PA9A_UTXD (1u << 9) /**< \brief Uart signal: UTXD */ +/* ========== Pio definition for UOTGHS peripheral ========== */ +#define PIO_PB11A_UOTGID (1u << 11) /**< \brief Uotghs signal: UOTGID */ +#define PIO_PB10A_UOTGVBOF (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB26A_CTS0 (1u << 26) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PB25A_RTS0 (1u << 25) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PA10A_RXD0 (1u << 10) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PA17B_SCK0 (1u << 17) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PA11A_TXD0 (1u << 11) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA15A_CTS1 (1u << 15) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA14A_RTS1 (1u << 14) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA12A_RXD1 (1u << 12) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA16A_SCK1 (1u << 16) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PA13A_TXD1 (1u << 13) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PB23A_CTS2 (1u << 23) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PB22A_RTS2 (1u << 22) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PB21A_RXD2 (1u << 21) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PB24A_SCK2 (1u << 24) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PB20A_TXD2 (1u << 20) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB10_IDX 42 +#define PIO_PB11_IDX 43 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PB14_IDX 46 +#define PIO_PB15_IDX 47 +#define PIO_PB16_IDX 48 +#define PIO_PB17_IDX 49 +#define PIO_PB18_IDX 50 +#define PIO_PB19_IDX 51 +#define PIO_PB20_IDX 52 +#define PIO_PB21_IDX 53 +#define PIO_PB22_IDX 54 +#define PIO_PB23_IDX 55 +#define PIO_PB24_IDX 56 +#define PIO_PB25_IDX 57 +#define PIO_PB26_IDX 58 +#define PIO_PB27_IDX 59 +#define PIO_PB28_IDX 60 +#define PIO_PB29_IDX 61 +#define PIO_PB30_IDX 62 +#define PIO_PB31_IDX 63 + +#endif /* _SAM3X8C_PIO_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h new file mode 100644 index 0000000..d2d7ae7 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8e.h @@ -0,0 +1,567 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3X8E_PIO_ +#define _SAM3X8E_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ +#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ +#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */ +#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */ +#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */ +#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */ +#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */ +#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */ +#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */ +#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */ +#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */ +#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */ +#define PIO_PB25 (1u << 25) /**< \brief Pin Controlled by PB25 */ +#define PIO_PB26 (1u << 26) /**< \brief Pin Controlled by PB26 */ +#define PIO_PB27 (1u << 27) /**< \brief Pin Controlled by PB27 */ +#define PIO_PB28 (1u << 28) /**< \brief Pin Controlled by PB28 */ +#define PIO_PB29 (1u << 29) /**< \brief Pin Controlled by PB29 */ +#define PIO_PB30 (1u << 30) /**< \brief Pin Controlled by PB30 */ +#define PIO_PB31 (1u << 31) /**< \brief Pin Controlled by PB31 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +/* ========== Pio definition for ADC peripheral ========== */ +#define PIO_PA2X1_AD0 (1u << 2) /**< \brief Adc signal: AD0 */ +#define PIO_PA3X1_AD1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */ +#define PIO_PA3X1_WKUP1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */ +#define PIO_PB17X1_AD10 (1u << 17) /**< \brief Adc signal: AD10 */ +#define PIO_PB18X1_AD11 (1u << 18) /**< \brief Adc signal: AD11 */ +#define PIO_PB19X1_AD12 (1u << 19) /**< \brief Adc signal: AD12 */ +#define PIO_PB20X1_AD13 (1u << 20) /**< \brief Adc signal: AD13 */ +#define PIO_PB21X1_AD14 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */ +#define PIO_PB21X1_WKUP13 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */ +#define PIO_PA4X1_AD2 (1u << 4) /**< \brief Adc signal: AD2 */ +#define PIO_PA6X1_AD3 (1u << 6) /**< \brief Adc signal: AD3 */ +#define PIO_PA22X1_AD4 (1u << 22) /**< \brief Adc signal: AD4 */ +#define PIO_PA23X1_AD5 (1u << 23) /**< \brief Adc signal: AD5 */ +#define PIO_PA24X1_AD6 (1u << 24) /**< \brief Adc signal: AD6 */ +#define PIO_PA16X1_AD7 (1u << 16) /**< \brief Adc signal: AD7 */ +#define PIO_PB12X1_AD8 (1u << 12) /**< \brief Adc signal: AD8 */ +#define PIO_PB13X1_AD9 (1u << 13) /**< \brief Adc signal: AD9 */ +#define PIO_PA11B_ADTRG (1u << 11) /**< \brief Adc signal: ADTRG */ +/* ========== Pio definition for CAN0 peripheral ========== */ +#define PIO_PA1A_CANRX0 (1u << 1) /**< \brief Can0 signal: CANRX0 */ +#define PIO_PA0A_CANTX0 (1u << 0) /**< \brief Can0 signal: CANTX0 */ +/* ========== Pio definition for CAN1 peripheral ========== */ +#define PIO_PB15A_CANRX1 (1u << 15) /**< \brief Can1 signal: CANRX1 */ +#define PIO_PB14A_CANTX1 (1u << 14) /**< \brief Can1 signal: CANTX1 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB15X1_DAC0 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */ +#define PIO_PB15X1_WKUP12 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */ +#define PIO_PB16X1_DAC1 (1u << 16) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA10B_DATRG (1u << 10) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC21A_A0 (1u << 21) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC21A_NBS0 (1u << 21) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC22A_A1 (1u << 22) /**< \brief Ebi signal: A1 */ +#define PIO_PD0A_A10 (1u << 0) /**< \brief Ebi signal: A10 */ +#define PIO_PD22A_A10 (1u << 22) /**< \brief Ebi signal: A10 */ +#define PIO_PD1A_A11 (1u << 1) /**< \brief Ebi signal: A11 */ +#define PIO_PD23A_A11 (1u << 23) /**< \brief Ebi signal: A11 */ +#define PIO_PD2A_A12 (1u << 2) /**< \brief Ebi signal: A12 */ +#define PIO_PD24A_A12 (1u << 24) /**< \brief Ebi signal: A12 */ +#define PIO_PD3A_A13 (1u << 3) /**< \brief Ebi signal: A13 */ +#define PIO_PD25A_A13 (1u << 25) /**< \brief Ebi signal: A13 */ +#define PIO_PD4A_A14 (1u << 4) /**< \brief Ebi signal: A14 */ +#define PIO_PD26A_A14 (1u << 26) /**< \brief Ebi signal: A14 */ +#define PIO_PD5A_A15 (1u << 5) /**< \brief Ebi signal: A15 */ +#define PIO_PD27A_A15 (1u << 27) /**< \brief Ebi signal: A15 */ +#define PIO_PD6A_A16 (1u << 6) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PD6A_BA0 (1u << 6) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PD28A_A16 (1u << 28) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PD28A_BA0 (1u << 28) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PD7A_A17 (1u << 7) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PD7A_BA1 (1u << 7) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PD29A_A17 (1u << 29) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PD29A_BA1 (1u << 29) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA25B_A18 (1u << 25) /**< \brief Ebi signal: A18 */ +#define PIO_PB10B_A18 (1u << 10) /**< \brief Ebi signal: A18 */ +#define PIO_PD30A_A18 (1u << 30) /**< \brief Ebi signal: A18 */ +#define PIO_PA26B_A19 (1u << 26) /**< \brief Ebi signal: A19 */ +#define PIO_PB11B_A19 (1u << 11) /**< \brief Ebi signal: A19 */ +#define PIO_PE0A_A19 (1u << 0) /**< \brief Ebi signal: A19 */ +#define PIO_PC23A_A2 (1u << 23) /**< \brief Ebi signal: A2 */ +#define PIO_PA18B_A20 (1u << 18) /**< \brief Ebi signal: A20 */ +#define PIO_PA27B_A20 (1u << 27) /**< \brief Ebi signal: A20 */ +#define PIO_PE1A_A20 (1u << 1) /**< \brief Ebi signal: A20 */ +#define PIO_PD8A_A21 (1u << 8) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PD8A_NANDALE (1u << 8) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PE2A_A21 (1u << 2) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PE2A_NANDALE (1u << 2) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PD9A_A22 (1u << 9) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PD9A_NANDCLE (1u << 9) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PE3A_A22 (1u << 3) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PE3A_NANDCLE (1u << 3) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PE4A_A23 (1u << 4) /**< \brief Ebi signal: A23 */ +#define PIO_PC24A_A3 (1u << 24) /**< \brief Ebi signal: A3 */ +#define PIO_PC25A_A4 (1u << 25) /**< \brief Ebi signal: A4 */ +#define PIO_PC26A_A5 (1u << 26) /**< \brief Ebi signal: A5 */ +#define PIO_PD17A_A5 (1u << 17) /**< \brief Ebi signal: A5 */ +#define PIO_PC27A_A6 (1u << 27) /**< \brief Ebi signal: A6 */ +#define PIO_PD18A_A6 (1u << 18) /**< \brief Ebi signal: A6 */ +#define PIO_PC28A_A7 (1u << 28) /**< \brief Ebi signal: A7 */ +#define PIO_PD19A_A7 (1u << 19) /**< \brief Ebi signal: A7 */ +#define PIO_PC29A_A8 (1u << 29) /**< \brief Ebi signal: A8 */ +#define PIO_PD20A_A8 (1u << 20) /**< \brief Ebi signal: A8 */ +#define PIO_PC30A_A9 (1u << 30) /**< \brief Ebi signal: A9 */ +#define PIO_PD21A_A9 (1u << 21) /**< \brief Ebi signal: A9 */ +#define PIO_PD16A_CAS (1u << 16) /**< \brief Ebi signal: CAS */ +#define PIO_PC2A_D0 (1u << 2) /**< \brief Ebi signal: D0 */ +#define PIO_PC3A_D1 (1u << 3) /**< \brief Ebi signal: D1 */ +#define PIO_PC12A_D10 (1u << 12) /**< \brief Ebi signal: D10 */ +#define PIO_PC13A_D11 (1u << 13) /**< \brief Ebi signal: D11 */ +#define PIO_PC14A_D12 (1u << 14) /**< \brief Ebi signal: D12 */ +#define PIO_PC15A_D13 (1u << 15) /**< \brief Ebi signal: D13 */ +#define PIO_PC16A_D14 (1u << 16) /**< \brief Ebi signal: D14 */ +#define PIO_PC17A_D15 (1u << 17) /**< \brief Ebi signal: D15 */ +#define PIO_PC4A_D2 (1u << 4) /**< \brief Ebi signal: D2 */ +#define PIO_PC5A_D3 (1u << 5) /**< \brief Ebi signal: D3 */ +#define PIO_PC6A_D4 (1u << 6) /**< \brief Ebi signal: D4 */ +#define PIO_PC7A_D5 (1u << 7) /**< \brief Ebi signal: D5 */ +#define PIO_PC8A_D6 (1u << 8) /**< \brief Ebi signal: D6 */ +#define PIO_PC9A_D7 (1u << 9) /**< \brief Ebi signal: D7 */ +#define PIO_PC10A_D8 (1u << 10) /**< \brief Ebi signal: D8 */ +#define PIO_PC11A_D9 (1u << 11) /**< \brief Ebi signal: D9 */ +#define PIO_PC19A_NANDOE (1u << 19) /**< \brief Ebi signal: NANDOE */ +#define PIO_PA2B_NANDRDY (1u << 2) /**< \brief Ebi signal: NANDRDY */ +#define PIO_PC20A_NANDWE (1u << 20) /**< \brief Ebi signal: NANDWE */ +#define PIO_PA6B_NCS0 (1u << 6) /**< \brief Ebi signal: NCS0 */ +#define PIO_PA7B_NCS1 (1u << 7) /**< \brief Ebi signal: NCS1 */ +#define PIO_PB24B_NCS2 (1u << 24) /**< \brief Ebi signal: NCS2 */ +#define PIO_PB27A_NCS3 (1u << 27) /**< \brief Ebi signal: NCS3 */ +#define PIO_PE5A_NCS4 (1u << 5) /**< \brief Ebi signal: NCS4 */ +#define PIO_PE6A_NCS5 (1u << 6) /**< \brief Ebi signal: NCS5 */ +#define PIO_PE18B_NCS6 (1u << 18) /**< \brief Ebi signal: NCS6 */ +#define PIO_PE27A_NCS7 (1u << 27) /**< \brief Ebi signal: NCS7 */ +#define PIO_PA29B_NRD (1u << 29) /**< \brief Ebi signal: NRD */ +#define PIO_PA4B_NWAIT (1u << 4) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC18A_NWR0 (1u << 18) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC18A_NWE (1u << 18) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD10A_NWR1 (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD10A_NBS1 (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15A_RAS (1u << 15) /**< \brief Ebi signal: RAS */ +#define PIO_PD11A_SDA10 (1u << 11) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13A_SDCKE (1u << 13) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD12A_SDCS (1u << 12) /**< \brief Ebi signal: SDCS */ +#define PIO_PD14A_SDWE (1u << 14) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for EMAC peripheral ========== */ +#define PIO_PC13B_ECOL (1u << 13) /**< \brief Emac signal: ECOL */ +#define PIO_PC10B_ECRS (1u << 10) /**< \brief Emac signal: ECRS */ +#define PIO_PB4A_ECRSDV (1u << 4) /**< \brief Emac signal: ECRSDV/ERXDV */ +#define PIO_PB4A_ERXDV (1u << 4) /**< \brief Emac signal: ECRSDV/ERXDV */ +#define PIO_PB8A_EMDC (1u << 8) /**< \brief Emac signal: EMDC */ +#define PIO_PB9A_EMDIO (1u << 9) /**< \brief Emac signal: EMDIO */ +#define PIO_PB5A_ERX0 (1u << 5) /**< \brief Emac signal: ERX0 */ +#define PIO_PB6A_ERX1 (1u << 6) /**< \brief Emac signal: ERX1 */ +#define PIO_PC11B_ERX2 (1u << 11) /**< \brief Emac signal: ERX2 */ +#define PIO_PC12B_ERX3 (1u << 12) /**< \brief Emac signal: ERX3 */ +#define PIO_PC14B_ERXCK (1u << 14) /**< \brief Emac signal: ERXCK */ +#define PIO_PB7A_ERXER (1u << 7) /**< \brief Emac signal: ERXER */ +#define PIO_PB2A_ETX0 (1u << 2) /**< \brief Emac signal: ETX0 */ +#define PIO_PB3A_ETX1 (1u << 3) /**< \brief Emac signal: ETX1 */ +#define PIO_PC15B_ETX2 (1u << 15) /**< \brief Emac signal: ETX2 */ +#define PIO_PC16B_ETX3 (1u << 16) /**< \brief Emac signal: ETX3 */ +#define PIO_PB0A_ETXCK (1u << 0) /**< \brief Emac signal: ETXCK */ +#define PIO_PB1A_ETXEN (1u << 1) /**< \brief Emac signal: ETXEN */ +#define PIO_PC17B_ETXER (1u << 17) /**< \brief Emac signal: ETXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA20A_MCCDA (1u << 20) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PE20B_MCCDB (1u << 20) /**< \brief Hsmci signal: MCCDB */ +#define PIO_PA19A_MCCK (1u << 19) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA21A_MCDA0 (1u << 21) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA22A_MCDA1 (1u << 22) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA23A_MCDA2 (1u << 23) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA24A_MCDA3 (1u << 24) /**< \brief Hsmci signal: MCDA3 */ +#define PIO_PD0B_MCDA4 (1u << 0) /**< \brief Hsmci signal: MCDA4 */ +#define PIO_PD1B_MCDA5 (1u << 1) /**< \brief Hsmci signal: MCDA5 */ +#define PIO_PD2B_MCDA6 (1u << 2) /**< \brief Hsmci signal: MCDA6 */ +#define PIO_PD3B_MCDA7 (1u << 3) /**< \brief Hsmci signal: MCDA7 */ +#define PIO_PE22B_MCDB0 (1u << 22) /**< \brief Hsmci signal: MCDB0 */ +#define PIO_PE24B_MCDB1 (1u << 24) /**< \brief Hsmci signal: MCDB1 */ +#define PIO_PE26B_MCDB2 (1u << 26) /**< \brief Hsmci signal: MCDB2 */ +#define PIO_PE27B_MCDB3 (1u << 27) /**< \brief Hsmci signal: MCDB3 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA1B_PCK0 (1u << 1) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB22B_PCK0 (1u << 22) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA24B_PCK1 (1u << 24) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA30B_PCK1 (1u << 30) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA28B_PCK2 (1u << 28) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM peripheral ========== */ +#define PIO_PA5B_PWMFI0 (1u << 5) /**< \brief Pwm signal: PWMFI0 */ +#define PIO_PA3B_PWMFI1 (1u << 3) /**< \brief Pwm signal: PWMFI1 */ +#define PIO_PD6B_PWMFI2 (1u << 6) /**< \brief Pwm signal: PWMFI2 */ +#define PIO_PA8B_PWMH0 (1u << 8) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PB12B_PWMH0 (1u << 12) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PC3B_PWMH0 (1u << 3) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PE15A_PWMH0 (1u << 15) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PB13B_PWMH1 (1u << 13) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PC5B_PWMH1 (1u << 5) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PE16A_PWMH1 (1u << 16) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PB14B_PWMH2 (1u << 14) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PC7B_PWMH2 (1u << 7) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PB15B_PWMH3 (1u << 15) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PC9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PF3A_PWMH3 (1u << 3) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PC20B_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */ +#define PIO_PE20A_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */ +#define PIO_PC19B_PWMH5 (1u << 19) /**< \brief Pwm signal: PWMH5 */ +#define PIO_PE22A_PWMH5 (1u << 22) /**< \brief Pwm signal: PWMH5 */ +#define PIO_PC18B_PWMH6 (1u << 18) /**< \brief Pwm signal: PWMH6 */ +#define PIO_PE24A_PWMH6 (1u << 24) /**< \brief Pwm signal: PWMH6 */ +#define PIO_PE26A_PWMH7 (1u << 26) /**< \brief Pwm signal: PWMH7 */ +#define PIO_PA21B_PWML0 (1u << 21) /**< \brief Pwm signal: PWML0 */ +#define PIO_PB16B_PWML0 (1u << 16) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC2B_PWML0 (1u << 2) /**< \brief Pwm signal: PWML0 */ +#define PIO_PE18A_PWML0 (1u << 18) /**< \brief Pwm signal: PWML0 */ +#define PIO_PA12B_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */ +#define PIO_PB17B_PWML1 (1u << 17) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC4B_PWML1 (1u << 4) /**< \brief Pwm signal: PWML1 */ +#define PIO_PA20B_PWML2 (1u << 20) /**< \brief Pwm signal: PWML2 */ +#define PIO_PB18B_PWML2 (1u << 18) /**< \brief Pwm signal: PWML2 */ +#define PIO_PC6B_PWML2 (1u << 6) /**< \brief Pwm signal: PWML2 */ +#define PIO_PE17A_PWML2 (1u << 17) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA0B_PWML3 (1u << 0) /**< \brief Pwm signal: PWML3 */ +#define PIO_PB19B_PWML3 (1u << 19) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC8B_PWML3 (1u << 8) /**< \brief Pwm signal: PWML3 */ +#define PIO_PB6B_PWML4 (1u << 6) /**< \brief Pwm signal: PWML4 */ +#define PIO_PC21B_PWML4 (1u << 21) /**< \brief Pwm signal: PWML4 */ +#define PIO_PE19A_PWML4 (1u << 19) /**< \brief Pwm signal: PWML4 */ +#define PIO_PB7B_PWML5 (1u << 7) /**< \brief Pwm signal: PWML5 */ +#define PIO_PC22B_PWML5 (1u << 22) /**< \brief Pwm signal: PWML5 */ +#define PIO_PE21A_PWML5 (1u << 21) /**< \brief Pwm signal: PWML5 */ +#define PIO_PB8B_PWML6 (1u << 8) /**< \brief Pwm signal: PWML6 */ +#define PIO_PC23B_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */ +#define PIO_PE23A_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */ +#define PIO_PB9B_PWML7 (1u << 9) /**< \brief Pwm signal: PWML7 */ +#define PIO_PC24B_PWML7 (1u << 24) /**< \brief Pwm signal: PWML7 */ +#define PIO_PE25A_PWML7 (1u << 25) /**< \brief Pwm signal: PWML7 */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PA25A_SPI0_MISO (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PA26A_SPI0_MOSI (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PA27A_SPI0_SPCK (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PB18A_RD (1u << 18) /**< \brief Ssc signal: RD */ +#define PIO_PB17A_RF (1u << 17) /**< \brief Ssc signal: RF */ +#define PIO_PB19A_RK (1u << 19) /**< \brief Ssc signal: RK */ +#define PIO_PA16B_TD (1u << 16) /**< \brief Ssc signal: TD */ +#define PIO_PA15B_TF (1u << 15) /**< \brief Ssc signal: TF */ +#define PIO_PA14B_TK (1u << 14) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PB26B_TCLK0 (1u << 26) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA4A_TCLK1 (1u << 4) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA7A_TCLK2 (1u << 7) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PB25B_TIOA0 (1u << 25) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA2A_TIOA1 (1u << 2) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA5A_TIOA2 (1u << 5) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PB27B_TIOB0 (1u << 27) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA3A_TIOB1 (1u << 3) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA6A_TIOB2 (1u << 6) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PA22B_TCLK3 (1u << 22) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PA23B_TCLK4 (1u << 23) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PB16A_TCLK5 (1u << 16) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PB0B_TIOA3 (1u << 0) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PE9A_TIOA3 (1u << 9) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PB2B_TIOA4 (1u << 2) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PE11A_TIOA4 (1u << 11) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PB4B_TIOA5 (1u << 4) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PE13A_TIOA5 (1u << 13) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PB1B_TIOB3 (1u << 1) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PE10A_TIOB3 (1u << 10) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PB3B_TIOB4 (1u << 3) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PE12A_TIOB4 (1u << 12) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PB5B_TIOB5 (1u << 5) /**< \brief Tc1 signal: TIOB5 */ +#define PIO_PE14A_TIOB5 (1u << 14) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC27B_TCLK6 (1u << 27) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC30B_TCLK7 (1u << 30) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PD9B_TCLK8 (1u << 9) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC25B_TIOA6 (1u << 25) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC28B_TIOA7 (1u << 28) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PD7B_TIOA8 (1u << 7) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC26B_TIOB6 (1u << 26) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC29B_TIOB7 (1u << 29) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PD8B_TIOB8 (1u << 8) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TWI0 peripheral ========== */ +#define PIO_PA18A_TWCK0 (1u << 18) /**< \brief Twi0 signal: TWCK0 */ +#define PIO_PA17A_TWD0 (1u << 17) /**< \brief Twi0 signal: TWD0 */ +/* ========== Pio definition for TWI1 peripheral ========== */ +#define PIO_PB13A_TWCK1 (1u << 13) /**< \brief Twi1 signal: TWCK1 */ +#define PIO_PB12A_TWD1 (1u << 12) /**< \brief Twi1 signal: TWD1 */ +/* ========== Pio definition for UART peripheral ========== */ +#define PIO_PA8A_URXD (1u << 8) /**< \brief Uart signal: URXD */ +#define PIO_PA9A_UTXD (1u << 9) /**< \brief Uart signal: UTXD */ +/* ========== Pio definition for UOTGHS peripheral ========== */ +#define PIO_PB11A_UOTGID (1u << 11) /**< \brief Uotghs signal: UOTGID */ +#define PIO_PB10A_UOTGVBOF (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB26A_CTS0 (1u << 26) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PB25A_RTS0 (1u << 25) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PA10A_RXD0 (1u << 10) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PA17B_SCK0 (1u << 17) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PA11A_TXD0 (1u << 11) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA15A_CTS1 (1u << 15) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA14A_RTS1 (1u << 14) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA12A_RXD1 (1u << 12) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA16A_SCK1 (1u << 16) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PA13A_TXD1 (1u << 13) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PB23A_CTS2 (1u << 23) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PB22A_RTS2 (1u << 22) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PB21A_RXD2 (1u << 21) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PB24A_SCK2 (1u << 24) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PB20A_TXD2 (1u << 20) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio definition for USART3 peripheral ========== */ +#define PIO_PF4A_CTS3 (1u << 4) /**< \brief Usart3 signal: CTS3 */ +#define PIO_PF5A_RTS3 (1u << 5) /**< \brief Usart3 signal: RTS3 */ +#define PIO_PD5B_RXD3 (1u << 5) /**< \brief Usart3 signal: RXD3 */ +#define PIO_PE16B_SCK3 (1u << 16) /**< \brief Usart3 signal: SCK3 */ +#define PIO_PD4B_TXD3 (1u << 4) /**< \brief Usart3 signal: TXD3 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB10_IDX 42 +#define PIO_PB11_IDX 43 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PB14_IDX 46 +#define PIO_PB15_IDX 47 +#define PIO_PB16_IDX 48 +#define PIO_PB17_IDX 49 +#define PIO_PB18_IDX 50 +#define PIO_PB19_IDX 51 +#define PIO_PB20_IDX 52 +#define PIO_PB21_IDX 53 +#define PIO_PB22_IDX 54 +#define PIO_PB23_IDX 55 +#define PIO_PB24_IDX 56 +#define PIO_PB25_IDX 57 +#define PIO_PB26_IDX 58 +#define PIO_PB27_IDX 59 +#define PIO_PB28_IDX 60 +#define PIO_PB29_IDX 61 +#define PIO_PB30_IDX 62 +#define PIO_PB31_IDX 63 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 + +#endif /* _SAM3X8E_PIO_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8h.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8h.h new file mode 100644 index 0000000..8e9b72b --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/pio/pio_sam3x8h.h @@ -0,0 +1,695 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3X8H_PIO_ +#define _SAM3X8H_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ +#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ +#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */ +#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */ +#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */ +#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */ +#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */ +#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */ +#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */ +#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */ +#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */ +#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */ +#define PIO_PB25 (1u << 25) /**< \brief Pin Controlled by PB25 */ +#define PIO_PB26 (1u << 26) /**< \brief Pin Controlled by PB26 */ +#define PIO_PB27 (1u << 27) /**< \brief Pin Controlled by PB27 */ +#define PIO_PB28 (1u << 28) /**< \brief Pin Controlled by PB28 */ +#define PIO_PB29 (1u << 29) /**< \brief Pin Controlled by PB29 */ +#define PIO_PB30 (1u << 30) /**< \brief Pin Controlled by PB30 */ +#define PIO_PB31 (1u << 31) /**< \brief Pin Controlled by PB31 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +#define PIO_PE6 (1u << 6) /**< \brief Pin Controlled by PE6 */ +#define PIO_PE7 (1u << 7) /**< \brief Pin Controlled by PE7 */ +#define PIO_PE8 (1u << 8) /**< \brief Pin Controlled by PE8 */ +#define PIO_PE9 (1u << 9) /**< \brief Pin Controlled by PE9 */ +#define PIO_PE10 (1u << 10) /**< \brief Pin Controlled by PE10 */ +#define PIO_PE11 (1u << 11) /**< \brief Pin Controlled by PE11 */ +#define PIO_PE12 (1u << 12) /**< \brief Pin Controlled by PE12 */ +#define PIO_PE13 (1u << 13) /**< \brief Pin Controlled by PE13 */ +#define PIO_PE14 (1u << 14) /**< \brief Pin Controlled by PE14 */ +#define PIO_PE15 (1u << 15) /**< \brief Pin Controlled by PE15 */ +#define PIO_PE16 (1u << 16) /**< \brief Pin Controlled by PE16 */ +#define PIO_PE17 (1u << 17) /**< \brief Pin Controlled by PE17 */ +#define PIO_PE18 (1u << 18) /**< \brief Pin Controlled by PE18 */ +#define PIO_PE19 (1u << 19) /**< \brief Pin Controlled by PE19 */ +#define PIO_PE20 (1u << 20) /**< \brief Pin Controlled by PE20 */ +#define PIO_PE21 (1u << 21) /**< \brief Pin Controlled by PE21 */ +#define PIO_PE22 (1u << 22) /**< \brief Pin Controlled by PE22 */ +#define PIO_PE23 (1u << 23) /**< \brief Pin Controlled by PE23 */ +#define PIO_PE24 (1u << 24) /**< \brief Pin Controlled by PE24 */ +#define PIO_PE25 (1u << 25) /**< \brief Pin Controlled by PE25 */ +#define PIO_PE26 (1u << 26) /**< \brief Pin Controlled by PE26 */ +#define PIO_PE27 (1u << 27) /**< \brief Pin Controlled by PE27 */ +#define PIO_PE28 (1u << 28) /**< \brief Pin Controlled by PE28 */ +#define PIO_PE29 (1u << 29) /**< \brief Pin Controlled by PE29 */ +#define PIO_PE30 (1u << 30) /**< \brief Pin Controlled by PE30 */ +#define PIO_PE31 (1u << 31) /**< \brief Pin Controlled by PE31 */ +#define PIO_PF0 (1u << 0) /**< \brief Pin Controlled by PF0 */ +#define PIO_PF1 (1u << 1) /**< \brief Pin Controlled by PF1 */ +#define PIO_PF2 (1u << 2) /**< \brief Pin Controlled by PF2 */ +#define PIO_PF3 (1u << 3) /**< \brief Pin Controlled by PF3 */ +#define PIO_PF4 (1u << 4) /**< \brief Pin Controlled by PF4 */ +#define PIO_PF5 (1u << 5) /**< \brief Pin Controlled by PF5 */ +/* ========== Pio definition for ADC peripheral ========== */ +#define PIO_PA2X1_AD0 (1u << 2) /**< \brief Adc signal: AD0 */ +#define PIO_PA3X1_AD1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */ +#define PIO_PA3X1_WKUP1 (1u << 3) /**< \brief Adc signal: AD1/WKUP1 */ +#define PIO_PB17X1_AD10 (1u << 17) /**< \brief Adc signal: AD10 */ +#define PIO_PB18X1_AD11 (1u << 18) /**< \brief Adc signal: AD11 */ +#define PIO_PB19X1_AD12 (1u << 19) /**< \brief Adc signal: AD12 */ +#define PIO_PB20X1_AD13 (1u << 20) /**< \brief Adc signal: AD13 */ +#define PIO_PB21X1_AD14 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */ +#define PIO_PB21X1_WKUP13 (1u << 21) /**< \brief Adc signal: AD14/WKUP13 */ +#define PIO_PA4X1_AD2 (1u << 4) /**< \brief Adc signal: AD2 */ +#define PIO_PA6X1_AD3 (1u << 6) /**< \brief Adc signal: AD3 */ +#define PIO_PA22X1_AD4 (1u << 22) /**< \brief Adc signal: AD4 */ +#define PIO_PA23X1_AD5 (1u << 23) /**< \brief Adc signal: AD5 */ +#define PIO_PA24X1_AD6 (1u << 24) /**< \brief Adc signal: AD6 */ +#define PIO_PA16X1_AD7 (1u << 16) /**< \brief Adc signal: AD7 */ +#define PIO_PB12X1_AD8 (1u << 12) /**< \brief Adc signal: AD8 */ +#define PIO_PB13X1_AD9 (1u << 13) /**< \brief Adc signal: AD9 */ +#define PIO_PA11B_ADTRG (1u << 11) /**< \brief Adc signal: ADTRG */ +/* ========== Pio definition for CAN0 peripheral ========== */ +#define PIO_PA1A_CANRX0 (1u << 1) /**< \brief Can0 signal: CANRX0 */ +#define PIO_PA0A_CANTX0 (1u << 0) /**< \brief Can0 signal: CANTX0 */ +/* ========== Pio definition for CAN1 peripheral ========== */ +#define PIO_PB15A_CANRX1 (1u << 15) /**< \brief Can1 signal: CANRX1 */ +#define PIO_PB14A_CANTX1 (1u << 14) /**< \brief Can1 signal: CANTX1 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB15X1_DAC0 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */ +#define PIO_PB15X1_WKUP12 (1u << 15) /**< \brief Dacc signal: DAC0/WKUP12 */ +#define PIO_PB16X1_DAC1 (1u << 16) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA10B_DATRG (1u << 10) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC21A_A0 (1u << 21) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC21A_NBS0 (1u << 21) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC22A_A1 (1u << 22) /**< \brief Ebi signal: A1 */ +#define PIO_PD0A_A10 (1u << 0) /**< \brief Ebi signal: A10 */ +#define PIO_PD22A_A10 (1u << 22) /**< \brief Ebi signal: A10 */ +#define PIO_PD1A_A11 (1u << 1) /**< \brief Ebi signal: A11 */ +#define PIO_PD23A_A11 (1u << 23) /**< \brief Ebi signal: A11 */ +#define PIO_PD2A_A12 (1u << 2) /**< \brief Ebi signal: A12 */ +#define PIO_PD24A_A12 (1u << 24) /**< \brief Ebi signal: A12 */ +#define PIO_PD3A_A13 (1u << 3) /**< \brief Ebi signal: A13 */ +#define PIO_PD25A_A13 (1u << 25) /**< \brief Ebi signal: A13 */ +#define PIO_PD4A_A14 (1u << 4) /**< \brief Ebi signal: A14 */ +#define PIO_PD26A_A14 (1u << 26) /**< \brief Ebi signal: A14 */ +#define PIO_PD5A_A15 (1u << 5) /**< \brief Ebi signal: A15 */ +#define PIO_PD27A_A15 (1u << 27) /**< \brief Ebi signal: A15 */ +#define PIO_PD6A_A16 (1u << 6) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PD6A_BA0 (1u << 6) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PD28A_A16 (1u << 28) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PD28A_BA0 (1u << 28) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PD7A_A17 (1u << 7) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PD7A_BA1 (1u << 7) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PD29A_A17 (1u << 29) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PD29A_BA1 (1u << 29) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA25B_A18 (1u << 25) /**< \brief Ebi signal: A18 */ +#define PIO_PB10B_A18 (1u << 10) /**< \brief Ebi signal: A18 */ +#define PIO_PD30A_A18 (1u << 30) /**< \brief Ebi signal: A18 */ +#define PIO_PA26B_A19 (1u << 26) /**< \brief Ebi signal: A19 */ +#define PIO_PB11B_A19 (1u << 11) /**< \brief Ebi signal: A19 */ +#define PIO_PE0A_A19 (1u << 0) /**< \brief Ebi signal: A19 */ +#define PIO_PC23A_A2 (1u << 23) /**< \brief Ebi signal: A2 */ +#define PIO_PA18B_A20 (1u << 18) /**< \brief Ebi signal: A20 */ +#define PIO_PA27B_A20 (1u << 27) /**< \brief Ebi signal: A20 */ +#define PIO_PE1A_A20 (1u << 1) /**< \brief Ebi signal: A20 */ +#define PIO_PD8A_A21 (1u << 8) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PD8A_NANDALE (1u << 8) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PE2A_A21 (1u << 2) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PE2A_NANDALE (1u << 2) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PD9A_A22 (1u << 9) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PD9A_NANDCLE (1u << 9) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PE3A_A22 (1u << 3) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PE3A_NANDCLE (1u << 3) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PE4A_A23 (1u << 4) /**< \brief Ebi signal: A23 */ +#define PIO_PC24A_A3 (1u << 24) /**< \brief Ebi signal: A3 */ +#define PIO_PC25A_A4 (1u << 25) /**< \brief Ebi signal: A4 */ +#define PIO_PC26A_A5 (1u << 26) /**< \brief Ebi signal: A5 */ +#define PIO_PD17A_A5 (1u << 17) /**< \brief Ebi signal: A5 */ +#define PIO_PC27A_A6 (1u << 27) /**< \brief Ebi signal: A6 */ +#define PIO_PD18A_A6 (1u << 18) /**< \brief Ebi signal: A6 */ +#define PIO_PC28A_A7 (1u << 28) /**< \brief Ebi signal: A7 */ +#define PIO_PD19A_A7 (1u << 19) /**< \brief Ebi signal: A7 */ +#define PIO_PC29A_A8 (1u << 29) /**< \brief Ebi signal: A8 */ +#define PIO_PD20A_A8 (1u << 20) /**< \brief Ebi signal: A8 */ +#define PIO_PC30A_A9 (1u << 30) /**< \brief Ebi signal: A9 */ +#define PIO_PD21A_A9 (1u << 21) /**< \brief Ebi signal: A9 */ +#define PIO_PD16A_CAS (1u << 16) /**< \brief Ebi signal: CAS */ +#define PIO_PC2A_D0 (1u << 2) /**< \brief Ebi signal: D0 */ +#define PIO_PC3A_D1 (1u << 3) /**< \brief Ebi signal: D1 */ +#define PIO_PC12A_D10 (1u << 12) /**< \brief Ebi signal: D10 */ +#define PIO_PC13A_D11 (1u << 13) /**< \brief Ebi signal: D11 */ +#define PIO_PC14A_D12 (1u << 14) /**< \brief Ebi signal: D12 */ +#define PIO_PC15A_D13 (1u << 15) /**< \brief Ebi signal: D13 */ +#define PIO_PC16A_D14 (1u << 16) /**< \brief Ebi signal: D14 */ +#define PIO_PC17A_D15 (1u << 17) /**< \brief Ebi signal: D15 */ +#define PIO_PC4A_D2 (1u << 4) /**< \brief Ebi signal: D2 */ +#define PIO_PC5A_D3 (1u << 5) /**< \brief Ebi signal: D3 */ +#define PIO_PC6A_D4 (1u << 6) /**< \brief Ebi signal: D4 */ +#define PIO_PC7A_D5 (1u << 7) /**< \brief Ebi signal: D5 */ +#define PIO_PC8A_D6 (1u << 8) /**< \brief Ebi signal: D6 */ +#define PIO_PC9A_D7 (1u << 9) /**< \brief Ebi signal: D7 */ +#define PIO_PC10A_D8 (1u << 10) /**< \brief Ebi signal: D8 */ +#define PIO_PC11A_D9 (1u << 11) /**< \brief Ebi signal: D9 */ +#define PIO_PC19A_NANDOE (1u << 19) /**< \brief Ebi signal: NANDOE */ +#define PIO_PA2B_NANDRDY (1u << 2) /**< \brief Ebi signal: NANDRDY */ +#define PIO_PC20A_NANDWE (1u << 20) /**< \brief Ebi signal: NANDWE */ +#define PIO_PA6B_NCS0 (1u << 6) /**< \brief Ebi signal: NCS0 */ +#define PIO_PA7B_NCS1 (1u << 7) /**< \brief Ebi signal: NCS1 */ +#define PIO_PB24B_NCS2 (1u << 24) /**< \brief Ebi signal: NCS2 */ +#define PIO_PB27A_NCS3 (1u << 27) /**< \brief Ebi signal: NCS3 */ +#define PIO_PE5A_NCS4 (1u << 5) /**< \brief Ebi signal: NCS4 */ +#define PIO_PE6A_NCS5 (1u << 6) /**< \brief Ebi signal: NCS5 */ +#define PIO_PE18B_NCS6 (1u << 18) /**< \brief Ebi signal: NCS6 */ +#define PIO_PE27A_NCS7 (1u << 27) /**< \brief Ebi signal: NCS7 */ +#define PIO_PA29B_NRD (1u << 29) /**< \brief Ebi signal: NRD */ +#define PIO_PA4B_NWAIT (1u << 4) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC18A_NWR0 (1u << 18) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC18A_NWE (1u << 18) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD10A_NWR1 (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD10A_NBS1 (1u << 10) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15A_RAS (1u << 15) /**< \brief Ebi signal: RAS */ +#define PIO_PD11A_SDA10 (1u << 11) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13A_SDCKE (1u << 13) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD12A_SDCS (1u << 12) /**< \brief Ebi signal: SDCS */ +#define PIO_PD14A_SDWE (1u << 14) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for EMAC peripheral ========== */ +#define PIO_PC13B_ECOL (1u << 13) /**< \brief Emac signal: ECOL */ +#define PIO_PC10B_ECRS (1u << 10) /**< \brief Emac signal: ECRS */ +#define PIO_PB4A_ECRSDV (1u << 4) /**< \brief Emac signal: ECRSDV/ERXDV */ +#define PIO_PB4A_ERXDV (1u << 4) /**< \brief Emac signal: ECRSDV/ERXDV */ +#define PIO_PB8A_EMDC (1u << 8) /**< \brief Emac signal: EMDC */ +#define PIO_PB9A_EMDIO (1u << 9) /**< \brief Emac signal: EMDIO */ +#define PIO_PB5A_ERX0 (1u << 5) /**< \brief Emac signal: ERX0 */ +#define PIO_PB6A_ERX1 (1u << 6) /**< \brief Emac signal: ERX1 */ +#define PIO_PC11B_ERX2 (1u << 11) /**< \brief Emac signal: ERX2 */ +#define PIO_PC12B_ERX3 (1u << 12) /**< \brief Emac signal: ERX3 */ +#define PIO_PC14B_ERXCK (1u << 14) /**< \brief Emac signal: ERXCK */ +#define PIO_PB7A_ERXER (1u << 7) /**< \brief Emac signal: ERXER */ +#define PIO_PB2A_ETX0 (1u << 2) /**< \brief Emac signal: ETX0 */ +#define PIO_PB3A_ETX1 (1u << 3) /**< \brief Emac signal: ETX1 */ +#define PIO_PC15B_ETX2 (1u << 15) /**< \brief Emac signal: ETX2 */ +#define PIO_PC16B_ETX3 (1u << 16) /**< \brief Emac signal: ETX3 */ +#define PIO_PB0A_ETXCK (1u << 0) /**< \brief Emac signal: ETXCK */ +#define PIO_PB1A_ETXEN (1u << 1) /**< \brief Emac signal: ETXEN */ +#define PIO_PC17B_ETXER (1u << 17) /**< \brief Emac signal: ETXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA20A_MCCDA (1u << 20) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PE20B_MCCDB (1u << 20) /**< \brief Hsmci signal: MCCDB */ +#define PIO_PA19A_MCCK (1u << 19) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA21A_MCDA0 (1u << 21) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA22A_MCDA1 (1u << 22) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA23A_MCDA2 (1u << 23) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA24A_MCDA3 (1u << 24) /**< \brief Hsmci signal: MCDA3 */ +#define PIO_PD0B_MCDA4 (1u << 0) /**< \brief Hsmci signal: MCDA4 */ +#define PIO_PD1B_MCDA5 (1u << 1) /**< \brief Hsmci signal: MCDA5 */ +#define PIO_PD2B_MCDA6 (1u << 2) /**< \brief Hsmci signal: MCDA6 */ +#define PIO_PD3B_MCDA7 (1u << 3) /**< \brief Hsmci signal: MCDA7 */ +#define PIO_PE22B_MCDB0 (1u << 22) /**< \brief Hsmci signal: MCDB0 */ +#define PIO_PE24B_MCDB1 (1u << 24) /**< \brief Hsmci signal: MCDB1 */ +#define PIO_PE26B_MCDB2 (1u << 26) /**< \brief Hsmci signal: MCDB2 */ +#define PIO_PE27B_MCDB3 (1u << 27) /**< \brief Hsmci signal: MCDB3 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA1B_PCK0 (1u << 1) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB22B_PCK0 (1u << 22) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA24B_PCK1 (1u << 24) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA30B_PCK1 (1u << 30) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA28B_PCK2 (1u << 28) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM peripheral ========== */ +#define PIO_PA5B_PWMFI0 (1u << 5) /**< \brief Pwm signal: PWMFI0 */ +#define PIO_PA3B_PWMFI1 (1u << 3) /**< \brief Pwm signal: PWMFI1 */ +#define PIO_PD6B_PWMFI2 (1u << 6) /**< \brief Pwm signal: PWMFI2 */ +#define PIO_PA8B_PWMH0 (1u << 8) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PB12B_PWMH0 (1u << 12) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PC3B_PWMH0 (1u << 3) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PE15A_PWMH0 (1u << 15) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PB13B_PWMH1 (1u << 13) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PC5B_PWMH1 (1u << 5) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PE16A_PWMH1 (1u << 16) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PB14B_PWMH2 (1u << 14) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PC7B_PWMH2 (1u << 7) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PB15B_PWMH3 (1u << 15) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PC9B_PWMH3 (1u << 9) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PF3A_PWMH3 (1u << 3) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PC20B_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */ +#define PIO_PE20A_PWMH4 (1u << 20) /**< \brief Pwm signal: PWMH4 */ +#define PIO_PC19B_PWMH5 (1u << 19) /**< \brief Pwm signal: PWMH5 */ +#define PIO_PE22A_PWMH5 (1u << 22) /**< \brief Pwm signal: PWMH5 */ +#define PIO_PC18B_PWMH6 (1u << 18) /**< \brief Pwm signal: PWMH6 */ +#define PIO_PE24A_PWMH6 (1u << 24) /**< \brief Pwm signal: PWMH6 */ +#define PIO_PE26A_PWMH7 (1u << 26) /**< \brief Pwm signal: PWMH7 */ +#define PIO_PA21B_PWML0 (1u << 21) /**< \brief Pwm signal: PWML0 */ +#define PIO_PB16B_PWML0 (1u << 16) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC2B_PWML0 (1u << 2) /**< \brief Pwm signal: PWML0 */ +#define PIO_PE18A_PWML0 (1u << 18) /**< \brief Pwm signal: PWML0 */ +#define PIO_PA12B_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */ +#define PIO_PB17B_PWML1 (1u << 17) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC4B_PWML1 (1u << 4) /**< \brief Pwm signal: PWML1 */ +#define PIO_PA20B_PWML2 (1u << 20) /**< \brief Pwm signal: PWML2 */ +#define PIO_PB18B_PWML2 (1u << 18) /**< \brief Pwm signal: PWML2 */ +#define PIO_PC6B_PWML2 (1u << 6) /**< \brief Pwm signal: PWML2 */ +#define PIO_PE17A_PWML2 (1u << 17) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA0B_PWML3 (1u << 0) /**< \brief Pwm signal: PWML3 */ +#define PIO_PB19B_PWML3 (1u << 19) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC8B_PWML3 (1u << 8) /**< \brief Pwm signal: PWML3 */ +#define PIO_PB6B_PWML4 (1u << 6) /**< \brief Pwm signal: PWML4 */ +#define PIO_PC21B_PWML4 (1u << 21) /**< \brief Pwm signal: PWML4 */ +#define PIO_PE19A_PWML4 (1u << 19) /**< \brief Pwm signal: PWML4 */ +#define PIO_PB7B_PWML5 (1u << 7) /**< \brief Pwm signal: PWML5 */ +#define PIO_PC22B_PWML5 (1u << 22) /**< \brief Pwm signal: PWML5 */ +#define PIO_PE21A_PWML5 (1u << 21) /**< \brief Pwm signal: PWML5 */ +#define PIO_PB8B_PWML6 (1u << 8) /**< \brief Pwm signal: PWML6 */ +#define PIO_PC23B_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */ +#define PIO_PE23A_PWML6 (1u << 23) /**< \brief Pwm signal: PWML6 */ +#define PIO_PB9B_PWML7 (1u << 9) /**< \brief Pwm signal: PWML7 */ +#define PIO_PC24B_PWML7 (1u << 24) /**< \brief Pwm signal: PWML7 */ +#define PIO_PE25A_PWML7 (1u << 25) /**< \brief Pwm signal: PWML7 */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PA25A_SPI0_MISO (1u << 25) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PA26A_SPI0_MOSI (1u << 26) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PA28A_SPI0_NPCS0 (1u << 28) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA29A_SPI0_NPCS1 (1u << 29) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PB20B_SPI0_NPCS1 (1u << 20) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PA30A_SPI0_NPCS2 (1u << 30) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PB21B_SPI0_NPCS2 (1u << 21) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PA31A_SPI0_NPCS3 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PB23B_SPI0_NPCS3 (1u << 23) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PA27A_SPI0_SPCK (1u << 27) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PE28A_SPI1_MISO (1u << 28) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PE29A_SPI1_MOSI (1u << 29) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PE31A_SPI1_NPCS0 (1u << 31) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PF0A_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PF1A_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PF2A_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PE30A_SPI1_SPCK (1u << 30) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PB18A_RD (1u << 18) /**< \brief Ssc signal: RD */ +#define PIO_PB17A_RF (1u << 17) /**< \brief Ssc signal: RF */ +#define PIO_PB19A_RK (1u << 19) /**< \brief Ssc signal: RK */ +#define PIO_PA16B_TD (1u << 16) /**< \brief Ssc signal: TD */ +#define PIO_PA15B_TF (1u << 15) /**< \brief Ssc signal: TF */ +#define PIO_PA14B_TK (1u << 14) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PB26B_TCLK0 (1u << 26) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA4A_TCLK1 (1u << 4) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA7A_TCLK2 (1u << 7) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PB25B_TIOA0 (1u << 25) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA2A_TIOA1 (1u << 2) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA5A_TIOA2 (1u << 5) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PB27B_TIOB0 (1u << 27) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA3A_TIOB1 (1u << 3) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA6A_TIOB2 (1u << 6) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PA22B_TCLK3 (1u << 22) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PA23B_TCLK4 (1u << 23) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PB16A_TCLK5 (1u << 16) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PB0B_TIOA3 (1u << 0) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PE9A_TIOA3 (1u << 9) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PB2B_TIOA4 (1u << 2) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PE11A_TIOA4 (1u << 11) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PB4B_TIOA5 (1u << 4) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PE13A_TIOA5 (1u << 13) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PB1B_TIOB3 (1u << 1) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PE10A_TIOB3 (1u << 10) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PB3B_TIOB4 (1u << 3) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PE12A_TIOB4 (1u << 12) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PB5B_TIOB5 (1u << 5) /**< \brief Tc1 signal: TIOB5 */ +#define PIO_PE14A_TIOB5 (1u << 14) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC27B_TCLK6 (1u << 27) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC30B_TCLK7 (1u << 30) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PD9B_TCLK8 (1u << 9) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC25B_TIOA6 (1u << 25) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC28B_TIOA7 (1u << 28) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PD7B_TIOA8 (1u << 7) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC26B_TIOB6 (1u << 26) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC29B_TIOB7 (1u << 29) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PD8B_TIOB8 (1u << 8) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TWI0 peripheral ========== */ +#define PIO_PA18A_TWCK0 (1u << 18) /**< \brief Twi0 signal: TWCK0 */ +#define PIO_PA17A_TWD0 (1u << 17) /**< \brief Twi0 signal: TWD0 */ +/* ========== Pio definition for TWI1 peripheral ========== */ +#define PIO_PB13A_TWCK1 (1u << 13) /**< \brief Twi1 signal: TWCK1 */ +#define PIO_PB12A_TWD1 (1u << 12) /**< \brief Twi1 signal: TWD1 */ +/* ========== Pio definition for UART peripheral ========== */ +#define PIO_PA8A_URXD (1u << 8) /**< \brief Uart signal: URXD */ +#define PIO_PA9A_UTXD (1u << 9) /**< \brief Uart signal: UTXD */ +/* ========== Pio definition for UOTGHS peripheral ========== */ +#define PIO_PB11A_UOTGID (1u << 11) /**< \brief Uotghs signal: UOTGID */ +#define PIO_PB10A_UOTGVBOF (1u << 10) /**< \brief Uotghs signal: UOTGVBOF */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB26A_CTS0 (1u << 26) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PB25A_RTS0 (1u << 25) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PA10A_RXD0 (1u << 10) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PA17B_SCK0 (1u << 17) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PA11A_TXD0 (1u << 11) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA15A_CTS1 (1u << 15) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA14A_RTS1 (1u << 14) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA12A_RXD1 (1u << 12) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA16A_SCK1 (1u << 16) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PA13A_TXD1 (1u << 13) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PB23A_CTS2 (1u << 23) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PB22A_RTS2 (1u << 22) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PB21A_RXD2 (1u << 21) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PB24A_SCK2 (1u << 24) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PB20A_TXD2 (1u << 20) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio definition for USART3 peripheral ========== */ +#define PIO_PF4A_CTS3 (1u << 4) /**< \brief Usart3 signal: CTS3 */ +#define PIO_PF5A_RTS3 (1u << 5) /**< \brief Usart3 signal: RTS3 */ +#define PIO_PD5B_RXD3 (1u << 5) /**< \brief Usart3 signal: RXD3 */ +#define PIO_PE16B_SCK3 (1u << 16) /**< \brief Usart3 signal: SCK3 */ +#define PIO_PD4B_TXD3 (1u << 4) /**< \brief Usart3 signal: TXD3 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB10_IDX 42 +#define PIO_PB11_IDX 43 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PB14_IDX 46 +#define PIO_PB15_IDX 47 +#define PIO_PB16_IDX 48 +#define PIO_PB17_IDX 49 +#define PIO_PB18_IDX 50 +#define PIO_PB19_IDX 51 +#define PIO_PB20_IDX 52 +#define PIO_PB21_IDX 53 +#define PIO_PB22_IDX 54 +#define PIO_PB23_IDX 55 +#define PIO_PB24_IDX 56 +#define PIO_PB25_IDX 57 +#define PIO_PB26_IDX 58 +#define PIO_PB27_IDX 59 +#define PIO_PB28_IDX 60 +#define PIO_PB29_IDX 61 +#define PIO_PB30_IDX 62 +#define PIO_PB31_IDX 63 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 +#define PIO_PE6_IDX 134 +#define PIO_PE7_IDX 135 +#define PIO_PE8_IDX 136 +#define PIO_PE9_IDX 137 +#define PIO_PE10_IDX 138 +#define PIO_PE11_IDX 139 +#define PIO_PE12_IDX 140 +#define PIO_PE13_IDX 141 +#define PIO_PE14_IDX 142 +#define PIO_PE15_IDX 143 +#define PIO_PE16_IDX 144 +#define PIO_PE17_IDX 145 +#define PIO_PE18_IDX 146 +#define PIO_PE19_IDX 147 +#define PIO_PE20_IDX 148 +#define PIO_PE21_IDX 149 +#define PIO_PE22_IDX 150 +#define PIO_PE23_IDX 151 +#define PIO_PE24_IDX 152 +#define PIO_PE25_IDX 153 +#define PIO_PE26_IDX 154 +#define PIO_PE27_IDX 155 +#define PIO_PE28_IDX 156 +#define PIO_PE29_IDX 157 +#define PIO_PE30_IDX 158 +#define PIO_PE31_IDX 159 +#define PIO_PF0_IDX 160 +#define PIO_PF1_IDX 161 +#define PIO_PF2_IDX 162 +#define PIO_PF3_IDX 163 +#define PIO_PF4_IDX 164 +#define PIO_PF5_IDX 165 + +#endif /* _SAM3X8H_PIO_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/sam3a4c.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/sam3a4c.h new file mode 100644 index 0000000..c669bca --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/sam3a4c.h @@ -0,0 +1,547 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3A4C_ +#define _SAM3A4C_ + +/** \addtogroup SAM3A4C_definitions SAM3A4C definitions + This file defines all structures and symbols for SAM3A4C: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAM3A4C */ +/* ************************************************************************** */ +/** \addtogroup SAM3A4C_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ +/****** SAM3A4C specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAM3A4C Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAM3A4C Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAM3A4C Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAM3A4C Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAM3A4C Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAM3A4C Power Management Controller (PMC) */ + EFC0_IRQn = 6, /**< 6 SAM3A4C Enhanced Flash Controller 0 (EFC0) */ + EFC1_IRQn = 7, /**< 7 SAM3A4C Enhanced Flash Controller 1 (EFC1) */ + UART_IRQn = 8, /**< 8 SAM3A4C Universal Asynchronous Receiver Transceiver (UART) */ + PIOA_IRQn = 11, /**< 11 SAM3A4C Parallel I/O Controller A, (PIOA) */ + PIOB_IRQn = 12, /**< 12 SAM3A4C Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 17, /**< 17 SAM3A4C USART 0 (USART0) */ + USART1_IRQn = 18, /**< 18 SAM3A4C USART 1 (USART1) */ + USART2_IRQn = 19, /**< 19 SAM3A4C USART 2 (USART2) */ + HSMCI_IRQn = 21, /**< 21 SAM3A4C Multimedia Card Interface (HSMCI) */ + TWI0_IRQn = 22, /**< 22 SAM3A4C Two-Wire Interface 0 (TWI0) */ + TWI1_IRQn = 23, /**< 23 SAM3A4C Two-Wire Interface 1 (TWI1) */ + SPI0_IRQn = 24, /**< 24 SAM3A4C Serial Peripheral Interface (SPI0) */ + SSC_IRQn = 26, /**< 26 SAM3A4C Synchronous Serial Controller (SSC) */ + TC0_IRQn = 27, /**< 27 SAM3A4C Timer Counter 0 (TC0) */ + TC1_IRQn = 28, /**< 28 SAM3A4C Timer Counter 1 (TC1) */ + TC2_IRQn = 29, /**< 29 SAM3A4C Timer Counter 2 (TC2) */ + TC3_IRQn = 30, /**< 30 SAM3A4C Timer Counter 3 (TC3) */ + TC4_IRQn = 31, /**< 31 SAM3A4C Timer Counter 4 (TC4) */ + TC5_IRQn = 32, /**< 32 SAM3A4C Timer Counter 5 (TC5) */ + PWM_IRQn = 36, /**< 36 SAM3A4C Pulse Width Modulation Controller (PWM) */ + ADC_IRQn = 37, /**< 37 SAM3A4C ADC Controller (ADC) */ + DACC_IRQn = 38, /**< 38 SAM3A4C DAC Controller (DACC) */ + DMAC_IRQn = 39, /**< 39 SAM3A4C DMA Controller (DMAC) */ + UOTGHS_IRQn = 40, /**< 40 SAM3A4C USB OTG High Speed (UOTGHS) */ + TRNG_IRQn = 41, /**< 41 SAM3A4C True Random Number Generator (TRNG) */ + CAN0_IRQn = 43, /**< 43 SAM3A4C CAN Controller 0 (CAN0) */ + CAN1_IRQn = 44 /**< 44 SAM3A4C CAN Controller 1 (CAN1) */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC0_Handler; /* 6 Enhanced Flash Controller 0 */ + void* pfnEFC1_Handler; /* 7 Enhanced Flash Controller 1 */ + void* pfnUART_Handler; /* 8 Universal Asynchronous Receiver Transceiver */ + void* pvReserved9; + void* pvReserved10; + void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A, */ + void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */ + void* pvReserved13; + void* pvReserved14; + void* pvReserved15; + void* pvReserved16; + void* pfnUSART0_Handler; /* 17 USART 0 */ + void* pfnUSART1_Handler; /* 18 USART 1 */ + void* pfnUSART2_Handler; /* 19 USART 2 */ + void* pvReserved20; + void* pfnHSMCI_Handler; /* 21 Multimedia Card Interface */ + void* pfnTWI0_Handler; /* 22 Two-Wire Interface 0 */ + void* pfnTWI1_Handler; /* 23 Two-Wire Interface 1 */ + void* pfnSPI0_Handler; /* 24 Serial Peripheral Interface */ + void* pvReserved25; + void* pfnSSC_Handler; /* 26 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 27 Timer Counter 0 */ + void* pfnTC1_Handler; /* 28 Timer Counter 1 */ + void* pfnTC2_Handler; /* 29 Timer Counter 2 */ + void* pfnTC3_Handler; /* 30 Timer Counter 3 */ + void* pfnTC4_Handler; /* 31 Timer Counter 4 */ + void* pfnTC5_Handler; /* 32 Timer Counter 5 */ + void* pvReserved33; + void* pvReserved34; + void* pvReserved35; + void* pfnPWM_Handler; /* 36 Pulse Width Modulation Controller */ + void* pfnADC_Handler; /* 37 ADC Controller */ + void* pfnDACC_Handler; /* 38 DAC Controller */ + void* pfnDMAC_Handler; /* 39 DMA Controller */ + void* pfnUOTGHS_Handler; /* 40 USB OTG High Speed */ + void* pfnTRNG_Handler; /* 41 True Random Number Generator */ + void* pvReserved42; + void* pfnCAN0_Handler; /* 43 CAN Controller 0 */ + void* pfnCAN1_Handler; /* 44 CAN Controller 1 */ +} DeviceVectors; + +/* Cortex-M3 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ADC_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void DACC_Handler ( void ); +void DMAC_Handler ( void ); +void EFC0_Handler ( void ); +void EFC1_Handler ( void ); +void HSMCI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PMC_Handler ( void ); +void PWM_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TRNG_Handler ( void ); +void TWI0_Handler ( void ); +void TWI1_Handler ( void ); +void UART_Handler ( void ); +void UOTGHS_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void WDT_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ + +#define __CM3_REV 0x0200 /**< SAM3A4C core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAM3A4C does provide a MPU */ +#define __NVIC_PRIO_BITS 4 /**< SAM3A4C uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sam3x.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3A4C */ +/* ************************************************************************** */ +/** \addtogroup SAM3A4C_api Peripheral Software API */ +/*@{*/ + +#include "component/component_adc.h" +#include "component/component_can.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_dmac.h" +#include "component/component_efc.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_matrix.h" +#include "component/component_pdc.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_rstc.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twi.h" +#include "component/component_uart.h" +#include "component/component_uotghs.h" +#include "component/component_usart.h" +#include "component/component_wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAM3A4C */ +/* ************************************************************************** */ +/** \addtogroup SAM3A4C_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_tc1.h" +#include "instance/instance_twi0.h" +#include "instance/instance_twi1.h" +#include "instance/instance_pwm.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_uotghs.h" +#include "instance/instance_can0.h" +#include "instance/instance_can1.h" +#include "instance/instance_trng.h" +#include "instance/instance_adc.h" +#include "instance/instance_dmac.h" +#include "instance/instance_dacc.h" +#include "instance/instance_matrix.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart.h" +#include "instance/instance_chipid.h" +#include "instance/instance_efc0.h" +#include "instance/instance_efc1.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAM3A4C */ +/* ************************************************************************** */ +/** \addtogroup SAM3A4C_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC0 ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */ +#define ID_EFC1 ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */ +#define ID_UART ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */ +#define ID_PIOA (11) /**< \brief Parallel I/O Controller A, (PIOA) */ +#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (17) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (18) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (19) /**< \brief USART 2 (USART2) */ +#define ID_HSMCI (21) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWI0 (22) /**< \brief Two-Wire Interface 0 (TWI0) */ +#define ID_TWI1 (23) /**< \brief Two-Wire Interface 1 (TWI1) */ +#define ID_SPI0 (24) /**< \brief Serial Peripheral Interface (SPI0) */ +#define ID_SSC (26) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (27) /**< \brief Timer Counter 0 (TC0) */ +#define ID_TC1 (28) /**< \brief Timer Counter 1 (TC1) */ +#define ID_TC2 (29) /**< \brief Timer Counter 2 (TC2) */ +#define ID_TC3 (30) /**< \brief Timer Counter 3 (TC3) */ +#define ID_TC4 (31) /**< \brief Timer Counter 4 (TC4) */ +#define ID_TC5 (32) /**< \brief Timer Counter 5 (TC5) */ +#define ID_PWM (36) /**< \brief Pulse Width Modulation Controller (PWM) */ +#define ID_ADC (37) /**< \brief ADC Controller (ADC) */ +#define ID_DACC (38) /**< \brief DAC Controller (DACC) */ +#define ID_DMAC (39) /**< \brief DMA Controller (DMAC) */ +#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */ +#define ID_TRNG (41) /**< \brief True Random Number Generator (TRNG) */ +#define ID_CAN0 (43) /**< \brief CAN Controller 0 (CAN0) */ +#define ID_CAN1 (44) /**< \brief CAN Controller 1 (CAN1) */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAM3A4C */ +/* ************************************************************************** */ +/** \addtogroup SAM3A4C_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x40080000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40084000U) /**< \brief (TC1 ) Base Address */ +#define TWI0 (0x4008C000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 (0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 (0x40090000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 (0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM (0x40094000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM (0x40094100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 (0x40098000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 (0x4009C000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */ +#define USART2 (0x400A0000U) /**< \brief (USART2 ) Base Address */ +#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */ +#define UOTGHS (0x400AC000U) /**< \brief (UOTGHS ) Base Address */ +#define CAN0 (0x400B4000U) /**< \brief (CAN0 ) Base Address */ +#define CAN1 (0x400B8000U) /**< \brief (CAN1 ) Base Address */ +#define TRNG (0x400BC000U) /**< \brief (TRNG ) Base Address */ +#define ADC (0x400C0000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC (0x400C0100U) /**< \brief (PDC_ADC ) Base Address */ +#define DMAC (0x400C4000U) /**< \brief (DMAC ) Base Address */ +#define DACC (0x400C8000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC (0x400C8100U) /**< \brief (PDC_DACC ) Base Address */ +#define MATRIX (0x400E0400U) /**< \brief (MATRIX ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART (0x400E0800U) /**< \brief (UART ) Base Address */ +#define PDC_UART (0x400E0900U) /**< \brief (PDC_UART ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID ) Base Address */ +#define EFC0 (0x400E0A00U) /**< \brief (EFC0 ) Base Address */ +#define EFC1 (0x400E0C00U) /**< \brief (EFC1 ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define RSTC (0x400E1A00U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1A10U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1A30U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1A50U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1A60U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1A90U) /**< \brief (GPBR ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x40080000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40084000U) /**< \brief (TC1 ) Base Address */ +#define TWI0 ((Twi *)0x4008C000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 ((Pdc *)0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 ((Twi *)0x40090000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 ((Pdc *)0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM ((Pwm *)0x40094000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM ((Pdc *)0x40094100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 ((Usart *)0x40098000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 ((Pdc *)0x40098100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 ((Usart *)0x4009C000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 ((Pdc *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */ +#define USART2 ((Usart *)0x400A0000U) /**< \brief (USART2 ) Base Address */ +#define PDC_USART2 ((Pdc *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */ +#define UOTGHS ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS ) Base Address */ +#define CAN0 ((Can *)0x400B4000U) /**< \brief (CAN0 ) Base Address */ +#define CAN1 ((Can *)0x400B8000U) /**< \brief (CAN1 ) Base Address */ +#define TRNG ((Trng *)0x400BC000U) /**< \brief (TRNG ) Base Address */ +#define ADC ((Adc *)0x400C0000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC ((Pdc *)0x400C0100U) /**< \brief (PDC_ADC ) Base Address */ +#define DMAC ((Dmac *)0x400C4000U) /**< \brief (DMAC ) Base Address */ +#define DACC ((Dacc *)0x400C8000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC ((Pdc *)0x400C8100U) /**< \brief (PDC_DACC ) Base Address */ +#define MATRIX ((Matrix *)0x400E0400U) /**< \brief (MATRIX ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART ((Uart *)0x400E0800U) /**< \brief (UART ) Base Address */ +#define PDC_UART ((Pdc *)0x400E0900U) /**< \brief (PDC_UART ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID ) Base Address */ +#define EFC0 ((Efc *)0x400E0A00U) /**< \brief (EFC0 ) Base Address */ +#define EFC1 ((Efc *)0x400E0C00U) /**< \brief (EFC1 ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define RSTC ((Rstc *)0x400E1A00U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1A10U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1A30U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1A50U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1A60U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1A90U) /**< \brief (GPBR ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAM3A4C */ +/* ************************************************************************** */ +/** \addtogroup SAM3A4C_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_sam3a4c.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAM3A4C */ +/* ************************************************************************** */ + +#define IFLASH0_SIZE (0x20000u) +#define IFLASH0_PAGE_SIZE (256u) +#define IFLASH0_LOCK_REGION_SIZE (16384u) +#define IFLASH0_NB_OF_PAGES (512u) +#define IFLASH1_SIZE (0x20000u) +#define IFLASH1_PAGE_SIZE (256u) +#define IFLASH1_LOCK_REGION_SIZE (16384u) +#define IFLASH1_NB_OF_PAGES (512u) +#define IRAM0_SIZE (0x8000u) +#define IRAM1_SIZE (0x8000u) +#define IFLASH_SIZE (IFLASH0_SIZE+IFLASH1_SIZE) +#define IRAM_SIZE (IRAM0_SIZE+IRAM1_SIZE) + +#define IFLASH0_ADDR (0x00080000u) /**< Internal Flash 0 base address */ +#if defined IFLASH0_SIZE +#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */ +#endif +#define IROM_ADDR (0x00100000u) /**< Internal ROM base address */ +#define IRAM0_ADDR (0x20000000u) /**< Internal RAM 0 base address */ +#define IRAM1_ADDR (0x20080000u) /**< Internal RAM 1 base address */ +#define NFC_RAM_ADDR (0x20100000u) /**< NAND Flash Controller RAM base address */ +#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define EBI_CS4_ADDR (0x64000000u) /**< EBI Chip Select 4 base address */ +#define EBI_CS5_ADDR (0x65000000u) /**< EBI Chip Select 5 base address */ +#define EBI_CS6_ADDR (0x66000000u) /**< EBI Chip Select 6 base address */ +#define EBI_CS7_ADDR (0x67000000u) /**< EBI Chip Select 7 base address */ + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAM3A4C */ +/* ************************************************************************** */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (84000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Write Wait State */ +#define CHIP_FLASH_WRITE_WAIT_STATE (6U) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.8V) */ +#define CHIP_FREQ_FWS_0 (19000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (50000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (64000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (90000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAM3A4C_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/sam3a8c.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/sam3a8c.h new file mode 100644 index 0000000..fe4b6ed --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/sam3a8c.h @@ -0,0 +1,547 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3A8C_ +#define _SAM3A8C_ + +/** \addtogroup SAM3A8C_definitions SAM3A8C definitions + This file defines all structures and symbols for SAM3A8C: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAM3A8C */ +/* ************************************************************************** */ +/** \addtogroup SAM3A8C_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ +/****** SAM3A8C specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAM3A8C Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAM3A8C Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAM3A8C Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAM3A8C Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAM3A8C Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAM3A8C Power Management Controller (PMC) */ + EFC0_IRQn = 6, /**< 6 SAM3A8C Enhanced Flash Controller 0 (EFC0) */ + EFC1_IRQn = 7, /**< 7 SAM3A8C Enhanced Flash Controller 1 (EFC1) */ + UART_IRQn = 8, /**< 8 SAM3A8C Universal Asynchronous Receiver Transceiver (UART) */ + PIOA_IRQn = 11, /**< 11 SAM3A8C Parallel I/O Controller A, (PIOA) */ + PIOB_IRQn = 12, /**< 12 SAM3A8C Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 17, /**< 17 SAM3A8C USART 0 (USART0) */ + USART1_IRQn = 18, /**< 18 SAM3A8C USART 1 (USART1) */ + USART2_IRQn = 19, /**< 19 SAM3A8C USART 2 (USART2) */ + HSMCI_IRQn = 21, /**< 21 SAM3A8C Multimedia Card Interface (HSMCI) */ + TWI0_IRQn = 22, /**< 22 SAM3A8C Two-Wire Interface 0 (TWI0) */ + TWI1_IRQn = 23, /**< 23 SAM3A8C Two-Wire Interface 1 (TWI1) */ + SPI0_IRQn = 24, /**< 24 SAM3A8C Serial Peripheral Interface (SPI0) */ + SSC_IRQn = 26, /**< 26 SAM3A8C Synchronous Serial Controller (SSC) */ + TC0_IRQn = 27, /**< 27 SAM3A8C Timer Counter 0 (TC0) */ + TC1_IRQn = 28, /**< 28 SAM3A8C Timer Counter 1 (TC1) */ + TC2_IRQn = 29, /**< 29 SAM3A8C Timer Counter 2 (TC2) */ + TC3_IRQn = 30, /**< 30 SAM3A8C Timer Counter 3 (TC3) */ + TC4_IRQn = 31, /**< 31 SAM3A8C Timer Counter 4 (TC4) */ + TC5_IRQn = 32, /**< 32 SAM3A8C Timer Counter 5 (TC5) */ + PWM_IRQn = 36, /**< 36 SAM3A8C Pulse Width Modulation Controller (PWM) */ + ADC_IRQn = 37, /**< 37 SAM3A8C ADC Controller (ADC) */ + DACC_IRQn = 38, /**< 38 SAM3A8C DAC Controller (DACC) */ + DMAC_IRQn = 39, /**< 39 SAM3A8C DMA Controller (DMAC) */ + UOTGHS_IRQn = 40, /**< 40 SAM3A8C USB OTG High Speed (UOTGHS) */ + TRNG_IRQn = 41, /**< 41 SAM3A8C True Random Number Generator (TRNG) */ + CAN0_IRQn = 43, /**< 43 SAM3A8C CAN Controller 0 (CAN0) */ + CAN1_IRQn = 44 /**< 44 SAM3A8C CAN Controller 1 (CAN1) */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC0_Handler; /* 6 Enhanced Flash Controller 0 */ + void* pfnEFC1_Handler; /* 7 Enhanced Flash Controller 1 */ + void* pfnUART_Handler; /* 8 Universal Asynchronous Receiver Transceiver */ + void* pvReserved9; + void* pvReserved10; + void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A, */ + void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */ + void* pvReserved13; + void* pvReserved14; + void* pvReserved15; + void* pvReserved16; + void* pfnUSART0_Handler; /* 17 USART 0 */ + void* pfnUSART1_Handler; /* 18 USART 1 */ + void* pfnUSART2_Handler; /* 19 USART 2 */ + void* pvReserved20; + void* pfnHSMCI_Handler; /* 21 Multimedia Card Interface */ + void* pfnTWI0_Handler; /* 22 Two-Wire Interface 0 */ + void* pfnTWI1_Handler; /* 23 Two-Wire Interface 1 */ + void* pfnSPI0_Handler; /* 24 Serial Peripheral Interface */ + void* pvReserved25; + void* pfnSSC_Handler; /* 26 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 27 Timer Counter 0 */ + void* pfnTC1_Handler; /* 28 Timer Counter 1 */ + void* pfnTC2_Handler; /* 29 Timer Counter 2 */ + void* pfnTC3_Handler; /* 30 Timer Counter 3 */ + void* pfnTC4_Handler; /* 31 Timer Counter 4 */ + void* pfnTC5_Handler; /* 32 Timer Counter 5 */ + void* pvReserved33; + void* pvReserved34; + void* pvReserved35; + void* pfnPWM_Handler; /* 36 Pulse Width Modulation Controller */ + void* pfnADC_Handler; /* 37 ADC Controller */ + void* pfnDACC_Handler; /* 38 DAC Controller */ + void* pfnDMAC_Handler; /* 39 DMA Controller */ + void* pfnUOTGHS_Handler; /* 40 USB OTG High Speed */ + void* pfnTRNG_Handler; /* 41 True Random Number Generator */ + void* pvReserved42; + void* pfnCAN0_Handler; /* 43 CAN Controller 0 */ + void* pfnCAN1_Handler; /* 44 CAN Controller 1 */ +} DeviceVectors; + +/* Cortex-M3 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ADC_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void DACC_Handler ( void ); +void DMAC_Handler ( void ); +void EFC0_Handler ( void ); +void EFC1_Handler ( void ); +void HSMCI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PMC_Handler ( void ); +void PWM_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TRNG_Handler ( void ); +void TWI0_Handler ( void ); +void TWI1_Handler ( void ); +void UART_Handler ( void ); +void UOTGHS_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void WDT_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ + +#define __CM3_REV 0x0200 /**< SAM3A8C core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAM3A8C does provide a MPU */ +#define __NVIC_PRIO_BITS 4 /**< SAM3A8C uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sam3x.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3A8C */ +/* ************************************************************************** */ +/** \addtogroup SAM3A8C_api Peripheral Software API */ +/*@{*/ + +#include "component/component_adc.h" +#include "component/component_can.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_dmac.h" +#include "component/component_efc.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_matrix.h" +#include "component/component_pdc.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_rstc.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twi.h" +#include "component/component_uart.h" +#include "component/component_uotghs.h" +#include "component/component_usart.h" +#include "component/component_wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAM3A8C */ +/* ************************************************************************** */ +/** \addtogroup SAM3A8C_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_tc1.h" +#include "instance/instance_twi0.h" +#include "instance/instance_twi1.h" +#include "instance/instance_pwm.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_uotghs.h" +#include "instance/instance_can0.h" +#include "instance/instance_can1.h" +#include "instance/instance_trng.h" +#include "instance/instance_adc.h" +#include "instance/instance_dmac.h" +#include "instance/instance_dacc.h" +#include "instance/instance_matrix.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart.h" +#include "instance/instance_chipid.h" +#include "instance/instance_efc0.h" +#include "instance/instance_efc1.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAM3A8C */ +/* ************************************************************************** */ +/** \addtogroup SAM3A8C_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC0 ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */ +#define ID_EFC1 ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */ +#define ID_UART ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */ +#define ID_PIOA (11) /**< \brief Parallel I/O Controller A, (PIOA) */ +#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (17) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (18) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (19) /**< \brief USART 2 (USART2) */ +#define ID_HSMCI (21) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWI0 (22) /**< \brief Two-Wire Interface 0 (TWI0) */ +#define ID_TWI1 (23) /**< \brief Two-Wire Interface 1 (TWI1) */ +#define ID_SPI0 (24) /**< \brief Serial Peripheral Interface (SPI0) */ +#define ID_SSC (26) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (27) /**< \brief Timer Counter 0 (TC0) */ +#define ID_TC1 (28) /**< \brief Timer Counter 1 (TC1) */ +#define ID_TC2 (29) /**< \brief Timer Counter 2 (TC2) */ +#define ID_TC3 (30) /**< \brief Timer Counter 3 (TC3) */ +#define ID_TC4 (31) /**< \brief Timer Counter 4 (TC4) */ +#define ID_TC5 (32) /**< \brief Timer Counter 5 (TC5) */ +#define ID_PWM (36) /**< \brief Pulse Width Modulation Controller (PWM) */ +#define ID_ADC (37) /**< \brief ADC Controller (ADC) */ +#define ID_DACC (38) /**< \brief DAC Controller (DACC) */ +#define ID_DMAC (39) /**< \brief DMA Controller (DMAC) */ +#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */ +#define ID_TRNG (41) /**< \brief True Random Number Generator (TRNG) */ +#define ID_CAN0 (43) /**< \brief CAN Controller 0 (CAN0) */ +#define ID_CAN1 (44) /**< \brief CAN Controller 1 (CAN1) */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAM3A8C */ +/* ************************************************************************** */ +/** \addtogroup SAM3A8C_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x40080000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40084000U) /**< \brief (TC1 ) Base Address */ +#define TWI0 (0x4008C000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 (0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 (0x40090000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 (0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM (0x40094000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM (0x40094100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 (0x40098000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 (0x4009C000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */ +#define USART2 (0x400A0000U) /**< \brief (USART2 ) Base Address */ +#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */ +#define UOTGHS (0x400AC000U) /**< \brief (UOTGHS ) Base Address */ +#define CAN0 (0x400B4000U) /**< \brief (CAN0 ) Base Address */ +#define CAN1 (0x400B8000U) /**< \brief (CAN1 ) Base Address */ +#define TRNG (0x400BC000U) /**< \brief (TRNG ) Base Address */ +#define ADC (0x400C0000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC (0x400C0100U) /**< \brief (PDC_ADC ) Base Address */ +#define DMAC (0x400C4000U) /**< \brief (DMAC ) Base Address */ +#define DACC (0x400C8000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC (0x400C8100U) /**< \brief (PDC_DACC ) Base Address */ +#define MATRIX (0x400E0400U) /**< \brief (MATRIX ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART (0x400E0800U) /**< \brief (UART ) Base Address */ +#define PDC_UART (0x400E0900U) /**< \brief (PDC_UART ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID ) Base Address */ +#define EFC0 (0x400E0A00U) /**< \brief (EFC0 ) Base Address */ +#define EFC1 (0x400E0C00U) /**< \brief (EFC1 ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define RSTC (0x400E1A00U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1A10U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1A30U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1A50U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1A60U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1A90U) /**< \brief (GPBR ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x40080000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40084000U) /**< \brief (TC1 ) Base Address */ +#define TWI0 ((Twi *)0x4008C000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 ((Pdc *)0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 ((Twi *)0x40090000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 ((Pdc *)0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM ((Pwm *)0x40094000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM ((Pdc *)0x40094100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 ((Usart *)0x40098000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 ((Pdc *)0x40098100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 ((Usart *)0x4009C000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 ((Pdc *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */ +#define USART2 ((Usart *)0x400A0000U) /**< \brief (USART2 ) Base Address */ +#define PDC_USART2 ((Pdc *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */ +#define UOTGHS ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS ) Base Address */ +#define CAN0 ((Can *)0x400B4000U) /**< \brief (CAN0 ) Base Address */ +#define CAN1 ((Can *)0x400B8000U) /**< \brief (CAN1 ) Base Address */ +#define TRNG ((Trng *)0x400BC000U) /**< \brief (TRNG ) Base Address */ +#define ADC ((Adc *)0x400C0000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC ((Pdc *)0x400C0100U) /**< \brief (PDC_ADC ) Base Address */ +#define DMAC ((Dmac *)0x400C4000U) /**< \brief (DMAC ) Base Address */ +#define DACC ((Dacc *)0x400C8000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC ((Pdc *)0x400C8100U) /**< \brief (PDC_DACC ) Base Address */ +#define MATRIX ((Matrix *)0x400E0400U) /**< \brief (MATRIX ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART ((Uart *)0x400E0800U) /**< \brief (UART ) Base Address */ +#define PDC_UART ((Pdc *)0x400E0900U) /**< \brief (PDC_UART ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID ) Base Address */ +#define EFC0 ((Efc *)0x400E0A00U) /**< \brief (EFC0 ) Base Address */ +#define EFC1 ((Efc *)0x400E0C00U) /**< \brief (EFC1 ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define RSTC ((Rstc *)0x400E1A00U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1A10U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1A30U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1A50U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1A60U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1A90U) /**< \brief (GPBR ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAM3A8C */ +/* ************************************************************************** */ +/** \addtogroup SAM3A8C_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_sam3a8c.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAM3A8C */ +/* ************************************************************************** */ + +#define IFLASH0_SIZE (0x40000u) +#define IFLASH0_PAGE_SIZE (256u) +#define IFLASH0_LOCK_REGION_SIZE (16384u) +#define IFLASH0_NB_OF_PAGES (1024u) +#define IFLASH1_SIZE (0x40000u) +#define IFLASH1_PAGE_SIZE (256u) +#define IFLASH1_LOCK_REGION_SIZE (16384u) +#define IFLASH1_NB_OF_PAGES (1024u) +#define IRAM0_SIZE (0x10000u) +#define IRAM1_SIZE (0x8000u) +#define IFLASH_SIZE (IFLASH0_SIZE+IFLASH1_SIZE) +#define IRAM_SIZE (IRAM0_SIZE+IRAM1_SIZE) + +#define IFLASH0_ADDR (0x00080000u) /**< Internal Flash 0 base address */ +#if defined IFLASH0_SIZE +#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */ +#endif +#define IROM_ADDR (0x00100000u) /**< Internal ROM base address */ +#define IRAM0_ADDR (0x20000000u) /**< Internal RAM 0 base address */ +#define IRAM1_ADDR (0x20080000u) /**< Internal RAM 1 base address */ +#define NFC_RAM_ADDR (0x20100000u) /**< NAND Flash Controller RAM base address */ +#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define EBI_CS4_ADDR (0x64000000u) /**< EBI Chip Select 4 base address */ +#define EBI_CS5_ADDR (0x65000000u) /**< EBI Chip Select 5 base address */ +#define EBI_CS6_ADDR (0x66000000u) /**< EBI Chip Select 6 base address */ +#define EBI_CS7_ADDR (0x67000000u) /**< EBI Chip Select 7 base address */ + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAM3A8C */ +/* ************************************************************************** */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (84000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Write Wait State */ +#define CHIP_FLASH_WRITE_WAIT_STATE (6U) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.8V) */ +#define CHIP_FREQ_FWS_0 (19000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (50000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (64000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (90000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAM3A8C_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/sam3x4c.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/sam3x4c.h new file mode 100644 index 0000000..e9ed8b8 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/sam3x4c.h @@ -0,0 +1,554 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3X4C_ +#define _SAM3X4C_ + +/** \addtogroup SAM3X4C_definitions SAM3X4C definitions + This file defines all structures and symbols for SAM3X4C: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAM3X4C */ +/* ************************************************************************** */ +/** \addtogroup SAM3X4C_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ +/****** SAM3X4C specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAM3X4C Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAM3X4C Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAM3X4C Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAM3X4C Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAM3X4C Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAM3X4C Power Management Controller (PMC) */ + EFC0_IRQn = 6, /**< 6 SAM3X4C Enhanced Flash Controller 0 (EFC0) */ + EFC1_IRQn = 7, /**< 7 SAM3X4C Enhanced Flash Controller 1 (EFC1) */ + UART_IRQn = 8, /**< 8 SAM3X4C Universal Asynchronous Receiver Transceiver (UART) */ + PIOA_IRQn = 11, /**< 11 SAM3X4C Parallel I/O Controller A, (PIOA) */ + PIOB_IRQn = 12, /**< 12 SAM3X4C Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 17, /**< 17 SAM3X4C USART 0 (USART0) */ + USART1_IRQn = 18, /**< 18 SAM3X4C USART 1 (USART1) */ + USART2_IRQn = 19, /**< 19 SAM3X4C USART 2 (USART2) */ + HSMCI_IRQn = 21, /**< 21 SAM3X4C Multimedia Card Interface (HSMCI) */ + TWI0_IRQn = 22, /**< 22 SAM3X4C Two-Wire Interface 0 (TWI0) */ + TWI1_IRQn = 23, /**< 23 SAM3X4C Two-Wire Interface 1 (TWI1) */ + SPI0_IRQn = 24, /**< 24 SAM3X4C Serial Peripheral Interface (SPI0) */ + SSC_IRQn = 26, /**< 26 SAM3X4C Synchronous Serial Controller (SSC) */ + TC0_IRQn = 27, /**< 27 SAM3X4C Timer Counter 0 (TC0) */ + TC1_IRQn = 28, /**< 28 SAM3X4C Timer Counter 1 (TC1) */ + TC2_IRQn = 29, /**< 29 SAM3X4C Timer Counter 2 (TC2) */ + TC3_IRQn = 30, /**< 30 SAM3X4C Timer Counter 3 (TC3) */ + TC4_IRQn = 31, /**< 31 SAM3X4C Timer Counter 4 (TC4) */ + TC5_IRQn = 32, /**< 32 SAM3X4C Timer Counter 5 (TC5) */ + PWM_IRQn = 36, /**< 36 SAM3X4C Pulse Width Modulation Controller (PWM) */ + ADC_IRQn = 37, /**< 37 SAM3X4C ADC Controller (ADC) */ + DACC_IRQn = 38, /**< 38 SAM3X4C DAC Controller (DACC) */ + DMAC_IRQn = 39, /**< 39 SAM3X4C DMA Controller (DMAC) */ + UOTGHS_IRQn = 40, /**< 40 SAM3X4C USB OTG High Speed (UOTGHS) */ + TRNG_IRQn = 41, /**< 41 SAM3X4C True Random Number Generator (TRNG) */ + EMAC_IRQn = 42, /**< 42 SAM3X4C Ethernet MAC (EMAC) */ + CAN0_IRQn = 43, /**< 43 SAM3X4C CAN Controller 0 (CAN0) */ + CAN1_IRQn = 44 /**< 44 SAM3X4C CAN Controller 1 (CAN1) */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC0_Handler; /* 6 Enhanced Flash Controller 0 */ + void* pfnEFC1_Handler; /* 7 Enhanced Flash Controller 1 */ + void* pfnUART_Handler; /* 8 Universal Asynchronous Receiver Transceiver */ + void* pvReserved9; + void* pvReserved10; + void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A, */ + void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */ + void* pvReserved13; + void* pvReserved14; + void* pvReserved15; + void* pvReserved16; + void* pfnUSART0_Handler; /* 17 USART 0 */ + void* pfnUSART1_Handler; /* 18 USART 1 */ + void* pfnUSART2_Handler; /* 19 USART 2 */ + void* pvReserved20; + void* pfnHSMCI_Handler; /* 21 Multimedia Card Interface */ + void* pfnTWI0_Handler; /* 22 Two-Wire Interface 0 */ + void* pfnTWI1_Handler; /* 23 Two-Wire Interface 1 */ + void* pfnSPI0_Handler; /* 24 Serial Peripheral Interface */ + void* pvReserved25; + void* pfnSSC_Handler; /* 26 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 27 Timer Counter 0 */ + void* pfnTC1_Handler; /* 28 Timer Counter 1 */ + void* pfnTC2_Handler; /* 29 Timer Counter 2 */ + void* pfnTC3_Handler; /* 30 Timer Counter 3 */ + void* pfnTC4_Handler; /* 31 Timer Counter 4 */ + void* pfnTC5_Handler; /* 32 Timer Counter 5 */ + void* pvReserved33; + void* pvReserved34; + void* pvReserved35; + void* pfnPWM_Handler; /* 36 Pulse Width Modulation Controller */ + void* pfnADC_Handler; /* 37 ADC Controller */ + void* pfnDACC_Handler; /* 38 DAC Controller */ + void* pfnDMAC_Handler; /* 39 DMA Controller */ + void* pfnUOTGHS_Handler; /* 40 USB OTG High Speed */ + void* pfnTRNG_Handler; /* 41 True Random Number Generator */ + void* pfnEMAC_Handler; /* 42 Ethernet MAC */ + void* pfnCAN0_Handler; /* 43 CAN Controller 0 */ + void* pfnCAN1_Handler; /* 44 CAN Controller 1 */ +} DeviceVectors; + +/* Cortex-M3 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ADC_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void DACC_Handler ( void ); +void DMAC_Handler ( void ); +void EFC0_Handler ( void ); +void EFC1_Handler ( void ); +void EMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PMC_Handler ( void ); +void PWM_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TRNG_Handler ( void ); +void TWI0_Handler ( void ); +void TWI1_Handler ( void ); +void UART_Handler ( void ); +void UOTGHS_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void WDT_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ + +#define __CM3_REV 0x0200 /**< SAM3X4C core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAM3X4C does provide a MPU */ +#define __NVIC_PRIO_BITS 4 /**< SAM3X4C uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sam3x.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3X4C */ +/* ************************************************************************** */ +/** \addtogroup SAM3X4C_api Peripheral Software API */ +/*@{*/ + +#include "component/component_adc.h" +#include "component/component_can.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_dmac.h" +#include "component/component_efc.h" +#include "component/component_emac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_matrix.h" +#include "component/component_pdc.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_rstc.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twi.h" +#include "component/component_uart.h" +#include "component/component_uotghs.h" +#include "component/component_usart.h" +#include "component/component_wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAM3X4C */ +/* ************************************************************************** */ +/** \addtogroup SAM3X4C_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_tc1.h" +#include "instance/instance_twi0.h" +#include "instance/instance_twi1.h" +#include "instance/instance_pwm.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_uotghs.h" +#include "instance/instance_emac.h" +#include "instance/instance_can0.h" +#include "instance/instance_can1.h" +#include "instance/instance_trng.h" +#include "instance/instance_adc.h" +#include "instance/instance_dmac.h" +#include "instance/instance_dacc.h" +#include "instance/instance_matrix.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart.h" +#include "instance/instance_chipid.h" +#include "instance/instance_efc0.h" +#include "instance/instance_efc1.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAM3X4C */ +/* ************************************************************************** */ +/** \addtogroup SAM3X4C_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC0 ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */ +#define ID_EFC1 ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */ +#define ID_UART ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */ +#define ID_PIOA (11) /**< \brief Parallel I/O Controller A, (PIOA) */ +#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (17) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (18) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (19) /**< \brief USART 2 (USART2) */ +#define ID_HSMCI (21) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWI0 (22) /**< \brief Two-Wire Interface 0 (TWI0) */ +#define ID_TWI1 (23) /**< \brief Two-Wire Interface 1 (TWI1) */ +#define ID_SPI0 (24) /**< \brief Serial Peripheral Interface (SPI0) */ +#define ID_SSC (26) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (27) /**< \brief Timer Counter 0 (TC0) */ +#define ID_TC1 (28) /**< \brief Timer Counter 1 (TC1) */ +#define ID_TC2 (29) /**< \brief Timer Counter 2 (TC2) */ +#define ID_TC3 (30) /**< \brief Timer Counter 3 (TC3) */ +#define ID_TC4 (31) /**< \brief Timer Counter 4 (TC4) */ +#define ID_TC5 (32) /**< \brief Timer Counter 5 (TC5) */ +#define ID_PWM (36) /**< \brief Pulse Width Modulation Controller (PWM) */ +#define ID_ADC (37) /**< \brief ADC Controller (ADC) */ +#define ID_DACC (38) /**< \brief DAC Controller (DACC) */ +#define ID_DMAC (39) /**< \brief DMA Controller (DMAC) */ +#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */ +#define ID_TRNG (41) /**< \brief True Random Number Generator (TRNG) */ +#define ID_EMAC (42) /**< \brief Ethernet MAC (EMAC) */ +#define ID_CAN0 (43) /**< \brief CAN Controller 0 (CAN0) */ +#define ID_CAN1 (44) /**< \brief CAN Controller 1 (CAN1) */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAM3X4C */ +/* ************************************************************************** */ +/** \addtogroup SAM3X4C_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x40080000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40084000U) /**< \brief (TC1 ) Base Address */ +#define TWI0 (0x4008C000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 (0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 (0x40090000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 (0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM (0x40094000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM (0x40094100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 (0x40098000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 (0x4009C000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */ +#define USART2 (0x400A0000U) /**< \brief (USART2 ) Base Address */ +#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */ +#define UOTGHS (0x400AC000U) /**< \brief (UOTGHS ) Base Address */ +#define EMAC (0x400B0000U) /**< \brief (EMAC ) Base Address */ +#define CAN0 (0x400B4000U) /**< \brief (CAN0 ) Base Address */ +#define CAN1 (0x400B8000U) /**< \brief (CAN1 ) Base Address */ +#define TRNG (0x400BC000U) /**< \brief (TRNG ) Base Address */ +#define ADC (0x400C0000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC (0x400C0100U) /**< \brief (PDC_ADC ) Base Address */ +#define DMAC (0x400C4000U) /**< \brief (DMAC ) Base Address */ +#define DACC (0x400C8000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC (0x400C8100U) /**< \brief (PDC_DACC ) Base Address */ +#define MATRIX (0x400E0400U) /**< \brief (MATRIX ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART (0x400E0800U) /**< \brief (UART ) Base Address */ +#define PDC_UART (0x400E0900U) /**< \brief (PDC_UART ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID ) Base Address */ +#define EFC0 (0x400E0A00U) /**< \brief (EFC0 ) Base Address */ +#define EFC1 (0x400E0C00U) /**< \brief (EFC1 ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define RSTC (0x400E1A00U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1A10U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1A30U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1A50U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1A60U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1A90U) /**< \brief (GPBR ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x40080000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40084000U) /**< \brief (TC1 ) Base Address */ +#define TWI0 ((Twi *)0x4008C000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 ((Pdc *)0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 ((Twi *)0x40090000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 ((Pdc *)0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM ((Pwm *)0x40094000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM ((Pdc *)0x40094100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 ((Usart *)0x40098000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 ((Pdc *)0x40098100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 ((Usart *)0x4009C000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 ((Pdc *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */ +#define USART2 ((Usart *)0x400A0000U) /**< \brief (USART2 ) Base Address */ +#define PDC_USART2 ((Pdc *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */ +#define UOTGHS ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS ) Base Address */ +#define EMAC ((Emac *)0x400B0000U) /**< \brief (EMAC ) Base Address */ +#define CAN0 ((Can *)0x400B4000U) /**< \brief (CAN0 ) Base Address */ +#define CAN1 ((Can *)0x400B8000U) /**< \brief (CAN1 ) Base Address */ +#define TRNG ((Trng *)0x400BC000U) /**< \brief (TRNG ) Base Address */ +#define ADC ((Adc *)0x400C0000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC ((Pdc *)0x400C0100U) /**< \brief (PDC_ADC ) Base Address */ +#define DMAC ((Dmac *)0x400C4000U) /**< \brief (DMAC ) Base Address */ +#define DACC ((Dacc *)0x400C8000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC ((Pdc *)0x400C8100U) /**< \brief (PDC_DACC ) Base Address */ +#define MATRIX ((Matrix *)0x400E0400U) /**< \brief (MATRIX ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART ((Uart *)0x400E0800U) /**< \brief (UART ) Base Address */ +#define PDC_UART ((Pdc *)0x400E0900U) /**< \brief (PDC_UART ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID ) Base Address */ +#define EFC0 ((Efc *)0x400E0A00U) /**< \brief (EFC0 ) Base Address */ +#define EFC1 ((Efc *)0x400E0C00U) /**< \brief (EFC1 ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define RSTC ((Rstc *)0x400E1A00U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1A10U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1A30U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1A50U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1A60U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1A90U) /**< \brief (GPBR ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAM3X4C */ +/* ************************************************************************** */ +/** \addtogroup SAM3X4C_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_sam3x4c.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAM3X4C */ +/* ************************************************************************** */ + +#define IFLASH0_SIZE (0x20000u) +#define IFLASH0_PAGE_SIZE (256u) +#define IFLASH0_LOCK_REGION_SIZE (16384u) +#define IFLASH0_NB_OF_PAGES (512u) +#define IFLASH1_SIZE (0x20000u) +#define IFLASH1_PAGE_SIZE (256u) +#define IFLASH1_LOCK_REGION_SIZE (16384u) +#define IFLASH1_NB_OF_PAGES (512u) +#define IRAM0_SIZE (0x8000u) +#define IRAM1_SIZE (0x8000u) +#define IFLASH_SIZE (IFLASH0_SIZE+IFLASH1_SIZE) +#define IRAM_SIZE (IRAM0_SIZE+IRAM1_SIZE) + +#define IFLASH0_ADDR (0x00080000u) /**< Internal Flash 0 base address */ +#if defined IFLASH0_SIZE +#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */ +#endif +#define IROM_ADDR (0x00100000u) /**< Internal ROM base address */ +#define IRAM0_ADDR (0x20000000u) /**< Internal RAM 0 base address */ +#define IRAM1_ADDR (0x20080000u) /**< Internal RAM 1 base address */ +#define NFC_RAM_ADDR (0x20100000u) /**< NAND Flash Controller RAM base address */ +#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define EBI_CS4_ADDR (0x64000000u) /**< EBI Chip Select 4 base address */ +#define EBI_CS5_ADDR (0x65000000u) /**< EBI Chip Select 5 base address */ +#define EBI_CS6_ADDR (0x66000000u) /**< EBI Chip Select 6 base address */ +#define EBI_CS7_ADDR (0x67000000u) /**< EBI Chip Select 7 base address */ + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAM3X4C */ +/* ************************************************************************** */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (84000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Write Wait State */ +#define CHIP_FLASH_WRITE_WAIT_STATE (6U) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.8V) */ +#define CHIP_FREQ_FWS_0 (19000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (50000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (64000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (90000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAM3X4C_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/sam3x4e.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/sam3x4e.h new file mode 100644 index 0000000..31b3579 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/sam3x4e.h @@ -0,0 +1,595 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3X4E_ +#define _SAM3X4E_ + +/** \addtogroup SAM3X4E_definitions SAM3X4E definitions + This file defines all structures and symbols for SAM3X4E: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAM3X4E */ +/* ************************************************************************** */ +/** \addtogroup SAM3X4E_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ +/****** SAM3X4E specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAM3X4E Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAM3X4E Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAM3X4E Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAM3X4E Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAM3X4E Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAM3X4E Power Management Controller (PMC) */ + EFC0_IRQn = 6, /**< 6 SAM3X4E Enhanced Flash Controller 0 (EFC0) */ + EFC1_IRQn = 7, /**< 7 SAM3X4E Enhanced Flash Controller 1 (EFC1) */ + UART_IRQn = 8, /**< 8 SAM3X4E Universal Asynchronous Receiver Transceiver (UART) */ + SMC_IRQn = 9, /**< 9 SAM3X4E Static Memory Controller (SMC) */ + PIOA_IRQn = 11, /**< 11 SAM3X4E Parallel I/O Controller A, (PIOA) */ + PIOB_IRQn = 12, /**< 12 SAM3X4E Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 13, /**< 13 SAM3X4E Parallel I/O Controller C (PIOC) */ + PIOD_IRQn = 14, /**< 14 SAM3X4E Parallel I/O Controller D (PIOD) */ + USART0_IRQn = 17, /**< 17 SAM3X4E USART 0 (USART0) */ + USART1_IRQn = 18, /**< 18 SAM3X4E USART 1 (USART1) */ + USART2_IRQn = 19, /**< 19 SAM3X4E USART 2 (USART2) */ + USART3_IRQn = 20, /**< 20 SAM3X4E USART 3 (USART3) */ + HSMCI_IRQn = 21, /**< 21 SAM3X4E Multimedia Card Interface (HSMCI) */ + TWI0_IRQn = 22, /**< 22 SAM3X4E Two-Wire Interface 0 (TWI0) */ + TWI1_IRQn = 23, /**< 23 SAM3X4E Two-Wire Interface 1 (TWI1) */ + SPI0_IRQn = 24, /**< 24 SAM3X4E Serial Peripheral Interface (SPI0) */ + SSC_IRQn = 26, /**< 26 SAM3X4E Synchronous Serial Controller (SSC) */ + TC0_IRQn = 27, /**< 27 SAM3X4E Timer Counter 0 (TC0) */ + TC1_IRQn = 28, /**< 28 SAM3X4E Timer Counter 1 (TC1) */ + TC2_IRQn = 29, /**< 29 SAM3X4E Timer Counter 2 (TC2) */ + TC3_IRQn = 30, /**< 30 SAM3X4E Timer Counter 3 (TC3) */ + TC4_IRQn = 31, /**< 31 SAM3X4E Timer Counter 4 (TC4) */ + TC5_IRQn = 32, /**< 32 SAM3X4E Timer Counter 5 (TC5) */ + TC6_IRQn = 33, /**< 33 SAM3X4E Timer Counter 6 (TC6) */ + TC7_IRQn = 34, /**< 34 SAM3X4E Timer Counter 7 (TC7) */ + TC8_IRQn = 35, /**< 35 SAM3X4E Timer Counter 8 (TC8) */ + PWM_IRQn = 36, /**< 36 SAM3X4E Pulse Width Modulation Controller (PWM) */ + ADC_IRQn = 37, /**< 37 SAM3X4E ADC Controller (ADC) */ + DACC_IRQn = 38, /**< 38 SAM3X4E DAC Controller (DACC) */ + DMAC_IRQn = 39, /**< 39 SAM3X4E DMA Controller (DMAC) */ + UOTGHS_IRQn = 40, /**< 40 SAM3X4E USB OTG High Speed (UOTGHS) */ + TRNG_IRQn = 41, /**< 41 SAM3X4E True Random Number Generator (TRNG) */ + EMAC_IRQn = 42, /**< 42 SAM3X4E Ethernet MAC (EMAC) */ + CAN0_IRQn = 43, /**< 43 SAM3X4E CAN Controller 0 (CAN0) */ + CAN1_IRQn = 44 /**< 44 SAM3X4E CAN Controller 1 (CAN1) */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC0_Handler; /* 6 Enhanced Flash Controller 0 */ + void* pfnEFC1_Handler; /* 7 Enhanced Flash Controller 1 */ + void* pfnUART_Handler; /* 8 Universal Asynchronous Receiver Transceiver */ + void* pfnSMC_Handler; /* 9 Static Memory Controller */ + void* pvReserved10; + void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A, */ + void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 13 Parallel I/O Controller C */ + void* pfnPIOD_Handler; /* 14 Parallel I/O Controller D */ + void* pvReserved15; + void* pvReserved16; + void* pfnUSART0_Handler; /* 17 USART 0 */ + void* pfnUSART1_Handler; /* 18 USART 1 */ + void* pfnUSART2_Handler; /* 19 USART 2 */ + void* pfnUSART3_Handler; /* 20 USART 3 */ + void* pfnHSMCI_Handler; /* 21 Multimedia Card Interface */ + void* pfnTWI0_Handler; /* 22 Two-Wire Interface 0 */ + void* pfnTWI1_Handler; /* 23 Two-Wire Interface 1 */ + void* pfnSPI0_Handler; /* 24 Serial Peripheral Interface */ + void* pvReserved25; + void* pfnSSC_Handler; /* 26 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 27 Timer Counter 0 */ + void* pfnTC1_Handler; /* 28 Timer Counter 1 */ + void* pfnTC2_Handler; /* 29 Timer Counter 2 */ + void* pfnTC3_Handler; /* 30 Timer Counter 3 */ + void* pfnTC4_Handler; /* 31 Timer Counter 4 */ + void* pfnTC5_Handler; /* 32 Timer Counter 5 */ + void* pfnTC6_Handler; /* 33 Timer Counter 6 */ + void* pfnTC7_Handler; /* 34 Timer Counter 7 */ + void* pfnTC8_Handler; /* 35 Timer Counter 8 */ + void* pfnPWM_Handler; /* 36 Pulse Width Modulation Controller */ + void* pfnADC_Handler; /* 37 ADC Controller */ + void* pfnDACC_Handler; /* 38 DAC Controller */ + void* pfnDMAC_Handler; /* 39 DMA Controller */ + void* pfnUOTGHS_Handler; /* 40 USB OTG High Speed */ + void* pfnTRNG_Handler; /* 41 True Random Number Generator */ + void* pfnEMAC_Handler; /* 42 Ethernet MAC */ + void* pfnCAN0_Handler; /* 43 CAN Controller 0 */ + void* pfnCAN1_Handler; /* 44 CAN Controller 1 */ +} DeviceVectors; + +/* Cortex-M3 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ADC_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void DACC_Handler ( void ); +void DMAC_Handler ( void ); +void EFC0_Handler ( void ); +void EFC1_Handler ( void ); +void EMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SMC_Handler ( void ); +void SPI0_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TRNG_Handler ( void ); +void TWI0_Handler ( void ); +void TWI1_Handler ( void ); +void UART_Handler ( void ); +void UOTGHS_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USART3_Handler ( void ); +void WDT_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ + +#define __CM3_REV 0x0200 /**< SAM3X4E core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAM3X4E does provide a MPU */ +#define __NVIC_PRIO_BITS 4 /**< SAM3X4E uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sam3x.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3X4E */ +/* ************************************************************************** */ +/** \addtogroup SAM3X4E_api Peripheral Software API */ +/*@{*/ + +#include "component/component_adc.h" +#include "component/component_can.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_dmac.h" +#include "component/component_efc.h" +#include "component/component_emac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_matrix.h" +#include "component/component_pdc.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_rstc.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_smc.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twi.h" +#include "component/component_uart.h" +#include "component/component_uotghs.h" +#include "component/component_usart.h" +#include "component/component_wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAM3X4E */ +/* ************************************************************************** */ +/** \addtogroup SAM3X4E_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_tc1.h" +#include "instance/instance_tc2.h" +#include "instance/instance_twi0.h" +#include "instance/instance_twi1.h" +#include "instance/instance_pwm.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_usart3.h" +#include "instance/instance_uotghs.h" +#include "instance/instance_emac.h" +#include "instance/instance_can0.h" +#include "instance/instance_can1.h" +#include "instance/instance_trng.h" +#include "instance/instance_adc.h" +#include "instance/instance_dmac.h" +#include "instance/instance_dacc.h" +#include "instance/instance_smc.h" +#include "instance/instance_matrix.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart.h" +#include "instance/instance_chipid.h" +#include "instance/instance_efc0.h" +#include "instance/instance_efc1.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_pioc.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAM3X4E */ +/* ************************************************************************** */ +/** \addtogroup SAM3X4E_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC0 ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */ +#define ID_EFC1 ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */ +#define ID_UART ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (11) /**< \brief Parallel I/O Controller A, (PIOA) */ +#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_PIOD (14) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_USART0 (17) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (18) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (19) /**< \brief USART 2 (USART2) */ +#define ID_USART3 (20) /**< \brief USART 3 (USART3) */ +#define ID_HSMCI (21) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWI0 (22) /**< \brief Two-Wire Interface 0 (TWI0) */ +#define ID_TWI1 (23) /**< \brief Two-Wire Interface 1 (TWI1) */ +#define ID_SPI0 (24) /**< \brief Serial Peripheral Interface (SPI0) */ +#define ID_SSC (26) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (27) /**< \brief Timer Counter 0 (TC0) */ +#define ID_TC1 (28) /**< \brief Timer Counter 1 (TC1) */ +#define ID_TC2 (29) /**< \brief Timer Counter 2 (TC2) */ +#define ID_TC3 (30) /**< \brief Timer Counter 3 (TC3) */ +#define ID_TC4 (31) /**< \brief Timer Counter 4 (TC4) */ +#define ID_TC5 (32) /**< \brief Timer Counter 5 (TC5) */ +#define ID_TC6 (33) /**< \brief Timer Counter 6 (TC6) */ +#define ID_TC7 (34) /**< \brief Timer Counter 7 (TC7) */ +#define ID_TC8 (35) /**< \brief Timer Counter 8 (TC8) */ +#define ID_PWM (36) /**< \brief Pulse Width Modulation Controller (PWM) */ +#define ID_ADC (37) /**< \brief ADC Controller (ADC) */ +#define ID_DACC (38) /**< \brief DAC Controller (DACC) */ +#define ID_DMAC (39) /**< \brief DMA Controller (DMAC) */ +#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */ +#define ID_TRNG (41) /**< \brief True Random Number Generator (TRNG) */ +#define ID_EMAC (42) /**< \brief Ethernet MAC (EMAC) */ +#define ID_CAN0 (43) /**< \brief CAN Controller 0 (CAN0) */ +#define ID_CAN1 (44) /**< \brief CAN Controller 1 (CAN1) */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAM3X4E */ +/* ************************************************************************** */ +/** \addtogroup SAM3X4E_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x40080000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40084000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40088000U) /**< \brief (TC2 ) Base Address */ +#define TWI0 (0x4008C000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 (0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 (0x40090000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 (0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM (0x40094000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM (0x40094100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 (0x40098000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 (0x4009C000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */ +#define USART2 (0x400A0000U) /**< \brief (USART2 ) Base Address */ +#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */ +#define USART3 (0x400A4000U) /**< \brief (USART3 ) Base Address */ +#define PDC_USART3 (0x400A4100U) /**< \brief (PDC_USART3) Base Address */ +#define UOTGHS (0x400AC000U) /**< \brief (UOTGHS ) Base Address */ +#define EMAC (0x400B0000U) /**< \brief (EMAC ) Base Address */ +#define CAN0 (0x400B4000U) /**< \brief (CAN0 ) Base Address */ +#define CAN1 (0x400B8000U) /**< \brief (CAN1 ) Base Address */ +#define TRNG (0x400BC000U) /**< \brief (TRNG ) Base Address */ +#define ADC (0x400C0000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC (0x400C0100U) /**< \brief (PDC_ADC ) Base Address */ +#define DMAC (0x400C4000U) /**< \brief (DMAC ) Base Address */ +#define DACC (0x400C8000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC (0x400C8100U) /**< \brief (PDC_DACC ) Base Address */ +#define SMC (0x400E0000U) /**< \brief (SMC ) Base Address */ +#define MATRIX (0x400E0400U) /**< \brief (MATRIX ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART (0x400E0800U) /**< \brief (UART ) Base Address */ +#define PDC_UART (0x400E0900U) /**< \brief (PDC_UART ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID ) Base Address */ +#define EFC0 (0x400E0A00U) /**< \brief (EFC0 ) Base Address */ +#define EFC1 (0x400E0C00U) /**< \brief (EFC1 ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1A00U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1A10U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1A30U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1A50U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1A60U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1A90U) /**< \brief (GPBR ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x40080000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40084000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40088000U) /**< \brief (TC2 ) Base Address */ +#define TWI0 ((Twi *)0x4008C000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 ((Pdc *)0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 ((Twi *)0x40090000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 ((Pdc *)0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM ((Pwm *)0x40094000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM ((Pdc *)0x40094100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 ((Usart *)0x40098000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 ((Pdc *)0x40098100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 ((Usart *)0x4009C000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 ((Pdc *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */ +#define USART2 ((Usart *)0x400A0000U) /**< \brief (USART2 ) Base Address */ +#define PDC_USART2 ((Pdc *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */ +#define USART3 ((Usart *)0x400A4000U) /**< \brief (USART3 ) Base Address */ +#define PDC_USART3 ((Pdc *)0x400A4100U) /**< \brief (PDC_USART3) Base Address */ +#define UOTGHS ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS ) Base Address */ +#define EMAC ((Emac *)0x400B0000U) /**< \brief (EMAC ) Base Address */ +#define CAN0 ((Can *)0x400B4000U) /**< \brief (CAN0 ) Base Address */ +#define CAN1 ((Can *)0x400B8000U) /**< \brief (CAN1 ) Base Address */ +#define TRNG ((Trng *)0x400BC000U) /**< \brief (TRNG ) Base Address */ +#define ADC ((Adc *)0x400C0000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC ((Pdc *)0x400C0100U) /**< \brief (PDC_ADC ) Base Address */ +#define DMAC ((Dmac *)0x400C4000U) /**< \brief (DMAC ) Base Address */ +#define DACC ((Dacc *)0x400C8000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC ((Pdc *)0x400C8100U) /**< \brief (PDC_DACC ) Base Address */ +#define SMC ((Smc *)0x400E0000U) /**< \brief (SMC ) Base Address */ +#define MATRIX ((Matrix *)0x400E0400U) /**< \brief (MATRIX ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART ((Uart *)0x400E0800U) /**< \brief (UART ) Base Address */ +#define PDC_UART ((Pdc *)0x400E0900U) /**< \brief (PDC_UART ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID ) Base Address */ +#define EFC0 ((Efc *)0x400E0A00U) /**< \brief (EFC0 ) Base Address */ +#define EFC1 ((Efc *)0x400E0C00U) /**< \brief (EFC1 ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1A00U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1A10U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1A30U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1A50U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1A60U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1A90U) /**< \brief (GPBR ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAM3X4E */ +/* ************************************************************************** */ +/** \addtogroup SAM3X4E_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_sam3x4e.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAM3X4E */ +/* ************************************************************************** */ + +#define IFLASH0_SIZE (0x20000u) +#define IFLASH0_PAGE_SIZE (256u) +#define IFLASH0_LOCK_REGION_SIZE (16384u) +#define IFLASH0_NB_OF_PAGES (512u) +#define IFLASH1_SIZE (0x20000u) +#define IFLASH1_PAGE_SIZE (256u) +#define IFLASH1_LOCK_REGION_SIZE (16384u) +#define IFLASH1_NB_OF_PAGES (512u) +#define IRAM0_SIZE (0x8000u) +#define IRAM1_SIZE (0x8000u) +#define NFCRAM_SIZE (0x1000u) +#define IFLASH_SIZE (IFLASH0_SIZE+IFLASH1_SIZE) +#define IRAM_SIZE (IRAM0_SIZE+IRAM1_SIZE) + +#define IFLASH0_ADDR (0x00080000u) /**< Internal Flash 0 base address */ +#if defined IFLASH0_SIZE +#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */ +#endif +#define IROM_ADDR (0x00100000u) /**< Internal ROM base address */ +#define IRAM0_ADDR (0x20000000u) /**< Internal RAM 0 base address */ +#define IRAM1_ADDR (0x20080000u) /**< Internal RAM 1 base address */ +#define NFC_RAM_ADDR (0x20100000u) /**< NAND Flash Controller RAM base address */ +#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define EBI_CS4_ADDR (0x64000000u) /**< EBI Chip Select 4 base address */ +#define EBI_CS5_ADDR (0x65000000u) /**< EBI Chip Select 5 base address */ +#define EBI_CS6_ADDR (0x66000000u) /**< EBI Chip Select 6 base address */ +#define EBI_CS7_ADDR (0x67000000u) /**< EBI Chip Select 7 base address */ + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAM3X4E */ +/* ************************************************************************** */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (84000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Write Wait State */ +#define CHIP_FLASH_WRITE_WAIT_STATE (6U) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.8V) */ +#define CHIP_FREQ_FWS_0 (19000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (50000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (64000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (90000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAM3X4E_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/sam3x8c.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/sam3x8c.h new file mode 100644 index 0000000..950b9af --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/sam3x8c.h @@ -0,0 +1,555 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3X8C_ +#define _SAM3X8C_ + +/** \addtogroup SAM3X8C_definitions SAM3X8C definitions + This file defines all structures and symbols for SAM3X8C: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAM3X8C */ +/* ************************************************************************** */ +/** \addtogroup SAM3X8C_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ +/****** SAM3X8C specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAM3X8C Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAM3X8C Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAM3X8C Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAM3X8C Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAM3X8C Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAM3X8C Power Management Controller (PMC) */ + EFC0_IRQn = 6, /**< 6 SAM3X8C Enhanced Flash Controller 0 (EFC0) */ + EFC1_IRQn = 7, /**< 7 SAM3X8C Enhanced Flash Controller 1 (EFC1) */ + UART_IRQn = 8, /**< 8 SAM3X8C Universal Asynchronous Receiver Transceiver (UART) */ + PIOA_IRQn = 11, /**< 11 SAM3X8C Parallel I/O Controller A, (PIOA) */ + PIOB_IRQn = 12, /**< 12 SAM3X8C Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 17, /**< 17 SAM3X8C USART 0 (USART0) */ + USART1_IRQn = 18, /**< 18 SAM3X8C USART 1 (USART1) */ + USART2_IRQn = 19, /**< 19 SAM3X8C USART 2 (USART2) */ + HSMCI_IRQn = 21, /**< 21 SAM3X8C Multimedia Card Interface (HSMCI) */ + TWI0_IRQn = 22, /**< 22 SAM3X8C Two-Wire Interface 0 (TWI0) */ + TWI1_IRQn = 23, /**< 23 SAM3X8C Two-Wire Interface 1 (TWI1) */ + SPI0_IRQn = 24, /**< 24 SAM3X8C Serial Peripheral Interface (SPI0) */ + SSC_IRQn = 26, /**< 26 SAM3X8C Synchronous Serial Controller (SSC) */ + TC0_IRQn = 27, /**< 27 SAM3X8C Timer Counter 0 (TC0) */ + TC1_IRQn = 28, /**< 28 SAM3X8C Timer Counter 1 (TC1) */ + TC2_IRQn = 29, /**< 29 SAM3X8C Timer Counter 2 (TC2) */ + TC3_IRQn = 30, /**< 30 SAM3X8C Timer Counter 3 (TC3) */ + TC4_IRQn = 31, /**< 31 SAM3X8C Timer Counter 4 (TC4) */ + TC5_IRQn = 32, /**< 32 SAM3X8C Timer Counter 5 (TC5) */ + PWM_IRQn = 36, /**< 36 SAM3X8C Pulse Width Modulation Controller (PWM) */ + ADC_IRQn = 37, /**< 37 SAM3X8C ADC Controller (ADC) */ + DACC_IRQn = 38, /**< 38 SAM3X8C DAC Controller (DACC) */ + DMAC_IRQn = 39, /**< 39 SAM3X8C DMA Controller (DMAC) */ + UOTGHS_IRQn = 40, /**< 40 SAM3X8C USB OTG High Speed (UOTGHS) */ + TRNG_IRQn = 41, /**< 41 SAM3X8C True Random Number Generator (TRNG) */ + EMAC_IRQn = 42, /**< 42 SAM3X8C Ethernet MAC (EMAC) */ + CAN0_IRQn = 43, /**< 43 SAM3X8C CAN Controller 0 (CAN0) */ + CAN1_IRQn = 44 /**< 44 SAM3X8C CAN Controller 1 (CAN1) */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC0_Handler; /* 6 Enhanced Flash Controller 0 */ + void* pfnEFC1_Handler; /* 7 Enhanced Flash Controller 1 */ + void* pfnUART_Handler; /* 8 Universal Asynchronous Receiver Transceiver */ + void* pvReserved9; + void* pvReserved10; + void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A, */ + void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */ + void* pvReserved13; + void* pvReserved14; + void* pvReserved15; + void* pvReserved16; + void* pfnUSART0_Handler; /* 17 USART 0 */ + void* pfnUSART1_Handler; /* 18 USART 1 */ + void* pfnUSART2_Handler; /* 19 USART 2 */ + void* pvReserved20; + void* pfnHSMCI_Handler; /* 21 Multimedia Card Interface */ + void* pfnTWI0_Handler; /* 22 Two-Wire Interface 0 */ + void* pfnTWI1_Handler; /* 23 Two-Wire Interface 1 */ + void* pfnSPI0_Handler; /* 24 Serial Peripheral Interface */ + void* pvReserved25; + void* pfnSSC_Handler; /* 26 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 27 Timer Counter 0 */ + void* pfnTC1_Handler; /* 28 Timer Counter 1 */ + void* pfnTC2_Handler; /* 29 Timer Counter 2 */ + void* pfnTC3_Handler; /* 30 Timer Counter 3 */ + void* pfnTC4_Handler; /* 31 Timer Counter 4 */ + void* pfnTC5_Handler; /* 32 Timer Counter 5 */ + void* pvReserved33; + void* pvReserved34; + void* pvReserved35; + void* pfnPWM_Handler; /* 36 Pulse Width Modulation Controller */ + void* pfnADC_Handler; /* 37 ADC Controller */ + void* pfnDACC_Handler; /* 38 DAC Controller */ + void* pfnDMAC_Handler; /* 39 DMA Controller */ + void* pfnUOTGHS_Handler; /* 40 USB OTG High Speed */ + void* pfnTRNG_Handler; /* 41 True Random Number Generator */ + void* pfnEMAC_Handler; /* 42 Ethernet MAC */ + void* pfnCAN0_Handler; /* 43 CAN Controller 0 */ + void* pfnCAN1_Handler; /* 44 CAN Controller 1 */ +} DeviceVectors; + +/* Cortex-M3 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ADC_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void DACC_Handler ( void ); +void DMAC_Handler ( void ); +void EFC0_Handler ( void ); +void EFC1_Handler ( void ); +void EMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PMC_Handler ( void ); +void PWM_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TRNG_Handler ( void ); +void TWI0_Handler ( void ); +void TWI1_Handler ( void ); +void UART_Handler ( void ); +void UOTGHS_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void WDT_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ + +#define __CM3_REV 0x0200 /**< SAM3X8C core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAM3X8C does provide a MPU */ +#define __NVIC_PRIO_BITS 4 /**< SAM3X8C uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sam3x.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3X8C */ +/* ************************************************************************** */ +/** \addtogroup SAM3X8C_api Peripheral Software API */ +/*@{*/ + +#include "component/component_adc.h" +#include "component/component_can.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_dmac.h" +#include "component/component_efc.h" +#include "component/component_emac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_matrix.h" +#include "component/component_pdc.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_rstc.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twi.h" +#include "component/component_uart.h" +#include "component/component_uotghs.h" +#include "component/component_usart.h" +#include "component/component_wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAM3X8C */ +/* ************************************************************************** */ +/** \addtogroup SAM3X8C_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_tc1.h" +#include "instance/instance_twi0.h" +#include "instance/instance_twi1.h" +#include "instance/instance_pwm.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_uotghs.h" +#include "instance/instance_emac.h" +#include "instance/instance_can0.h" +#include "instance/instance_can1.h" +#include "instance/instance_trng.h" +#include "instance/instance_adc.h" +#include "instance/instance_dmac.h" +#include "instance/instance_dacc.h" +#include "instance/instance_matrix.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart.h" +#include "instance/instance_chipid.h" +#include "instance/instance_efc0.h" +#include "instance/instance_efc1.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAM3X8C */ +/* ************************************************************************** */ +/** \addtogroup SAM3X8C_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC0 ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */ +#define ID_EFC1 ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */ +#define ID_UART ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */ +#define ID_PIOA (11) /**< \brief Parallel I/O Controller A, (PIOA) */ +#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (17) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (18) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (19) /**< \brief USART 2 (USART2) */ +#define ID_HSMCI (21) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWI0 (22) /**< \brief Two-Wire Interface 0 (TWI0) */ +#define ID_TWI1 (23) /**< \brief Two-Wire Interface 1 (TWI1) */ +#define ID_SPI0 (24) /**< \brief Serial Peripheral Interface (SPI0) */ +#define ID_SSC (26) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (27) /**< \brief Timer Counter 0 (TC0) */ +#define ID_TC1 (28) /**< \brief Timer Counter 1 (TC1) */ +#define ID_TC2 (29) /**< \brief Timer Counter 2 (TC2) */ +#define ID_TC3 (30) /**< \brief Timer Counter 3 (TC3) */ +#define ID_TC4 (31) /**< \brief Timer Counter 4 (TC4) */ +#define ID_TC5 (32) /**< \brief Timer Counter 5 (TC5) */ +#define ID_PWM (36) /**< \brief Pulse Width Modulation Controller (PWM) */ +#define ID_ADC (37) /**< \brief ADC Controller (ADC) */ +#define ID_DACC (38) /**< \brief DAC Controller (DACC) */ +#define ID_DMAC (39) /**< \brief DMA Controller (DMAC) */ +#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */ +#define ID_TRNG (41) /**< \brief True Random Number Generator (TRNG) */ +#define ID_EMAC (42) /**< \brief Ethernet MAC (EMAC) */ +#define ID_CAN0 (43) /**< \brief CAN Controller 0 (CAN0) */ +#define ID_CAN1 (44) /**< \brief CAN Controller 1 (CAN1) */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAM3X8C */ +/* ************************************************************************** */ +/** \addtogroup SAM3X8C_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x40080000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40084000U) /**< \brief (TC1 ) Base Address */ +#define TWI0 (0x4008C000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 (0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 (0x40090000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 (0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM (0x40094000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM (0x40094100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 (0x40098000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 (0x4009C000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */ +#define USART2 (0x400A0000U) /**< \brief (USART2 ) Base Address */ +#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */ +#define UOTGHS (0x400AC000U) /**< \brief (UOTGHS ) Base Address */ +#define EMAC (0x400B0000U) /**< \brief (EMAC ) Base Address */ +#define CAN0 (0x400B4000U) /**< \brief (CAN0 ) Base Address */ +#define CAN1 (0x400B8000U) /**< \brief (CAN1 ) Base Address */ +#define TRNG (0x400BC000U) /**< \brief (TRNG ) Base Address */ +#define ADC (0x400C0000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC (0x400C0100U) /**< \brief (PDC_ADC ) Base Address */ +#define DMAC (0x400C4000U) /**< \brief (DMAC ) Base Address */ +#define DACC (0x400C8000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC (0x400C8100U) /**< \brief (PDC_DACC ) Base Address */ +#define MATRIX (0x400E0400U) /**< \brief (MATRIX ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART (0x400E0800U) /**< \brief (UART ) Base Address */ +#define PDC_UART (0x400E0900U) /**< \brief (PDC_UART ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID ) Base Address */ +#define EFC0 (0x400E0A00U) /**< \brief (EFC0 ) Base Address */ +#define EFC1 (0x400E0C00U) /**< \brief (EFC1 ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define RSTC (0x400E1A00U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1A10U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1A30U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1A50U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1A60U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1A90U) /**< \brief (GPBR ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x40080000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40084000U) /**< \brief (TC1 ) Base Address */ +#define TWI0 ((Twi *)0x4008C000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 ((Pdc *)0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 ((Twi *)0x40090000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 ((Pdc *)0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM ((Pwm *)0x40094000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM ((Pdc *)0x40094100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 ((Usart *)0x40098000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 ((Pdc *)0x40098100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 ((Usart *)0x4009C000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 ((Pdc *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */ +#define USART2 ((Usart *)0x400A0000U) /**< \brief (USART2 ) Base Address */ +#define PDC_USART2 ((Pdc *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */ +#define UOTGHS ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS ) Base Address */ +#define EMAC ((Emac *)0x400B0000U) /**< \brief (EMAC ) Base Address */ +#define CAN0 ((Can *)0x400B4000U) /**< \brief (CAN0 ) Base Address */ +#define CAN1 ((Can *)0x400B8000U) /**< \brief (CAN1 ) Base Address */ +#define TRNG ((Trng *)0x400BC000U) /**< \brief (TRNG ) Base Address */ +#define ADC ((Adc *)0x400C0000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC ((Pdc *)0x400C0100U) /**< \brief (PDC_ADC ) Base Address */ +#define DMAC ((Dmac *)0x400C4000U) /**< \brief (DMAC ) Base Address */ +#define DACC ((Dacc *)0x400C8000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC ((Pdc *)0x400C8100U) /**< \brief (PDC_DACC ) Base Address */ +#define MATRIX ((Matrix *)0x400E0400U) /**< \brief (MATRIX ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART ((Uart *)0x400E0800U) /**< \brief (UART ) Base Address */ +#define PDC_UART ((Pdc *)0x400E0900U) /**< \brief (PDC_UART ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID ) Base Address */ +#define EFC0 ((Efc *)0x400E0A00U) /**< \brief (EFC0 ) Base Address */ +#define EFC1 ((Efc *)0x400E0C00U) /**< \brief (EFC1 ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define RSTC ((Rstc *)0x400E1A00U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1A10U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1A30U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1A50U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1A60U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1A90U) /**< \brief (GPBR ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAM3X8C */ +/* ************************************************************************** */ +/** \addtogroup SAM3X8C_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_sam3x8c.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAM3X8C */ +/* ************************************************************************** */ + +#define IFLASH0_SIZE (0x40000u) +#define IFLASH0_PAGE_SIZE (256u) +#define IFLASH0_LOCK_REGION_SIZE (16384u) +#define IFLASH0_NB_OF_PAGES (1024u) +#define IFLASH1_SIZE (0x40000u) +#define IFLASH1_PAGE_SIZE (256u) +#define IFLASH1_LOCK_REGION_SIZE (16384u) +#define IFLASH1_NB_OF_PAGES (1024u) +#define IRAM0_SIZE (0x10000u) +#define IRAM1_SIZE (0x8000u) +#define IFLASH_SIZE (IFLASH0_SIZE+IFLASH1_SIZE) +#define IRAM_SIZE (IRAM0_SIZE+IRAM1_SIZE) + +#define IFLASH0_ADDR (0x00080000u) /**< Internal Flash 0 base address */ +#if defined IFLASH0_SIZE +#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */ +#endif +#define IROM_ADDR (0x00100000u) /**< Internal ROM base address */ +#define IRAM0_ADDR (0x20000000u) /**< Internal RAM 0 base address */ +#define IRAM1_ADDR (0x20080000u) /**< Internal RAM 1 base address */ +#define NFC_RAM_ADDR (0x20100000u) /**< NAND Flash Controller RAM base address */ +#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define EBI_CS4_ADDR (0x64000000u) /**< EBI Chip Select 4 base address */ +#define EBI_CS5_ADDR (0x65000000u) /**< EBI Chip Select 5 base address */ +#define EBI_CS6_ADDR (0x66000000u) /**< EBI Chip Select 6 base address */ +#define EBI_CS7_ADDR (0x67000000u) /**< EBI Chip Select 7 base address */ + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAM3X8C */ +/* ************************************************************************** */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (84000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Write Wait State */ +#define CHIP_FLASH_WRITE_WAIT_STATE (6U) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.8V) */ +#define CHIP_FREQ_FWS_0 (19000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (50000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (64000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (90000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAM3X8C_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h new file mode 100644 index 0000000..8ad5f03 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/sam3x8e.h @@ -0,0 +1,594 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3X8E_ +#define _SAM3X8E_ + +/** \addtogroup SAM3X8E_definitions SAM3X8E definitions + This file defines all structures and symbols for SAM3X8E: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAM3X8E */ +/* ************************************************************************** */ +/** \addtogroup SAM3X8E_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ +/****** SAM3X8E specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAM3X8E Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAM3X8E Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAM3X8E Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAM3X8E Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAM3X8E Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAM3X8E Power Management Controller (PMC) */ + EFC0_IRQn = 6, /**< 6 SAM3X8E Enhanced Flash Controller 0 (EFC0) */ + EFC1_IRQn = 7, /**< 7 SAM3X8E Enhanced Flash Controller 1 (EFC1) */ + UART_IRQn = 8, /**< 8 SAM3X8E Universal Asynchronous Receiver Transceiver (UART) */ + SMC_IRQn = 9, /**< 9 SAM3X8E Static Memory Controller (SMC) */ + PIOA_IRQn = 11, /**< 11 SAM3X8E Parallel I/O Controller A, (PIOA) */ + PIOB_IRQn = 12, /**< 12 SAM3X8E Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 13, /**< 13 SAM3X8E Parallel I/O Controller C (PIOC) */ + PIOD_IRQn = 14, /**< 14 SAM3X8E Parallel I/O Controller D (PIOD) */ + USART0_IRQn = 17, /**< 17 SAM3X8E USART 0 (USART0) */ + USART1_IRQn = 18, /**< 18 SAM3X8E USART 1 (USART1) */ + USART2_IRQn = 19, /**< 19 SAM3X8E USART 2 (USART2) */ + USART3_IRQn = 20, /**< 20 SAM3X8E USART 3 (USART3) */ + HSMCI_IRQn = 21, /**< 21 SAM3X8E Multimedia Card Interface (HSMCI) */ + TWI0_IRQn = 22, /**< 22 SAM3X8E Two-Wire Interface 0 (TWI0) */ + TWI1_IRQn = 23, /**< 23 SAM3X8E Two-Wire Interface 1 (TWI1) */ + SPI0_IRQn = 24, /**< 24 SAM3X8E Serial Peripheral Interface (SPI0) */ + SSC_IRQn = 26, /**< 26 SAM3X8E Synchronous Serial Controller (SSC) */ + TC0_IRQn = 27, /**< 27 SAM3X8E Timer Counter 0 (TC0) */ + TC1_IRQn = 28, /**< 28 SAM3X8E Timer Counter 1 (TC1) */ + TC2_IRQn = 29, /**< 29 SAM3X8E Timer Counter 2 (TC2) */ + TC3_IRQn = 30, /**< 30 SAM3X8E Timer Counter 3 (TC3) */ + TC4_IRQn = 31, /**< 31 SAM3X8E Timer Counter 4 (TC4) */ + TC5_IRQn = 32, /**< 32 SAM3X8E Timer Counter 5 (TC5) */ + TC6_IRQn = 33, /**< 33 SAM3X8E Timer Counter 6 (TC6) */ + TC7_IRQn = 34, /**< 34 SAM3X8E Timer Counter 7 (TC7) */ + TC8_IRQn = 35, /**< 35 SAM3X8E Timer Counter 8 (TC8) */ + PWM_IRQn = 36, /**< 36 SAM3X8E Pulse Width Modulation Controller (PWM) */ + ADC_IRQn = 37, /**< 37 SAM3X8E ADC Controller (ADC) */ + DACC_IRQn = 38, /**< 38 SAM3X8E DAC Controller (DACC) */ + DMAC_IRQn = 39, /**< 39 SAM3X8E DMA Controller (DMAC) */ + UOTGHS_IRQn = 40, /**< 40 SAM3X8E USB OTG High Speed (UOTGHS) */ + TRNG_IRQn = 41, /**< 41 SAM3X8E True Random Number Generator (TRNG) */ + EMAC_IRQn = 42, /**< 42 SAM3X8E Ethernet MAC (EMAC) */ + CAN0_IRQn = 43, /**< 43 SAM3X8E CAN Controller 0 (CAN0) */ + CAN1_IRQn = 44 /**< 44 SAM3X8E CAN Controller 1 (CAN1) */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC0_Handler; /* 6 Enhanced Flash Controller 0 */ + void* pfnEFC1_Handler; /* 7 Enhanced Flash Controller 1 */ + void* pfnUART_Handler; /* 8 Universal Asynchronous Receiver Transceiver */ + void* pfnSMC_Handler; /* 9 Static Memory Controller */ + void* pvReserved10; + void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A, */ + void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 13 Parallel I/O Controller C */ + void* pfnPIOD_Handler; /* 14 Parallel I/O Controller D */ + void* pvReserved15; + void* pvReserved16; + void* pfnUSART0_Handler; /* 17 USART 0 */ + void* pfnUSART1_Handler; /* 18 USART 1 */ + void* pfnUSART2_Handler; /* 19 USART 2 */ + void* pfnUSART3_Handler; /* 20 USART 3 */ + void* pfnHSMCI_Handler; /* 21 Multimedia Card Interface */ + void* pfnTWI0_Handler; /* 22 Two-Wire Interface 0 */ + void* pfnTWI1_Handler; /* 23 Two-Wire Interface 1 */ + void* pfnSPI0_Handler; /* 24 Serial Peripheral Interface */ + void* pvReserved25; + void* pfnSSC_Handler; /* 26 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 27 Timer Counter 0 */ + void* pfnTC1_Handler; /* 28 Timer Counter 1 */ + void* pfnTC2_Handler; /* 29 Timer Counter 2 */ + void* pfnTC3_Handler; /* 30 Timer Counter 3 */ + void* pfnTC4_Handler; /* 31 Timer Counter 4 */ + void* pfnTC5_Handler; /* 32 Timer Counter 5 */ + void* pfnTC6_Handler; /* 33 Timer Counter 6 */ + void* pfnTC7_Handler; /* 34 Timer Counter 7 */ + void* pfnTC8_Handler; /* 35 Timer Counter 8 */ + void* pfnPWM_Handler; /* 36 Pulse Width Modulation Controller */ + void* pfnADC_Handler; /* 37 ADC Controller */ + void* pfnDACC_Handler; /* 38 DAC Controller */ + void* pfnDMAC_Handler; /* 39 DMA Controller */ + void* pfnUOTGHS_Handler; /* 40 USB OTG High Speed */ + void* pfnTRNG_Handler; /* 41 True Random Number Generator */ + void* pfnEMAC_Handler; /* 42 Ethernet MAC */ + void* pfnCAN0_Handler; /* 43 CAN Controller 0 */ + void* pfnCAN1_Handler; /* 44 CAN Controller 1 */ +} DeviceVectors; + +/* Cortex-M3 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ADC_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void DACC_Handler ( void ); +void DMAC_Handler ( void ); +void EFC0_Handler ( void ); +void EFC1_Handler ( void ); +void EMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SMC_Handler ( void ); +void SPI0_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TRNG_Handler ( void ); +void TWI0_Handler ( void ); +void TWI1_Handler ( void ); +void UART_Handler ( void ); +void UOTGHS_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USART3_Handler ( void ); +void WDT_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ + +#define __CM3_REV 0x0200 /**< SAM3X8E core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAM3X8E does provide a MPU */ +#define __NVIC_PRIO_BITS 4 /**< SAM3X8E uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sam3x.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3X8E */ +/* ************************************************************************** */ +/** \addtogroup SAM3X8E_api Peripheral Software API */ +/*@{*/ + +#include "component/component_adc.h" +#include "component/component_can.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_dmac.h" +#include "component/component_efc.h" +#include "component/component_emac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_matrix.h" +#include "component/component_pdc.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_rstc.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_smc.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twi.h" +#include "component/component_uart.h" +#include "component/component_uotghs.h" +#include "component/component_usart.h" +#include "component/component_wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAM3X8E */ +/* ************************************************************************** */ +/** \addtogroup SAM3X8E_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_tc1.h" +#include "instance/instance_tc2.h" +#include "instance/instance_twi0.h" +#include "instance/instance_twi1.h" +#include "instance/instance_pwm.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_usart3.h" +#include "instance/instance_uotghs.h" +#include "instance/instance_emac.h" +#include "instance/instance_can0.h" +#include "instance/instance_can1.h" +#include "instance/instance_trng.h" +#include "instance/instance_adc.h" +#include "instance/instance_dmac.h" +#include "instance/instance_dacc.h" +#include "instance/instance_smc.h" +#include "instance/instance_matrix.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart.h" +#include "instance/instance_chipid.h" +#include "instance/instance_efc0.h" +#include "instance/instance_efc1.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_pioc.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAM3X8E */ +/* ************************************************************************** */ +/** \addtogroup SAM3X8E_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC0 ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */ +#define ID_EFC1 ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */ +#define ID_UART ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (11) /**< \brief Parallel I/O Controller A, (PIOA) */ +#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_PIOD (14) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_USART0 (17) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (18) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (19) /**< \brief USART 2 (USART2) */ +#define ID_USART3 (20) /**< \brief USART 3 (USART3) */ +#define ID_HSMCI (21) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWI0 (22) /**< \brief Two-Wire Interface 0 (TWI0) */ +#define ID_TWI1 (23) /**< \brief Two-Wire Interface 1 (TWI1) */ +#define ID_SPI0 (24) /**< \brief Serial Peripheral Interface (SPI0) */ +#define ID_SSC (26) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (27) /**< \brief Timer Counter 0 (TC0) */ +#define ID_TC1 (28) /**< \brief Timer Counter 1 (TC1) */ +#define ID_TC2 (29) /**< \brief Timer Counter 2 (TC2) */ +#define ID_TC3 (30) /**< \brief Timer Counter 3 (TC3) */ +#define ID_TC4 (31) /**< \brief Timer Counter 4 (TC4) */ +#define ID_TC5 (32) /**< \brief Timer Counter 5 (TC5) */ +#define ID_TC6 (33) /**< \brief Timer Counter 6 (TC6) */ +#define ID_TC7 (34) /**< \brief Timer Counter 7 (TC7) */ +#define ID_TC8 (35) /**< \brief Timer Counter 8 (TC8) */ +#define ID_PWM (36) /**< \brief Pulse Width Modulation Controller (PWM) */ +#define ID_ADC (37) /**< \brief ADC Controller (ADC) */ +#define ID_DACC (38) /**< \brief DAC Controller (DACC) */ +#define ID_DMAC (39) /**< \brief DMA Controller (DMAC) */ +#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */ +#define ID_TRNG (41) /**< \brief True Random Number Generator (TRNG) */ +#define ID_EMAC (42) /**< \brief Ethernet MAC (EMAC) */ +#define ID_CAN0 (43) /**< \brief CAN Controller 0 (CAN0) */ +#define ID_CAN1 (44) /**< \brief CAN Controller 1 (CAN1) */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAM3X8E */ +/* ************************************************************************** */ +/** \addtogroup SAM3X8E_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x40080000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40084000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40088000U) /**< \brief (TC2 ) Base Address */ +#define TWI0 (0x4008C000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 (0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 (0x40090000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 (0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM (0x40094000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM (0x40094100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 (0x40098000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 (0x4009C000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */ +#define USART2 (0x400A0000U) /**< \brief (USART2 ) Base Address */ +#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */ +#define USART3 (0x400A4000U) /**< \brief (USART3 ) Base Address */ +#define PDC_USART3 (0x400A4100U) /**< \brief (PDC_USART3) Base Address */ +#define UOTGHS (0x400AC000U) /**< \brief (UOTGHS ) Base Address */ +#define EMAC (0x400B0000U) /**< \brief (EMAC ) Base Address */ +#define CAN0 (0x400B4000U) /**< \brief (CAN0 ) Base Address */ +#define CAN1 (0x400B8000U) /**< \brief (CAN1 ) Base Address */ +#define TRNG (0x400BC000U) /**< \brief (TRNG ) Base Address */ +#define ADC (0x400C0000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC (0x400C0100U) /**< \brief (PDC_ADC ) Base Address */ +#define DMAC (0x400C4000U) /**< \brief (DMAC ) Base Address */ +#define DACC (0x400C8000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC (0x400C8100U) /**< \brief (PDC_DACC ) Base Address */ +#define SMC (0x400E0000U) /**< \brief (SMC ) Base Address */ +#define MATRIX (0x400E0400U) /**< \brief (MATRIX ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART (0x400E0800U) /**< \brief (UART ) Base Address */ +#define PDC_UART (0x400E0900U) /**< \brief (PDC_UART ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID ) Base Address */ +#define EFC0 (0x400E0A00U) /**< \brief (EFC0 ) Base Address */ +#define EFC1 (0x400E0C00U) /**< \brief (EFC1 ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1A00U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1A10U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1A30U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1A50U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1A60U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1A90U) /**< \brief (GPBR ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x40080000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40084000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40088000U) /**< \brief (TC2 ) Base Address */ +#define TWI0 ((Twi *)0x4008C000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 ((Pdc *)0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 ((Twi *)0x40090000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 ((Pdc *)0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM ((Pwm *)0x40094000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM ((Pdc *)0x40094100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 ((Usart *)0x40098000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 ((Pdc *)0x40098100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 ((Usart *)0x4009C000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 ((Pdc *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */ +#define USART2 ((Usart *)0x400A0000U) /**< \brief (USART2 ) Base Address */ +#define PDC_USART2 ((Pdc *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */ +#define USART3 ((Usart *)0x400A4000U) /**< \brief (USART3 ) Base Address */ +#define PDC_USART3 ((Pdc *)0x400A4100U) /**< \brief (PDC_USART3) Base Address */ +#define UOTGHS ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS ) Base Address */ +#define EMAC ((Emac *)0x400B0000U) /**< \brief (EMAC ) Base Address */ +#define CAN0 ((Can *)0x400B4000U) /**< \brief (CAN0 ) Base Address */ +#define CAN1 ((Can *)0x400B8000U) /**< \brief (CAN1 ) Base Address */ +#define TRNG ((Trng *)0x400BC000U) /**< \brief (TRNG ) Base Address */ +#define ADC ((Adc *)0x400C0000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC ((Pdc *)0x400C0100U) /**< \brief (PDC_ADC ) Base Address */ +#define DMAC ((Dmac *)0x400C4000U) /**< \brief (DMAC ) Base Address */ +#define DACC ((Dacc *)0x400C8000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC ((Pdc *)0x400C8100U) /**< \brief (PDC_DACC ) Base Address */ +#define SMC ((Smc *)0x400E0000U) /**< \brief (SMC ) Base Address */ +#define MATRIX ((Matrix *)0x400E0400U) /**< \brief (MATRIX ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART ((Uart *)0x400E0800U) /**< \brief (UART ) Base Address */ +#define PDC_UART ((Pdc *)0x400E0900U) /**< \brief (PDC_UART ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID ) Base Address */ +#define EFC0 ((Efc *)0x400E0A00U) /**< \brief (EFC0 ) Base Address */ +#define EFC1 ((Efc *)0x400E0C00U) /**< \brief (EFC1 ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1A00U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1A10U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1A30U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1A50U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1A60U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1A90U) /**< \brief (GPBR ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAM3X8E */ +/* ************************************************************************** */ +/** \addtogroup SAM3X8E_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_sam3x8e.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAM3X8E */ +/* ************************************************************************** */ + +#define IFLASH0_SIZE (0x40000u) +#define IFLASH0_PAGE_SIZE (256u) +#define IFLASH0_LOCK_REGION_SIZE (16384u) +#define IFLASH0_NB_OF_PAGES (1024u) +#define IFLASH1_SIZE (0x40000u) +#define IFLASH1_PAGE_SIZE (256u) +#define IFLASH1_LOCK_REGION_SIZE (16384u) +#define IFLASH1_NB_OF_PAGES (1024u) +#define IRAM0_SIZE (0x10000u) +#define IRAM1_SIZE (0x8000u) +#define NFCRAM_SIZE (0x1000u) +#define IFLASH_SIZE (IFLASH0_SIZE+IFLASH1_SIZE) +#define IRAM_SIZE (IRAM0_SIZE+IRAM1_SIZE) + +#define IFLASH0_ADDR (0x00080000u) /**< Internal Flash 0 base address */ +#if defined IFLASH0_SIZE +#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */ +#endif +#define IROM_ADDR (0x00100000u) /**< Internal ROM base address */ +#define IRAM0_ADDR (0x20000000u) /**< Internal RAM 0 base address */ +#define IRAM1_ADDR (0x20080000u) /**< Internal RAM 1 base address */ +#define NFC_RAM_ADDR (0x20100000u) /**< NAND Flash Controller RAM base address */ +#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define EBI_CS4_ADDR (0x64000000u) /**< EBI Chip Select 4 base address */ +#define EBI_CS5_ADDR (0x65000000u) /**< EBI Chip Select 5 base address */ +#define EBI_CS6_ADDR (0x66000000u) /**< EBI Chip Select 6 base address */ +#define EBI_CS7_ADDR (0x67000000u) /**< EBI Chip Select 7 base address */ + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAM3X8E */ +/* ************************************************************************** */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (84000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Write Wait State */ +#define CHIP_FLASH_WRITE_WAIT_STATE (6U) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.8V) */ +#define CHIP_FREQ_FWS_0 (19000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (50000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (64000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (90000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAM3X8E_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/sam3x8h.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/sam3x8h.h new file mode 100644 index 0000000..3e37425 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/sam3x8h.h @@ -0,0 +1,619 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3X8H_ +#define _SAM3X8H_ + +/** \addtogroup SAM3X8H_definitions SAM3X8H definitions + This file defines all structures and symbols for SAM3X8H: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAM3X8H */ +/* ************************************************************************** */ +/** \addtogroup SAM3X8H_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ +/****** SAM3X8H specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAM3X8H Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAM3X8H Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAM3X8H Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAM3X8H Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAM3X8H Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAM3X8H Power Management Controller (PMC) */ + EFC0_IRQn = 6, /**< 6 SAM3X8H Enhanced Flash Controller 0 (EFC0) */ + EFC1_IRQn = 7, /**< 7 SAM3X8H Enhanced Flash Controller 1 (EFC1) */ + UART_IRQn = 8, /**< 8 SAM3X8H Universal Asynchronous Receiver Transceiver (UART) */ + SMC_IRQn = 9, /**< 9 SAM3X8H Static Memory Controller (SMC) */ + SDRAMC_IRQn = 10, /**< 10 SAM3X8H Synchronous Dynamic RAM Controller (SDRAMC) */ + PIOA_IRQn = 11, /**< 11 SAM3X8H Parallel I/O Controller A, (PIOA) */ + PIOB_IRQn = 12, /**< 12 SAM3X8H Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 13, /**< 13 SAM3X8H Parallel I/O Controller C (PIOC) */ + PIOD_IRQn = 14, /**< 14 SAM3X8H Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 15, /**< 15 SAM3X8H Parallel I/O Controller E (PIOE) */ + PIOF_IRQn = 16, /**< 16 SAM3X8H Parallel I/O Controller F (PIOF) */ + USART0_IRQn = 17, /**< 17 SAM3X8H USART 0 (USART0) */ + USART1_IRQn = 18, /**< 18 SAM3X8H USART 1 (USART1) */ + USART2_IRQn = 19, /**< 19 SAM3X8H USART 2 (USART2) */ + USART3_IRQn = 20, /**< 20 SAM3X8H USART 3 (USART3) */ + HSMCI_IRQn = 21, /**< 21 SAM3X8H Multimedia Card Interface (HSMCI) */ + TWI0_IRQn = 22, /**< 22 SAM3X8H Two-Wire Interface 0 (TWI0) */ + TWI1_IRQn = 23, /**< 23 SAM3X8H Two-Wire Interface 1 (TWI1) */ + SPI0_IRQn = 24, /**< 24 SAM3X8H Serial Peripheral Interface (SPI0) */ + SPI1_IRQn = 25, /**< 25 SAM3X8H Serial Peripheral Interface (SPI1) */ + SSC_IRQn = 26, /**< 26 SAM3X8H Synchronous Serial Controller (SSC) */ + TC0_IRQn = 27, /**< 27 SAM3X8H Timer Counter 0 (TC0) */ + TC1_IRQn = 28, /**< 28 SAM3X8H Timer Counter 1 (TC1) */ + TC2_IRQn = 29, /**< 29 SAM3X8H Timer Counter 2 (TC2) */ + TC3_IRQn = 30, /**< 30 SAM3X8H Timer Counter 3 (TC3) */ + TC4_IRQn = 31, /**< 31 SAM3X8H Timer Counter 4 (TC4) */ + TC5_IRQn = 32, /**< 32 SAM3X8H Timer Counter 5 (TC5) */ + TC6_IRQn = 33, /**< 33 SAM3X8H Timer Counter 6 (TC6) */ + TC7_IRQn = 34, /**< 34 SAM3X8H Timer Counter 7 (TC7) */ + TC8_IRQn = 35, /**< 35 SAM3X8H Timer Counter 8 (TC8) */ + PWM_IRQn = 36, /**< 36 SAM3X8H Pulse Width Modulation Controller (PWM) */ + ADC_IRQn = 37, /**< 37 SAM3X8H ADC Controller (ADC) */ + DACC_IRQn = 38, /**< 38 SAM3X8H DAC Controller (DACC) */ + DMAC_IRQn = 39, /**< 39 SAM3X8H DMA Controller (DMAC) */ + UOTGHS_IRQn = 40, /**< 40 SAM3X8H USB OTG High Speed (UOTGHS) */ + TRNG_IRQn = 41, /**< 41 SAM3X8H True Random Number Generator (TRNG) */ + EMAC_IRQn = 42, /**< 42 SAM3X8H Ethernet MAC (EMAC) */ + CAN0_IRQn = 43, /**< 43 SAM3X8H CAN Controller 0 (CAN0) */ + CAN1_IRQn = 44 /**< 44 SAM3X8H CAN Controller 1 (CAN1) */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC0_Handler; /* 6 Enhanced Flash Controller 0 */ + void* pfnEFC1_Handler; /* 7 Enhanced Flash Controller 1 */ + void* pfnUART_Handler; /* 8 Universal Asynchronous Receiver Transceiver */ + void* pfnSMC_Handler; /* 9 Static Memory Controller */ + void* pfnSDRAMC_Handler; /* 10 Synchronous Dynamic RAM Controller */ + void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A, */ + void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 13 Parallel I/O Controller C */ + void* pfnPIOD_Handler; /* 14 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 15 Parallel I/O Controller E */ + void* pfnPIOF_Handler; /* 16 Parallel I/O Controller F */ + void* pfnUSART0_Handler; /* 17 USART 0 */ + void* pfnUSART1_Handler; /* 18 USART 1 */ + void* pfnUSART2_Handler; /* 19 USART 2 */ + void* pfnUSART3_Handler; /* 20 USART 3 */ + void* pfnHSMCI_Handler; /* 21 Multimedia Card Interface */ + void* pfnTWI0_Handler; /* 22 Two-Wire Interface 0 */ + void* pfnTWI1_Handler; /* 23 Two-Wire Interface 1 */ + void* pfnSPI0_Handler; /* 24 Serial Peripheral Interface */ + void* pfnSPI1_Handler; /* 25 Serial Peripheral Interface */ + void* pfnSSC_Handler; /* 26 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 27 Timer Counter 0 */ + void* pfnTC1_Handler; /* 28 Timer Counter 1 */ + void* pfnTC2_Handler; /* 29 Timer Counter 2 */ + void* pfnTC3_Handler; /* 30 Timer Counter 3 */ + void* pfnTC4_Handler; /* 31 Timer Counter 4 */ + void* pfnTC5_Handler; /* 32 Timer Counter 5 */ + void* pfnTC6_Handler; /* 33 Timer Counter 6 */ + void* pfnTC7_Handler; /* 34 Timer Counter 7 */ + void* pfnTC8_Handler; /* 35 Timer Counter 8 */ + void* pfnPWM_Handler; /* 36 Pulse Width Modulation Controller */ + void* pfnADC_Handler; /* 37 ADC Controller */ + void* pfnDACC_Handler; /* 38 DAC Controller */ + void* pfnDMAC_Handler; /* 39 DMA Controller */ + void* pfnUOTGHS_Handler; /* 40 USB OTG High Speed */ + void* pfnTRNG_Handler; /* 41 True Random Number Generator */ + void* pfnEMAC_Handler; /* 42 Ethernet MAC */ + void* pfnCAN0_Handler; /* 43 CAN Controller 0 */ + void* pfnCAN1_Handler; /* 44 CAN Controller 1 */ +} DeviceVectors; + +/* Cortex-M3 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ADC_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void DACC_Handler ( void ); +void DMAC_Handler ( void ); +void EFC0_Handler ( void ); +void EFC1_Handler ( void ); +void EMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PIOF_Handler ( void ); +void PMC_Handler ( void ); +void PWM_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TRNG_Handler ( void ); +void TWI0_Handler ( void ); +void TWI1_Handler ( void ); +void UART_Handler ( void ); +void UOTGHS_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USART3_Handler ( void ); +void WDT_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ + +#define __CM3_REV 0x0200 /**< SAM3X8H core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAM3X8H does provide a MPU */ +#define __NVIC_PRIO_BITS 4 /**< SAM3X8H uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sam3x.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3X8H */ +/* ************************************************************************** */ +/** \addtogroup SAM3X8H_api Peripheral Software API */ +/*@{*/ + +#include "component/component_adc.h" +#include "component/component_can.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_dmac.h" +#include "component/component_efc.h" +#include "component/component_emac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_matrix.h" +#include "component/component_pdc.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_rstc.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_sdramc.h" +#include "component/component_smc.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twi.h" +#include "component/component_uart.h" +#include "component/component_uotghs.h" +#include "component/component_usart.h" +#include "component/component_wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAM3X8H */ +/* ************************************************************************** */ +/** \addtogroup SAM3X8H_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_spi1.h" +#include "instance/instance_tc0.h" +#include "instance/instance_tc1.h" +#include "instance/instance_tc2.h" +#include "instance/instance_twi0.h" +#include "instance/instance_twi1.h" +#include "instance/instance_pwm.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_usart3.h" +#include "instance/instance_uotghs.h" +#include "instance/instance_emac.h" +#include "instance/instance_can0.h" +#include "instance/instance_can1.h" +#include "instance/instance_trng.h" +#include "instance/instance_adc.h" +#include "instance/instance_dmac.h" +#include "instance/instance_dacc.h" +#include "instance/instance_smc.h" +#include "instance/instance_sdramc.h" +#include "instance/instance_matrix.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart.h" +#include "instance/instance_chipid.h" +#include "instance/instance_efc0.h" +#include "instance/instance_efc1.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_pioc.h" +#include "instance/instance_piod.h" +#include "instance/instance_pioe.h" +#include "instance/instance_piof.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAM3X8H */ +/* ************************************************************************** */ +/** \addtogroup SAM3X8H_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC0 ( 6) /**< \brief Enhanced Flash Controller 0 (EFC0) */ +#define ID_EFC1 ( 7) /**< \brief Enhanced Flash Controller 1 (EFC1) */ +#define ID_UART ( 8) /**< \brief Universal Asynchronous Receiver Transceiver (UART) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_SDRAMC (10) /**< \brief Synchronous Dynamic RAM Controller (SDRAMC) */ +#define ID_PIOA (11) /**< \brief Parallel I/O Controller A, (PIOA) */ +#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_PIOD (14) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (15) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_PIOF (16) /**< \brief Parallel I/O Controller F (PIOF) */ +#define ID_USART0 (17) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (18) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (19) /**< \brief USART 2 (USART2) */ +#define ID_USART3 (20) /**< \brief USART 3 (USART3) */ +#define ID_HSMCI (21) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWI0 (22) /**< \brief Two-Wire Interface 0 (TWI0) */ +#define ID_TWI1 (23) /**< \brief Two-Wire Interface 1 (TWI1) */ +#define ID_SPI0 (24) /**< \brief Serial Peripheral Interface (SPI0) */ +#define ID_SPI1 (25) /**< \brief Serial Peripheral Interface (SPI1) */ +#define ID_SSC (26) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (27) /**< \brief Timer Counter 0 (TC0) */ +#define ID_TC1 (28) /**< \brief Timer Counter 1 (TC1) */ +#define ID_TC2 (29) /**< \brief Timer Counter 2 (TC2) */ +#define ID_TC3 (30) /**< \brief Timer Counter 3 (TC3) */ +#define ID_TC4 (31) /**< \brief Timer Counter 4 (TC4) */ +#define ID_TC5 (32) /**< \brief Timer Counter 5 (TC5) */ +#define ID_TC6 (33) /**< \brief Timer Counter 6 (TC6) */ +#define ID_TC7 (34) /**< \brief Timer Counter 7 (TC7) */ +#define ID_TC8 (35) /**< \brief Timer Counter 8 (TC8) */ +#define ID_PWM (36) /**< \brief Pulse Width Modulation Controller (PWM) */ +#define ID_ADC (37) /**< \brief ADC Controller (ADC) */ +#define ID_DACC (38) /**< \brief DAC Controller (DACC) */ +#define ID_DMAC (39) /**< \brief DMA Controller (DMAC) */ +#define ID_UOTGHS (40) /**< \brief USB OTG High Speed (UOTGHS) */ +#define ID_TRNG (41) /**< \brief True Random Number Generator (TRNG) */ +#define ID_EMAC (42) /**< \brief Ethernet MAC (EMAC) */ +#define ID_CAN0 (43) /**< \brief CAN Controller 0 (CAN0) */ +#define ID_CAN1 (44) /**< \brief CAN Controller 1 (CAN1) */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAM3X8H */ +/* ************************************************************************** */ +/** \addtogroup SAM3X8H_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define SPI1 (0x4000C000U) /**< \brief (SPI1 ) Base Address */ +#define TC0 (0x40080000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40084000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40088000U) /**< \brief (TC2 ) Base Address */ +#define TWI0 (0x4008C000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 (0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 (0x40090000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 (0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM (0x40094000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM (0x40094100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 (0x40098000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 (0x40098100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 (0x4009C000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 (0x4009C100U) /**< \brief (PDC_USART1) Base Address */ +#define USART2 (0x400A0000U) /**< \brief (USART2 ) Base Address */ +#define PDC_USART2 (0x400A0100U) /**< \brief (PDC_USART2) Base Address */ +#define USART3 (0x400A4000U) /**< \brief (USART3 ) Base Address */ +#define PDC_USART3 (0x400A4100U) /**< \brief (PDC_USART3) Base Address */ +#define UOTGHS (0x400AC000U) /**< \brief (UOTGHS ) Base Address */ +#define EMAC (0x400B0000U) /**< \brief (EMAC ) Base Address */ +#define CAN0 (0x400B4000U) /**< \brief (CAN0 ) Base Address */ +#define CAN1 (0x400B8000U) /**< \brief (CAN1 ) Base Address */ +#define TRNG (0x400BC000U) /**< \brief (TRNG ) Base Address */ +#define ADC (0x400C0000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC (0x400C0100U) /**< \brief (PDC_ADC ) Base Address */ +#define DMAC (0x400C4000U) /**< \brief (DMAC ) Base Address */ +#define DACC (0x400C8000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC (0x400C8100U) /**< \brief (PDC_DACC ) Base Address */ +#define SMC (0x400E0000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x400E0200U) /**< \brief (SDRAMC ) Base Address */ +#define MATRIX (0x400E0400U) /**< \brief (MATRIX ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART (0x400E0800U) /**< \brief (UART ) Base Address */ +#define PDC_UART (0x400E0900U) /**< \brief (PDC_UART ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID ) Base Address */ +#define EFC0 (0x400E0A00U) /**< \brief (EFC0 ) Base Address */ +#define EFC1 (0x400E0C00U) /**< \brief (EFC1 ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define PIOF (0x400E1800U) /**< \brief (PIOF ) Base Address */ +#define RSTC (0x400E1A00U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1A10U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1A30U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1A50U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1A60U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1A90U) /**< \brief (GPBR ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define SPI1 ((Spi *)0x4000C000U) /**< \brief (SPI1 ) Base Address */ +#define TC0 ((Tc *)0x40080000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40084000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40088000U) /**< \brief (TC2 ) Base Address */ +#define TWI0 ((Twi *)0x4008C000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 ((Pdc *)0x4008C100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 ((Twi *)0x40090000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 ((Pdc *)0x40090100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM ((Pwm *)0x40094000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM ((Pdc *)0x40094100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 ((Usart *)0x40098000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 ((Pdc *)0x40098100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 ((Usart *)0x4009C000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 ((Pdc *)0x4009C100U) /**< \brief (PDC_USART1) Base Address */ +#define USART2 ((Usart *)0x400A0000U) /**< \brief (USART2 ) Base Address */ +#define PDC_USART2 ((Pdc *)0x400A0100U) /**< \brief (PDC_USART2) Base Address */ +#define USART3 ((Usart *)0x400A4000U) /**< \brief (USART3 ) Base Address */ +#define PDC_USART3 ((Pdc *)0x400A4100U) /**< \brief (PDC_USART3) Base Address */ +#define UOTGHS ((Uotghs *)0x400AC000U) /**< \brief (UOTGHS ) Base Address */ +#define EMAC ((Emac *)0x400B0000U) /**< \brief (EMAC ) Base Address */ +#define CAN0 ((Can *)0x400B4000U) /**< \brief (CAN0 ) Base Address */ +#define CAN1 ((Can *)0x400B8000U) /**< \brief (CAN1 ) Base Address */ +#define TRNG ((Trng *)0x400BC000U) /**< \brief (TRNG ) Base Address */ +#define ADC ((Adc *)0x400C0000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC ((Pdc *)0x400C0100U) /**< \brief (PDC_ADC ) Base Address */ +#define DMAC ((Dmac *)0x400C4000U) /**< \brief (DMAC ) Base Address */ +#define DACC ((Dacc *)0x400C8000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC ((Pdc *)0x400C8100U) /**< \brief (PDC_DACC ) Base Address */ +#define SMC ((Smc *)0x400E0000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x400E0200U) /**< \brief (SDRAMC ) Base Address */ +#define MATRIX ((Matrix *)0x400E0400U) /**< \brief (MATRIX ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART ((Uart *)0x400E0800U) /**< \brief (UART ) Base Address */ +#define PDC_UART ((Pdc *)0x400E0900U) /**< \brief (PDC_UART ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID ) Base Address */ +#define EFC0 ((Efc *)0x400E0A00U) /**< \brief (EFC0 ) Base Address */ +#define EFC1 ((Efc *)0x400E0C00U) /**< \brief (EFC1 ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define PIOF ((Pio *)0x400E1800U) /**< \brief (PIOF ) Base Address */ +#define RSTC ((Rstc *)0x400E1A00U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1A10U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1A30U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1A50U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1A60U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1A90U) /**< \brief (GPBR ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAM3X8H */ +/* ************************************************************************** */ +/** \addtogroup SAM3X8H_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_sam3x8h.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAM3X8H */ +/* ************************************************************************** */ + +#define IFLASH0_SIZE (0x40000u) +#define IFLASH0_PAGE_SIZE (256u) +#define IFLASH0_LOCK_REGION_SIZE (16384u) +#define IFLASH0_NB_OF_PAGES (1024u) +#define IFLASH1_SIZE (0x40000u) +#define IFLASH1_PAGE_SIZE (256u) +#define IFLASH1_LOCK_REGION_SIZE (16384u) +#define IFLASH1_NB_OF_PAGES (1024u) +#define IRAM0_SIZE (0x10000u) +#define IRAM1_SIZE (0x8000u) +#define NFCRAM_SIZE (0x1000u) +#define IFLASH_SIZE (IFLASH0_SIZE+IFLASH1_SIZE) +#define IRAM_SIZE (IRAM0_SIZE+IRAM1_SIZE) + +#define IFLASH0_ADDR (0x00080000u) /**< Internal Flash 0 base address */ +#if defined IFLASH0_SIZE +#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */ +#endif +#define IROM_ADDR (0x00100000u) /**< Internal ROM base address */ +#define IRAM0_ADDR (0x20000000u) /**< Internal RAM 0 base address */ +#define IRAM1_ADDR (0x20080000u) /**< Internal RAM 1 base address */ +#define NFC_RAM_ADDR (0x20100000u) /**< NAND Flash Controller RAM base address */ +#define UOTGHS_RAM_ADDR (0x20180000u) /**< USB On-The-Go Interface RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define EBI_CS4_ADDR (0x64000000u) /**< EBI Chip Select 4 base address */ +#define EBI_CS5_ADDR (0x65000000u) /**< EBI Chip Select 5 base address */ +#define EBI_CS6_ADDR (0x66000000u) /**< EBI Chip Select 6 base address */ +#define EBI_CS7_ADDR (0x67000000u) /**< EBI Chip Select 7 base address */ + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAM3X8H */ +/* ************************************************************************** */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (84000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Write Wait State */ +#define CHIP_FLASH_WRITE_WAIT_STATE (6U) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.8V) */ +#define CHIP_FREQ_FWS_0 (19000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (50000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (64000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (90000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAM3X8H_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h new file mode 100644 index 0000000..1752d1a --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/include/sam3xa.h @@ -0,0 +1,66 @@ +/** + * \file + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM3XA_ +#define _SAM3XA_ + +#if defined __SAM3A4C__ + #include "sam3a4c.h" +#elif defined __SAM3A8C__ + #include "sam3a8c.h" +#elif defined __SAM3X4C__ + #include "sam3x4c.h" +#elif defined __SAM3X4E__ + #include "sam3x4e.h" +#elif defined __SAM3X8C__ + #include "sam3x8c.h" +#elif defined __SAM3X8E__ + #include "sam3x8e.h" +#elif defined __SAM3X8H__ + #include "sam3x8h.h" +#else + #error Library does not support the specified device. +#endif + +#endif /* _SAM3XA_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.c b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.c new file mode 100644 index 0000000..e647e12 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.c @@ -0,0 +1,242 @@ +/** + * \file + * + * \brief This file contains the default exception handlers. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + * \par Purpose + * + * This file provides basic support for Cortex-M processor based + * microcontrollers. + * + * \note + * The exception handler has weak aliases. + * As they are weak aliases, any function with the same name will override + * this definition. + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#include "exceptions.h" + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/* @endcond */ + +#ifdef __GNUC__ +/* Cortex-M3 core handlers */ +void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemManage_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMon_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void SUPC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EFC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EFC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef _SAM3XA_SMC_INSTANCE_ +void SMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAM3XA_SMC_INSTANCE_ */ +#ifdef _SAM3XA_SDRAMC_INSTANCE_ +void SDRAMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAM3XA_SDRAMC_INSTANCE_ */ +void PIOA_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef _SAM3XA_PIOC_INSTANCE_ +void PIOC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAM3XA_PIOC_INSTANCE_ */ +#ifdef _SAM3XA_PIOD_INSTANCE_ +void PIOD_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAM3XA_PIOD_INSTANCE_ */ +#ifdef _SAM3XA_PIOE_INSTANCE_ +void PIOE_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAM3XA_PIOE_INSTANCE_ */ +#ifdef _SAM3XA_PIOF_INSTANCE_ +void PIOF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAM3XA_PIOF_INSTANCE_ */ +void USART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef _SAM3XA_USART3_INSTANCE_ +void USART3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAM3XA_USART3_INSTANCE_ */ +void HSMCI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWI0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWI1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SPI0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef _SAM3XA_SPI1_INSTANCE_ +void SPI1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAM3XA_SPI1_INSTANCE_ */ +void SSC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef _SAM3XA_TC2_INSTANCE_ +void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAM3XA_TC2_INSTANCE_ */ +void PWM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UOTGHS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef _SAM3XA_EMAC_INSTANCE_ +void EMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAM3XA_EMAC_INSTANCE_ */ +void CAN0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void CAN1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* __GNUC__ */ + +#ifdef __ICCARM__ +/* Cortex-M3 core handlers */ +#pragma weak NMI_Handler=Dummy_Handler +#pragma weak HardFault_Handler=Dummy_Handler +#pragma weak MemManage_Handler=Dummy_Handler +#pragma weak BusFault_Handler=Dummy_Handler +#pragma weak UsageFault_Handler=Dummy_Handler +#pragma weak SVC_Handler=Dummy_Handler +#pragma weak DebugMon_Handler=Dummy_Handler +#pragma weak PendSV_Handler=Dummy_Handler +#pragma weak SysTick_Handler=Dummy_Handler + +/* Peripherals handlers */ +#pragma weak SUPC_Handler=Dummy_Handler +#pragma weak RSTC_Handler=Dummy_Handler +#pragma weak RTC_Handler=Dummy_Handler +#pragma weak RTT_Handler=Dummy_Handler +#pragma weak WDT_Handler=Dummy_Handler +#pragma weak PMC_Handler=Dummy_Handler +#pragma weak EFC0_Handler=Dummy_Handler +#pragma weak EFC1_Handler=Dummy_Handler +#pragma weak UART_Handler=Dummy_Handler +#ifdef _SAM3XA_SMC_INSTANCE_ +#pragma weak SMC_Handler=Dummy_Handler +#endif /* _SAM3XA_SMC_INSTANCE_ */ +#ifdef _SAM3XA_SDRAMC_INSTANCE_ +#pragma weak SDRAMC_Handler=Dummy_Handler +#endif /* _SAM3XA_SDRAMC_INSTANCE_ */ +#pragma weak PIOA_Handler=Dummy_Handler +#pragma weak PIOB_Handler=Dummy_Handler +#ifdef _SAM3XA_PIOC_INSTANCE_ +#pragma weak PIOC_Handler=Dummy_Handler +#endif /* _SAM3XA_PIOC_INSTANCE_ */ +#ifdef _SAM3XA_PIOD_INSTANCE_ +#pragma weak PIOD_Handler=Dummy_Handler +#endif /* _SAM3XA_PIOD_INSTANCE_ */ +#ifdef _SAM3XA_PIOE_INSTANCE_ +#pragma weak PIOE_Handler=Dummy_Handler +#endif /* _SAM3XA_PIOE_INSTANCE_ */ +#ifdef _SAM3XA_PIOF_INSTANCE_ +#pragma weak PIOF_Handler=Dummy_Handler +#endif /* _SAM3XA_PIOF_INSTANCE_ */ +#pragma weak USART0_Handler=Dummy_Handler +#pragma weak USART1_Handler=Dummy_Handler +#pragma weak USART2_Handler=Dummy_Handler +#ifdef _SAM3XA_USART3_INSTANCE_ +#pragma weak USART3_Handler=Dummy_Handler +#endif /* _SAM3XA_USART3_INSTANCE_ */ +#pragma weak HSMCI_Handler=Dummy_Handler +#pragma weak TWI0_Handler=Dummy_Handler +#pragma weak TWI1_Handler=Dummy_Handler +#pragma weak SPI0_Handler=Dummy_Handler +#ifdef _SAM3XA_SPI1_INSTANCE_ +#pragma weak SPI1_Handler=Dummy_Handler +#endif /* _SAM3XA_SPI1_INSTANCE_ */ +#pragma weak SSC_Handler=Dummy_Handler +#pragma weak TC0_Handler=Dummy_Handler +#pragma weak TC1_Handler=Dummy_Handler +#pragma weak TC2_Handler=Dummy_Handler +#pragma weak TC3_Handler=Dummy_Handler +#pragma weak TC4_Handler=Dummy_Handler +#pragma weak TC5_Handler=Dummy_Handler +#ifdef _SAM3XA_TC2_INSTANCE_ +#pragma weak TC6_Handler=Dummy_Handler +#pragma weak TC7_Handler=Dummy_Handler +#pragma weak TC8_Handler=Dummy_Handler +#endif /* _SAM3XA_TC2_INSTANCE_ */ +#pragma weak PWM_Handler=Dummy_Handler +#pragma weak ADC_Handler=Dummy_Handler +#pragma weak DACC_Handler=Dummy_Handler +#pragma weak DMAC_Handler=Dummy_Handler +#pragma weak UOTGHS_Handler=Dummy_Handler +#pragma weak TRNG_Handler=Dummy_Handler +#ifdef _SAM3XA_EMAC_INSTANCE_ +#pragma weak EMAC_Handler=Dummy_Handler +#endif /* _SAM3XA_EMAC_INSTANCE_ */ +#pragma weak CAN0_Handler=Dummy_Handler +#pragma weak CAN1_Handler=Dummy_Handler +#endif /* __ICCARM__ */ + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/* @endcond */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.h new file mode 100644 index 0000000..dc32622 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/source/templates/exceptions.h @@ -0,0 +1,74 @@ +/** + * \file + * + * \brief This file contains the interface for default exception handlers. + * + * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef EXCEPTIONS_H_INCLUDED +#define EXCEPTIONS_H_INCLUDED + +#include "sam3xa.h" + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/* @endcond */ + +/* Function prototype for exception table items (interrupt handler). */ +typedef void (*IntFunc) (void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/* @endcond */ + +#endif /* EXCEPTIONS_H_INCLUDED */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/source/templates/gcc/startup_sam3x.c b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/source/templates/gcc/startup_sam3x.c new file mode 100644 index 0000000..04285e8 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/source/templates/gcc/startup_sam3x.c @@ -0,0 +1,224 @@ +/** + * \file + * + * \brief Startup file for SAM3X. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#include "exceptions.h" +#include "sam3xa.h" +#include "system_sam3x.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +IntFunc exception_table[] = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + (IntFunc) (&_estack), + (void*) Reset_Handler, + + (void*) NMI_Handler, + (void*) HardFault_Handler, + (void*) MemManage_Handler, + (void*) BusFault_Handler, + (void*) UsageFault_Handler, + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) SVC_Handler, + (void*) DebugMon_Handler, + (void*) (0UL), /* Reserved */ + (void*) PendSV_Handler, + (void*) SysTick_Handler, + + /* Configurable interrupts */ + (void*) SUPC_Handler, /* 0 Supply Controller */ + (void*) RSTC_Handler, /* 1 Reset Controller */ + (void*) RTC_Handler, /* 2 Real Time Clock */ + (void*) RTT_Handler, /* 3 Real Time Timer */ + (void*) WDT_Handler, /* 4 Watchdog Timer */ + (void*) PMC_Handler, /* 5 PMC */ + (void*) EFC0_Handler, /* 6 EFC 0 */ + (void*) EFC1_Handler, /* 7 EFC 1 */ + (void*) UART_Handler, /* 8 UART */ +#ifdef _SAM3XA_SMC_INSTANCE_ + (void*) SMC_Handler, /* 9 SMC */ +#else + (void*) (0UL), /* 9 Reserved */ +#endif /* _SAM3XA_SMC_INSTANCE_ */ +#ifdef _SAM3XA_SDRAMC_INSTANCE_ + (void*) SDRAMC_Handler, /* 10 SDRAMC */ +#else + (void*) (0UL), /* 10 Reserved */ +#endif /* _SAM3XA_SDRAMC_INSTANCE_ */ + (void*) PIOA_Handler, /* 11 Parallel IO Controller A */ + (void*) PIOB_Handler, /* 12 Parallel IO Controller B */ +#ifdef _SAM3XA_PIOC_INSTANCE_ + (void*) PIOC_Handler, /* 13 Parallel IO Controller C */ +#else + (void*) (0UL), /* 13 Reserved */ +#endif /* _SAM3XA_PIOC_INSTANCE_ */ +#ifdef _SAM3XA_PIOD_INSTANCE_ + (void*) PIOD_Handler, /* 14 Parallel IO Controller D */ +#else + (void*) (0UL), /* 14 Reserved */ +#endif /* _SAM3XA_PIOD_INSTANCE_ */ +#ifdef _SAM3XA_PIOE_INSTANCE_ + (void*) PIOE_Handler, /* 15 Parallel IO Controller E */ +#else + (void*) (0UL), /* 15 Reserved */ +#endif /* _SAM3XA_PIOE_INSTANCE_ */ +#ifdef _SAM3XA_PIOF_INSTANCE_ + (void*) PIOF_Handler, /* 16 Parallel IO Controller F */ +#else + (void*) (0UL), /* 16 Reserved */ +#endif /* _SAM3XA_PIOF_INSTANCE_ */ + (void*) USART0_Handler, /* 17 USART 0 */ + (void*) USART1_Handler, /* 18 USART 1 */ + (void*) USART2_Handler, /* 19 USART 2 */ +#ifdef _SAM3XA_USART3_INSTANCE_ + (void*) USART3_Handler, /* 20 USART 3 */ +#else + (void*) (0UL), /* 20 Reserved */ +#endif /* _SAM3XA_USART3_INSTANCE_ */ + (void*) HSMCI_Handler, /* 21 MCI */ + (void*) TWI0_Handler, /* 22 TWI 0 */ + (void*) TWI1_Handler, /* 23 TWI 1 */ + (void*) SPI0_Handler, /* 24 SPI 0 */ +#ifdef _SAM3XA_SPI1_INSTANCE_ + (void*) SPI1_Handler, /* 25 SPI 1 */ +#else + (void*) (0UL), /* 25 Reserved */ +#endif /* _SAM3XA_SPI1_INSTANCE_ */ + (void*) SSC_Handler, /* 26 SSC */ + (void*) TC0_Handler, /* 27 Timer Counter 0 */ + (void*) TC1_Handler, /* 28 Timer Counter 1 */ + (void*) TC2_Handler, /* 29 Timer Counter 2 */ + (void*) TC3_Handler, /* 30 Timer Counter 3 */ + (void*) TC4_Handler, /* 31 Timer Counter 4 */ + (void*) TC5_Handler, /* 32 Timer Counter 5 */ +#ifdef _SAM3XA_TC2_INSTANCE_ + (void*) TC6_Handler, /* 33 Timer Counter 6 */ + (void*) TC7_Handler, /* 34 Timer Counter 7 */ + (void*) TC8_Handler, /* 35 Timer Counter 8 */ +#else + (void*) (0UL), /* 33 Reserved */ + (void*) (0UL), /* 34 Reserved */ + (void*) (0UL), /* 35 Reserved */ +#endif /* _SAM3XA_TC2_INSTANCE_ */ + (void*) PWM_Handler, /* 36 PWM */ + (void*) ADC_Handler, /* 37 ADC controller */ + (void*) DACC_Handler, /* 38 DAC controller */ + (void*) DMAC_Handler, /* 39 DMA Controller */ + (void*) UOTGHS_Handler, /* 40 USB OTG High Speed */ + (void*) TRNG_Handler, /* 41 True Random Number Generator */ +#ifdef _SAM3XA_EMAC_INSTANCE_ + (void*) EMAC_Handler, /* 42 Ethernet MAC */ +#else + (void*) (0UL), /* 42 Reserved */ +#endif /* _SAM3XA_EMAC_INSTANCE_ */ + (void*) CAN0_Handler, /* 43 CAN Controller 0 */ + (void*) CAN1_Handler /* 44 CAN Controller 1 */ +}; + +/* TEMPORARY PATCH FOR SCB */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + if (((uint32_t) pSrc >= IRAM0_ADDR) && ((uint32_t) pSrc < NFC_RAM_ADDR)) { + SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos; + } + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.c b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.c new file mode 100644 index 0000000..5d8caef --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.c @@ -0,0 +1,229 @@ +/** + * \file + * + * \brief Provides the low-level initialization functions that called + * on chip startup. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#include "system_sam3x.h" +#include "sam3xa.h" + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/* @endcond */ + +/* Clock settings (84MHz) */ +#define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8)) +#define SYS_BOARD_PLLAR (CKGR_PLLAR_ONE \ + | CKGR_PLLAR_MULA(0xdUL) \ + | CKGR_PLLAR_PLLACOUNT(0x3fUL) \ + | CKGR_PLLAR_DIVA(0x1UL)) +#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK) + +/* Clock Definitions */ +#define SYS_UTMIPLL (480000000UL) /* UTMI PLL frequency */ + +#define SYS_CKGR_MOR_KEY_VALUE CKGR_MOR_KEY(0x37) /* Key to unlock MOR register */ + +/* FIXME: should be generated by sock */ +uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; + +/** + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemFrequency variable. + */ +__no_inline +RAMFUNC +void SystemInit(void) +{ + /* Set FWS according to SYS_BOARD_MCKR configuration */ + EFC0->EEFC_FMR = EEFC_FMR_FWS(4); + EFC1->EEFC_FMR = EEFC_FMR_FWS(4); + + /* Initialize main oscillator */ + if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) { + PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT | + CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN; + while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) { + } + } + + /* Switch to 3-20MHz Xtal oscillator */ + PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT | + CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL; + + while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) { + } + PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | + PMC_MCKR_CSS_MAIN_CLK; + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { + } + + /* Initialize PLLA */ + PMC->CKGR_PLLAR = SYS_BOARD_PLLAR; + while (!(PMC->PMC_SR & PMC_SR_LOCKA)) { + } + + /* Switch to main clock */ + PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK; + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { + } + + /* Switch to PLLA */ + PMC->PMC_MCKR = SYS_BOARD_MCKR; + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { + } + + SystemCoreClock = CHIP_FREQ_CPU_MAX; +} + +void SystemCoreClockUpdate(void) +{ + /* Determine clock frequency according to clock register values */ + switch (PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) { + case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */ + if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) { + SystemCoreClock = CHIP_FREQ_XTAL_32K; + } else { + SystemCoreClock = CHIP_FREQ_SLCK_RC; + } + break; + case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */ + if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) { + SystemCoreClock = CHIP_FREQ_XTAL_12M; + } else { + SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; + + switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) { + case CKGR_MOR_MOSCRCF_4_MHz: + break; + case CKGR_MOR_MOSCRCF_8_MHz: + SystemCoreClock *= 2U; + break; + case CKGR_MOR_MOSCRCF_12_MHz: + SystemCoreClock *= 3U; + break; + default: + break; + } + } + break; + case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */ + case PMC_MCKR_CSS_UPLL_CLK: /* UPLL clock */ + if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) { + SystemCoreClock = CHIP_FREQ_XTAL_12M; + } else { + SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; + + switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) { + case CKGR_MOR_MOSCRCF_4_MHz: + break; + case CKGR_MOR_MOSCRCF_8_MHz: + SystemCoreClock *= 2U; + break; + case CKGR_MOR_MOSCRCF_12_MHz: + SystemCoreClock *= 3U; + break; + default: + break; + } + } + if ((PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK) { + SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >> + CKGR_PLLAR_MULA_Pos) + 1U); + SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >> + CKGR_PLLAR_DIVA_Pos)); + } else { + SystemCoreClock = SYS_UTMIPLL / 2U; + } + break; + } + + if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) { + SystemCoreClock /= 3U; + } else { + SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> + PMC_MCKR_PRES_Pos); + } +} + +/** + * Initialize flash. + */ +__no_inline +RAMFUNC +void system_init_flash(uint32_t ul_clk) +{ + /* Set FWS for embedded Flash access according to operating frequency */ + if (ul_clk < CHIP_FREQ_FWS_0) { + EFC0->EEFC_FMR = EEFC_FMR_FWS(0); + EFC1->EEFC_FMR = EEFC_FMR_FWS(0); + } else if (ul_clk < CHIP_FREQ_FWS_1) { + EFC0->EEFC_FMR = EEFC_FMR_FWS(1); + EFC1->EEFC_FMR = EEFC_FMR_FWS(1); + } else if (ul_clk < CHIP_FREQ_FWS_2) { + EFC0->EEFC_FMR = EEFC_FMR_FWS(2); + EFC1->EEFC_FMR = EEFC_FMR_FWS(2); + } else if (ul_clk < CHIP_FREQ_FWS_3) { + EFC0->EEFC_FMR = EEFC_FMR_FWS(3); + EFC1->EEFC_FMR = EEFC_FMR_FWS(3); + } else if (ul_clk < CHIP_FREQ_FWS_4) { + EFC0->EEFC_FMR = EEFC_FMR_FWS(4); + EFC1->EEFC_FMR = EEFC_FMR_FWS(4); + } else { + EFC0->EEFC_FMR = EEFC_FMR_FWS(5); + EFC1->EEFC_FMR = EEFC_FMR_FWS(5); + } +} + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/* @endcond */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h new file mode 100644 index 0000000..8e522ed --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/cmsis/sam3x/source/templates/system_sam3x.h @@ -0,0 +1,89 @@ +/** + * \file + * + * \brief Provides the low-level initialization functions that called + * on chip startup. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef SYSTEM_SAM3X_H_INCLUDED +#define SYSTEM_SAM3X_H_INCLUDED + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/* @endcond */ + +#include +#include + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +/** + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void); + +/** + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void); + +/** + * Initialize flash. + */ +void system_init_flash(uint32_t ul_clk); + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/* @endcond */ + +#endif /* SYSTEM_SAM3X_H_INCLUDED */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/compiler.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/compiler.h new file mode 100644 index 0000000..bfaf65f --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/compiler.h @@ -0,0 +1,1199 @@ +/** + * \file + * + * \brief Commonly used includes, types and macros. + * + * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef UTILS_COMPILER_H +#define UTILS_COMPILER_H + +/** + * \defgroup group_sam_utils Compiler abstraction layer and code utilities + * + * Compiler abstraction layer and code utilities for AT91SAM. + * This module provides various abstraction layers and utilities to make code compatible between different compilers. + * + * \{ + */ +#include + +#if (defined __ICCARM__) +# include +#endif + +#include +#include "preprocessor.h" + +#include + +//_____ D E C L A R A T I O N S ____________________________________________ + +#ifndef __ASSEMBLY__ // Not defined for assembling. + +#include +#include +#include +#include + +#ifdef __ICCARM__ +/*! \name Compiler Keywords + * + * Port of some keywords from GCC to IAR Embedded Workbench. + */ +//! @{ +#define __asm__ asm +#define __inline__ inline +#define __volatile__ +//! @} + +#endif + +#define FUNC_PTR void * +/** + * \def UNUSED + * \brief Marking \a v as a unused parameter or value. + */ +#define UNUSED(v) (void)(v) + +/** + * \def unused + * \brief Marking \a v as a unused parameter or value. + */ +#define unused(v) do { (void)(v); } while(0) + +/** + * \def barrier + * \brief Memory barrier + */ +#define barrier() __DMB() + +/** + * \brief Emit the compiler pragma \a arg. + * + * \param arg The pragma directive as it would appear after \e \#pragma + * (i.e. not stringified). + */ +#define COMPILER_PRAGMA(arg) _Pragma(#arg) + +/** + * \def COMPILER_PACK_SET(alignment) + * \brief Set maximum alignment for subsequent struct and union + * definitions to \a alignment. + */ +#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment)) + +/** + * \def COMPILER_PACK_RESET() + * \brief Set default alignment for subsequent struct and union + * definitions. + */ +#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack()) + + +/** + * \brief Set aligned boundary. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +# define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#elif (defined __ICCARM__) +# define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a) +#endif + +/** + * \brief Set word-aligned boundary. + */ +#if (defined __GNUC__) || defined(__CC_ARM) +#define COMPILER_WORD_ALIGNED __attribute__((__aligned__(4))) +#elif (defined __ICCARM__) +#define COMPILER_WORD_ALIGNED COMPILER_PRAGMA(data_alignment = 4) +#endif + +/** + * \def __always_inline + * \brief The function should always be inlined. + * + * This annotation instructs the compiler to ignore its inlining + * heuristics and inline the function no matter how big it thinks it + * becomes. + */ +#if defined(__CC_ARM) +# define __always_inline __forceinline +#elif (defined __GNUC__) +#ifdef __always_inline +# undef __always_inline +#endif +# define __always_inline inline __attribute__((__always_inline__)) +#elif (defined __ICCARM__) +# define __always_inline _Pragma("inline=forced") +#endif + +/** + * \def __no_inline + * \brief The function should not be inlined. + * + * This annotation instructs the compiler to ignore its inlining + * heuristics and not inline the function. + */ +#if defined(__CC_ARM) +# define __no_inline __attribute__((noinline)) +#elif (defined __GNUC__) +# define __no_inline __attribute__((__noinline__)) +#elif (defined __ICCARM__) +# define __no_inline _Pragma("inline=never") +#endif + +/*! \brief This macro is used to test fatal errors. + * + * The macro tests if the expression is false. If it is, a fatal error is + * detected and the application hangs up. If TEST_SUITE_DEFINE_ASSERT_MACRO + * is defined, a unit test version of the macro is used, to allow execution + * of further tests after a false expression. + * + * \param expr Expression to evaluate and supposed to be nonzero. + */ +#if defined(_ASSERT_ENABLE_) +# if defined(TEST_SUITE_DEFINE_ASSERT_MACRO) + // Assert() is defined in unit_test/suite.h +# include "unit_test/suite.h" +# else +#undef TEST_SUITE_DEFINE_ASSERT_MACRO +# define Assert(expr) \ + {\ + if (!(expr)) while (true);\ + } +# endif +#else +# define Assert(expr) ((void) 0) +#endif + +/* Define WEAK attribute */ +#if defined ( __CC_ARM ) /* Keil µVision 4 */ +# define WEAK __attribute__ ((weak)) +#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */ +# define WEAK __weak +#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */ +# define WEAK __attribute__ ((weak)) +#endif + +/* Define NO_INIT attribute */ +#if defined ( __CC_ARM ) +# define NO_INIT __attribute__((zero_init)) +#elif defined ( __ICCARM__ ) +# define NO_INIT __no_init +#elif defined ( __GNUC__ ) +# define NO_INIT __attribute__((section(".no_init"))) +#endif + +/* Define RAMFUNC attribute */ +#if defined ( __CC_ARM ) /* Keil µVision 4 */ +# define RAMFUNC __attribute__ ((section(".ramfunc"))) +#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */ +# define RAMFUNC __ramfunc +#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */ +# define RAMFUNC __attribute__ ((section(".ramfunc"))) +#endif + +/* Define OPTIMIZE_HIGH attribute */ +#if defined ( __CC_ARM ) /* Keil µVision 4 */ +# define OPTIMIZE_HIGH _Pragma("O3") +#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */ +# define OPTIMIZE_HIGH _Pragma("optimize=high") +#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */ +# define OPTIMIZE_HIGH __attribute__((optimize(s))) +#endif + +#include "interrupt.h" + +/*! \name Usual Types + */ +//! @{ +typedef unsigned char Bool; //!< Boolean. +#ifndef __cplusplus +#if !defined(__bool_true_false_are_defined) +typedef unsigned char bool; //!< Boolean. +#endif +#endif +typedef int8_t S8 ; //!< 8-bit signed integer. +typedef uint8_t U8 ; //!< 8-bit unsigned integer. +typedef int16_t S16; //!< 16-bit signed integer. +typedef uint16_t U16; //!< 16-bit unsigned integer. +typedef uint16_t le16_t; +typedef uint16_t be16_t; +typedef int32_t S32; //!< 32-bit signed integer. +typedef uint32_t U32; //!< 32-bit unsigned integer. +typedef uint32_t le32_t; +typedef uint32_t be32_t; +typedef int64_t S64; //!< 64-bit signed integer. +typedef uint64_t U64; //!< 64-bit unsigned integer. +typedef float F32; //!< 32-bit floating-point number. +typedef double F64; //!< 64-bit floating-point number. +typedef uint32_t iram_size_t; +//! @} + + +/*! \name Status Types + */ +//! @{ +typedef bool Status_bool_t; //!< Boolean status. +typedef U8 Status_t; //!< 8-bit-coded status. +//! @} + + +/*! \name Aliasing Aggregate Types + */ +//! @{ + +//! 16-bit union. +typedef union +{ + S16 s16 ; + U16 u16 ; + S8 s8 [2]; + U8 u8 [2]; +} Union16; + +//! 32-bit union. +typedef union +{ + S32 s32 ; + U32 u32 ; + S16 s16[2]; + U16 u16[2]; + S8 s8 [4]; + U8 u8 [4]; +} Union32; + +//! 64-bit union. +typedef union +{ + S64 s64 ; + U64 u64 ; + S32 s32[2]; + U32 u32[2]; + S16 s16[4]; + U16 u16[4]; + S8 s8 [8]; + U8 u8 [8]; +} Union64; + +//! Union of pointers to 64-, 32-, 16- and 8-bit unsigned integers. +typedef union +{ + S64 *s64ptr; + U64 *u64ptr; + S32 *s32ptr; + U32 *u32ptr; + S16 *s16ptr; + U16 *u16ptr; + S8 *s8ptr ; + U8 *u8ptr ; +} UnionPtr; + +//! Union of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. +typedef union +{ + volatile S64 *s64ptr; + volatile U64 *u64ptr; + volatile S32 *s32ptr; + volatile U32 *u32ptr; + volatile S16 *s16ptr; + volatile U16 *u16ptr; + volatile S8 *s8ptr ; + volatile U8 *u8ptr ; +} UnionVPtr; + +//! Union of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. +typedef union +{ + const S64 *s64ptr; + const U64 *u64ptr; + const S32 *s32ptr; + const U32 *u32ptr; + const S16 *s16ptr; + const U16 *u16ptr; + const S8 *s8ptr ; + const U8 *u8ptr ; +} UnionCPtr; + +//! Union of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. +typedef union +{ + const volatile S64 *s64ptr; + const volatile U64 *u64ptr; + const volatile S32 *s32ptr; + const volatile U32 *u32ptr; + const volatile S16 *s16ptr; + const volatile U16 *u16ptr; + const volatile S8 *s8ptr ; + const volatile U8 *u8ptr ; +} UnionCVPtr; + +//! Structure of pointers to 64-, 32-, 16- and 8-bit unsigned integers. +typedef struct +{ + S64 *s64ptr; + U64 *u64ptr; + S32 *s32ptr; + U32 *u32ptr; + S16 *s16ptr; + U16 *u16ptr; + S8 *s8ptr ; + U8 *u8ptr ; +} StructPtr; + +//! Structure of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. +typedef struct +{ + volatile S64 *s64ptr; + volatile U64 *u64ptr; + volatile S32 *s32ptr; + volatile U32 *u32ptr; + volatile S16 *s16ptr; + volatile U16 *u16ptr; + volatile S8 *s8ptr ; + volatile U8 *u8ptr ; +} StructVPtr; + +//! Structure of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. +typedef struct +{ + const S64 *s64ptr; + const U64 *u64ptr; + const S32 *s32ptr; + const U32 *u32ptr; + const S16 *s16ptr; + const U16 *u16ptr; + const S8 *s8ptr ; + const U8 *u8ptr ; +} StructCPtr; + +//! Structure of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. +typedef struct +{ + const volatile S64 *s64ptr; + const volatile U64 *u64ptr; + const volatile S32 *s32ptr; + const volatile U32 *u32ptr; + const volatile S16 *s16ptr; + const volatile U16 *u16ptr; + const volatile S8 *s8ptr ; + const volatile U8 *u8ptr ; +} StructCVPtr; + +//! @} + +#endif // #ifndef __ASSEMBLY__ + +/*! \name Usual Constants + */ +//! @{ +#define DISABLE 0 +#define ENABLE 1 +#ifndef __cplusplus +#if !defined(__bool_true_false_are_defined) +#define false 0 +#define true 1 +#endif +#endif +#define PASS 0 +#define FAIL 1 +#define LOW 0 +#define HIGH 1 +//! @} + + +#ifndef __ASSEMBLY__ // not for assembling. + +//! \name Optimization Control +//@{ + +/** + * \def likely(exp) + * \brief The expression \a exp is likely to be true + */ +#ifndef likely +# define likely(exp) (exp) +#endif + +/** + * \def unlikely(exp) + * \brief The expression \a exp is unlikely to be true + */ +#ifndef unlikely +# define unlikely(exp) (exp) +#endif + +/** + * \def is_constant(exp) + * \brief Determine if an expression evaluates to a constant value. + * + * \param exp Any expression + * + * \return true if \a exp is constant, false otherwise. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +# define is_constant(exp) __builtin_constant_p(exp) +#else +# define is_constant(exp) (0) +#endif + +//! @} + +/*! \name Bit-Field Handling + */ +//! @{ + +/*! \brief Reads the bits of a value specified by a given bit-mask. + * + * \param value Value to read bits from. + * \param mask Bit-mask indicating bits to read. + * + * \return Read bits. + */ +#define Rd_bits( value, mask) ((value) & (mask)) + +/*! \brief Writes the bits of a C lvalue specified by a given bit-mask. + * + * \param lvalue C lvalue to write bits to. + * \param mask Bit-mask indicating bits to write. + * \param bits Bits to write. + * + * \return Resulting value with written bits. + */ +#define Wr_bits(lvalue, mask, bits) ((lvalue) = ((lvalue) & ~(mask)) |\ + ((bits ) & (mask))) + +/*! \brief Tests the bits of a value specified by a given bit-mask. + * + * \param value Value of which to test bits. + * \param mask Bit-mask indicating bits to test. + * + * \return \c 1 if at least one of the tested bits is set, else \c 0. + */ +#define Tst_bits( value, mask) (Rd_bits(value, mask) != 0) + +/*! \brief Clears the bits of a C lvalue specified by a given bit-mask. + * + * \param lvalue C lvalue of which to clear bits. + * \param mask Bit-mask indicating bits to clear. + * + * \return Resulting value with cleared bits. + */ +#define Clr_bits(lvalue, mask) ((lvalue) &= ~(mask)) + +/*! \brief Sets the bits of a C lvalue specified by a given bit-mask. + * + * \param lvalue C lvalue of which to set bits. + * \param mask Bit-mask indicating bits to set. + * + * \return Resulting value with set bits. + */ +#define Set_bits(lvalue, mask) ((lvalue) |= (mask)) + +/*! \brief Toggles the bits of a C lvalue specified by a given bit-mask. + * + * \param lvalue C lvalue of which to toggle bits. + * \param mask Bit-mask indicating bits to toggle. + * + * \return Resulting value with toggled bits. + */ +#define Tgl_bits(lvalue, mask) ((lvalue) ^= (mask)) + +/*! \brief Reads the bit-field of a value specified by a given bit-mask. + * + * \param value Value to read a bit-field from. + * \param mask Bit-mask indicating the bit-field to read. + * + * \return Read bit-field. + */ +#define Rd_bitfield( value, mask) (Rd_bits( value, mask) >> ctz(mask)) + +/*! \brief Writes the bit-field of a C lvalue specified by a given bit-mask. + * + * \param lvalue C lvalue to write a bit-field to. + * \param mask Bit-mask indicating the bit-field to write. + * \param bitfield Bit-field to write. + * + * \return Resulting value with written bit-field. + */ +#define Wr_bitfield(lvalue, mask, bitfield) (Wr_bits(lvalue, mask, (U32)(bitfield) << ctz(mask))) + +//! @} + + +/*! \name Zero-Bit Counting + * + * Under GCC, __builtin_clz and __builtin_ctz behave like macros when + * applied to constant expressions (values known at compile time), so they are + * more optimized than the use of the corresponding assembly instructions and + * they can be used as constant expressions e.g. to initialize objects having + * static storage duration, and like the corresponding assembly instructions + * when applied to non-constant expressions (values unknown at compile time), so + * they are more optimized than an assembly periphrasis. Hence, clz and ctz + * ensure a possible and optimized behavior for both constant and non-constant + * expressions. + */ +//! @{ + +/*! \brief Counts the leading zero bits of the given value considered as a 32-bit integer. + * + * \param u Value of which to count the leading zero bits. + * + * \return The count of leading zero bits in \a u. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +# define clz(u) __builtin_clz(u) +#elif (defined __ICCARM__) +# define clz(u) __CLZ(u) +#else +# define clz(u) (((u) == 0) ? 32 : \ + ((u) & (1ul << 31)) ? 0 : \ + ((u) & (1ul << 30)) ? 1 : \ + ((u) & (1ul << 29)) ? 2 : \ + ((u) & (1ul << 28)) ? 3 : \ + ((u) & (1ul << 27)) ? 4 : \ + ((u) & (1ul << 26)) ? 5 : \ + ((u) & (1ul << 25)) ? 6 : \ + ((u) & (1ul << 24)) ? 7 : \ + ((u) & (1ul << 23)) ? 8 : \ + ((u) & (1ul << 22)) ? 9 : \ + ((u) & (1ul << 21)) ? 10 : \ + ((u) & (1ul << 20)) ? 11 : \ + ((u) & (1ul << 19)) ? 12 : \ + ((u) & (1ul << 18)) ? 13 : \ + ((u) & (1ul << 17)) ? 14 : \ + ((u) & (1ul << 16)) ? 15 : \ + ((u) & (1ul << 15)) ? 16 : \ + ((u) & (1ul << 14)) ? 17 : \ + ((u) & (1ul << 13)) ? 18 : \ + ((u) & (1ul << 12)) ? 19 : \ + ((u) & (1ul << 11)) ? 20 : \ + ((u) & (1ul << 10)) ? 21 : \ + ((u) & (1ul << 9)) ? 22 : \ + ((u) & (1ul << 8)) ? 23 : \ + ((u) & (1ul << 7)) ? 24 : \ + ((u) & (1ul << 6)) ? 25 : \ + ((u) & (1ul << 5)) ? 26 : \ + ((u) & (1ul << 4)) ? 27 : \ + ((u) & (1ul << 3)) ? 28 : \ + ((u) & (1ul << 2)) ? 29 : \ + ((u) & (1ul << 1)) ? 30 : \ + 31) +#endif + +/*! \brief Counts the trailing zero bits of the given value considered as a 32-bit integer. + * + * \param u Value of which to count the trailing zero bits. + * + * \return The count of trailing zero bits in \a u. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +# define ctz(u) __builtin_ctz(u) +#else +# define ctz(u) ((u) & (1ul << 0) ? 0 : \ + (u) & (1ul << 1) ? 1 : \ + (u) & (1ul << 2) ? 2 : \ + (u) & (1ul << 3) ? 3 : \ + (u) & (1ul << 4) ? 4 : \ + (u) & (1ul << 5) ? 5 : \ + (u) & (1ul << 6) ? 6 : \ + (u) & (1ul << 7) ? 7 : \ + (u) & (1ul << 8) ? 8 : \ + (u) & (1ul << 9) ? 9 : \ + (u) & (1ul << 10) ? 10 : \ + (u) & (1ul << 11) ? 11 : \ + (u) & (1ul << 12) ? 12 : \ + (u) & (1ul << 13) ? 13 : \ + (u) & (1ul << 14) ? 14 : \ + (u) & (1ul << 15) ? 15 : \ + (u) & (1ul << 16) ? 16 : \ + (u) & (1ul << 17) ? 17 : \ + (u) & (1ul << 18) ? 18 : \ + (u) & (1ul << 19) ? 19 : \ + (u) & (1ul << 20) ? 20 : \ + (u) & (1ul << 21) ? 21 : \ + (u) & (1ul << 22) ? 22 : \ + (u) & (1ul << 23) ? 23 : \ + (u) & (1ul << 24) ? 24 : \ + (u) & (1ul << 25) ? 25 : \ + (u) & (1ul << 26) ? 26 : \ + (u) & (1ul << 27) ? 27 : \ + (u) & (1ul << 28) ? 28 : \ + (u) & (1ul << 29) ? 29 : \ + (u) & (1ul << 30) ? 30 : \ + (u) & (1ul << 31) ? 31 : \ + 32) +#endif + +//! @} + + +/*! \name Bit Reversing + */ +//! @{ + +/*! \brief Reverses the bits of \a u8. + * + * \param u8 U8 of which to reverse the bits. + * + * \return Value resulting from \a u8 with reversed bits. + */ +#define bit_reverse8(u8) ((U8)(bit_reverse32((U8)(u8)) >> 24)) + +/*! \brief Reverses the bits of \a u16. + * + * \param u16 U16 of which to reverse the bits. + * + * \return Value resulting from \a u16 with reversed bits. + */ +#define bit_reverse16(u16) ((U16)(bit_reverse32((U16)(u16)) >> 16)) + +/*! \brief Reverses the bits of \a u32. + * + * \param u32 U32 of which to reverse the bits. + * + * \return Value resulting from \a u32 with reversed bits. + */ +#define bit_reverse32(u32) __RBIT(u32) + +/*! \brief Reverses the bits of \a u64. + * + * \param u64 U64 of which to reverse the bits. + * + * \return Value resulting from \a u64 with reversed bits. + */ +#define bit_reverse64(u64) ((U64)(((U64)bit_reverse32((U64)(u64) >> 32)) |\ + ((U64)bit_reverse32((U64)(u64)) << 32))) + +//! @} + + +/*! \name Alignment + */ +//! @{ + +/*! \brief Tests alignment of the number \a val with the \a n boundary. + * + * \param val Input value. + * \param n Boundary. + * + * \return \c 1 if the number \a val is aligned with the \a n boundary, else \c 0. + */ +#define Test_align(val, n ) (!Tst_bits( val, (n) - 1 ) ) + +/*! \brief Gets alignment of the number \a val with respect to the \a n boundary. + * + * \param val Input value. + * \param n Boundary. + * + * \return Alignment of the number \a val with respect to the \a n boundary. + */ +#define Get_align( val, n ) ( Rd_bits( val, (n) - 1 ) ) + +/*! \brief Sets alignment of the lvalue number \a lval to \a alg with respect to the \a n boundary. + * + * \param lval Input/output lvalue. + * \param n Boundary. + * \param alg Alignment. + * + * \return New value of \a lval resulting from its alignment set to \a alg with respect to the \a n boundary. + */ +#define Set_align(lval, n, alg) ( Wr_bits(lval, (n) - 1, alg) ) + +/*! \brief Aligns the number \a val with the upper \a n boundary. + * + * \param val Input value. + * \param n Boundary. + * + * \return Value resulting from the number \a val aligned with the upper \a n boundary. + */ +#define Align_up( val, n ) (((val) + ((n) - 1)) & ~((n) - 1)) + +/*! \brief Aligns the number \a val with the lower \a n boundary. + * + * \param val Input value. + * \param n Boundary. + * + * \return Value resulting from the number \a val aligned with the lower \a n boundary. + */ +#define Align_down(val, n ) ( (val) & ~((n) - 1)) + +//! @} + + +/*! \name Mathematics + * + * The same considerations as for clz and ctz apply here but GCC does not + * provide built-in functions to access the assembly instructions abs, min and + * max and it does not produce them by itself in most cases, so two sets of + * macros are defined here: + * - Abs, Min and Max to apply to constant expressions (values known at + * compile time); + * - abs, min and max to apply to non-constant expressions (values unknown at + * compile time), abs is found in stdlib.h. + */ +//! @{ + +/*! \brief Takes the absolute value of \a a. + * + * \param a Input value. + * + * \return Absolute value of \a a. + * + * \note More optimized if only used with values known at compile time. + */ +#define Abs(a) (((a) < 0 ) ? -(a) : (a)) + +/*! \brief Takes the minimal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Minimal value of \a a and \a b. + * + * \note More optimized if only used with values known at compile time. + */ +#define Min(a, b) (((a) < (b)) ? (a) : (b)) + +/*! \brief Takes the maximal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Maximal value of \a a and \a b. + * + * \note More optimized if only used with values known at compile time. + */ +#define Max(a, b) (((a) > (b)) ? (a) : (b)) + +// abs() is already defined by stdlib.h + +/*! \brief Takes the minimal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Minimal value of \a a and \a b. + * + * \note More optimized if only used with values unknown at compile time. + */ +#define min(a, b) Min(a, b) + +/*! \brief Takes the maximal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Maximal value of \a a and \a b. + * + * \note More optimized if only used with values unknown at compile time. + */ +#define max(a, b) Max(a, b) + +//! @} + + +/*! \brief Calls the routine at address \a addr. + * + * It generates a long call opcode. + * + * For example, `Long_call(0x80000000)' generates a software reset on a UC3 if + * it is invoked from the CPU supervisor mode. + * + * \param addr Address of the routine to call. + * + * \note It may be used as a long jump opcode in some special cases. + */ +#define Long_call(addr) ((*(void (*)(void))(addr))()) + + +/*! \name MCU Endianism Handling + * ARM is MCU little endianism. + */ +//! @{ +#define MSB(u16) (((U8 *)&(u16))[1]) //!< Most significant byte of \a u16. +#define LSB(u16) (((U8 *)&(u16))[0]) //!< Least significant byte of \a u16. + +#define MSH(u32) (((U16 *)&(u32))[1]) //!< Most significant half-word of \a u32. +#define LSH(u32) (((U16 *)&(u32))[0]) //!< Least significant half-word of \a u32. +#define MSB0W(u32) (((U8 *)&(u32))[3]) //!< Most significant byte of 1st rank of \a u32. +#define MSB1W(u32) (((U8 *)&(u32))[2]) //!< Most significant byte of 2nd rank of \a u32. +#define MSB2W(u32) (((U8 *)&(u32))[1]) //!< Most significant byte of 3rd rank of \a u32. +#define MSB3W(u32) (((U8 *)&(u32))[0]) //!< Most significant byte of 4th rank of \a u32. +#define LSB3W(u32) MSB0W(u32) //!< Least significant byte of 4th rank of \a u32. +#define LSB2W(u32) MSB1W(u32) //!< Least significant byte of 3rd rank of \a u32. +#define LSB1W(u32) MSB2W(u32) //!< Least significant byte of 2nd rank of \a u32. +#define LSB0W(u32) MSB3W(u32) //!< Least significant byte of 1st rank of \a u32. + +#define MSW(u64) (((U32 *)&(u64))[1]) //!< Most significant word of \a u64. +#define LSW(u64) (((U32 *)&(u64))[0]) //!< Least significant word of \a u64. +#define MSH0(u64) (((U16 *)&(u64))[3]) //!< Most significant half-word of 1st rank of \a u64. +#define MSH1(u64) (((U16 *)&(u64))[2]) //!< Most significant half-word of 2nd rank of \a u64. +#define MSH2(u64) (((U16 *)&(u64))[1]) //!< Most significant half-word of 3rd rank of \a u64. +#define MSH3(u64) (((U16 *)&(u64))[0]) //!< Most significant half-word of 4th rank of \a u64. +#define LSH3(u64) MSH0(u64) //!< Least significant half-word of 4th rank of \a u64. +#define LSH2(u64) MSH1(u64) //!< Least significant half-word of 3rd rank of \a u64. +#define LSH1(u64) MSH2(u64) //!< Least significant half-word of 2nd rank of \a u64. +#define LSH0(u64) MSH3(u64) //!< Least significant half-word of 1st rank of \a u64. +#define MSB0D(u64) (((U8 *)&(u64))[7]) //!< Most significant byte of 1st rank of \a u64. +#define MSB1D(u64) (((U8 *)&(u64))[6]) //!< Most significant byte of 2nd rank of \a u64. +#define MSB2D(u64) (((U8 *)&(u64))[5]) //!< Most significant byte of 3rd rank of \a u64. +#define MSB3D(u64) (((U8 *)&(u64))[4]) //!< Most significant byte of 4th rank of \a u64. +#define MSB4D(u64) (((U8 *)&(u64))[3]) //!< Most significant byte of 5th rank of \a u64. +#define MSB5D(u64) (((U8 *)&(u64))[2]) //!< Most significant byte of 6th rank of \a u64. +#define MSB6D(u64) (((U8 *)&(u64))[1]) //!< Most significant byte of 7th rank of \a u64. +#define MSB7D(u64) (((U8 *)&(u64))[0]) //!< Most significant byte of 8th rank of \a u64. +#define LSB7D(u64) MSB0D(u64) //!< Least significant byte of 8th rank of \a u64. +#define LSB6D(u64) MSB1D(u64) //!< Least significant byte of 7th rank of \a u64. +#define LSB5D(u64) MSB2D(u64) //!< Least significant byte of 6th rank of \a u64. +#define LSB4D(u64) MSB3D(u64) //!< Least significant byte of 5th rank of \a u64. +#define LSB3D(u64) MSB4D(u64) //!< Least significant byte of 4th rank of \a u64. +#define LSB2D(u64) MSB5D(u64) //!< Least significant byte of 3rd rank of \a u64. +#define LSB1D(u64) MSB6D(u64) //!< Least significant byte of 2nd rank of \a u64. +#define LSB0D(u64) MSB7D(u64) //!< Least significant byte of 1st rank of \a u64. + +#define BE16(x) swap16(x) +#define LE16(x) (x) + +#define le16_to_cpu(x) (x) +#define cpu_to_le16(x) (x) +#define LE16_TO_CPU(x) (x) +#define CPU_TO_LE16(x) (x) + +#define be16_to_cpu(x) swap16(x) +#define cpu_to_be16(x) swap16(x) +#define BE16_TO_CPU(x) swap16(x) +#define CPU_TO_BE16(x) swap16(x) + +#define le32_to_cpu(x) (x) +#define cpu_to_le32(x) (x) +#define LE32_TO_CPU(x) (x) +#define CPU_TO_LE32(x) (x) + +#define be32_to_cpu(x) swap32(x) +#define cpu_to_be32(x) swap32(x) +#define BE32_TO_CPU(x) swap32(x) +#define CPU_TO_BE32(x) swap32(x) +//! @} + + +/*! \name Endianism Conversion + * + * The same considerations as for clz and ctz apply here but GCC's + * __builtin_bswap_32 and __builtin_bswap_64 do not behave like macros when + * applied to constant expressions, so two sets of macros are defined here: + * - Swap16, Swap32 and Swap64 to apply to constant expressions (values known + * at compile time); + * - swap16, swap32 and swap64 to apply to non-constant expressions (values + * unknown at compile time). + */ +//! @{ + +/*! \brief Toggles the endianism of \a u16 (by swapping its bytes). + * + * \param u16 U16 of which to toggle the endianism. + * + * \return Value resulting from \a u16 with toggled endianism. + * + * \note More optimized if only used with values known at compile time. + */ +#define Swap16(u16) ((U16)(((U16)(u16) >> 8) |\ + ((U16)(u16) << 8))) + +/*! \brief Toggles the endianism of \a u32 (by swapping its bytes). + * + * \param u32 U32 of which to toggle the endianism. + * + * \return Value resulting from \a u32 with toggled endianism. + * + * \note More optimized if only used with values known at compile time. + */ +#define Swap32(u32) ((U32)(((U32)Swap16((U32)(u32) >> 16)) |\ + ((U32)Swap16((U32)(u32)) << 16))) + +/*! \brief Toggles the endianism of \a u64 (by swapping its bytes). + * + * \param u64 U64 of which to toggle the endianism. + * + * \return Value resulting from \a u64 with toggled endianism. + * + * \note More optimized if only used with values known at compile time. + */ +#define Swap64(u64) ((U64)(((U64)Swap32((U64)(u64) >> 32)) |\ + ((U64)Swap32((U64)(u64)) << 32))) + +/*! \brief Toggles the endianism of \a u16 (by swapping its bytes). + * + * \param u16 U16 of which to toggle the endianism. + * + * \return Value resulting from \a u16 with toggled endianism. + * + * \note More optimized if only used with values unknown at compile time. + */ +#define swap16(u16) Swap16(u16) + +/*! \brief Toggles the endianism of \a u32 (by swapping its bytes). + * + * \param u32 U32 of which to toggle the endianism. + * + * \return Value resulting from \a u32 with toggled endianism. + * + * \note More optimized if only used with values unknown at compile time. + */ +#if (defined __GNUC__) +# define swap32(u32) ((U32)__builtin_bswap32((U32)(u32))) +#else +# define swap32(u32) Swap32(u32) +#endif + +/*! \brief Toggles the endianism of \a u64 (by swapping its bytes). + * + * \param u64 U64 of which to toggle the endianism. + * + * \return Value resulting from \a u64 with toggled endianism. + * + * \note More optimized if only used with values unknown at compile time. + */ +#if (defined __GNUC__) +# define swap64(u64) ((U64)__builtin_bswap64((U64)(u64))) +#else +# define swap64(u64) ((U64)(((U64)swap32((U64)(u64) >> 32)) |\ + ((U64)swap32((U64)(u64)) << 32))) +#endif + +//! @} + + +/*! \name Target Abstraction + */ +//! @{ + +#define _GLOBEXT_ extern //!< extern storage-class specifier. +#define _CONST_TYPE_ const //!< const type qualifier. +#define _MEM_TYPE_SLOW_ //!< Slow memory type. +#define _MEM_TYPE_MEDFAST_ //!< Fairly fast memory type. +#define _MEM_TYPE_FAST_ //!< Fast memory type. + +typedef U8 Byte; //!< 8-bit unsigned integer. + +#define memcmp_ram2ram memcmp //!< Target-specific memcmp of RAM to RAM. +#define memcmp_code2ram memcmp //!< Target-specific memcmp of RAM to NVRAM. +#define memcpy_ram2ram memcpy //!< Target-specific memcpy from RAM to RAM. +#define memcpy_code2ram memcpy //!< Target-specific memcpy from NVRAM to RAM. + +#define LSB0(u32) LSB0W(u32) //!< Least significant byte of 1st rank of \a u32. +#define LSB1(u32) LSB1W(u32) //!< Least significant byte of 2nd rank of \a u32. +#define LSB2(u32) LSB2W(u32) //!< Least significant byte of 3rd rank of \a u32. +#define LSB3(u32) LSB3W(u32) //!< Least significant byte of 4th rank of \a u32. +#define MSB3(u32) MSB3W(u32) //!< Most significant byte of 4th rank of \a u32. +#define MSB2(u32) MSB2W(u32) //!< Most significant byte of 3rd rank of \a u32. +#define MSB1(u32) MSB1W(u32) //!< Most significant byte of 2nd rank of \a u32. +#define MSB0(u32) MSB0W(u32) //!< Most significant byte of 1st rank of \a u32. + +//! @} + +/** + * \brief Calculate \f$ \left\lceil \frac{a}{b} \right\rceil \f$ using + * integer arithmetic. + * + * \param a An integer + * \param b Another integer + * + * \return (\a a / \a b) rounded up to the nearest integer. + */ +#define div_ceil(a, b) (((a) + (b) - 1) / (b)) + +#endif // #ifndef __ASSEMBLY__ + + +#if defined(__ICCARM__) +#define SHORTENUM __packed +#elif defined(__GNUC__) +#define SHORTENUM __attribute__((packed)) +#endif + +/* No operation */ +#if defined(__ICCARM__) +#define nop() __no_operation() +#elif defined(__GNUC__) +#define nop() (__NOP()) +#endif + +#define FLASH_DECLARE(x) const x +#define FLASH_EXTERN(x) extern const x +#define PGM_READ_BYTE(x) *(x) +#define PGM_READ_WORD(x) *(x) +#define PGM_READ_DWORD(x) *(x) +#define MEMCPY_ENDIAN memcpy +#define PGM_READ_BLOCK(dst, src, len) memcpy((dst), (src), (len)) + +/*Defines the Flash Storage for the request and response of MAC*/ +#define CMD_ID_OCTET (0) + +/* Converting of values from CPU endian to little endian. */ +#define CPU_ENDIAN_TO_LE16(x) (x) +#define CPU_ENDIAN_TO_LE32(x) (x) +#define CPU_ENDIAN_TO_LE64(x) (x) + +/* Converting of values from little endian to CPU endian. */ +#define LE16_TO_CPU_ENDIAN(x) (x) +#define LE32_TO_CPU_ENDIAN(x) (x) +#define LE64_TO_CPU_ENDIAN(x) (x) + +/* Converting of constants from little endian to CPU endian. */ +#define CLE16_TO_CPU_ENDIAN(x) (x) +#define CLE32_TO_CPU_ENDIAN(x) (x) +#define CLE64_TO_CPU_ENDIAN(x) (x) + +/* Converting of constants from CPU endian to little endian. */ +#define CCPU_ENDIAN_TO_LE16(x) (x) +#define CCPU_ENDIAN_TO_LE32(x) (x) +#define CCPU_ENDIAN_TO_LE64(x) (x) + +#define ADDR_COPY_DST_SRC_16(dst, src) ((dst) = (src)) +#define ADDR_COPY_DST_SRC_64(dst, src) ((dst) = (src)) + +/** + * @brief Converts a 64-Bit value into a 8 Byte array + * + * @param[in] value 64-Bit value + * @param[out] data Pointer to the 8 Byte array to be updated with 64-Bit value + * @ingroup apiPalApi + */ +static inline void convert_64_bit_to_byte_array(uint64_t value, uint8_t *data) +{ + uint8_t val_index = 0; + + while (val_index < 8) + { + data[val_index++] = value & 0xFF; + value = value >> 8; + } +} + +/** + * @brief Converts a 16-Bit value into a 2 Byte array + * + * @param[in] value 16-Bit value + * @param[out] data Pointer to the 2 Byte array to be updated with 16-Bit value + * @ingroup apiPalApi + */ +static inline void convert_16_bit_to_byte_array(uint16_t value, uint8_t *data) +{ + data[0] = value & 0xFF; + data[1] = (value >> 8) & 0xFF; +} + +/* Converts a 16-Bit value into a 2 Byte array */ +static inline void convert_spec_16_bit_to_byte_array(uint16_t value, uint8_t *data) +{ + data[0] = value & 0xFF; + data[1] = (value >> 8) & 0xFF; +} + +/* Converts a 16-Bit value into a 2 Byte array */ +static inline void convert_16_bit_to_byte_address(uint16_t value, uint8_t *data) +{ + data[0] = value & 0xFF; + data[1] = (value >> 8) & 0xFF; +} + +/* + * @brief Converts a 2 Byte array into a 16-Bit value + * + * @param data Specifies the pointer to the 2 Byte array + * + * @return 16-Bit value + * @ingroup apiPalApi + */ +static inline uint16_t convert_byte_array_to_16_bit(uint8_t *data) +{ + return (data[0] | ((uint16_t)data[1] << 8)); +} + +/* Converts a 8 Byte array into a 32-Bit value */ +static inline uint32_t convert_byte_array_to_32_bit(uint8_t *data) +{ + union + { + uint32_t u32; + uint8_t u8[8]; + }long_addr; + uint8_t index; + for (index = 0; index < 4; index++) + { + long_addr.u8[index] = *data++; + } + return long_addr.u32; +} + +/** + * @brief Converts a 8 Byte array into a 64-Bit value + * + * @param data Specifies the pointer to the 8 Byte array + * + * @return 64-Bit value + * @ingroup apiPalApi + */ +static inline uint64_t convert_byte_array_to_64_bit(uint8_t *data) +{ + union + { + uint64_t u64; + uint8_t u8[8]; + } long_addr; + + uint8_t val_index; + + for (val_index = 0; val_index < 8; val_index++) + { + long_addr.u8[val_index] = *data++; + } + + return long_addr.u64; +} +/** + * \} + */ + +#endif /* UTILS_COMPILER_H */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/header_files/io.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/header_files/io.h new file mode 100644 index 0000000..a79c646 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/header_files/io.h @@ -0,0 +1,157 @@ +/** + * \file + * + * \brief Arch file for SAM. + * + * This file defines common SAM series. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _SAM_IO_ +#define _SAM_IO_ + +/* SAM3 family */ + +/* SAM3S series */ +#if (SAM3S) +# if (SAM3S8 || SAM3SD8) +# include "sam3s8.h" +# else +# include "sam3s.h" +# endif +#endif + +/* SAM3U series */ +#if (SAM3U) +# include "sam3u.h" +#endif + +/* SAM3N series */ +#if (SAM3N) +# include "sam3n.h" +#endif + +/* SAM3XA series */ +#if (SAM3XA) +# include "sam3xa.h" +#endif + +/* SAM4S series */ +#if (SAM4S) +# include "sam4s.h" +#endif + +/* SAM4L series */ +#if (SAM4L) +# include "sam4l.h" +#endif + +/* SAM4E series */ +#if (SAM4E) +# include "sam4e.h" +#endif + +/* SAM4N series */ +#if (SAM4N) +# include "sam4n.h" +#endif + +/* SAM4C series */ +#if (SAM4C) +# include "sam4c.h" +#endif + +/* SAM4CM series */ +#if (SAM4CM) +# if (SAM4CMP32 || SAM4CMS32) +# include "sam4cm32.h" +# else +# include "sam4cm.h" +# endif +#endif + +/* SAM4CP series */ +#if (SAM4CP) +# include "sam4cp.h" +#endif + +/* SAMG51 series */ +#if (SAMG51) +# include "samg51.h" +#endif + +/* SAMG53 series */ +#if (SAMG53) +# include "samg53.h" +#endif + +/* SAMG54 series */ +#if (SAMG54) +# include "samg54.h" +#endif + +/* SAMG55 series */ +#if (SAMG55) +# include "samg55.h" +#endif + +/* SAMV71 series */ +#if (SAMV71) +# include "samv71.h" +#endif + +/* SAMV70 series */ +#if (SAMV70) +# include "samv70.h" +#endif + +/* SAME70 series */ +#if (SAME70) +# include "same70.h" +#endif + +/* SAMS70 series */ +#if (SAMS70) +# include "sams70.h" +#endif + +#endif /* _SAM_IO_ */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/linker_scripts/sam3x/sam3x8/gcc/flash.ld b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/linker_scripts/sam3x/sam3x8/gcc/flash.ld new file mode 100644 index 0000000..a399f0e --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/linker_scripts/sam3x/sam3x8/gcc/flash.ld @@ -0,0 +1,160 @@ +/** + * \file + * + * \brief Flash Linker script for SAM. + * + * Copyright (c) 2011-2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00080000, LENGTH = 0x00080000 /* Flash, 512K */ + sram0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* sram0, 64K */ + sram1 (rwx) : ORIGIN = 0x20080000, LENGTH = 0x00008000 /* sram1, 32K */ + ram (rwx) : ORIGIN = 0x20070000, LENGTH = 0x00018000 /* sram, 96K */ +/* ram (rwx) : ORIGIN = ORIGIN( sram1 )-LENGTH( sram0 ), LENGTH = LENGTH( sram0 )+LENGTH( sram1 ) */ /* sram, 96K */ +} + +/* The stack size used by the application. NOTE: you need to adjust */ +__stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 0x2000; +__ram_end__ = ORIGIN(ram) + LENGTH(ram) - 4; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + __stack_size__; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/make/Makefile.sam.in b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/make/Makefile.sam.in new file mode 100644 index 0000000..23c6697 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/make/Makefile.sam.in @@ -0,0 +1,496 @@ +# List of available make goals: +# +# all Default target, builds the project +# clean Clean up the project +# rebuild Rebuild the project +# debug_flash Builds the project and debug in flash +# debug_sram Builds the project and debug in sram +# +# doc Build the documentation +# cleandoc Clean up the documentation +# rebuilddoc Rebuild the documentation +# +# \file +# +# Copyright (c) 2011 - 2013 Atmel Corporation. All rights reserved. +# +# \asf_license_start +# +# \page License +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# 3. The name of Atmel may not be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# 4. This software may only be redistributed and used in connection with an +# Atmel microcontroller product. +# +# THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +# EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR +# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +# STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +# \asf_license_stop +# + +# Include the config.mk file from the current working path, e.g., where the +# user called make. +include config.mk + +# Tool to use to generate documentation from the source code +DOCGEN ?= doxygen + +# Look for source files relative to the top-level source directory +VPATH := $(PRJ_PATH) + +# Output target file +project_type := $(PROJECT_TYPE) + +# Output target file +ifeq ($(project_type),flash) +target := $(TARGET_FLASH) +linker_script := $(PRJ_PATH)/$(LINKER_SCRIPT_FLASH) +debug_script := $(PRJ_PATH)/$(DEBUG_SCRIPT_FLASH) +else +target := $(TARGET_SRAM) +linker_script := $(PRJ_PATH)/$(LINKER_SCRIPT_SRAM) +debug_script := $(PRJ_PATH)/$(DEBUG_SCRIPT_SRAM) +endif + +# Output project name (target name minus suffix) +project := $(basename $(target)) + +# Output target file (typically ELF or static library) +ifeq ($(suffix $(target)),.a) +target_type := lib +else +ifeq ($(suffix $(target)),.elf) +target_type := elf +else +$(error "Target type $(target_type) is not supported") +endif +endif + +# Allow override of operating system detection. The user can add OS=Linux or +# OS=Windows on the command line to explicit set the host OS. +# +# This allows to work around broken uname utility on certain systems. +ifdef OS + ifeq ($(strip $(OS)), Linux) + os_type := Linux + endif + ifeq ($(strip $(OS)), Windows) + os_type := windows32_64 + endif +endif + +os_type ?= $(strip $(shell uname)) + +ifeq ($(os_type),windows32) +os := Windows +else +ifeq ($(os_type),windows64) +os := Windows +else +ifeq ($(os_type),windows32_64) +os ?= Windows +else +ifeq ($(os_type),) +os := Windows +else +# Default to Linux style operating system. Both Cygwin and mingw are fully +# compatible (for this Makefile) with Linux. +os := Linux +endif +endif +endif +endif + +# Output documentation directory and configuration file. +docdir := ../doxygen/html +doccfg := ../doxygen/doxyfile.doxygen + +CROSS ?= arm-none-eabi- +AR := $(CROSS)ar +AS := $(CROSS)as +CC := $(CROSS)gcc +CPP := $(CROSS)gcc -E +CXX := $(CROSS)g++ +LD := $(CROSS)g++ +NM := $(CROSS)nm +OBJCOPY := $(CROSS)objcopy +OBJDUMP := $(CROSS)objdump +SIZE := $(CROSS)size +GDB := $(CROSS)gdb + +RM := rm +ifeq ($(os),Windows) +RMDIR := rmdir /S /Q +else +RMDIR := rmdir -p --ignore-fail-on-non-empty +endif + +# On Windows, we need to override the shell to force the use of cmd.exe +ifeq ($(os),Windows) +SHELL := cmd +endif + +# Strings for beautifying output +MSG_CLEAN_FILES = "RM *.o *.d" +MSG_CLEAN_DIRS = "RMDIR $(strip $(clean-dirs))" +MSG_CLEAN_DOC = "RMDIR $(docdir)" +MSG_MKDIR = "MKDIR $(dir $@)" + +MSG_INFO = "INFO " +MSG_PREBUILD = "PREBUILD $(PREBUILD_CMD)" +MSG_POSTBUILD = "POSTBUILD $(POSTBUILD_CMD)" + +MSG_ARCHIVING = "AR $@" +MSG_ASSEMBLING = "AS $@" +MSG_BINARY_IMAGE = "OBJCOPY $@" +MSG_COMPILING = "CC $@" +MSG_COMPILING_CXX = "CXX $@" +MSG_EXTENDED_LISTING = "OBJDUMP $@" +MSG_IHEX_IMAGE = "OBJCOPY $@" +MSG_LINKING = "LN $@" +MSG_PREPROCESSING = "CPP $@" +MSG_SIZE = "SIZE $@" +MSG_SYMBOL_TABLE = "NM $@" + +MSG_GENERATING_DOC = "DOXYGEN $(docdir)" + +# Don't use make's built-in rules and variables +MAKEFLAGS += -rR + +# Don't print 'Entering directory ...' +MAKEFLAGS += --no-print-directory + +# Function for reversing the order of a list +reverse = $(if $(1),$(call reverse,$(wordlist 2,$(words $(1)),$(1)))) $(firstword $(1)) + +# Hide command output by default, but allow the user to override this +# by adding V=1 on the command line. +# +# This is inspired by the Kbuild system used by the Linux kernel. +ifdef V + ifeq ("$(origin V)", "command line") + VERBOSE = $(V) + endif +endif +ifndef VERBOSE + VERBOSE = 0 +endif + +ifeq ($(VERBOSE), 1) + Q = +else + Q = @ +endif + +arflags-gnu-y := $(ARFLAGS) +asflags-gnu-y := $(ASFLAGS) +cflags-gnu-y := $(CFLAGS) +cxxflags-gnu-y := $(CXXFLAGS) +cppflags-gnu-y := $(CPPFLAGS) +cpuflags-gnu-y := +dbgflags-gnu-y := $(DBGFLAGS) +libflags-gnu-y := $(foreach LIB,$(LIBS),-l$(LIB)) +ldflags-gnu-y := $(LDFLAGS) +flashflags-gnu-y := +clean-files := +clean-dirs := + +clean-files += $(wildcard $(target) $(project).map) +clean-files += $(wildcard $(project).hex $(project).bin) +clean-files += $(wildcard $(project).lss $(project).sym) +clean-files += $(wildcard $(build)) + +# Use pipes instead of temporary files for communication between processes +cflags-gnu-y += -pipe +asflags-gnu-y += -pipe +ldflags-gnu-y += -pipe + +# Archiver flags. +arflags-gnu-y += rcs + +# Always enable warnings. And be very careful about implicit +# declarations. +cflags-gnu-y += -Wall -Wstrict-prototypes -Wmissing-prototypes +cflags-gnu-y += -Werror-implicit-function-declaration +cxxflags-gnu-y += -Wall +# IAR doesn't allow arithmetic on void pointers, so warn about that. +cflags-gnu-y += -Wpointer-arith +cxxflags-gnu-y += -Wpointer-arith + +# Preprocessor flags. +cppflags-gnu-y += $(foreach INC,$(addprefix $(PRJ_PATH)/,$(INC_PATH)),-I$(INC)) +asflags-gnu-y += $(foreach INC,$(addprefix $(PRJ_PATH)/,$(INC_PATH)),'-Wa,-I$(INC)') + +# CPU specific flags. +cpuflags-gnu-y += -mcpu=$(ARCH) -mthumb -D=__$(PART)__ + +# Dependency file flags. +depflags = -MD -MP -MQ $@ + +# Debug specific flags. +ifdef BUILD_DEBUG_LEVEL +dbgflags-gnu-y += -g$(BUILD_DEBUG_LEVEL) +else +dbgflags-gnu-y += -g3 +endif + +# Optimization specific flags. +ifdef BUILD_OPTIMIZATION +optflags-gnu-y = -O$(BUILD_OPTIMIZATION) +else +optflags-gnu-y = $(OPTIMIZATION) +endif + +# Always preprocess assembler files. +asflags-gnu-y += -x assembler-with-cpp +# Compile C files using the GNU99 standard. +cflags-gnu-y += -std=gnu99 +# Compile C++ files using the GNU++98 standard. +cxxflags-gnu-y += -std=gnu++98 + +# Don't use strict aliasing (very common in embedded applications). +cflags-gnu-y += -fno-strict-aliasing +cxxflags-gnu-y += -fno-strict-aliasing + +# Separate each function and data into its own separate section to allow +# garbage collection of unused sections. +cflags-gnu-y += -ffunction-sections -fdata-sections +cxxflags-gnu-y += -ffunction-sections -fdata-sections + +# Various cflags. +cflags-gnu-y += -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int +cflags-gnu-y += -Wmain -Wparentheses +cflags-gnu-y += -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused +cflags-gnu-y += -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef +cflags-gnu-y += -Wshadow -Wbad-function-cast -Wwrite-strings +cflags-gnu-y += -Wsign-compare -Waggregate-return +cflags-gnu-y += -Wmissing-declarations +cflags-gnu-y += -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations +cflags-gnu-y += -Wpacked -Wredundant-decls -Wnested-externs -Winline -Wlong-long +cflags-gnu-y += -Wunreachable-code +cflags-gnu-y += -Wcast-align +cflags-gnu-y += --param max-inline-insns-single=500 + +# Garbage collect unreferred sections when linking. +ldflags-gnu-y += -Wl,--gc-sections + +# Use the linker script if provided by the project. +ifneq ($(strip $(linker_script)),) +ldflags-gnu-y += -Wl,-T $(linker_script) +endif + +# Output a link map file and a cross reference table +ldflags-gnu-y += -Wl,-Map=$(project).map,--cref + +# Add library search paths relative to the top level directory. +ldflags-gnu-y += $(foreach _LIB_PATH,$(addprefix $(PRJ_PATH)/,$(LIB_PATH)),-L$(_LIB_PATH)) + +a_flags = $(cpuflags-gnu-y) $(depflags) $(cppflags-gnu-y) $(asflags-gnu-y) -D__ASSEMBLY__ +c_flags = $(cpuflags-gnu-y) $(dbgflags-gnu-y) $(depflags) $(optflags-gnu-y) $(cppflags-gnu-y) $(cflags-gnu-y) +cxx_flags= $(cpuflags-gnu-y) $(dbgflags-gnu-y) $(depflags) $(optflags-gnu-y) $(cppflags-gnu-y) $(cxxflags-gnu-y) +l_flags = -Wl,--entry=Reset_Handler -Wl,--cref $(cpuflags-gnu-y) $(optflags-gnu-y) $(ldflags-gnu-y) +ar_flags = $(arflags-gnu-y) + +# Source files list and part informations must already be included before +# running this makefile + +# If a custom build directory is specified, use it -- force trailing / in directory name. +ifdef BUILD_DIR + build-dir := $(dir $(BUILD_DIR))$(if $(notdir $(BUILD_DIR)),$(notdir $(BUILD_DIR))/) +else + build-dir = +endif + +# Create object files list from source files list. +obj-y := $(addprefix $(build-dir), $(addsuffix .o,$(basename $(CSRCS) $(ASSRCS)))) +# Create dependency files list from source files list. +dep-files := $(wildcard $(foreach f,$(obj-y),$(basename $(f)).d)) + +clean-files += $(wildcard $(obj-y)) +clean-files += $(dep-files) + +clean-dirs += $(call reverse,$(sort $(wildcard $(dir $(obj-y))))) + +# Default target. +.PHONY: all +ifeq ($(project_type),all) +all: + $(MAKE) all PROJECT_TYPE=flash + $(MAKE) all PROJECT_TYPE=sram +else +ifeq ($(target_type),lib) +all: $(target) $(project).lss $(project).sym +else +ifeq ($(target_type),elf) +all: prebuild $(target) $(project).lss $(project).sym $(project).hex $(project).bin postbuild +endif +endif +endif + +prebuild: +ifneq ($(strip $(PREBUILD_CMD)),) + @echo $(MSG_PREBUILD) + $(Q)$(PREBUILD_CMD) +endif + +postbuild: +ifneq ($(strip $(POSTBUILD_CMD)),) + @echo $(MSG_POSTBUILD) + $(Q)$(POSTBUILD_CMD) +endif + +# Clean up the project. +.PHONY: clean +clean: + @$(if $(strip $(clean-files)),echo $(MSG_CLEAN_FILES)) + $(if $(strip $(clean-files)),$(Q)$(RM) $(clean-files),) + @$(if $(strip $(clean-dirs)),echo $(MSG_CLEAN_DIRS)) +# Remove created directories, and make sure we only remove existing +# directories, since recursive rmdir might help us a bit on the way. +ifeq ($(os),Windows) + $(Q)$(if $(strip $(clean-dirs)), \ + $(RMDIR) $(strip $(subst /,\,$(clean-dirs)))) +else + $(Q)$(if $(strip $(clean-dirs)), \ + for directory in $(strip $(clean-dirs)); do \ + if [ -d "$$directory" ]; then \ + $(RMDIR) $$directory; \ + fi \ + done \ + ) +endif + +# Rebuild the project. +.PHONY: rebuild +rebuild: clean all + +# Debug the project in flash. +.PHONY: debug_flash +debug_flash: all + $(GDB) -x "$(PRJ_PATH)/$(DEBUG_SCRIPT_FLASH)" -ex "reset" -readnow -se $(TARGET_FLASH) + +# Debug the project in sram. +.PHONY: debug_sram +debug_sram: all + $(GDB) -x "$(PRJ_PATH)/$(DEBUG_SCRIPT_SRAM)" -ex "reset" -readnow -se $(TARGET_SRAM) + +.PHONY: objfiles +objfiles: $(obj-y) + +# Create object files from C source files. +$(build-dir)%.o: %.c $(MAKEFILE_PATH) config.mk + $(Q)test -d $(dir $@) || echo $(MSG_MKDIR) +ifeq ($(os),Windows) + $(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@)) +else + $(Q)test -d $(dir $@) || mkdir -p $(dir $@) +endif + @echo $(MSG_COMPILING) + $(Q)$(CC) $(c_flags) -c $< -o $@ + +# Create object files from C++ source files. +$(build-dir)%.o: %.cpp $(MAKEFILE_PATH) config.mk + $(Q)test -d $(dir $@) || echo $(MSG_MKDIR) +ifeq ($(os),Windows) + $(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@)) +else + $(Q)test -d $(dir $@) || mkdir -p $(dir $@) +endif + @echo $(MSG_COMPILING_CXX) + $(Q)$(CXX) $(cxx_flags) -c $< -o $@ + +# Preprocess and assemble: create object files from assembler source files. +$(build-dir)%.o: %.S $(MAKEFILE_PATH) config.mk + $(Q)test -d $(dir $@) || echo $(MSG_MKDIR) +ifeq ($(os),Windows) + $(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@)) +else + $(Q)test -d $(dir $@) || mkdir -p $(dir $@) +endif + @echo $(MSG_ASSEMBLING) + $(Q)$(CC) $(a_flags) -c $< -o $@ + +# Include all dependency files to add depedency to all header files in use. +include $(dep-files) + +ifeq ($(target_type),lib) +# Archive object files into an archive +$(target): $(MAKEFILE_PATH) config.mk $(obj-y) + @echo $(MSG_ARCHIVING) + $(Q)$(AR) $(ar_flags) $@ $(obj-y) + @echo $(MSG_SIZE) + $(Q)$(SIZE) -Bxt $@ +else +ifeq ($(target_type),elf) +# Link the object files into an ELF file. Also make sure the target is rebuilt +# if the common Makefile.sam.in or project config.mk is changed. +$(target): $(linker_script) $(MAKEFILE_PATH) config.mk $(obj-y) + @echo $(MSG_LINKING) + $(Q)$(LD) $(l_flags) $(obj-y) $(libflags-gnu-y) -o $@ + @echo $(MSG_SIZE) + $(Q)$(SIZE) -Ax $@ + $(Q)$(SIZE) -Bx $@ +endif +endif + +# Create extended function listing from target output file. +%.lss: $(target) + @echo $(MSG_EXTENDED_LISTING) + $(Q)$(OBJDUMP) -h -S $< > $@ + +# Create symbol table from target output file. +%.sym: $(target) + @echo $(MSG_SYMBOL_TABLE) + $(Q)$(NM) -n $< > $@ + +# Create Intel HEX image from ELF output file. +%.hex: $(target) + @echo $(MSG_IHEX_IMAGE) + $(Q)$(OBJCOPY) -O ihex $(flashflags-gnu-y) $< $@ + +# Create binary image from ELF output file. +%.bin: $(target) + @echo $(MSG_BINARY_IMAGE) + $(Q)$(OBJCOPY) -O binary $< $@ + +# Provide information about the detected host operating system. +.SECONDARY: info-os +info-os: + @echo $(MSG_INFO)$(os) build host detected + +# Build Doxygen generated documentation. +.PHONY: doc +doc: + @echo $(MSG_GENERATING_DOC) + $(Q)cd $(dir $(doccfg)) && $(DOCGEN) $(notdir $(doccfg)) + +# Clean Doxygen generated documentation. +.PHONY: cleandoc +cleandoc: + @$(if $(wildcard $(docdir)),echo $(MSG_CLEAN_DOC)) + $(Q)$(if $(wildcard $(docdir)),$(RM) --recursive $(docdir)) + +# Rebuild the Doxygen generated documentation. +.PHONY: rebuilddoc +rebuilddoc: cleandoc doc diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/preprocessor/mrepeat.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/preprocessor/mrepeat.h new file mode 100644 index 0000000..5a2017b --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/preprocessor/mrepeat.h @@ -0,0 +1,339 @@ +/** + * \file + * + * \brief Preprocessor macro repeating utils. + * + * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _MREPEAT_H_ +#define _MREPEAT_H_ + +/** + * \defgroup group_sam_utils_mrepeat Preprocessor - Macro Repeat + * + * \ingroup group_sam_utils + * + * \{ + */ + +#include "preprocessor.h" + + +//! Maximal number of repetitions supported by MREPEAT. +#define MREPEAT_LIMIT 256 + +/*! \brief Macro repeat. + * + * This macro represents a horizontal repetition construct. + * + * \param count The number of repetitious calls to macro. Valid values range from 0 to MREPEAT_LIMIT. + * \param macro A binary operation of the form macro(n, data). This macro is expanded by MREPEAT with + * the current repetition number and the auxiliary data argument. + * \param data Auxiliary data passed to macro. + * + * \return macro(0, data) macro(1, data) ... macro(count - 1, data) + */ +#define MREPEAT(count, macro, data) TPASTE2(MREPEAT, count)(macro, data) + +#define MREPEAT0( macro, data) +#define MREPEAT1( macro, data) MREPEAT0( macro, data) macro( 0, data) +#define MREPEAT2( macro, data) MREPEAT1( macro, data) macro( 1, data) +#define MREPEAT3( macro, data) MREPEAT2( macro, data) macro( 2, data) +#define MREPEAT4( macro, data) MREPEAT3( macro, data) macro( 3, data) +#define MREPEAT5( macro, data) MREPEAT4( macro, data) macro( 4, data) +#define MREPEAT6( macro, data) MREPEAT5( macro, data) macro( 5, data) +#define MREPEAT7( macro, data) MREPEAT6( macro, data) macro( 6, data) +#define MREPEAT8( macro, data) MREPEAT7( macro, data) macro( 7, data) +#define MREPEAT9( macro, data) MREPEAT8( macro, data) macro( 8, data) +#define MREPEAT10( macro, data) MREPEAT9( macro, data) macro( 9, data) +#define MREPEAT11( macro, data) MREPEAT10( macro, data) macro( 10, data) +#define MREPEAT12( macro, data) MREPEAT11( macro, data) macro( 11, data) +#define MREPEAT13( macro, data) MREPEAT12( macro, data) macro( 12, data) +#define MREPEAT14( macro, data) MREPEAT13( macro, data) macro( 13, data) +#define MREPEAT15( macro, data) MREPEAT14( macro, data) macro( 14, data) +#define MREPEAT16( macro, data) MREPEAT15( macro, data) macro( 15, data) +#define MREPEAT17( macro, data) MREPEAT16( macro, data) macro( 16, data) +#define MREPEAT18( macro, data) MREPEAT17( macro, data) macro( 17, data) +#define MREPEAT19( macro, data) MREPEAT18( macro, data) macro( 18, data) +#define MREPEAT20( macro, data) MREPEAT19( macro, data) macro( 19, data) +#define MREPEAT21( macro, data) MREPEAT20( macro, data) macro( 20, data) +#define MREPEAT22( macro, data) MREPEAT21( macro, data) macro( 21, data) +#define MREPEAT23( macro, data) MREPEAT22( macro, data) macro( 22, data) +#define MREPEAT24( macro, data) MREPEAT23( macro, data) macro( 23, data) +#define MREPEAT25( macro, data) MREPEAT24( macro, data) macro( 24, data) +#define MREPEAT26( macro, data) MREPEAT25( macro, data) macro( 25, data) +#define MREPEAT27( macro, data) MREPEAT26( macro, data) macro( 26, data) +#define MREPEAT28( macro, data) MREPEAT27( macro, data) macro( 27, data) +#define MREPEAT29( macro, data) MREPEAT28( macro, data) macro( 28, data) +#define MREPEAT30( macro, data) MREPEAT29( macro, data) macro( 29, data) +#define MREPEAT31( macro, data) MREPEAT30( macro, data) macro( 30, data) +#define MREPEAT32( macro, data) MREPEAT31( macro, data) macro( 31, data) +#define MREPEAT33( macro, data) MREPEAT32( macro, data) macro( 32, data) +#define MREPEAT34( macro, data) MREPEAT33( macro, data) macro( 33, data) +#define MREPEAT35( macro, data) MREPEAT34( macro, data) macro( 34, data) +#define MREPEAT36( macro, data) MREPEAT35( macro, data) macro( 35, data) +#define MREPEAT37( macro, data) MREPEAT36( macro, data) macro( 36, data) +#define MREPEAT38( macro, data) MREPEAT37( macro, data) macro( 37, data) +#define MREPEAT39( macro, data) MREPEAT38( macro, data) macro( 38, data) +#define MREPEAT40( macro, data) MREPEAT39( macro, data) macro( 39, data) +#define MREPEAT41( macro, data) MREPEAT40( macro, data) macro( 40, data) +#define MREPEAT42( macro, data) MREPEAT41( macro, data) macro( 41, data) +#define MREPEAT43( macro, data) MREPEAT42( macro, data) macro( 42, data) +#define MREPEAT44( macro, data) MREPEAT43( macro, data) macro( 43, data) +#define MREPEAT45( macro, data) MREPEAT44( macro, data) macro( 44, data) +#define MREPEAT46( macro, data) MREPEAT45( macro, data) macro( 45, data) +#define MREPEAT47( macro, data) MREPEAT46( macro, data) macro( 46, data) +#define MREPEAT48( macro, data) MREPEAT47( macro, data) macro( 47, data) +#define MREPEAT49( macro, data) MREPEAT48( macro, data) macro( 48, data) +#define MREPEAT50( macro, data) MREPEAT49( macro, data) macro( 49, data) +#define MREPEAT51( macro, data) MREPEAT50( macro, data) macro( 50, data) +#define MREPEAT52( macro, data) MREPEAT51( macro, data) macro( 51, data) +#define MREPEAT53( macro, data) MREPEAT52( macro, data) macro( 52, data) +#define MREPEAT54( macro, data) MREPEAT53( macro, data) macro( 53, data) +#define MREPEAT55( macro, data) MREPEAT54( macro, data) macro( 54, data) +#define MREPEAT56( macro, data) MREPEAT55( macro, data) macro( 55, data) +#define MREPEAT57( macro, data) MREPEAT56( macro, data) macro( 56, data) +#define MREPEAT58( macro, data) MREPEAT57( macro, data) macro( 57, data) +#define MREPEAT59( macro, data) MREPEAT58( macro, data) macro( 58, data) +#define MREPEAT60( macro, data) MREPEAT59( macro, data) macro( 59, data) +#define MREPEAT61( macro, data) MREPEAT60( macro, data) macro( 60, data) +#define MREPEAT62( macro, data) MREPEAT61( macro, data) macro( 61, data) +#define MREPEAT63( macro, data) MREPEAT62( macro, data) macro( 62, data) +#define MREPEAT64( macro, data) MREPEAT63( macro, data) macro( 63, data) +#define MREPEAT65( macro, data) MREPEAT64( macro, data) macro( 64, data) +#define MREPEAT66( macro, data) MREPEAT65( macro, data) macro( 65, data) +#define MREPEAT67( macro, data) MREPEAT66( macro, data) macro( 66, data) +#define MREPEAT68( macro, data) MREPEAT67( macro, data) macro( 67, data) +#define MREPEAT69( macro, data) MREPEAT68( macro, data) macro( 68, data) +#define MREPEAT70( macro, data) MREPEAT69( macro, data) macro( 69, data) +#define MREPEAT71( macro, data) MREPEAT70( macro, data) macro( 70, data) +#define MREPEAT72( macro, data) MREPEAT71( macro, data) macro( 71, data) +#define MREPEAT73( macro, data) MREPEAT72( macro, data) macro( 72, data) +#define MREPEAT74( macro, data) MREPEAT73( macro, data) macro( 73, data) +#define MREPEAT75( macro, data) MREPEAT74( macro, data) macro( 74, data) +#define MREPEAT76( macro, data) MREPEAT75( macro, data) macro( 75, data) +#define MREPEAT77( macro, data) MREPEAT76( macro, data) macro( 76, data) +#define MREPEAT78( macro, data) MREPEAT77( macro, data) macro( 77, data) +#define MREPEAT79( macro, data) MREPEAT78( macro, data) macro( 78, data) +#define MREPEAT80( macro, data) MREPEAT79( macro, data) macro( 79, data) +#define MREPEAT81( macro, data) MREPEAT80( macro, data) macro( 80, data) +#define MREPEAT82( macro, data) MREPEAT81( macro, data) macro( 81, data) +#define MREPEAT83( macro, data) MREPEAT82( macro, data) macro( 82, data) +#define MREPEAT84( macro, data) MREPEAT83( macro, data) macro( 83, data) +#define MREPEAT85( macro, data) MREPEAT84( macro, data) macro( 84, data) +#define MREPEAT86( macro, data) MREPEAT85( macro, data) macro( 85, data) +#define MREPEAT87( macro, data) MREPEAT86( macro, data) macro( 86, data) +#define MREPEAT88( macro, data) MREPEAT87( macro, data) macro( 87, data) +#define MREPEAT89( macro, data) MREPEAT88( macro, data) macro( 88, data) +#define MREPEAT90( macro, data) MREPEAT89( macro, data) macro( 89, data) +#define MREPEAT91( macro, data) MREPEAT90( macro, data) macro( 90, data) +#define MREPEAT92( macro, data) MREPEAT91( macro, data) macro( 91, data) +#define MREPEAT93( macro, data) MREPEAT92( macro, data) macro( 92, data) +#define MREPEAT94( macro, data) MREPEAT93( macro, data) macro( 93, data) +#define MREPEAT95( macro, data) MREPEAT94( macro, data) macro( 94, data) +#define MREPEAT96( macro, data) MREPEAT95( macro, data) macro( 95, data) +#define MREPEAT97( macro, data) MREPEAT96( macro, data) macro( 96, data) +#define MREPEAT98( macro, data) MREPEAT97( macro, data) macro( 97, data) +#define MREPEAT99( macro, data) MREPEAT98( macro, data) macro( 98, data) +#define MREPEAT100(macro, data) MREPEAT99( macro, data) macro( 99, data) +#define MREPEAT101(macro, data) MREPEAT100(macro, data) macro(100, data) +#define MREPEAT102(macro, data) MREPEAT101(macro, data) macro(101, data) +#define MREPEAT103(macro, data) MREPEAT102(macro, data) macro(102, data) +#define MREPEAT104(macro, data) MREPEAT103(macro, data) macro(103, data) +#define MREPEAT105(macro, data) MREPEAT104(macro, data) macro(104, data) +#define MREPEAT106(macro, data) MREPEAT105(macro, data) macro(105, data) +#define MREPEAT107(macro, data) MREPEAT106(macro, data) macro(106, data) +#define MREPEAT108(macro, data) MREPEAT107(macro, data) macro(107, data) +#define MREPEAT109(macro, data) MREPEAT108(macro, data) macro(108, data) +#define MREPEAT110(macro, data) MREPEAT109(macro, data) macro(109, data) +#define MREPEAT111(macro, data) MREPEAT110(macro, data) macro(110, data) +#define MREPEAT112(macro, data) MREPEAT111(macro, data) macro(111, data) +#define MREPEAT113(macro, data) MREPEAT112(macro, data) macro(112, data) +#define MREPEAT114(macro, data) MREPEAT113(macro, data) macro(113, data) +#define MREPEAT115(macro, data) MREPEAT114(macro, data) macro(114, data) +#define MREPEAT116(macro, data) MREPEAT115(macro, data) macro(115, data) +#define MREPEAT117(macro, data) MREPEAT116(macro, data) macro(116, data) +#define MREPEAT118(macro, data) MREPEAT117(macro, data) macro(117, data) +#define MREPEAT119(macro, data) MREPEAT118(macro, data) macro(118, data) +#define MREPEAT120(macro, data) MREPEAT119(macro, data) macro(119, data) +#define MREPEAT121(macro, data) MREPEAT120(macro, data) macro(120, data) +#define MREPEAT122(macro, data) MREPEAT121(macro, data) macro(121, data) +#define MREPEAT123(macro, data) MREPEAT122(macro, data) macro(122, data) +#define MREPEAT124(macro, data) MREPEAT123(macro, data) macro(123, data) +#define MREPEAT125(macro, data) MREPEAT124(macro, data) macro(124, data) +#define MREPEAT126(macro, data) MREPEAT125(macro, data) macro(125, data) +#define MREPEAT127(macro, data) MREPEAT126(macro, data) macro(126, data) +#define MREPEAT128(macro, data) MREPEAT127(macro, data) macro(127, data) +#define MREPEAT129(macro, data) MREPEAT128(macro, data) macro(128, data) +#define MREPEAT130(macro, data) MREPEAT129(macro, data) macro(129, data) +#define MREPEAT131(macro, data) MREPEAT130(macro, data) macro(130, data) +#define MREPEAT132(macro, data) MREPEAT131(macro, data) macro(131, data) +#define MREPEAT133(macro, data) MREPEAT132(macro, data) macro(132, data) +#define MREPEAT134(macro, data) MREPEAT133(macro, data) macro(133, data) +#define MREPEAT135(macro, data) MREPEAT134(macro, data) macro(134, data) +#define MREPEAT136(macro, data) MREPEAT135(macro, data) macro(135, data) +#define MREPEAT137(macro, data) MREPEAT136(macro, data) macro(136, data) +#define MREPEAT138(macro, data) MREPEAT137(macro, data) macro(137, data) +#define MREPEAT139(macro, data) MREPEAT138(macro, data) macro(138, data) +#define MREPEAT140(macro, data) MREPEAT139(macro, data) macro(139, data) +#define MREPEAT141(macro, data) MREPEAT140(macro, data) macro(140, data) +#define MREPEAT142(macro, data) MREPEAT141(macro, data) macro(141, data) +#define MREPEAT143(macro, data) MREPEAT142(macro, data) macro(142, data) +#define MREPEAT144(macro, data) MREPEAT143(macro, data) macro(143, data) +#define MREPEAT145(macro, data) MREPEAT144(macro, data) macro(144, data) +#define MREPEAT146(macro, data) MREPEAT145(macro, data) macro(145, data) +#define MREPEAT147(macro, data) MREPEAT146(macro, data) macro(146, data) +#define MREPEAT148(macro, data) MREPEAT147(macro, data) macro(147, data) +#define MREPEAT149(macro, data) MREPEAT148(macro, data) macro(148, data) +#define MREPEAT150(macro, data) MREPEAT149(macro, data) macro(149, data) +#define MREPEAT151(macro, data) MREPEAT150(macro, data) macro(150, data) +#define MREPEAT152(macro, data) MREPEAT151(macro, data) macro(151, data) +#define MREPEAT153(macro, data) MREPEAT152(macro, data) macro(152, data) +#define MREPEAT154(macro, data) MREPEAT153(macro, data) macro(153, data) +#define MREPEAT155(macro, data) MREPEAT154(macro, data) macro(154, data) +#define MREPEAT156(macro, data) MREPEAT155(macro, data) macro(155, data) +#define MREPEAT157(macro, data) MREPEAT156(macro, data) macro(156, data) +#define MREPEAT158(macro, data) MREPEAT157(macro, data) macro(157, data) +#define MREPEAT159(macro, data) MREPEAT158(macro, data) macro(158, data) +#define MREPEAT160(macro, data) MREPEAT159(macro, data) macro(159, data) +#define MREPEAT161(macro, data) MREPEAT160(macro, data) macro(160, data) +#define MREPEAT162(macro, data) MREPEAT161(macro, data) macro(161, data) +#define MREPEAT163(macro, data) MREPEAT162(macro, data) macro(162, data) +#define MREPEAT164(macro, data) MREPEAT163(macro, data) macro(163, data) +#define MREPEAT165(macro, data) MREPEAT164(macro, data) macro(164, data) +#define MREPEAT166(macro, data) MREPEAT165(macro, data) macro(165, data) +#define MREPEAT167(macro, data) MREPEAT166(macro, data) macro(166, data) +#define MREPEAT168(macro, data) MREPEAT167(macro, data) macro(167, data) +#define MREPEAT169(macro, data) MREPEAT168(macro, data) macro(168, data) +#define MREPEAT170(macro, data) MREPEAT169(macro, data) macro(169, data) +#define MREPEAT171(macro, data) MREPEAT170(macro, data) macro(170, data) +#define MREPEAT172(macro, data) MREPEAT171(macro, data) macro(171, data) +#define MREPEAT173(macro, data) MREPEAT172(macro, data) macro(172, data) +#define MREPEAT174(macro, data) MREPEAT173(macro, data) macro(173, data) +#define MREPEAT175(macro, data) MREPEAT174(macro, data) macro(174, data) +#define MREPEAT176(macro, data) MREPEAT175(macro, data) macro(175, data) +#define MREPEAT177(macro, data) MREPEAT176(macro, data) macro(176, data) +#define MREPEAT178(macro, data) MREPEAT177(macro, data) macro(177, data) +#define MREPEAT179(macro, data) MREPEAT178(macro, data) macro(178, data) +#define MREPEAT180(macro, data) MREPEAT179(macro, data) macro(179, data) +#define MREPEAT181(macro, data) MREPEAT180(macro, data) macro(180, data) +#define MREPEAT182(macro, data) MREPEAT181(macro, data) macro(181, data) +#define MREPEAT183(macro, data) MREPEAT182(macro, data) macro(182, data) +#define MREPEAT184(macro, data) MREPEAT183(macro, data) macro(183, data) +#define MREPEAT185(macro, data) MREPEAT184(macro, data) macro(184, data) +#define MREPEAT186(macro, data) MREPEAT185(macro, data) macro(185, data) +#define MREPEAT187(macro, data) MREPEAT186(macro, data) macro(186, data) +#define MREPEAT188(macro, data) MREPEAT187(macro, data) macro(187, data) +#define MREPEAT189(macro, data) MREPEAT188(macro, data) macro(188, data) +#define MREPEAT190(macro, data) MREPEAT189(macro, data) macro(189, data) +#define MREPEAT191(macro, data) MREPEAT190(macro, data) macro(190, data) +#define MREPEAT192(macro, data) MREPEAT191(macro, data) macro(191, data) +#define MREPEAT193(macro, data) MREPEAT192(macro, data) macro(192, data) +#define MREPEAT194(macro, data) MREPEAT193(macro, data) macro(193, data) +#define MREPEAT195(macro, data) MREPEAT194(macro, data) macro(194, data) +#define MREPEAT196(macro, data) MREPEAT195(macro, data) macro(195, data) +#define MREPEAT197(macro, data) MREPEAT196(macro, data) macro(196, data) +#define MREPEAT198(macro, data) MREPEAT197(macro, data) macro(197, data) +#define MREPEAT199(macro, data) MREPEAT198(macro, data) macro(198, data) +#define MREPEAT200(macro, data) MREPEAT199(macro, data) macro(199, data) +#define MREPEAT201(macro, data) MREPEAT200(macro, data) macro(200, data) +#define MREPEAT202(macro, data) MREPEAT201(macro, data) macro(201, data) +#define MREPEAT203(macro, data) MREPEAT202(macro, data) macro(202, data) +#define MREPEAT204(macro, data) MREPEAT203(macro, data) macro(203, data) +#define MREPEAT205(macro, data) MREPEAT204(macro, data) macro(204, data) +#define MREPEAT206(macro, data) MREPEAT205(macro, data) macro(205, data) +#define MREPEAT207(macro, data) MREPEAT206(macro, data) macro(206, data) +#define MREPEAT208(macro, data) MREPEAT207(macro, data) macro(207, data) +#define MREPEAT209(macro, data) MREPEAT208(macro, data) macro(208, data) +#define MREPEAT210(macro, data) MREPEAT209(macro, data) macro(209, data) +#define MREPEAT211(macro, data) MREPEAT210(macro, data) macro(210, data) +#define MREPEAT212(macro, data) MREPEAT211(macro, data) macro(211, data) +#define MREPEAT213(macro, data) MREPEAT212(macro, data) macro(212, data) +#define MREPEAT214(macro, data) MREPEAT213(macro, data) macro(213, data) +#define MREPEAT215(macro, data) MREPEAT214(macro, data) macro(214, data) +#define MREPEAT216(macro, data) MREPEAT215(macro, data) macro(215, data) +#define MREPEAT217(macro, data) MREPEAT216(macro, data) macro(216, data) +#define MREPEAT218(macro, data) MREPEAT217(macro, data) macro(217, data) +#define MREPEAT219(macro, data) MREPEAT218(macro, data) macro(218, data) +#define MREPEAT220(macro, data) MREPEAT219(macro, data) macro(219, data) +#define MREPEAT221(macro, data) MREPEAT220(macro, data) macro(220, data) +#define MREPEAT222(macro, data) MREPEAT221(macro, data) macro(221, data) +#define MREPEAT223(macro, data) MREPEAT222(macro, data) macro(222, data) +#define MREPEAT224(macro, data) MREPEAT223(macro, data) macro(223, data) +#define MREPEAT225(macro, data) MREPEAT224(macro, data) macro(224, data) +#define MREPEAT226(macro, data) MREPEAT225(macro, data) macro(225, data) +#define MREPEAT227(macro, data) MREPEAT226(macro, data) macro(226, data) +#define MREPEAT228(macro, data) MREPEAT227(macro, data) macro(227, data) +#define MREPEAT229(macro, data) MREPEAT228(macro, data) macro(228, data) +#define MREPEAT230(macro, data) MREPEAT229(macro, data) macro(229, data) +#define MREPEAT231(macro, data) MREPEAT230(macro, data) macro(230, data) +#define MREPEAT232(macro, data) MREPEAT231(macro, data) macro(231, data) +#define MREPEAT233(macro, data) MREPEAT232(macro, data) macro(232, data) +#define MREPEAT234(macro, data) MREPEAT233(macro, data) macro(233, data) +#define MREPEAT235(macro, data) MREPEAT234(macro, data) macro(234, data) +#define MREPEAT236(macro, data) MREPEAT235(macro, data) macro(235, data) +#define MREPEAT237(macro, data) MREPEAT236(macro, data) macro(236, data) +#define MREPEAT238(macro, data) MREPEAT237(macro, data) macro(237, data) +#define MREPEAT239(macro, data) MREPEAT238(macro, data) macro(238, data) +#define MREPEAT240(macro, data) MREPEAT239(macro, data) macro(239, data) +#define MREPEAT241(macro, data) MREPEAT240(macro, data) macro(240, data) +#define MREPEAT242(macro, data) MREPEAT241(macro, data) macro(241, data) +#define MREPEAT243(macro, data) MREPEAT242(macro, data) macro(242, data) +#define MREPEAT244(macro, data) MREPEAT243(macro, data) macro(243, data) +#define MREPEAT245(macro, data) MREPEAT244(macro, data) macro(244, data) +#define MREPEAT246(macro, data) MREPEAT245(macro, data) macro(245, data) +#define MREPEAT247(macro, data) MREPEAT246(macro, data) macro(246, data) +#define MREPEAT248(macro, data) MREPEAT247(macro, data) macro(247, data) +#define MREPEAT249(macro, data) MREPEAT248(macro, data) macro(248, data) +#define MREPEAT250(macro, data) MREPEAT249(macro, data) macro(249, data) +#define MREPEAT251(macro, data) MREPEAT250(macro, data) macro(250, data) +#define MREPEAT252(macro, data) MREPEAT251(macro, data) macro(251, data) +#define MREPEAT253(macro, data) MREPEAT252(macro, data) macro(252, data) +#define MREPEAT254(macro, data) MREPEAT253(macro, data) macro(253, data) +#define MREPEAT255(macro, data) MREPEAT254(macro, data) macro(254, data) +#define MREPEAT256(macro, data) MREPEAT255(macro, data) macro(255, data) + +/** + * \} + */ + +#endif // _MREPEAT_H_ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/preprocessor/preprocessor.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/preprocessor/preprocessor.h new file mode 100644 index 0000000..184c03a --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/preprocessor/preprocessor.h @@ -0,0 +1,55 @@ +/** + * \file + * + * \brief Preprocessor utils. + * + * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _PREPROCESSOR_H_ +#define _PREPROCESSOR_H_ + +#include "tpaste.h" +#include "stringz.h" +#include "mrepeat.h" + + +#endif // _PREPROCESSOR_H_ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/preprocessor/stringz.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/preprocessor/stringz.h new file mode 100644 index 0000000..b914b73 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/preprocessor/stringz.h @@ -0,0 +1,85 @@ +/** + * \file + * + * \brief Preprocessor stringizing utils. + * + * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _STRINGZ_H_ +#define _STRINGZ_H_ + +/** + * \defgroup group_sam_utils_stringz Preprocessor - Stringize + * + * \ingroup group_sam_utils + * + * \{ + */ + +/*! \brief Stringize. + * + * Stringize a preprocessing token, this token being allowed to be \#defined. + * + * May be used only within macros with the token passed as an argument if the token is \#defined. + * + * For example, writing STRINGZ(PIN) within a macro \#defined by PIN_NAME(PIN) + * and invoked as PIN_NAME(PIN0) with PIN0 \#defined as A0 is equivalent to + * writing "A0". + */ +#define STRINGZ(x) #x + +/*! \brief Absolute stringize. + * + * Stringize a preprocessing token, this token being allowed to be \#defined. + * + * No restriction of use if the token is \#defined. + * + * For example, writing ASTRINGZ(PIN0) anywhere with PIN0 \#defined as A0 is + * equivalent to writing "A0". + */ +#define ASTRINGZ(x) STRINGZ(x) + +/** + * \} + */ + +#endif // _STRINGZ_H_ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/preprocessor/tpaste.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/preprocessor/tpaste.h new file mode 100644 index 0000000..f8ec44a --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/preprocessor/tpaste.h @@ -0,0 +1,105 @@ +/** + * \file + * + * \brief Preprocessor token pasting utils. + * + * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _TPASTE_H_ +#define _TPASTE_H_ + +/** + * \defgroup group_sam_utils_tpaste Preprocessor - Token Paste + * + * \ingroup group_sam_utils + * + * \{ + */ + +/*! \name Token Paste + * + * Paste N preprocessing tokens together, these tokens being allowed to be \#defined. + * + * May be used only within macros with the tokens passed as arguments if the tokens are \#defined. + * + * For example, writing TPASTE2(U, WIDTH) within a macro \#defined by + * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is + * equivalent to writing U32. + */ +//! @{ +#define TPASTE2( a, b) a##b +#define TPASTE3( a, b, c) a##b##c +#define TPASTE4( a, b, c, d) a##b##c##d +#define TPASTE5( a, b, c, d, e) a##b##c##d##e +#define TPASTE6( a, b, c, d, e, f) a##b##c##d##e##f +#define TPASTE7( a, b, c, d, e, f, g) a##b##c##d##e##f##g +#define TPASTE8( a, b, c, d, e, f, g, h) a##b##c##d##e##f##g##h +#define TPASTE9( a, b, c, d, e, f, g, h, i) a##b##c##d##e##f##g##h##i +#define TPASTE10(a, b, c, d, e, f, g, h, i, j) a##b##c##d##e##f##g##h##i##j +//! @} + +/*! \name Absolute Token Paste + * + * Paste N preprocessing tokens together, these tokens being allowed to be \#defined. + * + * No restriction of use if the tokens are \#defined. + * + * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined + * as 32 is equivalent to writing U32. + */ +//! @{ +#define ATPASTE2( a, b) TPASTE2( a, b) +#define ATPASTE3( a, b, c) TPASTE3( a, b, c) +#define ATPASTE4( a, b, c, d) TPASTE4( a, b, c, d) +#define ATPASTE5( a, b, c, d, e) TPASTE5( a, b, c, d, e) +#define ATPASTE6( a, b, c, d, e, f) TPASTE6( a, b, c, d, e, f) +#define ATPASTE7( a, b, c, d, e, f, g) TPASTE7( a, b, c, d, e, f, g) +#define ATPASTE8( a, b, c, d, e, f, g, h) TPASTE8( a, b, c, d, e, f, g, h) +#define ATPASTE9( a, b, c, d, e, f, g, h, i) TPASTE9( a, b, c, d, e, f, g, h, i) +#define ATPASTE10(a, b, c, d, e, f, g, h, i, j) TPASTE10(a, b, c, d, e, f, g, h, i, j) +//! @} + +/** + * \} + */ + +#endif // _TPASTE_H_ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/status_codes.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/status_codes.h new file mode 100644 index 0000000..d5e6dd6 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/status_codes.h @@ -0,0 +1,113 @@ +/** + * \file + * + * \brief Status code definitions. + * + * This file defines various status codes returned by functions, + * indicating success or failure as well as what kind of failure. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef STATUS_CODES_H_INCLUDED +#define STATUS_CODES_H_INCLUDED + +/* Note: this is a local workaround to avoid a pre-processor clash due to the + * lwIP macro ERR_TIMEOUT. */ +#if defined(__LWIP_ERR_H__) && defined(ERR_TIMEOUT) +#if (ERR_TIMEOUT != -3) + +/* Internal check to make sure that the later restore of lwIP's ERR_TIMEOUT + * macro is set to the correct value. Note that it is highly improbable that + * this value ever changes in lwIP. */ +#error ASF developers: check lwip err.h new value for ERR_TIMEOUT +#endif +#undef ERR_TIMEOUT +#endif + +/** + * Status code that may be returned by shell commands and protocol + * implementations. + * + * \note Any change to these status codes and the corresponding + * message strings is strictly forbidden. New codes can be added, + * however, but make sure that any message string tables are updated + * at the same time. + */ +enum status_code { + STATUS_OK = 0, //!< Success + STATUS_ERR_BUSY = 0x19, + STATUS_ERR_DENIED = 0x1C, + STATUS_ERR_TIMEOUT = 0x12, + ERR_IO_ERROR = -1, //!< I/O error + ERR_FLUSHED = -2, //!< Request flushed from queue + ERR_TIMEOUT = -3, //!< Operation timed out + ERR_BAD_DATA = -4, //!< Data integrity check failed + ERR_PROTOCOL = -5, //!< Protocol error + ERR_UNSUPPORTED_DEV = -6, //!< Unsupported device + ERR_NO_MEMORY = -7, //!< Insufficient memory + ERR_INVALID_ARG = -8, //!< Invalid argument + ERR_BAD_ADDRESS = -9, //!< Bad address + ERR_BUSY = -10, //!< Resource is busy + ERR_BAD_FORMAT = -11, //!< Data format not recognized + ERR_NO_TIMER = -12, //!< No timer available + ERR_TIMER_ALREADY_RUNNING = -13, //!< Timer already running + ERR_TIMER_NOT_RUNNING = -14, //!< Timer not running + ERR_ABORTED = -15, //!< Operation aborted by user + /** + * \brief Operation in progress + * + * This status code is for driver-internal use when an operation + * is currently being performed. + * + * \note Drivers should never return this status code to any + * callers. It is strictly for internal use. + */ + OPERATION_IN_PROGRESS = -128, +}; + +typedef enum status_code status_code_t; + +#if defined(__LWIP_ERR_H__) +#define ERR_TIMEOUT -3 +#endif + +#endif /* STATUS_CODES_H_INCLUDED */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/syscalls/gcc/syscalls.c b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/syscalls/gcc/syscalls.c new file mode 100644 index 0000000..69dcede --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/sam/utils/syscalls/gcc/syscalls.c @@ -0,0 +1,145 @@ +/** + * \file + * + * \brief Syscalls for SAM (GCC). + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#include +#include +#include +#include + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +#undef errno +extern int errno; +extern int _end; +extern int __ram_end__; + +extern caddr_t _sbrk(int incr); +extern int link(char *old, char *new); +extern int _close(int file); +extern int _fstat(int file, struct stat *st); +extern int _isatty(int file); +extern int _lseek(int file, int ptr, int dir); +extern void _exit(int status); +extern void _kill(int pid, int sig); +extern int _getpid(void); + +extern caddr_t _sbrk(int incr) +{ + static unsigned char *heap = NULL; + unsigned char *prev_heap; + int ramend = (int)&__ram_end__; + + if (heap == NULL) { + heap = (unsigned char *)&_end; + } + prev_heap = heap; + + if (((int)prev_heap + incr) > ramend) { + return (caddr_t) -1; + } + + heap += incr; + + return (caddr_t) prev_heap; +} + +extern int link(char *old, char *new) +{ + return -1; +} + +extern int _close(int file) +{ + return -1; +} + +extern int _fstat(int file, struct stat *st) +{ + st->st_mode = S_IFCHR; + + return 0; +} + +extern int _isatty(int file) +{ + return 1; +} + +extern int _lseek(int file, int ptr, int dir) +{ + return 0; +} + +extern void _exit(int status) +{ + printf("Exiting with status %d.\n", status); + + for (;;); +} + +extern void _kill(int pid, int sig) +{ + return; +} + +extern int _getpid(void) +{ + return -1; +} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/thirdparty/CMSIS/ATMEL-disclaimer.txt b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/thirdparty/CMSIS/ATMEL-disclaimer.txt new file mode 100644 index 0000000..422f7fe --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/thirdparty/CMSIS/ATMEL-disclaimer.txt @@ -0,0 +1,20 @@ +/* + * Only the CMSIS required parts for ASF are included here, go to the below + * address for the full package: + * http://www.arm.com/products/processors/cortex-m/cortex-microcontroller-software-interface-standard.php + * + * The library file thirdparty/CMSIS/Lib/GCC/libarm_cortexM4lf_math_softfp.a was generated by ATMEL, which + * is support -mfloat-abi=softfp compiler flag, and this is also the default selection for device that + * have FPU module and enabled. + * If customer want to use -mfloat-abi=hard compiler flag, the project compile/link flag and link library + * should be manual modified. The library thirdparty/CMSIS/Lib/GCC/libarm_cortexM4lf_math.a is used for + * -mfloat-abi=hard configration. + * + * __CORTEX_SC is not defined for cortex-m0+, and may cause compiler warning, so the include file + * thirdparty/CMSIS/Include/core_cmInstr.h was modified to void such warning. + * Modified from: + * #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + * to: + * #if (__CORTEX_M >= 0x03) || ((defined(__CORTEX_SC)) && (__CORTEX_SC >= 300)) + * + */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/thirdparty/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/thirdparty/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf new file mode 100644 index 0000000..b374366 Binary files /dev/null and b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/thirdparty/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf differ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/thirdparty/CMSIS/Include/arm_common_tables.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/thirdparty/CMSIS/Include/arm_common_tables.h new file mode 100644 index 0000000..76aadca --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/thirdparty/CMSIS/Include/arm_common_tables.h @@ -0,0 +1,136 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 31. July 2014 +* $Revision: V1.4.4 +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +//extern const q31_t realCoefAQ31[1024]; +//extern const q31_t realCoefBQ31[1024]; +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) +#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) +#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) +#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) +#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) +#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) +#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) +#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/thirdparty/CMSIS/Include/arm_const_structs.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/thirdparty/CMSIS/Include/arm_const_structs.h new file mode 100644 index 0000000..217f1d5 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/thirdparty/CMSIS/Include/arm_const_structs.h @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 31. July 2014 +* $Revision: V1.4.4 +* +* Project: CMSIS DSP Library +* Title: arm_const_structs.h +* +* Description: This file has constant structs that are initialized for +* user convenience. For example, some can be given as +* arguments to the arm_cfft_f32() function. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/thirdparty/CMSIS/Include/core_cm3.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/thirdparty/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000..e1357c6 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/thirdparty/CMSIS/Include/core_cm3.h @@ -0,0 +1,1650 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200 + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h new file mode 100644 index 0000000..01089f1 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h @@ -0,0 +1,637 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.00 + * @date 28. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h new file mode 100644 index 0000000..2e3bb0e --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h @@ -0,0 +1,880 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.00 + * @date 28. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constrant "l" + * Otherwise, use general registers, specified by constrant "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + uint32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); +} + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +#if (__CORTEX_M >= 0x03) || ((defined(__CORTEX_SC)) && (__CORTEX_SC >= 300)) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/thirdparty/CMSIS/Lib/GCC/libarm_cortexM3l_math.a b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/thirdparty/CMSIS/Lib/GCC/libarm_cortexM3l_math.a new file mode 100644 index 0000000..f5687c0 Binary files /dev/null and b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/thirdparty/CMSIS/Lib/GCC/libarm_cortexM3l_math.a differ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/thirdparty/CMSIS/Lib/license.txt b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/thirdparty/CMSIS/Lib/license.txt new file mode 100644 index 0000000..139c1ff --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/thirdparty/CMSIS/Lib/license.txt @@ -0,0 +1,28 @@ +All pre-build libraries contained in the folders "ARM" and "GCC" +are guided by the following license: + +Copyright (C) 2009-2014 ARM Limited. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/thirdparty/CMSIS/README.txt b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/thirdparty/CMSIS/README.txt new file mode 100644 index 0000000..e42a543 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/ASF/thirdparty/CMSIS/README.txt @@ -0,0 +1,42 @@ +* ------------------------------------------------------------------- +* Copyright (C) 2011-2014 ARM Limited. All rights reserved. +* +* Date: 17 February 2014 +* Revision: V4.00 +* +* Project: Cortex Microcontroller Software Interface Standard (CMSIS) +* Title: Release Note for CMSIS +* +* ------------------------------------------------------------------- + + +NOTE - Open the index.html file to access CMSIS documentation + + +The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all +Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects +and reduces time-to-market for new embedded applications. + +CMSIS is released under the terms of the end user license agreement ("CMSIS_END_USER_LICENCE_AGREEMENT.pdf"). +Any user of the software package is bound to the terms and conditions of the end user license agreement. + + +You will find the following sub-directories: + +Documentation - Contains CMSIS documentation. + +DSP_Lib - MDK project files, Examples and source files etc.. to build the + CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors. + +Include - CMSIS Core Support and CMSIS DSP Include Files. + +Lib - CMSIS DSP Libraries. + +RTOS - CMSIS RTOS API template header file. + +Driver - CMSIS Peripheral Driver Interface. + +Pack - CMSIS Software Packs. + Mechanism to install software, device support, APIs, and example projects. + +SVD - CMSIS SVD Schema files and Conversion Utility. diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/asf.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/asf.h new file mode 100644 index 0000000..10594bc --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/asf.h @@ -0,0 +1,114 @@ +/** + * \file + * + * \brief Autogenerated API include file for the Atmel Software Framework (ASF) + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef ASF_H +#define ASF_H + +/* + * This file includes all API header files for the selected drivers from ASF. + * Note: There might be duplicate includes required by more than one driver. + * + * The file is automatically generated and will be re-written when + * running the ASF driver selector tool. Any changes will be discarded. + */ + +// From module: Common SAM compiler driver +#include +#include + +// From module: Ethernet MAC (EMAC) +#include + +// From module: Ethernet Physical Transceiver (DM9161A) +#include + +// From module: GPIO - General purpose Input/Output +#include + +// From module: Generic board support +#include + +// From module: IOPORT - General purpose I/O service +#include + +// From module: Interrupt management - SAM implementation +#include + +// From module: PIO - Parallel Input/Output Controller +#include + +// From module: PMC - Power Management Controller +#include +#include + +// From module: Part identification macros +#include + +// From module: RSTC - Reset Controller +#include + +// From module: SAM3X EK LED support enabled +#include + +// From module: SAM3X startup code +#include + +// From module: Standard serial I/O (stdio) - SAM implementation +#include + +// From module: System Clock Control - SAM3X/A implementation +#include + +// From module: UART - Univ. Async Rec/Trans +#include + +// From module: USART - Serial interface - SAM implementation for devices with both UART and USART +#include + +// From module: USART - Univ. Syn Async Rec/Trans +#include + +// From module: pio_handler support enabled +#include + +#endif // ASF_H diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/config/conf_board.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/config/conf_board.h new file mode 100644 index 0000000..0525a1e --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/config/conf_board.h @@ -0,0 +1,59 @@ +/** + * \file + * + * \brief Board configuration. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef CONF_BOARD_H_INCLUDED +#define CONF_BOARD_H_INCLUDED + +/** Usart Hw ID used by the console (UART0) */ +#define CONSOLE_UART_ID ID_UART + +/** Enable debug uart pins */ +#define CONF_BOARD_UART_CONSOLE + +/* Enable EMAC feature */ +#define CONF_BOARD_EMAC + +#endif /* CONF_BOARD_H_INCLUDED */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/config/conf_clock.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/config/conf_clock.h new file mode 100644 index 0000000..6d6aad6 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/config/conf_clock.h @@ -0,0 +1,100 @@ +/** + * \file + * + * \brief SAM3X clock configuration. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef CONF_CLOCK_H_INCLUDED +#define CONF_CLOCK_H_INCLUDED + +// ===== System Clock (MCK) Source Options +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_RC +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_XTAL +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_BYPASS +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_8M_RC +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_12M_RC +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_XTAL +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_BYPASS +#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK +//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_UPLLCK + +// ===== System Clock (MCK) Prescaler Options (Fmck = Fsys / (SYSCLK_PRES)) +//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_1 +#define CONFIG_SYSCLK_PRES SYSCLK_PRES_2 +//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_4 +//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_8 +//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_16 +//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_32 +//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_64 +//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_3 + +// ===== PLL0 (A) Options (Fpll = (Fclk * PLL_mul) / PLL_div) +// Use mul and div effective values here. +#define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL +#define CONFIG_PLL0_MUL 14 +#define CONFIG_PLL0_DIV 1 + +// ===== UPLL (UTMI) Hardware fixed at 480 MHz. + +// ===== USB Clock Source Options (Fusb = FpllX / USB_div) +// Use div effective value here. +//#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0 +//#define CONFIG_USBCLK_SOURCE USBCLK_SRC_UPLL +//#define CONFIG_USBCLK_DIV 1 + +// ===== Target frequency (System clock) +// - XTAL frequency: 12MHz +// - System clock source: PLLA +// - System clock prescaler: 2 (divided by 2) +// - PLLA source: XTAL +// - PLLA output: XTAL * 14 / 1 +// - System clock is: 12 * 14 / 1 /2 = 84MHz +// ===== Target frequency (USB Clock) +// - USB clock source: UPLL +// - USB clock divider: 1 (not divided) +// - UPLL frequency: 480MHz +// - USB clock: 480 / 1 = 480MHz + + +#endif /* CONF_CLOCK_H_INCLUDED */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/config/conf_eth.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/config/conf_eth.h new file mode 100644 index 0000000..e8212ad --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/config/conf_eth.h @@ -0,0 +1,88 @@ + /** + * \file + * + * \brief EMAC (Ethernet MAC) driver for SAM. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef CONF_EMAC_H_INCLUDED +#define CONF_EMAC_H_INCLUDED + +/** Number of buffer for RX */ +#define EMAC_RX_BUFFERS 16 + +/** Number of buffer for TX */ +#define EMAC_TX_BUFFERS 8 + +/** MAC PHY operation max retry count */ +#define MAC_PHY_RETRY_MAX 1000000 + +/** MAC address definition. The MAC address must be unique on the network. */ +#define ETHERNET_CONF_ETHADDR0 0x00 +#define ETHERNET_CONF_ETHADDR1 0x04 +#define ETHERNET_CONF_ETHADDR2 0x25 +#define ETHERNET_CONF_ETHADDR3 0x1C +#define ETHERNET_CONF_ETHADDR4 0xA0 +#define ETHERNET_CONF_ETHADDR5 0x02 + +/** The IP address being used. */ +#define ETHERNET_CONF_IPADDR0 192 +#define ETHERNET_CONF_IPADDR1 168 +#define ETHERNET_CONF_IPADDR2 0 +#define ETHERNET_CONF_IPADDR3 2 + +/** The gateway address being used. */ +#define ETHERNET_CONF_GATEWAY_ADDR0 192 +#define ETHERNET_CONF_GATEWAY_ADDR1 168 +#define ETHERNET_CONF_GATEWAY_ADDR2 0 +#define ETHERNET_CONF_GATEWAY_ADDR3 1 + +/** The network mask being used. */ +#define ETHERNET_CONF_NET_MASK0 255 +#define ETHERNET_CONF_NET_MASK1 255 +#define ETHERNET_CONF_NET_MASK2 255 +#define ETHERNET_CONF_NET_MASK3 0 + +/** Ethernet MII/RMII mode */ +#define ETH_PHY_MODE BOARD_EMAC_MODE_RMII + +#endif /* CONF_EMAC_H_INCLUDED */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/config/conf_uart_serial.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/config/conf_uart_serial.h new file mode 100644 index 0000000..dac4c16 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/config/conf_uart_serial.h @@ -0,0 +1,57 @@ +/** + * \file + * + * \brief Serial USART service configuration. + * + * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef CONF_USART_SERIAL_H +#define CONF_USART_SERIAL_H + +/** UART Interface */ +#define CONF_UART CONSOLE_UART +/** Baudrate setting */ +#define CONF_UART_BAUDRATE 115200 +/** Parity setting */ +#define CONF_UART_PARITY UART_MR_PAR_NO + +#endif/* CONF_USART_SERIAL_H_INCLUDED */ diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/emac_example.c b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/emac_example.c new file mode 100644 index 0000000..866e9dc --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/emac_example.c @@ -0,0 +1,503 @@ +/** + * \file + * + * \brief EMAC example for SAM. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/** + * \mainpage EMAC Example + * + * \section Purpose + * + * This example uses the Ethernet MAC (EMAC) and the on-board Ethernet + * transceiver available on Atmel evaluation kits. It enables the device to + * respond to a ping command sent by a host computer. + * + * \section Requirements + * + * - SAM microcontrollers with EMAC feature. + * - On-board ethernet interface. + * + * \section Description + * + * Upon startup, the program will configure the EMAC with a default IP and + * MAC address and then ask the transceiver to auto-negotiate the best mode + * of operation. Once this is done, it will start to monitor incoming packets + * and process them whenever appropriate. + * + * The basic will only answer to two kinds of packets: + * + * - It will reply to ARP requests with its MAC address, + * - and to ICMP ECHO request so that the device can be PING'ed. + * + * You may use 'ping' command to check if the board responds correctly to + * ping requests. + * + * \section Usage + * + * -# Build the program and download it into the evaluation board. + * -# On the computer, open and configure a terminal application + * (e.g., HyperTerminal on Microsoft Windows) with these settings: + * - 115200 bauds + * - 8 bits of data + * - No parity + * - 1 stop bit + * - No flow control + * -# Connect an Ethernet cable between the evaluation board and the network. + * The board may be connected directly to a computer; in this case, + * make sure to use a cross/twisted wired cable such as the one provided + * with the evaluation kit. + * -# Start the application. It will display the following message on the terminal: + * \code + -- EMAC Example -- + -- SAMxxxxxx-xx + -- Compiled: xxx xx xxxx xx:xx:xx -- + MAC 00:45:56:78:9a:bc + IP 192.168.0.2 +\endcode + * -# The program will then auto-negotiate the mode of operation and start + * receiving packets, displaying feedback on the terminal. To display additional + * information, press any key in the terminal application. + * -# To test if the board responds to ICMP ECHO requests, type the following + * command line in a shell: + * \code + ping 192.168.0.2 +\endcode + * Response to 'ping' cmd will appear in the shell. + * + * \note + * Make sure the IP address of the device(EK board) and the computer are in the same network. + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#include +#include +#include "mini_ip.h" +#include "conf_eth.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +#define STRING_EOL "\r" +#define STRING_HEADER "-- EMAC Example --\r" \ + "-- "BOARD_NAME" --\r" \ + "-- Compiled: "__DATE__" "__TIME__" --"STRING_EOL + +/** The MAC address used for the test */ +static uint8_t gs_uc_mac_address[] = + { ETHERNET_CONF_ETHADDR0, ETHERNET_CONF_ETHADDR1, ETHERNET_CONF_ETHADDR2, + ETHERNET_CONF_ETHADDR3, ETHERNET_CONF_ETHADDR4, ETHERNET_CONF_ETHADDR5 +}; + +/** The IP address used for test (ping ...) */ +static uint8_t gs_uc_ip_address[] = + { ETHERNET_CONF_IPADDR0, ETHERNET_CONF_IPADDR1, + ETHERNET_CONF_IPADDR2, ETHERNET_CONF_IPADDR3 }; + +/** The EMAC driver instance */ +static emac_device_t gs_emac_dev; + +/** Buffer for ethernet packets */ +static volatile uint8_t gs_uc_eth_buffer[EMAC_FRAME_LENTGH_MAX]; + +/** + * \brief Process & return the ICMP checksum. + * + * \param p_buff Pointer to the buffer. + * \param ul_len The length of the buffered data. + * + * \return Checksum of the ICMP. + */ +static uint16_t emac_icmp_checksum(uint16_t *p_buff, uint32_t ul_len) +{ + uint32_t i, ul_tmp; + + for (i = 0, ul_tmp = 0; i < ul_len; i++, p_buff++) { + + ul_tmp += SWAP16(*p_buff); + } + ul_tmp = (ul_tmp & 0xffff) + (ul_tmp >> 16); + + return (uint16_t) (~ul_tmp); +} + +/** + * \brief Display the IP packet. + * + * \param p_ip_header Pointer to the IP header. + * \param ul_size The data size. + */ +static void emac_display_ip_packet(p_ip_header_t p_ip_header, uint32_t ul_size) +{ + printf("======= IP %4d bytes, HEADER ==========\n\r", (int)ul_size); + printf(" IP Version = v.%d", (p_ip_header->ip_hl_v & 0xF0) >> 4); + printf("\n\r Header Length = %d", p_ip_header->ip_hl_v & 0x0F); + printf("\n\r Type of service = 0x%x", p_ip_header->ip_tos); + printf("\n\r Total IP Length = 0x%X", + (((p_ip_header->ip_len) >> 8) & 0xff) + + (((p_ip_header->ip_len) << 8) & 0xff00)); + printf("\n\r ID = 0x%X", + (((p_ip_header->ip_id) >> 8) & 0xff) + + (((p_ip_header->ip_id) << 8) & 0xff00)); + printf("\n\r Header Checksum = 0x%X", + (((p_ip_header->ip_sum) >> 8) & 0xff) + + (((p_ip_header->ip_sum) << 8) & 0xff00)); + puts("\r Protocol = "); + + switch (p_ip_header->ip_p) { + case IP_PROT_ICMP: + puts("ICMP"); + break; + + case IP_PROT_IP: + puts("IP"); + break; + + case IP_PROT_TCP: + puts("TCP"); + break; + + case IP_PROT_UDP: + puts("UDP"); + break; + + default: + printf("%d (0x%X)", p_ip_header->ip_p, p_ip_header->ip_p); + break; + } + + printf("\n\r IP Src Address = %d:%d:%d:%d", + p_ip_header->ip_src[0], + p_ip_header->ip_src[1], + p_ip_header->ip_src[2], p_ip_header->ip_src[3]); + + printf("\n\r IP Dest Address = %d:%d:%d:%d", + p_ip_header->ip_dst[0], + p_ip_header->ip_dst[1], + p_ip_header->ip_dst[2], p_ip_header->ip_dst[3]); + puts("\n\r----------------------------------------\r"); +} + +/** + * \brief Process the received ARP packet; change address and send it back. + * + * \param p_uc_data The data to process. + * \param ul_size The data size. + */ +static void emac_process_arp_packet(uint8_t *p_uc_data, uint32_t ul_size) +{ + uint32_t i; + uint8_t ul_rc = EMAC_OK; + + p_ethernet_header_t p_eth = (p_ethernet_header_t) p_uc_data; + p_arp_header_t p_arp = (p_arp_header_t) (p_uc_data + ETH_HEADER_SIZE); + + if (SWAP16(p_arp->ar_op) == ARP_REQUEST) { + printf("-- IP %d.%d.%d.%d\n\r", + p_eth->et_dest[0], p_eth->et_dest[1], + p_eth->et_dest[2], p_eth->et_dest[3]); + + printf("-- IP %d.%d.%d.%d\n\r", + p_eth->et_src[0], p_eth->et_src[1], + p_eth->et_src[2], p_eth->et_src[3]); + + /* ARP reply operation */ + p_arp->ar_op = SWAP16(ARP_REPLY); + + /* Fill the destination address and source address */ + for (i = 0; i < 6; i++) { + /* Swap ethernet destination address and ethernet source address */ + p_eth->et_dest[i] = p_eth->et_src[i]; + p_eth->et_src[i] = gs_uc_mac_address[i]; + p_arp->ar_tha[i] = p_arp->ar_sha[i]; + p_arp->ar_sha[i] = gs_uc_mac_address[i]; + } + /* Swap the source IP address and the destination IP address */ + for (i = 0; i < 4; i++) { + p_arp->ar_tpa[i] = p_arp->ar_spa[i]; + p_arp->ar_spa[i] = gs_uc_ip_address[i]; + } + ul_rc = emac_dev_write(&gs_emac_dev, p_uc_data, ul_size, NULL); + if (ul_rc != EMAC_OK) { + printf("E: ARP Send - 0x%x\n\r", ul_rc); + } + } +} + +/** + * \brief Process the received IP packet; change address and send it back. + * + * \param p_uc_data The data to process. + * \param ul_size The data size. + */ +static void emac_process_ip_packet(uint8_t *p_uc_data, uint32_t ul_size) +{ + uint32_t i; + uint32_t ul_icmp_len; + int32_t ul_rc = EMAC_OK; + + /* avoid Cppcheck Warning */ + UNUSED(ul_size); + + p_ethernet_header_t p_eth = (p_ethernet_header_t) p_uc_data; + p_ip_header_t p_ip_header = (p_ip_header_t) (p_uc_data + ETH_HEADER_SIZE); + + p_icmp_echo_header_t p_icmp_echo = + (p_icmp_echo_header_t) ((int8_t *) p_ip_header + + ETH_IP_HEADER_SIZE); + printf("-- IP %d.%d.%d.%d\n\r", p_eth->et_dest[0], p_eth->et_dest[1], + p_eth->et_dest[2], p_eth->et_dest[3]); + + printf("-- IP %d.%d.%d.%d\n\r", + p_eth->et_src[0], p_eth->et_src[1], p_eth->et_src[2], + p_eth->et_src[3]); + switch (p_ip_header->ip_p) { + case IP_PROT_ICMP: + if (p_icmp_echo->type == ICMP_ECHO_REQUEST) { + p_icmp_echo->type = ICMP_ECHO_REPLY; + p_icmp_echo->code = 0; + p_icmp_echo->cksum = 0; + + /* Checksum of the ICMP message */ + ul_icmp_len = (SWAP16(p_ip_header->ip_len) - ETH_IP_HEADER_SIZE); + if (ul_icmp_len % 2) { + *((uint8_t *) p_icmp_echo + ul_icmp_len) = 0; + ul_icmp_len++; + } + ul_icmp_len = ul_icmp_len / sizeof(uint16_t); + + p_icmp_echo->cksum = SWAP16( + emac_icmp_checksum((uint16_t *)p_icmp_echo, ul_icmp_len)); + /* Swap the IP destination address and the IP source address */ + for (i = 0; i < 4; i++) { + p_ip_header->ip_dst[i] = + p_ip_header->ip_src[i]; + p_ip_header->ip_src[i] = gs_uc_ip_address[i]; + } + /* Swap ethernet destination address and ethernet source address */ + for (i = 0; i < 6; i++) { + /* Swap ethernet destination address and ethernet source address */ + p_eth->et_dest[i] = p_eth->et_src[i]; + p_eth->et_src[i] = gs_uc_mac_address[i]; + } + /* Send the echo_reply */ + ul_rc = emac_dev_write(&gs_emac_dev, p_uc_data, + SWAP16(p_ip_header->ip_len) + 14, NULL); + if (ul_rc != EMAC_OK) { + printf("E: ICMP Send - 0x%x\n\r", ul_rc); + } + } + break; + + default: + break; + } +} + +/** + * \brief Process the received EMAC packet. + * + * \param p_uc_data The data to process. + * \param ul_size The data size. + */ +static void emac_process_eth_packet(uint8_t *p_uc_data, uint32_t ul_size) +{ + uint16_t us_pkt_format; + + p_ethernet_header_t p_eth = (p_ethernet_header_t) (p_uc_data); + p_ip_header_t p_ip_header = (p_ip_header_t) (p_uc_data + ETH_HEADER_SIZE); + ip_header_t ip_header; + us_pkt_format = SWAP16(p_eth->et_protlen); + + switch (us_pkt_format) { + /* ARP Packet format */ + case ETH_PROT_ARP: + /* Process the ARP packet */ + emac_process_arp_packet(p_uc_data, ul_size); + + break; + + /* IP protocol frame */ + case ETH_PROT_IP: + /* Backup the header */ + memcpy(&ip_header, p_ip_header, sizeof(ip_header_t)); + + /* Process the IP packet */ + emac_process_ip_packet(p_uc_data, ul_size); + + /* Dump the IP header */ + emac_display_ip_packet(&ip_header, ul_size); + break; + + default: + printf("=== Default w_pkt_format= 0x%X===\n\r", us_pkt_format); + break; + } +} + +/** + * \brief Configure UART console. + */ +static void configure_console(void) +{ + const usart_serial_options_t uart_serial_options = { + .baudrate = CONF_UART_BAUDRATE, + .paritytype = CONF_UART_PARITY + }; + + /* Configure console UART. */ + sysclk_enable_peripheral_clock(CONSOLE_UART_ID); + stdio_serial_init(CONF_UART, &uart_serial_options); +} + +/** + * \brief EMAC interrupt handler. + */ +void EMAC_Handler(void) +{ + emac_handler(&gs_emac_dev); +} + +/** + * \brief EMAC example entry point. + * + * \return Unused (ANSI-C compatibility). + */ +int main(void) +{ + uint32_t ul_frm_size; + volatile uint32_t ul_delay; + emac_options_t emac_option; + + /* Initialize the SAM system. */ + sysclk_init(); + board_init(); + + /* Initialize the console UART. */ + configure_console(); + + puts(STRING_HEADER); + + /* Display MAC & IP settings */ + printf("-- MAC %x:%x:%x:%x:%x:%x\n\r", + gs_uc_mac_address[0], gs_uc_mac_address[1], gs_uc_mac_address[2], + gs_uc_mac_address[3], gs_uc_mac_address[4], gs_uc_mac_address[5]); + + printf("-- IP %d.%d.%d.%d\n\r", gs_uc_ip_address[0], gs_uc_ip_address[1], + gs_uc_ip_address[2], gs_uc_ip_address[3]); + + /* Reset PHY */ + rstc_set_external_reset(RSTC, 13); /* (2^(13+1))/32768 */ + rstc_reset_extern(RSTC); + while (rstc_get_status(RSTC) & RSTC_SR_NRSTL) { + }; + rstc_set_external_reset(RSTC, 0); /* restore default */ + + /* Wait for PHY to be ready (CAT811: Max400ms) */ + ul_delay = sysclk_get_cpu_hz() / 1000 / 3 * 400; + while (ul_delay--); + + /* Enable EMAC clock */ + pmc_enable_periph_clk(ID_EMAC); + + /* Fill in EMAC options */ + emac_option.uc_copy_all_frame = 0; + emac_option.uc_no_boardcast = 0; + + memcpy(emac_option.uc_mac_addr, gs_uc_mac_address, sizeof(gs_uc_mac_address)); + + gs_emac_dev.p_hw = EMAC; + + /* Init EMAC driver structure */ + emac_dev_init(EMAC, &gs_emac_dev, &emac_option); + + /* Enable Interrupt */ + NVIC_EnableIRQ(EMAC_IRQn); + + /* Init MAC PHY driver */ + if (ethernet_phy_init(EMAC, BOARD_EMAC_PHY_ADDR, sysclk_get_cpu_hz()) + != EMAC_OK) { + puts("PHY Initialize ERROR!\r"); + return -1; + } + + /* Auto Negotiate, work in RMII mode */ + if (ethernet_phy_auto_negotiate(EMAC, BOARD_EMAC_PHY_ADDR) != EMAC_OK) { + + puts("Auto Negotiate ERROR!\r"); + return -1; + } + + /* Establish ethernet link */ + while (ethernet_phy_set_link(EMAC, BOARD_EMAC_PHY_ADDR, 1) != EMAC_OK) { + puts("Set link ERROR!\r"); + return -1; + } + + puts("Link detected. \r"); + + while (1) { + /* Process packets */ + if (EMAC_OK != emac_dev_read(&gs_emac_dev, (uint8_t *) gs_uc_eth_buffer, + sizeof(gs_uc_eth_buffer), &ul_frm_size)) { + continue; + } + + if (ul_frm_size > 0) { + /* Handle input frame */ + emac_process_eth_packet((uint8_t *) gs_uc_eth_buffer, ul_frm_size); + } + } +} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/mini_ip.h b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/mini_ip.h new file mode 100644 index 0000000..9cc60b0 --- /dev/null +++ b/EMAC_EMAC_EXAMPLE_TAIJI_DUE/EMAC_EMAC_EXAMPLE_TAIJI_DUE/src/mini_ip.h @@ -0,0 +1,170 @@ + /** + * \file + * + * \brief Include definitions for the mini ip. + * + * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef MINIIP_H_INCLUDED +#define MINIIP_H_INCLUDED + +#include + +/** Ethernet types */ +#define ETH_PROT_IP 0x0800 /**< 2048 (0x0800) IPv4 */ +#define ETH_PROT_ARP 0x0806 /**< 2054 (0x0806) ARP */ +#define ETH_PROT_APPLETALK 0x8019 /**< 32923 (0x8019) Appletalk */ +#define ETH_PROT_IPV6 0x86DD /**< 34525 (0x86DD) IPv6 */ + +/** ARP OP codes */ +#define ARP_REQUEST 0x0001 /**< ARP Request packet */ +#define ARP_REPLY 0x0002 /**< ARP Reply packet */ + +/** IP protocols code */ +/* http://www.iana.org/assignments/protocol-numbers */ +#define IP_PROT_ICMP 1 +#define IP_PROT_IP 4 +#define IP_PROT_TCP 6 +#define IP_PROT_UDP 17 + +/** ICMP types */ +/* http://www.iana.org/assignments/icmp-parameters */ +#define ICMP_ECHO_REPLY 0x00 /**< Echo reply (used to ping) */ +/* 1 and 2 Reserved */ +#define ICMP_DEST_UNREACHABLE 0x03 /**< Destination Unreachable */ +#define ICMP_SOURCE_QUENCH 0x04 /**< Source Quench */ +#define ICMP_REDIR_MESSAGE 0x05 /**< Redirect Message */ +#define ICMP_ALT_HOST_ADD 0x06 /**< Alternate Host Address */ +/* 0x07 Reserved */ +#define ICMP_ECHO_REQUEST 0x08 /**< Echo Request */ +#define ICMP_ROUTER_ADV 0x09 /**< Router Advertisement */ +#define ICMP_ROUTER_SOL 0x0A /**< Router Solicitation */ +#define ICMP_TIME_EXC 0x0B /**< Time Exceeded */ +#define ICMP_PARAM_PB 0x0C /**< Parameter Problem: Bad IP header */ +#define ICMP_TIMESTAMP 0x0D /**< Timestamp */ +#define ICMP_TIMESTAMP_REP 0x0E /**< Timestamp Reply */ +#define ICMP_INFO_REQ 0x0F /**< Information Request */ +#define ICMP_INFO_REPLY 0x10 /**< Information Reply */ +#define ICMP_ADD_MASK_REQ 0x11 /**< Address Mask Request */ +#define ICMP_ADD_MASK_REP 0x12 /**< Address Mask Reply */ +/* 0x13 Reserved for security */ +/* 0X14 through 0x1D Reserved for robustness experiment */ +#define ICMP_TRACEROUTE 0x1E /**< Traceroute */ +#define ICMP_DAT_CONV_ERROR 0x1F /**< Datagram Conversion Error */ +#define ICMP_MOB_HOST_RED 0x20 /**< Mobile Host Redirect */ +#define ICMP_W_A_Y 0x21 /**< Where-Are-You (originally meant for IPv6) */ +#define ICMP_H_I_A 0x22 /**< Here-I-Am (originally meant for IPv6) */ +#define ICMP_MOB_REG_REQ 0x23 /**< Mobile Registration Request */ +#define ICMP_MOB_REG_REP 0x24 /**< Mobile Registration Reply */ +#define ICMP_DOM_NAME_REQ 0x25 /**< Domain Name Request */ +#define ICMP_DOM_NAME_REP 0x26 /**< Domain Name Reply */ +#define ICMP_SKIP_ALGO_PROT 0x27 /**< SKIP Algorithm Discovery Protocol, Simple Key-Management for Internet Protocol */ +#define ICMP_PHOTURIS 0x28 /**< Photuris, Security failures */ +#define ICMP_EXP_MOBIL 0x29 /**< ICMP for experimental mobility protocols such as Seamoby [RFC4065] */ +/* 0x2A through 0xFF Reserved */ + +/** Swap 2 bytes of a word */ +#define SWAP16(x) (((x & 0xff) << 8) | (x >> 8)) + +/** Ethernet header structure */ +COMPILER_PACK_SET(1) +typedef struct ethernet_header { + uint8_t et_dest[6]; /**< Destination node */ + uint8_t et_src[6]; /**< Source node */ + uint16_t et_protlen; /**< Protocol or length */ +} ethernet_header_t, *p_ethernet_header_t; + +/** ARP header structure */ +COMPILER_PACK_SET(1) +typedef struct arp_header { + uint16_t ar_hrd; /**< Format of hardware address */ + uint16_t ar_pro; /**< Format of protocol address */ + uint8_t ar_hln; /**< Length of hardware address */ + uint8_t ar_pln; /**< Length of protocol address */ + uint16_t ar_op; /**< Operation */ + uint8_t ar_sha[6]; /**< Sender hardware address */ + uint8_t ar_spa[4]; /**< Sender protocol address */ + uint8_t ar_tha[6]; /**< Target hardware address */ + uint8_t ar_tpa[4]; /**< Target protocol address */ +} arp_header_t, *p_arp_header_t; + +/** IP Header structure */ +COMPILER_PACK_SET(1) +typedef struct _IPheader { + uint8_t ip_hl_v; /**< Header length and version */ + uint8_t ip_tos; /**< Type of service */ + uint16_t ip_len; /**< Total length */ + uint16_t ip_id; /**< Identification */ + uint16_t ip_off; /**< Fragment offset field */ + uint8_t ip_ttl; /**< Time to live */ + uint8_t ip_p; /**< Protocol */ + uint16_t ip_sum; /**< Checksum */ + uint8_t ip_src[4]; /**< Source IP address */ + uint8_t ip_dst[4]; /**< Destination IP address */ +} ip_header_t, *p_ip_header_t; + +/** ICMP echo header structure */ +COMPILER_PACK_SET(1) +typedef struct icmp_echo_header { + uint8_t type; /**< Type of message */ + uint8_t code; /**< Type subcode */ + uint16_t cksum; /**< 1's complement cksum of struct */ + uint16_t id; /**< Identifier */ + uint16_t seq; /**< Sequence number */ +} icmp_echo_header_t, *p_icmp_echo_header_t; + +/** Ethernet packet structure */ +COMPILER_PACK_SET(1) +typedef struct eth_packet { + ethernet_header_t eth_hdr; + arp_header_t arp_hdr; +} eth_packet_t, *p_eth_packet_t; + +COMPILER_PACK_RESET() + +/** Ethernet header size */ +#define ETH_HEADER_SIZE (sizeof(ethernet_header_t)) + +/** Ethernet IP header size */ +#define ETH_IP_HEADER_SIZE (sizeof(ip_header_t)) + +#endif /* MINIIP_H_INCLUDED */