Full RCC support for STM32F107

Author: algesten

embassy-stm32/src/rcc/f107.rs

@@ -0,0 +1,239 @@
+use crate::pac::flash::vals::Latency;
+pub use crate::pac::rcc::vals::{
+    Adcpre as ADCPrescaler, Hpre as AHBPrescaler, Pll2mul, Pllmul as PllMul, Pllsrc, Ppre as APBPrescaler, Prediv1,
+    Prediv1src, Sw as Sysclk,
+};
+use crate::pac::{FLASH, RCC};
+use crate::time::Hertz;
+
+/// HSI speed
+pub const HSI_FREQ: Hertz = Hertz(8_000_000);
+
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub enum HseMode {
+    Oscillator,
+    Bypass,
+}
+
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub struct Hse {
+    pub freq: Hertz,
+    pub mode: HseMode,
+}
+
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub enum PllSource {
+    HSE,
+    HSI,
+}
+
+#[derive(Clone, Copy)]
+pub struct Pll {
+    pub src: PllSource,
+    pub prediv: Prediv1,
+    pub mul: PllMul,
+}
+
+#[derive(Clone, Copy)]
+pub struct Pll23 {
+    pub mul: Pll2mul,
+}
+
+#[derive(Clone, Copy)]
+pub struct Config {
+    pub hsi: bool,
+    pub hse: Option<Hse>,
+    pub sys: Sysclk,
+    pub pll: Option<Pll>,
+    pub pll2: Option<Pll23>,
+    pub pll3: Option<Pll23>,
+    pub prediv1_src: Option<Prediv1src>,
+    pub prediv2: Option<Prediv1>,
+    pub ahb_pre: AHBPrescaler,
+    pub apb1_pre: APBPrescaler,
+    pub apb2_pre: APBPrescaler,
+    pub adc_pre: ADCPrescaler,
+    pub usb_pre: Option<crate::pac::rcc::vals::Usbpre>,
+    pub i2s2_src: Option<crate::pac::rcc::vals::I2s2src>,
+    pub i2s3_src: Option<crate::pac::rcc::vals::I2s2src>,
+}
+
+impl Default for Config {
+    fn default() -> Self {
+        Self {
+            hsi: true,
+            hse: None,
+            sys: Sysclk::HSI,
+            pll: None,
+            pll2: None,
+            pll3: None,
+            prediv1_src: None,
+            prediv2: None,
+            ahb_pre: AHBPrescaler::DIV1,
+            apb1_pre: APBPrescaler::DIV1,
+            apb2_pre: APBPrescaler::DIV1,
+            adc_pre: ADCPrescaler::DIV6,
+            usb_pre: None,
+            i2s2_src: None,
+            i2s3_src: None,
+        }
+    }
+}
+
+pub(crate) unsafe fn init(config: Config) {
+    RCC.cr().modify(|w| w.set_hsion(true));
+    while !RCC.cr().read().hsirdy() {}
+
+    RCC.cfgr().modify(|w| w.set_sw(Sysclk::HSI));
+    while RCC.cfgr().read().sws() != Sysclk::HSI {}
+
+    let hsi = if config.hsi { Some(HSI_FREQ) } else { None };
+
+    let hse = match config.hse {
+        None => {
+            RCC.cr().modify(|w| w.set_hseon(false));
+            None
+        }
+        Some(hse) => {
+            RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
+            RCC.cr().modify(|w| w.set_hseon(true));
+            while !RCC.cr().read().hserdy() {}
+            Some(hse.freq)
+        }
+    };
+
+    // Calculate pll2clk and pll3clk
+    let pll2clk = config.pll2.map(|pll2| {
+        let prediv2 = config.prediv2.unwrap_or(Prediv1::DIV1);
+        let in_freq = hse.unwrap() / (prediv2.to_bits() + 1);
+        in_freq * pll2.mul
+    });
+    trace!("pll2clk: {:?}", pll2clk);
+
+    let pll3clk = config.pll3.map(|pll3| {
+        let prediv2 = config.prediv2.unwrap_or(Prediv1::DIV1);
+        let in_freq = hse.unwrap() / (prediv2.to_bits() + 1);
+        in_freq * pll3.mul
+    });
+    trace!("pll3clk: {:?}", pll3clk);
+
+    let pll = config.pll.map(|pll| {
+        let prediv1_src = config.prediv1_src.unwrap_or(Prediv1src::HSE);
+        let (src_val, src_freq) = match pll.src {
+            PllSource::HSI => {
+                if pll.prediv != Prediv1::DIV2 {
+                    panic!("if PLL source is HSI, PLL prediv must be 2.");
+                }
+                (Pllsrc::HSI_DIV2, hsi.unwrap())
+            }
+            PllSource::HSE => (
+                Pllsrc::HSE_DIV_PREDIV,
+                match prediv1_src {
+                    Prediv1src::HSE => hse.unwrap(),
+                    Prediv1src::PLL2 => pll2clk.unwrap(),
+                },
+            ),
+        };
+        let in_freq = src_freq / (pll.prediv.to_bits() + 1);
+        let out_freq = in_freq * pll.mul;
+
+        RCC.cfgr2().modify(|w| w.set_prediv1(pll.prediv));
+        RCC.cfgr().modify(|w| {
+            w.set_pllmul(pll.mul);
+            w.set_pllsrc(src_val);
+        });
+        RCC.cr().modify(|w| w.set_pllon(true));
+        while !RCC.cr().read().pllrdy() {}
+
+        out_freq
+    });
+
+    // Configure Prediv1 Source Mux
+    if let Some(prediv1_src) = config.prediv1_src {
+        RCC.cfgr2().modify(|w| w.set_prediv1src(prediv1_src));
+    }
+
+    // Configure common prediv for PLL2 and PLL3
+    if let Some(prediv) = config.prediv2 {
+        RCC.cfgr2().modify(|w| w.set_prediv2(prediv));
+    }
+
+    // Configure PLL2
+    if let Some(pll2) = config.pll2 {
+        RCC.cfgr2().modify(|w| w.set_pll2mul(pll2.mul));
+        RCC.cr().modify(|w| w.set_pll2on(true));
+        while !RCC.cr().read().pll2rdy() {}
+    }
+
+    // Configure PLL3
+    if let Some(pll3) = config.pll3 {
+        RCC.cfgr2().modify(|w| w.set_pll3mul(pll3.mul));
+        RCC.cr().modify(|w| w.set_pll3on(true));
+        while !RCC.cr().read().pll3rdy() {}
+    }
+
+    let sys = match config.sys {
+        Sysclk::HSI => hsi.unwrap(),
+        Sysclk::HSE => hse.unwrap(),
+        Sysclk::PLL1_P => pll.unwrap(),
+        _ => unreachable!(),
+    };
+
+    let hclk = sys / config.ahb_pre;
+    let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
+    let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk, config.apb2_pre);
+
+    let latency = match hclk.0 {
+        ..=24_000_000 => Latency::WS0,
+        ..=48_000_000 => Latency::WS1,
+        _ => Latency::WS2,
+    };
+    FLASH.acr().modify(|w| {
+        w.set_latency(latency);
+        w.set_prftbe(true);
+    });
+
+    RCC.cfgr().modify(|w| {
+        w.set_ppre1(config.apb1_pre);
+        w.set_ppre2(config.apb2_pre);
+        w.set_hpre(config.ahb_pre);
+        w.set_adcpre(config.adc_pre);
+        if let Some(usb_pre) = config.usb_pre {
+            w.set_usbpre(usb_pre);
+        }
+    });
+
+    if let Some(i2s2_src) = config.i2s2_src {
+        RCC.cfgr2().modify(|w| w.set_i2s2src(i2s2_src));
+    }
+
+    if let Some(i2s3_src) = config.i2s3_src {
+        RCC.cfgr2().modify(|w| w.set_i2s3src(i2s3_src));
+    }
+
+    cortex_m::asm::delay(16);
+
+    RCC.cfgr().modify(|w| w.set_sw(config.sys));
+    while RCC.cfgr().read().sws() != config.sys {}
+
+    if !config.hsi {
+        RCC.cr().modify(|w| w.set_hsion(false));
+    }
+
+    // Set clocks
+    set_clocks!(
+        sys: Some(sys),
+        hclk1: Some(hclk),
+        pclk1: Some(pclk1),
+        pclk1_tim: Some(pclk1_tim),
+        pclk2: Some(pclk2),
+        pclk2_tim: Some(pclk2_tim),
+        pll1_p: pll,
+        hsi: hsi,
+        hse: hse,
+        rtc: None,
+        lsi: None,
+        lse: None,
+        usb: None,
+    );
+}

embassy-stm32/src/rcc/mod.rs

@@ -19,7 +19,8 @@ mod hsi48;
 #[cfg(crs)]
 pub use hsi48::*;
 
-#[cfg_attr(any(stm32f0, stm32f1, stm32f3), path = "f013.rs")]
+#[cfg_attr(any(stm32f0, all(stm32f1, not(stm32f107)), stm32f3), path = "f013.rs")]
+#[cfg_attr(any(stm32f107), path = "f107.rs")]
 #[cfg_attr(any(stm32f2, stm32f4, stm32f7), path = "f247.rs")]
 #[cfg_attr(stm32c0, path = "c0.rs")]
 #[cfg_attr(stm32g0, path = "g0.rs")]