From e34f7e9397a961a12ce03905c206ec29a49df5fe Mon Sep 17 00:00:00 2001 From: Martin Algesten Date: Fri, 24 Jan 2025 09:08:11 +0100 Subject: [PATCH] Review fixes --- embassy-stm32/build.rs | 2 +- embassy-stm32/src/rcc/f013.rs | 71 +++++++++++++---------------------- 2 files changed, 28 insertions(+), 45 deletions(-) diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs index 4abbf8d694..09fcc0d03e 100644 --- a/embassy-stm32/build.rs +++ b/embassy-stm32/build.rs @@ -1383,7 +1383,7 @@ fn main() { for e in rcc_registers.ir.enums { fn is_rcc_name(e: &str) -> bool { match e { - "Pllp" | "Pllq" | "Pllr" | "Pllm" | "Plln" => true, + "Pllp" | "Pllq" | "Pllr" | "Pllm" | "Plln" | "Prediv1" | "Prediv2" => true, "Timpre" | "Pllrclkpre" => false, e if e.ends_with("pre") || e.ends_with("pres") || e.ends_with("div") || e.ends_with("mul") => true, _ => false, diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs index 27e43fa56c..10768cf6a2 100644 --- a/embassy-stm32/src/rcc/f013.rs +++ b/embassy-stm32/src/rcc/f013.rs @@ -41,6 +41,8 @@ pub enum PllSource { HSI, #[cfg(rcc_f0v4)] HSI48, + #[cfg(stm32f107)] + PLL2, } #[derive(Clone, Copy)] @@ -100,9 +102,7 @@ pub struct Config { #[cfg(stm32f107)] pub pll3: Option, #[cfg(stm32f107)] - pub prediv1_src: Option, - #[cfg(stm32f107)] - pub prediv2: Option, + pub prediv2: PllPreDiv, pub ahb_pre: AHBPrescaler, pub apb1_pre: APBPrescaler, @@ -118,9 +118,9 @@ pub struct Config { pub adc34: AdcClockSource, #[cfg(stm32f107)] - pub i2s2_src: Option, + pub i2s2_src: I2s2src, #[cfg(stm32f107)] - pub i2s3_src: Option, + pub i2s3_src: I2s2src, /// Per-peripheral kernel clock selection muxes pub mux: super::mux::ClockMux, @@ -143,9 +143,7 @@ impl Default for Config { #[cfg(stm32f107)] pll3: None, #[cfg(stm32f107)] - prediv1_src: None, - #[cfg(stm32f107)] - prediv2: None, + prediv2: PllPreDiv::DIV1, ahb_pre: AHBPrescaler::DIV1, apb1_pre: APBPrescaler::DIV1, @@ -163,9 +161,9 @@ impl Default for Config { adc34: AdcClockSource::Hclk(AdcHclkPrescaler::Div1), #[cfg(stm32f107)] - i2s2_src: None, + i2s2_src: I2s2src::SYS, #[cfg(stm32f107)] - i2s3_src: None, + i2s3_src: I2s2src::SYS, mux: Default::default(), } @@ -209,8 +207,7 @@ pub(crate) unsafe fn init(config: Config) { #[cfg(stm32f107)] let pll2freq = config.pll2.map(|pll2| { - let prediv2 = config.prediv2.unwrap_or(PllPreDiv::DIV1); - let in_freq = hse.unwrap() / (prediv2.to_bits() + 1); + let in_freq = hse.unwrap() / config.prediv2; in_freq * pll2.mul }); @@ -222,8 +219,6 @@ pub(crate) unsafe fn init(config: Config) { // Enable PLL let pll = config.pll.map(|pll| { - #[cfg(stm32f107)] - let prediv1_src = config.prediv1_src.unwrap_or(PreDiv1Src::HSE); let (src_val, src_freq) = match pll.src { #[cfg(any(rcc_f0v3, rcc_f0v4, rcc_f3v3))] PllSource::HSI => (Pllsrc::HSI_DIV_PREDIV, unwrap!(hsi)), @@ -234,25 +229,26 @@ pub(crate) unsafe fn init(config: Config) { } (Pllsrc::HSI_DIV2, unwrap!(hsi)) } - #[cfg(not(stm32f107))] - PllSource::HSE => (Pllsrc::HSE_DIV_PREDIV, unwrap!(hse)), - #[cfg(stm32f107)] - PllSource::HSE => ( - Pllsrc::HSE_DIV_PREDIV, - match prediv1_src { - PreDiv1Src::HSE => unwrap!(hse), - PreDiv1Src::PLL2 => unwrap!(pll2freq), - }, - ), + PllSource::HSE => { + #[cfg(stm32f107)] + RCC.cfgr2().modify(|w| w.set_prediv1src(PreDiv1Src::HSE)); + + (Pllsrc::HSE_DIV_PREDIV, unwrap!(hse)) + } #[cfg(rcc_f0v4)] PllSource::HSI48 => (Pllsrc::HSI48_DIV_PREDIV, unwrap!(hsi48)), + #[cfg(stm32f107)] + PllSource::PLL2 => { + if config.pll2.is_none() { + panic!("if PLL source is PLL2, Config::pll2 must also be set."); + } + + RCC.cfgr2().modify(|w| w.set_prediv1src(PreDiv1Src::PLL2)); + (Pllsrc::HSE_DIV_PREDIV, unwrap!(pll2freq)) + } }; - #[cfg(not(stm32f107))] let in_freq = src_freq / pll.prediv; - #[cfg(stm32f107)] - let in_freq = src_freq / (pll.prediv.to_bits() + 1); - rcc_assert!(max::PLL_IN.contains(&in_freq)); let out_freq = in_freq * pll.mul; rcc_assert!(max::PLL_OUT.contains(&out_freq)); @@ -275,19 +271,11 @@ pub(crate) unsafe fn init(config: Config) { out_freq }); - // Prediv1 Source Mux (HSE or PLL2) - #[cfg(stm32f107)] - if let Some(prediv1_src) = config.prediv1_src { - RCC.cfgr2().modify(|w| w.set_prediv1src(prediv1_src)); - } - // pll2 and pll3 #[cfg(stm32f107)] { // Common prediv for PLL2 and PLL3 - if let Some(prediv) = config.prediv2 { - RCC.cfgr2().modify(|w| w.set_prediv2(prediv)); - } + RCC.cfgr2().modify(|w| w.set_prediv2(config.prediv2)); // Configure PLL2 if let Some(pll2) = config.pll2 { @@ -390,13 +378,8 @@ pub(crate) unsafe fn init(config: Config) { // I2S2 and I2S3 #[cfg(stm32f107)] { - if let Some(i2s2_src) = config.i2s2_src { - RCC.cfgr2().modify(|w| w.set_i2s2src(i2s2_src)); - } - - if let Some(i2s3_src) = config.i2s3_src { - RCC.cfgr2().modify(|w| w.set_i2s3src(i2s3_src)); - } + RCC.cfgr2().modify(|w| w.set_i2s2src(config.i2s2_src)); + RCC.cfgr2().modify(|w| w.set_i2s3src(config.i2s3_src)); } // Wait for the new prescalers to kick in