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Merge pull request #359 from VOGL-electronic/add_insignis_NDS36PT5
modules: add Insignis NDS36PT5
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litedram/modules.py

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@@ -544,6 +544,15 @@ class M12L16161A(SDRModule):
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technology_timings = _TechnologyTimings(tREFI=64e6/4096, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 10))
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speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 55), tFAW=None, tRAS=40)}
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class NDS36PT5(SDRModule):
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# geometry
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nbanks = 4
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nrows = 8192
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ncols = 512
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# timings
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technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=(2, 10))
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speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=10, tRFC=(None, 55), tFAW=None, tRAS=40)}
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class W9825G6KH6(SDRModule):
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# geometry
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nbanks = 4

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