From fb5512f6d57c11c89f95ad156968a25db83ccc09 Mon Sep 17 00:00:00 2001 From: Andrew Dennison Date: Mon, 13 Nov 2023 11:03:45 +1100 Subject: [PATCH 1/2] soc/integration/soc: simplify hybrid etherbone --- litex/soc/integration/soc.py | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index fee8de48c5..67a950a421 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1781,8 +1781,7 @@ def add_etherbone(self, name="etherbone", phy=None, phy_cd="eth", data_width=8, buffer_depth = 16, with_ip_broadcast = True, with_timing_constraints = True, - interface = "crossbar", - endianness = "big"): + ethernet = False): # Imports from liteeth.core import LiteEthUDPIPCore from liteeth.frontend.etherbone import LiteEthEtherbone @@ -1801,10 +1800,10 @@ def add_etherbone(self, name="etherbone", phy=None, phy_cd="eth", data_width=8, dw = data_width, with_ip_broadcast = with_ip_broadcast, with_sys_datapath = with_sys_datapath, - interface = interface, - endianness = endianness, + interface = "hybrid" if ethernet else "crossbar", + endianness = self.cpu.endianness if ethernet else "big", ) - if interface == "hybrid": + if ethernet: ethcore.autocsr_exclude = {"mac"} # Exclude MAC here since added externally. if not with_sys_datapath: # Use PHY's eth_tx/eth_rx clock domains. @@ -1840,6 +1839,18 @@ def add_etherbone(self, name="etherbone", phy=None, phy_cd="eth", data_width=8, else: self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk) + if ethernet: + # Software Interface. + self.ethmac = ethmac = ethcore.mac + ethmac_region_size = (ethmac.rx_slots.constant + ethmac.tx_slots.constant)*ethmac.slot_size.constant + ethmac_region = SoCRegion(origin=self.mem_map.get("ethmac", None), size=ethmac_region_size, cached=False) + self.bus.add_slave(name="ethmac", slave=ethmac.bus, region=ethmac_region) + # Add IRQs (if enabled). + if self.irq.enabled: + self.irq.add("ethmac", use_loc_if_exists=True) + + self.add_constant("ETH_PHY_NO_RESET") # Disable reset from BIOS to avoid disabling Hardware Interface. + # Add SPI Flash -------------------------------------------------------------------------------- def add_spi_flash(self, name="spiflash", mode="4x", clk_freq=None, module=None, phy=None, rate="1:1", software_debug=False, **kwargs): # Imports. From 885d5b9cb139a842a45a7341f59f7e3bae3237c7 Mon Sep 17 00:00:00 2001 From: Andrew Dennison Date: Mon, 13 Nov 2023 11:13:19 +1100 Subject: [PATCH 2/2] tools/litex_sim: update hybrid etherbone integration --- litex/tools/litex_sim.py | 29 ++++------------------------- 1 file changed, 4 insertions(+), 25 deletions(-) diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py index 81699f32cb..c51595bcaa 100755 --- a/litex/tools/litex_sim.py +++ b/litex/tools/litex_sim.py @@ -233,29 +233,16 @@ def __init__(self, else: raise ValueError("Unknown Ethernet PHY model:", ethernet_phy_model) - # Ethernet and Etherbone ------------------------------------------------------------------- - if with_ethernet and with_etherbone: - # Etherbone. + # Etherbone with optional Ethernet --------------------------------------------------------- + if with_etherbone: self.add_etherbone( phy = self.ethphy, ip_address = etherbone_ip_address, mac_address = etherbone_mac_address, data_width = 8, - interface = "hybrid", - endianness = self.cpu.endianness + ethernet = with_ethernet, ) - - # Software Interface. - self.ethmac = ethmac = self.get_module("ethcore_etherbone").mac - ethmac_region_size = (ethmac.rx_slots.constant + ethmac.tx_slots.constant)*ethmac.slot_size.constant - ethmac_region = SoCRegion(origin=self.mem_map.get("ethmac", None), size=ethmac_region_size, cached=False) - self.bus.add_slave(name="ethmac", slave=ethmac.bus, region=ethmac_region) - - # Add IRQs (if enabled). - if self.irq.enabled: - self.irq.add("ethmac", use_loc_if_exists=True) - - # Ethernet --------------------------------------------------------------------------------- + # Ethernet only ---------------------------------------------------------------------------- elif with_ethernet: # Ethernet MAC self.ethmac = ethmac = LiteEthMAC( @@ -272,14 +259,6 @@ def __init__(self, if self.irq.enabled: self.irq.add("ethmac", use_loc_if_exists=True) - # Etherbone -------------------------------------------------------------------------------- - elif with_etherbone: - self.add_etherbone( - phy = self.ethphy, - ip_address = etherbone_ip_address, - mac_address = etherbone_mac_address - ) - # I2C -------------------------------------------------------------------------------------- if with_i2c: pads = platform.request("i2c", 0)