From 9760493c32b4f42bf959b1a9c2695c2eab57c568 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 26 Sep 2024 17:46:07 +0200
Subject: [PATCH] build/efinix/common: Switch to LiteXModule.

---
 litex/build/efinix/common.py | 34 +++++++++++++++++-----------------
 1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/litex/build/efinix/common.py b/litex/build/efinix/common.py
index 97b29cea72..2dcb3fdb19 100644
--- a/litex/build/efinix/common.py
+++ b/litex/build/efinix/common.py
@@ -41,7 +41,7 @@ def assert_is_signal_or_clocksignal(obj):
 
 # Efinix AsyncResetSynchronizer --------------------------------------------------------------------
 
-class EfinixAsyncResetSynchronizerImpl(Module):
+class EfinixAsyncResetSynchronizerImpl(LiteXModule):
     def __init__(self, cd, async_reset):
         rst1 = Signal()
         self.specials += [
@@ -71,7 +71,7 @@ def lower(dr):
 
 # Efinix Clk Input ---------------------------------------------------------------------------------
 
-class EfinixClkInputImpl(Module):
+class EfinixClkInputImpl(LiteXModule):
     n = 0
     def __init__(self, i, o):
         platform = LiteXContext.platform
@@ -102,14 +102,14 @@ def __init__(self, i, o):
             o = clk_out
         EfinixClkInputImpl.n += 1 # FIXME: Improve.
 
-class EfinixClkInput(Module):
+class EfinixClkInput(LiteXModule):
     @staticmethod
     def lower(dr):
         return EfinixClkInputImpl(dr.i, dr.o)
 
 # Efinix Clk Output --------------------------------------------------------------------------------
 
-class EfinixClkOutputImpl(Module):
+class EfinixClkOutputImpl(LiteXModule):
     def __init__(self, i, o):
         assert_is_signal_or_clocksignal(i)
         platform = LiteXContext.platform
@@ -124,14 +124,14 @@ def __init__(self, i, o):
         platform.toolchain.ifacewriter.blocks.append(block)
         platform.toolchain.excluded_ios.append(o)
 
-class EfinixClkOutput(Module):
+class EfinixClkOutput(LiteXModule):
     @staticmethod
     def lower(dr):
         return EfinixClkOutputImpl(dr.i, dr.o)
 
 # Efinix Tristate ----------------------------------------------------------------------------------
 
-class EfinixTristateImpl(Module):
+class EfinixTristateImpl(LiteXModule):
     def __init__(self, io, o, oe, i=None):
         platform = LiteXContext.platform
         if len(io) == 1:
@@ -162,14 +162,14 @@ def __init__(self, io, o, oe, i=None):
         platform.toolchain.ifacewriter.blocks.append(block)
         platform.toolchain.excluded_ios.append(platform.get_pin(io))
 
-class EfinixTristate(Module):
+class EfinixTristate(LiteXModule):
     @staticmethod
     def lower(dr):
         return EfinixTristateImpl(dr.target, dr.o, dr.oe, dr.i)
 
 # Efinix DifferentialOutput ------------------------------------------------------------------------
 
-class EfinixDifferentialOutputImpl(Module):
+class EfinixDifferentialOutputImpl(LiteXModule):
     def __init__(self, i, o_p, o_n):
         platform = LiteXContext.platform
         # only keep _p
@@ -214,7 +214,7 @@ def lower(dr):
 
 # Efinix DifferentialInput -------------------------------------------------------------------------
 
-class EfinixDifferentialInputImpl(Module):
+class EfinixDifferentialInputImpl(LiteXModule):
     def __init__(self, i_p, i_n, o):
         platform = LiteXContext.platform
         # only keep _p
@@ -274,7 +274,7 @@ def lower(dr):
 
 # Efinix DDRTristate -------------------------------------------------------------------------------
 
-class EfinixDDRTristateImpl(Module):
+class EfinixDDRTristateImpl(LiteXModule):
     def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk):
         assert oe1 == oe2
         assert_is_signal_or_clocksignal(clk)
@@ -319,7 +319,7 @@ def lower(dr):
 
 # Efinix SDRTristate -------------------------------------------------------------------------------
 
-class EfinixSDRTristateImpl(Module):
+class EfinixSDRTristateImpl(LiteXModule):
     def __init__(self, io, o, oe, i, clk):
         assert_is_signal_or_clocksignal(clk)
         platform = LiteXContext.platform
@@ -353,14 +353,14 @@ def __init__(self, io, o, oe, i, clk):
         platform.toolchain.excluded_ios.append(platform.get_pin(io))
 
 
-class EfinixSDRTristate(Module):
+class EfinixSDRTristate(LiteXModule):
     @staticmethod
     def lower(dr):
         return EfinixSDRTristateImpl(dr.io, dr.o, dr.oe, dr.i, dr.clk)
 
 # Efinix SDROutput ---------------------------------------------------------------------------------
 
-class EfinixSDROutputImpl(Module):
+class EfinixSDROutputImpl(LiteXModule):
     def __init__(self, i, o, clk):
         assert_is_signal_or_clocksignal(clk)
         platform = LiteXContext.platform
@@ -386,14 +386,14 @@ def __init__(self, i, o, clk):
         platform.toolchain.excluded_ios.append(platform.get_pin(o))
 
 
-class EfinixSDROutput(Module):
+class EfinixSDROutput(LiteXModule):
     @staticmethod
     def lower(dr):
         return EfinixSDROutputImpl(dr.i, dr.o, dr.clk)
 
 # Efinix DDROutput ---------------------------------------------------------------------------------
 
-class EfinixDDROutputImpl(Module):
+class EfinixDDROutputImpl(LiteXModule):
     def __init__(self, i1, i2, o, clk):
         assert_is_signal_or_clocksignal(clk)
         platform = LiteXContext.platform
@@ -427,7 +427,7 @@ def lower(dr):
 
 # Efinix SDRInput ----------------------------------------------------------------------------------
 
-class EfinixSDRInputImpl(Module):
+class EfinixSDRInputImpl(LiteXModule):
     def __init__(self, i, o, clk):
         assert_is_signal_or_clocksignal(clk)
         platform = LiteXContext.platform
@@ -457,7 +457,7 @@ def lower(dr):
 
 # Efinix DDRInput ----------------------------------------------------------------------------------
 
-class EfinixDDRInputImpl(Module):
+class EfinixDDRInputImpl(LiteXModule):
     def __init__(self, i, o1, o2, clk):
         assert_is_signal_or_clocksignal(clk)
         platform = LiteXContext.platform