diff --git a/README.md b/README.md new file mode 100644 index 0000000..e0469e9 --- /dev/null +++ b/README.md @@ -0,0 +1,9 @@ +# Super Breakout for Analogue Pocket + ++ FPGA implementation by james10952001 of Arcade _Dominos_ (Atari, 1977) for Analogue Pocket. ++ Ported from [MiSTer.](https://github.com/MiSTer-devel/Arcade-Dominos_MiSTer/) ++ Multiplayer support via dock. + +## ROM Instructions + +ROM files are not included, you must use [mra-tools-c](https://github.com/sebdel/mra-tools-c/) to convert to a singular `dominos.rom` file, then place the ROM file in `/Assets/dominos/common`. \ No newline at end of file diff --git a/dist/Assets/dominos/common/.keep b/dist/Assets/dominos/common/.keep new file mode 100644 index 0000000..e69de29 diff --git a/dist/Cores/ericlewis.Dominos/audio.json b/dist/Cores/ericlewis.Dominos/audio.json new file mode 100644 index 0000000..7c5daf9 --- /dev/null +++ b/dist/Cores/ericlewis.Dominos/audio.json @@ -0,0 +1,5 @@ +{ + "audio": { + "magic": "APF_VER_1" + } +} \ No newline at end of file diff --git a/dist/Cores/ericlewis.Dominos/bitstream.rbf_r b/dist/Cores/ericlewis.Dominos/bitstream.rbf_r new file mode 100644 index 0000000..04cb7c4 Binary files /dev/null and b/dist/Cores/ericlewis.Dominos/bitstream.rbf_r differ diff --git a/dist/Cores/ericlewis.Dominos/core.json b/dist/Cores/ericlewis.Dominos/core.json new file mode 100644 index 0000000..b3ee3ee --- /dev/null +++ b/dist/Cores/ericlewis.Dominos/core.json @@ -0,0 +1,34 @@ +{ + "core": { + "magic": "APF_VER_1", + "metadata": { + "platform_ids": ["dominos"], + "shortname": "Dominos", + "description": "Atari's 1977 Dominos.", + "author": "ericlewis", + "url": "https://github.com/ericlewis/openfpga-dominos", + "version": "0.0.1", + "date_release": "2022-09-16" + }, + "framework": { + "target_product": "Analogue Pocket", + "version_required": "1.1", + "sleep_supported": false, + "dock": { + "supported": true, + "analog_output": false + }, + "hardware": { + "link_port": false, + "cartridge_adapter": -1 + } + }, + "cores": [ + { + "name": "default", + "id": 0, + "filename": "bitstream.rbf_r" + } + ] + } +} diff --git a/dist/Cores/ericlewis.Dominos/data.json b/dist/Cores/ericlewis.Dominos/data.json new file mode 100644 index 0000000..0bafb59 --- /dev/null +++ b/dist/Cores/ericlewis.Dominos/data.json @@ -0,0 +1,14 @@ +{ + "data": { + "magic": "APF_VER_1", + "data_slots": [ + { + "name": "ROM", + "required": true, + "parameters": 8, + "filename": "dominos.rom", + "address": "0x00000000" + } + ] + } +} \ No newline at end of file diff --git a/dist/Cores/ericlewis.Dominos/icon.bin b/dist/Cores/ericlewis.Dominos/icon.bin new file mode 100644 index 0000000..7e6007c Binary files /dev/null and b/dist/Cores/ericlewis.Dominos/icon.bin differ diff --git a/dist/Cores/ericlewis.Dominos/info.txt b/dist/Cores/ericlewis.Dominos/info.txt new file mode 100644 index 0000000..befea7b --- /dev/null +++ b/dist/Cores/ericlewis.Dominos/info.txt @@ -0,0 +1 @@ +Atari's Arcade 1977 Dominos. Ported from MiSTer. \ No newline at end of file diff --git a/dist/Cores/ericlewis.Dominos/input.json b/dist/Cores/ericlewis.Dominos/input.json new file mode 100644 index 0000000..9a6a3ea --- /dev/null +++ b/dist/Cores/ericlewis.Dominos/input.json @@ -0,0 +1,22 @@ +{ + "input": { + "magic": "APF_VER_1", + "controllers": [ + { + "type": "default", + "mappings": [ + { + "id": 1, + "name": "Insert Coin", + "key": "pad_btn_select" + }, + { + "id": 2, + "name": "Start", + "key": "pad_btn_start" + } + ] + } + ] + } +} \ No newline at end of file diff --git a/dist/Cores/ericlewis.Dominos/interact.json b/dist/Cores/ericlewis.Dominos/interact.json new file mode 100644 index 0000000..f061588 --- /dev/null +++ b/dist/Cores/ericlewis.Dominos/interact.json @@ -0,0 +1,7 @@ +{ + "interact": { + "magic": "APF_VER_1", + "variables": [], + "messages": [] + } +} \ No newline at end of file diff --git a/dist/Cores/ericlewis.Dominos/variants.json b/dist/Cores/ericlewis.Dominos/variants.json new file mode 100644 index 0000000..c2dbd41 --- /dev/null +++ b/dist/Cores/ericlewis.Dominos/variants.json @@ -0,0 +1,6 @@ +{ + "variants": { + "magic": "APF_VER_1", + "variant_list": [] + } +} \ No newline at end of file diff --git a/dist/Cores/ericlewis.Dominos/video.json b/dist/Cores/ericlewis.Dominos/video.json new file mode 100644 index 0000000..1f46325 --- /dev/null +++ b/dist/Cores/ericlewis.Dominos/video.json @@ -0,0 +1,15 @@ +{ + "video": { + "magic": "APF_VER_1", + "scaler_modes": [ + { + "width": 320, + "height": 240, + "aspect_w": 4, + "aspect_h": 3, + "rotation": 0, + "mirror": 0 + } + ] + } +} \ No newline at end of file diff --git a/dist/Platforms/_images/dominos.bin b/dist/Platforms/_images/dominos.bin new file mode 100644 index 0000000..4881c7d Binary files /dev/null and b/dist/Platforms/_images/dominos.bin differ diff --git a/dist/Platforms/dominos.json b/dist/Platforms/dominos.json new file mode 100644 index 0000000..bb4ebd8 --- /dev/null +++ b/dist/Platforms/dominos.json @@ -0,0 +1,8 @@ +{ + "platform": { + "category": "Arcade", + "name": "Dominos", + "year": 1977, + "manufacturer": "Atari" + } +} diff --git a/mra/Dominos.mra b/mra/Dominos.mra new file mode 100644 index 0000000..1ec767a --- /dev/null +++ b/mra/Dominos.mra @@ -0,0 +1,50 @@ + + Dominos + + no + no + + + + + 1977 + Atari + Maze + + dominos + dominos + 0220 + dominos + + + 15kHz + horizontal + + + 2 (simultaneous) + 4-way + + 0 + + + + + + + + + + + + + + + + + + + + + + 20210430005030 + diff --git a/src/fpga/.gitignore b/src/fpga/.gitignore new file mode 100644 index 0000000..9d946bf --- /dev/null +++ b/src/fpga/.gitignore @@ -0,0 +1,28 @@ +*/db/ +*/incremental_db/ +*/simulation/ +*/greybox_tmp/ +incremental_db/ +db/ +PLLJ_PLLSPE_INFO.txt +c5_pin_model_dump.txt +cr_ie_info.json +*.pin +*.pof +*.ptf.* +*.qar +*.qarlog +*.qws +*.rpt +*.smsg +*.sof +*.sopc_builder +*.summary +*.txt +*.bak +*.cmp +*.done +*.xml +*.sld +*.cdf + diff --git a/src/fpga/ap_core.out.sdc b/src/fpga/ap_core.out.sdc new file mode 100644 index 0000000..6a8bcfd --- /dev/null +++ b/src/fpga/ap_core.out.sdc @@ -0,0 +1,139 @@ +## Generated SDC file "ap_core.out.sdc" + +## Copyright (C) 2022 Intel Corporation. All rights reserved. +## Your use of Intel Corporation's design tools, logic functions +## and other software and tools, and any partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Intel Program License +## Subscription Agreement, the Intel Quartus Prime License Agreement, +## the Intel FPGA IP License Agreement, or other applicable license +## agreement, including, without limitation, that your use is for +## the sole purpose of programming logic devices manufactured by +## Intel and sold by Intel or its authorized distributors. Please +## refer to the applicable agreement for further details, at +## https://fpgasoftware.intel.com/eula. + + +## VENDOR "Altera" +## PROGRAM "Quartus Prime" +## VERSION "Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition" + +## DATE "Tue Sep 13 13:20:17 2022" + +## +## DEVICE "5CEBA4F23C8" +## + + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + + + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name {clk_74a} -period 13.468 -waveform { 0.000 6.734 } [get_ports {clk_74a}] +create_clock -name {clk_74b} -period 13.468 -waveform { 0.000 6.734 } [get_ports {clk_74b}] +create_clock -name {bridge_spiclk} -period 13.468 -waveform { 0.000 6.734 } [get_ports {bridge_spiclk}] + + +#************************************************************** +# Create Generated Clock +#************************************************************** + +create_generated_clock -name {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} -source [get_pins {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 48 -divide_by 11 -master_clock {clk_74a} [get_pins {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}] +create_generated_clock -name {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 27 -master_clock {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] +create_generated_clock -name {ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 27 -phase 7499880/83333 -master_clock {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + +set_clock_uncertainty -rise_from [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.160 +set_clock_uncertainty -rise_from [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 +set_clock_uncertainty -rise_from [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.160 +set_clock_uncertainty -rise_from [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 +set_clock_uncertainty -fall_from [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.160 +set_clock_uncertainty -fall_from [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 +set_clock_uncertainty -fall_from [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -setup 0.160 +set_clock_uncertainty -fall_from [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060 +set_clock_uncertainty -rise_from [get_clocks {clk_74a}] -rise_to [get_clocks {clk_74a}] -setup 0.280 +set_clock_uncertainty -rise_from [get_clocks {clk_74a}] -rise_to [get_clocks {clk_74a}] -hold 0.270 +set_clock_uncertainty -rise_from [get_clocks {clk_74a}] -fall_to [get_clocks {clk_74a}] -setup 0.280 +set_clock_uncertainty -rise_from [get_clocks {clk_74a}] -fall_to [get_clocks {clk_74a}] -hold 0.270 +set_clock_uncertainty -fall_from [get_clocks {clk_74a}] -rise_to [get_clocks {clk_74a}] -setup 0.280 +set_clock_uncertainty -fall_from [get_clocks {clk_74a}] -rise_to [get_clocks {clk_74a}] -hold 0.270 +set_clock_uncertainty -fall_from [get_clocks {clk_74a}] -fall_to [get_clocks {clk_74a}] -setup 0.280 +set_clock_uncertainty -fall_from [get_clocks {clk_74a}] -fall_to [get_clocks {clk_74a}] -hold 0.270 +set_clock_uncertainty -rise_from [get_clocks {bridge_spiclk}] -rise_to [get_clocks {bridge_spiclk}] -setup 0.100 +set_clock_uncertainty -rise_from [get_clocks {bridge_spiclk}] -rise_to [get_clocks {bridge_spiclk}] -hold 0.060 +set_clock_uncertainty -rise_from [get_clocks {bridge_spiclk}] -fall_to [get_clocks {bridge_spiclk}] -setup 0.100 +set_clock_uncertainty -rise_from [get_clocks {bridge_spiclk}] -fall_to [get_clocks {bridge_spiclk}] -hold 0.060 +set_clock_uncertainty -fall_from [get_clocks {bridge_spiclk}] -rise_to [get_clocks {bridge_spiclk}] -setup 0.100 +set_clock_uncertainty -fall_from [get_clocks {bridge_spiclk}] -rise_to [get_clocks {bridge_spiclk}] -hold 0.060 +set_clock_uncertainty -fall_from [get_clocks {bridge_spiclk}] -fall_to [get_clocks {bridge_spiclk}] -setup 0.100 +set_clock_uncertainty -fall_from [get_clocks {bridge_spiclk}] -fall_to [get_clocks {bridge_spiclk}] -hold 0.060 + + +#************************************************************** +# Set Input Delay +#************************************************************** + + + +#************************************************************** +# Set Output Delay +#************************************************************** + + + +#************************************************************** +# Set Clock Groups +#************************************************************** + +set_clock_groups -asynchronous -group [get_clocks { bridge_spiclk }] -group [get_clocks { clk_74a }] -group [get_clocks { clk_74b }] -group [get_clocks { ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk }] -group [get_clocks { ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk }] -group [get_clocks { ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk }] +set_clock_groups -asynchronous -group [get_clocks { bridge_spiclk }] -group [get_clocks { clk_74a }] -group [get_clocks { clk_74b }] -group [get_clocks { ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk }] -group [get_clocks { ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk }] -group [get_clocks { ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk }] + + +#************************************************************** +# Set False Path +#************************************************************** + + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + + + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + diff --git a/src/fpga/ap_core.qpf b/src/fpga/ap_core.qpf new file mode 100644 index 0000000..dce59fc --- /dev/null +++ b/src/fpga/ap_core.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2019 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition +# Date created = 21:31:36 January 22, 2020 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "18.1" +DATE = "21:31:36 January 22, 2020" + +# Revisions + +PROJECT_REVISION = "ap_core" diff --git a/src/fpga/ap_core.qsf b/src/fpga/ap_core.qsf new file mode 100644 index 0000000..b128d76 --- /dev/null +++ b/src/fpga/ap_core.qsf @@ -0,0 +1,768 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2019 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition +# Date created = 19:22:02 April 19, 2022 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# ap_core_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:31:36 JANUARY 22, 2020" +set_global_assignment -name LAST_QUARTUS_VERSION "21.1.1 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:apf/build_id_gen.tcl" +set_global_assignment -name SMART_RECOMPILE ON + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_T17 -to bridge_spiclk +set_location_assignment PIN_M21 -to bridge_spimiso +set_location_assignment PIN_M20 -to bridge_spimosi +set_location_assignment PIN_AA9 -to cart_tran_bank0[7] +set_location_assignment PIN_AB8 -to cart_tran_bank0[6] +set_location_assignment PIN_AA8 -to cart_tran_bank0[5] +set_location_assignment PIN_AB7 -to cart_tran_bank0[4] +set_location_assignment PIN_AB6 -to cart_tran_bank0_dir +set_location_assignment PIN_AA10 -to cart_tran_bank1[7] +set_location_assignment PIN_AB10 -to cart_tran_bank1[6] +set_location_assignment PIN_Y10 -to cart_tran_bank1[5] +set_location_assignment PIN_AB11 -to cart_tran_bank1[4] +set_location_assignment PIN_Y11 -to cart_tran_bank1[3] +set_location_assignment PIN_AB12 -to cart_tran_bank1[2] +set_location_assignment PIN_AA12 -to cart_tran_bank1[1] +set_location_assignment PIN_AB13 -to cart_tran_bank1[0] +set_location_assignment PIN_AA13 -to cart_tran_bank1_dir +set_location_assignment PIN_AB15 -to cart_tran_bank2[7] +set_location_assignment PIN_AA15 -to cart_tran_bank2[6] +set_location_assignment PIN_AB17 -to cart_tran_bank2[5] +set_location_assignment PIN_AA17 -to cart_tran_bank2[4] +set_location_assignment PIN_AB18 -to cart_tran_bank2[3] +set_location_assignment PIN_AB20 -to cart_tran_bank2[0] +set_location_assignment PIN_AA19 -to cart_tran_bank2[1] +set_location_assignment PIN_AA18 -to cart_tran_bank2[2] +set_location_assignment PIN_AA14 -to cart_tran_bank2_dir +set_location_assignment PIN_AA20 -to cart_tran_bank3[7] +set_location_assignment PIN_AB21 -to cart_tran_bank3[6] +set_location_assignment PIN_AB22 -to cart_tran_bank3[5] +set_location_assignment PIN_AA22 -to cart_tran_bank3[4] +set_location_assignment PIN_Y21 -to cart_tran_bank3[3] +set_location_assignment PIN_Y22 -to cart_tran_bank3[2] +set_location_assignment PIN_W21 -to cart_tran_bank3[1] +set_location_assignment PIN_W22 -to cart_tran_bank3[0] +set_location_assignment PIN_V21 -to cart_tran_bank3_dir +set_location_assignment PIN_AB5 -to cart_tran_pin30_dir +set_location_assignment PIN_L8 -to cart_tran_pin30 +set_location_assignment PIN_K9 -to cart_tran_pin31 +set_location_assignment PIN_V15 -to clk_74a +set_location_assignment PIN_H16 -to clk_74b +set_location_assignment PIN_H8 -to cram0_a[21] +set_location_assignment PIN_H9 -to cram0_a[20] +set_location_assignment PIN_B7 -to cram0_a[19] +set_location_assignment PIN_B6 -to cram0_a[18] +set_location_assignment PIN_C6 -to cram0_a[17] +set_location_assignment PIN_H6 -to cram0_a[16] +set_location_assignment PIN_J8 -to cram0_adv_n +set_location_assignment PIN_B5 -to cram0_ce0_n +set_location_assignment PIN_E10 -to cram0_ce1_n +set_location_assignment PIN_G10 -to cram0_clk +set_location_assignment PIN_F7 -to cram0_cre +set_location_assignment PIN_J9 -to cram0_dq[15] +set_location_assignment PIN_L7 -to cram0_dq[14] +set_location_assignment PIN_F9 -to cram0_dq[13] +set_location_assignment PIN_E7 -to cram0_dq[12] +set_location_assignment PIN_A8 -to cram0_dq[11] +set_location_assignment PIN_D9 -to cram0_dq[10] +set_location_assignment PIN_A10 -to cram0_dq[9] +set_location_assignment PIN_C9 -to cram0_dq[8] +set_location_assignment PIN_J7 -to cram0_dq[7] +set_location_assignment PIN_G6 -to cram0_dq[6] +set_location_assignment PIN_F10 -to cram0_dq[5] +set_location_assignment PIN_E9 -to cram0_dq[4] +set_location_assignment PIN_D7 -to cram0_dq[3] +set_location_assignment PIN_A9 -to cram0_dq[2] +set_location_assignment PIN_C8 -to cram0_dq[1] +set_location_assignment PIN_B10 -to cram0_dq[0] +set_location_assignment PIN_A5 -to cram0_lb_n +set_location_assignment PIN_D6 -to cram0_oe_n +set_location_assignment PIN_A7 -to cram0_ub_n +set_location_assignment PIN_K7 -to cram0_wait +set_location_assignment PIN_G8 -to cram0_we_n +set_location_assignment PIN_Y3 -to cram1_a[21] +set_location_assignment PIN_AA2 -to cram1_a[20] +set_location_assignment PIN_L2 -to cram1_a[19] +set_location_assignment PIN_N1 -to cram1_a[18] +set_location_assignment PIN_U1 -to cram1_a[17] +set_location_assignment PIN_U2 -to cram1_a[16] +set_location_assignment PIN_U8 -to cram1_adv_n +set_location_assignment PIN_N2 -to cram1_ce0_n +set_location_assignment PIN_T8 -to cram1_ce1_n +set_location_assignment PIN_W2 -to cram1_clk +set_location_assignment PIN_T7 -to cram1_cre +set_location_assignment PIN_W8 -to cram1_dq[15] +set_location_assignment PIN_U6 -to cram1_dq[14] +set_location_assignment PIN_R7 -to cram1_dq[13] +set_location_assignment PIN_R6 -to cram1_dq[12] +set_location_assignment PIN_P7 -to cram1_dq[11] +set_location_assignment PIN_N6 -to cram1_dq[10] +set_location_assignment PIN_C2 -to cram1_dq[9] +set_location_assignment PIN_D3 -to cram1_dq[8] +set_location_assignment PIN_V6 -to cram1_dq[7] +set_location_assignment PIN_U7 -to cram1_dq[6] +set_location_assignment PIN_M6 -to cram1_dq[5] +set_location_assignment PIN_R5 -to cram1_dq[4] +set_location_assignment PIN_P6 -to cram1_dq[3] +set_location_assignment PIN_E2 -to cram1_dq[2] +set_location_assignment PIN_G2 -to cram1_dq[1] +set_location_assignment PIN_C1 -to cram1_dq[0] +set_location_assignment PIN_L1 -to cram1_lb_n +set_location_assignment PIN_M7 -to cram1_oe_n +set_location_assignment PIN_G1 -to cram1_ub_n +set_location_assignment PIN_W9 -to cram1_wait +set_location_assignment PIN_AA1 -to cram1_we_n +set_location_assignment PIN_J17 -to dram_a[12] +set_location_assignment PIN_F15 -to dram_a[11] +set_location_assignment PIN_C13 -to dram_a[10] +set_location_assignment PIN_G17 -to dram_a[9] +set_location_assignment PIN_J18 -to dram_a[8] +set_location_assignment PIN_F14 -to dram_a[7] +set_location_assignment PIN_E15 -to dram_a[6] +set_location_assignment PIN_E16 -to dram_a[5] +set_location_assignment PIN_F13 -to dram_a[4] +set_location_assignment PIN_E14 -to dram_a[3] +set_location_assignment PIN_F12 -to dram_a[2] +set_location_assignment PIN_D12 -to dram_a[1] +set_location_assignment PIN_D17 -to dram_a[0] +set_location_assignment PIN_E12 -to dram_ba[1] +set_location_assignment PIN_C16 -to dram_ba[0] +set_location_assignment PIN_B16 -to dram_cas_n +set_location_assignment PIN_G18 -to dram_cke +set_location_assignment PIN_G12 -to dram_clk +set_location_assignment PIN_K20 -to dram_dq[15] +set_location_assignment PIN_G11 -to dram_dq[14] +set_location_assignment PIN_J19 -to dram_dq[13] +set_location_assignment PIN_H13 -to dram_dq[12] +set_location_assignment PIN_G13 -to dram_dq[11] +set_location_assignment PIN_G16 -to dram_dq[10] +set_location_assignment PIN_G15 -to dram_dq[9] +set_location_assignment PIN_J13 -to dram_dq[8] +set_location_assignment PIN_A12 -to dram_dq[7] +set_location_assignment PIN_A13 -to dram_dq[6] +set_location_assignment PIN_B12 -to dram_dq[5] +set_location_assignment PIN_A14 -to dram_dq[4] +set_location_assignment PIN_B13 -to dram_dq[3] +set_location_assignment PIN_A15 -to dram_dq[2] +set_location_assignment PIN_B15 -to dram_dq[1] +set_location_assignment PIN_C15 -to dram_dq[0] +set_location_assignment PIN_B11 -to dram_ras_n +set_location_assignment PIN_C11 -to dram_we_n +set_location_assignment PIN_H10 -to port_ir_rx +set_location_assignment PIN_H11 -to port_ir_tx +set_location_assignment PIN_AA7 -to port_tran_sck +set_location_assignment PIN_R9 -to port_tran_sd +set_location_assignment PIN_V10 -to port_tran_si +set_location_assignment PIN_T13 -to port_tran_so_dir +set_location_assignment PIN_V9 -to port_tran_si_dir +set_location_assignment PIN_T9 -to port_tran_sd_dir +set_location_assignment PIN_Y9 -to port_tran_sck_dir +set_location_assignment PIN_J11 -to port_tran_so +set_location_assignment PIN_H15 -to scal_audadc +set_location_assignment PIN_K19 -to scal_auddac +set_location_assignment PIN_K17 -to scal_audlrck +set_location_assignment PIN_K16 -to scal_audmclk +set_location_assignment PIN_R17 -to scal_clk +set_location_assignment PIN_N20 -to scal_de +set_location_assignment PIN_P17 -to scal_hs +set_location_assignment PIN_N21 -to scal_skip +set_location_assignment PIN_T15 -to scal_vs +set_location_assignment PIN_U10 -to bist +set_location_assignment PIN_V16 -to sram_a[16] +set_location_assignment PIN_U12 -to sram_a[15] +set_location_assignment PIN_U15 -to sram_a[14] +set_location_assignment PIN_R10 -to sram_a[13] +set_location_assignment PIN_V14 -to sram_a[12] +set_location_assignment PIN_T10 -to sram_a[11] +set_location_assignment PIN_U11 -to sram_a[10] +set_location_assignment PIN_Y14 -to sram_a[9] +set_location_assignment PIN_U13 -to sram_a[8] +set_location_assignment PIN_Y19 -to sram_a[7] +set_location_assignment PIN_P8 -to sram_a[6] +set_location_assignment PIN_V19 -to sram_a[5] +set_location_assignment PIN_N9 -to sram_a[4] +set_location_assignment PIN_U21 -to sram_a[3] +set_location_assignment PIN_M8 -to sram_a[2] +set_location_assignment PIN_M9 -to sram_a[1] +set_location_assignment PIN_T14 -to sram_a[0] +set_location_assignment PIN_Y15 -to sram_dq[15] +set_location_assignment PIN_W16 -to sram_dq[14] +set_location_assignment PIN_Y16 -to sram_dq[13] +set_location_assignment PIN_Y17 -to sram_dq[12] +set_location_assignment PIN_V20 -to sram_dq[11] +set_location_assignment PIN_V18 -to sram_dq[10] +set_location_assignment PIN_U20 -to sram_dq[9] +set_location_assignment PIN_U16 -to sram_dq[8] +set_location_assignment PIN_R12 -to sram_dq[7] +set_location_assignment PIN_V13 -to sram_dq[6] +set_location_assignment PIN_T12 -to sram_dq[5] +set_location_assignment PIN_W19 -to sram_dq[4] +set_location_assignment PIN_Y20 -to sram_dq[3] +set_location_assignment PIN_P14 -to sram_dq[2] +set_location_assignment PIN_P9 -to sram_dq[1] +set_location_assignment PIN_N8 -to sram_dq[0] +set_location_assignment PIN_U17 -to sram_ub_n +set_location_assignment PIN_R11 -to sram_we_n +set_location_assignment PIN_N19 -to vblank +set_location_assignment PIN_R14 -to sram_oe_n +set_location_assignment PIN_P12 -to sram_lb_n +set_location_assignment PIN_H14 -to bridge_spiss +set_location_assignment PIN_M22 -to user1 +set_location_assignment PIN_L22 -to user2 +set_location_assignment PIN_K21 -to dbg_tx +set_location_assignment PIN_K22 -to dbg_rx +set_location_assignment PIN_L19 -to bridge_1wire +set_location_assignment PIN_R16 -to scal_vid[11] +set_location_assignment PIN_R15 -to scal_vid[10] +set_location_assignment PIN_R22 -to scal_vid[9] +set_location_assignment PIN_T22 -to scal_vid[8] +set_location_assignment PIN_T18 -to scal_vid[7] +set_location_assignment PIN_T19 -to scal_vid[6] +set_location_assignment PIN_T20 -to scal_vid[5] +set_location_assignment PIN_P19 -to scal_vid[4] +set_location_assignment PIN_P18 -to scal_vid[3] +set_location_assignment PIN_N16 -to scal_vid[2] +set_location_assignment PIN_P22 -to scal_vid[1] +set_location_assignment PIN_R21 -to scal_vid[0] +set_location_assignment PIN_P16 -to vpll_feed +set_location_assignment PIN_L18 -to port_ir_rx_disable +set_location_assignment PIN_D13 -to dram_dqm[0] +set_location_assignment PIN_H18 -to dram_dqm[1] +set_location_assignment PIN_U22 -to cart_tran_pin31_dir +set_location_assignment PIN_L17 -to cart_pin30_pwroff_reset +set_location_assignment PIN_M16 -to aux_scl +set_location_assignment PIN_M18 -to aux_sda + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON + +# Compiler Assignments +# ==================== +set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name TOP_LEVEL_ENTITY apf_top +set_global_assignment -name SAFE_STATE_MACHINE ON +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT ON +set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON +set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MUX_RESTRUCTURE OFF + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE 5CEBA4F23C8 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON +set_global_assignment -name ECO_OPTIMIZE_TIMING ON +set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON + +# Assembler Assignments +# ===================== +set_global_assignment -name ENABLE_OCT_DONE OFF +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name GENERATE_RBF_FILE ON + +# Signal Tap Assignments +# ====================== +set_global_assignment -name ENABLE_SIGNALTAP ON +set_global_assignment -name USE_SIGNALTAP_FILE core/stp1.stp + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# --------------------- +# start ENTITY(apf_top) + + # Fitter Assignments + # ================== +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank0[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_we_n +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_lb_n +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to bist +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_tran_si_dir +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_tran_si +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_tran_sd_dir +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_tran_sd +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_tran_sck_dir +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_tran_sck +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_pin30_dir +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank1[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank1[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank0_dir +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank0[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank0[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank0[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to vblank +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_ub_n +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_oe_n +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_tran_so_dir +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to clk_74a +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank3_dir +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank3[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank3[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank3[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank3[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank3[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank3[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank3[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank3[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank2_dir +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank2[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank2[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank2[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank2[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank2[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank2[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank2[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank2[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank1_dir +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank1[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank1[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vs +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_skip +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_hs +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_de +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_clk +set_instance_assignment -name IO_STANDARD "1.8 V" -to bridge_spimosi +set_instance_assignment -name IO_STANDARD "1.8 V" -to bridge_spimiso +set_instance_assignment -name IO_STANDARD "1.8 V" -to bridge_spiclk +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_audmclk +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_audlrck +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_auddac +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_audadc +set_instance_assignment -name IO_STANDARD "1.8 V" -to port_tran_so +set_instance_assignment -name IO_STANDARD "1.8 V" -to port_ir_tx +set_instance_assignment -name IO_STANDARD "1.8 V" -to port_ir_rx +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_we_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_ras_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[8] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[9] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[10] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[11] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[12] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[13] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[14] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[15] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_clk +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_cke +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_cas_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_ba[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_ba[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[8] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[9] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[10] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[11] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[12] +set_instance_assignment -name IO_STANDARD "1.8 V" -to clk_74b +set_instance_assignment -name IO_STANDARD "1.8 V" -to cart_tran_pin31 +set_instance_assignment -name IO_STANDARD "1.8 V" -to cart_tran_pin30 +set_instance_assignment -name IO_STANDARD "1.8 V" -to bridge_spiss +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_we_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_wait +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_ub_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_oe_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_lb_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[8] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[9] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[10] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[11] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[12] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[13] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[14] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[15] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_cre +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_clk +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_ce1_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_ce0_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_adv_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_a[16] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_a[17] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_a[18] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_a[19] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_a[20] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_a[21] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_we_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_ub_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_lb_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[8] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[9] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_clk +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_ce0_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_a[16] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_a[17] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_a[18] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_a[19] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_a[20] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_a[21] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_wait +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_oe_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[10] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[11] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[12] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[13] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[14] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[15] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_cre +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_ce1_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_adv_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to user1 +set_instance_assignment -name IO_STANDARD "1.8 V" -to user2 +set_instance_assignment -name IO_STANDARD "1.8 V" -to dbg_rx +set_instance_assignment -name IO_STANDARD "1.8 V" -to dbg_tx +set_instance_assignment -name IO_STANDARD "1.8 V" -to bridge_1wire +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[11] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[10] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[9] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[8] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dqm[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dqm[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to aux_sda +set_instance_assignment -name IO_STANDARD "1.8 V" -to aux_scl +set_instance_assignment -name IO_STANDARD "1.8 V" -to cart_pin30_pwroff_reset +set_instance_assignment -name IO_STANDARD "1.8 V" -to port_ir_rx_disable +set_instance_assignment -name IO_STANDARD "1.8 V" -to vpll_feed +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_pin31_dir +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to cram0_clk +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to dram_clk +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_audmclk +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_auddac +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_audlrck +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to vpll_feed +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to cram1_clk +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_clk +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dqm[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dqm[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[13] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[14] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[15] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_we_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_cas_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_ras_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[15] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_cke +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_ba[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_ba[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to dbg_tx +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_we_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_wait +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_ub_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_oe_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_lb_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[13] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[14] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_cre +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_ce1_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_ce0_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_adv_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_a[16] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_a[17] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_a[18] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_a[19] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_a[20] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_a[21] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_we_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_wait +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_ub_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_oe_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_lb_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[13] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[14] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[15] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_cre +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_ce1_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_ce0_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_adv_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_a[16] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_a[17] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_a[18] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_a[19] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_a[20] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_a[21] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cart_tran_pin31 +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cart_tran_pin30 +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cart_pin30_pwroff_reset +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to bridge_spimosi +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to bridge_spimiso +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to bridge_1wire +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to aux_sda +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to aux_scl +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to bridge_spiclk +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_de +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vs +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[0] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[1] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[2] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[3] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[4] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[5] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[6] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[7] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[8] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[9] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[10] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[11] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_hs +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_skip +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to port_tran_so +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to port_ir_tx +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to port_ir_rx_disable +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to port_ir_rx + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(apf_top) +# ------------------- + +# ------------------------ +# start ENTITY(mf_pllbase) + + # Project-Wide Assignments + # ======================== + +# end ENTITY(mf_pllbase) +# ---------------------- + +# ----------------------------- +# start ENTITY(mf_pllbase_0002) + + # Project-Wide Assignments + # ======================== + +# end ENTITY(mf_pllbase_0002) +# --------------------------- +set_global_assignment -name VHDL_FILE core/rtl/dpram.vhd +set_global_assignment -name VERILOG_FILE core/data_loader_8.v +set_global_assignment -name VHDL_FILE core/rtl/T65/T65_Pack.vhd +set_global_assignment -name VHDL_FILE core/rtl/T65/T65_MCode.vhd +set_global_assignment -name VHDL_FILE core/rtl/T65/T65_ALU.vhd +set_global_assignment -name VHDL_FILE core/rtl/T65/T65.vhd +set_global_assignment -name QIP_FILE core/rtl/Altera/ram1k_dp.qip +set_global_assignment -name VHDL_FILE core/rtl/sync_prom.vhd +set_global_assignment -name VHDL_FILE core/rtl/sync.vhd +set_global_assignment -name VHDL_FILE core/rtl/playfield.vhd +set_global_assignment -name VHDL_FILE core/rtl/oscillator.vhd +set_global_assignment -name VHDL_FILE core/rtl/Inputs.vhd +set_global_assignment -name VHDL_FILE core/rtl/dominos_sound.vhd +set_global_assignment -name VHDL_FILE core/rtl/dominos.vhd +set_global_assignment -name VHDL_FILE core/rtl/deltasigma.vhd +set_global_assignment -name VHDL_FILE core/rtl/cpu_mem.vhd +set_global_assignment -name QIP_FILE apf/apf.qip +set_global_assignment -name QIP_FILE apf/mf_ddio_bidir_12.qip +set_global_assignment -name VERILOG_FILE core/core_top.v +set_global_assignment -name VERILOG_FILE core/core_bridge_cmd.v +set_global_assignment -name SDC_FILE core/core_constraints.sdc +set_global_assignment -name SIGNALTAP_FILE core/stp1.stp +set_global_assignment -name QIP_FILE core/mf_pllbase.qip +set_global_assignment -name SIP_FILE core/mf_pllbase.sip +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM +set_global_assignment -name QII_AUTO_PACKED_REGISTERS NORMAL +set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp \ No newline at end of file diff --git a/src/fpga/ap_core_assignment_defaults.qdf b/src/fpga/ap_core_assignment_defaults.qdf new file mode 100644 index 0000000..5ac481d --- /dev/null +++ b/src/fpga/ap_core_assignment_defaults.qdf @@ -0,0 +1,806 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2022 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition +# Date created = 11:06:43 September 12, 2022 +# +# -------------------------------------------------------------------------- # +# +# Note: +# +# 1) Do not modify this file. This file was generated +# automatically by the Quartus Prime software and is used +# to preserve global assignments across Quartus Prime versions. +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off +set_global_assignment -name IP_COMPONENT_INTERNAL Off +set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On +set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off +set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off +set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db +set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off +set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off +set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off +set_global_assignment -name HC_OUTPUT_DIR hc_output +set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off +set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off +set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" +set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On +set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On +set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off +set_global_assignment -name REVISION_TYPE Base -family "Arria V" +set_global_assignment -name REVISION_TYPE Base -family "Stratix V" +set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ" +set_global_assignment -name REVISION_TYPE Base -family "Cyclone V" +set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" +set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On +set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On +set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On +set_global_assignment -name DO_COMBINED_ANALYSIS Off +set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off +set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off +set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off +set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off +set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On +set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone V" +set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V" +set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100 +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V" +set_global_assignment -name OPTIMIZATION_MODE Balanced +set_global_assignment -name ALLOW_REGISTER_MERGING On +set_global_assignment -name ALLOW_REGISTER_DUPLICATION On +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix IV" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV E" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Arria 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX II" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone V" +set_global_assignment -name MUX_RESTRUCTURE Auto +set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off +set_global_assignment -name ENABLE_IP_DEBUG Off +set_global_assignment -name SAVE_DISK_SPACE On +set_global_assignment -name OCP_HW_EVAL Enable +set_global_assignment -name DEVICE_FILTER_PACKAGE Any +set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name TRUE_WYSIWYG_FLOW Off +set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off +set_global_assignment -name STATE_MACHINE_PROCESSING Auto +set_global_assignment -name SAFE_STATE_MACHINE Off +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On +set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On +set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off +set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 +set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 +set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On +set_global_assignment -name PARALLEL_SYNTHESIS On +set_global_assignment -name DSP_BLOCK_BALANCING Auto +set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" +set_global_assignment -name NOT_GATE_PUSH_BACK On +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On +set_global_assignment -name IGNORE_CARRY_BUFFERS Off +set_global_assignment -name IGNORE_CASCADE_BUFFERS Off +set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_LCELL_BUFFERS Off +set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO +set_global_assignment -name IGNORE_SOFT_BUFFERS On +set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off +set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off +set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On +set_global_assignment -name AUTO_GLOBAL_OE_MAX On +set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off +set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut +set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name ALLOW_XOR_GATE_USAGE On +set_global_assignment -name AUTO_LCELL_INSERTION On +set_global_assignment -name CARRY_CHAIN_LENGTH 48 +set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 +set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name CASCADE_CHAIN_LENGTH 2 +set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 +set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 +set_global_assignment -name AUTO_CARRY_CHAINS On +set_global_assignment -name AUTO_CASCADE_CHAINS On +set_global_assignment -name AUTO_PARALLEL_EXPANDERS On +set_global_assignment -name AUTO_OPEN_DRAIN_PINS On +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off +set_global_assignment -name AUTO_ROM_RECOGNITION On +set_global_assignment -name AUTO_RAM_RECOGNITION On +set_global_assignment -name AUTO_DSP_RECOGNITION On +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto +set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On +set_global_assignment -name STRICT_RAM_RECOGNITION Off +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On +set_global_assignment -name FORCE_SYNCH_CLEAR Off +set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On +set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off +set_global_assignment -name AUTO_RESOURCE_SHARING Off +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off +set_global_assignment -name MAX7000_FANIN_PER_CELL 100 +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On +set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" +set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off +set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" +set_global_assignment -name REPORT_PARAMETER_SETTINGS On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On +set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100 +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 +set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000 +set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off +set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" +set_global_assignment -name MAX_LABS "-1 (Unlimited)" +set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On +set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" +set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On +set_global_assignment -name PRPOF_ID Off +set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off +set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On +set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name TXPMA_SLEW_RATE Low +set_global_assignment -name ADCE_ENABLED Auto +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name PHYSICAL_SYNTHESIS Off +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name ENABLE_NCEO_OUTPUT Off +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image" +set_global_assignment -name CVP_MODE Off +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V" +set_global_assignment -name VID_OPERATION_MODE "PMBus Slave" +set_global_assignment -name USE_CONF_DONE AUTO +set_global_assignment -name USE_PWRMGT_SCL AUTO +set_global_assignment -name USE_PWRMGT_SDA AUTO +set_global_assignment -name USE_PWRMGT_ALERT AUTO +set_global_assignment -name USE_INIT_DONE AUTO +set_global_assignment -name USE_CVP_CONFDONE AUTO +set_global_assignment -name USE_SEU_ERROR AUTO +set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off +set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On +set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name INIT_DONE_OPEN_DRAIN On +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name ENABLE_CONFIGURATION_PINS On +set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off +set_global_assignment -name ENABLE_NCE_PIN Off +set_global_assignment -name ENABLE_BOOT_SEL_PIN On +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name INTERNAL_SCRUBBING Off +set_global_assignment -name PR_ERROR_OPEN_DRAIN On +set_global_assignment -name PR_READY_OPEN_DRAIN On +set_global_assignment -name ENABLE_CVP_CONFDONE Off +set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On +set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ" +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF +set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto +set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V" +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto +set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" +set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off +set_global_assignment -name PR_DONE_OPEN_DRAIN On +set_global_assignment -name NCEO_OPEN_DRAIN On +set_global_assignment -name ENABLE_CRC_ERROR_PIN Off +set_global_assignment -name ENABLE_PR_PINS Off +set_global_assignment -name RESERVE_PR_PINS Off +set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off +set_global_assignment -name PR_PINS_OPEN_DRAIN Off +set_global_assignment -name CLAMPING_DIODE Off +set_global_assignment -name TRI_STATE_SPI_PINS Off +set_global_assignment -name UNUSED_TSD_PINS_GND Off +set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off +set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V" +set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0 +set_global_assignment -name SEU_FIT_REPORT Off +set_global_assignment -name HYPER_RETIMER Off -family "Arria 10" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE On +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130" +set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000 +set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery" +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0 +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP" +set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V" +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF +set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off +set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off +set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off +set_global_assignment -name POR_SCHEME "Instant ON" +set_global_assignment -name EN_USER_IO_WEAK_PULLUP On +set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On +set_global_assignment -name POF_VERIFY_PROTECT Off +set_global_assignment -name ENABLE_SPI_MODE_CHECK Off +set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On +set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0 +set_global_assignment -name GENERATE_PMSF_FILES On +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off +set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO +set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name DRC_GATED_CLOCK_FEED 30 +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name ENABLE_DRC_SETTINGS Off +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 +set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 +set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 +set_global_assignment -name MERGE_HEX_FILE Off +set_global_assignment -name GENERATE_SVF_FILE Off +set_global_assignment -name GENERATE_ISC_FILE Off +set_global_assignment -name GENERATE_JAM_FILE Off +set_global_assignment -name GENERATE_JBC_FILE Off +set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off +set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off +set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" +set_global_assignment -name HPS_EARLY_IO_RELEASE Off +set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off +set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name POWER_HPS_ENABLE Off +set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 +set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off +set_global_assignment -name IGNORE_PARTITIONS Off +set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off +set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On +set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" +set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On +set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On +set_global_assignment -name RTLV_GROUP_RELATED_NODES On +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off +set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On +set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On +set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On +set_global_assignment -name EQC_BBOX_MERGE On +set_global_assignment -name EQC_LVDS_MERGE On +set_global_assignment -name EQC_RAM_UNMERGING On +set_global_assignment -name EQC_DFF_SS_EMULATION On +set_global_assignment -name EQC_RAM_REGISTER_UNPACK On +set_global_assignment -name EQC_MAC_REGISTER_UNPACK On +set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? +set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? +set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? +set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST On -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? +set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? +set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? +set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? +set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? +set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? +set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ? diff --git a/src/fpga/apf/apf.qip b/src/fpga/apf/apf.qip new file mode 100644 index 0000000..f6786a8 --- /dev/null +++ b/src/fpga/apf/apf.qip @@ -0,0 +1,7 @@ +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "apf_top.v"] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "common.v"] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "io_bridge_peripheral.v"] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "io_pad_controller.v"] +set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) "apf_constraints.sdc"] +set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "mf_ddio_bidir_12.qip"] +set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "mf_datatable.qip"] diff --git a/src/fpga/apf/apf_constraints.sdc b/src/fpga/apf/apf_constraints.sdc new file mode 100644 index 0000000..048ddcf --- /dev/null +++ b/src/fpga/apf/apf_constraints.sdc @@ -0,0 +1,20 @@ +# +# APF constraints +# Do not edit this file. +# +# Add your own constraints in the \core_constraints.sdc in the core directory, which will also be loaded. + +create_clock -name clk_74a -period 13.468 [get_ports clk_74a] +create_clock -name clk_74b -period 13.468 [get_ports clk_74b] +create_clock -name bridge_spiclk -period 13.468 [get_ports bridge_spiclk] + +# autogenerate PLL clock names for use down below +derive_pll_clocks + + +# io constraints go here +# + + +# load in user constraints +read_sdc "core/core_constraints.sdc" \ No newline at end of file diff --git a/src/fpga/apf/apf_top.v b/src/fpga/apf/apf_top.v new file mode 100644 index 0000000..e82f37b --- /dev/null +++ b/src/fpga/apf/apf_top.v @@ -0,0 +1,475 @@ +// Software License Agreement + +// The software supplied herewith by Analogue Enterprises Limited (the "Company”), +// the Analogue Pocket Framework (“APF”), is provided and licensed to you, the +// Company's customer, solely for use in designing, testing and creating +// applications for use with Company's Products or Services. The software is +// owned by the Company and/or its licensors, and is protected under applicable +// laws, including, but not limited to, U.S. copyright law. All rights are +// reserved. By using the APF code you are agreeing to the terms of the End User +// License Agreement (“EULA”) located at [https://www.analogue.link/pocket-eula] +// and incorporated herein by reference. To the extent any use of the APF requires +// application of the MIT License or the GNU General Public License and terms of +// this APF Software License Agreement and EULA are inconsistent with such license, +// the applicable terms of the MIT License or the GNU General Public License, as +// applicable, will prevail. + +// THE SOFTWARE IS PROVIDED "AS-IS" AND WE EXPRESSLY DISCLAIM ANY IMPLIED +// WARRANTIES TO THE FULLEST EXTENT PROVIDED BY LAW, INCLUDING BUT NOT LIMITED TO, +// ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE OR +// NON-INFRINGEMENT. TO THE EXTENT APPLICABLE LAWS PROHIBIT TERMS OF USE FROM +// DISCLAIMING ANY IMPLIED WARRANTY, SUCH IMPLIED WARRANTY SHALL BE LIMITED TO THE +// MINIMUM WARRANTY PERIOD REQUIRED BY LAW, AND IF NO SUCH PERIOD IS REQUIRED, +// THEN THIRTY (30) DAYS FROM FIRST USE OF THE SOFTWARE. WE CANNOT GUARANTEE AND +// DO NOT PROMISE ANY SPECIFIC RESULTS FROM USE OF THE SOFTWARE. WITHOUT LIMITING +// THE FOREGOING, WE DO NOT WARRANT THAT THE SOFTWARE WILL BE UNINTERRUPTED OR +// ERROR-FREE. IN NO EVENT WILL WE BE LIABLE TO YOU OR ANY OTHER PERSON FOR ANY +// INDIRECT, CONSEQUENTIAL, EXEMPLARY, INCIDENTAL, SPECIAL OR PUNITIVE DAMAGES, +// INCLUDING BUT NOT LIMITED TO, LOST PROFITS ARISING OUT OF YOUR USE, OR +// INABILITY TO USE, THE SOFTWARE, EVEN IF WE HAVE BEEN ADVISED OF THE POSSIBILITY +// OF SUCH DAMAGES. UNDER NO CIRCUMSTANCES SHALL OUR LIABILITY TO YOU FOR ANY +// CLAIM OR CAUSE OF ACTION WHATSOEVER, AND REGARDLESS OF THE FORM OF THE ACTION, +// WHETHER ARISING IN CONTRACT, TORT OR OTHERWISE, EXCEED THE AMOUNT PAID BY YOU +// TO US, IF ANY, DURING THE 90 DAY PERIOD IMMEDIATELY PRECEDING THE DATE ON WHICH +// YOU FIRST ASSERT ANY SUCH CLAIM. THE FOREGOING LIMITATIONS SHALL APPLY TO THE +// FULLEST EXTENT PERMITTED BY APPLICABLE LAW. +// +// 6515C - Analogue Pocket main unit +// SOCRATES FPGA +// +// 2022-08-17 Analogue + +`default_nettype none + +module apf_top ( +/////////////////////////////////////////////////// +// clock inputs 74.25mhz. not phase aligned, so treat these domains as asynchronous + +input wire clk_74a, // mainclk1 +input wire clk_74b, // mainclk1 + +/////////////////////////////////////////////////// +// cartridge interface +// switches between 3.3v and 5v mechanically +// output enable for multibit translators controlled by PIC32 + +// GBA AD[15:8] +inout wire [7:0] cart_tran_bank2, +output wire cart_tran_bank2_dir, + +// GBA AD[7:0] +inout wire [7:0] cart_tran_bank3, +output wire cart_tran_bank3_dir, + +// GBA A[23:16] +inout wire [7:0] cart_tran_bank1, +output wire cart_tran_bank1_dir, + +// GBA [7] PHI# +// GBA [6] WR# +// GBA [5] RD# +// GBA [4] CS1#/CS# +// [3:0] unwired +inout wire [7:4] cart_tran_bank0, +output wire cart_tran_bank0_dir, + +// GBA CS2#/RES# +inout wire cart_tran_pin30, +output wire cart_tran_pin30_dir, +// when GBC cart is inserted, this signal when low or weak will pull GBC /RES low with a special circuit +// the goal is that when unconfigured, the FPGA weak pullups won't interfere. +// thus, if GBC cart is inserted, FPGA must drive this high in order to let the level translators +// and general IO drive this pin. +output wire cart_pin30_pwroff_reset, + +// GBA IRQ/DRQ +inout wire cart_tran_pin31, +output wire cart_tran_pin31_dir, + +// infrared +// avoid driving the TX LED with DC or leaving it stuck on. pulsed usage is fine +input wire port_ir_rx, +output wire port_ir_tx, +output wire port_ir_rx_disable, + +// GBA link port +inout wire port_tran_si, +output wire port_tran_si_dir, +inout wire port_tran_so, +output wire port_tran_so_dir, +inout wire port_tran_sck, +output wire port_tran_sck_dir, +inout wire port_tran_sd, +output wire port_tran_sd_dir, + +/////////////////////////////////////////////////// +// video output to the scaler + +inout wire [11:0] scal_vid, +inout wire scal_clk, +inout wire scal_de, +inout wire scal_skip, +inout wire scal_vs, +inout wire scal_hs, + +output wire scal_audmclk, +input wire scal_audadc, +output wire scal_auddac, +output wire scal_audlrck, + +/////////////////////////////////////////////////// +// communication between main and scaler (aristotle) fpga. +// spi bus with aristotle as controller. + +inout wire bridge_spimosi, +inout wire bridge_spimiso, +inout wire bridge_spiclk, +input wire bridge_spiss, +inout wire bridge_1wire, + +/////////////////////////////////////////////////// +// cellular psram 0 and 1, two chips (64mbit x2 dual die per chip) + +output wire [21:16] cram0_a, +inout wire [15:0] cram0_dq, +input wire cram0_wait, +output wire cram0_clk, +output wire cram0_adv_n, +output wire cram0_cre, +output wire cram0_ce0_n, +output wire cram0_ce1_n, +output wire cram0_oe_n, +output wire cram0_we_n, +output wire cram0_ub_n, +output wire cram0_lb_n, + +output wire [21:16] cram1_a, +inout wire [15:0] cram1_dq, +input wire cram1_wait, +output wire cram1_clk, +output wire cram1_adv_n, +output wire cram1_cre, +output wire cram1_ce0_n, +output wire cram1_ce1_n, +output wire cram1_oe_n, +output wire cram1_we_n, +output wire cram1_ub_n, +output wire cram1_lb_n, + +/////////////////////////////////////////////////// +// sdram, 512mbit x16 + +output wire [12:0] dram_a, +output wire [1:0] dram_ba, +inout wire [15:0] dram_dq, +output wire [1:0] dram_dqm, +output wire dram_clk, +output wire dram_cke, +output wire dram_ras_n, +output wire dram_cas_n, +output wire dram_we_n, + +/////////////////////////////////////////////////// +// sram, 1mbit x16 + +output wire [16:0] sram_a, +inout wire [15:0] sram_dq, +output wire sram_oe_n, +output wire sram_we_n, +output wire sram_ub_n, +output wire sram_lb_n, + +/////////////////////////////////////////////////// +// vblank output to scaler + +input wire vblank, + +/////////////////////////////////////////////////// +// i/o to 6515D breakout usb uart + +output wire dbg_tx, +input wire dbg_rx, + +/////////////////////////////////////////////////// +// i/o pads near jtag connector user can solder to + +output wire user1, +input wire user2, + +/////////////////////////////////////////////////// +// powerup self test, do not use + +inout wire bist, +output wire vpll_feed, + +/////////////////////////////////////////////////// +// RFU internal i2c bus (DNU) + +inout wire aux_sda, +output wire aux_scl + +); + +assign bist = 1'bZ; + +// reset generation + + reg [24:0] count; + reg reset_n; + +initial begin + count <= 0; + reset_n <= 0; +end +always @(posedge clk_74a) begin + count <= count + 1'b1; + + if(count[15]) begin + // exit reset + reset_n <= 1; + end + +end + + + + +// convert 24-bit rgb data to 12-bit DDR for ARISTOTLE + + wire [23:0] video_rgb; + wire video_rgb_clock; + wire video_rgb_clock_90; + wire video_de; + wire video_skip; + wire video_vs; + wire video_hs; + +mf_ddio_bidir_12 isco ( + .oe ( 1'b1 ), + .datain_h ( video_rgb[23:12] ), + .datain_l ( video_rgb[11: 0] ), + .outclock ( video_rgb_clock ), + .padio ( scal_ddio_12 ) +); + +wire [11:0] scal_ddio_12; +assign scal_vid = scal_ddio_12; + +mf_ddio_bidir_12 iscc ( + .oe ( 1'b1 ), + .datain_h ( {video_vs, video_hs, video_de, video_skip} ), + .datain_l ( {video_vs, video_hs, video_de, video_skip} ), + .outclock ( video_rgb_clock ), + .padio ( scal_ddio_ctrl ) +); + +wire [3:0] scal_ddio_ctrl; +assign scal_vs = scal_ddio_ctrl[3]; +assign scal_hs = scal_ddio_ctrl[2]; +assign scal_de = scal_ddio_ctrl[1]; +assign scal_skip = scal_ddio_ctrl[0]; + +mf_ddio_bidir_12 isclk( + .oe ( 1'b1 ), + .datain_h ( 1'b1 ), + .datain_l ( 1'b0 ), + .outclock ( video_rgb_clock_90 ), + .padio ( scal_clk ) +); + + + +// controller data (pad) controller. + wire [15:0] cont1_key; + wire [15:0] cont2_key; + wire [15:0] cont3_key; + wire [15:0] cont4_key; + wire [31:0] cont1_joy; + wire [31:0] cont2_joy; + wire [31:0] cont3_joy; + wire [31:0] cont4_joy; + wire [15:0] cont1_trig; + wire [15:0] cont2_trig; + wire [15:0] cont3_trig; + wire [15:0] cont4_trig; + +io_pad_controller ipm ( + .clk ( clk_74a ), + .reset_n ( reset_n ), + + .pad_1wire ( bridge_1wire ), + + .cont1_key ( cont1_key ), + .cont2_key ( cont2_key ), + .cont3_key ( cont3_key ), + .cont4_key ( cont4_key ), + .cont1_joy ( cont1_joy ), + .cont2_joy ( cont2_joy ), + .cont3_joy ( cont3_joy ), + .cont4_joy ( cont4_joy ), + .cont1_trig ( cont1_trig ), + .cont2_trig ( cont2_trig ), + .cont3_trig ( cont3_trig ), + .cont4_trig ( cont4_trig ) +); + + +// virtual pmp bridge + wire bridge_endian_little; + wire [31:0] bridge_addr; + wire bridge_rd; + wire [31:0] bridge_rd_data; + wire bridge_wr; + wire [31:0] bridge_wr_data; + +io_bridge_peripheral ibs ( + + .clk ( clk_74a ), + .reset_n ( reset_n ), + + .endian_little ( bridge_endian_little ), + + .pmp_addr ( bridge_addr ), + .pmp_rd ( bridge_rd ), + .pmp_rd_data ( bridge_rd_data ), + .pmp_wr ( bridge_wr ), + .pmp_wr_data ( bridge_wr_data ), + + .phy_spimosi ( bridge_spimosi ), + .phy_spimiso ( bridge_spimiso ), + .phy_spiclk ( bridge_spiclk ), + .phy_spiss ( bridge_spiss ) + +); + + +/////////////////////////////////////////////////// +// instantiate the user core top-level + +core_top ic ( + + // physical connections + // + .clk_74a ( clk_74a ), + .clk_74b ( clk_74b ), + + .cart_tran_bank2 ( cart_tran_bank2 ), + .cart_tran_bank2_dir ( cart_tran_bank2_dir ), + .cart_tran_bank3 ( cart_tran_bank3 ), + .cart_tran_bank3_dir ( cart_tran_bank3_dir ), + .cart_tran_bank1 ( cart_tran_bank1 ), + .cart_tran_bank1_dir ( cart_tran_bank1_dir ), + .cart_tran_bank0 ( cart_tran_bank0 ), + .cart_tran_bank0_dir ( cart_tran_bank0_dir ), + .cart_tran_pin30 ( cart_tran_pin30 ), + .cart_tran_pin30_dir ( cart_tran_pin30_dir ), + .cart_pin30_pwroff_reset ( cart_pin30_pwroff_reset ), + .cart_tran_pin31 ( cart_tran_pin31 ), + .cart_tran_pin31_dir ( cart_tran_pin31_dir ), + + .port_ir_rx ( port_ir_rx ), + .port_ir_tx ( port_ir_tx ), + .port_ir_rx_disable ( port_ir_rx_disable ), + + .port_tran_si ( port_tran_si ), + .port_tran_si_dir ( port_tran_si_dir ), + .port_tran_so ( port_tran_so ), + .port_tran_so_dir ( port_tran_so_dir ), + .port_tran_sck ( port_tran_sck ), + .port_tran_sck_dir ( port_tran_sck_dir ), + .port_tran_sd ( port_tran_sd ), + .port_tran_sd_dir ( port_tran_sd_dir ), + + .cram0_a ( cram0_a ), + .cram0_dq ( cram0_dq ), + .cram0_wait ( cram0_wait ), + .cram0_clk ( cram0_clk ), + .cram0_adv_n ( cram0_adv_n ), + .cram0_cre ( cram0_cre ), + .cram0_ce0_n ( cram0_ce0_n ), + .cram0_ce1_n ( cram0_ce1_n ), + .cram0_oe_n ( cram0_oe_n ), + .cram0_we_n ( cram0_we_n ), + .cram0_ub_n ( cram0_ub_n ), + .cram0_lb_n ( cram0_lb_n ), + .cram1_a ( cram1_a ), + .cram1_dq ( cram1_dq ), + .cram1_wait ( cram1_wait ), + .cram1_clk ( cram1_clk ), + .cram1_adv_n ( cram1_adv_n ), + .cram1_cre ( cram1_cre ), + .cram1_ce0_n ( cram1_ce0_n ), + .cram1_ce1_n ( cram1_ce1_n ), + .cram1_oe_n ( cram1_oe_n ), + .cram1_we_n ( cram1_we_n ), + .cram1_ub_n ( cram1_ub_n ), + .cram1_lb_n ( cram1_lb_n ), + + .dram_a ( dram_a ), + .dram_ba ( dram_ba ), + .dram_dq ( dram_dq ), + .dram_dqm ( dram_dqm ), + .dram_clk ( dram_clk ), + .dram_cke ( dram_cke ), + .dram_ras_n ( dram_ras_n ), + .dram_cas_n ( dram_cas_n ), + .dram_we_n ( dram_we_n ), + + .sram_a ( sram_a ), + .sram_dq ( sram_dq ), + .sram_oe_n ( sram_oe_n ), + .sram_we_n ( sram_we_n ), + .sram_ub_n ( sram_ub_n ), + .sram_lb_n ( sram_lb_n ), + + .vblank ( vblank ), + .vpll_feed ( vpll_feed ), + + .dbg_tx ( dbg_tx ), + .dbg_rx ( dbg_rx ), + .user1 ( user1 ), + .user2 ( user2 ), + + .aux_sda ( aux_sda ), + .aux_scl ( aux_scl ), + + + // logical connections with user core + // + .video_rgb ( video_rgb ), + .video_rgb_clock ( video_rgb_clock ), + .video_rgb_clock_90 ( video_rgb_clock_90 ), + .video_de ( video_de ), + .video_skip ( video_skip ), + .video_vs ( video_vs ), + .video_hs ( video_hs ), + + .audio_mclk ( scal_audmclk ), + .audio_adc ( scal_audadc ), + .audio_dac ( scal_auddac ), + .audio_lrck ( scal_audlrck ), + + .bridge_endian_little ( bridge_endian_little ), + .bridge_addr ( bridge_addr ), + .bridge_rd ( bridge_rd ), + .bridge_rd_data ( bridge_rd_data ), + .bridge_wr ( bridge_wr ), + .bridge_wr_data ( bridge_wr_data ), + + .cont1_key ( cont1_key ), + .cont2_key ( cont2_key ), + .cont3_key ( cont3_key ), + .cont4_key ( cont4_key ), + .cont1_joy ( cont1_joy ), + .cont2_joy ( cont2_joy ), + .cont3_joy ( cont3_joy ), + .cont4_joy ( cont4_joy ), + .cont1_trig ( cont1_trig ), + .cont2_trig ( cont2_trig ), + .cont3_trig ( cont3_trig ), + .cont4_trig ( cont4_trig ) + +); + +endmodule + diff --git a/src/fpga/apf/build_id.mif b/src/fpga/apf/build_id.mif new file mode 100644 index 0000000..a70cb06 --- /dev/null +++ b/src/fpga/apf/build_id.mif @@ -0,0 +1,16 @@ +-- Build ID Memory Initialization File +-- + +DEPTH = 256; +WIDTH = 32; +ADDRESS_RADIX = HEX; +DATA_RADIX = HEX; + +CONTENT +BEGIN + + 0E0 : 20220916; + 0E1 : 00141807; + 0E2 : 8bb2844e; + +END; diff --git a/src/fpga/apf/build_id_gen.tcl b/src/fpga/apf/build_id_gen.tcl new file mode 100644 index 0000000..eb598fd --- /dev/null +++ b/src/fpga/apf/build_id_gen.tcl @@ -0,0 +1,171 @@ +# ================================================================================ +# (c) 2011 Altera Corporation. All rights reserved. +# Altera products are protected under numerous U.S. and foreign patents, maskwork +# rights, copyrights and other intellectual property laws. +# +# This reference design file, and your use thereof, is subject to and governed +# by the terms and conditions of the applicable Altera Reference Design License +# Agreement (either as signed by you, agreed by you upon download or as a +# "click-through" agreement upon installation andor found at www.altera.com). +# By using this reference design file, you indicate your acceptance of such terms +# and conditions between you and Altera Corporation. In the event that you do +# not agree with such terms and conditions, you may not use the reference design +# file and please promptly destroy any copies you have made. +# +# This reference design file is being provided on an "as-is" basis and as an +# accommodation and therefore all warranties, representations or guarantees of +# any kind (whether express, implied or statutory) including, without limitation, +# warranties of merchantability, non-infringement, or fitness for a particular +# purpose, are specifically disclaimed. By making this reference design file +# available, Altera expressly does not recommend, suggest or require that this +# reference design file be used in combination with any other product not +# provided by Altera. +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, physical address, and host name +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# The format for each value is as follows: +# Date - 32-bit decimal number of the format mmddyyyy +# Time - 32-bit decimal number of the format hhmmss +# Phyiscal Address - 48-bit hexadecimal number +# Host name - 120-bit hexadecimal number with pairs of digits equal to the +# hexadecimal code for the first 15 ASCII characters of the host +# name. For added clarity, host names that have fewer than 30 +# hexadecimal digits (15 characters) are padded on the left with +# zeros. +# +# Usage: +# +# To manually execute this script, source this file using the following Tcl commands: +# source build_id_verilog.tcl +# +# To have this script automatically execute each time your project is built, use the +# following command (see: http://www.altera.com/support/examples/tcl/auto_processing.html): +# set_global_assignment -name PRE_FLOW_SCRIPT_FILE quartus_sh:build_id_verilog.tcl +# +# Comment out the last line to prevent the process from automatically executing when +# the file is sourced. The process can then be executed with the following command: +# generateBuildID_Verilog +# +# +# For more information, see "build_identification.pdf" +# +# ================================================================================ +# +# 2021-01-21 Analogue +# +# Only care about generating build date/time, so the rest was removed. +# The original can be downloaded from the Intel resource page +# + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %Y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "apf/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "// Build ID Verilog Module" + puts $outputFile "//" + puts $outputFile "// Note - these are stored as binary coded decimal" + puts $outputFile "// Date: $buildDate" + puts $outputFile "// Time: $buildTime" + puts $outputFile "" + puts $outputFile "module build_id" + puts $outputFile "(" + puts $outputFile " output \[31:0\] build_date," + puts $outputFile " output \[31:0\] build_time" + puts $outputFile ");" + puts $outputFile "" + puts $outputFile " assign build_date = 32'h$buildDate;" + puts $outputFile " assign build_time = 32'h$buildTime;" + puts $outputFile "" + puts $outputFile "endmodule" + close $outputFile + + + + # Send confirmation message to the Messages window + #post_message "APF core build date/time generated: [pwd]/$outputFileName" + #post_message "Date: $buildDate" + #post_message "Time: $buildTime" +} + + +proc generateBuildID_MIF {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %Y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + set buildUnique [expr {int(rand()*(4294967295))}] + + set buildDateNoLeadingZeros [string trimleft $buildDate "0"] + set buildTimeNoLeadingZeros [string trimleft $buildTime "0"] + set buildDate4Byte [format "%08d" $buildDateNoLeadingZeros] + set buildTime4Byte [format "%08d" $buildTimeNoLeadingZeros] + set buildUnique4Byte [format "%08x" $buildUnique] + + #set buildDate4Byte \ + [concat [string range $buildDate 0 1] \ + [string range $buildDate 2 3] \ + [string range $buildDate 4 5] \ + [string range $buildDate 6 7] ] + + + set buildDateNumBytes 4 + set buildTimeNumBytes 4 + + # Calculate depth of the memory (8-bit) words + set memoryDepth [expr $buildDateNumBytes + $buildTimeNumBytes] + + # Create a Memory Initialization File for output + set outputFileName "apf/build_id.mif" + set outputFile [open $outputFileName "w"] + + # Output the MIF header (see: http://quartushelp.altera.com/current/mergedProjects/reference/glossary/def_mif.htm) + puts $outputFile "-- Build ID Memory Initialization File" + puts $outputFile "--" + puts $outputFile "" + puts $outputFile "DEPTH = 256;" + puts $outputFile "WIDTH = 32;" + puts $outputFile "ADDRESS_RADIX = HEX;" + puts $outputFile "DATA_RADIX = HEX;" + puts $outputFile "" + puts $outputFile "CONTENT" + puts $outputFile "BEGIN" + puts $outputFile "" + puts $outputFile " 0E0 : $buildDate4Byte;" + puts $outputFile " 0E1 : $buildTime4Byte;" + puts $outputFile " 0E2 : $buildUnique4Byte;" + puts $outputFile "" + puts $outputFile "END;" + + # Close file to complete write + close $outputFile + + # Send confirmation message to the Messages window + post_message "APF core build date/time generated: [pwd]/$outputFileName" +} + +generateBuildID_MIF + +# 2021-01-21 Analogue +# +# There are some circumstances where you want all parts of a FPGA flow to be deterministic, especially +# when trying to hash out timing issues. +# You should comment this line out and temporarily bypass buildid generation so that synthesis/par +# have consistent working input. MIF bram contents like above won't affect the random seed or trigger +# recompilation. +# Don't forget to re-enable before you release. +# +# generateBuildID_Verilog diff --git a/src/fpga/apf/common.v b/src/fpga/apf/common.v new file mode 100644 index 0000000..6481788 --- /dev/null +++ b/src/fpga/apf/common.v @@ -0,0 +1,156 @@ +// Software License Agreement + +// The software supplied herewith by Analogue Enterprises Limited (the "Company”), +// the Analogue Pocket Framework (“APF”), is provided and licensed to you, the +// Company's customer, solely for use in designing, testing and creating +// applications for use with Company's Products or Services. The software is +// owned by the Company and/or its licensors, and is protected under applicable +// laws, including, but not limited to, U.S. copyright law. All rights are +// reserved. By using the APF code you are agreeing to the terms of the End User +// License Agreement (“EULA”) located at [https://www.analogue.link/pocket-eula] +// and incorporated herein by reference. To the extent any use of the APF requires +// application of the MIT License or the GNU General Public License and terms of +// this APF Software License Agreement and EULA are inconsistent with such license, +// the applicable terms of the MIT License or the GNU General Public License, as +// applicable, will prevail. + +// THE SOFTWARE IS PROVIDED "AS-IS" AND WE EXPRESSLY DISCLAIM ANY IMPLIED +// WARRANTIES TO THE FULLEST EXTENT PROVIDED BY LAW, INCLUDING BUT NOT LIMITED TO, +// ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE OR +// NON-INFRINGEMENT. TO THE EXTENT APPLICABLE LAWS PROHIBIT TERMS OF USE FROM +// DISCLAIMING ANY IMPLIED WARRANTY, SUCH IMPLIED WARRANTY SHALL BE LIMITED TO THE +// MINIMUM WARRANTY PERIOD REQUIRED BY LAW, AND IF NO SUCH PERIOD IS REQUIRED, +// THEN THIRTY (30) DAYS FROM FIRST USE OF THE SOFTWARE. WE CANNOT GUARANTEE AND +// DO NOT PROMISE ANY SPECIFIC RESULTS FROM USE OF THE SOFTWARE. WITHOUT LIMITING +// THE FOREGOING, WE DO NOT WARRANT THAT THE SOFTWARE WILL BE UNINTERRUPTED OR +// ERROR-FREE. IN NO EVENT WILL WE BE LIABLE TO YOU OR ANY OTHER PERSON FOR ANY +// INDIRECT, CONSEQUENTIAL, EXEMPLARY, INCIDENTAL, SPECIAL OR PUNITIVE DAMAGES, +// INCLUDING BUT NOT LIMITED TO, LOST PROFITS ARISING OUT OF YOUR USE, OR +// INABILITY TO USE, THE SOFTWARE, EVEN IF WE HAVE BEEN ADVISED OF THE POSSIBILITY +// OF SUCH DAMAGES. UNDER NO CIRCUMSTANCES SHALL OUR LIABILITY TO YOU FOR ANY +// CLAIM OR CAUSE OF ACTION WHATSOEVER, AND REGARDLESS OF THE FORM OF THE ACTION, +// WHETHER ARISING IN CONTRACT, TORT OR OTHERWISE, EXCEED THE AMOUNT PAID BY YOU +// TO US, IF ANY, DURING THE 90 DAY PERIOD IMMEDIATELY PRECEDING THE DATE ON WHICH +// YOU FIRST ASSERT ANY SUCH CLAIM. THE FOREGOING LIMITATIONS SHALL APPLY TO THE +// FULLEST EXTENT PERMITTED BY APPLICABLE LAW. +// +// 2-stage synchronizer +// +module synch_2 #(parameter WIDTH = 1) ( + input wire [WIDTH-1:0] i, // input signal + output reg [WIDTH-1:0] o, // synchronized output + input wire clk, // clock to synchronize on + output wire rise, // one-cycle rising edge pulse + output wire fall // one-cycle falling edge pulse +); + +reg [WIDTH-1:0] stage_1; +reg [WIDTH-1:0] stage_2; +reg [WIDTH-1:0] stage_3; + +assign rise = (WIDTH == 1) ? (o & ~stage_2) : 1'b0; +assign fall = (WIDTH == 1) ? (~o & stage_2) : 1'b0; +always @(posedge clk) + {stage_2, o, stage_1} <= {o, stage_1, i}; + +endmodule + + +// +// 3-stage synchronizer +// +module synch_3 #(parameter WIDTH = 1) ( + input wire [WIDTH-1:0] i, // input signal + output reg [WIDTH-1:0] o, // synchronized output + input wire clk, // clock to synchronize on + output wire rise, // one-cycle rising edge pulse + output wire fall // one-cycle falling edge pulse +); + +reg [WIDTH-1:0] stage_1; +reg [WIDTH-1:0] stage_2; +reg [WIDTH-1:0] stage_3; + +assign rise = (WIDTH == 1) ? (o & ~stage_3) : 1'b0; +assign fall = (WIDTH == 1) ? (~o & stage_3) : 1'b0; +always @(posedge clk) + {stage_3, o, stage_2, stage_1} <= {o, stage_2, stage_1, i}; + +endmodule + + +module bram_block_dp #( + parameter DATA = 32, + parameter ADDR = 7 +) ( + input wire a_clk, + input wire a_wr, + input wire [ADDR-1:0] a_addr, + input wire [DATA-1:0] a_din, + output reg [DATA-1:0] a_dout, + + input wire b_clk, + input wire b_wr, + input wire [ADDR-1:0] b_addr, + input wire [DATA-1:0] b_din, + output reg [DATA-1:0] b_dout +); + +reg [DATA-1:0] mem [(2**ADDR)-1:0]; + +always @(posedge a_clk) begin + if(a_wr) begin + a_dout <= a_din; + mem[a_addr] <= a_din; + end else + a_dout <= mem[a_addr]; +end + +always @(posedge b_clk) begin + if(b_wr) begin + b_dout <= b_din; + mem[b_addr] <= b_din; + end else + b_dout <= mem[b_addr]; +end + +endmodule + + +module bram_block_dp_nonstd #( + parameter DATA = 32, + parameter ADDR = 7, + parameter DEPTH = 128 +) ( + input wire a_clk, + input wire a_wr, + input wire [ADDR-1:0] a_addr, + input wire [DATA-1:0] a_din, + output reg [DATA-1:0] a_dout, + + input wire b_clk, + input wire b_wr, + input wire [ADDR-1:0] b_addr, + input wire [DATA-1:0] b_din, + output reg [DATA-1:0] b_dout +); + +reg [DATA-1:0] mem [DEPTH-1:0]; + +always @(posedge a_clk) begin + if(a_wr) begin + a_dout <= a_din; + mem[a_addr] <= a_din; + end else + a_dout <= mem[a_addr]; +end + +always @(posedge b_clk) begin + if(b_wr) begin + b_dout <= b_din; + mem[b_addr] <= b_din; + end else + b_dout <= mem[b_addr]; +end + +endmodule diff --git a/src/fpga/apf/io_bridge_peripheral.v b/src/fpga/apf/io_bridge_peripheral.v new file mode 100644 index 0000000..eda3bb0 --- /dev/null +++ b/src/fpga/apf/io_bridge_peripheral.v @@ -0,0 +1,334 @@ +// Software License Agreement + +// The software supplied herewith by Analogue Enterprises Limited (the "Company”), +// the Analogue Pocket Framework (“APF”), is provided and licensed to you, the +// Company's customer, solely for use in designing, testing and creating +// applications for use with Company's Products or Services. The software is +// owned by the Company and/or its licensors, and is protected under applicable +// laws, including, but not limited to, U.S. copyright law. All rights are +// reserved. By using the APF code you are agreeing to the terms of the End User +// License Agreement (“EULA”) located at [https://www.analogue.link/pocket-eula] +// and incorporated herein by reference. To the extent any use of the APF requires +// application of the MIT License or the GNU General Public License and terms of +// this APF Software License Agreement and EULA are inconsistent with such license, +// the applicable terms of the MIT License or the GNU General Public License, as +// applicable, will prevail. + +// THE SOFTWARE IS PROVIDED "AS-IS" AND WE EXPRESSLY DISCLAIM ANY IMPLIED +// WARRANTIES TO THE FULLEST EXTENT PROVIDED BY LAW, INCLUDING BUT NOT LIMITED TO, +// ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE OR +// NON-INFRINGEMENT. TO THE EXTENT APPLICABLE LAWS PROHIBIT TERMS OF USE FROM +// DISCLAIMING ANY IMPLIED WARRANTY, SUCH IMPLIED WARRANTY SHALL BE LIMITED TO THE +// MINIMUM WARRANTY PERIOD REQUIRED BY LAW, AND IF NO SUCH PERIOD IS REQUIRED, +// THEN THIRTY (30) DAYS FROM FIRST USE OF THE SOFTWARE. WE CANNOT GUARANTEE AND +// DO NOT PROMISE ANY SPECIFIC RESULTS FROM USE OF THE SOFTWARE. WITHOUT LIMITING +// THE FOREGOING, WE DO NOT WARRANT THAT THE SOFTWARE WILL BE UNINTERRUPTED OR +// ERROR-FREE. IN NO EVENT WILL WE BE LIABLE TO YOU OR ANY OTHER PERSON FOR ANY +// INDIRECT, CONSEQUENTIAL, EXEMPLARY, INCIDENTAL, SPECIAL OR PUNITIVE DAMAGES, +// INCLUDING BUT NOT LIMITED TO, LOST PROFITS ARISING OUT OF YOUR USE, OR +// INABILITY TO USE, THE SOFTWARE, EVEN IF WE HAVE BEEN ADVISED OF THE POSSIBILITY +// OF SUCH DAMAGES. UNDER NO CIRCUMSTANCES SHALL OUR LIABILITY TO YOU FOR ANY +// CLAIM OR CAUSE OF ACTION WHATSOEVER, AND REGARDLESS OF THE FORM OF THE ACTION, +// WHETHER ARISING IN CONTRACT, TORT OR OTHERWISE, EXCEED THE AMOUNT PAID BY YOU +// TO US, IF ANY, DURING THE 90 DAY PERIOD IMMEDIATELY PRECEDING THE DATE ON WHICH +// YOU FIRST ASSERT ANY SUCH CLAIM. THE FOREGOING LIMITATIONS SHALL APPLY TO THE +// FULLEST EXTENT PERMITTED BY APPLICABLE LAW. +// +// bridge peripheral for socrates PMP bridge to heraclitus+aristotle +// 2020-2022 Analogue +// +// please note that while writes are immediate, +// reads are buffered by 1 word. this is necessary to maintain +// data throughput while reading from slower data sources like +// sdram. +// reads should always return the current bus value, and kickstart +// into the next read immediately. this way, you have the entire +// next word time to retrieve the data, instead of just a few +// cycles. +// +// the worst-case read/write timing is every 88 cycles @ 74.25mhz +// which is about 1180ns. + +module io_bridge_peripheral ( + +input wire clk, +input wire reset_n, + +input wire endian_little, + +output reg [31:0] pmp_addr, +output reg pmp_addr_valid, +output reg pmp_rd, +input wire [31:0] pmp_rd_data, +output reg pmp_wr, +output reg [31:0] pmp_wr_data, + +inout reg phy_spimosi, +inout reg phy_spimiso, +inout reg phy_spiclk, +input wire phy_spiss + +); + +// +// clock domain: clk (74.25mhz) rising edge +// + wire reset_n_s; +synch_3 s00(reset_n, reset_n_s, clk); + + wire endian_little_s; +synch_3 s01(endian_little, endian_little_s, clk); + + wire phy_spiss_s, phy_spiss_r, phy_spiss_f; +synch_3 s02(phy_spiss, phy_spiss_s, clk, phy_spiss_r, phy_spiss_f); + + + reg [4:0] state; + localparam ST_RESET = 'd0; + localparam ST_IDLE = 'd1; + localparam ST_READ_0 = 'd2; + localparam ST_READ_1 = 'd3; + localparam ST_READ_2 = 'd4; + localparam ST_READ_3 = 'd5; + localparam ST_WRITE_0 = 'd6; + localparam ST_WRITE_1 = 'd7; + localparam ST_WRITE_2 = 'd8; + localparam ST_ADDR_0 = 'd9; + + reg [1:0] addr_cnt; + reg [1:0] data_cnt; + reg [6:0] read_cnt; + + // synchronize rd byte flag's rising edge into clk + wire rx_byte_done_s, rx_byte_done_r; +synch_3 s03(rx_byte_done, rx_byte_done_s, clk, rx_byte_done_r); + + reg [4:0] spis; + localparam ST_SIDLE = 'd1; + localparam ST_SEND_N = 'd6; + localparam ST_SEND_0 = 'd2; + localparam ST_SEND_1 = 'd3; + localparam ST_SEND_2 = 'd4; + localparam ST_SEND_3 = 'd5; + reg spis_tx; + reg [31:0] spis_word_tx; + reg [31:0] spis_word; + reg [4:0] spis_count; + reg spis_done; + + reg rx_byte_done_r_1, rx_byte_done_r_2; + reg [7:0] rx_byte_1, rx_byte_2; + + // handle reversing endianness on both ports + reg [31:0] pmp_wr_data_latch; + reg [31:0] pmp_rd_data_e; // asynchronous + reg [31:0] pmp_rd_data_buf; // buffer the last word for immediate response +always @(*) begin + pmp_wr_data <= endian_little_s ? { pmp_wr_data_latch[7:0], + pmp_wr_data_latch[15:8], + pmp_wr_data_latch[23:16], + pmp_wr_data_latch[31:24] + } : pmp_wr_data_latch; + + pmp_rd_data_e <= endian_little_s ? {pmp_rd_data[7:0], + pmp_rd_data[15:8], + pmp_rd_data[23:16], + pmp_rd_data[31:24] + } : pmp_rd_data; +end + +always @(posedge clk) begin + + rx_byte_2 <= rx_byte_1; + rx_byte_1 <= rx_byte; + + rx_byte_done_r_1 <= rx_byte_done_r; + rx_byte_done_r_2 <= rx_byte_done_r_1; + + case(state) + ST_RESET: begin + addr_cnt <= 0; + data_cnt <= 0; + pmp_wr <= 0; + pmp_rd <= 0; + pmp_addr_valid <= 0; + spis_tx <= 0; + + state <= ST_ADDR_0; + end + ST_ADDR_0: begin + // transaction has started + + if(rx_byte_done_r_2) begin + case(addr_cnt) + 0: pmp_addr[31:24] <= rx_byte_2; + 1: pmp_addr[23:16] <= rx_byte_2; + 2: pmp_addr[15: 8] <= rx_byte_2; + 3: begin + pmp_addr[ 7: 0] <= {rx_byte_2[7:2], 2'b00}; + // address is latched + if( rx_byte_2[0] ) begin + data_cnt <= 0; + state <= ST_WRITE_0; + end else begin + data_cnt <= 0; + read_cnt <= 0; + state <= ST_READ_0; + end + end + endcase + + addr_cnt <= addr_cnt + 1'b1; + end + end + ST_WRITE_0: begin + // give notice, address has become valid + pmp_addr_valid <= 1; + + if(rx_byte_done_r_2) begin + case(data_cnt) + 0: pmp_wr_data_latch[31:24] <= rx_byte_2; + 1: pmp_wr_data_latch[23:16] <= rx_byte_2; + 2: pmp_wr_data_latch[15: 8] <= rx_byte_2; + 3: begin + pmp_wr_data_latch[ 7: 0] <= rx_byte_2; + state <= ST_WRITE_1; + end + endcase + data_cnt <= data_cnt + 1'b1; + end + end + ST_WRITE_1: begin + pmp_wr <= 1; + state <= ST_WRITE_2; + end + ST_WRITE_2: begin + // exited upon new transaction + pmp_wr <= 0; + end + ST_READ_0: begin + pmp_addr_valid <= 1; + + // delay a few cycles + read_cnt <= read_cnt + 1'b1; + if(read_cnt == 4-1) begin + // load the buffer with the current data + // and give the current buffer contents to bridge + spis_word_tx <= pmp_rd_data_e; + spis_tx <= 1; + + state <= ST_READ_1; + end + end + ST_READ_1: begin + pmp_rd <= 1; + state <= ST_READ_2; + end + ST_READ_2: begin + pmp_rd <= 0; + if(spis_done) begin + spis_tx <= 0; + state <= ST_READ_3; + end + end + ST_READ_3: begin + // exited upon new transaction + end + endcase + + + + + // + // word transmit + // + spis_done <= 0; + case(spis) + ST_SIDLE: begin + spis_count <= 0; + + phy_spiclk <= 1'bZ; + phy_spimosi <= 1'bZ; + phy_spimiso <= 1'bZ; + + if(spis_tx) begin + spis_word <= spis_word_tx; + spis <= ST_SEND_N; + end + end + // drive high first + ST_SEND_N: begin + phy_spiclk <= 1'b1; + phy_spimosi <= 1'b1; + phy_spimiso <= 1'b1; + spis <= ST_SEND_0; + end + // tx, shift out bits + ST_SEND_0: begin + phy_spiclk <= 0; + spis <= ST_SEND_1; + phy_spimosi <= spis_word[31]; + phy_spimiso <= spis_word[30]; + spis_word <= {spis_word[29:0], 2'b00}; + end + ST_SEND_1: begin + phy_spiclk <= 1; + spis <= ST_SEND_0; + spis_count <= spis_count + 1'b1; + if(spis_count == 15) spis <= ST_SEND_2; + end + ST_SEND_2: begin + phy_spiclk <= 1'b1; + phy_spimosi <= 1'b1; + phy_spimiso <= 1'b1; + spis <= ST_SEND_3; + spis_done <= 1; + end + ST_SEND_3: begin + spis <= ST_SIDLE; + end + endcase + + if(phy_spiss_s) begin + // select is high, go back to reset + state <= ST_RESET; + spis <= ST_SIDLE; + end + +end + + +// +// clock domain: phy_spiclk rising edge +// + reg [1:0] rx_latch_idx; + reg [7:0] rx_dat; + reg [7:0] rx_byte; // latched by clk, but upon a synchronized trigger + reg rx_byte_done; + +always @(posedge phy_spiclk or posedge phy_spiss) begin + + if(phy_spiss) begin + // reset + rx_byte_done <= 0; + rx_latch_idx <= 0; + + end else begin + // spiclk rising edge, latch data + rx_byte_done <= 0; + + case(rx_latch_idx) + 0: begin rx_dat[7:6] <= {phy_spimosi, phy_spimiso}; rx_latch_idx <= 1; end + 1: begin rx_dat[5:4] <= {phy_spimosi, phy_spimiso}; rx_latch_idx <= 2; end + 2: begin rx_dat[3:2] <= {phy_spimosi, phy_spimiso}; rx_latch_idx <= 3; end + 3: begin + // final 2 bits + rx_byte <= {rx_dat[7:2], phy_spimosi, phy_spimiso}; + rx_latch_idx <= 0; + rx_byte_done <= 1; + end + endcase + end +end + +endmodule diff --git a/src/fpga/apf/io_pad_controller.v b/src/fpga/apf/io_pad_controller.v new file mode 100644 index 0000000..c3886ac --- /dev/null +++ b/src/fpga/apf/io_pad_controller.v @@ -0,0 +1,328 @@ +// Software License Agreement + +// The software supplied herewith by Analogue Enterprises Limited (the "Company”), +// the Analogue Pocket Framework (“APF”), is provided and licensed to you, the +// Company's customer, solely for use in designing, testing and creating +// applications for use with Company's Products or Services. The software is +// owned by the Company and/or its licensors, and is protected under applicable +// laws, including, but not limited to, U.S. copyright law. All rights are +// reserved. By using the APF code you are agreeing to the terms of the End User +// License Agreement (“EULA”) located at [https://www.analogue.link/pocket-eula] +// and incorporated herein by reference. To the extent any use of the APF requires +// application of the MIT License or the GNU General Public License and terms of +// this APF Software License Agreement and EULA are inconsistent with such license, +// the applicable terms of the MIT License or the GNU General Public License, as +// applicable, will prevail. + +// THE SOFTWARE IS PROVIDED "AS-IS" AND WE EXPRESSLY DISCLAIM ANY IMPLIED +// WARRANTIES TO THE FULLEST EXTENT PROVIDED BY LAW, INCLUDING BUT NOT LIMITED TO, +// ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE OR +// NON-INFRINGEMENT. TO THE EXTENT APPLICABLE LAWS PROHIBIT TERMS OF USE FROM +// DISCLAIMING ANY IMPLIED WARRANTY, SUCH IMPLIED WARRANTY SHALL BE LIMITED TO THE +// MINIMUM WARRANTY PERIOD REQUIRED BY LAW, AND IF NO SUCH PERIOD IS REQUIRED, +// THEN THIRTY (30) DAYS FROM FIRST USE OF THE SOFTWARE. WE CANNOT GUARANTEE AND +// DO NOT PROMISE ANY SPECIFIC RESULTS FROM USE OF THE SOFTWARE. WITHOUT LIMITING +// THE FOREGOING, WE DO NOT WARRANT THAT THE SOFTWARE WILL BE UNINTERRUPTED OR +// ERROR-FREE. IN NO EVENT WILL WE BE LIABLE TO YOU OR ANY OTHER PERSON FOR ANY +// INDIRECT, CONSEQUENTIAL, EXEMPLARY, INCIDENTAL, SPECIAL OR PUNITIVE DAMAGES, +// INCLUDING BUT NOT LIMITED TO, LOST PROFITS ARISING OUT OF YOUR USE, OR +// INABILITY TO USE, THE SOFTWARE, EVEN IF WE HAVE BEEN ADVISED OF THE POSSIBILITY +// OF SUCH DAMAGES. UNDER NO CIRCUMSTANCES SHALL OUR LIABILITY TO YOU FOR ANY +// CLAIM OR CAUSE OF ACTION WHATSOEVER, AND REGARDLESS OF THE FORM OF THE ACTION, +// WHETHER ARISING IN CONTRACT, TORT OR OTHERWISE, EXCEED THE AMOUNT PAID BY YOU +// TO US, IF ANY, DURING THE 90 DAY PERIOD IMMEDIATELY PRECEDING THE DATE ON WHICH +// YOU FIRST ASSERT ANY SUCH CLAIM. THE FOREGOING LIMITATIONS SHALL APPLY TO THE +// FULLEST EXTENT PERMITTED BY APPLICABLE LAW. +// +// pad controller +// 2020-08-17 Analogue +// + +module io_pad_controller ( + +input wire clk, +input wire reset_n, + +inout reg pad_1wire, + +output reg [15:0] cont1_key, +output reg [15:0] cont2_key, +output reg [15:0] cont3_key, +output reg [15:0] cont4_key, +output reg [31:0] cont1_joy, +output reg [31:0] cont2_joy, +output reg [31:0] cont3_joy, +output reg [31:0] cont4_joy, +output reg [15:0] cont1_trig, +output reg [15:0] cont2_trig, +output reg [15:0] cont3_trig, +output reg [15:0] cont4_trig, + +output reg rx_timed_out +); + + wire reset_n_s; +synch_3 s00(reset_n, reset_n_s, clk); + + wire pad_1wire_s, pad_1wire_r, pad_1wire_f; +synch_3 s01(pad_1wire, pad_1wire_s, clk, pad_1wire_r, pad_1wire_f); + + +// +// protocol fsm +// + + reg [20:0] rx_timeout; // ~28ms + + reg [15:0] auto_poll_cnt; // 882us + reg auto_poll_queue; + + reg [18:0] heartbeat_cnt; // 7ms + reg heartbeat_queue; + + + localparam ST_RESET = 'd0; + localparam ST_IDLE = 'd1; + localparam ST_RX_BUTTON_1 = 'd2; + localparam ST_RX_BUTTON_2 = 'd3; + localparam ST_TX_SCALER = 'd4; + localparam ST_END_TX = 'd5; + + reg [3:0] state; + reg [3:0] cnt; + +always @(posedge clk) begin + tx_word_start <= 0; + + auto_poll_cnt <= auto_poll_cnt + 1'b1; + heartbeat_cnt <= heartbeat_cnt + 1'b1; + + // increment rx timeout, override and reset when idle below + rx_timeout <= rx_timeout + 1'b1; + + case(state) + ST_RESET: begin + reset_tr_n <= 0; + rx_timed_out <= 0; + + if(&rx_timeout[19:0]) begin + state <= ST_IDLE; + end + end + ST_IDLE: begin + // idle state + reset_tr_n <= 1; + rx_timeout <= 0; + cnt <= 0; + if(auto_poll_queue) begin + auto_poll_queue <= 0; + + tx_word_start <= 1; + tx_word <= 32'h4A10000C; + + state <= ST_RX_BUTTON_1; + end else if(heartbeat_queue) begin + heartbeat_queue <= 0; + + tx_word_start <= 1; + tx_word <= 32'h4AFE0000; + + state <= ST_END_TX; + end + end + // receive button words + ST_RX_BUTTON_1: begin + if(tx_word_done) begin + state <= ST_RX_BUTTON_2; + end + end + ST_RX_BUTTON_2: begin + if(rx_word_done) begin + cnt <= cnt + 1'b1; + case(cnt) + 0: cont1_key <= rx_word[15:0]; + 1: cont1_joy <= rx_word; + 2: cont1_trig <= rx_word[15:0]; + + 3: cont2_key <= rx_word[15:0]; + 4: cont2_joy <= rx_word; + 5: cont2_trig <= rx_word[15:0]; + + 6: cont3_key <= rx_word[15:0]; + 7: cont3_joy <= rx_word; + 8: cont3_trig <= rx_word[15:0]; + + 9: cont4_key <= rx_word[15:0]; + 10: cont4_joy <= rx_word; + 11: begin + cont4_trig <= rx_word[15:0]; + state <= ST_IDLE; + end + endcase + end + end + // do nothing + ST_END_TX: begin + // done sending, idle again + if(tx_word_done) begin + state <= ST_IDLE; + end + end + endcase + + + if(&auto_poll_cnt) begin + auto_poll_queue <= 1; + end + if(&heartbeat_cnt) begin + heartbeat_queue <= 1; + end + + if(&rx_timeout) begin + // reset protocol FSM which will also reset t/r engine + rx_timed_out <= 1; + rx_timeout <= 0; + state <= ST_RESET; + end + + if(~reset_n_s) begin + state <= ST_RESET; + end +end + + + + + +// +// word receive/transmit engine +// + reg reset_tr_n; + localparam BITLEN = 60; + + reg rx_word_done; + reg [31:0] rx_word_shift; + reg [31:0] rx_word; + + reg tx_word_start, tx_word_start_1; + reg tx_word_done; + reg [31:0] tx_word; + reg [31:0] tx_word_shift; + + reg [7:0] tr_cnt; + reg [5:0] tr_bit; + + localparam TR_IDLE = 'd1; + localparam TR_TX_START = 'd2; + localparam TR_TX_CONTINUE = 'd3; + localparam TR_TX_DONE = 'd4; + localparam TR_RX_START = 'd5; + localparam TR_RX_WAITEDGE = 'd6; + localparam TR_RX_DONE = 'd7; + + reg [3:0] tr_state; + +always @(posedge clk) begin + + rx_word_done <= 0; + tx_word_done <= 0; + + tx_word_start_1 <= tx_word_start; + + case(tr_state) + TR_IDLE: begin + tr_bit <= 0; + tr_cnt <= 0; + + pad_1wire <= 1'bZ; + + if(tx_word_start & ~tx_word_start_1) begin + // transmit word + tx_word_shift <= tx_word; + tr_state <= TR_TX_START; + end + + if(pad_1wire_f) begin + // receive word + tr_state <= TR_RX_START; + end + end + + // transmit 32bit + TR_TX_START: begin + // insert delay + tr_cnt <= tr_cnt + 1'b1; + if(&tr_cnt) begin + // drive from tristate(high) to explicitly high to prevent glitching + pad_1wire <= 1'b1; + tr_state <= TR_TX_CONTINUE; + end + end + TR_TX_CONTINUE: begin + tr_cnt <= tr_cnt + 1'b1; + case(tr_cnt) + 0: begin + pad_1wire <= 1'b0; + end + (BITLEN/3): begin + pad_1wire <= tx_word_shift[31]; + end + (BITLEN*2/3): begin + pad_1wire <= 1'b1; + end + (BITLEN-1): begin + tr_cnt <= 0; + tx_word_shift <= {tx_word_shift[30:0], 1'b1}; + + tr_bit <= tr_bit + 1'b1; + if(tr_bit == 31) begin + tr_state <= TR_TX_DONE; + end + end + endcase + end + TR_TX_DONE: begin + tx_word_done <= 1; + tr_state <= TR_IDLE; + end + + // receive 32bit + TR_RX_START: begin + tr_cnt <= tr_cnt + 1'b1; + case(tr_cnt) + (BITLEN/2-4): begin + rx_word_shift <= {rx_word_shift[30:0], pad_1wire_s}; + end + (BITLEN*5/6): begin + tr_cnt <= 0; + + // wait for next falling edge + tr_state <= TR_RX_WAITEDGE; + tr_bit <= tr_bit + 1'b1; + if(tr_bit == 31) begin + // if this is bit32, don't wait and finish + tr_state <= TR_RX_DONE; + end + end + endcase + end + TR_RX_WAITEDGE: begin + if(pad_1wire_f) begin + tr_state <= TR_RX_START; + end + end + TR_RX_DONE: begin + rx_word <= rx_word_shift; + rx_word_done <= 1; + tr_state <= TR_IDLE; + end + + default: begin + tr_state <= TR_IDLE; + end + endcase + + if(~reset_n_s | ~reset_tr_n) tr_state <= TR_IDLE; +end + +endmodule diff --git a/src/fpga/apf/mf_datatable.qip b/src/fpga/apf/mf_datatable.qip new file mode 100644 index 0000000..e7e597d --- /dev/null +++ b/src/fpga/apf/mf_datatable.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" +set_global_assignment -name IP_TOOL_VERSION "21.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "mf_datatable.v"] diff --git a/src/fpga/apf/mf_datatable.v b/src/fpga/apf/mf_datatable.v new file mode 100644 index 0000000..dfdbe86 --- /dev/null +++ b/src/fpga/apf/mf_datatable.v @@ -0,0 +1,247 @@ +// megafunction wizard: %RAM: 2-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: mf_datatable.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 21.1.1 Build 850 06/23/2022 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2022 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details, at +//https://fpgasoftware.intel.com/eula. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module mf_datatable ( + address_a, + address_b, + clock_a, + clock_b, + data_a, + data_b, + wren_a, + wren_b, + q_a, + q_b); + + input [7:0] address_a; + input [7:0] address_b; + input clock_a; + input clock_b; + input [31:0] data_a; + input [31:0] data_b; + input wren_a; + input wren_b; + output [31:0] q_a; + output [31:0] q_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock_a; + tri0 wren_a; + tri0 wren_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [31:0] sub_wire0; + wire [31:0] sub_wire1; + wire [31:0] q_a = sub_wire0[31:0]; + wire [31:0] q_b = sub_wire1[31:0]; + + altsyncram altsyncram_component ( + .address_a (address_a), + .address_b (address_b), + .clock0 (clock_a), + .clock1 (clock_b), + .data_a (data_a), + .data_b (data_b), + .wren_a (wren_a), + .wren_b (wren_b), + .q_a (sub_wire0), + .q_b (sub_wire1), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .eccstatus (), + .rden_a (1'b1), + .rden_b (1'b1)); + defparam + altsyncram_component.address_reg_b = "CLOCK1", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.indata_reg_b = "CLOCK1", + altsyncram_component.init_file = "./apf/build_id.mif", + altsyncram_component.intended_device_family = "Cyclone V", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 256, + altsyncram_component.numwords_b = 256, + altsyncram_component.operation_mode = "BIDIR_DUAL_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_a = "CLOCK0", + altsyncram_component.outdata_reg_b = "CLOCK1", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 8, + altsyncram_component.widthad_b = 8, + altsyncram_component.width_a = 32, + altsyncram_component.width_b = 32, + altsyncram_component.width_byteena_a = 1, + altsyncram_component.width_byteena_b = 1, + altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLRdata NUMERIC "0" +// Retrieval info: PRIVATE: CLRq NUMERIC "0" +// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRrren NUMERIC "0" +// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRwren NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "5" +// Retrieval info: PRIVATE: Clock_A NUMERIC "0" +// Retrieval info: PRIVATE: Clock_B NUMERIC "0" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192" +// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "./apf/build_id.mif" +// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" +// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" +// Retrieval info: PRIVATE: REGdata NUMERIC "1" +// Retrieval info: PRIVATE: REGq NUMERIC "1" +// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: REGrren NUMERIC "0" +// Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +// Retrieval info: PRIVATE: REGwren NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +// Retrieval info: PRIVATE: VarWidth NUMERIC "0" +// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32" +// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32" +// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32" +// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32" +// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: enable NUMERIC "0" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1" +// Retrieval info: CONSTANT: INIT_FILE STRING "./apf/build_id.mif" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" +// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32" +// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" +// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1" +// Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL "address_a[7..0]" +// Retrieval info: USED_PORT: address_b 0 0 8 0 INPUT NODEFVAL "address_b[7..0]" +// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a" +// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b" +// Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL "data_a[31..0]" +// Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL "data_b[31..0]" +// Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]" +// Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]" +// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a" +// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b" +// Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0 +// Retrieval info: CONNECT: @address_b 0 0 8 0 address_b 0 0 8 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0 +// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0 +// Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 +// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 +// Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0 +// Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_datatable.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_datatable.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_datatable.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_datatable.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_datatable_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_datatable_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf diff --git a/src/fpga/apf/mf_ddio_bidir_12.ppf b/src/fpga/apf/mf_ddio_bidir_12.ppf new file mode 100644 index 0000000..1dac726 --- /dev/null +++ b/src/fpga/apf/mf_ddio_bidir_12.ppf @@ -0,0 +1,15 @@ + + + + + + + + + + + + + + + diff --git a/src/fpga/apf/mf_ddio_bidir_12.qip b/src/fpga/apf/mf_ddio_bidir_12.qip new file mode 100644 index 0000000..86120bf --- /dev/null +++ b/src/fpga/apf/mf_ddio_bidir_12.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "ALTDDIO_BIDIR" +set_global_assignment -name IP_TOOL_VERSION "21.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "mf_ddio_bidir_12.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mf_ddio_bidir_12.ppf"] diff --git a/src/fpga/apf/mf_ddio_bidir_12.v b/src/fpga/apf/mf_ddio_bidir_12.v new file mode 100644 index 0000000..3b00634 --- /dev/null +++ b/src/fpga/apf/mf_ddio_bidir_12.v @@ -0,0 +1,133 @@ +// megafunction wizard: %ALTDDIO_BIDIR% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTDDIO_BIDIR + +// ============================================================ +// File Name: mf_ddio_bidir_12.v +// Megafunction Name(s): +// ALTDDIO_BIDIR +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 21.1.1 Build 850 06/23/2022 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2022 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details, at +//https://fpgasoftware.intel.com/eula. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module mf_ddio_bidir_12 ( + datain_h, + datain_l, + inclock, + oe, + outclock, + dataout_h, + dataout_l, + padio); + + input [11:0] datain_h; + input [11:0] datain_l; + input inclock; + input oe; + input outclock; + output [11:0] dataout_h; + output [11:0] dataout_l; + inout [11:0] padio; + + wire [11:0] sub_wire0; + wire [11:0] sub_wire1; + wire [11:0] dataout_h = sub_wire0[11:0]; + wire [11:0] dataout_l = sub_wire1[11:0]; + + altddio_bidir ALTDDIO_BIDIR_component ( + .datain_h (datain_h), + .datain_l (datain_l), + .inclock (inclock), + .oe (oe), + .outclock (outclock), + .padio (padio), + .dataout_h (sub_wire0), + .dataout_l (sub_wire1), + .aclr (1'b0), + .aset (1'b0), + .combout (), + .dqsundelayedout (), + .inclocken (1'b1), + .oe_out (), + .outclocken (1'b1), + .sclr (1'b0), + .sset (1'b0)); + defparam + ALTDDIO_BIDIR_component.extend_oe_disable = "OFF", + ALTDDIO_BIDIR_component.implement_input_in_lcell = "OFF", + ALTDDIO_BIDIR_component.intended_device_family = "Cyclone V", + ALTDDIO_BIDIR_component.invert_output = "OFF", + ALTDDIO_BIDIR_component.lpm_hint = "UNUSED", + ALTDDIO_BIDIR_component.lpm_type = "altddio_bidir", + ALTDDIO_BIDIR_component.oe_reg = "UNREGISTERED", + ALTDDIO_BIDIR_component.power_up_high = "OFF", + ALTDDIO_BIDIR_component.width = 12; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF" +// Retrieval info: CONSTANT: IMPLEMENT_INPUT_IN_LCELL STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_bidir" +// Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +// Retrieval info: CONSTANT: WIDTH NUMERIC "12" +// Retrieval info: USED_PORT: datain_h 0 0 12 0 INPUT NODEFVAL "datain_h[11..0]" +// Retrieval info: CONNECT: @datain_h 0 0 12 0 datain_h 0 0 12 0 +// Retrieval info: USED_PORT: datain_l 0 0 12 0 INPUT NODEFVAL "datain_l[11..0]" +// Retrieval info: CONNECT: @datain_l 0 0 12 0 datain_l 0 0 12 0 +// Retrieval info: USED_PORT: dataout_h 0 0 12 0 OUTPUT NODEFVAL "dataout_h[11..0]" +// Retrieval info: CONNECT: dataout_h 0 0 12 0 @dataout_h 0 0 12 0 +// Retrieval info: USED_PORT: dataout_l 0 0 12 0 OUTPUT NODEFVAL "dataout_l[11..0]" +// Retrieval info: CONNECT: dataout_l 0 0 12 0 @dataout_l 0 0 12 0 +// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "inclock" +// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0 +// Retrieval info: USED_PORT: oe 0 0 0 0 INPUT NODEFVAL "oe" +// Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0 +// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock" +// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +// Retrieval info: USED_PORT: padio 0 0 12 0 BIDIR NODEFVAL "padio[11..0]" +// Retrieval info: CONNECT: padio 0 0 12 0 @padio 0 0 12 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.qip TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.bsf FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12_inst.v FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12_bb.v FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.inc FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.cmp FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.ppf TRUE FALSE diff --git a/src/fpga/core/core_bridge_cmd.v b/src/fpga/core/core_bridge_cmd.v new file mode 100644 index 0000000..1039089 --- /dev/null +++ b/src/fpga/core/core_bridge_cmd.v @@ -0,0 +1,445 @@ +// +// bridge host/target command handler +// 2022 Analogue +// + +// mapped to 0xF8xxxxxx on bridge +// the spec is loose enough to allow implementation with either +// block rams and a soft CPU, or simply hard logic with some case statements. +// +// the implementation spec is documented, and depending on your application you +// may want to completely replace this module. this is only one of many +// possible ways to accomplish the host/target command system and data table. +// +// this module should always be clocked by a direct clock input and never a PLL, +// because it should report PLL lock status +// + +module core_bridge_cmd ( + +input wire clk, +output reg reset_n, + +input wire bridge_endian_little, +input wire [31:0] bridge_addr, +input wire bridge_rd, +output reg [31:0] bridge_rd_data, +input wire bridge_wr, +input wire [31:0] bridge_wr_data, + +// all these signals should be synchronous to clk +// add synchronizers if these need to be used in other clock domains +input wire status_boot_done, // assert when PLLs lock and logic is ready +input wire status_setup_done, // assert when core is happy with what's been loaded into it +input wire status_running, // assert when pocket's taken core out of reset and is running + +output reg dataslot_requestread, +output reg [15:0] dataslot_requestread_id, +input wire dataslot_requestread_ack, +input wire dataslot_requestread_ok, + +output reg dataslot_requestwrite, +output reg [15:0] dataslot_requestwrite_id, +input wire dataslot_requestwrite_ack, +input wire dataslot_requestwrite_ok, + +output reg dataslot_allcomplete, + +input wire savestate_supported, +input wire [31:0] savestate_addr, +input wire [31:0] savestate_size, +input wire [31:0] savestate_maxloadsize, + +output reg osnotify_inmenu, + +output reg savestate_start, // core should detect rising edge on this, +input wire savestate_start_ack, // and then assert ack for at least 1 cycle +input wire savestate_start_busy, // assert constantly while in progress after ack +input wire savestate_start_ok, // assert continuously when done, and clear when new process is started +input wire savestate_start_err, // assert continuously on error, and clear when new process is started + +output reg savestate_load, +input wire savestate_load_ack, +input wire savestate_load_busy, +input wire savestate_load_ok, +input wire savestate_load_err, + +input wire [9:0] datatable_addr, +input wire datatable_wren, +input wire [31:0] datatable_data, +output wire [31:0] datatable_q + +); + +// handle endianness + reg [31:0] bridge_wr_data_in; + reg [31:0] bridge_rd_data_out; + + wire endian_little_s; +synch_3 s01(bridge_endian_little, endian_little_s, clk); + +always @(*) begin + bridge_rd_data <= endian_little_s ? { + bridge_rd_data_out[7:0], + bridge_rd_data_out[15:8], + bridge_rd_data_out[23:16], + bridge_rd_data_out[31:24] + } : bridge_rd_data_out; + + bridge_wr_data_in <= endian_little_s ? { + bridge_wr_data[7:0], + bridge_wr_data[15:8], + bridge_wr_data[23:16], + bridge_wr_data[31:24] + } : bridge_wr_data; +end + + +// minimalistic approach here - +// keep the commonly used registers in logic, but data table in BRAM. +// implementation could be changed quite a bit for a more advanced use case + +// host + + reg [31:0] host_0; + reg [31:0] host_4 = 'h20; // host cmd parameter data at 0x20 + reg [31:0] host_8 = 'h40; // host cmd response data at 0x40 + + reg [31:0] host_20; // parameter data + reg [31:0] host_24; + reg [31:0] host_28; + reg [31:0] host_2C; + + reg [31:0] host_40; // response data + reg [31:0] host_44; + reg [31:0] host_48; + reg [31:0] host_4C; + + reg host_cmd_start; + reg [15:0] host_cmd_startval; + reg [15:0] host_cmd; + reg [15:0] host_resultcode; + +localparam [3:0] ST_IDLE = 'd0; +localparam [3:0] ST_PARSE = 'd1; +localparam [3:0] ST_WORK = 'd2; +localparam [3:0] ST_DONE_OK = 'd13; +localparam [3:0] ST_DONE_CODE = 'd14; +localparam [3:0] ST_DONE_ERR = 'd15; + reg [3:0] hstate; + +// target + + reg [31:0] target_0; + reg [31:0] target_4 = 'h20; + reg [31:0] target_8 = 'h40; + + reg [31:0] target_20; // parameter data + reg [31:0] target_24; + reg [31:0] target_28; + reg [31:0] target_2C; + + reg [31:0] target_40; // response data + reg [31:0] target_44; + reg [31:0] target_48; + reg [31:0] target_4C; + +localparam [3:0] TARG_ST_IDLE = 'd0; +localparam [3:0] TARG_ST_READYTORUN = 'd1; +localparam [3:0] TARG_ST_DISPMSG = 'd2; +localparam [3:0] TARG_ST_SLOTREAD = 'd3; +localparam [3:0] TARG_ST_SLOTRELOAD = 'd4; +localparam [3:0] TARG_ST_SLOTWRITE = 'd5; +localparam [3:0] TARG_ST_SLOTFLUSH = 'd6; +localparam [3:0] TARG_ST_WAITRESULT = 'd15; + reg [3:0] tstate; + + reg status_setup_done_1; + reg status_setup_done_queue; + + +initial begin + reset_n <= 0; + dataslot_requestread <= 0; + dataslot_requestwrite <= 0; + dataslot_allcomplete <= 0; + savestate_start <= 0; + savestate_load <= 0; + osnotify_inmenu <= 0; + status_setup_done_queue <= 0; +end + +always @(posedge clk) begin + + // detect a rising edge on the input signal + // and flag a queue that will be cleared later + status_setup_done_1 <= status_setup_done; + if(status_setup_done & ~status_setup_done_1) begin + status_setup_done_queue <= 1; + end + + b_datatable_wren <= 0; + b_datatable_addr <= bridge_addr >> 2; + + if(bridge_wr) begin + casex(bridge_addr) + 32'hF8xx00xx: begin + case(bridge_addr[7:0]) + 8'h0: begin + host_0 <= bridge_wr_data_in; // command/status + // check for command + if(bridge_wr_data_in[31:16] == 16'h434D) begin + // host wants us to do a command + host_cmd_startval <= bridge_wr_data_in[15:0]; + host_cmd_start <= 1; + end + end + 8'h20: host_20 <= bridge_wr_data_in; // parameter data regs + 8'h24: host_24 <= bridge_wr_data_in; + 8'h28: host_28 <= bridge_wr_data_in; + 8'h2C: host_2C <= bridge_wr_data_in; + endcase + end + 32'hF8xx10xx: begin + case(bridge_addr[7:0]) + 8'h0: target_0 <= bridge_wr_data_in; // command/status + 8'h4: target_4 <= bridge_wr_data_in; // parameter data pointer + 8'h8: target_8 <= bridge_wr_data_in; // response data pointer + 8'h40: target_40 <= bridge_wr_data_in; // response data regs + 8'h44: target_44 <= bridge_wr_data_in; + 8'h48: target_48 <= bridge_wr_data_in; + 8'h4C: target_4C <= bridge_wr_data_in; + endcase + end + 32'hF8xx2xxx: begin + b_datatable_wren <= 1; + end + endcase + end + if(bridge_rd) begin + casex(bridge_addr) + 32'hF8xx00xx: begin + case(bridge_addr[7:0]) + 8'h0: bridge_rd_data_out <= host_0; // command/status + 8'h4: bridge_rd_data_out <= host_4; // parameter data pointer + 8'h8: bridge_rd_data_out <= host_8; // response data pointer + 8'h40: bridge_rd_data_out <= host_40; // response data regs + 8'h44: bridge_rd_data_out <= host_44; + 8'h48: bridge_rd_data_out <= host_48; + 8'h4C: bridge_rd_data_out <= host_4C; + endcase + end + 32'hF8xx10xx: begin + case(bridge_addr[7:0]) + 8'h0: bridge_rd_data_out <= target_0; + 8'h4: bridge_rd_data_out <= target_4; + 8'h8: bridge_rd_data_out <= target_8; + 8'h20: bridge_rd_data_out <= target_20; // parameter data regs + 8'h24: bridge_rd_data_out <= target_24; + 8'h28: bridge_rd_data_out <= target_28; + 8'h2C: bridge_rd_data_out <= target_2C; + endcase + end + 32'hF8xx2xxx: begin + bridge_rd_data_out <= b_datatable_q; + + end + endcase + end + + + + + + // host > target command executer + case(hstate) + ST_IDLE: begin + + dataslot_requestread <= 0; + dataslot_requestwrite <= 0; + savestate_start <= 0; + savestate_load <= 0; + + // there is no queueing. pocket will always make sure any outstanding host + // commands are finished before starting another + if(host_cmd_start) begin + host_cmd_start <= 0; + // save the command in case it gets clobbered later + host_cmd <= host_cmd_startval; + hstate <= ST_PARSE; + end + + end + ST_PARSE: begin + // overwrite command semaphore with busy flag + host_0 <= {16'h4255, host_cmd}; + + case(host_cmd) + 16'h0000: begin + // Request Status + host_resultcode <= 1; // default: booting + if(status_boot_done) begin + host_resultcode <= 2; // setup + if(status_setup_done) begin + host_resultcode <= 3; // idle + end else if(status_running) begin + host_resultcode <= 4; // running + end + end + hstate <= ST_DONE_CODE; + end + 16'h0010: begin + // Reset Enter + reset_n <= 0; + hstate <= ST_DONE_OK; + end + 16'h0011: begin + // Reset Exit + reset_n <= 1; + hstate <= ST_DONE_OK; + end + 16'h0080: begin + // Data slot request read + dataslot_allcomplete <= 0; + dataslot_requestread <= 1; + dataslot_requestread_id <= host_20[15:0]; + if(dataslot_requestread_ack) begin + host_resultcode <= 0; + if(!dataslot_requestread_ok) host_resultcode <= 2; + hstate <= ST_DONE_CODE; + end + end + 16'h0082: begin + // Data slot request write + dataslot_allcomplete <= 0; + dataslot_requestwrite <= 1; + dataslot_requestwrite_id <= host_20[15:0]; + if(dataslot_requestwrite_ack) begin + host_resultcode <= 0; + if(!dataslot_requestwrite_ok) host_resultcode <= 2; + hstate <= ST_DONE_CODE; + end + end + 16'h008F: begin + // Data slot access all complete + dataslot_allcomplete <= 1; + hstate <= ST_DONE_OK; + end + 16'h00A0: begin + // Savestate: Start/Query + host_40 <= savestate_supported; + host_44 <= savestate_addr; + host_48 <= savestate_size; + + host_resultcode <= 0; + if(savestate_start_busy) host_resultcode <= 1; + if(savestate_start_ok) host_resultcode <= 2; + if(savestate_start_err) host_resultcode <= 3; + + if(host_20[0]) begin + // Request Start! + savestate_start <= 1; + // stay in this state until ack'd + if(savestate_start_ack) begin + hstate <= ST_DONE_CODE; + end + end else begin + hstate <= ST_DONE_CODE; + end + end + 16'h00A4: begin + // Savestate: Load/Query + host_40 <= savestate_supported; + host_44 <= savestate_addr; + host_48 <= savestate_maxloadsize; + + host_resultcode <= 0; + if(savestate_load_busy) host_resultcode <= 1; + if(savestate_load_ok) host_resultcode <= 2; + if(savestate_load_err) host_resultcode <= 3; + + if(host_20[0]) begin + // Request Load! + savestate_load <= 1; + // stay in this state until ack'd + if(savestate_load_ack) begin + hstate <= ST_DONE_CODE; + end + end else begin + hstate <= ST_DONE_CODE; + end + end + 16'h00B0: begin + // OS Notify: Menu State + osnotify_inmenu <= host_20[0]; + hstate <= ST_DONE_OK; + end + default: begin + hstate <= ST_DONE_ERR; + end + endcase + end + ST_WORK: begin + hstate <= ST_IDLE; + end + ST_DONE_OK: begin + host_0 <= 32'h4F4B0000; // result code 0 + hstate <= ST_IDLE; + end + ST_DONE_CODE: begin + host_0 <= {16'h4F4B, host_resultcode}; + hstate <= ST_IDLE; + end + ST_DONE_ERR: begin + host_0 <= 32'h4F4BFFFF; // result code FFFF = unknown command + hstate <= ST_IDLE; + end + endcase + + + + + // target > host command executer + case(tstate) + TARG_ST_IDLE: begin + if(status_setup_done_queue) begin + status_setup_done_queue <= 0; + tstate <= TARG_ST_READYTORUN; + end + + end + TARG_ST_READYTORUN: begin + target_0 <= 32'h636D_0140; + tstate <= TARG_ST_WAITRESULT; + end + TARG_ST_WAITRESULT: begin + if(target_0[31:16] == 16'h6F6B) begin + // done + tstate <= TARG_ST_IDLE; + end + + end + endcase + + +end + + wire [31:0] b_datatable_q; + reg [9:0] b_datatable_addr; + reg b_datatable_wren; + +mf_datatable idt ( + .address_a ( datatable_addr ), + .address_b ( b_datatable_addr ), + .clock_a ( clk ), + .clock_b ( clk ), + .data_a ( datatable_data ), + .data_b ( bridge_wr_data_in ), + .wren_a ( datatable_wren ), + .wren_b ( b_datatable_wren ), + .q_a ( datatable_q ), + .q_b ( b_datatable_q ) +); + + +endmodule diff --git a/src/fpga/core/core_constraints.sdc b/src/fpga/core/core_constraints.sdc new file mode 100644 index 0000000..733dd5c --- /dev/null +++ b/src/fpga/core/core_constraints.sdc @@ -0,0 +1,15 @@ +# +# user core constraints +# +# put your clock groups in here as well as any net assignments +# + +set_clock_groups -asynchronous \ + -group { bridge_spiclk } \ + -group { clk_74a } \ + -group { clk_74b } \ + -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk } \ + -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk } \ + -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk } \ + -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk } \ + -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk } \ No newline at end of file diff --git a/src/fpga/core/core_top.v b/src/fpga/core/core_top.v new file mode 100644 index 0000000..e294b50 --- /dev/null +++ b/src/fpga/core/core_top.v @@ -0,0 +1,733 @@ +// +// User core top-level +// +// Instantiated by the real top-level: apf_top +// + +`default_nettype none + +module core_top ( + +// +// physical connections +// + +/////////////////////////////////////////////////// +// clock inputs 74.25mhz. not phase aligned, so treat these domains as asynchronous + +input wire clk_74a, // mainclk1 +input wire clk_74b, // mainclk1 + +/////////////////////////////////////////////////// +// cartridge interface +// switches between 3.3v and 5v mechanically +// output enable for multibit translators controlled by pic32 + +// GBA AD[15:8] +inout wire [7:0] cart_tran_bank2, +output wire cart_tran_bank2_dir, + +// GBA AD[7:0] +inout wire [7:0] cart_tran_bank3, +output wire cart_tran_bank3_dir, + +// GBA A[23:16] +inout wire [7:0] cart_tran_bank1, +output wire cart_tran_bank1_dir, + +// GBA [7] PHI# +// GBA [6] WR# +// GBA [5] RD# +// GBA [4] CS1#/CS# +// [3:0] unwired +inout wire [7:4] cart_tran_bank0, +output wire cart_tran_bank0_dir, + +// GBA CS2#/RES# +inout wire cart_tran_pin30, +output wire cart_tran_pin30_dir, +// when GBC cart is inserted, this signal when low or weak will pull GBC /RES low with a special circuit +// the goal is that when unconfigured, the FPGA weak pullups won't interfere. +// thus, if GBC cart is inserted, FPGA must drive this high in order to let the level translators +// and general IO drive this pin. +output wire cart_pin30_pwroff_reset, + +// GBA IRQ/DRQ +inout wire cart_tran_pin31, +output wire cart_tran_pin31_dir, + +// infrared +input wire port_ir_rx, +output wire port_ir_tx, +output wire port_ir_rx_disable, + +// GBA link port +inout wire port_tran_si, +output wire port_tran_si_dir, +inout wire port_tran_so, +output wire port_tran_so_dir, +inout wire port_tran_sck, +output wire port_tran_sck_dir, +inout wire port_tran_sd, +output wire port_tran_sd_dir, + +/////////////////////////////////////////////////// +// cellular psram 0 and 1, two chips (64mbit x2 dual die per chip) + +output wire [21:16] cram0_a, +inout wire [15:0] cram0_dq, +input wire cram0_wait, +output wire cram0_clk, +output wire cram0_adv_n, +output wire cram0_cre, +output wire cram0_ce0_n, +output wire cram0_ce1_n, +output wire cram0_oe_n, +output wire cram0_we_n, +output wire cram0_ub_n, +output wire cram0_lb_n, + +output wire [21:16] cram1_a, +inout wire [15:0] cram1_dq, +input wire cram1_wait, +output wire cram1_clk, +output wire cram1_adv_n, +output wire cram1_cre, +output wire cram1_ce0_n, +output wire cram1_ce1_n, +output wire cram1_oe_n, +output wire cram1_we_n, +output wire cram1_ub_n, +output wire cram1_lb_n, + +/////////////////////////////////////////////////// +// sdram, 512mbit 16bit + +output wire [12:0] dram_a, +output wire [1:0] dram_ba, +inout wire [15:0] dram_dq, +output wire [1:0] dram_dqm, +output wire dram_clk, +output wire dram_cke, +output wire dram_ras_n, +output wire dram_cas_n, +output wire dram_we_n, + +/////////////////////////////////////////////////// +// sram, 1mbit 16bit + +output wire [16:0] sram_a, +inout wire [15:0] sram_dq, +output wire sram_oe_n, +output wire sram_we_n, +output wire sram_ub_n, +output wire sram_lb_n, + +/////////////////////////////////////////////////// +// vblank driven by dock for sync in a certain mode + +input wire vblank, + +/////////////////////////////////////////////////// +// i/o to 6515D breakout usb uart + +output wire dbg_tx, +input wire dbg_rx, + +/////////////////////////////////////////////////// +// i/o pads near jtag connector user can solder to + +output wire user1, +input wire user2, + +/////////////////////////////////////////////////// +// RFU internal i2c bus + +inout wire aux_sda, +output wire aux_scl, + +/////////////////////////////////////////////////// +// RFU, do not use +output wire vpll_feed, + + +// +// logical connections +// + +/////////////////////////////////////////////////// +// video, audio output to scaler +output wire [23:0] video_rgb, +output wire video_rgb_clock, +output wire video_rgb_clock_90, +output wire video_de, +output wire video_skip, +output wire video_vs, +output wire video_hs, + +output wire audio_mclk, +input wire audio_adc, +output wire audio_dac, +output wire audio_lrck, + +/////////////////////////////////////////////////// +// bridge bus connection +// synchronous to clk_74a +output wire bridge_endian_little, +input wire [31:0] bridge_addr, +input wire bridge_rd, +output reg [31:0] bridge_rd_data, +input wire bridge_wr, +input wire [31:0] bridge_wr_data, + +/////////////////////////////////////////////////// +// controller data +// +// key bitmap: +// [0] dpad_up +// [1] dpad_down +// [2] dpad_left +// [3] dpad_right +// [4] face_a +// [5] face_b +// [6] face_x +// [7] face_y +// [8] trig_l1 +// [9] trig_r1 +// [10] trig_l2 +// [11] trig_r2 +// [12] trig_l3 +// [13] trig_r3 +// [14] face_select +// [15] face_start +// joy values - unsigned +// [ 7: 0] lstick_x +// [15: 8] lstick_y +// [23:16] rstick_x +// [31:24] rstick_y +// trigger values - unsigned +// [ 7: 0] ltrig +// [15: 8] rtrig +// +input wire [15:0] cont1_key, +input wire [15:0] cont2_key, +input wire [15:0] cont3_key, +input wire [15:0] cont4_key, +input wire [31:0] cont1_joy, +input wire [31:0] cont2_joy, +input wire [31:0] cont3_joy, +input wire [31:0] cont4_joy, +input wire [15:0] cont1_trig, +input wire [15:0] cont2_trig, +input wire [15:0] cont3_trig, +input wire [15:0] cont4_trig + +); + +// not using the IR port, so turn off both the LED, and +// disable the receive circuit to save power +assign port_ir_tx = 0; +assign port_ir_rx_disable = 1; + +// bridge endianness +assign bridge_endian_little = 0; + +// cart is unused, so set all level translators accordingly +// directions are 0:IN, 1:OUT +assign cart_tran_bank3 = 8'hzz; +assign cart_tran_bank3_dir = 1'b0; +assign cart_tran_bank2 = 8'hzz; +assign cart_tran_bank2_dir = 1'b0; +assign cart_tran_bank1 = 8'hzz; +assign cart_tran_bank1_dir = 1'b0; +assign cart_tran_bank0 = 4'hf; +assign cart_tran_bank0_dir = 1'b1; +assign cart_tran_pin30 = 1'b0; // reset or cs2, we let the hw control it by itself +assign cart_tran_pin30_dir = 1'bz; +assign cart_pin30_pwroff_reset = 1'b0; // hardware can control this +assign cart_tran_pin31 = 1'bz; // input +assign cart_tran_pin31_dir = 1'b0; // input + +// link port is input only +assign port_tran_so = 1'bz; +assign port_tran_so_dir = 1'b0; // SO is output only +assign port_tran_si = 1'bz; +assign port_tran_si_dir = 1'b0; // SI is input only +assign port_tran_sck = 1'bz; +assign port_tran_sck_dir = 1'b0; // clock direction can change +assign port_tran_sd = 1'bz; +assign port_tran_sd_dir = 1'b0; // SD is input and not used + +// tie off the rest of the pins we are not using +assign cram0_a = 'h0; +assign cram0_dq = {16{1'bZ}}; +assign cram0_clk = 0; +assign cram0_adv_n = 1; +assign cram0_cre = 0; +assign cram0_ce0_n = 1; +assign cram0_ce1_n = 1; +assign cram0_oe_n = 1; +assign cram0_we_n = 1; +assign cram0_ub_n = 1; +assign cram0_lb_n = 1; + +assign cram1_a = 'h0; +assign cram1_dq = {16{1'bZ}}; +assign cram1_clk = 0; +assign cram1_adv_n = 1; +assign cram1_cre = 0; +assign cram1_ce0_n = 1; +assign cram1_ce1_n = 1; +assign cram1_oe_n = 1; +assign cram1_we_n = 1; +assign cram1_ub_n = 1; +assign cram1_lb_n = 1; + +assign dram_a = 'h0; +assign dram_ba = 'h0; +assign dram_dq = {16{1'bZ}}; +assign dram_dqm = 'h0; +assign dram_clk = 'h0; +assign dram_cke = 'h0; +assign dram_ras_n = 'h1; +assign dram_cas_n = 'h1; +assign dram_we_n = 'h1; + +assign sram_a = 'h0; +assign sram_dq = {16{1'bZ}}; +assign sram_oe_n = 1; +assign sram_we_n = 1; +assign sram_ub_n = 1; +assign sram_lb_n = 1; + +assign dbg_tx = 1'bZ; +assign user1 = 1'bZ; +assign aux_scl = 1'bZ; +assign vpll_feed = 1'bZ; + + +// for bridge write data, we just broadcast it to all bus devices +// for bridge read data, we have to mux it +// add your own devices here +always @(*) begin + casex(bridge_addr) + default: begin + bridge_rd_data <= 0; + end + 32'h10xxxxxx: begin + // example + // bridge_rd_data <= example_device_data; + bridge_rd_data <= 0; + end + 32'hF8xxxxxx: begin + bridge_rd_data <= cmd_bridge_rd_data; + end + endcase +end + + +// +// host/target command handler +// + wire reset_n; // driven by host commands, can be used as core-wide reset + wire [31:0] cmd_bridge_rd_data; + +// bridge host commands +// synchronous to clk_74a + wire status_boot_done = pll_core_locked; + wire status_setup_done = pll_core_locked; // rising edge triggers a target command + wire status_running = reset_n; // we are running as soon as reset_n goes high + + wire dataslot_requestread; + wire [15:0] dataslot_requestread_id; + wire dataslot_requestread_ack = 1; + wire dataslot_requestread_ok = 1; + + wire dataslot_requestwrite; + wire [15:0] dataslot_requestwrite_id; + wire dataslot_requestwrite_ack = 1; + wire dataslot_requestwrite_ok = 1; + + wire dataslot_allcomplete; + + wire savestate_supported; + wire [31:0] savestate_addr; + wire [31:0] savestate_size; + wire [31:0] savestate_maxloadsize; + + wire savestate_start; + wire savestate_start_ack; + wire savestate_start_busy; + wire savestate_start_ok; + wire savestate_start_err; + + wire savestate_load; + wire savestate_load_ack; + wire savestate_load_busy; + wire savestate_load_ok; + wire savestate_load_err; + + wire osnotify_inmenu; + +// bridge target commands +// synchronous to clk_74a + + +// bridge data slot access + + wire [9:0] datatable_addr; + wire datatable_wren; + wire [31:0] datatable_data; + wire [31:0] datatable_q; + +core_bridge_cmd icb ( + + .clk ( clk_74a ), + .reset_n ( reset_n ), + + .bridge_endian_little ( bridge_endian_little ), + .bridge_addr ( bridge_addr ), + .bridge_rd ( bridge_rd ), + .bridge_rd_data ( cmd_bridge_rd_data ), + .bridge_wr ( bridge_wr ), + .bridge_wr_data ( bridge_wr_data ), + + .status_boot_done ( status_boot_done ), + .status_setup_done ( status_setup_done ), + .status_running ( status_running ), + + .dataslot_requestread ( dataslot_requestread ), + .dataslot_requestread_id ( dataslot_requestread_id ), + .dataslot_requestread_ack ( dataslot_requestread_ack ), + .dataslot_requestread_ok ( dataslot_requestread_ok ), + + .dataslot_requestwrite ( dataslot_requestwrite ), + .dataslot_requestwrite_id ( dataslot_requestwrite_id ), + .dataslot_requestwrite_ack ( dataslot_requestwrite_ack ), + .dataslot_requestwrite_ok ( dataslot_requestwrite_ok ), + + .dataslot_allcomplete ( dataslot_allcomplete ), + + .savestate_supported ( savestate_supported ), + .savestate_addr ( savestate_addr ), + .savestate_size ( savestate_size ), + .savestate_maxloadsize ( savestate_maxloadsize ), + + .savestate_start ( savestate_start ), + .savestate_start_ack ( savestate_start_ack ), + .savestate_start_busy ( savestate_start_busy ), + .savestate_start_ok ( savestate_start_ok ), + .savestate_start_err ( savestate_start_err ), + + .savestate_load ( savestate_load ), + .savestate_load_ack ( savestate_load_ack ), + .savestate_load_busy ( savestate_load_busy ), + .savestate_load_ok ( savestate_load_ok ), + .savestate_load_err ( savestate_load_err ), + + .osnotify_inmenu ( osnotify_inmenu ), + + .datatable_addr ( datatable_addr ), + .datatable_wren ( datatable_wren ), + .datatable_data ( datatable_data ), + .datatable_q ( datatable_q ), + +); + + + +//////////////////////////////////////////////////////////////////////////////////////// + + wire clk_core_12; + wire clk_core_12_90deg; + wire clk_50; + wire clk_25; + wire clk_25_90deg; + + wire pll_core_locked; + +mf_pllbase mp1 ( + .refclk ( clk_74a ), + .rst ( 0 ), + + .outclk_0 ( clk_core_12 ), + .outclk_1 ( clk_core_12_90deg ), + .outclk_2 ( clk_50 ), + .outclk_3 ( clk_25 ), + .outclk_4 ( clk_25_90deg ), + + .locked ( pll_core_locked ) +); + +/////////////////////////////////////// +// Core Data +/////////////////////////////////////// + +wire io_wr; +wire [24:0] io_addr; +wire [7:0] io_dout; + +data_loader #( + .ADDRESS_SIZE(16), + .WRITE_MEM_CLOCK_DELAY(4) +) rom_loader ( + .clk_74a(clk_74a), + .clk_memory(clk_sys), + + .bridge_wr(bridge_wr), + .bridge_endian_little(bridge_endian_little), + .bridge_addr(bridge_addr), + .bridge_wr_data(bridge_wr_data), + + .write_en(io_wr), + .write_addr(io_addr), + .write_data(io_dout) +); + +/////////////////////////////////////// +// Core Audio +/////////////////////////////////////// + +wire [6:0] audio; + +assign audio_mclk = audgen_mclk; +assign audio_dac = audgen_dac; +assign audio_lrck = audgen_lrck; + +reg audgen_nextsamp; + +// generate MCLK = 12.288mhz with fractional accumulator +reg [21:0] audgen_accum; +reg audgen_mclk; +parameter [20:0] CYCLE_48KHZ = 21'd122880 * 2; +always @(posedge clk_74a) begin + audgen_accum <= audgen_accum + CYCLE_48KHZ; + if(audgen_accum >= 21'd742500) begin + audgen_mclk <= ~audgen_mclk; + audgen_accum <= audgen_accum - 21'd742500 + CYCLE_48KHZ; + end +end + +// generate SCLK = 3.072mhz by dividing MCLK by 4 +reg [1:0] aud_mclk_divider; +wire audgen_sclk = aud_mclk_divider[1] /* synthesis keep*/; +always @(posedge audgen_mclk) begin + aud_mclk_divider <= aud_mclk_divider + 1'b1; +end + +// shift out audio data as I2S +// 32 total bits per channel, but only 16 active bits at the start and then 16 dummy bits +// +// synchronize audio samples coming from the core +wire [31:0] audgen_sampdata_s; +synch_3 #(.WIDTH(32)) s5(({audio, audio}), audgen_sampdata_s, audgen_sclk); +reg [31:0] audgen_sampshift; +reg [4:0] audgen_lrck_cnt; +reg audgen_lrck; +reg audgen_dac; + +always @(negedge audgen_sclk) begin + // output the next bit + audgen_dac <= audgen_sampshift[31]; + + // 48khz * 64 + audgen_lrck_cnt <= audgen_lrck_cnt + 1'b1; + if(audgen_lrck_cnt == 31) begin + // switch channels + audgen_lrck <= ~audgen_lrck; + + // Reload sample shifter + if(~audgen_lrck) begin + audgen_sampshift <= audgen_sampdata_s; + end + end else if(audgen_lrck_cnt < 16) begin + // only shift for 16 clocks per channel + audgen_sampshift <= {audgen_sampshift[30:0], 1'b0}; + end +end + +/////////////////////////////////////// +// Core Video +/////////////////////////////////////// + +wire videowht, videoblk, compositesync, lamp1, lamp2; +wire hblank, vblank_internal; +wire hs, vs; +wire [2:0] r, g, b; + +reg [7:0] vid_mono; + +assign r = vid_mono[7:5]; +assign g = vid_mono[7:5]; +assign b = vid_mono[7:5]; + +always @(posedge clk_sys) begin + casex({videowht, videoblk}) + 2'b01: vid_mono <= 8'b01010000; + 2'b10: vid_mono <= 8'b10000110; + 2'b11: vid_mono <= 8'b11111111; + 2'b00: vid_mono <= 8'b00000000; + endcase +end + +assign video_rgb_clock = clk_25; +assign video_rgb_clock_90 = clk_25_90deg; + +reg video_de_reg; +reg video_hs_reg; +reg video_vs_reg; +reg [23:0] video_rgb_reg; +reg video_skip_reg; + +assign video_de = video_de_reg; +assign video_hs = video_hs_reg; +assign video_vs = video_vs_reg; +assign video_rgb = video_rgb_reg; +assign video_skip = video_skip_reg; + +reg hs_prev; +reg vs_prev; + +always @(posedge clk_25) begin + video_de_reg <= 0; + video_rgb_reg <= 24'h0; + + if (~(VBlank || HBlank)) begin + video_de_reg <= 1; + video_rgb_reg[23:16] <= {3{r}}; + video_rgb_reg[15:8] <= {3{g}}; + video_rgb_reg[7:0] <= {3{b}}; + end + + video_hs_reg <= ~hs_prev && hs; + video_vs_reg <= ~vs_prev && vs; + hs_prev <= hs; + vs_prev <= vs; +end + +/////////////////////////////////////// +// Core Controls +/////////////////////////////////////// + +wire [15:0] cont1_key_s; +wire [15:0] cont2_key_s; + +synch_2 #( + .WIDTH(16) +) cont1_s ( + cont1_key, + cont1_key_s, + clk_core_12 +); + +synch_2 #( + .WIDTH(16) +) cont2_s ( + cont2_key, + cont2_key_s, + clk_core_12 +); + +wire m_left1 = cont1_key_s[2]; +wire m_right1 = cont1_key_s[3]; +wire m_up1 = cont1_key_s[0]; +wire m_down1 = cont1_key_s[1]; + +wire m_left2 = cont2_key_s[2]; +wire m_right2 = cont2_key_s[3]; +wire m_up2 = cont2_key_s[0]; +wire m_down2 = cont2_key_s[1]; + +wire m_coin1 = cont1_key_s[15]; +wire m_coin2 = cont2_key_s[8]; +wire m_start1 = cont1_key_s[14]; +wire m_start2 = cont2_key_s[9]; + +/////////////////////////////////////// +// Core Instance +/////////////////////////////////////// + +/* +-- Configuration DIP switches, these can be brought out to external switches if desired +-- See dominos 2 manual page 11 for complete information. Active low (0 = On, 1 = Off) +-- 1 2 Points to win (00 - 3, 01 - 4, 10 - 5, 11 - 6) +-- 3 4 Game Cost (10 - 1 Coin per player) +-- 5 6 7 8 Unused +SW1 <= SW1_I; -- "1010"; -- Config dip switches 1-4 +*/ + +wire [3:0] SW1 = {1'b1, 1'b0, 1'b1, 1'b0}; + +wire clk_sys; + +dominos dominos( + .Clk_50_I(clk_50), + .Reset_I(reset_n), + + .dn_addr(io_addr[16:0]), + .dn_data(io_dout), + .dn_wr(io_wr), + + .VideoW_O(videowht), + .VideoB_O(videoblk), + + .Sync_O(compositesync), + .Audio_O(audio), + + // ???? + .Coin1_I(~(m_start1)), + .Coin2_I(~(m_start2)), + .Start1_I(~m_coin1), + .Start2_I(~m_coin2), + + .Up1(~m_up1), + .Down1(~m_down1), + .Left1(~m_left1), + .Right1(~m_right1), + + .Up2(~m_up2), + .Down2(~m_down2), + .Left2(~m_left2), + .Right2(~m_right2), + + .Test_I (1'b1), + .Lamp1_O(lamp1), + .Lamp2_O(lamp2), + .hs_O(hs), + .vs_O(vs), + .hblank_O(hblank), + .vblank_O(vblank_internal), + .clk_12(clk_core_12), + .clk_6_O(ce_pix), + .SW1_I(SW1) +); + +assign clk_sys = clk_core_12; + +wire ce_pix; +reg HBlank, VBlank; + +always @(posedge clk_sys) begin + reg [10:0] hcnt, vcnt; + reg old_hbl, old_vbl; + + if(ce_pix) begin + hcnt <= hcnt + 1'd1; + old_hbl <= hblank; + if(old_hbl & ~hblank) begin + hcnt <= 0; + + vcnt <= vcnt + 1'd1; + old_vbl <= vblank_internal; + if(old_vbl & ~vblank_internal) vcnt <= 0; + end + + if (hcnt == 6) HBlank <= 0; + if (hcnt == 326) HBlank <= 1; + + if (vcnt == 0) VBlank <= 0; + if (vcnt == 241) VBlank <= 1; + end +end + +endmodule diff --git a/src/fpga/core/data_loader_8.v b/src/fpga/core/data_loader_8.v new file mode 100644 index 0000000..ea181fa --- /dev/null +++ b/src/fpga/core/data_loader_8.v @@ -0,0 +1,223 @@ +// MIT License + +// Copyright (c) 2022 Adam Gastineau + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +// SOFTWARE. +// +//////////////////////////////////////////////////////////////////////////////// + +// A data loader for consuming APF bridge writes and directing them to some storage medium +// +// This takes the 32 bit words from APF, and splits it into four / OUTPUT_WORD_SIZE words (4 separate bytes, or 2 16-bit words). +// You can configure the cycle delay by setting WRITE_MEM_CLOCK_DELAY +module data_loader #( + // Upper 4 bits of address + parameter ADDRESS_MASK_UPPER_4 = 0, + parameter ADDRESS_SIZE = 14, + + // Number of clk_memory cycles to delay each write output + // Min 4. Component will assert this value is within the valid range + // Be aware that APF sends data every ~75 74MHz cycles, so you cannot send data slower than this + parameter WRITE_MEM_CLOCK_DELAY = 4, + + // Number of clk_memory cycles to hold the write_en signal high + // Min 1. Component will assert this value is within the valid range + parameter WRITE_MEM_EN_CYCLE_LENGTH = 1, + + // Word size in number of bytes. Can either be 1 (output 8 bits), or 2 (output 16 bits) + // Component will assert this value is within the valid range + parameter OUTPUT_WORD_SIZE = 1 +) ( + input wire clk_74a, + input wire clk_memory, + + input wire bridge_wr, + input wire bridge_endian_little, + input wire [31:0] bridge_addr, + input wire [31:0] bridge_wr_data, + + // These outputs are synced to the memory clock + output reg write_en = 0, + output reg [ADDRESS_SIZE:0] write_addr = 0, + output reg [8 * OUTPUT_WORD_SIZE - 1:0] write_data = 0 +); + + `define MAX(x, y) ((x > y) ? x : y) + + localparam WORD_SIZE = 8 * OUTPUT_WORD_SIZE; + + // Only use the lower 28 bits of the address + localparam FIFO_SIZE = WORD_SIZE + 28; + + wire mem_empty; + + wire [FIFO_SIZE - 1:0] fifo_out; + + reg read_req = 0; + reg write_req = 0; + reg [31:0] shift_data; + reg [27:0] buff_bridge_addr; + + wire [FIFO_SIZE - 1:0] fifo_in = {shift_data[WORD_SIZE-1:0], buff_bridge_addr[27:0]}; + + dcfifo dcfifo_component ( + .data(fifo_in), + .rdclk(clk_memory), + .rdreq(read_req), + .wrclk(clk_74a), + .wrreq(write_req), + .q(fifo_out), + .rdempty(mem_empty) + // .wrempty(), + // .aclr(), + // .eccstatus(), + // .rdfull(), + // .rdusedw(), + // .wrfull(), + // .wrusedw() + ); + defparam dcfifo_component.clocks_are_synchronized = "FALSE", + dcfifo_component.intended_device_family = "Cyclone V", dcfifo_component.lpm_numwords = 4, + dcfifo_component.lpm_showahead = "OFF", dcfifo_component.lpm_type = "dcfifo", + dcfifo_component.lpm_width = FIFO_SIZE, dcfifo_component.lpm_widthu = 2, + dcfifo_component.overflow_checking = "OFF", dcfifo_component.rdsync_delaypipe = 5, + dcfifo_component.underflow_checking = "OFF", dcfifo_component.use_eab = "OFF", + dcfifo_component.wrsync_delaypipe = 5; + + /// APF to Mem clock + + reg prev_bridge_wr = 0; + reg [2:0] write_count = 0; + reg [2:0] write_state = 0; + + localparam WRITE_START = 1; + localparam WRITE_REQ_SHIFT = 2; + + // Receive APF writes and buffer them into the memory clock domain + always @(posedge clk_74a) begin + prev_bridge_wr <= bridge_wr; + + if (~prev_bridge_wr && bridge_wr && bridge_addr[31:28] == ADDRESS_MASK_UPPER_4) begin + // Beginning APF write to core + write_state <= WRITE_REQ_SHIFT; + write_req <= 1; + write_count <= 0; + + shift_data <= bridge_endian_little ? bridge_wr_data : { + bridge_wr_data[7:0], bridge_wr_data[15:8], bridge_wr_data[23:16], bridge_wr_data[31:24] + }; + + buff_bridge_addr <= bridge_addr[27:0]; + end + + case (write_state) + WRITE_START: begin + write_req <= 1; + + write_state <= WRITE_REQ_SHIFT; + end + WRITE_REQ_SHIFT: begin + write_req <= 0; + + // We will be writing again in the next cycle + shift_data <= {8'h0, shift_data[31:WORD_SIZE]}; + buff_bridge_addr <= buff_bridge_addr + OUTPUT_WORD_SIZE; + + write_count <= write_count + 1; + + if (write_count == (4 / OUTPUT_WORD_SIZE) - 1) begin + // Finished write + write_state <= 0; + end else begin + write_state <= WRITE_START; + end + end + endcase + end + + /// Mem clock to core + + reg [5:0] read_state = 0; + + localparam READ_DELAY = 1; + localparam READ_WRITE = 2; + localparam READ_WRITE_EN_CYCLE_OFF = READ_WRITE + WRITE_MEM_EN_CYCLE_LENGTH; + localparam READ_WRITE_END_DEFAULT = WRITE_MEM_CLOCK_DELAY - 1; + // Must use max to prevent READ_WRITE_END from being the same as READ_WRITE_EN_CYCLE_OFF + localparam READ_WRITE_END = + `MAX(READ_WRITE_END_DEFAULT, READ_WRITE_EN_CYCLE_OFF + 1); + localparam HAS_DELAY = READ_WRITE_END_DEFAULT > READ_WRITE_EN_CYCLE_OFF; + + always @(posedge clk_memory) begin + if (read_state != 0) begin + read_state <= read_state + 1; + end else if (~mem_empty) begin + // Start read + read_state <= READ_DELAY; + read_req <= 1; + end + + case (read_state) + READ_DELAY: begin + read_req <= 0; + write_en <= 0; + end + READ_WRITE: begin + // Read data is available + write_en <= 1; + + // Lowest 28 bits are the address + write_addr <= fifo_out[27:0]; + + write_data <= fifo_out[WORD_SIZE+27:28]; + + read_req <= 0; + end + READ_WRITE_EN_CYCLE_OFF: begin + write_en <= 0; + + if (!HAS_DELAY) begin + // No extra delay, immediately go back to start + read_state <= 0; + end + end + READ_WRITE_END: begin + read_state <= 0; + end + endcase + end + + initial begin + // Verify parameters + if (WRITE_MEM_CLOCK_DELAY < 4) begin + $error("WRITE_MEM_CLOCK_DELAY has a minimum value of 4. Received %d", WRITE_MEM_CLOCK_DELAY); + end + + if (WRITE_MEM_EN_CYCLE_LENGTH < 1 || WRITE_MEM_EN_CYCLE_LENGTH >= WRITE_MEM_CLOCK_DELAY - 2) begin + $error( + "WRITE_MEM_EN_CYCLE_LENGTH must be between 1 and %d (inclusive, based off of WRITE_MEM_CLOCK_DELAY). Received %d", + WRITE_MEM_CLOCK_DELAY - 2 - 1, WRITE_MEM_EN_CYCLE_LENGTH); + end + + if (OUTPUT_WORD_SIZE < 1 || OUTPUT_WORD_SIZE > 2) begin + $error("OUTPUT_WORD_SIZE must be 1 or 2. Received %d", OUTPUT_WORD_SIZE); + end + end + +endmodule \ No newline at end of file diff --git a/src/fpga/core/mf_pllbase.bsf b/src/fpga/core/mf_pllbase.bsf new file mode 100644 index 0000000..101956a --- /dev/null +++ b/src/fpga/core/mf_pllbase.bsf @@ -0,0 +1,126 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2022 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 160 304) + (text "mf_pllbase" (rect 48 -1 91 11)(font "Arial" (font_size 10))) + (text "inst" (rect 8 288 20 300)(font "Arial" )) + (port + (pt 0 72) + (input) + (text "refclk" (rect 0 0 22 12)(font "Arial" (font_size 8))) + (text "refclk" (rect 4 61 40 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 48 72)(line_width 1)) + ) + (port + (pt 0 112) + (input) + (text "rst" (rect 0 0 10 12)(font "Arial" (font_size 8))) + (text "rst" (rect 4 101 22 112)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 48 112)(line_width 1)) + ) + (port + (pt 160 72) + (output) + (text "outclk_0" (rect 0 0 33 12)(font "Arial" (font_size 8))) + (text "outclk_0" (rect 117 61 165 72)(font "Arial" (font_size 8))) + (line (pt 160 72)(pt 112 72)(line_width 1)) + ) + (port + (pt 160 112) + (output) + (text "outclk_1" (rect 0 0 31 12)(font "Arial" (font_size 8))) + (text "outclk_1" (rect 119 101 167 112)(font "Arial" (font_size 8))) + (line (pt 160 112)(pt 112 112)(line_width 1)) + ) + (port + (pt 160 152) + (output) + (text "outclk_2" (rect 0 0 33 12)(font "Arial" (font_size 8))) + (text "outclk_2" (rect 117 141 165 152)(font "Arial" (font_size 8))) + (line (pt 160 152)(pt 112 152)(line_width 1)) + ) + (port + (pt 160 192) + (output) + (text "outclk_3" (rect 0 0 33 12)(font "Arial" (font_size 8))) + (text "outclk_3" (rect 117 181 165 192)(font "Arial" (font_size 8))) + (line (pt 160 192)(pt 112 192)(line_width 1)) + ) + (port + (pt 160 232) + (output) + (text "outclk_4" (rect 0 0 34 12)(font "Arial" (font_size 8))) + (text "outclk_4" (rect 117 221 165 232)(font "Arial" (font_size 8))) + (line (pt 160 232)(pt 112 232)(line_width 1)) + ) + (port + (pt 160 272) + (output) + (text "locked" (rect 0 0 24 12)(font "Arial" (font_size 8))) + (text "locked" (rect 127 261 163 272)(font "Arial" (font_size 8))) + (line (pt 160 272)(pt 112 272)(line_width 1)) + ) + (drawing + (text "refclk" (rect 16 43 68 99)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 53 67 124 144)(font "Arial" (color 0 0 0))) + (text "reset" (rect 19 83 68 179)(font "Arial" (color 128 0 0)(font_size 9))) + (text "reset" (rect 53 107 136 224)(font "Arial" (color 0 0 0))) + (text "outclk0" (rect 113 43 268 99)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 97 67 212 144)(font "Arial" (color 0 0 0))) + (text "outclk1" (rect 113 83 268 179)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 97 107 212 224)(font "Arial" (color 0 0 0))) + (text "outclk2" (rect 113 123 268 259)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 97 147 212 304)(font "Arial" (color 0 0 0))) + (text "outclk3" (rect 113 163 268 339)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 97 187 212 384)(font "Arial" (color 0 0 0))) + (text "outclk4" (rect 113 203 268 419)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 97 227 212 464)(font "Arial" (color 0 0 0))) + (text "locked" (rect 113 243 262 499)(font "Arial" (color 128 0 0)(font_size 9))) + (text "export" (rect 82 267 200 544)(font "Arial" (color 0 0 0))) + (text " altera_pll " (rect 118 288 308 586)(font "Arial" )) + (line (pt 48 32)(pt 112 32)(line_width 1)) + (line (pt 112 32)(pt 112 288)(line_width 1)) + (line (pt 48 288)(pt 112 288)(line_width 1)) + (line (pt 48 32)(pt 48 288)(line_width 1)) + (line (pt 49 52)(pt 49 76)(line_width 1)) + (line (pt 50 52)(pt 50 76)(line_width 1)) + (line (pt 49 92)(pt 49 116)(line_width 1)) + (line (pt 50 92)(pt 50 116)(line_width 1)) + (line (pt 111 52)(pt 111 76)(line_width 1)) + (line (pt 110 52)(pt 110 76)(line_width 1)) + (line (pt 111 92)(pt 111 116)(line_width 1)) + (line (pt 110 92)(pt 110 116)(line_width 1)) + (line (pt 111 132)(pt 111 156)(line_width 1)) + (line (pt 110 132)(pt 110 156)(line_width 1)) + (line (pt 111 172)(pt 111 196)(line_width 1)) + (line (pt 110 172)(pt 110 196)(line_width 1)) + (line (pt 111 212)(pt 111 236)(line_width 1)) + (line (pt 110 212)(pt 110 236)(line_width 1)) + (line (pt 111 252)(pt 111 276)(line_width 1)) + (line (pt 110 252)(pt 110 276)(line_width 1)) + (line (pt 0 0)(pt 160 0)(line_width 1)) + (line (pt 160 0)(pt 160 304)(line_width 1)) + (line (pt 0 304)(pt 160 304)(line_width 1)) + (line (pt 0 0)(pt 0 304)(line_width 1)) + ) +) diff --git a/src/fpga/core/mf_pllbase.ppf b/src/fpga/core/mf_pllbase.ppf new file mode 100644 index 0000000..8e1d7c2 --- /dev/null +++ b/src/fpga/core/mf_pllbase.ppf @@ -0,0 +1,17 @@ + + + + + + + + + + + + + diff --git a/src/fpga/core/mf_pllbase.qip b/src/fpga/core/mf_pllbase.qip new file mode 100644 index 0000000..4e07e99 --- /dev/null +++ b/src/fpga/core/mf_pllbase.qip @@ -0,0 +1,337 @@ +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_TOOL_VERSION "21.1" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_TOOL_ENV "mwpim" +set_global_assignment -library "mf_pllbase" -name MISC_FILE [file join $::quartus(qip_path) "mf_pllbase.cmp"] +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_QSYS_MODE "UNKNOWN" +set_global_assignment -name SYNTHESIS_ONLY_QIP ON +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_COMPONENT_NAME "bWZfcGxsYmFzZQ==" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA=" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_COMPONENT_VERSION "MjEuMQ==" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_NAME "bWZfcGxsYmFzZV8wMDAy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_VERSION "MjEuMQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::RnJhY3Rpb25hbC1OIFBMTA==::UExMIE1vZGU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::dHJ1ZQ==::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NzQuMjU=::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NzQuMjUgTUh6::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::bm9ybWFs::T3BlcmF0aW9uIE1vZGU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::bm9ybWFs::b3BlcmF0aW9uX21vZGU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::NQ==::TnVtYmVyIE9mIENsb2Nrcw==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::NQ==::bnVtYmVyX29mX2Nsb2Nrcw==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MTIuMDk2Nzc0::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::NDMzODI0MTQ4::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::NjI=::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MTIuMDk2Nzc0::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::NDMzODI0MTQ4::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::NjI=::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::Mjc2Ljc0MDY0MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::ZGVncmVlcw==::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MjAzNDU=::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::OTAuMA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::NTAuMA==::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::NDMzODI0MTQ4::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MTU=::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::ZGVncmVlcw==::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::Ni4wNDgzODc=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::NDMzODI0MTQ4::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MTI0::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::ZGVncmVlcw==::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::NTgxMQ==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MjI1LjAgZGVn::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::Ni4wNDgzODc=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::NDMzODI0MTQ4::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MTI0::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::ZGVncmVlcw==::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::NTY0Mg==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::OTAuMA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MTIuMDk2NzcyIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MTIuMDk2NzcyIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MjA2NjcgcHM=::cGhhc2Vfc2hpZnQx" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::NDkuOTk5OTkwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::Ni4wNDgzODUgTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::Ni4wNDgzODUgTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::NDEzMzMgcHM=::cGhhc2Vfc2hpZnQ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T2Zm::UExMIEF1dG8gUmVzZXQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTMgSGkgRGl2aWRlLEMtQ291bnRlci0zIExvdyBEaXZpZGUsQy1Db3VudGVyLTMgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0zIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTMgSW5wdXQgU291cmNlLEMtQ291bnRlci0zIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTMgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTQgSGkgRGl2aWRlLEMtQ291bnRlci00IExvdyBEaXZpZGUsQy1Db3VudGVyLTQgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci00IFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTQgSW5wdXQgU291cmNlLEMtQ291bnRlci00IEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTQgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NSw1LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSwzMSwzMSwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwzMSwzMSwxNiw0LHBoX211eF9jbGssZmFsc2UsZmFsc2UsOCw3LDEsMCxwaF9tdXhfY2xrLGZhbHNlLHRydWUsNjIsNjIsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsNjIsNjIsMzIsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDEsMzAsMjAwMCw3NDkuOTk5ODExIE1Ieiw0MzM4MjQxNDgsZ2NsayxnbGIsZmJfMSxwaF9tdXhfY2xrLGZhbHNl::UGFyYW1ldGVyIFZhbHVlcw==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw=" + +set_global_assignment -library "mf_pllbase" -name VERILOG_FILE [file join $::quartus(qip_path) "mf_pllbase.v"] +set_global_assignment -library "mf_pllbase" -name VERILOG_FILE [file join $::quartus(qip_path) "mf_pllbase/mf_pllbase_0002.v"] +set_global_assignment -library "mf_pllbase" -name QIP_FILE [file join $::quartus(qip_path) "mf_pllbase/mf_pllbase_0002.qip"] + +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_TOOL_VERSION "21.1" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_TOOL_ENV "mwpim" diff --git a/src/fpga/core/mf_pllbase.sip b/src/fpga/core/mf_pllbase.sip new file mode 100644 index 0000000..dfd33b0 --- /dev/null +++ b/src/fpga/core/mf_pllbase.sip @@ -0,0 +1,6 @@ +set_global_assignment -entity "mf_pllbase" -library "lib_mf_pllbase" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "mf_pllbase" -library "lib_mf_pllbase" -name IP_TOOL_VERSION "21.1" +set_global_assignment -entity "mf_pllbase" -library "lib_mf_pllbase" -name IP_TOOL_ENV "mwpim" +set_global_assignment -library "lib_mf_pllbase" -name SPD_FILE [file join $::quartus(sip_path) "mf_pllbase.spd"] + +set_global_assignment -library "lib_mf_pllbase" -name MISC_FILE [file join $::quartus(sip_path) "mf_pllbase_sim/mf_pllbase.vo"] diff --git a/src/fpga/core/mf_pllbase.spd b/src/fpga/core/mf_pllbase.spd new file mode 100644 index 0000000..025504e --- /dev/null +++ b/src/fpga/core/mf_pllbase.spd @@ -0,0 +1,6 @@ + + + + + + diff --git a/src/fpga/core/mf_pllbase.v b/src/fpga/core/mf_pllbase.v new file mode 100644 index 0000000..85867f5 --- /dev/null +++ b/src/fpga/core/mf_pllbase.v @@ -0,0 +1,261 @@ +// megafunction wizard: %PLL Intel FPGA IP v21.1% +// GENERATION: XML +// mf_pllbase.v + +// Generated using ACDS version 21.1 850 + +`timescale 1 ps / 1 ps +module mf_pllbase ( + input wire refclk, // refclk.clk + input wire rst, // reset.reset + output wire outclk_0, // outclk0.clk + output wire outclk_1, // outclk1.clk + output wire outclk_2, // outclk2.clk + output wire outclk_3, // outclk3.clk + output wire outclk_4, // outclk4.clk + output wire locked // locked.export + ); + + mf_pllbase_0002 mf_pllbase_inst ( + .refclk (refclk), // refclk.clk + .rst (rst), // reset.reset + .outclk_0 (outclk_0), // outclk0.clk + .outclk_1 (outclk_1), // outclk1.clk + .outclk_2 (outclk_2), // outclk2.clk + .outclk_3 (outclk_3), // outclk3.clk + .outclk_4 (outclk_4), // outclk4.clk + .locked (locked) // locked.export + ); + +endmodule +// Retrieval info: +// +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval 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info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// IPFS_FILES : mf_pllbase.vo +// RELATED_FILES: mf_pllbase.v, mf_pllbase_0002.v diff --git a/src/fpga/core/mf_pllbase/mf_pllbase_0002.qip b/src/fpga/core/mf_pllbase/mf_pllbase_0002.qip new file mode 100644 index 0000000..5578caa --- /dev/null +++ b/src/fpga/core/mf_pllbase/mf_pllbase_0002.qip @@ -0,0 +1,4 @@ +set_instance_assignment -name PLL_COMPENSATION_MODE NORMAL -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_AUTO_RESET OFF -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*" diff --git a/src/fpga/core/mf_pllbase/mf_pllbase_0002.v b/src/fpga/core/mf_pllbase/mf_pllbase_0002.v new file mode 100644 index 0000000..5d3e2ea --- /dev/null +++ b/src/fpga/core/mf_pllbase/mf_pllbase_0002.v @@ -0,0 +1,99 @@ +`timescale 1ns/10ps +module mf_pllbase_0002( + + // interface 'refclk' + input wire refclk, + + // interface 'reset' + input wire rst, + + // interface 'outclk0' + output wire outclk_0, + + // interface 'outclk1' + output wire outclk_1, + + // interface 'outclk2' + output wire outclk_2, + + // interface 'outclk3' + output wire outclk_3, + + // interface 'outclk4' + output wire outclk_4, + + // interface 'locked' + output wire locked +); + + altera_pll #( + .fractional_vco_multiplier("true"), + .reference_clock_frequency("74.25 MHz"), + .operation_mode("normal"), + .number_of_clocks(5), + .output_clock_frequency0("12.096772 MHz"), + .phase_shift0("0 ps"), + .duty_cycle0(50), + .output_clock_frequency1("12.096772 MHz"), + .phase_shift1("20667 ps"), + .duty_cycle1(50), + .output_clock_frequency2("49.999990 MHz"), + .phase_shift2("0 ps"), + .duty_cycle2(50), + .output_clock_frequency3("6.048385 MHz"), + .phase_shift3("0 ps"), + .duty_cycle3(50), + .output_clock_frequency4("6.048385 MHz"), + .phase_shift4("41333 ps"), + .duty_cycle4(50), + .output_clock_frequency5("0 MHz"), + .phase_shift5("0 ps"), + .duty_cycle5(50), + .output_clock_frequency6("0 MHz"), + .phase_shift6("0 ps"), + .duty_cycle6(50), + .output_clock_frequency7("0 MHz"), + .phase_shift7("0 ps"), + .duty_cycle7(50), + .output_clock_frequency8("0 MHz"), + .phase_shift8("0 ps"), + .duty_cycle8(50), + .output_clock_frequency9("0 MHz"), + .phase_shift9("0 ps"), + .duty_cycle9(50), + .output_clock_frequency10("0 MHz"), + .phase_shift10("0 ps"), + .duty_cycle10(50), + .output_clock_frequency11("0 MHz"), + .phase_shift11("0 ps"), + .duty_cycle11(50), + .output_clock_frequency12("0 MHz"), + .phase_shift12("0 ps"), + .duty_cycle12(50), + .output_clock_frequency13("0 MHz"), + .phase_shift13("0 ps"), + .duty_cycle13(50), + .output_clock_frequency14("0 MHz"), + .phase_shift14("0 ps"), + .duty_cycle14(50), + .output_clock_frequency15("0 MHz"), + .phase_shift15("0 ps"), + .duty_cycle15(50), + .output_clock_frequency16("0 MHz"), + .phase_shift16("0 ps"), + .duty_cycle16(50), + .output_clock_frequency17("0 MHz"), + .phase_shift17("0 ps"), + .duty_cycle17(50), + .pll_type("General"), + .pll_subtype("General") + ) altera_pll_i ( + .rst (rst), + .outclk ({outclk_4, outclk_3, outclk_2, outclk_1, outclk_0}), + .locked (locked), + .fboutclk ( ), + .fbclk (1'b0), + .refclk (refclk) + ); +endmodule + diff --git a/src/fpga/core/mf_pllbase_sim.f b/src/fpga/core/mf_pllbase_sim.f new file mode 100644 index 0000000..a4f4055 --- /dev/null +++ b/src/fpga/core/mf_pllbase_sim.f @@ -0,0 +1 @@ +mf_pllbase_sim/mf_pllbase.vo diff --git a/src/fpga/core/mf_pllbase_sim/aldec/rivierapro_setup.tcl b/src/fpga/core/mf_pllbase_sim/aldec/rivierapro_setup.tcl new file mode 100644 index 0000000..d1443f0 --- /dev/null +++ b/src/fpga/core/mf_pllbase_sim/aldec/rivierapro_setup.tcl @@ -0,0 +1,278 @@ + +# (C) 2001-2022 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions and +# other software and tools, and its AMPP partner logic functions, and +# any output files any of the foregoing (including device programming +# or simulation files), and any associated documentation or information +# are expressly subject to the terms and conditions of the Altera +# Program License Subscription Agreement, Altera MegaCore Function +# License Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by Altera +# or its authorized distributors. Please refer to the applicable +# agreement for further details. + +# ACDS 21.1 850 win32 2022.09.16.11:12:12 +# ---------------------------------------- +# Auto-generated simulation script rivierapro_setup.tcl +# ---------------------------------------- +# This script provides commands to simulate the following IP detected in +# your Quartus project: +# mf_pllbase +# +# Altera recommends that you source this Quartus-generated IP simulation +# script from your own customized top-level script, and avoid editing this +# generated script. +# +# To write a top-level script that compiles Altera simulation libraries and +# the Quartus-generated IP in your project, along with your design and +# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below +# into a new file, e.g. named "aldec.do", and modify the text as directed. +# +# ---------------------------------------- +# # TOP-LEVEL TEMPLATE - BEGIN +# # +# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to +# # construct paths to the files required to simulate the IP in your Quartus +# # project. By default, the IP script assumes that you are launching the +# # simulator from the IP script location. If launching from another +# # location, set QSYS_SIMDIR to the output directory you specified when you +# # generated the IP script, relative to the directory from which you launch +# # the simulator. +# # +# set QSYS_SIMDIR