info.yaml

# Tiny Tapeout project information
project:
  title:        "DDR throughput and flop aperature test"
  author:       "Eric Smith"
  discord:      "ericsmith8798"
  description:  "Grab data on every edge of clock with varying pos pulse width"
  language:     "Verilog"
  clock_hz:     0     

  # How many tiles your design occupies? A single tile is about 167x108 uM.
  tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2

  # Your top module name must start with "tt_um_". Make it unique by including your github username:
  top_module:  "tt_um_wokwi_407306064811090945"

  # List your project's source files here.
  # Source files must be in ./src and you must list each source file separately, one per line.
  # Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
  source_files:
    - "project.v"

# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
pinout:
  # Inputs
  ui[0]: "pulse = 1 inv"
  ui[1]: "pulse = 3 inv"
  ui[2]: "pulse = 5 inv"
  ui[3]: "pulse = 7 inv"
  ui[4]: ""
  ui[5]: ""
  ui[6]: ""
  ui[7]: ""

  # Outputs
  uo[0]: "q for pulse = 1 inv"
  uo[1]: "q for pulse = 3 inv "
  uo[2]: "q for pulse = 5 inv"
  uo[3]: "q for pulse = 7 inv"
  uo[4]: "q for normal flop"
  uo[5]: "1"
  uo[6]: "1"
  uo[7]: "clk"

  # Bidirectional pins
  uio[0]: ""
  uio[1]: ""
  uio[2]: ""
  uio[3]: ""
  uio[4]: ""
  uio[5]: ""
  uio[6]: ""
  uio[7]: ""

# Do not change!
yaml_version: 6