roms missing when building caravel user project

[mattvenn]

Hi Eric,
not sure how to solve this in context of your project, but wanted to make a note.
The paddle and sine roms needed to be in the src directory for yosys to find them in the caravel context.

so what's interesting is that in this case the roms need to be in the same directory as the source files.
but they need to be elsewhere for the tests. What would be ideal is if we could just have them in the src location and somehow make the tests find them.

[mattvenn]

I guess we could just put symlinks in the src directory as well, but it's weird that in the caravel context they need to be src not your top level.

[erikvanzijst]

Yeah, the tools seem fairly picky in resolving rom paths. It would make sense for them to at least look in the same directory as the source file that loads them, followed by the tool's own PWD, but unfortunately they don't all do that. iverilator does not look relative to the source file and so fails when run from somewhere else.

As mentioned I've been creating symlinks in various places, but it's obviously not ideal :-)

[erikvanzijst]

I'm assuming you ran into this running make user_project_wrapper in caravel_user_project?

erik@erik-pc:~/work/caravel_user_project$ make user_project_wrapper
cd openlane && make user_project_wrapper
make[1]: Entering directory '/home/erik/work/caravel_user_project/openlane'
###############################################
[INFO]: 
	___   ____   ___  ____   _       ____  ____     ___
	/   \ |    \ /  _]|    \ | |     /    ||    \   /  _]
	|     ||  o  )  [_ |  _  || |    |  o  ||  _  | /  [_
	|  O  ||   _/    _]|  |  || |___ |     ||  |  ||    _]
	|     ||  | |   [_ |  |  ||     ||  _  ||  |  ||   [_
	\___/ |__| |_____||__|__||_____||__|__||__|__||_____|

[...]

1. Executing Verilog-2005 frontend: /project/openlane/user_project_wrapper/../../caravel/verilog/rtl/defines.v
Parsing Verilog input from `/project/openlane/user_project_wrapper/../../caravel/verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: /project/openlane/user_project_wrapper/../../verilog/rtl/user_project_includes.v
/project/openlane/user_project_wrapper/../../verilog/rtl/wrapped_pong/pong/src/trig.v:0: ERROR: Can not open file `sine.lut` for \$readmemb.
[ERROR]: during executing: "yosys -c /openLANE_flow/scripts/synth_top.tcl -l /project/openlane/user_project_wrapper/runs/user_project_wrapper/logs/synthesis/1-yosys.log |& tee >&@stdout"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child process exited abnormally

[ERROR]: Please check yosys  log file
[ERROR]: Dumping to /project/openlane/user_project_wrapper/runs/user_project_wrapper/error.log
[INFO]: Calculating Runtime From the Start...
[INFO]: Flow failed for user_project_wrapper/31-05_20-47 in 0h0m4s
[INFO]: Generating Final Summary Report...
[INFO]: Design Name: user_project_wrapper
Run Directory: /project/openlane/user_project_wrapper/runs/user_project_wrapper
Source not found.
----------------------------------------

LVS Summary:
Source: /project/openlane/user_project_wrapper/runs/user_project_wrapper/results/lvs/user_project_wrapper.lvs_parsed.gds.log
Source not found.
----------------------------------------

Antenna Summary:
No antenna report found.
[INFO]: check full report here: /project/openlane/user_project_wrapper/runs/user_project_wrapper/reports/final_summary_report.csv
[ERROR]: Flow Failed.

    while executing
"try_catch [get_yosys_bin]  -c $::env(SYNTH_SCRIPT)  -l [index_file $::env(yosys_log_file_tag).log 0]  |& tee $::env(TERMINAL_OUTPUT)"
    (procedure "run_yosys" line 34)
    invoked from within
"run_yosys"
    (procedure "run_synthesis" line 9)
    invoked from within
"run_synthesis"
    (procedure "run_non_interactive_mode" line 14)
    invoked from within
"run_non_interactive_mode {*}$argv"
    invoked from within
"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {
	puts_info "Running interactively"
	if { [info exists arg_values(-file)..."
    (file "/openLANE_flow/flow.tcl" line 223)
make[1]: *** [Makefile:43: user_project_wrapper] Error 1
make[1]: Leaving directory '/home/erik/work/caravel_user_project/openlane'
make: *** [Makefile:71: user_project_wrapper] Error 2

How did you work around that? It's unclear from what directory yosys is run and therefore where to create more symlinks.

[mattvenn]

I symlinked them from the wrapped_pong/pong/src directory. Might have got that directory wrong, but the same directory as paddle.v that tries to read the rom. That's what I meant about it being weird that when we run yosys in this context it expects the roms to be where the source files are. I still don't know how to alter this.

…

On Mon, 31 May 2021 at 23:01, Erik van Zijst ***@***.***> wrote: I'm assuming you ran into this running make user_project_wrapper in caravel_user_project? ***@***.***:~/work/caravel_user_project$ make user_project_wrapper cd openlane && make user_project_wrapper make[1]: Entering directory '/home/erik/work/caravel_user_project/openlane' ############################################### [INFO]: ___ ____ ___ ____ _ ____ ____ ___ / \ | \ / _]| \ | | / || \ / _] | || o ) [_ | _ || | | o || _ | / [_ | O || _/ _]| | || |___ | || | || _] | || | | [_ | | || || _ || | || [_ \___/ |__| |_____||__|__||_____||__|__||__|__||_____| [...] 1. Executing Verilog-2005 frontend: /project/openlane/user_project_wrapper/../../caravel/verilog/rtl/defines.v Parsing Verilog input from `/project/openlane/user_project_wrapper/../../caravel/verilog/rtl/defines.v' to AST representation. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: /project/openlane/user_project_wrapper/../../verilog/rtl/user_project_includes.v /project/openlane/user_project_wrapper/../../verilog/rtl/wrapped_pong/pong/src/trig.v:0: ERROR: Can not open file `sine.lut` for \$readmemb. [ERROR]: during executing: "yosys -c /openLANE_flow/scripts/synth_top.tcl -l /project/openlane/user_project_wrapper/runs/user_project_wrapper/logs/synthesis/1-yosys.log |& tee ***@***.***" [ERROR]: Exit code: 1 [ERROR]: Last 10 lines: child process exited abnormally [ERROR]: Please check yosys log file [ERROR]: Dumping to /project/openlane/user_project_wrapper/runs/user_project_wrapper/error.log [INFO]: Calculating Runtime From the Start... [INFO]: Flow failed for user_project_wrapper/31-05_20-47 in 0h0m4s [INFO]: Generating Final Summary Report... [INFO]: Design Name: user_project_wrapper Run Directory: /project/openlane/user_project_wrapper/runs/user_project_wrapper Source not found. ---------------------------------------- LVS Summary: Source: /project/openlane/user_project_wrapper/runs/user_project_wrapper/results/lvs/user_project_wrapper.lvs_parsed.gds.log Source not found. ---------------------------------------- Antenna Summary: No antenna report found. [INFO]: check full report here: /project/openlane/user_project_wrapper/runs/user_project_wrapper/reports/final_summary_report.csv [ERROR]: Flow Failed. while executing "try_catch [get_yosys_bin] -c $::env(SYNTH_SCRIPT) -l [index_file $::env(yosys_log_file_tag).log 0] |& tee $::env(TERMINAL_OUTPUT)" (procedure "run_yosys" line 34) invoked from within "run_yosys" (procedure "run_synthesis" line 9) invoked from within "run_synthesis" (procedure "run_non_interactive_mode" line 14) invoked from within "run_non_interactive_mode {*}$argv" invoked from within "if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } { puts_info "Running interactively" if { [info exists arg_values(-file)..." (file "/openLANE_flow/flow.tcl" line 223) make[1]: *** [Makefile:43: user_project_wrapper] Error 1 make[1]: Leaving directory '/home/erik/work/caravel_user_project/openlane' make: *** [Makefile:71: user_project_wrapper] Error 2 How did you work around that? It's unclear from what directory yosys is run and therefore where to create more symlinks. — You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub <#1 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AAE223HCXGA474FOOQYOIPDTQP2MJANCNFSM45UARYNQ> .

-- Matthew Venn web mattvenn.net twitter @matthewvenn <https://twitter.com/matthewvenn>