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gpio_set_level for GPIO_NUM_16 & GPIO_NUM_25 is not working for me. (IDFGH-5235) #7005

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iam-jd opened this issue May 10, 2021 · 13 comments
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Resolution: Done Issue is done internally Status: Done Issue is done internally

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@iam-jd
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iam-jd commented May 10, 2021

Environment

  • Module or chip used: ESP32-WROOM-32
  • IDF version : v4.2.1
  • Build System: idf.py
  • Compiler version : 8.4.0
  • Operating System: Windows
  • (Windows only) environment type: ESP Command Prompt
  • Using an IDE?: Yes, VSCode IDE
  • Power Supply: USB

Problem Description

//Detailed problem description goes here.
I have on going project which has binary size of 1457 KB.
When I try to gpio_set_level(GPIO_NUM_16,1) after initializing everything properly, that GPIO 16 it is not set to High.

Expected Behavior

When I call for gpio_set_level(GPIO_NUM_16,1). It has to set to High.

Actual Behavior

It is not Set to High. But when I call it in While loop without any delay or any other function it is set to high.

Steps to reproduce

I have tried to modify the gpio example code. it works perfectly. but when I tried to add it to my project it is not working.
I even tried to disable entire program logic. and just used the same code as like as example. But result is same.

And I tried to call the gpio_set_level in a loop which makes it work

This is happening only for the GPIO_NUM_16 and GPIO_NUM_25. other GPIOs are working perfectly.

Code to reproduce this issue

// the code should be wrapped in the ```cpp tag so that it will be displayed better.
#include "esp_log.h"
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/queue.h"
#include "driver/gpio.h"

#define GPIO_OUTPUT_IO_0    16
#define GPIO_OUTPUT_IO_1    25
#define GPIO_OUTPUT_PIN_SEL  ((1ULL<<GPIO_OUTPUT_IO_0) | (1ULL<<GPIO_OUTPUT_IO_1))
#define GPIO_INPUT_IO_0     4
#define GPIO_INPUT_IO_1     5
#define GPIO_INPUT_PIN_SEL  ((1ULL<<GPIO_INPUT_IO_0) | (1ULL<<GPIO_INPUT_IO_1))
#define ESP_INTR_FLAG_DEFAULT 0

#define HIGH 1
#define LOW 0

void app_main(void)
{
    gpio_config_t io_conf;
    //disable interrupt
    io_conf.intr_type = GPIO_PIN_INTR_DISABLE;
    //set as output mode
    io_conf.mode = GPIO_MODE_OUTPUT;
    //bit mask of the pins that you want to set,e.g.GPIO18/19
    io_conf.pin_bit_mask = GPIO_OUTPUT_PIN_SEL;
    //disable pull-down mode
    io_conf.pull_down_en = 0;
    //disable pull-up mode
    io_conf.pull_up_en = 0;
    //configure GPIO with the given settings
    gpio_config(&io_conf);

    //interrupt of rising edge
    io_conf.intr_type = GPIO_PIN_INTR_POSEDGE;
    //bit mask of the pins, use GPIO4/5 here
    io_conf.pin_bit_mask = GPIO_INPUT_PIN_SEL;
    //set as input mode    
    io_conf.mode = GPIO_MODE_INPUT;
    //enable pull-up mode
    io_conf.pull_up_en = 1;
    gpio_config(&io_conf);

    //change gpio intrrupt type for one pin
    gpio_set_intr_type(GPIO_INPUT_IO_0, GPIO_INTR_ANYEDGE);

    //create a queue to handle gpio event from isr
    // gpio_evt_queue = xQueueCreate(10, sizeof(uint32_t));
    // //start gpio task
    // xTaskCreate(gpio_task_example, "gpio_task_example", 2048, NULL, 10, NULL);

    //install gpio isr service
    gpio_install_isr_service(ESP_INTR_FLAG_DEFAULT);
    //hook isr handler for specific gpio pin
    // gpio_isr_handler_add(GPIO_INPUT_IO_0, gpio_isr_handler, (void*) GPIO_INPUT_IO_0);
    // //hook isr handler for specific gpio pin
    // gpio_isr_handler_add(GPIO_INPUT_IO_1, gpio_isr_handler, (void*) GPIO_INPUT_IO_1);

    //remove isr handler for gpio number.
    // gpio_isr_handler_remove(GPIO_INPUT_IO_0);
    // //hook isr handler for specific gpio pin again
    // gpio_isr_handler_add(GPIO_INPUT_IO_0, gpio_isr_handler, (void*) GPIO_INPUT_IO_0);

    int cnt = 0;
    gpio_set_level(GPIO_OUTPUT_IO_0,HIGH);
    gpio_set_level(GPIO_OUTPUT_IO_1,HIGH);
    // while(1) {
    //     printf("cnt: %d\n", cnt++);
    //     vTaskDelay(1000 / portTICK_RATE_MS);
    //     gpio_set_level(GPIO_OUTPUT_IO_0, cnt % 2);
    //     gpio_set_level(GPIO_OUTPUT_IO_1, cnt % 2);
    // }
}

// If your code is longer than 30 lines, GIST is preferred.

Debug Logs

entry 0x40080710
I (29) boot: ESP-IDF v4.2 2nd stage bootloader
I (29) boot: compile time 17:10:29
I (29) boot: chip revision: 1
I (31) qio_mode: Enabling default flash chip QIO
I (36) boot.esp32: SPI Speed      : 40MHz
I (41) boot.esp32: SPI Mode       : QIO
I (46) boot.esp32: SPI Flash Size : 4MB
I (50) boot: Enabling RNG early entropy source...
I (56) boot: Partition Table:
I (59) boot: ## Label            Usage          Type ST Offset   Length
I (66) boot:  0 nvs              WiFi data        01 02 00009000 00004000
I (74) boot:  1 otadata          OTA data         01 00 0000d000 00002000
I (81) boot:  2 phy_init         RF data          01 01 0000f000 00001000
I (89) boot:  3 ota_0            OTA app          00 10 00010000 001c2000
I (96) boot:  4 ota_1            OTA app          00 11 001e0000 001c2000
I (104) boot:  5 storage          Unknown data     01 82 003a2000 00040000
I (111) boot:  6 nvs_key          NVS keys         01 04 003e2000 00001000
I (119) boot: End of partition table
I (123) boot: No factory image, trying OTA 0
I (128) esp_image: segment 0: paddr=0x00010020 vaddr=0x3f400020 size=0x46c80 (289920) map
I (232) esp_image: segment 1: paddr=0x00056ca8 vaddr=0x3ffbdb60 size=0x04140 ( 16704) load
I (238) esp_image: segment 2: paddr=0x0005adf0 vaddr=0x40080000 size=0x00404 (  1028) load

I (239) esp_image: segment 3: paddr=0x0005b1fc vaddr=0x40080404 size=0x04e1c ( 19996) load
I (256) esp_image: segment 4: paddr=0x00060020 vaddr=0x400d0020 size=0xf9804 (1021956) map
0x400d0020: _stext at ??:?

I (592) esp_image: segment 5: paddr=0x0015982c vaddr=0x40085220 size=0x19314 (103188) load
0x40085220: coex_classic_bt_release$part$0 at ld_fm.c:?

I (632) esp_image: segment 6: paddr=0x00172b48 vaddr=0x400c0000 size=0x00064 (   100) load
I (648) boot: Loaded app from partition at offset 0x10000
I (682) boot: Set actual ota_seq=1 in otadata[0]
I (682) boot: Disabling RNG early entropy source...
I (682) cpu_start: Pro cpu up.
I (685) cpu_start: Application information:
I (690) cpu_start: Project name:     ABCD
I (695) cpu_start: App version:      40569bf-dirty
I (700) cpu_start: Compile time:     May 10 2021 17:10:17
I (706) cpu_start: ELF file SHA256:  471e1d12ceecb37a...
I (712) cpu_start: ESP-IDF:          v4.2
I (717) cpu_start: Starting app cpu, entry point is 0x40081890

I (0) cpu_start: App cpu up.
D (727) memory_layout: Checking 11 reserved memory ranges:
D (733) memory_layout: Reserved memory range 0x3ffae000 - 0x3ffae6e0
D (739) memory_layout: Reserved memory range 0x3ffae6e0 - 0x3ffaff10
D (746) memory_layout: Reserved memory range 0x3ffb0000 - 0x3ffb6388
D (752) memory_layout: Reserved memory range 0x3ffb8000 - 0x3ffb9a20
D (758) memory_layout: Reserved memory range 0x3ffbdb28 - 0x3ffbdb5c
D (765) memory_layout: Reserved memory range 0x3ffbdb60 - 0x3ffcd7b0
D (771) memory_layout: Reserved memory range 0x3ffe0000 - 0x3ffe0440
D (778) memory_layout: Reserved memory range 0x3ffe3f20 - 0x3ffe4350
D (784) memory_layout: Reserved memory range 0x40070000 - 0x40078000
D (791) memory_layout: Reserved memory range 0x40078000 - 0x40080000

D (797) memory_layout: Reserved memory range 0x40080000 - 0x4009e534

D (803) memory_layout: Building list of available memory regions:
D (810) memory_layout: Available memory region 0x3ffaff10 - 0x3ffb0000
D (816) memory_layout: Available memory region 0x3ffb6388 - 0x3ffb8000
D (823) memory_layout: Available memory region 0x3ffb9a20 - 0x3ffbdb28
D (829) memory_layout: Available memory region 0x3ffcd7b0 - 0x3ffce000
D (836) memory_layout: Available memory region 0x3ffce000 - 0x3ffd0000
D (842) memory_layout: Available memory region 0x3ffd0000 - 0x3ffd2000
D (849) memory_layout: Available memory region 0x3ffd2000 - 0x3ffd4000
D (856) memory_layout: Available memory region 0x3ffd4000 - 0x3ffd6000
D (862) memory_layout: Available memory region 0x3ffd6000 - 0x3ffd8000
D (869) memory_layout: Available memory region 0x3ffd8000 - 0x3ffda000
D (875) memory_layout: Available memory region 0x3ffda000 - 0x3ffdc000
D (882) memory_layout: Available memory region 0x3ffdc000 - 0x3ffde000
D (889) memory_layout: Available memory region 0x3ffde000 - 0x3ffe0000
D (895) memory_layout: Available memory region 0x3ffe0440 - 0x3ffe3f20
D (902) memory_layout: Available memory region 0x3ffe4350 - 0x3ffe8000
D (908) memory_layout: Available memory region 0x3ffe8000 - 0x3fff0000
D (915) memory_layout: Available memory region 0x3fff0000 - 0x3fff8000
D (922) memory_layout: Available memory region 0x3fff8000 - 0x3fffc000
D (928) memory_layout: Available memory region 0x3fffc000 - 0x40000000
D (935) memory_layout: Available memory region 0x4009e534 - 0x400a0000
I (941) heap_init: Initializing. RAM available for dynamic allocation:
D (949) heap_init: New heap initialised at 0x3ffaff10
I (954) heap_init: At 3FFAFF10 len 000000F0 (0 KiB): DRAM
D (960) heap_init: New heap initialised at 0x3ffb6388
I (965) heap_init: At 3FFB6388 len 00001C78 (7 KiB): DRAM
D (971) heap_init: New heap initialised at 0x3ffb9a20
I (976) heap_init: At 3FFB9A20 len 00004108 (16 KiB): DRAM
D (982) heap_init: New heap initialised at 0x3ffcd7b0
I (987) heap_init: At 3FFCD7B0 len 00012850 (74 KiB): DRAM
I (994) heap_init: At 3FFE0440 len 00003AE0 (14 KiB): D/IRAM
I (1000) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
D (1006) heap_init: New heap initialised at 0x4009e534
I (1012) heap_init: At 4009E534 len 00001ACC (6 KiB): IRAM
I (1018) cpu_start: Pro cpu start user code
D (1023) clk: waiting for 32k oscillator to start up
D (1059) clk: RTC_SLOW_CLK calibration value: 11414464
D (1065) intr_alloc: Connected src 46 to int 2 (cpu 0)
D (1065) intr_alloc: Connected src 17 to int 3 (cpu 0)
D (1066) intr_alloc: Connected src 24 to int 9 (cpu 0)
D (1071) FLASH_HAL: extra_dummy: 1
D (1074) spi_flash: trying chip: issi
D (1078) spi_flash: trying chip: gd
D (1082) spi_flash: trying chip: mxic
D (1085) spi_flash: trying chip: generic
I (1089) spi_flash: detected chip: generic
I (1094) spi_flash: flash io: qio
D (1098) chip_generic: set_io_mode: status before 0x200
I (1103) cpu_start: Starting scheduler on PRO CPU.
D (0) intr_alloc: Connected src 25 to int 2 (cpu 1)
I (0) cpu_start: Starting scheduler on APP CPU.
D (1119) heap_init: New heap initialised at 0x3ffe0440
D (1129) heap_init: New heap initialised at 0x3ffe4350
D (1139) intr_alloc: Connected src 16 to int 12 (cpu 0)
D (1139) APP: [APP] StartuP..
D (1139) APP: [APP] Free memory: 206936 bytes
D (1149) APP: [APP] IDF version: v4.2
D (1149) partition: Loading the partition table
D (1169) event: running task for loop 0x3ffbd778
D (1169) event: created task for loop 0x3ffbd778
D (1169) event: created event loop 0x3ffbd778
D (1169) APP: Heaps Are Valid
D (1179) SLEEP: Not a deep sleep reset

D (1179) history: Initializing SPIFFS
I (1209) history: Partition size: total: 233681, used: 502
D (1209) ADC: ADC Calibrartion Type 0

I (1209) gpio: GPIO[15]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:0
I (1219) gpio: GPIO[16]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:0
I (1229) gpio: GPIO[17]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:0
I (1239) gpio: GPIO[19]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:0
I (1249) gpio: GPIO[21]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:0
I (1259) gpio: GPIO[22]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:0
I (1269) gpio: GPIO[23]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:0
I (1269) gpio: GPIO[12]| InputEn: 1| OutputEn: 0| OpenDrain: 0| Pullup: 1| Pulldown: 0| Intr:0
I (1279) gpio: GPIO[18]| InputEn: 1| OutputEn: 0| OpenDrain: 0| Pullup: 1| Pulldown: 0| Intr:0
D (1289) intr_alloc: Connected src 22 to int 13 (cpu 0)
D (1299) intr_alloc: Connected src 35 to int 17 (cpu 0)
D (1299) intr_alloc: Connected src 49 to int 18 (cpu 0)
@espressif-bot espressif-bot added the Status: Opened Issue is new label May 10, 2021
@github-actions github-actions bot changed the title gpio_set_level for GPIO_NUM_16 & GPIO_NUM_25 is not working for me. gpio_set_level for GPIO_NUM_16 & GPIO_NUM_25 is not working for me. (IDFGH-5235) May 10, 2021
@iam-jd
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iam-jd commented May 11, 2021

Problem Description

Hey, Today I found something strange. Could someone help me with this. Even though I disable All GPIO Configs in my Code. Somehow intr_alloc is adding specific GPIO 16 & 25 to interrupt logics.

Code to reproduce this issue

// the code should be wrapped in the ```cpp tag so that it will be displayed better.
#include "esp_log.h"

void app_main(void)
{
    // gpio_config_t io_conf;
    // //disable interrupt
    // io_conf.intr_type = GPIO_PIN_INTR_DISABLE;
    // //set as output mode
    // io_conf.mode = GPIO_MODE_OUTPUT;
    // //bit mask of the pins that you want to set,e.g.GPIO18/19
    // io_conf.pin_bit_mask = GPIO_OUTPUT_PIN_SEL;
    // //disable pull-down mode
    // io_conf.pull_down_en = 0;
    // //disable pull-up mode
    // io_conf.pull_up_en = 0;
    // //configure GPIO with the given settings
    // gpio_config(&io_conf);

    // //interrupt of rising edge
    // io_conf.intr_type = GPIO_PIN_INTR_POSEDGE;
    // //bit mask of the pins, use GPIO4/5 here
    // io_conf.pin_bit_mask = GPIO_INPUT_PIN_SEL;
    // //set as input mode    
    // io_conf.mode = GPIO_MODE_INPUT;
    // //enable pull-up mode
    // io_conf.pull_up_en = 1;
    // gpio_config(&io_conf);

    //change gpio intrrupt type for one pin
    // gpio_set_intr_type(GPIO_INPUT_IO_0, GPIO_INTR_ANYEDGE);

    //create a queue to handle gpio event from isr
    // gpio_evt_queue = xQueueCreate(10, sizeof(uint32_t));
    // //start gpio task
    // xTaskCreate(gpio_task_example, "gpio_task_example", 2048, NULL, 10, NULL);

    //install gpio isr service
    // gpio_install_isr_service(ESP_INTR_FLAG_DEFAULT);
    //hook isr handler for specific gpio pin
    // gpio_isr_handler_add(GPIO_INPUT_IO_0, gpio_isr_handler, (void*) GPIO_INPUT_IO_0);
    // //hook isr handler for specific gpio pin
    // gpio_isr_handler_add(GPIO_INPUT_IO_1, gpio_isr_handler, (void*) GPIO_INPUT_IO_1);

    //remove isr handler for gpio number.
    // gpio_isr_handler_remove(GPIO_INPUT_IO_0);
    // //hook isr handler for specific gpio pin again
    // gpio_isr_handler_add(GPIO_INPUT_IO_0, gpio_isr_handler, (void*) GPIO_INPUT_IO_0);

    int cnt = 0;
	// while (1){
	gpio_set_level(BM_LITE_RST_N,HIGH);
	ESP_LOGD(TAG,"BM_LITE_IRQ GPIO Level: %d",gpio_get_level(BM_LITE_IRQ));
	ESP_LOGD(TAG,"LOCK_PLATE_FEEDBACK GPIO Level: %d",gpio_get_level(LOCK_PLATE_FEEDBACK));

	// }
    // while(1) {
    //     printf("cnt: %d\n", cnt++);
    //     vTaskDelay(1000 / portTICK_RATE_MS);
    //     gpio_set_level(GPIO_OUTPUT_IO_0, cnt % 2);
    //     gpio_set_level(GPIO_OUTPUT_IO_1, cnt % 2);
    // }
}

// If your code is longer than 30 lines, GIST is preferred.

Debug Logs

I (220) boot: Loaded app from partition at offset 0x10000
I (220) boot: Disabling RNG early entropy source...
I (220) cpu_start: Pro cpu up.
I (224) cpu_start: Application information:
I (229) cpu_start: Project name:     APP
I (233) cpu_start: App version:      40569bf-dirty
I (239) cpu_start: Compile time:     May 11 2021 11:18:28
I (245) cpu_start: ELF file SHA256:  6f43b9403b5d0046...
I (251) cpu_start: ESP-IDF:          v4.2.1
I (256) cpu_start: Starting app cpu, entry point is 0x400814a0

I (0) cpu_start: App cpu up.
D (266) memory_layout: Checking 11 reserved memory ranges:
D (271) memory_layout: Reserved memory range 0x3ffae000 - 0x3ffae6e0
D (278) memory_layout: Reserved memory range 0x3ffae6e0 - 0x3ffaff10
D (284) memory_layout: Reserved memory range 0x3ffb0000 - 0x3ffb6388
D (291) memory_layout: Reserved memory range 0x3ffb8000 - 0x3ffb9a20
D (297) memory_layout: Reserved memory range 0x3ffbdb28 - 0x3ffbdb5c
D (303) memory_layout: Reserved memory range 0x3ffbdb60 - 0x3ffc03d0
D (310) memory_layout: Reserved memory range 0x3ffe0000 - 0x3ffe0440
D (316) memory_layout: Reserved memory range 0x3ffe3f20 - 0x3ffe4350
D (323) memory_layout: Reserved memory range 0x40070000 - 0x40078000
D (329) memory_layout: Reserved memory range 0x40078000 - 0x40080000

D (335) memory_layout: Reserved memory range 0x40080000 - 0x400891e4

D (342) memory_layout: Building list of available memory regions:
D (348) memory_layout: Available memory region 0x3ffaff10 - 0x3ffb0000
D (355) memory_layout: Available memory region 0x3ffb6388 - 0x3ffb8000
D (361) memory_layout: Available memory region 0x3ffb9a20 - 0x3ffbdb28
D (368) memory_layout: Available memory region 0x3ffc03d0 - 0x3ffc2000
D (374) memory_layout: Available memory region 0x3ffc2000 - 0x3ffc4000
D (381) memory_layout: Available memory region 0x3ffc4000 - 0x3ffc6000
D (388) memory_layout: Available memory region 0x3ffc6000 - 0x3ffc8000
D (394) memory_layout: Available memory region 0x3ffc8000 - 0x3ffca000
D (401) memory_layout: Available memory region 0x3ffca000 - 0x3ffcc000
D (407) memory_layout: Available memory region 0x3ffcc000 - 0x3ffce000
D (414) memory_layout: Available memory region 0x3ffce000 - 0x3ffd0000
D (421) memory_layout: Available memory region 0x3ffd0000 - 0x3ffd2000
D (427) memory_layout: Available memory region 0x3ffd2000 - 0x3ffd4000
D (434) memory_layout: Available memory region 0x3ffd4000 - 0x3ffd6000
D (440) memory_layout: Available memory region 0x3ffd6000 - 0x3ffd8000
D (447) memory_layout: Available memory region 0x3ffd8000 - 0x3ffda000
D (454) memory_layout: Available memory region 0x3ffda000 - 0x3ffdc000
D (460) memory_layout: Available memory region 0x3ffdc000 - 0x3ffde000
D (467) memory_layout: Available memory region 0x3ffde000 - 0x3ffe0000
D (473) memory_layout: Available memory region 0x3ffe0440 - 0x3ffe3f20
D (480) memory_layout: Available memory region 0x3ffe4350 - 0x3ffe8000
D (487) memory_layout: Available memory region 0x3ffe8000 - 0x3fff0000
D (493) memory_layout: Available memory region 0x3fff0000 - 0x3fff8000
D (500) memory_layout: Available memory region 0x3fff8000 - 0x3fffc000
D (506) memory_layout: Available memory region 0x3fffc000 - 0x40000000
D (513) memory_layout: Available memory region 0x400891e4 - 0x4008a000
D (520) memory_layout: Available memory region 0x4008a000 - 0x4008c000
D (526) memory_layout: Available memory region 0x4008c000 - 0x4008e000
D (533) memory_layout: Available memory region 0x4008e000 - 0x40090000
D (539) memory_layout: Available memory region 0x40090000 - 0x40092000
D (546) memory_layout: Available memory region 0x40092000 - 0x40094000
D (553) memory_layout: Available memory region 0x40094000 - 0x40096000
D (559) memory_layout: Available memory region 0x40096000 - 0x40098000
D (566) memory_layout: Available memory region 0x40098000 - 0x4009a000
D (572) memory_layout: Available memory region 0x4009a000 - 0x4009c000
D (579) memory_layout: Available memory region 0x4009c000 - 0x4009e000
D (586) memory_layout: Available memory region 0x4009e000 - 0x400a0000
I (592) heap_init: Initializing. RAM available for dynamic allocation:
D (599) heap_init: New heap initialised at 0x3ffaff10
I (604) heap_init: At 3FFAFF10 len 000000F0 (0 KiB): DRAM
D (611) heap_init: New heap initialised at 0x3ffb6388
I (616) heap_init: At 3FFB6388 len 00001C78 (7 KiB): DRAM
D (622) heap_init: New heap initialised at 0x3ffb9a20
I (627) heap_init: At 3FFB9A20 len 00004108 (16 KiB): DRAM
D (633) heap_init: New heap initialised at 0x3ffc03d0
I (638) heap_init: At 3FFC03D0 len 0001FC30 (127 KiB): DRAM
I (644) heap_init: At 3FFE0440 len 00003AE0 (14 KiB): D/IRAM
I (651) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
D (657) heap_init: New heap initialised at 0x400891e4
I (662) heap_init: At 400891E4 len 00016E1C (91 KiB): IRAM
I (668) cpu_start: Pro cpu start user code
D (673) clk: waiting for 32k oscillator to start up
D (709) clk: RTC_SLOW_CLK calibration value: 11948147
D (715) intr_alloc: Connected src 46 to int 2 (cpu 0)
D (715) intr_alloc: Connected src 17 to int 3 (cpu 0)
D (716) intr_alloc: Connected src 24 to int 9 (cpu 0)
D (721) FLASH_HAL: extra_dummy: 1
D (724) spi_flash: trying chip: issi
D (728) spi_flash: trying chip: gd
D (731) spi_flash: trying chip: mxic
D (735) spi_flash: trying chip: generic
I (739) spi_flash: detected chip: generic
I (744) spi_flash: flash io: qio
D (747) chip_generic: set_io_mode: status before 0x200
I (753) cpu_start: Starting scheduler on PRO CPU.
D (0) intr_alloc: Connected src 25 to int 2 (cpu 1)
I (0) cpu_start: Starting scheduler on APP CPU.
D (768) heap_init: New heap initialised at 0x3ffe0440
D (778) heap_init: New heap initialised at 0x3ffe4350
D (778) intr_alloc: Connected src 16 to int 12 (cpu 0)

@negativekelvin
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D (0) intr_alloc: Connected src 25 to int 2 (cpu 1)

This has nothing to do with gpios, interrupt sources have their own numbering system

@iam-jd
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iam-jd commented May 11, 2021

But As I Can see clearly, I can't able set the level for these GPIOs to High without Calling it in loop. But Other GPIOs are working fine. I even tried to declared them as a Inputs. In that case it works fine. What may be reason?.

@ryan4volts
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ryan4volts commented May 14, 2021

Try something more rudimentary like the below.

const int io_25 = 25;
gpio_pad_select_gpio(io_25);
ESP_ERROR_CHECK(gpio_set_direction((gpio_num_t)io_25 , (gpio_mode_t)GPIO_MODE_OUTPUT));
ESP_ERROR_CHECK(gpio_set_level((gpio_num_t)io_25 , 1));

Note the following IOs are used for flash/ram and SHOULD not be used for general ios:

  • IO11
  • IO7
  • IO16
  • IO17
  • IO6
  • IO8

@iam-jd
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iam-jd commented May 24, 2021

Try something more rudimentary like the below.

const int io_25 = 25;
gpio_pad_select_gpio(io_25);
ESP_ERROR_CHECK(gpio_set_direction((gpio_num_t)io_25 , (gpio_mode_t)GPIO_MODE_OUTPUT));
ESP_ERROR_CHECK(gpio_set_level((gpio_num_t)io_25 , 1));

Note the following IOs are used for flash/ram and SHOULD not be used for general ios:

  • IO11
  • IO7
  • IO16
  • IO17
  • IO6
  • IO8

I tried this. But it didn't show any progress. The issue is still there.
Also, As PSRAM is Optional one, I didn't use that in my design.

@iam-jd
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iam-jd commented May 24, 2021

D (0) intr_alloc: Connected src 25 to int 2 (cpu 1)

This has nothing to do with gpios, interrupt sources have their own numbering system

But I can't able use those pins as output. Particularly , GPIO16, 17 and 25. Which is connected to the intr_alloc. Can you please help me with this.?

@iam-jd
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iam-jd commented Jul 31, 2021

@negativekelvin Can I get any suggestion regard this. I am still getting this issue. even after I update esp-idf to v4.3.

@ginkgm
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ginkgm commented Aug 2, 2021

Hi @Dineshkumar-J ,

Your issue looks like a concurrency issue, I wonder if there are too many controller for the same GPIO. Are you using gpio_set_level in different threads for GPIO16 and GPIO25 respectively? btw, using interrupt will not reduce your problem, unless you are moving all the code into the interrupt, otherwise you are just adding one possible controller for the GPIO to make it more uncontrollable.

Another thought, as you say, if your code is simpled enough (only one task), and looks very like the example but still can't work. The only difference between your code and the example is the sdkconfig. Maybe you can compare the sdkconfig of the example, and your project.

Michael

@mkeyno
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mkeyno commented Apr 15, 2022

GPIO_NUM_17 & GPIO_NUM_16 are used on the chips that use the PSRAM, however, the chip I use (Sparkfun ESP32 microcode) has no PSRAM, however, I can not control it as output
I'm guessing using the flash of any type disables those pin functionality

@ginkgm
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ginkgm commented Apr 17, 2022

Hi @mkeyno ,
I don't know too much about 3rd party module/devkits. But basically which pins are occupied by Flash and PSRAM is determined by:

  1. the efuse inside your module. (decides CLK, CS, MOSI, MISO, HD, package)
  2. bootloader sdkconfig (decides WP, will also check the package above)
  3. PSRAM sdkconfig (decides CLK and CS of PSRAM, will also check the package above)

But before continue debugging, I suggest check if those pins are break out on your devkit first. If you are sure your devkit vendor supports that, please come up with:

  1. The sdkconfig you are using (please check your vendors' documentation on what's the default sdkconfig you are suggested to use)
  2. The efuse inside your chip (by calling espefuse.py summary)

btw, I think this issue (package related) is case by case, next time please open a new issue, instead of replying under the same topic. This topic will be closed as soon as this discussion is resolved.

@Alvin1Zhang
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Thanks for reporting, will close due to short of feedback, feel free to reopen.

@espressif-bot espressif-bot added Status: Done Issue is done internally Resolution: Done Issue is done internally and removed Status: Opened Issue is new labels Jun 14, 2023
@L-KAYA
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L-KAYA commented Jun 14, 2023

For now, there is a function to check whether a pin on the current SoC is reserved for other purpose, for example:

#include "esp_gpio_reserve.h"
...
uint32_t pin = 16;
bool is_reserved = esp_gpio_is_pin_reserved(pin);

@vvb333007
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Hello from 2025! They did change location of the include file as well as the function name.

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