What was it like to learn SystemVerilog?

[ErikSchierboom]

We’ve recently started a project to find the best way to design our tracks, in order to optimize the learning experience of students.

As a first step, we’ll be examining the ways in which languages are unique and the ways in which they are similar. For this, we’d really like to use the knowledge of everyone involved in the Exercism community (students, mentors, maintainers) to answer the following questions:

1. How was your experience learning SystemVerilog? What was helpful while learning SystemVerilog? What did you struggle with? How did you tackle problems?
2. In what ways did SystemVerilog differ from other languages you knew at the time? What was hard to learn? What did you have to unlearn? What syntax did you have to remap? What concepts carried over nicely?

Could you spare 5 minutes to help us by answering these questions? It would greatly help us improve the experience students have learning SystemVerilog :)

Note: this issue is not meant as a discussion, just as a place for people to post their own, personal experiences.

Want to keep your thoughts private but still help? Feel free to email me at erik@exercism.io

Thank you!

[ErikSchierboom]

We're closing this issue as it was part of our research for the v3 version of Exercism which has just been released.

Thanks everyone for chipping in! It has been greatly appreciated.