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cpu.c
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/********************************************************************
* cpu.c
*
* MC6809E CPU emulation module.
*
* Resource MC6809E data sheet Motorola INC. 1984 DS9846-R2:
* Figure 4 - Programming model
* Figure 14 - Instruction flow chart
* Figure 17 - Cycle by cycle performance
*
* Motorola 6809 and Hitachi 6309 Programmer's Reference:
* https://colorcomputerarchive.com/repo/Documents/Books/Motorola%206809%20and%20Hitachi%206309%20Programming%20Reference%20(Darren%20Atkinson).pdf
*
* July 4, 2020
*
*******************************************************************/
#include <string.h>
#include "mc6809e.h"
#include "mem.h"
#include "cpu.h"
/* -----------------------------------------
Local definitions
----------------------------------------- */
/* MC6809E vector addresses, where
* each vector is two bytes long.
*/
#define VEC_RESET 0xfffe
#define VEC_NMI 0xfffc
#define VEC_SWI 0xfffa
#define VEC_IRQ 0xfff8
#define VEC_FIRQ 0xfff6
#define VEC_SWI2 0xfff4
#define VEC_SWI3 0xfff2
#define VEC_RESERVED 0xfff0
/* Interrupt sources
*/
#define INT_NMI 1
#define INT_IRQ 2
#define INT_FIRQ 4
/* Indexed addressing post-byte bit fields
*/
#define INDX_POST_5BIT_OFF 0x80
#define INDX_POST_REG 0x60
#define INDX_POST_INDIRECT 0x10
#define INDX_POST_MODE 0x0f
/* Condition-code register bit
*/
#define CC_FLAG_CLR 0
#define CC_FLAG_SET 1
/* Word and Byte operations
*/
#define GET_REG_HIGH(r) ((uint8_t)(r >> 8))
#define GET_REG_LOW(r) ((uint8_t)r)
#define SIG_EXTEND(b) ((((uint8_t)b) & 0x80) ? (((uint16_t)b) | 0xff00):((uint16_t)b))
/* -----------------------------------------
Module static functions
----------------------------------------- */
/* CPU op-code processing.
* These functions manipulate global variable,
* CPU registers and CC flags.
*/
static uint8_t adc(uint8_t acc, uint8_t byte);
static uint8_t add(uint8_t acc, uint8_t byte);
static void addd(uint16_t word);
static uint8_t and(uint8_t acc, uint8_t byte);
static void andcc(uint8_t byte);
static uint8_t asl(uint8_t byte);
static uint8_t asr(uint8_t byte);
static void bit(uint8_t acc, uint8_t byte);
static uint8_t clr(void);
static void cmp(uint8_t arg, uint8_t byte);
static void cmp16(uint16_t arg, uint16_t word);
static uint8_t com(uint8_t byte);
static void cwai(uint8_t byte);
static void daa(void);
static uint8_t dec(uint8_t byte);
static uint8_t eor(uint8_t acc, uint8_t byte);
static void exg(uint8_t regs);
static uint8_t inc(uint8_t byte);
static uint8_t lsr(uint8_t byte);
static uint8_t neg(uint8_t byte);
static uint8_t or(uint8_t acc, uint8_t byte);
static void orcc(uint8_t byte);
static void pshs(uint8_t push_list, int *cycles);
static void pshu(uint8_t push_list, int *cycles);
static void puls(uint8_t pull_list, int *cycles);
static void pulu(uint8_t pull_list, int *cycles);
static uint8_t rol(uint8_t byte);
static uint8_t ror(uint8_t byte);
static void rti(int *cycles);
static uint8_t sbc(uint8_t acc, uint8_t byte);
static void sex(void);
static uint8_t sub(uint8_t acc, uint8_t byte);
static void subd(uint16_t word);
static void swi(int swi_id);
static void tfr(uint8_t regs);
static void tst(uint8_t byte);
/* CPU op-code support functions
*/
static void branch(int instruction, int long_short, uint16_t effective_address, int *cycles);
static void do_branch(int long_short, uint16_t effective_address, int *cycles);
static int get_eff_addr(int op_code, int *cycles, int *bytes);
static uint16_t read_register(int reg);
static void write_register(int reg, uint16_t data);
/* Condition code register CC functions
*/
static void eval_cc_c(uint16_t value);
static void eval_cc_c16(uint32_t value);
static void eval_cc_z(uint16_t value);
static void eval_cc_z16(uint32_t value);
static void eval_cc_n(uint16_t value);
static void eval_cc_n16(uint32_t value);
static void eval_cc_v(uint8_t val1, uint8_t val2, uint16_t result);
static void eval_cc_v16(uint16_t val1, uint16_t val2, uint32_t result);
static void eval_cc_h(uint8_t val1, uint8_t val2, uint8_t result);
static uint8_t get_cc(void);
static void set_cc(uint8_t value);
/* -----------------------------------------
Module globals
----------------------------------------- */
/* MC6809E register file
*/
static cpu_state_t cpu;
static struct cc_t
{
int c;
int v;
int z;
int n;
int i;
int h;
int f;
int e;
} cc;
#define d ((uint16_t)(((uint16_t)cpu.a << 8) + cpu.b)) // Accumulator D
/*------------------------------------------------
* cpu_init()
*
* Initialize the CPU for command execution at address.
* Function should be called once before cpu_run() or cpu_single_step().
*
* param: Start address
* return: 0- initialization ok, 1- Start address error
*/
int cpu_init(int address)
{
/* Registers
*/
cpu.x = 0;
cpu.y = 0;
cpu.u = 0;
cpu.s = 0;
cpu.pc = 0;
cpu.a = 0;
cpu.b = 0;
cpu.dp = 0;
set_cc(0);
/* CPU state
*/
cpu.nmi_armed = 0;
cpu.nmi_latched = 0;
cpu.halt_asserted = 0;
cpu.reset_asserted = 0;
cpu.irq_asserted = 0;
cpu.firq_asserted = 0;
cpu.int_latch = 0;
cpu.cpu_state = CPU_HALTED;
cpu.exception_line_num = -1;
/* Check start address and update PC
*/
if ( address < 0 || address > (MEMORY-1) )
return 1;
cpu.pc = address;
return 0;
}
/*------------------------------------------------
* cpu_halt()
*
* Assert HALT state
*
* param: 0- clear, 1- asserted
* return: Nothing
*/
void cpu_halt(int state)
{
cpu.halt_asserted = state;
}
/*------------------------------------------------
* cpu_reset()
*
* Assert RESET state
*
* param: 0- clear, 1- asserted
* return: Nothing
*/
void cpu_reset(int state)
{
cpu.reset_asserted = state;
}
/*------------------------------------------------
* cpu_nmi()
*
* Trigger a Non Mask-able Interrupt (NMI) state
*
* param: 0- clear, 1- asserted
* return: Nothing
*/
void cpu_nmi_trigger(void)
{
cpu.nmi_latched = 1;
}
/*------------------------------------------------
* cpu_firq()
*
* Assert Fast IRQ (FIRQ) state
*
* param: 0- clear, 1- asserted
* return: Nothing
*/
void cpu_firq(int state)
{
cpu.firq_asserted = state;
}
/*------------------------------------------------
* cpu_irq()
*
* Assert IRQ state
*
* param: 0- clear, 1- asserted
* return: Nothing
*/
void cpu_irq(int state)
{
cpu.irq_asserted = state;
}
/*------------------------------------------------
* cpu_run()
*
* Start CPU.
* Function should be called periodically
* after an initialization by cpu_run_init().
*
* param: Nothing
* return: Integer of CPU_* value (see #define CPU_*)
*/
cpu_run_state_t cpu_run(void)
{
int op_code_index;
int cycles;
int bytes;
int eff_addr;
uint8_t operand8;
uint16_t operand16;
int intr_latch = 0;
int op_code = -1;
/* Latch interrupt requests
*/
intr_latch |= cpu.nmi_latched ? INT_NMI : 0;
intr_latch |= cpu.irq_asserted ? INT_IRQ : 0;
intr_latch |= cpu.firq_asserted ? INT_FIRQ : 0;
/* Check RESET at every cycle
* this will emulate an asynchronous RESET response.
*/
if ( cpu.reset_asserted )
{
cc.f = CC_FLAG_SET;
cc.i = CC_FLAG_SET;
cpu.dp = 0;
cpu.nmi_armed = 0;
cpu.nmi_latched = 0;
bytes = 0;
cycles = 0;
cpu.cpu_state = CPU_RESET;
cpu.pc = (mem_read(VEC_RESET) << 8) + mem_read(VEC_RESET+1);
cpu.last_pc = cpu.pc;
}
else
{
/* At exit of this function PC will point to the next op-code
* so this preserves the current PC for other uses such as
* single step etc.
*/
cpu.last_pc = cpu.pc;
/* Only check HALT and interrupts before instruction
* fetch execution
*/
if ( cpu.halt_asserted )
{
cpu.cpu_state = CPU_HALTED;
return cpu.cpu_state;
}
/* We get here if not in RESET and not HALTed.
* If the CPU was put into SYNC mode by 'SYNC' or 'CWAI'
* then this point will force the emulation to exit execution
* and stay in wait mode, or if an interrupt was latched
* then execution will proceed with op-code fetch.
*/
if ( cpu.cpu_state == CPU_SYNC )
{
if ( intr_latch & (INT_NMI | INT_FIRQ | INT_IRQ) )
{
cpu.cpu_state = CPU_EXEC;
}
else
{
return cpu.cpu_state;
}
}
/* If an interrupt is received and it is enabled, then
* setup stack frame and call interrupt service by
* setting the PC to the vectors content.
* Release CPU state to CPU_EXEC to let COU emulation
* start fetching and executing instructions.
*
* NMI signal is latched at any time and services here.
* The NMI signal is transition driven.
* The NMI latch/logic is cleared when it is acknowledged.
* FIRQ and IRQ will be samples at each op-code cycle,
* but if the IRQ/FIRQ signal was removed before sapling
* then it will not be serviced.
* The IRQ and FIRQ signal is level driven.
*/
if ( cpu.nmi_armed && (intr_latch & INT_NMI) )
{
cpu.cpu_state = CPU_EXEC;
cc.e = CC_FLAG_SET;
cpu.s--;
mem_write(cpu.s, cpu.pc & 0xff);
cpu.s--;
mem_write(cpu.s, (cpu.pc >> 8) & 0xff);
cpu.s--;
mem_write(cpu.s, cpu.u & 0xff);
cpu.s--;
mem_write(cpu.s, (cpu.u >> 8) & 0xff);
cpu.s--;
mem_write(cpu.s, cpu.y & 0xff);
cpu.s--;
mem_write(cpu.s, (cpu.y >> 8) & 0xff);
cpu.s--;
mem_write(cpu.s, cpu.x & 0xff);
cpu.s--;
mem_write(cpu.s, (cpu.x >> 8) & 0xff);
cpu.s--;
mem_write(cpu.s, cpu.dp);
cpu.s--;
mem_write(cpu.s, cpu.b);
cpu.s--;
mem_write(cpu.s, cpu.a);
cpu.s--;
mem_write(cpu.s, get_cc());
cpu.nmi_latched = 0;
cc.f = CC_FLAG_SET;
cc.i = CC_FLAG_SET;
cpu.pc = (mem_read(VEC_NMI) << 8) + mem_read(VEC_NMI+1);
}
else if ( !(cc.f) && (intr_latch & INT_FIRQ) )
{
cpu.cpu_state = CPU_EXEC;
cc.e = CC_FLAG_CLR;
cpu.s--;
mem_write(cpu.s, cpu.pc & 0xff);
cpu.s--;
mem_write(cpu.s, (cpu.pc >> 8) & 0xff);
cpu.s--;
mem_write(cpu.s, get_cc());
cc.f = CC_FLAG_SET;
cc.i = CC_FLAG_SET;
cpu.pc = (mem_read(VEC_FIRQ) << 8) + mem_read(VEC_FIRQ+1);
}
else if ( !(cc.i) && (intr_latch & INT_IRQ) )
{
cpu.cpu_state = CPU_EXEC;
cc.e = CC_FLAG_SET;
cpu.s--;
mem_write(cpu.s, cpu.pc & 0xff);
cpu.s--;
mem_write(cpu.s, (cpu.pc >> 8) & 0xff);
cpu.s--;
mem_write(cpu.s, cpu.u & 0xff);
cpu.s--;
mem_write(cpu.s, (cpu.u >> 8) & 0xff);
cpu.s--;
mem_write(cpu.s, cpu.y & 0xff);
cpu.s--;
mem_write(cpu.s, (cpu.y >> 8) & 0xff);
cpu.s--;
mem_write(cpu.s, cpu.x & 0xff);
cpu.s--;
mem_write(cpu.s, (cpu.x >> 8) & 0xff);
cpu.s--;
mem_write(cpu.s, cpu.dp);
cpu.s--;
mem_write(cpu.s, cpu.b);
cpu.s--;
mem_write(cpu.s, cpu.a);
cpu.s--;
mem_write(cpu.s, get_cc());
cc.i = CC_FLAG_SET;
cpu.pc = (mem_read(VEC_IRQ) << 8) + mem_read(VEC_IRQ+1);
}
/* CPU now running so fetch instruction.
* First we force state to CPU_EXEC so that the
* state is defined if we just came out of reset.
*/
cpu.cpu_state = CPU_EXEC;
op_code = mem_read(cpu.pc);
cpu.pc++;
/* Double-byte 0x10 prefix
*/
if ( op_code == 0x10 )
{
op_code = mem_read(cpu.pc);
cpu.pc++;
/* Search for 0x10 double byte op-code. If not found
* then fall through the loop and catch the issue in the
* switch-case below.
*/
for ( op_code_index = OP_CODE10; op_code_index < OP_CODE11; op_code_index++ )
{
if ( machine_code[op_code_index].op == op_code )
{
cycles = machine_code[op_code_index].cycles;
bytes = machine_code[op_code_index].bytes;
break;
}
}
eff_addr = get_eff_addr(op_code_index, &cycles, &bytes);
switch ( op_code )
{
/* CMPD
*/
case 0x83:
case 0x93:
case 0xa3:
case 0xb3:
operand8 = (uint8_t) mem_read(eff_addr);
eff_addr++;
operand16 = ((uint16_t) operand8 << 8) + (uint16_t) mem_read(eff_addr);
cmp16(d, operand16);
break;
/* CMPY
*/
case 0x8c:
case 0x9c:
case 0xac:
case 0xbc:
operand8 = (uint8_t) mem_read(eff_addr);
eff_addr++;
operand16 = ((uint16_t) operand8 << 8) + (uint16_t) mem_read(eff_addr);
cmp16(cpu.y, operand16);
break;
/* LDS
*/
case 0xce:
case 0xde:
case 0xee:
case 0xfe:
operand8 = (uint8_t) mem_read(eff_addr);
eff_addr++;
cpu.s = ((uint16_t) operand8 << 8) + (uint16_t) mem_read(eff_addr);
eval_cc_z16(cpu.s);
eval_cc_n16(cpu.s);
cc.v = CC_FLAG_CLR;
cpu.nmi_armed = 1;
break;
/* LDY
*/
case 0x8e:
case 0x9e:
case 0xae:
case 0xbe:
operand8 = (uint8_t) mem_read(eff_addr);
eff_addr++;
cpu.y = ((uint16_t) operand8 << 8) + (uint16_t) mem_read(eff_addr);
eval_cc_z16(cpu.y);
eval_cc_n16(cpu.y);
cc.v = CC_FLAG_CLR;
break;
/* STS
*/
case 0xdf:
case 0xef:
case 0xff:
mem_write(eff_addr, (uint8_t) (cpu.s >> 8));
mem_write(eff_addr + 1, (uint8_t) (cpu.s));
eval_cc_z16(cpu.s);
eval_cc_n16(cpu.s);
cc.v = CC_FLAG_CLR;
break;
/* STY
*/
case 0x9f:
case 0xaf:
case 0xbf:
mem_write(eff_addr, (uint8_t) (cpu.y >> 8));
mem_write(eff_addr + 1, (uint8_t) (cpu.y));
eval_cc_z16(cpu.y);
eval_cc_n16(cpu.y);
cc.v = CC_FLAG_CLR;
break;
/* LBRN
*/
case 0x21:
// Long branch never
break;
/* Long conditional branches
*/
case 0x22 ... 0x2f:
branch(op_code, 1, eff_addr, &cycles);
break;
/* SWI2
*/
case 0x3f:
swi(2);
break;
default:
/* Exception: Illegal 0x10 op-code cpu_run()
*/
cpu.cpu_state = CPU_EXCEPTION;
cpu.exception_line_num = __LINE__;
}
}
/* Double-byte 0x11 prefix
*/
else if ( op_code == 0x11 )
{
op_code = mem_read(cpu.pc);
cpu.pc++;
/* Search for 0x11 double byte op-code. If not found
* then fall through the loop and catch the issue in the
* switch-case below.
*/
for ( op_code_index = OP_CODE11; op_code_index < sizeof(machine_code)/sizeof(machine_code_t); op_code_index++ )
{
if ( machine_code[op_code_index].op == op_code )
{
cycles = machine_code[op_code_index].cycles;
bytes = machine_code[op_code_index].bytes;
break;
}
}
eff_addr = get_eff_addr(op_code_index, &cycles, &bytes);
switch ( op_code )
{
/* CMPU
*/
case 0x83:
case 0x93:
case 0xa3:
case 0xb3:
operand8 = (uint8_t) mem_read(eff_addr);
eff_addr++;
operand16 = ((uint16_t) operand8 << 8) + (uint16_t) mem_read(eff_addr);
cmp16(cpu.u, operand16);
break;
/* CMPS
*/
case 0x8c:
case 0x9c:
case 0xac:
case 0xbc:
operand8 = (uint8_t) mem_read(eff_addr);
eff_addr++;
operand16 = ((uint16_t) operand8 << 8) + (uint16_t) mem_read(eff_addr);
cmp16(cpu.s, operand16);
break;
/* SWI3
*/
case 0x3f:
swi(3);
break;
default:
/* Exception: Illegal 0x11 op-code cpu_run()
*/
cpu.cpu_state = CPU_EXCEPTION;
cpu.exception_line_num = __LINE__;
}
}
/* Common op-code processing
*/
else
{
/* 'operand8' will be operand byte, and for a 16-bit operand 'operand8'
* will be the high order byte and low order byte should be read separately
* and combined into 16-bit value.
*/
cycles = machine_code[op_code].cycles;
bytes = machine_code[op_code].bytes;
eff_addr = get_eff_addr(op_code, &cycles, &bytes);
switch ( op_code )
{
/* ABX
*/
case 0x3a:
cpu.x += cpu.b;
break;
/* ADCA
*/
case 0x89:
case 0x99:
case 0xa9:
case 0xb9:
operand8 = (uint8_t) mem_read(eff_addr);
cpu.a = adc(cpu.a, operand8);
break;
/* ADCB
*/
case 0xc9:
case 0xd9:
case 0xe9:
case 0xf9:
operand8 = (uint8_t) mem_read(eff_addr);
cpu.b = adc(cpu.b, operand8);
break;
/* ADDA
*/
case 0x8b:
case 0x9b:
case 0xab:
case 0xbb:
operand8 = (uint8_t) mem_read(eff_addr);
cpu.a = add(cpu.a, operand8);
break;
/* ADDB
*/
case 0xcb:
case 0xdb:
case 0xeb:
case 0xfb:
operand8 = (uint8_t) mem_read(eff_addr);
cpu.b = add(cpu.b, operand8);
break;
/* ADDD
*/
case 0xc3:
case 0xd3:
case 0xe3:
case 0xf3:
operand8 = (uint8_t) mem_read(eff_addr);
eff_addr++;
operand16 = ((uint16_t) operand8 << 8) + (uint16_t) mem_read(eff_addr);
addd(operand16);
break;
/* ANDA
*/
case 0x84:
case 0x94:
case 0xa4:
case 0xb4:
operand8 = (uint8_t) mem_read(eff_addr);
cpu.a = and(cpu.a, operand8);
break;
/* ADDB
*/
case 0xc4:
case 0xd4:
case 0xe4:
case 0xf4:
operand8 = (uint8_t) mem_read(eff_addr);
cpu.b = and(cpu.b, operand8);
break;
/* ANDCC
*/
case 0x1c:
operand8 = (uint8_t) mem_read(eff_addr);
andcc(operand8);
break;
/* ASL, ASLA, ASLB
* LSL, LSLA, LSLB
*/
case 0x08:
case 0x68:
case 0x78:
operand8 = (uint8_t) mem_read(eff_addr);
operand8 = asl(operand8);
mem_write(eff_addr, operand8);
break;
case 0x48:
cpu.a = asl(cpu.a);
break;
case 0x58:
cpu.b = asl(cpu.b);
break;
/* ASR, ASRA, ASRB
*/
case 0x07:
case 0x67:
case 0x77:
operand8 = (uint8_t) mem_read(eff_addr);
operand8 = asr(operand8);
mem_write(eff_addr, operand8);
break;
case 0x47:
cpu.a = asr(cpu.a);
break;
case 0x57:
cpu.b = asr(cpu.b);
break;
/* BITA
*/
case 0x85:
case 0x95:
case 0xa5:
case 0xb5:
operand8 = (uint8_t) mem_read(eff_addr);
bit(cpu.a, operand8);
break;
/* BITB
*/
case 0xc5:
case 0xd5:
case 0xe5:
case 0xf5:
operand8 = (uint8_t) mem_read(eff_addr);
bit(cpu.b, operand8);
break;
/* CLR, CLRA, CLRB
*/
case 0x0f:
case 0x6f:
case 0x7f:
operand8 = clr();
mem_write(eff_addr, operand8);
break;
case 0x4f:
cpu.a = clr();
break;
case 0x5f:
cpu.b = clr();
break;
/* CMPA
*/
case 0x81:
case 0x91:
case 0xa1:
case 0xb1:
operand8 = (uint8_t) mem_read(eff_addr);
cmp(cpu.a, operand8);
break;
/* CMPB
*/
case 0xc1:
case 0xd1:
case 0xe1:
case 0xf1:
operand8 = (uint8_t) mem_read(eff_addr);
cmp(cpu.b, operand8);
break;
/* CMPX
*/
case 0x8c:
case 0x9c:
case 0xac:
case 0xbc:
operand8 = (uint8_t) mem_read(eff_addr);
eff_addr++;
operand16 = ((uint16_t) operand8 << 8) + (uint16_t) mem_read(eff_addr);
cmp16(cpu.x, operand16);
break;
/* COM, COMA, COMB
*/
case 0x03:
case 0x63:
case 0x73:
operand8 = (uint8_t) mem_read(eff_addr);
operand8 = com(operand8);
mem_write(eff_addr, operand8);
break;
case 0x43:
cpu.a = com(cpu.a);
break;
case 0x53:
cpu.b = com(cpu.b);
break;
/* CWAI
*/
case 0x3c:
operand8 = (uint8_t) mem_read(eff_addr);
cwai(operand8);
break;
/* DAA
*/
case 0x19:
daa();
break;
/* DEC, DECA, DECB
*/
case 0x0a:
case 0x6a:
case 0x7a:
operand8 = (uint8_t) mem_read(eff_addr);
operand8 = dec(operand8);
mem_write(eff_addr, operand8);
break;
case 0x4a:
cpu.a = dec(cpu.a);
break;
case 0x5a:
cpu.b = dec(cpu.b);
break;
/* EORA
*/
case 0x88:
case 0x98:
case 0xa8:
case 0xb8:
operand8 = (uint8_t) mem_read(eff_addr);
cpu.a = eor(cpu.a, operand8);
break;
/* EORB
*/
case 0xc8:
case 0xd8:
case 0xe8:
case 0xf8:
operand8 = (uint8_t) mem_read(eff_addr);
cpu.b = eor(cpu.b, operand8);
break;
/* EXG
*/
case 0x1e:
operand8 = (uint8_t) mem_read(eff_addr);
exg(operand8);
break;
/* INC, INCA, INCB
*/
case 0x0c:
case 0x6c:
case 0x7c:
operand8 = (uint8_t) mem_read(eff_addr);
operand8 = inc(operand8);
mem_write(eff_addr, operand8);
break;
case 0x4c:
cpu.a = inc(cpu.a);
break;
case 0x5c:
cpu.b = inc(cpu.b);
break;
/* JMP
*/
case 0x0e:
case 0x6e:
case 0x7e:
cpu.pc = eff_addr;
break;
/* JSR
*/
case 0x9d:
case 0xad:
case 0xbd:
cpu.s--;
mem_write(cpu.s, GET_REG_LOW(cpu.pc));
cpu.s--;
mem_write(cpu.s, GET_REG_HIGH(cpu.pc));
cpu.pc = eff_addr;
break;
/* LDA
*/
case 0x86:
case 0x96:
case 0xa6:
case 0xb6:
cpu.a = (uint8_t) mem_read(eff_addr);;
eval_cc_z((uint16_t) cpu.a);
eval_cc_n((uint16_t) cpu.a);
cc.v = CC_FLAG_CLR;
break;
/* LDB
*/
case 0xc6:
case 0xd6:
case 0xe6:
case 0xf6:
cpu.b = (uint8_t) mem_read(eff_addr);;
eval_cc_z((uint16_t) cpu.b);
eval_cc_n((uint16_t) cpu.b);
cc.v = CC_FLAG_CLR;
break;
/* LDD
*/
case 0xcc:
case 0xdc:
case 0xec:
case 0xfc:
cpu.a = (uint8_t) mem_read(eff_addr);;
eff_addr++;
cpu.b = (uint8_t) mem_read(eff_addr);
eval_cc_z16(d);
eval_cc_n16(d);
cc.v = CC_FLAG_CLR;
break;