Risc-v Support is missing

[apcameron]

Please add support for Riscv-v based systems

[briancoutinho]

@apcameron We don't have any RISC-V systems at handto develop on, but we are open to contributions in that space
By the way, when you say support are you talking about 1) just having an rpm/deb package for RISC-v, 2) Support CPU performance counters for RISC V?

[apcameron]

1. It does not compile on a Risc-v System.
2. Support CPU performance counters for RISC V? is missing.

I was able to force it to compile with the patch below but the counters etc are missing.

diff -Naur a/hbt/src/common/System.h b/hbt/src/common/System.h
--- a/hbt/src/common/System.h   2024-01-21 15:26:26.940486370 +0000
+++ b/hbt/src/common/System.h   2024-01-21 22:22:36.713134358 +0000
@@ -445,6 +445,14 @@
   asm volatile("mrs %0, cntvct_el0" : "=r"(tstamp));
   cpu = getCpu();
   return tstamp;
+#elif defined(__riscv)
+inline TimeStamp rdtscp(CpuId& cpu) {
+  TimeStamp tstamp;
+  // Use the RDCYCLE instruction for RISC-V.
+  asm volatile("rdcycle %0" : "=r"(tstamp));
+  cpu = getCpu();
+  return tstamp;
+
 }
 #endif
 

[apcameron]

@apcameron We don't have any RISC-V systems at handto develop on, but we are open to contributions in that space By the way, when you say support are you talking about 1) just having an rpm/deb package for RISC-v, 2) Support CPU performance counters for RISC V?

Why don't you try using QEMU to emulate a Risc-V environment.
See the example here

[briancoutinho]

Hi @apcameron, thanks for sharing the fix to the build, we had to add a similar one for Arm architecture too at the same spot. Would you be comfortable contributing that to dynolog? please see Contributing.md for help and let me know any questions you may have. Regarding hardware counters, the hbt library is where the counter support should go. I believe commonly defined counters like instructions and cycles should work out of box. These are defined in Linux perf event subsystem and we use them directly. Let me know if this is not the case and we can fix it. Thanks, Brian

…

On Sun, Feb 4, 2024 at 1:07 PM apcameron ***@***.***> wrote: @apcameron <https://github.com/apcameron> We don't have any RISC-V systems at handto develop on, but we are open to contributions in that space By the way, when you say support are you talking about 1) just having an rpm/deb package for RISC-v, 2) Support CPU performance counters for RISC V? Why don't you try using QEMU to emulate a Risc-V environment. See the example here <https://discourse.ubuntu.com/t/ubuntu-installation-on-a-risc-v-virtual-machine-using-a-server-install-image-and-qemu/27636> — Reply to this email directly, view it on GitHub <#215 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/ABUZ7ZDCHTZ3K4YZ72CHKEDYR72BVAVCNFSM6AAAAABCFEKLZCVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMYTSMRVHEYTIMZZGE> . You are receiving this because you commented.Message ID: ***@***.***>

[apcameron]

Hi @apcameron, thanks for sharing the fix to the build, we had to add a similar one for Arm architecture too at the same spot. Would you be comfortable contributing that to dynolog? please see Contributing.md for help and let me know any questions you may have. Regarding hardware counters, the hbt library is where the counter support should go. I believe commonly defined counters like instructions and cycles should work out of box. These are defined in Linux perf event subsystem and we use them directly. Let me know if this is not the case and we can fix it. Thanks, Brian
…
On Sun, Feb 4, 2024 at 1:07 PM apcameron @.> wrote: @apcameron https://github.com/apcameron We don't have any RISC-V systems at handto develop on, but we are open to contributions in that space By the way, when you say support are you talking about 1) just having an rpm/deb package for RISC-v, 2) Support CPU performance counters for RISC V? Why don't you try using QEMU to emulate a Risc-V environment. See the example here https://discourse.ubuntu.com/t/ubuntu-installation-on-a-risc-v-virtual-machine-using-a-server-install-image-and-qemu/27636 — Reply to this email directly, view it on GitHub <#215 (comment)>, or unsubscribe https://github.com/notifications/unsubscribe-auth/ABUZ7ZDCHTZ3K4YZ72CHKEDYR72BVAVCNFSM6AAAAABCFEKLZCVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMYTSMRVHEYTIMZZGE . You are receiving this because you commented.Message ID: @.>

I will leave it to your team to make the updates and validate that it works correctly.