diff --git a/rtl/fwrisc_mul_div_shift.sv b/rtl/fwrisc_mul_div_shift.sv
index c7ece1e..9252c5c 100644
--- a/rtl/fwrisc_mul_div_shift.sv
+++ b/rtl/fwrisc_mul_div_shift.sv
@@ -126,7 +126,7 @@ module fwrisc_mul_div_shift #(
 					end
 				endcase
 				if (op == OP_DIV) begin
-					div_sign <= (in_a[31] != in_a[31]);
+					div_sign <= (in_a[31] != in_b[31]);
 				end else begin
 					// OP_REM and others
 					div_sign <= in_a[31];