mcd: cdc refactor

Author: Federico Berti

src/main/java/mcd/cdc/CdcImpl.java

@@ -86,7 +86,7 @@ public void write(MegaCdDict.RegSpecMcd regSpec, int address, int value, Size si
             case MCD_CDC_MODE -> {
                 int resWord = memoryContext.handleRegWrite(SUB_M68K, regSpec, address, value, size);
                 cdcContext.address = resWord & NUM_CDC_REG_MASK;
-                transfer.destination = (resWord >> 8) & 7;
+                transfer.destination = CdcTransferDestination.vals[(resWord >> 8) & 7];
                 transfer.completed = (resWord >> 15) & 1;
                 transfer.ready = (resWord >> 14) & 1;
             }
@@ -121,7 +121,7 @@ public int read(MegaCdDict.RegSpecMcd regSpec, int address, Size size) {
                 int res2 = readBuffer(memoryContext.getRegBuffer(BufferUtil.CpuDeviceAccess.SUB_M68K, regSpec),
                         address & MDC_SUB_GATE_REGS_MASK, size);
                 //according to mcd-ver, reading DSR,EDT resets them to 0 (only for DMA transfers?)
-                if (transfer.destination != 2 && transfer.destination != 3) {
+                if (transfer.destination.isDma()) {
                     transfer.completed = 0;
                     transfer.ready = 0;
                     updateCdcMode4();
@@ -396,7 +396,7 @@ public void step(int cycles) {
     }
 
     private void updateCdcMode4() {
-        int val = cdcContext.address | (transfer.destination << 8) |
+        int val = cdcContext.address | (transfer.destination.ordinal() << 8) |
                 (transfer.ready << 14) | (transfer.completed << 15);
         //TODO improve, cannot use the regWriteHandlers as bus writes cannot modify EDT,DSR
         writeBufferRaw(memoryContext.getRegBuffer(SUB_M68K, MCD_CDC_MODE),

src/main/java/mcd/cdc/CdcModel.java

@@ -86,8 +86,29 @@ interface CdcTransferAction {
         void complete();
     }
 
+    enum CdcTransferDestination {
+        NONE_0, NONE_1, MAIN_READ_2, SUB_READ_3, DMA_PCM_4, DMA_PROGRAM_5, NONE_6, DMA_SUB_WRAM_7;
+
+        public static CdcTransferDestination[] vals = CdcTransferDestination.values();
+        private boolean dmaDestination;
+        private boolean valid;
+
+        CdcTransferDestination() {
+            dmaDestination = name().startsWith("DMA");
+            valid = !name().startsWith("NONE");
+        }
+
+        public boolean isDma() {
+            return dmaDestination;
+        }
+
+        public boolean isValid() {
+            return valid;
+        }
+    }
+
     class CdcTransfer {
-        public int destination; //n3
+        public CdcTransferDestination destination; //n3
         public int address; //n19
 
         public int source; //n16

src/main/java/mcd/cdc/CdcTransferHelper.java

@@ -45,8 +45,9 @@ public void start() {
         if (t.enable == 0) return;
         t.active = 1;
         t.busy = 1;
+        assert t.destination.isValid() : t.destination;
         //DSR is set when destination is mainCpuRead or subCpuRead
-        t.ready = (t.destination == 2 || t.destination == 3) ? 1 : 0;
+        t.ready = (t.destination.isDma()) ? 0 : 1;
         t.completed = 0;
         CdcModel.CdcContext ctx = cdc.getContext();
         ctx.irq.transfer.pending = 0;
@@ -69,13 +70,9 @@ public void stop() {
 
     @Override
     public int read() {
-        if (t.destination != 2 && t.destination != 3) {
+        if (t.destination.isDma()) {
             if (t.ready == 0) return 0xFFFF;
         }
-        return readInternal();
-    }
-
-    private int readInternal() {
         int data = ram.getShort(t.source);
         if (verbose) LOG.info("CDC,RAM_R,ram[{}]={}", th(t.source), th(data));
         t.source = (t.source + 2) & 0x3FFF;
@@ -93,23 +90,23 @@ private int readInternal() {
 
     @Override
     public void dma() {
-        if (t.active == 0) {
+        if (t.active == 0 || !t.destination.isDma()) {
             return;
         }
-        if (t.destination != 4 && t.destination != 5 && t.destination != 7) return;
+        assert t.destination.isValid();
         int data = ram.getShort(t.source);
         switch (t.destination) {
-            case 7 -> { //WRAM
+            case DMA_SUB_WRAM_7 -> { //WRAM
                 int baseAddr = memoryContext.wramSetup.mode == MegaCdMemoryContext.WordRamMode._1M
                         ? START_MCD_SUB_WORD_RAM_1M : START_MCD_SUB_WORD_RAM_2M;
                 memoryContext.writeWordRamWord(SUB_M68K, baseAddr | t.address, data);
                 if (verbose) LOG.info("CDC,DMA_WRAM,wram[{}]={}", th(baseAddr | t.address), th(data));
             }
-            case 5 -> {  //PRG-RAM
+            case DMA_PROGRAM_5 -> {  //PRG-RAM
                 memoryContext.writeProgRam(t.address, data, Size.WORD);
                 //mcd.write(1, 1, 0x000000 | (n19) address & ~1, data);
             }
-            case 4 -> {
+            case DMA_PCM_4 -> {
                 assert t.length > 0;
                 //PCM DMA requires two 8-bit writes per transfer
                 writePcm(t.address, data >> 8);

src/main/java/mcd/cdd/CdBiosHelper.java

@@ -263,6 +263,9 @@ public static String getCdBiosEntryPointIfAny(int pc) {
     }
 
     public static void logCdPcInfo(int pc, MC68000 cpu) {
+        if (!enabled) {
+            return;
+        }
         if (pc >= LOW_ENTRY && pc <= HIGH_ENTRY) {
             String res = CdBiosHelper.getCdBiosEntryPointIfAny(pc);
             if (res != CdBiosHelper.NO_ENTRY_POINT) {