TLCS900: reduce usage of preprocessor macros.

felipesanches · felipesanches · commit 3ab74512c44f · 2024-09-10T12:07:24.000-03:00
diff --git a/src/devices/cpu/tlcs900/tlcs900.cpp b/src/devices/cpu/tlcs900/tlcs900.cpp
@@ -70,13 +70,12 @@ std::unique_ptr<util::disasm_interface> tlcs900_device::create_disassembler()
 }
 
 
-/* Flag defines */
-#define FLAG_CF     0x01
-#define FLAG_NF     0x02
-#define FLAG_VF     0x04
-#define FLAG_HF     0x10
-#define FLAG_ZF     0x40
-#define FLAG_SF     0x80
+static constexpr u8 FLAG_CF = 0x01;
+static constexpr u8 FLAG_NF = 0x02;
+static constexpr u8 FLAG_VF = 0x04;
+static constexpr u8 FLAG_HF = 0x10;
+static constexpr u8 FLAG_ZF = 0x40;
+static constexpr u8 FLAG_SF = 0x80;
 
 
 inline uint8_t tlcs900_device::RDOP()
diff --git a/src/devices/cpu/tlcs900/tmp95c061.cpp b/src/devices/cpu/tlcs900/tmp95c061.cpp
@@ -257,50 +257,51 @@ void tmp95c061_device::device_reset()
 	}
 }
 
+enum {
+	INTE0AD,
+	INTE45,
+	INTE67,
+	INTET10,
+	INTET32,
+	INTET54,
+	INTET76,
+	INTES0,
+	INTES1,
+	INTETC10,
+	INTETC32
+};
 
-#define TMP95C061_INTE0AD     0x0
-#define TMP95C061_INTE45      0x1
-#define TMP95C061_INTE67      0x2
-#define TMP95C061_INTET10     0x3
-#define TMP95C061_INTET32     0x4
-#define TMP95C061_INTET54     0x5
-#define TMP95C061_INTET76     0x6
-#define TMP95C061_INTES0      0x7
-#define TMP95C061_INTES1      0x8
-#define TMP95C061_INTETC10    0x9
-#define TMP95C061_INTETC32    0xa
-
-#define TMP95C061_NUM_MASKABLE_IRQS   22
 static const struct {
 	uint8_t reg;
 	uint8_t iff;
 	uint8_t vector;
-} tmp95c061_irq_vector_map[TMP95C061_NUM_MASKABLE_IRQS] =
-{
-	{ TMP95C061_INTETC32, 0x80, 0x80 },   /* INTTC3 */
-	{ TMP95C061_INTETC32, 0x08, 0x7c },   /* INTTC2 */
-	{ TMP95C061_INTETC10, 0x80, 0x78 },   /* INTTC1 */
-	{ TMP95C061_INTETC10, 0x08, 0x74 },   /* INTTC0 */
-	{ TMP95C061_INTE0AD, 0x80, 0x70 },    /* INTAD */
-	{ TMP95C061_INTES1, 0x80, 0x6c },     /* INTTX1 */
-	{ TMP95C061_INTES1, 0x08, 0x68 },     /* INTRX1 */
-	{ TMP95C061_INTES0, 0x80, 0x64 },     /* INTTX0 */
-	{ TMP95C061_INTES0, 0x08, 0x60 },     /* INTRX0 */
-	{ TMP95C061_INTET76, 0x80, 0x5c },    /* INTTR7 */
-	{ TMP95C061_INTET76, 0x08, 0x58 },    /* INTTR6 */
-	{ TMP95C061_INTET54, 0x80, 0x54 },    /* INTTR5 */
-	{ TMP95C061_INTET54, 0x08, 0x50 },    /* INTTR4 */
-	{ TMP95C061_INTET32, 0x80, 0x4c },    /* INTT3 */
-	{ TMP95C061_INTET32, 0x08, 0x48 },    /* INTT2 */
-	{ TMP95C061_INTET10, 0x80, 0x44 },    /* INTT1 */
-	{ TMP95C061_INTET10, 0x08, 0x40 },    /* INTT0 */
+} tmp95c061_irq_vector_map[] =
+{
+	{ INTETC32, 0x80, 0x80 },   /* INTTC3 */
+	{ INTETC32, 0x08, 0x7c },   /* INTTC2 */
+	{ INTETC10, 0x80, 0x78 },   /* INTTC1 */
+	{ INTETC10, 0x08, 0x74 },   /* INTTC0 */
+	{ INTE0AD, 0x80, 0x70 },    /* INTAD */
+	{ INTES1, 0x80, 0x6c },     /* INTTX1 */
+	{ INTES1, 0x08, 0x68 },     /* INTRX1 */
+	{ INTES0, 0x80, 0x64 },     /* INTTX0 */
+	{ INTES0, 0x08, 0x60 },     /* INTRX0 */
+	{ INTET76, 0x80, 0x5c },    /* INTTR7 */
+	{ INTET76, 0x08, 0x58 },    /* INTTR6 */
+	{ INTET54, 0x80, 0x54 },    /* INTTR5 */
+	{ INTET54, 0x08, 0x50 },    /* INTTR4 */
+	{ INTET32, 0x80, 0x4c },    /* INTT3 */
+	{ INTET32, 0x08, 0x48 },    /* INTT2 */
+	{ INTET10, 0x80, 0x44 },    /* INTT1 */
+	{ INTET10, 0x08, 0x40 },    /* INTT0 */
 								/* 0x3c - reserved */
-	{ TMP95C061_INTE67, 0x80, 0x38 },     /* INT7 */
-	{ TMP95C061_INTE67, 0x08, 0x34 },     /* INT6 */
-	{ TMP95C061_INTE45, 0x80, 0x30 },     /* INT5 */
-	{ TMP95C061_INTE45, 0x08, 0x2c },     /* INT4 */
-	{ TMP95C061_INTE0AD, 0x08, 0x28 }     /* INT0 */
+	{ INTE67, 0x80, 0x38 },     /* INT7 */
+	{ INTE67, 0x08, 0x34 },     /* INT6 */
+	{ INTE45, 0x80, 0x30 },     /* INT5 */
+	{ INTE45, 0x08, 0x2c },     /* INT4 */
+	{ INTE0AD, 0x08, 0x28 }     /* INT0 */
 };
+static constexpr u8 NUM_MASKABLE_IRQS = sizeof(tmp95c061_irq_vector_map) / 3;
 
 
 int tmp95c061_device::tlcs900_process_hdma( int channel )
@@ -312,11 +313,11 @@ int tmp95c061_device::tlcs900_process_hdma( int channel )
 	{
 		int irq = 0;
 
-		while( irq < TMP95C061_NUM_MASKABLE_IRQS && tmp95c061_irq_vector_map[irq].vector != vector )
+		while( irq < NUM_MASKABLE_IRQS && tmp95c061_irq_vector_map[irq].vector != vector )
 			irq++;
 
 		/* Check if our interrupt flip-flop is set */
-		if ( irq < TMP95C061_NUM_MASKABLE_IRQS && m_int_reg[tmp95c061_irq_vector_map[irq].reg] & tmp95c061_irq_vector_map[irq].iff )
+		if ( irq < NUM_MASKABLE_IRQS && m_int_reg[tmp95c061_irq_vector_map[irq].reg] & tmp95c061_irq_vector_map[irq].iff )
 		{
 			switch( m_dmam[channel].b.l & 0x1f )
 			{
@@ -406,16 +407,16 @@ int tmp95c061_device::tlcs900_process_hdma( int channel )
 				switch( channel )
 				{
 				case 0:
-					m_int_reg[TMP95C061_INTETC10] |= 0x08;
+					m_int_reg[INTETC10] |= 0x08;
 					break;
 				case 1:
-					m_int_reg[TMP95C061_INTETC10] |= 0x80;
+					m_int_reg[INTETC10] |= 0x80;
 					break;
 				case 2:
-					m_int_reg[TMP95C061_INTETC32] |= 0x08;
+					m_int_reg[INTETC32] |= 0x08;
 					break;
 				case 3:
-					m_int_reg[TMP95C061_INTETC32] |= 0x80;
+					m_int_reg[INTETC32] |= 0x80;
 					break;
 				}
 			}
@@ -475,7 +476,7 @@ void tmp95c061_device::tlcs900_check_irqs()
 	}
 
 	/* Check regular irqs */
-	for( i = 0; i < TMP95C061_NUM_MASKABLE_IRQS; i++ )
+	for( i = 0; i < NUM_MASKABLE_IRQS; i++ )
 	{
 		if ( m_int_reg[tmp95c061_irq_vector_map[i].reg] & tmp95c061_irq_vector_map[i].iff )
 		{
@@ -563,7 +564,7 @@ void tmp95c061_device::tlcs900_handle_ad()
 			m_ad_mode &= ~ 0x40;
 			m_ad_mode |= 0x80;
 
-			m_int_reg[TMP95C061_INTE0AD] |= 0x80;
+			m_int_reg[INTE0AD] |= 0x80;
 			m_check_irqs = 1;
 
 			/* AD repeat mode */
@@ -661,7 +662,7 @@ void tmp95c061_device::tlcs900_handle_timers()
 				if ( ( m_t8_mode[0] & 0xc0 ) != 0x40 )
 				{
 					m_timer[0] = 0;
-					m_int_reg[TMP95C061_INTET10] |= 0x08;
+					m_int_reg[INTET10] |= 0x08;
 				}
 			}
 		}
@@ -691,7 +692,7 @@ void tmp95c061_device::tlcs900_handle_timers()
 			if ( m_timer[1] == m_t8_reg[1] )
 			{
 				m_timer[1] = 0;
-				m_int_reg[TMP95C061_INTET10] |= 0x80;
+				m_int_reg[INTET10] |= 0x80;
 
 				if ( m_t8_invert & 0x02 )
 				{
@@ -738,7 +739,7 @@ void tmp95c061_device::tlcs900_handle_timers()
 				if ( ( m_t8_mode[1] & 0xc0 ) != 0x40 )
 				{
 					m_timer[2] = 0;
-					m_int_reg[TMP95C061_INTET32] |= 0x08;
+					m_int_reg[INTET32] |= 0x08;
 				}
 			}
 		}
@@ -768,7 +769,7 @@ void tmp95c061_device::tlcs900_handle_timers()
 			if ( m_timer[3] == m_t8_reg[3] )
 			{
 				m_timer[3] = 0;
-				m_int_reg[TMP95C061_INTET32] |= 0x80;
+				m_int_reg[INTET32] |= 0x80;
 
 				if ( m_t8_invert & 0x20 )
 				{
@@ -815,16 +816,16 @@ void tmp95c061_device::execute_set_input(int input, int level)
 				{
 					/* Leave HALT state */
 					m_halted = 0;
-					m_int_reg[TMP95C061_INTE0AD] |= 0x08;
+					m_int_reg[INTE0AD] |= 0x08;
 				}
 			}
 			else
 			{
 				/* Level detect */
 				if ( level == ASSERT_LINE )
-					m_int_reg[TMP95C061_INTE0AD] |= 0x08;
+					m_int_reg[INTE0AD] |= 0x08;
 				else
-					m_int_reg[TMP95C061_INTE0AD] &= ~ 0x08;
+					m_int_reg[INTE0AD] &= ~ 0x08;
 			}
 		}
 		m_level[TLCS900_INT0] = level;
@@ -835,7 +836,7 @@ void tmp95c061_device::execute_set_input(int input, int level)
 		{
 			if ( m_level[TLCS900_INT4] == CLEAR_LINE && level == ASSERT_LINE )
 			{
-				m_int_reg[TMP95C061_INTE45] |= 0x08;
+				m_int_reg[INTE45] |= 0x08;
 			}
 		}
 		m_level[TLCS900_INT4] = level;
@@ -846,7 +847,7 @@ void tmp95c061_device::execute_set_input(int input, int level)
 		{
 			if ( m_level[TLCS900_INT5] == CLEAR_LINE && level == ASSERT_LINE )
 			{
-				m_int_reg[TMP95C061_INTE45] |= 0x80;
+				m_int_reg[INTE45] |= 0x80;
 			}
 		}
 		m_level[TLCS900_INT5] = level;
@@ -1262,7 +1263,7 @@ uint8_t tmp95c061_device::sc0buf_r()
 void tmp95c061_device::sc0buf_w(uint8_t data)
 {
 	// Fake finish sending data
-	m_int_reg[TMP95C061_INTES0] |= 0x80;
+	m_int_reg[INTES0] |= 0x80;
 	m_check_irqs = 1;
 }
 
@@ -1307,7 +1308,7 @@ uint8_t tmp95c061_device::sc1buf_r()
 void tmp95c061_device::sc1buf_w(uint8_t data)
 {
 	// Fake finish sending data
-	m_int_reg[TMP95C061_INTES1] |= 0x80;
+	m_int_reg[INTES1] |= 0x80;
 	m_check_irqs = 1;
 }
 
@@ -1364,7 +1365,7 @@ uint8_t tmp95c061_device::adreg_r(offs_t offset)
 		return m_ad_result[offset >> 1] >> 2;
 
 	// Reading data from the upper 8 bits clears INTE0AD IADC
-	m_int_reg[TMP95C061_INTE0AD] &= ~0x80;
+	m_int_reg[INTE0AD] &= ~0x80;
 	return m_ad_result[offset >> 1] << 6 | 0x3f;
 }
 
diff --git a/src/devices/cpu/tlcs900/tmp95c063.cpp b/src/devices/cpu/tlcs900/tmp95c063.cpp

Original file line number	Diff line number	Diff line change
`@@ -257,50 +257,51 @@ void tmp95c061_device::device_reset()`
`257`	`257`	`}`
`258`	`258`	`}`
`259`	`259`
	`260`	`+enum {`
	`261`	`+ INTE0AD,`
	`262`	`+ INTE45,`
	`263`	`+ INTE67,`
	`264`	`+ INTET10,`
	`265`	`+ INTET32,`
	`266`	`+ INTET54,`
	`267`	`+ INTET76,`
	`268`	`+ INTES0,`
	`269`	`+ INTES1,`
	`270`	`+ INTETC10,`
	`271`	`+ INTETC32`
	`272`	`+};`
`260`	`273`
`261`		`-#define TMP95C061_INTE0AD 0x0`
`262`		`-#define TMP95C061_INTE45 0x1`
`263`		`-#define TMP95C061_INTE67 0x2`
`264`		`-#define TMP95C061_INTET10 0x3`
`265`		`-#define TMP95C061_INTET32 0x4`
`266`		`-#define TMP95C061_INTET54 0x5`
`267`		`-#define TMP95C061_INTET76 0x6`
`268`		`-#define TMP95C061_INTES0 0x7`
`269`		`-#define TMP95C061_INTES1 0x8`
`270`		`-#define TMP95C061_INTETC10 0x9`
`271`		`-#define TMP95C061_INTETC32 0xa`
`272`		`-`
`273`		`-#define TMP95C061_NUM_MASKABLE_IRQS 22`
`274`	`274`	`static const struct {`
`275`	`275`	`uint8_t reg;`
`276`	`276`	`uint8_t iff;`
`277`	`277`	`uint8_t vector;`
`278`		`-} tmp95c061_irq_vector_map[TMP95C061_NUM_MASKABLE_IRQS] =`
`279`		`-{`
`280`		`- { TMP95C061_INTETC32, 0x80, 0x80 }, /* INTTC3 */`
`281`		`- { TMP95C061_INTETC32, 0x08, 0x7c }, /* INTTC2 */`
`282`		`- { TMP95C061_INTETC10, 0x80, 0x78 }, /* INTTC1 */`
`283`		`- { TMP95C061_INTETC10, 0x08, 0x74 }, /* INTTC0 */`
`284`		`- { TMP95C061_INTE0AD, 0x80, 0x70 }, /* INTAD */`
`285`		`- { TMP95C061_INTES1, 0x80, 0x6c }, /* INTTX1 */`
`286`		`- { TMP95C061_INTES1, 0x08, 0x68 }, /* INTRX1 */`
`287`		`- { TMP95C061_INTES0, 0x80, 0x64 }, /* INTTX0 */`
`288`		`- { TMP95C061_INTES0, 0x08, 0x60 }, /* INTRX0 */`
`289`		`- { TMP95C061_INTET76, 0x80, 0x5c }, /* INTTR7 */`
`290`		`- { TMP95C061_INTET76, 0x08, 0x58 }, /* INTTR6 */`
`291`		`- { TMP95C061_INTET54, 0x80, 0x54 }, /* INTTR5 */`
`292`		`- { TMP95C061_INTET54, 0x08, 0x50 }, /* INTTR4 */`
`293`		`- { TMP95C061_INTET32, 0x80, 0x4c }, /* INTT3 */`
`294`		`- { TMP95C061_INTET32, 0x08, 0x48 }, /* INTT2 */`
`295`		`- { TMP95C061_INTET10, 0x80, 0x44 }, /* INTT1 */`
`296`		`- { TMP95C061_INTET10, 0x08, 0x40 }, /* INTT0 */`
	`278`	`+} tmp95c061_irq_vector_map[] =`
	`279`	`+{`
	`280`	`+ { INTETC32, 0x80, 0x80 }, /* INTTC3 */`
	`281`	`+ { INTETC32, 0x08, 0x7c }, /* INTTC2 */`
	`282`	`+ { INTETC10, 0x80, 0x78 }, /* INTTC1 */`
	`283`	`+ { INTETC10, 0x08, 0x74 }, /* INTTC0 */`
	`284`	`+ { INTE0AD, 0x80, 0x70 }, /* INTAD */`
	`285`	`+ { INTES1, 0x80, 0x6c }, /* INTTX1 */`
	`286`	`+ { INTES1, 0x08, 0x68 }, /* INTRX1 */`
	`287`	`+ { INTES0, 0x80, 0x64 }, /* INTTX0 */`
	`288`	`+ { INTES0, 0x08, 0x60 }, /* INTRX0 */`
	`289`	`+ { INTET76, 0x80, 0x5c }, /* INTTR7 */`
	`290`	`+ { INTET76, 0x08, 0x58 }, /* INTTR6 */`
	`291`	`+ { INTET54, 0x80, 0x54 }, /* INTTR5 */`
	`292`	`+ { INTET54, 0x08, 0x50 }, /* INTTR4 */`
	`293`	`+ { INTET32, 0x80, 0x4c }, /* INTT3 */`
	`294`	`+ { INTET32, 0x08, 0x48 }, /* INTT2 */`
	`295`	`+ { INTET10, 0x80, 0x44 }, /* INTT1 */`
	`296`	`+ { INTET10, 0x08, 0x40 }, /* INTT0 */`
`297`	`297`	`/* 0x3c - reserved */`
`298`		`- { TMP95C061_INTE67, 0x80, 0x38 }, /* INT7 */`
`299`		`- { TMP95C061_INTE67, 0x08, 0x34 }, /* INT6 */`
`300`		`- { TMP95C061_INTE45, 0x80, 0x30 }, /* INT5 */`
`301`		`- { TMP95C061_INTE45, 0x08, 0x2c }, /* INT4 */`
`302`		`- { TMP95C061_INTE0AD, 0x08, 0x28 } /* INT0 */`
	`298`	`+ { INTE67, 0x80, 0x38 }, /* INT7 */`
	`299`	`+ { INTE67, 0x08, 0x34 }, /* INT6 */`
	`300`	`+ { INTE45, 0x80, 0x30 }, /* INT5 */`
	`301`	`+ { INTE45, 0x08, 0x2c }, /* INT4 */`
	`302`	`+ { INTE0AD, 0x08, 0x28 } /* INT0 */`
`303`	`303`	`};`
	`304`	`+static constexpr u8 NUM_MASKABLE_IRQS = sizeof(tmp95c061_irq_vector_map) / 3;`
`304`	`305`
`305`	`306`
`306`	`307`	`int tmp95c061_device::tlcs900_process_hdma( int channel )`
`@@ -312,11 +313,11 @@ int tmp95c061_device::tlcs900_process_hdma( int channel )`
`312`	`313`	`{`
`313`	`314`	`int irq = 0;`
`314`	`315`
`315`		`- while( irq < TMP95C061_NUM_MASKABLE_IRQS && tmp95c061_irq_vector_map[irq].vector != vector )`
	`316`	`+ while( irq < NUM_MASKABLE_IRQS && tmp95c061_irq_vector_map[irq].vector != vector )`
`316`	`317`	`irq++;`
`317`	`318`
`318`	`319`	`/* Check if our interrupt flip-flop is set */`
`319`		`- if ( irq < TMP95C061_NUM_MASKABLE_IRQS && m_int_reg[tmp95c061_irq_vector_map[irq].reg] & tmp95c061_irq_vector_map[irq].iff )`
	`320`	`+ if ( irq < NUM_MASKABLE_IRQS && m_int_reg[tmp95c061_irq_vector_map[irq].reg] & tmp95c061_irq_vector_map[irq].iff )`
`320`	`321`	`{`
`321`	`322`	`switch( m_dmam[channel].b.l & 0x1f )`
`322`	`323`	`{`
`@@ -406,16 +407,16 @@ int tmp95c061_device::tlcs900_process_hdma( int channel )`
`406`	`407`	`switch( channel )`
`407`	`408`	`{`
`408`	`409`	`case 0:`
`409`		`- m_int_reg[TMP95C061_INTETC10] \|= 0x08;`
	`410`	`+ m_int_reg[INTETC10] \|= 0x08;`
`410`	`411`	`break;`
`411`	`412`	`case 1:`
`412`		`- m_int_reg[TMP95C061_INTETC10] \|= 0x80;`
	`413`	`+ m_int_reg[INTETC10] \|= 0x80;`
`413`	`414`	`break;`
`414`	`415`	`case 2:`
`415`		`- m_int_reg[TMP95C061_INTETC32] \|= 0x08;`
	`416`	`+ m_int_reg[INTETC32] \|= 0x08;`
`416`	`417`	`break;`
`417`	`418`	`case 3:`
`418`		`- m_int_reg[TMP95C061_INTETC32] \|= 0x80;`
	`419`	`+ m_int_reg[INTETC32] \|= 0x80;`
`419`	`420`	`break;`
`420`	`421`	`}`
`421`	`422`	`}`
`@@ -475,7 +476,7 @@ void tmp95c061_device::tlcs900_check_irqs()`
`475`	`476`	`}`
`476`	`477`
`477`	`478`	`/* Check regular irqs */`
`478`		`- for( i = 0; i < TMP95C061_NUM_MASKABLE_IRQS; i++ )`
	`479`	`+ for( i = 0; i < NUM_MASKABLE_IRQS; i++ )`
`479`	`480`	`{`
`480`	`481`	`if ( m_int_reg[tmp95c061_irq_vector_map[i].reg] & tmp95c061_irq_vector_map[i].iff )`
`481`	`482`	`{`
`@@ -563,7 +564,7 @@ void tmp95c061_device::tlcs900_handle_ad()`
`563`	`564`	`m_ad_mode &= ~ 0x40;`
`564`	`565`	`m_ad_mode \|= 0x80;`
`565`	`566`
`566`		`- m_int_reg[TMP95C061_INTE0AD] \|= 0x80;`
	`567`	`+ m_int_reg[INTE0AD] \|= 0x80;`
`567`	`568`	`m_check_irqs = 1;`
`568`	`569`
`569`	`570`	`/* AD repeat mode */`
`@@ -661,7 +662,7 @@ void tmp95c061_device::tlcs900_handle_timers()`
`661`	`662`	`if ( ( m_t8_mode[0] & 0xc0 ) != 0x40 )`
`662`	`663`	`{`
`663`	`664`	`m_timer[0] = 0;`
`664`		`- m_int_reg[TMP95C061_INTET10] \|= 0x08;`
	`665`	`+ m_int_reg[INTET10] \|= 0x08;`
`665`	`666`	`}`
`666`	`667`	`}`
`667`	`668`	`}`
`@@ -691,7 +692,7 @@ void tmp95c061_device::tlcs900_handle_timers()`
`691`	`692`	`if ( m_timer[1] == m_t8_reg[1] )`
`692`	`693`	`{`
`693`	`694`	`m_timer[1] = 0;`
`694`		`- m_int_reg[TMP95C061_INTET10] \|= 0x80;`
	`695`	`+ m_int_reg[INTET10] \|= 0x80;`
`695`	`696`
`696`	`697`	`if ( m_t8_invert & 0x02 )`
`697`	`698`	`{`
`@@ -738,7 +739,7 @@ void tmp95c061_device::tlcs900_handle_timers()`
`738`	`739`	`if ( ( m_t8_mode[1] & 0xc0 ) != 0x40 )`
`739`	`740`	`{`
`740`	`741`	`m_timer[2] = 0;`
`741`		`- m_int_reg[TMP95C061_INTET32] \|= 0x08;`
	`742`	`+ m_int_reg[INTET32] \|= 0x08;`
`742`	`743`	`}`
`743`	`744`	`}`
`744`	`745`	`}`
`@@ -768,7 +769,7 @@ void tmp95c061_device::tlcs900_handle_timers()`
`768`	`769`	`if ( m_timer[3] == m_t8_reg[3] )`
`769`	`770`	`{`
`770`	`771`	`m_timer[3] = 0;`
`771`		`- m_int_reg[TMP95C061_INTET32] \|= 0x80;`
	`772`	`+ m_int_reg[INTET32] \|= 0x80;`
`772`	`773`
`773`	`774`	`if ( m_t8_invert & 0x20 )`
`774`	`775`	`{`
`@@ -815,16 +816,16 @@ void tmp95c061_device::execute_set_input(int input, int level)`
`815`	`816`	`{`
`816`	`817`	`/* Leave HALT state */`
`817`	`818`	`m_halted = 0;`
`818`		`- m_int_reg[TMP95C061_INTE0AD] \|= 0x08;`
	`819`	`+ m_int_reg[INTE0AD] \|= 0x08;`
`819`	`820`	`}`
`820`	`821`	`}`
`821`	`822`	`else`
`822`	`823`	`{`
`823`	`824`	`/* Level detect */`
`824`	`825`	`if ( level == ASSERT_LINE )`
`825`		`- m_int_reg[TMP95C061_INTE0AD] \|= 0x08;`
	`826`	`+ m_int_reg[INTE0AD] \|= 0x08;`
`826`	`827`	`else`
`827`		`- m_int_reg[TMP95C061_INTE0AD] &= ~ 0x08;`
	`828`	`+ m_int_reg[INTE0AD] &= ~ 0x08;`
`828`	`829`	`}`
`829`	`830`	`}`
`830`	`831`	`m_level[TLCS900_INT0] = level;`
`@@ -835,7 +836,7 @@ void tmp95c061_device::execute_set_input(int input, int level)`
`835`	`836`	`{`
`836`	`837`	`if ( m_level[TLCS900_INT4] == CLEAR_LINE && level == ASSERT_LINE )`
`837`	`838`	`{`
`838`		`- m_int_reg[TMP95C061_INTE45] \|= 0x08;`
	`839`	`+ m_int_reg[INTE45] \|= 0x08;`
`839`	`840`	`}`
`840`	`841`	`}`
`841`	`842`	`m_level[TLCS900_INT4] = level;`
`@@ -846,7 +847,7 @@ void tmp95c061_device::execute_set_input(int input, int level)`
`846`	`847`	`{`
`847`	`848`	`if ( m_level[TLCS900_INT5] == CLEAR_LINE && level == ASSERT_LINE )`
`848`	`849`	`{`
`849`		`- m_int_reg[TMP95C061_INTE45] \|= 0x80;`
	`850`	`+ m_int_reg[INTE45] \|= 0x80;`
`850`	`851`	`}`
`851`	`852`	`}`
`852`	`853`	`m_level[TLCS900_INT5] = level;`
`@@ -1262,7 +1263,7 @@ uint8_t tmp95c061_device::sc0buf_r()`
`1262`	`1263`	`void tmp95c061_device::sc0buf_w(uint8_t data)`
`1263`	`1264`	`{`
`1264`	`1265`	`// Fake finish sending data`
`1265`		`- m_int_reg[TMP95C061_INTES0] \|= 0x80;`
	`1266`	`+ m_int_reg[INTES0] \|= 0x80;`
`1266`	`1267`	`m_check_irqs = 1;`
`1267`	`1268`	`}`
`1268`	`1269`
`@@ -1307,7 +1308,7 @@ uint8_t tmp95c061_device::sc1buf_r()`
`1307`	`1308`	`void tmp95c061_device::sc1buf_w(uint8_t data)`
`1308`	`1309`	`{`
`1309`	`1310`	`// Fake finish sending data`
`1310`		`- m_int_reg[TMP95C061_INTES1] \|= 0x80;`
	`1311`	`+ m_int_reg[INTES1] \|= 0x80;`
`1311`	`1312`	`m_check_irqs = 1;`
`1312`	`1313`	`}`
`1313`	`1314`
`@@ -1364,7 +1365,7 @@ uint8_t tmp95c061_device::adreg_r(offs_t offset)`
`1364`	`1365`	`return m_ad_result[offset >> 1] >> 2;`
`1365`	`1366`
`1366`	`1367`	`// Reading data from the upper 8 bits clears INTE0AD IADC`
`1367`		`- m_int_reg[TMP95C061_INTE0AD] &= ~0x80;`
	`1368`	`+ m_int_reg[INTE0AD] &= ~0x80;`
`1368`	`1369`	`return m_ad_result[offset >> 1] << 6 \| 0x3f;`
`1369`	`1370`	`}`
`1370`	`1371`