Update multi-file generation option

Added --generate-components-library command line option to enable the generation of a library for standard Bambu RTL components separated from the generated top function RTL description

Author: Ansaya

src/BambuParameter.cpp

@@ -226,6 +226,7 @@
 #define OPT_SHARED_INPUT_REGISTERS (1 + OPT_NANOXPLORE_BYPASS)
 #define OPT_INLINE_FUNCTIONS (1 + OPT_SHARED_INPUT_REGISTERS)
 #define OPT_AXI_BURST_TYPE (1 + OPT_INLINE_FUNCTIONS)
+#define OPT_GENERATE_COMPONENTS_LIBRARY (1 + OPT_AXI_BURST_TYPE)
 
 /// constant correspond to the "parametric list based option"
 #define PAR_LIST_BASED_OPT "parametric-list-based"
@@ -876,6 +877,8 @@ void BambuParameter::PrintHelp(std::ostream& os) const
       << std::endl;
    // options defining where backend tools could be found
    os << "  Backend configuration:\n\n"
+      << "    --generate-components-library\n"
+      << "        Export standard Bambu RTL components as a separate library"
       << "    --mentor-visualizer\n"
       << "        Simulate the RTL implementation and then open Mentor Visualizer.\n"
       << "        (Mentor root has to be correctly set, see --mentor-root)\n\n"
@@ -1095,6 +1098,7 @@ int BambuParameter::Exec()
       {"verilator-parallel", optional_argument, nullptr, OPT_VERILATOR_PARALLEL},
       {"shared-input-registers", no_argument, nullptr, OPT_SHARED_INPUT_REGISTERS},
       {"inline-fname", required_argument, nullptr, OPT_INLINE_FUNCTIONS},
+      {"generate-components-library", no_argument, nullptr, OPT_GENERATE_COMPONENTS_LIBRARY},
       GCC_LONG_OPTIONS,
       {nullptr, 0, nullptr, 0}
    };
@@ -2124,6 +2128,11 @@ int BambuParameter::Exec()
             setOption(OPT_inline_functions, std::string(optarg));
             break;
          }
+         case OPT_GENERATE_COMPONENTS_LIBRARY:
+         {
+            setOption(OPT_generate_components_library, true);
+            break;
+         }
          case 0:
          {
             if(strcmp(long_options[option_index].name, "module-binding") == 0)
@@ -3736,6 +3745,7 @@ void BambuParameter::SetDefaults()
    setOption(OPT_evaluation_mode, Evaluation_Mode::NONE);
    setOption(OPT_evaluation_objectives, "");
 
+   setOption(OPT_generate_components_library, false);
    setOption(OPT_altera_root, "/opt/altera" STR_CST_string_separator "/opt/intelFPGA");
    setOption(OPT_lattice_root, "/opt/diamond" STR_CST_string_separator "/usr/local/diamond");
    setOption(OPT_mentor_root, "/opt/mentor");

src/HLS/backend/generate_hdl.cpp

@@ -116,6 +116,7 @@ DesignFlowStep_Status generate_hdl::Exec()
       top_circuits.push_back(HLSMgr->get_HLS(top_fnode->index)->top->get_circ());
    }
 
-   HM.hdl_gen(file_name, top_circuits, HLSMgr->hdl_files, HLSMgr->aux_files, false);
+   const auto generate_bambu_lib = parameters->getOption<bool>(OPT_generate_components_library);
+   HM.hdl_gen(file_name, top_circuits, HLSMgr->hdl_files, HLSMgr->aux_files, !generate_bambu_lib);
    return DesignFlowStep_Status::SUCCESS;
 }

src/Parameter.hpp

@@ -102,7 +102,7 @@ class xml_element;
        mentor_root)(mentor_modelsim_bin)(mentor_optimizer)(verilator)(verilator_timescale_override)(                   \
        verilator_parallel)(altera_root)(quartus_settings)(quartus_13_settings)(quartus_13_64bit)(nanoxplore_root)(     \
        nanoxplore_settings)(nanoxplore_bypass)(shared_input_registers)(inline_functions)(function_constraints)(        \
-       resource_constraints)(axi_burst_type)
+       resource_constraints)(axi_burst_type)(generate_components_library)
 
 #define FRAMEWORK_OPTIONS                                                                                            \
    (benchmark_name)(cat_args)(find_max_transformations)(max_transformations)(compatible_compilers)(compute_size_of)( \

src/design_flows/backend/ToHDL/HDL_manager.cpp

@@ -54,6 +54,7 @@
 #include "fileIO.hpp"
 #include "generic_device.hpp"
 #include "hls_manager.hpp"
+#include "library_manager.hpp"
 #include "string_manipulation.hpp"
 #include "structural_manager.hpp"
 #include "structural_objects.hpp"
@@ -218,10 +219,9 @@ std::string HDL_manager::write_components(const std::string& filename, HDLWriter
 }
 
 void HDL_manager::write_components(const std::string& filename, const std::list<structural_objectRef>& components,
-                                   std::list<std::string>& hdl_files, std::list<std::string>& aux_files, bool tb)
+                                   std::list<std::string>& hdl_files, std::list<std::string>& aux_files,
+                                   bool unique_out)
 {
-   bool multiFileP =
-       !tb && parameters->IsParameter("enable-multifiles") && parameters->GetParameter<bool>("enable-multifiles");
    /// default language
    auto language = parameters->getOption<HDLWriter_Language>(OPT_writer_language);
 
@@ -246,122 +246,81 @@ void HDL_manager::write_components(const std::string& filename, const std::list<
    }
 
    /// determine the proper language for each component
-   std::map<HDLWriter_Language, std::list<structural_objectRef>> component_language;
+   std::map<HDLWriter_Language, std::list<structural_objectRef>> hdl_comp, aux_comp;
    for(const auto& component : components)
    {
-      auto* mod = GetPointer<module>(component);
+      const auto mod = GetPointer<module>(component);
       THROW_ASSERT(mod, "Expected a component object");
+      const auto n_elements = mod->get_internal_objects_size();
+      const auto np = mod->get_NP_functionality();
 
-      unsigned int n_elements = mod->get_internal_objects_size();
-
-      const NP_functionalityRef np = mod->get_NP_functionality();
-
-      if(n_elements || (np && (np->exist_NP_functionality(type) ||
-                               (language == HDLWriter_Language::VERILOG &&
-                                np->exist_NP_functionality(NP_functionality::VERILOG_FILE_PROVIDED)) ||
-                               (language == HDLWriter_Language::VHDL &&
-                                np->exist_NP_functionality(NP_functionality::VHDL_PROVIDED)))))
-      {
-         component_language[language].push_back(component);
-      }
-      else
+      HDLWriter_Language comp_language = language;
+      if(!n_elements && np)
       {
-         if(np and
-            (np->exist_NP_functionality(NP_functionality::FSM) or np->exist_NP_functionality(NP_functionality::FSM_CS)))
+         const auto has_verilog = np->exist_NP_functionality(NP_functionality::VERILOG_PROVIDED) ||
+                                  np->exist_NP_functionality(NP_functionality::VERILOG_FILE_PROVIDED);
+         const auto has_vhdl = np->exist_NP_functionality(NP_functionality::VHDL_PROVIDED) ||
+                               np->exist_NP_functionality(NP_functionality::FLOPOCO_PROVIDED) ||
+                               np->exist_NP_functionality(NP_functionality::VHDL_FILE_PROVIDED);
+         if(np->exist_NP_functionality(type) || (language == HDLWriter_Language::VERILOG && has_verilog) ||
+            (language == HDLWriter_Language::VHDL && has_vhdl) || np->exist_NP_functionality(NP_functionality::FSM) ||
+            np->exist_NP_functionality(NP_functionality::FSM_CS))
          {
-            component_language[language].push_back(component);
+            comp_language = language;
          }
-         else if(np && (np->exist_NP_functionality(NP_functionality::VERILOG_PROVIDED) ||
-                        np->exist_NP_functionality(NP_functionality::VERILOG_FILE_PROVIDED)))
+         else if(has_verilog)
          {
-            if(!parameters->getOption<bool>(OPT_mixed_design))
-            {
-               THROW_ERROR("VHDL implementation of " + component->get_path() + " is not available");
-            }
-            component_language[HDLWriter_Language::VERILOG].push_back(component);
+            comp_language = HDLWriter_Language::VERILOG;
          }
-         else if(np && (np->exist_NP_functionality(NP_functionality::VHDL_PROVIDED) ||
-                        np->exist_NP_functionality(NP_functionality::FLOPOCO_PROVIDED) ||
-                        np->exist_NP_functionality(NP_functionality::VHDL_FILE_PROVIDED)))
+         else if(has_vhdl)
          {
-            if(!parameters->getOption<bool>(OPT_mixed_design))
-            {
-               THROW_ERROR("Verilog implementation of " + component->get_path() + " is not available");
-            }
-            else
-            {
-               THROW_WARNING(component->get_path() + " is available only in VHDL");
-            }
-            component_language[HDLWriter_Language::VHDL].push_back(component);
+            comp_language = HDLWriter_Language::VHDL;
          }
-         else if(np && np->exist_NP_functionality(NP_functionality::SYSTEM_VERILOG_PROVIDED))
+         else if(np->exist_NP_functionality(NP_functionality::SYSTEM_VERILOG_PROVIDED))
          {
-            component_language[HDLWriter_Language::SYSTEM_VERILOG].push_back(component);
+            comp_language = HDLWriter_Language::SYSTEM_VERILOG;
          }
          else
          {
             THROW_ERROR("Language not supported! Module " + mod->get_path());
          }
       }
-   }
-
-   /// generate the auxiliary files
-   for(auto l = component_language.begin(); l != component_language.end(); ++l)
-   {
-      if(language == l->first)
+      const auto library = TM->get_library(component->get_typeRef()->id_type);
+      if(unique_out || library.empty() || !starts_with(library, "STD"))
       {
-         continue;
-      }
-      if(multiFileP)
-      {
-         language_writerRef writer = language_writer::create_writer(l->first, TM, parameters);
-         for(const auto& c : component_language[l->first])
-         {
-            std::list<structural_objectRef> singletonList;
-            singletonList.push_back(c);
-            std::string mod_name = convert_to_identifier(writer.get(), GET_TYPE_NAME(c));
-            std::string generated_filename = write_components(mod_name, l->first, singletonList, aux_files);
-            aux_files.push_back(generated_filename);
-         }
+         hdl_comp[comp_language].push_back(component);
       }
       else
       {
-         std::string generated_filename = write_components(filename, l->first, component_language[l->first], aux_files);
-         aux_files.push_back(generated_filename);
+         aux_comp[comp_language].push_back(component);
       }
    }
 
-   if(multiFileP)
+   for(auto& [lang, comps] : aux_comp)
    {
-      language_writerRef writer = language_writer::create_writer(language, TM, parameters);
-
-      auto counter = component_language[language].size();
-      for(const auto& c : component_language[language])
+      auto writer = language_writer::create_writer(lang, TM, parameters);
+      auto lib_dir = "bambu_lib/" + writer->get_name() + "/";
+      std::filesystem::create_directories(lib_dir);
+      for(auto& comp : comps)
       {
-         --counter;
-         std::list<structural_objectRef> singletonList;
-         singletonList.push_back(c);
-         std::string mod_name = convert_to_identifier(writer.get(), GET_TYPE_NAME(c));
-         if(counter == 0)
-         {
-            mod_name = filename;
-         }
-         std::string generated_filename = write_components(mod_name, language, singletonList, aux_files);
-         if(counter == 0)
-         {
-            hdl_files.push_back(generated_filename);
-         }
-         else
-         {
-            aux_files.push_back(generated_filename);
-         }
+         auto mod_name = lib_dir + convert_to_identifier(writer.get(), GET_TYPE_NAME(comp));
+         auto generated_filename = write_components(mod_name, lang, {comp}, aux_files);
+         aux_files.push_back(generated_filename);
       }
    }
-   else
+
+   for(auto& [lang, comps] : hdl_comp)
    {
-      std::string complete_filename = write_components(filename, language, component_language[language], aux_files);
-      /// add the generated file to the global list
-      hdl_files.push_back(complete_filename);
+      auto writer = language_writer::create_writer(lang, TM, parameters);
+      auto generated_filename = write_components(filename, lang, comps, aux_files);
+      if(lang == language)
+      {
+         hdl_files.push_back(generated_filename);
+      }
+      else
+      {
+         aux_files.push_back(generated_filename);
+      }
    }
 
 #if HAVE_FLOPOCO
@@ -375,7 +334,7 @@ void HDL_manager::write_components(const std::string& filename, const std::list<
 }
 
 void HDL_manager::hdl_gen(const std::string& filename, const std::list<structural_objectRef>& cirs,
-                          std::list<std::string>& hdl_files, std::list<std::string>& aux_files, bool tb)
+                          std::list<std::string>& hdl_files, std::list<std::string>& aux_files, bool unique_out)
 {
    PRINT_DBG_MEX(DEBUG_LEVEL_VERY_PEDANTIC, debug_level,
                  "  compute the list of components for which a structural description exists");
@@ -398,7 +357,7 @@ void HDL_manager::hdl_gen(const std::string& filename, const std::list<structura
    }
 
    /// generate the HDL descriptions for all the components
-   write_components(filename, list_of_com, hdl_files, aux_files, tb);
+   write_components(filename, list_of_com, hdl_files, aux_files, unique_out);
 }
 
 /**

src/design_flows/backend/ToHDL/HDL_manager.hpp

@@ -122,7 +122,7 @@ class HDL_manager
     * Determines the proper language for each component and generates the corresponding HDL descriptions
     */
    void write_components(const std::string& filename, const std::list<structural_objectRef>& components,
-                         std::list<std::string>& hdl_files, std::list<std::string>& aux_files, bool tb);
+                         std::list<std::string>& hdl_files, std::list<std::string>& aux_files, bool unique_out);
 
    /**
     * Writes the module description.
@@ -201,9 +201,10 @@ class HDL_manager
     * @param cirs are the structural objects representing the components to be generated
     * @param the created files (file_name + other files)
     * @param the created aux files
+    * @param single_file generate a unique output file with all components
     */
    void hdl_gen(const std::string& filename, const std::list<structural_objectRef>& cirs,
-                std::list<std::string>& hdl_files, std::list<std::string>& aux_files, bool tb);
+                std::list<std::string>& hdl_files, std::list<std::string>& aux_files, bool unique_out = false);
 
    /**
     * Converts a generic string to a language compliant identifier

src/technology/RTL_characterization.cpp

@@ -1160,7 +1160,7 @@ void RTLCharacterization::AnalyzeCell(functional_unit* fu, const unsigned int pr
       std::list<std::string> hdl_files, aux_files;
       std::list<structural_objectRef> circuits;
       circuits.push_back(circuit);
-      HDL->hdl_gen(fu_name, circuits, hdl_files, aux_files, false);
+      HDL->hdl_gen(fu_name, circuits, hdl_files, aux_files);
       int PipelineDepth = -1;
 #if HAVE_FLOPOCO
       if(n_pipe_parameters > 0 && NPF && NPF->exist_NP_functionality(NP_functionality::FLOPOCO_PROVIDED) &&

src/technology/parse_technology.cpp

@@ -71,7 +71,7 @@ void read_technology_File(const std::string& fn, const technology_managerRef& TM
          }
          for(const auto& library : TM->get_library_list())
          {
-            if(WORK_LIBRARY == library || DESIGN == library || PROXY_LIBRARY == library)
+            if(WORK_LIBRARY == library || PROXY_LIBRARY == library)
             {
                continue;
             }

src/technology/technology_manager.cpp

@@ -201,12 +201,7 @@ void technology_manager::add(const technology_nodeRef curr, const std::string& L
    auto it = std::find(libraries.begin(), libraries.end(), Library);
    if(it == libraries.end())
    {
-      bool std = true;
-      if(Library == CG_LIBRARY || Library == DESIGN)
-      {
-         std = false;
-      }
-      library_managerRef lib(new library_manager(Library, Param, std));
+      library_managerRef lib(new library_manager(Library, Param, true));
       library_map[Library] = lib;
       libraries.push_back(Library);
    }

src/technology/technology_manager.hpp

@@ -41,10 +41,6 @@
  */
 #ifndef TECHNOLOGY_MANAGER_HPP
 #define TECHNOLOGY_MANAGER_HPP
-
-/// Autoheader include
-#include "config_HAVE_CIRCUIT_BUILT.hpp"
-
 #include "custom_map.hpp"
 #include "custom_set.hpp"
 #include "refcount.hpp"
@@ -54,8 +50,8 @@
 #include <string>
 #include <vector>
 
-/// working library.
-#define DESIGN std::string("design")
+#include "config_HAVE_CIRCUIT_BUILT.hpp"
+
 /// working library.
 #define WORK_LIBRARY std::string("work")
 /// OpenMP library
@@ -68,8 +64,6 @@
 #define LIBRARY_STD std::string("STD")
 /// standard library where all standard HLS resources are defined
 #define LIBRARY_STD_FU std::string("STD_FU")
-/// compound gates
-#define CG_LIBRARY std::string("CG")
 /// standard library for parallel controller
 #define LIBRARY_PC std::string("STD_PC")
 /// standard library for dataflow interface modules