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emsx_top.map.rpt
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emsx_top.map.rpt
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Analysis & Synthesis report for emsx_top
Thu Apr 18 20:44:14 2024
Quartus II Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. Analysis & Synthesis RAM Summary
9. Analysis & Synthesis IP Cores Summary
10. State Machine - |emsx_top|wifi:uwifi|my_cmd_state
11. State Machine - |emsx_top|wifi:uwifi|my_rx_state
12. State Machine - |emsx_top|wifi:uwifi|my_tx_state
13. State Machine - |emsx_top|wifi:uwifi|UART:U1|tx_current_state_s
14. State Machine - |emsx_top|wifi:uwifi|UART:U1|rx_current_state_s
15. State Machine - |emsx_top|VDP:U20|VDP_COMMAND:U_VDP_COMMAND|STATE
16. State Machine - |emsx_top|VDP:U20|VDP_SPRITE:U_SPRITE|SPSTATE
17. State Machine - |emsx_top|VDP:U20|VDP_NTSC_PAL:U_VDP_NTSC_PAL|FF_SSTATE
18. State Machine - |emsx_top|eseps2:U06|ff_matupd_state
19. State Machine - |emsx_top|eseps2:U06|ff_ps2_state
20. Registers Removed During Synthesis
21. Removed Registers Triggering Further Register Optimizations
22. General Register Statistics
23. Inverted Register Statistics
24. Registers Packed Into Inferred Megafunctions
25. Registers Added for RAM Pass-Through Logic
26. Multiplexer Restructuring Statistics (Restructuring Performed)
27. Source assignments for VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_RO|altsyncram:IMEM_rtl_0|altsyncram_u241:auto_generated
28. Source assignments for VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_RE|altsyncram:IMEM_rtl_0|altsyncram_u241:auto_generated
29. Source assignments for VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_GO|altsyncram:IMEM_rtl_0|altsyncram_u241:auto_generated
30. Source assignments for VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_GE|altsyncram:IMEM_rtl_0|altsyncram_u241:auto_generated
31. Source assignments for VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BO|altsyncram:IMEM_rtl_0|altsyncram_u241:auto_generated
32. Source assignments for VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BE|altsyncram:IMEM_rtl_0|altsyncram_u241:auto_generated
33. Source assignments for rtc:U07|ram:u_mem|altsyncram:blkram_rtl_0|altsyncram_2041:auto_generated
34. Source assignments for VDP:U20|VDP_REGISTER:U_VDP_REGISTER|ram:U_PALETTEMEMRB|altsyncram:blkram_rtl_0|altsyncram_vv31:auto_generated
35. Source assignments for VDP:U20|VDP_REGISTER:U_VDP_REGISTER|ram:U_PALETTEMEMG|altsyncram:blkram_rtl_0|altsyncram_sv31:auto_generated
36. Source assignments for T80a:U01|T80:u0|T80_Reg:Regs|altsyncram:RegsL_rtl_0|altsyncram_iag1:auto_generated
37. Source assignments for T80a:U01|T80:u0|T80_Reg:Regs|altsyncram:RegsH_rtl_0|altsyncram_iag1:auto_generated
38. Source assignments for eseps2:U06|ram:u_matrix_ram|altsyncram:blkram_rtl_0|altsyncram_1041:auto_generated
39. Source assignments for esepwm:U33|esefir5:U1|tapram:u0|altsyncram:TapMem_rtl_0|altsyncram_6dg1:auto_generated
40. Source assignments for VDP:U20|VDP_SPRITE:U_SPRITE|ram:U_EVEN_LINE_BUF|altsyncram:blkram_rtl_0|altsyncram_r141:auto_generated
41. Source assignments for VDP:U20|VDP_SPRITE:U_SPRITE|ram:U_ODD_LINE_BUF|altsyncram:blkram_rtl_0|altsyncram_r141:auto_generated
42. Source assignments for VDP:U20|VDP_SPRITE:U_SPRITE|VDP_SPINFORAM:ISPINFORAM|altsyncram:IMEM_rtl_0|altsyncram_tv31:auto_generated
43. Source assignments for wifi:uwifi|FIFO:U2|altsyncram:memory_rtl_0|altsyncram_mmg1:auto_generated
44. Source assignments for VDP:U20|VDP_GRAPHIC4567:U_VDP_GRAPHIC4567|ram:U_FIFOMEM|altsyncram:blkram_rtl_0|altsyncram_r141:auto_generated
45. Source assignments for eseps2:U06|keymap:u_keymap|altsyncram:Mux7_rtl_0|altsyncram_9mv:auto_generated
46. Source assignments for iplrom:U02|altsyncram:WideOr0_rtl_0|altsyncram_4iv:auto_generated
47. Source assignments for VENCODE:U21|altsyncram:Mux3_rtl_0|altsyncram_agv:auto_generated
48. Parameter Settings for User Entity Instance: Top-level Entity: |emsx_top
49. Parameter Settings for User Entity Instance: PLL4X:U00|altpll:altpll_component
50. Parameter Settings for User Entity Instance: T80a:U01
51. Parameter Settings for User Entity Instance: T80a:U01|T80:u0
52. Parameter Settings for User Entity Instance: T80a:U01|T80:u0|T80_MCode:mcode
53. Parameter Settings for User Entity Instance: T80a:U01|T80:u0|T80_ALU:alu
54. Parameter Settings for User Entity Instance: eseps2:U06
55. Parameter Settings for User Entity Instance: INTERPO:u_interpo
56. Parameter Settings for User Entity Instance: INTERPO:u_interpo|INTERPO_MUL:U_INTERPO_MUL
57. Parameter Settings for User Entity Instance: LPF2:u_lpf2
58. Parameter Settings for User Entity Instance: esepwm:U33
59. Parameter Settings for User Entity Instance: esepwm:U33|esefir5:U1
60. Parameter Settings for User Entity Instance: esepwm:U33|esefir5:U1|tapram:u0
61. Parameter Settings for User Entity Instance: wifi:uwifi|FIFO:U2
62. Parameter Settings for Inferred Entity Instance: VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_RO|altsyncram:IMEM_rtl_0
63. Parameter Settings for Inferred Entity Instance: VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_RE|altsyncram:IMEM_rtl_0
64. Parameter Settings for Inferred Entity Instance: VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_GO|altsyncram:IMEM_rtl_0
65. Parameter Settings for Inferred Entity Instance: VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_GE|altsyncram:IMEM_rtl_0
66. Parameter Settings for Inferred Entity Instance: VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BO|altsyncram:IMEM_rtl_0
67. Parameter Settings for Inferred Entity Instance: VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BE|altsyncram:IMEM_rtl_0
68. Parameter Settings for Inferred Entity Instance: rtc:U07|ram:u_mem|altsyncram:blkram_rtl_0
69. Parameter Settings for Inferred Entity Instance: VDP:U20|VDP_REGISTER:U_VDP_REGISTER|ram:U_PALETTEMEMRB|altsyncram:blkram_rtl_0
70. Parameter Settings for Inferred Entity Instance: VDP:U20|VDP_REGISTER:U_VDP_REGISTER|ram:U_PALETTEMEMG|altsyncram:blkram_rtl_0
71. Parameter Settings for Inferred Entity Instance: T80a:U01|T80:u0|T80_Reg:Regs|altsyncram:RegsL_rtl_0
72. Parameter Settings for Inferred Entity Instance: T80a:U01|T80:u0|T80_Reg:Regs|altsyncram:RegsH_rtl_0
73. Parameter Settings for Inferred Entity Instance: eseps2:U06|ram:u_matrix_ram|altsyncram:blkram_rtl_0
74. Parameter Settings for Inferred Entity Instance: esepwm:U33|esefir5:U1|tapram:u0|altsyncram:TapMem_rtl_0
75. Parameter Settings for Inferred Entity Instance: VDP:U20|VDP_SPRITE:U_SPRITE|ram:U_EVEN_LINE_BUF|altsyncram:blkram_rtl_0
76. Parameter Settings for Inferred Entity Instance: VDP:U20|VDP_SPRITE:U_SPRITE|ram:U_ODD_LINE_BUF|altsyncram:blkram_rtl_0
77. Parameter Settings for Inferred Entity Instance: VDP:U20|VDP_SPRITE:U_SPRITE|VDP_SPINFORAM:ISPINFORAM|altsyncram:IMEM_rtl_0
78. Parameter Settings for Inferred Entity Instance: wifi:uwifi|FIFO:U2|altsyncram:memory_rtl_0
79. Parameter Settings for Inferred Entity Instance: VDP:U20|VDP_GRAPHIC4567:U_VDP_GRAPHIC4567|ram:U_FIFOMEM|altsyncram:blkram_rtl_0
80. Parameter Settings for Inferred Entity Instance: eseps2:U06|keymap:u_keymap|altsyncram:Mux7_rtl_0
81. Parameter Settings for Inferred Entity Instance: iplrom:U02|altsyncram:WideOr0_rtl_0
82. Parameter Settings for Inferred Entity Instance: VENCODE:U21|altsyncram:Mux3_rtl_0
83. Parameter Settings for Inferred Entity Instance: VENCODE:U21|lpm_mult:Mult3
84. Parameter Settings for Inferred Entity Instance: VENCODE:U21|lpm_mult:Mult2
85. Parameter Settings for Inferred Entity Instance: VENCODE:U21|lpm_mult:Mult1
86. Parameter Settings for Inferred Entity Instance: VENCODE:U21|lpm_mult:Mult0
87. Parameter Settings for Inferred Entity Instance: esepwm:U33|esefir5:U1|lpm_mult:Mult0
88. Parameter Settings for Inferred Entity Instance: INTERPO:u_interpo|INTERPO_MUL:U_INTERPO_MUL|lpm_mult:Mult0
89. Parameter Settings for Inferred Entity Instance: lpm_mult:Mult1
90. Parameter Settings for Inferred Entity Instance: lpm_mult:Mult2
91. Parameter Settings for Inferred Entity Instance: lpm_mult:Mult0
92. altpll Parameter Settings by Entity Instance
93. altsyncram Parameter Settings by Entity Instance
94. lpm_mult Parameter Settings by Entity Instance
95. Port Connectivity Checks: "wifi:uwifi|UART:U1"
96. Port Connectivity Checks: "tr_pcm:U40"
97. Port Connectivity Checks: "switched_io_ports:U35"
98. Port Connectivity Checks: "megaram:U31_2"
99. Port Connectivity Checks: "megaram:U31_1"
100. Port Connectivity Checks: "psg:U30"
101. Port Connectivity Checks: "VDP:U20|VDP_REGISTER:U_VDP_REGISTER|ram:U_PALETTEMEMG"
102. Port Connectivity Checks: "VDP:U20|VDP_REGISTER:U_VDP_REGISTER|ram:U_PALETTEMEMRB"
103. Port Connectivity Checks: "VDP:U20|VDP_SPRITE:U_SPRITE|VDP_SPINFORAM:ISPINFORAM"
104. Port Connectivity Checks: "VDP:U20|VDP_SSG:U_SSG"
105. Port Connectivity Checks: "VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF"
106. Port Connectivity Checks: "VDP:U20"
107. Port Connectivity Checks: "rtc:U07|ram:u_mem"
108. Port Connectivity Checks: "rtc:U07"
109. Port Connectivity Checks: "eseps2:U06|ram:u_matrix_ram"
110. Port Connectivity Checks: "eseps2:U06"
111. Port Connectivity Checks: "mapper:U05"
112. Port Connectivity Checks: "megasd:U03"
113. Port Connectivity Checks: "T80a:U01|T80:u0"
114. Port Connectivity Checks: "T80a:U01"
115. Port Connectivity Checks: "scc_mix_mul:u_mul"
116. Elapsed Time Per Partition
117. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2011 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Apr 18 20:44:14 2024 ;
; Quartus II Version ; 11.0 Build 208 07/03/2011 SP 1 SJ Web Edition ;
; Revision Name ; emsx_top ;
; Top-level Entity Name ; emsx_top ;
; Family ; Cyclone ;
; Total logic elements ; 10,550 ;
; Total pins ; 171 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 63,566 ;
; Total PLLs ; 1 ;
+-----------------------------+-----------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device ; EP1C12Q240C8 ; ;
; Top-level entity name ; emsx_top ; emsx_top ;
; Family name ; Cyclone ; Cyclone IV GX ;
; Maximum processors allowed for parallel compilation ; All ; ;
; Preserve fewer node names ; Off ; On ;
; Power-Up Don't Care ; Off ; On ;
; Ignore LCELL Buffers ; On ; Off ;
; Optimization Technique ; Area ; Balanced ;
; Force Use of Synchronous Clear Signals ; On ; Off ;
; Auto Resource Sharing ; On ; Off ;
; Allow Any RAM Size For Recognition ; On ; Off ;
; Allow Any ROM Size For Recognition ; On ; Off ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Parallel Synthesis ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Auto RAM Block Balancing ; On ; On ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Report Parameter Settings ; On ; On ;
; Report Source Assignments ; On ; On ;
; Report Connectivity Checks ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Block Design Naming ; Auto ; Auto ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Resource Aware Inference For Block RAM ; On ; On ;
; Synthesis Seed ; 2 ; 2 ;
+----------------------------------------------------------------------------+--------------------+--------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 16 ;
; Maximum allowed ; 16 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; ; ;
; Usage by Processor ; % Time Used ;
; 1 processor ; 100.0% ;
; 2-16 processors ; 0.0% ;
+----------------------------+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------+------------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------+------------------------------------------------------------------------------------------+
; src/video/vdp.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/video/vdp.vhd ;
; src/video/vdp_colordec.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/video/vdp_colordec.vhd ;
; src/video/vdp_command.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/video/vdp_command.vhd ;
; src/video/vdp_doublebuf.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/video/vdp_doublebuf.vhd ;
; src/video/vdp_graphic123m.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/video/vdp_graphic123m.vhd ;
; src/video/vdp_graphic4567.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/video/vdp_graphic4567.vhd ;
; src/video/vdp_hvcounter.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/video/vdp_hvcounter.vhd ;
; src/video/vdp_interrupt.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/video/vdp_interrupt.vhd ;
; src/video/vdp_linebuf.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/video/vdp_linebuf.vhd ;
; src/video/vdp_ntsc_pal.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/video/vdp_ntsc_pal.vhd ;
; src/video/vdp_package.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/video/vdp_package.vhd ;
; src/video/vdp_register.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/video/vdp_register.vhd ;
; src/video/vdp_spinforam.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/video/vdp_spinforam.vhd ;
; src/video/vdp_sprite.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/video/vdp_sprite.vhd ;
; src/video/vdp_ssg.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/video/vdp_ssg.vhd ;
; src/video/vdp_text12.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/video/vdp_text12.vhd ;
; src/video/vdp_vga.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/video/vdp_vga.vhd ;
; src/video/vdp_wait_control.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/video/vdp_wait_control.vhd ;
; src/video/vencode.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/video/vencode.vhd ;
; src/sound/tr_pcm/tr_pcm.v ; yes ; User Verilog HDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/sound/tr_pcm/tr_pcm.v ;
; src/sound/scc/megaram.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/sound/scc/megaram.vhd ;
; src/sound/scc/scc_wave.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/sound/scc/scc_wave.vhd ;
; src/sound/psg/psg.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/sound/psg/psg.vhd ;
; src/sound/psg/psg_wave.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/sound/psg/psg_wave.vhd ;
; src/sound/lpf/lpf.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/sound/lpf/lpf.vhd ;
; src/sound/filter/esefir5.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/sound/filter/esefir5.vhd ;
; src/sound/filter/tapram.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/sound/filter/tapram.vhd ;
; src/sound/dac/esepwm.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/sound/dac/esepwm.vhd ;
; src/peripheral/fifo.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/peripheral/fifo.vhd ;
; src/peripheral/keymap.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/peripheral/keymap.vhd ;
; src/peripheral/mapper.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/peripheral/mapper.vhd ;
; src/peripheral/midi.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/peripheral/midi.vhd ;
; src/peripheral/ram.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/peripheral/ram.vhd ;
; src/peripheral/swioports.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/peripheral/swioports.vhd ;
; src/peripheral/UART.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/peripheral/UART.vhd ;
; src/peripheral/wifi_lite.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/peripheral/wifi_lite.vhd ;
; src/sys/pll4x.vhd ; yes ; User Wizard-Generated File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/sys/pll4x.vhd ;
; src/cpu/T80.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/cpu/T80.vhd ;
; src/cpu/T80_ALU.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/cpu/T80_ALU.vhd ;
; src/cpu/T80_MCode.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/cpu/T80_MCode.vhd ;
; src/cpu/T80_Pack.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/cpu/T80_Pack.vhd ;
; src/cpu/T80_Reg.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/cpu/T80_Reg.vhd ;
; src/cpu/T80a.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/cpu/T80a.vhd ;
; src/emsx_top.vhd ; yes ; User VHDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/emsx_top.vhd ;
; src/peripheral/eseps2.v ; yes ; User Verilog HDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/peripheral/eseps2.v ;
; src/peripheral/iplrom_304k.v ; yes ; User Verilog HDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/peripheral/iplrom_304k.v ;
; src/peripheral/megasd.v ; yes ; User Verilog HDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/peripheral/megasd.v ;
; src/peripheral/rtc.v ; yes ; User Verilog HDL File ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/peripheral/rtc.v ;
; altpll.tdf ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/altpll.tdf ;
; aglobal110.inc ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/aglobal110.inc ;
; stratix_pll.inc ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/stratix_pll.inc ;
; stratixii_pll.inc ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/stratixii_pll.inc ;
; cycloneii_pll.inc ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/cycloneii_pll.inc ;
; altsyncram.tdf ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/altsyncram.tdf ;
; stratix_ram_block.inc ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/stratix_ram_block.inc ;
; lpm_mux.inc ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/lpm_mux.inc ;
; lpm_decode.inc ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/lpm_decode.inc ;
; a_rdenreg.inc ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/a_rdenreg.inc ;
; altrom.inc ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/altrom.inc ;
; altram.inc ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/altram.inc ;
; altdpram.inc ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/altdpram.inc ;
; db/altsyncram_u241.tdf ; yes ; Auto-Generated Megafunction ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/db/altsyncram_u241.tdf ;
; db/altsyncram_2041.tdf ; yes ; Auto-Generated Megafunction ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/db/altsyncram_2041.tdf ;
; db/altsyncram_vv31.tdf ; yes ; Auto-Generated Megafunction ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/db/altsyncram_vv31.tdf ;
; db/altsyncram_sv31.tdf ; yes ; Auto-Generated Megafunction ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/db/altsyncram_sv31.tdf ;
; db/altsyncram_iag1.tdf ; yes ; Auto-Generated Megafunction ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/db/altsyncram_iag1.tdf ;
; db/altsyncram_1041.tdf ; yes ; Auto-Generated Megafunction ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/db/altsyncram_1041.tdf ;
; db/altsyncram_6dg1.tdf ; yes ; Auto-Generated Megafunction ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/db/altsyncram_6dg1.tdf ;
; db/altsyncram_r141.tdf ; yes ; Auto-Generated Megafunction ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/db/altsyncram_r141.tdf ;
; db/altsyncram_tv31.tdf ; yes ; Auto-Generated Megafunction ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/db/altsyncram_tv31.tdf ;
; db/altsyncram_mmg1.tdf ; yes ; Auto-Generated Megafunction ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/db/altsyncram_mmg1.tdf ;
; db/altsyncram_9mv.tdf ; yes ; Auto-Generated Megafunction ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/db/altsyncram_9mv.tdf ;
; db/altsyncram_4iv.tdf ; yes ; Auto-Generated Megafunction ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/db/altsyncram_4iv.tdf ;
; db/altsyncram_agv.tdf ; yes ; Auto-Generated Megafunction ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/db/altsyncram_agv.tdf ;
; lpm_mult.tdf ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf ;
; lpm_add_sub.inc ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/lpm_add_sub.inc ;
; multcore.inc ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/multcore.inc ;
; bypassff.inc ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/bypassff.inc ;
; altshift.inc ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/altshift.inc ;
; multcore.tdf ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/multcore.tdf ;
; csa_add.inc ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/csa_add.inc ;
; mpar_add.inc ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/mpar_add.inc ;
; muleabz.inc ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/muleabz.inc ;
; mul_lfrg.inc ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/mul_lfrg.inc ;
; mul_boothc.inc ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/mul_boothc.inc ;
; alt_ded_mult.inc ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/alt_ded_mult.inc ;
; alt_ded_mult_y.inc ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/alt_ded_mult_y.inc ;
; dffpipe.inc ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/dffpipe.inc ;
; mpar_add.tdf ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/mpar_add.tdf ;
; lpm_add_sub.tdf ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf ;
; addcore.inc ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/addcore.inc ;
; look_add.inc ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/look_add.inc ;
; alt_stratix_add_sub.inc ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/alt_stratix_add_sub.inc ;
; addcore.tdf ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/addcore.tdf ;
; a_csnbuffer.inc ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/a_csnbuffer.inc ;
; a_csnbuffer.tdf ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/a_csnbuffer.tdf ;
; altshift.tdf ; yes ; Megafunction ; c:/altera/11.0sp1/quartus/libraries/megafunctions/altshift.tdf ;
; db/mult_evs.tdf ; yes ; Auto-Generated Megafunction ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/db/mult_evs.tdf ;
; db/mult_gos.tdf ; yes ; Auto-Generated Megafunction ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/db/mult_gos.tdf ;
+----------------------------------+-----------------+------------------------------+------------------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-----------------------------------------+
; Resource ; Usage ;
+---------------------------------------------+-----------------------------------------+
; Total logic elements ; 10550 ;
; -- Combinational with no register ; 7246 ;
; -- Register only ; 1976 ;
; -- Combinational with a register ; 1328 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 4842 ;
; -- 3 input functions ; 2272 ;
; -- 2 input functions ; 1289 ;
; -- 1 input functions ; 166 ;
; -- 0 input functions ; 5 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 9240 ;
; -- arithmetic mode ; 1310 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 821 ;
; -- asynchronous clear/load mode ; 1964 ;
; ; ;
; Total registers ; 3304 ;
; Total logic cells in carry chains ; 1457 ;
; I/O pins ; 171 ;
; Total memory bits ; 63566 ;
; Total PLLs ; 1 ;
; -- PLLs ; 1 ;
; ; ;
; Maximum fan-out node ; PLL4X:U00|altpll:altpll_component|_clk0 ;
; Maximum fan-out ; 3071 ;
; Total fan-out ; 41340 ;
; Average fan-out ; 3.79 ;
+---------------------------------------------+-----------------------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------------------------------+--------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------------------------------+--------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; |emsx_top ; 10550 (1057) ; 3304 ; 63566 ; 171 ; 0 ; 7246 (637) ; 1976 (198) ; 1328 (222) ; 1457 (121) ; 0 (0) ; |emsx_top ; ;
; |INTERPO:u_interpo| ; 152 (93) ; 45 ; 0 ; 0 ; 0 ; 107 (48) ; 28 (28) ; 17 (17) ; 73 (48) ; 0 (0) ; |emsx_top|INTERPO:u_interpo ; ;
; |INTERPO_MUL:U_INTERPO_MUL| ; 59 (0) ; 0 ; 0 ; 0 ; 0 ; 59 (0) ; 0 (0) ; 0 (0) ; 25 (0) ; 0 (0) ; |emsx_top|INTERPO:u_interpo|INTERPO_MUL:U_INTERPO_MUL ; ;
; |lpm_mult:Mult0| ; 59 (0) ; 0 ; 0 ; 0 ; 0 ; 59 (0) ; 0 (0) ; 0 (0) ; 25 (0) ; 0 (0) ; |emsx_top|INTERPO:u_interpo|INTERPO_MUL:U_INTERPO_MUL|lpm_mult:Mult0 ; ;
; |mult_gos:auto_generated| ; 59 (59) ; 0 ; 0 ; 0 ; 0 ; 59 (59) ; 0 (0) ; 0 (0) ; 25 (25) ; 0 (0) ; |emsx_top|INTERPO:u_interpo|INTERPO_MUL:U_INTERPO_MUL|lpm_mult:Mult0|mult_gos:auto_generated ; ;
; |LPF2:u_lpf2| ; 221 (221) ; 126 ; 0 ; 0 ; 0 ; 95 (95) ; 112 (112) ; 14 (14) ; 109 (109) ; 0 (0) ; |emsx_top|LPF2:u_lpf2 ; ;
; |PLL4X:U00| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|PLL4X:U00 ; ;
; |altpll:altpll_component| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|PLL4X:U00|altpll:altpll_component ; ;
; |T80a:U01| ; 2334 (33) ; 381 ; 128 ; 0 ; 0 ; 1953 (16) ; 242 (12) ; 139 (5) ; 138 (0) ; 0 (0) ; |emsx_top|T80a:U01 ; ;
; |T80:u0| ; 2301 (889) ; 364 ; 128 ; 0 ; 0 ; 1937 (677) ; 230 (78) ; 134 (134) ; 138 (103) ; 0 (0) ; |emsx_top|T80a:U01|T80:u0 ; ;
; |T80_ALU:alu| ; 528 (528) ; 0 ; 0 ; 0 ; 0 ; 528 (528) ; 0 (0) ; 0 (0) ; 35 (35) ; 0 (0) ; |emsx_top|T80a:U01|T80:u0|T80_ALU:alu ; ;
; |T80_MCode:mcode| ; 538 (538) ; 0 ; 0 ; 0 ; 0 ; 538 (538) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|T80a:U01|T80:u0|T80_MCode:mcode ; ;
; |T80_Reg:Regs| ; 346 (346) ; 152 ; 128 ; 0 ; 0 ; 194 (194) ; 152 (152) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|T80a:U01|T80:u0|T80_Reg:Regs ; ;
; |altsyncram:RegsH_rtl_0| ; 0 (0) ; 0 ; 64 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|T80a:U01|T80:u0|T80_Reg:Regs|altsyncram:RegsH_rtl_0 ; ;
; |altsyncram_iag1:auto_generated| ; 0 (0) ; 0 ; 64 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|T80a:U01|T80:u0|T80_Reg:Regs|altsyncram:RegsH_rtl_0|altsyncram_iag1:auto_generated ; ;
; |altsyncram:RegsL_rtl_0| ; 0 (0) ; 0 ; 64 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|T80a:U01|T80:u0|T80_Reg:Regs|altsyncram:RegsL_rtl_0 ; ;
; |altsyncram_iag1:auto_generated| ; 0 (0) ; 0 ; 64 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|T80a:U01|T80:u0|T80_Reg:Regs|altsyncram:RegsL_rtl_0|altsyncram_iag1:auto_generated ; ;
; |VDP:U20| ; 3412 (393) ; 1281 ; 25736 ; 0 ; 0 ; 2131 (319) ; 784 (38) ; 497 (36) ; 444 (31) ; 0 (0) ; |emsx_top|VDP:U20 ; ;
; |VDP_COLORDEC:U_VDP_COLORDEC| ; 99 (99) ; 52 ; 0 ; 0 ; 0 ; 47 (47) ; 18 (18) ; 34 (34) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_COLORDEC:U_VDP_COLORDEC ; ;
; |VDP_COMMAND:U_VDP_COMMAND| ; 668 (668) ; 180 ; 0 ; 0 ; 0 ; 488 (488) ; 69 (69) ; 111 (111) ; 92 (92) ; 0 (0) ; |emsx_top|VDP:U20|VDP_COMMAND:U_VDP_COMMAND ; ;
; |VDP_GRAPHIC123M:U_VDP_GRAPHIC123M| ; 97 (97) ; 61 ; 0 ; 0 ; 0 ; 36 (36) ; 32 (32) ; 29 (29) ; 5 (5) ; 0 (0) ; |emsx_top|VDP:U20|VDP_GRAPHIC123M:U_VDP_GRAPHIC123M ; ;
; |VDP_GRAPHIC4567:U_VDP_GRAPHIC4567| ; 295 (295) ; 153 ; 2048 ; 0 ; 0 ; 142 (142) ; 123 (123) ; 30 (30) ; 73 (73) ; 0 (0) ; |emsx_top|VDP:U20|VDP_GRAPHIC4567:U_VDP_GRAPHIC4567 ; ;
; |ram:U_FIFOMEM| ; 0 (0) ; 0 ; 2048 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_GRAPHIC4567:U_VDP_GRAPHIC4567|ram:U_FIFOMEM ; ;
; |altsyncram:blkram_rtl_0| ; 0 (0) ; 0 ; 2048 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_GRAPHIC4567:U_VDP_GRAPHIC4567|ram:U_FIFOMEM|altsyncram:blkram_rtl_0 ; ;
; |altsyncram_r141:auto_generated| ; 0 (0) ; 0 ; 2048 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_GRAPHIC4567:U_VDP_GRAPHIC4567|ram:U_FIFOMEM|altsyncram:blkram_rtl_0|altsyncram_r141:auto_generated ; ;
; |VDP_INTERRUPT:U_INTERRUPT| ; 11 (11) ; 2 ; 0 ; 0 ; 0 ; 9 (9) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_INTERRUPT:U_INTERRUPT ; ;
; |VDP_NTSC_PAL:U_VDP_NTSC_PAL| ; 41 (41) ; 4 ; 0 ; 0 ; 0 ; 37 (37) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_NTSC_PAL:U_VDP_NTSC_PAL ; ;
; |VDP_REGISTER:U_VDP_REGISTER| ; 461 (461) ; 241 ; 144 ; 0 ; 0 ; 220 (220) ; 209 (209) ; 32 (32) ; 10 (10) ; 0 (0) ; |emsx_top|VDP:U20|VDP_REGISTER:U_VDP_REGISTER ; ;
; |ram:U_PALETTEMEMG| ; 0 (0) ; 0 ; 48 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_REGISTER:U_VDP_REGISTER|ram:U_PALETTEMEMG ; ;
; |altsyncram:blkram_rtl_0| ; 0 (0) ; 0 ; 48 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_REGISTER:U_VDP_REGISTER|ram:U_PALETTEMEMG|altsyncram:blkram_rtl_0 ; ;
; |altsyncram_sv31:auto_generated| ; 0 (0) ; 0 ; 48 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_REGISTER:U_VDP_REGISTER|ram:U_PALETTEMEMG|altsyncram:blkram_rtl_0|altsyncram_sv31:auto_generated ; ;
; |ram:U_PALETTEMEMRB| ; 0 (0) ; 0 ; 96 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_REGISTER:U_VDP_REGISTER|ram:U_PALETTEMEMRB ; ;
; |altsyncram:blkram_rtl_0| ; 0 (0) ; 0 ; 96 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_REGISTER:U_VDP_REGISTER|ram:U_PALETTEMEMRB|altsyncram:blkram_rtl_0 ; ;
; |altsyncram_vv31:auto_generated| ; 0 (0) ; 0 ; 96 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_REGISTER:U_VDP_REGISTER|ram:U_PALETTEMEMRB|altsyncram:blkram_rtl_0|altsyncram_vv31:auto_generated ; ;
; |VDP_SPRITE:U_SPRITE| ; 549 (549) ; 281 ; 4344 ; 0 ; 0 ; 268 (268) ; 165 (165) ; 116 (116) ; 59 (59) ; 0 (0) ; |emsx_top|VDP:U20|VDP_SPRITE:U_SPRITE ; ;
; |VDP_SPINFORAM:ISPINFORAM| ; 0 (0) ; 0 ; 248 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_SPRITE:U_SPRITE|VDP_SPINFORAM:ISPINFORAM ; ;
; |altsyncram:IMEM_rtl_0| ; 0 (0) ; 0 ; 248 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_SPRITE:U_SPRITE|VDP_SPINFORAM:ISPINFORAM|altsyncram:IMEM_rtl_0 ; ;
; |altsyncram_tv31:auto_generated| ; 0 (0) ; 0 ; 248 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_SPRITE:U_SPRITE|VDP_SPINFORAM:ISPINFORAM|altsyncram:IMEM_rtl_0|altsyncram_tv31:auto_generated ; ;
; |ram:U_EVEN_LINE_BUF| ; 0 (0) ; 0 ; 2048 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_SPRITE:U_SPRITE|ram:U_EVEN_LINE_BUF ; ;
; |altsyncram:blkram_rtl_0| ; 0 (0) ; 0 ; 2048 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_SPRITE:U_SPRITE|ram:U_EVEN_LINE_BUF|altsyncram:blkram_rtl_0 ; ;
; |altsyncram_r141:auto_generated| ; 0 (0) ; 0 ; 2048 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_SPRITE:U_SPRITE|ram:U_EVEN_LINE_BUF|altsyncram:blkram_rtl_0|altsyncram_r141:auto_generated ; ;
; |ram:U_ODD_LINE_BUF| ; 0 (0) ; 0 ; 2048 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_SPRITE:U_SPRITE|ram:U_ODD_LINE_BUF ; ;
; |altsyncram:blkram_rtl_0| ; 0 (0) ; 0 ; 2048 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_SPRITE:U_SPRITE|ram:U_ODD_LINE_BUF|altsyncram:blkram_rtl_0 ; ;
; |altsyncram_r141:auto_generated| ; 0 (0) ; 0 ; 2048 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_SPRITE:U_SPRITE|ram:U_ODD_LINE_BUF|altsyncram:blkram_rtl_0|altsyncram_r141:auto_generated ; ;
; |VDP_SSG:U_SSG| ; 308 (194) ; 104 ; 0 ; 0 ; 0 ; 204 (127) ; 52 (18) ; 52 (49) ; 115 (66) ; 0 (0) ; |emsx_top|VDP:U20|VDP_SSG:U_SSG ; ;
; |VDP_HVCOUNTER:U_HVCOUNTER| ; 114 (114) ; 37 ; 0 ; 0 ; 0 ; 77 (77) ; 34 (34) ; 3 (3) ; 49 (49) ; 0 (0) ; |emsx_top|VDP:U20|VDP_SSG:U_SSG|VDP_HVCOUNTER:U_HVCOUNTER ; ;
; |VDP_TEXT12:U_VDP_TEXT12| ; 182 (182) ; 95 ; 0 ; 0 ; 0 ; 87 (87) ; 50 (50) ; 45 (45) ; 19 (19) ; 0 (0) ; |emsx_top|VDP:U20|VDP_TEXT12:U_VDP_TEXT12 ; ;
; |VDP_VGA:U_VDP_VGA| ; 120 (100) ; 20 ; 19200 ; 0 ; 0 ; 100 (80) ; 12 (12) ; 8 (8) ; 26 (26) ; 0 (0) ; |emsx_top|VDP:U20|VDP_VGA:U_VDP_VGA ; ;
; |VDP_DOUBLEBUF:DBUF| ; 20 (20) ; 0 ; 19200 ; 0 ; 0 ; 20 (20) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF ; ;
; |VDP_LINEBUF:U_BUF_BE| ; 0 (0) ; 0 ; 3200 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BE ; ;
; |altsyncram:IMEM_rtl_0| ; 0 (0) ; 0 ; 3200 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BE|altsyncram:IMEM_rtl_0 ; ;
; |altsyncram_u241:auto_generated| ; 0 (0) ; 0 ; 3200 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BE|altsyncram:IMEM_rtl_0|altsyncram_u241:auto_generated ; ;
; |VDP_LINEBUF:U_BUF_BO| ; 0 (0) ; 0 ; 3200 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BO ; ;
; |altsyncram:IMEM_rtl_0| ; 0 (0) ; 0 ; 3200 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BO|altsyncram:IMEM_rtl_0 ; ;
; |altsyncram_u241:auto_generated| ; 0 (0) ; 0 ; 3200 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BO|altsyncram:IMEM_rtl_0|altsyncram_u241:auto_generated ; ;
; |VDP_LINEBUF:U_BUF_GE| ; 0 (0) ; 0 ; 3200 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_GE ; ;
; |altsyncram:IMEM_rtl_0| ; 0 (0) ; 0 ; 3200 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_GE|altsyncram:IMEM_rtl_0 ; ;
; |altsyncram_u241:auto_generated| ; 0 (0) ; 0 ; 3200 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_GE|altsyncram:IMEM_rtl_0|altsyncram_u241:auto_generated ; ;
; |VDP_LINEBUF:U_BUF_GO| ; 0 (0) ; 0 ; 3200 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_GO ; ;
; |altsyncram:IMEM_rtl_0| ; 0 (0) ; 0 ; 3200 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_GO|altsyncram:IMEM_rtl_0 ; ;
; |altsyncram_u241:auto_generated| ; 0 (0) ; 0 ; 3200 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_GO|altsyncram:IMEM_rtl_0|altsyncram_u241:auto_generated ; ;
; |VDP_LINEBUF:U_BUF_RE| ; 0 (0) ; 0 ; 3200 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_RE ; ;
; |altsyncram:IMEM_rtl_0| ; 0 (0) ; 0 ; 3200 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_RE|altsyncram:IMEM_rtl_0 ; ;
; |altsyncram_u241:auto_generated| ; 0 (0) ; 0 ; 3200 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_RE|altsyncram:IMEM_rtl_0|altsyncram_u241:auto_generated ; ;
; |VDP_LINEBUF:U_BUF_RO| ; 0 (0) ; 0 ; 3200 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_RO ; ;
; |altsyncram:IMEM_rtl_0| ; 0 (0) ; 0 ; 3200 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_RO|altsyncram:IMEM_rtl_0 ; ;
; |altsyncram_u241:auto_generated| ; 0 (0) ; 0 ; 3200 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_RO|altsyncram:IMEM_rtl_0|altsyncram_u241:auto_generated ; ;
; |VDP_WAIT_CONTROL:U_VDP_WAIT_CONTROL| ; 188 (188) ; 14 ; 0 ; 0 ; 0 ; 174 (174) ; 14 (14) ; 0 (0) ; 14 (14) ; 0 (0) ; |emsx_top|VDP:U20|VDP_WAIT_CONTROL:U_VDP_WAIT_CONTROL ; ;
; |VENCODE:U21| ; 381 (324) ; 72 ; 128 ; 0 ; 0 ; 309 (252) ; 52 (52) ; 20 (20) ; 206 (177) ; 0 (0) ; |emsx_top|VENCODE:U21 ; ;
; |altsyncram:Mux3_rtl_0| ; 0 (0) ; 0 ; 128 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VENCODE:U21|altsyncram:Mux3_rtl_0 ; ;
; |altsyncram_agv:auto_generated| ; 0 (0) ; 0 ; 128 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|VENCODE:U21|altsyncram:Mux3_rtl_0|altsyncram_agv:auto_generated ; ;
; |lpm_mult:Mult0| ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 16 (0) ; 0 (0) ; 0 (0) ; 8 (0) ; 0 (0) ; |emsx_top|VENCODE:U21|lpm_mult:Mult0 ; ;
; |multcore:mult_core| ; 16 (8) ; 0 ; 0 ; 0 ; 0 ; 16 (8) ; 0 (0) ; 0 (0) ; 8 (0) ; 0 (0) ; |emsx_top|VENCODE:U21|lpm_mult:Mult0|multcore:mult_core ; ;
; |mpar_add:padder| ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; 8 (0) ; 0 (0) ; 0 (0) ; 8 (0) ; 0 (0) ; |emsx_top|VENCODE:U21|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder ; ;
; |lpm_add_sub:adder[0]| ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; 8 (0) ; 0 (0) ; 0 (0) ; 8 (0) ; 0 (0) ; |emsx_top|VENCODE:U21|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0] ; ;
; |addcore:adder| ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; 8 (0) ; 0 (0) ; 0 (0) ; 8 (0) ; 0 (0) ; |emsx_top|VENCODE:U21|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder ; ;
; |a_csnbuffer:result_node| ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 8 (8) ; 0 (0) ; 0 (0) ; 8 (8) ; 0 (0) ; |emsx_top|VENCODE:U21|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node ; ;
; |lpm_mult:Mult1| ; 13 (0) ; 0 ; 0 ; 0 ; 0 ; 13 (0) ; 0 (0) ; 0 (0) ; 7 (0) ; 0 (0) ; |emsx_top|VENCODE:U21|lpm_mult:Mult1 ; ;
; |multcore:mult_core| ; 13 (6) ; 0 ; 0 ; 0 ; 0 ; 13 (6) ; 0 (0) ; 0 (0) ; 7 (0) ; 0 (0) ; |emsx_top|VENCODE:U21|lpm_mult:Mult1|multcore:mult_core ; ;
; |mpar_add:padder| ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; 7 (0) ; 0 (0) ; 0 (0) ; 7 (0) ; 0 (0) ; |emsx_top|VENCODE:U21|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder ; ;
; |lpm_add_sub:adder[0]| ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; 7 (0) ; 0 (0) ; 0 (0) ; 7 (0) ; 0 (0) ; |emsx_top|VENCODE:U21|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0] ; ;
; |addcore:adder| ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; 7 (0) ; 0 (0) ; 0 (0) ; 7 (0) ; 0 (0) ; |emsx_top|VENCODE:U21|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder ; ;
; |a_csnbuffer:result_node| ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 7 (7) ; 0 (0) ; |emsx_top|VENCODE:U21|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node ; ;
; |lpm_mult:Mult2| ; 17 (0) ; 0 ; 0 ; 0 ; 0 ; 17 (0) ; 0 (0) ; 0 (0) ; 8 (0) ; 0 (0) ; |emsx_top|VENCODE:U21|lpm_mult:Mult2 ; ;
; |multcore:mult_core| ; 17 (9) ; 0 ; 0 ; 0 ; 0 ; 17 (9) ; 0 (0) ; 0 (0) ; 8 (0) ; 0 (0) ; |emsx_top|VENCODE:U21|lpm_mult:Mult2|multcore:mult_core ; ;
; |mpar_add:padder| ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; 8 (0) ; 0 (0) ; 0 (0) ; 8 (0) ; 0 (0) ; |emsx_top|VENCODE:U21|lpm_mult:Mult2|multcore:mult_core|mpar_add:padder ; ;
; |lpm_add_sub:adder[0]| ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; 8 (0) ; 0 (0) ; 0 (0) ; 8 (0) ; 0 (0) ; |emsx_top|VENCODE:U21|lpm_mult:Mult2|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0] ; ;
; |addcore:adder| ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; 8 (0) ; 0 (0) ; 0 (0) ; 8 (0) ; 0 (0) ; |emsx_top|VENCODE:U21|lpm_mult:Mult2|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder ; ;
; |a_csnbuffer:result_node| ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 8 (8) ; 0 (0) ; 0 (0) ; 8 (8) ; 0 (0) ; |emsx_top|VENCODE:U21|lpm_mult:Mult2|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node ; ;
; |lpm_mult:Mult3| ; 11 (0) ; 0 ; 0 ; 0 ; 0 ; 11 (0) ; 0 (0) ; 0 (0) ; 6 (0) ; 0 (0) ; |emsx_top|VENCODE:U21|lpm_mult:Mult3 ; ;
; |multcore:mult_core| ; 11 (5) ; 0 ; 0 ; 0 ; 0 ; 11 (5) ; 0 (0) ; 0 (0) ; 6 (0) ; 0 (0) ; |emsx_top|VENCODE:U21|lpm_mult:Mult3|multcore:mult_core ; ;
; |mpar_add:padder| ; 6 (0) ; 0 ; 0 ; 0 ; 0 ; 6 (0) ; 0 (0) ; 0 (0) ; 6 (0) ; 0 (0) ; |emsx_top|VENCODE:U21|lpm_mult:Mult3|multcore:mult_core|mpar_add:padder ; ;
; |lpm_add_sub:adder[0]| ; 6 (0) ; 0 ; 0 ; 0 ; 0 ; 6 (0) ; 0 (0) ; 0 (0) ; 6 (0) ; 0 (0) ; |emsx_top|VENCODE:U21|lpm_mult:Mult3|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0] ; ;
; |addcore:adder| ; 6 (0) ; 0 ; 0 ; 0 ; 0 ; 6 (0) ; 0 (0) ; 0 (0) ; 6 (0) ; 0 (0) ; |emsx_top|VENCODE:U21|lpm_mult:Mult3|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder ; ;
; |a_csnbuffer:result_node| ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 0 (0) ; 6 (6) ; 0 (0) ; |emsx_top|VENCODE:U21|lpm_mult:Mult3|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node ; ;
; |eseps2:U06| ; 326 (316) ; 130 ; 16512 ; 0 ; 0 ; 196 (188) ; 58 (58) ; 72 (70) ; 20 (20) ; 0 (0) ; |emsx_top|eseps2:U06 ; ;
; |keymap:u_keymap| ; 10 (10) ; 2 ; 16384 ; 0 ; 0 ; 8 (8) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 (0) ; |emsx_top|eseps2:U06|keymap:u_keymap ; ;
; |altsyncram:Mux7_rtl_0| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|eseps2:U06|keymap:u_keymap|altsyncram:Mux7_rtl_0 ; ;
; |altsyncram_9mv:auto_generated| ; 0 (0) ; 0 ; 16384 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|eseps2:U06|keymap:u_keymap|altsyncram:Mux7_rtl_0|altsyncram_9mv:auto_generated ; ;
; |ram:u_matrix_ram| ; 0 (0) ; 0 ; 128 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|eseps2:U06|ram:u_matrix_ram ; ;
; |altsyncram:blkram_rtl_0| ; 0 (0) ; 0 ; 128 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|eseps2:U06|ram:u_matrix_ram|altsyncram:blkram_rtl_0 ; ;
; |altsyncram_1041:auto_generated| ; 0 (0) ; 0 ; 128 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|eseps2:U06|ram:u_matrix_ram|altsyncram:blkram_rtl_0|altsyncram_1041:auto_generated ; ;
; |esepwm:U33| ; 236 (15) ; 61 ; 70 ; 0 ; 0 ; 175 (0) ; 38 (0) ; 23 (15) ; 96 (15) ; 0 (0) ; |emsx_top|esepwm:U33 ; ;
; |esefir5:U1| ; 221 (92) ; 46 ; 70 ; 0 ; 0 ; 175 (46) ; 38 (38) ; 8 (8) ; 81 (22) ; 0 (0) ; |emsx_top|esepwm:U33|esefir5:U1 ; ;
; |lpm_mult:Mult0| ; 129 (0) ; 0 ; 0 ; 0 ; 0 ; 129 (0) ; 0 (0) ; 0 (0) ; 59 (0) ; 0 (0) ; |emsx_top|esepwm:U33|esefir5:U1|lpm_mult:Mult0 ; ;
; |mult_evs:auto_generated| ; 129 (129) ; 0 ; 0 ; 0 ; 0 ; 129 (129) ; 0 (0) ; 0 (0) ; 59 (59) ; 0 (0) ; |emsx_top|esepwm:U33|esefir5:U1|lpm_mult:Mult0|mult_evs:auto_generated ; ;
; |tapram:u0| ; 0 (0) ; 0 ; 70 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|esepwm:U33|esefir5:U1|tapram:u0 ; ;
; |altsyncram:TapMem_rtl_0| ; 0 (0) ; 0 ; 70 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|esepwm:U33|esefir5:U1|tapram:u0|altsyncram:TapMem_rtl_0 ; ;
; |altsyncram_6dg1:auto_generated| ; 0 (0) ; 0 ; 70 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|esepwm:U33|esefir5:U1|tapram:u0|altsyncram:TapMem_rtl_0|altsyncram_6dg1:auto_generated ; ;
; |iplrom:U02| ; 0 (0) ; 0 ; 4096 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|iplrom:U02 ; ;
; |altsyncram:WideOr0_rtl_0| ; 0 (0) ; 0 ; 4096 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|iplrom:U02|altsyncram:WideOr0_rtl_0 ; ;
; |altsyncram_4iv:auto_generated| ; 0 (0) ; 0 ; 4096 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|iplrom:U02|altsyncram:WideOr0_rtl_0|altsyncram_4iv:auto_generated ; ;
; |lpm_mult:Mult0| ; 46 (0) ; 0 ; 0 ; 0 ; 0 ; 46 (0) ; 0 (0) ; 0 (0) ; 20 (0) ; 0 (0) ; |emsx_top|lpm_mult:Mult0 ; ;
; |multcore:mult_core| ; 46 (26) ; 0 ; 0 ; 0 ; 0 ; 46 (26) ; 0 (0) ; 0 (0) ; 20 (0) ; 0 (0) ; |emsx_top|lpm_mult:Mult0|multcore:mult_core ; ;
; |mpar_add:padder| ; 20 (0) ; 0 ; 0 ; 0 ; 0 ; 20 (0) ; 0 (0) ; 0 (0) ; 20 (0) ; 0 (0) ; |emsx_top|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder ; ;
; |lpm_add_sub:adder[0]| ; 10 (0) ; 0 ; 0 ; 0 ; 0 ; 10 (0) ; 0 (0) ; 0 (0) ; 10 (0) ; 0 (0) ; |emsx_top|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0] ; ;
; |addcore:adder| ; 10 (0) ; 0 ; 0 ; 0 ; 0 ; 10 (0) ; 0 (0) ; 0 (0) ; 10 (0) ; 0 (0) ; |emsx_top|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder ; ;
; |a_csnbuffer:result_node| ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 10 (10) ; 0 (0) ; 0 (0) ; 10 (10) ; 0 (0) ; |emsx_top|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node ; ;
; |mpar_add:sub_par_add| ; 10 (0) ; 0 ; 0 ; 0 ; 0 ; 10 (0) ; 0 (0) ; 0 (0) ; 10 (0) ; 0 (0) ; |emsx_top|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add ; ;
; |lpm_add_sub:adder[0]| ; 10 (0) ; 0 ; 0 ; 0 ; 0 ; 10 (0) ; 0 (0) ; 0 (0) ; 10 (0) ; 0 (0) ; |emsx_top|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0] ; ;
; |addcore:adder| ; 10 (0) ; 0 ; 0 ; 0 ; 0 ; 10 (0) ; 0 (0) ; 0 (0) ; 10 (0) ; 0 (0) ; |emsx_top|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder ; ;
; |a_csnbuffer:result_node| ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 10 (10) ; 0 (0) ; 0 (0) ; 10 (10) ; 0 (0) ; |emsx_top|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node ; ;
; |lpm_mult:Mult1| ; 42 (0) ; 0 ; 0 ; 0 ; 0 ; 42 (0) ; 0 (0) ; 0 (0) ; 18 (0) ; 0 (0) ; |emsx_top|lpm_mult:Mult1 ; ;
; |multcore:mult_core| ; 42 (24) ; 0 ; 0 ; 0 ; 0 ; 42 (24) ; 0 (0) ; 0 (0) ; 18 (0) ; 0 (0) ; |emsx_top|lpm_mult:Mult1|multcore:mult_core ; ;
; |mpar_add:padder| ; 18 (0) ; 0 ; 0 ; 0 ; 0 ; 18 (0) ; 0 (0) ; 0 (0) ; 18 (0) ; 0 (0) ; |emsx_top|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder ; ;
; |lpm_add_sub:adder[0]| ; 9 (0) ; 0 ; 0 ; 0 ; 0 ; 9 (0) ; 0 (0) ; 0 (0) ; 9 (0) ; 0 (0) ; |emsx_top|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0] ; ;
; |addcore:adder| ; 9 (0) ; 0 ; 0 ; 0 ; 0 ; 9 (0) ; 0 (0) ; 0 (0) ; 9 (0) ; 0 (0) ; |emsx_top|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder ; ;
; |a_csnbuffer:result_node| ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 9 (9) ; 0 (0) ; 0 (0) ; 9 (9) ; 0 (0) ; |emsx_top|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node ; ;
; |mpar_add:sub_par_add| ; 9 (0) ; 0 ; 0 ; 0 ; 0 ; 9 (0) ; 0 (0) ; 0 (0) ; 9 (0) ; 0 (0) ; |emsx_top|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add ; ;
; |lpm_add_sub:adder[0]| ; 9 (0) ; 0 ; 0 ; 0 ; 0 ; 9 (0) ; 0 (0) ; 0 (0) ; 9 (0) ; 0 (0) ; |emsx_top|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0] ; ;
; |addcore:adder| ; 9 (0) ; 0 ; 0 ; 0 ; 0 ; 9 (0) ; 0 (0) ; 0 (0) ; 9 (0) ; 0 (0) ; |emsx_top|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder ; ;
; |a_csnbuffer:result_node| ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 9 (9) ; 0 (0) ; 0 (0) ; 9 (9) ; 0 (0) ; |emsx_top|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node ; ;
; |lpm_mult:Mult2| ; 17 (0) ; 0 ; 0 ; 0 ; 0 ; 17 (0) ; 0 (0) ; 0 (0) ; 16 (0) ; 0 (0) ; |emsx_top|lpm_mult:Mult2 ; ;
; |multcore:mult_core| ; 17 (1) ; 0 ; 0 ; 0 ; 0 ; 17 (1) ; 0 (0) ; 0 (0) ; 16 (0) ; 0 (0) ; |emsx_top|lpm_mult:Mult2|multcore:mult_core ; ;
; |mpar_add:padder| ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 16 (0) ; 0 (0) ; 0 (0) ; 16 (0) ; 0 (0) ; |emsx_top|lpm_mult:Mult2|multcore:mult_core|mpar_add:padder ; ;
; |lpm_add_sub:adder[0]| ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; 8 (0) ; 0 (0) ; 0 (0) ; 8 (0) ; 0 (0) ; |emsx_top|lpm_mult:Mult2|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0] ; ;
; |addcore:adder| ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; 8 (0) ; 0 (0) ; 0 (0) ; 8 (0) ; 0 (0) ; |emsx_top|lpm_mult:Mult2|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder ; ;
; |a_csnbuffer:result_node| ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 8 (8) ; 0 (0) ; 0 (0) ; 8 (8) ; 0 (0) ; |emsx_top|lpm_mult:Mult2|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node ; ;
; |mpar_add:sub_par_add| ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; 8 (0) ; 0 (0) ; 0 (0) ; 8 (0) ; 0 (0) ; |emsx_top|lpm_mult:Mult2|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add ; ;
; |lpm_add_sub:adder[0]| ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; 8 (0) ; 0 (0) ; 0 (0) ; 8 (0) ; 0 (0) ; |emsx_top|lpm_mult:Mult2|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0] ; ;
; |addcore:adder| ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; 8 (0) ; 0 (0) ; 0 (0) ; 8 (0) ; 0 (0) ; |emsx_top|lpm_mult:Mult2|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder ; ;
; |a_csnbuffer:result_node| ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 8 (8) ; 0 (0) ; 0 (0) ; 8 (8) ; 0 (0) ; |emsx_top|lpm_mult:Mult2|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node ; ;
; |mapper:U05| ; 61 (61) ; 32 ; 0 ; 0 ; 0 ; 29 (29) ; 32 (32) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|mapper:U05 ; ;
; |megasd:U03| ; 120 (120) ; 74 ; 0 ; 0 ; 0 ; 46 (46) ; 59 (59) ; 15 (15) ; 10 (10) ; 0 (0) ; |emsx_top|megasd:U03 ; ;
; |psg:U30| ; 604 (94) ; 221 ; 0 ; 0 ; 0 ; 383 (71) ; 186 (12) ; 35 (11) ; 77 (0) ; 0 (0) ; |emsx_top|psg:U30 ; ;
; |psg_wave:u_psgch| ; 510 (510) ; 198 ; 0 ; 0 ; 0 ; 312 (312) ; 174 (174) ; 24 (24) ; 77 (77) ; 0 (0) ; |emsx_top|psg:U30|psg_wave:u_psgch ; ;
; |rtc:U07| ; 270 (270) ; 75 ; 256 ; 0 ; 0 ; 195 (195) ; 24 (24) ; 51 (51) ; 0 (0) ; 0 (0) ; |emsx_top|rtc:U07 ; ;
; |ram:u_mem| ; 0 (0) ; 0 ; 256 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|rtc:U07|ram:u_mem ; ;
; |altsyncram:blkram_rtl_0| ; 0 (0) ; 0 ; 256 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|rtc:U07|ram:u_mem|altsyncram:blkram_rtl_0 ; ;
; |altsyncram_2041:auto_generated| ; 0 (0) ; 0 ; 256 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|rtc:U07|ram:u_mem|altsyncram:blkram_rtl_0|altsyncram_2041:auto_generated ; ;
; |switched_io_ports:U35| ; 705 (705) ; 112 ; 0 ; 0 ; 0 ; 593 (593) ; 2 (2) ; 110 (110) ; 0 (0) ; 0 (0) ; |emsx_top|switched_io_ports:U35 ; ;
; |tr_pcm:U40| ; 77 (77) ; 50 ; 0 ; 0 ; 0 ; 27 (27) ; 33 (33) ; 17 (17) ; 8 (8) ; 0 (0) ; |emsx_top|tr_pcm:U40 ; ;
; |wifi:uwifi| ; 489 (115) ; 224 ; 16640 ; 0 ; 0 ; 265 (52) ; 128 (38) ; 96 (25) ; 101 (0) ; 0 (0) ; |emsx_top|wifi:uwifi ; ;
; |FIFO:U2| ; 153 (153) ; 60 ; 16640 ; 0 ; 0 ; 93 (93) ; 50 (50) ; 10 (10) ; 37 (37) ; 0 (0) ; |emsx_top|wifi:uwifi|FIFO:U2 ; ;
; |altsyncram:memory_rtl_0| ; 0 (0) ; 0 ; 16640 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|wifi:uwifi|FIFO:U2|altsyncram:memory_rtl_0 ; ;
; |altsyncram_mmg1:auto_generated| ; 0 (0) ; 0 ; 16640 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |emsx_top|wifi:uwifi|FIFO:U2|altsyncram:memory_rtl_0|altsyncram_mmg1:auto_generated ; ;
; |UART:U1| ; 221 (221) ; 101 ; 0 ; 0 ; 0 ; 120 (120) ; 40 (40) ; 61 (61) ; 64 (64) ; 0 (0) ; |emsx_top|wifi:uwifi|UART:U1 ; ;
+----------------------------------------------------+--------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+-----------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+-----------------------------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+-----------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+-----------------------------+
; T80a:U01|T80:u0|T80_Reg:Regs|altsyncram:RegsH_rtl_0|altsyncram_iag1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 8 ; 8 ; 8 ; 8 ; 64 ; None ;
; T80a:U01|T80:u0|T80_Reg:Regs|altsyncram:RegsL_rtl_0|altsyncram_iag1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 8 ; 8 ; 8 ; 8 ; 64 ; None ;
; VDP:U20|VDP_GRAPHIC4567:U_VDP_GRAPHIC4567|ram:U_FIFOMEM|altsyncram:blkram_rtl_0|altsyncram_r141:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 256 ; 8 ; -- ; -- ; 2048 ; None ;
; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|ram:U_PALETTEMEMG|altsyncram:blkram_rtl_0|altsyncram_sv31:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 16 ; 3 ; -- ; -- ; 48 ; None ;
; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|ram:U_PALETTEMEMRB|altsyncram:blkram_rtl_0|altsyncram_vv31:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 16 ; 6 ; -- ; -- ; 96 ; None ;
; VDP:U20|VDP_SPRITE:U_SPRITE|VDP_SPINFORAM:ISPINFORAM|altsyncram:IMEM_rtl_0|altsyncram_tv31:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 8 ; 31 ; -- ; -- ; 248 ; None ;
; VDP:U20|VDP_SPRITE:U_SPRITE|ram:U_EVEN_LINE_BUF|altsyncram:blkram_rtl_0|altsyncram_r141:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 256 ; 8 ; -- ; -- ; 2048 ; None ;
; VDP:U20|VDP_SPRITE:U_SPRITE|ram:U_ODD_LINE_BUF|altsyncram:blkram_rtl_0|altsyncram_r141:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 256 ; 8 ; -- ; -- ; 2048 ; None ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BE|altsyncram:IMEM_rtl_0|altsyncram_u241:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 640 ; 5 ; -- ; -- ; 3200 ; None ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BO|altsyncram:IMEM_rtl_0|altsyncram_u241:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 640 ; 5 ; -- ; -- ; 3200 ; None ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_GE|altsyncram:IMEM_rtl_0|altsyncram_u241:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 640 ; 5 ; -- ; -- ; 3200 ; None ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_GO|altsyncram:IMEM_rtl_0|altsyncram_u241:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 640 ; 5 ; -- ; -- ; 3200 ; None ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_RE|altsyncram:IMEM_rtl_0|altsyncram_u241:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 640 ; 5 ; -- ; -- ; 3200 ; None ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_RO|altsyncram:IMEM_rtl_0|altsyncram_u241:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 640 ; 5 ; -- ; -- ; 3200 ; None ;
; VENCODE:U21|altsyncram:Mux3_rtl_0|altsyncram_agv:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; 32 ; 4 ; -- ; -- ; 128 ; uMSX_EdFJ.emsx_top2.rtl.mif ;
; eseps2:U06|keymap:u_keymap|altsyncram:Mux7_rtl_0|altsyncram_9mv:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; 1024 ; 16 ; -- ; -- ; 16384 ; uMSX_EdFJ.emsx_top0.rtl.mif ;
; eseps2:U06|ram:u_matrix_ram|altsyncram:blkram_rtl_0|altsyncram_1041:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 16 ; 8 ; -- ; -- ; 128 ; None ;
; esepwm:U33|esefir5:U1|tapram:u0|altsyncram:TapMem_rtl_0|altsyncram_6dg1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 5 ; 14 ; 5 ; 14 ; 70 ; None ;
; iplrom:U02|altsyncram:WideOr0_rtl_0|altsyncram_4iv:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; 512 ; 8 ; -- ; -- ; 4096 ; uMSX_EdFJ.emsx_top1.rtl.mif ;
; rtc:U07|ram:u_mem|altsyncram:blkram_rtl_0|altsyncram_2041:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 64 ; 4 ; -- ; -- ; 256 ; None ;
; wifi:uwifi|FIFO:U2|altsyncram:memory_rtl_0|altsyncram_mmg1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 2080 ; 8 ; 2080 ; 8 ; 16640 ; None ;
+-----------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+-----------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary ;
+--------+--------------+---------+--------------+--------------+---------------------+-----------------------------------------------------------------------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ;
+--------+--------------+---------+--------------+--------------+---------------------+-----------------------------------------------------------------------------+
; Altera ; ALTPLL ; N/A ; N/A ; N/A ; |emsx_top|PLL4X:U00 ; E:/Almacenaje/Mundo MSX/uMSX/Programas FPGA/uMSX_EdFJ_1_0/src/sys/pll4x.vhd ;
+--------+--------------+---------+--------------+--------------+---------------------+-----------------------------------------------------------------------------+
Encoding Type: One-Hot
+---------------------------------------------------------------------------------------------------------------------------+
; State Machine - |emsx_top|wifi:uwifi|my_cmd_state ;
+-------------------------------+-------------------------------+-----------------------------+-----------------------------+
; Name ; my_cmd_state.STATE_CMD_FINISH ; my_cmd_state.STATE_CMD_DATA ; my_cmd_state.STATE_CMD_IDLE ;
+-------------------------------+-------------------------------+-----------------------------+-----------------------------+
; my_cmd_state.STATE_CMD_IDLE ; 0 ; 0 ; 0 ;
; my_cmd_state.STATE_CMD_DATA ; 0 ; 1 ; 1 ;
; my_cmd_state.STATE_CMD_FINISH ; 1 ; 0 ; 1 ;
+-------------------------------+-------------------------------+-----------------------------+-----------------------------+
Encoding Type: One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |emsx_top|wifi:uwifi|my_rx_state ;
+-------------------------------+-----------------------------+-------------------------------+---------------------------+---------------------------+
; Name ; my_rx_state.STATE_RX_FINISH ; my_rx_state.STATE_RX_WAITDATA ; my_rx_state.STATE_RX_DATA ; my_rx_state.STATE_RX_IDLE ;
+-------------------------------+-----------------------------+-------------------------------+---------------------------+---------------------------+
; my_rx_state.STATE_RX_IDLE ; 0 ; 0 ; 0 ; 0 ;
; my_rx_state.STATE_RX_DATA ; 0 ; 0 ; 1 ; 1 ;
; my_rx_state.STATE_RX_WAITDATA ; 0 ; 1 ; 0 ; 1 ;
; my_rx_state.STATE_RX_FINISH ; 1 ; 0 ; 0 ; 1 ;
+-------------------------------+-----------------------------+-------------------------------+---------------------------+---------------------------+
Encoding Type: One-Hot
+-------------------------------------------------------------------------------------------------------------------+
; State Machine - |emsx_top|wifi:uwifi|my_tx_state ;
+-----------------------------+-----------------------------+---------------------------+---------------------------+
; Name ; my_tx_state.STATE_TX_FINISH ; my_tx_state.STATE_TX_DATA ; my_tx_state.STATE_TX_IDLE ;
+-----------------------------+-----------------------------+---------------------------+---------------------------+
; my_tx_state.STATE_TX_IDLE ; 0 ; 0 ; 0 ;
; my_tx_state.STATE_TX_DATA ; 0 ; 1 ; 1 ;
; my_tx_state.STATE_TX_FINISH ; 1 ; 0 ; 1 ;
+-----------------------------+-----------------------------+---------------------------+---------------------------+
Encoding Type: One-Hot
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |emsx_top|wifi:uwifi|UART:U1|tx_current_state_s ;
+------------------------------------+------------------------------------+----------------------------------+----------------------------------+-----------------------------------+----------------------------------+
; Name ; tx_current_state_s.STATE_TX_FINISH ; tx_current_state_s.STATE_TX_STOP ; tx_current_state_s.STATE_TX_DATA ; tx_current_state_s.STATE_TX_START ; tx_current_state_s.STATE_TX_IDLE ;
+------------------------------------+------------------------------------+----------------------------------+----------------------------------+-----------------------------------+----------------------------------+
; tx_current_state_s.STATE_TX_IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ;
; tx_current_state_s.STATE_TX_START ; 0 ; 0 ; 0 ; 1 ; 1 ;
; tx_current_state_s.STATE_TX_DATA ; 0 ; 0 ; 1 ; 0 ; 1 ;
; tx_current_state_s.STATE_TX_STOP ; 0 ; 1 ; 0 ; 0 ; 1 ;
; tx_current_state_s.STATE_TX_FINISH ; 1 ; 0 ; 0 ; 0 ; 1 ;
+------------------------------------+------------------------------------+----------------------------------+----------------------------------+-----------------------------------+----------------------------------+
Encoding Type: One-Hot
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |emsx_top|wifi:uwifi|UART:U1|rx_current_state_s ;
+------------------------------------+------------------------------------+----------------------------------+----------------------------------+-----------------------------------+----------------------------------+
; Name ; rx_current_state_s.STATE_RX_FINISH ; rx_current_state_s.STATE_RX_STOP ; rx_current_state_s.STATE_RX_DATA ; rx_current_state_s.STATE_RX_START ; rx_current_state_s.STATE_RX_IDLE ;
+------------------------------------+------------------------------------+----------------------------------+----------------------------------+-----------------------------------+----------------------------------+
; rx_current_state_s.STATE_RX_IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ;
; rx_current_state_s.STATE_RX_START ; 0 ; 0 ; 0 ; 1 ; 1 ;
; rx_current_state_s.STATE_RX_DATA ; 0 ; 0 ; 1 ; 0 ; 1 ;
; rx_current_state_s.STATE_RX_STOP ; 0 ; 1 ; 0 ; 0 ; 1 ;
; rx_current_state_s.STATE_RX_FINISH ; 1 ; 0 ; 0 ; 0 ; 1 ;
+------------------------------------+------------------------------------+----------------------------------+----------------------------------+-----------------------------------+----------------------------------+
Encoding Type: One-Hot
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |emsx_top|VDP:U20|VDP_COMMAND:U_VDP_COMMAND|STATE ;
+-------------------------+-----------------+---------------------+---------------------+--------------------+--------------------+----------------+-----------------------+-------------------+------------------------+-------------------------+--------------------+----------------+-----------------+---------------+-----------------+--------------+
; Name ; STATE.STEXECEND ; STATE.STSRCHCHKLOOP ; STATE.STLINECHKLOOP ; STATE.STLINENEWPOS ; STATE.STWAITWRVRAM ; STATE.STWRVRAM ; STATE.STWAITPRERDVRAM ; STATE.STPRERDVRAM ; STATE.STSRCHWAITRDVRAM ; STATE.STPOINTWAITRDVRAM ; STATE.STWAITRDVRAM ; STATE.STRDVRAM ; STATE.STWAITCPU ; STATE.STRDCPU ; STATE.STCHKLOOP ; STATE.STIDLE ;
+-------------------------+-----------------+---------------------+---------------------+--------------------+--------------------+----------------+-----------------------+-------------------+------------------------+-------------------------+--------------------+----------------+-----------------+---------------+-----------------+--------------+
; STATE.STIDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; STATE.STCHKLOOP ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ;
; STATE.STRDCPU ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ;
; STATE.STWAITCPU ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ;
; STATE.STRDVRAM ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ;
; STATE.STWAITRDVRAM ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; STATE.STPOINTWAITRDVRAM ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; STATE.STSRCHWAITRDVRAM ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; STATE.STPRERDVRAM ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; STATE.STWAITPRERDVRAM ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; STATE.STWRVRAM ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; STATE.STWAITWRVRAM ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; STATE.STLINENEWPOS ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; STATE.STLINECHKLOOP ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; STATE.STSRCHCHKLOOP ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; STATE.STEXECEND ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
+-------------------------+-----------------+---------------------+---------------------+--------------------+--------------------+----------------+-----------------------+-------------------+------------------------+-------------------------+--------------------+----------------+-----------------+---------------+-----------------+--------------+
Encoding Type: One-Hot
+----------------------------------------------------------------------------------------------------------+
; State Machine - |emsx_top|VDP:U20|VDP_SPRITE:U_SPRITE|SPSTATE ;
+----------------------------+-------------------------+----------------------------+----------------------+
; Name ; SPSTATE.SPSTATE_PREPARE ; SPSTATE.SPSTATE_YTEST_DRAW ; SPSTATE.SPSTATE_IDLE ;
+----------------------------+-------------------------+----------------------------+----------------------+
; SPSTATE.SPSTATE_IDLE ; 0 ; 0 ; 0 ;
; SPSTATE.SPSTATE_YTEST_DRAW ; 0 ; 1 ; 1 ;
; SPSTATE.SPSTATE_PREPARE ; 1 ; 0 ; 1 ;
+----------------------------+-------------------------+----------------------------+----------------------+
Encoding Type: One-Hot
+--------------------------------------------------------------------------------------------------------+
; State Machine - |emsx_top|VDP:U20|VDP_NTSC_PAL:U_VDP_NTSC_PAL|FF_SSTATE ;
+--------------------+--------------------+--------------------+--------------------+--------------------+
; Name ; FF_SSTATE.SSTATE_D ; FF_SSTATE.SSTATE_C ; FF_SSTATE.SSTATE_B ; FF_SSTATE.SSTATE_A ;
+--------------------+--------------------+--------------------+--------------------+--------------------+
; FF_SSTATE.SSTATE_A ; 0 ; 0 ; 0 ; 0 ;
; FF_SSTATE.SSTATE_B ; 0 ; 0 ; 1 ; 1 ;
; FF_SSTATE.SSTATE_C ; 0 ; 1 ; 0 ; 1 ;
; FF_SSTATE.SSTATE_D ; 1 ; 0 ; 0 ; 1 ;
+--------------------+--------------------+--------------------+--------------------+--------------------+
Encoding Type: One-Hot
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |emsx_top|eseps2:U06|ff_matupd_state ;
+--------------------------------------------+-----------------------------------------+--------------------------------------------+--------------------------------------------+----------------------------------------+-----------------------------------------+--------------------------------------------+--------------------------------------------+----------------------------------------+--------------------------------+---------------------------------+
; Name ; ff_matupd_state.MATUPD_ST_MATRIX_WRITE2 ; ff_matupd_state.MATUPD_ST_MATRIX_READ2_RES ; ff_matupd_state.MATUPD_ST_MATRIX_READ2_REQ ; ff_matupd_state.MATUPD_ST_KEYMAP_READ2 ; ff_matupd_state.MATUPD_ST_MATRIX_WRITE1 ; ff_matupd_state.MATUPD_ST_MATRIX_READ1_RES ; ff_matupd_state.MATUPD_ST_MATRIX_READ1_REQ ; ff_matupd_state.MATUPD_ST_KEYMAP_READ1 ; ff_matupd_state.MATUPD_ST_IDLE ; ff_matupd_state.MATUPD_ST_RESET ;
+--------------------------------------------+-----------------------------------------+--------------------------------------------+--------------------------------------------+----------------------------------------+-----------------------------------------+--------------------------------------------+--------------------------------------------+----------------------------------------+--------------------------------+---------------------------------+
; ff_matupd_state.MATUPD_ST_RESET ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; ff_matupd_state.MATUPD_ST_IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ;
; ff_matupd_state.MATUPD_ST_KEYMAP_READ1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ;
; ff_matupd_state.MATUPD_ST_MATRIX_READ1_REQ ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ;
; ff_matupd_state.MATUPD_ST_MATRIX_READ1_RES ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ;
; ff_matupd_state.MATUPD_ST_MATRIX_WRITE1 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; ff_matupd_state.MATUPD_ST_KEYMAP_READ2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; ff_matupd_state.MATUPD_ST_MATRIX_READ2_REQ ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; ff_matupd_state.MATUPD_ST_MATRIX_READ2_RES ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; ff_matupd_state.MATUPD_ST_MATRIX_WRITE2 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
+--------------------------------------------+-----------------------------------------+--------------------------------------------+--------------------------------------------+----------------------------------------+-----------------------------------------+--------------------------------------------+--------------------------------------------+----------------------------------------+--------------------------------+---------------------------------+
Encoding Type: One-Hot
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |emsx_top|eseps2:U06|ff_ps2_state ;
+--------------------------------+------------------------------+--------------------------+------------------------------+-----------------------------+------------------------------+--------------------------------+-----------------------------+-----------------------------+------------------------------+--------------------------------+--------------------------------+------------------------------+-------------------------------+---------------------------+
; Name ; ff_ps2_state.PS2_ST_RCV_SCAN ; ff_ps2_state.PS2_ST_IDLE ; ff_ps2_state.PS2_ST_RCV_ACK4 ; ff_ps2_state.PS2_ST_SND_OPT ; ff_ps2_state.PS2_ST_RCV_ACK3 ; ff_ps2_state.PS2_ST_SND_SETMON ; ff_ps2_state.PS2_ST_RCV_IDH ; ff_ps2_state.PS2_ST_RCV_IDL ; ff_ps2_state.PS2_ST_RCV_ACK2 ; ff_ps2_state.PS2_ST_SND_IDREAD ; ff_ps2_state.PS2_ST_RCV_BATCMP ; ff_ps2_state.PS2_ST_RCV_ACK1 ; ff_ps2_state.PS2_ST_SND_RESET ; ff_ps2_state.PS2_ST_RESET ;
+--------------------------------+------------------------------+--------------------------+------------------------------+-----------------------------+------------------------------+--------------------------------+-----------------------------+-----------------------------+------------------------------+--------------------------------+--------------------------------+------------------------------+-------------------------------+---------------------------+
; ff_ps2_state.PS2_ST_RESET ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; ff_ps2_state.PS2_ST_SND_RESET ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ;
; ff_ps2_state.PS2_ST_RCV_ACK1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ;
; ff_ps2_state.PS2_ST_RCV_BATCMP ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ;
; ff_ps2_state.PS2_ST_SND_IDREAD ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ;
; ff_ps2_state.PS2_ST_RCV_ACK2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; ff_ps2_state.PS2_ST_RCV_IDL ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; ff_ps2_state.PS2_ST_RCV_IDH ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; ff_ps2_state.PS2_ST_SND_SETMON ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; ff_ps2_state.PS2_ST_RCV_ACK3 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; ff_ps2_state.PS2_ST_SND_OPT ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; ff_ps2_state.PS2_ST_RCV_ACK4 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; ff_ps2_state.PS2_ST_IDLE ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; ff_ps2_state.PS2_ST_RCV_SCAN ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
+--------------------------------+------------------------------+--------------------------+------------------------------+-----------------------------+------------------------------+--------------------------------+-----------------------------+-----------------------------+------------------------------+--------------------------------+--------------------------------+------------------------------+-------------------------------+---------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+
; Register name ; Reason for Removal ;
+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+
; Scanlines[0] ; Stuck at GND due to stuck port data_in ;
; ff_psg[0,1,15] ; Stuck at GND due to stuck port data_in ;
; pDac_SR[4]~en ; Stuck at GND due to stuck port data_in ;
; pDac_SR[1]~reg0 ; Stuck at GND due to stuck port data_in ;
; jSltScc1 ; Stuck at GND due to stuck port data_in ;
; jSltScc2 ; Stuck at GND due to stuck port data_in ;
; megaram:U31_2|scc_wave:SccCh|dbi[0..7] ; Lost fanout ;
; megaram:U31_1|scc_wave:SccCh|dbi[0..7] ; Lost fanout ;
; SdrSize[1] ; Stuck at VCC due to stuck port data_in ;
; ff_dip_req[3..6] ; Stuck at GND due to stuck port data_in ;
; psg:U30|joyb[2]~en ; Stuck at GND due to stuck port data_in ;
; psg:U30|joyb[1]~en ; Stuck at GND due to stuck port data_in ;
; psg:U30|joyb[0]~en ; Stuck at GND due to stuck port data_in ;
; psg:U30|joya[5]~reg0 ; Stuck at GND due to stuck port data_in ;
; psg:U30|joya[4]~reg0 ; Stuck at GND due to stuck port data_in ;
; psg:U30|joyb[5]~reg0 ; Stuck at GND due to stuck port data_in ;
; psg:U30|joyb[4]~reg0 ; Stuck at GND due to stuck port data_in ;
; psg:U30|joyb[3]~en ; Stuck at GND due to stuck port data_in ;
; psg:U30|joya[0]~en ; Stuck at GND due to stuck port data_in ;
; psg:U30|joya[1]~en ; Stuck at GND due to stuck port data_in ;
; psg:U30|joya[2]~en ; Stuck at GND due to stuck port data_in ;
; psg:U30|joya[3]~en ; Stuck at GND due to stuck port data_in ;
; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|ram:U_PALETTEMEMG|iadr[4..7] ; Stuck at GND due to stuck port data_in ;
; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|ram:U_PALETTEMEMRB|iadr[4..7] ; Stuck at GND due to stuck port data_in ;
; VDP:U20|VDP_SPRITE:U_SPRITE|FF_Y_TEST_VRAM_ADDR[0,1] ; Stuck at GND due to stuck port data_in ;
; VDP:U20|VDP_VGA:U_VDP_VGA|DISP_START_X[7..31] ; Stuck at GND due to stuck port data_in ;
; rtc:U07|ram:u_mem|iadr[6,7] ; Stuck at GND due to stuck port data_in ;
; eseps2:U06|ff_ps2_clk ; Stuck at GND due to stuck port data_in ;
; eseps2:U06|ram:u_matrix_ram|iadr[4..7] ; Stuck at GND due to stuck port data_in ;
; T80a:U01|T80:u0|OldNMI_n ; Lost fanout ;
; T80a:U01|T80:u0|BusReq_s ; Stuck at GND due to stuck port data_in ;
; T80a:U01|T80:u0|BusAck ; Stuck at GND due to stuck port data_in ;
; switched_io_ports:U35|prev_scan[0,1] ; Lost fanout ;
; megaram:U31_2|SccBank0[7] ; Lost fanout ;
; megaram:U31_2|SccBank2[7] ; Lost fanout ;
; megaram:U31_2|SccModeA[4,6] ; Lost fanout ;
; megaram:U31_1|SccBank0[7] ; Lost fanout ;
; megaram:U31_1|SccBank2[7] ; Lost fanout ;
; megaram:U31_1|SccModeA[4,6] ; Lost fanout ;
; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|PALETTEDATARB_IN[3,7] ; Lost fanout ;
; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|PALETTEDATAG_IN[3..7] ; Lost fanout ;
; VDP:U20|PRAMDBO[0]~en ; Lost fanout ;
; VDP:U20|PRAMDBO[1]~en ; Lost fanout ;
; VDP:U20|PRAMDBO[2]~en ; Lost fanout ;
; VDP:U20|PRAMDBO[3]~en ; Lost fanout ;
; VDP:U20|PRAMDBO[4]~en ; Lost fanout ;
; VDP:U20|PRAMDBO[5]~en ; Lost fanout ;
; VDP:U20|PRAMDBO[6]~en ; Lost fanout ;
; VDP:U20|PRAMDBO[7]~en ; Lost fanout ;
; switched_io_ports:U35|VDP_ID[0,2..4] ; Stuck at GND due to stuck port data_in ;
; VDP:U20|VDP_GRAPHIC4567:U_VDP_GRAPHIC4567|LOCALDOTCOUNTERX[0] ; Stuck at GND due to stuck port data_in ;
; T80a:U01|T80:u0|NMI_s ; Stuck at GND due to stuck port data_in ;
; T80a:U01|T80:u0|NMICycle ; Stuck at GND due to stuck port data_in ;
; wifi:uwifi|out_uart_status[7] ; Merged with wifi:uwifi|out_uart_status[6] ;
; ff_scc[14] ; Merged with ff_scc[15] ;
; ff_tr_pcm[10..14] ; Merged with ff_tr_pcm[15] ;
; ff_tr_pcm[0,1] ; Merged with ff_tr_pcm[2] ;
; megaram:U31_1|SccModeB[4] ; Merged with megaram:U31_2|SccBank2[5] ;
; megaram:U31_2|SccBank2[0,4] ; Merged with megaram:U31_2|SccBank2[5] ;
; megaram:U31_1|SccBank2[0,4,5] ; Merged with megaram:U31_2|SccBank2[5] ;
; megaram:U31_1|SccModeB[5] ; Merged with megaram:U31_2|SccBank2[5] ;
; megaram:U31_1|SccBank3[7] ; Merged with megaram:U31_2|SccBank2[5] ;
; megaram:U31_1|SccBank2[3] ; Merged with megaram:U31_2|SccBank2[5] ;
; megaram:U31_2|SccBank3[7] ; Merged with megaram:U31_2|SccBank2[5] ;
; megaram:U31_1|SccBank2[2] ; Merged with megaram:U31_2|SccBank2[5] ;
; megaram:U31_2|SccBank2[2,3] ; Merged with megaram:U31_2|SccBank2[5] ;
; megaram:U31_1|SccBank2[1] ; Merged with megaram:U31_2|SccBank2[1] ;
; megaram:U31_2|SccModeB[4] ; Merged with megaram:U31_2|SccModeB[5] ;
; VENCODE:U21|FF_TABLEDAT[6,7] ; Merged with VENCODE:U21|FF_TABLEDAT[5] ;
; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|ram:U_PALETTEMEMRB|iadr[0] ; Merged with VDP:U20|VDP_REGISTER:U_VDP_REGISTER|ram:U_PALETTEMEMG|iadr[0] ;
; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|ram:U_PALETTEMEMRB|iadr[1] ; Merged with VDP:U20|VDP_REGISTER:U_VDP_REGISTER|ram:U_PALETTEMEMG|iadr[1] ;
; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|ram:U_PALETTEMEMRB|iadr[2] ; Merged with VDP:U20|VDP_REGISTER:U_VDP_REGISTER|ram:U_PALETTEMEMG|iadr[2] ;
; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|ram:U_PALETTEMEMRB|iadr[3] ; Merged with VDP:U20|VDP_REGISTER:U_VDP_REGISTER|ram:U_PALETTEMEMG|iadr[3] ;
; VDP:U20|VDP_SSG:U_SSG|FF_RIGHT_MASK[4..7] ; Merged with VDP:U20|VDP_SSG:U_SSG|FF_RIGHT_MASK[3] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_RO|IADDRESS[1] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BO|IADDRESS[1] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_GO|IADDRESS[1] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BO|IADDRESS[1] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_RO|IADDRESS[0] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BO|IADDRESS[0] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_GO|IADDRESS[0] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BO|IADDRESS[0] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_RO|IADDRESS[2] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BO|IADDRESS[2] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_GO|IADDRESS[2] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BO|IADDRESS[2] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_RO|IADDRESS[3] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BO|IADDRESS[3] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_GO|IADDRESS[3] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BO|IADDRESS[3] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_RO|IADDRESS[4] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BO|IADDRESS[4] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_GO|IADDRESS[4] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BO|IADDRESS[4] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_RO|IADDRESS[5] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BO|IADDRESS[5] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_GO|IADDRESS[5] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BO|IADDRESS[5] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_RO|IADDRESS[6] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BO|IADDRESS[6] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_GO|IADDRESS[6] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BO|IADDRESS[6] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_RO|IADDRESS[7] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BO|IADDRESS[7] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_GO|IADDRESS[7] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BO|IADDRESS[7] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_RO|IADDRESS[8] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BO|IADDRESS[8] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_GO|IADDRESS[8] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BO|IADDRESS[8] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_RO|IADDRESS[9] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BO|IADDRESS[9] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_GO|IADDRESS[9] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BO|IADDRESS[9] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_RE|IADDRESS[1] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BE|IADDRESS[1] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_GE|IADDRESS[1] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BE|IADDRESS[1] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_RE|IADDRESS[0] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BE|IADDRESS[0] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_GE|IADDRESS[0] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BE|IADDRESS[0] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_RE|IADDRESS[2] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BE|IADDRESS[2] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_GE|IADDRESS[2] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BE|IADDRESS[2] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_RE|IADDRESS[3] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BE|IADDRESS[3] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_GE|IADDRESS[3] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BE|IADDRESS[3] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_RE|IADDRESS[4] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BE|IADDRESS[4] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_GE|IADDRESS[4] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BE|IADDRESS[4] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_RE|IADDRESS[5] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BE|IADDRESS[5] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_GE|IADDRESS[5] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BE|IADDRESS[5] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_RE|IADDRESS[6] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BE|IADDRESS[6] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_GE|IADDRESS[6] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BE|IADDRESS[6] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_RE|IADDRESS[7] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BE|IADDRESS[7] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_GE|IADDRESS[7] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BE|IADDRESS[7] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_RE|IADDRESS[8] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BE|IADDRESS[8] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_GE|IADDRESS[8] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BE|IADDRESS[8] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_RE|IADDRESS[9] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BE|IADDRESS[9] ;
; VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_GE|IADDRESS[9] ; Merged with VDP:U20|VDP_VGA:U_VDP_VGA|VDP_DOUBLEBUF:DBUF|VDP_LINEBUF:U_BUF_BE|IADDRESS[9] ;
; switched_io_ports:U35|OFFSET_Y[6] ; Merged with switched_io_ports:U35|OFFSET_Y[5] ;
; psg:U30|psgregptr[3] ; Merged with psg:U30|psg_wave:u_psgch|PsgRegPtr[3] ;
; psg:U30|psgregptr[2] ; Merged with psg:U30|psg_wave:u_psgch|PsgRegPtr[2] ;
; psg:U30|psgregptr[1] ; Merged with psg:U30|psg_wave:u_psgch|PsgRegPtr[1] ;
; psg:U30|psgregptr[0] ; Merged with psg:U30|psg_wave:u_psgch|PsgRegPtr[0] ;
; VENCODE:U21|FF_VCOUNTER[8] ; Merged with VENCODE:U21|FF_PAL_DET_CNT[8] ;
; VENCODE:U21|FF_VCOUNTER[7] ; Merged with VENCODE:U21|FF_PAL_DET_CNT[7] ;
; VENCODE:U21|FF_VCOUNTER[6] ; Merged with VENCODE:U21|FF_PAL_DET_CNT[6] ;
; VENCODE:U21|FF_VCOUNTER[5] ; Merged with VENCODE:U21|FF_PAL_DET_CNT[5] ;
; VENCODE:U21|FF_VCOUNTER[4] ; Merged with VENCODE:U21|FF_PAL_DET_CNT[4] ;
; VENCODE:U21|FF_VCOUNTER[3] ; Merged with VENCODE:U21|FF_PAL_DET_CNT[3] ;
; VENCODE:U21|FF_VCOUNTER[2] ; Merged with VENCODE:U21|FF_PAL_DET_CNT[2] ;
; VENCODE:U21|FF_VCOUNTER[1] ; Merged with VENCODE:U21|FF_PAL_DET_CNT[1] ;
; VENCODE:U21|FF_VCOUNTER[0] ; Merged with VENCODE:U21|FF_PAL_DET_CNT[0] ;
; VDP:U20|VDP_SSG:U_SSG|PREDOTCOUNTERYPSTART[7,8] ; Merged with VDP:U20|VDP_SSG:U_SSG|PREDOTCOUNTERYPSTART[6] ;
; eseps2:U06|ff_ps2_snd_dat[6,7] ; Merged with eseps2:U06|ff_ps2_snd_dat[5] ;
; megaram:U31_2|SccBank2[5] ; Stuck at GND due to stuck port data_in ;
; megaram:U31_2|SccModeB[5] ; Stuck at GND due to stuck port data_in ;
; megaram:U31_1|flag ; Stuck at GND due to stuck port data_in ;
; megaram:U31_2|flag ; Stuck at GND due to stuck port data_in ;
; megaram:U31_1|scc_wave:SccCh|ff_req_dl ; Stuck at GND due to stuck port data_in ;
; megaram:U31_1|scc_wave:SccCh|reg_freq_ch_a[0..11] ; Stuck at GND due to stuck port clock_enable ;
; megaram:U31_1|scc_wave:SccCh|reg_freq_ch_b[0..11] ; Stuck at GND due to stuck port clock_enable ;
; megaram:U31_1|scc_wave:SccCh|reg_freq_ch_c[0..11] ; Stuck at GND due to stuck port clock_enable ;
; megaram:U31_1|scc_wave:SccCh|reg_freq_ch_d[0..11] ; Stuck at GND due to stuck port clock_enable ;
; megaram:U31_1|scc_wave:SccCh|reg_freq_ch_e[0..11] ; Stuck at GND due to stuck port clock_enable ;
; megaram:U31_1|scc_wave:SccCh|reg_vol_ch_a[0..3] ; Stuck at GND due to stuck port clock_enable ;
; megaram:U31_1|scc_wave:SccCh|reg_vol_ch_b[0..3] ; Stuck at GND due to stuck port clock_enable ;
; megaram:U31_1|scc_wave:SccCh|reg_vol_ch_c[0..3] ; Stuck at GND due to stuck port clock_enable ;
; megaram:U31_1|scc_wave:SccCh|reg_vol_ch_d[0..3] ; Stuck at GND due to stuck port clock_enable ;
; megaram:U31_1|scc_wave:SccCh|reg_vol_ch_e[0..3] ; Stuck at GND due to stuck port clock_enable ;
; megaram:U31_1|scc_wave:SccCh|reg_ch_sel[0..4] ; Stuck at GND due to stuck port clock_enable ;
; megaram:U31_1|scc_wave:SccCh|reg_mode_sel[5] ; Stuck at GND due to stuck port clock_enable ;
; megaram:U31_1|scc_wave:SccCh|ff_wave_ce ; Stuck at GND due to stuck port data_in ;
; megaram:U31_1|scc_wave:SccCh|ff_wave_ce_dl ; Stuck at GND due to stuck port data_in ;
; megaram:U31_2|scc_wave:SccCh|ff_req_dl ; Stuck at GND due to stuck port data_in ;
; megaram:U31_2|scc_wave:SccCh|reg_freq_ch_a[0..11] ; Stuck at GND due to stuck port clock_enable ;
; megaram:U31_2|scc_wave:SccCh|reg_freq_ch_b[0..11] ; Stuck at GND due to stuck port clock_enable ;
; megaram:U31_2|scc_wave:SccCh|reg_freq_ch_c[0..11] ; Stuck at GND due to stuck port clock_enable ;
; megaram:U31_2|scc_wave:SccCh|reg_freq_ch_d[0..11] ; Stuck at GND due to stuck port clock_enable ;
; megaram:U31_2|scc_wave:SccCh|reg_freq_ch_e[0..11] ; Stuck at GND due to stuck port clock_enable ;
; megaram:U31_2|scc_wave:SccCh|reg_vol_ch_a[0..3] ; Stuck at GND due to stuck port clock_enable ;
; megaram:U31_2|scc_wave:SccCh|reg_vol_ch_b[0..3] ; Stuck at GND due to stuck port clock_enable ;
; megaram:U31_2|scc_wave:SccCh|reg_vol_ch_c[0..3] ; Stuck at GND due to stuck port clock_enable ;
; megaram:U31_2|scc_wave:SccCh|reg_vol_ch_d[0..3] ; Stuck at GND due to stuck port clock_enable ;
; megaram:U31_2|scc_wave:SccCh|reg_vol_ch_e[0..3] ; Stuck at GND due to stuck port clock_enable ;
; megaram:U31_2|scc_wave:SccCh|reg_ch_sel[0..4] ; Stuck at GND due to stuck port clock_enable ;
; megaram:U31_2|scc_wave:SccCh|reg_mode_sel[5] ; Stuck at GND due to stuck port clock_enable ;
; megaram:U31_2|scc_wave:SccCh|ff_wave_ce ; Stuck at GND due to stuck port data_in ;
; megaram:U31_2|scc_wave:SccCh|ff_wave_ce_dl ; Stuck at GND due to stuck port data_in ;
; megaram:U31_1|scc_wave:SccCh|ff_wave_dat[0..7] ; Stuck at GND due to stuck port data_in ;
; megaram:U31_2|scc_wave:SccCh|ff_wave_dat[0..7] ; Stuck at GND due to stuck port data_in ;
; megaram:U31_2|WavCpy ; Stuck at GND due to stuck port data_in ;
; megaram:U31_2|scc_wave:SccCh|ff_rst_ch_a ; Stuck at GND due to stuck port data_in ;
; megaram:U31_2|scc_wave:SccCh|ff_rst_ch_b ; Stuck at GND due to stuck port data_in ;
; megaram:U31_2|scc_wave:SccCh|ff_rst_ch_c ; Stuck at GND due to stuck port data_in ;
; megaram:U31_2|scc_wave:SccCh|ff_rst_ch_d ; Stuck at GND due to stuck port data_in ;
; megaram:U31_2|scc_wave:SccCh|ff_rst_ch_e ; Stuck at GND due to stuck port data_in ;
; megaram:U31_1|WavCpy ; Stuck at GND due to stuck port data_in ;
; megaram:U31_1|scc_wave:SccCh|ff_rst_ch_a ; Stuck at GND due to stuck port data_in ;
; megaram:U31_1|scc_wave:SccCh|ff_rst_ch_b ; Stuck at GND due to stuck port data_in ;
; megaram:U31_1|scc_wave:SccCh|ff_rst_ch_c ; Stuck at GND due to stuck port data_in ;
; megaram:U31_1|scc_wave:SccCh|ff_rst_ch_d ; Stuck at GND due to stuck port data_in ;
; megaram:U31_1|scc_wave:SccCh|ff_rst_ch_e ; Stuck at GND due to stuck port data_in ;
; megaram:U31_2|scc_wave:SccCh|ff_cnt_ch_a[0..11] ; Stuck at GND due to stuck port data_in ;
; megaram:U31_2|scc_wave:SccCh|ff_cnt_ch_b[0..11] ; Stuck at GND due to stuck port data_in ;
; megaram:U31_2|scc_wave:SccCh|ff_cnt_ch_c[0..11] ; Stuck at GND due to stuck port data_in ;
; megaram:U31_2|scc_wave:SccCh|ff_cnt_ch_d[0..11] ; Stuck at GND due to stuck port data_in ;
; megaram:U31_2|scc_wave:SccCh|ff_cnt_ch_e[0..11] ; Stuck at GND due to stuck port data_in ;
; megaram:U31_2|scc_wave:SccCh|ff_ptr_ch_a[0..4] ; Stuck at GND due to stuck port data_in ;
; megaram:U31_2|scc_wave:SccCh|ff_ptr_ch_b[0..4] ; Stuck at GND due to stuck port data_in ;
; megaram:U31_2|scc_wave:SccCh|ff_ptr_ch_c[0..4] ; Stuck at GND due to stuck port data_in ;
; megaram:U31_2|scc_wave:SccCh|ff_ptr_ch_d[0..4] ; Stuck at GND due to stuck port data_in ;
; megaram:U31_2|scc_wave:SccCh|ff_ptr_ch_e[0..4] ; Stuck at GND due to stuck port data_in ;
; megaram:U31_2|scc_wave:SccCh|ram:wavemem|iadr[1..4] ; Stuck at GND due to stuck port data_in ;
; megaram:U31_1|scc_wave:SccCh|ff_cnt_ch_a[0..11] ; Stuck at GND due to stuck port data_in ;
; megaram:U31_1|scc_wave:SccCh|ff_cnt_ch_b[0..11] ; Stuck at GND due to stuck port data_in ;
; megaram:U31_1|scc_wave:SccCh|ff_cnt_ch_c[0..11] ; Stuck at GND due to stuck port data_in ;
; megaram:U31_1|scc_wave:SccCh|ff_cnt_ch_d[0..11] ; Stuck at GND due to stuck port data_in ;
; megaram:U31_1|scc_wave:SccCh|ff_cnt_ch_e[0..11] ; Stuck at GND due to stuck port data_in ;
; megaram:U31_1|scc_wave:SccCh|ff_ptr_ch_a[0..4] ; Stuck at GND due to stuck port data_in ;
; megaram:U31_1|scc_wave:SccCh|ff_ptr_ch_b[0..4] ; Stuck at GND due to stuck port data_in ;
; megaram:U31_1|scc_wave:SccCh|ff_ptr_ch_c[0..4] ; Stuck at GND due to stuck port data_in ;
; megaram:U31_1|scc_wave:SccCh|ff_ptr_ch_d[0..4] ; Stuck at GND due to stuck port data_in ;
; megaram:U31_1|scc_wave:SccCh|ff_ptr_ch_e[0..4] ; Stuck at GND due to stuck port data_in ;
; megaram:U31_1|scc_wave:SccCh|ram:wavemem|iadr[1..4] ; Stuck at GND due to stuck port data_in ;
; megaram:U31_2|scc_wave:SccCh|ram:wavemem|iadr[0] ; Stuck at GND due to stuck port data_in ;
; megaram:U31_1|scc_wave:SccCh|ram:wavemem|iadr[0] ; Stuck at GND due to stuck port data_in ;
; pDac_SR[4]~reg0 ; Stuck at GND due to stuck port data_in ;
; psg:U30|joya[3]~reg0 ; Stuck at GND due to stuck port data_in ;
; psg:U30|joya[2]~reg0 ; Stuck at GND due to stuck port data_in ;
; psg:U30|joya[1]~reg0 ; Stuck at GND due to stuck port data_in ;
; psg:U30|joya[0]~reg0 ; Stuck at GND due to stuck port data_in ;
; psg:U30|joyb[0]~reg0 ; Stuck at GND due to stuck port data_in ;
; psg:U30|joyb[3]~reg0 ; Stuck at GND due to stuck port data_in ;
; psg:U30|joyb[2]~reg0 ; Stuck at GND due to stuck port data_in ;
; psg:U30|joyb[1]~reg0 ; Stuck at GND due to stuck port data_in ;
; eseps2:U06|ff_ps2_dat ; Stuck at GND due to stuck port data_in ;
; megaram:U31_2|scc_wave:SccCh|ff_mix[0..14] ; Stuck at GND due to stuck port data_in ;
; megaram:U31_2|scc_wave:SccCh|ff_wave[1..14] ; Stuck at GND due to stuck port data_in ;
; megaram:U31_1|scc_wave:SccCh|ff_mix[0..14] ; Stuck at GND due to stuck port data_in ;
; megaram:U31_1|scc_wave:SccCh|ff_wave[1..14] ; Stuck at GND due to stuck port data_in ;
; megaram:U31_2|scc_wave:SccCh|ff_wave[0] ; Stuck at GND due to stuck port data_in ;
; megaram:U31_1|scc_wave:SccCh|ff_wave[0] ; Stuck at GND due to stuck port data_in ;
; ff_prescc[0..15] ; Stuck at GND due to stuck port data_in ;
; ff_scc[0..13,15] ; Stuck at GND due to stuck port data_in ;
; VDP:U20|VDP_SSG:U_SSG|FF_PRE_X_CNT_START1[5] ; Merged with psg:U30|rega[6] ;
; eseps2:U06|ff_div[0] ; Merged with psg:U30|psg_wave:u_psgch|PsgClkEna[0] ;
; VDP:U20|VDP_SSG:U_SSG|PREDOTCOUNTERYPSTART[0..5] ; Lost fanout ;
; T80a:U01|T80:u0|MULU_Prod32[0..27] ; Lost fanout ;
; T80a:U01|T80:u0|MULU_Fakt1[0..15] ; Lost fanout ;
; T80a:U01|T80:u0|MULU_Prod32[28..31] ; Lost fanout ;
; eseps2:U06|keymap:u_keymap|ff_dbi[0..7] ; Lost fanout ;
; SdrAdr[12] ; Stuck at GND due to stuck port data_in ;