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emsx_top.sta.rpt
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emsx_top.sta.rpt
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TimeQuest Timing Analyzer report for emsx_top
Thu Apr 18 20:45:19 2024
Quartus II Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. TimeQuest Timing Analyzer Summary
3. Parallel Compilation
4. SDC File List
5. Clocks
6. Slow Model Fmax Summary
7. Slow Model Setup Summary
8. Slow Model Hold Summary
9. Slow Model Recovery Summary
10. Slow Model Removal Summary
11. Slow Model Minimum Pulse Width Summary
12. Slow Model Setup: 'PLL4X:U00|altpll:altpll_component|_clk1'
13. Slow Model Setup: 'PLL4X:U00|altpll:altpll_component|_clk0'
14. Slow Model Hold: 'PLL4X:U00|altpll:altpll_component|_clk0'
15. Slow Model Hold: 'PLL4X:U00|altpll:altpll_component|_clk1'
16. Slow Model Recovery: 'PLL4X:U00|altpll:altpll_component|_clk1'
17. Slow Model Recovery: 'PLL4X:U00|altpll:altpll_component|_clk0'
18. Slow Model Removal: 'PLL4X:U00|altpll:altpll_component|_clk0'
19. Slow Model Removal: 'PLL4X:U00|altpll:altpll_component|_clk1'
20. Slow Model Minimum Pulse Width: 'PLL4X:U00|altpll:altpll_component|_clk1'
21. Slow Model Minimum Pulse Width: 'PLL4X:U00|altpll:altpll_component|_clk0'
22. Slow Model Minimum Pulse Width: 'pClk21m'
23. Setup Times
24. Hold Times
25. Clock to Output Times
26. Minimum Clock to Output Times
27. Propagation Delay
28. Minimum Propagation Delay
29. Output Enable Times
30. Minimum Output Enable Times
31. Output Disable Times
32. Minimum Output Disable Times
33. Fast Model Setup Summary
34. Fast Model Hold Summary
35. Fast Model Recovery Summary
36. Fast Model Removal Summary
37. Fast Model Minimum Pulse Width Summary
38. Fast Model Setup: 'PLL4X:U00|altpll:altpll_component|_clk1'
39. Fast Model Setup: 'PLL4X:U00|altpll:altpll_component|_clk0'
40. Fast Model Hold: 'PLL4X:U00|altpll:altpll_component|_clk0'
41. Fast Model Hold: 'PLL4X:U00|altpll:altpll_component|_clk1'
42. Fast Model Recovery: 'PLL4X:U00|altpll:altpll_component|_clk1'
43. Fast Model Recovery: 'PLL4X:U00|altpll:altpll_component|_clk0'
44. Fast Model Removal: 'PLL4X:U00|altpll:altpll_component|_clk0'
45. Fast Model Removal: 'PLL4X:U00|altpll:altpll_component|_clk1'
46. Fast Model Minimum Pulse Width: 'PLL4X:U00|altpll:altpll_component|_clk1'
47. Fast Model Minimum Pulse Width: 'PLL4X:U00|altpll:altpll_component|_clk0'
48. Fast Model Minimum Pulse Width: 'pClk21m'
49. Setup Times
50. Hold Times
51. Clock to Output Times
52. Minimum Clock to Output Times
53. Propagation Delay
54. Minimum Propagation Delay
55. Output Enable Times
56. Minimum Output Enable Times
57. Output Disable Times
58. Minimum Output Disable Times
59. Multicorner Timing Analysis Summary
60. Setup Times
61. Hold Times
62. Clock to Output Times
63. Minimum Clock to Output Times
64. Progagation Delay
65. Minimum Progagation Delay
66. Setup Transfers
67. Hold Transfers
68. Recovery Transfers
69. Removal Transfers
70. Report TCCS
71. Report RSKM
72. Unconstrained Paths
73. TimeQuest Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2011 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary ;
+--------------------+-----------------------------------------------------------------+
; Quartus II Version ; Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Web Edition ;
; Revision Name ; emsx_top ;
; Device Family ; Cyclone ;
; Device Name ; EP1C12Q240C8 ;
; Timing Models ; Final ;
; Delay Model ; Combined ;
; Rise/Fall Delays ; Unavailable ;
+--------------------+-----------------------------------------------------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 4 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.50 ;
; Maximum used ; 2 ;
; ; ;
; Usage by Processor ; % Time Used ;
; 1 processor ; 100.0% ;
; 2 processors ; 33.3% ;
; 3-4 processors ; 0.0% ;
+----------------------------+-------------+
+-------------------------------------------------------------+
; SDC File List ;
+-------------------------+--------+--------------------------+
; SDC File Path ; Status ; Read at ;
+-------------------------+--------+--------------------------+
; emsx_top_constrains.sdc ; OK ; Thu Apr 18 20:45:17 2024 ;
+-------------------------+--------+--------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks ;
+--------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------+-----------------------------------+----------------------------------------+
; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
+--------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------+-----------------------------------+----------------------------------------+
; pClk21m ; Base ; 46.554 ; 21.48 MHz ; 0.000 ; 23.277 ; ; ; ; ; ; ; ; ; ; ; { pClk21m } ;
; PLL4X:U00|altpll:altpll_component|_clk0 ; Generated ; 46.554 ; 21.48 MHz ; 0.000 ; 23.277 ; 50.00 ; 1 ; 1 ; ; ; ; ; false ; pClk21m ; U00|altpll_component|pll|inclk[0] ; { U00|altpll_component|pll|clk[0] } ;
; PLL4X:U00|altpll:altpll_component|_clk1 ; Generated ; 11.638 ; 85.93 MHz ; 0.000 ; 5.819 ; 50.00 ; 1 ; 4 ; ; ; ; ; false ; pClk21m ; U00|altpll_component|pll|inclk[0] ; { U00|altpll_component|pll|clk[1] } ;
; PLL4X:U00|altpll:altpll_component|_extclk0 ; Generated ; 11.638 ; 85.93 MHz ; 0.000 ; 5.819 ; 50.00 ; 1 ; 4 ; ; ; ; ; false ; pClk21m ; U00|altpll_component|pll|inclk[0] ; { U00|altpll_component|pll|extclk[0] } ;
+--------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------+-----------------------------------+----------------------------------------+
+-------------------------------------------------------------------------------+
; Slow Model Fmax Summary ;
+------------+-----------------+-----------------------------------------+------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+------------+-----------------+-----------------------------------------+------+
; 39.45 MHz ; 39.45 MHz ; PLL4X:U00|altpll:altpll_component|_clk0 ; ;
; 107.48 MHz ; 107.48 MHz ; PLL4X:U00|altpll:altpll_component|_clk1 ; ;
+------------+-----------------+-----------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+------------------------------------------------------------------+
; Slow Model Setup Summary ;
+-----------------------------------------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+-----------------------------------------+--------+---------------+
; PLL4X:U00|altpll:altpll_component|_clk1 ; 2.334 ; 0.000 ;
; PLL4X:U00|altpll:altpll_component|_clk0 ; 10.602 ; 0.000 ;
+-----------------------------------------+--------+---------------+
+-----------------------------------------------------------------+
; Slow Model Hold Summary ;
+-----------------------------------------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+-----------------------------------------+-------+---------------+
; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.822 ; 0.000 ;
; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.886 ; 0.000 ;
+-----------------------------------------+-------+---------------+
+------------------------------------------------------------------+
; Slow Model Recovery Summary ;
+-----------------------------------------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+-----------------------------------------+--------+---------------+
; PLL4X:U00|altpll:altpll_component|_clk1 ; 4.436 ; 0.000 ;
; PLL4X:U00|altpll:altpll_component|_clk0 ; 41.613 ; 0.000 ;
+-----------------------------------------+--------+---------------+
+-----------------------------------------------------------------+
; Slow Model Removal Summary ;
+-----------------------------------------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+-----------------------------------------+-------+---------------+
; PLL4X:U00|altpll:altpll_component|_clk0 ; 1.423 ; 0.000 ;
; PLL4X:U00|altpll:altpll_component|_clk1 ; 6.431 ; 0.000 ;
+-----------------------------------------+-------+---------------+
+------------------------------------------------------------------+
; Slow Model Minimum Pulse Width Summary ;
+-----------------------------------------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+-----------------------------------------+--------+---------------+
; PLL4X:U00|altpll:altpll_component|_clk1 ; 4.001 ; 0.000 ;
; PLL4X:U00|altpll:altpll_component|_clk0 ; 21.459 ; 0.000 ;
; pClk21m ; 23.277 ; 0.000 ;
+-----------------------------------------+--------+---------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'PLL4X:U00|altpll:altpll_component|_clk1' ;
+-------+---------------+-------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------+-------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
; 2.334 ; iSlt0_1 ; SdrAdr[5] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.317 ; 8.470 ;
; 2.548 ; pMemDat[8] ; RamDbi[0] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; 2.465 ; 5.118 ;
; 2.608 ; pMemDat[10] ; RamDbi[2] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; 2.465 ; 5.058 ;
; 2.645 ; pMemDat[4] ; RamDbi[4] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; 2.465 ; 5.021 ;
; 2.646 ; pMemDat[1] ; RamDbi[1] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; 2.465 ; 5.020 ;
; 2.664 ; pMemDat[11] ; RamDbi[3] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; 2.465 ; 5.002 ;
; 2.784 ; pMemDat[9] ; RamDbi[1] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; 2.465 ; 4.882 ;
; 2.839 ; pMemDat[0] ; RamDbi[0] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; 2.465 ; 4.827 ;
; 2.845 ; pMemDat[2] ; RamDbi[2] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; 2.465 ; 4.821 ;
; 2.903 ; pMemDat[5] ; VrmDbi[5] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; 2.465 ; 4.763 ;
; 2.908 ; pMemDat[3] ; RamDbi[3] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; 2.465 ; 4.758 ;
; 2.910 ; pMemDat[8] ; VrmDbi[8] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; 2.465 ; 4.756 ;
; 2.928 ; pMemDat[12] ; VrmDbi[12] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; 2.465 ; 4.738 ;
; 2.930 ; pMemDat[7] ; RamDbi[7] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; 2.465 ; 4.736 ;
; 2.932 ; pMemDat[6] ; VrmDbi[6] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; 2.465 ; 4.734 ;
; 2.934 ; pMemDat[9] ; VrmDbi[9] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; 2.465 ; 4.732 ;
; 2.972 ; pMemDat[10] ; VrmDbi[10] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; 2.465 ; 4.694 ;
; 2.976 ; pMemDat[15] ; RamDbi[7] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; 2.465 ; 4.690 ;
; 2.979 ; pMemDat[15] ; VrmDbi[15] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; 2.465 ; 4.687 ;
; 2.984 ; pMemDat[0] ; VrmDbi[0] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; 2.465 ; 4.682 ;
; 2.992 ; iSlt0_1 ; SdrAdr[4] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.317 ; 7.812 ;
; 2.996 ; pMemDat[2] ; VrmDbi[2] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; 2.465 ; 4.670 ;
; 3.007 ; pMemDat[4] ; VrmDbi[4] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; 2.465 ; 4.659 ;
; 3.010 ; pMemDat[1] ; VrmDbi[1] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; 2.465 ; 4.656 ;
; 3.013 ; pMemDat[5] ; RamDbi[5] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; 2.465 ; 4.653 ;
; 3.027 ; pMemDat[11] ; VrmDbi[11] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; 2.465 ; 4.639 ;
; 3.037 ; pMemDat[6] ; RamDbi[6] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; 2.465 ; 4.629 ;
; 3.041 ; iSlt0_1 ; SdrAdr[6] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.317 ; 7.763 ;
; 3.075 ; pMemDat[3] ; VrmDbi[3] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; 2.465 ; 4.591 ;
; 3.077 ; RstSeq[4] ; SdrAdr[8] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.315 ; 7.729 ;
; 3.147 ; pMemDat[14] ; RamDbi[6] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; 2.465 ; 4.519 ;
; 3.149 ; pMemDat[12] ; RamDbi[4] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; 2.465 ; 4.517 ;
; 3.151 ; pMemDat[14] ; VrmDbi[14] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; 2.465 ; 4.515 ;
; 3.179 ; pMemDat[13] ; RamDbi[5] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; 2.465 ; 4.487 ;
; 3.261 ; RstSeq[3] ; SdrAdr[8] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.315 ; 7.545 ;
; 3.290 ; pMemDat[7] ; VrmDbi[7] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; 2.465 ; 4.376 ;
; 3.292 ; RstSeq[4] ; SdrAdr[0] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.315 ; 7.514 ;
; 3.304 ; iSlt0_1 ; SdrLdq ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.317 ; 7.500 ;
; 3.424 ; ff_sdr_seq[1] ; SdrAdr[4] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.315 ; 7.382 ;
; 3.476 ; RstSeq[3] ; SdrAdr[0] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.315 ; 7.330 ;
; 3.529 ; iSlt0_1 ; SdrAdr[8] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.317 ; 7.275 ;
; 3.671 ; iSlt0_1 ; SdrAdr[1] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.317 ; 7.133 ;
; 3.689 ; iSlt0_1 ; SdrUdq ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.317 ; 7.115 ;
; 3.690 ; pMemDat[13] ; VrmDbi[13] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; 2.524 ; 4.035 ;
; 3.702 ; RstSeq[4] ; SdrAdr[6] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.315 ; 7.104 ;
; 3.726 ; RstSeq[4] ; SdrDat[0] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.315 ; 7.080 ;
; 3.762 ; ff_sdr_seq[1] ; SdrAdr[5] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.315 ; 7.044 ;
; 3.775 ; RstSeq[4] ; SdrDat[4] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.315 ; 7.031 ;
; 3.809 ; SdrAdr[0] ; pMemAdr[0] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -2.209 ; 4.120 ;
; 3.809 ; SdrAdr[1] ; pMemAdr[1] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -2.209 ; 4.120 ;
; 3.809 ; SdrAdr[2] ; pMemAdr[2] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -2.209 ; 4.120 ;
; 3.809 ; SdrAdr[3] ; pMemAdr[3] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -2.209 ; 4.120 ;
; 3.809 ; SdrAdr[4] ; pMemAdr[4] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -2.209 ; 4.120 ;
; 3.809 ; SdrAdr[5] ; pMemAdr[5] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -2.209 ; 4.120 ;
; 3.809 ; SdrAdr[6] ; pMemAdr[6] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -2.209 ; 4.120 ;
; 3.809 ; SdrAdr[7] ; pMemAdr[7] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -2.209 ; 4.120 ;
; 3.809 ; SdrAdr[8] ; pMemAdr[8] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -2.209 ; 4.120 ;
; 3.809 ; SdrAdr[9] ; pMemAdr[9] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -2.209 ; 4.120 ;
; 3.809 ; SdrAdr[10] ; pMemAdr[10] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -2.209 ; 4.120 ;
; 3.809 ; SdrAdr[11] ; pMemAdr[11] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -2.209 ; 4.120 ;
; 3.809 ; SdrCmd[1] ; pMemCas_n ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -2.209 ; 4.120 ;
; 3.809 ; SdrDat[0] ; pMemDat[0] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -2.209 ; 4.120 ;
; 3.809 ; SdrDat[1] ; pMemDat[1] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -2.209 ; 4.120 ;
; 3.809 ; SdrDat[2] ; pMemDat[2] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -2.209 ; 4.120 ;
; 3.809 ; SdrDat[3] ; pMemDat[3] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -2.209 ; 4.120 ;
; 3.809 ; SdrDat[4] ; pMemDat[4] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -2.209 ; 4.120 ;
; 3.809 ; SdrDat[5] ; pMemDat[5] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -2.209 ; 4.120 ;
; 3.809 ; SdrDat[6] ; pMemDat[6] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -2.209 ; 4.120 ;
; 3.809 ; SdrDat[7] ; pMemDat[7] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -2.209 ; 4.120 ;
; 3.809 ; SdrDat[8] ; pMemDat[8] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -2.209 ; 4.120 ;
; 3.809 ; SdrDat[9] ; pMemDat[9] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -2.209 ; 4.120 ;
; 3.809 ; SdrDat[10] ; pMemDat[10] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -2.209 ; 4.120 ;
; 3.809 ; SdrDat[11] ; pMemDat[11] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -2.209 ; 4.120 ;
; 3.809 ; SdrDat[12] ; pMemDat[12] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -2.209 ; 4.120 ;
; 3.809 ; SdrDat[13] ; pMemDat[13] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -2.209 ; 4.120 ;
; 3.809 ; SdrDat[14] ; pMemDat[14] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -2.209 ; 4.120 ;
; 3.809 ; SdrDat[15] ; pMemDat[15] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -2.209 ; 4.120 ;
; 3.809 ; SdrLdq ; pMemLdq ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -2.209 ; 4.120 ;
; 3.809 ; SdrCmd[2] ; pMemRas_n ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -2.209 ; 4.120 ;
; 3.809 ; SdrUdq ; pMemUdq ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -2.209 ; 4.120 ;
; 3.809 ; SdrCmd[0] ; pMemWe_n ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -2.209 ; 4.120 ;
; 3.821 ; RstSeq[4] ; SdrAdr[5] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.315 ; 6.985 ;
; 3.848 ; RstSeq[2] ; SdrAdr[8] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.315 ; 6.958 ;
; 3.886 ; RstSeq[3] ; SdrAdr[6] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.315 ; 6.920 ;
; 3.890 ; iSlt0_1 ; SdrAdr[7] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.317 ; 6.914 ;
; 3.992 ; RstSeq[4] ; SdrAdr[2] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.315 ; 6.814 ;
; 4.005 ; RstSeq[3] ; SdrAdr[5] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.315 ; 6.801 ;
; 4.007 ; RstSeq[4] ; SdrAdr[7] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.315 ; 6.799 ;
; 4.011 ; iSlt0_1 ; SdrAdr[3] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.317 ; 6.793 ;
; 4.036 ; RstSeq[4] ; SdrDat[3] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.315 ; 6.770 ;
; 4.044 ; RstSeq[4] ; SdrAdr[1] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.315 ; 6.762 ;
; 4.045 ; RstSeq[4] ; SdrAdr[11] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.315 ; 6.761 ;
; 4.053 ; RstSeq[4] ; SdrDat[1] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.315 ; 6.753 ;
; 4.063 ; RstSeq[2] ; SdrAdr[0] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.315 ; 6.743 ;
; 4.071 ; RstSeq[4] ; SdrDat[2] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.315 ; 6.735 ;
; 4.073 ; RstSeq[1] ; SdrAdr[8] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.315 ; 6.733 ;
; 4.106 ; RstSeq[4] ; SdrDat[7] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.315 ; 6.700 ;
; 4.112 ; ff_sdr_seq[1] ; SdrAdr[0] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.315 ; 6.694 ;
; 4.176 ; RstSeq[3] ; SdrAdr[2] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.315 ; 6.630 ;
; 4.191 ; RstSeq[3] ; SdrAdr[7] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.315 ; 6.615 ;
+-------+---------------+-------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'PLL4X:U00|altpll:altpll_component|_clk0' ;
+--------+-------------+--------------------------------------------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------+--------------------------------------------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
; 10.602 ; wrt ; switched_io_ports:U35|OpllVol[2]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 12.556 ;
; 11.026 ; wrt ; switched_io_ports:U35|io43_id212[4]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 12.132 ;
; 11.049 ; wrt ; switched_io_ports:U35|OpllVol[1]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 12.109 ;
; 11.268 ; wrt ; switched_io_ports:U35|io42_id212[0]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 11.890 ;
; 11.271 ; wrt ; switched_io_ports:U35|SccVol[2]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 11.887 ;
; 11.412 ; wrt ; switched_io_ports:U35|io41_id008_n~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.041 ; 11.787 ;
; 11.428 ; wrt ; switched_io_ports:U35|io43_id212[3]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 11.730 ;
; 11.482 ; wrt ; switched_io_ports:U35|Mapper_req~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.078 ; 11.680 ;
; 11.539 ; wrt ; switched_io_ports:U35|SccVol[1]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 11.619 ;
; 11.549 ; wrt ; switched_io_ports:U35|PsgVol[1]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.141 ; 11.550 ;
; 11.617 ; wrt ; switched_io_ports:U35|PsgVol[2]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.141 ; 11.482 ;
; 11.626 ; wrt ; switched_io_ports:U35|io44_id212[6]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.078 ; 11.536 ;
; 11.684 ; wrt ; switched_io_ports:U35|xmr_ena~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.078 ; 11.478 ;
; 11.700 ; wrt ; switched_io_ports:U35|CustomSpeed[1]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.078 ; 11.462 ;
; 11.954 ; wrt ; switched_io_ports:U35|OFFSET_Y[0] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 11.204 ;
; 11.954 ; wrt ; switched_io_ports:U35|OFFSET_Y[1] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 11.204 ;
; 11.954 ; wrt ; switched_io_ports:U35|OFFSET_Y[4] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 11.204 ;
; 11.973 ; wrt ; switched_io_ports:U35|io44_id212[1]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.078 ; 11.189 ;
; 11.973 ; wrt ; switched_io_ports:U35|io44_id212[2]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.078 ; 11.189 ;
; 11.973 ; wrt ; switched_io_ports:U35|io44_id212[3]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.078 ; 11.189 ;
; 11.973 ; wrt ; switched_io_ports:U35|io44_id212[4]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.078 ; 11.189 ;
; 11.973 ; wrt ; switched_io_ports:U35|io44_id212[5]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.078 ; 11.189 ;
; 11.973 ; wrt ; switched_io_ports:U35|io44_id212[7]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.078 ; 11.189 ;
; 12.105 ; wrt ; switched_io_ports:U35|io42_id212[5]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 11.053 ;
; 12.140 ; wrt ; switched_io_ports:U35|CustomSpeed[2]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.078 ; 11.022 ;
; 12.281 ; wrt ; switched_io_ports:U35|bios_reload_ack ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.078 ; 10.881 ;
; 12.287 ; wrt ; switched_io_ports:U35|PsgVol[0]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.141 ; 10.812 ;
; 12.325 ; wrt ; switched_io_ports:U35|swioCmt~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 10.833 ;
; 12.392 ; wrt ; switched_io_ports:U35|CustomSpeed[3]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 10.766 ;
; 12.397 ; wrt ; switched_io_ports:U35|CustomSpeed[0]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 10.761 ;
; 12.421 ; wrt ; switched_io_ports:U35|MstrVol[2]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.073 ; 10.746 ;
; 12.440 ; wrt ; switched_io_ports:U35|ntsc_pal_type~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 10.718 ;
; 12.440 ; wrt ; switched_io_ports:U35|tPanaRedir~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 10.718 ;
; 12.491 ; wrt ; switched_io_ports:U35|io43_id212[6]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 10.667 ;
; 12.549 ; wrt ; switched_io_ports:U35|forced_v_mode~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 10.609 ;
; 12.575 ; wrt ; switched_io_ports:U35|MstrVol[0]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.141 ; 10.524 ;
; 12.691 ; wrt ; switched_io_ports:U35|WarmMSXlogo~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.039 ; 10.510 ;
; 12.752 ; wrt ; switched_io_ports:U35|right_inverse~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 10.406 ;
; 12.768 ; wrt ; switched_io_ports:U35|OFFSET_Y[3] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 10.390 ;
; 12.768 ; wrt ; switched_io_ports:U35|OFFSET_Y[2] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 10.390 ;
; 12.812 ; wrt ; switched_io_ports:U35|MstrVol[1]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.141 ; 10.287 ;
; 12.819 ; wrt ; switched_io_ports:U35|io42_id212[4]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 10.339 ;
; 12.845 ; wrt ; switched_io_ports:U35|RatioMode[1]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 10.313 ;
; 12.850 ; wrt ; switched_io_ports:U35|RatioMode[0]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 10.308 ;
; 12.856 ; wrt ; switched_io_ports:U35|io44_id212[0]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.039 ; 10.345 ;
; 12.858 ; wrt ; switched_io_ports:U35|io43_id212[7]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 10.300 ;
; 12.908 ; wrt ; switched_io_ports:U35|io43_id212[2]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 10.250 ;
; 12.929 ; wrt ; switched_io_ports:U35|RatioMode[2]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 10.229 ;
; 12.960 ; wrt ; switched_io_ports:U35|centerYJK_R25_n~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 10.198 ;
; 13.052 ; wrt ; switched_io_ports:U35|ff_dip_ack[1]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.041 ; 10.147 ;
; 13.075 ; wrt ; switched_io_ports:U35|Blink_ena~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.078 ; 10.087 ;
; 13.075 ; wrt ; switched_io_ports:U35|io42_id212[3]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 10.083 ;
; 13.081 ; wrt ; switched_io_ports:U35|swioRESET_n~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.078 ; 10.081 ;
; 13.105 ; wrt ; switched_io_ports:U35|SccVol[0]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 10.053 ;
; 13.153 ; wrt ; switched_io_ports:U35|pseudoStereo~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 10.005 ;
; 13.489 ; wrt ; switched_io_ports:U35|ff_dip_ack[2]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.041 ; 9.710 ;
; 13.534 ; wrt ; rtc:U07|reg_day[0] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.065 ; 9.641 ;
; 13.534 ; wrt ; rtc:U07|reg_day[1] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.065 ; 9.641 ;
; 13.534 ; wrt ; rtc:U07|reg_day[2] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.065 ; 9.641 ;
; 13.534 ; wrt ; rtc:U07|reg_day[3] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.065 ; 9.641 ;
; 13.586 ; wrt ; switched_io_ports:U35|io43_id212[1]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 9.572 ;
; 13.639 ; wrt ; switched_io_ports:U35|io43_id212[0]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 9.519 ;
; 13.647 ; wrt ; switched_io_ports:U35|tMegaSD~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 9.511 ;
; 13.675 ; wrt ; switched_io_ports:U35|Red_sta~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 9.483 ;
; 13.716 ; iSltAdr[15] ; jSltMem ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; 0.010 ; 9.534 ;
; 13.731 ; wrt ; switched_io_ports:U35|iSlt2_linear~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 9.427 ;
; 13.909 ; wrt ; switched_io_ports:U35|legacy_sel~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.141 ; 9.190 ;
; 13.936 ; wrt ; switched_io_ports:U35|Slot0_req~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 9.222 ;
; 14.001 ; PpiPortA[0] ; jSltMem ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; 0.000 ; 9.239 ;
; 14.040 ; iSltAdr[14] ; jSltMem ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; 0.010 ; 9.210 ;
; 14.093 ; wrt ; switched_io_ports:U35|warmRESET~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 9.065 ;
; 14.096 ; wrt ; switched_io_ports:U35|MegaSD_req~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.078 ; 9.066 ;
; 14.133 ; iSltAdr[0] ; jSltMem ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; 0.000 ; 9.107 ;
; 14.209 ; wrt ; switched_io_ports:U35|VdpSpeedMode~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 8.949 ;
; 14.272 ; wrt ; rtc:U07|reg_wee[0] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.065 ; 8.903 ;
; 14.272 ; wrt ; rtc:U07|reg_wee[1] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.065 ; 8.903 ;
; 14.272 ; wrt ; rtc:U07|reg_wee[2] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.065 ; 8.903 ;
; 14.408 ; wrt ; switched_io_ports:U35|OpllVol[0]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 8.750 ;
; 14.476 ; wrt ; switched_io_ports:U35|io42_id212[1]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.078 ; 8.686 ;
; 14.494 ; wrt ; switched_io_ports:U35|io43_id212[5]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.039 ; 8.707 ;
; 14.504 ; wrt ; switched_io_ports:U35|Mapper0_req~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.078 ; 8.658 ;
; 14.522 ; wrt ; switched_io_ports:U35|io42_id212[2]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.078 ; 8.640 ;
; 14.673 ; ExpSlot0[0] ; jSltMem ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; 0.010 ; 8.577 ;
; 14.694 ; PpiPortA[6] ; jSltMem ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; 0.000 ; 8.546 ;
; 14.723 ; wrt ; switched_io_ports:U35|swioKmap~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.078 ; 8.439 ;
; 14.782 ; wrt ; switched_io_ports:U35|vram_slot_ids[5]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.078 ; 8.380 ;
; 14.783 ; wrt ; switched_io_ports:U35|vram_slot_ids[1]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.078 ; 8.379 ;
; 14.786 ; wrt ; switched_io_ports:U35|vram_slot_ids[0]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.078 ; 8.376 ;
; 14.824 ; iSltAdr[12] ; jSltMem ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; 0.010 ; 8.426 ;
; 14.855 ; wrt ; switched_io_ports:U35|iSlt1_linear~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.082 ; 8.303 ;
; 14.916 ; wrt ; switched_io_ports:U35|vram_slot_ids[2]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; 0.006 ; 8.330 ;
; 14.953 ; iSltAdr[13] ; jSltMem ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; 0.000 ; 8.287 ;
; 14.971 ; wrt ; switched_io_ports:U35|VDP_ID[1] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.141 ; 8.128 ;
; 15.024 ; ExpSlot0[1] ; jSltMem ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; 0.010 ; 8.226 ;
; 15.026 ; wrt ; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|VDPP1DATA[2] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.141 ; 8.073 ;
; 15.026 ; wrt ; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|VDPP1DATA[1] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.141 ; 8.073 ;
; 15.026 ; wrt ; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|VDPP1DATA[0] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.141 ; 8.073 ;
; 15.026 ; wrt ; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|VDPP1DATA[3] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.141 ; 8.073 ;
; 15.026 ; wrt ; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|VDPP1DATA[5] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.141 ; 8.073 ;
; 15.026 ; wrt ; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|VDPP1DATA[7] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 23.277 ; -0.141 ; 8.073 ;
+--------+-------------+--------------------------------------------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'PLL4X:U00|altpll:altpll_component|_clk0' ;
+-------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
; 0.822 ; VDP:U20|VDP_COMMAND:U_VDP_COMMAND|VDPVRAMACCESSX[1] ; VDP:U20|VDP_COMMAND:U_VDP_COMMAND|VDPVRAMACCESSX[1] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_COMMAND:U_VDP_COMMAND|VDPVRAMACCESSX[2] ; VDP:U20|VDP_COMMAND:U_VDP_COMMAND|VDPVRAMACCESSX[2] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_COMMAND:U_VDP_COMMAND|VDPVRAMACCESSX[3] ; VDP:U20|VDP_COMMAND:U_VDP_COMMAND|VDPVRAMACCESSX[3] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_COMMAND:U_VDP_COMMAND|VDPVRAMACCESSX[4] ; VDP:U20|VDP_COMMAND:U_VDP_COMMAND|VDPVRAMACCESSX[4] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_COMMAND:U_VDP_COMMAND|VDPVRAMACCESSX[5] ; VDP:U20|VDP_COMMAND:U_VDP_COMMAND|VDPVRAMACCESSX[5] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_COMMAND:U_VDP_COMMAND|VDPVRAMACCESSX[6] ; VDP:U20|VDP_COMMAND:U_VDP_COMMAND|VDPVRAMACCESSX[6] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_COMMAND:U_VDP_COMMAND|VDPVRAMACCESSX[7] ; VDP:U20|VDP_COMMAND:U_VDP_COMMAND|VDPVRAMACCESSX[7] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|VDPREGWRPULSE ; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|VDPREGWRPULSE ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; eseps2:U06|ff_ps2_state.PS2_ST_SND_RESET ; eseps2:U06|ff_ps2_state.PS2_ST_SND_RESET ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; wifi:uwifi|FIFO:U2|tail_s[1] ; wifi:uwifi|FIFO:U2|tail_s[1] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; wifi:uwifi|FIFO:U2|tail_s[3] ; wifi:uwifi|FIFO:U2|tail_s[3] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; wifi:uwifi|FIFO:U2|tail_s[7] ; wifi:uwifi|FIFO:U2|tail_s[7] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; wifi:uwifi|FIFO:U2|tail_s[6] ; wifi:uwifi|FIFO:U2|tail_s[6] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; wifi:uwifi|FIFO:U2|tail_s[9] ; wifi:uwifi|FIFO:U2|tail_s[9] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; wifi:uwifi|FIFO:U2|tail_s[8] ; wifi:uwifi|FIFO:U2|tail_s[8] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; wifi:uwifi|FIFO:U2|tail_s[10] ; wifi:uwifi|FIFO:U2|tail_s[10] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_SPRITE:U_SPRITE|SPPREDRAWLOCALPLANENUM[0] ; VDP:U20|VDP_SPRITE:U_SPRITE|SPPREDRAWLOCALPLANENUM[0] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_SPRITE:U_SPRITE|SPPREDRAWLOCALPLANENUM[1] ; VDP:U20|VDP_SPRITE:U_SPRITE|SPPREDRAWLOCALPLANENUM[1] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_SPRITE:U_SPRITE|SPPREDRAWLOCALPLANENUM[2] ; VDP:U20|VDP_SPRITE:U_SPRITE|SPPREDRAWLOCALPLANENUM[2] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; switched_io_ports:U35|VDP_ID[1] ; switched_io_ports:U35|VDP_ID[1] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; eseps2:U06|ff_timer[3] ; eseps2:U06|ff_timer[3] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; eseps2:U06|ff_timer[4] ; eseps2:U06|ff_timer[4] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|VDPP1IS1STBYTE ; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|VDPP1IS1STBYTE ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_COMMAND:U_VDP_COMMAND|VDPVRAMACCESSY[9] ; VDP:U20|VDP_COMMAND:U_VDP_COMMAND|VDPVRAMACCESSY[9] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_COMMAND:U_VDP_COMMAND|VDPVRAMACCESSX[0] ; VDP:U20|VDP_COMMAND:U_VDP_COMMAND|VDPVRAMACCESSX[0] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_COMMAND:U_VDP_COMMAND|VDPVRAMACCESSX[8] ; VDP:U20|VDP_COMMAND:U_VDP_COMMAND|VDPVRAMACCESSX[8] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; esepwm:U33|esefir5:U1|ff_mute[3] ; esepwm:U33|esefir5:U1|ff_mute[3] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; esepwm:U33|esefir5:U1|ff_mute[1] ; esepwm:U33|esefir5:U1|ff_mute[1] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; portF4_bit7 ; portF4_bit7 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_INTERRUPT:U_INTERRUPT|FF_VSYNC_INT_N ; VDP:U20|VDP_INTERRUPT:U_INTERRUPT|FF_VSYNC_INT_N ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_SSG:U_SSG|IVIDEOVS_N ; VDP:U20|VDP_SSG:U_SSG|IVIDEOVS_N ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS5S6SPCOLLISIONYV[0] ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS5S6SPCOLLISIONYV[0] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS5S6SPCOLLISIONYV[8] ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS5S6SPCOLLISIONYV[8] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS3S4SPCOLLISIONXV[8] ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS3S4SPCOLLISIONXV[8] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS3S4SPCOLLISIONXV[0] ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS3S4SPCOLLISIONXV[0] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS5S6SPCOLLISIONYV[1] ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS5S6SPCOLLISIONYV[1] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS3S4SPCOLLISIONXV[1] ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS3S4SPCOLLISIONXV[1] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS5S6SPCOLLISIONYV[2] ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS5S6SPCOLLISIONYV[2] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS3S4SPCOLLISIONXV[2] ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS3S4SPCOLLISIONXV[2] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS5S6SPCOLLISIONYV[3] ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS5S6SPCOLLISIONYV[3] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS3S4SPCOLLISIONXV[3] ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS3S4SPCOLLISIONXV[3] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS5S6SPCOLLISIONYV[4] ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS5S6SPCOLLISIONYV[4] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS3S4SPCOLLISIONXV[4] ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS3S4SPCOLLISIONXV[4] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS5S6SPCOLLISIONYV[5] ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS5S6SPCOLLISIONYV[5] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS3S4SPCOLLISIONXV[5] ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS3S4SPCOLLISIONXV[5] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS5S6SPCOLLISIONYV[6] ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS5S6SPCOLLISIONYV[6] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS3S4SPCOLLISIONXV[6] ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS3S4SPCOLLISIONXV[6] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS5S6SPCOLLISIONYV[7] ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS5S6SPCOLLISIONYV[7] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS3S4SPCOLLISIONXV[7] ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS3S4SPCOLLISIONXV[7] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|VDPP2IS1STBYTE ; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|VDPP2IS1STBYTE ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; eseps2:U06|ff_matupd_we ; eseps2:U06|ff_matupd_we ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; psg:U30|psg_wave:u_psgch|PsgCntEnv[10] ; psg:U30|psg_wave:u_psgch|PsgCntEnv[10] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; psg:U30|psg_wave:u_psgch|PsgCntEnv[12] ; psg:U30|psg_wave:u_psgch|PsgCntEnv[12] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; psg:U30|psg_wave:u_psgch|PsgCntEnv[14] ; psg:U30|psg_wave:u_psgch|PsgCntEnv[14] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; psg:U30|psg_wave:u_psgch|PsgGenNoise[0] ; psg:U30|psg_wave:u_psgch|PsgGenNoise[0] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.822 ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS0SPCOLLISIONINCIDENCEV ; VDP:U20|VDP_SPRITE:U_SPRITE|VDPS0SPCOLLISIONINCIDENCEV ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.837 ;
; 0.859 ; iSltDat[2] ; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|VDPP1DATA[2] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.874 ;
; 0.860 ; switched_io_ports:U35|io42_id212[2]~reg0 ; switched_io_ports:U35|io42_id212[2]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.875 ;
; 0.860 ; INTERPO:u_interpo|FF_D2[6] ; INTERPO:u_interpo|FF_D1[6] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.875 ;
; 0.860 ; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|FF_R2_PT_NAM_ADDR[0] ; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|REG_R2_PT_NAM_ADDR[0] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.875 ;
; 0.860 ; LPF2:u_lpf2|FF_D7[4] ; LPF2:u_lpf2|FF_D8[4] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.875 ;
; 0.860 ; LPF2:u_lpf2|FF_D1[0] ; LPF2:u_lpf2|FF_D2[0] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.875 ;
; 0.861 ; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|REG_R11R5_SP_ATR_ADDR[5] ; VDP:U20|VDP_SPRITE:U_SPRITE|SPATTRTBLBASEADDR[5] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.876 ;
; 0.861 ; wifi:uwifi|fifo_data_in[6] ; wifi:uwifi|FIFO:U2|memory_rtl_0_bypass[31] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.876 ;
; 0.861 ; LPF2:u_lpf2|FF_D7[7] ; LPF2:u_lpf2|FF_D8[7] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.876 ;
; 0.861 ; LPF2:u_lpf2|FF_D1[4] ; LPF2:u_lpf2|FF_D2[4] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.876 ;
; 0.861 ; LPF2:u_lpf2|FF_D2[3] ; LPF2:u_lpf2|FF_D3[3] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.876 ;
; 0.862 ; VDP:U20|VDP_COLORDEC:U_VDP_COLORDEC|FF_PALETTE_ADDR[1] ; VDP:U20|VDP_COLORDEC:U_VDP_COLORDEC|FF_PALETTE_ADDR[1] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.877 ;
; 0.862 ; INTERPO:u_interpo|FF_D2[12] ; INTERPO:u_interpo|FF_D1[12] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.877 ;
; 0.862 ; INTERPO:u_interpo|FF_D2[5] ; INTERPO:u_interpo|FF_D1[5] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.877 ;
; 0.862 ; psg:U30|regb[4] ; psg:U30|stra ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.877 ;
; 0.862 ; megasd:U03|ff_send_data[7] ; megasd:U03|mmc_di~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.877 ;
; 0.862 ; VDP:U20|VDP_GRAPHIC4567:U_VDP_GRAPHIC4567|LATCHEDPTNNAMETBLBASEADDR[2] ; VDP:U20|VDP_GRAPHIC4567:U_VDP_GRAPHIC4567|PRAMADR[12] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.877 ;
; 0.862 ; VDP:U20|VDP_GRAPHIC4567:U_VDP_GRAPHIC4567|LATCHEDPTNNAMETBLBASEADDR[3] ; VDP:U20|VDP_GRAPHIC4567:U_VDP_GRAPHIC4567|PRAMADR[13] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.877 ;
; 0.862 ; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|REG_R11R5_SP_ATR_ADDR[3] ; VDP:U20|VDP_SPRITE:U_SPRITE|SPATTRTBLBASEADDR[3] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.877 ;
; 0.862 ; VDP:U20|VDP_GRAPHIC4567:U_VDP_GRAPHIC4567|LATCHEDPTNNAMETBLBASEADDR[0] ; VDP:U20|VDP_GRAPHIC4567:U_VDP_GRAPHIC4567|PRAMADR[10] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.877 ;
; 0.862 ; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|REG_R6_SP_GEN_ADDR[0] ; VDP:U20|VDP_SPRITE:U_SPRITE|SPPTNGENETBLBASEADDR[0] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.877 ;
; 0.862 ; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|REG_R6_SP_GEN_ADDR[1] ; VDP:U20|VDP_SPRITE:U_SPRITE|SPPTNGENETBLBASEADDR[1] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.877 ;
; 0.862 ; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|REG_R6_SP_GEN_ADDR[3] ; VDP:U20|VDP_SPRITE:U_SPRITE|SPPTNGENETBLBASEADDR[3] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.877 ;
; 0.862 ; wifi:uwifi|fifo_data_in[4] ; wifi:uwifi|FIFO:U2|memory_rtl_0_bypass[29] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.877 ;
; 0.862 ; wifi:uwifi|fifo_data_in[7] ; wifi:uwifi|FIFO:U2|memory_rtl_0_bypass[32] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.877 ;
; 0.862 ; VDP:U20|VDP_GRAPHIC123M:U_VDP_GRAPHIC123M|FF_PRE_PAT_COL[2] ; VDP:U20|VDP_GRAPHIC123M:U_VDP_GRAPHIC123M|FF_PAT_COL[2] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.877 ;
; 0.862 ; VDP:U20|VDP_GRAPHIC123M:U_VDP_GRAPHIC123M|FF_PRE_PAT_COL[5] ; VDP:U20|VDP_GRAPHIC123M:U_VDP_GRAPHIC123M|FF_PAT_COL[5] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.877 ;
; 0.862 ; LPF2:u_lpf2|FF_D2[1] ; LPF2:u_lpf2|FF_D3[1] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.877 ;
; 0.863 ; DACin[3] ; INTERPO:u_interpo|FF_D2[3] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.878 ;
; 0.863 ; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|REG_R6_SP_GEN_ADDR[2] ; VDP:U20|VDP_SPRITE:U_SPRITE|SPPTNGENETBLBASEADDR[2] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.878 ;
; 0.863 ; LPF2:u_lpf2|FF_D6[3] ; LPF2:u_lpf2|FF_D7[3] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.878 ;
; 0.864 ; VDP:U20|VDP_COLORDEC:U_VDP_COLORDEC|FF_VIDEO_G[3] ; VDP:U20|VDP_COLORDEC:U_VDP_COLORDEC|FF_VIDEO_G[3] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.879 ;
; 0.865 ; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|FF_R26_H_SCROLL[3] ; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|REG_R26_H_SCROLL[3] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.880 ;
; 0.865 ; VDP:U20|VDP_COLORDEC:U_VDP_COLORDEC|FF_VIDEO_B[5] ; VDP:U20|VDP_COLORDEC:U_VDP_COLORDEC|FF_VIDEO_B[5] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.880 ;
; 0.865 ; wifi:uwifi|out_tx_data[2] ; wifi:uwifi|UART:U1|tx_data_s[2] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.880 ;
; 0.865 ; VDP:U20|VDP_GRAPHIC123M:U_VDP_GRAPHIC123M|FF_PRE_PAT_COL[3] ; VDP:U20|VDP_GRAPHIC123M:U_VDP_GRAPHIC123M|FF_PAT_COL[3] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.880 ;
; 0.865 ; LPF2:u_lpf2|FF_D6[6] ; LPF2:u_lpf2|FF_D7[6] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.880 ;
; 0.865 ; INTERPO:u_interpo|ODATA[3] ; LPF2:u_lpf2|FF_D1[3] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.880 ;
; 0.865 ; LPF2:u_lpf2|FF_D1[2] ; LPF2:u_lpf2|FF_D2[2] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.880 ;
; 0.866 ; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|FF_R2_PT_NAM_ADDR[3] ; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|REG_R2_PT_NAM_ADDR[3] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.881 ;
; 0.866 ; pDac_SR[0]~reg0 ; pDac_SR[0]~reg0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.881 ;
; 0.866 ; wifi:uwifi|out_tx_data[0] ; wifi:uwifi|UART:U1|tx_data_s[0] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.881 ;
; 0.866 ; VDP:U20|VDP_GRAPHIC4567:U_VDP_GRAPHIC4567|LATCHEDPTNNAMETBLBASEADDR[6] ; VDP:U20|VDP_GRAPHIC4567:U_VDP_GRAPHIC4567|PRAMADR[16] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.881 ;
; 0.866 ; eseps2:U06|ff_ps2_clk_delay[1] ; eseps2:U06|ff_ps2_clk_delay[2] ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 0.881 ;
+-------+------------------------------------------------------------------------+-----------------------------------------------------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'PLL4X:U00|altpll:altpll_component|_clk1' ;
+-------+-------------------+-----------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------+-----------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
; 0.886 ; ff_mem_seq[0] ; ff_mem_seq[1] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 0.901 ;
; 1.046 ; FreeCounter[0] ; FreeCounter[0] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.061 ;
; 1.248 ; ff_mem_seq[1] ; FreeCounter[0] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.263 ;
; 1.251 ; ff_mem_seq[1] ; ff_mem_seq[0] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.266 ;
; 1.260 ; ff_reload_n ; ff_reload_n ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.275 ;
; 1.264 ; power_on_reset ; power_on_reset ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.279 ;
; 1.295 ; ff_sdr_seq[0] ; ff_sdr_seq[2] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.310 ;
; 1.309 ; ff_sdr_seq[1] ; ff_sdr_seq[1] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.324 ;
; 1.327 ; FreeCounter[1] ; FreeCounter[1] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.342 ;
; 1.330 ; FreeCounter[6] ; FreeCounter[6] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.345 ;
; 1.331 ; FreeCounter[3] ; FreeCounter[3] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.346 ;
; 1.333 ; SdrSize[0] ; SdrSize[0] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.348 ;
; 1.335 ; SdrSta[2] ; SdrSta[2] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.350 ;
; 1.336 ; FreeCounter[2] ; FreeCounter[2] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.351 ;
; 1.336 ; FreeCounter[8] ; FreeCounter[8] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.351 ;
; 1.340 ; FreeCounter[12] ; FreeCounter[12] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.355 ;
; 1.343 ; FreeCounter[13] ; FreeCounter[13] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.358 ;
; 1.348 ; FreeCounter[11] ; FreeCounter[11] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.363 ;
; 1.376 ; ff_sdr_seq[2] ; ff_sdr_seq[2] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.391 ;
; 1.481 ; FreeCounter[7] ; FreeCounter[7] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.496 ;
; 1.481 ; FreeCounter[9] ; FreeCounter[9] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.496 ;
; 1.486 ; FreeCounter[4] ; FreeCounter[4] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.501 ;
; 1.487 ; FreeCounter[5] ; FreeCounter[5] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.502 ;
; 1.488 ; FreeCounter[14] ; FreeCounter[14] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.503 ;
; 1.491 ; FreeCounter[10] ; FreeCounter[10] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.506 ;
; 1.493 ; FreeCounter[15] ; FreeCounter[15] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.508 ;
; 1.510 ; ff_mem_seq[0] ; FreeCounter[0] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.525 ;
; 1.551 ; ff_sdr_seq[0] ; ff_sdr_seq[0] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.566 ;
; 1.740 ; clkdiv4[2] ; clkdiv4[2] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.755 ;
; 1.802 ; clkdiv4[4] ; clkdiv4[4] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.817 ;
; 1.839 ; ff_sdr_seq[1] ; ff_sdr_seq[2] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.854 ;
; 1.869 ; ff_sdr_seq[0] ; ff_sdr_seq[1] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.884 ;
; 1.916 ; RstSeq[4] ; RstSeq[4] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.931 ;
; 1.926 ; FreeCounter[1] ; FreeCounter[2] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.941 ;
; 1.929 ; FreeCounter[6] ; FreeCounter[7] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.944 ;
; 1.930 ; FreeCounter[3] ; FreeCounter[4] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.945 ;
; 1.935 ; FreeCounter[8] ; FreeCounter[9] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.950 ;
; 1.942 ; FreeCounter[13] ; FreeCounter[14] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.957 ;
; 1.947 ; FreeCounter[11] ; FreeCounter[12] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 1.962 ;
; 1.987 ; ff_clk21m_cnt[19] ; power_on_reset ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk1 ; -0.002 ; 0.000 ; 2.000 ;
; 2.008 ; FreeCounter[3] ; FreeCounter[5] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.023 ;
; 2.013 ; FreeCounter[8] ; FreeCounter[10] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.028 ;
; 2.020 ; FreeCounter[13] ; FreeCounter[15] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.035 ;
; 2.054 ; RstSeq[2] ; RstSeq[2] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.069 ;
; 2.077 ; RstSeq[3] ; RstSeq[3] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.092 ;
; 2.086 ; FreeCounter[3] ; FreeCounter[6] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.101 ;
; 2.090 ; FreeCounter[9] ; FreeCounter[10] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.105 ;
; 2.091 ; FreeCounter[8] ; FreeCounter[11] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.106 ;
; 2.095 ; FreeCounter[4] ; FreeCounter[5] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.110 ;
; 2.096 ; FreeCounter[5] ; FreeCounter[6] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.111 ;
; 2.097 ; FreeCounter[14] ; FreeCounter[15] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.112 ;
; 2.100 ; FreeCounter[10] ; FreeCounter[11] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.115 ;
; 2.102 ; clkdiv4[1] ; clkdiv4[1] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.117 ;
; 2.148 ; FreeCounter[1] ; FreeCounter[3] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.163 ;
; 2.148 ; FreeCounter[1] ; FreeCounter[4] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.163 ;
; 2.148 ; FreeCounter[1] ; FreeCounter[5] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.163 ;
; 2.148 ; FreeCounter[1] ; FreeCounter[6] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.163 ;
; 2.148 ; FreeCounter[1] ; FreeCounter[7] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.163 ;
; 2.151 ; FreeCounter[2] ; FreeCounter[3] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.166 ;
; 2.151 ; FreeCounter[2] ; FreeCounter[4] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.166 ;
; 2.151 ; FreeCounter[2] ; FreeCounter[5] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.166 ;
; 2.151 ; FreeCounter[2] ; FreeCounter[6] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.166 ;
; 2.151 ; FreeCounter[2] ; FreeCounter[7] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.166 ;
; 2.152 ; iSltRst_n ; reset ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk1 ; -0.002 ; 0.000 ; 2.165 ;
; 2.155 ; FreeCounter[12] ; FreeCounter[13] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.170 ;
; 2.155 ; FreeCounter[12] ; FreeCounter[14] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.170 ;
; 2.155 ; FreeCounter[12] ; FreeCounter[15] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.170 ;
; 2.159 ; clkdiv4[3] ; clkdiv4[3] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.174 ;
; 2.159 ; clkdiv4[3] ; clkdiv4[2] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.174 ;
; 2.164 ; FreeCounter[3] ; FreeCounter[7] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.179 ;
; 2.168 ; FreeCounter[9] ; FreeCounter[11] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.183 ;
; 2.169 ; FreeCounter[8] ; FreeCounter[12] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.184 ;
; 2.169 ; FreeCounter[11] ; FreeCounter[13] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.184 ;
; 2.169 ; FreeCounter[11] ; FreeCounter[14] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.184 ;
; 2.169 ; FreeCounter[11] ; FreeCounter[15] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.184 ;
; 2.173 ; FreeCounter[4] ; FreeCounter[6] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.188 ;
; 2.174 ; FreeCounter[5] ; FreeCounter[7] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.189 ;
; 2.178 ; FreeCounter[10] ; FreeCounter[12] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.193 ;
; 2.223 ; RstSeq[1] ; RstSeq[1] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.238 ;
; 2.246 ; FreeCounter[9] ; FreeCounter[12] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.261 ;
; 2.251 ; FreeCounter[4] ; FreeCounter[7] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.266 ;
; 2.282 ; RstSeq[3] ; SdrSta[1] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.297 ;
; 2.290 ; FreeCounter[0] ; FreeCounter[1] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.305 ;
; 2.311 ; FreeCounter[6] ; FreeCounter[8] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.326 ;
; 2.311 ; FreeCounter[6] ; FreeCounter[9] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.326 ;
; 2.311 ; FreeCounter[6] ; FreeCounter[10] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.326 ;
; 2.311 ; FreeCounter[6] ; FreeCounter[11] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.326 ;
; 2.311 ; FreeCounter[6] ; FreeCounter[12] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.326 ;
; 2.312 ; RstSeq[1] ; SdrBa[0] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.327 ;
; 2.324 ; clkdiv4[2] ; clkdiv4[3] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.339 ;
; 2.325 ; RstSeq[3] ; RstSeq[4] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.340 ;
; 2.331 ; RstSeq[4] ; SdrSta[1] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.346 ;
; 2.348 ; ff_sdr_seq[2] ; ff_sdr_seq[0] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.363 ;
; 2.388 ; FreeCounter[6] ; FreeCounter[13] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.403 ;
; 2.388 ; FreeCounter[6] ; FreeCounter[14] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.403 ;
; 2.388 ; FreeCounter[6] ; FreeCounter[15] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.403 ;
; 2.390 ; ff_sdr_seq[1] ; SdrSta[0] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.405 ;
; 2.397 ; FreeCounter[8] ; FreeCounter[13] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.412 ;
; 2.397 ; FreeCounter[8] ; FreeCounter[14] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.412 ;
; 2.397 ; FreeCounter[8] ; FreeCounter[15] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 2.412 ;
+-------+-------------------+-----------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Recovery: 'PLL4X:U00|altpll:altpll_component|_clk1' ;
+-------+-----------+------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------+------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
; 4.436 ; reset ; clkdiv4[0] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.068 ; 7.097 ;
; 4.437 ; reset ; clkdiv4[1] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.068 ; 7.096 ;
; 4.469 ; reset ; clk4mhzb ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; 0.000 ; 7.132 ;
; 5.155 ; reset ; clkdiv4[4] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.068 ; 6.378 ;
; 5.155 ; reset ; clkdiv4[3] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.068 ; 6.378 ;
; 5.155 ; reset ; clkdiv4[2] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 11.638 ; -0.068 ; 6.378 ;
+-------+-----------+------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Recovery: 'PLL4X:U00|altpll:altpll_component|_clk0' ;
+--------+------------------------------------------+-----------------------------------------------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------+-----------------------------------------------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
; 41.613 ; switched_io_ports:U35|forced_v_mode~reg0 ; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|REG_R9_PAL_MODE ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 46.554 ; -0.059 ; 4.845 ;
; 42.827 ; CmtScro ; eseps2:U06|ff_led_scroll_lock ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 46.554 ; 0.041 ; 3.731 ;
; 43.135 ; PpiPortC[6] ; eseps2:U06|ff_led_caps_lock ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 46.554 ; -0.041 ; 3.341 ;
; 43.789 ; switched_io_ports:U35|LastRst_sta~reg0 ; portF4_bit7 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 46.554 ; 0.045 ; 2.773 ;
; 45.079 ; psg:U30|kana ; eseps2:U06|ff_led_kana_lock ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 46.554 ; 0.000 ; 1.438 ;
; 50.960 ; reset ; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|REG_R9_PAL_MODE ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; -0.068 ; 7.129 ;
; 50.976 ; reset ; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|VDPP1IS1STBYTE ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.010 ; 7.191 ;
; 50.980 ; reset ; VDP:U20|VDP_COMMAND:U_VDP_COMMAND|TR ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.008 ; 7.185 ;
; 50.987 ; reset ; VDP:U20|VDP_SSG:U_SSG|IVIDEOVS_N ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; -0.068 ; 7.102 ;
; 50.997 ; reset ; VDP:U20|IRAMADR[0] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; -0.068 ; 7.092 ;
; 50.997 ; reset ; VDP:U20|IRAMADR[2] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; -0.068 ; 7.092 ;
; 50.997 ; reset ; VDP:U20|IRAMADR[3] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; -0.068 ; 7.092 ;
; 50.997 ; reset ; eseps2:U06|ff_ps2_clk~en ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.034 ; 7.194 ;
; 51.001 ; reset ; VDP:U20|VDP_VGA:U_VDP_VGA|FF_VSYNC_N ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; -0.068 ; 7.088 ;
; 51.004 ; reset ; VDP:U20|VDP_INTERRUPT:U_INTERRUPT|FF_HSYNC_INT_N ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; -0.068 ; 7.085 ;
; 51.004 ; reset ; VDP:U20|VDP_INTERRUPT:U_INTERRUPT|FF_VSYNC_INT_N ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; -0.068 ; 7.085 ;
; 51.006 ; reset ; VDP:U20|IRAMADR[16] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.000 ; 7.151 ;
; 51.006 ; reset ; VDP:U20|IRAMADR[15] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.000 ; 7.151 ;
; 51.006 ; reset ; VDP:U20|IRAMADR[7] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.000 ; 7.151 ;
; 51.008 ; reset ; VDP:U20|PRAMWE_N ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; -0.068 ; 7.081 ;
; 51.015 ; reset ; iSltDat[6] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; -0.068 ; 7.074 ;
; 51.018 ; reset ; VDP:U20|IRAMADR[11] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; -0.067 ; 7.072 ;
; 51.018 ; reset ; VDP:U20|IRAMADR[13] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; -0.067 ; 7.072 ;
; 51.018 ; reset ; VDP:U20|IRAMADR[14] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; -0.067 ; 7.072 ;
; 51.018 ; reset ; VDP:U20|IRAMADR[10] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; -0.067 ; 7.072 ;
; 51.021 ; reset ; PpiPortA[4] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.083 ; 7.219 ;
; 51.021 ; reset ; PpiPortA[2] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.083 ; 7.219 ;
; 51.023 ; reset ; iSltDat[2] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; -0.068 ; 7.066 ;
; 51.025 ; reset ; clk4mhz ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.000 ; 7.132 ;
; 51.025 ; reset ; hybridclk_n ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.000 ; 7.132 ;
; 51.031 ; reset ; PpiPortA[0] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.083 ; 7.209 ;
; 51.031 ; reset ; PpiPortA[6] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.083 ; 7.209 ;
; 51.031 ; reset ; megasd:U03|ff_send_data[7] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.083 ; 7.209 ;
; 51.031 ; reset ; dlydbi[0] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.083 ; 7.209 ;
; 51.031 ; reset ; dlydbi[1] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.083 ; 7.209 ;
; 51.031 ; reset ; megasd:U03|ff_send_data[6] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.083 ; 7.209 ;
; 51.031 ; reset ; VDP:U20|VDP_VGA:U_VDP_VGA|FF_HSYNC_N ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; -0.068 ; 7.058 ;
; 51.031 ; reset ; megasd:U03|ff_send_data[5] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.083 ; 7.209 ;
; 51.031 ; reset ; megasd:U03|ff_send_data[4] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.083 ; 7.209 ;
; 51.034 ; reset ; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|VDPP2IS1STBYTE ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.000 ; 7.123 ;
; 51.038 ; reset ; dlydbi[7] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.083 ; 7.202 ;
; 51.038 ; reset ; eseps2:U06|ff_key_x[4] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.083 ; 7.202 ;
; 51.038 ; reset ; eseps2:U06|ff_key_x[5] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.083 ; 7.202 ;
; 51.039 ; reset ; iSltDat[5] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.076 ; 7.194 ;
; 51.039 ; reset ; VDP:U20|VDP_SPRITE:U_SPRITE|FF_SP_OVERMAP_NUM[0] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.000 ; 7.118 ;
; 51.039 ; reset ; VDP:U20|VDP_SPRITE:U_SPRITE|FF_SP_OVERMAP_NUM[1] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.000 ; 7.118 ;
; 51.039 ; reset ; VDP:U20|VDP_SPRITE:U_SPRITE|FF_SP_OVERMAP_NUM[2] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.000 ; 7.118 ;
; 51.039 ; reset ; VDP:U20|VDP_SPRITE:U_SPRITE|FF_SP_OVERMAP_NUM[3] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.000 ; 7.118 ;
; 51.039 ; reset ; VDP:U20|VDP_SPRITE:U_SPRITE|FF_SP_OVERMAP_NUM[4] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.000 ; 7.118 ;
; 51.040 ; reset ; iSltAdr[6] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.083 ; 7.200 ;
; 51.040 ; reset ; iSltAdr[5] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.083 ; 7.200 ;
; 51.040 ; reset ; iSltAdr[4] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.083 ; 7.200 ;
; 51.040 ; reset ; iSltAdr[2] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.083 ; 7.200 ;
; 51.040 ; reset ; iSltAdr[3] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.083 ; 7.200 ;
; 51.040 ; reset ; iSltAdr[7] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.083 ; 7.200 ;
; 51.040 ; reset ; VDP:U20|IRAMADR[4] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.000 ; 7.117 ;
; 51.040 ; reset ; VDP:U20|IRAMADR[5] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.000 ; 7.117 ;
; 51.040 ; reset ; VDP:U20|IRAMADR[6] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.000 ; 7.117 ;
; 51.040 ; reset ; VDP:U20|IRAMADR[8] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.000 ; 7.117 ;
; 51.040 ; reset ; VDP:U20|IRAMADR[9] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.000 ; 7.117 ;
; 51.041 ; reset ; iSltDat[1] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; -0.067 ; 7.049 ;
; 51.041 ; reset ; psg:U30|psg_wave:u_psgch|PsgShapeEnv[0] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.069 ; 7.185 ;
; 51.041 ; reset ; psg:U30|psg_wave:u_psgch|PsgShapeEnv[3] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.069 ; 7.185 ;
; 51.044 ; reset ; iSltDat[7] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.069 ; 7.182 ;
; 51.044 ; reset ; iSltAdr[11] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.073 ; 7.186 ;
; 51.044 ; reset ; iSltAdr[10] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.073 ; 7.186 ;
; 51.045 ; reset ; iSltAdr[0] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.083 ; 7.195 ;
; 51.045 ; reset ; ExpSlot3[5] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.083 ; 7.195 ;
; 51.045 ; reset ; ExpSlot3[3] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.083 ; 7.195 ;
; 51.045 ; reset ; ExpSlot3[1] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.083 ; 7.195 ;
; 51.045 ; reset ; ExpSlot3[0] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.083 ; 7.195 ;
; 51.045 ; reset ; dlydbi[4] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.083 ; 7.195 ;
; 51.045 ; reset ; dlydbi[6] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.083 ; 7.195 ;
; 51.050 ; reset ; iSltDat[0] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; -0.005 ; 7.102 ;
; 51.051 ; reset ; VDP:U20|IRAMADR[12] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.083 ; 7.189 ;
; 51.051 ; reset ; VDP:U20|IRAMADR[1] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.083 ; 7.189 ;
; 51.055 ; reset ; iSltDat[3] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.008 ; 7.110 ;
; 51.055 ; reset ; iSltDat[4] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.008 ; 7.110 ;
; 51.055 ; reset ; eseps2:U06|ff_led_caps_lock ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.032 ; 7.134 ;
; 51.055 ; reset ; eseps2:U06|ff_led_kana_lock ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.032 ; 7.134 ;
; 51.055 ; reset ; eseps2:U06|ff_led_scroll_lock ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.032 ; 7.134 ;
; 51.055 ; reset ; dlydbi[2] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.083 ; 7.185 ;
; 51.055 ; reset ; dlydbi[3] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.083 ; 7.185 ;
; 51.055 ; reset ; dlydbi[5] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.083 ; 7.185 ;
; 51.055 ; reset ; tr_pcm:U40|ff_da0[5] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.008 ; 7.110 ;
; 51.055 ; reset ; tr_pcm:U40|ff_da0[4] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.008 ; 7.110 ;
; 51.055 ; reset ; tr_pcm:U40|ff_da0[3] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.008 ; 7.110 ;
; 51.056 ; reset ; iSltMerq_n ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.032 ; 7.133 ;
; 51.056 ; reset ; iSltRfsh_n ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.032 ; 7.133 ;
; 51.057 ; reset ; iSltAdr[14] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.073 ; 7.173 ;
; 51.057 ; reset ; PpiPortA[5] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.073 ; 7.173 ;
; 51.057 ; reset ; PpiPortA[3] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.073 ; 7.173 ;
; 51.057 ; reset ; PpiPortA[1] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.073 ; 7.173 ;
; 51.057 ; reset ; PpiPortA[7] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.073 ; 7.173 ;
; 51.058 ; reset ; psg:U30|psg_wave:u_psgch|PsgFreqChB[8] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.069 ; 7.168 ;
; 51.058 ; reset ; psg:U30|psg_wave:u_psgch|PsgFreqChC[8] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.079 ; 7.178 ;
; 51.058 ; reset ; psg:U30|psg_wave:u_psgch|PsgFreqChB[9] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.069 ; 7.168 ;
; 51.058 ; reset ; psg:U30|psg_wave:u_psgch|PsgFreqChB[1] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.073 ; 7.172 ;
; 51.058 ; reset ; psg:U30|psg_wave:u_psgch|PsgFreqChC[9] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.079 ; 7.178 ;
; 51.058 ; reset ; psg:U30|psg_wave:u_psgch|PsgFreqChB[10] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 58.194 ; 0.069 ; 7.168 ;
+--------+------------------------------------------+-----------------------------------------------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Removal: 'PLL4X:U00|altpll:altpll_component|_clk0' ;
+-------+------------------------------------------+-----------------------------------------------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------+-----------------------------------------------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
; 1.423 ; psg:U30|kana ; eseps2:U06|ff_led_kana_lock ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.000 ; 1.438 ;
; 2.713 ; switched_io_ports:U35|LastRst_sta~reg0 ; portF4_bit7 ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.045 ; 2.773 ;
; 3.367 ; PpiPortC[6] ; eseps2:U06|ff_led_caps_lock ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; -0.041 ; 3.341 ;
; 3.675 ; CmtScro ; eseps2:U06|ff_led_scroll_lock ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; 0.041 ; 3.731 ;
; 4.889 ; switched_io_ports:U35|forced_v_mode~reg0 ; VDP:U20|VDP_REGISTER:U_VDP_REGISTER|REG_R9_PAL_MODE ; PLL4X:U00|altpll:altpll_component|_clk0 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.000 ; -0.059 ; 4.845 ;
; 4.985 ; power_on_reset ; esepwm:U33|DACout ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; esepwm:U33|Acu[13] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; esepwm:U33|Acu[12] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; esepwm:U33|esefir5:U1|ff_sum[21] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; esepwm:U33|esefir5:U1|ff_state[0] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; esepwm:U33|esefir5:U1|ff_state[1] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; esepwm:U33|esefir5:U1|ff_state[2] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; esepwm:U33|Acu[11] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; esepwm:U33|Acu[10] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; esepwm:U33|esefir5:U1|ff_sum[19] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; esepwm:U33|Acu[9] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; esepwm:U33|esefir5:U1|ff_sum[18] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; esepwm:U33|Acu[8] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; esepwm:U33|esefir5:U1|ff_sum[17] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; esepwm:U33|Acu[7] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_OUT[13] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_OUT[12] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_OUT[11] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_OUT[10] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_OUT[9] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_OUT[8] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_OUT[7] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_OUT[6] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_OUT[5] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_OUT[4] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_OUT[3] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_OUT[2] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; esepwm:U33|esefir5:U1|ff_sum[7] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_OUT[1] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; esepwm:U33|esefir5:U1|ff_sum[6] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_OUT[0] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; esepwm:U33|esefir5:U1|ff_sum[5] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; esepwm:U33|esefir5:U1|ff_sum[4] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; esepwm:U33|esefir5:U1|ff_sum[3] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; esepwm:U33|esefir5:U1|ff_sum[2] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; esepwm:U33|esefir5:U1|ff_sum[1] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; esepwm:U33|esefir5:U1|ff_sum[0] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; esepwm:U33|esefir5:U1|ff_wavout[13] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; esepwm:U33|esefir5:U1|ff_wavout[12] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; esepwm:U33|esefir5:U1|ff_wavout[11] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; esepwm:U33|esefir5:U1|ff_wavout[10] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; esepwm:U33|esefir5:U1|ff_wavout[9] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; esepwm:U33|esefir5:U1|ff_wavout[8] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; esepwm:U33|esefir5:U1|ff_wavout[7] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; esepwm:U33|esefir5:U1|ff_wavout[5] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; esepwm:U33|esefir5:U1|ff_wavout[3] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D1[13] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D2[13] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D3[13] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D4[13] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D5[13] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D6[13] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D7[13] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D8[13] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; esepwm:U33|esefir5:U1|ff_wavout[1] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D1[12] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D2[12] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D3[12] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D4[12] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D5[12] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D6[12] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D7[12] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; INTERPO:u_interpo|ODATA[13] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D8[12] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; esepwm:U33|esefir5:U1|ff_wavout[0] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D1[11] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D2[11] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D3[11] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D4[11] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D5[11] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D6[11] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D7[11] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; INTERPO:u_interpo|ODATA[12] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D8[11] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; INTERPO:u_interpo|ODATA[11] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D8[10] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D1[9] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D2[9] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D3[9] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D4[9] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D5[9] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D6[9] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D7[9] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; INTERPO:u_interpo|ODATA[10] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D8[9] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D1[8] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D2[8] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D3[8] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D4[8] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D5[8] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D6[8] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D7[8] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; INTERPO:u_interpo|ODATA[9] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D8[8] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
; 4.985 ; power_on_reset ; LPF2:u_lpf2|FF_D1[7] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk0 ; 0.002 ; 0.008 ; 5.010 ;
+-------+------------------------------------------+-----------------------------------------------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Removal: 'PLL4X:U00|altpll:altpll_component|_clk1' ;
+-------+-----------+------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------+------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
; 6.431 ; reset ; clkdiv4[4] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; -0.068 ; 6.378 ;
; 6.431 ; reset ; clkdiv4[3] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; -0.068 ; 6.378 ;
; 6.431 ; reset ; clkdiv4[2] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; -0.068 ; 6.378 ;
; 7.117 ; reset ; clk4mhzb ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; 0.000 ; 7.132 ;
; 7.149 ; reset ; clkdiv4[1] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; -0.068 ; 7.096 ;
; 7.150 ; reset ; clkdiv4[0] ; PLL4X:U00|altpll:altpll_component|_clk1 ; PLL4X:U00|altpll:altpll_component|_clk1 ; 0.000 ; -0.068 ; 7.097 ;
+-------+-----------+------------+-----------------------------------------+-----------------------------------------+--------------+------------+------------+
+-----------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'PLL4X:U00|altpll:altpll_component|_clk1' ;
+-------+--------------+----------------+------------------+-----------------------------------------+------------+-----------------+
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
+-------+--------------+----------------+------------------+-----------------------------------------+------------+-----------------+
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; FreeCounter[0] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; FreeCounter[0] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; FreeCounter[10] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; FreeCounter[10] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; FreeCounter[11] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; FreeCounter[11] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; FreeCounter[12] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; FreeCounter[12] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; FreeCounter[13] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; FreeCounter[13] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; FreeCounter[14] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; FreeCounter[14] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; FreeCounter[15] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; FreeCounter[15] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; FreeCounter[1] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; FreeCounter[1] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; FreeCounter[2] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; FreeCounter[2] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; FreeCounter[3] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; FreeCounter[3] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; FreeCounter[4] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; FreeCounter[4] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; FreeCounter[5] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; FreeCounter[5] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; FreeCounter[6] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; FreeCounter[6] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; FreeCounter[7] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; FreeCounter[7] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; FreeCounter[8] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; FreeCounter[8] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; FreeCounter[9] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; FreeCounter[9] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; RamDbi[0] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; RamDbi[0] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; RamDbi[1] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; RamDbi[1] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; RamDbi[2] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; RamDbi[2] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; RamDbi[3] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; RamDbi[3] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; RamDbi[4] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; RamDbi[4] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; RamDbi[5] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; RamDbi[5] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; RamDbi[6] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; RamDbi[6] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; RamDbi[7] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; RamDbi[7] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; RstSeq[0] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; RstSeq[0] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; RstSeq[1] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; RstSeq[1] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; RstSeq[2] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; RstSeq[2] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; RstSeq[3] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; RstSeq[3] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; RstSeq[4] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; RstSeq[4] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrAdr[0] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrAdr[0] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrAdr[10] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrAdr[10] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrAdr[11] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrAdr[11] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrAdr[1] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrAdr[1] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrAdr[2] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrAdr[2] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrAdr[3] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrAdr[3] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrAdr[4] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrAdr[4] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrAdr[5] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrAdr[5] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrAdr[6] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrAdr[6] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrAdr[7] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrAdr[7] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrAdr[8] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrAdr[8] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrAdr[9] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrAdr[9] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrBa[0] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrBa[0] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrBa[1] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrBa[1] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrCmd[0] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrCmd[0] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrCmd[1] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrCmd[1] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrCmd[2] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrCmd[2] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrDat[0] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrDat[0] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrDat[0]~en ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrDat[0]~en ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrDat[10] ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrDat[10] ;
; 4.001 ; 5.819 ; 1.818 ; High Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrDat[10]~en ;
; 4.001 ; 5.819 ; 1.818 ; Low Pulse Width ; PLL4X:U00|altpll:altpll_component|_clk1 ; Rise ; SdrDat[10]~en ;
+-------+--------------+----------------+------------------+-----------------------------------------+------------+-----------------+