README

This directory contains the model generator for Gnucap

== Summary

Gnucap is a modular mixed-signal circuit simulator that partially implements
Verilog-AMS, that aspires to eventually implement the complete language. This
package adds support for the behavioural modelling section.

== Funding

This project is funded through the NGI0 Entrust Fund, a fund established by
NLnet with financial support from the European Commission's Next Generation
Internet programme, under the aegis of DG Communications Networks, Content and
Technology under grant agreement No 101069594.

https://nlnet.nl/project/Gnucap-VerilogAMS/
https://nlnet.nl/project/Gnucap-MixedSignals/

== Preliminaries

Modelgen-verilog snapshots require Gnucap tagged at the same date, or latest
since. Generally develop branch may only work with Gnucap develop branch.

== Build instructions

To build the package, install Gnucap and type

$ cd some_empty_directory
$ $OLDPWD/configure
$ make # tested with GNU Make.

Alternatively, move the modelgen-verilog source directory into the Gnucap
source directory, and build Gnucap following the instructions there.

== Tests

Type "make check" to build and run regression tests.
see tests/README

== Installation

To install the package, type

$ make install

Files will end up in the directories configured in the main package. A
separate prefix option is planned.

== General use

Modelgen-verilog preprocesses, parses and dumps vams files.

$ modelgen-verilog { -I path -D def .. } --dump some_file.vams > some_file.dump

To emit C++ code for use with Gnucap, type

$ modelgen-verilog { -I path -D def .. } --cc some_file.vams > some_file.cc

or

$ modelgen-verilog { -I path -D def .. } -o some_file.cc --cc some_file.vams.

Compile and link the output into Gnucap plugin

$ c++ -fPIC -I path_to/include some_file.cc -o some_file.o -c
$ c++ -shared  some_file.o -o some_file.so

Load into Gnucap

$ gnucap -a ./some_file.so
gnucap> [..]

or

$ gnucap
gnucap> load ./some_file
gnucap> [..]

== Preprocessor notes

- modelgen-verilog { -o output -I path -D def .. } --pp file
- `include "quoted" works simlar to quoted C #include.
- -I sets include path.
- -D defines a symbol. Assign a value with -D"VARIABLE value"..
- -o sets output path.
- Files are located following logic from gcc implementation.
- Output is sent to standard out, unless -o is specified earlier.

== Language plugin note

This package ships a modified/experimental lang_verilog plugin.
To make use of new language features in the simulator, load it.
$ gnucap -a vams/lang_verilog.so
or
gnucap > load vams/lang_verilog.so

== Header note

We use the free discipline.vams header from the ADMS project. Similarly the
included constants.vams header is based on constants.h from Gnucap and equally
free. Using restricted versions is not recommended, but possible. Invoke
modelgen with "-I/path/to/non-free/stuff".

== LICENSE

All code in this package is licensed under GPL 3 or any later version.

Any modelgen-verilog output is subject to the same license as the input. In
addition, binaries compiled from unmodified modelgen-verilog output against
unmodified Gnucap headers using unmodified gcc are subject to the license(s)
of the Verilog input used only.