Can we avoid changing XLS module port source to _source? #3888
Description
Describe the bug
Previously, DSLX code could define a module boundary port named source. When Verilog was emitted, the port name remained source, which worked correctly.
At some point in the past few months, this behavior changed, and the emitted name is now _source.
After investigating, it appears this renaming may be occurring because source is treated as a keyword in the XLS IR. However, it is unclear that this renaming is necessary at the Verilog boundary. By the time IR is generated, the DSLX source has already been parsed and identifiers are structurally disambiguated, so IR keywords would not seem to require rewriting user-visible identifiers during Verilog emission.
This change is also breaking for downstream users: updating XLS versions required corresponding updates to existing SystemVerilog integrations. (Understood that strict API compatibility may not be guaranteed — this is simply reporting user impact.)
From a user perspective, the change is surprising. Code is written using the identifier source, but integration at the Verilog level now requires connecting to a differently named port (_source) without an obvious external reason.
Additionally, this introduces nonstandard port naming that requires lint waivers in downstream flows.
I would even generalize this beyond 'source' to the other XLS IR keywords.
Expected behavior
The emitted Verilog port name should remain source.
If the renaming is required internally due to IR keyword constraints, would it be possible either to preserve the original identifier at the Verilog boundary or to make this behavior configurable? Thanks.