gateware.usb2.endpoints: use amaranth.lib.streams for isochronous endpoints

Author: antoinevg

luna/gateware/stream/future.py

@@ -0,0 +1,18 @@
+#
+# This file is part of LUNA.
+#
+# Copyright (c) 2025 Great Scott Gadgets <info@greatscottgadgets.com>
+# SPDX-License-Identifier: BSD-3-Clause
+
+""" Core stream definitions for supporting native Amaranth 0.5 streams. """
+
+from amaranth      import *
+from amaranth.lib  import data
+
+class Packet(data.StructLayout):
+    def __init__(self, data_layout, first=True, last=True):
+        sig = (first and { "first": unsigned(1) } or {}) \
+            | (last  and { "last":  unsigned(1) } or {})
+        super().__init__(sig | {
+            "data": data_layout
+        })

luna/gateware/usb/usb2/endpoints/isochronous_in.py

@@ -9,11 +9,10 @@
 interfaces to hosts via isochronous pipes.
 """
 
-from amaranth             import Elaboratable, Module, Signal, unsigned
-# TODO from amaranth.lib         import stream
+from amaranth      import *
+from amaranth.lib  import stream
 
-from ..endpoint           import EndpointInterface
-from ...stream            import StreamInterface # TODO
+from ..endpoint    import EndpointInterface
 
 
 class USBIsochronousStreamInEndpoint(Elaboratable):
@@ -69,10 +68,7 @@ def __init__(self, *, endpoint_number, max_packet_size):
         # I/O Port
         #
         self.interface      = EndpointInterface()
-        # TODO self.stream         = stream.Interface(
-        #     stream.Signature(unsigned(8))
-        # )
-        self.stream    = StreamInterface()
+        self.stream         = stream.Interface(stream.Signature(unsigned(8)))
         self.data_requested = Signal()
         self.frame_finished = Signal()
 

luna/gateware/usb/usb2/endpoints/isochronous_out.py

@@ -10,11 +10,14 @@
 interfaces to hosts via isochronous pipes.
 """
 
-from amaranth       import Elaboratable, Module, Signal
+from amaranth              import *
+from amaranth.lib          import stream, wiring
+from amaranth.lib .wiring  import In, Out
 
-from ..endpoint     import EndpointInterface
-from ...stream      import StreamInterface, USBOutStreamBoundaryDetector
-from ....memory     import TransactionalizedFIFO
+from ..endpoint            import EndpointInterface
+from ...stream             import USBOutStreamBoundaryDetector
+from ....stream.future     import Packet
+from ....memory            import TransactionalizedFIFO
 
 
 class USBIsochronousStreamOutEndpoint(Elaboratable):
@@ -52,9 +55,15 @@ def __init__(self, *, endpoint_number, max_packet_size, buffer_size=None):
         #
         # I/O port
         #
-        self.stream    = StreamInterface()
+        self.stream = stream.Interface(
+            stream.Signature(
+                Packet(unsigned(8))
+            )
+        )
         self.interface = EndpointInterface()
 
+        self.busy      = Signal()
+        self.byteclk   = Signal()
 
     def elaborate(self, platform):
         m = Module()
@@ -125,17 +134,17 @@ def elaborate(self, platform):
 
             # Our stream data always comes directly out of the FIFO; and is valid
             # whenever our FIFO actually has data for us to read.
-            stream.valid      .eq(~fifo.empty),
-            stream.payload    .eq(fifo.read_data[0:8]),
+            stream.valid        .eq(~fifo.empty),
+            stream.p.data       .eq(fifo.read_data[0:8]),
 
             # Our `last` bit comes directly from the FIFO; and we know a `first` bit immediately
             # follows a `last` one.
-            stream.last       .eq(fifo.read_data[8]),
-            stream.first      .eq(fifo.read_data[9]),
+            stream.p.last        .eq(fifo.read_data[8]),
+            stream.p.first       .eq(fifo.read_data[9]),
 
             # Move to the next byte in the FIFO whenever our stream is advaced.
-            fifo.read_en      .eq(stream.ready),
-            fifo.read_commit  .eq(1)
+            fifo.read_en         .eq(stream.ready),
+            fifo.read_commit     .eq(1)
         ]
 
         # Count bytes in packet.
@@ -155,4 +164,11 @@ def elaborate(self, platform):
             m.d.usb += overflow.eq(0)
             m.d.usb += rx_cnt.eq(0)
 
+        # Debug
+        last_cnt = Signal.like(rx_cnt)
+        m.d.comb += self.busy.eq(rx_cnt != 0)
+        m.d.usb += last_cnt.eq(rx_cnt)
+        with m.If(last_cnt != rx_cnt):
+            m.d.usb += self.byteclk.eq(~self.byteclk)
+
         return m