To implement

[gustavonmartins]

• U lui
• U auipc
• J jal
• I jalr
• B beq
• B bne
• B blt
• B bge
• B bltu
• B bgeu
• I lb
• I lh
• I lw
• I lbu
• I lhu
• S sb
• S sh
• S sw
• I addi
• I slti
• I sltiu
• I xori
• I ori
• I andi
• I slli
• I srli
• I srai
• R add
• R sub
• R sll
• R slt
• R sltu
• R xor
• R srl
• R sra
• R or
• R and
• I fence
• I fence.i
• I ecall
• I ebreak
• I csrrw
• I csrrs
• I csrrc
• I csrrwi
• I csrrsi
• I csrrci

Currently, the memory of FPGA is not being used. The SoC is using LUTs as its memory, so more LUTs are being used than avaiable. It is needed to start using FPGA memory. For this to be done properly, I have to stop reading and writing memory on the same clock cycle: I will have to use one cycle to read and another to write. This implies that I will have to execute each instruction across many cycles, so a finite state machine is needed.

• Implement instructions to be done in multi-cycles using a FSM so that the SoC memory really uses FPGA's memory instead of LUTs