diff --git a/BUILDING b/BUILDING deleted file mode 100644 index 082c59838..000000000 --- a/BUILDING +++ /dev/null @@ -1,172 +0,0 @@ -------------------------------------------------------------------------------- - - - Building Hercules - - -If you are wanting to build the Windows version of Hercules refer to the -README.WIN64 document for detailed instructions. - -As for non-Windows *nix builds, if you're simply trying to figure out how to -build Hercules from the distributed source tarball (i.e. NOT from the source -directly pulled from the repository), then skip to the "Building Hercules" -section further below. - - ------------------- - BUILD PREPARATION - ------------------- - - -In order to build Hercules from the repository sources, you must have -installed the minimum versions of the development packages as reported -by the 'bldlvlck' script in the 'util' subdirectory: - - - Note: the below listed versions may not be correct; - please run the 'util/bldlvlck' script for the - most current list of minimum versions. - - - Package Version (or greater!) - ---------------------------------- - autoconf 2.64 (or greater!) - automake 1.9 (or greater!) - flex 2.5 (or greater!) - gawk 3.0 (or greater!) - gcc 3.0 (or greater!) - grep 1.0 (or greater!) - m4 1.4.6 (or greater!) - make 3.79 (or greater!) - perl 5.6 (or greater!) - sed 3.02 (or greater!) - - -The following package(s) is(are) optional - - Package Version (or greater!) - ---------------------------------- - libgcrypt 0.4.4 (or greater!) (for z990 crypto instructions) - zlib ? (for ZLIB compression) - libbz2 ? (for BZIP2 compression) - - -* If an optional package is not installed, the resulting build may lack - an optional feature, but should be usable otherwise. - -All of these tools can be found at www.gnu.org in source code form, and -are also widely available in packaged form (RPM, DEB, Solaris packages, -etc.). - -Once you have the minimum versions of all of the above tools installed, -simply enter the following command: - - sh ./autogen.sh - -This will, among other things, create you a shell script called "configure". -The resulting configure script (created by the above 'autogen' command) is -then what you use to build Hercules with. (It will probably create a bunch -of other directories and files too, but we're mostly concerned about the -configure script). - - - ------------------- - BUILDING HERCULES - ------------------- - - -Now that a 'configure' script has been built for us, let's use it! :) - -(Note: if you're simply trying to build Hercules from the distributed -tarball (i.e. NOT directly from the pulled respository sources), then just -use the 'configure' script that should have been included with the source -distribution tarball.) - - +------------------------------------------------------------+ - | | - | ** NOTE ** | - | | - | See also refer to instructions in the BUILD PREPARATION | - | section above regarding the 'bldlvlck' script which can | - | be used to check to see if you have all of the required | - | packages installed or not to build Hercules from source. | - | | - +------------------------------------------------------------+ - -Before you trying using the configure script, you may wish to review -the information in the INSTALL file. It contains generic installation -instructions for how to build/install most any package. The instructions -there pertain just as much to Hercules as they do to any other package. - -Since the information there is pretty detailed however, rather than try -to slog your way through it all, you may wish to first review the below -summarized version first. - -Briefly, the way you build Herc is to first "configure" the building -process and then invoke your pre-configured building process. The build -process basically consists of a 'make' command which processes a 'makefile'. -The makfile however needs to be customized for your system. That's what -the "configure" script does. It contructs a customized makefile and that -is what is meant by "configuring your building process". - - -Here's the entire build process step-by-step: - - - To build Herc, first switch to the directory where the source files - are: - - cd hercules - - If you are building directly from repository source, it is a good - habit to always recreate the configure script each time you build: - - sh ./autogen.sh - - configure your build options by entering the following command: - - ./configure ... - - (Note: you may or may not wish to enter additional parameters - to the configure command. See further below) - - Then simply invoke your pre-configured build process by entering - the following command: - - make - - That's it! The 'make' command should build Hercules for you. After - it's been built, you may or may not wish to "install" it. - - To "install" Hercules into the default package installation - directory after building it, enter the following command: - - make install - - That will copy the just built binaries to their proper place. - - To uninstall Hercules once it's been installed, simply enter the - command: - - make uninstall - - and the previously copied files will be removed (deleted). - - -Note: you may or may not wish to add some additional parameters to -the above mentioned "configure" command. One of the more common ones -for those who are building Herc under Cygwin is "--enable-fthreads". -Enter "./configure --help" for more information regarding the various -parameters that Hercules's customized "configure" script supports -for building Hercules. - - --- -original author: -Matt Zimmerman -08 Oct, 2001 - - -Updated by many others over the course of time of course. -Refer to repository commit log if you're that interested. - -------------------------------------------------------------------------------- diff --git a/BUILDING.txt b/BUILDING.txt new file mode 100644 index 000000000..df1e4a6e6 --- /dev/null +++ b/BUILDING.txt @@ -0,0 +1,233 @@ +----------------------------------------------------------------------- + + + Building Hercules + +Copyright 2016 by Stephen R. Orso. This work is licensed under the Creative +Commons Attribution-ShareAlike 4.0 International License. To view a copy of +this license, visit http://creativecommons.org/licenses/by-sa/4.0/ or send +a letter to Creative Commons, PO Box 1866, Mountain View, CA 94042, USA. + + +To build Hercules from source, perform the following steps: + +1. Ensure your computer has the required versions of the software + packages needed to build Hercules. + +2. Install any of the optional packages you wish to use with Hercules. + +3. Build the recommended directory structure for a Hercules build + +4. Obtain SoftFloat 3a For Hercules and build it using the instructions + included with that package. A pre-built set of binaries exists for + Windows. + +5. Obtain and build Hercules using the README specific to your + platform. + + +Please Note: UNIX-like operating systems, including descendants of +AT&T System V UNIX, GNU/Linux, BSD, and OS/X, are collectively referred +in these readme files as "UNIX." While The Open Group owns the +trademark to UNIX and has several pages describing how that trademark +may be used, it would be wise of The Open Group to remember two words: + + kleenex and ketchup. + + +REQUIRED SOFTWARE PACKAGES + + The required packages vary by host system type, UNIX or Windows. + + UNIX: You will need the packages required to configure, compile, + link, and install a C application. Either gcc or clang may be + used. You will also need automake, autoconf, and a few other + utilities. README.BuildUNIX provides details about the packages + and versions required. Most required packages are available with + many UNIX distributions, but you may need to build from source to + get the version you require. + + Windows: You will need Visual Studio 2015 Community Edition, an + appropriate Windows Software Development Kit (SDK), and the file + win32.mak from the Windows 7.1 SDK. README.BuildWIN has + specifics, URLs to obtain the needed software, and instructions + for installing win32.mak. + + Both UNIX and Windows: You will need CMake to build Softfloat 3a For + Hercules, and Windows builders will need it to build the PCRE + package. Version 3.2.0 or higher is required. + + +OPTIONAL SOFTWARE PACKAGES + + REXX interpreters + + You must install a REXX interpreter if you plan to do any of the + following: + + - Use runtest - to run one or more Hercules test scripts from + the tests directory. + - (UNIX) perform a "make check" after the build. + - Use REXX program files in RC scripts, on the Hercules console, + or in the configuration file. All of these are described + in chapter 14 of the Hercules - User Reference Guide for + Version 4.00. + + If you are not sure, install one or both REXX interpreters if your + host system does not have one of them installed already. Your + choices are: + + - ooRexx: Open Object REXX, an open source derivative of a subset + of the IBM program product Object REXX. Find it at: + + http://ooRexx.org + + - Regina Rexx, an open source REXX interpreter that may be found + here: + + http://regina-rexx.sourceforge.net/index.html + + Source and installable executables are available for Windows and + many UNIX distributions. + + Disk and Tape Compression Libraries + + To reduce storage requirements, emulated disk and tape volumes may + compressed on the fly. Compression has its own disk space versus + system performance trade-off, and you are in the best position to + decide whether to compress volumes. + + For file and volume interchange purposes, it is recommended that + you instal both compression libraries and enable their use when + building Hercules. Even if you do not compress the volumes you + use with Hercules, having the capability lets you work with a + compressed voluem you may have received from someone else. + + Note that tape volume compression is specified in the HETINIT host + command that creates the emulated tape, and the compression type, + bzip2 or zlib, is specified in the Hercules command devinit or + attach. Disk volume compression is specified exclusively in the + DASDINIT host command that initialized the emulated disk. + + Note also that a few of the test scripts specifically test + compression, so a Hercules built without compression will cause + those tests to fail. + + Either or both of of the following compression libraries can be + used with Hercules. + + - zlib: Can be used by Hercules to compress both disk and tape + volumes. Available in the software repositories for many + UNIX distributions. Obtain source at: + + http://www.zlib.net + + - libbz2 Can be used by Hercules to compress both disk and tape + volumes. Available in the software repositories for many + UNIX distributions. Obtain source at: + + http://www.bzip.org/ + + (Windows only) Perl Compatible Regular Expression Support + + If you are building on Windows and plan to use the Hercules + Automated Operator (HAO) capability, you must install the PCRE + package to provide regular expression support for HAO. + + On UNIX systems, the Hercules Automated Operator uses the regular + expression support built into the host system. + + You can obtain PCRE here: + + http://www.airesoft.co.uk/pcre + + Download version 8.20. + + +RECOMMENDED DIRECTORY STRUCTURE + + The following recommended directory structure is used for an + out-of-source build for UNIX. (Windows is built in-source, but + all build activities are in directories separate from the Hercules + source and distribution materials.) + + /hyperion/ # Hyperion source (see Note 1.) + /winbuild/ # Windows-only: support packages + /SoftFloat-3a # SoftFloat 3a For Hercules source + //hyperion/ # Hyperion build/install directory + //s3fh # S3FH install dir + # ..includes copyright notices + //s3fh/lib # contains S3FH s3fhFloat.lib + //s3fh/include # contains S3FH public headers + //s3fh.release # S3FH Release build dir + //s3fh.debug # S3FH Debug build dir + + Nonce error for UNIX users: the current development state of + the UNIX build process does not allow for builds using other than + the above structure. This will be addressed. + + Windows users will need to turn the slashes the other way. + + The winbuild directory is the top of a tree containing three packages + commonly available in UNIX but which must be installed for Hercules + on Windows. + + can be anything you wish, but Hercules is suggested. This + directory can be placed anywhere you have read-write permissions, + consistent with common sense and the requirements of your host + system. + + Replace as follows: + - Windows: You must use the value of the %PROCESSOR-ARCHITECTURE% + environment variable. If you do not, you will need to follow + the instructions in README.BuildWIN to point the build process at + the SoftFloat 3a For Hercules Library. + - UNIX: It is recommended but not required to use the value returned + by uname -m. + + Other directory structures might be used, but you are on your + own. The above structure is the supported structure. + + +BUILD SOFTFLOAT 3A FOR HERCULES + + Windows users who wish to avoid building SoftFloat 3a For Hercules + may instead download a zip file containing binaries and public + headers in the correct directory structure from here: + + https://github.com/hercules-390/SoftFloat-3a/releases/download/v1.0.0/s3fh.zip + + You can find source for SoftFloat 3a For Hercules here: + + https://github.com/hercules-390/SoftFloat-3a/releases/latest + + The document BUILDING in that repository has the build instructions. + + You only need to build SoftFloat 3a For Hercules once, even if you + build Hercules multiple times. A rebuild of SoftFloat 3a For + Hercules is required only if you are recreating the entire build + directory structure, are developing SoftFloat 3a For Hercules, or + need an updated version of the package. + + Note that while SoftFloat 3a For Hercules is based on John Hauser's + SoftFloat package, version 3a, it is not the same as that package. + it has been modified as needed to implement the specifics of IBM's + implementation of binary floating point arithmetic based on the + IEEE 754 standard. (Note that IBM implements elements of both the + 1985 and 2008 versions of IEEE 754.) + + +BUILD HERCULES FOR YOUR HOST PLATFORM + +Instructions for this can be found in the following host platform +specific README files: + + README.BuildUNIX - For all UNIX-like platforms, including OS/X + + README.BuildWIN - For all supported versions of Windows, both + 32-bit and 64-bit. + + +Rewritten by Stephen Orso, stephen.orso@yahoo.com, late 2016. + +----------------------------------------------------------------------- diff --git a/README.BuildUNIX.txt b/README.BuildUNIX.txt new file mode 100644 index 000000000..1cc0d450c --- /dev/null +++ b/README.BuildUNIX.txt @@ -0,0 +1,185 @@ +------------------------------------------------------------------------------- + + + BUILDING HERCULES FOR UNIX-LIKE SYSTEMS README FILE + +Copyright 2016 by Stephen R. Orso. This work is licensed under the Creative +Commons Attribution-ShareAlike 4.0 International License. To view a copy of +this license, visit http://creativecommons.org/licenses/by-sa/4.0/ or send +a letter to Creative Commons, PO Box 1866, Mountain View, CA 94042, USA. + + +OVERVIEW + +If you have not read the 'BUILDING' file yet, you should. BUILDING +is the starting point for building Hercules. It contains important +information. Read BUILDING, then come back here. + +And when you have come back here, be sure you have built SoftFloat 3a +For Hercules first (that was the instruction in BUILDING). You will +not be able to build Hercules without SoftFloat 3a For Hercules. + +Hercules can be build on many UNIX-like 32-bit and 64-bit systems, +including CentOS, Debian, and FreeBSD. + + +REQUIRED SOFTWARE PACKAGES + + You will need the following packages installed to successfully build + Hercules. Most of these packages are required for the build process + itself, and one is incorporated into the built Hercules. + + Packages for the build process: + + Package Minimum Version + + autoconf 2.64 + automake 1.9 + flex 2.5 + gawk 3.0 + gcc 3.0 + grep 1.0 + m4 1.4.6 + make 3.79 + perl 5.6 + sed 3.02 + cmake 3.2 (used for SoftFloat 3a For Hercules) + + SoftFloat 3a For Hercules, from the Hercules-390 repository. + + Use your host system's package manager to verify that the above build + tools are installed at the appropriate level. + + You may build Hercules with clang so long as it reports a gcc + equivalent version at or above 3.0. + + +OPTIONAL SOFTWARE PACKAGES + + libbz2 ? (1.0.6 recommended) + zlib ? (1.2.8 recommended) + ooRexx Any? (4.2.0 recommended) + Regina Rexx Any? (3.9.1 recommended) + + Compression libraries + + To enable compression, you need to install the development + library for either or both of bzip and/or zlib2. + + bzip: used for tape and disk compression. If not available in + your host system's package repositories, you may download and + build from source using the following: + + http://www.bzip.org/ + + zlib2: used for tape and disk compression. If not available in + your host system's package repositories, you may download and + build from source using the following: + + http://www.zlib.net + + REXX libraries + + A REXX runtime is required to do either of the following: + + make check - at the completion of the build + runtest - at any time + + The corresponding development library is required if you wish + to use REXX scripts in the Hercules console. + + You may install one or both of ooRexx and Regina Rexx. If an + appropriate version of the runtime and development libraries is + not available in your host system's software repositories, you + may build from source. + + +RECOMMENDED DIRECTORY STRUCTURE + + The following recommended directory structure is used for an + out-of-source build for UNIX. + + /hyperion/ # Hyperion source (see Note 1.) + /SoftFloat-3a # SoftFloat 3a For Hercules source + //hyperion/ # Hyperion build/install directory + //s3fh # S3FH install dir + # ..includes copyright notices + //s3fh/lib # contains S3FH s3fhFloat.lib + //s3fh/include # contains S3FH public headers + //s3fh.release # S3FH Release build dir + //s3fh.debug # S3FH Debug build dir + + Nonce error for UNIX users: the current development state of + the UNIX build process does not allow for builds using other than + the above structure. + + can be anything you wish, but Hercules is suggested. + + Replace as follows: + - Windows: You must use the value of the %PROCESSOR-ARCHITECTURE% + environment variable. + - UNIX: It is recommended but not required to use the value returned + by uname -m. + + Other directory structures might be used, but you are on your + own. The above structure is the supported structure. + + +PREPARING TO BUILD HERCULES + + Change to the source directory for Hercules, "hyperion" in this + document. + + Run bldlvlck to verify the versions of all installed software + required to build Hercules. + + ./util/bldlvlck + + Correct any issues that may arrise. + + Run autogen in the source direcctory to run the autoconfigure and + automake steps: + + sh ./autogen.sh + + +BUILD Hercules + + Change to the build directory and run the configure script: + + cd ..//hyperion + ../../hyperion/configure [options] + + Replace [options] with those you wish. Common options include: + + --enable-cckd-bzip2 # allow bzip2 compressed disks + --enable-het-bzip2 # allow bzip2 compressed tapes + --enable-regina-rexx # Include Regina Rexx support for scripting + --enable-object-rexx # Include Open Object Rexx support for scripting + --enable-ipv6 # Include support for IP V6 + + ../../hyperion/configure --help will give you a list of all options. + + Build Hercules using the make command with no operands + + make + + Once the build is complete, run make check to perform an initial test + of Hercules. Make check will run every test script included with the + Hercules distribution; these are in the tests subdirectory. + + make check + + Once make check has completed, you may install Hercules. This will + re-link many of the shared executables to reflect their new location + post installation. There is no requirement to install Hercules; the + program can be run from the build directory, and many people do just + that. + + make install + + The Hercules build process includes the expected make targets "clean" + and "uninstall," which have their expected respective functions. + + + \ No newline at end of file diff --git a/README.BuildWIN.txt b/README.BuildWIN.txt new file mode 100644 index 000000000..8e47d62d4 --- /dev/null +++ b/README.BuildWIN.txt @@ -0,0 +1,438 @@ +------------------------------------------------------------------------------- + + BUILDING HERCULES FOR WINDOWS README FILE + +Copyright 2016 by Stephen R. Orso. This work is licensed under the Creative +Commons Attribution-ShareAlike 4.0 International License. To view a copy of +this license, visit http://creativecommons.org/licenses/by-sa/4.0/ or send +a letter to Creative Commons, PO Box 1866, Mountain View, CA 94042, USA. + + +OVERVIEW + +If you have not read the 'BUILDING' file yet, you should. BUILDING +is the starting point for building Hercules. It contains important +information. Read BUILDING, then come back here. + +And when you have come back here, be sure you have built SoftFloat 3a +For Hercules first (that was the instruction in BUILDING). You will +not be able to build Hercules without SoftFloat 3a For Hercules. + +Hercules can be build on Windows 32-bit and 64-bit systems. + +While the Hercules application can be run on Windows XP 64-bit or +later, these instructions use Microsoft Visual Studio 2015 +Community edition, which require Windows 7 Service Pack 1 (or 7.1) +or newer. Builds on older versions of Windows require older +versions of Visual Studio, most of which require payment of license +fees. + + +DIRECTORY STRUCTURE FOR HERCULES FOR WINDOWS + + When built under Windows, Hercules expects the following directory + structure: + + \hyperion # Hercules source\build directory + \SoftFloat-3a # SoftFloat 3a For Hercules source + \winbuild # Contains pcre, zlib2, and bzip dirs + \\hyperion # Hyperion build\install directory + \\s3fh # S3FH install dir + # ..includes copyright notices + \\s3fh\lib # contains S3FH s3fhFloat.lib + \\s3fh\include # contains S3FH public headers + \\s3fh.release # S3FH Release build dir + \\s3fh.debug # S3FH Debug build dir + + can be anything you wish, but Hercules is suggested. This + directory can be placed anywhere you have read-write permissions, + consistent with common sense and the requirements of your host + system. + + All of the directories named s3fh are built when you follow the + procedure for building SoftFloat 3a For Hercules. + + Replace with the value of the %PROCESSOR-ARCHITECTURE% + environment variable. If you do not, you will need to follow the + instructions below for pointing Hercules at the directory containing + SoftFloat 3a For Hercules. + + The Windows build process will create the following additional + directories in the above structure: + + \hyperion\\bin # Executables and DLLs + \hyperion\\map # Linker address maps + \hyperion\\obj # object, export, and resource files + \hyperion\\pdb # Program Databases/Symbol files + + is either "dllmod" for 32-bit builds or "AMD64" for 64-bit + builds. The directory is prefixed by "debug\" for debug + builds. + + +DIRECTORY STRUCTURE FOR THE BZIP2, PCRE, AND ZLIB OPTIONAL PACKAGES + + The Windows build of Hercules by default expects to find the bzip2, + pcre, and zlib packages in the winbuild directory, which should be at + the same level as the hyperion directory, like so: + + \hyperion # Hercules source\build directory + \winbuild # Packages for Windows builds + \winbuild\bzip2 # ..bzip2 compression + \winbuild\pcre # ..perl-compatible regular expr. + \winbuild\zlib # ..zip2 compression + + If you wish, you may place the winbuild directory whereever you wish + and override the Hercules Windows build defaults by setting the + following Windows environment variables: + + SET ZLIB_DIR=\winbuild\zlib + SET BZIP2_DIR=\winbuild\bzip2 + SET PCRE_DIR=\winbuild\pcre + + Replace with the drive letter and with the path + containing the top directory of the Hercules build. + + You can enter these commands in the build command prompt, or you can + make them system environment variables. + + +REQUIRED SOFTWARE PACKAGES + + Note: Visual Studio 2015 Community Edition is also required to + build SoftFloat 3a For Hercules. If you have built that, there + is no need to install it again. + + Visual Studio 2015 Community Edition (VS2015CE). + + Required to build Hercules, regardless of whether the build + is done in the integrated development environment (IDE) or using + a command line. VS2015CE can be used to develop and build + Hercules without requiring payment of license fees to Microsoft + (see Appendix below for details). Obtain VS215CE here: + + https://www.visualstudio.com/vs/community/ + + Other versions of Visual Studio 2015 (Professional, Enterprise) + should work but have not been tested. Use of other versions + requires payment of license fees to Microsoft. + + Visual Studio 2015 Installation Options + + Install the following VS2015CE components to build Hercules. + + - Common Tools for Visual C++ 2015 + - Windows XP Support for Visual C++ + - Microsoft Web Developer Tools + - Tools 1.4.1 and Windows 10 SDK (10.014393) + + A higher SDK version should also work. Web Developer Tools is + absolutely required to build Hercules. The Common Tools for + Visual C++ may not be required; further testing is needed. + Feedback is welcomed. + + Microsoft Windows SDK for Windows 7 and .NET Framework 4 + + This SDK is installed as part of Visual Studio 2015 Community + Edition when the "Windows XP Support for Visual C++" component is + installed. + + It can also be obtained using this link: + + https://www.microsoft.com/en-us/download/details.aspx?id=8279 + + Note: According to Microsoft, this SDK can also be used to + target Windows XP and Windows Vista. The download page does not + say this, nor do the release notes, but the following SDK archive + page is quite clear about this (Click "Earlier releases" to see): + + https://developer.microsoft.com/en-us/windows/downloads/sdk-archive + + See the Appendix below for details on the requirement for + win32.mak. + + CMake Build Tools + + CMake is needed to build SoftFloat 3a For Hercules and the bzip2, + pcre, and zlib package. Version 3.2.0 or higher is needed. + Version 3.5.2 has been successfully used, and there is every + reason to expect that newer versions will also work. Obtain + CMake here: + + https://cmake.org/download/ + + Windows installer .msi files exist for 32-bit and 64-bit versions + of Windows. + + +MAKING WIN32.MAK AVAILABLE + + You must copy win32.mak from the Windows 7 SDK directory to the + Windows 10 SDK directory installed by VS2015CE. You will find + win32.mak in any of the following directories, depending on which + legacy Windows SDKs you have installed. + + C:\Program Files\Microsoft SDKs\Windows\v6.0A\Include + C:\Program Files\Microsoft SDKs\Windows\v7.1\Include + C:\Program Files\Microsoft SDKs\Windows\v7.1A\Include + C:\Program Files (x86)\Microsoft SDKs\Windows\v7.1\Include + C:\Program Files (x86)\Microsoft SDKs\Windows\v7.1A\Include + + Copy win32.mak to the following directory. If you find multiple + copies, fear not. They are the same, or at least good enough to + be used to build Hercules. + + C:\Program Files\Microsoft Visual Studio 14.0\VC\include + + +OPTIONAL SOFTWARE PACKAGES FOR BUILDING HERCULES + + REXX interpreters + + - ooRexx: Open Object REXX, an open source derivative of a subset + of the IBM program product Object REXX. Find it at: + + http://ooRexx.org + + Self-installing executables for the current version of ooRexx + are available for 32-bit and 64-bit versions of Windows. The + installers put ooRexx in an appropriate Program Files + subdirectory and set environment variables. The Hercules build + uses these variables to locate ooRexx. + + - Regina Rexx, an open source REXX interpreter that may be found + here: + + http://regina-rexx.sourceforge.net/index.html + + Self-installing executables for the current version of ooRexx + are available for 32-bit and 64-bit versions of Windows. The + installers put ooRexx in an appropriate Program Files + subdirectory and set environment variables. The Hercules build + uses these variables to locate ooRexx. + + Installation of either package includes the runtime components, + needed for using the runtest command, and the development library, + use to include REXX scripting support in Hercules. + + Disk and Tape Compression Libraries + + - zlib: Can be used by Hercules to compress both disk and tape + volumes. Can be found at: + + http://www.winimage.com/zLibDll/ + + Repackaging into the directory structure required for Hercules + will be needed. Original package available at: + + http://www.zlib.net + + At the moment, Windows users will need to build from source. + A binary distribution is not available at the moment. If you + have a version of zlib that was used to build a previous version + of Hyperion, you can use that in lieu of building again. + + - libbz2: Can be used by Hercules to compress both disk and tape + volumes. Can be found at: + + http://www.bzip.org/ + + At the moment, Windows users will need to build from source. + A binary distribution is not available at the moment. If you + have a version of zlib that was used to build a previous version + of Hyperion, you can use that in lieu of building again. + + - pcre: used to provide support for Perl-compatible regular + expressions in Windows. (This support is provided by UNIX-like + operating systems; no separate module is needed.) Obtain pcre + version 8.2.0 here: + + http://www.airesoft.co.uk/pcre + + Other versions are available on that page. 8.20 has been tested + and found to work. The source for pcre may be found here. + + http://www.pcre.org/ + + Newer versions are available but have been found to create + problems for Hercules. pcre2, a successor package available + at the same site, has not been tested on Hercules. + + At the moment, Windows users will need to build from source + using CMake. A binary distribution is not available at the + moment. If you have a version of zlib that was used to build + a previous version of Hyperion, you can use that in lieu of + building again. + + +OPTIONAL SOFTWARE PACKAGES FOR DEVELOPING HERCULES + + If you plan to develop Hercules, the following additional packages + will be helpful. And if you decide later to become a developer, you + can just add these packages; no re-installation of other packages is + required. + + - A Git client. There are several for Windows, and Hercules is not + dependent on the Git client's characteristics. + + - The Stand Alone Took Kit (SATK). This is an essential collection + of tools for developing test cases (if you are developing, you are + testing, right?) for Hercules. Chief among the tools in SATK is a + very functional assembler that can generate output for the + Hercules runtest testing environment. See the tests subdirectory + for more information. + + +BUILD USING THE VISUAL STUDIO 2015 INTEGRATED DEVELOPMENT ENVIRONMENT + + + When building within the IDE, the following makefile.bat command + is invoked by the IDE based on the build target and build type. + + +COMMAND LINE BUILD USING MAKEFILE.BAT + + Use of makefile.bat is recommended for command line builds for + consistency with builds done within the Visual Studio 2015 + IDE. VS 2015 uses makefile.bat to build from within its GUI. + + 1. Open a VS2015 Native Tools Command Prompt. The + navigation to do this is Windows version specific; the following + is for Windows 10. Replace with x86 for 32-bit systems + and x86_64 for 64-bit systems. + + Windows key + Scroll to the Visual Studio 2015 folder icon (not the IDE icon) + Click on the folder icon + Click on VS2015 Native Tools Command Prompt + + 2. CD to the Hercules source directory (\hyperion in the + above Recommended Directory Structure). + + 3. Use the makefile.bat command to perform the command-line build. + + makefile.bat + [-asm] + [-title "custom build title"] + [-hqa ] + [-a] | [clean] + [] + + +PARAMETERS AND OPTIONS FOR MAKEFILE.BAT + + any of the following values + DEBUG Source debugging build to run on 32-bit hosts + RETAIL Optimized production build to run on 32-bit hosts + DEBUG-X64 Source debugging build to run on 64-bit hosts + RETAIL-X64 Optimized production build to run on 64-bit hosts + + name of the makefile to be used for the build. + makefile.dllmod.msvc is provided with Hercules. + If you have developed your own, use that instead. + + - Maximum number of CPU engines allowed in the + Hercules being built. + + [-asm] Create assembly listings, file extension .cod. + + [-title "custom build title"] Creates a custom name for this + build. + + [-hqa ] - Used by developers to create a Hercules QA + build. Not for general use. + + [-a [clean] ] + [clean] + [] + + + +COMMAND LINE BUILD WITHOUT USING MAKEFILE.BAT + + Note: the preferred method for a command line build is to use + makefile.bat, described above. Building without makefile.bak is + described here to provide a complete README.BuildWIN. + + 1. Open a VS2015 Native Tools Command Prompt. The + navigation to do this is Windows version specific; the following + is for Windows 10. Replace with x86 for 32-bit systems + and x86_64 for 64-bit systems. + + Windows key + Scroll to the Visual Studio 2015 folder icon (not the IDE icon) + Click on the folder icon + Click on VS2015 Native Tools Command Prompt + + 2. Clean up any left-overs from any previous build: + + nmake clean -f makefile-dllmod.msvc + + 3. Build Hercules: + + nmake -f makefile-dllmod.msvc + + The binaries will be built in subfolder "msvc..bin" + is either "dllmod" for 32-bit builds or "AMD64" for 64-bit + builds. The directory is prefixed by "debug\" for debug + builds. + + +APPENDIX: VISUAL STUDIO 2015 COMMUNITY EDITION LICENSING + + The VS2015CE license agreement appears to allow use without payment + of license fees: + + 1) by individuals + 2) or for development of software licensed under an agreement + approved by the Open Source Initiative. + + The Q license, used for most Hercules code, is an OSI-approved + open source software license. For a complete list, see: + + https://opensource.org/licenses/alphabetical + + Other terms and conditions apply for development outside of the + above parameters. For complete license details, see a lawyear and: + + https://www.visualstudio.com/license-terms/mt171547/ + + +APPENDIX: WHY IS WIN32.MAK REQUIRED TO BUILD HERCULES? + + Hercules uses the Microsoft tool nmake for builds. Microsoft + includes this tool in Visual Studio. Nmake requires win32.mak to + complete builds. Microsoft provides win32.mak as part of a Windows + SDK. + + All works well until Microsoft decides to forcibly transition its + developer base from the nmake tool to the msbuild tool. The forcible + part was the removal of win32.mak from SDK's targeting Windows 8.0 + and newer. Nmake was still included in Visual Studio 2015. + Visual Studio 2015 will not build with an SDK earlier than Windows + 8.0. + + What is the easiest way to address this issue: copy win32.mak from + an earlier SDK. And that is what many developers have done. + + +DEPRECATED BUT SUPPORTED ALTERNATE WINBUILD DIRECTORY LOCATION + + Hercules formerly expected the winbuild directory to be located + within the hyperion directory tree, thus: + + \hyperion # Hercules source\build directory + \hyperion\winbuild # Packages for Windows builds + \hyperion\winbuild\bzip2 # ..bzip2 compression + \hyperion\winbuild\pcre # ..perl-compatible regular expr. + \hyperion\winbuild\zlib # ..zip2 compression + + This default is left over from early Cygwin/MinGW-based builds of + Hercules under Windows and is deprecated. While it is currently + supported, you are urged to move the winbuild directory to the + same level as the hyperion directory. + + Support for this directory location will be removed in a future + release. + + diff --git a/README.BuildWINSupp.txt b/README.BuildWINSupp.txt new file mode 100644 index 000000000..447ff9314 --- /dev/null +++ b/README.BuildWINSupp.txt @@ -0,0 +1,399 @@ +------------------------------------------------------------------------------- + + BUILDING HERCULES SUPPORT MODULES FOR WINDOWS README FILE + +Copyright 2016 by Stephen R. Orso. This work is licensed under the Creative +Commons Attribution-ShareAlike 4.0 International License. To view a copy of +this license, visit http://creativecommons.org/licenses/by-sa/4.0/ or send +a letter to Creative Commons, PO Box 1866, Mountain View, CA 94042, USA. + + +OVERVIEW + + If you have not read the 'BUILDING' file yet, you should. BUILDING + is the starting point for building Hercules. It contains important + information. Read BUILDING, then come back here. + + The Windows Support Modules provide functions for Windows builders of + Hercules that are readily available to UNIX builders. Three modules + are included: + + bzip2 - a compression library, used for disk and tape compression + zlib - another compression library, also for tape and disk + pcre - Perl-Compatible Regular Expressions, used for the Hercules + Automated Operator (HAO). + + If you just wish to install Hercules, you do not need to build the + Windows Support Modules, and you need read no further here unless + you wish to. + + The Windows Support Modules are not required when installing Hercules + on any platform. The Windows Support Modules are included in the + Hercules Windows installation files and are not required for UNIX + installation. + + If you are a Hercules Developer who develops on Windows, you do not + need to build the Windows Support Modules. The pre-compiled binaries + will be sufficient to allow Hercules development on Windows. + + Should you wish to update the Windows Support Modules with a newer + version of bzip2, pcre, or zlib, then the rests of this README will + help you through the process. + + +BUILD PROCESS OVERVIEW + + For each package, you must: + + 1. Obtain sources from the package's web site. + 2. Build 32-bit and 64-bit versions of the package's shared library + (.dll) and imports library (.lib). + 3. Copy the public headers, the DLLs, and imports libraries to + the correct locations in the winbuild directory tree. + 4. Copy the copyright and license documentation applicable to binary + distribution of each package to the winbuild directory. + + When the above steps have been done for each of the three packages, + build the self-extracting .zip archive from the winbuild tree. + + And, of course, other Hercules developers working on Windows will + really appreciate it if you test the results before you post. + + Each of the three packages is built with Visual Studio 2015 Community + Edition (or better). bzip2 uses nmake to build, which means you will + need to transfer win32.mak from the Windows 7.1 SDK to the Visual + Studio 2015 Visual C include directory. See the README.BuildWin.txt + file for details. + + The resulting directory structure, also documented in README.BuildWIN, + looks like this. The easiest way to create this structure is to + download and extract the current version of the Windows Support + Modules, winbuild.zip. + + winbuild # Packages for Windows builds + ├───bzip2 # ..bzip 32-bit dll, lib, headers + │ └───x64 # 64-bit dll, lib, headers + ├───pcre # ..perl-compatible regular expr. + │ ├───bin # 32-bit dlls + │ ├───include # public headers + │ ├───lib # import libraries + │ └───x64 # ..64-bit binaries etc + │ ├───bin # 64-bit dlls + │ ├───include # public headers + │ └───lib # import libraries + └───zlib # ..zip2 compression 32-bit dll + ├───include # public headers + ├───lib # 32-bit import library + └───x64 # ..64-bit dll + ├───include # public headers + └───lib # 64-bit import library + + It is recommended to build pcre and zlib out of source using the + following directory structure. + + + ├───amd64 #64-bit builds + │ ├───pcre.build + │ └───zlib.build + ├───bzip #source + ├───pcre #source + ├───winbuild #install + │ ├───bzip2 + │ ├───pcre + │ └───zlib + ├───x86 #32-bit builds + │ ├───pcre.build + │ └───zlib.build + └───zlip #source + + Bzip2 uses nmake, and its build process is set up for in-source build. + + +OBTAIN SOURCES + + bzip2 - http://www.bzip.org/ + zlib - http://www.zlib.net/ + pcre - http://www.pcre.org/ + + +BUILDING BZIP2 + + Bzip2 has an nmake-based build process that works with VS2015CE to + build both 32-bit and 64-bit versions of the libraries. Two builds + are needed to build the required libraries. + + Create the dll target in makefile.msc + + The provided bzip2 build nmake does not create a dll. Do the + following to add the target for the dll and corresponding import + library: + + 1. Edit makefile.msc and locate the following target on or about + line 22: + + all: lib bzip2 test + + Change the line to: + + all: dll lib bzip2 test + + 2. Locate the bzip2: target on or about line 22 and change it to: + + bzip2: dll lib + $(CC) $(CFLAGS) /Febzip2 bzip2.c libbz2.lib setargv.obj + $(CC) $(CFLAGS) /Febzip2recover bzip2recover.c + + These changes link the executable with the dll and remove + obsolete c compiler flags. + + 3. Add the dll: target between the current lib: and test: targets. + Be sure to leave a blank line between the dll: target and each + of the exsting targets. + + dll: $(OBJS) + $(LINK) $(LFLAGS) /dll /implib:libbz2.lib /out:libbz2.dll /def:libbz2.def $(OBJS) + + 4. Change the lib: target to change the static library created by + the target so that it does not conflict with the import library + created by the dll: target. When you are done, the lib: target + should look like this: + + lib: $(OBJS) + lib -nologo /out:libbz2s.lib $(OBJS) + + 5. Add the following new files to the clean: target: + + del libbz2s.lib + del libbz2.dll + del libbz2.pdb + + Now you are ready to build. + + Build the binaries: + + 1. Open a Visual Studio 2015 32-bit tools command prompt. The + start menu item is titled: + + VS2015 x86 Native Tools Command Prompt + + 2. Issue the following command to build the 32-bit dll and + corresponding import library: + + nmake -f makefile.msc all + + 3. Copy the 32-bit files to the winbuild directory + + \bzip2.dll --> winbuild\bzip2 + \bzip2.lib --> winbuild\bzip2 + \bzip2.h --> winbuild\bzip2 + + 4 Remove the 32-bit binaries from the source directory + + nmake -f makefile.msc clean + + 5. Open a Visual Studio 2015 64-bit tools command prompt using the + Windows Start menu. On a 64-bit Windows machine, the start + menu item is titled: + + VS2015 x64 Native Tools Command Prompt + + On a 32-bit machine, look for: + + VS2015 x86 x64 Cross Tools Command Prompt + + 6. Issue the following command to build the 64-bit dll and + corresponding import library: + + nmake -f makefile.msc all + + 7. Copy the 64-bit files to the winbuild directory + + \bzip2.dll --> winbuild\bzip2\x64 + \bzip2.lib --> winbuild\bzip2\x64 + + + +BUILDING PCRE + + Pcre has a nearly complete CMake-based build process that generates + dll and import libriaries without a "3" suffix. This change in name + from Hyperion's earlier "3" suffix convention ("pcre3.dll") means + the library built with this procedure can only be used with newer + commits of Hyperion. + + Build twice, once using a VS2015 x86 Native Tools command prompt, and + once using a VS2015 x64 Native Tools command prompt. You will need + separate build directories for the 32-bit and 64-bit builds. + + 1. Open a Visual Studio 2015 32-bit tools command prompt. The Start + Menu item is titled: + + VS2015 x86 Native Tools Command Prompt + + 2. Issue the following command to start the CMake Windows GUI. + + cmake-gui + + 3. Point cmake-gui at the source and build directories, then click + Configure. When asked to specify the generator for the project, + select: + + "Visual Studio 14 2015" + + Do not specify "Visual Studio 14 2015 Win64". You will do that + when building the 64-bit libraries. Leave "Use default native + compilers" selected and Click Finish. + + 4. Cmake-gui displaiys a list of options for building pcre. Select + ASM686 and click Configure again. The options list changes from + red to white. + + 5. Click Generate. When that completes, exit cmake-gui. + + 6. Issue the following command to build the 32-bit dll and + corresponding import library. The Release directory will + contain the created library and dll: + + cmake --build . -config release + + 7. Copy the 32-bit files to the winbuild directory: + + <32-bit_build_dir>\release\pcre.dll --> winbuild\pcre\bin + <32-bit_build_dir>\release\pcreposix.dll --> winbuild\pcre\bin + <32-bit_build_dir>\release\pcre.lib --> winbuild\pcre\lib + <32-bit_build_dir>\release\pcreposix.lib --> winbuild\pcre\lib + \pcreposix.h --> winbuild\pcre\include + + 8. Open a Visual Studio 2015 64-bit tools command prompt using the + Windows Start menu. On a 64-bit Windows machine, the start + menu item is titled: + + VS2015 x64 Native Tools Command Prompt + + On a 32-bit machine, look for: + + VS2015 x86 x64 Cross Tools Command Prompt + + 9. Issue the following command to start the CMake Windows GUI. + + cmake-gui + + 10. Point cmake-gui at the source and build directories, then click + Configure. When asked to specify the generator for the project, + select: + + "Visual Studio 14 2015 Win64" + + Leave "Use default native compilers" selected and Click Finish. + + 11. Cmake-gui displaiys a list of options for building pcre. Select + AMD64 and click Configure again. The options list changes from + red to white. + + 12. Click Generate. When that completes, exit cmake-gui. + + 13. Issue the following command to build the 64-bit dll and + corresponding import library. The Release directory will + contain the created library and dll: + + cmake --build . -config release + + 14. Copy the 64-bit files to the winbuild directory: + + <64-bit_build_dir>\release\pcre.dll --> winbuild\pcre\x64\bin + <64-bit_build_dir>\release\pcreposix.dll --> winbuild\pcre\x64\bin + <64-bit_build_dir>\release\pcre.lib --> winbuild\pcre\x64\lib + <64-bit_build_dir>\release\pcreposix.lib --> winbuild\pcre\x64\lib + \pcreposix.h --> winbuild\pcre\include\x64 + + +BUILDING ZLIB + + Zlib has a nearly complete CMake-based build process that generates + dll and import libriaries. + + Build twice, once using a VS2015 x86 Native Tools command prompt, and + once using a VS2015 x64 Native Tools command prompt. You will need + separate build directories for the 32-bit and 64-bit builds. + + 1. Open a Visual Studio 2015 32-bit tools command prompt. The Start + Menu item is titled: + + VS2015 x86 Native Tools Command Prompt + + 2. Issue the following command to start the CMake Windows GUI. + + cmake-gui + + 3. Point cmake-gui at the source and build directories, then click + Configure. When asked to specify the generator for the project, + select: + + "Visual Studio 14 2015" + + Do not specify "Visual Studio 14 2015 Win64". You will do that + when building the 64-bit libraries. Leave "Use default native + compilers" selected and Click Finish. + + 4. Cmake-gui displaiys a list of options for building zlib. Select + BUILD_SHARED_LIBRARY, uncheck all of the other checkboxes, and + click Configure again. The options list changes from red to white. + + 5. Click Generate. When that completes, exit cmake-gui. + + 6. Issue the following command to build the 32-bit dll and + corresponding import library. The Release directory will + contain the created library and dll: + + cmake --build . -config release + + 7. Copy the 32-bit files to the winbuild directory: + + <32-bit_build_dir>\release\zlib1.dll --> winbuild\zlib + <32-bit_build_dir>\release\zdll.lib --> winbuild\zlib\lib + <32-bit_build_dir>\zconf.h --> winbuild\zlib\include + \zlib.h --> winbuild\zlib\include + + 8. Open a Visual Studio 2015 64-bit tools command prompt using the + Windows Start menu. On a 64-bit Windows machine, the start + menu item is titled: + + VS2015 x64 Native Tools Command Prompt + + On a 32-bit machine, look for: + + VS2015 x86 x64 Cross Tools Command Prompt + + 9. Issue the following command to start the CMake Windows GUI. + + cmake-gui + + 10. Point cmake-gui at the source and build directories, then click + Configure. When asked to specify the generator for the project, + select: + + "Visual Studio 14 2015 Win64" + + Leave "Use default native compilers" selected and Click Finish. + + 11. Cmake-gui displaiys a list of options for building zlib. Select + BUILD_SHARED_LIBRARY, uncheck all of the other checkboxes, and + click Configure again. The options list changes from red to white. + + 12. Click Generate. When that completes, exit cmake-gui. + + 13. Issue the following command to build the 64-bit dll and + corresponding import library. The Release directory will + contain the created library and dll: + + cmake --build . -config release + + 14. Copy the 64-bit files to the winbuild directory: + + <64-bit_build_dir>\release\zlib1.dll --> winbuild\zlib\x64 + <64-bit_build_dir>\release\zdll.lib --> winbuild\zlib\x64\lib + <64-bit_build_dir>\zconf.h --> winbuild\zlib\x64\include + \zlib.h --> winbuild\zlib\x64\include + + + \ No newline at end of file diff --git a/README.SOFTFLOAT b/README.SOFTFLOAT deleted file mode 100644 index 24c23f663..000000000 --- a/README.SOFTFLOAT +++ /dev/null @@ -1,113 +0,0 @@ ---- start of preamble - -This is a verbatim copy of the README distributed with original unmodified -SoftFloat package with only this preamble added - -no code modifications were done to the Hercules of the -package - ---- - -To fix the incompatibilities found when building Hercules on different platforms -the SoftFloat needed sources were copied to the main source path - -To make clear the components of the SoftFloat package ( as related to Hercules ) -all the sources start with SoftFloat ( case sensitive ) - -milieu.h was renamed to SoftFloat-milieu.h -and all the sources interested/involved were modified accordingly -( SoftFloat provided sources and ieee.c ) - -as a cosmetic change -all the occurrences of SoftFloat were changed to SoftFloat ( case sensitive ) -to make searching easier - -for such a minor change no need to muck around the copyright notice - -the following has been inserted in the interested/involved sources - -/* SoftFloat was repackaged to reside in the main source path */ -/* to provide FULL CROSS PLATFORM build compatibility. */ -/* To make evident the SoftFloat rePackaging standardized names */ -/* were used */ -/* mileu.h was renamed to SoftFloat-milieu.h and all the sources */ -/* were modified accordingly. */ -/* no other modifications were made */ -/* no reason to clutter the copyright stuff for such a minor change */ -/* */ -/* the original unmodified SoftFloat package is still distributed */ -/* in zipped format here as SoftFloat-2b.zip */ - ---- end of preamble - -Package Overview for SoftFloat Release 2b - -John R. Hauser -2002 May 27 - - ----------------------------------------------------------------------------- -Overview - -SoftFloat is a software implementation of floating-point that conforms to -the IEC/IEEE Standard for Binary Floating-Point Arithmetic. SoftFloat is -distributed in the form of C source code. Compiling the SoftFloat sources -generates two things: - --- A SoftFloat object file (typically `SoftFloat.o') containing the complete - set of IEC/IEEE floating-point routines. - --- A `timesoftfloat' program for evaluating the speed of the SoftFloat - routines. (The SoftFloat module is linked into this program.) - -The SoftFloat package is documented in four text files: - - SoftFloat.txt Documentation for using the SoftFloat functions. - SoftFloat-source.txt Documentation for compiling SoftFloat. - SoftFloat-history.txt History of major changes to SoftFloat. - timesoftfloat.txt Documentation for using `timesoftfloat'. - -Other files in the package comprise the source code for SoftFloat. - -Please be aware that some work is involved in porting this software to other -targets. It is not just a matter of getting `make' to complete without -error messages. I would have written the code that way if I could, but -there are fundamental differences between systems that can't be hidden. -You should not attempt to compile SoftFloat without first reading both -`SoftFloat.txt' and `SoftFloat-source.txt'. - - ----------------------------------------------------------------------------- -Legal Notice - -SoftFloat was written by me, John R. Hauser. This work was made possible in -part by the International Computer Science Institute, located at Suite 600, -1947 Center Street, Berkeley, California 94704. Funding was partially -provided by the National Science Foundation under grant MIP-9311980. The -original version of this code was written as part of a project to build -a fixed-point vector processor in collaboration with the University of -California at Berkeley, overseen by Profs. Nelson Morgan and John Wawrzynek. - -THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort -has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT -TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO -PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL -LOSSES, COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO -FURTHERMORE EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER -SCIENCE INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, -COSTS, OR OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE -SOFTWARE. - -Derivative works are acceptable, even for commercial purposes, provided -that the minimal documentation requirements stated in the source code are -satisfied. - - ----------------------------------------------------------------------------- -Contact Information - -At the time of this writing, the most up-to-date information about -SoftFloat and the latest release can be found at the Web page `http:// -www.cs.berkeley.edu/~jhauser/arithmetic/SoftFloat.html'. - - diff --git a/SoftFloat-2b.zip b/SoftFloat-2b.zip deleted file mode 100644 index d68679408..000000000 Binary files a/SoftFloat-2b.zip and /dev/null differ diff --git a/SoftFloat-macros.h b/SoftFloat-macros.h deleted file mode 100644 index cf705be57..000000000 --- a/SoftFloat-macros.h +++ /dev/null @@ -1,752 +0,0 @@ -/* SoftFloat-macros.h (C) John R. Hauser, 1998-2002 */ -/* This module is part of the SoftFloat package. */ -/* */ -/* Released under "The Q Public License Version 1" */ -/* (http://www.hercules-390.org/herclic.html) */ -/* as modifications to Hercules. */ - -/* This module is an UNMODIFIED version of John R. Hauser's */ -/* 'SoftFloat-macros.h' module, and is wholly copyright by him. */ -/* Refer to the documents "SoftFloat.txt", "SoftFloat-source.txt", */ -/* and "SoftFloat-history.txt" for detailed SoftFloat information. */ - -/* SoftFloat was repackaged to reside in the main source path */ -/* to provide FULL CROSS PLATFORM build compatibility. */ -/* To make evident the SoftFloat rePackaging standardized names */ -/* were used */ -/* mileu.h was renamed to SoftFloat-milieu.h and all the sources */ -/* were modified accordingly. */ -/* no other modifications were made */ -/* no reason to clutter the copyright stuff for such a minor change */ -/* */ -/* the original unmodified SoftFloat package is still distributed */ -/* in zipped format here as SoftFloat-2b.zip */ - -/*============================================================================ - -This C source fragment is part of the SoftFloat IEC/IEEE Floating-point -Arithmetic Package, Release 2b. - -Written by John R. Hauser. This work was made possible in part by the -International Computer Science Institute, located at Suite 600, 1947 Center -Street, Berkeley, California 94704. Funding was partially provided by the -National Science Foundation under grant MIP-9311980. The original version -of this code was written as part of a project to build a fixed-point vector -processor in collaboration with the University of California at Berkeley, -overseen by Profs. Nelson Morgan and John Wawrzynek. More information -is available through the Web page `http://www.cs.berkeley.edu/~jhauser/ -arithmetic/SoftFloat.html'. - -THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has -been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES -RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS -AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES, -COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE -EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE -INSTITUTE (possibly via similar legal notice) AGAINST ALL LOSSES, COSTS, OR -OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE. - -Derivative works are acceptable, even for commercial purposes, so long as -(1) the source code for the derivative work includes prominent notice that -the work is derivative, and (2) the source code includes prominent notice with -these four paragraphs for those parts of this code that are retained. - -=============================================================================*/ - -#ifndef _SOFTFLOAT_MACROS_H_ -#define _SOFTFLOAT_MACROS_H_ - -PUSH_GCC_WARNINGS() -DISABLE_GCC_WARNING( "-Wunused-function" ) - -/*---------------------------------------------------------------------------- -| Shifts `a' right by the number of bits given in `count'. If any nonzero -| bits are shifted off, they are ``jammed'' into the least significant bit of -| the result by setting the least significant bit to 1. The value of `count' -| can be arbitrarily large; in particular, if `count' is greater than 32, the -| result will be either 0 or 1, depending on whether `a' is zero or nonzero. -| The result is stored in the location pointed to by `zPtr'. -*----------------------------------------------------------------------------*/ - -static INLINE void shift32RightJamming( bits32 a, int16 count, bits32 *zPtr ) -{ - bits32 z; - - if ( count == 0 ) { - z = a; - } - else if ( count < 32 ) { - z = ( a>>count ) | ( ( a<<( ( - count ) & 31 ) ) != 0 ); - } - else { - z = ( a != 0 ); - } - *zPtr = z; - -} - -/*---------------------------------------------------------------------------- -| Shifts `a' right by the number of bits given in `count'. If any nonzero -| bits are shifted off, they are ``jammed'' into the least significant bit of -| the result by setting the least significant bit to 1. The value of `count' -| can be arbitrarily large; in particular, if `count' is greater than 64, the -| result will be either 0 or 1, depending on whether `a' is zero or nonzero. -| The result is stored in the location pointed to by `zPtr'. -*----------------------------------------------------------------------------*/ - -static INLINE void shift64RightJamming( bits64 a, int16 count, bits64 *zPtr ) -{ - bits64 z; - - if ( count == 0 ) { - z = a; - } - else if ( count < 64 ) { - z = ( a>>count ) | ( ( a<<( ( - count ) & 63 ) ) != 0 ); - } - else { - z = ( a != 0 ); - } - *zPtr = z; - -} - -/*---------------------------------------------------------------------------- -| Shifts the 128-bit value formed by concatenating `a0' and `a1' right by 64 -| _plus_ the number of bits given in `count'. The shifted result is at most -| 64 nonzero bits; this is stored at the location pointed to by `z0Ptr'. The -| bits shifted off form a second 64-bit result as follows: The _last_ bit -| shifted off is the most-significant bit of the extra result, and the other -| 63 bits of the extra result are all zero if and only if _all_but_the_last_ -| bits shifted off were all zero. This extra result is stored in the location -| pointed to by `z1Ptr'. The value of `count' can be arbitrarily large. -| (This routine makes more sense if `a0' and `a1' are considered to form -| a fixed-point value with binary point between `a0' and `a1'. This fixed- -| point value is shifted right by the number of bits given in `count', and -| the integer part of the result is returned at the location pointed to by -| `z0Ptr'. The fractional part of the result may be slightly corrupted as -| described above, and is returned at the location pointed to by `z1Ptr'.) -*----------------------------------------------------------------------------*/ - -static INLINE void - shift64ExtraRightJamming( - bits64 a0, bits64 a1, int16 count, bits64 *z0Ptr, bits64 *z1Ptr ) -{ - bits64 z0, z1; - int8 negCount = ( - count ) & 63; - - if ( count == 0 ) { - z1 = a1; - z0 = a0; - } - else if ( count < 64 ) { - z1 = ( a0<>count; - } - else { - if ( count == 64 ) { - z1 = a0 | ( a1 != 0 ); - } - else { - z1 = ( ( a0 | a1 ) != 0 ); - } - z0 = 0; - } - *z1Ptr = z1; - *z0Ptr = z0; - -} - -/*---------------------------------------------------------------------------- -| Shifts the 128-bit value formed by concatenating `a0' and `a1' right by the -| number of bits given in `count'. Any bits shifted off are lost. The value -| of `count' can be arbitrarily large; in particular, if `count' is greater -| than 128, the result will be 0. The result is broken into two 64-bit pieces -| which are stored at the locations pointed to by `z0Ptr' and `z1Ptr'. -*----------------------------------------------------------------------------*/ - -static INLINE void - shift128Right( - bits64 a0, bits64 a1, int16 count, bits64 *z0Ptr, bits64 *z1Ptr ) -{ - bits64 z0, z1; - int8 negCount = ( - count ) & 63; - - if ( count == 0 ) { - z1 = a1; - z0 = a0; - } - else if ( count < 64 ) { - z1 = ( a0<>count ); - z0 = a0>>count; - } - else { - z1 = ( count < 64 ) ? ( a0>>( count & 63 ) ) : 0; - z0 = 0; - } - *z1Ptr = z1; - *z0Ptr = z0; - -} - -/*---------------------------------------------------------------------------- -| Shifts the 128-bit value formed by concatenating `a0' and `a1' right by the -| number of bits given in `count'. If any nonzero bits are shifted off, they -| are ``jammed'' into the least significant bit of the result by setting the -| least significant bit to 1. The value of `count' can be arbitrarily large; -| in particular, if `count' is greater than 128, the result will be either -| 0 or 1, depending on whether the concatenation of `a0' and `a1' is zero or -| nonzero. The result is broken into two 64-bit pieces which are stored at -| the locations pointed to by `z0Ptr' and `z1Ptr'. -*----------------------------------------------------------------------------*/ - -static INLINE void - shift128RightJamming( - bits64 a0, bits64 a1, int16 count, bits64 *z0Ptr, bits64 *z1Ptr ) -{ - bits64 z0, z1; - int8 negCount = ( - count ) & 63; - - if ( count == 0 ) { - z1 = a1; - z0 = a0; - } - else if ( count < 64 ) { - z1 = ( a0<>count ) | ( ( a1<>count; - } - else { - if ( count == 64 ) { - z1 = a0 | ( a1 != 0 ); - } - else if ( count < 128 ) { - z1 = ( a0>>( count & 63 ) ) | ( ( ( a0<>count ); - z0 = a0>>count; - } - else { - if ( count == 64 ) { - z2 = a1; - z1 = a0; - } - else { - a2 |= a1; - if ( count < 128 ) { - z2 = a0<>( count & 63 ); - } - else { - z2 = ( count == 128 ) ? a0 : ( a0 != 0 ); - z1 = 0; - } - } - z0 = 0; - } - z2 |= ( a2 != 0 ); - } - *z2Ptr = z2; - *z1Ptr = z1; - *z0Ptr = z0; - -} - -/*---------------------------------------------------------------------------- -| Shifts the 128-bit value formed by concatenating `a0' and `a1' left by the -| number of bits given in `count'. Any bits shifted off are lost. The value -| of `count' must be less than 64. The result is broken into two 64-bit -| pieces which are stored at the locations pointed to by `z0Ptr' and `z1Ptr'. -*----------------------------------------------------------------------------*/ - -static INLINE void - shortShift128Left( - bits64 a0, bits64 a1, int16 count, bits64 *z0Ptr, bits64 *z1Ptr ) -{ - - *z1Ptr = a1<>( ( - count ) & 63 ) ); - -} - -/*---------------------------------------------------------------------------- -| Shifts the 192-bit value formed by concatenating `a0', `a1', and `a2' left -| by the number of bits given in `count'. Any bits shifted off are lost. -| The value of `count' must be less than 64. The result is broken into three -| 64-bit pieces which are stored at the locations pointed to by `z0Ptr', -| `z1Ptr', and `z2Ptr'. -*----------------------------------------------------------------------------*/ - -static INLINE void - shortShift192Left( - bits64 a0, - bits64 a1, - bits64 a2, - int16 count, - bits64 *z0Ptr, - bits64 *z1Ptr, - bits64 *z2Ptr - ) -{ - bits64 z0, z1, z2; - int8 negCount; - - z2 = a2<>negCount; - z0 |= a1>>negCount; - } - *z2Ptr = z2; - *z1Ptr = z1; - *z0Ptr = z0; - -} - -/*---------------------------------------------------------------------------- -| Adds the 128-bit value formed by concatenating `a0' and `a1' to the 128-bit -| value formed by concatenating `b0' and `b1'. Addition is modulo 2^128, so -| any carry out is lost. The result is broken into two 64-bit pieces which -| are stored at the locations pointed to by `z0Ptr' and `z1Ptr'. -*----------------------------------------------------------------------------*/ - -static INLINE void - add128( - bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 *z0Ptr, bits64 *z1Ptr ) -{ - bits64 z1; - - z1 = a1 + b1; - *z1Ptr = z1; - *z0Ptr = a0 + b0 + ( z1 < a1 ); - -} - -/*---------------------------------------------------------------------------- -| Adds the 192-bit value formed by concatenating `a0', `a1', and `a2' to the -| 192-bit value formed by concatenating `b0', `b1', and `b2'. Addition is -| modulo 2^192, so any carry out is lost. The result is broken into three -| 64-bit pieces which are stored at the locations pointed to by `z0Ptr', -| `z1Ptr', and `z2Ptr'. -*----------------------------------------------------------------------------*/ - -static INLINE void - add192( - bits64 a0, - bits64 a1, - bits64 a2, - bits64 b0, - bits64 b1, - bits64 b2, - bits64 *z0Ptr, - bits64 *z1Ptr, - bits64 *z2Ptr - ) -{ - bits64 z0, z1, z2; - bits8 carry0, carry1; - - z2 = a2 + b2; - carry1 = ( z2 < a2 ); - z1 = a1 + b1; - carry0 = ( z1 < a1 ); - z0 = a0 + b0; - z1 += carry1; - z0 += ( z1 < carry1 ); - z0 += carry0; - *z2Ptr = z2; - *z1Ptr = z1; - *z0Ptr = z0; - -} - -/*---------------------------------------------------------------------------- -| Subtracts the 128-bit value formed by concatenating `b0' and `b1' from the -| 128-bit value formed by concatenating `a0' and `a1'. Subtraction is modulo -| 2^128, so any borrow out (carry out) is lost. The result is broken into two -| 64-bit pieces which are stored at the locations pointed to by `z0Ptr' and -| `z1Ptr'. -*----------------------------------------------------------------------------*/ - -static INLINE void - sub128( - bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 *z0Ptr, bits64 *z1Ptr ) -{ - - *z1Ptr = a1 - b1; - *z0Ptr = a0 - b0 - ( a1 < b1 ); - -} - -/*---------------------------------------------------------------------------- -| Subtracts the 192-bit value formed by concatenating `b0', `b1', and `b2' -| from the 192-bit value formed by concatenating `a0', `a1', and `a2'. -| Subtraction is modulo 2^192, so any borrow out (carry out) is lost. The -| result is broken into three 64-bit pieces which are stored at the locations -| pointed to by `z0Ptr', `z1Ptr', and `z2Ptr'. -*----------------------------------------------------------------------------*/ - -static INLINE void - sub192( - bits64 a0, - bits64 a1, - bits64 a2, - bits64 b0, - bits64 b1, - bits64 b2, - bits64 *z0Ptr, - bits64 *z1Ptr, - bits64 *z2Ptr - ) -{ - bits64 z0, z1, z2; - bits8 borrow0, borrow1; - - z2 = a2 - b2; - borrow1 = ( a2 < b2 ); - z1 = a1 - b1; - borrow0 = ( a1 < b1 ); - z0 = a0 - b0; - z0 -= ( z1 < borrow1 ); - z1 -= borrow1; - z0 -= borrow0; - *z2Ptr = z2; - *z1Ptr = z1; - *z0Ptr = z0; - -} - -/*---------------------------------------------------------------------------- -| Multiplies `a' by `b' to obtain a 128-bit product. The product is broken -| into two 64-bit pieces which are stored at the locations pointed to by -| `z0Ptr' and `z1Ptr'. -*----------------------------------------------------------------------------*/ - -static INLINE void mul64To128( bits64 a, bits64 b, bits64 *z0Ptr, bits64 *z1Ptr ) -{ - bits32 aHigh, aLow, bHigh, bLow; - bits64 z0, zMiddleA, zMiddleB, z1; - - aLow = a; - aHigh = a>>32; - bLow = b; - bHigh = b>>32; - z1 = ( (bits64) aLow ) * bLow; - zMiddleA = ( (bits64) aLow ) * bHigh; - zMiddleB = ( (bits64) aHigh ) * bLow; - z0 = ( (bits64) aHigh ) * bHigh; - zMiddleA += zMiddleB; - z0 += ( ( (bits64) ( zMiddleA < zMiddleB ) )<<32 ) + ( zMiddleA>>32 ); - zMiddleA <<= 32; - z1 += zMiddleA; - z0 += ( z1 < zMiddleA ); - *z1Ptr = z1; - *z0Ptr = z0; - -} - -/*---------------------------------------------------------------------------- -| Multiplies the 128-bit value formed by concatenating `a0' and `a1' by -| `b' to obtain a 192-bit product. The product is broken into three 64-bit -| pieces which are stored at the locations pointed to by `z0Ptr', `z1Ptr', and -| `z2Ptr'. -*----------------------------------------------------------------------------*/ - -static INLINE void - mul128By64To192( - bits64 a0, - bits64 a1, - bits64 b, - bits64 *z0Ptr, - bits64 *z1Ptr, - bits64 *z2Ptr - ) -{ - bits64 z0, z1, z2, more1; - - mul64To128( a1, b, &z1, &z2 ); - mul64To128( a0, b, &z0, &more1 ); - add128( z0, more1, 0, z1, &z0, &z1 ); - *z2Ptr = z2; - *z1Ptr = z1; - *z0Ptr = z0; - -} - -/*---------------------------------------------------------------------------- -| Multiplies the 128-bit value formed by concatenating `a0' and `a1' to the -| 128-bit value formed by concatenating `b0' and `b1' to obtain a 256-bit -| product. The product is broken into four 64-bit pieces which are stored at -| the locations pointed to by `z0Ptr', `z1Ptr', `z2Ptr', and `z3Ptr'. -*----------------------------------------------------------------------------*/ - -static INLINE void - mul128To256( - bits64 a0, - bits64 a1, - bits64 b0, - bits64 b1, - bits64 *z0Ptr, - bits64 *z1Ptr, - bits64 *z2Ptr, - bits64 *z3Ptr - ) -{ - bits64 z0, z1, z2, z3; - bits64 more1, more2; - - mul64To128( a1, b1, &z2, &z3 ); - mul64To128( a1, b0, &z1, &more2 ); - add128( z1, more2, 0, z2, &z1, &z2 ); - mul64To128( a0, b0, &z0, &more1 ); - add128( z0, more1, 0, z1, &z0, &z1 ); - mul64To128( a0, b1, &more1, &more2 ); - add128( more1, more2, 0, z2, &more1, &z2 ); - add128( z0, z1, 0, more1, &z0, &z1 ); - *z3Ptr = z3; - *z2Ptr = z2; - *z1Ptr = z1; - *z0Ptr = z0; - -} - -/*---------------------------------------------------------------------------- -| Returns an approximation to the 64-bit integer quotient obtained by dividing -| `b' into the 128-bit value formed by concatenating `a0' and `a1'. The -| divisor `b' must be at least 2^63. If q is the exact quotient truncated -| toward zero, the approximation returned lies between q and q + 2 inclusive. -| If the exact quotient q is larger than 64 bits, the maximum positive 64-bit -| unsigned integer is returned. -*----------------------------------------------------------------------------*/ - -static bits64 estimateDiv128To64( bits64 a0, bits64 a1, bits64 b ) -{ - bits64 b0, b1; - bits64 rem0, rem1, term0, term1; - bits64 z; - - if ( b <= a0 ) return LIT64( 0xFFFFFFFFFFFFFFFF ); - b0 = b>>32; - z = ( b0<<32 <= a0 ) ? LIT64( 0xFFFFFFFF00000000 ) : ( a0 / b0 )<<32; - mul64To128( b, z, &term0, &term1 ); - sub128( a0, a1, term0, term1, &rem0, &rem1 ); - while ( ( (sbits64) rem0 ) < 0 ) { - z -= LIT64( 0x100000000 ); - b1 = b<<32; - add128( rem0, rem1, b0, b1, &rem0, &rem1 ); - } - rem0 = ( rem0<<32 ) | ( rem1>>32 ); - z |= ( b0<<32 <= rem0 ) ? 0xFFFFFFFF : rem0 / b0; - return z; - -} - -/*---------------------------------------------------------------------------- -| Returns an approximation to the square root of the 32-bit significand given -| by `a'. Considered as an integer, `a' must be at least 2^31. If bit 0 of -| `aExp' (the least significant bit) is 1, the integer returned approximates -| 2^31*sqrt(`a'/2^31), where `a' is considered an integer. If bit 0 of `aExp' -| is 0, the integer returned approximates 2^31*sqrt(`a'/2^30). In either -| case, the approximation returned lies strictly within +/-2 of the exact -| value. -*----------------------------------------------------------------------------*/ - -static bits32 estimateSqrt32( int16 aExp, bits32 a ) -{ - static const bits16 sqrtOddAdjustments[] = { - 0x0004, 0x0022, 0x005D, 0x00B1, 0x011D, 0x019F, 0x0236, 0x02E0, - 0x039C, 0x0468, 0x0545, 0x0631, 0x072B, 0x0832, 0x0946, 0x0A67 - }; - static const bits16 sqrtEvenAdjustments[] = { - 0x0A2D, 0x08AF, 0x075A, 0x0629, 0x051A, 0x0429, 0x0356, 0x029E, - 0x0200, 0x0179, 0x0109, 0x00AF, 0x0068, 0x0034, 0x0012, 0x0002 - }; - int8 index; - bits32 z; - - index = ( a>>27 ) & 15; - if ( aExp & 1 ) { - z = 0x4000 + ( a>>17 ) - sqrtOddAdjustments[ index ]; - z = ( ( a / z )<<14 ) + ( z<<15 ); - a >>= 1; - } - else { - z = 0x8000 + ( a>>17 ) - sqrtEvenAdjustments[ index ]; - z = a / z + z; - z = ( 0x20000 <= z ) ? 0xFFFF8000 : ( z<<15 ); - if ( z <= a ) return (bits32) ( ( (sbits32) a )>>1 ); - } - return ( (bits32) ( ( ( (bits64) a )<<31 ) / z ) ) + ( z>>1 ); - -} - -/*---------------------------------------------------------------------------- -| Returns the number of leading 0 bits before the most-significant 1 bit of -| `a'. If `a' is zero, 32 is returned. -*----------------------------------------------------------------------------*/ - -static int8 countLeadingZeros32( bits32 a ) -{ - static const int8 countLeadingZerosHigh[] = { - 8, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, - 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, - 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, - 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 - }; - int8 shiftCount; - - shiftCount = 0; - if ( a < 0x10000 ) { - shiftCount += 16; - a <<= 16; - } - if ( a < 0x1000000 ) { - shiftCount += 8; - a <<= 8; - } - shiftCount += countLeadingZerosHigh[ a>>24 ]; - return shiftCount; - -} - -/*---------------------------------------------------------------------------- -| Returns the number of leading 0 bits before the most-significant 1 bit of -| `a'. If `a' is zero, 64 is returned. -*----------------------------------------------------------------------------*/ - -static int8 countLeadingZeros64( bits64 a ) -{ - int8 shiftCount; - - shiftCount = 0; - if ( a < ( (bits64) 1 )<<32 ) { - shiftCount += 32; - } - else { - a >>= 32; - } - shiftCount += countLeadingZeros32( a ); - return shiftCount; - -} - -/*---------------------------------------------------------------------------- -| Returns 1 if the 128-bit value formed by concatenating `a0' and `a1' -| is equal to the 128-bit value formed by concatenating `b0' and `b1'. -| Otherwise, returns 0. -*----------------------------------------------------------------------------*/ - -static INLINE flag eq128( bits64 a0, bits64 a1, bits64 b0, bits64 b1 ) -{ - - return ( a0 == b0 ) && ( a1 == b1 ); - -} - -/*---------------------------------------------------------------------------- -| Returns 1 if the 128-bit value formed by concatenating `a0' and `a1' is less -| than or equal to the 128-bit value formed by concatenating `b0' and `b1'. -| Otherwise, returns 0. -*----------------------------------------------------------------------------*/ - -static INLINE flag le128( bits64 a0, bits64 a1, bits64 b0, bits64 b1 ) -{ - - return ( a0 < b0 ) || ( ( a0 == b0 ) && ( a1 <= b1 ) ); - -} - -/*---------------------------------------------------------------------------- -| Returns 1 if the 128-bit value formed by concatenating `a0' and `a1' is less -| than the 128-bit value formed by concatenating `b0' and `b1'. Otherwise, -| returns 0. -*----------------------------------------------------------------------------*/ - -static INLINE flag lt128( bits64 a0, bits64 a1, bits64 b0, bits64 b1 ) -{ - - return ( a0 < b0 ) || ( ( a0 == b0 ) && ( a1 < b1 ) ); - -} - -/*---------------------------------------------------------------------------- -| Returns 1 if the 128-bit value formed by concatenating `a0' and `a1' is -| not equal to the 128-bit value formed by concatenating `b0' and `b1'. -| Otherwise, returns 0. -*----------------------------------------------------------------------------*/ - -static INLINE flag ne128( bits64 a0, bits64 a1, bits64 b0, bits64 b1 ) -{ - - return ( a0 != b0 ) || ( a1 != b1 ); - -} - -POP_GCC_WARNINGS() - -#endif // _SOFTFLOAT_MACROS_H_ diff --git a/SoftFloat-milieu.h b/SoftFloat-milieu.h deleted file mode 100644 index d1fb76b16..000000000 --- a/SoftFloat-milieu.h +++ /dev/null @@ -1,79 +0,0 @@ -/* SoftFloat-milieu.h (C) John R. Hauser, 1998-2002 */ -/* This module is part of the SoftFloat package. */ -/* */ -/* Released under "The Q Public License Version 1" */ -/* (http://www.hercules-390.org/herclic.html) */ -/* as modifications to Hercules. */ - -/* This module is an UNMODIFIED version of John R. Hauser's milieu.h */ -/* header file, and is wholly copyright by him. */ -/* Refer to the documents "SoftFloat.txt", "SoftFloat-source.txt", */ -/* and "SoftFloat-history.txt" for detailed SoftFloat information. */ - -/* SoftFloat was repackaged to reside in the main source path */ -/* to provide FULL CROSS PLATFORM build compatibility. */ -/* To make evident the SoftFloat rePackaging standardized names */ -/* were used */ -/* mileu.h was renamed to SoftFloat-milieu.h and all the sources */ -/* were modified accordingly. */ -/* no other modifications were made */ -/* no reason to clutter the copyright stuff for such a minor change */ -/* */ -/* the original unmodified SoftFloat package is still distributed */ -/* in zipped format here as SoftFloat-2b.zip */ - -/*============================================================================ - -This C header file is part of the SoftFloat IEC/IEEE Floating-point Arithmetic -Package, Release 2b. - -Written by John R. Hauser. This work was made possible in part by the -International Computer Science Institute, located at Suite 600, 1947 Center -Street, Berkeley, California 94704. Funding was partially provided by the -National Science Foundation under grant MIP-9311980. The original version -of this code was written as part of a project to build a fixed-point vector -processor in collaboration with the University of California at Berkeley, -overseen by Profs. Nelson Morgan and John Wawrzynek. More information -is available through the Web page `http://www.cs.berkeley.edu/~jhauser/ -arithmetic/SoftFloat.html'. - -THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has -been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES -RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS -AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES, -COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE -EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE -INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR -OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE. - -Derivative works are acceptable, even for commercial purposes, so long as -(1) the source code for the derivative work includes prominent notice that -the work is derivative, and (2) the source code includes prominent notice with -these four paragraphs for those parts of this code that are retained. - -=============================================================================*/ - -#ifndef _SOFTFLOAT_MILIEU_H_ -#define _SOFTFLOAT_MILIEU_H_ - -/*---------------------------------------------------------------------------- -| Suppress some compiler warnings -*----------------------------------------------------------------------------*/ -#include "ccnowarn.h" - -/*---------------------------------------------------------------------------- -| Include common integer types and flags. -*----------------------------------------------------------------------------*/ -#include "SoftFloat-types.h" - -/*---------------------------------------------------------------------------- -| Symbolic Boolean literals. -*----------------------------------------------------------------------------*/ -#ifndef FALSE -enum { - FALSE = 0, - TRUE = 1 -}; -#endif - -#endif // _SOFTFLOAT_MILIEU_H_ diff --git a/SoftFloat-specialise.c b/SoftFloat-specialise.c deleted file mode 100644 index ba6cac25e..000000000 --- a/SoftFloat-specialise.c +++ /dev/null @@ -1,312 +0,0 @@ -/* SoftFloat-specialize.c (C) John R. Hauser, 1998-2002 */ -/* (C) Copyright "Fish" (David B. Trout), 2011 */ -/* This module is part of the SoftFloat package. */ -/* */ -/* Released under "The Q Public License Version 1" */ -/* (http://www.hercules-390.org/herclic.html) */ -/* as modifications to Hercules. */ - -/* This module is a SLIGHTLY modified version of John R. Hauser's */ -/* 'SoftFloat-specialize.h', and is largely copyright by him. All */ -/* I (i.e. "Fish", David B. Trout) did was enhance it to interface */ -/* with the Hercules emulator by passing along a void* pointer to */ -/* a generic "context" structure rather than use global variables */ -/* the way it was originally written. It is 99.9999% John's work. */ -/* Refer to the documents "SoftFloat.txt", "SoftFloat-source.txt", */ -/* and "SoftFloat-history.txt" for detailed SoftFloat information. */ -/* Fish note: 'FLOATX80' support was removed as we don't need it. */ - -/* SoftFloat was repackaged to reside in the main source path */ -/* to provide FULL CROSS PLATFORM build compatibility. */ -/* To make evident the SoftFloat rePackaging standardized names */ -/* were used */ -/* mileu.h was renamed to SoftFloat-milieu.h and all the sources */ -/* were modified accordingly. */ -/* no other modifications were made */ -/* no reason to clutter the copyright stuff for such a minor change */ -/* */ -/* the original unmodified SoftFloat package is still distributed */ -/* in zipped format here as SoftFloat-2b.zip */ - -/*============================================================================ - -This C source fragment is part of the SoftFloat IEC/IEEE Floating-point -Arithmetic Package, Release 2b. - -Written by John R. Hauser. This work was made possible in part by the -International Computer Science Institute, located at Suite 600, 1947 Center -Street, Berkeley, California 94704. Funding was partially provided by the -National Science Foundation under grant MIP-9311980. The original version -of this code was written as part of a project to build a fixed-point vector -processor in collaboration with the University of California at Berkeley, -overseen by Profs. Nelson Morgan and John Wawrzynek. More information -is available through the Web page `http://www.cs.berkeley.edu/~jhauser/ -arithmetic/SoftFloat.html'. - -THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has -been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES -RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS -AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES, -COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE -EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE -INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR -OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE. - -Derivative works are acceptable, even for commercial purposes, so long as -(1) the source code for the derivative work includes prominent notice that -the work is derivative, and (2) the source code includes prominent notice with -these four paragraphs for those parts of this code that are retained. - -=============================================================================*/ - -#include "hstdinc.h" -#include "hercules.h" - -#include "SoftFloat-milieu.h" -#include "SoftFloat-types.h" -#include "SoftFloat.h" -#include "SoftFloat-macros.h" -#include "SoftFloat-specialise.h" -#include "hscutl.h" - -PUSH_GCC_WARNINGS() -DISABLE_GCC_WARNING( "-Wunused-function" ) - -/*---------------------------------------------------------------------------- -| Returns 1 if the single-precision floating-point value `a' is a NaN; -| otherwise returns 0. -*----------------------------------------------------------------------------*/ - -flag float32_is_nan( float32 a ) -{ - return ( 0xFF000000 < (bits32) ( a<<1 ) ); -} - -/*---------------------------------------------------------------------------- -| Returns 1 if the single-precision floating-point value `a' is a signaling -| NaN; otherwise returns 0. -*----------------------------------------------------------------------------*/ - -flag float32_is_signaling_nan( float32 a ) -{ - return ( ( ( a>>22 ) & 0x1FF ) == 0x1FE ) && ( a & 0x003FFFFF ); -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the single-precision floating-point NaN -| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ - -commonNaNT float32ToCommonNaN( void* ctx, float32 a ) -{ - commonNaNT z; - - if ( float32_is_signaling_nan( a ) ) float_raise( ctx, float_flag_invalid ); - z.sign = a>>31; - z.low = 0; - z.high = ( (bits64) a )<<41; - return z; -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the canonical NaN `a' to the single- -| precision floating-point format. -*----------------------------------------------------------------------------*/ - -float32 commonNaNToFloat32( commonNaNT a ) -{ - return ( ( (bits32) a.sign )<<31 ) | 0x7FC00000 | ( a.high>>41 ); -} - -/*---------------------------------------------------------------------------- -| Takes two single-precision floating-point values `a' and `b', one of which -| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ - -float32 propagateFloat32NaN( void* ctx, float32 a, float32 b ) -{ - flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN; - - aIsNaN = float32_is_nan( a ); - aIsSignalingNaN = float32_is_signaling_nan( a ); - bIsNaN = float32_is_nan( b ); - bIsSignalingNaN = float32_is_signaling_nan( b ); - a |= 0x00400000; - b |= 0x00400000; - if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( ctx, float_flag_invalid ); - - /* Refer to figure 19-20 Results: Divide. */ - - if ( aIsSignalingNaN ) return a; - if ( bIsSignalingNaN ) return b; - if ( aIsNaN ) return a; - if ( bIsNaN ) return b; - - /* Neither is a NaN. How did we get here? */ - return a; -} - -/*---------------------------------------------------------------------------- -| Returns 1 if the double-precision floating-point value `a' is a NaN; -| otherwise returns 0. -*----------------------------------------------------------------------------*/ - -flag float64_is_nan( float64 a ) -{ - return 0x7ff == (0x7ff & (a >> 52)) && (0x000FFFFFFFFFFFFFLL & a); -} - -/*---------------------------------------------------------------------------- -| Returns 1 if the double-precision floating-point value `a' is a signaling -| NaN; otherwise returns 0. -*----------------------------------------------------------------------------*/ - -flag float64_is_signaling_nan( float64 a ) -{ - return float64_is_nan(a) && !(0x0008000000000000LL & a); -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the double-precision floating-point NaN -| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ - -commonNaNT float64ToCommonNaN( void* ctx, float64 a ) -{ - commonNaNT z; - - if ( float64_is_signaling_nan( a ) ) float_raise( ctx, float_flag_invalid ); - z.sign = a>>63; - z.low = 0; - z.high = a<<12; - return z; -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the canonical NaN `a' to the double- -| precision floating-point format. -*----------------------------------------------------------------------------*/ - -float64 commonNaNToFloat64( commonNaNT a ) -{ - return - ( ( (bits64) a.sign )<<63 ) - | LIT64( 0x7FF8000000000000 ) - | ( a.high>>12 ); -} - -/*---------------------------------------------------------------------------- -| Takes two double-precision floating-point values `a' and `b', one of which -| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ - -float64 propagateFloat64NaN( void* ctx, float64 a, float64 b ) -{ - flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN; - - aIsNaN = float64_is_nan( a ); - aIsSignalingNaN = float64_is_signaling_nan( a ); - bIsNaN = float64_is_nan( b ); - bIsSignalingNaN = float64_is_signaling_nan( b ); - - a |= LIT64( 0x0008000000000000 ); - b |= LIT64( 0x0008000000000000 ); - if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( ctx, float_flag_invalid ); - if ( aIsSignalingNaN ) return a; - if ( bIsSignalingNaN ) return b; - if ( aIsNaN ) return a; - if ( bIsNaN ) return b; - - /* Neither is a NaN. How did we get here? */ - return b; -} - -#ifdef FLOAT128 - -/*---------------------------------------------------------------------------- -| Returns 1 if the quadruple-precision floating-point value `a' is a NaN; -| otherwise returns 0. -*----------------------------------------------------------------------------*/ - -flag float128_is_nan( float128 a ) -{ - return - ( LIT64( 0xFFFE000000000000 ) <= (bits64) ( a.high<<1 ) ) - && ( a.low || ( a.high & LIT64( 0x0000FFFFFFFFFFFF ) ) ); -} - -/*---------------------------------------------------------------------------- -| Returns 1 if the quadruple-precision floating-point value `a' is a -| signaling NaN; otherwise returns 0. -*----------------------------------------------------------------------------*/ - -flag float128_is_signaling_nan( float128 a ) -{ - return - ( ( ( a.high>>47 ) & 0xFFFF ) == 0xFFFE ) - && ( a.low || ( a.high & LIT64( 0x00007FFFFFFFFFFF ) ) ); -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the quadruple-precision floating-point NaN -| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ - -commonNaNT float128ToCommonNaN( void* ctx, float128 a ) -{ - commonNaNT z; - - if ( float128_is_signaling_nan( a ) ) float_raise( ctx, float_flag_invalid ); - z.sign = a.high>>63; - shortShift128Left( a.high, a.low, 16, &z.high, &z.low ); - return z; -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the canonical NaN `a' to the quadruple- -| precision floating-point format. -*----------------------------------------------------------------------------*/ - -float128 commonNaNToFloat128( commonNaNT a ) -{ - float128 z; - - shift128Right( a.high, a.low, 16, &z.high, &z.low ); - z.high |= ( ( (bits64) a.sign )<<63 ) | LIT64( 0x7FFF800000000000 ); - return z; -} - -/*---------------------------------------------------------------------------- -| Takes two quadruple-precision floating-point values `a' and `b', one of -| which is a NaN, and returns the appropriate NaN result. If either `a' or -| `b' is a signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ - -float128 propagateFloat128NaN( void* ctx, float128 a, float128 b ) -{ - flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN; - - aIsNaN = float128_is_nan( a ); - aIsSignalingNaN = float128_is_signaling_nan( a ); - bIsNaN = float128_is_nan( b ); - bIsSignalingNaN = float128_is_signaling_nan( b ); - a.high |= LIT64( 0x0000800000000000 ); - b.high |= LIT64( 0x0000800000000000 ); - if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( ctx, float_flag_invalid ); - if ( aIsSignalingNaN ) return a; - if ( bIsSignalingNaN ) return b; - if ( aIsNaN ) return a; - if ( bIsNaN ) return b; - - /* Neither is a NaN. How did we get here? */ - return a; -} - -#endif - -POP_GCC_WARNINGS() diff --git a/SoftFloat-specialise.h b/SoftFloat-specialise.h deleted file mode 100644 index f5403afa7..000000000 --- a/SoftFloat-specialise.h +++ /dev/null @@ -1,210 +0,0 @@ -/* SoftFloat-specialize.h (C) John R. Hauser, 1998-2002 */ -/* (C) Copyright "Fish" (David B. Trout), 2011 */ -/* This module is part of the SoftFloat package. */ -/* */ -/* Released under "The Q Public License Version 1" */ -/* (http://www.hercules-390.org/herclic.html) */ -/* as modifications to Hercules. */ - -/* This module is a SLIGHTLY modified version of John R. Hauser's */ -/* 'SoftFloat-specialize.h', and is largely copyright by him. All */ -/* I (i.e. "Fish", David B. Trout) did was enhance it to interface */ -/* with the Hercules emulator by passing along a void* pointer to */ -/* a generic "context" structure rather than use global variables */ -/* the way it was originally written. It is 99.9999% John's work. */ -/* Refer to the documents "SoftFloat.txt", "SoftFloat-source.txt", */ -/* and "SoftFloat-history.txt" for detailed SoftFloat information. */ -/* Fish note: 'FLOATX80' support was removed as we don't need it. */ - -/* SoftFloat was repackaged to reside in the main source path */ -/* to provide FULL CROSS PLATFORM build compatibility. */ -/* To make evident the SoftFloat rePackaging standardized names */ -/* were used */ -/* mileu.h was renamed to SoftFloat-milieu.h and all the sources */ -/* were modified accordingly. */ -/* no other modifications were made */ -/* no reason to clutter the copyright stuff for such a minor change */ -/* */ -/* the original unmodified SoftFloat package is still distributed */ -/* in zipped format here as SoftFloat-2b.zip */ - -/*============================================================================ - -This C source fragment is part of the SoftFloat IEC/IEEE Floating-point -Arithmetic Package, Release 2b. - -Written by John R. Hauser. This work was made possible in part by the -International Computer Science Institute, located at Suite 600, 1947 Center -Street, Berkeley, California 94704. Funding was partially provided by the -National Science Foundation under grant MIP-9311980. The original version -of this code was written as part of a project to build a fixed-point vector -processor in collaboration with the University of California at Berkeley, -overseen by Profs. Nelson Morgan and John Wawrzynek. More information -is available through the Web page `http://www.cs.berkeley.edu/~jhauser/ -arithmetic/SoftFloat.html'. - -THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has -been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES -RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS -AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES, -COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE -EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE -INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR -OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE. - -Derivative works are acceptable, even for commercial purposes, so long as -(1) the source code for the derivative work includes prominent notice that -the work is derivative, and (2) the source code includes prominent notice with -these four paragraphs for those parts of this code that are retained. - -=============================================================================*/ - -#ifndef _SOFTFLOAT_SPECIALIZE_H_ -#define _SOFTFLOAT_SPECIALIZE_H_ - -PUSH_GCC_WARNINGS() -DISABLE_GCC_WARNING( "-Wunused-function" ) - -/*---------------------------------------------------------------------------- -| Internal canonical NaN format. -*----------------------------------------------------------------------------*/ -typedef struct { - flag sign; - bits64 high, low; -} commonNaNT; - -/*---------------------------------------------------------------------------- -| The pattern for a default generated single-precision NaN. -*----------------------------------------------------------------------------*/ -#define float32_default_nan 0xFFC00000 - -/*---------------------------------------------------------------------------- -| Returns 1 if the single-precision floating-point value `a' is a NaN; -| otherwise returns 0. -*----------------------------------------------------------------------------*/ - -flag float32_is_nan( float32 a ); - -/*---------------------------------------------------------------------------- -| Returns 1 if the single-precision floating-point value `a' is a signaling -| NaN; otherwise returns 0. -*----------------------------------------------------------------------------*/ - -flag float32_is_signaling_nan( float32 a ); - -/*---------------------------------------------------------------------------- -| Returns the result of converting the single-precision floating-point NaN -| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ - -commonNaNT float32ToCommonNaN( void* ctx, float32 a ); - -/*---------------------------------------------------------------------------- -| Returns the result of converting the canonical NaN `a' to the single- -| precision floating-point format. -*----------------------------------------------------------------------------*/ - -float32 commonNaNToFloat32( commonNaNT a ); - -/*---------------------------------------------------------------------------- -| Takes two single-precision floating-point values `a' and `b', one of which -| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ - -float32 propagateFloat32NaN( void* ctx, float32 a, float32 b ); - -/*---------------------------------------------------------------------------- -| The pattern for a default generated double-precision NaN. -*----------------------------------------------------------------------------*/ -#define float64_default_nan LIT64( 0xFFF8000000000000 ) - -/*---------------------------------------------------------------------------- -| Returns 1 if the double-precision floating-point value `a' is a NaN; -| otherwise returns 0. -*----------------------------------------------------------------------------*/ - -flag float64_is_nan( float64 a ); - -/*---------------------------------------------------------------------------- -| Returns 1 if the double-precision floating-point value `a' is a signaling -| NaN; otherwise returns 0. -*----------------------------------------------------------------------------*/ - -flag float64_is_signaling_nan( float64 a ); - -/*---------------------------------------------------------------------------- -| Returns the result of converting the double-precision floating-point NaN -| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ - -commonNaNT float64ToCommonNaN( void* ctx, float64 a ); - -/*---------------------------------------------------------------------------- -| Returns the result of converting the canonical NaN `a' to the double- -| precision floating-point format. -*----------------------------------------------------------------------------*/ - -float64 commonNaNToFloat64( commonNaNT a ); - -/*---------------------------------------------------------------------------- -| Takes two double-precision floating-point values `a' and `b', one of which -| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ - -float64 propagateFloat64NaN( void* ctx, float64 a, float64 b ); - -#ifdef FLOAT128 - -/*---------------------------------------------------------------------------- -| The pattern for a default generated quadruple-precision NaN. The `high' and -| `low' values hold the most- and least-significant bits, respectively. -*----------------------------------------------------------------------------*/ -#define float128_default_nan_high LIT64( 0xFFFF800000000000 ) -#define float128_default_nan_low LIT64( 0x0000000000000000 ) - -/*---------------------------------------------------------------------------- -| Returns 1 if the quadruple-precision floating-point value `a' is a NaN; -| otherwise returns 0. -*----------------------------------------------------------------------------*/ - -flag float128_is_nan( float128 a ); - -/*---------------------------------------------------------------------------- -| Returns 1 if the quadruple-precision floating-point value `a' is a -| signaling NaN; otherwise returns 0. -*----------------------------------------------------------------------------*/ - -flag float128_is_signaling_nan( float128 a ); - -/*---------------------------------------------------------------------------- -| Returns the result of converting the quadruple-precision floating-point NaN -| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ - -commonNaNT float128ToCommonNaN( void* ctx, float128 a ); - -/*---------------------------------------------------------------------------- -| Returns the result of converting the canonical NaN `a' to the quadruple- -| precision floating-point format. -*----------------------------------------------------------------------------*/ - -float128 commonNaNToFloat128( commonNaNT a ); - -/*---------------------------------------------------------------------------- -| Takes two quadruple-precision floating-point values `a' and `b', one of -| which is a NaN, and returns the appropriate NaN result. If either `a' or -| `b' is a signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ - -float128 propagateFloat128NaN( void* ctx, float128 a, float128 b ); - -#endif //FLOAT128 - -POP_GCC_WARNINGS() - -#endif // _SOFTFLOAT_SPECIALIZE_H_ diff --git a/SoftFloat-types.h b/SoftFloat-types.h deleted file mode 100644 index f36bf8af5..000000000 --- a/SoftFloat-types.h +++ /dev/null @@ -1,144 +0,0 @@ -/* SoftFloat-types.h (C) John R. Hauser, 1998-2002 */ -/* (C) Copyright "Fish" (David B. Trout), 2011 */ -/* This module is part of the SoftFloat package. */ -/* */ -/* Released under "The Q Public License Version 1" */ -/* (http://www.hercules-390.org/herclic.html) */ -/* as modifications to Hercules. */ - -/* This module is a SLIGHTLY modified version of John R. Hauser's */ -/* 'SoftFloat-types.h', and is largely copyright by him. All I did */ -/* (i.e. "Fish", David B. Trout) was change the default underflow */ -/* tininess-detection mode, rounding mode and exception flags values */ -/* to match values required by z/Architecture and to integrate it */ -/* with the Hercules emulator. It is 99.9999% John's work. Refer */ -/* to the documents "SoftFloat.txt", "SoftFloat-source.txt", and */ -/* "SoftFloat-history.txt" for detailed SoftFloat information. */ -/* Fish note: 'FLOATX80' support was removed as we don't need it. */ - -/* SoftFloat was repackaged to reside in the main source path */ -/* to provide FULL CROSS PLATFORM build compatibility. */ -/* To make evident the SoftFloat rePackaging standardized names */ -/* were used */ -/* mileu.h was renamed to SoftFloat-milieu.h and all the sources */ -/* were modified accordingly. */ -/* no other modifications were made */ -/* no reason to clutter the copyright stuff for such a minor change */ -/* */ -/* the original unmodified SoftFloat package is still distributed */ -/* in zipped format here as SoftFloat-2b.zip */ - -#ifndef _SOFTFLOAT_TYPES_H_ -#define _SOFTFLOAT_TYPES_H_ - -/*---------------------------------------------------------------------------- -| One of the macros `BIGENDIAN' or `LITTLEENDIAN' must be defined. -*----------------------------------------------------------------------------*/ -#if 0 // never referenced! -#define LITTLEENDIAN -#endif - -/*---------------------------------------------------------------------------- -| The macro `BITS64' can be defined to indicate that 64-bit integer types are -| supported by the compiler. -*----------------------------------------------------------------------------*/ -#define BITS64 - -/*---------------------------------------------------------------------------- -| Each of the following `typedef's defines the most convenient type that holds -| integers of at least as many bits as specified. For example, `uint8' should -| be the most convenient type that can hold unsigned integers of as many as -| 8 bits. The `flag' type must be able to hold either a 0 or 1. For most -| implementations of C, `flag', `uint8', and `int8' should all be `typedef'ed -| to the same as `int'. -*----------------------------------------------------------------------------*/ -typedef char flag; -typedef unsigned char uint8; -typedef signed char int8; -typedef int uint16; -typedef int int16; -typedef unsigned int uint32; -typedef signed int int32; -#ifdef BITS64 -typedef unsigned long long int uint64; -typedef signed long long int int64; -#endif - -/*---------------------------------------------------------------------------- -| Each of the following `typedef's defines a type that holds integers -| of _exactly_ the number of bits specified. For instance, for most -| implementation of C, `bits16' and `sbits16' should be `typedef'ed to -| `unsigned short int' and `signed short int' (or `short int'), respectively. -*----------------------------------------------------------------------------*/ -typedef unsigned char bits8; -typedef signed char sbits8; -typedef unsigned short int bits16; -typedef signed short int sbits16; -typedef unsigned int bits32; -typedef signed int sbits32; -#ifdef BITS64 -typedef unsigned long long int bits64; -typedef signed long long int sbits64; -#endif - -#ifdef BITS64 -/*---------------------------------------------------------------------------- -| The `LIT64' macro takes as its argument a textual integer literal and -| if necessary ``marks'' the literal as having a 64-bit integer type. -| For example, the GNU C Compiler (`gcc') requires that 64-bit literals be -| appended with the letters `LL' standing for `long long', which is `gcc's -| name for the 64-bit integer type. Some compilers may allow `LIT64' to be -| defined as the identity macro: `#define LIT64( a ) a'. -*----------------------------------------------------------------------------*/ -#define LIT64( a ) a##LL -#endif - -/*---------------------------------------------------------------------------- -| The macro `INLINE' can be used before functions that should be inlined. If -| a compiler does not support explicit inlining, this macro should be defined -| to be `static'. -*----------------------------------------------------------------------------*/ -#ifndef INLINE -#define INLINE __inline -#endif - -/*---------------------------------------------------------------------------- -| The following macro can be used in switch statements to tell the compiler -| that the default branch of the switch statement will never be reached. -*----------------------------------------------------------------------------*/ -#ifndef NODEFAULT -#define NODEFAULT default: UNREACHABLE_CODE( break ); -#endif - -/*---------------------------------------------------------------------------- -| Software IEC/IEEE floating-point underflow tininess-detection mode. -*----------------------------------------------------------------------------*/ -enum { - float_tininess_after_rounding = 0, - float_tininess_before_rounding = 1 /* SA22-7832-08, page 9-22 */ -}; - -/*---------------------------------------------------------------------------- -| Software IEC/IEEE floating-point rounding mode. -*----------------------------------------------------------------------------*/ -enum { - /* These must match the FPC values */ - float_round_nearest_even = 0, - float_round_to_zero = 1, - float_round_up = 2, - float_round_down = 3 -}; - -/*---------------------------------------------------------------------------- -| Software IEC/IEEE floating-point exception flags. -*----------------------------------------------------------------------------*/ -enum { - /* These must match the FPC values */ - float_flag_invalid = 0x00800000, - float_flag_divbyzero = 0x00400000, - float_flag_overflow = 0x00200000, - float_flag_underflow = 0x00100000, - float_flag_inexact = 0x00080000 -}; - -#endif // _SOFTFLOAT_TYPES_H_ diff --git a/SoftFloat.c b/SoftFloat.c deleted file mode 100644 index f96e90c39..000000000 --- a/SoftFloat.c +++ /dev/null @@ -1,3811 +0,0 @@ -/* SoftFloat.c (C) John R. Hauser, 1998-2002 */ -/* (C) Copyright "Fish" (David B. Trout), 2011 */ -/* This module is part of the SoftFloat package. */ -/* */ -/* Released under "The Q Public License Version 1" */ -/* (http://www.hercules-390.org/herclic.html) */ -/* as modifications to Hercules. */ - -/* This module is a SLIGHTLY modified version of John R. Hauser's */ -/* original 'SoftFloat.c' module, and is largely copyright by him. */ -/* I (i.e. "Fish", David B. Trout) simply enhanced it to interface */ -/* with the Hercules emulator by passing along a void* pointer to */ -/* a generic "context" structure rather than use global variables */ -/* the way it was originally written. It is 99.9999% John's work. */ -/* Refer to the documents "SoftFloat.txt", "SoftFloat-source.txt", */ -/* and "SoftFloat-history.txt" for detailed SoftFloat information. */ -/* Fish note: 'FLOATX80' support was removed as we don't need it. */ - -/* SoftFloat was repackaged to reside in the main source path */ -/* to provide FULL CROSS PLATFORM build compatibility. */ -/* To make evident the SoftFloat rePackaging standardized names */ -/* were used */ -/* mileu.h was renamed to SoftFloat-milieu.h and all the sources */ -/* were modified accordingly. */ -/* no other modifications were made */ -/* no reason to clutter the copyright stuff for such a minor change */ -/* */ -/* the original unmodified SoftFloat package is still distributed */ -/* in zipped format here as SoftFloat-2b.zip */ - -/*============================================================================ - -This C source file is part of the SoftFloat IEC/IEEE Floating-point Arithmetic -Package, Release 2b. - -Written by John R. Hauser. This work was made possible in part by the -International Computer Science Institute, located at Suite 600, 1947 Center -Street, Berkeley, California 94704. Funding was partially provided by the -National Science Foundation under grant MIP-9311980. The original version -of this code was written as part of a project to build a fixed-point vector -processor in collaboration with the University of California at Berkeley, -overseen by Profs. Nelson Morgan and John Wawrzynek. More information -is available through the Web page `http://www.cs.berkeley.edu/~jhauser/ -arithmetic/SoftFloat.html'. - -THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has -been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES -RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS -AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES, -COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE -EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE -INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR -OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE. - -Derivative works are acceptable, even for commercial purposes, so long as -(1) the source code for the derivative work includes prominent notice that -the work is derivative, and (2) the source code includes prominent notice with -these four paragraphs for those parts of this code that are retained. - -=============================================================================*/ - -#include "hstdinc.h" -#include "hercules.h" - -#include "SoftFloat-milieu.h" -#include "SoftFloat-types.h" -#include "SoftFloat.h" -#include "SoftFloat-macros.h" -#include "SoftFloat-specialise.h" - -/*---------------------------------------------------------------------------- -| Takes a 64-bit fixed-point value `absZ' with binary point between bits 6 -| and 7, and returns the properly rounded 32-bit integer corresponding to the -| input. If `zSign' is 1, the input is negated before being converted to an -| integer. Bit 63 of `absZ' must be zero. Ordinarily, the fixed-point input -| is simply rounded to an integer, with the inexact exception raised if the -| input cannot be represented exactly as an integer. However, if the fixed- -| point input is too large, the invalid exception is raised and the largest -| positive or negative integer is returned. -*----------------------------------------------------------------------------*/ - -static int32 roundAndPackInt32( void* ctx, flag zSign, bits64 absZ ) -{ - int8 roundingMode; - flag roundNearestEven; - int8 roundIncrement, roundBits; - int32 z; - - roundingMode = get_float_rounding_mode( ctx ); - roundNearestEven = ( roundingMode == float_round_nearest_even ); - roundIncrement = 0x40; - if ( ! roundNearestEven ) { - if ( roundingMode == float_round_to_zero ) { - roundIncrement = 0; - } - else { - roundIncrement = 0x7F; - if ( zSign ) { - if ( roundingMode == float_round_up ) roundIncrement = 0; - } - else { - if ( roundingMode == float_round_down ) roundIncrement = 0; - } - } - } - roundBits = absZ & 0x7F; - absZ = ( absZ + roundIncrement )>>7; - absZ &= ~ ( ( ( roundBits ^ 0x40 ) == 0 ) & roundNearestEven ); - z = absZ; - if ( zSign ) z = - z; - if ( ( absZ>>32 ) || ( z && ( ( z < 0 ) ^ zSign ) ) ) { - float_raise( ctx, float_flag_inexact ); /*@Z900*/ - float_raise( ctx, float_flag_invalid ); - return zSign ? (sbits32) 0x80000000 : 0x7FFFFFFF; - } - if ( roundBits ) set_exception_flags( ctx, float_flag_inexact ); - return z; - -} - -/*---------------------------------------------------------------------------- -| Takes the 128-bit fixed-point value formed by concatenating `absZ0' and -| `absZ1', with binary point between bits 63 and 64 (between the input words), -| and returns the properly rounded 64-bit integer corresponding to the input. -| If `zSign' is 1, the input is negated before being converted to an integer. -| Ordinarily, the fixed-point input is simply rounded to an integer, with -| the inexact exception raised if the input cannot be represented exactly as -| an integer. However, if the fixed-point input is too large, the invalid -| exception is raised and the largest positive or negative integer is -| returned. -*----------------------------------------------------------------------------*/ - -static int64 roundAndPackInt64( void* ctx, flag zSign, bits64 absZ0, bits64 absZ1 ) -{ - int8 roundingMode; - flag roundNearestEven, increment; - int64 z; - - roundingMode = get_float_rounding_mode( ctx ); - roundNearestEven = ( roundingMode == float_round_nearest_even ); - increment = ( (sbits64) absZ1 < 0 ); - if ( ! roundNearestEven ) { - if ( roundingMode == float_round_to_zero ) { - increment = 0; - } - else { - if ( zSign ) { - increment = ( roundingMode == float_round_down ) && absZ1; - } - else { - increment = ( roundingMode == float_round_up ) && absZ1; - } - } - } - if ( increment ) { - ++absZ0; - if ( absZ0 == 0 ) goto overflow; - absZ0 &= ~ ( ( (bits64) ( absZ1<<1 ) == 0 ) & roundNearestEven ); - } - z = absZ0; - if ( zSign ) z = - z; - if ( z && ( ( z < 0 ) ^ zSign ) ) { - overflow: - float_raise( ctx, float_flag_inexact ); /*@Z900*/ - float_raise( ctx, float_flag_invalid ); - return - zSign ? (sbits64) LIT64( 0x8000000000000000 ) - : LIT64( 0x7FFFFFFFFFFFFFFF ); - } - if ( absZ1 ) set_exception_flags( ctx, float_flag_inexact ); - return z; - -} - -/*---------------------------------------------------------------------------- -| Returns the fraction bits of the single-precision floating-point value `a'. -*----------------------------------------------------------------------------*/ - -static INLINE bits32 extractFloat32Frac( float32 a ) -{ - - return a & 0x007FFFFF; - -} - -/*---------------------------------------------------------------------------- -| Returns the exponent bits of the single-precision floating-point value `a'. -*----------------------------------------------------------------------------*/ - -static INLINE int16 extractFloat32Exp( float32 a ) -{ - - return ( a>>23 ) & 0xFF; - -} - -/*---------------------------------------------------------------------------- -| Returns the sign bit of the single-precision floating-point value `a'. -*----------------------------------------------------------------------------*/ - -static INLINE flag extractFloat32Sign( float32 a ) -{ - - return a>>31; - -} - -/*---------------------------------------------------------------------------- -| Normalizes the subnormal single-precision floating-point value represented -| by the denormalized significand `aSig'. The normalized exponent and -| significand are stored at the locations pointed to by `zExpPtr' and -| `zSigPtr', respectively. -*----------------------------------------------------------------------------*/ - -static void - normalizeFloat32Subnormal( bits32 aSig, int16 *zExpPtr, bits32 *zSigPtr ) -{ - int8 shiftCount; - - shiftCount = countLeadingZeros32( aSig ) - 8; - *zSigPtr = aSig<>7; - zSig &= ~ ( ( ( roundBits ^ 0x40 ) == 0 ) & roundNearestEven ); - if ( zSig == 0 ) zExp = 0; - return packFloat32( zSign, zExp, zSig ); - -} - -/*---------------------------------------------------------------------------- -| Takes an abstract floating-point value having sign `zSign', exponent `zExp', -| and significand `zSig', and returns the proper single-precision floating- -| point value corresponding to the abstract input. This routine is just like -| `roundAndPackFloat32' except that `zSig' does not have to be normalized. -| Bit 31 of `zSig' must be zero, and `zExp' must be 1 less than the ``true'' -| floating-point exponent. -*----------------------------------------------------------------------------*/ - -static float32 - normalizeRoundAndPackFloat32( void* ctx, flag zSign, int16 zExp, bits32 zSig ) -{ - int8 shiftCount; - - shiftCount = countLeadingZeros32( zSig ) - 1; - - if (shiftCount >= 0) - return roundAndPackFloat32( ctx, zSign, zExp - shiftCount, zSig << shiftCount ); - else - return roundAndPackFloat32( ctx, zSign, zExp + 1, zSig >> 1 ); -} - -/*---------------------------------------------------------------------------- -| Returns the fraction bits of the double-precision floating-point value `a'. -*----------------------------------------------------------------------------*/ - -static INLINE bits64 extractFloat64Frac( float64 a ) -{ - - return a & LIT64( 0x000FFFFFFFFFFFFF ); - -} - -/*---------------------------------------------------------------------------- -| Returns the exponent bits of the double-precision floating-point value `a'. -*----------------------------------------------------------------------------*/ - -static INLINE int16 extractFloat64Exp( float64 a ) -{ - - return ( a>>52 ) & 0x7FF; - -} - -/*---------------------------------------------------------------------------- -| Returns the sign bit of the double-precision floating-point value `a'. -*----------------------------------------------------------------------------*/ - -static INLINE flag extractFloat64Sign( float64 a ) -{ - - return a>>63; - -} - -/*---------------------------------------------------------------------------- -| Normalizes the subnormal double-precision floating-point value represented -| by the denormalized significand `aSig'. The normalized exponent and -| significand are stored at the locations pointed to by `zExpPtr' and -| `zSigPtr', respectively. -*----------------------------------------------------------------------------*/ - -static void - normalizeFloat64Subnormal( bits64 aSig, int16 *zExpPtr, bits64 *zSigPtr ) -{ - int8 shiftCount; - - shiftCount = countLeadingZeros64( aSig ) - 11; - *zSigPtr = aSig<>10; - zSig &= ~ ( ( ( roundBits ^ 0x200 ) == 0 ) & roundNearestEven ); - if ( zSig == 0 ) zExp = 0; - return packFloat64( zSign, zExp, zSig ); - -} - -/*---------------------------------------------------------------------------- -| Takes an abstract floating-point value having sign `zSign', exponent `zExp', -| and significand `zSig', and returns the proper double-precision floating- -| point value corresponding to the abstract input. This routine is just like -| `roundAndPackFloat64' except that `zSig' does not have to be normalized. -| Bit 63 of `zSig' must be zero, and `zExp' must be 1 less than the ``true'' -| floating-point exponent. -*----------------------------------------------------------------------------*/ - -static float64 - normalizeRoundAndPackFloat64( void* ctx, flag zSign, int16 zExp, bits64 zSig ) -{ - int8 shiftCount; - - shiftCount = countLeadingZeros64( zSig ) - 1; - - if (shiftCount >= 0) - return roundAndPackFloat64( ctx, zSign, zExp - shiftCount, zSig << shiftCount ); - else - return roundAndPackFloat64( ctx, zSign, zExp + 1, zSig >> 1 ); -} - -#ifdef FLOAT128 - -/*---------------------------------------------------------------------------- -| Returns the least-significant 64 fraction bits of the quadruple-precision -| floating-point value `a'. -*----------------------------------------------------------------------------*/ - -static INLINE bits64 extractFloat128Frac1( float128 a ) -{ - - return a.low; - -} - -/*---------------------------------------------------------------------------- -| Returns the most-significant 48 fraction bits of the quadruple-precision -| floating-point value `a'. -*----------------------------------------------------------------------------*/ - -static INLINE bits64 extractFloat128Frac0( float128 a ) -{ - - return a.high & LIT64( 0x0000FFFFFFFFFFFF ); - -} - -/*---------------------------------------------------------------------------- -| Returns the exponent bits of the quadruple-precision floating-point value -| `a'. -*----------------------------------------------------------------------------*/ - -static INLINE int32 extractFloat128Exp( float128 a ) -{ - - return ( a.high>>48 ) & 0x7FFF; - -} - -/*---------------------------------------------------------------------------- -| Returns the sign bit of the quadruple-precision floating-point value `a'. -*----------------------------------------------------------------------------*/ - -static INLINE flag extractFloat128Sign( float128 a ) -{ - - return a.high>>63; - -} - -/*---------------------------------------------------------------------------- -| Normalizes the subnormal quadruple-precision floating-point value -| represented by the denormalized significand formed by the concatenation of -| `aSig0' and `aSig1'. The normalized exponent is stored at the location -| pointed to by `zExpPtr'. The most significant 49 bits of the normalized -| significand are stored at the location pointed to by `zSig0Ptr', and the -| least significant 64 bits of the normalized significand are stored at the -| location pointed to by `zSig1Ptr'. -*----------------------------------------------------------------------------*/ - -static void - normalizeFloat128Subnormal( - bits64 aSig0, - bits64 aSig1, - int32 *zExpPtr, - bits64 *zSig0Ptr, - bits64 *zSig1Ptr - ) -{ - int8 shiftCount; - - if ( aSig0 == 0 ) { - shiftCount = countLeadingZeros64( aSig1 ) - 15; - if ( shiftCount < 0 ) { - *zSig0Ptr = aSig1>>( - shiftCount ); - *zSig1Ptr = aSig1<<( shiftCount & 63 ); - } - else { - *zSig0Ptr = aSig1<>( - shiftCount ); - if ( (bits32) ( aSig<<( shiftCount & 31 ) ) ) { - set_exception_flags( ctx, float_flag_inexact ); - } - if ( aSign ) z = - z; - return z; - -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the single-precision floating-point value -| `a' to the 64-bit two's complement integer format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic---which means in particular that the conversion is rounded -| according to the current rounding mode. If `a' is a NaN, the largest -| positive integer is returned. Otherwise, if the conversion overflows, the -| largest integer with the same sign as `a' is returned. -*----------------------------------------------------------------------------*/ - -int64 float32_to_int64( void* ctx, float32 a ) -{ - flag aSign; - int16 aExp, shiftCount; - bits32 aSig; - bits64 aSig64, aSigExtra; - - aSig = extractFloat32Frac( a ); - aExp = extractFloat32Exp( a ); - aSign = extractFloat32Sign( a ); - shiftCount = 0xBE - aExp; - if ( shiftCount < 0 ) { - float_raise( ctx, float_flag_inexact ); /*@Z900*/ - float_raise( ctx, float_flag_invalid ); - if ( ( aExp == 0xFF ) && aSig ) { /*@Z900*/ - return LIT64( 0x8000000000000000 ); /*@Z900*/ - } /*@Z900*/ - if ( ! aSign || ( ( aExp == 0xFF ) && aSig ) ) { - return LIT64( 0x7FFFFFFFFFFFFFFF ); - } - return (sbits64) LIT64( 0x8000000000000000 ); - } - if ( aExp ) aSig |= 0x00800000; - aSig64 = aSig; - aSig64 <<= 40; - shift64ExtraRightJamming( aSig64, 0, shiftCount, &aSig64, &aSigExtra ); - return roundAndPackInt64( ctx, aSign, aSig64, aSigExtra ); - -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the single-precision floating-point value -| `a' to the 64-bit two's complement integer format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic, except that the conversion is always rounded toward zero. If -| `a' is a NaN, the largest positive integer is returned. Otherwise, if the -| conversion overflows, the largest integer with the same sign as `a' is -| returned. -*----------------------------------------------------------------------------*/ - -int64 float32_to_int64_round_to_zero( void* ctx, float32 a ) -{ - flag aSign; - int16 aExp, shiftCount; - bits32 aSig; - bits64 aSig64; - int64 z; - - aSig = extractFloat32Frac( a ); - aExp = extractFloat32Exp( a ); - aSign = extractFloat32Sign( a ); - shiftCount = aExp - 0xBE; - if ( 0 <= shiftCount ) { - if ( a != 0xDF000000 ) { - float_raise( ctx, float_flag_inexact ); /*@Z900*/ - float_raise( ctx, float_flag_invalid ); - if ( ( aExp == 0xFF ) && aSig ) { /*@Z900*/ - return LIT64( 0x8000000000000000 ); /*@Z900*/ - } /*@Z900*/ - if ( ! aSign || ( ( aExp == 0xFF ) && aSig ) ) { - return LIT64( 0x7FFFFFFFFFFFFFFF ); - } - } - return (sbits64) LIT64( 0x8000000000000000 ); - } - else if ( aExp <= 0x7E ) { - if ( aExp | aSig ) set_exception_flags( ctx, float_flag_inexact ); - return 0; - } - aSig64 = aSig | 0x00800000; - aSig64 <<= 40; - z = aSig64>>( - shiftCount ); - if ( (bits64) ( aSig64<<( shiftCount & 63 ) ) ) { - set_exception_flags( ctx, float_flag_inexact ); - } - if ( aSign ) z = - z; - return z; - -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the single-precision floating-point value -| `a' to the double-precision floating-point format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic. -*----------------------------------------------------------------------------*/ - -float64 float32_to_float64( void* ctx, float32 a ) -{ - flag aSign; - int16 aExp; - bits32 aSig; - - aSig = extractFloat32Frac( a ); - aExp = extractFloat32Exp( a ); - aSign = extractFloat32Sign( a ); - if ( aExp == 0xFF ) { - if ( aSig ) return commonNaNToFloat64( float32ToCommonNaN( ctx, a ) ); - return packFloat64( aSign, 0x7FF, 0 ); - } - if ( aExp == 0 ) { - if ( aSig == 0 ) return packFloat64( aSign, 0, 0 ); - normalizeFloat32Subnormal( aSig, &aExp, &aSig ); - --aExp; - } - return packFloat64( aSign, aExp + 0x380, ( (bits64) aSig )<<29 ); - -} - -#ifdef FLOAT128 - -/*---------------------------------------------------------------------------- -| Returns the result of converting the single-precision floating-point value -| `a' to the double-precision floating-point format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic. -*----------------------------------------------------------------------------*/ - -float128 float32_to_float128( void* ctx, float32 a ) -{ - flag aSign; - int16 aExp; - bits32 aSig; - - aSig = extractFloat32Frac( a ); - aExp = extractFloat32Exp( a ); - aSign = extractFloat32Sign( a ); - if ( aExp == 0xFF ) { - if ( aSig ) return commonNaNToFloat128( float32ToCommonNaN( ctx, a ) ); - return packFloat128( aSign, 0x7FFF, 0, 0 ); - } - if ( aExp == 0 ) { - if ( aSig == 0 ) return packFloat128( aSign, 0, 0, 0 ); - normalizeFloat32Subnormal( aSig, &aExp, &aSig ); - --aExp; - } - return packFloat128( aSign, aExp + 0x3F80, ( (bits64) aSig )<<25, 0 ); - -} - -#endif - -/*---------------------------------------------------------------------------- -| Rounds the single-precision floating-point value `a' to an integer, and -| returns the result as a single-precision floating-point value. The -| operation is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -float32 float32_round_to_int( void* ctx, float32 a ) -{ - flag aSign; - int16 aExp; - bits32 lastBitMask, roundBitsMask; - int8 roundingMode; - float32 z; - - aExp = extractFloat32Exp( a ); - if ( 0x96 <= aExp ) { - if ( ( aExp == 0xFF ) && extractFloat32Frac( a ) ) { - return propagateFloat32NaN( ctx, a, a ); - } - return a; - } - if ( aExp <= 0x7E ) { - if ( (bits32) ( a<<1 ) == 0 ) return a; - set_exception_flags( ctx, float_flag_inexact ); - aSign = extractFloat32Sign( a ); - switch ( get_float_rounding_mode( ctx ) ) { - case float_round_nearest_even: - if ( ( aExp == 0x7E ) && extractFloat32Frac( a ) ) { - return packFloat32( aSign, 0x7F, 0 ); - } - break; - case float_round_down: - return aSign ? 0xBF800000 : 0; - case float_round_up: - return aSign ? 0x80000000 : 0x3F800000; - } - return packFloat32( aSign, 0, 0 ); - } - lastBitMask = 1; - lastBitMask <<= 0x96 - aExp; - roundBitsMask = lastBitMask - 1; - z = a; - roundingMode = get_float_rounding_mode( ctx ); - if ( roundingMode == float_round_nearest_even ) { - z += lastBitMask>>1; - if ( ( z & roundBitsMask ) == 0 ) z &= ~ lastBitMask; - } - else if ( roundingMode != float_round_to_zero ) { - if ( extractFloat32Sign( z ) ^ ( roundingMode == float_round_up ) ) { - z += roundBitsMask; - } - } - z &= ~ roundBitsMask; - if ( z != a ) set_exception_flags( ctx, float_flag_inexact ); - return z; - -} - -/*---------------------------------------------------------------------------- -| Returns the result of adding the absolute values of the single-precision -| floating-point values `a' and `b'. If `zSign' is 1, the sum is negated -| before being returned. `zSign' is ignored if the result is a NaN. -| The addition is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -static float32 addFloat32Sigs( void* ctx, float32 a, float32 b, flag zSign ) -{ - int16 aExp, bExp, zExp; - bits32 aSig, bSig, zSig; - int16 expDiff; - - aSig = extractFloat32Frac( a ); - aExp = extractFloat32Exp( a ); - bSig = extractFloat32Frac( b ); - bExp = extractFloat32Exp( b ); - expDiff = aExp - bExp; - aSig <<= 6; - bSig <<= 6; - if ( 0 < expDiff ) { - if ( aExp == 0xFF ) { - if ( aSig ) return propagateFloat32NaN( ctx, a, b ); - return a; - } - if ( bExp == 0 ) { - --expDiff; - } - else { - bSig |= 0x20000000; - } - shift32RightJamming( bSig, expDiff, &bSig ); - zExp = aExp; - } - else if ( expDiff < 0 ) { - if ( bExp == 0xFF ) { - if ( bSig ) return propagateFloat32NaN( ctx, a, b ); - return packFloat32( zSign, 0xFF, 0 ); - } - if ( aExp == 0 ) { - ++expDiff; - } - else { - aSig |= 0x20000000; - } - shift32RightJamming( aSig, - expDiff, &aSig ); - zExp = bExp; - } - else { - if ( aExp == 0xFF ) { - if ( aSig | bSig ) return propagateFloat32NaN( ctx, a, b ); - return a; - } - if ( aExp == 0 ) return packFloat32( zSign, 0, ( aSig + bSig )>>6 ); - zSig = 0x40000000 + aSig + bSig; - zExp = aExp; - goto roundAndPack; - } - aSig |= 0x20000000; - zSig = ( aSig + bSig )<<1; - --zExp; - if ( (sbits32) zSig < 0 ) { - zSig = aSig + bSig; - ++zExp; - } - roundAndPack: - return roundAndPackFloat32( ctx, zSign, zExp, zSig ); - -} - -/*---------------------------------------------------------------------------- -| Returns the result of subtracting the absolute values of the single- -| precision floating-point values `a' and `b'. If `zSign' is 1, the -| difference is negated before being returned. `zSign' is ignored if the -| result is a NaN. The subtraction is performed according to the IEC/IEEE -| Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -static float32 subFloat32Sigs( void* ctx, float32 a, float32 b, flag zSign ) -{ - int16 aExp, bExp, zExp; - bits32 aSig, bSig, zSig; - int16 expDiff; - - aSig = extractFloat32Frac( a ); - aExp = extractFloat32Exp( a ); - bSig = extractFloat32Frac( b ); - bExp = extractFloat32Exp( b ); - expDiff = aExp - bExp; - aSig <<= 7; - bSig <<= 7; - if ( 0 < expDiff ) goto aExpBigger; - if ( expDiff < 0 ) goto bExpBigger; - if ( aExp == 0xFF ) { - if ( aSig | bSig ) return propagateFloat32NaN( ctx, a, b ); - float_raise( ctx, float_flag_invalid ); - return float32_default_nan; - } - if ( aExp == 0 ) { - aExp = 1; - bExp = 1; - } - if ( bSig < aSig ) goto aBigger; - if ( aSig < bSig ) goto bBigger; - return packFloat32( get_float_rounding_mode( ctx ) == float_round_down, 0, 0 ); - bExpBigger: - if ( bExp == 0xFF ) { - if ( bSig ) return propagateFloat32NaN( ctx, a, b ); - return packFloat32( zSign ^ 1, 0xFF, 0 ); - } - if ( aExp == 0 ) { - ++expDiff; - } - else { - aSig |= 0x40000000; - } - shift32RightJamming( aSig, - expDiff, &aSig ); - bSig |= 0x40000000; - bBigger: - zSig = bSig - aSig; - zExp = bExp; - zSign ^= 1; - goto normalizeRoundAndPack; - aExpBigger: - if ( aExp == 0xFF ) { - if ( aSig ) return propagateFloat32NaN( ctx, a, b ); - return a; - } - if ( bExp == 0 ) { - --expDiff; - } - else { - bSig |= 0x40000000; - } - shift32RightJamming( bSig, expDiff, &bSig ); - aSig |= 0x40000000; - aBigger: - zSig = aSig - bSig; - zExp = aExp; - normalizeRoundAndPack: - --zExp; - return normalizeRoundAndPackFloat32( ctx, zSign, zExp, zSig ); - -} - -/*---------------------------------------------------------------------------- -| Returns the result of adding the single-precision floating-point values `a' -| and `b'. The operation is performed according to the IEC/IEEE Standard for -| Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -float32 float32_add( void* ctx, float32 a, float32 b ) -{ - flag aSign, bSign; - - aSign = extractFloat32Sign( a ); - bSign = extractFloat32Sign( b ); - if ( aSign == bSign ) { - return addFloat32Sigs( ctx, a, b, aSign ); - } - else { - return subFloat32Sigs( ctx, a, b, aSign ); - } - -} - -/*---------------------------------------------------------------------------- -| Returns the result of subtracting the single-precision floating-point values -| `a' and `b'. The operation is performed according to the IEC/IEEE Standard -| for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -float32 float32_sub( void* ctx, float32 a, float32 b ) -{ - flag aSign, bSign; - - aSign = extractFloat32Sign( a ); - bSign = extractFloat32Sign( b ); - if ( aSign == bSign ) { - return subFloat32Sigs( ctx, a, b, aSign ); - } - else { - return addFloat32Sigs( ctx, a, b, aSign ); - } - -} - -/*---------------------------------------------------------------------------- -| Returns the result of multiplying the single-precision floating-point values -| `a' and `b'. The operation is performed according to the IEC/IEEE Standard -| for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -float32 float32_mul( void* ctx, float32 a, float32 b ) -{ - flag aSign, bSign, zSign; - int16 aExp, bExp, zExp; - bits32 aSig, bSig; - bits64 zSig64; - bits32 zSig; - - aSig = extractFloat32Frac( a ); - aExp = extractFloat32Exp( a ); - aSign = extractFloat32Sign( a ); - bSig = extractFloat32Frac( b ); - bExp = extractFloat32Exp( b ); - bSign = extractFloat32Sign( b ); - zSign = aSign ^ bSign; - if ( aExp == 0xFF ) { - if ( aSig || ( ( bExp == 0xFF ) && bSig ) ) { - return propagateFloat32NaN( ctx, a, b ); - } - if ( ( bExp | bSig ) == 0 ) { - float_raise( ctx, float_flag_invalid ); - return float32_default_nan; - } - return packFloat32( zSign, 0xFF, 0 ); - } - if ( bExp == 0xFF ) { - if ( bSig ) return propagateFloat32NaN( ctx, a, b ); - if ( ( aExp | aSig ) == 0 ) { - float_raise( ctx, float_flag_invalid ); - return float32_default_nan; - } - return packFloat32( zSign, 0xFF, 0 ); - } - if ( aExp == 0 ) { - if ( aSig == 0 ) return packFloat32( zSign, 0, 0 ); - normalizeFloat32Subnormal( aSig, &aExp, &aSig ); - } - if ( bExp == 0 ) { - if ( bSig == 0 ) return packFloat32( zSign, 0, 0 ); - normalizeFloat32Subnormal( bSig, &bExp, &bSig ); - } - zExp = aExp + bExp - 0x7F; - aSig = ( aSig | 0x00800000 )<<7; - bSig = ( bSig | 0x00800000 )<<8; - shift64RightJamming( ( (bits64) aSig ) * bSig, 32, &zSig64 ); - zSig = zSig64; - if ( 0 <= (sbits32) ( zSig<<1 ) ) { - zSig <<= 1; - --zExp; - } - return roundAndPackFloat32( ctx, zSign, zExp, zSig ); - -} - -/*---------------------------------------------------------------------------- -| Returns the result of dividing the single-precision floating-point value `a' -| by the corresponding value `b'. The operation is performed according to the -| IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -float32 float32_div( void* ctx, float32 a, float32 b ) -{ - flag aSign, bSign, zSign; - int16 aExp, bExp, zExp; - bits32 aSig, bSig, zSig; - - aSig = extractFloat32Frac( a ); - aExp = extractFloat32Exp( a ); - aSign = extractFloat32Sign( a ); - bSig = extractFloat32Frac( b ); - bExp = extractFloat32Exp( b ); - bSign = extractFloat32Sign( b ); - zSign = aSign ^ bSign; - if ( aExp == 0xFF ) { - if ( aSig ) return propagateFloat32NaN( ctx, a, b ); - if ( bExp == 0xFF ) { - if ( bSig ) return propagateFloat32NaN( ctx, a, b ); - float_raise( ctx, float_flag_invalid ); - return float32_default_nan; - } - return packFloat32( zSign, 0xFF, 0 ); - } - if ( bExp == 0xFF ) { - if ( bSig ) return propagateFloat32NaN( ctx, a, b ); - return packFloat32( zSign, 0, 0 ); - } - if ( bExp == 0 ) { - if ( bSig == 0 ) { - if ( ( aExp | aSig ) == 0 ) { - float_raise( ctx, float_flag_invalid ); - return float32_default_nan; - } - float_raise( ctx, float_flag_divbyzero ); - return packFloat32( zSign, 0xFF, 0 ); - } - normalizeFloat32Subnormal( bSig, &bExp, &bSig ); - } - if ( aExp == 0 ) { - if ( aSig == 0 ) return packFloat32( zSign, 0, 0 ); - normalizeFloat32Subnormal( aSig, &aExp, &aSig ); - } - zExp = aExp - bExp + 0x7D; - aSig = ( aSig | 0x00800000 )<<7; - bSig = ( bSig | 0x00800000 )<<8; - if ( bSig <= ( aSig + aSig ) ) { - aSig >>= 1; - ++zExp; - } - zSig = ( ( (bits64) aSig )<<32 ) / bSig; - if ( ( zSig & 0x3F ) == 0 ) { - zSig |= ( (bits64) bSig * zSig != ( (bits64) aSig )<<32 ); - } - return roundAndPackFloat32( ctx, zSign, zExp, zSig ); - -} - -/*---------------------------------------------------------------------------- -| Returns the remainder of the single-precision floating-point value `a' -| with respect to the corresponding value `b'. The operation is performed -| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -float32 float32_rem( void* ctx, float32 a, float32 b ) -{ - flag aSign, bSign, zSign; - int16 aExp, bExp, expDiff; - bits32 aSig, bSig; - bits32 q; - bits64 aSig64, bSig64, q64; - bits32 alternateASig; - sbits32 sigMean; - - aSig = extractFloat32Frac( a ); - aExp = extractFloat32Exp( a ); - aSign = extractFloat32Sign( a ); - bSig = extractFloat32Frac( b ); - bExp = extractFloat32Exp( b ); - bSign = extractFloat32Sign( b ); - if ( aExp == 0xFF ) { - if ( aSig || ( ( bExp == 0xFF ) && bSig ) ) { - return propagateFloat32NaN( ctx, a, b ); - } - float_raise( ctx, float_flag_invalid ); - return float32_default_nan; - } - if ( bExp == 0xFF ) { - if ( bSig ) return propagateFloat32NaN( ctx, a, b ); - return a; - } - if ( bExp == 0 ) { - if ( bSig == 0 ) { - float_raise( ctx, float_flag_invalid ); - return float32_default_nan; - } - normalizeFloat32Subnormal( bSig, &bExp, &bSig ); - } - if ( aExp == 0 ) { - if ( aSig == 0 ) return a; - normalizeFloat32Subnormal( aSig, &aExp, &aSig ); - } - expDiff = aExp - bExp; - aSig |= 0x00800000; - bSig |= 0x00800000; - if ( expDiff < 32 ) { - aSig <<= 8; - bSig <<= 8; - if ( expDiff < 0 ) { - if ( expDiff < -1 ) return a; - aSig >>= 1; - } - q = ( bSig <= aSig ); - if ( q ) aSig -= bSig; - if ( 0 < expDiff ) { - q = ( ( (bits64) aSig )<<32 ) / bSig; - q >>= 32 - expDiff; - bSig >>= 2; - aSig = ( ( aSig>>1 )<<( expDiff - 1 ) ) - bSig * q; - } - else { - aSig >>= 2; - bSig >>= 2; - } - } - else { - if ( bSig <= aSig ) aSig -= bSig; - aSig64 = ( (bits64) aSig )<<40; - bSig64 = ( (bits64) bSig )<<40; - expDiff -= 64; - while ( 0 < expDiff ) { - q64 = estimateDiv128To64( aSig64, 0, bSig64 ); - q64 = ( 2 < q64 ) ? q64 - 2 : 0; - aSig64 = - ( ( bSig * q64 )<<38 ); - expDiff -= 62; - } - expDiff += 64; - q64 = estimateDiv128To64( aSig64, 0, bSig64 ); - q64 = ( 2 < q64 ) ? q64 - 2 : 0; - q = q64>>( 64 - expDiff ); - bSig <<= 6; - aSig = ( ( aSig64>>33 )<<( expDiff - 1 ) ) - bSig * q; - } - do { - alternateASig = aSig; - ++q; - aSig -= bSig; - } while ( 0 <= (sbits32) aSig ); - sigMean = aSig + alternateASig; - if ( ( sigMean < 0 ) || ( ( sigMean == 0 ) && ( q & 1 ) ) ) { - aSig = alternateASig; - } - zSign = ( (sbits32) aSig < 0 ); - if ( zSign ) aSig = - aSig; - return normalizeRoundAndPackFloat32( ctx, aSign ^ zSign, bExp, aSig ); - -} - -/*---------------------------------------------------------------------------- -| Returns the square root of the single-precision floating-point value `a'. -| The operation is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -float32 float32_sqrt( void* ctx, float32 a ) -{ - flag aSign; - int16 aExp, zExp; - bits32 aSig, zSig; - bits64 rem, term; - - aSig = extractFloat32Frac( a ); - aExp = extractFloat32Exp( a ); - aSign = extractFloat32Sign( a ); - if ( aExp == 0xFF ) { - if ( aSig ) return propagateFloat32NaN( ctx, a, 0 ); - if ( ! aSign ) return a; - float_raise( ctx, float_flag_invalid ); - return float32_default_nan; - } - if ( aSign ) { - if ( ( aExp | aSig ) == 0 ) return a; - float_raise( ctx, float_flag_invalid ); - return float32_default_nan; - } - if ( aExp == 0 ) { - if ( aSig == 0 ) return 0; - normalizeFloat32Subnormal( aSig, &aExp, &aSig ); - } - zExp = ( ( aExp - 0x7F )>>1 ) + 0x7E; - aSig = ( aSig | 0x00800000 )<<8; - zSig = estimateSqrt32( aExp, aSig ) + 2; - if ( ( zSig & 0x7F ) <= 5 ) { - if ( zSig < 2 ) { - zSig = 0x7FFFFFFF; - goto roundAndPack; - } - aSig >>= aExp & 1; - term = ( (bits64) zSig ) * zSig; - rem = ( ( (bits64) aSig )<<32 ) - term; - while ( (sbits64) rem < 0 ) { - --zSig; - rem += ( ( (bits64) zSig )<<1 ) | 1; - } - zSig |= ( rem != 0 ); - } - shift32RightJamming( zSig, 1, &zSig ); - roundAndPack: - return roundAndPackFloat32( ctx, 0, zExp, zSig ); - -} - -/*---------------------------------------------------------------------------- -| Returns 1 if the single-precision floating-point value `a' is equal to -| the corresponding value `b', and 0 otherwise. The comparison is performed -| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -flag float32_eq( void* ctx, float32 a, float32 b ) -{ - - if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) ) - || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) ) - ) { - if ( float32_is_signaling_nan( a ) || float32_is_signaling_nan( b ) ) { - float_raise( ctx, float_flag_invalid ); - } - return 0; - } - return ( a == b ) || ( (bits32) ( ( a | b )<<1 ) == 0 ); - -} - -/*---------------------------------------------------------------------------- -| Returns 1 if the single-precision floating-point value `a' is less than -| or equal to the corresponding value `b', and 0 otherwise. The comparison -| is performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic. -*----------------------------------------------------------------------------*/ - -flag float32_le( void* ctx, float32 a, float32 b ) -{ - flag aSign, bSign; - - if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) ) - || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) ) - ) { - float_raise( ctx, float_flag_invalid ); - return 0; - } - aSign = extractFloat32Sign( a ); - bSign = extractFloat32Sign( b ); - if ( aSign != bSign ) return aSign || ( (bits32) ( ( a | b )<<1 ) == 0 ); - return ( a == b ) || ( aSign ^ ( a < b ) ); - -} - -/*---------------------------------------------------------------------------- -| Returns 1 if the single-precision floating-point value `a' is less than -| the corresponding value `b', and 0 otherwise. The comparison is performed -| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -flag float32_lt( void* ctx, float32 a, float32 b ) -{ - flag aSign, bSign; - - if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) ) - || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) ) - ) { - float_raise( ctx, float_flag_invalid ); - return 0; - } - aSign = extractFloat32Sign( a ); - bSign = extractFloat32Sign( b ); - if ( aSign != bSign ) return aSign && ( (bits32) ( ( a | b )<<1 ) != 0 ); - return ( a != b ) && ( aSign ^ ( a < b ) ); - -} - -/*---------------------------------------------------------------------------- -| Returns 1 if the single-precision floating-point value `a' is equal to -| the corresponding value `b', and 0 otherwise. The invalid exception is -| raised if either operand is a NaN. Otherwise, the comparison is performed -| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -flag float32_eq_signaling( void* ctx, float32 a, float32 b ) -{ - - if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) ) - || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) ) - ) { - float_raise( ctx, float_flag_invalid ); - return 0; - } - return ( a == b ) || ( (bits32) ( ( a | b )<<1 ) == 0 ); - -} - -/*---------------------------------------------------------------------------- -| Returns 1 if the single-precision floating-point value `a' is less than or -| equal to the corresponding value `b', and 0 otherwise. Quiet NaNs do not -| cause an exception. Otherwise, the comparison is performed according to the -| IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -flag float32_le_quiet( void* ctx, float32 a, float32 b ) -{ - flag aSign, bSign; - - if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) ) - || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) ) - ) { - if ( float32_is_signaling_nan( a ) || float32_is_signaling_nan( b ) ) { - float_raise( ctx, float_flag_invalid ); - } - return 0; - } - aSign = extractFloat32Sign( a ); - bSign = extractFloat32Sign( b ); - if ( aSign != bSign ) return aSign || ( (bits32) ( ( a | b )<<1 ) == 0 ); - return ( a == b ) || ( aSign ^ ( a < b ) ); - -} - -/*---------------------------------------------------------------------------- -| Returns 1 if the single-precision floating-point value `a' is less than -| the corresponding value `b', and 0 otherwise. Quiet NaNs do not cause an -| exception. Otherwise, the comparison is performed according to the IEC/IEEE -| Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -flag float32_lt_quiet( void* ctx, float32 a, float32 b ) -{ - flag aSign, bSign; - - if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) ) - || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) ) - ) { - if ( float32_is_signaling_nan( a ) || float32_is_signaling_nan( b ) ) { - float_raise( ctx, float_flag_invalid ); - } - return 0; - } - aSign = extractFloat32Sign( a ); - bSign = extractFloat32Sign( b ); - if ( aSign != bSign ) return aSign && ( (bits32) ( ( a | b )<<1 ) != 0 ); - return ( a != b ) && ( aSign ^ ( a < b ) ); - -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the double-precision floating-point value -| `a' to the 32-bit two's complement integer format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic---which means in particular that the conversion is rounded -| according to the current rounding mode. If `a' is a NaN, the largest -| positive integer is returned. Otherwise, if the conversion overflows, the -| largest integer with the same sign as `a' is returned. -*----------------------------------------------------------------------------*/ - -int32 float64_to_int32( void* ctx, float64 a ) -{ - flag aSign; - int16 aExp, shiftCount; - bits64 aSig; - - aSig = extractFloat64Frac( a ); - aExp = extractFloat64Exp( a ); - aSign = extractFloat64Sign( a ); -// if ( ( aExp == 0x7FF ) && aSig ) aSign = 0; - if ( ( aExp == 0x7FF ) && aSig ) aSign = 1; /*@Z900*/ - if ( aExp ) aSig |= LIT64( 0x0010000000000000 ); - shiftCount = 0x42C - aExp; - if ( 0 < shiftCount ) shift64RightJamming( aSig, shiftCount, &aSig ); - return roundAndPackInt32( ctx, aSign, aSig ); - -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the double-precision floating-point value -| `a' to the 32-bit two's complement integer format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic, except that the conversion is always rounded toward zero. -| If `a' is a NaN, the largest positive integer is returned. Otherwise, if -| the conversion overflows, the largest integer with the same sign as `a' is -| returned. -*----------------------------------------------------------------------------*/ - -int32 float64_to_int32_round_to_zero( void* ctx, float64 a ) -{ - flag aSign; - int16 aExp, shiftCount; - bits64 aSig, savedASig; - int32 z; - - aSig = extractFloat64Frac( a ); - aExp = extractFloat64Exp( a ); - aSign = extractFloat64Sign( a ); - if ( 0x41E < aExp ) { -// if ( ( aExp == 0x7FF ) && aSig ) aSign = 0; - if ( ( aExp == 0x7FF ) && aSig ) aSign = 1; /*@Z900*/ - goto invalid; - } - else if ( aExp < 0x3FF ) { - if ( aExp || aSig ) set_exception_flags( ctx, float_flag_inexact ); - return 0; - } - aSig |= LIT64( 0x0010000000000000 ); - shiftCount = 0x433 - aExp; - savedASig = aSig; - aSig >>= shiftCount; - z = aSig; - if ( aSign ) z = - z; - if ( ( z < 0 ) ^ aSign ) { - invalid: - float_raise( ctx, float_flag_inexact ); /*@Z900*/ - float_raise( ctx, float_flag_invalid ); - return aSign ? (sbits32) 0x80000000 : 0x7FFFFFFF; - } - if ( ( aSig<>( - shiftCount ); - if ( (bits64) ( aSig<<( shiftCount & 63 ) ) ) { - set_exception_flags( ctx, float_flag_inexact ); - } - } - if ( aSign ) z = - z; - return z; - -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the double-precision floating-point value -| `a' to the single-precision floating-point format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic. -*----------------------------------------------------------------------------*/ - -float32 float64_to_float32( void* ctx, float64 a ) -{ - flag aSign; - int16 aExp; - bits64 aSig; - bits32 zSig; - - aSig = extractFloat64Frac( a ); - aExp = extractFloat64Exp( a ); - aSign = extractFloat64Sign( a ); - if ( aExp == 0x7FF ) { - if ( aSig ) return commonNaNToFloat32( float64ToCommonNaN( ctx, a ) ); - return packFloat32( aSign, 0xFF, 0 ); - } - shift64RightJamming( aSig, 22, &aSig ); - zSig = aSig; - if ( aExp || zSig ) { - zSig |= 0x40000000; - aExp -= 0x381; - } - return roundAndPackFloat32( ctx, aSign, aExp, zSig ); - -} - -#ifdef FLOAT128 - -/*---------------------------------------------------------------------------- -| Returns the result of converting the double-precision floating-point value -| `a' to the quadruple-precision floating-point format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic. -*----------------------------------------------------------------------------*/ - -float128 float64_to_float128( void* ctx, float64 a ) -{ - flag aSign; - int16 aExp; - bits64 aSig, zSig0, zSig1; - - aSig = extractFloat64Frac( a ); - aExp = extractFloat64Exp( a ); - aSign = extractFloat64Sign( a ); - if ( aExp == 0x7FF ) { - if ( aSig ) return commonNaNToFloat128( float64ToCommonNaN( ctx, a ) ); - return packFloat128( aSign, 0x7FFF, 0, 0 ); - } - if ( aExp == 0 ) { - if ( aSig == 0 ) return packFloat128( aSign, 0, 0, 0 ); - normalizeFloat64Subnormal( aSig, &aExp, &aSig ); - --aExp; - } - shift128Right( aSig, 0, 4, &zSig0, &zSig1 ); - return packFloat128( aSign, aExp + 0x3C00, zSig0, zSig1 ); - -} - -#endif - -/*---------------------------------------------------------------------------- -| Rounds the double-precision floating-point value `a' to an integer, and -| returns the result as a double-precision floating-point value. The -| operation is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -float64 float64_round_to_int( void* ctx, float64 a ) -{ - flag aSign; - int16 aExp; - bits64 lastBitMask, roundBitsMask; - int8 roundingMode; - float64 z; - - aExp = extractFloat64Exp( a ); - if ( 0x433 <= aExp ) { - if ( ( aExp == 0x7FF ) && extractFloat64Frac( a ) ) { - return propagateFloat64NaN( ctx, a, a ); - } - return a; - } - if ( aExp < 0x3FF ) { - if ( (bits64) ( a<<1 ) == 0 ) return a; - set_exception_flags( ctx, float_flag_inexact ); - aSign = extractFloat64Sign( a ); - switch ( get_float_rounding_mode( ctx ) ) { - case float_round_nearest_even: - if ( ( aExp == 0x3FE ) && extractFloat64Frac( a ) ) { - return packFloat64( aSign, 0x3FF, 0 ); - } - break; - case float_round_down: - return aSign ? LIT64( 0xBFF0000000000000 ) : 0; - case float_round_up: - return - aSign ? LIT64( 0x8000000000000000 ) : LIT64( 0x3FF0000000000000 ); - } - return packFloat64( aSign, 0, 0 ); - } - lastBitMask = 1; - lastBitMask <<= 0x433 - aExp; - roundBitsMask = lastBitMask - 1; - z = a; - roundingMode = get_float_rounding_mode( ctx ); - if ( roundingMode == float_round_nearest_even ) { - z += lastBitMask>>1; - if ( ( z & roundBitsMask ) == 0 ) z &= ~ lastBitMask; - } - else if ( roundingMode != float_round_to_zero ) { - if ( extractFloat64Sign( z ) ^ ( roundingMode == float_round_up ) ) { - z += roundBitsMask; - } - } - z &= ~ roundBitsMask; - if ( z != a ) set_exception_flags( ctx, float_flag_inexact ); - return z; - -} - -/*---------------------------------------------------------------------------- -| Returns the result of adding the absolute values of the double-precision -| floating-point values `a' and `b'. If `zSign' is 1, the sum is negated -| before being returned. `zSign' is ignored if the result is a NaN. -| The addition is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -static float64 addFloat64Sigs( void* ctx, float64 a, float64 b, flag zSign ) -{ - int16 aExp, bExp, zExp; - bits64 aSig, bSig, zSig; - int16 expDiff; - - aSig = extractFloat64Frac( a ); - aExp = extractFloat64Exp( a ); - bSig = extractFloat64Frac( b ); - bExp = extractFloat64Exp( b ); - expDiff = aExp - bExp; - aSig <<= 9; - bSig <<= 9; - if ( 0 < expDiff ) { - if ( aExp == 0x7FF ) { - if ( aSig ) return propagateFloat64NaN( ctx, a, b ); - return a; - } - if ( bExp == 0 ) { - --expDiff; - } - else { - bSig |= LIT64( 0x2000000000000000 ); - } - shift64RightJamming( bSig, expDiff, &bSig ); - zExp = aExp; - } - else if ( expDiff < 0 ) { - if ( bExp == 0x7FF ) { - if ( bSig ) return propagateFloat64NaN( ctx, a, b ); - return packFloat64( zSign, 0x7FF, 0 ); - } - if ( aExp == 0 ) { - ++expDiff; - } - else { - aSig |= LIT64( 0x2000000000000000 ); - } - shift64RightJamming( aSig, - expDiff, &aSig ); - zExp = bExp; - } - else { - if ( aExp == 0x7FF ) { - if ( aSig | bSig ) return propagateFloat64NaN( ctx, a, b ); - return a; - } - if ( aExp == 0 ) return packFloat64( zSign, 0, ( aSig + bSig )>>9 ); - zSig = LIT64( 0x4000000000000000 ) + aSig + bSig; - zExp = aExp; - goto roundAndPack; - } - aSig |= LIT64( 0x2000000000000000 ); - zSig = ( aSig + bSig )<<1; - --zExp; - if ( (sbits64) zSig < 0 ) { - zSig = aSig + bSig; - ++zExp; - } - roundAndPack: - return roundAndPackFloat64( ctx, zSign, zExp, zSig ); - -} - -/*---------------------------------------------------------------------------- -| Returns the result of subtracting the absolute values of the double- -| precision floating-point values `a' and `b'. If `zSign' is 1, the -| difference is negated before being returned. `zSign' is ignored if the -| result is a NaN. The subtraction is performed according to the IEC/IEEE -| Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -static float64 subFloat64Sigs( void* ctx, float64 a, float64 b, flag zSign ) -{ - int16 aExp, bExp, zExp; - bits64 aSig, bSig, zSig; - int16 expDiff; - - aSig = extractFloat64Frac( a ); - aExp = extractFloat64Exp( a ); - bSig = extractFloat64Frac( b ); - bExp = extractFloat64Exp( b ); - expDiff = aExp - bExp; - aSig <<= 10; - bSig <<= 10; - if ( 0 < expDiff ) goto aExpBigger; - if ( expDiff < 0 ) goto bExpBigger; - if ( aExp == 0x7FF ) { - if ( aSig | bSig ) return propagateFloat64NaN( ctx, a, b ); - float_raise( ctx, float_flag_invalid ); - return float64_default_nan; - } - if ( aExp == 0 ) { - aExp = 1; - bExp = 1; - } - if ( bSig < aSig ) goto aBigger; - if ( aSig < bSig ) goto bBigger; - return packFloat64( get_float_rounding_mode( ctx ) == float_round_down, 0, 0 ); - bExpBigger: - if ( bExp == 0x7FF ) { - if ( bSig ) return propagateFloat64NaN( ctx, a, b ); - return packFloat64( zSign ^ 1, 0x7FF, 0 ); - } - if ( aExp == 0 ) { - ++expDiff; - } - else { - aSig |= LIT64( 0x4000000000000000 ); - } - shift64RightJamming( aSig, - expDiff, &aSig ); - bSig |= LIT64( 0x4000000000000000 ); - bBigger: - zSig = bSig - aSig; - zExp = bExp; - zSign ^= 1; - goto normalizeRoundAndPack; - aExpBigger: - if ( aExp == 0x7FF ) { - if ( aSig ) return propagateFloat64NaN( ctx, a, b ); - return a; - } - if ( bExp == 0 ) { - --expDiff; - } - else { - bSig |= LIT64( 0x4000000000000000 ); - } - shift64RightJamming( bSig, expDiff, &bSig ); - aSig |= LIT64( 0x4000000000000000 ); - aBigger: - zSig = aSig - bSig; - zExp = aExp; - normalizeRoundAndPack: - --zExp; - return normalizeRoundAndPackFloat64( ctx, zSign, zExp, zSig ); - -} - -/*---------------------------------------------------------------------------- -| Returns the result of adding the double-precision floating-point values `a' -| and `b'. The operation is performed according to the IEC/IEEE Standard for -| Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -float64 float64_add( void* ctx, float64 a, float64 b ) -{ - flag aSign, bSign; - - aSign = extractFloat64Sign( a ); - bSign = extractFloat64Sign( b ); - if ( aSign == bSign ) { - return addFloat64Sigs( ctx, a, b, aSign ); - } - else { - return subFloat64Sigs( ctx, a, b, aSign ); - } - -} - -/*---------------------------------------------------------------------------- -| Returns the result of subtracting the double-precision floating-point values -| `a' and `b'. The operation is performed according to the IEC/IEEE Standard -| for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -float64 float64_sub( void* ctx, float64 a, float64 b ) -{ - flag aSign, bSign; - - aSign = extractFloat64Sign( a ); - bSign = extractFloat64Sign( b ); - if ( aSign == bSign ) { - return subFloat64Sigs( ctx, a, b, aSign ); - } - else { - return addFloat64Sigs( ctx, a, b, aSign ); - } - -} - -/*---------------------------------------------------------------------------- -| Returns the result of multiplying the double-precision floating-point values -| `a' and `b'. The operation is performed according to the IEC/IEEE Standard -| for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -float64 float64_mul( void* ctx, float64 a, float64 b ) -{ - flag aSign, bSign, zSign; - int16 aExp, bExp, zExp; - bits64 aSig, bSig, zSig0, zSig1; - - aSig = extractFloat64Frac( a ); - aExp = extractFloat64Exp( a ); - aSign = extractFloat64Sign( a ); - bSig = extractFloat64Frac( b ); - bExp = extractFloat64Exp( b ); - bSign = extractFloat64Sign( b ); - zSign = aSign ^ bSign; - if ( aExp == 0x7FF ) { - if ( aSig || ( ( bExp == 0x7FF ) && bSig ) ) { - return propagateFloat64NaN( ctx, a, b ); - } - if ( ( bExp | bSig ) == 0 ) { - float_raise( ctx, float_flag_invalid ); - return float64_default_nan; - } - return packFloat64( zSign, 0x7FF, 0 ); - } - if ( bExp == 0x7FF ) { - if ( bSig ) return propagateFloat64NaN( ctx, a, b ); - if ( ( aExp | aSig ) == 0 ) { - float_raise( ctx, float_flag_invalid ); - return float64_default_nan; - } - return packFloat64( zSign, 0x7FF, 0 ); - } - if ( aExp == 0 ) { - if ( aSig == 0 ) return packFloat64( zSign, 0, 0 ); - normalizeFloat64Subnormal( aSig, &aExp, &aSig ); - } - if ( bExp == 0 ) { - if ( bSig == 0 ) return packFloat64( zSign, 0, 0 ); - normalizeFloat64Subnormal( bSig, &bExp, &bSig ); - } - zExp = aExp + bExp - 0x3FF; - aSig = ( aSig | LIT64( 0x0010000000000000 ) )<<10; - bSig = ( bSig | LIT64( 0x0010000000000000 ) )<<11; - mul64To128( aSig, bSig, &zSig0, &zSig1 ); - zSig0 |= ( zSig1 != 0 ); - if ( 0 <= (sbits64) ( zSig0<<1 ) ) { - zSig0 <<= 1; - --zExp; - } - return roundAndPackFloat64( ctx, zSign, zExp, zSig0 ); - -} - -/*---------------------------------------------------------------------------- -| Returns the result of dividing the double-precision floating-point value `a' -| by the corresponding value `b'. The operation is performed according to -| the IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -float64 float64_div( void* ctx, float64 a, float64 b ) -{ - flag aSign, bSign, zSign; - int16 aExp, bExp, zExp; - bits64 aSig, bSig, zSig; - bits64 rem0, rem1; - bits64 term0, term1; - -#if 0 - dumpStorageReversed(&a, sizeof(a), "float a"); - dumpStorageReversed(&b, sizeof(b), "float b"); -#endif - aSig = extractFloat64Frac( a ); - aExp = extractFloat64Exp( a ); - aSign = extractFloat64Sign( a ); - bSig = extractFloat64Frac( b ); - bExp = extractFloat64Exp( b ); - bSign = extractFloat64Sign( b ); - zSign = aSign ^ bSign; - if ( aExp == 0x7FF ) { - if ( aSig ) return propagateFloat64NaN( ctx, a, b ); - if ( bExp == 0x7FF ) { - if ( bSig ) return propagateFloat64NaN( ctx, a, b ); - float_raise( ctx, float_flag_invalid ); - return float64_default_nan; - } - return packFloat64( zSign, 0x7FF, 0 ); - } - if ( bExp == 0x7FF ) { - if ( bSig ) return propagateFloat64NaN( ctx, a, b ); - return packFloat64( zSign, 0, 0 ); - } - if ( bExp == 0 ) { - if ( bSig == 0 ) { - if ( ( aExp | aSig ) == 0 ) { - float_raise( ctx, float_flag_invalid ); - return float64_default_nan; - } - float_raise( ctx, float_flag_divbyzero ); - return packFloat64( zSign, 0x7FF, 0 ); - } - normalizeFloat64Subnormal( bSig, &bExp, &bSig ); - } - if ( aExp == 0 ) { - if ( aSig == 0 ) return packFloat64( zSign, 0, 0 ); - normalizeFloat64Subnormal( aSig, &aExp, &aSig ); - } - zExp = aExp - bExp + 0x3FD; - aSig = ( aSig | LIT64( 0x0010000000000000 ) )<<10; - bSig = ( bSig | LIT64( 0x0010000000000000 ) )<<11; - if ( bSig <= ( aSig + aSig ) ) { - aSig >>= 1; - ++zExp; - } - zSig = estimateDiv128To64( aSig, 0, bSig ); - if ( ( zSig & 0x1FF ) <= 2 ) { - mul64To128( bSig, zSig, &term0, &term1 ); - sub128( aSig, 0, term0, term1, &rem0, &rem1 ); - while ( (sbits64) rem0 < 0 ) { - --zSig; - add128( rem0, rem1, 0, bSig, &rem0, &rem1 ); - } - zSig |= ( rem1 != 0 ); - } - return roundAndPackFloat64( ctx, zSign, zExp, zSig ); - -} - -/*---------------------------------------------------------------------------- -| Returns the remainder of the double-precision floating-point value `a' -| with respect to the corresponding value `b'. The operation is performed -| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -float64 float64_rem( void* ctx, float64 a, float64 b ) -{ - flag aSign, bSign, zSign; - int16 aExp, bExp, expDiff; - bits64 aSig, bSig; - bits64 q, alternateASig; - sbits64 sigMean; - - aSig = extractFloat64Frac( a ); - aExp = extractFloat64Exp( a ); - aSign = extractFloat64Sign( a ); - bSig = extractFloat64Frac( b ); - bExp = extractFloat64Exp( b ); - bSign = extractFloat64Sign( b ); - if ( aExp == 0x7FF ) { - if ( aSig || ( ( bExp == 0x7FF ) && bSig ) ) { - return propagateFloat64NaN( ctx, a, b ); - } - float_raise( ctx, float_flag_invalid ); - return float64_default_nan; - } - if ( bExp == 0x7FF ) { - if ( bSig ) return propagateFloat64NaN( ctx, a, b ); - return a; - } - if ( bExp == 0 ) { - if ( bSig == 0 ) { - float_raise( ctx, float_flag_invalid ); - return float64_default_nan; - } - normalizeFloat64Subnormal( bSig, &bExp, &bSig ); - } - if ( aExp == 0 ) { - if ( aSig == 0 ) return a; - normalizeFloat64Subnormal( aSig, &aExp, &aSig ); - } - expDiff = aExp - bExp; - aSig = ( aSig | LIT64( 0x0010000000000000 ) )<<11; - bSig = ( bSig | LIT64( 0x0010000000000000 ) )<<11; - if ( expDiff < 0 ) { - if ( expDiff < -1 ) return a; - aSig >>= 1; - } - q = ( bSig <= aSig ); - if ( q ) aSig -= bSig; - expDiff -= 64; - while ( 0 < expDiff ) { - q = estimateDiv128To64( aSig, 0, bSig ); - q = ( 2 < q ) ? q - 2 : 0; - aSig = - ( ( bSig>>2 ) * q ); - expDiff -= 62; - } - expDiff += 64; - if ( 0 < expDiff ) { - q = estimateDiv128To64( aSig, 0, bSig ); - q = ( 2 < q ) ? q - 2 : 0; - q >>= 64 - expDiff; - bSig >>= 2; - aSig = ( ( aSig>>1 )<<( expDiff - 1 ) ) - bSig * q; - } - else { - aSig >>= 2; - bSig >>= 2; - } - do { - alternateASig = aSig; - ++q; - aSig -= bSig; - } while ( 0 <= (sbits64) aSig ); - sigMean = aSig + alternateASig; - if ( ( sigMean < 0 ) || ( ( sigMean == 0 ) && ( q & 1 ) ) ) { - aSig = alternateASig; - } - zSign = ( (sbits64) aSig < 0 ); - if ( zSign ) aSig = - aSig; - return normalizeRoundAndPackFloat64( ctx, aSign ^ zSign, bExp, aSig ); - -} - -/*---------------------------------------------------------------------------- -| Returns the square root of the double-precision floating-point value `a'. -| The operation is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -float64 float64_sqrt( void* ctx, float64 a ) -{ - flag aSign; - int16 aExp, zExp; - bits64 aSig, zSig, doubleZSig; - bits64 rem0, rem1, term0, term1; - - aSig = extractFloat64Frac( a ); - aExp = extractFloat64Exp( a ); - aSign = extractFloat64Sign( a ); - if ( aExp == 0x7FF ) { - if ( aSig ) return propagateFloat64NaN( ctx, a, a ); - if ( ! aSign ) return a; - float_raise( ctx, float_flag_invalid ); - return float64_default_nan; - } - if ( aSign ) { - if ( ( aExp | aSig ) == 0 ) return a; - float_raise( ctx, float_flag_invalid ); - return float64_default_nan; - } - if ( aExp == 0 ) { - if ( aSig == 0 ) return 0; - normalizeFloat64Subnormal( aSig, &aExp, &aSig ); - } - zExp = ( ( aExp - 0x3FF )>>1 ) + 0x3FE; - aSig |= LIT64( 0x0010000000000000 ); - zSig = estimateSqrt32( aExp, aSig>>21 ); - aSig <<= 9 - ( aExp & 1 ); - zSig = estimateDiv128To64( aSig, 0, zSig<<32 ) + ( zSig<<30 ); - if ( ( zSig & 0x1FF ) <= 5 ) { - doubleZSig = zSig<<1; - mul64To128( zSig, zSig, &term0, &term1 ); - sub128( aSig, 0, term0, term1, &rem0, &rem1 ); - while ( (sbits64) rem0 < 0 ) { - --zSig; - doubleZSig -= 2; - add128( rem0, rem1, zSig>>63, doubleZSig | 1, &rem0, &rem1 ); - } - zSig |= ( ( rem0 | rem1 ) != 0 ); - } - return roundAndPackFloat64( ctx, 0, zExp, zSig ); - -} - -/*---------------------------------------------------------------------------- -| Returns 1 if the double-precision floating-point value `a' is equal to the -| corresponding value `b', and 0 otherwise. The comparison is performed -| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -flag float64_eq( void* ctx, float64 a, float64 b ) -{ - - if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) ) - || ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) ) - ) { - if ( float64_is_signaling_nan( a ) || float64_is_signaling_nan( b ) ) { - float_raise( ctx, float_flag_invalid ); - } - return 0; - } - return ( a == b ) || ( (bits64) ( ( a | b )<<1 ) == 0 ); - -} - -/*---------------------------------------------------------------------------- -| Returns 1 if the double-precision floating-point value `a' is less than or -| equal to the corresponding value `b', and 0 otherwise. The comparison is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic. -*----------------------------------------------------------------------------*/ - -flag float64_le( void* ctx, float64 a, float64 b ) -{ - flag aSign, bSign; - - if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) ) - || ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) ) - ) { - float_raise( ctx, float_flag_invalid ); - return 0; - } - aSign = extractFloat64Sign( a ); - bSign = extractFloat64Sign( b ); - if ( aSign != bSign ) return aSign || ( (bits64) ( ( a | b )<<1 ) == 0 ); - return ( a == b ) || ( aSign ^ ( a < b ) ); - -} - -/*---------------------------------------------------------------------------- -| Returns 1 if the double-precision floating-point value `a' is less than -| the corresponding value `b', and 0 otherwise. The comparison is performed -| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -flag float64_lt( void* ctx, float64 a, float64 b ) -{ - flag aSign, bSign; - - if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) ) - || ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) ) - ) { - float_raise( ctx, float_flag_invalid ); - return 0; - } - aSign = extractFloat64Sign( a ); - bSign = extractFloat64Sign( b ); - if ( aSign != bSign ) return aSign && ( (bits64) ( ( a | b )<<1 ) != 0 ); - return ( a != b ) && ( aSign ^ ( a < b ) ); - -} - -/*---------------------------------------------------------------------------- -| Returns 1 if the double-precision floating-point value `a' is equal to the -| corresponding value `b', and 0 otherwise. The invalid exception is raised -| if either operand is a NaN. Otherwise, the comparison is performed -| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -flag float64_eq_signaling( void* ctx, float64 a, float64 b ) -{ - - if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) ) - || ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) ) - ) { - float_raise( ctx, float_flag_invalid ); - return 0; - } - return ( a == b ) || ( (bits64) ( ( a | b )<<1 ) == 0 ); - -} - -/*---------------------------------------------------------------------------- -| Returns 1 if the double-precision floating-point value `a' is less than or -| equal to the corresponding value `b', and 0 otherwise. Quiet NaNs do not -| cause an exception. Otherwise, the comparison is performed according to the -| IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -flag float64_le_quiet( void* ctx, float64 a, float64 b ) -{ - flag aSign, bSign; - - if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) ) - || ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) ) - ) { - if ( float64_is_signaling_nan( a ) || float64_is_signaling_nan( b ) ) { - float_raise( ctx, float_flag_invalid ); - } - return 0; - } - aSign = extractFloat64Sign( a ); - bSign = extractFloat64Sign( b ); - if ( aSign != bSign ) return aSign || ( (bits64) ( ( a | b )<<1 ) == 0 ); - return ( a == b ) || ( aSign ^ ( a < b ) ); - -} - -/*---------------------------------------------------------------------------- -| Returns 1 if the double-precision floating-point value `a' is less than -| the corresponding value `b', and 0 otherwise. Quiet NaNs do not cause an -| exception. Otherwise, the comparison is performed according to the IEC/IEEE -| Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -flag float64_lt_quiet( void* ctx, float64 a, float64 b ) -{ - flag aSign, bSign; - - if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) ) - || ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) ) - ) { - if ( float64_is_signaling_nan( a ) || float64_is_signaling_nan( b ) ) { - float_raise( ctx, float_flag_invalid ); - } - return 0; - } - aSign = extractFloat64Sign( a ); - bSign = extractFloat64Sign( b ); - if ( aSign != bSign ) return aSign && ( (bits64) ( ( a | b )<<1 ) != 0 ); - return ( a != b ) && ( aSign ^ ( a < b ) ); - -} - -#ifdef FLOAT128 - -/*---------------------------------------------------------------------------- -| Returns the result of converting the quadruple-precision floating-point -| value `a' to the 32-bit two's complement integer format. The conversion -| is performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic---which means in particular that the conversion is rounded -| according to the current rounding mode. If `a' is a NaN, the largest -| positive integer is returned. Otherwise, if the conversion overflows, the -| largest integer with the same sign as `a' is returned. -*----------------------------------------------------------------------------*/ - -int32 float128_to_int32( void* ctx, float128 a ) -{ - flag aSign; - int32 aExp, shiftCount; - bits64 aSig0, aSig1; - - aSig1 = extractFloat128Frac1( a ); - aSig0 = extractFloat128Frac0( a ); - aExp = extractFloat128Exp( a ); - aSign = extractFloat128Sign( a ); -// if ( ( aExp == 0x7FFF ) && ( aSig0 | aSig1 ) ) aSign = 0; - if ( ( aExp == 0x7FFF ) && ( aSig0 | aSig1 ) ) aSign = 1; /*@Z900*/ - if ( aExp ) aSig0 |= LIT64( 0x0001000000000000 ); - aSig0 |= ( aSig1 != 0 ); - shiftCount = 0x4028 - aExp; - if ( 0 < shiftCount ) shift64RightJamming( aSig0, shiftCount, &aSig0 ); - return roundAndPackInt32( ctx, aSign, aSig0 ); - -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the quadruple-precision floating-point -| value `a' to the 32-bit two's complement integer format. The conversion -| is performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic, except that the conversion is always rounded toward zero. If -| `a' is a NaN, the largest positive integer is returned. Otherwise, if the -| conversion overflows, the largest integer with the same sign as `a' is -| returned. -*----------------------------------------------------------------------------*/ - -int32 float128_to_int32_round_to_zero( void* ctx, float128 a ) -{ - flag aSign; - int32 aExp, shiftCount; - bits64 aSig0, aSig1, savedASig; - int32 z; - - aSig1 = extractFloat128Frac1( a ); - aSig0 = extractFloat128Frac0( a ); - aExp = extractFloat128Exp( a ); - aSign = extractFloat128Sign( a ); - aSig0 |= ( aSig1 != 0 ); - if ( 0x401E < aExp ) { -// if ( ( aExp == 0x7FFF ) && aSig0 ) aSign = 0; - if ( ( aExp == 0x7FFF ) && aSig0 ) aSign = 1; /*@Z900*/ - goto invalid; - } - else if ( aExp < 0x3FFF ) { - if ( aExp || aSig0 ) set_exception_flags( ctx, float_flag_inexact ); - return 0; - } - aSig0 |= LIT64( 0x0001000000000000 ); - shiftCount = 0x402F - aExp; - savedASig = aSig0; - aSig0 >>= shiftCount; - z = aSig0; - if ( aSign ) z = - z; - if ( ( z < 0 ) ^ aSign ) { - invalid: - float_raise( ctx, float_flag_inexact ); /*@Z900*/ - float_raise( ctx, float_flag_invalid ); - return aSign ? (sbits32) 0x80000000 : 0x7FFFFFFF; - } - if ( ( aSig0<>( ( - shiftCount ) & 63 ) ); - if ( (bits64) ( aSig1<>( - shiftCount ); - if ( aSig1 - || ( shiftCount && (bits64) ( aSig0<<( shiftCount & 63 ) ) ) ) { - set_exception_flags( ctx, float_flag_inexact ); - } - } - if ( aSign ) z = - z; - return z; - -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the quadruple-precision floating-point -| value `a' to the single-precision floating-point format. The conversion -| is performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic. -*----------------------------------------------------------------------------*/ - -float32 float128_to_float32( void* ctx, float128 a ) -{ - flag aSign; - int32 aExp; - bits64 aSig0, aSig1; - bits32 zSig; - - aSig1 = extractFloat128Frac1( a ); - aSig0 = extractFloat128Frac0( a ); - aExp = extractFloat128Exp( a ); - aSign = extractFloat128Sign( a ); - if ( aExp == 0x7FFF ) { - if ( aSig0 | aSig1 ) { - return commonNaNToFloat32( float128ToCommonNaN( ctx, a ) ); - } - return packFloat32( aSign, 0xFF, 0 ); - } - aSig0 |= ( aSig1 != 0 ); - shift64RightJamming( aSig0, 18, &aSig0 ); - zSig = aSig0; - if ( aExp || zSig ) { - zSig |= 0x40000000; - aExp -= 0x3F81; - } - return roundAndPackFloat32( ctx, aSign, aExp, zSig ); - -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the quadruple-precision floating-point -| value `a' to the double-precision floating-point format. The conversion -| is performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic. -*----------------------------------------------------------------------------*/ - -float64 float128_to_float64( void* ctx, float128 a ) -{ - flag aSign; - int32 aExp; - bits64 aSig0, aSig1; - - aSig1 = extractFloat128Frac1( a ); - aSig0 = extractFloat128Frac0( a ); - aExp = extractFloat128Exp( a ); - aSign = extractFloat128Sign( a ); - if ( aExp == 0x7FFF ) { - if ( aSig0 | aSig1 ) { - return commonNaNToFloat64( float128ToCommonNaN( ctx, a ) ); - } - return packFloat64( aSign, 0x7FF, 0 ); - } - shortShift128Left( aSig0, aSig1, 14, &aSig0, &aSig1 ); - aSig0 |= ( aSig1 != 0 ); - if ( aExp || aSig0 ) { - aSig0 |= LIT64( 0x4000000000000000 ); - aExp -= 0x3C01; - } - return roundAndPackFloat64( ctx, aSign, aExp, aSig0 ); - -} - -/*---------------------------------------------------------------------------- -| Rounds the quadruple-precision floating-point value `a' to an integer, and -| returns the result as a quadruple-precision floating-point value. The -| operation is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -float128 float128_round_to_int( void* ctx, float128 a ) -{ - flag aSign; - int32 aExp; - bits64 lastBitMask, roundBitsMask; - int8 roundingMode; - float128 z; - - aExp = extractFloat128Exp( a ); - if ( 0x402F <= aExp ) { - if ( 0x406F <= aExp ) { - if ( ( aExp == 0x7FFF ) - && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) ) - ) { - return propagateFloat128NaN( ctx, a, a ); - } - return a; - } - lastBitMask = 1; - lastBitMask = ( lastBitMask<<( 0x406E - aExp ) )<<1; - roundBitsMask = lastBitMask - 1; - z = a; - roundingMode = get_float_rounding_mode( ctx ); - if ( roundingMode == float_round_nearest_even ) { - if ( lastBitMask ) { - add128( z.high, z.low, 0, lastBitMask>>1, &z.high, &z.low ); - if ( ( z.low & roundBitsMask ) == 0 ) z.low &= ~ lastBitMask; - } - else { - if ( (sbits64) z.low < 0 ) { - ++z.high; - if ( (bits64) ( z.low<<1 ) == 0 ) z.high &= ~1; - } - } - } - else if ( roundingMode != float_round_to_zero ) { - if ( extractFloat128Sign( z ) - ^ ( roundingMode == float_round_up ) ) { - add128( z.high, z.low, 0, roundBitsMask, &z.high, &z.low ); - } - } - z.low &= ~ roundBitsMask; - } - else { - if ( aExp < 0x3FFF ) { - if ( ( ( (bits64) ( a.high<<1 ) ) | a.low ) == 0 ) return a; - set_exception_flags( ctx, float_flag_inexact ); - aSign = extractFloat128Sign( a ); - switch ( get_float_rounding_mode( ctx ) ) { - case float_round_nearest_even: - if ( ( aExp == 0x3FFE ) - && ( extractFloat128Frac0( a ) - | extractFloat128Frac1( a ) ) - ) { - return packFloat128( aSign, 0x3FFF, 0, 0 ); - } - break; - case float_round_down: - return - aSign ? packFloat128( 1, 0x3FFF, 0, 0 ) - : packFloat128( 0, 0, 0, 0 ); - case float_round_up: - return - aSign ? packFloat128( 1, 0, 0, 0 ) - : packFloat128( 0, 0x3FFF, 0, 0 ); - } - return packFloat128( aSign, 0, 0, 0 ); - } - lastBitMask = 1; - lastBitMask <<= 0x402F - aExp; - roundBitsMask = lastBitMask - 1; - z.low = 0; - z.high = a.high; - roundingMode = get_float_rounding_mode( ctx ); - if ( roundingMode == float_round_nearest_even ) { - z.high += lastBitMask>>1; - if ( ( ( z.high & roundBitsMask ) | a.low ) == 0 ) { - z.high &= ~ lastBitMask; - } - } - else if ( roundingMode != float_round_to_zero ) { - if ( extractFloat128Sign( z ) - ^ ( roundingMode == float_round_up ) ) { - z.high |= ( a.low != 0 ); - z.high += roundBitsMask; - } - } - z.high &= ~ roundBitsMask; - } - if ( ( z.low != a.low ) || ( z.high != a.high ) ) { - set_exception_flags( ctx, float_flag_inexact ); - } - return z; - -} - -/*---------------------------------------------------------------------------- -| Returns the result of adding the absolute values of the quadruple-precision -| floating-point values `a' and `b'. If `zSign' is 1, the sum is negated -| before being returned. `zSign' is ignored if the result is a NaN. -| The addition is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -static float128 addFloat128Sigs( void* ctx, float128 a, float128 b, flag zSign ) -{ - int32 aExp, bExp, zExp; - bits64 aSig0, aSig1, bSig0, bSig1, zSig0, zSig1, zSig2; - int32 expDiff; - - aSig1 = extractFloat128Frac1( a ); - aSig0 = extractFloat128Frac0( a ); - aExp = extractFloat128Exp( a ); - bSig1 = extractFloat128Frac1( b ); - bSig0 = extractFloat128Frac0( b ); - bExp = extractFloat128Exp( b ); - expDiff = aExp - bExp; - if ( 0 < expDiff ) { - if ( aExp == 0x7FFF ) { - if ( aSig0 | aSig1 ) return propagateFloat128NaN( ctx, a, b ); - return a; - } - if ( bExp == 0 ) { - --expDiff; - } - else { - bSig0 |= LIT64( 0x0001000000000000 ); - } - shift128ExtraRightJamming( - bSig0, bSig1, 0, expDiff, &bSig0, &bSig1, &zSig2 ); - zExp = aExp; - } - else if ( expDiff < 0 ) { - if ( bExp == 0x7FFF ) { - if ( bSig0 | bSig1 ) return propagateFloat128NaN( ctx, a, b ); - return packFloat128( zSign, 0x7FFF, 0, 0 ); - } - if ( aExp == 0 ) { - ++expDiff; - } - else { - aSig0 |= LIT64( 0x0001000000000000 ); - } - shift128ExtraRightJamming( - aSig0, aSig1, 0, - expDiff, &aSig0, &aSig1, &zSig2 ); - zExp = bExp; - } - else { - if ( aExp == 0x7FFF ) { - if ( aSig0 | aSig1 | bSig0 | bSig1 ) { - return propagateFloat128NaN( ctx, a, b ); - } - return a; - } - add128( aSig0, aSig1, bSig0, bSig1, &zSig0, &zSig1 ); - if ( aExp == 0 ) return packFloat128( zSign, 0, zSig0, zSig1 ); - zSig2 = 0; - zSig0 |= LIT64( 0x0002000000000000 ); - zExp = aExp; - goto shiftRight1; - } - aSig0 |= LIT64( 0x0001000000000000 ); - add128( aSig0, aSig1, bSig0, bSig1, &zSig0, &zSig1 ); - --zExp; - if ( zSig0 < LIT64( 0x0002000000000000 ) ) goto roundAndPack; - ++zExp; - shiftRight1: - shift128ExtraRightJamming( - zSig0, zSig1, zSig2, 1, &zSig0, &zSig1, &zSig2 ); - roundAndPack: - return roundAndPackFloat128( ctx, zSign, zExp, zSig0, zSig1, zSig2 ); - -} - -/*---------------------------------------------------------------------------- -| Returns the result of subtracting the absolute values of the quadruple- -| precision floating-point values `a' and `b'. If `zSign' is 1, the -| difference is negated before being returned. `zSign' is ignored if the -| result is a NaN. The subtraction is performed according to the IEC/IEEE -| Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -static float128 subFloat128Sigs( void* ctx, float128 a, float128 b, flag zSign ) -{ - int32 aExp, bExp, zExp; - bits64 aSig0, aSig1, bSig0, bSig1, zSig0, zSig1; - int32 expDiff; - float128 z; - - aSig1 = extractFloat128Frac1( a ); - aSig0 = extractFloat128Frac0( a ); - aExp = extractFloat128Exp( a ); - bSig1 = extractFloat128Frac1( b ); - bSig0 = extractFloat128Frac0( b ); - bExp = extractFloat128Exp( b ); - expDiff = aExp - bExp; - shortShift128Left( aSig0, aSig1, 14, &aSig0, &aSig1 ); - shortShift128Left( bSig0, bSig1, 14, &bSig0, &bSig1 ); - if ( 0 < expDiff ) goto aExpBigger; - if ( expDiff < 0 ) goto bExpBigger; - if ( aExp == 0x7FFF ) { - if ( aSig0 | aSig1 | bSig0 | bSig1 ) { - return propagateFloat128NaN( ctx, a, b ); - } - float_raise( ctx, float_flag_invalid ); - z.low = float128_default_nan_low; - z.high = float128_default_nan_high; - return z; - } - if ( aExp == 0 ) { - aExp = 1; - bExp = 1; - } - if ( bSig0 < aSig0 ) goto aBigger; - if ( aSig0 < bSig0 ) goto bBigger; - if ( bSig1 < aSig1 ) goto aBigger; - if ( aSig1 < bSig1 ) goto bBigger; - return packFloat128( get_float_rounding_mode( ctx ) == float_round_down, 0, 0, 0 ); - bExpBigger: - if ( bExp == 0x7FFF ) { - if ( bSig0 | bSig1 ) return propagateFloat128NaN( ctx, a, b ); - return packFloat128( zSign ^ 1, 0x7FFF, 0, 0 ); - } - if ( aExp == 0 ) { - ++expDiff; - } - else { - aSig0 |= LIT64( 0x4000000000000000 ); - } - shift128RightJamming( aSig0, aSig1, - expDiff, &aSig0, &aSig1 ); - bSig0 |= LIT64( 0x4000000000000000 ); - bBigger: - sub128( bSig0, bSig1, aSig0, aSig1, &zSig0, &zSig1 ); - zExp = bExp; - zSign ^= 1; - goto normalizeRoundAndPack; - aExpBigger: - if ( aExp == 0x7FFF ) { - if ( aSig0 | aSig1 ) return propagateFloat128NaN( ctx, a, b ); - return a; - } - if ( bExp == 0 ) { - --expDiff; - } - else { - bSig0 |= LIT64( 0x4000000000000000 ); - } - shift128RightJamming( bSig0, bSig1, expDiff, &bSig0, &bSig1 ); - aSig0 |= LIT64( 0x4000000000000000 ); - aBigger: - sub128( aSig0, aSig1, bSig0, bSig1, &zSig0, &zSig1 ); - zExp = aExp; - normalizeRoundAndPack: - --zExp; - return normalizeRoundAndPackFloat128( ctx, zSign, zExp - 14, zSig0, zSig1 ); - -} - -/*---------------------------------------------------------------------------- -| Returns the result of adding the quadruple-precision floating-point values -| `a' and `b'. The operation is performed according to the IEC/IEEE Standard -| for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -float128 float128_add( void* ctx, float128 a, float128 b ) -{ - flag aSign, bSign; - - aSign = extractFloat128Sign( a ); - bSign = extractFloat128Sign( b ); - if ( aSign == bSign ) { - return addFloat128Sigs( ctx, a, b, aSign ); - } - else { - return subFloat128Sigs( ctx, a, b, aSign ); - } - -} - -/*---------------------------------------------------------------------------- -| Returns the result of subtracting the quadruple-precision floating-point -| values `a' and `b'. The operation is performed according to the IEC/IEEE -| Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -float128 float128_sub( void* ctx, float128 a, float128 b ) -{ - flag aSign, bSign; - - aSign = extractFloat128Sign( a ); - bSign = extractFloat128Sign( b ); - if ( aSign == bSign ) { - return subFloat128Sigs( ctx, a, b, aSign ); - } - else { - return addFloat128Sigs( ctx, a, b, aSign ); - } - -} - -/*---------------------------------------------------------------------------- -| Returns the result of multiplying the quadruple-precision floating-point -| values `a' and `b'. The operation is performed according to the IEC/IEEE -| Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -float128 float128_mul( void* ctx, float128 a, float128 b ) -{ - flag aSign, bSign, zSign; - int32 aExp, bExp, zExp; - bits64 aSig0, aSig1, bSig0, bSig1, zSig0, zSig1, zSig2, zSig3; - float128 z; - - aSig1 = extractFloat128Frac1( a ); - aSig0 = extractFloat128Frac0( a ); - aExp = extractFloat128Exp( a ); - aSign = extractFloat128Sign( a ); - bSig1 = extractFloat128Frac1( b ); - bSig0 = extractFloat128Frac0( b ); - bExp = extractFloat128Exp( b ); - bSign = extractFloat128Sign( b ); - zSign = aSign ^ bSign; - if ( aExp == 0x7FFF ) { - if ( ( aSig0 | aSig1 ) - || ( ( bExp == 0x7FFF ) && ( bSig0 | bSig1 ) ) ) { - return propagateFloat128NaN( ctx, a, b ); - } - if ( ( bExp | bSig0 | bSig1 ) == 0 ) goto invalid; - return packFloat128( zSign, 0x7FFF, 0, 0 ); - } - if ( bExp == 0x7FFF ) { - if ( bSig0 | bSig1 ) return propagateFloat128NaN( ctx, a, b ); - if ( ( aExp | aSig0 | aSig1 ) == 0 ) { - invalid: - float_raise( ctx, float_flag_invalid ); - z.low = float128_default_nan_low; - z.high = float128_default_nan_high; - return z; - } - return packFloat128( zSign, 0x7FFF, 0, 0 ); - } - if ( aExp == 0 ) { - if ( ( aSig0 | aSig1 ) == 0 ) return packFloat128( zSign, 0, 0, 0 ); - normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 ); - } - if ( bExp == 0 ) { - if ( ( bSig0 | bSig1 ) == 0 ) return packFloat128( zSign, 0, 0, 0 ); - normalizeFloat128Subnormal( bSig0, bSig1, &bExp, &bSig0, &bSig1 ); - } - zExp = aExp + bExp - 0x4000; - aSig0 |= LIT64( 0x0001000000000000 ); - shortShift128Left( bSig0, bSig1, 16, &bSig0, &bSig1 ); - mul128To256( aSig0, aSig1, bSig0, bSig1, &zSig0, &zSig1, &zSig2, &zSig3 ); - add128( zSig0, zSig1, aSig0, aSig1, &zSig0, &zSig1 ); - zSig2 |= ( zSig3 != 0 ); - if ( LIT64( 0x0002000000000000 ) <= zSig0 ) { - shift128ExtraRightJamming( - zSig0, zSig1, zSig2, 1, &zSig0, &zSig1, &zSig2 ); - ++zExp; - } - return roundAndPackFloat128( ctx, zSign, zExp, zSig0, zSig1, zSig2 ); - -} - -/*---------------------------------------------------------------------------- -| Returns the result of dividing the quadruple-precision floating-point value -| `a' by the corresponding value `b'. The operation is performed according to -| the IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -float128 float128_div( void* ctx, float128 a, float128 b ) -{ - flag aSign, bSign, zSign; - int32 aExp, bExp, zExp; - bits64 aSig0, aSig1, bSig0, bSig1, zSig0, zSig1, zSig2; - bits64 rem0, rem1, rem2, rem3, term0, term1, term2, term3; - float128 z; - - aSig1 = extractFloat128Frac1( a ); - aSig0 = extractFloat128Frac0( a ); - aExp = extractFloat128Exp( a ); - aSign = extractFloat128Sign( a ); - bSig1 = extractFloat128Frac1( b ); - bSig0 = extractFloat128Frac0( b ); - bExp = extractFloat128Exp( b ); - bSign = extractFloat128Sign( b ); - zSign = aSign ^ bSign; - if ( aExp == 0x7FFF ) { - if ( aSig0 | aSig1 ) return propagateFloat128NaN( ctx, a, b ); - if ( bExp == 0x7FFF ) { - if ( bSig0 | bSig1 ) return propagateFloat128NaN( ctx, a, b ); - goto invalid; - } - return packFloat128( zSign, 0x7FFF, 0, 0 ); - } - if ( bExp == 0x7FFF ) { - if ( bSig0 | bSig1 ) return propagateFloat128NaN( ctx, a, b ); - return packFloat128( zSign, 0, 0, 0 ); - } - if ( bExp == 0 ) { - if ( ( bSig0 | bSig1 ) == 0 ) { - if ( ( aExp | aSig0 | aSig1 ) == 0 ) { - invalid: - float_raise( ctx, float_flag_invalid ); - z.low = float128_default_nan_low; - z.high = float128_default_nan_high; - return z; - } - float_raise( ctx, float_flag_divbyzero ); - return packFloat128( zSign, 0x7FFF, 0, 0 ); - } - normalizeFloat128Subnormal( bSig0, bSig1, &bExp, &bSig0, &bSig1 ); - } - if ( aExp == 0 ) { - if ( ( aSig0 | aSig1 ) == 0 ) return packFloat128( zSign, 0, 0, 0 ); - normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 ); - } - zExp = aExp - bExp + 0x3FFD; - shortShift128Left( - aSig0 | LIT64( 0x0001000000000000 ), aSig1, 15, &aSig0, &aSig1 ); - shortShift128Left( - bSig0 | LIT64( 0x0001000000000000 ), bSig1, 15, &bSig0, &bSig1 ); - if ( le128( bSig0, bSig1, aSig0, aSig1 ) ) { - shift128Right( aSig0, aSig1, 1, &aSig0, &aSig1 ); - ++zExp; - } - zSig0 = estimateDiv128To64( aSig0, aSig1, bSig0 ); - mul128By64To192( bSig0, bSig1, zSig0, &term0, &term1, &term2 ); - sub192( aSig0, aSig1, 0, term0, term1, term2, &rem0, &rem1, &rem2 ); - while ( (sbits64) rem0 < 0 ) { - --zSig0; - add192( rem0, rem1, rem2, 0, bSig0, bSig1, &rem0, &rem1, &rem2 ); - } - zSig1 = estimateDiv128To64( rem1, rem2, bSig0 ); - if ( ( zSig1 & 0x3FFF ) <= 4 ) { - mul128By64To192( bSig0, bSig1, zSig1, &term1, &term2, &term3 ); - sub192( rem1, rem2, 0, term1, term2, term3, &rem1, &rem2, &rem3 ); - while ( (sbits64) rem1 < 0 ) { - --zSig1; - add192( rem1, rem2, rem3, 0, bSig0, bSig1, &rem1, &rem2, &rem3 ); - } - zSig1 |= ( ( rem1 | rem2 | rem3 ) != 0 ); - } - shift128ExtraRightJamming( zSig0, zSig1, 0, 15, &zSig0, &zSig1, &zSig2 ); - return roundAndPackFloat128( ctx, zSign, zExp, zSig0, zSig1, zSig2 ); - -} - -/*---------------------------------------------------------------------------- -| Returns the remainder of the quadruple-precision floating-point value `a' -| with respect to the corresponding value `b'. The operation is performed -| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -float128 float128_rem( void* ctx, float128 a, float128 b ) -{ - flag aSign, bSign, zSign; - int32 aExp, bExp, expDiff; - bits64 aSig0, aSig1, bSig0, bSig1, q, term0, term1, term2; - bits64 allZero, alternateASig0, alternateASig1, sigMean1; - sbits64 sigMean0; - float128 z; - - aSig1 = extractFloat128Frac1( a ); - aSig0 = extractFloat128Frac0( a ); - aExp = extractFloat128Exp( a ); - aSign = extractFloat128Sign( a ); - bSig1 = extractFloat128Frac1( b ); - bSig0 = extractFloat128Frac0( b ); - bExp = extractFloat128Exp( b ); - bSign = extractFloat128Sign( b ); - if ( aExp == 0x7FFF ) { - if ( ( aSig0 | aSig1 ) - || ( ( bExp == 0x7FFF ) && ( bSig0 | bSig1 ) ) ) { - return propagateFloat128NaN( ctx, a, b ); - } - goto invalid; - } - if ( bExp == 0x7FFF ) { - if ( bSig0 | bSig1 ) return propagateFloat128NaN( ctx, a, b ); - return a; - } - if ( bExp == 0 ) { - if ( ( bSig0 | bSig1 ) == 0 ) { - invalid: - float_raise( ctx, float_flag_invalid ); - z.low = float128_default_nan_low; - z.high = float128_default_nan_high; - return z; - } - normalizeFloat128Subnormal( bSig0, bSig1, &bExp, &bSig0, &bSig1 ); - } - if ( aExp == 0 ) { - if ( ( aSig0 | aSig1 ) == 0 ) return a; - normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 ); - } - expDiff = aExp - bExp; - if ( expDiff < -1 ) return a; - shortShift128Left( - aSig0 | LIT64( 0x0001000000000000 ), - aSig1, - 15 - ( expDiff < 0 ), - &aSig0, - &aSig1 - ); - shortShift128Left( - bSig0 | LIT64( 0x0001000000000000 ), bSig1, 15, &bSig0, &bSig1 ); - q = le128( bSig0, bSig1, aSig0, aSig1 ); - if ( q ) sub128( aSig0, aSig1, bSig0, bSig1, &aSig0, &aSig1 ); - expDiff -= 64; - while ( 0 < expDiff ) { - q = estimateDiv128To64( aSig0, aSig1, bSig0 ); - q = ( 4 < q ) ? q - 4 : 0; - mul128By64To192( bSig0, bSig1, q, &term0, &term1, &term2 ); - shortShift192Left( term0, term1, term2, 61, &term1, &term2, &allZero ); - shortShift128Left( aSig0, aSig1, 61, &aSig0, &allZero ); - sub128( aSig0, 0, term1, term2, &aSig0, &aSig1 ); - expDiff -= 61; - } - if ( -64 < expDiff ) { - q = estimateDiv128To64( aSig0, aSig1, bSig0 ); - q = ( 4 < q ) ? q - 4 : 0; - q >>= - expDiff; - shift128Right( bSig0, bSig1, 12, &bSig0, &bSig1 ); - expDiff += 52; - if ( expDiff < 0 ) { - shift128Right( aSig0, aSig1, - expDiff, &aSig0, &aSig1 ); - } - else { - shortShift128Left( aSig0, aSig1, expDiff, &aSig0, &aSig1 ); - } - mul128By64To192( bSig0, bSig1, q, &term0, &term1, &term2 ); - sub128( aSig0, aSig1, term1, term2, &aSig0, &aSig1 ); - } - else { - shift128Right( aSig0, aSig1, 12, &aSig0, &aSig1 ); - shift128Right( bSig0, bSig1, 12, &bSig0, &bSig1 ); - } - do { - alternateASig0 = aSig0; - alternateASig1 = aSig1; - ++q; - sub128( aSig0, aSig1, bSig0, bSig1, &aSig0, &aSig1 ); - } while ( 0 <= (sbits64) aSig0 ); - add128( - aSig0, aSig1, alternateASig0, alternateASig1, (bits64*)&sigMean0, &sigMean1 ); - if ( ( sigMean0 < 0 ) - || ( ( ( sigMean0 | sigMean1 ) == 0 ) && ( q & 1 ) ) ) { - aSig0 = alternateASig0; - aSig1 = alternateASig1; - } - zSign = ( (sbits64) aSig0 < 0 ); - if ( zSign ) sub128( 0, 0, aSig0, aSig1, &aSig0, &aSig1 ); - return - normalizeRoundAndPackFloat128( ctx, aSign ^ zSign, bExp - 4, aSig0, aSig1 ); - -} - -/*---------------------------------------------------------------------------- -| Returns the square root of the quadruple-precision floating-point value `a'. -| The operation is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -float128 float128_sqrt( void* ctx, float128 a ) -{ - flag aSign; - int32 aExp, zExp; - bits64 aSig0, aSig1, zSig0, zSig1, zSig2, doubleZSig0; - bits64 rem0, rem1, rem2, rem3, term0, term1, term2, term3; - float128 z; - - aSig1 = extractFloat128Frac1( a ); - aSig0 = extractFloat128Frac0( a ); - aExp = extractFloat128Exp( a ); - aSign = extractFloat128Sign( a ); - if ( aExp == 0x7FFF ) { - if ( aSig0 | aSig1 ) return propagateFloat128NaN( ctx, a, a ); - if ( ! aSign ) return a; - goto invalid; - } - if ( aSign ) { - if ( ( aExp | aSig0 | aSig1 ) == 0 ) return a; - invalid: - float_raise( ctx, float_flag_invalid ); - z.low = float128_default_nan_low; - z.high = float128_default_nan_high; - return z; - } - if ( aExp == 0 ) { - if ( ( aSig0 | aSig1 ) == 0 ) return packFloat128( 0, 0, 0, 0 ); - normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 ); - } - zExp = ( ( aExp - 0x3FFF )>>1 ) + 0x3FFE; - aSig0 |= LIT64( 0x0001000000000000 ); - zSig0 = estimateSqrt32( aExp, aSig0>>17 ); - shortShift128Left( aSig0, aSig1, 13 - ( aExp & 1 ), &aSig0, &aSig1 ); - zSig0 = estimateDiv128To64( aSig0, aSig1, zSig0<<32 ) + ( zSig0<<30 ); - doubleZSig0 = zSig0<<1; - mul64To128( zSig0, zSig0, &term0, &term1 ); - sub128( aSig0, aSig1, term0, term1, &rem0, &rem1 ); - while ( (sbits64) rem0 < 0 ) { - --zSig0; - doubleZSig0 -= 2; - add128( rem0, rem1, zSig0>>63, doubleZSig0 | 1, &rem0, &rem1 ); - } - zSig1 = estimateDiv128To64( rem1, 0, doubleZSig0 ); - if ( ( zSig1 & 0x1FFF ) <= 5 ) { - if ( zSig1 == 0 ) zSig1 = 1; - mul64To128( doubleZSig0, zSig1, &term1, &term2 ); - sub128( rem1, 0, term1, term2, &rem1, &rem2 ); - mul64To128( zSig1, zSig1, &term2, &term3 ); - sub192( rem1, rem2, 0, 0, term2, term3, &rem1, &rem2, &rem3 ); - while ( (sbits64) rem1 < 0 ) { - --zSig1; - shortShift128Left( 0, zSig1, 1, &term2, &term3 ); - term3 |= 1; - term2 |= doubleZSig0; - add192( rem1, rem2, rem3, 0, term2, term3, &rem1, &rem2, &rem3 ); - } - zSig1 |= ( ( rem1 | rem2 | rem3 ) != 0 ); - } - shift128ExtraRightJamming( zSig0, zSig1, 0, 14, &zSig0, &zSig1, &zSig2 ); - return roundAndPackFloat128( ctx, 0, zExp, zSig0, zSig1, zSig2 ); - -} - -/*---------------------------------------------------------------------------- -| Returns 1 if the quadruple-precision floating-point value `a' is equal to -| the corresponding value `b', and 0 otherwise. The comparison is performed -| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -flag float128_eq( void* ctx, float128 a, float128 b ) -{ - - if ( ( ( extractFloat128Exp( a ) == 0x7FFF ) - && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) ) ) - || ( ( extractFloat128Exp( b ) == 0x7FFF ) - && ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) ) - ) { - if ( float128_is_signaling_nan( a ) - || float128_is_signaling_nan( b ) ) { - float_raise( ctx, float_flag_invalid ); - } - return 0; - } - return - ( a.low == b.low ) - && ( ( a.high == b.high ) - || ( ( a.low == 0 ) - && ( (bits64) ( ( a.high | b.high )<<1 ) == 0 ) ) - ); - -} - -/*---------------------------------------------------------------------------- -| Returns 1 if the quadruple-precision floating-point value `a' is less than -| or equal to the corresponding value `b', and 0 otherwise. The comparison -| is performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic. -*----------------------------------------------------------------------------*/ - -flag float128_le( void* ctx, float128 a, float128 b ) -{ - flag aSign, bSign; - - if ( ( ( extractFloat128Exp( a ) == 0x7FFF ) - && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) ) ) - || ( ( extractFloat128Exp( b ) == 0x7FFF ) - && ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) ) - ) { - float_raise( ctx, float_flag_invalid ); - return 0; - } - aSign = extractFloat128Sign( a ); - bSign = extractFloat128Sign( b ); - if ( aSign != bSign ) { - return - aSign - || ( ( ( (bits64) ( ( a.high | b.high )<<1 ) ) | a.low | b.low ) - == 0 ); - } - return - aSign ? le128( b.high, b.low, a.high, a.low ) - : le128( a.high, a.low, b.high, b.low ); - -} - -/*---------------------------------------------------------------------------- -| Returns 1 if the quadruple-precision floating-point value `a' is less than -| the corresponding value `b', and 0 otherwise. The comparison is performed -| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -flag float128_lt( void* ctx, float128 a, float128 b ) -{ - flag aSign, bSign; - - if ( ( ( extractFloat128Exp( a ) == 0x7FFF ) - && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) ) ) - || ( ( extractFloat128Exp( b ) == 0x7FFF ) - && ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) ) - ) { - float_raise( ctx, float_flag_invalid ); - return 0; - } - aSign = extractFloat128Sign( a ); - bSign = extractFloat128Sign( b ); - if ( aSign != bSign ) { - return - aSign - && ( ( ( (bits64) ( ( a.high | b.high )<<1 ) ) | a.low | b.low ) - != 0 ); - } - return - aSign ? lt128( b.high, b.low, a.high, a.low ) - : lt128( a.high, a.low, b.high, b.low ); - -} - -/*---------------------------------------------------------------------------- -| Returns 1 if the quadruple-precision floating-point value `a' is equal to -| the corresponding value `b', and 0 otherwise. The invalid exception is -| raised if either operand is a NaN. Otherwise, the comparison is performed -| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -flag float128_eq_signaling( void* ctx, float128 a, float128 b ) -{ - - if ( ( ( extractFloat128Exp( a ) == 0x7FFF ) - && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) ) ) - || ( ( extractFloat128Exp( b ) == 0x7FFF ) - && ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) ) - ) { - float_raise( ctx, float_flag_invalid ); - return 0; - } - return - ( a.low == b.low ) - && ( ( a.high == b.high ) - || ( ( a.low == 0 ) - && ( (bits64) ( ( a.high | b.high )<<1 ) == 0 ) ) - ); - -} - -/*---------------------------------------------------------------------------- -| Returns 1 if the quadruple-precision floating-point value `a' is less than -| or equal to the corresponding value `b', and 0 otherwise. Quiet NaNs do not -| cause an exception. Otherwise, the comparison is performed according to the -| IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -flag float128_le_quiet( void* ctx, float128 a, float128 b ) -{ - flag aSign, bSign; - - if ( ( ( extractFloat128Exp( a ) == 0x7FFF ) - && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) ) ) - || ( ( extractFloat128Exp( b ) == 0x7FFF ) - && ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) ) - ) { - if ( float128_is_signaling_nan( a ) - || float128_is_signaling_nan( b ) ) { - float_raise( ctx, float_flag_invalid ); - } - return 0; - } - aSign = extractFloat128Sign( a ); - bSign = extractFloat128Sign( b ); - if ( aSign != bSign ) { - return - aSign - || ( ( ( (bits64) ( ( a.high | b.high )<<1 ) ) | a.low | b.low ) - == 0 ); - } - return - aSign ? le128( b.high, b.low, a.high, a.low ) - : le128( a.high, a.low, b.high, b.low ); - -} - -/*---------------------------------------------------------------------------- -| Returns 1 if the quadruple-precision floating-point value `a' is less than -| the corresponding value `b', and 0 otherwise. Quiet NaNs do not cause an -| exception. Otherwise, the comparison is performed according to the IEC/IEEE -| Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -flag float128_lt_quiet( void* ctx, float128 a, float128 b ) -{ - flag aSign, bSign; - - if ( ( ( extractFloat128Exp( a ) == 0x7FFF ) - && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) ) ) - || ( ( extractFloat128Exp( b ) == 0x7FFF ) - && ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) ) - ) { - if ( float128_is_signaling_nan( a ) - || float128_is_signaling_nan( b ) ) { - float_raise( ctx, float_flag_invalid ); - } - return 0; - } - aSign = extractFloat128Sign( a ); - bSign = extractFloat128Sign( b ); - if ( aSign != bSign ) { - return - aSign - && ( ( ( (bits64) ( ( a.high | b.high )<<1 ) ) | a.low | b.low ) - != 0 ); - } - return - aSign ? lt128( b.high, b.low, a.high, a.low ) - : lt128( a.high, a.low, b.high, b.low ); - -} - -#endif // FLOAT128 diff --git a/softfloat_types.h b/softfloat_types.h new file mode 100644 index 000000000..c7b67ae91 --- /dev/null +++ b/softfloat_types.h @@ -0,0 +1,80 @@ + +/*============================================================================ + +This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic +Package, Release 3a, by John R. Hauser. + +Copyright 2011, 2012, 2013, 2014 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +#ifndef softfloat_types_h +#define softfloat_types_h 1 + +#include + +/*---------------------------------------------------------------------------- +| Types used to pass 32-bit, 64-bit, and 128-bit floating-point arguments and +| results to/from functions. These types must be exactly 32 bits, 64 bits, +| and 128 bits in size, respectively. Where a platform has "native" support +| for IEEE-Standard floating-point formats, the types below may, if desired, +| be defined as aliases for the native types (typically `float' and `double', +| and possibly `long double'). +*----------------------------------------------------------------------------*/ +typedef struct { uint32_t v; } float32_t; +typedef struct { uint64_t v; } float64_t; +typedef struct { uint64_t v[2]; } float128_t; + +/*---------------------------------------------------------------------------- +| The format of an 80-bit extended floating-point number in memory. This +| structure must contain a 16-bit field named `signExp' and a 64-bit field +| named `signif'. +*----------------------------------------------------------------------------*/ +#ifdef LITTLEENDIAN +struct extFloat80M { uint64_t signif; uint16_t signExp; }; +#else +struct extFloat80M { uint16_t signExp; uint64_t signif; }; +#endif + +/*---------------------------------------------------------------------------- +| The type used to pass 80-bit extended floating-point arguments and +| results to/from functions. This type must have size identical to +| `struct extFloat80M'. Type `extFloat80_t' can be defined as an alias for +| `struct extFloat80M'. Alternatively, if a platform has "native" support +| for IEEE-Standard 80-bit extended floating-point, it may be possible, +| if desired, to define `extFloat80_t' as an alias for the native type +| (presumably either `long double' or a nonstandard compiler-intrinsic type). +| In that case, the `signif' and `signExp' fields of `struct extFloat80M' +| must align exactly with the locations in memory of the sign, exponent, and +| significand of the native type. +*----------------------------------------------------------------------------*/ +typedef struct extFloat80M extFloat80_t; + +#endif + diff --git a/tests/bfp-001-divtoint.asm b/tests/bfp-001-divtoint.asm new file mode 100644 index 000000000..ebdfba0ae --- /dev/null +++ b/tests/bfp-001-divtoint.asm @@ -0,0 +1,1561 @@ + TITLE 'bfp-001-divtoint.asm: Test IEEE Divide To Integer' +*********************************************************************** +* +*Testcase IEEE DIVIDE TO INTEGER +* Test case capability includes IEEE exceptions trappable and +* otherwise. Test results, FPCR flags, and any DXC are saved for all +* tests. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* bfp-001-divtoint.asm +* +* This assembly-language source file is part of the +* Hercules Decimal Floating Point Validation Package +* by Stephen R. Orso +* +* Copyright 2016 by Stephen R Orso. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* +* 3. The name of the author may not be used to endorse or promote +* products derived from this software without specific prior written +* permission. +* +* DISCLAMER: THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* HOLDER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*********************************************************************** + SPACE 2 +* +*Outstanding Issues: +* - 'A' versions of instructions are not tested. Space for these added +* results has not been allowed for in the results areas. Eight +* additional results are needed per input pair. +* - Initial execution on real hardware shows no inexact / truncated on +* underflow; not sure this case can be created on Add. Finite +* rounding mode test cases must be reviewed. +* - The quantum exception is not tested. This is only available in the +* 'A' mode instructions, and only the finite tests will detect a +* quantum trap. This has implications for the test case selection +* and the selection of the instruction used for the test. Note: the +* M4 rounding mode used with the 'A' instructions must be in the +* range 8-15. +* - Note that the test case values selected for the rounding mode tests +* will never trigger the quantum flag. +* +* - If Quantum exceptions can be created, they will be tested in the +* Finite tests. +* - A fourth test run will perform pathlength validation on the M4 +* Rounding Mode tests, rather than run 16 additional tests on each of +* 8 (at present) rounding mode test pairs. A pair of tests is +* sufficient: a positive RNTE odd and a negative RNTE even. (Or the +* other way around.) +* +* +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* Tests the following three conversion instructions +* DIVIDE TO INTEGER (short BFP, RRE) +* DIVIDE TO INTEGER (long BFP, RRE) +* +* Test data is compiled into this program. The test script that runs +* this program can provide alternative test data through Hercules R +* commands. +* +* Test Case Order +* 1) Short BFP basic tests, including traps and NaN propagation +* 2) Short BFP finite number tests, incl. partial and final results +* 3) Short BFP rounding, tests of quotient and remainder rounding +* 4) Long BFP basic tests, including traps and NaN propagation +* 5) Long BFP finite number tests, incl. partial and final results +* 6) Short BFP rounding, tests of quotient and remainder rounding +* +* Three input test sets are provided each for short and long +* BFP inputs. Test values are conceptually the same for each +* precision, but the values differ between precisions. Overflow, +* for example, is triggered by different values in short and long, +* but each test set includes overflow tests. +* +* Also tests the following floating point support instructions +* LOAD (Short) +* LOAD (Long) +* LFPC (Load Floating Point Control Register) +* SRNMB (Set BFP Rounding Mode 2-bit) +* SRNMB (Set BFP Rounding Mode 3-bit) +* STORE (Short) +* STORE (Long) +* STFPC (Store Floating Point Control Register) +* +*********************************************************************** + SPACE 2 + MACRO + PADCSECT &ENDLABL +.* +.* Macro to pad the CSECT to include result data areas if this test +.* program is not being assembled using asma. asma generates a core +.* image that is loaded by the loadcore command, and because the +.* core image is a binary stored in Github, it makes sense to make +.* this small effort to keep the core image small. +.* + AIF (D'&ENDLABL).GOODPAD + MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + MNOTE *,'No CSECT padding performed' + MEXIT +.* +.GOODPAD ANOP Label valid. See if we're on asma + AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + ORG &ENDLABL-1 Not ASMA. Pad CSECT + MEXIT +.* +.NOPAD ANOP + MNOTE *,'asma detected; no CSECT padding performed' + MEND +* +* Note: for compatibility with the z/CMS test rig, do not change +* or use R11, R14, or R15. Everything else is fair game. +* +BFPDV2NT START 0 +STRTLABL EQU * +R0 EQU 0 Work register for cc extraction +R1 EQU 1 +R2 EQU 2 Holds count of test input values +R3 EQU 3 Points to next test input value(s) +R4 EQU 4 Rounding tests inner loop control +R5 EQU 5 Rounding tests outer loop control +R6 EQU 6 Rounding tests top of inner loop +R7 EQU 7 Pointer to next result value(s) +R8 EQU 8 Pointer to next FPCR result +R9 EQU 9 Rounding tests top of outer loop +R10 EQU 10 Pointer to test address list +R11 EQU 11 **Reserved for z/CMS test rig +R12 EQU 12 Holds number of test cases in set +R13 EQU 13 Mainline return address +R14 EQU 14 **Return address for z/CMS test rig +R15 EQU 15 **Base register on z/CMS or Hyperion +* +* Floating Point Register equates to keep the cross reference clean +* +FPR0 EQU 0 +FPR1 EQU 1 +FPR2 EQU 2 +FPR3 EQU 3 +FPR4 EQU 4 +FPR5 EQU 5 +FPR6 EQU 6 +FPR7 EQU 7 +FPR8 EQU 8 +FPR9 EQU 9 +FPR10 EQU 10 +FPR11 EQU 11 +FPR12 EQU 12 +FPR13 EQU 13 +FPR14 EQU 14 +FPR15 EQU 15 +* + USING *,R15 +* +* Above works on real iron (R15=0 after sysclear) +* and in z/CMS (R15 points to start of load module) +* + SPACE 2 +*********************************************************************** +* +* Low core definitions, Restart PSW, and Program Check Routine. +* +*********************************************************************** + SPACE 2 + ORG STRTLABL+X'8E' Program check interrution code +PCINTCD DS H +* +PCOLDPSW EQU STRTLABL+X'150' z/Arch Program check old PSW +* + ORG STRTLABL+X'1A0' z/Arch Restart PSW + DC X'0000000180000000',AD(START) +* + ORG STRTLABL+X'1D0' z/Arch Program check old PSW + DC X'0000000000000000',AD(PROGCHK) +* +* Program check routine. If Data Exception, continue execution at +* the instruction following the program check. Otherwise, hard wait. +* No need to collect data. All interesting DXC stuff is captured +* in the FPCR. +* + ORG STRTLABL+X'200' +PROGCHK DS 0H Program check occured... + CLI PCINTCD+1,X'07' Data Exception? + JNE PCNOTDTA ..no, hardwait + LPSWE PCOLDPSW ..yes, resume program execution +PCNOTDTA DS 0H + LTR R14,R14 Return address provided? + BNZR R14 Yes, return to z/CMS test rig. + LPSWE HARDWAIT Not data exception, enter disabled wait + EJECT +*********************************************************************** +* +* Main program. Enable Advanced Floating Point, process test cases. +* +*********************************************************************** + SPACE 2 +START DS 0H + STCTL R0,R0,CTLR0 Store CR0 to enable AFP + OI CTLR0+1,X'04' Turn on AFP bit + LCTL R0,R0,CTLR0 Reload updated CR0 +* + LA R10,SHORTNF Point to short BFP non-finite inputs + BAS R13,DIEBRNF Divide to Integer short BFP non-finite + LA R10,SHORTF Point to short BFP finite inputs + BAS R13,DIEBRF Divide to Integer short BFP finites + LA R10,RMSHORTS Point to short BFP rounding mode tests + BAS R13,DIEBRRM Convert using all rounding mode options +* + LA R10,LONGNF Point to long BFP non-finite inputs + BAS R13,DIDBRNF Divide to Integer long BFP basic + LA R10,LONGF Point to long BFP finite inputs + BAS R13,DIDBRF Divide to Integer long BFP basic + LA R10,RMLONGS Point to long BFP rounding mode tests + BAS R13,DIDBRRM Convert using all rounding mode options +* + LTR R14,R14 Return address provided? + BNZR R14 ..Yes, return to z/CMS test rig. + LPSWE WAITPSW All done +* + DS 0D Ensure correct alignment for psw +WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end +* +CTLR0 DS F +FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags +* +* Input values parameter list, four fullwords for each test data set +* 1) Count, +* 2) Address of inputs, +* 3) Address to place results, and +* 4) Address to place DXC/Flags/cc values. +* + ORG STRTLABL+X'300' Enable run-time replacement +SHORTNF DS 0F Input pairs for short BFP non-finite tests + DC A(SBFPNFCT) + DC A(SBFPNFIN) + DC A(SBFPNFOT) + DC A(SBFPNFFL) +* +SHORTF DS 0F Input pairs for short BFP finite tests + DC A(SBFPCT) + DC A(SBFPIN) + DC A(SBFPOUT) + DC A(SBFPFLGS) +* +RMSHORTS DS 0F Input pairs for short BFP rounding testing + DC A(SBFPRMCT) + DC A(SBFPINRM) + DC A(SBFPRMO) + DC A(SBFPRMOF) +* +LONGNF DS 0F Input pairs for long BFP non-finite testing + DC A(LBFPNFCT) + DC A(LBFPNFIN) + DC A(LBFPNFOT) + DC A(LBFPNFFL) +* +LONGF DS 0F Input pairs for long BFP finite testing + DC A(LBFPCT) + DC A(LBFPIN) + DC A(LBFPOUT) + DC A(LBFPFLGS) +* +RMLONGS DS 0F Input pairs for long BFP rounding testing + DC A(LBFPRMCT) + DC A(LBFPINRM) + DC A(LBFPRMO) + DC A(LBFPRMOF) + EJECT +*********************************************************************** +* +* Perform Divide to Integer using provided short BFP input pairs. This +* set of tests checks NaN propagation and operations on values that are +* not finite numbers. +* +* A pair of results is generated for each input: one with all +* exceptions non-trappable, and the second with all exceptions +* trappable. The FPCR and condition code is stored for each result. +* +*********************************************************************** + SPACE 2 +DIEBRNF DS 0H BFP Short non-finite values tests + LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LFPC FPCREGNT Set exceptions non-trappable + LE FPR0,0(,R3) Get short BFP dividend + LE FPR1,4(,R3) Get short BFP divisor + LZER FPR2 Zero remainder register + DIEBR FPR0,FPR2,FPR1,0 Div to Int FPR0/FPR1, M4=use FPCR +* Quotient in FPR2, remainder in FPR0 + STE FPR0,0(,R7) Store short BFP remainder + STE FPR2,4(,R7) Store short BFP quotient + STFPC 0(R8) Store resulting FPCR flags and DXC + IPM R0 Retrieve condition code + SRL R0,28 Move CC to low-order r0, dump prog mask + STC R0,3(0,R8) Store in last byte of FPCR +* + LFPC FPCREGTR Set exceptions trappable + LE FPR0,0(,R3) Get short BFP dividend + LE FPR1,4(,R3) Get short BFP divisor + LZER FPR2 Zero remainder register + DIEBR FPR0,FPR2,FPR1,0 Div to Int FPR0/FPR1, M4=use FPCR +* Quotient in FPR2, remainder in FPR0 + STE FPR0,8(,R7) Store short BFP remainder + STE FPR2,12(,R7) Store short BFP quotient + STFPC 4(R8) Store resulting FPCR flags and DXC + IPM R0 Retrieve condition code + SRL R0,28 Move CC to low-order r0, dump prog mask + STC R0,7(,R8) Store in last byte of FPCR +* + LA R3,8(,R3) Point to next input value pair + LA R7,16(,R7) Point to next quo&rem result value pair + LA R8,8(,R8) Point to next FPCR result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Divide to Integer using provided short BFP input pairs. This +* set of tests performs basic checks of Divide To Integer emulation +* where both inputs are finite non-zero numbers. +* +* Four results (six values) are generated for each input: +* 1) Divide to integer with all exceptions non-trappable (two values) +* 2) Multiply integer quotient by divisor, add remainder (one value) +* 3) Divide to integerwith all exceptions trappable (two values) +* 4) Multiply integer quotient by divisor, add remainder (one value) +* +* The FPCR and condition code is stored for each result. Note: the +* Multiply and Add instruction does not set the condition code. +* +* Results two and four (multiply and add) validate the calculation +* of the integer quotient and remainder. +* +*********************************************************************** + SPACE 2 +DIEBRF LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LFPC FPCREGNT Set exceptions non-trappable + LE FPR0,0(,R3) Get short BFP dividend + LE FPR1,4(,R3) Get short BFP divisor + LZER FPR2 Zero remainder register + DIEBR FPR0,FPR2,FPR1,0 Div to Int FPR0/FPR1, M4=use FPCR +* Quotient in FPR2, remainder in FPR0 + STE FPR0,0(,R7) Store short BFP remainder + STE FPR2,4(,R7) Store short BFP quotient + STFPC 0(R8) Store resulting FPCR flags and DXC + IPM R0 Retrieve condition code + SRL R0,28 Move CC to low-order r0, dump prog mask + STC R0,3(,R8) Store in last byte of FPCR +* +* FPR1 still has divisor, FPR0 has remainder, FPR2 has integer quotient +* + LFPC FPCREGNT Set exceptions non-trappable + MAEBR FPR0,FPR2,FPR1 Multiply and add to recreate inputs +* Sum of product and remainder in FPR0 + STE FPR0,8(,R7) Store short BFP product-sum + STFPC 4(R8) Store resulting FPCR flags and DXC + IPM R0 Retrieve condition code + SRL R0,28 Move CC to low-order r0, dump prog mask + STC R0,7(,R8) Store in last byte of FPCR +* + LFPC FPCREGTR Set exceptions trappable + LE FPR0,0(,R3) Get short BFP dividend + LE FPR1,4(,R3) Get short BFP divisor + LZER FPR2 Zero remainder register + DIEBR FPR0,FPR2,FPR1,0 Div to Int FPR0/FPR1, M4=use FPCR +* Quotient in FPR2, remainder in FPR0 + STE FPR0,16(,R7) Store short BFP remainder + STE FPR2,20(,R7) Store short BFP quotient + STFPC 8(R8) Store resulting FPCR flags and DXC + IPM R0 Retrieve condition code + SRL R0,28 Move CC to low-order r0, dump prog mask + STC R0,11(,R8) Store in last byte of FPCR +* +* FPR1 still has divisor, FPR0 has remainder, FPR2 has integer quotient +* + LFPC FPCREGNT Set exceptions non-trappable + MAEBR FPR0,FPR2,FPR1 Multiply and add to recreate inputs +* Sum of product and remainder in FPR0 + STE FPR0,24(,R7) Store short BFP remainder + STFPC 12(R8) Store resulting FPCR flags and DXC + IPM R0 Retrieve condition code + SRL R0,28 Move CC to low-order r0, dump prog mask + STC R0,15(,R8) Store in last byte of FPCR + +* + LA R3,8(,R3) Point to next input value pair + LA R7,32(,R7) Point to next quo&rem result value pair + LA R8,16(,R8) Point to next FPCR result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* The next tests operate on finite number input pairs and exhastively +* test rounding modes and partial and final results. +* +* Two rounding modes can be specified for each operation: one for the +* quotient, specified in the M4 field, and the second for the +* remainder, specified in the FPCR. +* +* Because six unique rounding modes can be specified in for the +* quotient and four for the remainder, there are a lot of results that +* need to be evaluated. Note: M4 rounding mode zero, use FPCR rounding +* mode, is not tested because it duplicates one of the six explicit +* M4 rounding modes. Which one depends on the current FPCR setting. +* +* The M4 rounding mode is assembled into the instruction. Back in the +* day, this would be a perfect candidate for an Execute instructoin. +* But the M4 field is not located such that it can be modified by +* an Execute instruction. So we will still use Execute, but only to +* select one of six DIEBR instructions for execution. That way we can +* build an outer loop to iterate through the four FPCR modes, and an +* inner loop to use each of the six M4-specified rounding modes. +* +*********************************************************************** + SPACE 2 +DIEBRRM LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + XR R1,R1 Zero register 1 for use in IC/STC/indexing + BASR R12,0 Set top of test case loop + + LA R5,FPCMCT Get count of FPC modes to be tested + BASR R9,0 Set top of rounding mode outer loop +* +* Update model FPC register settings with the BFP rounding mode for +* this iteration of the loop. +* + IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode +* + LA R4,D2IMCT Get count of M4 modes to be tested + BASR R6,0 Set top of rounding mode inner loop +* +* Non-trap execution of the instruction. +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode + SRNMB 0(R1) Set FPC Rounding Mode + LE FPR0,0(,R3) Get short BFP dividend + LE FPR1,4(,R3) Get short BFP divisor + LZER FPR2 Zero remainder register + IC R1,D2IMODES-L'D2IMODES(R4) Get index DIEBR inst table + EX 0,DIEBRTAB(R1) Execute Divide to Integer + STE FPR0,0(,R7) Store short BFP remainder + STE FPR2,4(,R7) Store short BFP quotient + STFPC 0(R8) Store resulting FPCR flags and DXC + IPM R0 Retrieve condition code + SRL R0,28 Move CC to low-order r0, dump prog mask + STC R0,3(,R8) Store in last byte of FPCR +* +* Trap-enabled execution of the instruction. +* + LFPC FPCREGTR Set exceptions trappable, clear flags + IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode + SRNMB 0(R1) Set FPC Rounding Mode + LE FPR0,0(,R3) Get short BFP dividend + LE FPR1,4(,R3) Get short BFP divisor + LZER FPR2 Zero remainder register + IC R1,D2IMODES-L'D2IMODES(R4) Get index DIEBR inst table + EX 0,DIEBRTAB(R1) Execute Divide to Integer + STE FPR0,8(,R7) Store short BFP remainder + STE FPR2,12(,R7) Store short BFP quotient + STFPC 4(R8) Store resulting FPCR flags and DXC + IPM R0 Retrieve condition code + SRL R0,28 Move CC to low-order r0, dump prog mask + STC R0,7(,R8) Store in last byte of FPCR +* + LA R7,16(,R7) Point to next quo&rem result value pair + LA R8,8(,R8) Point to next FPCR result area +* + BCTR R4,R6 Iterate inner loop +* +* End of M4 modes to be tested. +* + BCTR R5,R9 Iterate outer loop +* +* End of FPC modes to be tested with each M4 mode. Advance to +* next test case. +* + LA R3,8(,R3) Point to next input value pair + BCTR R2,R12 Divide next input value lots of times +* + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Divide to Integer using provided long BFP input pairs. This +* set of tests checks NaN propagation and operations on values that are +* not finite numbers. +* +* A pair of results is generated for each input: one with all +* exceptions non-trappable, and the second with all exceptions +* trappable. The FPCR and condition code is stored for each result. +* +*********************************************************************** + SPACE 2 +DIDBRNF LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LFPC FPCREGNT Set exceptions non-trappable + LD FPR0,0(,R3) Get long BFP dividend + LD FPR1,8(,R3) Get long BFP divisor + LZDR FPR2 Zero remainder register + DIDBR FPR0,FPR2,FPR1,0 Div to Int FPR0/FPR1, M4=use FPCR +* Quotient in FPR2, remainder in FPR0 + STD FPR0,0(,R7) Store long BFP remainder + STD FPR2,8(,R7) Store long BFP quotient + STFPC 0(R8) Store resulting FPCR flags and DXC + IPM R0 Retrieve condition code + SRL R0,28 Move CC to low-order r0, dump prog mask + STC R0,3(,R8) Store in last byte of FPCR +* + LFPC FPCREGTR Set exceptions trappable + LD FPR0,0(,R3) Get long BFP dividend + LD FPR1,8(,R3) Get long BFP divisor + LZDR FPR2 Zero remainder register + DIDBR FPR0,FPR2,FPR1,0 Div to Int FPR0/FPR1, M4=use FPCR +* Quotient in FPR2, remainder in FPR0 + STD FPR0,16(,R7) Store long BFP remainder + STD FPR2,24(,R7) Store long BFP quotient + STFPC 4(R8) Store resulting FPCR flags and DXC + IPM R0 Retrieve condition code + SRL R0,28 Move CC to low-order r0, dump prog mask + STC R0,7(,R8) Store in last byte of FPCR +* + LA R3,16(,R3) Point to next input value pair + LA R7,32(,R7) Point to next quo&rem result value pair + LA R8,8(,R8) Point to next FPCR result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Divide to Integer using provided long BFP input pairs. This +* set of tests performs basic checks of Divide To Integer emulation +* where both inputs are finite non-zero numbers. +* +* Four results (six values) are generated for each input: +* 1) Divide to integer with all exceptions non-trappable (two values) +* 2) Multiply integer quotient by divisor, add remainder (one value) +* 3) Divide to integerwith all exceptions trappable (two values) +* 4) Multiply integer quotient by divisor, add remainder (one value) +* +* The FPCR and condition code is stored for each result. Note: the +* Multiply and Add instruction does not set the condition code. +* +* Results two and four (multiply and add) validate the calculation +* of the integer quotient and remainder. +* +*********************************************************************** + SPACE 2 +DIDBRF LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LFPC FPCREGNT Set exceptions non-trappable + LD FPR0,0*32+0(,R3) Get long BFP dividend + LD FPR1,0*32+8(,R3) Get long BFP divisor + LZDR FPR2 Zero remainder register + DIDBR FPR0,FPR2,FPR1,0 Div to Int FPR0/FPR1, M4=use FPCR +* Quotient in FPR2, remainder in FPR0 + STD FPR0,0*32+0(,R7) Store long BFP remainder + STD FPR2,0*32+8(,R7) Store long BFP quotient + STFPC 0*4(R8) Store resulting FPCR flags and DXC + IPM R0 Retrieve condition code + SRL R0,28 Move CC to low-order r0, dump prog mask + STC R0,0*4+3(,R8) Store in last byte of FPCR +* +* FPR1 still has divisor, FPR0 has remainder, FPR2 has integer quotient +* + LFPC FPCREGNT Set exceptions non-trappable + MADBR FPR0,FPR2,FPR1 Multiply and add to recreate inputs +* Sum of product and remainder in FPR0 + STD FPR0,0*32+16(,R7) Store short BFP product-sum + STFPC 1*4(R8) Store resulting FPCR flags and DXC + IPM R0 Retrieve condition code + SRL R0,28 Move CC to low-order r0, dump prog mask + STC R0,1*4+3(,R8) Store in last byte of FPCR +* + LFPC FPCREGTR Set exceptions trappable + LD FPR0,0(,R3) Get long BFP dividend + LD FPR1,8(,R3) Get long BFP divisor + LZDR FPR2 Zero remainder register + DIDBR FPR0,FPR2,FPR1,0 Div to Int FPR0/FPR1, M4=use FPCR +* Quotient in FPR2, remainder in FPR0 + STD FPR0,1*32+0(,R7) Store long BFP remainder + STD FPR2,1*32+8(,R7) Store long BFP quotient + STFPC 2*4(R8) Store resulting FPCR flags and DXC + IPM R0 Retrieve condition code + SRL R0,28 Move CC to low-order r0, dump prog mask + STC R0,2*4+3(,R8) Store in last byte of FPCR +* +* FPR1 still has divisor, FPR0 has remainder, FPR2 has integer quotient +* + LFPC FPCREGNT Set exceptions non-trappable + MADBR FPR0,FPR2,FPR1 Multiply and add to recreate inputs +* Sum of product and remainder in FPR0 + STD FPR0,1*32+16(,R7) Store short BFP product-sum + STFPC 3*4(R8) Store resulting FPCR flags and DXC + IPM R0 Retrieve condition code + SRL R0,28 Move CC to low-order r0, dump prog mask + STC R0,3*4+3(,R8) Store in last byte of FPCR +* + LA R3,16(,R3) Point to next input value pair + LA R7,64(,R7) Point to next quo&rem result value pair + LA R8,16(,R8) Point to next FPCR result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* The next tests operate on finite number input pairs and exhastively +* test rounding modes and partial and final results. +* +* Two rounding modes can be specified for each operation: one for the +* quotient, specified in the M4 field, and the second for the +* remainder, specified in the FPCR. +* +* Because six unique rounding modes can be specified in for the +* quotient and four for the remainder, there are a lot of results that +* need to be evaluated. Note: M4 rounding mode zero, use FPCR rounding +* mode, is not tested because it duplicates one of the six explicit +* M4 rounding modes. Which one depends on the current FPCR setting. +* +* The M4 rounding mode is assembled into the instruction. Back in the +* day, this would be a perfect candidate for an Execute instructoin. +* But the M4 field is not located such that it can be modified by +* an Execute instruction. So we will still use Execute, but only to +* select one of six DIEBR instructions for execution. That way we can +* build an outer loop to iterate through the four FPCR modes, and an +* inner loop to use each of the six M4-specified rounding modes. +* +*********************************************************************** + SPACE 2 +DIDBRRM LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + XR R1,R1 Zero register 1 for use in IC/STC/indexing + BASR R12,0 Set top of test case loop + + LA R5,FPCMCT Get count of FPC modes to be tested + BASR R9,0 Set top of rounding mode outer loop +* +* Update model FPC register settings with the BFP rounding mode for +* this iteration of the loop. +* + IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode + STC R1,FPCREGNT+3 Update non-trap register settings + STC R1,FPCREGTR+3 Update trap-enabled register settings +* + LA R4,D2IMCT Get count of M4 modes to be tested + BASR R6,0 Set top of rounding mode inner loop +* +* Non-trap execution of the instruction. +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode + SRNMB 0(R1) Set FPC Rounding Mode + LD FPR0,0(,R3) Get short BFP dividend + LD FPR1,8(,R3) Get short BFP divisor + LZDR FPR2 Zero remainder register + IC R1,D2IMODES-L'D2IMODES(R4) Get index DIEBR inst table + EX 0,DIDBRTAB(R1) Execute Divide to Integer + STD FPR0,0(,R7) Store short BFP remainder + STD FPR2,8(,R7) Store short BFP quotient + STFPC 0(R8) Store resulting FPCR flags and DXC + IPM R0 Retrieve condition code + SRL R0,28 Move CC to low-order r0, dump prog mask + STC R0,3(,R8) Store in last byte of FPCR +* +* Trap-enabled execution of the instruction. +* + LFPC FPCREGTR Set exceptions trappable, clear flags + IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode + SRNMB 0(R1) Set FPC Rounding Mode + LD FPR0,0(,R3) Get short BFP dividend + LD FPR1,8(,R3) Get short BFP divisor + LZER FPR2 Zero remainder register + IC R1,D2IMODES-L'D2IMODES(R4) Get index DIEBR inst table + EX 0,DIDBRTAB(R1) Execute Divide to Integer + STD FPR0,16(,R7) Store short BFP remainder + STD FPR2,24(,R7) Store short BFP quotient + STFPC 4(R8) Store resulting FPCR flags and DXC + IPM R0 Retrieve condition code + SRL R0,28 Move CC to low-order r0, dump prog mask + STC R0,7(,R8) Store in last byte of FPCR +* + LA R7,32(,R7) Point to next quo&rem result value pair + LA R8,8(,R8) Point to next FPCR result area +* + BCTR R4,R6 Iterate inner loop +* +* End of M4 modes to be tested. +* + BCTR R5,R9 Iterate outer loop +* +* End of FPC modes to be tested with each M4 mode. Advance to +* next test case. +* + LA R3,16(,R3) Point to next input value pair + BCTR R2,R12 Divide next input value lots of times +* + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Tables and indices used to exhaustively test remainder and quotient +* rounding modes. +* +* The Execute instruction with an appropriate index * is used to +* execute the correct DIEBR/DIDBR instruction. Because * the quotient +* rounding mode is encoded in the DIxBR instruction in the wrong place +* to use Execute to dynamically modify the rounding mode, we will just +* use it to select the correct instruction. +* +* The Set BFP Rounding Mode does allow specification of the FPC +* rounding mode as an address, so we shall index into a table of +* BFP rounding modes without bothering with Execute. +* +*********************************************************************** + SPACE 2 +* +* Rounding modes that may be set in the FPCR. The FPCR controls +* rounding of the quotient. The same table is used for both DIEBR +* and DIDBR instruction testing. +* +* These are indexed directly by the loop counter, which counts down. +* So the modes are listed in reverse order here. +* +FPCMODES DS 0C + DC AL1(7) RFS, Round for shorter precision + DC AL1(3) RM, Round to -infinity + DC AL1(2) RP, Round to +infinity + DC AL1(1) RZ, Round to zero +*** DC AL1(0) RNTE, Round to Nearest, ties to even +FPCMCT EQU *-FPCMODES Count of FPC Modes to be tested +* +* Table of indices into table of DIDBR/DIEBR instructions. The table +* is used for both DIDBR and DIEBR, with the table value being used +* as the index register of an Execute instruction that points to +* either the DIDBR or DIEBR instruction list. +* +* These are indexed directly by the loop counter, which counts down. +* So the instruction indices are listed in reverse order here. +* +D2IMODES DS 0C + DC AL1(6*4) RM, Round to -infinity + DC AL1(5*4) RP, Round to +infinity + DC AL1(4*4) RZ, Round to zero + DC AL1(3*4) RNTE, Round to Nearest, ties to even + DC AL1(2*4) RFS, Round for Shorter Precision + DC AL1(1*4) RNTA, Round to Nearest, ties away +*** DC AL1(0*4) Use FPCR rounding mode +D2IMCT EQU *-D2IMODES Count of M4 Modes to be tested +* +* List of DIEBR instructions, each with a different rounding mode. +* These are Execute'd by the rounding mode test routing using an index +* obtained from the D2IMODES table above. +* +* This table and the DIDBRTAB table below should remain in the same +* sequence, or you'll be scratching your head keeping the result order +* straight between short and long results. +* +DIEBRTAB DS 0F Table of DIEBR instructions + DIEBR FPR0,FPR2,FPR1,0 Div to Int FPR0/FPR1, M4=use FPCR +* Above is not used + DIEBR FPR0,FPR2,FPR1,1 Div to Int FPR0/FPR1, M4=RNTA + DIEBR FPR0,FPR2,FPR1,3 Div to Int FPR0/FPR1, M4=RFS + DIEBR FPR0,FPR2,FPR1,4 Div to Int FPR0/FPR1, M4=RNTE + DIEBR FPR0,FPR2,FPR1,5 Div to Int FPR0/FPR1, M4=RZ + DIEBR FPR0,FPR2,FPR1,6 Div to Int FPR0/FPR1, M4=RP + DIEBR FPR0,FPR2,FPR1,7 Div to Int FPR0/FPR1, M4=RM +* +* List of DIDBR instructions, each with a different rounding mode. +* These are Execute'd by the rounding mode test routing using an index +* obtained from the D2IMODES table above. +* +* This table and the DIEBRTAB table above should remain in the same +* sequence, or you'll be scratching your head keeping the result order +* straight between short and long results. +* +DIDBRTAB DS 0F Table of DIDBR instructions + DIDBR FPR0,FPR2,FPR1,0 Div to Int FPR0/FPR1, M4=use FPCR +* Above is not used + DIDBR FPR0,FPR2,FPR1,1 Div to Int FPR0/FPR1, M4=RNTA + DIDBR FPR0,FPR2,FPR1,3 Div to Int FPR0/FPR1, M4=RFS + DIDBR FPR0,FPR2,FPR1,4 Div to Int FPR0/FPR1, M4=RNTE + DIDBR FPR0,FPR2,FPR1,5 Div to Int FPR0/FPR1, M4=RZ + DIDBR FPR0,FPR2,FPR1,6 Div to Int FPR0/FPR1, M4=RP + DIDBR FPR0,FPR2,FPR1,7 Div to Int FPR0/FPR1, M4=RM +* + EJECT +*********************************************************************** +* +* Short integer test data sets for Divide to Integer testing. +* +* Each test data set member consists of two values, the dividend and +* the divisor, in that order. +* +* The first test data set is used for tests of basic functionality, +* NaN propagation, and results from operations involving other than +* finite numbers. +* +* The secondd test data set is used for testing boundary conditions +* using two finite non-zero values. Each possible condition code +* and type of result (normal, scaled, etc) is created by members of +* this test data set. +* +* The third test data set is used for exhaustive testing of final +* results across the panoply of rounding mode combinations available +* for Divide to Integer (five for the remainder, seven for the +* quotient). +* +*********************************************************************** + SPACE 2 +* +* First input test data set, to test operations using non-finite or +* zero inputs. Member values chosen to validate part 1 of Figure 19-21 +* on page 19-29 of SA22-7832-10. +* +SBFPNFIN DS 0F Inputs for short BFP non-finite tests +* +* NaN propagation tests (Tests 1-4) +* + DC X'7F8A0000' SNaN + DC X'7F8B0000' SNaN +* + DC X'7FCA0000' QNaN + DC X'7FCB0000' QNaN +* + DC X'40000000' Finite number + DC X'7FCB0000' QNaN +* + DC X'7FCA0000' QNaN + DC X'7F8B0000' SNaN +* +* Dividend is -inf (Tests 5-10) +* + DC X'FF800000' -inf + DC X'FF800000' -inf +* + DC X'FF800000' -inf + DC X'C0000000' -2.0 +* + DC X'FF800000' -inf + DC X'80000000' -0 +* + DC X'FF800000' -inf + DC X'00000000' +0 +* + DC X'FF800000' -inf + DC X'40000000' +2.0 +* + DC X'FF800000' -inf + DC X'7F800000' +inf +* +* Dividend is +inf (Tests 11-16) +* + DC X'7F800000' +inf + DC X'FF800000' -inf +* + DC X'7F800000' +inf + DC X'C0000000' -2.0 +* + DC X'7F800000' +inf + DC X'80000000' -0 +* + DC X'7F800000' +inf + DC X'00000000' +0 +* + DC X'7F800000' +inf + DC X'40000000' +2.0 +* + DC X'7F800000' +inf + DC X'7F800000' +inf +* +* Divisor is -0. (+/-inf dividend tested above) +* (Tests 17-20) +* + DC X'C0000000' -2.0 + DC X'80000000' -0 +* + DC X'80000000' -0 + DC X'80000000' -0 +* + DC X'00000000' +0 + DC X'80000000' -0 +* + DC X'40000000' +2.0 + DC X'80000000' -0 +* +* Divisor is +0. (+/-inf dividend tested above) +* (Tests 21-24) +* + DC X'C0000000' -2.0 + DC X'00000000' +0 +* + DC X'80000000' -0 + DC X'00000000' +0 +* + DC X'00000000' +0 + DC X'00000000' +0 +* + DC X'40000000' +2.0 + DC X'00000000' +0 +* +* Divisor is -inf. (+/-inf dividend tested above) +* (Tests 25-28) +* + DC X'C0000000' -2.0 + DC X'FF800000' -inf +* + DC X'80000000' -0 + DC X'FF800000' -inf +* + DC X'00000000' +0 + DC X'FF800000' -inf +* + DC X'40000000' +2.0 + DC X'FF800000' -inf +* +* Divisor is +inf. (+/-inf dividend tested above) +* (Tests 29-32) +* + DC X'C0000000' -2.0 + DC X'7F800000' +inf +* + DC X'80000000' -0 + DC X'7F800000' +inf +* + DC X'00000000' +0 + DC X'7F800000' +inf +* + DC X'40000000' +2.0 + DC X'7F800000' +inf +* +SBFPNFCT EQU (*-SBFPNFIN)4/2 Count of short BFP in list + SPACE 3 +*********************************************************************** +* +* Second input test data set. These are finite pairs intended to +* test all combinations of finite values and results (final +* results due to remainder zero, final results due to quotient +* within range, and partial results. +* +*********************************************************************** + SPACE 2 +SBFPIN DS 0F Inputs for short BFP finite tests +* +* Dividend and Divisor are both finite numbers. +* +* Remainder tests from SA22-7832-10, Figure 19-7 on page 19-6 +* (Finite tests 1-16; negative divisor) +* + DC X'C1000000' -8 + DC X'C0800000' -4 +* + DC X'C0E00000' -7 + DC X'C0800000' -4 +* + DC X'C0C00000' -6 + DC X'C0800000' -4 +* + DC X'C0A00000' -5 + DC X'C0800000' -4 +* + DC X'C0800000' -4 + DC X'C0800000' -4 +* + DC X'C0400000' -3 + DC X'C0800000' -4 +* + DC X'C0000000' -2 + DC X'C0800000' -4 +* + DC X'BF800000' -1 + DC X'C0800000' -4 +* +* The +/- zero - +/- zero cases are handled above and skipped here +* + DC X'3F800000' +1 + DC X'C0800000' -4 +* + DC X'40000000' +2 + DC X'C0800000' -4 +* + DC X'40400000' +3 + DC X'C0800000' -4 +* + DC X'40800000' +4 + DC X'C0800000' -4 +* + DC X'40A00000' +5 + DC X'C0800000' -4 +* + DC X'40C00000' +6 + DC X'C0800000' -4 +* + DC X'40E00000' +7 + DC X'C0800000' -4 +* + DC X'41000000' +8 + DC X'C0800000' -4 +* +* Finite tests 17-32; positive divisor +* + DC X'C1000000' -8 + DC X'40800000' +4 +* + DC X'C0E00000' -7 + DC X'40800000' +4 +* + DC X'C0C00000' -6 + DC X'40800000' +4 +* + DC X'C0A00000' -5 + DC X'40800000' +4 +* + DC X'C0800000' -4 + DC X'40800000' +4 +* + DC X'C0400000' -3 + DC X'40800000' +4 +* + DC X'C0000000' -2 + DC X'40800000' +4 +* + DC X'3F800000' -1 + DC X'40800000' +4 +* + DC X'3F800000' +1 + DC X'40800000' +4 +* + DC X'40000000' +2 + DC X'40800000' +4 +* + DC X'40400000' +3 + DC X'40800000' +4 +* + DC X'40800000' +4 + DC X'40800000' +4 +* + DC X'40A00000' +5 + DC X'40800000' +4 +* + DC X'40C00000' +6 + DC X'40800000' +4 +* + DC X'40E00000' +7 + DC X'40800000' +4 +* + DC X'41000000' +8 + DC X'40800000' +4 +* +* Finite value boundary condition tests +* Tests 17-22 +* + DC X'42200000' +40.0 + DC X'C1100000' -9.0 +* +* Following forces quotient overflow, remainder zero. +* Final result, scaled quotient, cc1 + DC X'7F7FFFFF' +maxvalue + DC X'00000001' +minvalue (tiny) +* + DC X'00FFFFFF' near +minvalue normal + DC X'00FFFFFE' almost above +* +* Following forces partial results without quotient overflow +* Partial result, scaled quotient, normal remainder, cc2 + DC X'4C800000' +2^26th + DC X'40400000' +3.0 +* Expected results from above case: remainder < 3, quotient mismatch +* z12 actual results: remainder 4, quotient match. +* +* Following forces zero quotient, remainder = divisor. +* + DC X'40100000' +2.25 + DC X'41200000' +10 +* +* Following five tests force quotient overflow. Four have non-zero +* Remainder. All five return partial results. +* +* Note: +minvalue+11 is the smallest divisor that generates a +* remainder. +* + DC X'7F7FFFFF' +maxvalue + DC X'0000000B' +minvalue + 11 (tiny) +* + DC X'7F7FFFFE' +maxvalue + DC X'0000000A' +minvalue + 11 (tiny) +* + DC X'7F7FFFFF' +maxvalue + DC X'0000000C' +minvalue + 11 (tiny) +* + DC X'7F7FFFFF' +maxvalue + DC X'00000013' +minvalue + 11 (tiny) +* + DC X'7F7FFFFF' +maxvalue + DC X'3F000000' +0.5 +* + DC X'40400000' +3 + DC X'40000000' +2 +* +SBFPCT EQU (*-SBFPIN)/4/2 Count of short BFP in list + SPACE 3 +*********************************************************************** +* +* Third input test data set. These are finite pairs intended to +* test all combinations of rounding mode for the quotient and the +* remainder. +* +* The quotient/remainder pairs are for Round to Nearest, Ties to Even. +* Other rounding modes have different results. +* +*********************************************************************** + SPACE 2 +SBFPINRM DS 0F Inputs for short BFP rounding testing + DC X'C1980000' -19 / 0.5 = -9.5, -9 rem +1 + DC X'40000000' ...+2.0 + DC X'C1300000' -11 / 0.5 = -5.5, -5 rem +1 + DC X'40000000' ...+2.0 + DC X'C0A00000' -5 / 0.5 = -2.5 + DC X'40000000' ...+2.0 + DC X'C0400000' -3 / 0.5 = -1.5 + DC X'40000000' ...+2.0 + DC X'BF800000' -1 / 0.5 = -0.5 + DC X'40000000' ...+2.0 + DC X'3F800000' +1 / 0.5 = +0.5 + DC X'40000000' ...+2.0 + DC X'40400000' +3 / 0.5 = +1.5 + DC X'40000000' ...+2.0 + DC X'40A00000' +5 / 0.5 = +2.5 + DC X'40000000' ...+2.0 + DC X'41300000' +11 / 0.5 = +5.5 + DC X'40000000' ...+2.0 + DC X'41980000' +19 / 0.5 = +9.5 + DC X'40000000' ...+2.0 + DC X'40000000' 2 / 2 = 1 + DC X'40000000' ...+2.0 + DC X'40400000' +3 / 5 = +0.6, 0 rem 3 + DC X'40A00000' ...+5.0 +SBFPRMCT EQU (*-SBFPINRM)/4/2 Count of short BFP rounding tests + EJECT +*********************************************************************** +* +* Long integer test data sets for Divide to Integer testing. +* +* Each test data set member consists of two values, the dividend and +* the divisor, in that order. +* +* The first test data set is used for tests of basic functionality, +* NaN propagation, and results from operations involving other than +* finite numbers. +* +* The secondd test data set is used for testing boundary conditions +* using two finite non-zero values. Each possible condition code +* and type of result (normal, scaled, etc) is created by members of +* this test data set. +* +* The third test data set is used for exhaustive testing of final +* results across the panoply of rounding mode combinations available +* for Divide to Integer (five for the remainder, seven for the +* quotient). +* +*********************************************************************** +* +LBFPNFIN DS 0F Inputs for long BFP testing +* +* NaN propagation tests +* + DC X'7FF0A00000000000' SNaN + DC X'7FF0B00000000000' SNaN +* + DC X'7FF8A00000000000' QNaN + DC X'7FF8B00000000000' QNaN +* + DC X'4000000000000000' Finite number + DC X'7FF8B00000000000' QNaN +* + DC X'7FF8A00000000000' QNaN + DC X'7FF0B00000000000' SNaN +* +* Dividend is -inf +* + DC X'FFF0000000000000' -inf + DC X'FFF0000000000000' -inf +* + DC X'FFF0000000000000' -inf + DC X'C000000000000000' -2.0 +* + DC X'FFF0000000000000' -inf + DC X'8000000000000000' -0 +* + DC X'FFF0000000000000' -inf + DC X'0000000000000000' +0 +* + DC X'FFF0000000000000' -inf + DC X'4000000000000000' +2.0 +* + DC X'FFF0000000000000' -inf + DC X'7FF0000000000000' +inf +* +* Dividend is +inf +* + DC X'7FF0000000000000' +inf + DC X'FFF0000000000000' -inf +* + DC X'7FF0000000000000' +inf + DC X'C000000000000000' -2.0 +* + DC X'7FF0000000000000' +inf + DC X'8000000000000000' -0 +* + DC X'7FF0000000000000' +inf + DC X'0000000000000000' +0 +* + DC X'7FF0000000000000' +inf + DC X'4000000000000000' +2.0 +* + DC X'7FF0000000000000' +inf + DC X'7FF0000000000000' +inf +* +* Divisor is -0. (+/-inf dividend tested above) +* + DC X'C000000000000000' -2.0 + DC X'8000000000000000' -0 +* + DC X'8000000000000000' -0 + DC X'8000000000000000' -0 +* + DC X'0000000000000000' +0 + DC X'8000000000000000' -0 +* + DC X'4000000000000000' +2.0 + DC X'8000000000000000' -0 +* +* Divisor is +0. (+/-inf dividend tested above) +* + DC X'C000000000000000' -2.0 + DC X'0000000000000000' +0 +* + DC X'8000000000000000' -0 + DC X'0000000000000000' +0 +* + DC X'0000000000000000' +0 + DC X'0000000000000000' +0 +* + DC X'4000000000000000' +2.0 + DC X'0000000000000000' +0 +* +* Divisor is -inf. (+/-inf dividend tested above) +* + DC X'C000000000000000' -2.0 + DC X'FFF0000000000000' -inf +* + DC X'8000000000000000' -0 + DC X'FFF0000000000000' -inf +* + DC X'0000000000000000' +0 + DC X'FFF0000000000000' -inf +* + DC X'4000000000000000' +2.0 + DC X'FFF0000000000000' -inf +* +* Divisor is +inf. (+/-inf dividend tested above) +* + DC X'C000000000000000' -2.0 + DC X'7FF0000000000000' +inf +* + DC X'8000000000000000' -0 + DC X'7FF0000000000000' +inf +* + DC X'0000000000000000' +0 + DC X'7FF0000000000000' +inf +* + DC X'4000000000000000' +2.0 + DC X'7FF0000000000000' +inf +LBFPNFCT EQU (*-LBFPNFIN)/8/2 Count of long BFP in list + SPACE 3 +*********************************************************************** +* +* Second set of test inputs. These are finite pairs intended to +* test all combinations of finite values and results (final +* results due to remainder zero, final results due to quotient +* within range, and partial results. +* +*********************************************************************** + SPACE 2 +LBFPIN DS 0F Inputs for long BFP finite tests +* +* Dividend and Divisor are both finite numbers. +* +* Remainder tests from SA22-7832-10, Figure 19-7 on page 19-6 +* (Finite tests 1-32) +* + DC X'C020000000000000' -8 + DC X'C010000000000000' -4 +* + DC X'C01C000000000000' -7 + DC X'C010000000000000' -4 +* + DC X'C018000000000000' -6 + DC X'C010000000000000' -4 +* + DC X'C014000000000000' -5 + DC X'C010000000000000' -4 +* + DC X'C010000000000000' -4 + DC X'C010000000000000' -4 +* + DC X'C008000000000000' -3 + DC X'C010000000000000' -4 +* + DC X'C000000000000000' -2 + DC X'C010000000000000' -4 +* + DC X'BFF0000000000000' -1 + DC X'C010000000000000' -4 +* +* The +/- zero - +/- zero cases are handled above and skipped here +* + DC X'3FF0000000000000' +1 + DC X'C010000000000000' -4 +* + DC X'4000000000000000' +2 + DC X'C010000000000000' -4 +* + DC X'4008000000000000' +3 + DC X'C010000000000000' -4 +* + DC X'4010000000000000' +4 + DC X'C010000000000000' -4 +* + DC X'4014000000000000' +5 + DC X'C010000000000000' -4 +* + DC X'4018000000000000' +6 + DC X'C010000000000000' -4 +* + DC X'401C000000000000' +7 + DC X'C010000000000000' -4 +* + DC X'4020000000000000' +8 + DC X'C010000000000000' -4 +* + DC X'C020000000000000' -8 + DC X'4010000000000000' +4 +* + DC X'C01C000000000000' -7 + DC X'4010000000000000' +4 +* + DC X'C018000000000000' -6 + DC X'4010000000000000' +4 +* + DC X'C014000000000000' -5 + DC X'4010000000000000' +4 +* + DC X'C010000000000000' -4 + DC X'4010000000000000' +4 +* + DC X'C008000000000000' -3 + DC X'4010000000000000' +4 +* + DC X'C000000000000000' -2 + DC X'4010000000000000' +4 +* + DC X'3FF0000000000000' -1 + DC X'4010000000000000' +4 +* + DC X'3FF0000000000000' +1 + DC X'4010000000000000' +4 +* + DC X'4000000000000000' +2 + DC X'4010000000000000' +4 +* + DC X'4008000000000000' +3 + DC X'4010000000000000' +4 +* + DC X'4010000000000000' +4 + DC X'4010000000000000' +4 +* + DC X'4014000000000000' +5 + DC X'4010000000000000' +4 +* + DC X'4018000000000000' +6 + DC X'4010000000000000' +4 +* + DC X'401C000000000000' +7 + DC X'4010000000000000' +4 +* + DC X'4020000000000000' +8 + DC X'4010000000000000' +4 +** +* Dividend and Divisor are both finite numbers. +* (Tests 33-38) +* + DC X'4044000000000000' +40.0 + DC X'C022000000000000' -9.0 +* +* Following forces quotient overflow, remainder zero. +* Final result, scaled quotient, cc1 + DC X'7FEFFFFFFFFFFFFF' +maxvalue + DC X'0000000000000001' +minvalue (tiny) +* +* Following forces quotient overflow, remainder non-zero. +* Partial result, scaled quotient, tiny remainder, cc3 +* Note: +minvalue+2 is the smallest divisor that +* generates a non-zero remainder. + DC X'7FEFFFFFFFFFFFFF' +maxvalue + DC X'0000000000000003' +minvalue (tiny) +* + DC X'000FFFFFFFFFFFFF' near +minvalue normal + DC X'000FFFFFFFFFFFFE' almost above +* +* Following forces partial results without quotient overflow +* Partial result, scaled quotient, normal remainder, cc2 + DC X'4370000000000000' +2^56th + DC X'4008000000000000' +3.0 +* Expected results from above case: remainder < 3, quotient mismatch +* z12 actual results: remainder 4, quotient match. +* +* Following forces zero quotient, remainder = divisor. +* + DC X'4002000000000000' +2.25 + DC X'4024000000000000' +10 +* +LBFPCT EQU (*-LBFPIN)/8/2 Count of long BFP in list + SPACE 3 +*********************************************************************** +* +* Third input test data set. These are finite pairs intended to +* test all combinations of rounding mode for the quotient and the +* remainder. +* +* The quotient/remainder pairs are for Round to Nearest, Ties to Even. +* Other rounding modes have different results. +* +*********************************************************************** + SPACE 2 +LBFPINRM DS 0F + DC X'C023000000000000' -9.5, -9 rem 1 + DC X'4000000000000000' +2 +* + DC X'C016000000000000' -5.5 + DC X'4000000000000000' +2 +* + DC X'C004000000000000' -2.5 + DC X'4000000000000000' +2 +* + DC X'BFF8000000000000' -1.5 + DC X'4000000000000000' +2 +* + DC X'BFE0000000000000' -0.5 + DC X'4000000000000000' +2 +* + DC X'3FE0000000000000' +0.5 + DC X'4000000000000000' +2 +* + DC X'3FF8000000000000' +1.5 + DC X'4000000000000000' +2 +* + DC X'4004000000000000' +2.5 + DC X'4000000000000000' +2 +* + DC X'4016000000000000' +5.5 + DC X'4000000000000000' +2 +* + DC X'4023000000000000' +9.5 + DC X'4000000000000000' +2 +* + DC X'4000000000000000' +2 + DC X'4000000000000000' +2 +* + DC X'4008000000000000' +3 + DC X'4014000000000000' +5 +* +LBFPRMCT EQU (*-LBFPINRM)/8/2 Count of long BFP rounding tests +* +* +* Locations for results +* +SBFPNFOT EQU STRTLABL+X'1000' Integer short non-finite BFP results +* ..room for 32 tests, 32 used +SBFPNFFL EQU STRTLABL+X'1200' FPCR flags and DXC from short BFP +* ..room for 32 tests, 32 used +* +LBFPNFOT EQU STRTLABL+X'1300' Integer long non-finite BFP results +* ..room for 32 tests, 32 used +LBFPNFFL EQU STRTLABL+X'1700' FPCR flags and DXC from long BFP +* ..room for 32 tests, 32 used +* +SBFPRMO EQU STRTLABL+X'2000' Short BFP rounding mode test results +* ..Room for 20, 10 used. +SBFPRMOF EQU STRTLABL+X'4000' Short BFP rounding mode FPCR results +* ..Room for 20, 10 used. +* +LBFPRMO EQU STRTLABL+X'5000' Long BFP rounding mode test results +* ..Room for 20, 10 used. +LBFPRMOF EQU STRTLABL+X'9000' Long BFP rounding mode FPCR results +* ..Room for 20, 10 used. +* +SBFPOUT EQU STRTLABL+X'A000' Integer short BFP finite results +* ..room for 64 tests, 38 used +SBFPFLGS EQU STRTLABL+X'A800' FPCR flags and DXC from short BFP +* ..room for 64 tests, 6 used +* +LBFPOUT EQU STRTLABL+X'B000' Integer long BFP finite results +* ..room for 64 tests, 6 used +LBFPFLGS EQU STRTLABL+X'AC00' FPCR flags and DXC from long BFP +* ..room for 64 tests, 6 used +* +* +ENDLABL EQU STRTLABL+X'C000' + PADCSECT ENDLABL + END diff --git a/tests/bfp-001-divtoint.core b/tests/bfp-001-divtoint.core new file mode 100644 index 000000000..18e6ae6e1 Binary files /dev/null and b/tests/bfp-001-divtoint.core differ diff --git a/tests/bfp-001-divtoint.list b/tests/bfp-001-divtoint.list new file mode 100644 index 000000000..de70db3cc --- /dev/null +++ b/tests/bfp-001-divtoint.list @@ -0,0 +1,1781 @@ +ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 1 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 2 *********************************************************************** + 3 * + 4 *Testcase IEEE DIVIDE TO INTEGER + 5 * Test case capability includes IEEE exceptions trappable and + 6 * otherwise. Test results, FPCR flags, and any DXC are saved for all + 7 * tests. + 8 * + 9 *********************************************************************** + + + 11 *********************************************************************** + 12 * + 13 * Tests the following three conversion instructions + 14 * DIVIDE TO INTEGER (short BFP, RRE) + 15 * DIVIDE TO INTEGER (long BFP, RRE) + 16 * + 17 * Test data is compiled into this program. The test script that runs + 18 * this program can provide alternative test data through Hercules R + 19 * commands. + 20 * + 21 * Test Case Order + 22 * 1) Short BFP basic tests, including traps and NaN propagation + 23 * 2) Short BFP finite number tests, incl. partial and final results + 24 * 3) Short BFP rounding, tests of quotient and remainder rounding + 25 * 4) Long BFP basic tests, including traps and NaN propagation + 26 * 5) Long BFP finite number tests, incl. partial and final results + 27 * 6) Short BFP rounding, tests of quotient and remainder rounding + 28 * + 29 * Three input test sets are provided each for short and long + 30 * BFP inputs. Test values are conceptually the same for each + 31 * precision, but the values differ between precisions. Overflow, + 32 * for example, is triggered by different values in short and long, + 33 * but each test set includes overflow tests. + 34 * + 35 * Also tests the following floating point support instructions + 36 * LOAD (Short) + 37 * LOAD (Long) + 38 * LFPC (Load Floating Point Control Register) + 39 * SRNMB (Set BFP Rounding Mode 2-bit) + 40 * SRNMB (Set BFP Rounding Mode 3-bit) + 41 * STORE (Short) + 42 * STORE (Long) + 43 * STFPC (Store Floating Point Control Register) + 44 * + 45 *********************************************************************** + + + 47 MACRO + 48 PADCSECT &ENDLABL + 49 .* + 50 .* Macro to pad the CSECT to include result data areas if this test + 51 .* program is not being assembled using asma. asma generates a core + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 2 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 52 .* image that is loaded by the loadcore command, and because the + 53 .* core image is a binary stored in Github, it makes sense to make + 54 .* this small effort to keep the core image small. + 55 .* + 56 AIF (D'&ENDLABL).GOODPAD + 57 MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + 58 MNOTE *,'No CSECT padding performed' + 59 MEXIT + 60 .* + 61 .GOODPAD ANOP Label valid. See if we're on asma + 62 AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + 63 ORG &ENDLABL-1 Not ASMA. Pad CSECT + 64 MEXIT + 65 .* + 66 .NOPAD ANOP + 67 MNOTE *,'asma detected; no CSECT padding performed' + 68 MEND + 69 * + 70 * Note: for compatibility with the z/CMS test rig, do not change + 71 * or use R11, R14, or R15. Everything else is fair game. + 72 * + 0000000000000000 0000000000000F13 73 BFPDV2NT START 0 + 0000000000000000 0000000000000001 74 R0 EQU 0 Work register for cc extraction + 0000000000000001 0000000000000001 75 R1 EQU 1 + 0000000000000002 0000000000000001 76 R2 EQU 2 Holds count of test input values + 0000000000000003 0000000000000001 77 R3 EQU 3 Points to next test input value(s) + 0000000000000004 0000000000000001 78 R4 EQU 4 Rounding tests inner loop control + 0000000000000005 0000000000000001 79 R5 EQU 5 Rounding tests outer loop control + 0000000000000006 0000000000000001 80 R6 EQU 6 Rounding tests top of inner loop + 0000000000000007 0000000000000001 81 R7 EQU 7 Pointer to next result value(s) + 0000000000000008 0000000000000001 82 R8 EQU 8 Pointer to next FPCR result + 0000000000000009 0000000000000001 83 R9 EQU 9 Rounding tests top of outer loop + 000000000000000A 0000000000000001 84 R10 EQU 10 Pointer to test address list + 000000000000000B 0000000000000001 85 R11 EQU 11 **Reserved for z/CMS test rig + 000000000000000C 0000000000000001 86 R12 EQU 12 Holds number of test cases in set + 000000000000000D 0000000000000001 87 R13 EQU 13 Mainline return address + 000000000000000E 0000000000000001 88 R14 EQU 14 **Return address for z/CMS test rig + 000000000000000F 0000000000000001 89 R15 EQU 15 **Base register on z/CMS or Hyperion + 90 * + 91 * Floating Point Register equates to keep the cross reference clean + 92 * + 0000000000000000 0000000000000001 93 FPR0 EQU 0 + 0000000000000001 0000000000000001 94 FPR1 EQU 1 + 0000000000000002 0000000000000001 95 FPR2 EQU 2 + 0000000000000003 0000000000000001 96 FPR3 EQU 3 + 0000000000000004 0000000000000001 97 FPR4 EQU 4 + 0000000000000005 0000000000000001 98 FPR5 EQU 5 + 0000000000000006 0000000000000001 99 FPR6 EQU 6 + 0000000000000007 0000000000000001 100 FPR7 EQU 7 + 0000000000000008 0000000000000001 101 FPR8 EQU 8 + 0000000000000009 0000000000000001 102 FPR9 EQU 9 + 000000000000000A 0000000000000001 103 FPR10 EQU 10 + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 3 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 000000000000000B 0000000000000001 104 FPR11 EQU 11 + 000000000000000C 0000000000000001 105 FPR12 EQU 12 + 000000000000000D 0000000000000001 106 FPR13 EQU 13 + 000000000000000E 0000000000000001 107 FPR14 EQU 14 + 000000000000000F 0000000000000001 108 FPR15 EQU 15 + 109 * +0000000000000000 0000000000000000 110 USING *,R15 + 111 * + 112 * Above works on real iron (R15=0 after sysclear) + 113 * and in z/CMS (R15 points to start of load module) + 114 * + + + 116 *********************************************************************** + 117 * + 118 * Low core definitions, Restart PSW, and Program Check Routine. + 119 * + 120 *********************************************************************** + + +0000000000000000 0000000000000000 000000000000008E 122 ORG BFPDV2NT+X'8E' Program check interrution code +000000000000008E 0000 123 PCINTCD DS H + 124 * + 0000000000000150 0000000000000000 125 PCOLDPSW EQU BFPDV2NT+X'150' z/Arch Program check old PSW + 126 * +0000000000000090 0000000000000090 00000000000001A0 127 ORG BFPDV2NT+X'1A0' z/Arch Restart PSW +00000000000001A0 00000001 80000000 128 DC X'0000000180000000',AD(START) + 129 * +00000000000001B0 00000000000001B0 00000000000001D0 130 ORG BFPDV2NT+X'1D0' z/Arch Program check old PSW +00000000000001D0 00000000 00000000 131 DC X'0000000000000000',AD(PROGCHK) + 132 * + 133 * Program check routine. If Data Exception, continue execution at + 134 * the instruction following the program check. Otherwise, hard wait. + 135 * No need to collect data. All interesting DXC stuff is captured + 136 * in the FPCR. + 137 * +00000000000001E0 00000000000001E0 0000000000000200 138 ORG BFPDV2NT+X'200' +0000000000000200 139 PROGCHK DS 0H Program check occured... +0000000000000200 9507 F08F 000000000000008F 140 CLI PCINTCD+1,X'07' Data Exception? +0000000000000204 A774 0004 000000000000020C 141 JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) +0000000000000208 B2B2 F150 0000000000000150 142 LPSWE PCOLDPSW ..yes, resume program execution +000000000000020C 143 PCNOTDTA DS 0H +000000000000020C 12EE 144 LTR R14,R14 Return address provided? +000000000000020E 077E 145 BNZR R14 Yes, return to z/CMS test rig. +0000000000000210 B2B2 F268 0000000000000268 146 LPSWE HARDWAIT Not data exception, enter disabled wait + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 4 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 148 *********************************************************************** + 149 * + 150 * Main program. Enable Advanced Floating Point, process test cases. + 151 * + 152 *********************************************************************** + + +0000000000000214 154 START DS 0H +0000000000000214 B600 F278 0000000000000278 155 STCTL R0,R0,CTLR0 Store CR0 to enable AFP +0000000000000218 9604 F279 0000000000000279 156 OI CTLR0+1,X'04' Turn on AFP bit +000000000000021C B700 F278 0000000000000278 157 LCTL R0,R0,CTLR0 Reload updated CR0 + 158 * +0000000000000220 41A0 F300 0000000000000300 159 LA R10,SHORTNF Point to short BFP non-finite inputs +0000000000000224 4DD0 F360 0000000000000360 160 BAS R13,DIEBRNF Divide to Integer short BFP non-finite +0000000000000228 41A0 F310 0000000000000310 161 LA R10,SHORTF Point to short BFP finite inputs +000000000000022C 4DD0 F3D6 00000000000003D6 162 BAS R13,DIEBRF Divide to Integer short BFP finites +0000000000000230 41A0 F320 0000000000000320 163 LA R10,RMSHORTS Point to short BFP rounding mode tests +0000000000000234 4DD0 F484 0000000000000484 164 BAS R13,DIEBRRM Convert using all rounding mode options + 165 * +0000000000000238 41A0 F330 0000000000000330 166 LA R10,LONGNF Point to long BFP non-finite inputs +000000000000023C 4DD0 F528 0000000000000528 167 BAS R13,DIDBRNF Divide to Integer long BFP basic +0000000000000240 41A0 F340 0000000000000340 168 LA R10,LONGF Point to long BFP finite inputs +0000000000000244 4DD0 F59E 000000000000059E 169 BAS R13,DIDBRF Divide to Integer long BFP basic +0000000000000248 41A0 F350 0000000000000350 170 LA R10,RMLONGS Point to long BFP rounding mode tests +000000000000024C 4DD0 F64C 000000000000064C 171 BAS R13,DIDBRRM Convert using all rounding mode options + 172 * +0000000000000250 12EE 173 LTR R14,R14 Return address provided? +0000000000000252 077E 174 BNZR R14 ..Yes, return to z/CMS test rig. +0000000000000254 B2B2 F258 0000000000000258 175 LPSWE WAITPSW All done + 176 * +0000000000000258 177 DS 0D Ensure correct alignment for psw +0000000000000258 00020000 00000000 178 WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +0000000000000268 00020000 00000000 179 HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end + 180 * +0000000000000278 00000000 181 CTLR0 DS F +000000000000027C 00000000 182 FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +0000000000000280 F8000000 183 FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags + 184 * + 185 * Input values parameter list, four fullwords for each test data set + 186 * 1) Count, + 187 * 2) Address of inputs, + 188 * 3) Address to place results, and + 189 * 4) Address to place DXC/Flags/cc values. + 190 * +0000000000000284 0000000000000284 0000000000000300 191 ORG BFPDV2NT+X'300' Enable run-time replacement +0000000000000300 192 SHORTNF DS 0F Input pairs for short BFP non-finite tests +0000000000000300 00000020 193 DC A(SBFPNFCT/4/2) +0000000000000304 0000073C 194 DC A(SBFPNFIN) +0000000000000308 00001000 195 DC A(SBFPNFOT) +000000000000030C 00001200 196 DC A(SBFPNFFL) + 197 * +0000000000000310 198 SHORTF DS 0F Input pairs for short BFP finite tests + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 5 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000310 0000002B 199 DC A(SBFPCT/4/2) +0000000000000314 0000083C 200 DC A(SBFPIN) +0000000000000318 0000A000 201 DC A(SBFPOUT) +000000000000031C 0000A800 202 DC A(SBFPFLGS) + 203 * +0000000000000320 204 RMSHORTS DS 0F Input pairs for short BFP finite testing +0000000000000320 0000000C 205 DC A(SBFPRMCT/4/2) +0000000000000324 00000994 206 DC A(SBFPINRM) +0000000000000328 00002000 207 DC A(SBFPRMO) +000000000000032C 00004000 208 DC A(SBFPRMOF) + 209 * +0000000000000330 210 LONGNF DS 0F Input pairs for long BFP non-finite testing +0000000000000330 00000020 211 DC A(LBFPNFCT/8/2) +0000000000000334 000009F4 212 DC A(LBFPNFIN) +0000000000000338 00001300 213 DC A(LBFPNFOT) +000000000000033C 00001700 214 DC A(LBFPNFFL) + 215 * +0000000000000340 216 LONGF DS 0F Input pairs for long BFP finite testing +0000000000000340 00000026 217 DC A(LBFPCT/8/2) +0000000000000344 00000BF4 218 DC A(LBFPIN) +0000000000000348 0000B000 219 DC A(LBFPOUT) +000000000000034C 0000AC00 220 DC A(LBFPFLGS) + 221 * +0000000000000350 222 RMLONGS DS 0F Input pairs for long BFP finite testing +0000000000000350 0000000C 223 DC A(LBFPRMCT/8/2) +0000000000000354 00000E54 224 DC A(LBFPINRM) +0000000000000358 00005000 225 DC A(LBFPRMO) +000000000000035C 00009000 226 DC A(LBFPRMOF) + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 6 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 228 *********************************************************************** + 229 * + 230 * Perform Divide to Integer using provided short BFP input pairs. This + 231 * set of tests checks NaN propagation and operations on values that are + 232 * not finite numbers. + 233 * + 234 * A pair of results is generated for each input: one with all + 235 * exceptions non-trappable, and the second with all exceptions + 236 * trappable. The FPCR and condition code is stored for each result. + 237 * + 238 *********************************************************************** + + +0000000000000360 240 DIEBRNF DS 0H BFP Short non-finite values tests +0000000000000360 9823 A000 0000000000000000 241 LM R2,R3,0(R10) Get count and address of test input values +0000000000000364 9878 A008 0000000000000008 242 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000368 1222 243 LTR R2,R2 Any test cases? +000000000000036A 078D 244 BZR R13 ..No, return to caller +000000000000036C 0DC0 245 BASR R12,0 Set top of loop + 246 * +000000000000036E B29D F27C 000000000000027C 247 LFPC FPCREGNT Set exceptions non-trappable +0000000000000372 7800 3000 0000000000000000 248 LE FPR0,0(,R3) Get short BFP dividend +0000000000000376 7810 3004 0000000000000004 249 LE FPR1,4(,R3) Get short BFP divisor +000000000000037A B374 0020 250 LZER FPR2 Zero remainder register +000000000000037E B353 2001 251 DIEBR FPR0,FPR2,FPR1,0 Div to Int FPR0/FPR1, M4=use FPCR + 252 * Quotient in FPR2, remainder in FPR0 +0000000000000382 7000 7000 0000000000000000 253 STE FPR0,0(,R7) Store short BFP remainder +0000000000000386 7020 7004 0000000000000004 254 STE FPR2,4(,R7) Store short BFP quotient +000000000000038A B29C 8000 0000000000000000 255 STFPC 0(R8) Store resulting FPCR flags and DXC +000000000000038E B222 0000 256 IPM R0 Retrieve condition code +0000000000000392 8800 001C 000000000000001C 257 SRL R0,28 Move CC to low-order r0, dump prog mask +0000000000000396 4200 8003 0000000000000003 258 STC R0,3(0,R8) Store in last byte of FPCR + 259 * +000000000000039A B29D F280 0000000000000280 260 LFPC FPCREGTR Set exceptions trappable +000000000000039E 7800 3000 0000000000000000 261 LE FPR0,0(,R3) Get short BFP dividend +00000000000003A2 7810 3004 0000000000000004 262 LE FPR1,4(,R3) Get short BFP divisor +00000000000003A6 B374 0020 263 LZER FPR2 Zero remainder register +00000000000003AA B353 2001 264 DIEBR FPR0,FPR2,FPR1,0 Div to Int FPR0/FPR1, M4=use FPCR + 265 * Quotient in FPR2, remainder in FPR0 +00000000000003AE 7000 7008 0000000000000008 266 STE FPR0,8(,R7) Store short BFP remainder +00000000000003B2 7020 700C 000000000000000C 267 STE FPR2,12(,R7) Store short BFP quotient +00000000000003B6 B29C 8004 0000000000000004 268 STFPC 4(R8) Store resulting FPCR flags and DXC +00000000000003BA B222 0000 269 IPM R0 Retrieve condition code +00000000000003BE 8800 001C 000000000000001C 270 SRL R0,28 Move CC to low-order r0, dump prog mask +00000000000003C2 4200 8007 0000000000000007 271 STC R0,7(,R8) Store in last byte of FPCR + 272 * +00000000000003C6 4130 3008 0000000000000008 273 LA R3,8(,R3) Point to next input value pair +00000000000003CA 4170 7010 0000000000000010 274 LA R7,16(,R7) Point to next quo&rem result value pair +00000000000003CE 4180 8008 0000000000000008 275 LA R8,8(,R8) Point to next FPCR result area +00000000000003D2 062C 276 BCTR R2,R12 Convert next input value. +00000000000003D4 07FD 277 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 7 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 279 *********************************************************************** + 280 * + 281 * Perform Divide to Integer using provided short BFP input pairs. This + 282 * set of tests performs basic checks of Divide To Integer emulation + 283 * where both inputs are finite non-zero numbers. + 284 * + 285 * Four results (six values) are generated for each input: + 286 * 1) Divide to integer with all exceptions non-trappable (two values) + 287 * 2) Multiply integer quotient by divisor, add remainder (one value) + 288 * 3) Divide to integerwith all exceptions trappable (two values) + 289 * 4) Multiply integer quotient by divisor, add remainder (one value) + 290 * + 291 * The FPCR and condition code is stored for each result. Note: the + 292 * Multiply and Add instruction does not set the condition code. + 293 * + 294 * Results two and four (multiply and add) validate the calculation + 295 * of the integer quotient and remainder. + 296 * + 297 *********************************************************************** + + +00000000000003D6 9823 A000 0000000000000000 299 DIEBRF LM R2,R3,0(R10) Get count and address of test input values +00000000000003DA 9878 A008 0000000000000008 300 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000003DE 1222 301 LTR R2,R2 Any test cases? +00000000000003E0 078D 302 BZR R13 ..No, return to caller +00000000000003E2 0DC0 303 BASR R12,0 Set top of loop + 304 * +00000000000003E4 B29D F27C 000000000000027C 305 LFPC FPCREGNT Set exceptions non-trappable +00000000000003E8 7800 3000 0000000000000000 306 LE FPR0,0(,R3) Get short BFP dividend +00000000000003EC 7810 3004 0000000000000004 307 LE FPR1,4(,R3) Get short BFP divisor +00000000000003F0 B374 0020 308 LZER FPR2 Zero remainder register +00000000000003F4 B353 2001 309 DIEBR FPR0,FPR2,FPR1,0 Div to Int FPR0/FPR1, M4=use FPCR + 310 * Quotient in FPR2, remainder in FPR0 +00000000000003F8 7000 7000 0000000000000000 311 STE FPR0,0(,R7) Store short BFP remainder +00000000000003FC 7020 7004 0000000000000004 312 STE FPR2,4(,R7) Store short BFP quotient +0000000000000400 B29C 8000 0000000000000000 313 STFPC 0(R8) Store resulting FPCR flags and DXC +0000000000000404 B222 0000 314 IPM R0 Retrieve condition code +0000000000000408 8800 001C 000000000000001C 315 SRL R0,28 Move CC to low-order r0, dump prog mask +000000000000040C 4200 8003 0000000000000003 316 STC R0,3(,R8) Store in last byte of FPCR + 317 * + 318 * FPR1 still has divisor, FPR0 has remainder, FPR2 has integer quotient + 319 * +0000000000000410 B29D F27C 000000000000027C 320 LFPC FPCREGNT Set exceptions non-trappable +0000000000000414 B30E 0021 321 MAEBR FPR0,FPR2,FPR1 Multiply and add to recreate inputs + 322 * Sum of product and remainder in FPR0 +0000000000000418 7000 7008 0000000000000008 323 STE FPR0,8(,R7) Store short BFP product-sum +000000000000041C B29C 8004 0000000000000004 324 STFPC 4(R8) Store resulting FPCR flags and DXC +0000000000000420 B222 0000 325 IPM R0 Retrieve condition code +0000000000000424 8800 001C 000000000000001C 326 SRL R0,28 Move CC to low-order r0, dump prog mask +0000000000000428 4200 8007 0000000000000007 327 STC R0,7(,R8) Store in last byte of FPCR + 328 * +000000000000042C B29D F280 0000000000000280 329 LFPC FPCREGTR Set exceptions trappable + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 8 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000430 7800 3000 0000000000000000 330 LE FPR0,0(,R3) Get short BFP dividend +0000000000000434 7810 3004 0000000000000004 331 LE FPR1,4(,R3) Get short BFP divisor +0000000000000438 B374 0020 332 LZER FPR2 Zero remainder register +000000000000043C B353 2001 333 DIEBR FPR0,FPR2,FPR1,0 Div to Int FPR0/FPR1, M4=use FPCR + 334 * Quotient in FPR2, remainder in FPR0 +0000000000000440 7000 7010 0000000000000010 335 STE FPR0,16(,R7) Store short BFP remainder +0000000000000444 7020 7014 0000000000000014 336 STE FPR2,20(,R7) Store short BFP quotient +0000000000000448 B29C 8008 0000000000000008 337 STFPC 8(R8) Store resulting FPCR flags and DXC +000000000000044C B222 0000 338 IPM R0 Retrieve condition code +0000000000000450 8800 001C 000000000000001C 339 SRL R0,28 Move CC to low-order r0, dump prog mask +0000000000000454 4200 800B 000000000000000B 340 STC R0,11(,R8) Store in last byte of FPCR + 341 * + 342 * FPR1 still has divisor, FPR0 has remainder, FPR2 has integer quotient + 343 * +0000000000000458 B29D F27C 000000000000027C 344 LFPC FPCREGNT Set exceptions non-trappable +000000000000045C B30E 0021 345 MAEBR FPR0,FPR2,FPR1 Multiply and add to recreate inputs + 346 * Sum of product and remainder in FPR0 +0000000000000460 7000 7018 0000000000000018 347 STE FPR0,24(,R7) Store short BFP remainder +0000000000000464 B29C 800C 000000000000000C 348 STFPC 12(R8) Store resulting FPCR flags and DXC +0000000000000468 B222 0000 349 IPM R0 Retrieve condition code +000000000000046C 8800 001C 000000000000001C 350 SRL R0,28 Move CC to low-order r0, dump prog mask +0000000000000470 4200 800F 000000000000000F 351 STC R0,15(,R8) Store in last byte of FPCR + 352 + 353 * +0000000000000474 4130 3008 0000000000000008 354 LA R3,8(,R3) Point to next input value pair +0000000000000478 4170 7020 0000000000000020 355 LA R7,32(,R7) Point to next quo&rem result value pair +000000000000047C 4180 8010 0000000000000010 356 LA R8,16(,R8) Point to next FPCR result area +0000000000000480 062C 357 BCTR R2,R12 Convert next input value. +0000000000000482 07FD 358 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 9 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 360 *********************************************************************** + 361 * + 362 * The next tests operate on finite number input pairs and exhastively + 363 * test rounding modes and partial and final results. + 364 * + 365 * Two rounding modes can be specified for each operation: one for the + 366 * quotient, specified in the M4 field, and the second for the + 367 * remainder, specified in the FPCR. + 368 * + 369 * Because six unique rounding modes can be specified in for the + 370 * quotient and four for the remainder, there are a lot of results that + 371 * need to be evaluated. Note: M4 rounding mode zero, use FPCR rounding + 372 * mode, is not tested because it duplicates one of the six explicit + 373 * M4 rounding modes. Which one depends on the current FPCR setting. + 374 * + 375 * The M4 rounding mode is assembled into the instruction. Back in the + 376 * day, this would be a perfect candidate for an Execute instructoin. + 377 * But the M4 field is not located such that it can be modified by + 378 * an Execute instruction. So we will still use Execute, but only to + 379 * select one of six DIEBR instructions for execution. That way we can + 380 * build an outer loop to iterate through the four FPCR modes, and an + 381 * inner loop to use each of the six M4-specified rounding modes. + 382 * + 383 *********************************************************************** + + +0000000000000484 9823 A000 0000000000000000 385 DIEBRRM LM R2,R3,0(R10) Get count and address of test input values +0000000000000488 9878 A008 0000000000000008 386 LM R7,R8,8(R10) Get address of result area and flag area. +000000000000048C 1222 387 LTR R2,R2 Any test cases? +000000000000048E 078D 388 BZR R13 ..No, return to caller +0000000000000490 1711 389 XR R1,R1 Zero register 1 for use in IC/STC/indexing +0000000000000492 0DC0 390 BASR R12,0 Set top of test case loop + 391 +0000000000000494 4150 0004 0000000000000004 392 LA R5,FPCMCT Get count of FPC modes to be tested +0000000000000498 0D90 393 BASR R9,0 Set top of rounding mode outer loop + 394 * + 395 * Update model FPC register settings with the BFP rounding mode for + 396 * this iteration of the loop. + 397 * +000000000000049A 4315 F6F7 00000000000006F7 398 IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode + 399 * +000000000000049E 4140 0006 0000000000000006 400 LA R4,D2IMCT Get count of M4 modes to be tested +00000000000004A2 0D60 401 BASR R6,0 Set top of rounding mode inner loop + 402 * + 403 * Non-trap execution of the instruction. + 404 * +00000000000004A4 B29D F27C 000000000000027C 405 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000004A8 4315 F6F7 00000000000006F7 406 IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode +00000000000004AC B2B8 1000 0000000000000000 407 SRNMB 0(R1) Set FPC Rounding Mode +00000000000004B0 7800 3000 0000000000000000 408 LE FPR0,0(,R3) Get short BFP dividend +00000000000004B4 7810 3004 0000000000000004 409 LE FPR1,4(,R3) Get short BFP divisor +00000000000004B8 B374 0020 410 LZER FPR2 Zero remainder register + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 10 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000004BC 4314 F6FB 00000000000006FB 411 IC R1,D2IMODES-L'D2IMODES(R4) Get index DIEBR inst table +00000000000004C0 4401 F704 0000000000000704 412 EX 0,DIEBRTAB(R1) Execute Divide to Integer +00000000000004C4 7000 7000 0000000000000000 413 STE FPR0,0(,R7) Store short BFP remainder +00000000000004C8 7020 7004 0000000000000004 414 STE FPR2,4(,R7) Store short BFP quotient +00000000000004CC B29C 8000 0000000000000000 415 STFPC 0(R8) Store resulting FPCR flags and DXC +00000000000004D0 B222 0000 416 IPM R0 Retrieve condition code +00000000000004D4 8800 001C 000000000000001C 417 SRL R0,28 Move CC to low-order r0, dump prog mask +00000000000004D8 4200 8003 0000000000000003 418 STC R0,3(,R8) Store in last byte of FPCR + 419 * + 420 * Trap-enabled execution of the instruction. + 421 * +00000000000004DC B29D F280 0000000000000280 422 LFPC FPCREGTR Set exceptions trappable, clear flags +00000000000004E0 4315 F6F7 00000000000006F7 423 IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode +00000000000004E4 B2B8 1000 0000000000000000 424 SRNMB 0(R1) Set FPC Rounding Mode +00000000000004E8 7800 3000 0000000000000000 425 LE FPR0,0(,R3) Get short BFP dividend +00000000000004EC 7810 3004 0000000000000004 426 LE FPR1,4(,R3) Get short BFP divisor +00000000000004F0 B374 0020 427 LZER FPR2 Zero remainder register +00000000000004F4 4314 F6FB 00000000000006FB 428 IC R1,D2IMODES-L'D2IMODES(R4) Get index DIEBR inst table +00000000000004F8 4401 F704 0000000000000704 429 EX 0,DIEBRTAB(R1) Execute Divide to Integer +00000000000004FC 7000 7008 0000000000000008 430 STE FPR0,8(,R7) Store short BFP remainder +0000000000000500 7020 700C 000000000000000C 431 STE FPR2,12(,R7) Store short BFP quotient +0000000000000504 B29C 8004 0000000000000004 432 STFPC 4(R8) Store resulting FPCR flags and DXC +0000000000000508 B222 0000 433 IPM R0 Retrieve condition code +000000000000050C 8800 001C 000000000000001C 434 SRL R0,28 Move CC to low-order r0, dump prog mask +0000000000000510 4200 8007 0000000000000007 435 STC R0,7(,R8) Store in last byte of FPCR + 436 * +0000000000000514 4170 7010 0000000000000010 437 LA R7,16(,R7) Point to next quo&rem result value pair +0000000000000518 4180 8008 0000000000000008 438 LA R8,8(,R8) Point to next FPCR result area + 439 * +000000000000051C 0646 440 BCTR R4,R6 Iterate inner loop + 441 * + 442 * End of M4 modes to be tested. + 443 * +000000000000051E 0659 444 BCTR R5,R9 Iterate outer loop + 445 * + 446 * End of FPC modes to be tested with each M4 mode. Advance to + 447 * next test case. + 448 * +0000000000000520 4130 3008 0000000000000008 449 LA R3,8(,R3) Point to next input value pair +0000000000000524 062C 450 BCTR R2,R12 Divide next input value lots of times + 451 * +0000000000000526 07FD 452 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 11 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 454 *********************************************************************** + 455 * + 456 * Perform Divide to Integer using provided long BFP input pairs. This + 457 * set of tests checks NaN propagation and operations on values that are + 458 * not finite numbers. + 459 * + 460 * A pair of results is generated for each input: one with all + 461 * exceptions non-trappable, and the second with all exceptions + 462 * trappable. The FPCR and condition code is stored for each result. + 463 * + 464 *********************************************************************** + + +0000000000000528 9823 A000 0000000000000000 466 DIDBRNF LM R2,R3,0(R10) Get count and address of test input values +000000000000052C 9878 A008 0000000000000008 467 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000530 1222 468 LTR R2,R2 Any test cases? +0000000000000532 078D 469 BZR R13 ..No, return to caller +0000000000000534 0DC0 470 BASR R12,0 Set top of loop + 471 * +0000000000000536 B29D F27C 000000000000027C 472 LFPC FPCREGNT Set exceptions non-trappable +000000000000053A 6800 3000 0000000000000000 473 LD FPR0,0(,R3) Get long BFP dividend +000000000000053E 6810 3008 0000000000000008 474 LD FPR1,8(,R3) Get long BFP divisor +0000000000000542 B375 0020 475 LZDR FPR2 Zero remainder register +0000000000000546 B35B 2001 476 DIDBR FPR0,FPR2,FPR1,0 Div to Int FPR0/FPR1, M4=use FPCR + 477 * Quotient in FPR2, remainder in FPR0 +000000000000054A 6000 7000 0000000000000000 478 STD FPR0,0(,R7) Store long BFP remainder +000000000000054E 6020 7008 0000000000000008 479 STD FPR2,8(,R7) Store long BFP quotient +0000000000000552 B29C 8000 0000000000000000 480 STFPC 0(R8) Store resulting FPCR flags and DXC +0000000000000556 B222 0000 481 IPM R0 Retrieve condition code +000000000000055A 8800 001C 000000000000001C 482 SRL R0,28 Move CC to low-order r0, dump prog mask +000000000000055E 4200 8003 0000000000000003 483 STC R0,3(,R8) Store in last byte of FPCR + 484 * +0000000000000562 B29D F280 0000000000000280 485 LFPC FPCREGTR Set exceptions trappable +0000000000000566 6800 3000 0000000000000000 486 LD FPR0,0(,R3) Get long BFP dividend +000000000000056A 6810 3008 0000000000000008 487 LD FPR1,8(,R3) Get long BFP divisor +000000000000056E B375 0020 488 LZDR FPR2 Zero remainder register +0000000000000572 B35B 2001 489 DIDBR FPR0,FPR2,FPR1,0 Div to Int FPR0/FPR1, M4=use FPCR + 490 * Quotient in FPR2, remainder in FPR0 +0000000000000576 6000 7010 0000000000000010 491 STD FPR0,16(,R7) Store long BFP remainder +000000000000057A 6020 7018 0000000000000018 492 STD FPR2,24(,R7) Store long BFP quotient +000000000000057E B29C 8004 0000000000000004 493 STFPC 4(R8) Store resulting FPCR flags and DXC +0000000000000582 B222 0000 494 IPM R0 Retrieve condition code +0000000000000586 8800 001C 000000000000001C 495 SRL R0,28 Move CC to low-order r0, dump prog mask +000000000000058A 4200 8007 0000000000000007 496 STC R0,7(,R8) Store in last byte of FPCR + 497 * +000000000000058E 4130 3010 0000000000000010 498 LA R3,16(,R3) Point to next input value pair +0000000000000592 4170 7020 0000000000000020 499 LA R7,32(,R7) Point to next quo&rem result value pair +0000000000000596 4180 8008 0000000000000008 500 LA R8,8(,R8) Point to next FPCR result area +000000000000059A 062C 501 BCTR R2,R12 Convert next input value. +000000000000059C 07FD 502 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 12 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 504 *********************************************************************** + 505 * + 506 * Perform Divide to Integer using provided long BFP input pairs. This + 507 * set of tests performs basic checks of Divide To Integer emulation + 508 * where both inputs are finite non-zero numbers. + 509 * + 510 * Four results (six values) are generated for each input: + 511 * 1) Divide to integer with all exceptions non-trappable (two values) + 512 * 2) Multiply integer quotient by divisor, add remainder (one value) + 513 * 3) Divide to integerwith all exceptions trappable (two values) + 514 * 4) Multiply integer quotient by divisor, add remainder (one value) + 515 * + 516 * The FPCR and condition code is stored for each result. Note: the + 517 * Multiply and Add instruction does not set the condition code. + 518 * + 519 * Results two and four (multiply and add) validate the calculation + 520 * of the integer quotient and remainder. + 521 * + 522 *********************************************************************** + + +000000000000059E 9823 A000 0000000000000000 524 DIDBRF LM R2,R3,0(R10) Get count and address of test input values +00000000000005A2 9878 A008 0000000000000008 525 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000005A6 1222 526 LTR R2,R2 Any test cases? +00000000000005A8 078D 527 BZR R13 ..No, return to caller +00000000000005AA 0DC0 528 BASR R12,0 Set top of loop + 529 * +00000000000005AC B29D F27C 000000000000027C 530 LFPC FPCREGNT Set exceptions non-trappable +00000000000005B0 6800 3000 0000000000000000 531 LD FPR0,0*32+0(,R3) Get long BFP dividend +00000000000005B4 6810 3008 0000000000000008 532 LD FPR1,0*32+8(,R3) Get long BFP divisor +00000000000005B8 B375 0020 533 LZDR FPR2 Zero remainder register +00000000000005BC B35B 2001 534 DIDBR FPR0,FPR2,FPR1,0 Div to Int FPR0/FPR1, M4=use FPCR + 535 * Quotient in FPR2, remainder in FPR0 +00000000000005C0 6000 7000 0000000000000000 536 STD FPR0,0*32+0(,R7) Store long BFP remainder +00000000000005C4 6020 7008 0000000000000008 537 STD FPR2,0*32+8(,R7) Store long BFP quotient +00000000000005C8 B29C 8000 0000000000000000 538 STFPC 0*4(R8) Store resulting FPCR flags and DXC +00000000000005CC B222 0000 539 IPM R0 Retrieve condition code +00000000000005D0 8800 001C 000000000000001C 540 SRL R0,28 Move CC to low-order r0, dump prog mask +00000000000005D4 4200 8003 0000000000000003 541 STC R0,0*4+3(,R8) Store in last byte of FPCR + 542 * + 543 * FPR1 still has divisor, FPR0 has remainder, FPR2 has integer quotient + 544 * +00000000000005D8 B29D F27C 000000000000027C 545 LFPC FPCREGNT Set exceptions non-trappable +00000000000005DC B31E 0021 546 MADBR FPR0,FPR2,FPR1 Multiply and add to recreate inputs + 547 * Sum of product and remainder in FPR0 +00000000000005E0 6000 7010 0000000000000010 548 STD FPR0,0*32+16(,R7) Store short BFP product-sum +00000000000005E4 B29C 8004 0000000000000004 549 STFPC 1*4(R8) Store resulting FPCR flags and DXC +00000000000005E8 B222 0000 550 IPM R0 Retrieve condition code +00000000000005EC 8800 001C 000000000000001C 551 SRL R0,28 Move CC to low-order r0, dump prog mask +00000000000005F0 4200 8007 0000000000000007 552 STC R0,1*4+3(,R8) Store in last byte of FPCR + 553 * +00000000000005F4 B29D F280 0000000000000280 554 LFPC FPCREGTR Set exceptions trappable + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 13 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000005F8 6800 3000 0000000000000000 555 LD FPR0,0(,R3) Get long BFP dividend +00000000000005FC 6810 3008 0000000000000008 556 LD FPR1,8(,R3) Get long BFP divisor +0000000000000600 B375 0020 557 LZDR FPR2 Zero remainder register +0000000000000604 B35B 2001 558 DIDBR FPR0,FPR2,FPR1,0 Div to Int FPR0/FPR1, M4=use FPCR + 559 * Quotient in FPR2, remainder in FPR0 +0000000000000608 6000 7020 0000000000000020 560 STD FPR0,1*32+0(,R7) Store long BFP remainder +000000000000060C 6020 7028 0000000000000028 561 STD FPR2,1*32+8(,R7) Store long BFP quotient +0000000000000610 B29C 8008 0000000000000008 562 STFPC 2*4(R8) Store resulting FPCR flags and DXC +0000000000000614 B222 0000 563 IPM R0 Retrieve condition code +0000000000000618 8800 001C 000000000000001C 564 SRL R0,28 Move CC to low-order r0, dump prog mask +000000000000061C 4200 800B 000000000000000B 565 STC R0,2*4+3(,R8) Store in last byte of FPCR + 566 * + 567 * FPR1 still has divisor, FPR0 has remainder, FPR2 has integer quotient + 568 * +0000000000000620 B29D F27C 000000000000027C 569 LFPC FPCREGNT Set exceptions non-trappable +0000000000000624 B31E 0021 570 MADBR FPR0,FPR2,FPR1 Multiply and add to recreate inputs + 571 * Sum of product and remainder in FPR0 +0000000000000628 6000 7030 0000000000000030 572 STD FPR0,1*32+16(,R7) Store short BFP product-sum +000000000000062C B29C 800C 000000000000000C 573 STFPC 3*4(R8) Store resulting FPCR flags and DXC +0000000000000630 B222 0000 574 IPM R0 Retrieve condition code +0000000000000634 8800 001C 000000000000001C 575 SRL R0,28 Move CC to low-order r0, dump prog mask +0000000000000638 4200 800F 000000000000000F 576 STC R0,3*4+3(,R8) Store in last byte of FPCR + 577 * +000000000000063C 4130 3010 0000000000000010 578 LA R3,16(,R3) Point to next input value pair +0000000000000640 4170 7040 0000000000000040 579 LA R7,64(,R7) Point to next quo&rem result value pair +0000000000000644 4180 8010 0000000000000010 580 LA R8,16(,R8) Point to next FPCR result area +0000000000000648 062C 581 BCTR R2,R12 Convert next input value. +000000000000064A 07FD 582 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 14 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 584 *********************************************************************** + 585 * + 586 * The next tests operate on finite number input pairs and exhastively + 587 * test rounding modes and partial and final results. + 588 * + 589 * Two rounding modes can be specified for each operation: one for the + 590 * quotient, specified in the M4 field, and the second for the + 591 * remainder, specified in the FPCR. + 592 * + 593 * Because six unique rounding modes can be specified in for the + 594 * quotient and four for the remainder, there are a lot of results that + 595 * need to be evaluated. Note: M4 rounding mode zero, use FPCR rounding + 596 * mode, is not tested because it duplicates one of the six explicit + 597 * M4 rounding modes. Which one depends on the current FPCR setting. + 598 * + 599 * The M4 rounding mode is assembled into the instruction. Back in the + 600 * day, this would be a perfect candidate for an Execute instructoin. + 601 * But the M4 field is not located such that it can be modified by + 602 * an Execute instruction. So we will still use Execute, but only to + 603 * select one of six DIEBR instructions for execution. That way we can + 604 * build an outer loop to iterate through the four FPCR modes, and an + 605 * inner loop to use each of the six M4-specified rounding modes. + 606 * + 607 *********************************************************************** + + +000000000000064C 9823 A000 0000000000000000 609 DIDBRRM LM R2,R3,0(R10) Get count and address of test input values +0000000000000650 9878 A008 0000000000000008 610 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000654 1222 611 LTR R2,R2 Any test cases? +0000000000000656 078D 612 BZR R13 ..No, return to caller +0000000000000658 1711 613 XR R1,R1 Zero register 1 for use in IC/STC/indexing +000000000000065A 0DC0 614 BASR R12,0 Set top of test case loop + 615 +000000000000065C 4150 0004 0000000000000004 616 LA R5,FPCMCT Get count of FPC modes to be tested +0000000000000660 0D90 617 BASR R9,0 Set top of rounding mode outer loop + 618 * + 619 * Update model FPC register settings with the BFP rounding mode for + 620 * this iteration of the loop. + 621 * +0000000000000662 4315 F6F7 00000000000006F7 622 IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode +0000000000000666 4210 F27F 000000000000027F 623 STC R1,FPCREGNT+3 Update non-trap register settings +000000000000066A 4210 F283 0000000000000283 624 STC R1,FPCREGTR+3 Update trap-enabled register settings + 625 * +000000000000066E 4140 0006 0000000000000006 626 LA R4,D2IMCT Get count of M4 modes to be tested +0000000000000672 0D60 627 BASR R6,0 Set top of rounding mode inner loop + 628 * + 629 * Non-trap execution of the instruction. + 630 * +0000000000000674 B29D F27C 000000000000027C 631 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000678 4315 F6F7 00000000000006F7 632 IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode +000000000000067C B2B8 1000 0000000000000000 633 SRNMB 0(R1) Set FPC Rounding Mode +0000000000000680 6800 3000 0000000000000000 634 LD FPR0,0(,R3) Get short BFP dividend + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 15 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000684 6810 3008 0000000000000008 635 LD FPR1,8(,R3) Get short BFP divisor +0000000000000688 B375 0020 636 LZDR FPR2 Zero remainder register +000000000000068C 4314 F6FB 00000000000006FB 637 IC R1,D2IMODES-L'D2IMODES(R4) Get index DIEBR inst table +0000000000000690 4401 F720 0000000000000720 638 EX 0,DIDBRTAB(R1) Execute Divide to Integer +0000000000000694 6000 7000 0000000000000000 639 STD FPR0,0(,R7) Store short BFP remainder +0000000000000698 6020 7008 0000000000000008 640 STD FPR2,8(,R7) Store short BFP quotient +000000000000069C B29C 8000 0000000000000000 641 STFPC 0(R8) Store resulting FPCR flags and DXC +00000000000006A0 B222 0000 642 IPM R0 Retrieve condition code +00000000000006A4 8800 001C 000000000000001C 643 SRL R0,28 Move CC to low-order r0, dump prog mask +00000000000006A8 4200 8003 0000000000000003 644 STC R0,3(,R8) Store in last byte of FPCR + 645 * + 646 * Trap-enabled execution of the instruction. + 647 * +00000000000006AC B29D F280 0000000000000280 648 LFPC FPCREGTR Set exceptions trappable, clear flags +00000000000006B0 4315 F6F7 00000000000006F7 649 IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode +00000000000006B4 B2B8 1000 0000000000000000 650 SRNMB 0(R1) Set FPC Rounding Mode +00000000000006B8 6800 3000 0000000000000000 651 LD FPR0,0(,R3) Get short BFP dividend +00000000000006BC 6810 3008 0000000000000008 652 LD FPR1,8(,R3) Get short BFP divisor +00000000000006C0 B374 0020 653 LZER FPR2 Zero remainder register +00000000000006C4 4314 F6FB 00000000000006FB 654 IC R1,D2IMODES-L'D2IMODES(R4) Get index DIEBR inst table +00000000000006C8 4401 F720 0000000000000720 655 EX 0,DIDBRTAB(R1) Execute Divide to Integer +00000000000006CC 6000 7010 0000000000000010 656 STD FPR0,16(,R7) Store short BFP remainder +00000000000006D0 6020 7018 0000000000000018 657 STD FPR2,24(,R7) Store short BFP quotient +00000000000006D4 B29C 8004 0000000000000004 658 STFPC 4(R8) Store resulting FPCR flags and DXC +00000000000006D8 B222 0000 659 IPM R0 Retrieve condition code +00000000000006DC 8800 001C 000000000000001C 660 SRL R0,28 Move CC to low-order r0, dump prog mask +00000000000006E0 4200 8007 0000000000000007 661 STC R0,7(,R8) Store in last byte of FPCR + 662 * +00000000000006E4 4170 7020 0000000000000020 663 LA R7,32(,R7) Point to next quo&rem result value pair +00000000000006E8 4180 8008 0000000000000008 664 LA R8,8(,R8) Point to next FPCR result area + 665 * +00000000000006EC 0646 666 BCTR R4,R6 Iterate inner loop + 667 * + 668 * End of M4 modes to be tested. + 669 * +00000000000006EE 0659 670 BCTR R5,R9 Iterate outer loop + 671 * + 672 * End of FPC modes to be tested with each M4 mode. Advance to + 673 * next test case. + 674 * +00000000000006F0 4130 3010 0000000000000010 675 LA R3,16(,R3) Point to next input value pair +00000000000006F4 062C 676 BCTR R2,R12 Divide next input value lots of times + 677 * +00000000000006F6 07FD 678 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 16 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 680 *********************************************************************** + 681 * + 682 * Tables and indices used to exhaustively test remainder and quotient + 683 * rounding modes. + 684 * + 685 * The Execute instruction with an appropriate index * is used to + 686 * execute the correct DIEBR/DIDBR instruction. Because * the quotient + 687 * rounding mode is encoded in the DIxBR instruction in the wrong place + 688 * to use Execute to dynamically modify the rounding mode, we will just + 689 * use it to select the correct instruction. + 690 * + 691 * The Set BFP Rounding Mode does allow specification of the FPC + 692 * rounding mode as an address, so we shall index into a table of + 693 * BFP rounding modes without bothering with Execute. + 694 * + 695 *********************************************************************** + + + 697 * + 698 * Rounding modes that may be set in the FPCR. The FPCR controls + 699 * rounding of the quotient. The same table is used for both DIEBR + 700 * and DIDBR instruction testing. + 701 * + 702 * These are indexed directly by the loop counter, which counts down. + 703 * So the modes are listed in reverse order here. + 704 * +00000000000006F8 705 FPCMODES DS 0C +00000000000006F8 07 706 DC AL1(7) RFS, Round for shorter precision +00000000000006F9 03 707 DC AL1(3) RM, Round to -infinity +00000000000006FA 02 708 DC AL1(2) RP, Round to +infinity +00000000000006FB 01 709 DC AL1(1) RZ, Round to zero + 710 *** DC AL1(0) RNTE, Round to Nearest, ties to even + 0000000000000004 0000000000000001 711 FPCMCT EQU *-FPCMODES Count of FPC Modes to be tested + 712 * + 713 * Table of indices into table of DIDBR/DIEBR instructions. The table + 714 * is used for both DIDBR and DIEBR, with the table value being used + 715 * as the index register of an Execute instruction that points to + 716 * either the DIDBR or DIEBR instruction list. + 717 * + 718 * These are indexed directly by the loop counter, which counts down. + 719 * So the instruction indices are listed in reverse order here. + 720 * +00000000000006FC 721 D2IMODES DS 0C +00000000000006FC 18 722 DC AL1(6*4) RM, Round to -infinity +00000000000006FD 14 723 DC AL1(5*4) RP, Round to +infinity +00000000000006FE 10 724 DC AL1(4*4) RZ, Round to zero +00000000000006FF 0C 725 DC AL1(3*4) RNTE, Round to Nearest, ties to even +0000000000000700 08 726 DC AL1(2*4) RFS, Round for Shorter Precision +0000000000000701 04 727 DC AL1(1*4) RNTA, Round to Nearest, ties away + 728 *** DC AL1(0*4) Use FPCR rounding mode + 0000000000000006 0000000000000001 729 D2IMCT EQU *-D2IMODES Count of M4 Modes to be tested + 730 * + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 17 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 731 * List of DIEBR instructions, each with a different rounding mode. + 732 * These are Execute'd by the rounding mode test routing using an index + 733 * obtained from the D2IMODES table above. + 734 * + 735 * This table and the DIDBRTAB table below should remain in the same + 736 * sequence, or you'll be scratching your head keeping the result order + 737 * straight between short and long results. + 738 * +0000000000000704 739 DIEBRTAB DS 0F Table of DIEBR instructions +0000000000000704 B353 2001 740 DIEBR FPR0,FPR2,FPR1,0 Div to Int FPR0/FPR1, M4=use FPCR + 741 * Above is not used +0000000000000708 B353 2101 742 DIEBR FPR0,FPR2,FPR1,1 Div to Int FPR0/FPR1, M4=RNTA +000000000000070C B353 2301 743 DIEBR FPR0,FPR2,FPR1,3 Div to Int FPR0/FPR1, M4=RFS +0000000000000710 B353 2401 744 DIEBR FPR0,FPR2,FPR1,4 Div to Int FPR0/FPR1, M4=RNTE +0000000000000714 B353 2501 745 DIEBR FPR0,FPR2,FPR1,5 Div to Int FPR0/FPR1, M4=RZ +0000000000000718 B353 2601 746 DIEBR FPR0,FPR2,FPR1,6 Div to Int FPR0/FPR1, M4=RP +000000000000071C B353 2701 747 DIEBR FPR0,FPR2,FPR1,7 Div to Int FPR0/FPR1, M4=RM + 748 * + 749 * List of DIDBR instructions, each with a different rounding mode. + 750 * These are Execute'd by the rounding mode test routing using an index + 751 * obtained from the D2IMODES table above. + 752 * + 753 * This table and the DIEBRTAB table above should remain in the same + 754 * sequence, or you'll be scratching your head keeping the result order + 755 * straight between short and long results. + 756 * +0000000000000720 757 DIDBRTAB DS 0F Table of DIDBR instructions +0000000000000720 B35B 2001 758 DIDBR FPR0,FPR2,FPR1,0 Div to Int FPR0/FPR1, M4=use FPCR + 759 * Above is not used +0000000000000724 B35B 2101 760 DIDBR FPR0,FPR2,FPR1,1 Div to Int FPR0/FPR1, M4=RNTA +0000000000000728 B35B 2301 761 DIDBR FPR0,FPR2,FPR1,3 Div to Int FPR0/FPR1, M4=RFS +000000000000072C B35B 2401 762 DIDBR FPR0,FPR2,FPR1,4 Div to Int FPR0/FPR1, M4=RNTE +0000000000000730 B35B 2501 763 DIDBR FPR0,FPR2,FPR1,5 Div to Int FPR0/FPR1, M4=RZ +0000000000000734 B35B 2601 764 DIDBR FPR0,FPR2,FPR1,6 Div to Int FPR0/FPR1, M4=RP +0000000000000738 B35B 2701 765 DIDBR FPR0,FPR2,FPR1,7 Div to Int FPR0/FPR1, M4=RM + 766 * + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 18 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 768 *********************************************************************** + 769 * + 770 * Short integer test data sets for Divide to Integer testing. + 771 * + 772 * Each test data set member consists of two values, the dividend and + 773 * the divisor, in that order. + 774 * + 775 * The first test data set is used for tests of basic functionality, + 776 * NaN propagation, and results from operations involving other than + 777 * finite numbers. + 778 * + 779 * The secondd test data set is used for testing boundary conditions + 780 * using two finite non-zero values. Each possible condition code + 781 * and type of result (normal, scaled, etc) is created by members of + 782 * this test data set. + 783 * + 784 * The third test data set is used for exhaustive testing of final + 785 * results across the panoply of rounding mode combinations available + 786 * for Divide to Integer (five for the remainder, seven for the + 787 * quotient). + 788 * + 789 *********************************************************************** + + + 791 * + 792 * First input test data set, to test operations using non-finite or + 793 * zero inputs. Member values chosen to validate part 1 of Figure 19-21 + 794 * on page 19-29 of SA22-7832-10. + 795 * +000000000000073C 796 SBFPNFIN DS 0F Inputs for short BFP non-finite tests + 797 * + 798 * NaN propagation tests (Tests 1-4) + 799 * +000000000000073C 7F8A0000 800 DC X'7F8A0000' SNaN +0000000000000740 7F8B0000 801 DC X'7F8B0000' SNaN + 802 * +0000000000000744 7FCA0000 803 DC X'7FCA0000' QNaN +0000000000000748 7FCB0000 804 DC X'7FCB0000' QNaN + 805 * +000000000000074C 40000000 806 DC X'40000000' Finite number +0000000000000750 7FCB0000 807 DC X'7FCB0000' QNaN + 808 * +0000000000000754 7FCA0000 809 DC X'7FCA0000' QNaN +0000000000000758 7F8B0000 810 DC X'7F8B0000' SNaN + 811 * + 812 * Dividend is -inf (Tests 5-10) + 813 * +000000000000075C FF800000 814 DC X'FF800000' -inf +0000000000000760 FF800000 815 DC X'FF800000' -inf + 816 * +0000000000000764 FF800000 817 DC X'FF800000' -inf +0000000000000768 C0000000 818 DC X'C0000000' -2.0 + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 19 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 819 * +000000000000076C FF800000 820 DC X'FF800000' -inf +0000000000000770 80000000 821 DC X'80000000' -0 + 822 * +0000000000000774 FF800000 823 DC X'FF800000' -inf +0000000000000778 00000000 824 DC X'00000000' +0 + 825 * +000000000000077C FF800000 826 DC X'FF800000' -inf +0000000000000780 40000000 827 DC X'40000000' +2.0 + 828 * +0000000000000784 FF800000 829 DC X'FF800000' -inf +0000000000000788 7F800000 830 DC X'7F800000' +inf + 831 * + 832 * Dividend is +inf (Tests 11-16) + 833 * +000000000000078C 7F800000 834 DC X'7F800000' +inf +0000000000000790 FF800000 835 DC X'FF800000' -inf + 836 * +0000000000000794 7F800000 837 DC X'7F800000' +inf +0000000000000798 C0000000 838 DC X'C0000000' -2.0 + 839 * +000000000000079C 7F800000 840 DC X'7F800000' +inf +00000000000007A0 80000000 841 DC X'80000000' -0 + 842 * +00000000000007A4 7F800000 843 DC X'7F800000' +inf +00000000000007A8 00000000 844 DC X'00000000' +0 + 845 * +00000000000007AC 7F800000 846 DC X'7F800000' +inf +00000000000007B0 40000000 847 DC X'40000000' +2.0 + 848 * +00000000000007B4 7F800000 849 DC X'7F800000' +inf +00000000000007B8 7F800000 850 DC X'7F800000' +inf + 851 * + 852 * Divisor is -0. (+/-inf dividend tested above) + 853 * (Tests 17-20) + 854 * +00000000000007BC C0000000 855 DC X'C0000000' -2.0 +00000000000007C0 80000000 856 DC X'80000000' -0 + 857 * +00000000000007C4 80000000 858 DC X'80000000' -0 +00000000000007C8 80000000 859 DC X'80000000' -0 + 860 * +00000000000007CC 00000000 861 DC X'00000000' +0 +00000000000007D0 80000000 862 DC X'80000000' -0 + 863 * +00000000000007D4 40000000 864 DC X'40000000' +2.0 +00000000000007D8 80000000 865 DC X'80000000' -0 + 866 * + 867 * Divisor is +0. (+/-inf dividend tested above) + 868 * (Tests 21-24) + 869 * +00000000000007DC C0000000 870 DC X'C0000000' -2.0 + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 20 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000007E0 00000000 871 DC X'00000000' +0 + 872 * +00000000000007E4 80000000 873 DC X'80000000' -0 +00000000000007E8 00000000 874 DC X'00000000' +0 + 875 * +00000000000007EC 00000000 876 DC X'00000000' +0 +00000000000007F0 00000000 877 DC X'00000000' +0 + 878 * +00000000000007F4 40000000 879 DC X'40000000' +2.0 +00000000000007F8 00000000 880 DC X'00000000' +0 + 881 * + 882 * Divisor is -inf. (+/-inf dividend tested above) + 883 * (Tests 25-28) + 884 * +00000000000007FC C0000000 885 DC X'C0000000' -2.0 +0000000000000800 FF800000 886 DC X'FF800000' -inf + 887 * +0000000000000804 80000000 888 DC X'80000000' -0 +0000000000000808 FF800000 889 DC X'FF800000' -inf + 890 * +000000000000080C 00000000 891 DC X'00000000' +0 +0000000000000810 FF800000 892 DC X'FF800000' -inf + 893 * +0000000000000814 40000000 894 DC X'40000000' +2.0 +0000000000000818 FF800000 895 DC X'FF800000' -inf + 896 * + 897 * Divisor is +inf. (+/-inf dividend tested above) + 898 * (Tests 29-32) + 899 * +000000000000081C C0000000 900 DC X'C0000000' -2.0 +0000000000000820 7F800000 901 DC X'7F800000' +inf + 902 * +0000000000000824 80000000 903 DC X'80000000' -0 +0000000000000828 7F800000 904 DC X'7F800000' +inf + 905 * +000000000000082C 00000000 906 DC X'00000000' +0 +0000000000000830 7F800000 907 DC X'7F800000' +inf + 908 * +0000000000000834 40000000 909 DC X'40000000' +2.0 +0000000000000838 7F800000 910 DC X'7F800000' +inf + 911 * + 0000000000000100 0000000000000001 912 SBFPNFCT EQU *-SBFPNFIN Count of short BFP in list * 4 + + + + 914 *********************************************************************** + 915 * + 916 * Second input test data set. These are finite pairs intended to + 917 * test all combinations of finite values and results (final + 918 * results due to remainder zero, final results due to quotient + 919 * within range, and partial results. + 920 * + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 21 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 921 *********************************************************************** + + +000000000000083C 923 SBFPIN DS 0F Inputs for short BFP finite tests + 924 * + 925 * Dividend and Divisor are both finite numbers. + 926 * + 927 * Remainder tests from SA22-7832-10, Figure 19-7 on page 19-6 + 928 * (Finite tests 1-16; negative divisor) + 929 * +000000000000083C C1000000 930 DC X'C1000000' -8 +0000000000000840 C0800000 931 DC X'C0800000' -4 + 932 * +0000000000000844 C0E00000 933 DC X'C0E00000' -7 +0000000000000848 C0800000 934 DC X'C0800000' -4 + 935 * +000000000000084C C0C00000 936 DC X'C0C00000' -6 +0000000000000850 C0800000 937 DC X'C0800000' -4 + 938 * +0000000000000854 C0A00000 939 DC X'C0A00000' -5 +0000000000000858 C0800000 940 DC X'C0800000' -4 + 941 * +000000000000085C C0800000 942 DC X'C0800000' -4 +0000000000000860 C0800000 943 DC X'C0800000' -4 + 944 * +0000000000000864 C0400000 945 DC X'C0400000' -3 +0000000000000868 C0800000 946 DC X'C0800000' -4 + 947 * +000000000000086C C0000000 948 DC X'C0000000' -2 +0000000000000870 C0800000 949 DC X'C0800000' -4 + 950 * +0000000000000874 BF800000 951 DC X'BF800000' -1 +0000000000000878 C0800000 952 DC X'C0800000' -4 + 953 * + 954 * The +/- zero - +/- zero cases are handled above and skipped here + 955 * +000000000000087C 3F800000 956 DC X'3F800000' +1 +0000000000000880 C0800000 957 DC X'C0800000' -4 + 958 * +0000000000000884 40000000 959 DC X'40000000' +2 +0000000000000888 C0800000 960 DC X'C0800000' -4 + 961 * +000000000000088C 40400000 962 DC X'40400000' +3 +0000000000000890 C0800000 963 DC X'C0800000' -4 + 964 * +0000000000000894 40800000 965 DC X'40800000' +4 +0000000000000898 C0800000 966 DC X'C0800000' -4 + 967 * +000000000000089C 40A00000 968 DC X'40A00000' +5 +00000000000008A0 C0800000 969 DC X'C0800000' -4 + 970 * +00000000000008A4 40C00000 971 DC X'40C00000' +6 + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 22 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000008A8 C0800000 972 DC X'C0800000' -4 + 973 * +00000000000008AC 40E00000 974 DC X'40E00000' +7 +00000000000008B0 C0800000 975 DC X'C0800000' -4 + 976 * +00000000000008B4 41000000 977 DC X'41000000' +8 +00000000000008B8 C0800000 978 DC X'C0800000' -4 + 979 * + 980 * Finite tests 17-32; positive divisor + 981 * +00000000000008BC C1000000 982 DC X'C1000000' -8 +00000000000008C0 40800000 983 DC X'40800000' +4 + 984 * +00000000000008C4 C0E00000 985 DC X'C0E00000' -7 +00000000000008C8 40800000 986 DC X'40800000' +4 + 987 * +00000000000008CC C0C00000 988 DC X'C0C00000' -6 +00000000000008D0 40800000 989 DC X'40800000' +4 + 990 * +00000000000008D4 C0A00000 991 DC X'C0A00000' -5 +00000000000008D8 40800000 992 DC X'40800000' +4 + 993 * +00000000000008DC C0800000 994 DC X'C0800000' -4 +00000000000008E0 40800000 995 DC X'40800000' +4 + 996 * +00000000000008E4 C0400000 997 DC X'C0400000' -3 +00000000000008E8 40800000 998 DC X'40800000' +4 + 999 * +00000000000008EC C0000000 1000 DC X'C0000000' -2 +00000000000008F0 40800000 1001 DC X'40800000' +4 + 1002 * +00000000000008F4 3F800000 1003 DC X'3F800000' -1 +00000000000008F8 40800000 1004 DC X'40800000' +4 + 1005 * +00000000000008FC 3F800000 1006 DC X'3F800000' +1 +0000000000000900 40800000 1007 DC X'40800000' +4 + 1008 * +0000000000000904 40000000 1009 DC X'40000000' +2 +0000000000000908 40800000 1010 DC X'40800000' +4 + 1011 * +000000000000090C 40400000 1012 DC X'40400000' +3 +0000000000000910 40800000 1013 DC X'40800000' +4 + 1014 * +0000000000000914 40800000 1015 DC X'40800000' +4 +0000000000000918 40800000 1016 DC X'40800000' +4 + 1017 * +000000000000091C 40A00000 1018 DC X'40A00000' +5 +0000000000000920 40800000 1019 DC X'40800000' +4 + 1020 * +0000000000000924 40C00000 1021 DC X'40C00000' +6 +0000000000000928 40800000 1022 DC X'40800000' +4 + 1023 * + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 23 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +000000000000092C 40E00000 1024 DC X'40E00000' +7 +0000000000000930 40800000 1025 DC X'40800000' +4 + 1026 * +0000000000000934 41000000 1027 DC X'41000000' +8 +0000000000000938 40800000 1028 DC X'40800000' +4 + 1029 * + 1030 * Finite value boundary condition tests + 1031 * Tests 17-22 + 1032 * +000000000000093C 42200000 1033 DC X'42200000' +40.0 +0000000000000940 C1100000 1034 DC X'C1100000' -9.0 + 1035 * + 1036 * Following forces quotient overflow, remainder zero. + 1037 * Final result, scaled quotient, cc1 +0000000000000944 7F7FFFFF 1038 DC X'7F7FFFFF' +maxvalue +0000000000000948 00000001 1039 DC X'00000001' +minvalue (tiny) + 1040 * +000000000000094C 00FFFFFF 1041 DC X'00FFFFFF' near +minvalue normal +0000000000000950 00FFFFFE 1042 DC X'00FFFFFE' almost above + 1043 * + 1044 * Following forces partial results without quotient overflow + 1045 * Partial result, scaled quotient, normal remainder, cc2 +0000000000000954 4C800000 1046 DC X'4C800000' +2^26th +0000000000000958 40400000 1047 DC X'40400000' +3.0 + 1048 * Expected results from above case: remainder < 3, quotient mismatch + 1049 * z12 actual results: remainder 4, quotient match. + 1050 * + 1051 * Following forces zero quotient, remainder = divisor. + 1052 * +000000000000095C 40100000 1053 DC X'40100000' +2.25 +0000000000000960 41200000 1054 DC X'41200000' +10 + 1055 * + 1056 * Following five tests force quotient overflow. Four have non-zero + 1057 * Remainder. All five return partial results. + 1058 * + 1059 * Note: +minvalue+11 is the smallest divisor that generates a + 1060 * remainder. + 1061 * +0000000000000964 7F7FFFFF 1062 DC X'7F7FFFFF' +maxvalue +0000000000000968 0000000B 1063 DC X'0000000B' +minvalue + 11 (tiny) + 1064 * +000000000000096C 7F7FFFFE 1065 DC X'7F7FFFFE' +maxvalue +0000000000000970 0000000A 1066 DC X'0000000A' +minvalue + 11 (tiny) + 1067 * +0000000000000974 7F7FFFFF 1068 DC X'7F7FFFFF' +maxvalue +0000000000000978 0000000C 1069 DC X'0000000C' +minvalue + 11 (tiny) + 1070 * +000000000000097C 7F7FFFFF 1071 DC X'7F7FFFFF' +maxvalue +0000000000000980 00000013 1072 DC X'00000013' +minvalue + 11 (tiny) + 1073 * +0000000000000984 7F7FFFFF 1074 DC X'7F7FFFFF' +maxvalue +0000000000000988 3F000000 1075 DC X'3F000000' +0.5 + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 24 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1076 * +000000000000098C 40400000 1077 DC X'40400000' +3 +0000000000000990 40000000 1078 DC X'40000000' +2 + 1079 * + 0000000000000158 0000000000000001 1080 SBFPCT EQU *-SBFPIN Count of short BFP in list * 4 + + + + 1082 *********************************************************************** + 1083 * + 1084 * Third input test data set. These are finite pairs intended to + 1085 * test all combinations of rounding mode for the quotient and the + 1086 * remainder. + 1087 * + 1088 * The quotient/remainder pairs are for Round to Nearest, Ties to Even. + 1089 * Other rounding modes have different results. + 1090 * + 1091 *********************************************************************** + + +0000000000000994 1093 SBFPINRM DS 0F Inputs for short BFP rounding testing +0000000000000994 C1980000 1094 DC X'C1980000' -19 / 0.5 = -9.5, -9 rem +1 +0000000000000998 40000000 1095 DC X'40000000' ...+2.0 +000000000000099C C1300000 1096 DC X'C1300000' -11 / 0.5 = -5.5, -5 rem +1 +00000000000009A0 40000000 1097 DC X'40000000' ...+2.0 +00000000000009A4 C0A00000 1098 DC X'C0A00000' -5 / 0.5 = -2.5 +00000000000009A8 40000000 1099 DC X'40000000' ...+2.0 +00000000000009AC C0400000 1100 DC X'C0400000' -3 / 0.5 = -1.5 +00000000000009B0 40000000 1101 DC X'40000000' ...+2.0 +00000000000009B4 BF800000 1102 DC X'BF800000' -1 / 0.5 = -0.5 +00000000000009B8 40000000 1103 DC X'40000000' ...+2.0 +00000000000009BC 3F800000 1104 DC X'3F800000' +1 / 0.5 = +0.5 +00000000000009C0 40000000 1105 DC X'40000000' ...+2.0 +00000000000009C4 40400000 1106 DC X'40400000' +3 / 0.5 = +1.5 +00000000000009C8 40000000 1107 DC X'40000000' ...+2.0 +00000000000009CC 40A00000 1108 DC X'40A00000' +5 / 0.5 = +2.5 +00000000000009D0 40000000 1109 DC X'40000000' ...+2.0 +00000000000009D4 41300000 1110 DC X'41300000' +11 / 0.5 = +5.5 +00000000000009D8 40000000 1111 DC X'40000000' ...+2.0 +00000000000009DC 41980000 1112 DC X'41980000' +19 / 0.5 = +9.5 +00000000000009E0 40000000 1113 DC X'40000000' ...+2.0 +00000000000009E4 40000000 1114 DC X'40000000' 2 / 2 = 1 +00000000000009E8 40000000 1115 DC X'40000000' ...+2.0 +00000000000009EC 40400000 1116 DC X'40400000' +3 / 5 = +0.6, 0 rem 3 +00000000000009F0 40A00000 1117 DC X'40A00000' ...+5.0 + 0000000000000060 0000000000000001 1118 SBFPRMCT EQU *-SBFPINRM Count of short BFP rounding tests * 4 + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 25 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1120 *********************************************************************** + 1121 * + 1122 * Long integer test data sets for Divide to Integer testing. + 1123 * + 1124 * Each test data set member consists of two values, the dividend and + 1125 * the divisor, in that order. + 1126 * + 1127 * The first test data set is used for tests of basic functionality, + 1128 * NaN propagation, and results from operations involving other than + 1129 * finite numbers. + 1130 * + 1131 * The secondd test data set is used for testing boundary conditions + 1132 * using two finite non-zero values. Each possible condition code + 1133 * and type of result (normal, scaled, etc) is created by members of + 1134 * this test data set. + 1135 * + 1136 * The third test data set is used for exhaustive testing of final + 1137 * results across the panoply of rounding mode combinations available + 1138 * for Divide to Integer (five for the remainder, seven for the + 1139 * quotient). + 1140 * + 1141 *********************************************************************** + 1142 * +00000000000009F4 1143 LBFPNFIN DS 0F Inputs for long BFP testing + 1144 * + 1145 * NaN propagation tests + 1146 * +00000000000009F4 7FF0A000 00000000 1147 DC X'7FF0A00000000000' SNaN +00000000000009FC 7FF0B000 00000000 1148 DC X'7FF0B00000000000' SNaN + 1149 * +0000000000000A04 7FF8A000 00000000 1150 DC X'7FF8A00000000000' QNaN +0000000000000A0C 7FF8B000 00000000 1151 DC X'7FF8B00000000000' QNaN + 1152 * +0000000000000A14 40000000 00000000 1153 DC X'4000000000000000' Finite number +0000000000000A1C 7FF8B000 00000000 1154 DC X'7FF8B00000000000' QNaN + 1155 * +0000000000000A24 7FF8A000 00000000 1156 DC X'7FF8A00000000000' QNaN +0000000000000A2C 7FF0B000 00000000 1157 DC X'7FF0B00000000000' SNaN + 1158 * + 1159 * Dividend is -inf + 1160 * +0000000000000A34 FFF00000 00000000 1161 DC X'FFF0000000000000' -inf +0000000000000A3C FFF00000 00000000 1162 DC X'FFF0000000000000' -inf + 1163 * +0000000000000A44 FFF00000 00000000 1164 DC X'FFF0000000000000' -inf +0000000000000A4C C0000000 00000000 1165 DC X'C000000000000000' -2.0 + 1166 * +0000000000000A54 FFF00000 00000000 1167 DC X'FFF0000000000000' -inf +0000000000000A5C 80000000 00000000 1168 DC X'8000000000000000' -0 + 1169 * +0000000000000A64 FFF00000 00000000 1170 DC X'FFF0000000000000' -inf +0000000000000A6C 00000000 00000000 1171 DC X'0000000000000000' +0 + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 26 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1172 * +0000000000000A74 FFF00000 00000000 1173 DC X'FFF0000000000000' -inf +0000000000000A7C 40000000 00000000 1174 DC X'4000000000000000' +2.0 + 1175 * +0000000000000A84 FFF00000 00000000 1176 DC X'FFF0000000000000' -inf +0000000000000A8C 7FF00000 00000000 1177 DC X'7FF0000000000000' +inf + 1178 * + 1179 * Dividend is +inf + 1180 * +0000000000000A94 7FF00000 00000000 1181 DC X'7FF0000000000000' +inf +0000000000000A9C FFF00000 00000000 1182 DC X'FFF0000000000000' -inf + 1183 * +0000000000000AA4 7FF00000 00000000 1184 DC X'7FF0000000000000' +inf +0000000000000AAC C0000000 00000000 1185 DC X'C000000000000000' -2.0 + 1186 * +0000000000000AB4 7FF00000 00000000 1187 DC X'7FF0000000000000' +inf +0000000000000ABC 80000000 00000000 1188 DC X'8000000000000000' -0 + 1189 * +0000000000000AC4 7FF00000 00000000 1190 DC X'7FF0000000000000' +inf +0000000000000ACC 00000000 00000000 1191 DC X'0000000000000000' +0 + 1192 * +0000000000000AD4 7FF00000 00000000 1193 DC X'7FF0000000000000' +inf +0000000000000ADC 40000000 00000000 1194 DC X'4000000000000000' +2.0 + 1195 * +0000000000000AE4 7FF00000 00000000 1196 DC X'7FF0000000000000' +inf +0000000000000AEC 7FF00000 00000000 1197 DC X'7FF0000000000000' +inf + 1198 * + 1199 * Divisor is -0. (+/-inf dividend tested above) + 1200 * +0000000000000AF4 C0000000 00000000 1201 DC X'C000000000000000' -2.0 +0000000000000AFC 80000000 00000000 1202 DC X'8000000000000000' -0 + 1203 * +0000000000000B04 80000000 00000000 1204 DC X'8000000000000000' -0 +0000000000000B0C 80000000 00000000 1205 DC X'8000000000000000' -0 + 1206 * +0000000000000B14 00000000 00000000 1207 DC X'0000000000000000' +0 +0000000000000B1C 80000000 00000000 1208 DC X'8000000000000000' -0 + 1209 * +0000000000000B24 40000000 00000000 1210 DC X'4000000000000000' +2.0 +0000000000000B2C 80000000 00000000 1211 DC X'8000000000000000' -0 + 1212 * + 1213 * Divisor is +0. (+/-inf dividend tested above) + 1214 * +0000000000000B34 C0000000 00000000 1215 DC X'C000000000000000' -2.0 +0000000000000B3C 00000000 00000000 1216 DC X'0000000000000000' +0 + 1217 * +0000000000000B44 80000000 00000000 1218 DC X'8000000000000000' -0 +0000000000000B4C 00000000 00000000 1219 DC X'0000000000000000' +0 + 1220 * +0000000000000B54 00000000 00000000 1221 DC X'0000000000000000' +0 +0000000000000B5C 00000000 00000000 1222 DC X'0000000000000000' +0 + 1223 * + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 27 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000B64 40000000 00000000 1224 DC X'4000000000000000' +2.0 +0000000000000B6C 00000000 00000000 1225 DC X'0000000000000000' +0 + 1226 * + 1227 * Divisor is -inf. (+/-inf dividend tested above) + 1228 * +0000000000000B74 C0000000 00000000 1229 DC X'C000000000000000' -2.0 +0000000000000B7C FFF00000 00000000 1230 DC X'FFF0000000000000' -inf + 1231 * +0000000000000B84 80000000 00000000 1232 DC X'8000000000000000' -0 +0000000000000B8C FFF00000 00000000 1233 DC X'FFF0000000000000' -inf + 1234 * +0000000000000B94 00000000 00000000 1235 DC X'0000000000000000' +0 +0000000000000B9C FFF00000 00000000 1236 DC X'FFF0000000000000' -inf + 1237 * +0000000000000BA4 40000000 00000000 1238 DC X'4000000000000000' +2.0 +0000000000000BAC FFF00000 00000000 1239 DC X'FFF0000000000000' -inf + 1240 * + 1241 * Divisor is +inf. (+/-inf dividend tested above) + 1242 * +0000000000000BB4 C0000000 00000000 1243 DC X'C000000000000000' -2.0 +0000000000000BBC 7FF00000 00000000 1244 DC X'7FF0000000000000' +inf + 1245 * +0000000000000BC4 80000000 00000000 1246 DC X'8000000000000000' -0 +0000000000000BCC 7FF00000 00000000 1247 DC X'7FF0000000000000' +inf + 1248 * +0000000000000BD4 00000000 00000000 1249 DC X'0000000000000000' +0 +0000000000000BDC 7FF00000 00000000 1250 DC X'7FF0000000000000' +inf + 1251 * +0000000000000BE4 40000000 00000000 1252 DC X'4000000000000000' +2.0 +0000000000000BEC 7FF00000 00000000 1253 DC X'7FF0000000000000' +inf + 0000000000000200 0000000000000001 1254 LBFPNFCT EQU *-LBFPNFIN Count of long BFP in list * 8 + + + + 1256 *********************************************************************** + 1257 * + 1258 * Second set of test inputs. These are finite pairs intended to + 1259 * test all combinations of finite values and results (final + 1260 * results due to remainder zero, final results due to quotient + 1261 * within range, and partial results. + 1262 * + 1263 *********************************************************************** + + +0000000000000BF4 1265 LBFPIN DS 0F Inputs for long BFP finite tests + 1266 * + 1267 * Dividend and Divisor are both finite numbers. + 1268 * + 1269 * Remainder tests from SA22-7832-10, Figure 19-7 on page 19-6 + 1270 * (Finite tests 1-32) + 1271 * +0000000000000BF4 C0200000 00000000 1272 DC X'C020000000000000' -8 + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 28 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000BFC C0100000 00000000 1273 DC X'C010000000000000' -4 + 1274 * +0000000000000C04 C01C0000 00000000 1275 DC X'C01C000000000000' -7 +0000000000000C0C C0100000 00000000 1276 DC X'C010000000000000' -4 + 1277 * +0000000000000C14 C0180000 00000000 1278 DC X'C018000000000000' -6 +0000000000000C1C C0100000 00000000 1279 DC X'C010000000000000' -4 + 1280 * +0000000000000C24 C0140000 00000000 1281 DC X'C014000000000000' -5 +0000000000000C2C C0100000 00000000 1282 DC X'C010000000000000' -4 + 1283 * +0000000000000C34 C0100000 00000000 1284 DC X'C010000000000000' -4 +0000000000000C3C C0100000 00000000 1285 DC X'C010000000000000' -4 + 1286 * +0000000000000C44 C0080000 00000000 1287 DC X'C008000000000000' -3 +0000000000000C4C C0100000 00000000 1288 DC X'C010000000000000' -4 + 1289 * +0000000000000C54 C0000000 00000000 1290 DC X'C000000000000000' -2 +0000000000000C5C C0100000 00000000 1291 DC X'C010000000000000' -4 + 1292 * +0000000000000C64 BFF00000 00000000 1293 DC X'BFF0000000000000' -1 +0000000000000C6C C0100000 00000000 1294 DC X'C010000000000000' -4 + 1295 * + 1296 * The +/- zero - +/- zero cases are handled above and skipped here + 1297 * +0000000000000C74 3FF00000 00000000 1298 DC X'3FF0000000000000' +1 +0000000000000C7C C0100000 00000000 1299 DC X'C010000000000000' -4 + 1300 * +0000000000000C84 40000000 00000000 1301 DC X'4000000000000000' +2 +0000000000000C8C C0100000 00000000 1302 DC X'C010000000000000' -4 + 1303 * +0000000000000C94 40080000 00000000 1304 DC X'4008000000000000' +3 +0000000000000C9C C0100000 00000000 1305 DC X'C010000000000000' -4 + 1306 * +0000000000000CA4 40100000 00000000 1307 DC X'4010000000000000' +4 +0000000000000CAC C0100000 00000000 1308 DC X'C010000000000000' -4 + 1309 * +0000000000000CB4 40140000 00000000 1310 DC X'4014000000000000' +5 +0000000000000CBC C0100000 00000000 1311 DC X'C010000000000000' -4 + 1312 * +0000000000000CC4 40180000 00000000 1313 DC X'4018000000000000' +6 +0000000000000CCC C0100000 00000000 1314 DC X'C010000000000000' -4 + 1315 * +0000000000000CD4 401C0000 00000000 1316 DC X'401C000000000000' +7 +0000000000000CDC C0100000 00000000 1317 DC X'C010000000000000' -4 + 1318 * +0000000000000CE4 40200000 00000000 1319 DC X'4020000000000000' +8 +0000000000000CEC C0100000 00000000 1320 DC X'C010000000000000' -4 + 1321 * +0000000000000CF4 C0200000 00000000 1322 DC X'C020000000000000' -8 +0000000000000CFC 40100000 00000000 1323 DC X'4010000000000000' +4 + 1324 * + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 29 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000D04 C01C0000 00000000 1325 DC X'C01C000000000000' -7 +0000000000000D0C 40100000 00000000 1326 DC X'4010000000000000' +4 + 1327 * +0000000000000D14 C0180000 00000000 1328 DC X'C018000000000000' -6 +0000000000000D1C 40100000 00000000 1329 DC X'4010000000000000' +4 + 1330 * +0000000000000D24 C0140000 00000000 1331 DC X'C014000000000000' -5 +0000000000000D2C 40100000 00000000 1332 DC X'4010000000000000' +4 + 1333 * +0000000000000D34 C0100000 00000000 1334 DC X'C010000000000000' -4 +0000000000000D3C 40100000 00000000 1335 DC X'4010000000000000' +4 + 1336 * +0000000000000D44 C0080000 00000000 1337 DC X'C008000000000000' -3 +0000000000000D4C 40100000 00000000 1338 DC X'4010000000000000' +4 + 1339 * +0000000000000D54 C0000000 00000000 1340 DC X'C000000000000000' -2 +0000000000000D5C 40100000 00000000 1341 DC X'4010000000000000' +4 + 1342 * +0000000000000D64 3FF00000 00000000 1343 DC X'3FF0000000000000' -1 +0000000000000D6C 40100000 00000000 1344 DC X'4010000000000000' +4 + 1345 * +0000000000000D74 3FF00000 00000000 1346 DC X'3FF0000000000000' +1 +0000000000000D7C 40100000 00000000 1347 DC X'4010000000000000' +4 + 1348 * +0000000000000D84 40000000 00000000 1349 DC X'4000000000000000' +2 +0000000000000D8C 40100000 00000000 1350 DC X'4010000000000000' +4 + 1351 * +0000000000000D94 40080000 00000000 1352 DC X'4008000000000000' +3 +0000000000000D9C 40100000 00000000 1353 DC X'4010000000000000' +4 + 1354 * +0000000000000DA4 40100000 00000000 1355 DC X'4010000000000000' +4 +0000000000000DAC 40100000 00000000 1356 DC X'4010000000000000' +4 + 1357 * +0000000000000DB4 40140000 00000000 1358 DC X'4014000000000000' +5 +0000000000000DBC 40100000 00000000 1359 DC X'4010000000000000' +4 + 1360 * +0000000000000DC4 40180000 00000000 1361 DC X'4018000000000000' +6 +0000000000000DCC 40100000 00000000 1362 DC X'4010000000000000' +4 + 1363 * +0000000000000DD4 401C0000 00000000 1364 DC X'401C000000000000' +7 +0000000000000DDC 40100000 00000000 1365 DC X'4010000000000000' +4 + 1366 * +0000000000000DE4 40200000 00000000 1367 DC X'4020000000000000' +8 +0000000000000DEC 40100000 00000000 1368 DC X'4010000000000000' +4 + 1369 ** + 1370 * Dividend and Divisor are both finite numbers. + 1371 * (Tests 33-38) + 1372 * +0000000000000DF4 40440000 00000000 1373 DC X'4044000000000000' +40.0 +0000000000000DFC C0220000 00000000 1374 DC X'C022000000000000' -9.0 + 1375 * + 1376 * Following forces quotient overflow, remainder zero. + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 30 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1377 * Final result, scaled quotient, cc1 +0000000000000E04 7FEFFFFF FFFFFFFF 1378 DC X'7FEFFFFFFFFFFFFF' +maxvalue +0000000000000E0C 00000000 00000001 1379 DC X'0000000000000001' +minvalue (tiny) + 1380 * + 1381 * Following forces quotient overflow, remainder non-zero. + 1382 * Partial result, scaled quotient, tiny remainder, cc3 + 1383 * Note: +minvalue+2 is the smallest divisor that + 1384 * generates a non-zero remainder. +0000000000000E14 7FEFFFFF FFFFFFFF 1385 DC X'7FEFFFFFFFFFFFFF' +maxvalue +0000000000000E1C 00000000 00000003 1386 DC X'0000000000000003' +minvalue (tiny) + 1387 * +0000000000000E24 000FFFFF FFFFFFFF 1388 DC X'000FFFFFFFFFFFFF' near +minvalue normal +0000000000000E2C 000FFFFF FFFFFFFE 1389 DC X'000FFFFFFFFFFFFE' almost above + 1390 * + 1391 * Following forces partial results without quotient overflow + 1392 * Partial result, scaled quotient, normal remainder, cc2 +0000000000000E34 43700000 00000000 1393 DC X'4370000000000000' +2^56th +0000000000000E3C 40080000 00000000 1394 DC X'4008000000000000' +3.0 + 1395 * Expected results from above case: remainder < 3, quotient mismatch + 1396 * z12 actual results: remainder 4, quotient match. + 1397 * + 1398 * Following forces zero quotient, remainder = divisor. + 1399 * +0000000000000E44 40020000 00000000 1400 DC X'4002000000000000' +2.25 +0000000000000E4C 40240000 00000000 1401 DC X'4024000000000000' +10 + 1402 * + 0000000000000260 0000000000000001 1403 LBFPCT EQU *-LBFPIN Count of long BFP in list * 8 + + + + 1405 *********************************************************************** + 1406 * + 1407 * Third input test data set. These are finite pairs intended to + 1408 * test all combinations of rounding mode for the quotient and the + 1409 * remainder. + 1410 * + 1411 * The quotient/remainder pairs are for Round to Nearest, Ties to Even. + 1412 * Other rounding modes have different results. + 1413 * + 1414 *********************************************************************** + + +0000000000000E54 1416 LBFPINRM DS 0F +0000000000000E54 C0230000 00000000 1417 DC X'C023000000000000' -9.5, -9 rem 1 +0000000000000E5C 40000000 00000000 1418 DC X'4000000000000000' +2 + 1419 * +0000000000000E64 C0160000 00000000 1420 DC X'C016000000000000' -5.5 +0000000000000E6C 40000000 00000000 1421 DC X'4000000000000000' +2 + 1422 * +0000000000000E74 C0040000 00000000 1423 DC X'C004000000000000' -2.5 +0000000000000E7C 40000000 00000000 1424 DC X'4000000000000000' +2 + 1425 * + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 31 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000E84 BFF80000 00000000 1426 DC X'BFF8000000000000' -1.5 +0000000000000E8C 40000000 00000000 1427 DC X'4000000000000000' +2 + 1428 * +0000000000000E94 BFE00000 00000000 1429 DC X'BFE0000000000000' -0.5 +0000000000000E9C 40000000 00000000 1430 DC X'4000000000000000' +2 + 1431 * +0000000000000EA4 3FE00000 00000000 1432 DC X'3FE0000000000000' +0.5 +0000000000000EAC 40000000 00000000 1433 DC X'4000000000000000' +2 + 1434 * +0000000000000EB4 3FF80000 00000000 1435 DC X'3FF8000000000000' +1.5 +0000000000000EBC 40000000 00000000 1436 DC X'4000000000000000' +2 + 1437 * +0000000000000EC4 40040000 00000000 1438 DC X'4004000000000000' +2.5 +0000000000000ECC 40000000 00000000 1439 DC X'4000000000000000' +2 + 1440 * +0000000000000ED4 40160000 00000000 1441 DC X'4016000000000000' +5.5 +0000000000000EDC 40000000 00000000 1442 DC X'4000000000000000' +2 + 1443 * +0000000000000EE4 40230000 00000000 1444 DC X'4023000000000000' +9.5 +0000000000000EEC 40000000 00000000 1445 DC X'4000000000000000' +2 + 1446 * +0000000000000EF4 40000000 00000000 1447 DC X'4000000000000000' +2 +0000000000000EFC 40000000 00000000 1448 DC X'4000000000000000' +2 + 1449 * +0000000000000F04 40080000 00000000 1450 DC X'4008000000000000' +3 +0000000000000F0C 40140000 00000000 1451 DC X'4014000000000000' +5 + 1452 * + 00000000000000C0 0000000000000001 1453 LBFPRMCT EQU *-LBFPINRM Count of long BFP rounding tests * 8 + 1454 * + 1455 * + 1456 * Locations for results + 1457 * + 0000000000001000 0000000000000000 1458 SBFPNFOT EQU BFPDV2NT+X'1000' Integer short non-finite BFP results + 1459 * ..room for 32 tests, 32 used + 0000000000001200 0000000000000000 1460 SBFPNFFL EQU BFPDV2NT+X'1200' FPCR flags and DXC from short BFP + 1461 * ..room for 32 tests, 32 used + 1462 * + 0000000000001300 0000000000000000 1463 LBFPNFOT EQU BFPDV2NT+X'1300' Integer long non-finite BFP results + 1464 * ..room for 32 tests, 32 used + 0000000000001700 0000000000000000 1465 LBFPNFFL EQU BFPDV2NT+X'1700' FPCR flags and DXC from long BFP + 1466 * ..room for 32 tests, 32 used + 1467 * + 0000000000002000 0000000000000000 1468 SBFPRMO EQU BFPDV2NT+X'2000' Short BFP rounding mode test results + 1469 * ..Room for 20, 10 used. + 0000000000004000 0000000000000000 1470 SBFPRMOF EQU BFPDV2NT+X'4000' Short BFP rounding mode FPCR results + 1471 * ..Room for 20, 10 used. + 1472 * + 0000000000005000 0000000000000000 1473 LBFPRMO EQU BFPDV2NT+X'5000' Long BFP rounding mode test results + 1474 * ..Room for 20, 10 used. + 0000000000009000 0000000000000000 1475 LBFPRMOF EQU BFPDV2NT+X'9000' Long BFP rounding mode FPCR results + 1476 * ..Room for 20, 10 used. + 1477 * + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 32 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 000000000000A000 0000000000000000 1478 SBFPOUT EQU BFPDV2NT+X'A000' Integer short BFP finite results + 1479 * ..room for 64 tests, 38 used + 000000000000A800 0000000000000000 1480 SBFPFLGS EQU BFPDV2NT+X'A800' FPCR flags and DXC from short BFP + 1481 * ..room for 64 tests, 6 used + 1482 * + 000000000000B000 0000000000000000 1483 LBFPOUT EQU BFPDV2NT+X'B000' Integer long BFP finite results + 1484 * ..room for 64 tests, 6 used + 000000000000AC00 0000000000000000 1485 LBFPFLGS EQU BFPDV2NT+X'AC00' FPCR flags and DXC from long BFP + 1486 * ..room for 64 tests, 6 used + 1487 * + 1488 * + 000000000000C000 0000000000000000 1489 ENDLABL EQU BFPDV2NT+X'C000' + 1490 PADCSECT ENDLABL + 1491+ MNOTE *,'asma detected; no CSECT padding performed' +0000000000000F14 1492 END + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 33 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +BFPDV2NT J 000000 3860 73 122 125 127 130 138 191 1458 1460 1463 1465 1468 1470 1473 1475 + 1478 1480 1483 1485 1489 +CTLR0 F 000278 4 181 155 156 157 +D2IMCT U 000006 1 729 400 626 +D2IMODES C 0006FC 1 721 729 411 428 637 654 +DIDBRF I 00059E 4 524 169 +DIDBRNF I 000528 4 466 167 +DIDBRRM I 00064C 4 609 171 +DIDBRTAB F 000720 4 757 638 655 +DIEBRF I 0003D6 4 299 162 +DIEBRNF H 000360 2 240 160 +DIEBRRM I 000484 4 385 164 +DIEBRTAB F 000704 4 739 412 429 +ENDLABL U 00C000 0 1489 +FPCMCT U 000004 1 711 392 616 +FPCMODES C 0006F8 1 705 711 398 406 423 622 632 649 +FPCREGNT X 00027C 4 182 247 305 320 344 405 472 530 545 569 623 631 +FPCREGTR X 000280 4 183 260 329 422 485 554 624 648 +FPR0 U 000000 1 93 248 251 253 261 264 266 306 309 311 321 323 330 333 335 + 345 347 408 413 425 430 473 476 478 486 489 491 531 534 + 536 546 548 555 558 560 570 572 634 639 651 656 740 742 + 743 744 745 746 747 758 760 761 762 763 764 765 +FPR1 U 000001 1 94 249 251 262 264 307 309 321 331 333 345 409 426 474 476 + 487 489 532 534 546 556 558 570 635 652 740 742 743 744 + 745 746 747 758 760 761 762 763 764 765 +FPR10 U 00000A 1 103 +FPR11 U 00000B 1 104 +FPR12 U 00000C 1 105 +FPR13 U 00000D 1 106 +FPR14 U 00000E 1 107 +FPR15 U 00000F 1 108 +FPR2 U 000002 1 95 250 251 254 263 264 267 308 309 312 321 332 333 336 345 + 410 414 427 431 475 476 479 488 489 492 533 534 537 546 + 557 558 561 570 636 640 653 657 740 742 743 744 745 746 + 747 758 760 761 762 763 764 765 +FPR3 U 000003 1 96 +FPR4 U 000004 1 97 +FPR5 U 000005 1 98 +FPR6 U 000006 1 99 +FPR7 U 000007 1 100 +FPR8 U 000008 1 101 +FPR9 U 000009 1 102 +HARDWAIT X 000268 8 179 146 +IMAGE 1 000000 3860 0 +LBFPCT U 000260 1 1403 217 +LBFPFLGS U 00AC00 0 1485 220 +LBFPIN F 000BF4 4 1265 1403 218 +LBFPINRM F 000E54 4 1416 1453 224 +LBFPNFCT U 000200 1 1254 211 +LBFPNFFL U 001700 0 1465 214 +LBFPNFIN F 0009F4 4 1143 1254 212 +LBFPNFOT U 001300 0 1463 213 + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 34 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +LBFPOUT U 00B000 0 1483 219 +LBFPRMCT U 0000C0 1 1453 223 +LBFPRMO U 005000 0 1473 225 +LBFPRMOF U 009000 0 1475 226 +LONGF F 000340 4 216 168 +LONGNF F 000330 4 210 166 +PCINTCD H 00008E 2 123 140 +PCNOTDTA H 00020C 2 143 141 +PCOLDPSW U 000150 0 125 142 +PROGCHK H 000200 2 139 131 +R0 U 000000 1 74 155 157 256 257 258 269 270 271 314 315 316 325 326 327 + 338 339 340 349 350 351 416 417 418 433 434 435 481 482 + 483 494 495 496 539 540 541 550 551 552 563 564 565 574 + 575 576 642 643 644 659 660 661 +R1 U 000001 1 75 389 398 406 407 411 412 423 424 428 429 613 622 623 624 + 632 633 637 638 649 650 654 655 +R10 U 00000A 1 84 159 161 163 166 168 170 241 242 299 300 385 386 466 467 + 524 525 609 610 +R11 U 00000B 1 85 +R12 U 00000C 1 86 245 276 303 357 390 450 470 501 528 581 614 676 +R13 U 00000D 1 87 160 162 164 167 169 171 244 277 302 358 388 452 469 502 + 527 582 612 678 +R14 U 00000E 1 88 144 145 173 174 +R15 U 00000F 1 89 110 +R2 U 000002 1 76 241 243 276 299 301 357 385 387 450 466 468 501 524 526 + 581 609 611 676 +R3 U 000003 1 77 241 248 249 261 262 273 299 306 307 330 331 354 385 408 + 409 425 426 449 466 473 474 486 487 498 524 531 532 555 + 556 578 609 634 635 651 652 675 +R4 U 000004 1 78 400 411 428 440 626 637 654 666 +R5 U 000005 1 79 392 398 406 423 444 616 622 632 649 670 +R6 U 000006 1 80 401 440 627 666 +R7 U 000007 1 81 242 253 254 266 267 274 300 311 312 323 335 336 347 355 + 386 413 414 430 431 437 467 478 479 491 492 499 525 536 + 537 548 560 561 572 579 610 639 640 656 657 663 +R8 U 000008 1 82 242 255 258 268 271 275 300 313 316 324 327 337 340 348 + 351 356 386 415 418 432 435 438 467 480 483 493 496 500 + 525 538 541 549 552 562 565 573 576 580 610 641 644 658 + 661 664 +R9 U 000009 1 83 393 444 617 670 +RMLONGS F 000350 4 222 170 +RMSHORTS F 000320 4 204 163 +SBFPCT U 000158 1 1080 199 +SBFPFLGS U 00A800 0 1480 202 +SBFPIN F 00083C 4 923 1080 200 +SBFPINRM F 000994 4 1093 1118 206 +SBFPNFCT U 000100 1 912 193 +SBFPNFFL U 001200 0 1460 196 +SBFPNFIN F 00073C 4 796 912 194 +SBFPNFOT U 001000 0 1458 195 +SBFPOUT U 00A000 0 1478 201 +SBFPRMCT U 000060 1 1118 205 + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 35 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +SBFPRMO U 002000 0 1468 207 +SBFPRMOF U 004000 0 1470 208 +SHORTF F 000310 4 198 161 +SHORTNF F 000300 4 192 159 +START H 000214 2 154 128 +WAITPSW X 000258 8 178 175 + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 36 + + MACRO DEFN REFERENCES + +PADCSECT 48 1490 + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 37 + + DESC SYMBOL SIZE POS ADDR + +Entry: 0 + +Image IMAGE 3860 000-F13 000-F13 + Region 3860 000-F13 000-F13 + CSECT BFPDV2NT 3860 000-F13 000-F13 + ASMA Ver. 0.2.0 ieee-divtoint.asm: Test IEEE Divide To Integer 31 Aug 2016 07:04:20 Page 38 + + STMT FILE NAME + +1 C:\Users\srorso\Documents\GitHub\hyperion\tests\bfp-001-divtoint.asm + + +** NO ERRORS FOUND ** + +[1491] MNOTE *,asma detected; no CSECT padding performed + \ No newline at end of file diff --git a/tests/bfp-001-divtoint.tst b/tests/bfp-001-divtoint.tst new file mode 100644 index 000000000..dc1f5bf32 --- /dev/null +++ b/tests/bfp-001-divtoint.tst @@ -0,0 +1,3348 @@ +*Testcase bfp-001-divtoint.tst: DIEBR, DIDBR + +#Testcase bfp-001-divtoint.tst: DIVIDE TO INTEGER (2) +#..Test cases evaluate NaN propagation, NaN generation, operations +#..using non-finite values, and exhaustive rounding testing of +#..operations on finite values. + +sysclear +archmode esame + +# +# Following suppresses logging of program checks. This test program, as part +# of its normal operation, generates 46 program check messages that have no +# value in the validation process. +# +ostailor quiet + +loadcore "$(testpath)/bfp-001-divtoint.core" + +runtest 1.0 + +ostailor null # restore messages for subsequent tests + + +# NaN propagation tests - BFP Short +*Compare +r 1000.10 # Expecting QNaN A +*Want "DIEBR test 1 NaN" 7FCA0000 7FCA0000 7F8A0000 00000000 +r 1010.10 # Expecting QNaN A +*Want "DIEBR test 2 NaN" 7FCA0000 7FCA0000 7FCA0000 7FCA0000 +r 1020.10 # Expecting QNaN B +*Want "DIEBR test 3 NaN" 7FCB0000 7FCB0000 7FCB0000 7FCB0000 +r 1030.10 # Expecting QNaN B +*Want "DIEBR test 4 NaN" 7FCB0000 7FCB0000 7FCA0000 00000000 + + +# Dividend -inf - BFP Short - all should be dNaN (a +QNaN) +r 1040.10 +*Want "DIEBR test 5 -inf dividend" 7FC00000 7FC00000 FF800000 00000000 +r 1050.10 +*Want "DIEBR test 6 -inf dividend" 7FC00000 7FC00000 FF800000 00000000 +r 1060.10 +*Want "DIEBR test 7 -inf dividend" 7FC00000 7FC00000 FF800000 00000000 +r 1070.10 +*Want "DIEBR test 8 -inf dividend" 7FC00000 7FC00000 FF800000 00000000 +r 1080.10 +*Want "DIEBR test 9 -inf dividend" 7FC00000 7FC00000 FF800000 00000000 +r 1090.10 +*Want "DIEBR test 10 -inf dividend" 7FC00000 7FC00000 FF800000 00000000 + +# Dividend +inf - BFP Short - all should be dNaN (a +QNaN) +r 10A0.10 +*Want "DIEBR test 11 +inf dividend" 7FC00000 7FC00000 7F800000 00000000 +r 10B0.10 +*Want "DIEBR test 12 +inf dividend" 7FC00000 7FC00000 7F800000 00000000 +r 10C0.10 +*Want "DIEBR test 13 +inf dividend" 7FC00000 7FC00000 7F800000 00000000 +r 10D0.10 +*Want "DIEBR test 14 +inf dividend" 7FC00000 7FC00000 7F800000 00000000 +r 10E0.10 +*Want "DIEBR test 15 +inf dividend" 7FC00000 7FC00000 7F800000 00000000 +r 10F0.10 +*Want "DIEBR test 16 +inf dividend" 7FC00000 7FC00000 7F800000 00000000 + + +# Divisor -0 - BFP Short - all should be dNaN (a +QNaN) +r 1100.10 +*Want "DIEBR test 17 -0 divisor" 7FC00000 7FC00000 C0000000 00000000 +r 1110.10 +*Want "DIEBR test 18 -0 divisor" 7FC00000 7FC00000 80000000 00000000 +r 1120.10 +*Want "DIEBR test 19 -0 divisor" 7FC00000 7FC00000 00000000 00000000 +r 1130.10 +*Want "DIEBR test 20 -0 divisor" 7FC00000 7FC00000 40000000 00000000 + +# Divisor +0 - BFP Short - all should be dNaN (a +QNaN) +r 1140.10 +*Want "DIEBR test 21 +0 divisor" 7FC00000 7FC00000 C0000000 00000000 +r 1150.10 +*Want "DIEBR test 22 +0 divisor" 7FC00000 7FC00000 80000000 00000000 +r 1160.10 +*Want "DIEBR test 23 +0 divisor" 7FC00000 7FC00000 00000000 00000000 +r 1170.10 +*Want "DIEBR test 24 +0 divisor" 7FC00000 7FC00000 40000000 00000000 + + +# Divisor -inf - BFP Short, remainder dividend, quotient zero, +r 1180.10 +*Want "DIEBR test 25 -inf divisor" C0000000 00000000 C0000000 00000000 +r 1190.10 +*Want "DIEBR test 26 -inf divisor" 80000000 00000000 80000000 00000000 +r 11A0.10 +*Want "DIEBR test 27 -inf divisor" 00000000 80000000 00000000 80000000 +r 11B0.10 +*Want "DIEBR test 28 -inf divisor" 40000000 80000000 40000000 80000000 + + +# Divisor +inf - BFP Short - all should be dNaN (a +QNaN) +r 11C0.10 +*Want "DIEBR test 29 +inf divisor" C0000000 80000000 C0000000 80000000 +r 11D0.10 +*Want "DIEBR test 30 +inf divisor" 80000000 80000000 80000000 80000000 +r 11E0.10 +*Want "DIEBR test 31 +inf divisor" 00000000 00000000 00000000 00000000 +r 11F0.10 +*Want "DIEBR test 32 +inf divisor" 40000000 00000000 40000000 00000000 + +*Compare +# NaN propagation tests - BFP Short - FPCR & cc +r 1200.10 +*Want "DIEBR FPCR pair NaN 1-2" 00800001 F8008001 00000001 F8000001 +r 1210.10 +*Want "DIEBR FPCR pair NaN 4-4" 00000001 F8000001 00800001 F8008001 + + +# Dividend -inf - BFP Short - FPCR & cc +r 1220.10 +*Want "DIEBR FPCR pair -inf 5-6" 00800001 F8008001 00800001 F8008001 +r 1230.10 +*Want "DIEBR FPCR pair -inf 7-8" 00800001 F8008001 00800001 F8008001 +r 1240.10 +*Want "DIEBR FPCR pair -inf 9-10" 00800001 F8008001 00800001 F8008001 + + +# Dividend +inf - BFP Short - FPCR & cc +r 1250.10 +*Want "DIEBR FPCR pair +inf 11-12" 00800001 F8008001 00800001 F8008001 +r 1260.10 +*Want "DIEBR FPCR pair +inf 13-14" 00800001 F8008001 00800001 F8008001 +r 1270.10 +*Want "DIEBR FPCR pair +inf 15-16" 00800001 F8008001 00800001 F8008001 + + +# Divisor -0 - BFP Short - FPCR & cc +r 1280.10 +*Want "DIEBR FPCR pair -0 17-18" 00800001 F8008001 00800001 F8008001 +r 1290.10 +*Want "DIEBR FPCR pair -0 19-20" 00800001 F8008001 00800001 F8008001 + +# Divisor +0 - BFP Short - FPCR & cc +r 12A0.10 +*Want "DIEBR FPCR pair +0 21-22" 00800001 F8008001 00800001 F8008001 +r 12B0.10 +*Want "DIEBR FPCR pair +0 23-24" 00800001 F8008001 00800001 F8008001 + + +# Divisor -inf - BFP Short - FPCR & cc +r 12C0.10 +*Want "DIEBR FPCR pair div -inf 25-26" 00000000 F8000000 00000000 F8000000 +r 12D0.10 +*Want "DIEBR FPCR pair div -inf 27-28" 00000000 F8000000 00000000 F8000000 + +# Divisor +inf - BFP Short - FPCR & cc +r 12E0.10 +*Want "DIEBR FPCR pair div +inf 29-30" 00000000 F8000000 00000000 F8000000 +r 12F0.10 +*Want "DIEBR FPCR pair div +inf 31-32" 00000000 F8000000 00000000 F8000000 + + + +# Dividend & Divisor finite - BFP Short - basic tests +r A000.0C +*Want "DIEBR finite test -8/-4 1a" 80000000 40000000 C1000000 +r A010.0C +*Want "DIEBR finite test -8/-4 1b" 80000000 40000000 C1000000 +r A020.0C +*Want "DIEBR finite test -7/-4 2a" 3F800000 40000000 C0E00000 +r A030.0C +*Want "DIEBR finite test -7/-4 2b" 3F800000 40000000 C0E00000 +r A040.0C +*Want "DIEBR finite test -6/-4 3a" 40000000 40000000 C0C00000 +r A050.0C +*Want "DIEBR finite test -6/-4 3b" 40000000 40000000 C0C00000 +r A060.0C +*Want "DIEBR finite test -5/-4 4a" BF800000 3F800000 C0A00000 +r A070.0C +*Want "DIEBR finite test -5/-4 4b" BF800000 3F800000 C0A00000 +r A080.0C +*Want "DIEBR finite test -4/-4 5a" 80000000 3F800000 C0800000 +r A090.0C +*Want "DIEBR finite test -4/-4 5b" 80000000 3F800000 C0800000 +r A0A0.0C +*Want "DIEBR finite test -3/-4 6a" 3F800000 3F800000 C0400000 +r A0B0.0C +*Want "DIEBR finite test -3/-4 6b" 3F800000 3F800000 C0400000 +r A0C0.0C +*Want "DIEBR finite test -2/-4 7a" C0000000 00000000 C0000000 +r A0D0.0C +*Want "DIEBR finite test -2/-4 7b" C0000000 00000000 C0000000 +r A0E0.0C +*Want "DIEBR finite test -1/-4 8a" BF800000 00000000 BF800000 +r A0F0.0C +*Want "DIEBR finite test -1/-4 8b" BF800000 00000000 BF800000 +r A100.0C +*Want "DIEBR finite test +1/-4 9a" 3F800000 80000000 3F800000 +r A110.0C +*Want "DIEBR finite test +1/-4 9b" 3F800000 80000000 3F800000 +r A120.0C +*Want "DIEBR finite test +2/-4 10a" 40000000 80000000 40000000 +r A130.0C +*Want "DIEBR finite test +2/-4 10b" 40000000 80000000 40000000 +r A140.0C +*Want "DIEBR finite test +3/-4 11a" BF800000 BF800000 40400000 +r A150.0C +*Want "DIEBR finite test +3/-4 11b" BF800000 BF800000 40400000 +r A160.0C +*Want "DIEBR finite test +4/-4 12a" 00000000 BF800000 40800000 +r A170.0C +*Want "DIEBR finite test +4/-4 12b" 00000000 BF800000 40800000 +r A180.0C +*Want "DIEBR finite test +5/-4 13a" 3F800000 BF800000 40A00000 +r A190.0C +*Want "DIEBR finite test +5/-4 13b" 3F800000 BF800000 40A00000 +r A1A0.0C +*Want "DIEBR finite test +6/-4 14a" C0000000 C0000000 40C00000 +r A1B0.0C +*Want "DIEBR finite test +6/-4 14b" C0000000 C0000000 40C00000 +r A1C0.0C +*Want "DIEBR finite test 15a" BF800000 C0000000 40E00000 +r A1D0.0C +*Want "DIEBR finite test 15b" BF800000 C0000000 40E00000 +r A1E0.0C +*Want "DIEBR finite test 16a" 00000000 C0000000 41000000 +r A1F0.0C +*Want "DIEBR finite test 16b" 00000000 C0000000 41000000 +r A200.0C +*Want "DIEBR finite test 17a" 80000000 C0000000 C1000000 +r A210.0C +*Want "DIEBR finite test 17b" 80000000 C0000000 C1000000 +r A220.0C +*Want "DIEBR finite test 18a" 3F800000 C0000000 C0E00000 +r A230.0C +*Want "DIEBR finite test 18b" 3F800000 C0000000 C0E00000 +r A240.0C +*Want "DIEBR finite test 19a" 40000000 C0000000 C0C00000 +r A250.0C +*Want "DIEBR finite test 19b" 40000000 C0000000 C0C00000 +r A260.0C +*Want "DIEBR finite test 20a" BF800000 BF800000 C0A00000 +r A270.0C +*Want "DIEBR finite test 20b" BF800000 BF800000 C0A00000 +r A280.0C +*Want "DIEBR finite test 21a" 80000000 BF800000 C0800000 +r A290.0C +*Want "DIEBR finite test 21b" 80000000 BF800000 C0800000 +r A2A0.0C +*Want "DIEBR finite test 22a" 3F800000 BF800000 C0400000 +r A2B0.0C +*Want "DIEBR finite test 22b" 3F800000 BF800000 C0400000 +r A2C0.0C +*Want "DIEBR finite test 23a" C0000000 80000000 C0000000 +r A2D0.0C +*Want "DIEBR finite test 23b" C0000000 80000000 C0000000 +r A2E0.0C +*Want "DIEBR finite test 24a" 3F800000 00000000 3F800000 +r A2F0.0C +*Want "DIEBR finite test 24b" 3F800000 00000000 3F800000 +r A300.0C +*Want "DIEBR finite test 25a" 3F800000 00000000 3F800000 +r A310.0C +*Want "DIEBR finite test 25b" 3F800000 00000000 3F800000 +r A320.0C +*Want "DIEBR finite test 26a" 40000000 00000000 40000000 +r A330.0C +*Want "DIEBR finite test 26b" 40000000 00000000 40000000 +r A340.0C +*Want "DIEBR finite test 27a" BF800000 3F800000 40400000 +r A350.0C +*Want "DIEBR finite test 27b" BF800000 3F800000 40400000 +r A360.0C +*Want "DIEBR finite test 28a" 00000000 3F800000 40800000 +r A370.0C +*Want "DIEBR finite test 28b" 00000000 3F800000 40800000 +r A380.0C +*Want "DIEBR finite test 29a" 3F800000 3F800000 40A00000 +r A390.0C +*Want "DIEBR finite test 29b" 3F800000 3F800000 40A00000 +r A3A0.0C +*Want "DIEBR finite test 30a" C0000000 40000000 40C00000 +r A3B0.0C +*Want "DIEBR finite test 30b" C0000000 40000000 40C00000 +r A3C0.0C +*Want "DIEBR finite test 31a" BF800000 40000000 40E00000 +r A3D0.0C +*Want "DIEBR finite test 31b" BF800000 40000000 40E00000 +r A3E0.0C +*Want "DIEBR finite test 32a" 00000000 40000000 41000000 +r A3F0.0C +*Want "DIEBR finite test 32b" 00000000 40000000 41000000 + + +r A400.0C # results validated on z/12 +*Want "DIEBR test 33a two finites" 40800000 C0800000 42200000 +r A410.0C # results validated on z/12 +*Want "DIEBR test 33b two finites" 40800000 C0800000 42200000 + +r A420.0C # third result differs from dividend due to scaling of overflowed quotient +# results validated on z/12 +*Want "DIEBR test 34a two finites" 00000000 69FFFFFF 1F7FFFFF +r A430.0C # third result differs from dividend due to scaling of overflowed quotient +# results validated on z/12 +*Want "DIEBR test 34b two finites" 00000000 69FFFFFF 1F7FFFFF + +r A440.0C +*Want "DIEBR test 35a two finites" 00000001 3F800000 00FFFFFF +r A450.0C +# results validated on z/12 +*Want "DIEBR test 35b two finites" 55000000 3F800000 55000000 + +r A460.0C +# # Very big number divided by 3 gives remainder 4. The oddities of partial results +# results validated on z/12 +*Want "DIEBR test 36a two finites" 40800000 4BAAAAAA 4C800000 +r A470.0C +# # Very big number divided by 3 gives remainder 4. The oddities of partial results +# results validated on z/12 +*Want "DIEBR test 36b two finites" 40800000 4BAAAAAA 4C800000 + +r A480.0C +*Want "DIEBR test 37a two finites" 40100000 00000000 40100000 +r A490.0C +*Want "DIEBR test 37b two finites" 40100000 00000000 40100000 + +r A4A0.0C # Not sure following two are correct; need hardware validation +# # Hyperion results differ in the multiply-add to get the original dividend +# # *Want reflects z/12 result +*Want "DIEBR test 38a two finites" 73A00000 683A2E8A 73A00000 +#Want "DIEBR test 38a two finites" 64A00000 683A2E8A 1F7FFFFF <--what I thought I would get +r A4B0.0C # Not sure following two are correct; need hardware validation +# # Hyperion results differ in the multiply-add to get the original dividend +# # *Want reflects z/12 result +*Want "DIEBR test 38a two finites" 73A00000 683A2E8A 73A00000 +#Want "DIEBR test 38a two finites" 64A00000 683A2E8A 1F7FFFFF <--what I thought I would get + + +*Compare +# Two finites - BFP Short - FPCR & cc (cc unchanged by re-multiply) +r A800.10 +*Want "DIEBR FPCR finite test -8/-4 1" 00000000 00000000 F8000000 00000000 +r A810.10 +*Want "DIEBR FPCR finite test -7/-4 2" 00000000 00000000 F8000000 00000000 +r A820.10 +*Want "DIEBR FPCR finite test -6/-4 3" 00000000 00000000 F8000000 00000000 +r A830.10 +*Want "DIEBR FPCR finite test -5/-4 4" 00000000 00000000 F8000000 00000000 +r A840.10 +*Want "DIEBR FPCR finite test -4/-4 5" 00000000 00000000 F8000000 00000000 +r A850.10 +*Want "DIEBR FPCR finite test -3/-4 6" 00000000 00000000 F8000000 00000000 +r A860.10 +*Want "DIEBR FPCR finite test -2/-4 7" 00000000 00000000 F8000000 00000000 +r A870.10 +*Want "DIEBR FPCR finite test -1/-4 8" 00000000 00000000 F8000000 00000000 +r A880.10 +*Want "DIEBR FPCR finite test +1/-4 9" 00000000 00000000 F8000000 00000000 +r A890.10 +*Want "DIEBR FPCR finite test +2/-4 10" 00000000 00000000 F8000000 00000000 +r A8A0.10 +*Want "DIEBR FPCR finite test +3/-4 11" 00000000 00000000 F8000000 00000000 +r A8B0.10 +*Want "DIEBR FPCR finite test +4/-4 12" 00000000 00000000 F8000000 00000000 +r A8C0.10 +*Want "DIEBR FPCR finite test +5/-4 13" 00000000 00000000 F8000000 00000000 +r A8D0.10 +*Want "DIEBR FPCR finite test +6/-4 14" 00000000 00000000 F8000000 00000000 +r A8E0.10 +*Want "DIEBR FPCR finite test 15" 00000000 00000000 F8000000 00000000 +r A8F0.10 +*Want "DIEBR FPCR finite test 16" 00000000 00000000 F8000000 00000000 +r A900.10 +*Want "DIEBR FPCR finite test 17" 00000000 00000000 F8000000 00000000 +r A910.10 +*Want "DIEBR FPCR finite test 18" 00000000 00000000 F8000000 00000000 +r A920.10 +*Want "DIEBR FPCR finite test 19" 00000000 00000000 F8000000 00000000 +r A930.10 +*Want "DIEBR FPCR finite test 20" 00000000 00000000 F8000000 00000000 +r A940.10 +*Want "DIEBR FPCR finite test 21" 00000000 00000000 F8000000 00000000 +r A950.10 +*Want "DIEBR FPCR finite test 22" 00000000 00000000 F8000000 00000000 +r A960.10 +*Want "DIEBR FPCR finite test 23" 00000000 00000000 F8000000 00000000 +r A970.10 +*Want "DIEBR FPCR finite test 24" 00000000 00000000 F8000000 00000000 +r A980.10 +*Want "DIEBR FPCR finite test 25" 00000000 00000000 F8000000 00000000 +r A990.10 +*Want "DIEBR FPCR finite test 26" 00000000 00000000 F8000000 00000000 +r A9A0.10 +*Want "DIEBR FPCR finite test 27" 00000000 00000000 F8000000 00000000 +r A9B0.10 +*Want "DIEBR FPCR finite test 28" 00000000 00000000 F8000000 00000000 +r A9C0.10 +*Want "DIEBR FPCR finite test 29" 00000000 00000000 F8000000 00000000 +r A9D0.10 +*Want "DIEBR FPCR finite test 30" 00000000 00000000 F8000000 00000000 +r A9E0.10 +*Want "DIEBR FPCR finite test 31" 00000000 00000000 F8000000 00000000 +r A9F0.10 +*Want "DIEBR FPCR finite test 32" 00000000 00000000 F8000000 00000000 + +r AA00.10 +*Want "DIEBR FPCR finite test 33" 00000000 00000000 F8000000 00000000 +r AA10.10 +*Want "DIEBR FPCR finite test 34" 00000001 00000001 F8000001 00000001 +r AA20.10 +# Apparently, on z/12 trappable pair four triggers underflow trap, scaled remainder. +*Want "DIEBR FPCR finite test 35" 00000000 00000000 F8001000 00080000 +r AA30.10 +*Want "DIEBR FPCR finite test 36" 00000002 00000002 F8000002 00000002 +r AA40.10 +*Want "DIEBR FPCR finite test 37" 00000000 00000000 F8000000 00000000 +r AA50.10 +*Want "DIEBR FPCR finite test 38" 00000003 00080003 F8000003 00080003 + + +r 2000.10 # RZ / RNTA +*Want "DIEBR Rounding case 1a" 3F800000 C1200000 3F800000 C1200000 +r 2010.10 # RZ / RFS +*Want "DIEBR Rounding case 1b" BF800000 C1100000 BF800000 C1100000 +r 2020.10 # RZ / RNTE +*Want "DIEBR Rounding case 1c" 3F800000 C1200000 3F800000 C1200000 +r 2030.10 # RZ / RZ +*Want "DIEBR Rounding case 1d" BF800000 C1100000 BF800000 C1100000 +r 2040.10 # RZ / RP +*Want "DIEBR Rounding case 1e" BF800000 C1100000 BF800000 C1100000 +r 2050.10 # RZ / RM +*Want "DIEBR Rounding case 1f" 3F800000 C1200000 3F800000 C1200000 +r 2060.10 # RP / RNTA +*Want "DIEBR Rounding case 1g" 3F800000 C1200000 3F800000 C1200000 +r 2070.10 # RP / RFS +*Want "DIEBR Rounding case 1h" BF800000 C1100000 BF800000 C1100000 +r 2080.10 # RP / RNTE +*Want "DIEBR Rounding case 1i" 3F800000 C1200000 3F800000 C1200000 +r 2090.10 # RP / RZ +*Want "DIEBR Rounding case 1j" BF800000 C1100000 BF800000 C1100000 +r 20A0.10 # RP / RP +*Want "DIEBR Rounding case 1k" BF800000 C1100000 BF800000 C1100000 +r 20B0.10 # RP / RM +*Want "DIEBR Rounding case 1l" 3F800000 C1200000 3F800000 C1200000 +r 20C0.10 # RM / RNTA +*Want "DIEBR Rounding case 1m" 3F800000 C1200000 3F800000 C1200000 +r 20D0.10 # RM / RFS +*Want "DIEBR Rounding case 1n" BF800000 C1100000 BF800000 C1100000 +r 20E0.10 # RM / RNTE +*Want "DIEBR Rounding case 1o" 3F800000 C1200000 3F800000 C1200000 +r 20F0.10 # RM / RZ +*Want "DIEBR Rounding case 1p" BF800000 C1100000 BF800000 C1100000 +r 2100.10 # RM / RP +*Want "DIEBR Rounding case 1q" BF800000 C1100000 BF800000 C1100000 +r 2110.10 # RM / RM +*Want "DIEBR Rounding case 1r" 3F800000 C1200000 3F800000 C1200000 +r 2120.10 # RFS / RNTA +*Want "DIEBR Rounding case 1s" 3F800000 C1200000 3F800000 C1200000 +r 2130.10 # RFS / RFS +*Want "DIEBR Rounding case 1t" BF800000 C1100000 BF800000 C1100000 +r 2140.10 # RFS / RNTE +*Want "DIEBR Rounding case 1u" 3F800000 C1200000 3F800000 C1200000 +r 2150.10 # RFS / RZ +*Want "DIEBR Rounding case 1v" BF800000 C1100000 BF800000 C1100000 +r 2160.10 # RFS / RP +*Want "DIEBR Rounding case 1w" BF800000 C1100000 BF800000 C1100000 +r 2170.10 # RFS / RM +*Want "DIEBR Rounding case 1x" 3F800000 C1200000 3F800000 C1200000 +r 2180.10 # RZ / RNTA +*Want "DIEBR Rounding case 2a" 3F800000 C0C00000 3F800000 C0C00000 +r 2190.10 # RZ / RFS +*Want "DIEBR Rounding case 2b" BF800000 C0A00000 BF800000 C0A00000 +r 21A0.10 # RZ / RNTE +*Want "DIEBR Rounding case 2c" 3F800000 C0C00000 3F800000 C0C00000 +r 21B0.10 # RZ / RZ +*Want "DIEBR Rounding case 2d" BF800000 C0A00000 BF800000 C0A00000 +r 21C0.10 # RZ / RP +*Want "DIEBR Rounding case 2e" BF800000 C0A00000 BF800000 C0A00000 +r 21D0.10 # RZ / RM +*Want "DIEBR Rounding case 2f" 3F800000 C0C00000 3F800000 C0C00000 +r 21E0.10 # RP / RNTA +*Want "DIEBR Rounding case 2g" 3F800000 C0C00000 3F800000 C0C00000 +r 21F0.10 # RP / RFS +*Want "DIEBR Rounding case 2h" BF800000 C0A00000 BF800000 C0A00000 +r 2200.10 # RP / RNTE +*Want "DIEBR Rounding case 2i" 3F800000 C0C00000 3F800000 C0C00000 +r 2210.10 # RP / RZ +*Want "DIEBR Rounding case 2j" BF800000 C0A00000 BF800000 C0A00000 +r 2220.10 # RP / RP +*Want "DIEBR Rounding case 2k" BF800000 C0A00000 BF800000 C0A00000 +r 2230.10 # RP / RM +*Want "DIEBR Rounding case 2l" 3F800000 C0C00000 3F800000 C0C00000 +r 2240.10 # RM / RNTA +*Want "DIEBR Rounding case 2m" 3F800000 C0C00000 3F800000 C0C00000 +r 2250.10 # RM / RFS +*Want "DIEBR Rounding case 2n" BF800000 C0A00000 BF800000 C0A00000 +r 2260.10 # RM / RNTE +*Want "DIEBR Rounding case 2o" 3F800000 C0C00000 3F800000 C0C00000 +r 2270.10 # RM / RZ +*Want "DIEBR Rounding case 2p" BF800000 C0A00000 BF800000 C0A00000 +r 2280.10 # RM / RP +*Want "DIEBR Rounding case 2q" BF800000 C0A00000 BF800000 C0A00000 +r 2290.10 # RM / RM +*Want "DIEBR Rounding case 2r" 3F800000 C0C00000 3F800000 C0C00000 +r 22A0.10 # RFS / RNTA +*Want "DIEBR Rounding case 2s" 3F800000 C0C00000 3F800000 C0C00000 +r 22B0.10 # RFS / RFS +*Want "DIEBR Rounding case 2t" BF800000 C0A00000 BF800000 C0A00000 +r 22C0.10 # RFS / RNTE +*Want "DIEBR Rounding case 2u" 3F800000 C0C00000 3F800000 C0C00000 +r 22D0.10 # RFS / RZ +*Want "DIEBR Rounding case 2v" BF800000 C0A00000 BF800000 C0A00000 +r 22E0.10 # RFS / RP +*Want "DIEBR Rounding case 2w" BF800000 C0A00000 BF800000 C0A00000 +r 22F0.10 # RFS / RM +*Want "DIEBR Rounding case 2x" 3F800000 C0C00000 3F800000 C0C00000 +r 2300.10 # RZ / RNTA +*Want "DIEBR Rounding case 3a" 3F800000 C0400000 3F800000 C0400000 +r 2310.10 # RZ / RFS +*Want "DIEBR Rounding case 3b" 3F800000 C0400000 3F800000 C0400000 +r 2320.10 # RZ / RNTE +*Want "DIEBR Rounding case 3c" BF800000 C0000000 BF800000 C0000000 +r 2330.10 # RZ / RZ +*Want "DIEBR Rounding case 3d" BF800000 C0000000 BF800000 C0000000 +r 2340.10 # RZ / RP +*Want "DIEBR Rounding case 3e" BF800000 C0000000 BF800000 C0000000 +r 2350.10 # RZ / RM +*Want "DIEBR Rounding case 3f" 3F800000 C0400000 3F800000 C0400000 +r 2360.10 # RP / RNTA +*Want "DIEBR Rounding case 3g" 3F800000 C0400000 3F800000 C0400000 +r 2370.10 # RP / RFS +*Want "DIEBR Rounding case 3h" 3F800000 C0400000 3F800000 C0400000 +r 2380.10 # RP / RNTE +*Want "DIEBR Rounding case 3i" BF800000 C0000000 BF800000 C0000000 +r 2390.10 # RP / RZ +*Want "DIEBR Rounding case 3j" BF800000 C0000000 BF800000 C0000000 +r 23A0.10 # RP / RP +*Want "DIEBR Rounding case 3k" BF800000 C0000000 BF800000 C0000000 +r 23B0.10 # RP / RM +*Want "DIEBR Rounding case 3l" 3F800000 C0400000 3F800000 C0400000 +r 23C0.10 # RM / RNTA +*Want "DIEBR Rounding case 3m" 3F800000 C0400000 3F800000 C0400000 +r 23D0.10 # RM / RFS +*Want "DIEBR Rounding case 3n" 3F800000 C0400000 3F800000 C0400000 +r 23E0.10 # RM / RNTE +*Want "DIEBR Rounding case 3o" BF800000 C0000000 BF800000 C0000000 +r 23F0.10 # RM / RZ +*Want "DIEBR Rounding case 3p" BF800000 C0000000 BF800000 C0000000 +r 2400.10 # RM / RP +*Want "DIEBR Rounding case 3q" BF800000 C0000000 BF800000 C0000000 +r 2410.10 # RM / RM +*Want "DIEBR Rounding case 3r" 3F800000 C0400000 3F800000 C0400000 +r 2420.10 # RFS / RNTA +*Want "DIEBR Rounding case 3s" 3F800000 C0400000 3F800000 C0400000 +r 2430.10 # RFS / RFS +*Want "DIEBR Rounding case 3t" 3F800000 C0400000 3F800000 C0400000 +r 2440.10 # RFS / RNTE +*Want "DIEBR Rounding case 3u" BF800000 C0000000 BF800000 C0000000 +r 2450.10 # RFS / RZ +*Want "DIEBR Rounding case 3v" BF800000 C0000000 BF800000 C0000000 +r 2460.10 # RFS / RP +*Want "DIEBR Rounding case 3w" BF800000 C0000000 BF800000 C0000000 +r 2470.10 # RFS / RM +*Want "DIEBR Rounding case 3x" 3F800000 C0400000 3F800000 C0400000 +r 2480.10 # RZ / RNTA +*Want "DIEBR Rounding case 4a" 3F800000 C0000000 3F800000 C0000000 +r 2490.10 # RZ / RFS +*Want "DIEBR Rounding case 4b" BF800000 BF800000 BF800000 BF800000 +r 24A0.10 # RZ / RNTE +*Want "DIEBR Rounding case 4c" 3F800000 C0000000 3F800000 C0000000 +r 24B0.10 # RZ / RZ +*Want "DIEBR Rounding case 4d" BF800000 BF800000 BF800000 BF800000 +r 24C0.10 # RZ / RP +*Want "DIEBR Rounding case 4e" BF800000 BF800000 BF800000 BF800000 +r 24D0.10 # RZ / RM +*Want "DIEBR Rounding case 4f" 3F800000 C0000000 3F800000 C0000000 +r 24E0.10 # RP / RNTA +*Want "DIEBR Rounding case 4g" 3F800000 C0000000 3F800000 C0000000 +r 24F0.10 # RP / RFS +*Want "DIEBR Rounding case 4h" BF800000 BF800000 BF800000 BF800000 +r 2500.10 # RP / RNTE +*Want "DIEBR Rounding case 4i" 3F800000 C0000000 3F800000 C0000000 +r 2510.10 # RP / RZ +*Want "DIEBR Rounding case 4j" BF800000 BF800000 BF800000 BF800000 +r 2520.10 # RP / RP +*Want "DIEBR Rounding case 4k" BF800000 BF800000 BF800000 BF800000 +r 2530.10 # RP / RM +*Want "DIEBR Rounding case 4l" 3F800000 C0000000 3F800000 C0000000 +r 2540.10 # RM / RNTA +*Want "DIEBR Rounding case 4m" 3F800000 C0000000 3F800000 C0000000 +r 2550.10 # RM / RFS +*Want "DIEBR Rounding case 4n" BF800000 BF800000 BF800000 BF800000 +r 2560.10 # RM / RNTE +*Want "DIEBR Rounding case 4o" 3F800000 C0000000 3F800000 C0000000 +r 2570.10 # RM / RZ +*Want "DIEBR Rounding case 4p" BF800000 BF800000 BF800000 BF800000 +r 2580.10 # RM / RP +*Want "DIEBR Rounding case 4q" BF800000 BF800000 BF800000 BF800000 +r 2590.10 # RM / RM +*Want "DIEBR Rounding case 4r" 3F800000 C0000000 3F800000 C0000000 +r 25A0.10 # RFS / RNTA +*Want "DIEBR Rounding case 4s" 3F800000 C0000000 3F800000 C0000000 +r 25B0.10 # RFS / RFS +*Want "DIEBR Rounding case 4t" BF800000 BF800000 BF800000 BF800000 +r 25C0.10 # RFS / RNTE +*Want "DIEBR Rounding case 4u" 3F800000 C0000000 3F800000 C0000000 +r 25D0.10 # RFS / RZ +*Want "DIEBR Rounding case 4v" BF800000 BF800000 BF800000 BF800000 +r 25E0.10 # RFS / RP +*Want "DIEBR Rounding case 4w" BF800000 BF800000 BF800000 BF800000 +r 25F0.10 # RFS / RM +*Want "DIEBR Rounding case 4x" 3F800000 C0000000 3F800000 C0000000 +r 2600.10 # RZ / RNTA +*Want "DIEBR Rounding case 5a" 3F800000 BF800000 3F800000 BF800000 +r 2610.10 # RZ / RFS +*Want "DIEBR Rounding case 5b" 3F800000 BF800000 3F800000 BF800000 +r 2620.10 # RZ / RNTE +*Want "DIEBR Rounding case 5c" BF800000 80000000 BF800000 80000000 +r 2630.10 # RZ / RZ +*Want "DIEBR Rounding case 5d" BF800000 80000000 BF800000 80000000 +r 2640.10 # RZ / RP +*Want "DIEBR Rounding case 5e" BF800000 80000000 BF800000 80000000 +r 2650.10 # RZ / RM +*Want "DIEBR Rounding case 5f" 3F800000 BF800000 3F800000 BF800000 +r 2660.10 # RP / RNTA +*Want "DIEBR Rounding case 5g" 3F800000 BF800000 3F800000 BF800000 +r 2670.10 # RP / RFS +*Want "DIEBR Rounding case 5h" 3F800000 BF800000 3F800000 BF800000 +r 2680.10 # RP / RNTE +*Want "DIEBR Rounding case 5i" BF800000 80000000 BF800000 80000000 +r 2690.10 # RP / RZ +*Want "DIEBR Rounding case 5j" BF800000 80000000 BF800000 80000000 +r 26A0.10 # RP / RP +*Want "DIEBR Rounding case 5k" BF800000 80000000 BF800000 80000000 +r 26B0.10 # RP / RM +*Want "DIEBR Rounding case 5l" 3F800000 BF800000 3F800000 BF800000 +r 26C0.10 # RM / RNTA +*Want "DIEBR Rounding case 5m" 3F800000 BF800000 3F800000 BF800000 +r 26D0.10 # RM / RFS +*Want "DIEBR Rounding case 5n" 3F800000 BF800000 3F800000 BF800000 +r 26E0.10 # RM / RNTE +*Want "DIEBR Rounding case 5o" BF800000 80000000 BF800000 80000000 +r 26F0.10 # RM / RZ +*Want "DIEBR Rounding case 5p" BF800000 80000000 BF800000 80000000 +r 2700.10 # RM / RP +*Want "DIEBR Rounding case 5q" BF800000 80000000 BF800000 80000000 +r 2710.10 # RM / RM +*Want "DIEBR Rounding case 5r" 3F800000 BF800000 3F800000 BF800000 +r 2720.10 # RFS / RNTA +*Want "DIEBR Rounding case 5s" 3F800000 BF800000 3F800000 BF800000 +r 2730.10 # RFS / RFS +*Want "DIEBR Rounding case 5t" 3F800000 BF800000 3F800000 BF800000 +r 2740.10 # RFS / RNTE +*Want "DIEBR Rounding case 5u" BF800000 80000000 BF800000 80000000 +r 2750.10 # RFS / RZ +*Want "DIEBR Rounding case 5v" BF800000 80000000 BF800000 80000000 +r 2760.10 # RFS / RP +*Want "DIEBR Rounding case 5w" BF800000 80000000 BF800000 80000000 +r 2770.10 # RFS / RM +*Want "DIEBR Rounding case 5x" 3F800000 BF800000 3F800000 BF800000 +r 2780.10 # RZ / RNTA +*Want "DIEBR Rounding case 6a" BF800000 3F800000 BF800000 3F800000 +r 2790.10 # RZ / RFS +*Want "DIEBR Rounding case 6b" BF800000 3F800000 BF800000 3F800000 +r 27A0.10 # RZ / RNTE +*Want "DIEBR Rounding case 6c" 3F800000 00000000 3F800000 00000000 +r 27B0.10 # RZ / RZ +*Want "DIEBR Rounding case 6d" 3F800000 00000000 3F800000 00000000 +r 27C0.10 # RZ / RP +*Want "DIEBR Rounding case 6e" BF800000 3F800000 BF800000 3F800000 +r 27D0.10 # RZ / RM +*Want "DIEBR Rounding case 6f" 3F800000 00000000 3F800000 00000000 +r 27E0.10 # RP / RNTA +*Want "DIEBR Rounding case 6g" BF800000 3F800000 BF800000 3F800000 +r 27F0.10 # RP / RFS +*Want "DIEBR Rounding case 6h" BF800000 3F800000 BF800000 3F800000 +r 2800.10 # RP / RNTE +*Want "DIEBR Rounding case 6i" 3F800000 00000000 3F800000 00000000 +r 2810.10 # RP / RZ +*Want "DIEBR Rounding case 6j" 3F800000 00000000 3F800000 00000000 +r 2820.10 # RP / RP +*Want "DIEBR Rounding case 6k" BF800000 3F800000 BF800000 3F800000 +r 2830.10 # RP / RM +*Want "DIEBR Rounding case 6l" 3F800000 00000000 3F800000 00000000 +r 2840.10 # RM / RNTA +*Want "DIEBR Rounding case 6m" BF800000 3F800000 BF800000 3F800000 +r 2850.10 # RM / RFS +*Want "DIEBR Rounding case 6n" BF800000 3F800000 BF800000 3F800000 +r 2860.10 # RM / RNTE +*Want "DIEBR Rounding case 6o" 3F800000 00000000 3F800000 00000000 +r 2870.10 # RM / RZ +*Want "DIEBR Rounding case 6p" 3F800000 00000000 3F800000 00000000 +r 2880.10 # RM / RP +*Want "DIEBR Rounding case 6q" BF800000 3F800000 BF800000 3F800000 +r 2890.10 # RM / RM +*Want "DIEBR Rounding case 6r" 3F800000 00000000 3F800000 00000000 +r 28A0.10 # RFS / RNTA +*Want "DIEBR Rounding case 6s" BF800000 3F800000 BF800000 3F800000 +r 28B0.10 # RFS / RFS +*Want "DIEBR Rounding case 6t" BF800000 3F800000 BF800000 3F800000 +r 28C0.10 # RFS / RNTE +*Want "DIEBR Rounding case 6u" 3F800000 00000000 3F800000 00000000 +r 28D0.10 # RFS / RZ +*Want "DIEBR Rounding case 6v" 3F800000 00000000 3F800000 00000000 +r 28E0.10 # RFS / RP +*Want "DIEBR Rounding case 6w" BF800000 3F800000 BF800000 3F800000 +r 28F0.10 # RFS / RM +*Want "DIEBR Rounding case 6x" 3F800000 00000000 3F800000 00000000 +r 2900.10 # RZ / RNTA +*Want "DIEBR Rounding case 7a" BF800000 40000000 BF800000 40000000 +r 2910.10 # RZ / RFS +*Want "DIEBR Rounding case 7b" 3F800000 3F800000 3F800000 3F800000 +r 2920.10 # RZ / RNTE +*Want "DIEBR Rounding case 7c" BF800000 40000000 BF800000 40000000 +r 2930.10 # RZ / RZ +*Want "DIEBR Rounding case 7d" 3F800000 3F800000 3F800000 3F800000 +r 2940.10 # RZ / RP +*Want "DIEBR Rounding case 7e" BF800000 40000000 BF800000 40000000 +r 2950.10 # RZ / RM +*Want "DIEBR Rounding case 7f" 3F800000 3F800000 3F800000 3F800000 +r 2960.10 # RP / RNTA +*Want "DIEBR Rounding case 7g" BF800000 40000000 BF800000 40000000 +r 2970.10 # RP / RFS +*Want "DIEBR Rounding case 7h" 3F800000 3F800000 3F800000 3F800000 +r 2980.10 # RP / RNTE +*Want "DIEBR Rounding case 7i" BF800000 40000000 BF800000 40000000 +r 2990.10 # RP / RZ +*Want "DIEBR Rounding case 7j" 3F800000 3F800000 3F800000 3F800000 +r 29A0.10 # RP / RP +*Want "DIEBR Rounding case 7k" BF800000 40000000 BF800000 40000000 +r 29B0.10 # RP / RM +*Want "DIEBR Rounding case 7l" 3F800000 3F800000 3F800000 3F800000 +r 29C0.10 # RM / RNTA +*Want "DIEBR Rounding case 7m" BF800000 40000000 BF800000 40000000 +r 29D0.10 # RM / RFS +*Want "DIEBR Rounding case 7n" 3F800000 3F800000 3F800000 3F800000 +r 29E0.10 # RM / RNTE +*Want "DIEBR Rounding case 7o" BF800000 40000000 BF800000 40000000 +r 29F0.10 # RM / RZ +*Want "DIEBR Rounding case 7p" 3F800000 3F800000 3F800000 3F800000 +r 2A00.10 # RM / RP +*Want "DIEBR Rounding case 7q" BF800000 40000000 BF800000 40000000 +r 2A10.10 # RM / RM +*Want "DIEBR Rounding case 7r" 3F800000 3F800000 3F800000 3F800000 +r 2A20.10 # RFS / RNTA +*Want "DIEBR Rounding case 7s" BF800000 40000000 BF800000 40000000 +r 2A30.10 # RFS / RFS +*Want "DIEBR Rounding case 7t" 3F800000 3F800000 3F800000 3F800000 +r 2A40.10 # RFS / RNTE +*Want "DIEBR Rounding case 7u" BF800000 40000000 BF800000 40000000 +r 2A50.10 # RFS / RZ +*Want "DIEBR Rounding case 7v" 3F800000 3F800000 3F800000 3F800000 +r 2A60.10 # RFS / RP +*Want "DIEBR Rounding case 7w" BF800000 40000000 BF800000 40000000 +r 2A70.10 # RFS / RM +*Want "DIEBR Rounding case 7x" 3F800000 3F800000 3F800000 3F800000 +r 2A80.10 # RZ / RNTA +*Want "DIEBR Rounding case 8a" BF800000 40400000 BF800000 40400000 +r 2A90.10 # RZ / RFS +*Want "DIEBR Rounding case 8b" BF800000 40400000 BF800000 40400000 +r 2AA0.10 # RZ / RNTE +*Want "DIEBR Rounding case 8c" 3F800000 40000000 3F800000 40000000 +r 2AB0.10 # RZ / RZ +*Want "DIEBR Rounding case 8d" 3F800000 40000000 3F800000 40000000 +r 2AC0.10 # RZ / RP +*Want "DIEBR Rounding case 8e" BF800000 40400000 BF800000 40400000 +r 2AD0.10 # RZ / RM +*Want "DIEBR Rounding case 8f" 3F800000 40000000 3F800000 40000000 +r 2AE0.10 # RP / RNTA +*Want "DIEBR Rounding case 8g" BF800000 40400000 BF800000 40400000 +r 2AF0.10 # RP / RFS +*Want "DIEBR Rounding case 8h" BF800000 40400000 BF800000 40400000 +r 2B00.10 # RP / RNTE +*Want "DIEBR Rounding case 8i" 3F800000 40000000 3F800000 40000000 +r 2B10.10 # RP / RZ +*Want "DIEBR Rounding case 8j" 3F800000 40000000 3F800000 40000000 +r 2B20.10 # RP / RP +*Want "DIEBR Rounding case 8k" BF800000 40400000 BF800000 40400000 +r 2B30.10 # RP / RM +*Want "DIEBR Rounding case 8l" 3F800000 40000000 3F800000 40000000 +r 2B40.10 # RM / RNTA +*Want "DIEBR Rounding case 8m" BF800000 40400000 BF800000 40400000 +r 2B50.10 # RM / RFS +*Want "DIEBR Rounding case 8n" BF800000 40400000 BF800000 40400000 +r 2B60.10 # RM / RNTE +*Want "DIEBR Rounding case 8o" 3F800000 40000000 3F800000 40000000 +r 2B70.10 # RM / RZ +*Want "DIEBR Rounding case 8p" 3F800000 40000000 3F800000 40000000 +r 2B80.10 # RM / RP +*Want "DIEBR Rounding case 8q" BF800000 40400000 BF800000 40400000 +r 2B90.10 # RM / RM +*Want "DIEBR Rounding case 8r" 3F800000 40000000 3F800000 40000000 +r 2BA0.10 # RFS / RNTA +*Want "DIEBR Rounding case 8s" BF800000 40400000 BF800000 40400000 +r 2BB0.10 # RFS / RFS +*Want "DIEBR Rounding case 8t" BF800000 40400000 BF800000 40400000 +r 2BC0.10 # RFS / RNTE +*Want "DIEBR Rounding case 8u" 3F800000 40000000 3F800000 40000000 +r 2BD0.10 # RFS / RZ +*Want "DIEBR Rounding case 8v" 3F800000 40000000 3F800000 40000000 +r 2BE0.10 # RFS / RP +*Want "DIEBR Rounding case 8w" BF800000 40400000 BF800000 40400000 +r 2BF0.10 # RFS / RM +*Want "DIEBR Rounding case 8x" 3F800000 40000000 3F800000 40000000 +r 2C00.10 # RZ / RNTA +*Want "DIEBR Rounding case 9a" BF800000 40C00000 BF800000 40C00000 +r 2C10.10 # RZ / RFS +*Want "DIEBR Rounding case 9b" 3F800000 40A00000 3F800000 40A00000 +r 2C20.10 # RZ / RNTE +*Want "DIEBR Rounding case 9c" BF800000 40C00000 BF800000 40C00000 +r 2C30.10 # RZ / RZ +*Want "DIEBR Rounding case 9d" 3F800000 40A00000 3F800000 40A00000 +r 2C40.10 # RZ / RP +*Want "DIEBR Rounding case 9e" BF800000 40C00000 BF800000 40C00000 +r 2C50.10 # RZ / RM +*Want "DIEBR Rounding case 9f" 3F800000 40A00000 3F800000 40A00000 +r 2C60.10 # RP / RNTA +*Want "DIEBR Rounding case 9g" BF800000 40C00000 BF800000 40C00000 +r 2C70.10 # RP / RFS +*Want "DIEBR Rounding case 9h" 3F800000 40A00000 3F800000 40A00000 +r 2C80.10 # RP / RNTE +*Want "DIEBR Rounding case 9i" BF800000 40C00000 BF800000 40C00000 +r 2C90.10 # RP / RZ +*Want "DIEBR Rounding case 9j" 3F800000 40A00000 3F800000 40A00000 +r 2CA0.10 # RP / RP +*Want "DIEBR Rounding case 9k" BF800000 40C00000 BF800000 40C00000 +r 2CB0.10 # RP / RM +*Want "DIEBR Rounding case 9l" 3F800000 40A00000 3F800000 40A00000 +r 2CC0.10 # RM / RNTA +*Want "DIEBR Rounding case 9m" BF800000 40C00000 BF800000 40C00000 +r 2CD0.10 # RM / RFS +*Want "DIEBR Rounding case 9n" 3F800000 40A00000 3F800000 40A00000 +r 2CE0.10 # RM / RNTE +*Want "DIEBR Rounding case 9o" BF800000 40C00000 BF800000 40C00000 +r 2CF0.10 # RM / RZ +*Want "DIEBR Rounding case 9p" 3F800000 40A00000 3F800000 40A00000 +r 2D00.10 # RM / RP +*Want "DIEBR Rounding case 9q" BF800000 40C00000 BF800000 40C00000 +r 2D10.10 # RM / RM +*Want "DIEBR Rounding case 9r" 3F800000 40A00000 3F800000 40A00000 +r 2D20.10 # RFS / RNTA +*Want "DIEBR Rounding case 9s" BF800000 40C00000 BF800000 40C00000 +r 2D30.10 # RFS / RFS +*Want "DIEBR Rounding case 9t" 3F800000 40A00000 3F800000 40A00000 +r 2D40.10 # RFS / RNTE +*Want "DIEBR Rounding case 9u" BF800000 40C00000 BF800000 40C00000 +r 2D50.10 # RFS / RZ +*Want "DIEBR Rounding case 9v" 3F800000 40A00000 3F800000 40A00000 +r 2D60.10 # RFS / RP +*Want "DIEBR Rounding case 9w" BF800000 40C00000 BF800000 40C00000 +r 2D70.10 # RFS / RM +*Want "DIEBR Rounding case 9x" 3F800000 40A00000 3F800000 40A00000 +r 2D80.10 # RZ / RNTA +*Want "DIEBR Rounding case 10a" BF800000 41200000 BF800000 41200000 +r 2D90.10 # RZ / RFS +*Want "DIEBR Rounding case 10b" 3F800000 41100000 3F800000 41100000 +r 2DA0.10 # RZ / RNTE +*Want "DIEBR Rounding case 10c" BF800000 41200000 BF800000 41200000 +r 2DB0.10 # RZ / RZ +*Want "DIEBR Rounding case 10d" 3F800000 41100000 3F800000 41100000 +r 2DC0.10 # RZ / RP +*Want "DIEBR Rounding case 10e" BF800000 41200000 BF800000 41200000 +r 2DD0.10 # RZ / RM +*Want "DIEBR Rounding case 10f" 3F800000 41100000 3F800000 41100000 +r 2DE0.10 # RP / RNTA +*Want "DIEBR Rounding case 10g" BF800000 41200000 BF800000 41200000 +r 2DF0.10 # RP / RFS +*Want "DIEBR Rounding case 10h" 3F800000 41100000 3F800000 41100000 +r 2E00.10 # RP / RNTE +*Want "DIEBR Rounding case 10i" BF800000 41200000 BF800000 41200000 +r 2E10.10 # RP / RZ +*Want "DIEBR Rounding case 10j" 3F800000 41100000 3F800000 41100000 +r 2E20.10 # RP / RP +*Want "DIEBR Rounding case 10k" BF800000 41200000 BF800000 41200000 +r 2E30.10 # RP / RM +*Want "DIEBR Rounding case 10l" 3F800000 41100000 3F800000 41100000 +r 2E40.10 # RM / RNTA +*Want "DIEBR Rounding case 10m" BF800000 41200000 BF800000 41200000 +r 2E50.10 # RM / RFS +*Want "DIEBR Rounding case 10n" 3F800000 41100000 3F800000 41100000 +r 2E60.10 # RM / RNTE +*Want "DIEBR Rounding case 10o" BF800000 41200000 BF800000 41200000 +r 2E70.10 # RM / RZ +*Want "DIEBR Rounding case 10p" 3F800000 41100000 3F800000 41100000 +r 2E80.10 # RM / RP +*Want "DIEBR Rounding case 10q" BF800000 41200000 BF800000 41200000 +r 2E90.10 # RM / RM +*Want "DIEBR Rounding case 10r" 3F800000 41100000 3F800000 41100000 +r 2EA0.10 # RFS / RNTA +*Want "DIEBR Rounding case 10s" BF800000 41200000 BF800000 41200000 +r 2EB0.10 # RFS / RFS +*Want "DIEBR Rounding case 10t" 3F800000 41100000 3F800000 41100000 +r 2EC0.10 # RFS / RNTE +*Want "DIEBR Rounding case 10u" BF800000 41200000 BF800000 41200000 +r 2ED0.10 # RFS / RZ +*Want "DIEBR Rounding case 10v" 3F800000 41100000 3F800000 41100000 +r 2EE0.10 # RFS / RP +*Want "DIEBR Rounding case 10w" BF800000 41200000 BF800000 41200000 +r 2EF0.10 # RFS / RM +*Want "DIEBR Rounding case 10x" 3F800000 41100000 3F800000 41100000 +r 2F00.10 # RZ / RNTA +*Want "DIEBR Rounding case 11" 00000000 3F800000 00000000 3F800000 +r 2F10.10 # RZ / RFS +*Want "DIEBR Rounding case 11" 00000000 3F800000 00000000 3F800000 +r 2F20.10 # RZ / RNTE +*Want "DIEBR Rounding case 11" 00000000 3F800000 00000000 3F800000 +r 2F30.10 # RZ / RZ +*Want "DIEBR Rounding case 11" 00000000 3F800000 00000000 3F800000 +r 2F40.10 # RZ / RP +*Want "DIEBR Rounding case 11" 00000000 3F800000 00000000 3F800000 +r 2F50.10 # RZ / RM +*Want "DIEBR Rounding case 11" 00000000 3F800000 00000000 3F800000 +r 2F60.10 # RP / RNTA +*Want "DIEBR Rounding case 11" 00000000 3F800000 00000000 3F800000 +r 2F70.10 # RP / RFS +*Want "DIEBR Rounding case 11" 00000000 3F800000 00000000 3F800000 +r 2F80.10 # RP / RNTE +*Want "DIEBR Rounding case 11" 00000000 3F800000 00000000 3F800000 +r 2F90.10 # RP / RZ +*Want "DIEBR Rounding case 11" 00000000 3F800000 00000000 3F800000 +r 2FA0.10 # RP / RP +*Want "DIEBR Rounding case 11" 00000000 3F800000 00000000 3F800000 +r 2FB0.10 # RP / RM +*Want "DIEBR Rounding case 11" 00000000 3F800000 00000000 3F800000 +r 2FC0.10 # RM / RNTA +*Want "DIEBR Rounding case 11" 00000000 3F800000 00000000 3F800000 +r 2FD0.10 # RM / RFS +*Want "DIEBR Rounding case 11" 00000000 3F800000 00000000 3F800000 +r 2FE0.10 # RM / RNTE +*Want "DIEBR Rounding case 11" 00000000 3F800000 00000000 3F800000 +r 2FF0.10 # RM / RZ +*Want "DIEBR Rounding case 11" 00000000 3F800000 00000000 3F800000 +r 3000.10 # RM / RP +*Want "DIEBR Rounding case 11" 00000000 3F800000 00000000 3F800000 +r 3010.10 # RM / RM +*Want "DIEBR Rounding case 11" 00000000 3F800000 00000000 3F800000 +r 3020.10 # RFS / RNTA +*Want "DIEBR Rounding case 11" 00000000 3F800000 00000000 3F800000 +r 3030.10 # RFS / RFS +*Want "DIEBR Rounding case 11" 00000000 3F800000 00000000 3F800000 +r 3040.10 # RFS / RNTE +*Want "DIEBR Rounding case 11" 00000000 3F800000 00000000 3F800000 +r 3050.10 # RFS / RZ +*Want "DIEBR Rounding case 11" 00000000 3F800000 00000000 3F800000 +r 3060.10 # RFS / RP +*Want "DIEBR Rounding case 11" 00000000 3F800000 00000000 3F800000 +r 3070.10 # RFS / RM +*Want "DIEBR Rounding case 11" 00000000 3F800000 00000000 3F800000 +r 3080.10 # RZ / RNTA +*Want "DIEBR Rounding case 12" C0000000 3F800000 C0000000 3F800000 +r 3090.10 # RZ / RFS +*Want "DIEBR Rounding case 12" C0000000 3F800000 C0000000 3F800000 +r 30A0.10 # RZ / RNTE +*Want "DIEBR Rounding case 12" C0000000 3F800000 C0000000 3F800000 +r 30B0.10 # RZ / RZ +*Want "DIEBR Rounding case 12" 40400000 00000000 40400000 00000000 +r 30C0.10 # RZ / RP +*Want "DIEBR Rounding case 12" C0000000 3F800000 C0000000 3F800000 +r 30D0.10 # RZ / RM +*Want "DIEBR Rounding case 12" 40400000 00000000 40400000 00000000 +r 30E0.10 # RP / RNTA +*Want "DIEBR Rounding case 12" C0000000 3F800000 C0000000 3F800000 +r 30F0.10 # RP / RFS +*Want "DIEBR Rounding case 12" C0000000 3F800000 C0000000 3F800000 +r 3100.10 # RP / RNTE +*Want "DIEBR Rounding case 12" C0000000 3F800000 C0000000 3F800000 +r 3110.10 # RP / RZ +*Want "DIEBR Rounding case 12" 40400000 00000000 40400000 00000000 +r 3120.10 # RP / RP +*Want "DIEBR Rounding case 12" C0000000 3F800000 C0000000 3F800000 +r 3130.10 # RP / RM +*Want "DIEBR Rounding case 12" 40400000 00000000 40400000 00000000 +r 3140.10 # RM / RNTA +*Want "DIEBR Rounding case 12" C0000000 3F800000 C0000000 3F800000 +r 3150.10 # RM / RFS +*Want "DIEBR Rounding case 12" C0000000 3F800000 C0000000 3F800000 +r 3160.10 # RM / RNTE +*Want "DIEBR Rounding case 12" C0000000 3F800000 C0000000 3F800000 +r 3170.10 # RM / RZ +*Want "DIEBR Rounding case 12" 40400000 00000000 40400000 00000000 +r 3180.10 # RM / RP +*Want "DIEBR Rounding case 12" C0000000 3F800000 C0000000 3F800000 +r 3190.10 # RM / RM +*Want "DIEBR Rounding case 12" 40400000 00000000 40400000 00000000 +r 31A0.10 # RFS / RNTA +*Want "DIEBR Rounding case 12" C0000000 3F800000 C0000000 3F800000 +r 31B0.10 # RFS / RFS +*Want "DIEBR Rounding case 12" C0000000 3F800000 C0000000 3F800000 +r 31C0.10 # RFS / RNTE +*Want "DIEBR Rounding case 12" C0000000 3F800000 C0000000 3F800000 +r 31D0.10 # RFS / RZ +*Want "DIEBR Rounding case 12" 40400000 00000000 40400000 00000000 +r 31E0.10 # RFS / RP +*Want "DIEBR Rounding case 12" C0000000 3F800000 C0000000 3F800000 +r 31F0.10 # RFS / RM +*Want "DIEBR Rounding case 12" 40400000 00000000 40400000 00000000 + + + + +*Compare +# Short BFP exhaustive rounding mode tests +r 4000.10 # RZ / RNTA RZ / RFS +*Want "DIEBR Rounding FPCR 1ab" 00000000 F8000000 00000000 F8000000 +r 4010.10 # RZ / RNTE RZ / RZ +*Want "DIEBR Rounding FPCR 1cd" 00000000 F8000000 00000000 F8000000 +r 4020.10 # RZ / RP RZ / RM +*Want "DIEBR Rounding FPCR 1ef" 00000000 F8000000 00000000 F8000000 +r 4030.10 # RP / RNTA RP / RFS +*Want "DIEBR Rounding FPCR 1gh" 00000000 F8000000 00000000 F8000000 +r 4040.10 # RP / RNTE RP / RZ +*Want "DIEBR Rounding FPCR 1ij" 00000000 F8000000 00000000 F8000000 +r 4050.10 # RP / RP RP / RM +*Want "DIEBR Rounding FPCR 1kl" 00000000 F8000000 00000000 F8000000 +r 4060.10 # RM / RNTA RM / RFS +*Want "DIEBR Rounding FPCR 1mn" 00000000 F8000000 00000000 F8000000 +r 4070.10 # RM / RNTE RM / RZ +*Want "DIEBR Rounding FPCR 1op" 00000000 F8000000 00000000 F8000000 +r 4080.10 # RM / RP RM / RM +*Want "DIEBR Rounding FPCR 1qr" 00000000 F8000000 00000000 F8000000 +r 4090.10 # RFS / RNTA RFS / RFS +*Want "DIEBR Rounding FPCR 1st" 00000000 F8000000 00000000 F8000000 +r 40A0.10 # RFS / RNTE RFS / RZ +*Want "DIEBR Rounding FPCR 1uv" 00000000 F8000000 00000000 F8000000 +r 40B0.10 # RFS / RP RFS / RM +*Want "DIEBR Rounding FPCR 1wx" 00000000 F8000000 00000000 F8000000 +r 40C0.10 # RZ / RNTA RZ / RFS +*Want "DIEBR Rounding FPCR 2ab" 00000000 F8000000 00000000 F8000000 +r 40D0.10 # RZ / RNTE RZ / RZ +*Want "DIEBR Rounding FPCR 2cd" 00000000 F8000000 00000000 F8000000 +r 40E0.10 # RZ / RP RZ / RM +*Want "DIEBR Rounding FPCR 2ef" 00000000 F8000000 00000000 F8000000 +r 40F0.10 # RP / RNTA RP / RFS +*Want "DIEBR Rounding FPCR 2gh" 00000000 F8000000 00000000 F8000000 +r 4100.10 # RP / RNTE RP / RZ +*Want "DIEBR Rounding FPCR 2ij" 00000000 F8000000 00000000 F8000000 +r 4110.10 # RP / RP RP / RM +*Want "DIEBR Rounding FPCR 2kl" 00000000 F8000000 00000000 F8000000 +r 4120.10 # RM / RNTA RM / RFS +*Want "DIEBR Rounding FPCR 2mn" 00000000 F8000000 00000000 F8000000 +r 4130.10 # RM / RNTE RM / RZ +*Want "DIEBR Rounding FPCR 2op" 00000000 F8000000 00000000 F8000000 +r 4140.10 # RM / RP RM / RM +*Want "DIEBR Rounding FPCR 2qr" 00000000 F8000000 00000000 F8000000 +r 4150.10 # RFS / RNTA RFS / RFS +*Want "DIEBR Rounding FPCR 2st" 00000000 F8000000 00000000 F8000000 +r 4160.10 # RFS / RNTE RFS / RZ +*Want "DIEBR Rounding FPCR 2uv" 00000000 F8000000 00000000 F8000000 +r 4170.10 # RFS / RP RFS / RM +*Want "DIEBR Rounding FPCR 2wx" 00000000 F8000000 00000000 F8000000 +r 4180.10 # RZ / RNTA RZ / RFS +*Want "DIEBR Rounding FPCR 3ab" 00000000 F8000000 00000000 F8000000 +r 4190.10 # RZ / RNTE RZ / RZ +*Want "DIEBR Rounding FPCR 3cd" 00000000 F8000000 00000000 F8000000 +r 41A0.10 # RZ / RP RZ / RM +*Want "DIEBR Rounding FPCR 3ef" 00000000 F8000000 00000000 F8000000 +r 41B0.10 # RP / RNTA RP / RFS +*Want "DIEBR Rounding FPCR 3gh" 00000000 F8000000 00000000 F8000000 +r 41C0.10 # RP / RNTE RP / RZ +*Want "DIEBR Rounding FPCR 3ij" 00000000 F8000000 00000000 F8000000 +r 41D0.10 # RP / RP RP / RM +*Want "DIEBR Rounding FPCR 3kl" 00000000 F8000000 00000000 F8000000 +r 41E0.10 # RM / RNTA RM / RFS +*Want "DIEBR Rounding FPCR 3mn" 00000000 F8000000 00000000 F8000000 +r 41F0.10 # RM / RNTE RM / RZ +*Want "DIEBR Rounding FPCR 3op" 00000000 F8000000 00000000 F8000000 +r 4200.10 # RM / RP RM / RM +*Want "DIEBR Rounding FPCR 3qr" 00000000 F8000000 00000000 F8000000 +r 4210.10 # RFS / RNTA RFS / RFS +*Want "DIEBR Rounding FPCR 3st" 00000000 F8000000 00000000 F8000000 +r 4220.10 # RFS / RNTE RFS / RZ +*Want "DIEBR Rounding FPCR 3uv" 00000000 F8000000 00000000 F8000000 +r 4230.10 # RFS / RP RFS / RM +*Want "DIEBR Rounding FPCR 3wx" 00000000 F8000000 00000000 F8000000 +r 4240.10 # RZ / RNTA RZ / RFS +*Want "DIEBR Rounding FPCR 4ab" 00000000 F8000000 00000000 F8000000 +r 4250.10 # RZ / RNTE RZ / RZ +*Want "DIEBR Rounding FPCR 4cd" 00000000 F8000000 00000000 F8000000 +r 4260.10 # RZ / RP RZ / RM +*Want "DIEBR Rounding FPCR 4ef" 00000000 F8000000 00000000 F8000000 +r 4270.10 # RP / RNTA RP / RFS +*Want "DIEBR Rounding FPCR 4gh" 00000000 F8000000 00000000 F8000000 +r 4280.10 # RP / RNTE RP / RZ +*Want "DIEBR Rounding FPCR 4ij" 00000000 F8000000 00000000 F8000000 +r 4290.10 # RP / RP RP / RM +*Want "DIEBR Rounding FPCR 4kl" 00000000 F8000000 00000000 F8000000 +r 42A0.10 # RM / RNTA RM / RFS +*Want "DIEBR Rounding FPCR 4mn" 00000000 F8000000 00000000 F8000000 +r 42B0.10 # RM / RNTE RM / RZ +*Want "DIEBR Rounding FPCR 4op" 00000000 F8000000 00000000 F8000000 +r 42C0.10 # RM / RP RM / RM +*Want "DIEBR Rounding FPCR 4qr" 00000000 F8000000 00000000 F8000000 +r 42D0.10 # RFS / RNTA RFS / RFS +*Want "DIEBR Rounding FPCR 4st" 00000000 F8000000 00000000 F8000000 +r 42E0.10 # RFS / RNTE RFS / RZ +*Want "DIEBR Rounding FPCR 4uv" 00000000 F8000000 00000000 F8000000 +r 42F0.10 # RFS / RP RFS / RM +*Want "DIEBR Rounding FPCR 4wx" 00000000 F8000000 00000000 F8000000 +r 4300.10 # RZ / RNTA RZ / RFS +*Want "DIEBR Rounding FPCR 5ab" 00000000 F8000000 00000000 F8000000 +r 4310.10 # RZ / RNTE RZ / RZ +*Want "DIEBR Rounding FPCR 5cd" 00000000 F8000000 00000000 F8000000 +r 4320.10 # RZ / RP RZ / RM +*Want "DIEBR Rounding FPCR 5ef" 00000000 F8000000 00000000 F8000000 +r 4330.10 # RP / RNTA RP / RFS +*Want "DIEBR Rounding FPCR 5gh" 00000000 F8000000 00000000 F8000000 +r 4340.10 # RP / RNTE RP / RZ +*Want "DIEBR Rounding FPCR 5ij" 00000000 F8000000 00000000 F8000000 +r 4350.10 # RP / RP RP / RM +*Want "DIEBR Rounding FPCR 5kl" 00000000 F8000000 00000000 F8000000 +r 4360.10 # RM / RNTA RM / RFS +*Want "DIEBR Rounding FPCR 5mn" 00000000 F8000000 00000000 F8000000 +r 4370.10 # RM / RNTE RM / RZ +*Want "DIEBR Rounding FPCR 5op" 00000000 F8000000 00000000 F8000000 +r 4380.10 # RM / RP RM / RM +*Want "DIEBR Rounding FPCR 5qr" 00000000 F8000000 00000000 F8000000 +r 4390.10 # RFS / RNTA RFS / RFS +*Want "DIEBR Rounding FPCR 5st" 00000000 F8000000 00000000 F8000000 +r 43A0.10 # RFS / RNTE RFS / RZ +*Want "DIEBR Rounding FPCR 5uv" 00000000 F8000000 00000000 F8000000 +r 43B0.10 # RFS / RP RFS / RM +*Want "DIEBR Rounding FPCR 5wx" 00000000 F8000000 00000000 F8000000 +r 43C0.10 # RZ / RNTA RZ / RFS +*Want "DIEBR Rounding FPCR 6ab" 00000000 F8000000 00000000 F8000000 +r 43D0.10 # RZ / RNTE RZ / RZ +*Want "DIEBR Rounding FPCR 6cd" 00000000 F8000000 00000000 F8000000 +r 43E0.10 # RZ / RP RZ / RM +*Want "DIEBR Rounding FPCR 6ef" 00000000 F8000000 00000000 F8000000 +r 43F0.10 # RP / RNTA RP / RFS +*Want "DIEBR Rounding FPCR 6gh" 00000000 F8000000 00000000 F8000000 +r 4400.10 # RP / RNTE RP / RZ +*Want "DIEBR Rounding FPCR 6ij" 00000000 F8000000 00000000 F8000000 +r 4410.10 # RP / RP RP / RM +*Want "DIEBR Rounding FPCR 6kl" 00000000 F8000000 00000000 F8000000 +r 4420.10 # RM / RNTA RM / RFS +*Want "DIEBR Rounding FPCR 6mn" 00000000 F8000000 00000000 F8000000 +r 4430.10 # RM / RNTE RM / RZ +*Want "DIEBR Rounding FPCR 6op" 00000000 F8000000 00000000 F8000000 +r 4440.10 # RM / RP RM / RM +*Want "DIEBR Rounding FPCR 6qr" 00000000 F8000000 00000000 F8000000 +r 4450.10 # RFS / RNTA RFS / RFS +*Want "DIEBR Rounding FPCR 6st" 00000000 F8000000 00000000 F8000000 +r 4460.10 # RFS / RNTE RFS / RZ +*Want "DIEBR Rounding FPCR 6uv" 00000000 F8000000 00000000 F8000000 +r 4470.10 # RFS / RP RFS / RM +*Want "DIEBR Rounding FPCR 6wx" 00000000 F8000000 00000000 F8000000 +r 4480.10 # RZ / RNTA RZ / RFS +*Want "DIEBR Rounding FPCR 7ab" 00000000 F8000000 00000000 F8000000 +r 4490.10 # RZ / RNTE RZ / RZ +*Want "DIEBR Rounding FPCR 7cd" 00000000 F8000000 00000000 F8000000 +r 44A0.10 # RZ / RP RZ / RM +*Want "DIEBR Rounding FPCR 7ef" 00000000 F8000000 00000000 F8000000 +r 44B0.10 # RP / RNTA RP / RFS +*Want "DIEBR Rounding FPCR 7gh" 00000000 F8000000 00000000 F8000000 +r 44C0.10 # RP / RNTE RP / RZ +*Want "DIEBR Rounding FPCR 7ij" 00000000 F8000000 00000000 F8000000 +r 44D0.10 # RP / RP RP / RM +*Want "DIEBR Rounding FPCR 7kl" 00000000 F8000000 00000000 F8000000 +r 44E0.10 # RM / RNTA RM / RFS +*Want "DIEBR Rounding FPCR 7mn" 00000000 F8000000 00000000 F8000000 +r 44F0.10 # RM / RNTE RM / RZ +*Want "DIEBR Rounding FPCR 7op" 00000000 F8000000 00000000 F8000000 +r 4500.10 # RM / RP RM / RM +*Want "DIEBR Rounding FPCR 7qr" 00000000 F8000000 00000000 F8000000 +r 4510.10 # RFS / RNTA RFS / RFS +*Want "DIEBR Rounding FPCR 7st" 00000000 F8000000 00000000 F8000000 +r 4520.10 # RFS / RNTE RFS / RZ +*Want "DIEBR Rounding FPCR 7uv" 00000000 F8000000 00000000 F8000000 +r 4530.10 # RFS / RP RFS / RM +*Want "DIEBR Rounding FPCR 7wx" 00000000 F8000000 00000000 F8000000 +r 4540.10 # RZ / RNTA RZ / RFS +*Want "DIEBR Rounding FPCR 8ab" 00000000 F8000000 00000000 F8000000 +r 4550.10 # RZ / RNTE RZ / RZ +*Want "DIEBR Rounding FPCR 8cd" 00000000 F8000000 00000000 F8000000 +r 4560.10 # RZ / RP RZ / RM +*Want "DIEBR Rounding FPCR 8ef" 00000000 F8000000 00000000 F8000000 +r 4570.10 # RP / RNTA RP / RFS +*Want "DIEBR Rounding FPCR 8gh" 00000000 F8000000 00000000 F8000000 +r 4580.10 # RP / RNTE RP / RZ +*Want "DIEBR Rounding FPCR 8ij" 00000000 F8000000 00000000 F8000000 +r 4590.10 # RP / RP RP / RM +*Want "DIEBR Rounding FPCR 8kl" 00000000 F8000000 00000000 F8000000 +r 45A0.10 # RM / RNTA RM / RFS +*Want "DIEBR Rounding FPCR 8mn" 00000000 F8000000 00000000 F8000000 +r 45B0.10 # RM / RNTE RM / RZ +*Want "DIEBR Rounding FPCR 8op" 00000000 F8000000 00000000 F8000000 +r 45C0.10 # RM / RP RM / RM +*Want "DIEBR Rounding FPCR 8qr" 00000000 F8000000 00000000 F8000000 +r 45D0.10 # RFS / RNTA RFS / RFS +*Want "DIEBR Rounding FPCR 8st" 00000000 F8000000 00000000 F8000000 +r 45E0.10 # RFS / RNTE RFS / RZ +*Want "DIEBR Rounding FPCR 8uv" 00000000 F8000000 00000000 F8000000 +r 45F0.10 # RFS / RP RFS / RM +*Want "DIEBR Rounding FPCR 8wx" 00000000 F8000000 00000000 F8000000 +r 4600.10 # RZ / RNTA RZ / RFS +*Want "DIEBR Rounding FPCR 9ab" 00000000 F8000000 00000000 F8000000 +r 4610.10 # RZ / RNTE RZ / RZ +*Want "DIEBR Rounding FPCR 9cd" 00000000 F8000000 00000000 F8000000 +r 4620.10 # RZ / RP RZ / RM +*Want "DIEBR Rounding FPCR 9ef" 00000000 F8000000 00000000 F8000000 +r 4630.10 # RP / RNTA RP / RFS +*Want "DIEBR Rounding FPCR 9gh" 00000000 F8000000 00000000 F8000000 +r 4640.10 # RP / RNTE RP / RZ +*Want "DIEBR Rounding FPCR 9ij" 00000000 F8000000 00000000 F8000000 +r 4650.10 # RP / RP RP / RM +*Want "DIEBR Rounding FPCR 9kl" 00000000 F8000000 00000000 F8000000 +r 4660.10 # RM / RNTA RM / RFS +*Want "DIEBR Rounding FPCR 9mn" 00000000 F8000000 00000000 F8000000 +r 4670.10 # RM / RNTE RM / RZ +*Want "DIEBR Rounding FPCR 9op" 00000000 F8000000 00000000 F8000000 +r 4680.10 # RM / RP RM / RM +*Want "DIEBR Rounding FPCR 9qr" 00000000 F8000000 00000000 F8000000 +r 4690.10 # RFS / RNTA RFS / RFS +*Want "DIEBR Rounding FPCR 9st" 00000000 F8000000 00000000 F8000000 +r 46A0.10 # RFS / RNTE RFS / RZ +*Want "DIEBR Rounding FPCR 9uv" 00000000 F8000000 00000000 F8000000 +r 46B0.10 # RFS / RP RFS / RM +*Want "DIEBR Rounding FPCR 9wx" 00000000 F8000000 00000000 F8000000 +r 46C0.10 # RZ / RNTA RZ / RFS +*Want "DIEBR Rounding FPCR 10ab" 00000000 F8000000 00000000 F8000000 +r 46D0.10 # RZ / RNTE RZ / RZ +*Want "DIEBR Rounding FPCR 10cd" 00000000 F8000000 00000000 F8000000 +r 46E0.10 # RZ / RP RZ / RM +*Want "DIEBR Rounding FPCR 10ef" 00000000 F8000000 00000000 F8000000 +r 46F0.10 # RP / RNTA RP / RFS +*Want "DIEBR Rounding FPCR 10gh" 00000000 F8000000 00000000 F8000000 +r 4700.10 # RP / RNTE RP / RZ +*Want "DIEBR Rounding FPCR 10ij" 00000000 F8000000 00000000 F8000000 +r 4710.10 # RP / RP RP / RM +*Want "DIEBR Rounding FPCR 10kl" 00000000 F8000000 00000000 F8000000 +r 4720.10 # RM / RNTA RM / RFS +*Want "DIEBR Rounding FPCR 10mn" 00000000 F8000000 00000000 F8000000 +r 4730.10 # RM / RNTE RM / RZ +*Want "DIEBR Rounding FPCR 10op" 00000000 F8000000 00000000 F8000000 +r 4740.10 # RM / RP RM / RM +*Want "DIEBR Rounding FPCR 10qr" 00000000 F8000000 00000000 F8000000 +r 4750.10 # RFS / RNTA RFS / RFS +*Want "DIEBR Rounding FPCR 10st" 00000000 F8000000 00000000 F8000000 +r 4760.10 # RFS / RNTE RFS / RZ +*Want "DIEBR Rounding FPCR 10uv" 00000000 F8000000 00000000 F8000000 +r 4770.10 # RFS / RP RFS / RM +*Want "DIEBR Rounding FPCR 10wx" 00000000 F8000000 00000000 F8000000 +r 4780.10 # RZ / RNTA RZ / RFS +*Want "DIEBR Rounding FPCR 11ab" 00000000 F8000000 00000000 F8000000 +r 4790.10 # RZ / RNTE RZ / RZ +*Want "DIEBR Rounding FPCR 11cd" 00000000 F8000000 00000000 F8000000 +r 47A0.10 # RZ / RP RZ / RM +*Want "DIEBR Rounding FPCR 11ef" 00000000 F8000000 00000000 F8000000 +r 47B0.10 # RP / RNTA RP / RFS +*Want "DIEBR Rounding FPCR 11gh" 00000000 F8000000 00000000 F8000000 +r 47C0.10 # RP / RNTE RP / RZ +*Want "DIEBR Rounding FPCR 11ij" 00000000 F8000000 00000000 F8000000 +r 47D0.10 # RP / RP RP / RM +*Want "DIEBR Rounding FPCR 11kl" 00000000 F8000000 00000000 F8000000 +r 47E0.10 # RM / RNTA RM / RFS +*Want "DIEBR Rounding FPCR 11mn" 00000000 F8000000 00000000 F8000000 +r 47F0.10 # RM / RNTE RM / RZ +*Want "DIEBR Rounding FPCR 11op" 00000000 F8000000 00000000 F8000000 +r 4800.10 # RM / RP RM / RM +*Want "DIEBR Rounding FPCR 11qr" 00000000 F8000000 00000000 F8000000 +r 4810.10 # RFS / RNTA RFS / RFS +*Want "DIEBR Rounding FPCR 11st" 00000000 F8000000 00000000 F8000000 +r 4820.10 # RFS / RNTE RFS / RZ +*Want "DIEBR Rounding FPCR 11uv" 00000000 F8000000 00000000 F8000000 +r 4830.10 # RFS / RP RFS / RM +*Want "DIEBR Rounding FPCR 11wx" 00000000 F8000000 00000000 F8000000 +r 4840.10 # RZ / RNTA RZ / RFS +*Want "DIEBR Rounding FPCR 12ab" 00000000 F8000000 00000000 F8000000 +r 4850.10 # RZ / RNTE RZ / RZ +*Want "DIEBR Rounding FPCR 12cd" 00000000 F8000000 00000000 F8000000 +r 4860.10 # RZ / RP RZ / RM +*Want "DIEBR Rounding FPCR 12ef" 00000000 F8000000 00000000 F8000000 +r 4870.10 # RP / RNTA RP / RFS +*Want "DIEBR Rounding FPCR 12gh" 00000000 F8000000 00000000 F8000000 +r 4880.10 # RP / RNTE RP / RZ +*Want "DIEBR Rounding FPCR 12ij" 00000000 F8000000 00000000 F8000000 +r 4890.10 # RP / RP RP / RM +*Want "DIEBR Rounding FPCR 12kl" 00000000 F8000000 00000000 F8000000 +r 48A0.10 # RM / RNTA RM / RFS +*Want "DIEBR Rounding FPCR 12mn" 00000000 F8000000 00000000 F8000000 +r 48B0.10 # RM / RNTE RM / RZ +*Want "DIEBR Rounding FPCR 12op" 00000000 F8000000 00000000 F8000000 +r 48C0.10 # RM / RP RM / RM +*Want "DIEBR Rounding FPCR 12qr" 00000000 F8000000 00000000 F8000000 +r 48D0.10 # RFS / RNTA RFS / RFS +*Want "DIEBR Rounding FPCR 12st" 00000000 F8000000 00000000 F8000000 +r 48E0.10 # RFS / RNTE RFS / RZ +*Want "DIEBR Rounding FPCR 12uv" 00000000 F8000000 00000000 F8000000 +r 48F0.10 # RFS / RP RFS / RM +*Want "DIEBR Rounding FPCR 12wx" 00000000 F8000000 00000000 F8000000 + + + + +*Compare +# NaN propagation tests - BFP Long +r 1300.10 # Expecting QNaN A +*Want "DIDBR test 1a NaN" 7FF8A000 00000000 7FF8A000 00000000 +r 1310.10 # Expecting QNaN A +*Want "DIDBR test 1b NaN" 7FF0A000 00000000 00000000 00000000 +r 1320.10 # Expecting QNaN A +*Want "DIDBR test 2a NaN" 7FF8A000 00000000 7FF8A000 00000000 +r 1330.10 # Expecting QNaN A +*Want "DIDBR test 2b NaN" 7FF8A000 00000000 7FF8A000 00000000 +r 1340.10 # Expecting QNaN A +*Want "DIDBR test 3a NaN" 7FF8B000 00000000 7FF8B000 00000000 +r 1350.10 # Expecting QNaN A +*Want "DIDBR test 3b NaN" 7FF8B000 00000000 7FF8B000 00000000 +r 1360.10 # Expecting QNaN B +*Want "DIDBR test 4a NaN" 7FF8B000 00000000 7FF8B000 00000000 +r 1370.10 # Expecting QNaN B +*Want "DIDBR test 4b NaN" 7FF8A000 00000000 00000000 00000000 + + +# Dividend -inf - BFP Long - all should be dNaN (a +QNaN) +r 1380.10 +*Want "DIDBR test 5a -inf dividend" 7FF80000 00000000 7FF80000 00000000 +r 1390.10 +*Want "DIDBR test 5b -inf dividend" FFF00000 00000000 00000000 00000000 +r 13A0.10 +*Want "DIDBR test 6a -inf dividend" 7FF80000 00000000 7FF80000 00000000 +r 13B0.10 +*Want "DIDBR test 6b -inf dividend" FFF00000 00000000 00000000 00000000 +r 13C0.10 +*Want "DIDBR test 7a -inf dividend" 7FF80000 00000000 7FF80000 00000000 +r 13D0.10 +*Want "DIDBR test 7b -inf dividend" FFF00000 00000000 00000000 00000000 +r 13E0.10 +*Want "DIDBR test 8a -inf dividend" 7FF80000 00000000 7FF80000 00000000 +r 13F0.10 +*Want "DIDBR test 8b -inf dividend" FFF00000 00000000 00000000 00000000 +r 1400.10 +*Want "DIDBR test 9a -inf dividend" 7FF80000 00000000 7FF80000 00000000 +r 1410.10 +*Want "DIDBR test 9b -inf dividend" FFF00000 00000000 00000000 00000000 +r 1420.10 +*Want "DIDBR test 10a -inf dividend" 7FF80000 00000000 7FF80000 00000000 +r 1430.10 +*Want "DIDBR test 10b -inf dividend" FFF00000 00000000 00000000 00000000 + + +# Dividend +inf - BFP Long - all should be dNaN (a +QNaN) +r 1440.10 +*Want "DIDBR test 11a +inf dividend" 7FF80000 00000000 7FF80000 00000000 +r 1450.10 +*Want "DIDBR test 11b +inf dividend" 7FF00000 00000000 00000000 00000000 +r 1460.10 +*Want "DIDBR test 12a +inf dividend" 7FF80000 00000000 7FF80000 00000000 +r 1470.10 +*Want "DIDBR test 12b +inf dividend" 7FF00000 00000000 00000000 00000000 +r 1480.10 +*Want "DIDBR test 13a +inf dividend" 7FF80000 00000000 7FF80000 00000000 +r 1490.10 +*Want "DIDBR test 13b +inf dividend" 7FF00000 00000000 00000000 00000000 +r 14A0.10 +*Want "DIDBR test 14a +inf dividend" 7FF80000 00000000 7FF80000 00000000 +r 14B0.10 +*Want "DIDBR test 14b +inf dividend" 7FF00000 00000000 00000000 00000000 +r 14C0.10 +*Want "DIDBR test 15a +inf dividend" 7FF80000 00000000 7FF80000 00000000 +r 14D0.10 +*Want "DIDBR test 15b +inf dividend" 7FF00000 00000000 00000000 00000000 +r 14E0.10 +*Want "DIDBR test 16a +inf dividend" 7FF80000 00000000 7FF80000 00000000 +r 14F0.10 +*Want "DIDBR test 16b +inf dividend" 7FF00000 00000000 00000000 00000000 + + +# Divisor -0 - BFP long - all should be dNaN (a +QNaN) +r 1500.10 +*Want "DIDBR test 17a -0 divisor" 7FF80000 00000000 7FF80000 00000000 +r 1510.10 +*Want "DIDBR test 17b -0 divisor" C0000000 00000000 00000000 00000000 +r 1520.10 +*Want "DIDBR test 18a -0 divisor" 7FF80000 00000000 7FF80000 00000000 +r 1530.10 +*Want "DIDBR test 18b -0 divisor" 80000000 00000000 00000000 00000000 +r 1540.10 +*Want "DIDBR test 19a -0 divisor" 7FF80000 00000000 7FF80000 00000000 +r 1550.10 +*Want "DIDBR test 19b -0 divisor" 00000000 00000000 00000000 00000000 +r 1560.10 +*Want "DIDBR test 20a -0 divisor" 7FF80000 00000000 7FF80000 00000000 +r 1570.10 +*Want "DIDBR test 20b -0 divisor" 40000000 00000000 00000000 00000000 + + +# Divisor +0 - BFP long - all should be dNaN (a +QNaN) +r 1580.10 +*Want "DIDBR test 21a +0 divisor" 7FF80000 00000000 7FF80000 00000000 +r 1590.10 +*Want "DIDBR test 21b +0 divisor" C0000000 00000000 00000000 00000000 +r 15A0.10 +*Want "DIDBR test 22a +0 divisor" 7FF80000 00000000 7FF80000 00000000 +r 15B0.10 +*Want "DIDBR test 22b +0 divisor" 80000000 00000000 00000000 00000000 +r 15C0.10 +*Want "DIDBR test 23a +0 divisor" 7FF80000 00000000 7FF80000 00000000 +r 15D0.10 +*Want "DIDBR test 23b +0 divisor" 00000000 00000000 00000000 00000000 +r 15E0.10 +*Want "DIDBR test 24a +0 divisor" 7FF80000 00000000 7FF80000 00000000 +r 15F0.10 +*Want "DIDBR test 24b +0 divisor" 40000000 00000000 00000000 00000000 + + +# Divisor -inf - BFP long - all should be dNaN (a +QNaN) +r 1600.10 +*Want "DIDBR test 25a -inf divisor" C0000000 00000000 00000000 00000000 +r 1610.10 +*Want "DIDBR test 25b -inf divisor" C0000000 00000000 00000000 00000000 +r 1620.10 +*Want "DIDBR test 26a -inf divisor" 80000000 00000000 00000000 00000000 +r 1630.10 +*Want "DIDBR test 26b -inf divisor" 80000000 00000000 00000000 00000000 +r 1640.10 +*Want "DIDBR test 27a -inf divisor" 00000000 00000000 80000000 00000000 +r 1650.10 +*Want "DIDBR test 27b -inf divisor" 00000000 00000000 80000000 00000000 +r 1660.10 +*Want "DIDBR test 28a -inf divisor" 40000000 00000000 80000000 00000000 +r 1670.10 +*Want "DIDBR test 28b -inf divisor" 40000000 00000000 80000000 00000000 + + +# Divisor +inf - BFP long - all should be dNaN (a +QNaN) +r 1680.10 +*Want "DIDBR test 29a +inf divisor" C0000000 00000000 80000000 00000000 +r 1690.10 +*Want "DIDBR test 29b +inf divisor" C0000000 00000000 80000000 00000000 +r 16A0.10 +*Want "DIDBR test 30a +inf divisor" 80000000 00000000 80000000 00000000 +r 16B0.10 +*Want "DIDBR test 30b +inf divisor" 80000000 00000000 80000000 00000000 +r 16C0.10 +*Want "DIDBR test 31a +inf divisor" 00000000 00000000 00000000 00000000 +r 16D0.10 +*Want "DIDBR test 31b +inf divisor" 00000000 00000000 00000000 00000000 +r 16E0.10 +*Want "DIDBR test 32a +inf divisor" 40000000 00000000 00000000 00000000 +r 16F0.10 +*Want "DIDBR test 32b +inf divisor" 40000000 00000000 00000000 00000000 + + +*Compare +# NaN propagation tests - BFP long - FPCR & cc +r 1700.10 +*Want "DIDBR FPCR pair 1-2" 00800001 F8008001 00000001 F8000001 +r 1710.10 +*Want "DIDBR FPCR pair 3-4" 00000001 F8000001 00800001 F8008001 + + +# Dividend -inf - BFP long - FPCR & cc +r 1720.10 +*Want "DIDBR FPCR pair 5-6" 00800001 F8008001 00800001 F8008001 +r 1730.10 +*Want "DIDBR FPCR pair 7-8" 00800001 F8008001 00800001 F8008001 +r 1740.10 +*Want "DIDBR FPCR pair 9-10" 00800001 F8008001 00800001 F8008001 + + +# Dividend -inf - BFP long - FPCR & cc +r 1750.10 +*Want "DIDBR FPCR pair 11-12" 00800001 F8008001 00800001 F8008001 +r 1760.10 +*Want "DIDBR FPCR pair 13-14" 00800001 F8008001 00800001 F8008001 +r 1770.10 +*Want "DIDBR FPCR pair 15-16" 00800001 F8008001 00800001 F8008001 + + +# Divisor -0 - BFP long - FPCR & cc +r 1780.10 +*Want "DIDBR FPCR pair 17-18" 00800001 F8008001 00800001 F8008001 +r 1790.10 +*Want "DIDBR FPCR pair 19-20" 00800001 F8008001 00800001 F8008001 + +# Divisor +0 - BFP long - FPCR & cc +r 17A0.10 +*Want "DIDBR FPCR pair 21-22" 00800001 F8008001 00800001 F8008001 +r 17B0.10 +*Want "DIDBR FPCR pair 23-24" 00800001 F8008001 00800001 F8008001 + + +# Divisor -inf - BFP long - FPCR & cc +r 17C0.10 +*Want "DIDBR FPCR pair 25-26" 00000000 F8000000 00000000 F8000000 +r 17D0.10 +*Want "DIDBR FPCR pair 27-28" 00000000 F8000000 00000000 F8000000 + +# Divisor +inf - BFP long - FPCR & cc +r 17E0.10 +*Want "DIDBR FPCR pair 29-30" 00000000 F8000000 00000000 F8000000 +r 17F0.10 +*Want "DIDBR FPCR pair 31-32" 00000000 F8000000 00000000 F8000000 + + + +# Dividend & Divisor finite - BFP Long - basic tests +r B000.10 +*Want "DIDBR finite test -8/-4 1a" 80000000 00000000 40000000 00000000 +r B010.08 +*Want "DIDBR finite test -8/-4 1a" C0200000 00000000 +r B020.10 +*Want "DIDBR finite test -8/-4 1b" 80000000 00000000 40000000 00000000 +r B030.08 +*Want "DIDBR finite test -8/-4 1b" C0200000 00000000 +r B040.10 +*Want "DIDBR finite test -7/-4 2a" 3FF00000 00000000 40000000 00000000 +r B050.08 +*Want "DIDBR finite test -7/-4 2a" C01C0000 00000000 +r B060.10 +*Want "DIDBR finite test -7/-4 2b" 3FF00000 00000000 40000000 00000000 +r B070.08 +*Want "DIDBR finite test -7/-4 2b" C01C0000 00000000 +r B080.10 +*Want "DIDBR finite test -6/-4 3a" 40000000 00000000 40000000 00000000 +r B090.08 +*Want "DIDBR finite test -6/-4 3a" C0180000 00000000 +r B0A0.10 +*Want "DIDBR finite test -6/-4 3b" 40000000 00000000 40000000 00000000 +r B0B0.08 +*Want "DIDBR finite test -6/-4 3b" C0180000 00000000 +r B0C0.10 +*Want "DIDBR finite test -5/-4 4a" BFF00000 00000000 3FF00000 00000000 +r B0D0.08 +*Want "DIDBR finite test -5/-4 4a" C0140000 00000000 +r B0E0.10 +*Want "DIDBR finite test -5/-4 4b" BFF00000 00000000 3FF00000 00000000 +r B0F0.08 +*Want "DIDBR finite test -5/-4 4b" C0140000 00000000 +r B100.10 +*Want "DIDBR finite test -4/-4 5a" 80000000 00000000 3FF00000 00000000 +r B110.08 +*Want "DIDBR finite test -4/-4 5a" C0100000 00000000 +r B120.10 +*Want "DIDBR finite test -4/-4 5b" 80000000 00000000 3FF00000 00000000 +r B130.08 +*Want "DIDBR finite test -4/-4 5b" C0100000 00000000 +r B140.10 +*Want "DIDBR finite test -3/-4 6a" 3FF00000 00000000 3FF00000 00000000 +r B150.08 +*Want "DIDBR finite test -3/-4 6a" C0080000 00000000 +r B160.10 +*Want "DIDBR finite test -3/-4 6b" 3FF00000 00000000 3FF00000 00000000 +r B170.08 +*Want "DIDBR finite test -3/-4 6b" C0080000 00000000 +r B180.10 +*Want "DIDBR finite test -2/-4 7a" C0000000 00000000 00000000 00000000 +r B190.08 +*Want "DIDBR finite test -2/-4 7a" C0000000 00000000 +r B1A0.10 +*Want "DIDBR finite test -2/-4 7b" C0000000 00000000 00000000 00000000 +r B1B0.08 +*Want "DIDBR finite test -2/-4 7b" C0000000 00000000 +r B1C0.10 +*Want "DIDBR finite test -1/-4 8a" BFF00000 00000000 00000000 00000000 +r B1D0.08 +*Want "DIDBR finite test -1/-4 8a" BFF00000 00000000 +r B1E0.10 +*Want "DIDBR finite test -1/-4 8b" BFF00000 00000000 00000000 00000000 +r B1F0.08 +*Want "DIDBR finite test -1/-4 8b" BFF00000 00000000 +r B200.10 +*Want "DIDBR finite test +1/-4 9a" 3FF00000 00000000 80000000 00000000 +r B210.08 +*Want "DIDBR finite test +1/-4 9a" 3FF00000 00000000 +r B220.10 +*Want "DIDBR finite test +1/-4 9b" 3FF00000 00000000 80000000 00000000 +r B230.08 +*Want "DIDBR finite test +1/-4 9b" 3FF00000 00000000 +r B240.10 +*Want "DIDBR finite test +2/-4 10a" 40000000 00000000 80000000 00000000 +r B250.08 +*Want "DIDBR finite test +2/-4 10a" 40000000 00000000 +r B260.10 +*Want "DIDBR finite test +2/-4 10b" 40000000 00000000 80000000 00000000 +r B270.08 +*Want "DIDBR finite test +2/-4 10b" 40000000 00000000 +r B280.10 +*Want "DIDBR finite test +3/-4 11a" BFF00000 00000000 BFF00000 00000000 +r B290.08 +*Want "DIDBR finite test +3/-4 11a" 40080000 00000000 +r B2A0.10 +*Want "DIDBR finite test +3/-4 11b" BFF00000 00000000 BFF00000 00000000 +r B2B0.08 +*Want "DIDBR finite test +3/-4 11b" 40080000 00000000 +r B2C0.10 +*Want "DIDBR finite test +4/-4 12a" 00000000 00000000 BFF00000 00000000 +r B2D0.08 +*Want "DIDBR finite test +4/-4 12a" 40100000 00000000 +r B2E0.10 +*Want "DIDBR finite test +4/-4 12b" 00000000 00000000 BFF00000 00000000 +r B2F0.08 +*Want "DIDBR finite test +4/-4 12b" 40100000 00000000 +r B300.10 +*Want "DIDBR finite test +5/-4 13a" 3FF00000 00000000 BFF00000 00000000 +r B310.08 +*Want "DIDBR finite test +5/-4 13a" 40140000 00000000 +r B320.10 +*Want "DIDBR finite test +5/-4 13b" 3FF00000 00000000 BFF00000 00000000 +r B330.08 +*Want "DIDBR finite test +5/-4 13b" 40140000 00000000 +r B340.10 +*Want "DIDBR finite test +6/-4 14a" C0000000 00000000 C0000000 00000000 +r B350.08 +*Want "DIDBR finite test +6/-4 14a" 40180000 00000000 +r B360.10 +*Want "DIDBR finite test +6/-4 14b" C0000000 00000000 C0000000 00000000 +r B370.08 +*Want "DIDBR finite test +6/-4 14b" 40180000 00000000 +r B380.10 +*Want "DIDBR finite test 15a" BFF00000 00000000 C0000000 00000000 +r B390.08 +*Want "DIDBR finite test 15a" 401C0000 00000000 +r B3A0.10 +*Want "DIDBR finite test 15b" BFF00000 00000000 C0000000 00000000 +r B3B0.08 +*Want "DIDBR finite test 15b" 401C0000 00000000 +r B3C0.10 +*Want "DIDBR finite test 16a" 00000000 00000000 C0000000 00000000 +r B3D0.08 +*Want "DIDBR finite test 16a" 40200000 00000000 +r B3E0.10 +*Want "DIDBR finite test 16b" 00000000 00000000 C0000000 00000000 +r B3F0.08 +*Want "DIDBR finite test 16b" 40200000 00000000 +r B400.10 +*Want "DIDBR finite test 17a" 80000000 00000000 C0000000 00000000 +r B410.08 +*Want "DIDBR finite test 17a" C0200000 00000000 +r B420.10 +*Want "DIDBR finite test 17b" 80000000 00000000 C0000000 00000000 +r B430.08 +*Want "DIDBR finite test 17b" C0200000 00000000 +r B440.10 +*Want "DIDBR finite test 18a" 3FF00000 00000000 C0000000 00000000 +r B450.08 +*Want "DIDBR finite test 18a" C01C0000 00000000 +r B460.10 +*Want "DIDBR finite test 18b" 3FF00000 00000000 C0000000 00000000 +r B470.08 +*Want "DIDBR finite test 18b" C01C0000 00000000 +r B480.10 +*Want "DIDBR finite test 19a" 40000000 00000000 C0000000 00000000 +r B490.08 +*Want "DIDBR finite test 19a" C0180000 00000000 +r B4A0.10 +*Want "DIDBR finite test 19b" 40000000 00000000 C0000000 00000000 +r B4B0.08 +*Want "DIDBR finite test 19b" C0180000 00000000 +r B4C0.10 +*Want "DIDBR finite test 20a" BFF00000 00000000 BFF00000 00000000 +r B4D0.08 +*Want "DIDBR finite test 20a" C0140000 00000000 +r B4E0.10 +*Want "DIDBR finite test 20b" BFF00000 00000000 BFF00000 00000000 +r B4F0.08 +*Want "DIDBR finite test 20b" C0140000 00000000 +r B500.10 +*Want "DIDBR finite test 21a" 80000000 00000000 BFF00000 00000000 +r B510.08 +*Want "DIDBR finite test 21a" C0100000 00000000 +r B520.10 +*Want "DIDBR finite test 21b" 80000000 00000000 BFF00000 00000000 +r B530.08 +*Want "DIDBR finite test 21b" C0100000 00000000 +r B540.10 +*Want "DIDBR finite test 22a" 3FF00000 00000000 BFF00000 00000000 +r B550.08 +*Want "DIDBR finite test 22a" C0080000 00000000 +r B560.10 +*Want "DIDBR finite test 22b" 3FF00000 00000000 BFF00000 00000000 +r B570.08 +*Want "DIDBR finite test 22b" C0080000 00000000 +r B580.10 +*Want "DIDBR finite test 23a" C0000000 00000000 80000000 00000000 +r B590.08 +*Want "DIDBR finite test 23a" C0000000 00000000 +r B5A0.10 +*Want "DIDBR finite test 23b" C0000000 00000000 80000000 00000000 +r B5B0.08 +*Want "DIDBR finite test 23b" C0000000 00000000 +r B5C0.10 +*Want "DIDBR finite test 24a" 3FF00000 00000000 00000000 00000000 +r B5D0.08 +*Want "DIDBR finite test 24a" 3FF00000 00000000 +r B5E0.10 +*Want "DIDBR finite test 24b" 3FF00000 00000000 00000000 00000000 +r B5F0.08 +*Want "DIDBR finite test 24b" 3FF00000 00000000 +r B600.10 +*Want "DIDBR finite test 25a" 3FF00000 00000000 00000000 00000000 +r B610.08 +*Want "DIDBR finite test 25a" 3FF00000 00000000 +r B620.10 +*Want "DIDBR finite test 25b" 3FF00000 00000000 00000000 00000000 +r B630.08 +*Want "DIDBR finite test 25b" 3FF00000 00000000 +r B640.10 +*Want "DIDBR finite test 26a" 40000000 00000000 00000000 00000000 +r B650.08 +*Want "DIDBR finite test 26a" 40000000 00000000 +r B660.10 +*Want "DIDBR finite test 26b" 40000000 00000000 00000000 00000000 +r B670.08 +*Want "DIDBR finite test 26b" 40000000 00000000 +r B680.10 +*Want "DIDBR finite test 27a" BFF00000 00000000 3FF00000 00000000 +r B690.08 +*Want "DIDBR finite test 27a" 40080000 00000000 +r B6A0.10 +*Want "DIDBR finite test 27b" BFF00000 00000000 3FF00000 00000000 +r B6B0.08 +*Want "DIDBR finite test 27b" 40080000 00000000 +r B6C0.10 +*Want "DIDBR finite test 28a" 00000000 00000000 3FF00000 00000000 +r B6D0.08 +*Want "DIDBR finite test 28a" 40100000 00000000 +r B6E0.10 +*Want "DIDBR finite test 28b" 00000000 00000000 3FF00000 00000000 +r B6F0.08 +*Want "DIDBR finite test 28b" 40100000 00000000 +r B700.10 +*Want "DIDBR finite test 29a" 3FF00000 00000000 3FF00000 00000000 +r B710.08 +*Want "DIDBR finite test 29a" 40140000 00000000 +r B720.10 +*Want "DIDBR finite test 29b" 3FF00000 00000000 3FF00000 00000000 +r B730.08 +*Want "DIDBR finite test 29b" 40140000 00000000 +r B740.10 +*Want "DIDBR finite test 30a" C0000000 00000000 40000000 00000000 +r B750.08 +*Want "DIDBR finite test 30a" 40180000 00000000 +r B760.10 +*Want "DIDBR finite test 30b" C0000000 00000000 40000000 00000000 +r B770.08 +*Want "DIDBR finite test 30b" 40180000 00000000 +r B780.10 +*Want "DIDBR finite test 31a" BFF00000 00000000 40000000 00000000 +r B790.08 +*Want "DIDBR finite test 31a" 401C0000 00000000 +r B7A0.10 +*Want "DIDBR finite test 31b" BFF00000 00000000 40000000 00000000 +r B7B0.08 +*Want "DIDBR finite test 31b" 401C0000 00000000 +r B7C0.10 +*Want "DIDBR finite test 32a" 00000000 00000000 40000000 00000000 +r B7D0.08 +*Want "DIDBR finite test 32a" 40200000 00000000 +r B7E0.10 +*Want "DIDBR finite test 32b" 00000000 00000000 40000000 00000000 +r B7F0.08 +*Want "DIDBR finite test 32b" 40200000 00000000 + +r B800.10 +*Want "DIDBR finite test 33a" 40100000 00000000 C0100000 00000000 +r B810.08 +*Want "DIDBR finite test 33a" 40440000 00000000 +r B820.10 +*Want "DIDBR finite test 33b" 40100000 00000000 C0100000 00000000 +r B830.08 +*Want "DIDBR finite test 33b" 40440000 00000000 + +r B840.10 +*Want "DIDBR finite test 34a" 00000000 00000000 630FFFFF FFFFFFFF +r B850.08 +*Want "DIDBR finite test 34a" 1FEFFFFF FFFFFFFF +r B860.10 +*Want "DIDBR finite test 34b" 00000000 00000000 630FFFFF FFFFFFFF +r B870.08 +*Want "DIDBR finite test 34b" 1FEFFFFF FFFFFFFF + +r B880.10 # Doubt the following are correct; need hardware validation +*Want "DIDBR finite test 35a" 7CA00000 00000000 62F55555 55555554 + +r B890.08 +*Want "DIDBR finite test 35a" 7CA00000 00000000 + +r B8A0.10 # Doubt the following are correct; need hardware validation +*Want "DIDBR finite test 35b" 7CA00000 00000000 62F55555 55555554 + +r B8B0.08 +*Want "DIDBR finite test 35b" 7CA00000 00000000 + +r B8C0.10 +*Want "DIDBR finite test 36a" 00000000 00000001 3FF00000 00000000 +r B8D0.08 +*Want "DIDBR finite test 36a" 000FFFFF FFFFFFFF + +r B8E0.10 +*Want "DIDBR finite test 36b" 5CD00000 00000000 3FF00000 00000000 + +r B8F0.08 +*Want "DIDBR finite test 36b" 5CD00000 00000000 + + +r B900.10 +*Want "DIDBR finite test 37a" 40100000 00000000 43555555 55555555 +r B910.08 +*Want "DIDBR finite test 37a" 43700000 00000000 +r B920.10 +*Want "DIDBR finite test 37b" 40100000 00000000 43555555 55555555 +r B930.08 +*Want "DIDBR finite test 37b" 43700000 00000000 + + +r B940.10 +*Want "DIDBR finite test 38a" 40020000 00000000 00000000 00000000 +r B950.08 +*Want "DIDBR finite test 38a" 40020000 00000000 +r B960.10 +*Want "DIDBR finite test 38b" 40020000 00000000 00000000 00000000 +r B970.08 +*Want "DIDBR finite test 38b" 40020000 00000000 + + +*Compare +# Two finites - BFP Long - FPCR & cc (cc unchanged by re-multiply) +r AC00.10 +*Want "DIDBR FPCR finite test -8/-4 1" 00000000 00000000 F8000000 00000000 +r AC10.10 +*Want "DIDBR FPCR finite test -7/-4 2" 00000000 00000000 F8000000 00000000 +r AC20.10 +*Want "DIDBR FPCR finite test -6/-4 3" 00000000 00000000 F8000000 00000000 +r AC30.10 +*Want "DIDBR FPCR finite test -5/-4 4" 00000000 00000000 F8000000 00000000 +r AC40.10 +*Want "DIDBR FPCR finite test -4/-4 5" 00000000 00000000 F8000000 00000000 +r AC50.10 +*Want "DIDBR FPCR finite test -3/-4 6" 00000000 00000000 F8000000 00000000 +r AC60.10 +*Want "DIDBR FPCR finite test -2/-4 7" 00000000 00000000 F8000000 00000000 +r AC70.10 +*Want "DIDBR FPCR finite test -1/-4 8" 00000000 00000000 F8000000 00000000 +r AC80.10 +*Want "DIDBR FPCR finite test +1/-4 9" 00000000 00000000 F8000000 00000000 +r AC90.10 +*Want "DIDBR FPCR finite test +2/-4 10" 00000000 00000000 F8000000 00000000 +r ACA0.10 +*Want "DIDBR FPCR finite test +3/-4 10" 00000000 00000000 F8000000 00000000 +r ACB0.10 +*Want "DIDBR FPCR finite test +4/-4 12" 00000000 00000000 F8000000 00000000 +r ACC0.10 +*Want "DIDBR FPCR finite test +5/-4 13" 00000000 00000000 F8000000 00000000 +r ACD0.10 +*Want "DIDBR FPCR finite test +6/-4 14" 00000000 00000000 F8000000 00000000 +r ACE0.10 +*Want "DIDBR FPCR finite test 15" 00000000 00000000 F8000000 00000000 +r ACF0.10 +*Want "DIDBR FPCR finite test 16" 00000000 00000000 F8000000 00000000 +r AD00.10 +*Want "DIDBR FPCR finite test 17" 00000000 00000000 F8000000 00000000 +r AD10.10 +*Want "DIDBR FPCR finite test 18" 00000000 00000000 F8000000 00000000 +r AD20.10 +*Want "DIDBR FPCR finite test 19" 00000000 00000000 F8000000 00000000 +r AD30.10 +*Want "DIDBR FPCR finite test 20" 00000000 00000000 F8000000 00000000 +r AD40.10 +*Want "DIDBR FPCR finite test 21" 00000000 00000000 F8000000 00000000 +r AD50.10 +*Want "DIDBR FPCR finite test 22" 00000000 00000000 F8000000 00000000 +r AD60.10 +*Want "DIDBR FPCR finite test 23" 00000000 00000000 F8000000 00000000 +r AD70.10 +*Want "DIDBR FPCR finite test 24" 00000000 00000000 F8000000 00000000 +r AD80.10 +*Want "DIDBR FPCR finite test 25" 00000000 00000000 F8000000 00000000 +r AD90.10 +*Want "DIDBR FPCR finite test 26" 00000000 00000000 F8000000 00000000 +r ADA0.10 +*Want "DIDBR FPCR finite test 27" 00000000 00000000 F8000000 00000000 +r ADB0.10 +*Want "DIDBR FPCR finite test 28" 00000000 00000000 F8000000 00000000 +r ADC0.10 +*Want "DIDBR FPCR finite test 29" 00000000 00000000 F8000000 00000000 +r ADD0.10 +*Want "DIDBR FPCR finite test 30" 00000000 00000000 F8000000 00000000 +r ADE0.10 +*Want "DIDBR FPCR finite test 31" 00000000 00000000 F8000000 00000000 +r ADF0.10 +*Want "DIDBR FPCR finite test 32" 00000000 00000000 F8000000 00000000 +r AE00.10 +*Want "DIDBR FPCR finite test 33" 00000000 00000000 F8000000 00000000 +r AE10.10 +*Want "DIDBR FPCR finite test 34" 00000001 00000001 F8000001 00000001 +r AE20.10 # unsure about case 3; hw validation required. +*Want "DIDBR FPCR finite test 35" 00000003 00080003 F8000003 00080003 +r AE30.10 +*Want "DIDBR FPCR finite test 36" 00000000 00000000 F8001000 00080000 +r AE40.10 +*Want "DIDBR FPCR finite test 37" 00000002 00000002 F8000002 00000002 +r AE50.10 +*Want "DIDBR FPCR finite test 38" 00000000 00000000 F8000000 00000000 + + +# Long BFP Exhaustive rounding tests +r 5000.10 # RZ / RNTA +*Want "DIDBR rounding test 1a NT" 3FE00000 00000000 C0140000 00000000 +r 5010.10 # RZ / RNTA +*Want "DIDBR rounding test 1a TR" 3FE00000 00000000 C0140000 00000000 +r 5020.10 # RZ / RFS +*Want "DIDBR rounding test 1b NT" 3FE00000 00000000 C0140000 00000000 +r 5030.10 # RZ / RFS +*Want "DIDBR rounding test 1b TR" 3FE00000 00000000 C0140000 00000000 +r 5040.10 # RZ / RNTE +*Want "DIDBR rounding test 1c NT" 3FE00000 00000000 C0140000 00000000 +r 5050.10 # RZ / RNTE +*Want "DIDBR rounding test 1c TR" 3FE00000 00000000 C0140000 00000000 +r 5060.10 # RZ / RZ +*Want "DIDBR rounding test 1d NT" BFF80000 00000000 C0100000 00000000 +r 5070.10 # RZ / RZ +*Want "DIDBR rounding test 1d TR" BFF80000 00000000 C0100000 00000000 +r 5080.10 # RZ / RP +*Want "DIDBR rounding test 1e NT" BFF80000 00000000 C0100000 00000000 +r 5090.10 # RZ / RP +*Want "DIDBR rounding test 1e TR" BFF80000 00000000 C0100000 00000000 +r 50A0.10 # RZ / RM +*Want "DIDBR rounding test 1f NT" 3FE00000 00000000 C0140000 00000000 +r 50B0.10 # RZ / RM +*Want "DIDBR rounding test 1f TR" 3FE00000 00000000 C0140000 00000000 +r 50C0.10 # RP / RNTA +*Want "DIDBR rounding test 1g NT" 3FE00000 00000000 C0140000 00000000 +r 50D0.10 # RP / RNTA +*Want "DIDBR rounding test 1g TR" 3FE00000 00000000 C0140000 00000000 +r 50E0.10 # RP / RFS +*Want "DIDBR rounding test 1h NT" 3FE00000 00000000 C0140000 00000000 +r 50F0.10 # RP / RFS +*Want "DIDBR rounding test 1h TR" 3FE00000 00000000 C0140000 00000000 +r 5100.10 # RP / RNTE +*Want "DIDBR rounding test 1i NT" 3FE00000 00000000 C0140000 00000000 +r 5110.10 # RP / RNTE +*Want "DIDBR rounding test 1i TR" 3FE00000 00000000 C0140000 00000000 +r 5120.10 # RP / RZ +*Want "DIDBR rounding test 1j NT" BFF80000 00000000 C0100000 00000000 +r 5130.10 # RP / RZ +*Want "DIDBR rounding test 1j TR" BFF80000 00000000 C0100000 00000000 +r 5140.10 # RP / RP +*Want "DIDBR rounding test 1k NT" BFF80000 00000000 C0100000 00000000 +r 5150.10 # RP / RP +*Want "DIDBR rounding test 1k TR" BFF80000 00000000 C0100000 00000000 +r 5160.10 # RP / RM +*Want "DIDBR rounding test 1l NT" 3FE00000 00000000 C0140000 00000000 +r 5170.10 # RP / RM +*Want "DIDBR rounding test 1l TR" 3FE00000 00000000 C0140000 00000000 +r 5180.10 # RM / RNTA +*Want "DIDBR rounding test 1m NT" 3FE00000 00000000 C0140000 00000000 +r 5190.10 # RM / RNTA +*Want "DIDBR rounding test 1m TR" 3FE00000 00000000 C0140000 00000000 +r 51A0.10 # RM / RFS +*Want "DIDBR rounding test 1n NT" 3FE00000 00000000 C0140000 00000000 +r 51B0.10 # RM / RFS +*Want "DIDBR rounding test 1n TR" 3FE00000 00000000 C0140000 00000000 +r 51C0.10 # RM / RNTE +*Want "DIDBR rounding test 1o NT" 3FE00000 00000000 C0140000 00000000 +r 51D0.10 # RM / RNTE +*Want "DIDBR rounding test 1o TR" 3FE00000 00000000 C0140000 00000000 +r 51E0.10 # RM / RZ +*Want "DIDBR rounding test 1p NT" BFF80000 00000000 C0100000 00000000 +r 51F0.10 # RM / RZ +*Want "DIDBR rounding test 1p TR" BFF80000 00000000 C0100000 00000000 +r 5200.10 # RM / RP +*Want "DIDBR rounding test 1q NT" BFF80000 00000000 C0100000 00000000 +r 5210.10 # RM / RP +*Want "DIDBR rounding test 1q TR" BFF80000 00000000 C0100000 00000000 +r 5220.10 # RM / RM +*Want "DIDBR rounding test 1r NT" 3FE00000 00000000 C0140000 00000000 +r 5230.10 # RM / RM +*Want "DIDBR rounding test 1r TR" 3FE00000 00000000 C0140000 00000000 +r 5240.10 # RFS / RNTA +*Want "DIDBR rounding test 1s NT" 3FE00000 00000000 C0140000 00000000 +r 5250.10 # RFS / RNTA +*Want "DIDBR rounding test 1s TR" 3FE00000 00000000 C0140000 00000000 +r 5260.10 # RFS / RFS +*Want "DIDBR rounding test 1t NT" 3FE00000 00000000 C0140000 00000000 +r 5270.10 # RFS / RFS +*Want "DIDBR rounding test 1t TR" 3FE00000 00000000 C0140000 00000000 +r 5280.10 # RFS / RNTE +*Want "DIDBR rounding test 1u NT" 3FE00000 00000000 C0140000 00000000 +r 5290.10 # RFS / RNTE +*Want "DIDBR rounding test 1u TR" 3FE00000 00000000 C0140000 00000000 +r 52A0.10 # RFS / RZ +*Want "DIDBR rounding test 1v NT" BFF80000 00000000 C0100000 00000000 +r 52B0.10 # RFS / RZ +*Want "DIDBR rounding test 1v TR" BFF80000 00000000 C0100000 00000000 +r 52C0.10 # RFS / RP +*Want "DIDBR rounding test 1w NT" BFF80000 00000000 C0100000 00000000 +r 52D0.10 # RFS / RP +*Want "DIDBR rounding test 1w TR" BFF80000 00000000 C0100000 00000000 +r 52E0.10 # RFS / RM +*Want "DIDBR rounding test 1x NT" 3FE00000 00000000 C0140000 00000000 +r 52F0.10 # RFS / RM +*Want "DIDBR rounding test 1x TR" 3FE00000 00000000 C0140000 00000000 +r 5300.10 # RZ / RNTA +*Want "DIDBR rounding test 2a NT" 3FE00000 00000000 C0080000 00000000 +r 5310.10 # RZ / RNTA +*Want "DIDBR rounding test 2a TR" 3FE00000 00000000 C0080000 00000000 +r 5320.10 # RZ / RFS +*Want "DIDBR rounding test 2b NT" 3FE00000 00000000 C0080000 00000000 +r 5330.10 # RZ / RFS +*Want "DIDBR rounding test 2b TR" 3FE00000 00000000 C0080000 00000000 +r 5340.10 # RZ / RNTE +*Want "DIDBR rounding test 2c NT" 3FE00000 00000000 C0080000 00000000 +r 5350.10 # RZ / RNTE +*Want "DIDBR rounding test 2c TR" 3FE00000 00000000 C0080000 00000000 +r 5360.10 # RZ / RZ +*Want "DIDBR rounding test 2d NT" BFF80000 00000000 C0000000 00000000 +r 5370.10 # RZ / RZ +*Want "DIDBR rounding test 2d TR" BFF80000 00000000 C0000000 00000000 +r 5380.10 # RZ / RP +*Want "DIDBR rounding test 2e NT" BFF80000 00000000 C0000000 00000000 +r 5390.10 # RZ / RP +*Want "DIDBR rounding test 2e TR" BFF80000 00000000 C0000000 00000000 +r 53A0.10 # RZ / RM +*Want "DIDBR rounding test 2f NT" 3FE00000 00000000 C0080000 00000000 +r 53B0.10 # RZ / RM +*Want "DIDBR rounding test 2f TR" 3FE00000 00000000 C0080000 00000000 +r 53C0.10 # RP / RNTA +*Want "DIDBR rounding test 2g NT" 3FE00000 00000000 C0080000 00000000 +r 53D0.10 # RP / RNTA +*Want "DIDBR rounding test 2g TR" 3FE00000 00000000 C0080000 00000000 +r 53E0.10 # RP / RFS +*Want "DIDBR rounding test 2h NT" 3FE00000 00000000 C0080000 00000000 +r 53F0.10 # RP / RFS +*Want "DIDBR rounding test 2h TR" 3FE00000 00000000 C0080000 00000000 +r 5400.10 # RP / RNTE +*Want "DIDBR rounding test 2i NT" 3FE00000 00000000 C0080000 00000000 +r 5410.10 # RP / RNTE +*Want "DIDBR rounding test 2i TR" 3FE00000 00000000 C0080000 00000000 +r 5420.10 # RP / RZ +*Want "DIDBR rounding test 2j NT" BFF80000 00000000 C0000000 00000000 +r 5430.10 # RP / RZ +*Want "DIDBR rounding test 2j TR" BFF80000 00000000 C0000000 00000000 +r 5440.10 # RP / RP +*Want "DIDBR rounding test 2k NT" BFF80000 00000000 C0000000 00000000 +r 5450.10 # RP / RP +*Want "DIDBR rounding test 2k TR" BFF80000 00000000 C0000000 00000000 +r 5460.10 # RP / RM +*Want "DIDBR rounding test 2l NT" 3FE00000 00000000 C0080000 00000000 +r 5470.10 # RP / RM +*Want "DIDBR rounding test 2l TR" 3FE00000 00000000 C0080000 00000000 +r 5480.10 # RM / RNTA +*Want "DIDBR rounding test 2m NT" 3FE00000 00000000 C0080000 00000000 +r 5490.10 # RM / RNTA +*Want "DIDBR rounding test 2m TR" 3FE00000 00000000 C0080000 00000000 +r 54A0.10 # RM / RFS +*Want "DIDBR rounding test 2n NT" 3FE00000 00000000 C0080000 00000000 +r 54B0.10 # RM / RFS +*Want "DIDBR rounding test 2n TR" 3FE00000 00000000 C0080000 00000000 +r 54C0.10 # RM / RNTE +*Want "DIDBR rounding test 2o NT" 3FE00000 00000000 C0080000 00000000 +r 54D0.10 # RM / RNTE +*Want "DIDBR rounding test 2o TR" 3FE00000 00000000 C0080000 00000000 +r 54E0.10 # RM / RZ +*Want "DIDBR rounding test 2p NT" BFF80000 00000000 C0000000 00000000 +r 54F0.10 # RM / RZ +*Want "DIDBR rounding test 2p TR" BFF80000 00000000 C0000000 00000000 +r 5500.10 # RM / RP +*Want "DIDBR rounding test 2q NT" BFF80000 00000000 C0000000 00000000 +r 5510.10 # RM / RP +*Want "DIDBR rounding test 2q TR" BFF80000 00000000 C0000000 00000000 +r 5520.10 # RM / RM +*Want "DIDBR rounding test 2r NT" 3FE00000 00000000 C0080000 00000000 +r 5530.10 # RM / RM +*Want "DIDBR rounding test 2r TR" 3FE00000 00000000 C0080000 00000000 +r 5540.10 # RFS / RNTA +*Want "DIDBR rounding test 2s NT" 3FE00000 00000000 C0080000 00000000 +r 5550.10 # RFS / RNTA +*Want "DIDBR rounding test 2s TR" 3FE00000 00000000 C0080000 00000000 +r 5560.10 # RFS / RFS +*Want "DIDBR rounding test 2t NT" 3FE00000 00000000 C0080000 00000000 +r 5570.10 # RFS / RFS +*Want "DIDBR rounding test 2t TR" 3FE00000 00000000 C0080000 00000000 +r 5580.10 # RFS / RNTE +*Want "DIDBR rounding test 2u NT" 3FE00000 00000000 C0080000 00000000 +r 5590.10 # RFS / RNTE +*Want "DIDBR rounding test 2u TR" 3FE00000 00000000 C0080000 00000000 +r 55A0.10 # RFS / RZ +*Want "DIDBR rounding test 2v NT" BFF80000 00000000 C0000000 00000000 +r 55B0.10 # RFS / RZ +*Want "DIDBR rounding test 2v TR" BFF80000 00000000 C0000000 00000000 +r 55C0.10 # RFS / RP +*Want "DIDBR rounding test 2w NT" BFF80000 00000000 C0000000 00000000 +r 55D0.10 # RFS / RP +*Want "DIDBR rounding test 2w TR" BFF80000 00000000 C0000000 00000000 +r 55E0.10 # RFS / RM +*Want "DIDBR rounding test 2x NT" 3FE00000 00000000 C0080000 00000000 +r 55F0.10 # RFS / RM +*Want "DIDBR rounding test 2x TR" 3FE00000 00000000 C0080000 00000000 +r 5600.10 # RZ / RNTA +*Want "DIDBR rounding test 3a NT" BFE00000 00000000 BFF00000 00000000 +r 5610.10 # RZ / RNTA +*Want "DIDBR rounding test 3a TR" BFE00000 00000000 BFF00000 00000000 +r 5620.10 # RZ / RFS +*Want "DIDBR rounding test 3b NT" BFE00000 00000000 BFF00000 00000000 +r 5630.10 # RZ / RFS +*Want "DIDBR rounding test 3b TR" BFE00000 00000000 BFF00000 00000000 +r 5640.10 # RZ / RNTE +*Want "DIDBR rounding test 3c NT" BFE00000 00000000 BFF00000 00000000 +r 5650.10 # RZ / RNTE +*Want "DIDBR rounding test 3c TR" BFE00000 00000000 BFF00000 00000000 +r 5660.10 # RZ / RZ +*Want "DIDBR rounding test 3d NT" BFE00000 00000000 BFF00000 00000000 +r 5670.10 # RZ / RZ +*Want "DIDBR rounding test 3d TR" BFE00000 00000000 BFF00000 00000000 +r 5680.10 # RZ / RP +*Want "DIDBR rounding test 3e NT" BFE00000 00000000 BFF00000 00000000 +r 5690.10 # RZ / RP +*Want "DIDBR rounding test 3e TR" BFE00000 00000000 BFF00000 00000000 +r 56A0.10 # RZ / RM +*Want "DIDBR rounding test 3f NT" 3FF80000 00000000 C0000000 00000000 +r 56B0.10 # RZ / RM +*Want "DIDBR rounding test 3f TR" 3FF80000 00000000 C0000000 00000000 +r 56C0.10 # RP / RNTA +*Want "DIDBR rounding test 3g NT" BFE00000 00000000 BFF00000 00000000 +r 56D0.10 # RP / RNTA +*Want "DIDBR rounding test 3g TR" BFE00000 00000000 BFF00000 00000000 +r 56E0.10 # RP / RFS +*Want "DIDBR rounding test 3h NT" BFE00000 00000000 BFF00000 00000000 +r 56F0.10 # RP / RFS +*Want "DIDBR rounding test 3h TR" BFE00000 00000000 BFF00000 00000000 +r 5700.10 # RP / RNTE +*Want "DIDBR rounding test 3i NT" BFE00000 00000000 BFF00000 00000000 +r 5710.10 # RP / RNTE +*Want "DIDBR rounding test 3i TR" BFE00000 00000000 BFF00000 00000000 +r 5720.10 # RP / RZ +*Want "DIDBR rounding test 3j NT" BFE00000 00000000 BFF00000 00000000 +r 5730.10 # RP / RZ +*Want "DIDBR rounding test 3j TR" BFE00000 00000000 BFF00000 00000000 +r 5740.10 # RP / RP +*Want "DIDBR rounding test 3k NT" BFE00000 00000000 BFF00000 00000000 +r 5750.10 # RP / RP +*Want "DIDBR rounding test 3k TR" BFE00000 00000000 BFF00000 00000000 +r 5760.10 # RP / RM +*Want "DIDBR rounding test 3l NT" 3FF80000 00000000 C0000000 00000000 +r 5770.10 # RP / RM +*Want "DIDBR rounding test 3l TR" 3FF80000 00000000 C0000000 00000000 +r 5780.10 # RM / RNTA +*Want "DIDBR rounding test 3m NT" BFE00000 00000000 BFF00000 00000000 +r 5790.10 # RM / RNTA +*Want "DIDBR rounding test 3m TR" BFE00000 00000000 BFF00000 00000000 +r 57A0.10 # RM / RFS +*Want "DIDBR rounding test 3n NT" BFE00000 00000000 BFF00000 00000000 +r 57B0.10 # RM / RFS +*Want "DIDBR rounding test 3n TR" BFE00000 00000000 BFF00000 00000000 +r 57C0.10 # RM / RNTE +*Want "DIDBR rounding test 3o NT" BFE00000 00000000 BFF00000 00000000 +r 57D0.10 # RM / RNTE +*Want "DIDBR rounding test 3o TR" BFE00000 00000000 BFF00000 00000000 +r 57E0.10 # RM / RZ +*Want "DIDBR rounding test 3p NT" BFE00000 00000000 BFF00000 00000000 +r 57F0.10 # RM / RZ +*Want "DIDBR rounding test 3p TR" BFE00000 00000000 BFF00000 00000000 +r 5800.10 # RM / RP +*Want "DIDBR rounding test 3q NT" BFE00000 00000000 BFF00000 00000000 +r 5810.10 # RM / RP +*Want "DIDBR rounding test 3q TR" BFE00000 00000000 BFF00000 00000000 +r 5820.10 # RM / RM +*Want "DIDBR rounding test 3r NT" 3FF80000 00000000 C0000000 00000000 +r 5830.10 # RM / RM +*Want "DIDBR rounding test 3r TR" 3FF80000 00000000 C0000000 00000000 +r 5840.10 # RFS / RNTA +*Want "DIDBR rounding test 3s NT" BFE00000 00000000 BFF00000 00000000 +r 5850.10 # RFS / RNTA +*Want "DIDBR rounding test 3s TR" BFE00000 00000000 BFF00000 00000000 +r 5860.10 # RFS / RFS +*Want "DIDBR rounding test 3t NT" BFE00000 00000000 BFF00000 00000000 +r 5870.10 # RFS / RFS +*Want "DIDBR rounding test 3t TR" BFE00000 00000000 BFF00000 00000000 +r 5880.10 # RFS / RNTE +*Want "DIDBR rounding test 3u NT" BFE00000 00000000 BFF00000 00000000 +r 5890.10 # RFS / RNTE +*Want "DIDBR rounding test 3u TR" BFE00000 00000000 BFF00000 00000000 +r 58A0.10 # RFS / RZ +*Want "DIDBR rounding test 3v NT" BFE00000 00000000 BFF00000 00000000 +r 58B0.10 # RFS / RZ +*Want "DIDBR rounding test 3v TR" BFE00000 00000000 BFF00000 00000000 +r 58C0.10 # RFS / RP +*Want "DIDBR rounding test 3w NT" BFE00000 00000000 BFF00000 00000000 +r 58D0.10 # RFS / RP +*Want "DIDBR rounding test 3w TR" BFE00000 00000000 BFF00000 00000000 +r 58E0.10 # RFS / RM +*Want "DIDBR rounding test 3x NT" 3FF80000 00000000 C0000000 00000000 +r 58F0.10 # RFS / RM +*Want "DIDBR rounding test 3x TR" 3FF80000 00000000 C0000000 00000000 +r 5900.10 # RZ / RNTA +*Want "DIDBR rounding test 4a NT" 3FE00000 00000000 BFF00000 00000000 +r 5910.10 # RZ / RNTA +*Want "DIDBR rounding test 4a TR" 3FE00000 00000000 BFF00000 00000000 +r 5920.10 # RZ / RFS +*Want "DIDBR rounding test 4b NT" 3FE00000 00000000 BFF00000 00000000 +r 5930.10 # RZ / RFS +*Want "DIDBR rounding test 4b TR" 3FE00000 00000000 BFF00000 00000000 +r 5940.10 # RZ / RNTE +*Want "DIDBR rounding test 4c NT" 3FE00000 00000000 BFF00000 00000000 +r 5950.10 # RZ / RNTE +*Want "DIDBR rounding test 4c TR" 3FE00000 00000000 BFF00000 00000000 +r 5960.10 # RZ / RZ +*Want "DIDBR rounding test 4d NT" BFF80000 00000000 80000000 00000000 +r 5970.10 # RZ / RZ +*Want "DIDBR rounding test 4d TR" BFF80000 00000000 80000000 00000000 +r 5980.10 # RZ / RP +*Want "DIDBR rounding test 4e NT" BFF80000 00000000 80000000 00000000 +r 5990.10 # RZ / RP +*Want "DIDBR rounding test 4e TR" BFF80000 00000000 80000000 00000000 +r 59A0.10 # RZ / RM +*Want "DIDBR rounding test 4f NT" 3FE00000 00000000 BFF00000 00000000 +r 59B0.10 # RZ / RM +*Want "DIDBR rounding test 4f TR" 3FE00000 00000000 BFF00000 00000000 +r 59C0.10 # RP / RNTA +*Want "DIDBR rounding test 4g NT" 3FE00000 00000000 BFF00000 00000000 +r 59D0.10 # RP / RNTA +*Want "DIDBR rounding test 4g TR" 3FE00000 00000000 BFF00000 00000000 +r 59E0.10 # RP / RFS +*Want "DIDBR rounding test 4h NT" 3FE00000 00000000 BFF00000 00000000 +r 59F0.10 # RP / RFS +*Want "DIDBR rounding test 4h TR" 3FE00000 00000000 BFF00000 00000000 +r 5A00.10 # RP / RNTE +*Want "DIDBR rounding test 4i NT" 3FE00000 00000000 BFF00000 00000000 +r 5A10.10 # RP / RNTE +*Want "DIDBR rounding test 4i TR" 3FE00000 00000000 BFF00000 00000000 +r 5A20.10 # RP / RZ +*Want "DIDBR rounding test 4j NT" BFF80000 00000000 80000000 00000000 +r 5A30.10 # RP / RZ +*Want "DIDBR rounding test 4j TR" BFF80000 00000000 80000000 00000000 +r 5A40.10 # RP / RP +*Want "DIDBR rounding test 4k NT" BFF80000 00000000 80000000 00000000 +r 5A50.10 # RP / RP +*Want "DIDBR rounding test 4k TR" BFF80000 00000000 80000000 00000000 +r 5A60.10 # RP / RM +*Want "DIDBR rounding test 4l NT" 3FE00000 00000000 BFF00000 00000000 +r 5A70.10 # RP / RM +*Want "DIDBR rounding test 4l TR" 3FE00000 00000000 BFF00000 00000000 +r 5A80.10 # RM / RNTA +*Want "DIDBR rounding test 4m NT" 3FE00000 00000000 BFF00000 00000000 +r 5A90.10 # RM / RNTA +*Want "DIDBR rounding test 4m TR" 3FE00000 00000000 BFF00000 00000000 +r 5AA0.10 # RM / RFS +*Want "DIDBR rounding test 4n NT" 3FE00000 00000000 BFF00000 00000000 +r 5AB0.10 # RM / RFS +*Want "DIDBR rounding test 4n TR" 3FE00000 00000000 BFF00000 00000000 +r 5AC0.10 # RM / RNTE +*Want "DIDBR rounding test 4o NT" 3FE00000 00000000 BFF00000 00000000 +r 5AD0.10 # RM / RNTE +*Want "DIDBR rounding test 4o TR" 3FE00000 00000000 BFF00000 00000000 +r 5AE0.10 # RM / RZ +*Want "DIDBR rounding test 4p NT" BFF80000 00000000 80000000 00000000 +r 5AF0.10 # RM / RZ +*Want "DIDBR rounding test 4p TR" BFF80000 00000000 80000000 00000000 +r 5B00.10 # RM / RP +*Want "DIDBR rounding test 4q NT" BFF80000 00000000 80000000 00000000 +r 5B10.10 # RM / RP +*Want "DIDBR rounding test 4q TR" BFF80000 00000000 80000000 00000000 +r 5B20.10 # RM / RM +*Want "DIDBR rounding test 4r NT" 3FE00000 00000000 BFF00000 00000000 +r 5B30.10 # RM / RM +*Want "DIDBR rounding test 4r TR" 3FE00000 00000000 BFF00000 00000000 +r 5B40.10 # RFS / RNTA +*Want "DIDBR rounding test 4s NT" 3FE00000 00000000 BFF00000 00000000 +r 5B50.10 # RFS / RNTA +*Want "DIDBR rounding test 4s TR" 3FE00000 00000000 BFF00000 00000000 +r 5B60.10 # RFS / RFS +*Want "DIDBR rounding test 4t NT" 3FE00000 00000000 BFF00000 00000000 +r 5B70.10 # RFS / RFS +*Want "DIDBR rounding test 4t TR" 3FE00000 00000000 BFF00000 00000000 +r 5B80.10 # RFS / RNTE +*Want "DIDBR rounding test 4u NT" 3FE00000 00000000 BFF00000 00000000 +r 5B90.10 # RFS / RNTE +*Want "DIDBR rounding test 4u TR" 3FE00000 00000000 BFF00000 00000000 +r 5BA0.10 # RFS / RZ +*Want "DIDBR rounding test 4v NT" BFF80000 00000000 80000000 00000000 +r 5BB0.10 # RFS / RZ +*Want "DIDBR rounding test 4v TR" BFF80000 00000000 80000000 00000000 +r 5BC0.10 # RFS / RP +*Want "DIDBR rounding test 4w NT" BFF80000 00000000 80000000 00000000 +r 5BD0.10 # RFS / RP +*Want "DIDBR rounding test 4w TR" BFF80000 00000000 80000000 00000000 +r 5BE0.10 # RFS / RM +*Want "DIDBR rounding test 4x NT" 3FE00000 00000000 BFF00000 00000000 +r 5BF0.10 # RFS / RM +*Want "DIDBR rounding test 4x TR" 3FE00000 00000000 BFF00000 00000000 +r 5C00.10 # RZ / RNTA +*Want "DIDBR rounding test 5a NT" BFE00000 00000000 80000000 00000000 +r 5C10.10 # RZ / RNTA +*Want "DIDBR rounding test 5a TR" BFE00000 00000000 80000000 00000000 +r 5C20.10 # RZ / RFS +*Want "DIDBR rounding test 5b NT" 3FF80000 00000000 BFF00000 00000000 +r 5C30.10 # RZ / RFS +*Want "DIDBR rounding test 5b TR" 3FF80000 00000000 BFF00000 00000000 +r 5C40.10 # RZ / RNTE +*Want "DIDBR rounding test 5c NT" BFE00000 00000000 80000000 00000000 +r 5C50.10 # RZ / RNTE +*Want "DIDBR rounding test 5c TR" BFE00000 00000000 80000000 00000000 +r 5C60.10 # RZ / RZ +*Want "DIDBR rounding test 5d NT" BFE00000 00000000 80000000 00000000 +r 5C70.10 # RZ / RZ +*Want "DIDBR rounding test 5d TR" BFE00000 00000000 80000000 00000000 +r 5C80.10 # RZ / RP +*Want "DIDBR rounding test 5e NT" BFE00000 00000000 80000000 00000000 +r 5C90.10 # RZ / RP +*Want "DIDBR rounding test 5e TR" BFE00000 00000000 80000000 00000000 +r 5CA0.10 # RZ / RM +*Want "DIDBR rounding test 5f NT" 3FF80000 00000000 BFF00000 00000000 +r 5CB0.10 # RZ / RM +*Want "DIDBR rounding test 5f TR" 3FF80000 00000000 BFF00000 00000000 +r 5CC0.10 # RP / RNTA +*Want "DIDBR rounding test 5g NT" BFE00000 00000000 80000000 00000000 +r 5CD0.10 # RP / RNTA +*Want "DIDBR rounding test 5g TR" BFE00000 00000000 80000000 00000000 +r 5CE0.10 # RP / RFS +*Want "DIDBR rounding test 5h NT" 3FF80000 00000000 BFF00000 00000000 +r 5CF0.10 # RP / RFS +*Want "DIDBR rounding test 5h TR" 3FF80000 00000000 BFF00000 00000000 +r 5D00.10 # RP / RNTE +*Want "DIDBR rounding test 5i NT" BFE00000 00000000 80000000 00000000 +r 5D10.10 # RP / RNTE +*Want "DIDBR rounding test 5i TR" BFE00000 00000000 80000000 00000000 +r 5D20.10 # RP / RZ +*Want "DIDBR rounding test 5j NT" BFE00000 00000000 80000000 00000000 +r 5D30.10 # RP / RZ +*Want "DIDBR rounding test 5j TR" BFE00000 00000000 80000000 00000000 +r 5D40.10 # RP / RP +*Want "DIDBR rounding test 5k NT" BFE00000 00000000 80000000 00000000 +r 5D50.10 # RP / RP +*Want "DIDBR rounding test 5k TR" BFE00000 00000000 80000000 00000000 +r 5D60.10 # RP / RM +*Want "DIDBR rounding test 5l NT" 3FF80000 00000000 BFF00000 00000000 +r 5D70.10 # RP / RM +*Want "DIDBR rounding test 5l TR" 3FF80000 00000000 BFF00000 00000000 +r 5D80.10 # RM / RNTA +*Want "DIDBR rounding test 5m NT" BFE00000 00000000 80000000 00000000 +r 5D90.10 # RM / RNTA +*Want "DIDBR rounding test 5m TR" BFE00000 00000000 80000000 00000000 +r 5DA0.10 # RM / RFS +*Want "DIDBR rounding test 5n NT" 3FF80000 00000000 BFF00000 00000000 +r 5DB0.10 # RM / RFS +*Want "DIDBR rounding test 5n TR" 3FF80000 00000000 BFF00000 00000000 +r 5DC0.10 # RM / RNTE +*Want "DIDBR rounding test 5o NT" BFE00000 00000000 80000000 00000000 +r 5DD0.10 # RM / RNTE +*Want "DIDBR rounding test 5o TR" BFE00000 00000000 80000000 00000000 +r 5DE0.10 # RM / RZ +*Want "DIDBR rounding test 5p NT" BFE00000 00000000 80000000 00000000 +r 5DF0.10 # RM / RZ +*Want "DIDBR rounding test 5p TR" BFE00000 00000000 80000000 00000000 +r 5E00.10 # RM / RP +*Want "DIDBR rounding test 5q NT" BFE00000 00000000 80000000 00000000 +r 5E10.10 # RM / RP +*Want "DIDBR rounding test 5q TR" BFE00000 00000000 80000000 00000000 +r 5E20.10 # RM / RM +*Want "DIDBR rounding test 5r NT" 3FF80000 00000000 BFF00000 00000000 +r 5E30.10 # RM / RM +*Want "DIDBR rounding test 5r TR" 3FF80000 00000000 BFF00000 00000000 +r 5E40.10 # RFS / RNTA +*Want "DIDBR rounding test 5s NT" BFE00000 00000000 80000000 00000000 +r 5E50.10 # RFS / RNTA +*Want "DIDBR rounding test 5s TR" BFE00000 00000000 80000000 00000000 +r 5E60.10 # RFS / RFS +*Want "DIDBR rounding test 5t NT" 3FF80000 00000000 BFF00000 00000000 +r 5E70.10 # RFS / RFS +*Want "DIDBR rounding test 5t TR" 3FF80000 00000000 BFF00000 00000000 +r 5E80.10 # RFS / RNTE +*Want "DIDBR rounding test 5u NT" BFE00000 00000000 80000000 00000000 +r 5E90.10 # RFS / RNTE +*Want "DIDBR rounding test 5u TR" BFE00000 00000000 80000000 00000000 +r 5EA0.10 # RFS / RZ +*Want "DIDBR rounding test 5v NT" BFE00000 00000000 80000000 00000000 +r 5EB0.10 # RFS / RZ +*Want "DIDBR rounding test 5v TR" BFE00000 00000000 80000000 00000000 +r 5EC0.10 # RFS / RP +*Want "DIDBR rounding test 5w NT" BFE00000 00000000 80000000 00000000 +r 5ED0.10 # RFS / RP +*Want "DIDBR rounding test 5w TR" BFE00000 00000000 80000000 00000000 +r 5EE0.10 # RFS / RM +*Want "DIDBR rounding test 5x NT" 3FF80000 00000000 BFF00000 00000000 +r 5EF0.10 # RFS / RM +*Want "DIDBR rounding test 5x TR" 3FF80000 00000000 BFF00000 00000000 +r 5F00.10 # RZ / RNTA +*Want "DIDBR rounding test 6a NT" 3FE00000 00000000 00000000 00000000 +r 5F10.10 # RZ / RNTA +*Want "DIDBR rounding test 6a TR" 3FE00000 00000000 00000000 00000000 +r 5F20.10 # RZ / RFS +*Want "DIDBR rounding test 6b NT" BFF80000 00000000 3FF00000 00000000 +r 5F30.10 # RZ / RFS +*Want "DIDBR rounding test 6b TR" BFF80000 00000000 3FF00000 00000000 +r 5F40.10 # RZ / RNTE +*Want "DIDBR rounding test 6c NT" 3FE00000 00000000 00000000 00000000 +r 5F50.10 # RZ / RNTE +*Want "DIDBR rounding test 6c TR" 3FE00000 00000000 00000000 00000000 +r 5F60.10 # RZ / RZ +*Want "DIDBR rounding test 6d NT" 3FE00000 00000000 00000000 00000000 +r 5F70.10 # RZ / RZ +*Want "DIDBR rounding test 6d TR" 3FE00000 00000000 00000000 00000000 +r 5F80.10 # RZ / RP +*Want "DIDBR rounding test 6e NT" BFF80000 00000000 3FF00000 00000000 +r 5F90.10 # RZ / RP +*Want "DIDBR rounding test 6e TR" BFF80000 00000000 3FF00000 00000000 +r 5FA0.10 # RZ / RM +*Want "DIDBR rounding test 6f NT" 3FE00000 00000000 00000000 00000000 +r 5FB0.10 # RZ / RM +*Want "DIDBR rounding test 6f TR" 3FE00000 00000000 00000000 00000000 +r 5FC0.10 # RP / RNTA +*Want "DIDBR rounding test 6g NT" 3FE00000 00000000 00000000 00000000 +r 5FD0.10 # RP / RNTA +*Want "DIDBR rounding test 6g TR" 3FE00000 00000000 00000000 00000000 +r 5FE0.10 # RP / RFS +*Want "DIDBR rounding test 6h NT" BFF80000 00000000 3FF00000 00000000 +r 5FF0.10 # RP / RFS +*Want "DIDBR rounding test 6h TR" BFF80000 00000000 3FF00000 00000000 +r 6000.10 # RP / RNTE +*Want "DIDBR rounding test 6i NT" 3FE00000 00000000 00000000 00000000 +r 6010.10 # RP / RNTE +*Want "DIDBR rounding test 6i TR" 3FE00000 00000000 00000000 00000000 +r 6020.10 # RP / RZ +*Want "DIDBR rounding test 6j NT" 3FE00000 00000000 00000000 00000000 +r 6030.10 # RP / RZ +*Want "DIDBR rounding test 6j TR" 3FE00000 00000000 00000000 00000000 +r 6040.10 # RP / RP +*Want "DIDBR rounding test 6k NT" BFF80000 00000000 3FF00000 00000000 +r 6050.10 # RP / RP +*Want "DIDBR rounding test 6k TR" BFF80000 00000000 3FF00000 00000000 +r 6060.10 # RP / RM +*Want "DIDBR rounding test 6l NT" 3FE00000 00000000 00000000 00000000 +r 6070.10 # RP / RM +*Want "DIDBR rounding test 6l TR" 3FE00000 00000000 00000000 00000000 +r 6080.10 # RM / RNTA +*Want "DIDBR rounding test 6m NT" 3FE00000 00000000 00000000 00000000 +r 6090.10 # RM / RNTA +*Want "DIDBR rounding test 6m TR" 3FE00000 00000000 00000000 00000000 +r 60A0.10 # RM / RFS +*Want "DIDBR rounding test 6n NT" BFF80000 00000000 3FF00000 00000000 +r 60B0.10 # RM / RFS +*Want "DIDBR rounding test 6n TR" BFF80000 00000000 3FF00000 00000000 +r 60C0.10 # RM / RNTE +*Want "DIDBR rounding test 6o NT" 3FE00000 00000000 00000000 00000000 +r 60D0.10 # RM / RNTE +*Want "DIDBR rounding test 6o TR" 3FE00000 00000000 00000000 00000000 +r 60E0.10 # RM / RZ +*Want "DIDBR rounding test 6p NT" 3FE00000 00000000 00000000 00000000 +r 60F0.10 # RM / RZ +*Want "DIDBR rounding test 6p TR" 3FE00000 00000000 00000000 00000000 +r 6100.10 # RM / RP +*Want "DIDBR rounding test 6q NT" BFF80000 00000000 3FF00000 00000000 +r 6110.10 # RM / RP +*Want "DIDBR rounding test 6q TR" BFF80000 00000000 3FF00000 00000000 +r 6120.10 # RM / RM +*Want "DIDBR rounding test 6r NT" 3FE00000 00000000 00000000 00000000 +r 6130.10 # RM / RM +*Want "DIDBR rounding test 6r TR" 3FE00000 00000000 00000000 00000000 +r 6140.10 # RFS / RNTA +*Want "DIDBR rounding test 6s NT" 3FE00000 00000000 00000000 00000000 +r 6150.10 # RFS / RNTA +*Want "DIDBR rounding test 6s TR" 3FE00000 00000000 00000000 00000000 +r 6160.10 # RFS / RFS +*Want "DIDBR rounding test 6t NT" BFF80000 00000000 3FF00000 00000000 +r 6170.10 # RFS / RFS +*Want "DIDBR rounding test 6t TR" BFF80000 00000000 3FF00000 00000000 +r 6180.10 # RFS / RNTE +*Want "DIDBR rounding test 6u NT" 3FE00000 00000000 00000000 00000000 +r 6190.10 # RFS / RNTE +*Want "DIDBR rounding test 6u TR" 3FE00000 00000000 00000000 00000000 +r 61A0.10 # RFS / RZ +*Want "DIDBR rounding test 6v NT" 3FE00000 00000000 00000000 00000000 +r 61B0.10 # RFS / RZ +*Want "DIDBR rounding test 6v TR" 3FE00000 00000000 00000000 00000000 +r 61C0.10 # RFS / RP +*Want "DIDBR rounding test 6w NT" BFF80000 00000000 3FF00000 00000000 +r 61D0.10 # RFS / RP +*Want "DIDBR rounding test 6w TR" BFF80000 00000000 3FF00000 00000000 +r 61E0.10 # RFS / RM +*Want "DIDBR rounding test 6x NT" 3FE00000 00000000 00000000 00000000 +r 61F0.10 # RFS / RM +*Want "DIDBR rounding test 6x TR" 3FE00000 00000000 00000000 00000000 +r 6200.10 # RZ / RNTA +*Want "DIDBR rounding test 7a NT" BFE00000 00000000 3FF00000 00000000 +r 6210.10 # RZ / RNTA +*Want "DIDBR rounding test 7a TR" BFE00000 00000000 3FF00000 00000000 +r 6220.10 # RZ / RFS +*Want "DIDBR rounding test 7b NT" BFE00000 00000000 3FF00000 00000000 +r 6230.10 # RZ / RFS +*Want "DIDBR rounding test 7b TR" BFE00000 00000000 3FF00000 00000000 +r 6240.10 # RZ / RNTE +*Want "DIDBR rounding test 7c NT" BFE00000 00000000 3FF00000 00000000 +r 6250.10 # RZ / RNTE +*Want "DIDBR rounding test 7c TR" BFE00000 00000000 3FF00000 00000000 +r 6260.10 # RZ / RZ +*Want "DIDBR rounding test 7d NT" 3FF80000 00000000 00000000 00000000 +r 6270.10 # RZ / RZ +*Want "DIDBR rounding test 7d TR" 3FF80000 00000000 00000000 00000000 +r 6280.10 # RZ / RP +*Want "DIDBR rounding test 7e NT" BFE00000 00000000 3FF00000 00000000 +r 6290.10 # RZ / RP +*Want "DIDBR rounding test 7e TR" BFE00000 00000000 3FF00000 00000000 +r 62A0.10 # RZ / RM +*Want "DIDBR rounding test 7f NT" 3FF80000 00000000 00000000 00000000 +r 62B0.10 # RZ / RM +*Want "DIDBR rounding test 7f TR" 3FF80000 00000000 00000000 00000000 +r 62C0.10 # RP / RNTA +*Want "DIDBR rounding test 7g NT" BFE00000 00000000 3FF00000 00000000 +r 62D0.10 # RP / RNTA +*Want "DIDBR rounding test 7g TR" BFE00000 00000000 3FF00000 00000000 +r 62E0.10 # RP / RFS +*Want "DIDBR rounding test 7h NT" BFE00000 00000000 3FF00000 00000000 +r 62F0.10 # RP / RFS +*Want "DIDBR rounding test 7h TR" BFE00000 00000000 3FF00000 00000000 +r 6300.10 # RP / RNTE +*Want "DIDBR rounding test 7i NT" BFE00000 00000000 3FF00000 00000000 +r 6310.10 # RP / RNTE +*Want "DIDBR rounding test 7i TR" BFE00000 00000000 3FF00000 00000000 +r 6320.10 # RP / RZ +*Want "DIDBR rounding test 7j NT" 3FF80000 00000000 00000000 00000000 +r 6330.10 # RP / RZ +*Want "DIDBR rounding test 7j TR" 3FF80000 00000000 00000000 00000000 +r 6340.10 # RP / RP +*Want "DIDBR rounding test 7k NT" BFE00000 00000000 3FF00000 00000000 +r 6350.10 # RP / RP +*Want "DIDBR rounding test 7k TR" BFE00000 00000000 3FF00000 00000000 +r 6360.10 # RP / RM +*Want "DIDBR rounding test 7l NT" 3FF80000 00000000 00000000 00000000 +r 6370.10 # RP / RM +*Want "DIDBR rounding test 7l TR" 3FF80000 00000000 00000000 00000000 +r 6380.10 # RM / RNTA +*Want "DIDBR rounding test 7m NT" BFE00000 00000000 3FF00000 00000000 +r 6390.10 # RM / RNTA +*Want "DIDBR rounding test 7m TR" BFE00000 00000000 3FF00000 00000000 +r 63A0.10 # RM / RFS +*Want "DIDBR rounding test 7n NT" BFE00000 00000000 3FF00000 00000000 +r 63B0.10 # RM / RFS +*Want "DIDBR rounding test 7n TR" BFE00000 00000000 3FF00000 00000000 +r 63C0.10 # RM / RNTE +*Want "DIDBR rounding test 7o NT" BFE00000 00000000 3FF00000 00000000 +r 63D0.10 # RM / RNTE +*Want "DIDBR rounding test 7o TR" BFE00000 00000000 3FF00000 00000000 +r 63E0.10 # RM / RZ +*Want "DIDBR rounding test 7p NT" 3FF80000 00000000 00000000 00000000 +r 63F0.10 # RM / RZ +*Want "DIDBR rounding test 7p TR" 3FF80000 00000000 00000000 00000000 +r 6400.10 # RM / RP +*Want "DIDBR rounding test 7q NT" BFE00000 00000000 3FF00000 00000000 +r 6410.10 # RM / RP +*Want "DIDBR rounding test 7q TR" BFE00000 00000000 3FF00000 00000000 +r 6420.10 # RM / RM +*Want "DIDBR rounding test 7r NT" 3FF80000 00000000 00000000 00000000 +r 6430.10 # RM / RM +*Want "DIDBR rounding test 7r TR" 3FF80000 00000000 00000000 00000000 +r 6440.10 # RFS / RNTA +*Want "DIDBR rounding test 7s NT" BFE00000 00000000 3FF00000 00000000 +r 6450.10 # RFS / RNTA +*Want "DIDBR rounding test 7s TR" BFE00000 00000000 3FF00000 00000000 +r 6460.10 # RFS / RFS +*Want "DIDBR rounding test 7t NT" BFE00000 00000000 3FF00000 00000000 +r 6470.10 # RFS / RFS +*Want "DIDBR rounding test 7t TR" BFE00000 00000000 3FF00000 00000000 +r 6480.10 # RFS / RNTE +*Want "DIDBR rounding test 7u NT" BFE00000 00000000 3FF00000 00000000 +r 6490.10 # RFS / RNTE +*Want "DIDBR rounding test 7u TR" BFE00000 00000000 3FF00000 00000000 +r 64A0.10 # RFS / RZ +*Want "DIDBR rounding test 7v NT" 3FF80000 00000000 00000000 00000000 +r 64B0.10 # RFS / RZ +*Want "DIDBR rounding test 7v TR" 3FF80000 00000000 00000000 00000000 +r 64C0.10 # RFS / RP +*Want "DIDBR rounding test 7w NT" BFE00000 00000000 3FF00000 00000000 +r 64D0.10 # RFS / RP +*Want "DIDBR rounding test 7w TR" BFE00000 00000000 3FF00000 00000000 +r 64E0.10 # RFS / RM +*Want "DIDBR rounding test 7x NT" 3FF80000 00000000 00000000 00000000 +r 64F0.10 # RFS / RM +*Want "DIDBR rounding test 7x TR" 3FF80000 00000000 00000000 00000000 +r 6500.10 # RZ / RNTA +*Want "DIDBR rounding test 8a NT" 3FE00000 00000000 3FF00000 00000000 +r 6510.10 # RZ / RNTA +*Want "DIDBR rounding test 8a TR" 3FE00000 00000000 3FF00000 00000000 +r 6520.10 # RZ / RFS +*Want "DIDBR rounding test 8b NT" 3FE00000 00000000 3FF00000 00000000 +r 6530.10 # RZ / RFS +*Want "DIDBR rounding test 8b TR" 3FE00000 00000000 3FF00000 00000000 +r 6540.10 # RZ / RNTE +*Want "DIDBR rounding test 8c NT" 3FE00000 00000000 3FF00000 00000000 +r 6550.10 # RZ / RNTE +*Want "DIDBR rounding test 8c TR" 3FE00000 00000000 3FF00000 00000000 +r 6560.10 # RZ / RZ +*Want "DIDBR rounding test 8d NT" 3FE00000 00000000 3FF00000 00000000 +r 6570.10 # RZ / RZ +*Want "DIDBR rounding test 8d TR" 3FE00000 00000000 3FF00000 00000000 +r 6580.10 # RZ / RP +*Want "DIDBR rounding test 8e NT" BFF80000 00000000 40000000 00000000 +r 6590.10 # RZ / RP +*Want "DIDBR rounding test 8e TR" BFF80000 00000000 40000000 00000000 +r 65A0.10 # RZ / RM +*Want "DIDBR rounding test 8f NT" 3FE00000 00000000 3FF00000 00000000 +r 65B0.10 # RZ / RM +*Want "DIDBR rounding test 8f TR" 3FE00000 00000000 3FF00000 00000000 +r 65C0.10 # RP / RNTA +*Want "DIDBR rounding test 8g NT" 3FE00000 00000000 3FF00000 00000000 +r 65D0.10 # RP / RNTA +*Want "DIDBR rounding test 8g TR" 3FE00000 00000000 3FF00000 00000000 +r 65E0.10 # RP / RFS +*Want "DIDBR rounding test 8h NT" 3FE00000 00000000 3FF00000 00000000 +r 65F0.10 # RP / RFS +*Want "DIDBR rounding test 8h TR" 3FE00000 00000000 3FF00000 00000000 +r 6600.10 # RP / RNTE +*Want "DIDBR rounding test 8i NT" 3FE00000 00000000 3FF00000 00000000 +r 6610.10 # RP / RNTE +*Want "DIDBR rounding test 8i TR" 3FE00000 00000000 3FF00000 00000000 +r 6620.10 # RP / RZ +*Want "DIDBR rounding test 8j NT" 3FE00000 00000000 3FF00000 00000000 +r 6630.10 # RP / RZ +*Want "DIDBR rounding test 8j TR" 3FE00000 00000000 3FF00000 00000000 +r 6640.10 # RP / RP +*Want "DIDBR rounding test 8k NT" BFF80000 00000000 40000000 00000000 +r 6650.10 # RP / RP +*Want "DIDBR rounding test 8k TR" BFF80000 00000000 40000000 00000000 +r 6660.10 # RP / RM +*Want "DIDBR rounding test 8l NT" 3FE00000 00000000 3FF00000 00000000 +r 6670.10 # RP / RM +*Want "DIDBR rounding test 8l TR" 3FE00000 00000000 3FF00000 00000000 +r 6680.10 # RM / RNTA +*Want "DIDBR rounding test 8m NT" 3FE00000 00000000 3FF00000 00000000 +r 6690.10 # RM / RNTA +*Want "DIDBR rounding test 8m TR" 3FE00000 00000000 3FF00000 00000000 +r 66A0.10 # RM / RFS +*Want "DIDBR rounding test 8n NT" 3FE00000 00000000 3FF00000 00000000 +r 66B0.10 # RM / RFS +*Want "DIDBR rounding test 8n TR" 3FE00000 00000000 3FF00000 00000000 +r 66C0.10 # RM / RNTE +*Want "DIDBR rounding test 8o NT" 3FE00000 00000000 3FF00000 00000000 +r 66D0.10 # RM / RNTE +*Want "DIDBR rounding test 8o TR" 3FE00000 00000000 3FF00000 00000000 +r 66E0.10 # RM / RZ +*Want "DIDBR rounding test 8p NT" 3FE00000 00000000 3FF00000 00000000 +r 66F0.10 # RM / RZ +*Want "DIDBR rounding test 8p TR" 3FE00000 00000000 3FF00000 00000000 +r 6700.10 # RM / RP +*Want "DIDBR rounding test 8q NT" BFF80000 00000000 40000000 00000000 +r 6710.10 # RM / RP +*Want "DIDBR rounding test 8q TR" BFF80000 00000000 40000000 00000000 +r 6720.10 # RM / RM +*Want "DIDBR rounding test 8r NT" 3FE00000 00000000 3FF00000 00000000 +r 6730.10 # RM / RM +*Want "DIDBR rounding test 8r TR" 3FE00000 00000000 3FF00000 00000000 +r 6740.10 # RFS / RNTA +*Want "DIDBR rounding test 8s NT" 3FE00000 00000000 3FF00000 00000000 +r 6750.10 # RFS / RNTA +*Want "DIDBR rounding test 8s TR" 3FE00000 00000000 3FF00000 00000000 +r 6760.10 # RFS / RFS +*Want "DIDBR rounding test 8t NT" 3FE00000 00000000 3FF00000 00000000 +r 6770.10 # RFS / RFS +*Want "DIDBR rounding test 8t TR" 3FE00000 00000000 3FF00000 00000000 +r 6780.10 # RFS / RNTE +*Want "DIDBR rounding test 8u NT" 3FE00000 00000000 3FF00000 00000000 +r 6790.10 # RFS / RNTE +*Want "DIDBR rounding test 8u TR" 3FE00000 00000000 3FF00000 00000000 +r 67A0.10 # RFS / RZ +*Want "DIDBR rounding test 8v NT" 3FE00000 00000000 3FF00000 00000000 +r 67B0.10 # RFS / RZ +*Want "DIDBR rounding test 8v TR" 3FE00000 00000000 3FF00000 00000000 +r 67C0.10 # RFS / RP +*Want "DIDBR rounding test 8w NT" BFF80000 00000000 40000000 00000000 +r 67D0.10 # RFS / RP +*Want "DIDBR rounding test 8w TR" BFF80000 00000000 40000000 00000000 +r 67E0.10 # RFS / RM +*Want "DIDBR rounding test 8x NT" 3FE00000 00000000 3FF00000 00000000 +r 67F0.10 # RFS / RM +*Want "DIDBR rounding test 8x TR" 3FE00000 00000000 3FF00000 00000000 +r 6800.10 # RZ / RNTA +*Want "DIDBR rounding test 9a NT" BFE00000 00000000 40080000 00000000 +r 6810.10 # RZ / RNTA +*Want "DIDBR rounding test 9a TR" BFE00000 00000000 40080000 00000000 +r 6820.10 # RZ / RFS +*Want "DIDBR rounding test 9b NT" BFE00000 00000000 40080000 00000000 +r 6830.10 # RZ / RFS +*Want "DIDBR rounding test 9b TR" BFE00000 00000000 40080000 00000000 +r 6840.10 # RZ / RNTE +*Want "DIDBR rounding test 9c NT" BFE00000 00000000 40080000 00000000 +r 6850.10 # RZ / RNTE +*Want "DIDBR rounding test 9c TR" BFE00000 00000000 40080000 00000000 +r 6860.10 # RZ / RZ +*Want "DIDBR rounding test 9d NT" 3FF80000 00000000 40000000 00000000 +r 6870.10 # RZ / RZ +*Want "DIDBR rounding test 9d TR" 3FF80000 00000000 40000000 00000000 +r 6880.10 # RZ / RP +*Want "DIDBR rounding test 9e NT" BFE00000 00000000 40080000 00000000 +r 6890.10 # RZ / RP +*Want "DIDBR rounding test 9e TR" BFE00000 00000000 40080000 00000000 +r 68A0.10 # RZ / RM +*Want "DIDBR rounding test 9f NT" 3FF80000 00000000 40000000 00000000 +r 68B0.10 # RZ / RM +*Want "DIDBR rounding test 9f TR" 3FF80000 00000000 40000000 00000000 +r 68C0.10 # RP / RNTA +*Want "DIDBR rounding test 9g NT" BFE00000 00000000 40080000 00000000 +r 68D0.10 # RP / RNTA +*Want "DIDBR rounding test 9g TR" BFE00000 00000000 40080000 00000000 +r 68E0.10 # RP / RFS +*Want "DIDBR rounding test 9h NT" BFE00000 00000000 40080000 00000000 +r 68F0.10 # RP / RFS +*Want "DIDBR rounding test 9h TR" BFE00000 00000000 40080000 00000000 +r 6900.10 # RP / RNTE +*Want "DIDBR rounding test 9i NT" BFE00000 00000000 40080000 00000000 +r 6910.10 # RP / RNTE +*Want "DIDBR rounding test 9i TR" BFE00000 00000000 40080000 00000000 +r 6920.10 # RP / RZ +*Want "DIDBR rounding test 9j NT" 3FF80000 00000000 40000000 00000000 +r 6930.10 # RP / RZ +*Want "DIDBR rounding test 9j TR" 3FF80000 00000000 40000000 00000000 +r 6940.10 # RP / RP +*Want "DIDBR rounding test 9k NT" BFE00000 00000000 40080000 00000000 +r 6950.10 # RP / RP +*Want "DIDBR rounding test 9k TR" BFE00000 00000000 40080000 00000000 +r 6960.10 # RP / RM +*Want "DIDBR rounding test 9l NT" 3FF80000 00000000 40000000 00000000 +r 6970.10 # RP / RM +*Want "DIDBR rounding test 9l TR" 3FF80000 00000000 40000000 00000000 +r 6980.10 # RM / RNTA +*Want "DIDBR rounding test 9m NT" BFE00000 00000000 40080000 00000000 +r 6990.10 # RM / RNTA +*Want "DIDBR rounding test 9m TR" BFE00000 00000000 40080000 00000000 +r 69A0.10 # RM / RFS +*Want "DIDBR rounding test 9n NT" BFE00000 00000000 40080000 00000000 +r 69B0.10 # RM / RFS +*Want "DIDBR rounding test 9n TR" BFE00000 00000000 40080000 00000000 +r 69C0.10 # RM / RNTE +*Want "DIDBR rounding test 9o NT" BFE00000 00000000 40080000 00000000 +r 69D0.10 # RM / RNTE +*Want "DIDBR rounding test 9o TR" BFE00000 00000000 40080000 00000000 +r 69E0.10 # RM / RZ +*Want "DIDBR rounding test 9p NT" 3FF80000 00000000 40000000 00000000 +r 69F0.10 # RM / RZ +*Want "DIDBR rounding test 9p TR" 3FF80000 00000000 40000000 00000000 +r 6A00.10 # RM / RP +*Want "DIDBR rounding test 9q NT" BFE00000 00000000 40080000 00000000 +r 6A10.10 # RM / RP +*Want "DIDBR rounding test 9q TR" BFE00000 00000000 40080000 00000000 +r 6A20.10 # RM / RM +*Want "DIDBR rounding test 9r NT" 3FF80000 00000000 40000000 00000000 +r 6A30.10 # RM / RM +*Want "DIDBR rounding test 9r TR" 3FF80000 00000000 40000000 00000000 +r 6A40.10 # RFS / RNTA +*Want "DIDBR rounding test 9s NT" BFE00000 00000000 40080000 00000000 +r 6A50.10 # RFS / RNTA +*Want "DIDBR rounding test 9s TR" BFE00000 00000000 40080000 00000000 +r 6A60.10 # RFS / RFS +*Want "DIDBR rounding test 9t NT" BFE00000 00000000 40080000 00000000 +r 6A70.10 # RFS / RFS +*Want "DIDBR rounding test 9t TR" BFE00000 00000000 40080000 00000000 +r 6A80.10 # RFS / RNTE +*Want "DIDBR rounding test 9u NT" BFE00000 00000000 40080000 00000000 +r 6A90.10 # RFS / RNTE +*Want "DIDBR rounding test 9u TR" BFE00000 00000000 40080000 00000000 +r 6AA0.10 # RFS / RZ +*Want "DIDBR rounding test 9v NT" 3FF80000 00000000 40000000 00000000 +r 6AB0.10 # RFS / RZ +*Want "DIDBR rounding test 9v TR" 3FF80000 00000000 40000000 00000000 +r 6AC0.10 # RFS / RP +*Want "DIDBR rounding test 9w NT" BFE00000 00000000 40080000 00000000 +r 6AD0.10 # RFS / RP +*Want "DIDBR rounding test 9w TR" BFE00000 00000000 40080000 00000000 +r 6AE0.10 # RFS / RM +*Want "DIDBR rounding test 9x NT" 3FF80000 00000000 40000000 00000000 +r 6AF0.10 # RFS / RM +*Want "DIDBR rounding test 9x TR" 3FF80000 00000000 40000000 00000000 +r 6B00.10 # RZ / RNTA +*Want "DIDBR rounding test 10a NT" BFE00000 00000000 40140000 00000000 +r 6B10.10 # RZ / RNTA +*Want "DIDBR rounding test 10a TR" BFE00000 00000000 40140000 00000000 +r 6B20.10 # RZ / RFS +*Want "DIDBR rounding test 10b NT" BFE00000 00000000 40140000 00000000 +r 6B30.10 # RZ / RFS +*Want "DIDBR rounding test 10b TR" BFE00000 00000000 40140000 00000000 +r 6B40.10 # RZ / RNTE +*Want "DIDBR rounding test 10c NT" BFE00000 00000000 40140000 00000000 +r 6B50.10 # RZ / RNTE +*Want "DIDBR rounding test 10c TR" BFE00000 00000000 40140000 00000000 +r 6B60.10 # RZ / RZ +*Want "DIDBR rounding test 10d NT" 3FF80000 00000000 40100000 00000000 +r 6B70.10 # RZ / RZ +*Want "DIDBR rounding test 10d TR" 3FF80000 00000000 40100000 00000000 +r 6B80.10 # RZ / RP +*Want "DIDBR rounding test 10e NT" BFE00000 00000000 40140000 00000000 +r 6B90.10 # RZ / RP +*Want "DIDBR rounding test 10e TR" BFE00000 00000000 40140000 00000000 +r 6BA0.10 # RZ / RM +*Want "DIDBR rounding test 10f NT" 3FF80000 00000000 40100000 00000000 +r 6BB0.10 # RZ / RM +*Want "DIDBR rounding test 10f TR" 3FF80000 00000000 40100000 00000000 +r 6BC0.10 # RP / RNTA +*Want "DIDBR rounding test 10g NT" BFE00000 00000000 40140000 00000000 +r 6BD0.10 # RP / RNTA +*Want "DIDBR rounding test 10g TR" BFE00000 00000000 40140000 00000000 +r 6BE0.10 # RP / RFS +*Want "DIDBR rounding test 10h NT" BFE00000 00000000 40140000 00000000 +r 6BF0.10 # RP / RFS +*Want "DIDBR rounding test 10h TR" BFE00000 00000000 40140000 00000000 +r 6C00.10 # RP / RNTE +*Want "DIDBR rounding test 10i NT" BFE00000 00000000 40140000 00000000 +r 6C10.10 # RP / RNTE +*Want "DIDBR rounding test 10i TR" BFE00000 00000000 40140000 00000000 +r 6C20.10 # RP / RZ +*Want "DIDBR rounding test 10j NT" 3FF80000 00000000 40100000 00000000 +r 6C30.10 # RP / RZ +*Want "DIDBR rounding test 10j TR" 3FF80000 00000000 40100000 00000000 +r 6C40.10 # RP / RP +*Want "DIDBR rounding test 10k NT" BFE00000 00000000 40140000 00000000 +r 6C50.10 # RP / RP +*Want "DIDBR rounding test 10k TR" BFE00000 00000000 40140000 00000000 +r 6C60.10 # RP / RM +*Want "DIDBR rounding test 10l NT" 3FF80000 00000000 40100000 00000000 +r 6C70.10 # RP / RM +*Want "DIDBR rounding test 10l TR" 3FF80000 00000000 40100000 00000000 +r 6C80.10 # RM / RNTA +*Want "DIDBR rounding test 10m NT" BFE00000 00000000 40140000 00000000 +r 6C90.10 # RM / RNTA +*Want "DIDBR rounding test 10m TR" BFE00000 00000000 40140000 00000000 +r 6CA0.10 # RM / RFS +*Want "DIDBR rounding test 10n NT" BFE00000 00000000 40140000 00000000 +r 6CB0.10 # RM / RFS +*Want "DIDBR rounding test 10n TR" BFE00000 00000000 40140000 00000000 +r 6CC0.10 # RM / RNTE +*Want "DIDBR rounding test 10o NT" BFE00000 00000000 40140000 00000000 +r 6CD0.10 # RM / RNTE +*Want "DIDBR rounding test 10o TR" BFE00000 00000000 40140000 00000000 +r 6CE0.10 # RM / RZ +*Want "DIDBR rounding test 10p NT" 3FF80000 00000000 40100000 00000000 +r 6CF0.10 # RM / RZ +*Want "DIDBR rounding test 10p TR" 3FF80000 00000000 40100000 00000000 +r 6D00.10 # RM / RP +*Want "DIDBR rounding test 10q NT" BFE00000 00000000 40140000 00000000 +r 6D10.10 # RM / RP +*Want "DIDBR rounding test 10q TR" BFE00000 00000000 40140000 00000000 +r 6D20.10 # RM / RM +*Want "DIDBR rounding test 10r NT" 3FF80000 00000000 40100000 00000000 +r 6D30.10 # RM / RM +*Want "DIDBR rounding test 10r TR" 3FF80000 00000000 40100000 00000000 +r 6D40.10 # RFS / RNTA +*Want "DIDBR rounding test 10s NT" BFE00000 00000000 40140000 00000000 +r 6D50.10 # RFS / RNTA +*Want "DIDBR rounding test 10s TR" BFE00000 00000000 40140000 00000000 +r 6D60.10 # RFS / RFS +*Want "DIDBR rounding test 10t NT" BFE00000 00000000 40140000 00000000 +r 6D70.10 # RFS / RFS +*Want "DIDBR rounding test 10t TR" BFE00000 00000000 40140000 00000000 +r 6D80.10 # RFS / RNTE +*Want "DIDBR rounding test 10u NT" BFE00000 00000000 40140000 00000000 +r 6D90.10 # RFS / RNTE +*Want "DIDBR rounding test 10u TR" BFE00000 00000000 40140000 00000000 +r 6DA0.10 # RFS / RZ +*Want "DIDBR rounding test 10v NT" 3FF80000 00000000 40100000 00000000 +r 6DB0.10 # RFS / RZ +*Want "DIDBR rounding test 10v TR" 3FF80000 00000000 40100000 00000000 +r 6DC0.10 # RFS / RP +*Want "DIDBR rounding test 10w NT" BFE00000 00000000 40140000 00000000 +r 6DD0.10 # RFS / RP +*Want "DIDBR rounding test 10w TR" BFE00000 00000000 40140000 00000000 +r 6DE0.10 # RFS / RM +*Want "DIDBR rounding test 10x NT" 3FF80000 00000000 40100000 00000000 +r 6DF0.10 # RFS / RM +*Want "DIDBR rounding test 10x TR" 3FF80000 00000000 40100000 00000000 +r 6E00.10 # RZ / RNTA +*Want "DIDBR rounding test 11a NT" 00000000 00000000 3FF00000 00000000 +r 6E10.10 # RZ / RNTA +*Want "DIDBR rounding test 11a TR" 00000000 00000000 3FF00000 00000000 +r 6E20.10 # RZ / RFS +*Want "DIDBR rounding test 11b NT" 00000000 00000000 3FF00000 00000000 +r 6E30.10 # RZ / RFS +*Want "DIDBR rounding test 11b TR" 00000000 00000000 3FF00000 00000000 +r 6E40.10 # RZ / RNTE +*Want "DIDBR rounding test 11c NT" 00000000 00000000 3FF00000 00000000 +r 6E50.10 # RZ / RNTE +*Want "DIDBR rounding test 11c TR" 00000000 00000000 3FF00000 00000000 +r 6E60.10 # RZ / RZ +*Want "DIDBR rounding test 11d NT" 00000000 00000000 3FF00000 00000000 +r 6E70.10 # RZ / RZ +*Want "DIDBR rounding test 11d TR" 00000000 00000000 3FF00000 00000000 +r 6E80.10 # RZ / RP +*Want "DIDBR rounding test 11e NT" 00000000 00000000 3FF00000 00000000 +r 6E90.10 # RZ / RP +*Want "DIDBR rounding test 11e TR" 00000000 00000000 3FF00000 00000000 +r 6EA0.10 # RZ / RM +*Want "DIDBR rounding test 11f NT" 00000000 00000000 3FF00000 00000000 +r 6EB0.10 # RZ / RM +*Want "DIDBR rounding test 11f TR" 00000000 00000000 3FF00000 00000000 +r 6EC0.10 # RP / RNTA +*Want "DIDBR rounding test 11g NT" 00000000 00000000 3FF00000 00000000 +r 6ED0.10 # RP / RNTA +*Want "DIDBR rounding test 11g TR" 00000000 00000000 3FF00000 00000000 +r 6EE0.10 # RP / RFS +*Want "DIDBR rounding test 11h NT" 00000000 00000000 3FF00000 00000000 +r 6EF0.10 # RP / RFS +*Want "DIDBR rounding test 11h TR" 00000000 00000000 3FF00000 00000000 +r 6F00.10 # RP / RNTE +*Want "DIDBR rounding test 11i NT" 00000000 00000000 3FF00000 00000000 +r 6F10.10 # RP / RNTE +*Want "DIDBR rounding test 11i TR" 00000000 00000000 3FF00000 00000000 +r 6F20.10 # RP / RZ +*Want "DIDBR rounding test 11j NT" 00000000 00000000 3FF00000 00000000 +r 6F30.10 # RP / RZ +*Want "DIDBR rounding test 11j TR" 00000000 00000000 3FF00000 00000000 +r 6F40.10 # RP / RP +*Want "DIDBR rounding test 11k NT" 00000000 00000000 3FF00000 00000000 +r 6F50.10 # RP / RP +*Want "DIDBR rounding test 11k TR" 00000000 00000000 3FF00000 00000000 +r 6F60.10 # RP / RM +*Want "DIDBR rounding test 11l NT" 00000000 00000000 3FF00000 00000000 +r 6F70.10 # RP / RM +*Want "DIDBR rounding test 11l TR" 00000000 00000000 3FF00000 00000000 +r 6F80.10 # RM / RNTA +*Want "DIDBR rounding test 11m NT" 00000000 00000000 3FF00000 00000000 +r 6F90.10 # RM / RNTA +*Want "DIDBR rounding test 11m TR" 00000000 00000000 3FF00000 00000000 +r 6FA0.10 # RM / RFS +*Want "DIDBR rounding test 11n NT" 00000000 00000000 3FF00000 00000000 +r 6FB0.10 # RM / RFS +*Want "DIDBR rounding test 11n TR" 00000000 00000000 3FF00000 00000000 +r 6FC0.10 # RM / RNTE +*Want "DIDBR rounding test 11o NT" 00000000 00000000 3FF00000 00000000 +r 6FD0.10 # RM / RNTE +*Want "DIDBR rounding test 11o TR" 00000000 00000000 3FF00000 00000000 +r 6FE0.10 # RM / RZ +*Want "DIDBR rounding test 11p NT" 00000000 00000000 3FF00000 00000000 +r 6FF0.10 # RM / RZ +*Want "DIDBR rounding test 11p TR" 00000000 00000000 3FF00000 00000000 +r 7000.10 # RM / RP +*Want "DIDBR rounding test 11q NT" 00000000 00000000 3FF00000 00000000 +r 7010.10 # RM / RP +*Want "DIDBR rounding test 11q TR" 00000000 00000000 3FF00000 00000000 +r 7020.10 # RM / RM +*Want "DIDBR rounding test 11r NT" 00000000 00000000 3FF00000 00000000 +r 7030.10 # RM / RM +*Want "DIDBR rounding test 11r TR" 00000000 00000000 3FF00000 00000000 +r 7040.10 # RFS / RNTA +*Want "DIDBR rounding test 11s NT" 00000000 00000000 3FF00000 00000000 +r 7050.10 # RFS / RNTA +*Want "DIDBR rounding test 11s TR" 00000000 00000000 3FF00000 00000000 +r 7060.10 # RFS / RFS +*Want "DIDBR rounding test 11t NT" 00000000 00000000 3FF00000 00000000 +r 7070.10 # RFS / RFS +*Want "DIDBR rounding test 11t TR" 00000000 00000000 3FF00000 00000000 +r 7080.10 # RFS / RNTE +*Want "DIDBR rounding test 11u NT" 00000000 00000000 3FF00000 00000000 +r 7090.10 # RFS / RNTE +*Want "DIDBR rounding test 11u TR" 00000000 00000000 3FF00000 00000000 +r 70A0.10 # RFS / RZ +*Want "DIDBR rounding test 11v NT" 00000000 00000000 3FF00000 00000000 +r 70B0.10 # RFS / RZ +*Want "DIDBR rounding test 11v TR" 00000000 00000000 3FF00000 00000000 +r 70C0.10 # RFS / RP +*Want "DIDBR rounding test 11w NT" 00000000 00000000 3FF00000 00000000 +r 70D0.10 # RFS / RP +*Want "DIDBR rounding test 11w TR" 00000000 00000000 3FF00000 00000000 +r 70E0.10 # RFS / RM +*Want "DIDBR rounding test 11x NT" 00000000 00000000 3FF00000 00000000 +r 70F0.10 # RFS / RM +*Want "DIDBR rounding test 11x TR" 00000000 00000000 3FF00000 00000000 +r 7100.10 # RZ / RNTA +*Want "DIDBR rounding test 12a NT" C0000000 00000000 3FF00000 00000000 +r 7110.10 # RZ / RNTA +*Want "DIDBR rounding test 12a TR" C0000000 00000000 3FF00000 00000000 +r 7120.10 # RZ / RFS +*Want "DIDBR rounding test 12b NT" C0000000 00000000 3FF00000 00000000 +r 7130.10 # RZ / RFS +*Want "DIDBR rounding test 12b TR" C0000000 00000000 3FF00000 00000000 +r 7140.10 # RZ / RNTE +*Want "DIDBR rounding test 12c NT" C0000000 00000000 3FF00000 00000000 +r 7150.10 # RZ / RNTE +*Want "DIDBR rounding test 12c TR" C0000000 00000000 3FF00000 00000000 +r 7160.10 # RZ / RZ +*Want "DIDBR rounding test 12d NT" 40080000 00000000 00000000 00000000 +r 7170.10 # RZ / RZ +*Want "DIDBR rounding test 12d TR" 40080000 00000000 00000000 00000000 +r 7180.10 # RZ / RP +*Want "DIDBR rounding test 12e NT" C0000000 00000000 3FF00000 00000000 +r 7190.10 # RZ / RP +*Want "DIDBR rounding test 12e TR" C0000000 00000000 3FF00000 00000000 +r 71A0.10 # RZ / RM +*Want "DIDBR rounding test 12f NT" 40080000 00000000 00000000 00000000 +r 71B0.10 # RZ / RM +*Want "DIDBR rounding test 12f TR" 40080000 00000000 00000000 00000000 +r 71C0.10 # RP / RNTA +*Want "DIDBR rounding test 12g NT" C0000000 00000000 3FF00000 00000000 +r 71D0.10 # RP / RNTA +*Want "DIDBR rounding test 12g TR" C0000000 00000000 3FF00000 00000000 +r 71E0.10 # RP / RFS +*Want "DIDBR rounding test 12h NT" C0000000 00000000 3FF00000 00000000 +r 71F0.10 # RP / RFS +*Want "DIDBR rounding test 12h TR" C0000000 00000000 3FF00000 00000000 +r 7200.10 # RP / RNTE +*Want "DIDBR rounding test 12i NT" C0000000 00000000 3FF00000 00000000 +r 7210.10 # RP / RNTE +*Want "DIDBR rounding test 12i TR" C0000000 00000000 3FF00000 00000000 +r 7220.10 # RP / RZ +*Want "DIDBR rounding test 12j NT" 40080000 00000000 00000000 00000000 +r 7230.10 # RP / RZ +*Want "DIDBR rounding test 12j TR" 40080000 00000000 00000000 00000000 +r 7240.10 # RP / RP +*Want "DIDBR rounding test 12k NT" C0000000 00000000 3FF00000 00000000 +r 7250.10 # RP / RP +*Want "DIDBR rounding test 12k TR" C0000000 00000000 3FF00000 00000000 +r 7260.10 # RP / RM +*Want "DIDBR rounding test 12l NT" 40080000 00000000 00000000 00000000 +r 7270.10 # RP / RM +*Want "DIDBR rounding test 12l TR" 40080000 00000000 00000000 00000000 +r 7280.10 # RM / RNTA +*Want "DIDBR rounding test 12m NT" C0000000 00000000 3FF00000 00000000 +r 7290.10 # RM / RNTA +*Want "DIDBR rounding test 12m TR" C0000000 00000000 3FF00000 00000000 +r 72A0.10 # RM / RFS +*Want "DIDBR rounding test 12n NT" C0000000 00000000 3FF00000 00000000 +r 72B0.10 # RM / RFS +*Want "DIDBR rounding test 12n TR" C0000000 00000000 3FF00000 00000000 +r 72C0.10 # RM / RNTE +*Want "DIDBR rounding test 12o NT" C0000000 00000000 3FF00000 00000000 +r 72D0.10 # RM / RNTE +*Want "DIDBR rounding test 12o TR" C0000000 00000000 3FF00000 00000000 +r 72E0.10 # RM / RZ +*Want "DIDBR rounding test 12p NT" 40080000 00000000 00000000 00000000 +r 72F0.10 # RM / RZ +*Want "DIDBR rounding test 12p TR" 40080000 00000000 00000000 00000000 +r 7300.10 # RM / RP +*Want "DIDBR rounding test 12q NT" C0000000 00000000 3FF00000 00000000 +r 7310.10 # RM / RP +*Want "DIDBR rounding test 12q TR" C0000000 00000000 3FF00000 00000000 +r 7320.10 # RM / RM +*Want "DIDBR rounding test 12r NT" 40080000 00000000 00000000 00000000 +r 7330.10 # RM / RM +*Want "DIDBR rounding test 12r TR" 40080000 00000000 00000000 00000000 +r 7340.10 # RFS / RNTA +*Want "DIDBR rounding test 12s NT" C0000000 00000000 3FF00000 00000000 +r 7350.10 # RFS / RNTA +*Want "DIDBR rounding test 12s TR" C0000000 00000000 3FF00000 00000000 +r 7360.10 # RFS / RFS +*Want "DIDBR rounding test 12t NT" C0000000 00000000 3FF00000 00000000 +r 7370.10 # RFS / RFS +*Want "DIDBR rounding test 12t TR" C0000000 00000000 3FF00000 00000000 +r 7380.10 # RFS / RNTE +*Want "DIDBR rounding test 12u NT" C0000000 00000000 3FF00000 00000000 +r 7390.10 # RFS / RNTE +*Want "DIDBR rounding test 12u TR" C0000000 00000000 3FF00000 00000000 +r 73A0.10 # RFS / RZ +*Want "DIDBR rounding test 12v NT" 40080000 00000000 00000000 00000000 +r 73B0.10 # RFS / RZ +*Want "DIDBR rounding test 12v TR" 40080000 00000000 00000000 00000000 +r 73C0.10 # RFS / RP +*Want "DIDBR rounding test 12w NT" C0000000 00000000 3FF00000 00000000 +r 73D0.10 # RFS / RP +*Want "DIDBR rounding test 12w TR" C0000000 00000000 3FF00000 00000000 +r 73E0.10 # RFS / RM +*Want "DIDBR rounding test 12x NT" 40080000 00000000 00000000 00000000 +r 73F0.10 # RFS / RM +*Want "DIDBR rounding test 12x TR" 40080000 00000000 00000000 00000000 + + + + + + + +*Compare +# Long BFP exhaustive rounding mode tests +r 9000.10 # RZ / RNTA RZ / RFS +*Want "DIDBR Rounding FPCR 1ab" 00000000 F8000000 00000000 F8000000 +r 9010.10 # RZ / RNTE RZ / RZ +*Want "DIDBR Rounding FPCR 1cd" 00000000 F8000000 00000000 F8000000 +r 9020.10 # RZ / RP RZ / RM +*Want "DIDBR Rounding FPCR 1ef" 00000000 F8000000 00000000 F8000000 +r 9030.10 # RP / RNTA RP / RFS +*Want "DIDBR Rounding FPCR 1gh" 00000000 F8000000 00000000 F8000000 +r 9040.10 # RP / RNTE RP / RZ +*Want "DIDBR Rounding FPCR 1ij" 00000000 F8000000 00000000 F8000000 +r 9050.10 # RP / RP RP / RM +*Want "DIDBR Rounding FPCR 1kl" 00000000 F8000000 00000000 F8000000 +r 9060.10 # RM / RNTA RM / RFS +*Want "DIDBR Rounding FPCR 1mn" 00000000 F8000000 00000000 F8000000 +r 9070.10 # RM / RNTE RM / RZ +*Want "DIDBR Rounding FPCR 1op" 00000000 F8000000 00000000 F8000000 +r 9080.10 # RM / RP RM / RM +*Want "DIDBR Rounding FPCR 1qr" 00000000 F8000000 00000000 F8000000 +r 9090.10 # RFS / RNTA RFS / RFS +*Want "DIDBR Rounding FPCR 1st" 00000000 F8000000 00000000 F8000000 +r 90A0.10 # RFS / RNTE RFS / RZ +*Want "DIDBR Rounding FPCR 1uv" 00000000 F8000000 00000000 F8000000 +r 90B0.10 # RFS / RP RFS / RM +*Want "DIDBR Rounding FPCR 1wx" 00000000 F8000000 00000000 F8000000 +r 90C0.10 # RZ / RNTA RZ / RFS +*Want "DIDBR Rounding FPCR 2ab" 00000000 F8000000 00000000 F8000000 +r 90D0.10 # RZ / RNTE RZ / RZ +*Want "DIDBR Rounding FPCR 2cd" 00000000 F8000000 00000000 F8000000 +r 90E0.10 # RZ / RP RZ / RM +*Want "DIDBR Rounding FPCR 2ef" 00000000 F8000000 00000000 F8000000 +r 90F0.10 # RP / RNTA RP / RFS +*Want "DIDBR Rounding FPCR 2gh" 00000000 F8000000 00000000 F8000000 +r 9100.10 # RP / RNTE RP / RZ +*Want "DIDBR Rounding FPCR 2ij" 00000000 F8000000 00000000 F8000000 +r 9110.10 # RP / RP RP / RM +*Want "DIDBR Rounding FPCR 2kl" 00000000 F8000000 00000000 F8000000 +r 9120.10 # RM / RNTA RM / RFS +*Want "DIDBR Rounding FPCR 2mn" 00000000 F8000000 00000000 F8000000 +r 9130.10 # RM / RNTE RM / RZ +*Want "DIDBR Rounding FPCR 2op" 00000000 F8000000 00000000 F8000000 +r 9140.10 # RM / RP RM / RM +*Want "DIDBR Rounding FPCR 2qr" 00000000 F8000000 00000000 F8000000 +r 9150.10 # RFS / RNTA RFS / RFS +*Want "DIDBR Rounding FPCR 2st" 00000000 F8000000 00000000 F8000000 +r 9160.10 # RFS / RNTE RFS / RZ +*Want "DIDBR Rounding FPCR 2uv" 00000000 F8000000 00000000 F8000000 +r 9170.10 # RFS / RP RFS / RM +*Want "DIDBR Rounding FPCR 2wx" 00000000 F8000000 00000000 F8000000 +r 9180.10 # RZ / RNTA RZ / RFS +*Want "DIDBR Rounding FPCR 3ab" 00000000 F8000000 00000000 F8000000 +r 9190.10 # RZ / RNTE RZ / RZ +*Want "DIDBR Rounding FPCR 3cd" 00000000 F8000000 00000000 F8000000 +r 91A0.10 # RZ / RP RZ / RM +*Want "DIDBR Rounding FPCR 3ef" 00000000 F8000000 00000000 F8000000 +r 91B0.10 # RP / RNTA RP / RFS +*Want "DIDBR Rounding FPCR 3gh" 00000000 F8000000 00000000 F8000000 +r 91C0.10 # RP / RNTE RP / RZ +*Want "DIDBR Rounding FPCR 3ij" 00000000 F8000000 00000000 F8000000 +r 91D0.10 # RP / RP RP / RM +*Want "DIDBR Rounding FPCR 3kl" 00000000 F8000000 00000000 F8000000 +r 91E0.10 # RM / RNTA RM / RFS +*Want "DIDBR Rounding FPCR 3mn" 00000000 F8000000 00000000 F8000000 +r 91F0.10 # RM / RNTE RM / RZ +*Want "DIDBR Rounding FPCR 3op" 00000000 F8000000 00000000 F8000000 +r 9200.10 # RM / RP RM / RM +*Want "DIDBR Rounding FPCR 3qr" 00000000 F8000000 00000000 F8000000 +r 9210.10 # RFS / RNTA RFS / RFS +*Want "DIDBR Rounding FPCR 3st" 00000000 F8000000 00000000 F8000000 +r 9220.10 # RFS / RNTE RFS / RZ +*Want "DIDBR Rounding FPCR 3uv" 00000000 F8000000 00000000 F8000000 +r 9230.10 # RFS / RP RFS / RM +*Want "DIDBR Rounding FPCR 3wx" 00000000 F8000000 00000000 F8000000 +r 9240.10 # RZ / RNTA RZ / RFS +*Want "DIDBR Rounding FPCR 4ab" 00000000 F8000000 00000000 F8000000 +r 9250.10 # RZ / RNTE RZ / RZ +*Want "DIDBR Rounding FPCR 4cd" 00000000 F8000000 00000000 F8000000 +r 9260.10 # RZ / RP RZ / RM +*Want "DIDBR Rounding FPCR 4ef" 00000000 F8000000 00000000 F8000000 +r 9270.10 # RP / RNTA RP / RFS +*Want "DIDBR Rounding FPCR 4gh" 00000000 F8000000 00000000 F8000000 +r 9280.10 # RP / RNTE RP / RZ +*Want "DIDBR Rounding FPCR 4ij" 00000000 F8000000 00000000 F8000000 +r 9290.10 # RP / RP RP / RM +*Want "DIDBR Rounding FPCR 4kl" 00000000 F8000000 00000000 F8000000 +r 92A0.10 # RM / RNTA RM / RFS +*Want "DIDBR Rounding FPCR 4mn" 00000000 F8000000 00000000 F8000000 +r 92B0.10 # RM / RNTE RM / RZ +*Want "DIDBR Rounding FPCR 4op" 00000000 F8000000 00000000 F8000000 +r 92C0.10 # RM / RP RM / RM +*Want "DIDBR Rounding FPCR 4qr" 00000000 F8000000 00000000 F8000000 +r 92D0.10 # RFS / RNTA RFS / RFS +*Want "DIDBR Rounding FPCR 4st" 00000000 F8000000 00000000 F8000000 +r 92E0.10 # RFS / RNTE RFS / RZ +*Want "DIDBR Rounding FPCR 4uv" 00000000 F8000000 00000000 F8000000 +r 92F0.10 # RFS / RP RFS / RM +*Want "DIDBR Rounding FPCR 4wx" 00000000 F8000000 00000000 F8000000 +r 9300.10 # RZ / RNTA RZ / RFS +*Want "DIDBR Rounding FPCR 5ab" 00000000 F8000000 00000000 F8000000 +r 9310.10 # RZ / RNTE RZ / RZ +*Want "DIDBR Rounding FPCR 5cd" 00000000 F8000000 00000000 F8000000 +r 9320.10 # RZ / RP RZ / RM +*Want "DIDBR Rounding FPCR 5ef" 00000000 F8000000 00000000 F8000000 +r 9330.10 # RP / RNTA RP / RFS +*Want "DIDBR Rounding FPCR 5gh" 00000000 F8000000 00000000 F8000000 +r 9340.10 # RP / RNTE RP / RZ +*Want "DIDBR Rounding FPCR 5ij" 00000000 F8000000 00000000 F8000000 +r 9350.10 # RP / RP RP / RM +*Want "DIDBR Rounding FPCR 5kl" 00000000 F8000000 00000000 F8000000 +r 9360.10 # RM / RNTA RM / RFS +*Want "DIDBR Rounding FPCR 5mn" 00000000 F8000000 00000000 F8000000 +r 9370.10 # RM / RNTE RM / RZ +*Want "DIDBR Rounding FPCR 5op" 00000000 F8000000 00000000 F8000000 +r 9380.10 # RM / RP RM / RM +*Want "DIDBR Rounding FPCR 5qr" 00000000 F8000000 00000000 F8000000 +r 9390.10 # RFS / RNTA RFS / RFS +*Want "DIDBR Rounding FPCR 5st" 00000000 F8000000 00000000 F8000000 +r 93A0.10 # RFS / RNTE RFS / RZ +*Want "DIDBR Rounding FPCR 5uv" 00000000 F8000000 00000000 F8000000 +r 93B0.10 # RFS / RP RFS / RM +*Want "DIDBR Rounding FPCR 5wx" 00000000 F8000000 00000000 F8000000 +r 93C0.10 # RZ / RNTA RZ / RFS +*Want "DIDBR Rounding FPCR 6ab" 00000000 F8000000 00000000 F8000000 +r 93D0.10 # RZ / RNTE RZ / RZ +*Want "DIDBR Rounding FPCR 6cd" 00000000 F8000000 00000000 F8000000 +r 93E0.10 # RZ / RP RZ / RM +*Want "DIDBR Rounding FPCR 6ef" 00000000 F8000000 00000000 F8000000 +r 93F0.10 # RP / RNTA RP / RFS +*Want "DIDBR Rounding FPCR 6gh" 00000000 F8000000 00000000 F8000000 +r 9400.10 # RP / RNTE RP / RZ +*Want "DIDBR Rounding FPCR 6ij" 00000000 F8000000 00000000 F8000000 +r 9410.10 # RP / RP RP / RM +*Want "DIDBR Rounding FPCR 6kl" 00000000 F8000000 00000000 F8000000 +r 9420.10 # RM / RNTA RM / RFS +*Want "DIDBR Rounding FPCR 6mn" 00000000 F8000000 00000000 F8000000 +r 9430.10 # RM / RNTE RM / RZ +*Want "DIDBR Rounding FPCR 6op" 00000000 F8000000 00000000 F8000000 +r 9440.10 # RM / RP RM / RM +*Want "DIDBR Rounding FPCR 6qr" 00000000 F8000000 00000000 F8000000 +r 9450.10 # RFS / RNTA RFS / RFS +*Want "DIDBR Rounding FPCR 6st" 00000000 F8000000 00000000 F8000000 +r 9460.10 # RFS / RNTE RFS / RZ +*Want "DIDBR Rounding FPCR 6uv" 00000000 F8000000 00000000 F8000000 +r 9470.10 # RFS / RP RFS / RM +*Want "DIDBR Rounding FPCR 6wx" 00000000 F8000000 00000000 F8000000 +r 9480.10 # RZ / RNTA RZ / RFS +*Want "DIDBR Rounding FPCR 7ab" 00000000 F8000000 00000000 F8000000 +r 9490.10 # RZ / RNTE RZ / RZ +*Want "DIDBR Rounding FPCR 7cd" 00000000 F8000000 00000000 F8000000 +r 94A0.10 # RZ / RP RZ / RM +*Want "DIDBR Rounding FPCR 7ef" 00000000 F8000000 00000000 F8000000 +r 94B0.10 # RP / RNTA RP / RFS +*Want "DIDBR Rounding FPCR 7gh" 00000000 F8000000 00000000 F8000000 +r 94C0.10 # RP / RNTE RP / RZ +*Want "DIDBR Rounding FPCR 7ij" 00000000 F8000000 00000000 F8000000 +r 94D0.10 # RP / RP RP / RM +*Want "DIDBR Rounding FPCR 7kl" 00000000 F8000000 00000000 F8000000 +r 94E0.10 # RM / RNTA RM / RFS +*Want "DIDBR Rounding FPCR 7mn" 00000000 F8000000 00000000 F8000000 +r 94F0.10 # RM / RNTE RM / RZ +*Want "DIDBR Rounding FPCR 7op" 00000000 F8000000 00000000 F8000000 +r 9500.10 # RM / RP RM / RM +*Want "DIDBR Rounding FPCR 7qr" 00000000 F8000000 00000000 F8000000 +r 9510.10 # RFS / RNTA RFS / RFS +*Want "DIDBR Rounding FPCR 7st" 00000000 F8000000 00000000 F8000000 +r 9520.10 # RFS / RNTE RFS / RZ +*Want "DIDBR Rounding FPCR 7uv" 00000000 F8000000 00000000 F8000000 +r 9530.10 # RFS / RP RFS / RM +*Want "DIDBR Rounding FPCR 7wx" 00000000 F8000000 00000000 F8000000 +r 9540.10 # RZ / RNTA RZ / RFS +*Want "DIDBR Rounding FPCR 8ab" 00000000 F8000000 00000000 F8000000 +r 9550.10 # RZ / RNTE RZ / RZ +*Want "DIDBR Rounding FPCR 8cd" 00000000 F8000000 00000000 F8000000 +r 9560.10 # RZ / RP RZ / RM +*Want "DIDBR Rounding FPCR 8ef" 00000000 F8000000 00000000 F8000000 +r 9570.10 # RP / RNTA RP / RFS +*Want "DIDBR Rounding FPCR 8gh" 00000000 F8000000 00000000 F8000000 +r 9580.10 # RP / RNTE RP / RZ +*Want "DIDBR Rounding FPCR 8ij" 00000000 F8000000 00000000 F8000000 +r 9590.10 # RP / RP RP / RM +*Want "DIDBR Rounding FPCR 8kl" 00000000 F8000000 00000000 F8000000 +r 95A0.10 # RM / RNTA RM / RFS +*Want "DIDBR Rounding FPCR 8mn" 00000000 F8000000 00000000 F8000000 +r 95B0.10 # RM / RNTE RM / RZ +*Want "DIDBR Rounding FPCR 8op" 00000000 F8000000 00000000 F8000000 +r 95C0.10 # RM / RP RM / RM +*Want "DIDBR Rounding FPCR 8qr" 00000000 F8000000 00000000 F8000000 +r 95D0.10 # RFS / RNTA RFS / RFS +*Want "DIDBR Rounding FPCR 8st" 00000000 F8000000 00000000 F8000000 +r 95E0.10 # RFS / RNTE RFS / RZ +*Want "DIDBR Rounding FPCR 8uv" 00000000 F8000000 00000000 F8000000 +r 95F0.10 # RFS / RP RFS / RM +*Want "DIDBR Rounding FPCR 8wx" 00000000 F8000000 00000000 F8000000 +r 9600.10 # RZ / RNTA RZ / RFS +*Want "DIDBR Rounding FPCR 9ab" 00000000 F8000000 00000000 F8000000 +r 9610.10 # RZ / RNTE RZ / RZ +*Want "DIDBR Rounding FPCR 9cd" 00000000 F8000000 00000000 F8000000 +r 9620.10 # RZ / RP RZ / RM +*Want "DIDBR Rounding FPCR 9ef" 00000000 F8000000 00000000 F8000000 +r 9630.10 # RP / RNTA RP / RFS +*Want "DIDBR Rounding FPCR 9gh" 00000000 F8000000 00000000 F8000000 +r 9640.10 # RP / RNTE RP / RZ +*Want "DIDBR Rounding FPCR 9ij" 00000000 F8000000 00000000 F8000000 +r 9650.10 # RP / RP RP / RM +*Want "DIDBR Rounding FPCR 9kl" 00000000 F8000000 00000000 F8000000 +r 9660.10 # RM / RNTA RM / RFS +*Want "DIDBR Rounding FPCR 9mn" 00000000 F8000000 00000000 F8000000 +r 9670.10 # RM / RNTE RM / RZ +*Want "DIDBR Rounding FPCR 9op" 00000000 F8000000 00000000 F8000000 +r 9680.10 # RM / RP RM / RM +*Want "DIDBR Rounding FPCR 9qr" 00000000 F8000000 00000000 F8000000 +r 9690.10 # RFS / RNTA RFS / RFS +*Want "DIDBR Rounding FPCR 9st" 00000000 F8000000 00000000 F8000000 +r 96A0.10 # RFS / RNTE RFS / RZ +*Want "DIDBR Rounding FPCR 9uv" 00000000 F8000000 00000000 F8000000 +r 96B0.10 # RFS / RP RFS / RM +*Want "DIDBR Rounding FPCR 9wx" 00000000 F8000000 00000000 F8000000 +r 96C0.10 # RZ / RNTA RZ / RFS +*Want "DIDBR Rounding FPCR 10ab" 00000000 F8000000 00000000 F8000000 +r 96D0.10 # RZ / RNTE RZ / RZ +*Want "DIDBR Rounding FPCR 10cd" 00000000 F8000000 00000000 F8000000 +r 96E0.10 # RZ / RP RZ / RM +*Want "DIDBR Rounding FPCR 10ef" 00000000 F8000000 00000000 F8000000 +r 96F0.10 # RP / RNTA RP / RFS +*Want "DIDBR Rounding FPCR 10gh" 00000000 F8000000 00000000 F8000000 +r 9700.10 # RP / RNTE RP / RZ +*Want "DIDBR Rounding FPCR 10ij" 00000000 F8000000 00000000 F8000000 +r 9710.10 # RP / RP RP / RM +*Want "DIDBR Rounding FPCR 10kl" 00000000 F8000000 00000000 F8000000 +r 9720.10 # RM / RNTA RM / RFS +*Want "DIDBR Rounding FPCR 10mn" 00000000 F8000000 00000000 F8000000 +r 9730.10 # RM / RNTE RM / RZ +*Want "DIDBR Rounding FPCR 10op" 00000000 F8000000 00000000 F8000000 +r 9740.10 # RM / RP RM / RM +*Want "DIDBR Rounding FPCR 10qr" 00000000 F8000000 00000000 F8000000 +r 9750.10 # RFS / RNTA RFS / RFS +*Want "DIDBR Rounding FPCR 10st" 00000000 F8000000 00000000 F8000000 +r 9760.10 # RFS / RNTE RFS / RZ +*Want "DIDBR Rounding FPCR 10uv" 00000000 F8000000 00000000 F8000000 +r 9770.10 # RFS / RP RFS / RM +*Want "DIDBR Rounding FPCR 10wx" 00000000 F8000000 00000000 F8000000 +r 9780.10 # RZ / RNTA RZ / RFS +*Want "DIDBR Rounding FPCR 11ab" 00000000 F8000000 00000000 F8000000 +r 9790.10 # RZ / RNTE RZ / RZ +*Want "DIDBR Rounding FPCR 11cd" 00000000 F8000000 00000000 F8000000 +r 97A0.10 # RZ / RP RZ / RM +*Want "DIDBR Rounding FPCR 11ef" 00000000 F8000000 00000000 F8000000 +r 97B0.10 # RP / RNTA RP / RFS +*Want "DIDBR Rounding FPCR 11gh" 00000000 F8000000 00000000 F8000000 +r 97C0.10 # RP / RNTE RP / RZ +*Want "DIDBR Rounding FPCR 11ij" 00000000 F8000000 00000000 F8000000 +r 97D0.10 # RP / RP RP / RM +*Want "DIDBR Rounding FPCR 11kl" 00000000 F8000000 00000000 F8000000 +r 97E0.10 # RM / RNTA RM / RFS +*Want "DIDBR Rounding FPCR 11mn" 00000000 F8000000 00000000 F8000000 +r 97F0.10 # RM / RNTE RM / RZ +*Want "DIDBR Rounding FPCR 11op" 00000000 F8000000 00000000 F8000000 +r 9800.10 # RM / RP RM / RM +*Want "DIDBR Rounding FPCR 11qr" 00000000 F8000000 00000000 F8000000 +r 9810.10 # RFS / RNTA RFS / RFS +*Want "DIDBR Rounding FPCR 11st" 00000000 F8000000 00000000 F8000000 +r 9810.10 # RFS / RNTE RFS / RZ +*Want "DIDBR Rounding FPCR 11uv" 00000000 F8000000 00000000 F8000000 +r 9820.10 # RFS / RP RFS / RM +*Want "DIDBR Rounding FPCR 11wx" 00000000 F8000000 00000000 F8000000 +r 9830.10 # RZ / RNTA RZ / RFS +*Want "DIDBR Rounding FPCR 12ab" 00000000 F8000000 00000000 F8000000 +r 9840.10 # RZ / RNTE RZ / RZ +*Want "DIDBR Rounding FPCR 12cd" 00000000 F8000000 00000000 F8000000 +r 9850.10 # RZ / RP RZ / RM +*Want "DIDBR Rounding FPCR 12ef" 00000000 F8000000 00000000 F8000000 +r 9860.10 # RP / RNTA RP / RFS +*Want "DIDBR Rounding FPCR 12gh" 00000000 F8000000 00000000 F8000000 +r 9870.10 # RP / RNTE RP / RZ +*Want "DIDBR Rounding FPCR 12ij" 00000000 F8000000 00000000 F8000000 +r 9880.10 # RP / RP RP / RM +*Want "DIDBR Rounding FPCR 12kl" 00000000 F8000000 00000000 F8000000 +r 9890.10 # RM / RNTA RM / RFS +*Want "DIDBR Rounding FPCR 12mn" 00000000 F8000000 00000000 F8000000 +r 98A0.10 # RM / RNTE RM / RZ +*Want "DIDBR Rounding FPCR 12op" 00000000 F8000000 00000000 F8000000 +r 98B0.10 # RM / RP RM / RM +*Want "DIDBR Rounding FPCR 12qr" 00000000 F8000000 00000000 F8000000 +r 98C0.10 # RFS / RNTA RFS / RFS +*Want "DIDBR Rounding FPCR 12st" 00000000 F8000000 00000000 F8000000 +r 98D0.10 # RFS / RNTE RFS / RZ +*Want "DIDBR Rounding FPCR 12uv" 00000000 F8000000 00000000 F8000000 +r 98E0.10 # RFS / RP RFS / RM +*Want "DIDBR Rounding FPCR 12wx" 00000000 F8000000 00000000 F8000000 + + +*Done + diff --git a/tests/bfp-002-loadr.asm b/tests/bfp-002-loadr.asm new file mode 100644 index 000000000..7e91a24b2 --- /dev/null +++ b/tests/bfp-002-loadr.asm @@ -0,0 +1,1197 @@ + TITLE 'ieee-loadr.asm: Test IEEE Load Rounded' +*********************************************************************** +* +*Testcase IEEE LOAD ROUNDED +* Test case capability includes IEEE exceptions, trappable and +* otherwise. Test result, FPCR flags, and DXC saved for all tests. +* Load Rounded does not set the condition code. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* bfp-002-loadr.asm +* +* This assembly-language source file is part of the +* Hercules Decimal Floating Point Validation Package +* by Stephen R. Orso +* +* Copyright 2016 by Stephen R Orso. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* +* 3. The name of the author may not be used to endorse or promote +* products derived from this software without specific prior written +* permission. +* +* DISCLAMER: THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* HOLDER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* +*Testcase IEEE LOAD ROUNDED +* Test case capability includes ieee exceptions trappable and +* otherwise. Test result, FPCR flags, and DXC saved for all tests. +* Load Rounded does not set the condition code. +* +* Tests the following three conversion instructions +* LOAD ROUNDED (long to short BFP, RRE) +* LOAD ROUNDED (extended to short BFP, RRE) +* LOAD ROUNDED (extended to long BFP, RRE) +* LOAD ROUNDED (long short BFP, RRF-e) +* LOAD ROUNDED (extended to long BFP, RRF-e) +* LOAD ROUNDED (extended to short BFP, RRF-e) +* +* This routine exhaustively tests rounding in 32- and 64-bit binary +* floating point. It is not possible to use Load Rounded to test +* rounding of 128-bit results. There is no Load Rounded that returns +* a 128-bit result. +* +* Test data is compiled into this program. The test script that runs +* this program can provide alternative test data through Hercules R +* commands. +* +* Test Case Order +* 1) Long to short BFP basic tests (exception traps and flags, NaNs) +* 2) Long to short BFP rounding mode tests +* 3) Extended to short BFP basic tests +* 4) Extended to short BFP rounding mode tests +* 5) Extended to long BFP basic tests. +* 6) Extended to long BFP rounding mode tests +* 7) Long to short BFP trappable underflow and overflow tests +* 8) Extended to short BFP trappable underflow and overflow tests +* 9) Extended to Long BFP trappable underflow and overflow tests +* +* Test data is 'white box,' meaning it is keyed to the internal +* characteristics of Softfloat 3a, while expecting results to conform +* to the z/Architecture Principles of Opeartion, SA22-7832-10. +* +* In the discussion below, "stored significand" does not include the +* implicit units digit that is always assumed to be one for a non- +* tiny Binary Floating Point value. +* +* Round long or extended to short: Softfloat uses the left-most 30 +* bits of the long or extended BFP stored significand for +* rounding, which means 7 'extra' bits participate in the +* rounding. If any of the right-hand 22 bits are non-zero, the +* 30-bit pre-rounded value is or'd with 1 in the low-order bit +* position. Bit 30 is the "sticky bit." +* +* Round extended to long: Softfloat uses the left-most 62 bits of +* the extended BFP stored significand for rounding, which means +* 10 'extra' bits participate in the rounding. If any of the +* remaining right-hand 50 bits are non-zero, the 62-bit pre- +* rounded value is or'd with 1 in the low-order bit position. Bit 62 +* is the "sticky bit." At least one of the test cases will have one +* bits in only the low-order 64 bits of the stored significand. +* +* The or'd 1 bit representing the bits not participating in the +* rounding process prevents false exacts. False exacts would +* otherwise occur when the extra 7 or 10 bits that participate +* in rounding are zero and bits to the right of them are not. +* +* Basic test cases are needed as follows: +* 0, +1.5, -1.5, QNaN, SNaN, +* +* Rounding test cases are needed as follows: +* Exact results are represented (no rounding needed) +* Ties are represented, both even (round down) and odd (round up) +* False exacts are represented +* Nearest value is toward zero +* Nearest value is away from zero. +* Each of the above must be represented in positive and negative. +* +* Because rounding decisions are based on the binary significand, +* there is limited value to considering test case inputs in +* decimal form. The binary representations are all that is +* important. +* +* If overflow/underflow occur and are trappable, the result should +* be in the source format but scaled to the target precision. +* These test cases are handled by both the basic tests to +* ensure that the non-trap results are correct and again by +* specific trappable overflow/underflow tests to ensure that the +* scaled result rounded to target precision is returned in +* the source format. +* +* Overflow/underflow behavior also means that result registers +* must be sanitized and allocated in pairs for extended inputs; +* results must store source format registers. Basic tests +* for overflow/underflow only store the target precision, so +* *Want needs to be coded accordingly. The trappable +* overflow/underflow tests store the source format. +* +* Overflow/underflow test cases include inputs that overflow +* the target precision and that result in a tiny in the target. +* Rounding mode for all overflow/underflow testing is Round +* to Nearest, Ties to Even (RNTE). +* +* Rounding test cases are needed as follows: +* Exact results are represented (no rounding needed) +* Ties are represented, both even (round down) and odd (round up) +* False exacts are represented +* Nearest value is toward zero +* Nearest value is away from zero. +* Each of the above must be represented in positive and negative. +* +* Because rounding decisions are based on the binary significand, +* there is limited value to considering test case inputs in +* decimal form. The binary representations are all that is +* important. +* +* Three input test data sets are provided, one for long to short, one +* for extended to short, and one for extended to long. We cannot use +* the same extended inputs for long and short results because the +* rounding points differ for the two result precisions. +* +* Also tests the following floating point support instructions +* LOAD (Short) +* LOAD (Long) +* LFPC (Load Floating Point Control Register) +* SRNMB (Set BFP Rounding Mode 3-bit) +* STFPC (Store Floating Point Control Register) +* STORE (Short) +* STORE (Long) +* + MACRO + PADCSECT &ENDLABL + AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + AGO .GOODPAD + AIF (D'&ENDLABL).GOODPAD + MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + MNOTE *,'No CSECT padding performed' + MEXIT +.GOODPAD ANOP + ORG &ENDLABL-1 + MEXIT +.NOPAD ANOP + MNOTE *,'asma detected; no CSECT padding performed' + MEND +* +BFPLDRND START 0 +R0 EQU 0 +R1 EQU 1 +R2 EQU 2 +R3 EQU 3 +R4 EQU 4 +R5 EQU 5 +R6 EQU 6 +R7 EQU 7 +R8 EQU 8 +R9 EQU 9 +R10 EQU 10 +R11 EQU 11 +R12 EQU 12 +R13 EQU 13 +R14 EQU 14 +R15 EQU 15 +* +* Floating Point Register equates to keep the cross reference clean +* +FPR0 EQU 0 +FPR1 EQU 1 +FPR2 EQU 2 +FPR3 EQU 3 +FPR4 EQU 4 +FPR5 EQU 5 +FPR6 EQU 6 +FPR7 EQU 7 +FPR8 EQU 8 +FPR9 EQU 9 +FPR10 EQU 10 +FPR11 EQU 11 +FPR12 EQU 12 +FPR13 EQU 13 +FPR14 EQU 14 +FPR15 EQU 15 +* + USING *,R15 +* +* Above works on real iron (R15=0 after sysclear) +* and in z/CMS (R15 points to start of load module) +* + ORG BFPLDRND+X'8E' Program check interrution code +PCINTCD DS H +* +PCOLDPSW EQU BFPLDRND+X'150' z/Arch Program check old PSW +* + ORG BFPLDRND+X'1A0' z/Arch Restart PSW + DC X'0000000180000000',AD(START) +* + ORG BFPLDRND+X'1D0' z/Arch Program check old PSW + DC X'0000000000000000',AD(PROGCHK) +* +* Program check routine. If Data Exception, continue execution at +* the instruction following the program check. Otherwise, hard wait. +* No need to collect data. All interesting DXC stuff is captured +* in the FPCR. +* + ORG BFPLDRND+X'200' +PROGCHK DS 0H Program check occured... + CLI PCINTCD+1,X'07' Data Exception? + JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) + LPSWE PCOLDPSW ..yes, resume program execution +PCNOTDTA DS 0H + LTR R14,R14 Return address provided? + BNZR R14 Yes, return to z/CMS test rig. + LPSWE HARDWAIT Not data exception, enter disabled wait + EJECT +*********************************************************************** +* +* Main program. Enable Advanced Floating Point, process test cases. +* +START STCTL R0,R0,CTLR0 Store CR0 to enable AFP + OI CTLR0+1,X'04' Turn on AFP bit + LCTL R0,R0,CTLR0 Reload updated CR0 +* +* Long Load Rounded to short tests +* + LA R10,LTOSBAS Long BFP test inputs + BAS R13,LEDBR Load rounded to short BFP + LA R10,LTOSRM Long BFP inputs for rounding tests + BAS R13,LEDBRA Round to short BFP using rm options +* +* Extended Load Rounded to short tests +* + LA R10,XTOSBAS Point to extended BFP test inputs + BAS R13,LEXBR Load rounded to short BFP + LA R10,XTOSRM Extended BFP inputs for rounding tests + BAS R13,LEXBRA Round to short BFP using rm options +* +* Extended Load Rounded to short tests +* + LA R10,XTOLBAS Point to extended BFP test inputs + BAS R13,LDXBR Load rounded to long BFP + LA R10,XTOLRM Extended BFP inputs for rounding tests + BAS R13,LDXBRA Round to long BFP using rm options +* +* Trappable long to short tests +* + LA R10,LTOSOU Long BFP over/underflow test inputs + BAS R13,LEDBROUT Load rounded to short BFP, trappable +* +* Trappable extended to short tests +* + LA R10,XTOSOU Extended BFP over/underflow test inputs + BAS R13,LEXBROUT Load rounded to short BFP, trappable +* +* Trappable extended to long tests +* + LA R10,XTOLOU Extended BFP over/underflow test inputs + BAS R13,LDXBROUT Load rounded to long BFP, trappable +* + LTR R14,R14 Return address provided? + BNZR R14 ..Yes, return to z/CMS test rig. + LPSWE WAITPSW ..No, load disabled wait PSW +* + DS 0D Ensure correct alignment for psw +WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end +* +CTLR0 DS F +FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags +* +* Input values parameter list, four fullwords: +* 1) Count, +* 2) Address of inputs, +* 3) Address to place results, and +* 4) Address to place DXC/Flags/cc values. +* + ORG BFPLDRND+X'300' +LTOSBAS DS 0F Inputs for long to short BFP tests + DC A(LTOSCT/8) + DC A(LTOSIN) + DC A(LTOSOUT) + DC A(LTOSFLGS) +* +XTOSBAS DS 0F Inputs for extended to short BFP tests + DC A(XTOSCT/16) + DC A(XTOSIN) + DC A(XTOSOUT) + DC A(XTOSFLGS) +* +XTOLBAS DS 0F Inputs for extended to long BFP tests + DC A(XTOLCT/16) + DC A(XTOLIN) + DC A(XTOLOUT) + DC A(XTOLFLGS) +* +LTOSRM DS 0F Inputs for long to short BFP rounding tests + DC A(LTOSRMCT/8) + DC A(LTOSINRM) + DC A(LTOSRMO) + DC A(LTOSRMOF) +* +XTOSRM DS 0F Inputs for extended to short BFP rounding tests + DC A(XTOSRMCT/16) + DC A(XTOSINRM) + DC A(XTOSRMO) + DC A(XTOSRMOF) +* +XTOLRM DS 0F Inputs for extended to long BFP rounding tests + DC A(XTOLRMCT/16) + DC A(XTOLINRM) + DC A(XTOLRMO) + DC A(XTOLRMOF) +* +LTOSOU DS 0F Inputs for long to short BFP rounding tests + DC A(LTOSOUCT/8) + DC A(LTOSINOU) + DC A(LTOSOUO) + DC A(LTOSOUOF) +* +XTOSOU DS 0F Inputs for extended to short BFP rounding tests + DC A(XTOSOUCT/16) + DC A(XTOSINOU) + DC A(XTOSOUO) + DC A(XTOSOUOF) +* +XTOLOU DS 0F Inputs for extended to long BFP rounding tests + DC A(XTOLOUCT/16) + DC A(XTOLINOU) + DC A(XTOLOUO) + DC A(XTOLOUOF) + EJECT +*********************************************************************** +* +* Round long BFP to short BFP. A pair of results is generated for each +* input: one with all exceptions non-trappable, and the second with all +* exceptions trappable. The FPCR contents are stored for each result. +* +*********************************************************************** + SPACE 2 +LEDBR LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LZDR FPR1 Zero FRP1 to clear any residual + LD FPR0,0(,R3) Get long BFP test value + LFPC FPCREGNT Set exceptions non-trappable + LEDBR FPR1,FPR0 Cvt long in FPR0 to short in FPR1 + STE FPR1,0(,R7) Store short BFP result + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LZDR FPR1 Zero FRP1 to clear any residual + LFPC FPCREGTR Set exceptions trappable + LEDBR FPR1,FPR0 Cvt long in FPR0 to short in FPR1 + STE FPR1,4(,R7) Store short BFP result + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LA R3,8(,R3) Point to next input value + LA R7,8(,R7) Point to next result pair + LA R8,8(,R8) Point to next FPCR result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Round long BFP to short BFP. Inputs are expected to generate +* overflow or underflow exceptions, all of which are trappable. This +* means a scaled result should be generated rounded to the target +* precision but returned in the source precision. The FPCR contents +* are stored for each result. +* +*********************************************************************** + SPACE 2 +LEDBROUT LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LZDR FPR1 Zero FRP1 to clear any residual + LD FPR0,0(,R3) Get long BFP test value + LFPC FPCREGTR Set exceptions trappable + LEDBR FPR1,FPR0 Cvt long in FPR0 into short in FPR1 + STD FPR1,0(,R7) Store long scaled BFP trapped result + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LA R3,8(,R3) Point to next input value + LA R7,8(,R7) Point to next long trapped result value + LA R8,4(,R8) Point to next FPCR result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert long BFP to rounded short BFP using each possible rounding +* mode. Ten test results are generated for each input. A 48-byte test +* result section is used to keep results sets aligned on a quad-double +* word. +* +* The first four tests use rounding modes specified in the FPCR with +* the IEEE Inexact exception supressed. SRNM (2-bit) is used for +* the first two FPCR-controlled tests and SRNMB (3-bit) is used for +* the last two To get full coverage of that instruction pair. +* +* The next six results use instruction-specified rounding modes. +* +* The default rounding mode (0 for RNTE) is not tested in this +* section; prior tests used the default rounding mode. RNTE is tested +* explicitly as a rounding mode in this section. +* +*********************************************************************** + SPACE 2 +LEDBRA LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LD FPR0,0(,R3) Get long BFP test value +* +* Test cases using rounding mode specified in the FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 1 SET FPCR to RZ, Round towards zero. + LEDBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, mask inexact + STE FPR1,0*4(,R7) Store shortened rounded BFP result + STFPC 0(R8) Store resulting FPCRflags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 2 SET FPCR to RP, Round to +infinity + LEDBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, mask inexact + STE FPR1,1*4(,R7) Store shortened rounded BFP result + STFPC 1*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 3 SET FPCR to RM, Round to -infinity + LEDBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, mask inexact + STE FPR1,2*4(,R7) Store shortened rounded BFP result + STFPC 2*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 7 RFS, Round Prepare for Shorter Precision + LEDBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, mask inexact + STE FPR1,3*4(,R7) Store shortened rounded BFP result + STFPC 3*4(R8) Store resulting FPCR flags and DXC +* +* Test cases using rounding mode specified in the instruction M3 field +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + LEDBRA FPR1,1,FPR0,B'0000' RNTA, to nearest, ties away + STE FPR1,4*4(,R7) Store shortened rounded BFP result + STFPC 4*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + LEDBRA FPR1,3,FPR0,B'0000' RFS, prepare for shorter precision + STE FPR1,5*4(,R7) Store shortened rounded BFP result + STFPC 5*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + LEDBRA FPR1,4,FPR0,B'0000' RNTE, to nearest, ties to even + STE FPR1,6*4(,R7) Store shortened rounded BFP result + STFPC 6*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + LEDBRA FPR1,5,FPR0,B'0000' RZ, toward zero + STE FPR1,7*4(,R7) Store shortened rounded BFP result + STFPC 7*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + LEDBRA FPR1,6,FPR0,B'0000' RP, to +inf + STE FPR1,8*4(,R7) Store shortened rounded BFP result + STFPC 8*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + LEDBRA FPR1,7,FPR0,B'0000' RM, to -inf + STE FPR1,9*4(,R7) Store shortened rounded BFP result + STFPC 9*4(R8) Store resulting FPCR flags and DXC +* + LA R3,8(,R3) Point to next input value + LA R7,12*4(,R7) Point to next short BFP result pair + LA R8,12*4(,R8) Point to next FPCR result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Round extended BFP to short BFP. A pair of results is genearted for +* each input: one with all exceptions non-trappable, and the second +* with all exceptions trappable. The FPCR contents are stored for +* each result. +* +*********************************************************************** + SPACE 2 +LEXBR LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LD FPR0,0(,R3) Get extended BFP test value part 1 + LD R2,8(,R3) Get extended BFP test value part 2 + LFPC FPCREGNT Set exceptions non-trappable + LEXBR FPR1,FPR0 Cvt extended in FPR0-2 to short in FPR1 + STE R1,0(,R7) Store short BFP result + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LZDR FPR1 Eliminate any residual results + LEXBR FPR1,FPR0 Cvt extended in FPR0-2 to short in FPR1 + STE FPR1,4(,R7) Store short BFP result + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LA R3,16(,R3) Point to next input value + LA R7,8(,R7) Point to next long rounded value pair + LA R8,8(,R8) Point to next FPCR result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Round extended BFP to short BFP. Inputs are expected to generate +* overflow or underflow exceptions, all of which are trappable. This +* means a scaled result should be generated rounded to the target +* precision but returned in the source precision. The FPCR contents +* are stored for each result. +* +*********************************************************************** + SPACE 2 +LEXBROUT LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LD FPR0,0(,R3) Get extended BFP test value part 1 + LD R2,8(,R3) Get extended BFP test value part 2 + LFPC FPCREGTR Set exceptions trappable + LEXBR FPR1,FPR0 Cvt float in FPR0-2 to scaled in FPR1-3 + STD FPR1,0(,R7) Store scaled extended BFP result part 1 + STD FPR3,8(,R7) Store scaled extended BFP result part 2 + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LA R3,16(,R3) Point to next input value + LA R7,16(,R7) Point to next extended trapped result + LA R8,4(,R8) Point to next FPCR result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert long BFP to integers using each possible rounding mode. +* Ten test results are generated for each input. A 48-byte test result +* section is used to keep results sets aligned on a quad-double word. +* +* The first four tests use rounding modes specified in the FPCR with +* the IEEE Inexact exception supressed. SRNM (2-bit) is used for +* the first two FPCR-controlled tests and SRNMB (3-bit) is used for +* the last two To get full coverage of that instruction pair. +* +* The next six results use instruction-specified rounding modes. +* +* The default rounding mode (0 for RNTE) is not tested in this +* section; prior tests used the default rounding mode. RNTE is tested +* explicitly as a rounding mode in this section. +* +*********************************************************************** + SPACE 2 +LEXBRA LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LD FPR0,0(,R3) Get long BFP test value +* +* Test cases using rounding mode specified in the FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 1 SET FPCR to RZ, Round towards zero. + LEXBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, mask inexact + STD FPR1,0*4(,R7) Store shortened rounded BFP result + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 2 SET FPCR to RP, Round to +infinity + LEXBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, mask inexact + STD FPR1,1*4(,R7) Store shortened rounded BFP result + STFPC 1*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 3 SET FPCR to RM, Round to -infinity + LEXBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, mask inexact + STD FPR1,2*4(,R7) Store shortened rounded BFP result + STFPC 2*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 7 RFS, Round Prepare for Shorter Precision + LEXBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, mask inexact + STD FPR1,3*4(,R7) Store shortened rounded BFP result + STFPC 3*4(R8) Store resulting FPCR flags and DXC +* +* Test cases using rounding mode specified in the instruction M3 field +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + LEXBRA FPR1,1,FPR0,B'0000' RNTA, to nearest, ties away + STD FPR1,4*4(,R7) Store shortened rounded BFP result + STFPC 4*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + LEXBRA FPR1,3,FPR0,B'0000' RFS, prepare for shorter precision + STD FPR1,5*4(,R7) Store shortened rounded BFP result + STFPC 5*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + LEXBRA FPR1,4,FPR0,B'0000' RNTE, to nearest, ties to even + STD FPR1,6*4(,R7) Store shortened rounded BFP result + STFPC 6*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + LEXBRA FPR1,5,FPR0,B'0000' RZ, toward zero + STD FPR1,7*4(,R7) Store shortened rounded BFP result + STFPC 7*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + LEXBRA FPR1,6,FPR0,B'0000' RP, to +inf + STD FPR1,8*4(,R7) Store shortened rounded BFP result + STFPC 8*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + LEXBRA FPR1,7,FPR0,B'0000' RM, to -inf + STD FPR1,9*4(,R7) Store shortened rounded BFP result + STFPC 9*4(R8) Store resulting FPCR flags and DXC +* + LA R3,16(,R3) Point to next input value + LA R7,12*4(,R7) Point to next long BFP converted values + LA R8,12*4(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Round extended BFP to long BFP. A pair of results is generated for +* each input: one with all exceptions non-trappable, and the second +* with all exceptions trappable. The FPCR contents are stored for +* each result. +* +*********************************************************************** + SPACE 2 +LDXBR LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LD FPR0,0(,R3) Get extended BFP test value part 1 + LD R2,8(,R3) Get extended BFP test value part 1 + LFPC FPCREGNT Set exceptions non-trappable + LDXBR FPR1,FPR0 Round extended in FPR0-2 to long in FPR1 + STD FPR1,0(,R7) Store shortened rounded BFP result + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LZXR FPR1 Eliminate any residual results + LDXBR FPR1,FPR0 Round extended in FPR0-2 to long in FPR1 + STD FPR1,8(,R7) Store shortened rounded BFP result + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LA R3,16(,R3) Point to next extended BFP input value + LA R7,16(,R7) Point to next long BFP rounded value pair + LA R8,8(,R8) Point to next FPCR result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Round extended BFP to long BFP. Inputs are expected to generate +* overflow or underflow exceptions, all of which are trappable. This +* means a scaled result should be generated rounded to the target +* precision but returned in the source precision. The FPCR contents +* are stored for each result. +* +*********************************************************************** + SPACE 2 +LDXBROUT LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LD FPR0,0(,R3) Get extended BFP test value part 1 + LD R2,8(,R3) Get extended BFP test value part 1 + LFPC FPCREGTR Set exceptions trappable + LDXBR FPR1,FPR0 Round ext'd in FPR0-2 to scaled in FPR1-3 + STD FPR1,0(,R7) Store scaled extended BFP result part 1 + STD FPR3,8(,R7) Store scaled extended BFP result part 2 + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LA R3,16(,R3) Point to next extended BFP input value + LA R7,16(,R7) Point to next long BFP rounded value pair + LA R8,4(,R8) Point to next FPCR result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert extended BFP to integers using each possible rounding mode. +* Ten test results are generated for each input. A 48-byte test result +* section is used to keep results sets aligned on a quad-double word. +* +* The first four tests use rounding modes specified in the FPCR with +* the IEEE Inexact exception supressed. SRNM (2-bit) is used for +* the first two FPCR-controlled tests and SRNMB (3-bit) is used for +* the last two To get full coverage of that instruction pair. +* +* The next six results use instruction-specified rounding modes. +* +* The default rounding mode (0 for RNTE) is not tested in this +* section; `prior tests used the default rounding mode. RNTE is tested +* explicitly as a rounding mode in this section. +* +*********************************************************************** + SPACE 2 +LDXBRA LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LD FPR0,0(,R3) Get extended BFP test value part 1 + LD R2,8(,R3) Get extended BFP test value part 2 +* +* Test cases using rounding mode specified in the FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 1 SET FPCR to RZ, Round towards zero. + LDXBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, mask inexact + STD FPR1,0*8(,R7) Store shortened rounded BFP result + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 2 SET FPCR to RP, Round to +infinity + LDXBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, mask inexact + STD FPR1,1*8(,R7) Store shortened rounded BFP result + STFPC 1*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 3 SET FPCR to RM, Round to -infinity + LDXBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, mask inexact + STD FPR1,2*8(,R7) Store shortened rounded BFP result + STFPC 2*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 7 RFS, Round Prepare for Shorter Precision + LDXBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, mask inexact + STD FPR1,3*8(,R7) Store shortened rounded BFP result + STFPC 3*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + LDXBRA FPR1,1,FPR0,B'0000' RNTA, to nearest, ties away + STD FPR1,4*8(,R7) Store shortened rounded BFP result + STFPC 4*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + LDXBRA FPR1,3,FPR0,B'0000' RFS, prepare for shorter precision + STD FPR1,5*8(,R7) Store shortened rounded BFP result + STFPC 5*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + LDXBRA FPR1,4,FPR0,B'0000' RNTE, to nearest, ties to even + STD FPR1,6*8(,R7) Store shortened rounded BFP result + STFPC 6*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + LDXBRA FPR1,5,FPR0,B'0000' RZ, toward zero + STD FPR1,7*8(,R7) Store shortened rounded BFP result + STFPC 7*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + LDXBRA FPR1,6,FPR0,B'0000' RP, to +inf + STD FPR1,8*8(,R7) Store shortened rounded BFP result + STFPC 8*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + LDXBRA FPR1,7,FPR0,B'0000' RM, to -inf + STD FPR1,9*8(,R7) Store shortened rounded BFP result + STFPC 9*4(R8) Store resulting FPCR flags and DXC +* + LA R3,16(,R3) Point to next input value + LA R7,10*8(,R7) Point to next long BFP rounded result + LA R8,12*4(,R8) Point to next FPCR result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* BFP inputs. One set of longs and two sets of extendeds are included. +* Each set includes input values for basic exception testing and input +* values for exhaustive rounding mode testing. One set of extended +* inputs is used to generate short results, and the other is used to +* generate long results. The same set cannot be used for both long +* and short because the rounding points are different. +* +* We can cheat and use the same decimal values for long to short and +* and extended to short because the result has the same number of +* bits and the rounding uses the same number of bits in the pre- +* rounded result. +* +*********************************************************************** + SPACE 2 +* +* Long to short basic tests, which tests trappable results, NaN +* propagation, and basic functionality. The second part of this list +* is used for testing trappable results. +* +LTOSIN DS 0D Inputs for long to short BFP basic tests + DC X'0000000000000000' +0 + DC X'3FF8000000000000' +1.5 + DC X'BFF8000000000000' -1.5 + DC X'7FF0100000000000' SNaN + DC X'7FF8110000000000' QNaN +* See rounding tests below for details on the following four +LTOSINOU DS 0D start of under/overflow tests + DC X'47EFFFFFFFFFFFFF' Positive oveflow test + DC X'C7EFFFFFFFFFFFFF' Negative oveflow test + DC X'47FFFFFFEFFFFFFF' Positive oveflow prec. test + DC X'C7FFFFFFEFFFFFFF' Negative oveflow prec. test + DC X'3690000000000000' Positive magnitude underflow + DC X'B690000000000000' Negative magnitude underflow + DC X'47F0000000000000' Positive magnitude overflow + DC X'C7F0000000000000' Negative magnitude overflow +* +LTOSCT EQU *-LTOSIN Count of long BFP in list * 8 +LTOSOUCT EQU *-LTOSINOU Ct * 8 of trappable over/underflow tests + SPACE 3 +* +* Test cases for exhaustive rounding mode tests of long to short +* Load Rounded. +* +LTOSINRM DS 0D Inputs for long to short BFP rounding tests +* x'8000000000000000' sign bit +* x'7FF0000000000000' Biased Exponent +* x'000FFFFFE0000000' Significand used in short +* x'000000001FC00000' Significand used in rounding +* x'00000000003FFFFF' 'extra' significand bits +* Note: in the comments below, 'up' and 'down' mean 'toward +* higher magnitude' and 'toward lower magnitude' respectively and +* without regard to the sign, and rounding is to short BFP. +* +* Exact (fits in short BFP) .. 1.99999988079071044921875 + DC X'3FFFFFFFE0000000' Positive exact + DC X'BFFFFFFFE0000000' Negative exact +* +* Tie odd - rounds up .. 1.999999940395355224609375 +* rounds up to .. 2.0 +* rounds down to .. 1.99999988079071044921875 + DC X'3FFFFFFFF0000000' Positive tie odd + DC X'BFFFFFFFF0000000' Negative tie odd +* +* Tie even - rounds down .. 1.999999821186065673828125 +* rounds up to .. 1.99999988079071044921875 +* rounds down to .. 1.9999997615814208984375 + DC X'3FFFFFFFD0000000' Positive tie even + DC X'BFFFFFFFD0000000' Negative tie even +* +* False exact 1.9999998817220328017896235905936919152736663818359375 +* ..rounds up to 2.0 +* ..rounds down to 1.99999988079071044921875 + DC X'3FFFFFFFE03FFFFF' Positive false exact + DC X'BFFFFFFFE03FFFFF' Negative false exact +* +* Nearest is towards zero: 1.9999998812563717365264892578125 +* ..rounds up to 2.0 +* ..rounds down to 1.99999988079071044921875 + DC X'3FFFFFFFE0200000' Positive zero closer + DC X'BFFFFFFFE0200000' Negative zero closer +* +* Nearest is away from zero: 1.999999999068677425384521484375 +* ..rounds up to 2.0 +* ..rounds down to 1.99999988079071044921875 + DC X'3FFFFFFFFFC00000' Positive zero further + DC X'BFFFFFFFFFC00000' Negative zero further +* +* Overflow test: 3.40282366920938425684442744474606501888E38 +* ..rounds up to Overflow +* ..rounds down to 3.40282346638528859811704183484516925440E38 + DC X'47EFFFFFFFFFFFFF' Positive oveflow test + DC X'C7EFFFFFFFFFFFFF' Negative oveflow test +* +* Underflow test: 7.00649232162408535461864791644958...E-46 +* ..rounds up to 1.40129846432481707092372958328991...E-45 +* represented in short bfp as a tiny. +* ..rounds down to underflow (but exact) + DC X'3690000000000000' Positive magnitude underflow + DC X'B690000000000000' Negative magnitude underflow +LTOSRMCT EQU *-LTOSINRM Count of long BFP rounding tests * 8 + SPACE 3 +* +* Extended to short basic tests, which tests trappable results, NaN +* propagation, and basic functionality. The second part of this list +* is used for testing trappable results. +* +XTOSIN DS 0D Inputs for extended to short BFP basic tests + DC X'00000000000000000000000000000000' +0 + DC X'3FFF8000000000000000000000000000' +1.5 + DC X'BFFF8000000000000000000000000000' -1.5 + DC X'7FFF0100000000000000000000000000' SNaN + DC X'7FFF8110000000000000000000000000' QNaN +* See rounding tests below for details on the following four +XTOSINOU DS 0D start of over/underflow test cases + DC X'407EFFFFFFFFFFFFFFFFFFFFFFFFFFFF' Pos. oveflow test + DC X'C07EFFFFFFFFFFFFFFFFFFFFFFFFFFFF' Neg. oveflow test + DC X'407FFFFFFEFFFFFFFFFFFFFFFFFFFFFF' Pos. oveflow test + DC X'C07FFFFFFEFFFFFFFFFFFFFFFFFFFFFF' Neg. oveflow test + DC X'3F690000000000000000000000000000' Pos. exact uflow +* ..result is tiny + DC X'BF690000000000000000000000000000' Neg. exact uflow +* ..result is tiny + DC X'407F0000000000000000000000000000' Pos. exact oflow + DC X'C07F0000000000000000000000000000' Neg. exact oflow +* +XTOSCT EQU *-XTOSIN Count of extended BFP in list * 16 +XTOSOUCT EQU *-XTOSINOU Ct * 16 of trappable over/underflow tests + SPACE 3 +* +* Test cases for exhaustive rounding mode tests of extended to short +* Load Rounded. +* +XTOSINRM DS 0D Inputs for extended to short BFP rounding tests +* x'80000000000000000000000000000000' sign bit +* x'7FFF0000000000000000000000000000' Biased Exponent +* x'0000FFFFFE0000000000000000000000' Sig'd used in short +* x'0000000001FC00000000000000000000' Sig'd used in rndg +* x'000000000003FFFFFFFFFFFFFFFFFFFF' 'extra' sig'd bits +* Note: in the comments below, 'up' and 'down' mean 'toward +* higher magnitude' and 'toward lower magnitude' respectively and +* without regard to the sign, and rounding is to short BFP. +* +* Exact (fits in short BFP) .. 1.99999988079071044921875 + DC X'3FFFFFFFFE0000000000000000000000' Pos. exact + DC X'BFFFFFFFFE0000000000000000000000' Neg. exact +* +* Tie odd - rounds up .. 1.999999940395355224609375 +* rounds up to .. 2.0 +* rounds down to .. 1.99999988079071044921875 + DC X'3FFFFFFFFF0000000000000000000000' Pos. tie odd + DC X'BFFFFFFFFF0000000000000000000000' Neg. tie odd +* +* Tie even - rounds down .. 1.999999821186065673828125 +* rounds up to .. 1.99999988079071044921875 +* rounds down to .. 1.9999997615814208984375 + DC X'3FFFFFFFFD0000000000000000000000' Pos. tie even + DC X'BFFFFFFFFD0000000000000000000000' Neg. tie even +* +* False exact 1.9999998817220330238342285156249998... (continues) +* ..07407005561276414694402205741507... (continues) +* ..2681461898351784611804760061204433441162109375 +* ..rounds up to 2.0 +* ..rounds down to 1.99999988079071044921875 + DC X'3FFFFFFFFE03FFFFFFFFFFFFFFFFFFFF' Pos. false exact + DC X'BFFFFFFFFE03FFFFFFFFFFFFFFFFFFFF' Neg. false exact +* +* Nearest is towards zero: 1.9999998812563717365264892578125 +* ..rounds up to 2.0 +* ..rounds down to 1.99999988079071044921875 + DC X'3FFFFFFFFE0200000000000000000000' Pos. zero closer + DC X'BFFFFFFFFE0200000000000000000000' Neg. zero closer +* +* Nearest is away from zero: 1.999999999068677425384521484375 +* ..rounds up to 2.0 +* ..rounds down to 1.99999988079071044921875 + DC X'3FFFFFFFFFFC00000000000000000000' Pos. zero further + DC X'BFFFFFFFFFFC00000000000000000000' Neg. zero further +* +* Overflow test: 3.40282366920938463463374607431768178688E38 +* ..rounds up to Overflow +* ..rounds down to 3.40282346638528859811704183484516925440E38 + DC X'407EFFFFFFFFFFFFFFFFFFFFFFFFFFFF' Pos. oveflow test + DC X'C07EFFFFFFFFFFFFFFFFFFFFFFFFFFFF' Neg. oveflow test +* +* Underflow test: 7.00649232162408535461864791644958...E-46 +* ..rounds up to 1.40129846432481707092372958328991...E-45 +* represented in short bfp as a tiny. +* ..rounds down to Underflow (but exact) + DC X'3F690000000000000000000000000000' Pos. exact u-flow +* ..result is tiny + DC X'BF690000000000000000000000000000' Neg. exact u-flow +* ..result is tiny +XTOSRMCT EQU *-XTOSINRM Count of extended BFP rounding tests * 16 +* +* Extended to long basic tests, which tests trappable results, NaN +* propagation, and basic functionality. The second part of this list +* is used for testing trappable results. +* +XTOLIN DS 0D Inputs for extended to long BFP basic tests + DC X'00000000000000000000000000000000' +0 + DC X'3FFF8000000000000000000000000000' +1.5 + DC X'BFFF8000000000000000000000000000' -1.5 + DC X'7FFF0100000000000000000000000000' SNaN + DC X'7FFF8110000000000000000000000000' QNaN +* See rounding tests below for details on the following four +XTOLINOU DS 0D Start of trappable over/underflow test cases + DC X'43FEFFFFFFFFFFFFFFFFFFFFFFFFFFFF' Pos. oveflow test + DC X'C3FEFFFFFFFFFFFFFFFFFFFFFFFFFFFF' Neg. oveflow test + DC X'43FFFFFFFFFFFFFFF7FFFFFFFFFFFFFF' Pos. oveflow test + DC X'C3FFFFFFFFFFFFFFF7FFFFFFFFFFFFFF' Neg. oveflow test + DC X'3BCC0000000000000000000000000000' Pos. underflow +* ..result is tiny + DC X'BBCC0000000000000000000000000000' Neg. underflow +* ..result is tiny + DC X'43FF0000000000000000000000000000' Pos. exact o-flow + DC X'C3FF0000000000000000000000000000' Neg. exact o-flow +XTOLCT EQU *-XTOLIN Count of extended BFP in list * 16 +XTOLOUCT EQU *-XTOLINOU Ct * 16 of trappable over/underflow tests +* +* Test cases for exhaustive rounding mode tests of long to short +* Load Rounded. +* +XTOLINRM DS 0D Inputs for extended to short BFP rounding tests +* x'80000000000000000000000000000000' sign bit +* x'7FFF0000000000000000000000000000' Biased Exponent +* x'0000FFFFFFFFFFFFF000000000000000' Sig'd used in long +* x'00000000000000000FFC000000000000' Sig'd used in rndg +* x'00000000000000000003FFFFFFFFFFFF' 'extra' sig'd bits +* +* Note: in the comments below, 'up' and 'down' mean 'toward +* higher magnitude' and 'toward lower magnitude' respectively and +* without regard to the sign, and rounding is to short BFP. +* +* +* Exact (fits in short BFP) +* .. 1.9999999999999997779553950749686919152736663818359375 +* + DC X'3FFFFFFFFFFFFFFFF000000000000000' Pos. exact + DC X'BFFFFFFFFFFFFFFFF000000000000000' Neg. exact +* +* +* Tie odd - rounds up +* .. 1.99999999999999988897769753748434595763683319091796875 +* rounds up to .. 2.0 +* rounds down to +* .. 1.9999999999999997779553950749686919152736663818359375 +* + DC X'3FFFFFFFFFFFFFFFF800000000000000' Pos. tie odd + DC X'BFFFFFFFFFFFFFFFF800000000000000' Neg. tie odd +* +* +* Tie even - rounds down +* .. 1.99999999999999966693309261245303787291049957275390625 +* rounds up to +* .. 1.9999999999999997779553950749686919152736663818359375 +* rounds down to +* .. 1.999999999999999555910790149937383830547332763671875 +* + DC X'3FFFFFFFFFFFFFFFE800000000000000' Pos. tie even + DC X'BFFFFFFFFFFFFFFFE800000000000000' Neg. tie even +* +* +* False exact 1.9999998817220330238342285156249998... (continues) +* ..07407005561276414694402205741507... (continues) +* ..2681461898351784611804760061204433441162109375 +* ..rounds up to 2.0 +* ..rounds down to +* .. 1.9999999999999997779553950749686919152736663818359375 +* + DC X'3FFFFFFFFFFFFFFFF003FFFFFFFFFFFF' Pos. false exact + DC X'BFFFFFFFFFFFFFFFF003FFFFFFFFFFFF' Neg. false exact +* +* +* Nearest is towards zero: +* .. 1.99999999999999977817223550946579280207515694200992584228515625 +* ..rounds up to 2.0 +* ..rounds down to +* .. 1.9999999999999997779553950749686919152736663818359375 +* + DC X'3FFFFFFFFFFFFFFFF004000000000000' Pos. zero closer + DC X'BFFFFFFFFFFFFFFFF004000000000000' Neg. zero closer +* +* Nearest is away from zero: +* .. 1.9999999999999999722444243843710864894092082977294921875 +* ..rounds up to 2.0 +* ..rounds down to +* .. 1.999999999999999555910790149937383830547332763671875 +* + DC X'3FFFFFFFFFFFFFFFFE00000000000000' Pos. zero further + DC X'BFFFFFFFFFFFFFFFFE00000000000000' Neg. zero further + DS 0D required by asma for following EQU to work. +* +* Overflow test: 1.797693134862315708145274237317043...E308 +* ..rounds up to Overflow +* ..rounds down to 1.797693134862315907729305190789024...E308 + DC X'43FEFFFFFFFFFFFFFFFFFFFFFFFFFFFF' Pos. oveflow test + DC X'C3FEFFFFFFFFFFFFFFFFFFFFFFFFFFFF' Neg. oveflow test +* +* Underflow test: 2.47032822920623272088284396434110...E-324 +* ..rounds up to 4.94065645841246544176568792868221...E-324 +* ..rounds down to Underflow + DC X'3BCC0000000000000000000000000000' Pos. tie odd +* ..result is tiny + DC X'BBCC0000000000000000000000000000' Neg. tie odd +* ..result is tiny +XTOLRMCT EQU *-XTOLINRM Count of extended BFP rounding tests * 16 +* +* Locations for results +* +LTOSOUT EQU BFPLDRND+X'1000' Short BFP rounded from long +* ..9 pairs used, room for 16 +LTOSFLGS EQU BFPLDRND+X'1080' FPCR flags and DXC from above +* ..9 pairs used, room for 16 +LTOSRMO EQU BFPLDRND+X'1100' Short BFP result rounding tests +* ..14 sets used, room for 21 +LTOSRMOF EQU BFPLDRND+X'1500' FPCR flags and DXC from above +* ..14 sets used, room for 21 +* +XTOSOUT EQU BFPLDRND+X'1900' Short BFP rounded from extended +* ..5 pairs used, room for 16 +XTOSFLGS EQU BFPLDRND+X'1980' FPCR flags and DXC from above +* ..5 pairs used, room for 16 +XTOSRMO EQU BFPLDRND+X'1A00' Short BFP rounding tests +* ..14 sets used, room for 21 +XTOSRMOF EQU BFPLDRND+X'1E00' FPCR flags and DXC from above +* ..14 sets used, room for 21 + +* +XTOLOUT EQU BFPLDRND+X'2200' Long BFP rounded from extended +* ..5 pairs used, room for 16 +XTOLFLGS EQU BFPLDRND+X'2300' FPCR flags and DXC from above +* ..5 pairs used, room for 32 +XTOLRMO EQU BFPLDRND+X'2400' Long BFP rounding tests +* ..12 results used, room for 22 +XTOLRMOF EQU BFPLDRND+X'2B00' FPCR flags and DXC from above +* ..12 results used, room for 21 +* +LTOSOUO EQU BFPLDRND+X'3000' Long BFP trappable o/uflow tests +* ..4 results used, room for 16 +LTOSOUOF EQU BFPLDRND+X'3080' FPCR flags and DXC from above +* +XTOSOUO EQU BFPLDRND+X'3100' Extd BFP trappable o/uflow tests +* ..4 results used, room for 8 +XTOSOUOF EQU BFPLDRND+X'3180' FPCR flags and DXC from above +* +XTOLOUO EQU BFPLDRND+X'3200' Extd BFP trappable o/uflow tests +* ..4 results used, room for 8 +XTOLOUOF EQU BFPLDRND+X'3280' FPCR flags and DXC from above +* +* +ENDRES EQU BFPLDRND+X'3300' next location for results +* + PADCSECT ENDRES Pad csect unless asma +* + END diff --git a/tests/bfp-002-loadr.core b/tests/bfp-002-loadr.core new file mode 100644 index 000000000..4c3c0f86c Binary files /dev/null and b/tests/bfp-002-loadr.core differ diff --git a/tests/bfp-002-loadr.list b/tests/bfp-002-loadr.list new file mode 100644 index 000000000..84071d295 --- /dev/null +++ b/tests/bfp-002-loadr.list @@ -0,0 +1,1438 @@ +ASMA Ver. 0.2.0 ieee-loadr.asm: Test IEEE Load Rounded 31 Aug 2016 19:54:48 Page 1 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 2 *********************************************************************** + 3 * + 4 *Testcase IEEE LOAD ROUNDED + 5 * Test case capability includes IEEE exceptions, trappable and + 6 * otherwise. Test result, FPCR flags, and DXC saved for all tests. + 7 * Load Rounded does not set the condition code. + 8 * + 9 *********************************************************************** + + + 11 *********************************************************************** + 12 * + 13 * + 14 *Testcase IEEE LOAD ROUNDED + 15 * Test case capability includes ieee exceptions trappable and + 16 * otherwise. Test result, FPCR flags, and DXC saved for all tests. + 17 * Load Rounded does not set the condition code. Overflow and + 18 * underflow are not tested by this program. + 19 * + 20 * Tests the following three conversion instructions + 21 * LOAD ROUNDED (long to short BFP, RRE) + 22 * LOAD ROUNDED (extended to short BFP, RRE) + 23 * LOAD ROUNDED (extended to long BFP, RRE) + 24 * LOAD ROUNDED (long short BFP, RRF-e) + 25 * LOAD ROUNDED (extended to long BFP, RRF-e) + 26 * LOAD ROUNDED (extended to short BFP, RRF-e) + 27 * + 28 * This routine exhaustively tests rounding in 32- and 64-bit binary + 29 * floating point. It is not possible to use Load Rounded to test + 30 * rounding of 128-bit results; we will have to back in to those tests + 31 * using Add. + 32 + 33 * Test data is compiled into this program. The test script that runs + 34 * this program can provide alternative test data through Hercules R + 35 * commands. + 36 * + 37 * Test Case Order + 38 * 1) Long to short BFP basic tests (exception traps and flags, NaNs) + 39 * 2) Long to short BFP rounding mode tests + 40 * 3) Extended to short BFP basic tests + 41 * 4) Extended to short BFP rounding mode tests + 42 * 5) Extended to long BFP basic tests. + 43 * 6) Extended to long BFP rounding mode tests + 44 * 7) Long to short BFP trappable underflow and overflow tests + 45 * 8) Extended to short BFP trappable underflow and overflow tests + 46 * 9) Extended to Long BFP trappable underflow and overflow tests + 47 * + 48 * Test data is 'white box,' meaning it is keyed to the internal + 49 * characteristics of Softfloat 3a, while expecting results to conform + 50 * to the z/Architecture Principles of Opeartion, SA22-7832-10. + 51 * + 52 * In the discussion below, "stored significand" does not include the + ASMA Ver. 0.2.0 ieee-loadr.asm: Test IEEE Load Rounded 31 Aug 2016 19:54:48 Page 2 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 53 * implicit units digit that is always assumed to be one for a non- + 54 * tiny Binary Floating Point value. + 55 * + 56 * Round long or extended to short: Softfloat uses the left-most 30 + 57 * bits of the long or extended BFP stored significand for + 58 * rounding, which means 7 'extra' bits participate in the + 59 * rounding. If any of the right-hand 22 bits are non-zero, the + 60 * 30-bit pre-rounded value is or'd with 1 in the low-order bit + 61 * position. + 62 * + 63 * Round extended to long: Softfloat uses the left-most 62 bits of + 64 * the extended BFP stored significand for rounding, which means + 65 * 10 'extra' bits participate in the rounding. If any of the + 66 * remaining right-hand 50 bits are non-zero, the 62-bit pre- + 67 * rounded value is or'd with 1 in the low-order bit position. + 68 * At least one of the test cases will have one bits in only the + 69 * low-order 64 bits of the stored significand. + 70 * + 71 * The or'd 1 bit representing the bits not participating in the + 72 * rounding process prevents false exacts. False exacts would + 73 * otherwise occur when the extra 7 or 10 bits that participate + 74 * in rounding are zero and bits to the right of them are not. + 75 * + 76 * Basic test cases are needed as follows: + 77 * 0, +1.5, -1.5, QNaN, SNaN, + 78 * + 79 * Rounding test cases are needed as follows: + 80 * Exact results are represented (no rounding needed) + 81 * Ties are represented, both even (round down) and odd (round up) + 82 * False exacts are represented + 83 * Nearest value is toward zero + 84 * Nearest value is away from zero. + 85 * Each of the above must be represented in positive and negative. + 86 * + 87 * Because rounding decisions are based on the binary significand, + 88 * there is limited value to considering test case inputs in + 89 * decimal form. The binary representations are all that is + 90 * important. + 91 * + 92 * If overflow/underflow occur and are trappable, the result should + 93 * be in the source format but scaled to the target precision. + 94 * These test cases are handled by both the basic tests to + 95 * ensure that the non-trap results are correct and again by + 96 * specific trappable overflow/underflow tests to ensure that the + 97 * scaled result rounded to target precision is returned in + 98 * the source format. + 99 * + 100 * Overflow/underflow behavior also means that result registers + 101 * must be sanitized and allocated in pairs for extended inputs; + 102 * results must store source format registers. Basic tests + 103 * for overflow/underflow only store the target precision, so + 104 * *Want needs to be coded accordingly. The trappable + ASMA Ver. 0.2.0 ieee-loadr.asm: Test IEEE Load Rounded 31 Aug 2016 19:54:48 Page 3 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 105 * overflow/underflow tests store the source format. + 106 * + 107 * Overflow/underflow test cases include inputs that overflow + 108 * the target precision and that result in a tiny in the target. + 109 * Rounding mode for all overflow/underflow testing is Round + 110 * to Nearest, Ties to Even (RNTE). + 111 * + 112 * Rounding test cases are needed as follows: + 113 * Exact results are represented (no rounding needed) + 114 * Ties are represented, both even (round down) and odd (round up) + 115 * False exacts are represented + 116 * Nearest value is toward zero + 117 * Nearest value is away from zero. + 118 * Each of the above must be represented in positive and negative. + 119 * + 120 * Because rounding decisions are based on the binary significand, + 121 * there is limited value to considering test case inputs in + 122 * decimal form. The binary representations are all that is + 123 * important. + 124 * + 125 * Three input test data sets are provided, one for long to short, one + 126 * for extended to short, and one for extended to long. We cannot use + 127 * the same extended inputs for long and short results because the + 128 * rounding points differ for the two result precisions. + 129 * + 130 * Also tests the following floating point support instructions + 131 * LOAD (Short) + 132 * LOAD (Long) + 133 * LFPC (Load Floating Point Control Register) + 134 * SRNMB (Set BFP Rounding Mode 3-bit) + 135 * STFPC (Store Floating Point Control Register) + 136 * STORE (Short) + 137 * STORE (Long) + 138 * + 139 MACRO + 140 PADCSECT &ENDLABL + 141 AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + 142 AGO .GOODPAD + 143 AIF (D'&ENDLABL).GOODPAD + 144 MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + 145 MNOTE *,'No CSECT padding performed' + 146 MEXIT + 147 .GOODPAD ANOP + 148 ORG &ENDLABL-1 + 149 MEXIT + 150 .NOPAD ANOP + 151 MNOTE *,'asma detected; no CSECT padding performed' + 152 MEND + 153 * + 0000000000000000 0000000000000C1F 154 BFPLDRND START 0 + 0000000000000000 0000000000000001 155 R0 EQU 0 + 0000000000000001 0000000000000001 156 R1 EQU 1 + ASMA Ver. 0.2.0 ieee-loadr.asm: Test IEEE Load Rounded 31 Aug 2016 19:54:48 Page 4 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 0000000000000002 0000000000000001 157 R2 EQU 2 + 0000000000000003 0000000000000001 158 R3 EQU 3 + 0000000000000004 0000000000000001 159 R4 EQU 4 + 0000000000000005 0000000000000001 160 R5 EQU 5 + 0000000000000006 0000000000000001 161 R6 EQU 6 + 0000000000000007 0000000000000001 162 R7 EQU 7 + 0000000000000008 0000000000000001 163 R8 EQU 8 + 0000000000000009 0000000000000001 164 R9 EQU 9 + 000000000000000A 0000000000000001 165 R10 EQU 10 + 000000000000000B 0000000000000001 166 R11 EQU 11 + 000000000000000C 0000000000000001 167 R12 EQU 12 + 000000000000000D 0000000000000001 168 R13 EQU 13 + 000000000000000E 0000000000000001 169 R14 EQU 14 + 000000000000000F 0000000000000001 170 R15 EQU 15 + 171 * + 172 * Floating Point Register equates to keep the cross reference clean + 173 * + 0000000000000000 0000000000000001 174 FPR0 EQU 0 + 0000000000000001 0000000000000001 175 FPR1 EQU 1 + 0000000000000002 0000000000000001 176 FPR2 EQU 2 + 0000000000000003 0000000000000001 177 FPR3 EQU 3 + 0000000000000004 0000000000000001 178 FPR4 EQU 4 + 0000000000000005 0000000000000001 179 FPR5 EQU 5 + 0000000000000006 0000000000000001 180 FPR6 EQU 6 + 0000000000000007 0000000000000001 181 FPR7 EQU 7 + 0000000000000008 0000000000000001 182 FPR8 EQU 8 + 0000000000000009 0000000000000001 183 FPR9 EQU 9 + 000000000000000A 0000000000000001 184 FPR10 EQU 10 + 000000000000000B 0000000000000001 185 FPR11 EQU 11 + 000000000000000C 0000000000000001 186 FPR12 EQU 12 + 000000000000000D 0000000000000001 187 FPR13 EQU 13 + 000000000000000E 0000000000000001 188 FPR14 EQU 14 + 000000000000000F 0000000000000001 189 FPR15 EQU 15 + 190 * +0000000000000000 0000000000000000 191 USING *,R15 + 192 * + 193 * Above works on real iron (R15=0 after sysclear) + 194 * and in z/CMS (R15 points to start of load module) + 195 * +0000000000000000 0000000000000000 000000000000008E 196 ORG BFPLDRND+X'8E' Program check interrution code +000000000000008E 0000 197 PCINTCD DS H + 198 * + 0000000000000150 0000000000000000 199 PCOLDPSW EQU BFPLDRND+X'150' z/Arch Program check old PSW + 200 * +0000000000000090 0000000000000090 00000000000001A0 201 ORG BFPLDRND+X'1A0' z/Arch Restart PSW +00000000000001A0 00000001 80000000 202 DC X'0000000180000000',AD(START) + 203 * +00000000000001B0 00000000000001B0 00000000000001D0 204 ORG BFPLDRND+X'1D0' z/Arch Program check old PSW +00000000000001D0 00000000 00000000 205 DC X'0000000000000000',AD(PROGCHK) + 206 * + 207 * Program check routine. If Data Exception, continue execution at + 208 * the instruction following the program check. Otherwise, hard wait. + ASMA Ver. 0.2.0 ieee-loadr.asm: Test IEEE Load Rounded 31 Aug 2016 19:54:48 Page 5 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 209 * No need to collect data. All interesting DXC stuff is captured + 210 * in the FPCR. + 211 * +00000000000001E0 00000000000001E0 0000000000000200 212 ORG BFPLDRND+X'200' +0000000000000200 213 PROGCHK DS 0H Program check occured... +0000000000000200 9507 F08F 000000000000008F 214 CLI PCINTCD+1,X'07' Data Exception? +0000000000000204 A774 0004 000000000000020C 215 JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) +0000000000000208 B2B2 F150 0000000000000150 216 LPSWE PCOLDPSW ..yes, resume program execution +000000000000020C 217 PCNOTDTA DS 0H +000000000000020C 12EE 218 LTR R14,R14 Return address provided? +000000000000020E 077E 219 BNZR R14 Yes, return to z/CMS test rig. +0000000000000210 B2B2 F280 0000000000000280 220 LPSWE HARDWAIT Not data exception, enter disabled wait + ASMA Ver. 0.2.0 ieee-loadr.asm: Test IEEE Load Rounded 31 Aug 2016 19:54:48 Page 6 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 222 *********************************************************************** + 223 * + 224 * Main program. Enable Advanced Floating Point, process test cases. + 225 * +0000000000000214 B600 F290 0000000000000290 226 START STCTL R0,R0,CTLR0 Store CR0 to enable AFP +0000000000000218 9604 F291 0000000000000291 227 OI CTLR0+1,X'04' Turn on AFP bit +000000000000021C B700 F290 0000000000000290 228 LCTL R0,R0,CTLR0 Reload updated CR0 + 229 * + 230 * Long Load Rounded to short tests + 231 * +0000000000000220 41A0 F300 0000000000000300 232 LA R10,LTOSBAS Long BFP test inputs +0000000000000224 4DD0 F390 0000000000000390 233 BAS R13,LEDBR Load rounded to short BFP +0000000000000228 41A0 F330 0000000000000330 234 LA R10,LTOSRM Long BFP inputs for rounding tests +000000000000022C 4DD0 F410 0000000000000410 235 BAS R13,LEDBRA Round to short BFP using rm options + 236 * + 237 * Extended Load Rounded to short tests + 238 * +0000000000000230 41A0 F310 0000000000000310 239 LA R10,XTOSBAS Point to extended BFP test inputs +0000000000000234 4DD0 F4E2 00000000000004E2 240 BAS R13,LEXBR Load rounded to short BFP +0000000000000238 41A0 F340 0000000000000340 241 LA R10,XTOSRM Extended BFP inputs for rounding tests +000000000000023C 4DD0 F566 0000000000000566 242 BAS R13,LEXBRA Round to short BFP using rm options + 243 * + 244 * Extended Load Rounded to short tests + 245 * +0000000000000240 41A0 F320 0000000000000320 246 LA R10,XTOLBAS Point to extended BFP test inputs +0000000000000244 4DD0 F638 0000000000000638 247 BAS R13,LDXBR Load rounded to long BFP +0000000000000248 41A0 F350 0000000000000350 248 LA R10,XTOLRM Extended BFP inputs for rounding tests +000000000000024C 4DD0 F6BC 00000000000006BC 249 BAS R13,LDXBRA Round to long BFP using rm options + 250 * + 251 * Trappable long to short tests + 252 * +0000000000000250 41A0 F360 0000000000000360 253 LA R10,LTOSOU Long BFP over/underflow test inputs +0000000000000254 4DD0 F3DA 00000000000003DA 254 BAS R13,LEDBROUT Load rounded to short BFP, trappable + 255 * + 256 * Trappable extended to short tests + 257 * +0000000000000258 41A0 F370 0000000000000370 258 LA R10,XTOSOU Extended BFP over/underflow test inputs +000000000000025C 4DD0 F52C 000000000000052C 259 BAS R13,LEXBROUT Load rounded to short BFP, trappable + 260 * + 261 * Trappable extended to long tests + 262 * +0000000000000260 41A0 F380 0000000000000380 263 LA R10,XTOLOU Extended BFP over/underflow test inputs +0000000000000264 4DD0 F682 0000000000000682 264 BAS R13,LDXBROUT Load rounded to long BFP, trappable + 265 * +0000000000000268 12EE 266 LTR R14,R14 Return address provided? +000000000000026A 077E 267 BNZR R14 ..Yes, return to z/CMS test rig. +000000000000026C B2B2 F270 0000000000000270 268 LPSWE WAITPSW ..No, load disabled wait PSW + 269 * +0000000000000270 270 DS 0D Ensure correct alignment for psw +0000000000000270 00020000 00000000 271 WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +0000000000000280 00020000 00000000 272 HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end + 273 * + ASMA Ver. 0.2.0 ieee-loadr.asm: Test IEEE Load Rounded 31 Aug 2016 19:54:48 Page 7 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000290 00000000 274 CTLR0 DS F +0000000000000294 00000000 275 FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +0000000000000298 F8000000 276 FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags + 277 * + 278 * Input values parameter list, four fullwords: + 279 * 1) Count, + 280 * 2) Address of inputs, + 281 * 3) Address to place results, and + 282 * 4) Address to place DXC/Flags/cc values. + 283 * +000000000000029C 000000000000029C 0000000000000300 284 ORG BFPLDRND+X'300' +0000000000000300 285 LTOSBAS DS 0F Inputs for long to short BFP tests +0000000000000300 0000000D 286 DC A(LTOSCT/8) +0000000000000304 00000798 287 DC A(LTOSIN) +0000000000000308 00001000 288 DC A(LTOSOUT) +000000000000030C 00001080 289 DC A(LTOSFLGS) + 290 * +0000000000000310 291 XTOSBAS DS 0F Inputs for extended to short BFP tests +0000000000000310 0000000D 292 DC A(XTOSCT/16) +0000000000000314 00000880 293 DC A(XTOSIN) +0000000000000318 00001900 294 DC A(XTOSOUT) +000000000000031C 00001980 295 DC A(XTOSFLGS) + 296 * +0000000000000320 297 XTOLBAS DS 0F Inputs for extended to long BFP tests +0000000000000320 0000000D 298 DC A(XTOLCT/16) +0000000000000324 00000A50 299 DC A(XTOLIN) +0000000000000328 00002200 300 DC A(XTOLOUT) +000000000000032C 00002300 301 DC A(XTOLFLGS) + 302 * +0000000000000330 303 LTOSRM DS 0F Inputs for long to short BFP rounding tests +0000000000000330 00000010 304 DC A(LTOSRMCT/8) +0000000000000334 00000800 305 DC A(LTOSINRM) +0000000000000338 00001100 306 DC A(LTOSRMO) +000000000000033C 00001500 307 DC A(LTOSRMOF) + 308 * +0000000000000340 309 XTOSRM DS 0F Inputs for extended to short BFP rounding tests +0000000000000340 00000010 310 DC A(XTOSRMCT/16) +0000000000000344 00000950 311 DC A(XTOSINRM) +0000000000000348 00001A00 312 DC A(XTOSRMO) +000000000000034C 00001E00 313 DC A(XTOSRMOF) + 314 * +0000000000000350 315 XTOLRM DS 0F Inputs for extended to long BFP rounding tests +0000000000000350 00000010 316 DC A(XTOLRMCT/16) +0000000000000354 00000B20 317 DC A(XTOLINRM) +0000000000000358 00002400 318 DC A(XTOLRMO) +000000000000035C 00002B00 319 DC A(XTOLRMOF) + 320 * +0000000000000360 321 LTOSOU DS 0F Inputs for long to short BFP rounding tests +0000000000000360 00000008 322 DC A(LTOSOUCT/8) +0000000000000364 000007C0 323 DC A(LTOSINOU) +0000000000000368 00003000 324 DC A(LTOSOUO) +000000000000036C 00003080 325 DC A(LTOSOUOF) + ASMA Ver. 0.2.0 ieee-loadr.asm: Test IEEE Load Rounded 31 Aug 2016 19:54:48 Page 8 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 326 * +0000000000000370 327 XTOSOU DS 0F Inputs for extended to short BFP rounding tests +0000000000000370 00000008 328 DC A(XTOSOUCT/16) +0000000000000374 000008D0 329 DC A(XTOSINOU) +0000000000000378 00003100 330 DC A(XTOSOUO) +000000000000037C 00003180 331 DC A(XTOSOUOF) + 332 * +0000000000000380 333 XTOLOU DS 0F Inputs for extended to long BFP rounding tests +0000000000000380 00000008 334 DC A(XTOLOUCT/16) +0000000000000384 00000AA0 335 DC A(XTOLINOU) +0000000000000388 00003200 336 DC A(XTOLOUO) +000000000000038C 00003280 337 DC A(XTOLOUOF) + ASMA Ver. 0.2.0 ieee-loadr.asm: Test IEEE Load Rounded 31 Aug 2016 19:54:48 Page 9 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 339 *********************************************************************** + 340 * + 341 * Round long BFP to short BFP. A pair of results is generated for each + 342 * input: one with all exceptions non-trappable, and the second with all + 343 * exceptions trappable. The FPCR contents are stored for each result. + 344 * + 345 *********************************************************************** + + +0000000000000390 9823 A000 0000000000000000 347 LEDBR LM R2,R3,0(R10) Get count and address of test input values +0000000000000394 9878 A008 0000000000000008 348 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000398 1222 349 LTR R2,R2 Any test cases? +000000000000039A 078D 350 BZR R13 ..No, return to caller +000000000000039C 0DC0 351 BASR R12,0 Set top of loop + 352 * +000000000000039E B375 0010 353 LZDR FPR1 Zero FRP1 to clear any residual +00000000000003A2 6800 3000 0000000000000000 354 LD FPR0,0(,R3) Get long BFP test value +00000000000003A6 B29D F294 0000000000000294 355 LFPC FPCREGNT Set exceptions non-trappable +00000000000003AA B344 0010 356 LEDBR FPR1,FPR0 Cvt long in FPR0 to short in FPR1 +00000000000003AE 7010 7000 0000000000000000 357 STE FPR1,0(,R7) Store short BFP result +00000000000003B2 B29C 8000 0000000000000000 358 STFPC 0(R8) Store resulting FPCR flags and DXC + 359 * +00000000000003B6 B375 0010 360 LZDR FPR1 Zero FRP1 to clear any residual +00000000000003BA B29D F298 0000000000000298 361 LFPC FPCREGTR Set exceptions trappable +00000000000003BE B344 0010 362 LEDBR FPR1,FPR0 Cvt long in FPR0 to short in FPR1 +00000000000003C2 7010 7004 0000000000000004 363 STE FPR1,4(,R7) Store short BFP result +00000000000003C6 B29C 8004 0000000000000004 364 STFPC 4(R8) Store resulting FPCR flags and DXC + 365 * +00000000000003CA 4130 3008 0000000000000008 366 LA R3,8(,R3) Point to next input value +00000000000003CE 4170 7008 0000000000000008 367 LA R7,8(,R7) Point to next result pair +00000000000003D2 4180 8008 0000000000000008 368 LA R8,8(,R8) Point to next FPCR result area +00000000000003D6 062C 369 BCTR R2,R12 Convert next input value. +00000000000003D8 07FD 370 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-loadr.asm: Test IEEE Load Rounded 31 Aug 2016 19:54:48 Page 10 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 372 *********************************************************************** + 373 * + 374 * Round long BFP to short BFP. Inputs are expected to generate + 375 * overflow or underflow exceptions, all of which are trappable. This + 376 * means a scaled result should be generated rounded to the target + 377 * precision but returned in the source precision. The FPCR contents + 378 * are stored for each result. + 379 * + 380 *********************************************************************** + + +00000000000003DA 9823 A000 0000000000000000 382 LEDBROUT LM R2,R3,0(R10) Get count and address of test input values +00000000000003DE 9878 A008 0000000000000008 383 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000003E2 1222 384 LTR R2,R2 Any test cases? +00000000000003E4 078D 385 BZR R13 ..No, return to caller +00000000000003E6 0DC0 386 BASR R12,0 Set top of loop + 387 * +00000000000003E8 B375 0010 388 LZDR FPR1 Zero FRP1 to clear any residual +00000000000003EC 6800 3000 0000000000000000 389 LD FPR0,0(,R3) Get long BFP test value +00000000000003F0 B29D F298 0000000000000298 390 LFPC FPCREGTR Set exceptions trappable +00000000000003F4 B344 0010 391 LEDBR FPR1,FPR0 Cvt long in FPR0 into short in FPR1 +00000000000003F8 6010 7000 0000000000000000 392 STD FPR1,0(,R7) Store long scaled BFP trapped result +00000000000003FC B29C 8000 0000000000000000 393 STFPC 0(R8) Store resulting FPCR flags and DXC + 394 * +0000000000000400 4130 3008 0000000000000008 395 LA R3,8(,R3) Point to next input value +0000000000000404 4170 7008 0000000000000008 396 LA R7,8(,R7) Point to next long trapped result value +0000000000000408 4180 8004 0000000000000004 397 LA R8,4(,R8) Point to next FPCR result area +000000000000040C 062C 398 BCTR R2,R12 Convert next input value. +000000000000040E 07FD 399 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-loadr.asm: Test IEEE Load Rounded 31 Aug 2016 19:54:48 Page 11 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 401 *********************************************************************** + 402 * + 403 * Convert long BFP to rounded short BFP using each possible rounding + 404 * mode. Ten test results are generated for each input. A 48-byte test + 405 * result section is used to keep results sets aligned on a quad-double + 406 * word. + 407 * + 408 * The first four tests use rounding modes specified in the FPCR with + 409 * the IEEE Inexact exception supressed. SRNM (2-bit) is used for + 410 * the first two FPCR-controlled tests and SRNMB (3-bit) is used for + 411 * the last two To get full coverage of that instruction pair. + 412 * + 413 * The next six results use instruction-specified rounding modes. + 414 * + 415 * The default rounding mode (0 for RNTE) is not tested in this + 416 * section; prior tests used the default rounding mode. RNTE is tested + 417 * explicitly as a rounding mode in this section. + 418 * + 419 *********************************************************************** + + +0000000000000410 9823 A000 0000000000000000 421 LEDBRA LM R2,R3,0(R10) Get count and address of test input values +0000000000000414 9878 A008 0000000000000008 422 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000418 1222 423 LTR R2,R2 Any test cases? +000000000000041A 078D 424 BZR R13 ..No, return to caller +000000000000041C 0DC0 425 BASR R12,0 Set top of loop + 426 * +000000000000041E 6800 3000 0000000000000000 427 LD FPR0,0(,R3) Get long BFP test value + 428 * + 429 * Test cases using rounding mode specified in the FPCR + 430 * +0000000000000422 B29D F294 0000000000000294 431 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000426 B299 0001 0000000000000001 432 SRNM 1 SET FPCR to RZ, Round towards zero. +000000000000042A B344 0410 433 LEDBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, mask inexact +000000000000042E 7010 7000 0000000000000000 434 STE FPR1,0*4(,R7) Store shortened rounded BFP result +0000000000000432 B29C 8000 0000000000000000 435 STFPC 0(R8) Store resulting FPCRflags and DXC + 436 * +0000000000000436 B29D F294 0000000000000294 437 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000043A B299 0002 0000000000000002 438 SRNM 2 SET FPCR to RP, Round to +infinity +000000000000043E B344 0410 439 LEDBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, mask inexact +0000000000000442 7010 7004 0000000000000004 440 STE FPR1,1*4(,R7) Store shortened rounded BFP result +0000000000000446 B29C 8004 0000000000000004 441 STFPC 1*4(R8) Store resulting FPCR flags and DXC + 442 * +000000000000044A B29D F294 0000000000000294 443 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000044E B2B8 0003 0000000000000003 444 SRNMB 3 SET FPCR to RM, Round to -infinity +0000000000000452 B344 0410 445 LEDBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, mask inexact +0000000000000456 7010 7008 0000000000000008 446 STE FPR1,2*4(,R7) Store shortened rounded BFP result +000000000000045A B29C 8008 0000000000000008 447 STFPC 2*4(R8) Store resulting FPCR flags and DXC + 448 * +000000000000045E B29D F294 0000000000000294 449 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000462 B2B8 0007 0000000000000007 450 SRNMB 7 RFS, Round Prepare for Shorter Precision +0000000000000466 B344 0410 451 LEDBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, mask inexact + ASMA Ver. 0.2.0 ieee-loadr.asm: Test IEEE Load Rounded 31 Aug 2016 19:54:48 Page 12 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +000000000000046A 7010 700C 000000000000000C 452 STE FPR1,3*4(,R7) Store shortened rounded BFP result +000000000000046E B29C 800C 000000000000000C 453 STFPC 3*4(R8) Store resulting FPCR flags and DXC + 454 * + 455 * Test cases using rounding mode specified in the instruction M3 field + 456 * +0000000000000472 B29D F294 0000000000000294 457 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000476 B344 1010 458 LEDBRA FPR1,1,FPR0,B'0000' RNTA, to nearest, ties away +000000000000047A 7010 7010 0000000000000010 459 STE FPR1,4*4(,R7) Store shortened rounded BFP result +000000000000047E B29C 8010 0000000000000010 460 STFPC 4*4(R8) Store resulting FPCR flags and DXC + 461 * +0000000000000482 B29D F294 0000000000000294 462 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000486 B344 3010 463 LEDBRA FPR1,3,FPR0,B'0000' RFS, prepare for shorter precision +000000000000048A 7010 7014 0000000000000014 464 STE FPR1,5*4(,R7) Store shortened rounded BFP result +000000000000048E B29C 8014 0000000000000014 465 STFPC 5*4(R8) Store resulting FPCR flags and DXC + 466 * +0000000000000492 B29D F294 0000000000000294 467 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000496 B344 4010 468 LEDBRA FPR1,4,FPR0,B'0000' RNTE, to nearest, ties to even +000000000000049A 7010 7018 0000000000000018 469 STE FPR1,6*4(,R7) Store shortened rounded BFP result +000000000000049E B29C 8018 0000000000000018 470 STFPC 6*4(R8) Store resulting FPCR flags and DXC + 471 * +00000000000004A2 B29D F294 0000000000000294 472 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000004A6 B344 5010 473 LEDBRA FPR1,5,FPR0,B'0000' RZ, toward zero +00000000000004AA 7010 701C 000000000000001C 474 STE FPR1,7*4(,R7) Store shortened rounded BFP result +00000000000004AE B29C 801C 000000000000001C 475 STFPC 7*4(R8) Store resulting FPCR flags and DXC + 476 * +00000000000004B2 B29D F294 0000000000000294 477 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000004B6 B344 6010 478 LEDBRA FPR1,6,FPR0,B'0000' RP, to +inf +00000000000004BA 7010 7020 0000000000000020 479 STE FPR1,8*4(,R7) Store shortened rounded BFP result +00000000000004BE B29C 8020 0000000000000020 480 STFPC 8*4(R8) Store resulting FPCR flags and DXC + 481 * +00000000000004C2 B29D F294 0000000000000294 482 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000004C6 B344 7010 483 LEDBRA FPR1,7,FPR0,B'0000' RM, to -inf +00000000000004CA 7010 7024 0000000000000024 484 STE FPR1,9*4(,R7) Store shortened rounded BFP result +00000000000004CE B29C 8024 0000000000000024 485 STFPC 9*4(R8) Store resulting FPCR flags and DXC + 486 * +00000000000004D2 4130 3008 0000000000000008 487 LA R3,8(,R3) Point to next input value +00000000000004D6 4170 7030 0000000000000030 488 LA R7,12*4(,R7) Point to next short BFP result pair +00000000000004DA 4180 8030 0000000000000030 489 LA R8,12*4(,R8) Point to next FPCR result area +00000000000004DE 062C 490 BCTR R2,R12 Convert next input value. +00000000000004E0 07FD 491 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-loadr.asm: Test IEEE Load Rounded 31 Aug 2016 19:54:48 Page 13 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 493 *********************************************************************** + 494 * + 495 * Round extended BFP to short BFP. A pair of results is genearted for + 496 * each input: one with all exceptions non-trappable, and the second + 497 * with all exceptions trappable. The FPCR contents are stored for + 498 * each result. + 499 * + 500 *********************************************************************** + + +00000000000004E2 9823 A000 0000000000000000 502 LEXBR LM R2,R3,0(R10) Get count and address of test input values +00000000000004E6 9878 A008 0000000000000008 503 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000004EA 1222 504 LTR R2,R2 Any test cases? +00000000000004EC 078D 505 BZR R13 ..No, return to caller +00000000000004EE 0DC0 506 BASR R12,0 Set top of loop + 507 * +00000000000004F0 6800 3000 0000000000000000 508 LD FPR0,0(,R3) Get extended BFP test value part 1 +00000000000004F4 6820 3008 0000000000000008 509 LD R2,8(,R3) Get extended BFP test value part 2 +00000000000004F8 B29D F294 0000000000000294 510 LFPC FPCREGNT Set exceptions non-trappable +00000000000004FC B346 0010 511 LEXBR FPR1,FPR0 Cvt extended in FPR0-2 to short in FPR1 +0000000000000500 7010 7000 0000000000000000 512 STE R1,0(,R7) Store short BFP result +0000000000000504 B29C 8000 0000000000000000 513 STFPC 0(R8) Store resulting FPCR flags and DXC + 514 * +0000000000000508 B29D F298 0000000000000298 515 LFPC FPCREGTR Set exceptions trappable +000000000000050C B375 0010 516 LZDR FPR1 Eliminate any residual results +0000000000000510 B346 0010 517 LEXBR FPR1,FPR0 Cvt extended in FPR0-2 to short in FPR1 +0000000000000514 7010 7004 0000000000000004 518 STE FPR1,4(,R7) Store short BFP result +0000000000000518 B29C 8004 0000000000000004 519 STFPC 4(R8) Store resulting FPCR flags and DXC + 520 * +000000000000051C 4130 3010 0000000000000010 521 LA R3,16(,R3) Point to next input value +0000000000000520 4170 7008 0000000000000008 522 LA R7,8(,R7) Point to next long rounded value pair +0000000000000524 4180 8008 0000000000000008 523 LA R8,8(,R8) Point to next FPCR result area +0000000000000528 062C 524 BCTR R2,R12 Convert next input value. +000000000000052A 07FD 525 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-loadr.asm: Test IEEE Load Rounded 31 Aug 2016 19:54:48 Page 14 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 527 *********************************************************************** + 528 * + 529 * Round extended BFP to short BFP. Inputs are expected to generate + 530 * overflow or underflow exceptions, all of which are trappable. This + 531 * means a scaled result should be generated rounded to the target + 532 * precision but returned in the source precision. The FPCR contents + 533 * are stored for each result. + 534 * + 535 *********************************************************************** + + +000000000000052C 9823 A000 0000000000000000 537 LEXBROUT LM R2,R3,0(R10) Get count and address of test input values +0000000000000530 9878 A008 0000000000000008 538 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000534 1222 539 LTR R2,R2 Any test cases? +0000000000000536 078D 540 BZR R13 ..No, return to caller +0000000000000538 0DC0 541 BASR R12,0 Set top of loop + 542 * +000000000000053A 6800 3000 0000000000000000 543 LD FPR0,0(,R3) Get extended BFP test value part 1 +000000000000053E 6820 3008 0000000000000008 544 LD R2,8(,R3) Get extended BFP test value part 2 +0000000000000542 B29D F298 0000000000000298 545 LFPC FPCREGTR Set exceptions trappable +0000000000000546 B346 0010 546 LEXBR FPR1,FPR0 Cvt float in FPR0-2 to scaled in FPR1-3 +000000000000054A 6010 7000 0000000000000000 547 STD FPR1,0(,R7) Store scaled extended BFP result part 1 +000000000000054E 6030 7008 0000000000000008 548 STD FPR3,8(,R7) Store scaled extended BFP result part 2 +0000000000000552 B29C 8000 0000000000000000 549 STFPC 0(R8) Store resulting FPCR flags and DXC + 550 * +0000000000000556 4130 3010 0000000000000010 551 LA R3,16(,R3) Point to next input value +000000000000055A 4170 7010 0000000000000010 552 LA R7,16(,R7) Point to next extended trapped result +000000000000055E 4180 8004 0000000000000004 553 LA R8,4(,R8) Point to next FPCR result area +0000000000000562 062C 554 BCTR R2,R12 Convert next input value. +0000000000000564 07FD 555 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-loadr.asm: Test IEEE Load Rounded 31 Aug 2016 19:54:48 Page 15 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 557 *********************************************************************** + 558 * + 559 * Convert long BFP to integers using each possible rounding mode. + 560 * Ten test results are generated for each input. A 48-byte test result + 561 * section is used to keep results sets aligned on a quad-double word. + 562 * + 563 * The first four tests use rounding modes specified in the FPCR with + 564 * the IEEE Inexact exception supressed. SRNM (2-bit) is used for + 565 * the first two FPCR-controlled tests and SRNMB (3-bit) is used for + 566 * the last two To get full coverage of that instruction pair. + 567 * + 568 * The next six results use instruction-specified rounding modes. + 569 * + 570 * The default rounding mode (0 for RNTE) is not tested in this + 571 * section; prior tests used the default rounding mode. RNTE is tested + 572 * explicitly as a rounding mode in this section. + 573 * + 574 *********************************************************************** + + +0000000000000566 9823 A000 0000000000000000 576 LEXBRA LM R2,R3,0(R10) Get count and address of test input values +000000000000056A 9878 A008 0000000000000008 577 LM R7,R8,8(R10) Get address of result area and flag area. +000000000000056E 1222 578 LTR R2,R2 Any test cases? +0000000000000570 078D 579 BZR R13 ..No, return to caller +0000000000000572 0DC0 580 BASR R12,0 Set top of loop + 581 * +0000000000000574 6800 3000 0000000000000000 582 LD FPR0,0(,R3) Get long BFP test value + 583 * + 584 * Test cases using rounding mode specified in the FPCR + 585 * +0000000000000578 B29D F294 0000000000000294 586 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000057C B299 0001 0000000000000001 587 SRNM 1 SET FPCR to RZ, Round towards zero. +0000000000000580 B346 0410 588 LEXBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, mask inexact +0000000000000584 6010 7000 0000000000000000 589 STD FPR1,0*4(,R7) Store shortened rounded BFP result +0000000000000588 B29C 8000 0000000000000000 590 STFPC 0(R8) Store resulting FPCR flags and DXC + 591 * +000000000000058C B29D F294 0000000000000294 592 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000590 B299 0002 0000000000000002 593 SRNM 2 SET FPCR to RP, Round to +infinity +0000000000000594 B346 0410 594 LEXBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, mask inexact +0000000000000598 6010 7004 0000000000000004 595 STD FPR1,1*4(,R7) Store shortened rounded BFP result +000000000000059C B29C 8004 0000000000000004 596 STFPC 1*4(R8) Store resulting FPCR flags and DXC + 597 * +00000000000005A0 B29D F294 0000000000000294 598 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000005A4 B2B8 0003 0000000000000003 599 SRNMB 3 SET FPCR to RM, Round to -infinity +00000000000005A8 B346 0410 600 LEXBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, mask inexact +00000000000005AC 6010 7008 0000000000000008 601 STD FPR1,2*4(,R7) Store shortened rounded BFP result +00000000000005B0 B29C 8008 0000000000000008 602 STFPC 2*4(R8) Store resulting FPCR flags and DXC + 603 * +00000000000005B4 B29D F294 0000000000000294 604 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000005B8 B2B8 0007 0000000000000007 605 SRNMB 7 RFS, Round Prepare for Shorter Precision +00000000000005BC B346 0410 606 LEXBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, mask inexact +00000000000005C0 6010 700C 000000000000000C 607 STD FPR1,3*4(,R7) Store shortened rounded BFP result + ASMA Ver. 0.2.0 ieee-loadr.asm: Test IEEE Load Rounded 31 Aug 2016 19:54:48 Page 16 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000005C4 B29C 800C 000000000000000C 608 STFPC 3*4(R8) Store resulting FPCR flags and DXC + 609 * + 610 * Test cases using rounding mode specified in the instruction M3 field + 611 * +00000000000005C8 B29D F294 0000000000000294 612 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000005CC B346 1010 613 LEXBRA FPR1,1,FPR0,B'0000' RNTA, to nearest, ties away +00000000000005D0 6010 7010 0000000000000010 614 STD FPR1,4*4(,R7) Store shortened rounded BFP result +00000000000005D4 B29C 8010 0000000000000010 615 STFPC 4*4(R8) Store resulting FPCR flags and DXC + 616 * +00000000000005D8 B29D F294 0000000000000294 617 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000005DC B346 3010 618 LEXBRA FPR1,3,FPR0,B'0000' RFS, prepare for shorter precision +00000000000005E0 6010 7014 0000000000000014 619 STD FPR1,5*4(,R7) Store shortened rounded BFP result +00000000000005E4 B29C 8014 0000000000000014 620 STFPC 5*4(R8) Store resulting FPCR flags and DXC + 621 * +00000000000005E8 B29D F294 0000000000000294 622 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000005EC B346 4010 623 LEXBRA FPR1,4,FPR0,B'0000' RNTE, to nearest, ties to even +00000000000005F0 6010 7018 0000000000000018 624 STD FPR1,6*4(,R7) Store shortened rounded BFP result +00000000000005F4 B29C 8018 0000000000000018 625 STFPC 6*4(R8) Store resulting FPCR flags and DXC + 626 * +00000000000005F8 B29D F294 0000000000000294 627 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000005FC B346 5010 628 LEXBRA FPR1,5,FPR0,B'0000' RZ, toward zero +0000000000000600 6010 701C 000000000000001C 629 STD FPR1,7*4(,R7) Store shortened rounded BFP result +0000000000000604 B29C 801C 000000000000001C 630 STFPC 7*4(R8) Store resulting FPCR flags and DXC + 631 * +0000000000000608 B29D F294 0000000000000294 632 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000060C B346 6010 633 LEXBRA FPR1,6,FPR0,B'0000' RP, to +inf +0000000000000610 6010 7020 0000000000000020 634 STD FPR1,8*4(,R7) Store shortened rounded BFP result +0000000000000614 B29C 8020 0000000000000020 635 STFPC 8*4(R8) Store resulting FPCR flags and DXC + 636 * +0000000000000618 B29D F294 0000000000000294 637 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000061C B346 7010 638 LEXBRA FPR1,7,FPR0,B'0000' RM, to -inf +0000000000000620 6010 7024 0000000000000024 639 STD FPR1,9*4(,R7) Store shortened rounded BFP result +0000000000000624 B29C 8024 0000000000000024 640 STFPC 9*4(R8) Store resulting FPCR flags and DXC + 641 * +0000000000000628 4130 3010 0000000000000010 642 LA R3,16(,R3) Point to next input value +000000000000062C 4170 7030 0000000000000030 643 LA R7,12*4(,R7) Point to next long BFP converted values +0000000000000630 4180 8030 0000000000000030 644 LA R8,12*4(,R8) Point to next FPCR/CC result area +0000000000000634 062C 645 BCTR R2,R12 Convert next input value. +0000000000000636 07FD 646 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-loadr.asm: Test IEEE Load Rounded 31 Aug 2016 19:54:48 Page 17 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 648 *********************************************************************** + 649 * + 650 * Round extended BFP to long BFP. A pair of results is generated for + 651 * each input: one with all exceptions non-trappable, and the second + 652 * with all exceptions trappable. The FPCR contents are stored for + 653 * each result. + 654 * + 655 *********************************************************************** + + +0000000000000638 9823 A000 0000000000000000 657 LDXBR LM R2,R3,0(R10) Get count and address of test input values +000000000000063C 9878 A008 0000000000000008 658 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000640 1222 659 LTR R2,R2 Any test cases? +0000000000000642 078D 660 BZR R13 ..No, return to caller +0000000000000644 0DC0 661 BASR R12,0 Set top of loop + 662 * +0000000000000646 6800 3000 0000000000000000 663 LD FPR0,0(,R3) Get extended BFP test value part 1 +000000000000064A 6820 3008 0000000000000008 664 LD R2,8(,R3) Get extended BFP test value part 1 +000000000000064E B29D F294 0000000000000294 665 LFPC FPCREGNT Set exceptions non-trappable +0000000000000652 B345 0010 666 LDXBR FPR1,FPR0 Round extended in FPR0-2 to long in FPR1 +0000000000000656 6010 7000 0000000000000000 667 STD FPR1,0(,R7) Store shortened rounded BFP result +000000000000065A B29C 8000 0000000000000000 668 STFPC 0(R8) Store resulting FPCR flags and DXC + 669 * +000000000000065E B29D F298 0000000000000298 670 LFPC FPCREGTR Set exceptions trappable +0000000000000662 B376 0010 671 LZXR FPR1 Eliminate any residual results +0000000000000666 B345 0010 672 LDXBR FPR1,FPR0 Round extended in FPR0-2 to long in FPR1 +000000000000066A 6010 7008 0000000000000008 673 STD FPR1,8(,R7) Store shortened rounded BFP result +000000000000066E B29C 8004 0000000000000004 674 STFPC 4(R8) Store resulting FPCR flags and DXC + 675 * +0000000000000672 4130 3010 0000000000000010 676 LA R3,16(,R3) Point to next extended BFP input value +0000000000000676 4170 7010 0000000000000010 677 LA R7,16(,R7) Point to next long BFP rounded value pair +000000000000067A 4180 8008 0000000000000008 678 LA R8,8(,R8) Point to next FPCR result area +000000000000067E 062C 679 BCTR R2,R12 Convert next input value. +0000000000000680 07FD 680 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-loadr.asm: Test IEEE Load Rounded 31 Aug 2016 19:54:48 Page 18 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 682 *********************************************************************** + 683 * + 684 * Round extended BFP to long BFP. Inputs are expected to generate + 685 * overflow or underflow exceptions, all of which are trappable. This + 686 * means a scaled result should be generated rounded to the target + 687 * precision but returned in the source precision. The FPCR contents + 688 * are stored for each result. + 689 * + 690 *********************************************************************** + + +0000000000000682 9823 A000 0000000000000000 692 LDXBROUT LM R2,R3,0(R10) Get count and address of test input values +0000000000000686 9878 A008 0000000000000008 693 LM R7,R8,8(R10) Get address of result area and flag area. +000000000000068A 1222 694 LTR R2,R2 Any test cases? +000000000000068C 078D 695 BZR R13 ..No, return to caller +000000000000068E 0DC0 696 BASR R12,0 Set top of loop + 697 * +0000000000000690 6800 3000 0000000000000000 698 LD FPR0,0(,R3) Get extended BFP test value part 1 +0000000000000694 6820 3008 0000000000000008 699 LD R2,8(,R3) Get extended BFP test value part 1 +0000000000000698 B29D F298 0000000000000298 700 LFPC FPCREGTR Set exceptions trappable +000000000000069C B345 0010 701 LDXBR FPR1,FPR0 Round ext'd in FPR0-2 to scaled in FPR1-3 +00000000000006A0 6010 7000 0000000000000000 702 STD FPR1,0(,R7) Store scaled extended BFP result part 1 +00000000000006A4 6030 7008 0000000000000008 703 STD FPR3,8(,R7) Store scaled extended BFP result part 2 +00000000000006A8 B29C 8000 0000000000000000 704 STFPC 0(R8) Store resulting FPCR flags and DXC + 705 * +00000000000006AC 4130 3010 0000000000000010 706 LA R3,16(,R3) Point to next extended BFP input value +00000000000006B0 4170 7010 0000000000000010 707 LA R7,16(,R7) Point to next long BFP rounded value pair +00000000000006B4 4180 8004 0000000000000004 708 LA R8,4(,R8) Point to next FPCR result area +00000000000006B8 062C 709 BCTR R2,R12 Convert next input value. +00000000000006BA 07FD 710 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-loadr.asm: Test IEEE Load Rounded 31 Aug 2016 19:54:48 Page 19 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 712 *********************************************************************** + 713 * + 714 * Convert extended BFP to integers using each possible rounding mode. + 715 * Ten test results are generated for each input. A 48-byte test result + 716 * section is used to keep results sets aligned on a quad-double word. + 717 * + 718 * The first four tests use rounding modes specified in the FPCR with + 719 * the IEEE Inexact exception supressed. SRNM (2-bit) is used for + 720 * the first two FPCR-controlled tests and SRNMB (3-bit) is used for + 721 * the last two To get full coverage of that instruction pair. + 722 * + 723 * The next six results use instruction-specified rounding modes. + 724 * + 725 * The default rounding mode (0 for RNTE) is not tested in this + 726 * section; `prior tests used the default rounding mode. RNTE is tested + 727 * explicitly as a rounding mode in this section. + 728 * + 729 *********************************************************************** + + +00000000000006BC 9823 A000 0000000000000000 731 LDXBRA LM R2,R3,0(R10) Get count and address of test input values +00000000000006C0 9878 A008 0000000000000008 732 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000006C4 1222 733 LTR R2,R2 Any test cases? +00000000000006C6 078D 734 BZR R13 ..No, return to caller +00000000000006C8 0DC0 735 BASR R12,0 Set top of loop + 736 * +00000000000006CA 6800 3000 0000000000000000 737 LD FPR0,0(,R3) Get extended BFP test value part 1 +00000000000006CE 6820 3008 0000000000000008 738 LD R2,8(,R3) Get extended BFP test value part 2 + 739 * + 740 * Test cases using rounding mode specified in the FPCR + 741 * +00000000000006D2 B29D F294 0000000000000294 742 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000006D6 B299 0001 0000000000000001 743 SRNM 1 SET FPCR to RZ, Round towards zero. +00000000000006DA B345 0410 744 LDXBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, mask inexact +00000000000006DE 6010 7000 0000000000000000 745 STD FPR1,0*8(,R7) Store shortened rounded BFP result +00000000000006E2 B29C 8000 0000000000000000 746 STFPC 0(R8) Store resulting FPCR flags and DXC + 747 * +00000000000006E6 B29D F294 0000000000000294 748 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000006EA B299 0002 0000000000000002 749 SRNM 2 SET FPCR to RP, Round to +infinity +00000000000006EE B345 0410 750 LDXBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, mask inexact +00000000000006F2 6010 7008 0000000000000008 751 STD FPR1,1*8(,R7) Store shortened rounded BFP result +00000000000006F6 B29C 8004 0000000000000004 752 STFPC 1*4(R8) Store resulting FPCR flags and DXC + 753 * +00000000000006FA B29D F294 0000000000000294 754 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000006FE B2B8 0003 0000000000000003 755 SRNMB 3 SET FPCR to RM, Round to -infinity +0000000000000702 B345 0410 756 LDXBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, mask inexact +0000000000000706 6010 7010 0000000000000010 757 STD FPR1,2*8(,R7) Store shortened rounded BFP result +000000000000070A B29C 8008 0000000000000008 758 STFPC 2*4(R8) Store resulting FPCR flags and DXC + 759 * +000000000000070E B29D F294 0000000000000294 760 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000712 B2B8 0007 0000000000000007 761 SRNMB 7 RFS, Round Prepare for Shorter Precision +0000000000000716 B345 0410 762 LDXBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, mask inexact + ASMA Ver. 0.2.0 ieee-loadr.asm: Test IEEE Load Rounded 31 Aug 2016 19:54:48 Page 20 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +000000000000071A 6010 7018 0000000000000018 763 STD FPR1,3*8(,R7) Store shortened rounded BFP result +000000000000071E B29C 800C 000000000000000C 764 STFPC 3*4(R8) Store resulting FPCR flags and DXC + 765 * +0000000000000722 B29D F294 0000000000000294 766 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000726 B345 1010 767 LDXBRA FPR1,1,FPR0,B'0000' RNTA, to nearest, ties away +000000000000072A 6010 7020 0000000000000020 768 STD FPR1,4*8(,R7) Store shortened rounded BFP result +000000000000072E B29C 8010 0000000000000010 769 STFPC 4*4(R8) Store resulting FPCR flags and DXC + 770 * +0000000000000732 B29D F294 0000000000000294 771 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000736 B345 3010 772 LDXBRA FPR1,3,FPR0,B'0000' RFS, prepare for shorter precision +000000000000073A 6010 7028 0000000000000028 773 STD FPR1,5*8(,R7) Store shortened rounded BFP result +000000000000073E B29C 8014 0000000000000014 774 STFPC 5*4(R8) Store resulting FPCR flags and DXC + 775 * +0000000000000742 B29D F294 0000000000000294 776 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000746 B345 4010 777 LDXBRA FPR1,4,FPR0,B'0000' RNTE, to nearest, ties to even +000000000000074A 6010 7030 0000000000000030 778 STD FPR1,6*8(,R7) Store shortened rounded BFP result +000000000000074E B29C 8018 0000000000000018 779 STFPC 6*4(R8) Store resulting FPCR flags and DXC + 780 * +0000000000000752 B29D F294 0000000000000294 781 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000756 B345 5010 782 LDXBRA FPR1,5,FPR0,B'0000' RZ, toward zero +000000000000075A 6010 7038 0000000000000038 783 STD FPR1,7*8(,R7) Store shortened rounded BFP result +000000000000075E B29C 801C 000000000000001C 784 STFPC 7*4(R8) Store resulting FPCR flags and DXC + 785 * +0000000000000762 B29D F294 0000000000000294 786 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000766 B345 6010 787 LDXBRA FPR1,6,FPR0,B'0000' RP, to +inf +000000000000076A 6010 7040 0000000000000040 788 STD FPR1,8*8(,R7) Store shortened rounded BFP result +000000000000076E B29C 8020 0000000000000020 789 STFPC 8*4(R8) Store resulting FPCR flags and DXC + 790 * +0000000000000772 B29D F294 0000000000000294 791 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000776 B345 7010 792 LDXBRA FPR1,7,FPR0,B'0000' RM, to -inf +000000000000077A 6010 7048 0000000000000048 793 STD FPR1,9*8(,R7) Store shortened rounded BFP result +000000000000077E B29C 8024 0000000000000024 794 STFPC 9*4(R8) Store resulting FPCR flags and DXC + 795 * +0000000000000782 4130 3010 0000000000000010 796 LA R3,16(,R3) Point to next input value +0000000000000786 4170 7050 0000000000000050 797 LA R7,10*8(,R7) Point to next long BFP rounded result +000000000000078A 4180 8030 0000000000000030 798 LA R8,12*4(,R8) Point to next FPCR result area +000000000000078E 062C 799 BCTR R2,R12 Convert next input value. +0000000000000790 07FD 800 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-loadr.asm: Test IEEE Load Rounded 31 Aug 2016 19:54:48 Page 21 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 802 *********************************************************************** + 803 * + 804 * BFP inputs. One set of longs and two sets of extendeds are included. + 805 * Each set includes input values for basic exception testing and input + 806 * values for exhaustive rounding mode testing. One set of extended + 807 * inputs is used to generate short results, and the other is used to + 808 * generate long results. The same set cannot be used for both long + 809 * and short because the rounding points are different. + 810 * + 811 * We can cheat and use the same decimal values for long to short and + 812 * and extended to short because the result has the same number of + 813 * bits and the rounding uses the same number of bits in the pre- + 814 * rounded result. + 815 * + 816 *********************************************************************** + + + 818 * + 819 * Long to short basic tests, which tests trappable results, NaN + 820 * propagation, and basic functionality. The second part of this list + 821 * is used for testing trappable results. + 822 * +0000000000000798 823 LTOSIN DS 0D Inputs for long to short BFP basic tests +0000000000000798 00000000 00000000 824 DC X'0000000000000000' +0 +00000000000007A0 3FF80000 00000000 825 DC X'3FF8000000000000' +1.5 +00000000000007A8 BFF80000 00000000 826 DC X'BFF8000000000000' -1.5 +00000000000007B0 7FF01000 00000000 827 DC X'7FF0100000000000' SNaN +00000000000007B8 7FF81100 00000000 828 DC X'7FF8110000000000' QNaN + 829 * See rounding tests below for details on the following four +00000000000007C0 830 LTOSINOU DS 0D start of under/overflow tests +00000000000007C0 47EFFFFF FFFFFFFF 831 DC X'47EFFFFFFFFFFFFF' Positive oveflow test +00000000000007C8 C7EFFFFF FFFFFFFF 832 DC X'C7EFFFFFFFFFFFFF' Negative oveflow test +00000000000007D0 47FFFFFF EFFFFFFF 833 DC X'47FFFFFFEFFFFFFF' Positive oveflow prec. test +00000000000007D8 C7FFFFFF EFFFFFFF 834 DC X'C7FFFFFFEFFFFFFF' Negative oveflow prec. test +00000000000007E0 36900000 00000000 835 DC X'3690000000000000' Positive magnitude underflow +00000000000007E8 B6900000 00000000 836 DC X'B690000000000000' Negative magnitude underflow +00000000000007F0 47F00000 00000000 837 DC X'47F0000000000000' Positive magnitude overflow +00000000000007F8 C7F00000 00000000 838 DC X'C7F0000000000000' Negative magnitude overflow + 839 * + 0000000000000068 0000000000000001 840 LTOSCT EQU *-LTOSIN Count of long BFP in list * 8 + 0000000000000040 0000000000000001 841 LTOSOUCT EQU *-LTOSINOU Ct * 8 of trappable over/underflow tests + + + + 843 * + 844 * Test cases for exhaustive rounding mode tests of long to short + 845 * Load Rounded. + 846 * +0000000000000800 847 LTOSINRM DS 0D Inputs for long to short BFP rounding tests + 848 * x'8000000000000000' sign bit + 849 * x'7FF0000000000000' Biased Exponent + 850 * x'000FFFFFE0000000' Significand used in short + ASMA Ver. 0.2.0 ieee-loadr.asm: Test IEEE Load Rounded 31 Aug 2016 19:54:48 Page 22 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 851 * x'000000001FC00000' Significand used in rounding + 852 * x'00000000003FFFFF' 'extra' significand bits + 853 * Note: in the comments below, 'up' and 'down' mean 'toward + 854 * higher magnitude' and 'toward lower magnitude' respectively and + 855 * without regard to the sign, and rounding is to short BFP. + 856 * + 857 * Exact (fits in short BFP) .. 1.99999988079071044921875 +0000000000000800 3FFFFFFF E0000000 858 DC X'3FFFFFFFE0000000' Positive exact +0000000000000808 BFFFFFFF E0000000 859 DC X'BFFFFFFFE0000000' Negative exact + 860 * + 861 * Tie odd - rounds up .. 1.999999940395355224609375 + 862 * rounds up to .. 2.0 + 863 * rounds down to .. 1.99999988079071044921875 +0000000000000810 3FFFFFFF F0000000 864 DC X'3FFFFFFFF0000000' Positive tie odd +0000000000000818 BFFFFFFF F0000000 865 DC X'BFFFFFFFF0000000' Negative tie odd + 866 * + 867 * Tie even - rounds down .. 1.999999821186065673828125 + 868 * rounds up to .. 1.99999988079071044921875 + 869 * rounds down to .. 1.9999997615814208984375 +0000000000000820 3FFFFFFF D0000000 870 DC X'3FFFFFFFD0000000' Positive tie even +0000000000000828 BFFFFFFF D0000000 871 DC X'BFFFFFFFD0000000' Negative tie even + 872 * + 873 * False exact 1.9999998817220328017896235905936919152736663818359375 + 874 * ..rounds up to 2.0 + 875 * ..rounds down to 1.99999988079071044921875 +0000000000000830 3FFFFFFF E03FFFFF 876 DC X'3FFFFFFFE03FFFFF' Positive false exact +0000000000000838 BFFFFFFF E03FFFFF 877 DC X'BFFFFFFFE03FFFFF' Negative false exact + 878 * + 879 * Nearest is towards zero: 1.9999998812563717365264892578125 + 880 * ..rounds up to 2.0 + 881 * ..rounds down to 1.99999988079071044921875 +0000000000000840 3FFFFFFF E0200000 882 DC X'3FFFFFFFE0200000' Positive zero closer +0000000000000848 BFFFFFFF E0200000 883 DC X'BFFFFFFFE0200000' Negative zero closer + 884 * + 885 * Nearest is away from zero: 1.999999999068677425384521484375 + 886 * ..rounds up to 2.0 + 887 * ..rounds down to 1.99999988079071044921875 +0000000000000850 3FFFFFFF FFC00000 888 DC X'3FFFFFFFFFC00000' Positive zero further +0000000000000858 BFFFFFFF FFC00000 889 DC X'BFFFFFFFFFC00000' Negative zero further + 890 * + 891 * Overflow test: 3.40282366920938425684442744474606501888E38 + 892 * ..rounds up to Overflow + 893 * ..rounds down to 3.40282346638528859811704183484516925440E38 +0000000000000860 47EFFFFF FFFFFFFF 894 DC X'47EFFFFFFFFFFFFF' Positive oveflow test +0000000000000868 C7EFFFFF FFFFFFFF 895 DC X'C7EFFFFFFFFFFFFF' Negative oveflow test + 896 * + 897 * Underflow test: 7.00649232162408535461864791644958...E-46 + 898 * ..rounds up to 1.40129846432481707092372958328991...E-45 + 899 * represented in short bfp as a tiny. + 900 * ..rounds down to underflow (but exact) +0000000000000870 36900000 00000000 901 DC X'3690000000000000' Positive magnitude underflow +0000000000000878 B6900000 00000000 902 DC X'B690000000000000' Negative magnitude underflow + ASMA Ver. 0.2.0 ieee-loadr.asm: Test IEEE Load Rounded 31 Aug 2016 19:54:48 Page 23 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 0000000000000080 0000000000000001 903 LTOSRMCT EQU *-LTOSINRM Count of long BFP rounding tests * 8 + + + + 905 * + 906 * Extended to short basic tests, which tests trappable results, NaN + 907 * propagation, and basic functionality. The second part of this list + 908 * is used for testing trappable results. + 909 * +0000000000000880 910 XTOSIN DS 0D Inputs for extended to short BFP basic tests +0000000000000880 00000000 00000000 911 DC X'00000000000000000000000000000000' +0 +0000000000000890 3FFF8000 00000000 912 DC X'3FFF8000000000000000000000000000' +1.5 +00000000000008A0 BFFF8000 00000000 913 DC X'BFFF8000000000000000000000000000' -1.5 +00000000000008B0 7FFF0100 00000000 914 DC X'7FFF0100000000000000000000000000' SNaN +00000000000008C0 7FFF8110 00000000 915 DC X'7FFF8110000000000000000000000000' QNaN + 916 * See rounding tests below for details on the following four +00000000000008D0 917 XTOSINOU DS 0D start of over/underflow test cases +00000000000008D0 407EFFFF FFFFFFFF 918 DC X'407EFFFFFFFFFFFFFFFFFFFFFFFFFFFF' Pos. oveflow test +00000000000008E0 C07EFFFF FFFFFFFF 919 DC X'C07EFFFFFFFFFFFFFFFFFFFFFFFFFFFF' Neg. oveflow test +00000000000008F0 407FFFFF FEFFFFFF 920 DC X'407FFFFFFEFFFFFFFFFFFFFFFFFFFFFF' Pos. oveflow test +0000000000000900 C07FFFFF FEFFFFFF 921 DC X'C07FFFFFFEFFFFFFFFFFFFFFFFFFFFFF' Neg. oveflow test +0000000000000910 3F690000 00000000 922 DC X'3F690000000000000000000000000000' Pos. exact uflow + 923 * ..result is tiny +0000000000000920 BF690000 00000000 924 DC X'BF690000000000000000000000000000' Neg. exact uflow + 925 * ..result is tiny +0000000000000930 407F0000 00000000 926 DC X'407F0000000000000000000000000000' Pos. exact oflow +0000000000000940 C07F0000 00000000 927 DC X'C07F0000000000000000000000000000' Neg. exact oflow + 928 * + 00000000000000D0 0000000000000001 929 XTOSCT EQU *-XTOSIN Count of extended BFP in list * 16 + 0000000000000080 0000000000000001 930 XTOSOUCT EQU *-XTOSINOU Ct * 16 of trappable over/underflow tests + + + + 932 * + 933 * Test cases for exhaustive rounding mode tests of extended to short + 934 * Load Rounded. + 935 * +0000000000000950 936 XTOSINRM DS 0D Inputs for extended to short BFP rounding tests + 937 * x'80000000000000000000000000000000' sign bit + 938 * x'7FFF0000000000000000000000000000' Biased Exponent + 939 * x'0000FFFFFE0000000000000000000000' Sig'd used in short + 940 * x'0000000001FC00000000000000000000' Sig'd used in rndg + 941 * x'000000000003FFFFFFFFFFFFFFFFFFFF' 'extra' sig'd bits + 942 * Note: in the comments below, 'up' and 'down' mean 'toward + 943 * higher magnitude' and 'toward lower magnitude' respectively and + 944 * without regard to the sign, and rounding is to short BFP. + 945 * + 946 * Exact (fits in short BFP) .. 1.99999988079071044921875 +0000000000000950 3FFFFFFF FE000000 947 DC X'3FFFFFFFFE0000000000000000000000' Pos. exact +0000000000000960 BFFFFFFF FE000000 948 DC X'BFFFFFFFFE0000000000000000000000' Neg. exact + 949 * + 950 * Tie odd - rounds up .. 1.999999940395355224609375 + ASMA Ver. 0.2.0 ieee-loadr.asm: Test IEEE Load Rounded 31 Aug 2016 19:54:48 Page 24 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 951 * rounds up to .. 2.0 + 952 * rounds down to .. 1.99999988079071044921875 +0000000000000970 3FFFFFFF FF000000 953 DC X'3FFFFFFFFF0000000000000000000000' Pos. tie odd +0000000000000980 BFFFFFFF FF000000 954 DC X'BFFFFFFFFF0000000000000000000000' Neg. tie odd + 955 * + 956 * Tie even - rounds down .. 1.999999821186065673828125 + 957 * rounds up to .. 1.99999988079071044921875 + 958 * rounds down to .. 1.9999997615814208984375 +0000000000000990 3FFFFFFF FD000000 959 DC X'3FFFFFFFFD0000000000000000000000' Pos. tie even +00000000000009A0 BFFFFFFF FD000000 960 DC X'BFFFFFFFFD0000000000000000000000' Neg. tie even + 961 * + 962 * False exact 1.9999998817220330238342285156249998... (continues) + 963 * ..07407005561276414694402205741507... (continues) + 964 * ..2681461898351784611804760061204433441162109375 + 965 * ..rounds up to 2.0 + 966 * ..rounds down to 1.99999988079071044921875 +00000000000009B0 3FFFFFFF FE03FFFF 967 DC X'3FFFFFFFFE03FFFFFFFFFFFFFFFFFFFF' Pos. false exact +00000000000009C0 BFFFFFFF FE03FFFF 968 DC X'BFFFFFFFFE03FFFFFFFFFFFFFFFFFFFF' Neg. false exact + 969 * + 970 * Nearest is towards zero: 1.9999998812563717365264892578125 + 971 * ..rounds up to 2.0 + 972 * ..rounds down to 1.99999988079071044921875 +00000000000009D0 3FFFFFFF FE020000 973 DC X'3FFFFFFFFE0200000000000000000000' Pos. zero closer +00000000000009E0 BFFFFFFF FE020000 974 DC X'BFFFFFFFFE0200000000000000000000' Neg. zero closer + 975 * + 976 * Nearest is away from zero: 1.999999999068677425384521484375 + 977 * ..rounds up to 2.0 + 978 * ..rounds down to 1.99999988079071044921875 +00000000000009F0 3FFFFFFF FFFC0000 979 DC X'3FFFFFFFFFFC00000000000000000000' Pos. zero further +0000000000000A00 BFFFFFFF FFFC0000 980 DC X'BFFFFFFFFFFC00000000000000000000' Neg. zero further + 981 * + 982 * Overflow test: 3.40282366920938463463374607431768178688E38 + 983 * ..rounds up to Overflow + 984 * ..rounds down to 3.40282346638528859811704183484516925440E38 +0000000000000A10 407EFFFF FFFFFFFF 985 DC X'407EFFFFFFFFFFFFFFFFFFFFFFFFFFFF' Pos. oveflow test +0000000000000A20 C07EFFFF FFFFFFFF 986 DC X'C07EFFFFFFFFFFFFFFFFFFFFFFFFFFFF' Neg. oveflow test + 987 * + 988 * Underflow test: 7.00649232162408535461864791644958...E-46 + 989 * ..rounds up to 1.40129846432481707092372958328991...E-45 + 990 * represented in short bfp as a tiny. + 991 * ..rounds down to Underflow (but exact) +0000000000000A30 3F690000 00000000 992 DC X'3F690000000000000000000000000000' Pos. exact u-flow + 993 * ..result is tiny +0000000000000A40 BF690000 00000000 994 DC X'BF690000000000000000000000000000' Neg. exact u-flow + 995 * ..result is tiny + 0000000000000100 0000000000000001 996 XTOSRMCT EQU *-XTOSINRM Count of extended BFP rounding tests * 16 + 997 * + 998 * Extended to long basic tests, which tests trappable results, NaN + 999 * propagation, and basic functionality. The second part of this list + 1000 * is used for testing trappable results. + 1001 * +0000000000000A50 1002 XTOLIN DS 0D Inputs for extended to long BFP basic tests + ASMA Ver. 0.2.0 ieee-loadr.asm: Test IEEE Load Rounded 31 Aug 2016 19:54:48 Page 25 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000A50 00000000 00000000 1003 DC X'00000000000000000000000000000000' +0 +0000000000000A60 3FFF8000 00000000 1004 DC X'3FFF8000000000000000000000000000' +1.5 +0000000000000A70 BFFF8000 00000000 1005 DC X'BFFF8000000000000000000000000000' -1.5 +0000000000000A80 7FFF0100 00000000 1006 DC X'7FFF0100000000000000000000000000' SNaN +0000000000000A90 7FFF8110 00000000 1007 DC X'7FFF8110000000000000000000000000' QNaN + 1008 * See rounding tests below for details on the following four +0000000000000AA0 1009 XTOLINOU DS 0D Start of trappable over/underflow test cases +0000000000000AA0 43FEFFFF FFFFFFFF 1010 DC X'43FEFFFFFFFFFFFFFFFFFFFFFFFFFFFF' Pos. oveflow test +0000000000000AB0 C3FEFFFF FFFFFFFF 1011 DC X'C3FEFFFFFFFFFFFFFFFFFFFFFFFFFFFF' Neg. oveflow test +0000000000000AC0 43FFFFFF FFFFFFFF 1012 DC X'43FFFFFFFFFFFFFFF7FFFFFFFFFFFFFF' Pos. oveflow test +0000000000000AD0 C3FFFFFF FFFFFFFF 1013 DC X'C3FFFFFFFFFFFFFFF7FFFFFFFFFFFFFF' Neg. oveflow test +0000000000000AE0 3BCC0000 00000000 1014 DC X'3BCC0000000000000000000000000000' Pos. underflow + 1015 * ..result is tiny +0000000000000AF0 BBCC0000 00000000 1016 DC X'BBCC0000000000000000000000000000' Neg. underflow + 1017 * ..result is tiny +0000000000000B00 43FF0000 00000000 1018 DC X'43FF0000000000000000000000000000' Pos. exact o-flow +0000000000000B10 C3FF0000 00000000 1019 DC X'C3FF0000000000000000000000000000' Neg. exact o-flow + 00000000000000D0 0000000000000001 1020 XTOLCT EQU *-XTOLIN Count of extended BFP in list * 16 + 0000000000000080 0000000000000001 1021 XTOLOUCT EQU *-XTOLINOU Ct * 16 of trappable over/underflow tests + 1022 * + 1023 * Test cases for exhaustive rounding mode tests of long to short + 1024 * Load Rounded. + 1025 * +0000000000000B20 1026 XTOLINRM DS 0D Inputs for extended to short BFP rounding tests + 1027 * x'80000000000000000000000000000000' sign bit + 1028 * x'7FFF0000000000000000000000000000' Biased Exponent + 1029 * x'0000FFFFFFFFFFFFF000000000000000' Sig'd used in long + 1030 * x'00000000000000000FFC000000000000' Sig'd used in rndg + 1031 * x'00000000000000000003FFFFFFFFFFFF' 'extra' sig'd bits + 1032 * + 1033 * Note: in the comments below, 'up' and 'down' mean 'toward + 1034 * higher magnitude' and 'toward lower magnitude' respectively and + 1035 * without regard to the sign, and rounding is to short BFP. + 1036 * + 1037 * + 1038 * Exact (fits in short BFP) + 1039 * .. 1.9999999999999997779553950749686919152736663818359375 + 1040 * +0000000000000B20 3FFFFFFF FFFFFFFF 1041 DC X'3FFFFFFFFFFFFFFFF000000000000000' Pos. exact +0000000000000B30 BFFFFFFF FFFFFFFF 1042 DC X'BFFFFFFFFFFFFFFFF000000000000000' Neg. exact + 1043 * + 1044 * + 1045 * Tie odd - rounds up + 1046 * .. 1.99999999999999988897769753748434595763683319091796875 + 1047 * rounds up to .. 2.0 + 1048 * rounds down to + 1049 * .. 1.9999999999999997779553950749686919152736663818359375 + 1050 * +0000000000000B40 3FFFFFFF FFFFFFFF 1051 DC X'3FFFFFFFFFFFFFFFF800000000000000' Pos. tie odd +0000000000000B50 BFFFFFFF FFFFFFFF 1052 DC X'BFFFFFFFFFFFFFFFF800000000000000' Neg. tie odd + 1053 * + 1054 * + ASMA Ver. 0.2.0 ieee-loadr.asm: Test IEEE Load Rounded 31 Aug 2016 19:54:48 Page 26 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1055 * Tie even - rounds down + 1056 * .. 1.99999999999999966693309261245303787291049957275390625 + 1057 * rounds up to + 1058 * .. 1.9999999999999997779553950749686919152736663818359375 + 1059 * rounds down to + 1060 * .. 1.999999999999999555910790149937383830547332763671875 + 1061 * +0000000000000B60 3FFFFFFF FFFFFFFF 1062 DC X'3FFFFFFFFFFFFFFFE800000000000000' Pos. tie even +0000000000000B70 BFFFFFFF FFFFFFFF 1063 DC X'BFFFFFFFFFFFFFFFE800000000000000' Neg. tie even + 1064 * + 1065 * + 1066 * False exact 1.9999998817220330238342285156249998... (continues) + 1067 * ..07407005561276414694402205741507... (continues) + 1068 * ..2681461898351784611804760061204433441162109375 + 1069 * ..rounds up to 2.0 + 1070 * ..rounds down to + 1071 * .. 1.9999999999999997779553950749686919152736663818359375 + 1072 * +0000000000000B80 3FFFFFFF FFFFFFFF 1073 DC X'3FFFFFFFFFFFFFFFF003FFFFFFFFFFFF' Pos. false exact +0000000000000B90 BFFFFFFF FFFFFFFF 1074 DC X'BFFFFFFFFFFFFFFFF003FFFFFFFFFFFF' Neg. false exact + 1075 * + 1076 * + 1077 * Nearest is towards zero: + 1078 * .. 1.99999999999999977817223550946579280207515694200992584228515625 + 1079 * ..rounds up to 2.0 + 1080 * ..rounds down to + 1081 * .. 1.9999999999999997779553950749686919152736663818359375 + 1082 * +0000000000000BA0 3FFFFFFF FFFFFFFF 1083 DC X'3FFFFFFFFFFFFFFFF004000000000000' Pos. zero closer +0000000000000BB0 BFFFFFFF FFFFFFFF 1084 DC X'BFFFFFFFFFFFFFFFF004000000000000' Neg. zero closer + 1085 * + 1086 * Nearest is away from zero: + 1087 * .. 1.9999999999999999722444243843710864894092082977294921875 + 1088 * ..rounds up to 2.0 + 1089 * ..rounds down to + 1090 * .. 1.999999999999999555910790149937383830547332763671875 + 1091 * +0000000000000BC0 3FFFFFFF FFFFFFFF 1092 DC X'3FFFFFFFFFFFFFFFFE00000000000000' Pos. zero further +0000000000000BD0 BFFFFFFF FFFFFFFF 1093 DC X'BFFFFFFFFFFFFFFFFE00000000000000' Neg. zero further +0000000000000BE0 1094 DS 0D required by asma for following EQU to work. + 1095 * + 1096 * Overflow test: 1.797693134862315708145274237317043...E308 + 1097 * ..rounds up to Overflow + 1098 * ..rounds down to 1.797693134862315907729305190789024...E308 +0000000000000BE0 43FEFFFF FFFFFFFF 1099 DC X'43FEFFFFFFFFFFFFFFFFFFFFFFFFFFFF' Pos. oveflow test +0000000000000BF0 C3FEFFFF FFFFFFFF 1100 DC X'C3FEFFFFFFFFFFFFFFFFFFFFFFFFFFFF' Neg. oveflow test + 1101 * + 1102 * Underflow test: 2.47032822920623272088284396434110...E-324 + 1103 * ..rounds up to 4.94065645841246544176568792868221...E-324 + 1104 * ..rounds down to Underflow +0000000000000C00 3BCC0000 00000000 1105 DC X'3BCC0000000000000000000000000000' Pos. tie odd + 1106 * ..result is tiny + ASMA Ver. 0.2.0 ieee-loadr.asm: Test IEEE Load Rounded 31 Aug 2016 19:54:48 Page 27 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000C10 BBCC0000 00000000 1107 DC X'BBCC0000000000000000000000000000' Neg. tie odd + 1108 * ..result is tiny + 0000000000000100 0000000000000001 1109 XTOLRMCT EQU *-XTOLINRM Count of extended BFP rounding tests * 16 + 1110 * + 1111 * Locations for results + 1112 * + 0000000000001000 0000000000000000 1113 LTOSOUT EQU BFPLDRND+X'1000' Short BFP rounded from long + 1114 * ..9 pairs used, room for 16 + 0000000000001080 0000000000000000 1115 LTOSFLGS EQU BFPLDRND+X'1080' FPCR flags and DXC from above + 1116 * ..9 pairs used, room for 16 + 0000000000001100 0000000000000000 1117 LTOSRMO EQU BFPLDRND+X'1100' Short BFP result rounding tests + 1118 * ..14 sets used, room for 21 + 0000000000001500 0000000000000000 1119 LTOSRMOF EQU BFPLDRND+X'1500' FPCR flags and DXC from above + 1120 * ..14 sets used, room for 21 + 1121 * + 0000000000001900 0000000000000000 1122 XTOSOUT EQU BFPLDRND+X'1900' Short BFP rounded from extended + 1123 * ..5 pairs used, room for 16 + 0000000000001980 0000000000000000 1124 XTOSFLGS EQU BFPLDRND+X'1980' FPCR flags and DXC from above + 1125 * ..5 pairs used, room for 16 + 0000000000001A00 0000000000000000 1126 XTOSRMO EQU BFPLDRND+X'1A00' Short BFP rounding tests + 1127 * ..14 sets used, room for 21 + 0000000000001E00 0000000000000000 1128 XTOSRMOF EQU BFPLDRND+X'1E00' FPCR flags and DXC from above + 1129 * ..14 sets used, room for 21 + 1130 + 1131 * + 0000000000002200 0000000000000000 1132 XTOLOUT EQU BFPLDRND+X'2200' Long BFP rounded from extended + 1133 * ..5 pairs used, room for 16 + 0000000000002300 0000000000000000 1134 XTOLFLGS EQU BFPLDRND+X'2300' FPCR flags and DXC from above + 1135 * ..5 pairs used, room for 32 + 0000000000002400 0000000000000000 1136 XTOLRMO EQU BFPLDRND+X'2400' Long BFP rounding tests + 1137 * ..12 results used, room for 22 + 0000000000002B00 0000000000000000 1138 XTOLRMOF EQU BFPLDRND+X'2B00' FPCR flags and DXC from above + 1139 * ..12 results used, room for 21 + 1140 * + 0000000000003000 0000000000000000 1141 LTOSOUO EQU BFPLDRND+X'3000' Long BFP trappable o/uflow tests + 1142 * ..4 results used, room for 16 + 0000000000003080 0000000000000000 1143 LTOSOUOF EQU BFPLDRND+X'3080' FPCR flags and DXC from above + 1144 * + 0000000000003100 0000000000000000 1145 XTOSOUO EQU BFPLDRND+X'3100' Extd BFP trappable o/uflow tests + 1146 * ..4 results used, room for 8 + 0000000000003180 0000000000000000 1147 XTOSOUOF EQU BFPLDRND+X'3180' FPCR flags and DXC from above + 1148 * + 0000000000003200 0000000000000000 1149 XTOLOUO EQU BFPLDRND+X'3200' Extd BFP trappable o/uflow tests + 1150 * ..4 results used, room for 8 + 0000000000003280 0000000000000000 1151 XTOLOUOF EQU BFPLDRND+X'3280' FPCR flags and DXC from above + 1152 * + 1153 * + 0000000000003300 0000000000000000 1154 ENDRES EQU BFPLDRND+X'3300' next location for results + 1155 * + 1156 PADCSECT ENDRES Pad csect unless asma + 1157+ MNOTE *,'asma detected; no CSECT padding performed' + 1158 * + ASMA Ver. 0.2.0 ieee-loadr.asm: Test IEEE Load Rounded 31 Aug 2016 19:54:48 Page 28 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000C20 1159 END + ASMA Ver. 0.2.0 ieee-loadr.asm: Test IEEE Load Rounded 31 Aug 2016 19:54:48 Page 29 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +BFPLDRND J 000000 3104 154 196 199 201 204 212 284 1113 1115 1117 1119 1122 1124 1126 1128 + 1132 1134 1136 1138 1141 1143 1145 1147 1149 1151 1154 +CTLR0 F 000290 4 274 226 227 228 +ENDRES U 003300 0 1154 +FPCREGNT X 000294 4 275 355 431 437 443 449 457 462 467 472 477 482 510 586 592 + 598 604 612 617 622 627 632 637 665 742 748 754 760 766 + 771 776 781 786 791 +FPCREGTR X 000298 4 276 361 390 515 545 670 700 +FPR0 U 000000 1 174 354 356 362 389 391 427 433 439 445 451 458 463 468 473 + 478 483 508 511 517 543 546 582 588 594 600 606 613 618 + 623 628 633 638 663 666 672 698 701 737 744 750 756 762 + 767 772 777 782 787 792 +FPR1 U 000001 1 175 353 356 357 360 362 363 388 391 392 433 434 439 440 445 + 446 451 452 458 459 463 464 468 469 473 474 478 479 483 + 484 511 516 517 518 546 547 588 589 594 595 600 601 606 + 607 613 614 618 619 623 624 628 629 633 634 638 639 666 + 667 671 672 673 701 702 744 745 750 751 756 757 762 763 + 767 768 772 773 777 778 782 783 787 788 792 793 +FPR10 U 00000A 1 184 +FPR11 U 00000B 1 185 +FPR12 U 00000C 1 186 +FPR13 U 00000D 1 187 +FPR14 U 00000E 1 188 +FPR15 U 00000F 1 189 +FPR2 U 000002 1 176 +FPR3 U 000003 1 177 548 703 +FPR4 U 000004 1 178 +FPR5 U 000005 1 179 +FPR6 U 000006 1 180 +FPR7 U 000007 1 181 +FPR8 U 000008 1 182 +FPR9 U 000009 1 183 +HARDWAIT X 000280 8 272 220 +IMAGE 1 000000 3104 0 +LDXBR I 000638 4 657 247 +LDXBRA I 0006BC 4 731 249 +LDXBROUT I 000682 4 692 264 +LEDBR I 000390 4 347 233 +LEDBRA I 000410 4 421 235 +LEDBROUT I 0003DA 4 382 254 +LEXBR I 0004E2 4 502 240 +LEXBRA I 000566 4 576 242 +LEXBROUT I 00052C 4 537 259 +LTOSBAS F 000300 4 285 232 +LTOSCT U 000068 1 840 286 +LTOSFLGS U 001080 0 1115 289 +LTOSIN D 000798 8 823 840 287 +LTOSINOU D 0007C0 8 830 841 323 +LTOSINRM D 000800 8 847 903 305 +LTOSOU F 000360 4 321 253 +LTOSOUCT U 000040 1 841 322 +LTOSOUO U 003000 0 1141 324 + ASMA Ver. 0.2.0 ieee-loadr.asm: Test IEEE Load Rounded 31 Aug 2016 19:54:48 Page 30 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +LTOSOUOF U 003080 0 1143 325 +LTOSOUT U 001000 0 1113 288 +LTOSRM F 000330 4 303 234 +LTOSRMCT U 000080 1 903 304 +LTOSRMO U 001100 0 1117 306 +LTOSRMOF U 001500 0 1119 307 +PCINTCD H 00008E 2 197 214 +PCNOTDTA H 00020C 2 217 215 +PCOLDPSW U 000150 0 199 216 +PROGCHK H 000200 2 213 205 +R0 U 000000 1 155 226 228 +R1 U 000001 1 156 512 +R10 U 00000A 1 165 232 234 239 241 246 248 253 258 263 347 348 382 383 421 + 422 502 503 537 538 576 577 657 658 692 693 731 732 +R11 U 00000B 1 166 +R12 U 00000C 1 167 351 369 386 398 425 490 506 524 541 554 580 645 661 679 + 696 709 735 799 +R13 U 00000D 1 168 233 235 240 242 247 249 254 259 264 350 370 385 399 424 + 491 505 525 540 555 579 646 660 680 695 710 734 800 +R14 U 00000E 1 169 218 219 266 267 +R15 U 00000F 1 170 191 +R2 U 000002 1 157 347 349 369 382 384 398 421 423 490 502 504 509 524 537 + 539 544 554 576 578 645 657 659 664 679 692 694 699 709 + 731 733 738 799 +R3 U 000003 1 158 347 354 366 382 389 395 421 427 487 502 508 509 521 537 + 543 544 551 576 582 642 657 663 664 676 692 698 699 706 + 731 737 738 796 +R4 U 000004 1 159 +R5 U 000005 1 160 +R6 U 000006 1 161 +R7 U 000007 1 162 348 357 363 367 383 392 396 422 434 440 446 452 459 464 + 469 474 479 484 488 503 512 518 522 538 547 548 552 577 + 589 595 601 607 614 619 624 629 634 639 643 658 667 673 + 677 693 702 703 707 732 745 751 757 763 768 773 778 783 + 788 793 797 +R8 U 000008 1 163 348 358 364 368 383 393 397 422 435 441 447 453 460 465 + 470 475 480 485 489 503 513 519 523 538 549 553 577 590 + 596 602 608 615 620 625 630 635 640 644 658 668 674 678 + 693 704 708 732 746 752 758 764 769 774 779 784 789 794 + 798 +R9 U 000009 1 164 +START I 000214 4 226 202 +WAITPSW X 000270 8 271 268 +XTOLBAS F 000320 4 297 246 +XTOLCT U 0000D0 1 1020 298 +XTOLFLGS U 002300 0 1134 301 +XTOLIN D 000A50 8 1002 1020 299 +XTOLINOU D 000AA0 8 1009 1021 335 +XTOLINRM D 000B20 8 1026 1109 317 +XTOLOU F 000380 4 333 263 +XTOLOUCT U 000080 1 1021 334 +XTOLOUO U 003200 0 1149 336 + ASMA Ver. 0.2.0 ieee-loadr.asm: Test IEEE Load Rounded 31 Aug 2016 19:54:48 Page 31 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +XTOLOUOF U 003280 0 1151 337 +XTOLOUT U 002200 0 1132 300 +XTOLRM F 000350 4 315 248 +XTOLRMCT U 000100 1 1109 316 +XTOLRMO U 002400 0 1136 318 +XTOLRMOF U 002B00 0 1138 319 +XTOSBAS F 000310 4 291 239 +XTOSCT U 0000D0 1 929 292 +XTOSFLGS U 001980 0 1124 295 +XTOSIN D 000880 8 910 929 293 +XTOSINOU D 0008D0 8 917 930 329 +XTOSINRM D 000950 8 936 996 311 +XTOSOU F 000370 4 327 258 +XTOSOUCT U 000080 1 930 328 +XTOSOUO U 003100 0 1145 330 +XTOSOUOF U 003180 0 1147 331 +XTOSOUT U 001900 0 1122 294 +XTOSRM F 000340 4 309 241 +XTOSRMCT U 000100 1 996 310 +XTOSRMO U 001A00 0 1126 312 +XTOSRMOF U 001E00 0 1128 313 + ASMA Ver. 0.2.0 ieee-loadr.asm: Test IEEE Load Rounded 31 Aug 2016 19:54:48 Page 32 + + MACRO DEFN REFERENCES + +PADCSECT 140 1156 + ASMA Ver. 0.2.0 ieee-loadr.asm: Test IEEE Load Rounded 31 Aug 2016 19:54:48 Page 33 + + DESC SYMBOL SIZE POS ADDR + +Entry: 0 + +Image IMAGE 3104 000-C1F 000-C1F + Region 3104 000-C1F 000-C1F + CSECT BFPLDRND 3104 000-C1F 000-C1F + ASMA Ver. 0.2.0 ieee-loadr.asm: Test IEEE Load Rounded 31 Aug 2016 19:54:48 Page 34 + + STMT FILE NAME + +1 C:\Users\srorso\Documents\GitHub\hyperion\tests\bfp-002-loadr.asm + + +** NO ERRORS FOUND ** + +[1157] MNOTE *,asma detected; no CSECT padding performed + \ No newline at end of file diff --git a/tests/bfp-002-loadr.tst b/tests/bfp-002-loadr.tst new file mode 100644 index 000000000..7beb5fdf9 --- /dev/null +++ b/tests/bfp-002-loadr.tst @@ -0,0 +1,1015 @@ +*Testcase bfp-002-loadr.tst: LEDBR, LEDB, LEXBR, LEXB, LDXBR, LDXB + +#Testcase bfp-002-loadr.tst: IEEE Load Rounded +#..Includes LOAD ROOUNDED (6). Tests traps, exceptions, results +#..from all rounding modes, and NaN propagation. + +sysclear +archmode esame + +# +# Following suppresses logging of program checks. This test program, as part +# of its normal operation, generates 51 program check messages that have no +# value in the validation process. (The messages, not the program checks.) +# +ostailor quiet + +loadcore "$(testpath)/bfp-002-loadr.core" + +runtest 1.0 + +ostailor null # restore messages for subsequent tests + + +# Long BFP Inputs converted to short BFP +*Compare +r 1000.10 +*Want "LEDBR result pairs 1-2" 00000000 00000000 3FC00000 3FC00000 +r 1010.10 +*Want "LEDBR result pairs 3-4" BFC00000 BFC00000 7FC08000 00000000 +r 1020.10 +*Want "LEDBR result pairs 5-6" 7FC08800 7FC08800 7F800000 27F00000 +r 1030.10 +*Want "LEDBR result pairs 7-8" FF800000 A7F00000 7F800000 27FFFFFF +r 1040.10 +*Want "LEDBR result pairs 9-10" FF800000 A7FFFFFF 00000000 56900000 +r 1050.10 +*Want "LEDBR result pairs 11-12" 80000000 D6900000 7F800000 27F00000 +r 1060.08 +*Want "LEDBR result pair 13" FF800000 A7F00000 + + +# Long BFP inputs converted to short BFP - FPC +*Compare +r 1080.10 +*Want "LEDBR FPCR pairs 1-2" 00000000 F8000000 00000000 F8000000 +r 1090.10 +*Want "LEDBR FPCR pairs 3-4" 00000000 F8000000 00800000 F8008000 +r 10A0.10 +*Want "LEDBR FPCR pairs 5-6" 00000000 F8000000 00280000 F8002C00 +r 10B0.10 +*Want "LEDBR FPCR pairs 7-8" 00280000 F8002C00 00280000 F8002800 +r 10C0.10 +*Want "LEDBR FPCR pairs 9-10" 00280000 F8002800 00180000 F8001000 +r 10D0.10 +*Want "LEXBR FPCR pairs 11-12" 00180000 F8001000 00280000 F8002000 +r 10E0.08 +*Want "LEXBR FPCR pair 13" 00280000 F8002000 + + + +# Long BFP inputs, trappable overflow/underflow tests +r 3000.10 +*Want "LEDBR trap results 1-2" 27F00000 00000000 A7F00000 00000000 +r 3010.10 +*Want "LEDBR trap results 3-4" 27FFFFFF E0000000 A7FFFFFF E0000000 +r 3020.10 +*Want "LEDBR trap results 5-6" 56900000 00000000 D6900000 00000000 +r 3030.10 +*Want "LEDBR trap results 7-8" 27F00000 00000000 A7F00000 00000000 + + +# Long BFP inputs, trappable overflow/underflow tests - FPC +r 3080.10 +*Want "LEDBR trap FPCR 1-4" F8002C00 F8002C00 F8002800 F8002800 +r 3090.10 +*Want "LEDBR trap FPCR 5-8" F8001000 F8001000 F8002000 F8002000 + + + +# Long BFP Inputs converted to short BFP - rounding mode test results +*Compare +r 1100.10 # RZ, RP, RM, RFS +*Want "LEDBRA +exact FPCR modes 1-3, 7" 3FFFFFFF 3FFFFFFF 3FFFFFFF 3FFFFFFF +r 1110.10 # RNTA, RFS, RNTE, RZ +*Want "LEDBRA +exact M3 modes 1, 3-5" 3FFFFFFF 3FFFFFFF 3FFFFFFF 3FFFFFFF +r 1120.08 # RP, RM +*Want "LEDBRA +exact M3 modes 6, 7" 3FFFFFFF 3FFFFFFF + +*Compare +r 1130.10 # RZ, RP, RM, RFS +*Want "LEDBRA -exact FPCR modes 1-3, 7" BFFFFFFF BFFFFFFF BFFFFFFF BFFFFFFF +r 1140.10 # RNTA, RFS, RNTE, RZ +*Want "LEDBRA -exact M3 modes 1, 3-5" BFFFFFFF BFFFFFFF BFFFFFFF BFFFFFFF +r 1150.08 # RP, RM +*Want "LEDBRA -exact M3 modes 6, 7" BFFFFFFF BFFFFFFF + +*Compare +r 1160.10 # RZ, RP, RM, RFS +*Want "LEDBRA +tie odd FPCR modes 1-3, 7" 3FFFFFFF 40000000 3FFFFFFF 3FFFFFFF +r 1170.10 # RNTA, RFS, RNTE, RZ +*Want "LEDBRA +tie odd M3 modes 1, 3-5" 40000000 3FFFFFFF 40000000 3FFFFFFF +r 1180.08 # RP, RM +*Want "LEDBRA +tie odd M3 modes 6, 7" 40000000 3FFFFFFF + +*Compare +r 1190.10 # RZ, RP, RM, RFS +*Want "LEDBRA -tie odd FPCR modes 1-3, 7" BFFFFFFF BFFFFFFF C0000000 BFFFFFFF +r 11A0.10 # RNTA, RFS, RNTE, RZ +*Want "LEDBRA -tie odd M3 modes 1, 3-5" C0000000 BFFFFFFF C0000000 BFFFFFFF +r 11B0.08 # RP, RM +*Want "LEDBRA -tie odd M3 modes 6, 7" BFFFFFFF C0000000 + +*Compare +r 11C0.10 # RZ, RP, RM, RFS +*Want "LEDBRA +tie even FPCR modes 1-3, 7" 3FFFFFFE 3FFFFFFF 3FFFFFFE 3FFFFFFF +r 11D0.10 # RNTA, RFS, RNTE, RZ +*Want "LEDBRA +tie even M3 modes 1, 3-5" 3FFFFFFF 3FFFFFFF 3FFFFFFE 3FFFFFFE +r 11E0.08 # RP, RM +*Want "LEDBRA +tie even M3 modes 6, 7" 3FFFFFFF 3FFFFFFE + +*Compare +r 11F0.10 # RZ, RP, RM, RFS +*Want "LEDBRA -tie even FPCR modes 1-3, 7" BFFFFFFE BFFFFFFE BFFFFFFF BFFFFFFF +r 1200.10 # RNTA, RFS, RNTE, RZ +*Want "LEDBRA -tie even M3 modes 1, 3-5" BFFFFFFF BFFFFFFF BFFFFFFE BFFFFFFE +r 1210.08 # RP, RM +*Want "LEDBRA -tie even M3 modes 6, 7" BFFFFFFE BFFFFFFF + +*Compare +r 1220.10 # RZ, RP, RM, RFS +*Want "LEDBRA +false exact FPCR modes 1-3, 7" 3FFFFFFF 40000000 3FFFFFFF 3FFFFFFF +r 1230.10 # RNTA, RFS, RNTE, RZ +*Want "LEDBRA +false exact M3 modes 1, 3-5" 3FFFFFFF 3FFFFFFF 3FFFFFFF 3FFFFFFF +r 1240.08 # RP, RM +*Want "LEDBRA +false exact M3 modes 6, 7" 40000000 3FFFFFFF + +*Compare +r 1250.10 # RZ, RP, RM, RFS +*Want "LEDBRA -false exact FPCR modes 1-3, 7" BFFFFFFF BFFFFFFF C0000000 BFFFFFFF +r 1260.10 # RNTA, RFS, RNTE, RZ +*Want "LEDBRA -false exact M3 modes 1, 3-5" BFFFFFFF BFFFFFFF BFFFFFFF BFFFFFFF +r 1270.08 # RP, RM +*Want "LEDBRA -false exact M3 modes 6, 7" BFFFFFFF C0000000 + +*Compare +r 1280.10 # RZ, RP, RM, RFS +*Want "LEDBRA +near zero FPCR modes 1-3, 7" 3FFFFFFF 40000000 3FFFFFFF 3FFFFFFF +r 1290.10 # RNTA, RFS, RNTE, RZ +*Want "LEDBRA +near zero M3 modes 1, 3-5" 3FFFFFFF 3FFFFFFF 3FFFFFFF 3FFFFFFF +r 12A0.08 # RP, RM +*Want "LEDBRA +near zero M3 modes 6, 7" 40000000 3FFFFFFF + +*Compare +r 12B0.10 # RZ, RP, RM, RFS +*Want "LEDBRA -near zero FPCR modes 1-3, 7" BFFFFFFF BFFFFFFF C0000000 BFFFFFFF +r 12C0.10 # RNTA, RFS, RNTE, RZ +*Want "LEDBRA -near zero M3 modes 1, 3-5" BFFFFFFF BFFFFFFF BFFFFFFF BFFFFFFF +r 12D0.08 # RP, RM +*Want "LEDBRA -near zero M3 modes 6, 7" BFFFFFFF C0000000 + +*Compare +r 12E0.10 # RZ, RP, RM, RFS +*Want "LEDBRA +near +inf FPCR modes 1-3, 7" 3FFFFFFF 40000000 3FFFFFFF 3FFFFFFF +r 12F0.10 # RNTA, RFS, RNTE, RZ +*Want "LEDBRA +near +inf M3 modes 1, 3-5" 40000000 3FFFFFFF 40000000 3FFFFFFF +r 1300.08 # RP, RM +*Want "LEDBRA +near +inf M3 modes 6, 7" 40000000 3FFFFFFF + +*Compare +r 1310.10 # RZ, RP, RM, RFS +*Want "LEDBRA -near -inf FPCR modes 1-3, 7" BFFFFFFF BFFFFFFF C0000000 BFFFFFFF +r 1320.10 # RNTA, RFS, RNTE, RZ +*Want "LEDBRA -near -inf M3 modes 1, 3-5" C0000000 BFFFFFFF C0000000 BFFFFFFF +r 1330.08 # RP, RM +*Want "LEDBRA -near -inf M3 modes 6, 7" BFFFFFFF C0000000 + +*Compare +r 1340.10 # RZ, RP, RM, RFS +*Want "LEDBRA +overflow FPCR modes 1-3, 7" 7F7FFFFF 7F800000 7F7FFFFF 7F7FFFFF +r 1350.10 # RNTA, RFS, RNTE, RZ +*Want "LEDBRA +overflow M3 modes 1, 3-5" 7F800000 7F7FFFFF 7F800000 7F7FFFFF +r 1360.08 # RP, RM +*Want "LEDBRA +overflow M3 modes 6, 7" 7F800000 7F7FFFFF + +*Compare +r 1370.10 # RZ, RP, RM, RFS +*Want "LEDBRA -overflow FPCR modes 1-3, 7" FF7FFFFF FF7FFFFF FF800000 FF7FFFFF +r 1380.10 # RNTA, RFS, RNTE, RZ +*Want "LEDBRA -overflow M3 modes 1, 3-5" FF800000 FF7FFFFF FF800000 FF7FFFFF +r 1390.08 # RP, RM +*Want "LEDBRA -overflow M3 modes 6, 7" FF7FFFFF FF800000 + +*Compare +r 13A0.10 # RZ, RP, RM, RFS +*Want "LEDBRA +tiny tie odd FPCR modes 1-3, 7" 00000000 00000001 00000000 00000001 +r 13B0.10 # RNTA, RFS, RNTE, RZ +*Want "LEDBRA +tiny tie odd M3 modes 1, 3-5" 00000001 00000001 00000000 00000000 +r 13C0.08 # RP, RM +*Want "LEDBRA +tiny tie odd M3 modes 6, 7" 00000001 00000000 + +*Compare +r 13D0.10 # RZ, RP, RM, RFS +*Want "LEDBRA -tiny tie odd FPCR modes 1-3, 7" 80000000 80000000 80000001 80000001 +r 13E0.10 # RNTA, RFS, RNTE, RZ +*Want "LEDBRA -tiny tie odd M3 modes 1, 3-5" 80000001 80000001 80000000 80000000 +r 13F0.08 # RP, RM +*Want "LEDBRA -tiny tie odd M3 modes 6, 7" 80000000 80000001 + + +# Long BFP Inputs converted to short BFP - rounding mode tests - FPCR contents +*Compare +r 1500.10 +*Want "LEDBRA +exact FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 1510.10 +*Want "LEDBRA +exact M3 modes 1, 3-5 FPCR" 00000000 00000000 00000000 00000000 +r 1520.08 +*Want "LEDBRA +exact M3 modes 6, 7 FCPR" 00000000 00000000 + +r 1530.10 +*Want "LEDBRA -exact FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 1540.10 +*Want "LEDBRA -exact M3 modes 1, 3-5 FPCR" 00000000 00000000 00000000 00000000 +r 1550.08 +*Want "LEDBRA -exact M3 modes 6, 7 FCPR" 00000000 00000000 + +r 1560.10 +*Want "LEDBRA +tie odd FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 1570.10 +*Want "LEDBRA +tie odd M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 1580.08 +*Want "LEDBRA +tie odd M3 modes 6, 7 FCPR" 00080000 00080000 + +r 1590.10 +*Want "LEDBRA -tie odd FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 15A0.10 +*Want "LEDBRA -tie odd M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 15B0.08 +*Want "LEDBRA -tie odd M3 modes 6, 7 FCPR" 00080000 00080000 + +r 15C0.10 +*Want "LEDBRA +tie even FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 15D0.10 +*Want "LEDBRA +tie even M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 15E0.08 +*Want "LEDBRA +tie even M3 modes 6, 7 FCPR" 00080000 00080000 + +r 15F0.10 +*Want "LEDBRA -tie even FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 1600.10 +*Want "LEDBRA -tie even M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 1610.08 +*Want "LEDBRA -tie even M3 modes 6, 7 FCPR" 00080000 00080000 + +r 1620.10 +*Want "LEDBRA +false exact FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 1630.10 +*Want "LEDBRA +false exact M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 1640.08 +*Want "LEDBRA +false exact M3 modes 6, 7 FCPR" 00080000 00080000 + +r 1650.10 +*Want "LEDBRA -false exact FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 1660.10 +*Want "LEDBRA -false exact M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 1670.08 +*Want "LEDBRA -false exact M3 modes 6, 7 FCPR" 00080000 00080000 + +r 1680.10 +*Want "LEDBRA +near zero FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 1690.10 +*Want "LEDBRA +near zero M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 16A0.08 +*Want "LEDBRA +near zero M3 modes 6, 7 FCPR" 00080000 00080000 + +r 16B0.10 +*Want "LEDBRA -near zero FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 16C0.10 +*Want "LEDBRA -near zero M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 16D0.08 +*Want "LEDBRA -near zero M3 modes 6, 7 FCPR" 00080000 00080000 + +r 16E0.10 +*Want "LEDBRA +near +inf FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 16F0.10 +*Want "LEDBRA +near +inf M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 1700.08 +*Want "LEDBRA +near +inf M3 modes 6, 7 FCPR" 00080000 00080000 + +r 1710.10 +*Want "LEDBRA -near -inf FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 1720.10 +*Want "LEDBRA -near -inf M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 1730.08 +*Want "LEDBRA -near -inf M3 modes 6, 7 FCPR" 00080000 00080000 + +*Compare +r 1740.10 # RZ, RP, RM, RFS +*Want "LEDBRA +overflow FPCR modes 1-3, 7 FPCR" 00000001 00200002 00000003 00000007 +r 1750.10 # RNTA, RFS, RNTE, RZ +*Want "LEDBRA +overflow M3 modes 1, 3-5 FPCR" 00280000 00080000 00280000 00080000 +r 1760.08 # RP, RM +*Want "LEDBRA +overflow M3 modes 6, 7 FPCR" 00280000 00080000 + +*Compare +r 1770.10 # RZ, RP, RM, RFS +*Want "LEDBRA -overflow FPCR modes 1-3, 7 FPCR" 00000001 00000002 00200003 00000007 +r 1780.10 # RNTA, RFS, RNTE, RZ +*Want "LEDBRA -overflow M3 modes 1, 3-5 FPCR" 00280000 00080000 00280000 00080000 +r 1790.08 # RP, RM +*Want "LEDBRA -overflow M3 modes 6, 7 FPCR" 00080000 00280000 + +*Compare +r 17A0.10 # RZ, RP, RM, RFS +*Want "LEDBRA +tiny tie odd FPCR modes 1-3, 7 FPCR" 00100001 00100002 00100003 00100007 +r 17B0.10 # RNTA, RFS, RNTE, RZ +*Want "LEDBRA +tiny tie odd M3 modes 1, 3-5 FPCR" 00180000 00180000 00180000 00180000 +r 17C0.08 # RP, RM +*Want "LEDBRA +tiny tie odd M3 modes 6, 7 FPCR" 00180000 00180000 + +*Compare +r 17D0.10 # RZ, RP, RM, RFS +*Want "LEDBRA -tiny tie odd FPCR modes 1-3, 7 FPCR" 00100001 00100002 00100003 00100007 +r 17E0.10 # RNTA, RFS, RNTE, RZ +*Want "LEDBRA -tiny tie odd M3 modes 1, 3-5 FPCR" 00180000 00180000 00180000 00180000 +r 17F0.08 # RP, RM +*Want "LEDBRA -tiny tie odd M3 modes 6, 7 FPCR" 00180000 00180000 + + + +# Extended BFP inputs rounded to short BFP +*Compare +r 1900.10 +*Want "LEXBR result pairs 1-2" 00000000 00000000 3FC00000 3FC00000 +r 1910.10 +*Want "LEXBR result pairs 3-4" BFC00000 BFC00000 7FC08000 00000000 +r 1920.10 +*Want "LEXBR result pairs 5-6" 7FC08800 7FC08800 7F800000 207F0000 +r 1930.10 +*Want "LEXBR result pairs 7-8" FF800000 A07F0000 7F800000 207FFFFF +r 1940.10 +*Want "LEXBR result pairs 9-10" FF800000 A07FFFFF 00000000 5F690000 +r 1950.10 +*Want "LEXBR result pair 11-12" 80000000 DF690000 7F800000 207F0000 +r 1960.08 +*Want "LEXBR result pair 13" FF800000 A07F0000 + + +# Extended BFP inputs rounded to short BFP - FPCR contents +*Compare +r 1980.10 +*Want "LEXBR FPCR pairs 1-2" 00000000 F8000000 00000000 F8000000 +r 1990.10 +*Want "LEXBR FPCR pairs 3-4" 00000000 F8000000 00800000 F8008000 +r 19A0.10 +*Want "LEXBR FPCR pairs 5-6" 00000000 F8000000 00280000 F8002C00 +r 19B0.10 +*Want "LEXBR FPCR pairs 7-8" 00280000 F8002C00 00280000 F8002800 +r 19C0.10 +*Want "LEXBR FPCR pairs 9-10" 00280000 F8002800 00180000 F8001000 +r 19D0.10 +*Want "LEXBR FPCR pairs 11-12" 00180000 F8001000 00280000 F8002000 +r 19E0.08 +*Want "LEXBR FPCR pair 13" 00280000 F8002000 + + + +# Extended BFP inputs, short results, trappable overflow/underflow tests +r 3100.10 +*Want "LEXBR trap results 1" 207F0000 00000000 00000000 00000000 +r 3110.10 +*Want "LEXBR trap results 2" A07F0000 00000000 00000000 00000000 +r 3120.10 +*Want "LEXBR trap results 3" 207FFFFF FE000000 00000000 00000000 +r 3130.10 +*Want "LEXBR trap results 4" A07FFFFF FE000000 00000000 00000000 +r 3140.10 +*Want "LEXBR trap results 5" 5F690000 00000000 00000000 00000000 +r 3150.10 +*Want "LEXBR trap results 6" DF690000 00000000 00000000 00000000 +r 3160.10 +*Want "LEXBR trap results 7" 207F0000 00000000 00000000 00000000 +r 3170.10 +*Want "LEXBR trap results 8" A07F0000 00000000 00000000 00000000 + + +# Extended BFP inputs, trappable overflow/underflow tests - FPC +r 3180.10 +*Want "LEXBR trap FPCR 1-4" F8002C00 F8002C00 F8002800 F8002800 +r 3190.10 +*Want "LEXBR trap FPCR 5-8" F8001000 F8001000 F8002000 F8002000 + + + +# Extended BFP inputs rounded to short BFP - rounding mode test results +*Compare +r 1A00.10 # RZ, RP, RM, RFS +*Want "LEXBRA +exact FPCR modes 1-3, 7" 3FFFFFFF 3FFFFFFF 3FFFFFFF 3FFFFFFF +r 1A10.10 # RNTA, RFS, RNTE, RZ +*Want "LEXBRA +exact M3 modes 1, 3-5" 3FFFFFFF 3FFFFFFF 3FFFFFFF 3FFFFFFF +r 1A20.08 # RP, RM +*Want "LEXBRA +exact M3 modes 6, 7" 3FFFFFFF 3FFFFFFF + +*Compare +r 1A30.10 # RZ, RP, RM, RFS +*Want "LEXBRA -exact FPCR modes 1-3, 7" BFFFFFFF BFFFFFFF BFFFFFFF BFFFFFFF +r 1A40.10 # RNTA, RFS, RNTE, RZ +*Want "LEXBRA -exact M3 modes 1, 3-5" BFFFFFFF BFFFFFFF BFFFFFFF BFFFFFFF +r 1A50.08 # RP, RM +*Want "LEXBRA -exact M3 modes 6, 7" BFFFFFFF BFFFFFFF + +*Compare +r 1A60.10 # RZ, RP, RM, RFS +*Want "LEXBRA +tie odd FPCR modes 1-3, 7" 3FFFFFFF 40000000 3FFFFFFF 3FFFFFFF +r 1A70.10 # RNTA, RFS, RNTE, RZ +*Want "LEXBRA +tie odd M3 modes 1, 3-5" 40000000 3FFFFFFF 40000000 3FFFFFFF +r 1A80.08 # RP, RM +*Want "LEXBRA +tie odd M3 modes 6, 7" 40000000 3FFFFFFF + +*Compare +r 1A90.10 # RZ, RP, RM, RFS +*Want "LEXBRA -tie odd FPCR modes 1-3, 7" BFFFFFFF BFFFFFFF C0000000 BFFFFFFF +r 1AA0.10 # RNTA, RFS, RNTE, RZ +*Want "LEXBRA -tie odd M3 modes 1, 3-5" C0000000 BFFFFFFF C0000000 BFFFFFFF +r 1AB0.08 # RP, RM +*Want "LEXBRA -tie odd M3 modes 6, 7" BFFFFFFF C0000000 + +*Compare +r 1AC0.10 # RZ, RP, RM, RFS +*Want "LEXBRA +tie even FPCR modes 1-3, 7" 3FFFFFFE 3FFFFFFF 3FFFFFFE 3FFFFFFF +r 1AD0.10 # RNTA, RFS, RNTE, RZ +*Want "LEXBRA +tie even M3 modes 1, 3-5" 3FFFFFFF 3FFFFFFF 3FFFFFFE 3FFFFFFE +r 1AE0.08 # RP, RM +*Want "LEXBRA +tie even M3 modes 6, 7" 3FFFFFFF 3FFFFFFE + +*Compare +r 1AF0.10 # RZ, RP, RM, RFS +*Want "LEXBRA -tie even FPCR modes 1-3, 7" BFFFFFFE BFFFFFFE BFFFFFFF BFFFFFFF +r 1B00.10 # RNTA, RFS, RNTE, RZ +*Want "LEXBRA -tie even M3 modes 1, 3-5" BFFFFFFF BFFFFFFF BFFFFFFE BFFFFFFE +r 1B10.08 # RP, RM +*Want "LEXBRA -tie even M3 modes 6, 7" BFFFFFFE BFFFFFFF + +*Compare +r 1B20.10 # RZ, RP, RM, RFS +*Want "LEXBRA +false exact FPCR modes 1-3, 7" 3FFFFFFF 40000000 3FFFFFFF 3FFFFFFF +r 1B30.10 # RNTA, RFS, RNTE, RZ +*Want "LEXBRA +false exact M3 modes 1, 3-5" 3FFFFFFF 3FFFFFFF 3FFFFFFF 3FFFFFFF +r 1B40.08 # RP, RM +*Want "LEXBRA +false exact M3 modes 6, 7" 40000000 3FFFFFFF + +*Compare +r 1B50.10 # RZ, RP, RM, RFS +*Want "LEXBRA -false exact FPCR modes 1-3, 7" BFFFFFFF BFFFFFFF C0000000 BFFFFFFF +r 1B60.10 # RNTA, RFS, RNTE, RZ +*Want "LEXBRA -false exact M3 modes 1, 3-5" BFFFFFFF BFFFFFFF BFFFFFFF BFFFFFFF +r 1B70.08 # RP, RM +*Want "LEXBRA -false exact M3 modes 6, 7" BFFFFFFF C0000000 + +*Compare +r 1B80.10 # RZ, RP, RM, RFS +*Want "LEXBRA +near zero FPCR modes 1-3, 7" 3FFFFFFF 40000000 3FFFFFFF 3FFFFFFF +r 1B90.10 # RNTA, RFS, RNTE, RZ +*Want "LEXBRA +near zero M3 modes 1, 3-5" 3FFFFFFF 3FFFFFFF 3FFFFFFF 3FFFFFFF +r 1BA0.08 # RP, RM +*Want "LEXBRA +near zero M3 modes 6, 7" 40000000 3FFFFFFF + +*Compare +r 1BB0.10 # RZ, RP, RM, RFS +*Want "LEXBRA -near zero FPCR modes 1-3, 7" BFFFFFFF BFFFFFFF C0000000 BFFFFFFF +r 1BC0.10 # RNTA, RFS, RNTE, RZ +*Want "LEXBRA -near zero M3 modes 1, 3-5" BFFFFFFF BFFFFFFF BFFFFFFF BFFFFFFF +r 1BD0.08 # RP, RM +*Want "LEXBRA -near zero M3 modes 6, 7" BFFFFFFF C0000000 + +*Compare +r 1BE0.10 # RZ, RP, RM, RFS +*Want "LEXBRA +near +inf FPCR modes 1-3, 7" 3FFFFFFF 40000000 3FFFFFFF 3FFFFFFF +r 1BF0.10 # RNTA, RFS, RNTE, RZ +*Want "LEXBRA +near +inf M3 modes 1, 3-5" 40000000 3FFFFFFF 40000000 3FFFFFFF +r 1C00.08 # RP, RM +*Want "LEXBRA +near +inf M3 modes 6, 7" 40000000 3FFFFFFF + +*Compare +r 1C10.10 # RZ, RP, RM, RFS +*Want "LEXBRA -near -inf FPCR modes 1-3, 7" BFFFFFFF BFFFFFFF C0000000 BFFFFFFF +r 1C20.10 # RNTA, RFS, RNTE, RZ +*Want "LEXBRA -near -inf M3 modes 1, 3-5" C0000000 BFFFFFFF C0000000 BFFFFFFF +r 1C30.08 # RP, RM +*Want "LEXBRA -near -inf M3 modes 6, 7" BFFFFFFF C0000000 + +*Compare +r 1C40.10 # RZ, RP, RM, RFS +*Want "LEXBRA +overflow FPCR modes 1-3, 7" 7F7FFFFF 7F800000 7F7FFFFF 7F7FFFFF +r 1C50.10 # RNTA, RFS, RNTE, RZ +*Want "LEXBRA +overflow M3 modes 1, 3-5" 7F800000 7F7FFFFF 7F800000 7F7FFFFF +r 1C60.08 # RP, RM +*Want "LEXBRA +overflow M3 modes 6, 7" 7F800000 7F7FFFFF + +*Compare +r 1C70.10 # RZ, RP, RM, RFS +*Want "LEXBRA -overflow FPCR modes 1-3, 7" FF7FFFFF FF7FFFFF FF800000 FF7FFFFF +r 1C80.10 # RNTA, RFS, RNTE, RZ +*Want "LEXBRA -overflow M3 modes 1, 3-5" FF800000 FF7FFFFF FF800000 FF7FFFFF +r 1C90.08 # RP, RM +*Want "LEXBRA -overflow M3 modes 6, 7" FF7FFFFF FF800000 + +*Compare +r 1CA0.10 # RZ, RP, RM, RFS +*Want "LEXBRA +tiny tie odd FPCR modes 1-3, 7" 00000000 00000001 00000000 00000001 +r 1CB0.10 # RNTA, RFS, RNTE, RZ +*Want "LEXBRA +tiny tie odd M3 modes 1, 3-5" 00000001 00000001 00000000 00000000 +r 1CC0.08 # RP, RM +*Want "LEXBRA +tiny tie odd M3 modes 6, 7" 00000001 00000000 + +*Compare +r 1CD0.10 # RZ, RP, RM, RFS +*Want "LEXBRA -tiny tie odd FPCR modes 1-3, 7" 80000000 80000000 80000001 80000001 +r 1CE0.10 # RNTA, RFS, RNTE, RZ +*Want "LEXBRA -tiny tie odd M3 modes 1, 3-5" 80000001 80000001 80000000 80000000 +r 1CF0.08 # RP, RM +*Want "LEXBRA -tiny tie odd M3 modes 6, 7" 80000000 80000001 + +# Extended BFP inputs converted to short BFP - rounding mode tests - FPCR contents +*Compare +r 1E00.10 +*Want "LEXBRA +exact FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 1E10.10 +*Want "LEXBRA +exact M3 modes 1, 3-5 FPCR" 00000000 00000000 00000000 00000000 +r 1E20.08 +*Want "LEXBRA +exact M3 modes 6, 7 FCPR" 00000000 00000000 + +r 1E30.10 +*Want "LEXBRA -exact FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 1E40.10 +*Want "LEXBRA -exact M3 modes 1, 3-5 FPCR" 00000000 00000000 00000000 00000000 +r 1E50.08 +*Want "LEXBRA -exact M3 modes 6, 7 FCPR" 00000000 00000000 + +r 1E60.10 +*Want "LEXBRA +tie odd FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 1E70.10 +*Want "LEXBRA +tie odd M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 1E80.08 +*Want "LEXBRA +tie odd M3 modes 6, 7 FCPR" 00080000 00080000 + +r 1E90.10 +*Want "LEXBRA -tie odd FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 1EA0.10 +*Want "LEXBRA -tie odd M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 1EB0.08 +*Want "LEXBRA -tie odd M3 modes 6, 7 FCPR" 00080000 00080000 + +r 1EC0.10 +*Want "LEXBRA +tie even FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 1ED0.10 +*Want "LEXBRA +tie even M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 1EE0.08 +*Want "LEXBRA +tie even M3 modes 6, 7 FCPR" 00080000 00080000 + +r 1EF0.10 +*Want "LEXBRA -tie even FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 1F00.10 +*Want "LEXBRA -tie even M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 1F10.08 +*Want "LEXBRA -tie even M3 modes 6, 7 FCPR" 00080000 00080000 + +r 1F20.10 +*Want "LEXBRA +false exact FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 1F30.10 +*Want "LEXBRA +false exact M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 1F40.08 +*Want "LEXBRA +false exact M3 modes 6, 7 FCPR" 00080000 00080000 + +r 1F50.10 +*Want "LEXBRA -false exact FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 1F60.10 +*Want "LEXBRA -false exact M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 1F70.08 +*Want "LEXBRA -false exact M3 modes 6, 7 FCPR" 00080000 00080000 + +r 1F80.10 +*Want "LEXBRA +near zero FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 1F90.10 +*Want "LEXBRA +near zero M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 1FA0.08 +*Want "LEXBRA +near zero M3 modes 6, 7 FCPR" 00080000 00080000 + +r 1FB0.10 +*Want "LEXBRA -near zero FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 1FC0.10 +*Want "LEXBRA -near zero M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 1FD0.08 +*Want "LEXBRA -near zero M3 modes 6, 7 FCPR" 00080000 00080000 + +r 1FE0.10 +*Want "LEXBRA +near +inf FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 1FF0.10 +*Want "LEXBRA +near +inf M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 2000.08 +*Want "LEXBRA +near +inf M3 modes 6, 7 FCPR" 00080000 00080000 + +r 2010.10 +*Want "LEXBRA -near -inf FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 2020.10 +*Want "LEXBRA -near -inf M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 2030.08 +*Want "LEXBRA -near -inf M3 modes 6, 7 FCPR" 00080000 00080000 + +*Compare +r 2040.10 # RZ, RP, RM, RFS +*Want "LEXBRA +overflow FPCR modes 1-3, 7 FPCR" 00000001 00200002 00000003 00000007 +r 2050.10 # RNTA, RFS, RNTE, RZ +*Want "LEXBRA +overflow M3 modes 1, 3-5 FPCR" 00280000 00080000 00280000 00080000 +r 2060.08 # RP, RM +*Want "LEXBRA +overflow M3 modes 6, 7 FPCR" 00280000 00080000 + +*Compare +r 2070.10 # RZ, RP, RM, RFS +*Want "LEXBRA -overflow FPCR modes 1-3, 7 FPCR" 00000001 00000002 00200003 00000007 +r 2080.10 # RNTA, RFS, RNTE, RZ +*Want "LEXBRA -overflow M3 modes 1, 3-5 FPCR" 00280000 00080000 00280000 00080000 +r 2090.08 # RP, RM +*Want "LEXBRA -overflow M3 modes 6, 7 FPCR" 00080000 00280000 + +*Compare +r 20A0.10 # RZ, RP, RM, RFS +*Want "LEXBRA +tiny tie odd FPCR modes 1-3, 7 FPCR" 00100001 00100002 00100003 00100007 +r 20B0.10 # RNTA, RFS, RNTE, RZ +*Want "LEXBRA +tiny tie odd M3 modes 1, 3-5 FPCR" 00180000 00180000 00180000 00180000 +r 20C0.08 # RP, RM +*Want "LEXBRA +tiny tie odd M3 modes 6, 7 FPCR" 00180000 00180000 + +*Compare +r 20D0.10 # RZ, RP, RM, RFS +*Want "LEXBRA -tiny tie odd FPCR modes 1-3, 7 FPCR" 00100001 00100002 00100003 00100007 +r 20E0.10 # RNTA, RFS, RNTE, RZ +*Want "LEXBRA -tiny tie odd M3 modes 1, 3-5 FPCR" 00180000 00180000 00180000 00180000 +r 20F0.08 # RP, RM +*Want "LEXBRA -tiny tie odd M3 modes 6, 7 FPCR" 00180000 00180000 + + +# Extended BFP inputs converted to long BFP - results +*Compare +r 2200.10 +*Want "LDXBR result pair 1" 00000000 00000000 00000000 00000000 +r 2210.10 +*Want "LDXBR result pair 2" 3FF80000 00000000 3FF80000 00000000 +r 2220.10 +*Want "LDXBR result pair 3" BFF80000 00000000 BFF80000 00000000 +r 2230.10 +*Want "LDXBR result pair 4" 7FF81000 00000000 00000000 00000000 +r 2240.10 +*Want "LDXBR result pair 5" 7FF81100 00000000 7FF81100 00000000 +r 2250.10 +*Want "LDXBR result pair 6" 7FF00000 00000000 23FF0000 00000000 +r 2260.10 +*Want "LDXBR result pair 7" FFF00000 00000000 A3FF0000 00000000 +r 2270.10 +*Want "LDXBR result pair 8" 7FF00000 00000000 23FFFFFF FFFFFFFF +r 2280.10 +*Want "LDXBR result pair 9" FFF00000 00000000 A3FFFFFF FFFFFFFF +r 2290.10 +*Want "LDXBR result pair 10" 00000000 00000000 5BCC0000 00000000 +r 22A0.10 +*Want "LDXBR result pair 11" 80000000 00000000 DBCC0000 00000000 +r 22B0.10 +*Want "LDXBR result pair 12" 7FF00000 00000000 23FF0000 00000000 +r 22C0.10 +*Want "LDXBR result pair 13" FFF00000 00000000 A3FF0000 00000000 + +# Extended BFP inputs converted to long BFP - FPCR contents +*Compare +r 2300.10 +*Want "LDXBR FPCR pairs 1-2" 00000000 F8000000 00000000 F8000000 +r 2310.10 +*Want "LDXBR FPCR pairs 3-4" 00000000 F8000000 00800000 F8008000 +r 2320.10 +*Want "LDXBR FPCR pairs 5-6" 00000000 F8000000 00280000 F8002C00 +r 2330.10 +*Want "LDXBR FPCR pairs 7-8" 00280000 F8002C00 00280000 F8002800 +r 2340.10 +*Want "LDXBR FPCR pairs 9-10" 00280000 F8002800 00180000 F8001000 +r 2350.10 +*Want "LDXBR FPCR pairs 11-12" 00180000 F8001000 00280000 F8002000 +r 2360.08 +*Want "LDXBR FPCR pair 13" 00280000 F8002000 + + +# Extended BFP inputs, short results, trappable overflow/underflow tests +r 3200.10 +*Want "LDXBR trap result 1" 23FF0000 00000000 00000000 00000000 +r 3210.10 +*Want "LDXBR trap result 2" A3FF0000 00000000 00000000 00000000 +r 3220.10 +*Want "LDXBR trap result 3" 23FFFFFF FFFFFFFF F0000000 00000000 +r 3230.10 +*Want "LDXBR trap result 4" A3FFFFFF FFFFFFFF F0000000 00000000 +r 3240.10 +*Want "LDXBR trap result 5" 5BCC0000 00000000 00000000 00000000 +r 3250.10 +*Want "LDXBR trap result 6" DBCC0000 00000000 00000000 00000000 +r 3260.10 +*Want "LDXBR trap result 7" 23FF0000 00000000 00000000 00000000 +r 3270.10 +*Want "LDXBR trap result 8" A3FF0000 00000000 00000000 00000000 + + +# Extended BFP inputs, trappable overflow/underflow tests - FPC +r 3280.10 +*Want "LDXBR trap FPCR 1-4" F8002C00 F8002C00 F8002800 F8002800 +r 3290.10 +*Want "LDXBR trap FPCR 5-8" F8001000 F8001000 F8002000 F8002000 + + +# Extended BFP inputs rounded to long BFP - rounding mode test results +*Compare +r 2400.10 # RZ, RP +*Want "LDXBRA +exact FPC modes 1, 2" 3FFFFFFF FFFFFFFF 3FFFFFFF FFFFFFFF +r 2410.10 # RM, RFS +*Want "LDXBRA +exact FPC modes 3, 7" 3FFFFFFF FFFFFFFF 3FFFFFFF FFFFFFFF +r 2420.10 # RNTA, RFS +*Want "LDXBRA +exact M3 modes 1, 3" 3FFFFFFF FFFFFFFF 3FFFFFFF FFFFFFFF +r 2430.10 # RNTE, RZ +*Want "LDXBRA +exact M3 modes 4, 5" 3FFFFFFF FFFFFFFF 3FFFFFFF FFFFFFFF +r 2440.10 # RP, RM +*Want "LDXBRA +exact M3 modes 6, 7" 3FFFFFFF FFFFFFFF 3FFFFFFF FFFFFFFF + +r 2450.10 # RZ, RP +*Want "LDXBRA -exact FPC modes 1, 2" BFFFFFFF FFFFFFFF BFFFFFFF FFFFFFFF +r 2460.10 # RM, RFS +*Want "LDXBRA -exact FPC modes 3, 7" BFFFFFFF FFFFFFFF BFFFFFFF FFFFFFFF +r 2470.10 # RNTA, RFS +*Want "LDXBRA -exact M3 modes 1, 3" BFFFFFFF FFFFFFFF BFFFFFFF FFFFFFFF +r 2480.10 # RNTE, RZ +*Want "LDXBRA -exact M3 modes 4, 5" BFFFFFFF FFFFFFFF BFFFFFFF FFFFFFFF +r 2490.10 # RP, RM +*Want "LDXBRA -exact M3 modes 6, 7" BFFFFFFF FFFFFFFF BFFFFFFF FFFFFFFF + +r 24A0.10 # RZ, RP +*Want "LDXBRA +tie odd FPC modes 1, 2" 3FFFFFFF FFFFFFFF 40000000 00000000 +r 24B0.10 # RM, RFS +*Want "LDXBRA +tie odd FPC modes 3, 7" 3FFFFFFF FFFFFFFF 3FFFFFFF FFFFFFFF +r 24C0.10 # RNTA, RFS +*Want "LDXBRA +tie odd M3 modes 1, 3" 40000000 00000000 3FFFFFFF FFFFFFFF +r 24D0.10 # RNTE, RZ +*Want "LDXBRA +tie odd M3 modes 4, 5" 40000000 00000000 3FFFFFFF FFFFFFFF +r 24E0.10 # RP, RM +*Want "LDXBRA +tie odd M3 modes 6, 7" 40000000 00000000 3FFFFFFF FFFFFFFF + +r 24F0.10 # RZ, RP +*Want "LDXBRA -tie odd FPC modes 1, 2" BFFFFFFF FFFFFFFF BFFFFFFF FFFFFFFF +r 2500.10 # RM, RFS +*Want "LDXBRA -tie odd FPC modes 3, 7" C0000000 00000000 BFFFFFFF FFFFFFFF +r 2510.10 # RNTA, RFS +*Want "LDXBRA -tie odd M3 modes 1, 3" C0000000 00000000 BFFFFFFF FFFFFFFF +r 2520.10 # RNTE, RZ +*Want "LDXBRA -tie odd M3 modes 4, 5" C0000000 00000000 BFFFFFFF FFFFFFFF +r 2530.10 # RP, RM +*Want "LDXBRA -tie odd M3 modes 6, 7" BFFFFFFF FFFFFFFF C0000000 00000000 + +r 2540.10 # RZ, RP +*Want "LDXBRA +tie even FPC modes 1, 2" 3FFFFFFF FFFFFFFE 3FFFFFFF FFFFFFFF +r 2550.10 # RM, RFS +*Want "LDXBRA +tie even FPC modes 3, 7" 3FFFFFFF FFFFFFFE 3FFFFFFF FFFFFFFF +r 2560.10 # RNTA, RFS +*Want "LDXBRA +tie even M3 modes 1, 3" 3FFFFFFF FFFFFFFF 3FFFFFFF FFFFFFFF +r 2570.10 # RNTE, RZ +*Want "LDXBRA +tie even M3 modes 4, 5" 3FFFFFFF FFFFFFFE 3FFFFFFF FFFFFFFE +r 2580.10 # RP, RM +*Want "LDXBRA +tie even M3 modes 6, 7" 3FFFFFFF FFFFFFFF 3FFFFFFF FFFFFFFE + +r 2590.10 # RZ, RP +*Want "LDXBRA -tie even FPC modes 1, 2" BFFFFFFF FFFFFFFE BFFFFFFF FFFFFFFE +r 25A0.10 # RM, RFS +*Want "LDXBRA -tie even FPC modes 3, 7" BFFFFFFF FFFFFFFF BFFFFFFF FFFFFFFF +r 25B0.10 # RNTA, RFS +*Want "LDXBRA -tie even M3 modes 1, 3" BFFFFFFF FFFFFFFF BFFFFFFF FFFFFFFF +r 25C0.10 # RNTE, RZ +*Want "LDXBRA -tie even M3 modes 4, 5" BFFFFFFF FFFFFFFE BFFFFFFF FFFFFFFE +r 25D0.10 # RP, RM +*Want "LDXBRA -tie even M3 modes 6, 7" BFFFFFFF FFFFFFFE BFFFFFFF FFFFFFFF + +r 25E0.10 # RZ, RP +*Want "LDXBRA +false exact FPC modes 1, 2" 3FFFFFFF FFFFFFFF 40000000 00000000 +r 25F0.10 # RM, RFS +*Want "LDXBRA +false exact FPC modes 3, 7" 3FFFFFFF FFFFFFFF 3FFFFFFF FFFFFFFF +r 2600.10 # RNTA, RFS +*Want "LDXBRA +false exact M3 modes 1, 3" 3FFFFFFF FFFFFFFF 3FFFFFFF FFFFFFFF +r 2610.10 # RNTE, RZ +*Want "LDXBRA +false exact M3 modes 4, 5" 3FFFFFFF FFFFFFFF 3FFFFFFF FFFFFFFF +r 2620.10 # RP, RM +*Want "LDXBRA +false exact M3 modes 6, 7" 40000000 00000000 3FFFFFFF FFFFFFFF + +r 2630.10 # RZ, RP +*Want "LDXBRA -false exact FPC modes 1, 2" BFFFFFFF FFFFFFFF BFFFFFFF FFFFFFFF +r 2640.10 # RM, RFS +*Want "LDXBRA -false exact FPC modes 3, 7" C0000000 00000000 BFFFFFFF FFFFFFFF +r 2650.10 # RNTA, RFS +*Want "LDXBRA -false exact M3 modes 1, 3" BFFFFFFF FFFFFFFF BFFFFFFF FFFFFFFF +r 2660.10 # RNTE, RZ +*Want "LDXBRA -false exact M3 modes 4, 5" BFFFFFFF FFFFFFFF BFFFFFFF FFFFFFFF +r 2670.10 # RP, RM +*Want "LDXBRA -false exact M3 modes 6, 7" BFFFFFFF FFFFFFFF C0000000 00000000 + +r 2680.10 # RZ, RP +*Want "LDXBRA +near zero FPC modes 1, 2" 3FFFFFFF FFFFFFFF 40000000 00000000 +r 2690.10 # RM, RFS +*Want "LDXBRA +near zero FPC modes 3, 7" 3FFFFFFF FFFFFFFF 3FFFFFFF FFFFFFFF +r 26A0.10 # RNTA, RFS +*Want "LDXBRA +near zero M3 modes 1, 3" 3FFFFFFF FFFFFFFF 3FFFFFFF FFFFFFFF +r 26B0.10 # RNTE, RZ +*Want "LDXBRA +near zero M3 modes 4, 5" 3FFFFFFF FFFFFFFF 3FFFFFFF FFFFFFFF +r 26C0.10 # RP, RM +*Want "LDXBRA +near zero M3 modes 6, 7" 40000000 00000000 3FFFFFFF FFFFFFFF + +r 26D0.10 # RZ, RP +*Want "LDXBRA -near zero FPC modes 1, 2" BFFFFFFF FFFFFFFF BFFFFFFF FFFFFFFF +r 26E0.10 # RM, RFS +*Want "LDXBRA -near zero FPC modes 3, 7" C0000000 00000000 BFFFFFFF FFFFFFFF +r 26F0.10 # RNTA, RFS +*Want "LDXBRA -near zero M3 modes 1, 3" BFFFFFFF FFFFFFFF BFFFFFFF FFFFFFFF +r 2700.10 # RNTE, RZ +*Want "LDXBRA -near zero M3 modes 4, 5" BFFFFFFF FFFFFFFF BFFFFFFF FFFFFFFF +r 2710.10 # RP, RM +*Want "LDXBRA -near zero M3 modes 6, 7" BFFFFFFF FFFFFFFF C0000000 00000000 + +r 2720.10 # RZ, RP +*Want "LDXBRA +near +inf FPC modes 1, 2" 3FFFFFFF FFFFFFFF 40000000 00000000 +r 2730.10 # RM, RFS +*Want "LDXBRA +near +inf FPC modes 3, 7" 3FFFFFFF FFFFFFFF 3FFFFFFF FFFFFFFF +r 2740.10 # RNTA, RFS +*Want "LDXBRA +near +inf M3 modes 1, 3" 40000000 00000000 3FFFFFFF FFFFFFFF +r 2750.10 # RNTE, RZ +*Want "LDXBRA +near +inf M3 modes 4, 5" 40000000 00000000 3FFFFFFF FFFFFFFF +r 2760.10 # RP, RM +*Want "LDXBRA +near +inf M3 modes 6, 7" 40000000 00000000 3FFFFFFF FFFFFFFF + +r 2770.10 # RZ, RP +*Want "LDXBRA -near -inf FPC modes 1, 2" BFFFFFFF FFFFFFFF BFFFFFFF FFFFFFFF +r 2780.10 # RM, RFS +*Want "LDXBRA -near -inf FPC modes 3, 7" C0000000 00000000 BFFFFFFF FFFFFFFF +r 2790.10 # RNTA, RFS +*Want "LDXBRA -near -inf M3 modes 1, 3" C0000000 00000000 BFFFFFFF FFFFFFFF +r 27A0.10 # RNTE, RZ +*Want "LDXBRA -near -inf M3 modes 4, 5" C0000000 00000000 BFFFFFFF FFFFFFFF +r 27B0.10 # RP, RM +*Want "LDXBRA -near -inf M3 modes 6, 7" BFFFFFFF FFFFFFFF C0000000 00000000 + +r 27C0.10 # RZ, RP +*Want "LDXBRA +overflow FPC modes 1, 2" 7FEFFFFF FFFFFFFF 7FF00000 00000000 +r 27D0.10 # RM, RFS +*Want "LDXBRA +overflow FPC modes 3, 7" 7FEFFFFF FFFFFFFF 7FEFFFFF FFFFFFFF +r 27E0.10 # RNTA, RFS +*Want "LDXBRA +overflow M3 modes 1, 3" 7FF00000 00000000 7FEFFFFF FFFFFFFF +r 27F0.10 # RNTE, RZ +*Want "LDXBRA +overflow M3 modes 4, 5" 7FF00000 00000000 7FEFFFFF FFFFFFFF +r 2800.10 # RP, RM +*Want "LDXBRA +overflow M3 modes 6, 7" 7FF00000 00000000 7FEFFFFF FFFFFFFF + +r 2810.10 # RZ, RP +*Want "LDXBRA -overflow FPC modes 1, 2" FFEFFFFF FFFFFFFF FFEFFFFF FFFFFFFF +r 2820.10 # RM, RFS +*Want "LDXBRA -overflow FPC modes 3, 7" FFF00000 00000000 FFEFFFFF FFFFFFFF +r 2830.10 # RNTA, RFS +*Want "LDXBRA -overflow M3 modes 1, 3" FFF00000 00000000 FFEFFFFF FFFFFFFF +r 2840.10 # RNTE, RZ +*Want "LDXBRA -overflow M3 modes 4, 5" FFF00000 00000000 FFEFFFFF FFFFFFFF +r 2850.10 # RP, RM +*Want "LDXBRA -overflow M3 modes 6, 7" FFEFFFFF FFFFFFFF FFF00000 00000000 + +r 2860.10 # RZ, RP +*Want "LDXBRA +tiny tie odd FPC modes 1, 2" 00000000 00000000 00000000 00000001 +r 2870.10 # RM, RFS +*Want "LDXBRA +tiny tie odd FPC modes 3, 7" 00000000 00000000 00000000 00000001 +r 2880.10 # RNTA, RFS +*Want "LDXBRA +tiny tie odd M3 modes 1, 3" 00000000 00000001 00000000 00000001 +r 2890.10 # RNTE, RZ +*Want "LDXBRA +tiny tie odd M3 modes 4, 5" 00000000 00000000 00000000 00000000 +r 28A0.10 # RP, RM +*Want "LDXBRA +tiny tie odd M3 modes 6, 7" 00000000 00000001 00000000 00000000 + +r 28B0.10 # RZ, RP +*Want "LDXBRA -tiny tie odd FPC modes 1, 2" 80000000 00000000 80000000 00000000 +r 28C0.10 # RM, RFS +*Want "LDXBRA -tiny tie odd FPC modes 3, 7" 80000000 00000001 80000000 00000001 +r 28D0.10 # RNTA, RFS +*Want "LDXBRA -tiny tie odd M3 modes 1, 3" 80000000 00000001 80000000 00000001 +r 28E0.10 # RNTE, RZ +*Want "LDXBRA -tiny tie odd M3 modes 4, 5" 80000000 00000000 80000000 00000000 +r 28F0.10 # RP, RM +*Want "LDXBRA -tiny tie odd M3 modes 6, 7" 80000000 00000000 80000000 00000001 + + +# Extended BFP inputs rounded to long BFP - rounding mode test FPCR contents +*Compare +r 2B00.10 +*Want "LDXBRA +exact FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 2B10.10 +*Want "LDXBRA +exact M3 modes 1, 3-5 FPCR" 00000000 00000000 00000000 00000000 +r 2B20.08 +*Want "LDXBRA +exact M3 modes 6, 7 FCPR" 00000000 00000000 + +r 2B30.10 +*Want "LDXBRA -exact FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 2B40.10 +*Want "LDXBRA -exact M3 modes 1, 3-5 FPCR" 00000000 00000000 00000000 00000000 +r 2B50.08 +*Want "LDXBRA -exact M3 modes 6, 7 FCPR" 00000000 00000000 + +r 2B60.10 +*Want "LDXBRA +tie odd FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 2B70.10 +*Want "LDXBRA +tie odd M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 2B80.08 +*Want "LDXBRA +tie odd M3 modes 6, 7 FCPR" 00080000 00080000 + +r 2B90.10 +*Want "LDXBRA -tie odd FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 2BA0.10 +*Want "LDXBRA -tie odd M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 2BB0.08 +*Want "LDXBRA -tie odd M3 modes 6, 7 FCPR" 00080000 00080000 + +r 2BC0.10 +*Want "LDXBRA +tie even FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 2BD0.10 +*Want "LDXBRA +tie even M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 2BE0.08 +*Want "LDXBRA +tie even M3 modes 6, 7 FCPR" 00080000 00080000 + +r 2BF0.10 +*Want "LDXBRA -tie even FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 2C00.10 +*Want "LDXBRA -tie even M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 2C10.08 +*Want "LDXBRA -tie even M3 modes 6, 7 FCPR" 00080000 00080000 + +r 2C20.10 +*Want "LDXBRA +false exact FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 2C30.10 +*Want "LDXBRA +false exact M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 2C40.08 +*Want "LDXBRA +false exact M3 modes 6, 7 FCPR" 00080000 00080000 + +r 2C50.10 +*Want "LDXBRA -false exact FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 2C60.10 +*Want "LDXBRA -false exact M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 2C70.08 +*Want "LDXBRA -false exact M3 modes 6, 7 FCPR" 00080000 00080000 + +r 2C80.10 +*Want "LDXBRA +near zero FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 2C90.10 +*Want "LDXBRA +near zero M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 2CA0.08 +*Want "LDXBRA +near zero M3 modes 6, 7 FCPR" 00080000 00080000 + +r 2CB0.10 +*Want "LDXBRA -near zero FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 2CC0.10 +*Want "LDXBRA -near zero M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 2CD0.08 +*Want "LDXBRA -near zero M3 modes 6, 7 FCPR" 00080000 00080000 + +r 2CE0.10 +*Want "LDXBRA +near +inf FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 2CF0.10 +*Want "LDXBRA +near +inf M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 2D00.08 +*Want "LDXBRA +near +inf M3 modes 6, 7 FCPR" 00080000 00080000 + +r 2D10.10 +*Want "LDXBRA -near -inf FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 2D20.10 +*Want "LDXBRA -near -inf M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 2D30.08 +*Want "LDXBRA -near -inf M3 modes 6, 7 FCPR" 00080000 00080000 + +*Compare +r 2D40.10 # RZ, RP, RM, RFS +*Want "LDXBRA +overflow FPCR modes 1-3, 7 FPCR" 00000001 00200002 00000003 00000007 +r 2D50.10 # RNTA, RFS, RNTE, RZ +*Want "LDXBRA +overflow M3 modes 1, 3-5 FPCR" 00280000 00080000 00280000 00080000 +r 2D60.08 # RP, RM +*Want "LDXBRA +overflow M3 modes 6, 7 FPCR" 00280000 00080000 + +*Compare +r 2D70.10 # RZ, RP, RM, RFS +*Want "LDXBRA -overflow FPCR modes 1-3, 7 FPCR" 00000001 00000002 00200003 00000007 +r 2D80.10 # RNTA, RFS, RNTE, RZ +*Want "LDXBRA -overflow M3 modes 1, 3-5 FPCR" 00280000 00080000 00280000 00080000 +r 2D90.08 # RP, RM +*Want "LDXBRA -overflow M3 modes 6, 7 FPCR" 00080000 00280000 + +*Compare +r 2DA0.10 # RZ, RP, RM, RFS +*Want "LDXBRA +tiny tie odd FPCR modes 1-3, 7 FPCR" 00100001 00100002 00100003 00100007 +r 2DB0.10 # RNTA, RFS, RNTE, RZ +*Want "LDXBRA +tiny tie odd M3 modes 1, 3-5 FPCR" 00180000 00180000 00180000 00180000 +r 2DC0.08 # RP, RM +*Want "LDXBRA +tiny tie odd M3 modes 6, 7 FPCR" 00180000 00180000 + +*Compare +r 2DD0.10 # RZ, RP, RM, RFS +*Want "LDXBRA -tiny tie odd FPCR modes 1-3, 7 FPCR" 00100001 00100002 00100003 00100007 +r 2DE0.10 # RNTA, RFS, RNTE, RZ +*Want "LDXBRA -tiny tie odd M3 modes 1, 3-5 FPCR" 00180000 00180000 00180000 00180000 +r 2DF0.08 # RP, RM +*Want "LDXBRA -tiny tie odd M3 modes 6, 7 FPCR" 00180000 00180000 + + + +*Done + diff --git a/tests/bfp-003-loadfpi.asm b/tests/bfp-003-loadfpi.asm new file mode 100644 index 000000000..50c5cf32c --- /dev/null +++ b/tests/bfp-003-loadfpi.asm @@ -0,0 +1,778 @@ + TITLE 'bfp-003-loadfpi.asm: Test IEEE Load FP Integer' +*********************************************************************** +* +*Testcase IEEE LOAD FP INTEGER +* Test case capability includes IEEE exceptions trappable and +* otherwise. Test results, FPCR flags, and any DXC are saved for all +* tests. Load FP Integer does not set the condition code. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* bfp-003-loadfpi.asm +* +* This assembly-language source file is part of the +* Hercules Decimal Floating Point Validation Package +* by Stephen R. Orso +* +* Copyright 2016 by Stephen R Orso. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* +* 3. The name of the author may not be used to endorse or promote +* products derived from this software without specific prior written +* permission. +* +* DISCLAMER: THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* HOLDER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* Tests the following three conversion instructions +* LOAD FP INTEGER (short BFP, RRE) +* LOAD FP INTEGER (long BFP, RRE) +* LOAD FP INTEGER (extended BFP, RRE) +* LOAD FP INTEGER (short BFP, RRF-e) +* LOAD FP INTEGER (long BFP, RRF-e) +* LOAD FP INTEGER (extended BFP, RRF-e) +* +* Test data is compiled into this program. The test script that runs +* this program can provide alternative test data through Hercules R +* commands. +* +* Test Case Order +* 1) Short BFP inexact masking/trapping & SNaN/QNaN tests +* 2) Short BFP rounding mode tests +* 3) Long BFP inexact masking/trapping & SNaN/QNaN tests +* 4) Long BFP rounding mode tests +* 5) Extended BFP inexact masking/trapping & SNaN/QNaN tests +* 6) Extended BFP rounding mode tests +* +* Provided test data is 1, 1.5, SNaN, and QNaN. +* The second value will trigger an inexact exception when LOAD FP +* INTEGER is executed. The final value will trigger an invalid +* exception. +* Provided test data for rounding tests is +* -9.5, -5.5, -2.5, -1.5, -0.5, +0.5, +1.5, +2.5, +5.5, +9.5 +* This data is taken from Table 9-11 on page 9-16 of SA22-7832-10. +* +* Three input test data sets are provided, one each for short, long, +* and extended precision BFP inputs. +* +* Also tests the following floating point support instructions +* LOAD (Short) +* LOAD (Long) +* LFPC (Load Floating Point Control Register) +* SRNMB (Set BFP Rounding Mode 2-bit) +* SRNMB (Set BFP Rounding Mode 3-bit) +* STORE (Short) +* STORE (Long) +* STFPC (Store Floating Point Control Register) +* +*********************************************************************** + SPACE 2 + MACRO + PADCSECT &ENDLABL +.* +.* Macro to pad the CSECT to include result data areas if this test +.* program is not being assembled using asma. asma generates a core +.* image that is loaded by the loadcore command, and because the +.* core image is a binary stored in Github, it makes sense to make +.* this small effort to keep the core image small. +.* + AIF (D'&ENDLABL).GOODPAD + MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + MNOTE *,'No CSECT padding performed' + MEXIT +.* +.GOODPAD ANOP Label valid. See if we're on asma + AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + ORG &ENDLABL-1 Not ASMA. Pad CSECT + MEXIT +.* +.NOPAD ANOP + MNOTE *,'asma detected; no CSECT padding performed' + MEND +* +* Note: for compatibility with the z/CMS test rig, do not change +* or use R11, R14, or R15. Everything else is fair game. +* +BFPLDFPI START 0 +R0 EQU 0 Work register for cc extraction +R1 EQU 1 Available +R2 EQU 2 Holds count of test input values +R3 EQU 3 Points to next test input value(s) +R4 EQU 4 Available +R5 EQU 5 Available +R6 EQU 6 Available +R7 EQU 7 Pointer to next result value(s) +R8 EQU 8 Pointer to next FPCR result +R9 EQU 9 Available +R10 EQU 10 Pointer to test address list +R11 EQU 11 **Reserved for z/CMS test rig +R12 EQU 12 Holds number of test cases in set +R13 EQU 13 Mainline return address +R14 EQU 14 **Return address for z/CMS test rig +R15 EQU 15 **Base register on z/CMS or Hyperion +* +* Floating Point Register equates to keep the cross reference clean +* +FPR0 EQU 0 +FPR1 EQU 1 +FPR2 EQU 2 +FPR3 EQU 3 +FPR4 EQU 4 +FPR5 EQU 5 +FPR6 EQU 6 +FPR7 EQU 7 +FPR8 EQU 8 +FPR9 EQU 9 +FPR10 EQU 10 +FPR11 EQU 11 +FPR12 EQU 12 +FPR13 EQU 13 +FPR14 EQU 14 +FPR15 EQU 15 +* + USING *,R15 +* Above works on real iron (R15=0 after sysclear) +* and in z/CMS (R15 points to start of load module) +* + SPACE 2 +*********************************************************************** +* +* Low core definitions, Restart PSW, and Program Check Routine. +* +*********************************************************************** + SPACE 2 + ORG BFPLDFPI+X'8E' Program check interrution code +PCINTCD DS H +* +PCOLDPSW EQU BFPLDFPI+X'150' z/Arch Program check old PSW +* + ORG BFPLDFPI+X'1A0' z/Arch Restart PSW + DC X'0000000180000000',AD(START) +* + ORG BFPLDFPI+X'1D0' z/Arch Program check old PSW + DC X'0000000000000000',AD(PROGCHK) +* +* Program check routine. If Data Exception, continue execution at +* the instruction following the program check. Otherwise, hard wait. +* No need to collect data. All interesting DXC stuff is captured +* in the FPCR. +* +PROGCHK DS 0H Program check occured... + CLI PCINTCD+1,X'07' Data Exception? + JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) + LPSWE PCOLDPSW ..yes, resume program execution +PCNOTDTA DS 0H + LTR R14,R14 Return address provided? + BNZR R14 Yes, return to z/CMS test rig. + LPSWE HARDWAIT Not data exception, enter disabled wait. + EJECT +*********************************************************************** +* +* Main program. Enable Advanced Floating Point, process test cases. +* +*********************************************************************** + SPACE 2 +START DS 0H + STCTL R0,R0,CTLR0 Store CR0 to enable AFP + OI CTLR0+1,X'04' Turn on AFP bit + LCTL R0,R0,CTLR0 Reload updated CR0 +* + LA R10,SHORTS Point to short BFP test inputs + BAS R13,FIEBR Convert short BFP to integer short BFP + LA R10,RMSHORTS Point to short BFP rounding test data + BAS R13,FIEBRA Convert using all rounding mode options +* + LA R10,LONGS Point to long BFP test inputs + BAS R13,FIDBR Convert long BFP to integer long BFP + LA R10,RMLONGS Point to long BFP rounding test data + BAS R13,FIDBRA Convert using all rounding mode options +* + LA R10,EXTDS Point to extended BFP test inputs + BAS R13,FIXBR Convert extd BFP to integer extd BFP + LA R10,RMEXTDS Point to extended BFP rounding test data + BAS R13,FIXBRA Convert using all rounding mode options +* + LTR R14,R14 Return address provided? + BNZR R14 ..Yes, return to z/CMS test rig. + LPSWE WAITPSW All done +* + DS 0D Ensure correct alignment for psw +WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end +* +CTLR0 DS F +FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags +* +* Input values parameter list, four fullwords: +* 1) Count, +* 2) Address of inputs, +* 3) Address to place results, and +* 4) Address to place DXC/Flags/cc values. +* + ORG BFPLDFPI+X'300' +SHORTS DS 0F Inputs for short BFP testing + DC A(SBFPCT/4) + DC A(SBFPIN) + DC A(SBFPOUT) + DC A(SBFPFLGS) +* +LONGS DS 0F Inputs for long BFP testing + DC A(LBFPCT/8) + DC A(LBFPIN) + DC A(LBFPOUT) + DC A(LBFPFLGS) +* +EXTDS DS 0F Inputs for Extended BFP testing + DC A(XBFPCT/16) + DC A(XBFPIN) + DC A(XBFPOUT) + DC A(XBFPFLGS) +* +RMSHORTS DS 0F Inputs for short BFP rounding testing + DC A(SBFPRMCT/4) + DC A(SBFPINRM) + DC A(SBFPRMO) + DC A(SBFPRMOF) +* +RMLONGS DS 0F Inputs for long BFP rounding testing + DC A(LBFPRMCT/8) + DC A(LBFPINRM) + DC A(LBFPRMO) + DC A(LBFPRMOF) +* +RMEXTDS DS 0F Inputs for extd BFP rounding testing + DC A(XBFPRMCT/16) + DC A(XBFPINRM) + DC A(XBFPRMO) + DC A(XBFPRMOF) + EJECT +*********************************************************************** +* +* Round short BFP inputs to integer short BFP. A pair of results is +* generated for each input: one with all exceptions non-trappable, and +* the second with all exceptions trappable. The FPCR is stored for +* each result. +* +*********************************************************************** + SPACE 2 +FIEBR DS 0H Round short BFP inputs to integer BFP + LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LE FPR0,0(,R3) Get short BFP test value + LFPC FPCREGNT Set exceptions non-trappable + FIEBR FPR1,0,FPR0 Cvt float in FPR0 to int float in FPR1 + STE FPR1,0(,R7) Store short BFP result + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LZER FPR1 Eliminate any residual results + FIEBR FPR1,0,FPR0 Cvt float in FPR0 to int float in FPR1 + STE FPR1,4(,R7) Store short BFP result + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LA R3,4(,R3) Point to next input value + LA R7,8(,R7) Point to next rounded rusult value pair + LA R8,8(,R8) Point to next FPCR result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert short BFP to integer BFP using each possible rounding mode. +* Ten test results are generated for each input. A 48-byte test result +* section is used to keep results sets aligned on a quad-double word. +* +* The first four tests use rounding modes specified in the FPCR with +* the IEEE Inexact exception supressed. SRNM (2-bit) is used for +* the first two FPCR-controlled tests and SRNMB (3-bit) is used for +* the last two To get full coverage of that instruction pair. +* +* The next six results use instruction-specified rounding modes. +* +* The default rounding mode (0 for RNTE) is not tested in this section; +* prior tests used the default rounding mode. RNTE is tested +* explicitly as a rounding mode in this section. +* +*********************************************************************** + SPACE 2 +FIEBRA LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LE FPR0,0(,R3) Get short BFP test value +* +* Test cases using rounding mode specified in the FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 1 SET FPCR to RZ, towards zero. + FIEBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked + STE FPR1,0*4(,R7) Store integer BFP result + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 2 SET FPCR to RP, to +infinity + FIEBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked + STE FPR1,1*4(,R7) Store integer BFP result + STFPC 1*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 3 SET FPCR to RM, to -infinity + FIEBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked + STE FPR1,2*4(,R7) Store integer BFP result + STFPC 2*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 7 RPS, Prepare for Shorter Precision + FIEBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked + STE FPR1,3*4(,R7) Store integer BFP result + STFPC 3*4(R8) Store resulting FPCR flags and DXC +* +* Test cases using rounding mode specified in the instruction M3 field +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + FIEBRA FPR1,1,FPR0,B'0000' RNTA, to nearest, ties away + STE FPR1,4*4(,R7) Store integer BFP result + STFPC 4*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + FIEBRA FPR1,3,FPR0,B'0000' RFS, prepare for shorter precision + STE FPR1,5*4(,R7) Store integer BFP result + STFPC 5*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + FIEBRA FPR1,4,FPR0,B'0000' RNTE, to nearest, ties to even + STE FPR1,6*4(,R7) Store integer BFP result + STFPC 6*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + FIEBRA FPR1,5,FPR0,B'0000' RZ, toward zero + STE FPR1,7*4(,R7) Store integer BFP result + STFPC 7*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + FIEBRA FPR1,6,FPR0,B'0000' RP, to +inf + STE FPR1,8*4(,R7) Store integer BFP result + STFPC 8*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + FIEBRA FPR1,7,FPR0,B'0000' RM, to -inf + STE FPR1,9*4(,R7) Store integer BFP result + STFPC 9*4(R8) Store resulting FPCR flags and DXC +* + LA R3,4(,R3) Point to next input values + LA R7,12*4(,R7) Point to next short BFP converted values + LA R8,12*4(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Round long BFP inputs to integer long BFP. A pair of results is +* generated for each input: one with all exceptions non-trappable, and +* the second with all exceptions trappable. The FPCR is stored for +* each result. +* +*********************************************************************** + SPACE 2 +FIDBR LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LD FPR0,0(,R3) Get long BFP test value + LFPC FPCREGNT Set exceptions non-trappable + FIDBR FPR1,0,FPR0 Cvt float in FPR0 to int float in FPR1 + STD R1,0(,R7) Store long BFP result + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LZDR FPR1 Eliminate any residual results + FIDBR FPR1,0,FPR0 Cvt float in FPR0 to int float in FPR1 + STD FPR1,8(,R7) Store int-32 result + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LA R3,8(,R3) Point to next input value + LA R7,16(,R7) Point to next rounded long BFP result pair + LA R8,8(,R8) Point to next FPCR result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert long BFP to integers using each possible rounding mode. +* Ten test results are generated for each input. A 48-byte test result +* section is used to keep results sets aligned on a quad-double word. +* +* The first four tests use rounding modes specified in the FPCR with +* the IEEE Inexact exception supressed. SRNM (2-bit) is used for +* the first two FPCR-controlled tests and SRNMB (3-bit) is used for +* the last two To get full coverage of that instruction pair. +* +* The next six results use instruction-specified rounding modes. +* +* The default rounding mode (0 for RNTE) is not tested in this section; +* prior tests used the default rounding mode. RNTE is tested +* explicitly as a rounding mode in this section. +* +*********************************************************************** + SPACE 2 +FIDBRA LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LD FPR0,0(,R3) Get long BFP test value +* +* Test cases using rounding mode specified in the FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 1 SET FPCR to RZ, towards zero. + FIDBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked + STD FPR1,0*8(,R7) Store integer BFP result + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 2 SET FPCR to RP, to +infinity + FIDBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked + STD FPR1,1*8(,R7) Store integer BFP result + STFPC 1*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 3 SET FPCR to RM, to -infinity + FIDBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked + STD FPR1,2*8(,R7) Store integer BFP result + STFPC 2*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 7 RPS, Prepare for Shorter Precision + FIDBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked + STD FPR1,3*8(,R7) Store integer BFP result + STFPC 3*4(R8) Store resulting FPCR flags and DXC +* +* Test cases using rounding mode specified in the instruction M3 field +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + FIDBRA FPR1,1,FPR0,B'0000' RNTA, to nearest, ties away + STD FPR1,4*8(,R7) Store integer BFP result + STFPC 4*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + FIDBRA FPR1,3,FPR0,B'0000' RFS, prepare for shorter precision + STD FPR1,5*8(,R7) Store integer BFP result + STFPC 5*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + FIDBRA FPR1,4,FPR0,B'0000' RNTE, to nearest, ties to even + STD FPR1,6*8(,R7) Store integer BFP result + STFPC 6*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + FIDBRA FPR1,5,FPR0,B'0000' RZ, toward zero + STD FPR1,7*8(,R7) Store integer BFP result + STFPC 7*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + FIDBRA FPR1,6,FPR0,B'0000' RP, to +inf + STD FPR1,8*8(,R7) Store integer BFP result + STFPC 8*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + FIDBRA FPR1,7,FPR0,B'0000' RM, to -inf + STD FPR1,9*8(,R7) Store integer BFP result + STFPC 9*4(R8) Store resulting FPCR flags and DXC +* + LA R3,8(,R3) Point to next input values + LA R7,10*8(,R7) Point to next long BFP converted values + LA R8,12*4(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Round extended BFP to integer extended BFP. A pair of results is +* generated for each input: one with all exceptions non-trappable, and +* the second with all exceptions trappable. The FPCR is stored for +* each result. +* +*********************************************************************** + SPACE 2 +FIXBR LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LD FPR0,0(,R3) Get extended BFP test value part 1 + LD FPR2,8(,R3) Get extended BFP test value part 2 + LFPC FPCREGNT Set exceptions non-trappable + FIXBR FPR1,0,FPR0 Cvt FPR0-FPR2 to int float in FPR1-FPR3 + STD FPR1,0(,R7) Store integer BFP result part 1 + STD FPR3,8(,R7) Store integer BFP result part 2 + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LZXR FPR1 Eliminate any residual results + FIXBR FPR1,0,FPR0 Cvt FPR0-FPR2 to int float in FPR1-FPR3 + STD FPR1,16(,R7) Store integer BFP result part 1 + STD FPR3,24(,R7) Store integer BFP result part 2 + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LA R3,16(,R3) Point to next extended BFP input value + LA R7,32(,R7) Point to next extd BFP rounded result pair + LA R8,8(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert extended BFP to integers using each possible rounding mode. +* Ten test results are generated for each input. A 48-byte test result +* section is used to keep results sets aligned on a quad-double word. +* +* The first four tests use rounding modes specified in the FPCR with +* the IEEE Inexact exception supressed. SRNM (2-bit) is used for +* the first two FPCR-controlled tests and SRNMB (3-bit) is used for +* the last two To get full coverage of that instruction pair. +* +* The next six results use instruction-specified rounding modes. +* +* The default rounding mode (0 for RNTE) is not tested in this section; +* prior tests used the default rounding mode. RNTE is tested +* explicitly as a rounding mode in this section. +* +*********************************************************************** + SPACE 2 +FIXBRA LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LD FPR0,0(,R3) Get extended BFP test value part 1 + LD FPR2,8(,R3) Get extended BFP test value part 2 +* +* Test cases using rounding mode specified in the FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 1 SET FPCR to RZ, towards zero. + FIXBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked + STD FPR1,0*16(,R7) Store integer BFP result part 1 + STD FPR3,(0*16)+8(,R7) Store integer BFP result part 2 + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 2 SET FPCR to RP, to +infinity + FIXBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked + STD FPR1,1*16(,R7) Store integer BFP result part 1 + STD FPR3,(1*16)+8(,R7) Store integer BFP result part 2 + STFPC 1*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 3 SET FPCR to RM, to -infinity + FIXBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked + STD FPR1,2*16(,R7) Store integer BFP result part 1 + STD FPR3,(2*16)+8(,R7) Store integer BFP result part 2 + STFPC 2*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 7 RFS, Prepare for Shorter Precision + FIXBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked + STD FPR1,3*16(,R7) Store integer BFP result part 1 + STD FPR3,(3*16)+8(,R7) Store integer BFP result part 2 + STFPC 3*4(R8) Store resulting FPCR flags and DXC +* +* Test cases using rounding mode specified in the instruction M3 field +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + FIXBRA FPR1,1,FPR0,B'0000' RNTA, to nearest, ties away + STD FPR1,4*16(,R7) Store integer BFP result part 1 + STD FPR3,(4*16)+8(,R7) Store integer BFP result part 2 + STFPC 4*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + FIXBRA FPR1,3,FPR0,B'0000' RFS, prepare for shorter precision + STD FPR1,5*16(,R7) Store integer BFP result part 1 + STD FPR3,(5*16)+8(,R7) Store integer BFP result part 2 + STFPC 5*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + FIXBRA FPR1,4,FPR0,B'0000' RNTE, to nearest, ties to even + STD FPR1,6*16(,R7) Store integer BFP result part 1 + STD FPR3,(6*16)+8(,R7) Store integer BFP result part 2 + STFPC 6*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + FIXBRA FPR1,5,FPR0,B'0000' RZ, toward zero + STD FPR1,7*16(,R7) Store integer BFP result part 1 + STD FPR3,(7*16)+8(,R7) Store integer BFP result part 2 + STFPC 7*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + FIXBRA FPR1,6,FPR0,B'0000' RP, to +inf + STD FPR1,8*16(,R7) Store integer BFP result part 1 + STD FPR3,(8*16)+8(,R7) Store integer BFP result part 2 + STFPC 8*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + FIXBRA FPR1,7,FPR0,B'0000' RM, to -inf + STD FPR1,9*16(,R7) Store integer BFP result part 1 + STD FPR3,(9*16)+8(,R7) Store integer BFP result part 2 + STFPC 9*4(R8) Store resulting FPCR flags and DXC +* + LA R3,16(,R3) Point to next input value + LA R7,10*16(,R7) Point to next long BFP converted values + LA R8,12*4(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Short integer inputs for Load FP Integer testing. The same +* values are used for short, long, and extended formats. +* +*********************************************************************** + SPACE 2 +SBFPIN DS 0F Inputs for short BFP testing + DC X'3F800000' +1.0 Exact + DC X'BFC00000' -1.5 Inexact, incremented + DC X'40200000' +2.5 Inexact only + DC X'7F810000' SNaN + DC X'7FC10000' QNaN + DC X'3F400000' +.75 Inexact, incremented + DC X'BE800000' -.25 Inexact +SBFPCT EQU *-SBFPIN Count of short BFP in list * 4 +* +SBFPINRM DS 0F Inputs for short BFP rounding testing + DC X'C1180000' -9.5 + DC X'C0B00000' -5.5 + DC X'C0200000' -2.5 + DC X'BFC00000' -1.5 + DC X'BF000000' -0.5 + DC X'3F000000' +0.5 + DC X'3FC00000' +1.5 + DC X'40200000' +2.5 + DC X'40B00000' +5.5 + DC X'41180000' +9.5 + DC X'3F400000' +.75 + DC X'BE800000' -.25 +SBFPRMCT EQU *-SBFPINRM Count of short BFP rounding tests * 4 +* +LBFPIN DS 0F Inputs for long BFP testing + DC X'3FF0000000000000' +1.0 + DC X'BFF8000000000000' -1.5 + DC X'4004000000000000' +2.5 + DC X'7FF0100000000000' SNaN + DC X'7FF8100000000000' QNaN + DC X'3FE8000000000000' +.75 + DC X'BFD0000000000000' -.25 +LBFPCT EQU *-LBFPIN Count of long BFP in list * 8 +* +LBFPINRM DS 0F + DC X'C023000000000000' -9.5 + DC X'C016000000000000' -5.5 + DC X'C004000000000000' -2.5 + DC X'BFF8000000000000' -1.5 + DC X'BFE0000000000000' -0.5 + DC X'3FE0000000000000' +0.5 + DC X'3FF8000000000000' +1.5 + DC X'4004000000000000' +2.5 + DC X'4016000000000000' +5.5 + DC X'4023000000000000' +9.5 + DC X'3FE8000000000000' +.75 + DC X'BFD0000000000000' -.25 +LBFPRMCT EQU *-LBFPINRM Count of long BFP rounding tests * 8 +* +XBFPIN DS 0D Inputs for long BFP testing + DC X'3FFF0000000000000000000000000000' +1.0 + DC X'BFFF8000000000000000000000000000' -1.5 + DC X'40004000000000000000000000000000' +2.5 + DC X'7FFF0100000000000000000000000000' SNaN + DC X'7FFF8100000000000000000000000000' QNaN + DC X'3FFE8000000000000000000000000000' +0.75 + DC X'BFFD0000000000000000000000000000' -0.25 +XBFPCT EQU *-XBFPIN Count of extended BFP in list * 16 +* +XBFPINRM DS 0D + DC X'C0023000000000000000000000000000' -9.5 + DC X'C0016000000000000000000000000000' -5.5 + DC X'C0004000000000000000000000000000' -2.5 + DC X'BFFF8000000000000000000000000000' -1.5 + DC X'BFFE0000000000000000000000000000' -0.5 + DC X'3FFE0000000000000000000000000000' +0.5 + DC X'3FFF8000000000000000000000000000' +1.5 + DC X'40004000000000000000000000000000' +2.5 + DC X'40016000000000000000000000000000' +5.5 + DC X'40023000000000000000000000000000' +9.5 + DC X'3FFE8000000000000000000000000000' +0.75 + DC X'BFFD0000000000000000000000000000' -0.25 +XBFPRMCT EQU *-XBFPINRM Count of extended BFP rounding tests * 16 +* +* Locations for results +* +SBFPOUT EQU BFPLDFPI+X'1000' Integer short BFP rounded results +* ..7 used, room for 16 +SBFPFLGS EQU BFPLDFPI+X'1080' FPCR flags and DXC from short BFP +* ..7 used, room for 16 +SBFPRMO EQU BFPLDFPI+X'1100' Short BFP rounding mode test results +* ..12 used, room for 16 +SBFPRMOF EQU BFPLDFPI+X'1400' Short BFP rounding mode FPCR results +* ..12 used +* +LBFPOUT EQU BFPLDFPI+X'2000' Integer long BFP rounded results +* ..7 used, room for 16 +LBFPFLGS EQU BFPLDFPI+X'2100' FPCR flags and DXC from long BFP +* ..7 used, room for 32 +LBFPRMO EQU BFPLDFPI+X'2200' Long BFP rounding mode test results +* ..12 used, room for 16 +LBFPRMOF EQU BFPLDFPI+X'2800' Long BFP rounding mode FPCR results +* ..12 used +* +XBFPOUT EQU BFPLDFPI+X'3000' Integer extended BFP rounded results +* ..7 used, room for 16 +XBFPFLGS EQU BFPLDFPI+X'3200' FPCR flags and DXC from extended BFP +* ..7 used, room for 32 +XBFPRMO EQU BFPLDFPI+X'3300' Extd BFP rounding mode test results +* ..12 used, room for 16 +XBFPRMOF EQU BFPLDFPI+X'3F00' Extd BFP rounding mode FPCR results +* ..12 used +* +* +ENDLABL EQU BFPLDFPI+X'4800' +* Pad CSECT if not running on ASMA for a stand-alone environment + PADCSECT ENDLABL + END diff --git a/tests/bfp-003-loadfpi.core b/tests/bfp-003-loadfpi.core new file mode 100644 index 000000000..ff53e6c30 Binary files /dev/null and b/tests/bfp-003-loadfpi.core differ diff --git a/tests/bfp-003-loadfpi.list b/tests/bfp-003-loadfpi.list new file mode 100644 index 000000000..1a49dbf71 --- /dev/null +++ b/tests/bfp-003-loadfpi.list @@ -0,0 +1,941 @@ +ASMA Ver. 0.2.0 ieee-loadfpi.asm: Test IEEE Load FP Integer 31 Aug 2016 20:30:05 Page 1 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 2 *********************************************************************** + 3 * + 4 *Testcase IEEE LOAD FP INTEGER + 5 * Test case capability includes IEEE exceptions trappable and + 6 * otherwise. Test results, FPCR flags, and any DXC are saved for all + 7 * tests. Load FP Integer does not set the condition code. + 8 * + 9 *********************************************************************** + + + 11 *********************************************************************** + 12 * + 13 * Tests the following three conversion instructions + 14 * LOAD FP INTEGER (short BFP, RRE) + 15 * LOAD FP INTEGER (long BFP, RRE) + 16 * LOAD FP INTEGER (extended BFP, RRE) + 17 * LOAD FP INTEGER (short BFP, RRF-e) + 18 * LOAD FP INTEGER (long BFP, RRF-e) + 19 * LOAD FP INTEGER (extended BFP, RRF-e) + 20 * + 21 * Test data is compiled into this program. The test script that runs + 22 * this program can provide alternative test data through Hercules R + 23 * commands. + 24 * + 25 * Test Case Order + 26 * 1) Short BFP inexact masking/trapping & SNaN/QNaN tests + 27 * 2) Short BFP rounding mode tests + 28 * 3) Long BFP inexact masking/trapping & SNaN/QNaN tests + 29 * 4) Long BFP rounding mode tests + 30 * 5) Extended BFP inexact masking/trapping & SNaN/QNaN tests + 31 * 6) Extended BFP rounding mode tests + 32 * + 33 * Provided test data is 1, 1.5, SNaN, and QNaN. + 34 * The second value will trigger an inexact exception when LOAD FP + 35 * INTEGER is executed. The final value will trigger an invalid + 36 * exception. + 37 * Provided test data for rounding tests is + 38 * -9.5, -5.5, -2.5, -1.5, -0.5, +0.5, +1.5, +2.5, +5.5, +9.5 + 39 * This data is taken from Table 9-11 on page 9-16 of SA22-7832-10. + 40 * + 41 * Three input test data sets are provided, one each for short, long, + 42 * and extended precision BFP inputs. + 43 * + 44 * Also tests the following floating point support instructions + 45 * LOAD (Short) + 46 * LOAD (Long) + 47 * LFPC (Load Floating Point Control Register) + 48 * SRNMB (Set BFP Rounding Mode 2-bit) + 49 * SRNMB (Set BFP Rounding Mode 3-bit) + 50 * STORE (Short) + 51 * STORE (Long) + 52 * STFPC (Store Floating Point Control Register) + ASMA Ver. 0.2.0 ieee-loadfpi.asm: Test IEEE Load FP Integer 31 Aug 2016 20:30:05 Page 2 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 53 * + 54 *********************************************************************** + + + 56 MACRO + 57 PADCSECT &ENDLABL + 58 .* + 59 .* Macro to pad the CSECT to include result data areas if this test + 60 .* program is not being assembled using asma. asma generates a core + 61 .* image that is loaded by the loadcore command, and because the + 62 .* core image is a binary stored in Github, it makes sense to make + 63 .* this small effort to keep the core image small. + 64 .* + 65 AIF (D'&ENDLABL).GOODPAD + 66 MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + 67 MNOTE *,'No CSECT padding performed' + 68 MEXIT + 69 .* + 70 .GOODPAD ANOP Label valid. See if we're on asma + 71 AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + 72 ORG &ENDLABL-1 Not ASMA. Pad CSECT + 73 MEXIT + 74 .* + 75 .NOPAD ANOP + 76 MNOTE *,'asma detected; no CSECT padding performed' + 77 MEND + 78 * + 79 * Note: for compatibility with the z/CMS test rig, do not change + 80 * or use R11, R14, or R15. Everything else is fair game. + 81 * + 0000000000000000 00000000000008F7 82 BFPLDFPI START 0 + 0000000000000000 0000000000000001 83 R0 EQU 0 Work register for cc extraction + 0000000000000001 0000000000000001 84 R1 EQU 1 + 0000000000000002 0000000000000001 85 R2 EQU 2 Holds count of test input values + 0000000000000003 0000000000000001 86 R3 EQU 3 Points to next test input value(s) + 0000000000000004 0000000000000001 87 R4 EQU 4 Rounding tests inner loop control + 0000000000000005 0000000000000001 88 R5 EQU 5 Rounding tests outer loop control + 0000000000000006 0000000000000001 89 R6 EQU 6 Rounding tests top of inner loop + 0000000000000007 0000000000000001 90 R7 EQU 7 Pointer to next result value(s) + 0000000000000008 0000000000000001 91 R8 EQU 8 Pointer to next FPCR result + 0000000000000009 0000000000000001 92 R9 EQU 9 Rounding tests top of outer loop + 000000000000000A 0000000000000001 93 R10 EQU 10 Pointer to test address list + 000000000000000B 0000000000000001 94 R11 EQU 11 **Reserved for z/CMS test rig + 000000000000000C 0000000000000001 95 R12 EQU 12 Holds number of test cases in set + 000000000000000D 0000000000000001 96 R13 EQU 13 Mainline return address + 000000000000000E 0000000000000001 97 R14 EQU 14 **Return address for z/CMS test rig + 000000000000000F 0000000000000001 98 R15 EQU 15 **Base register on z/CMS or Hyperion + 99 * + 100 * Floating Point Register equates to keep the cross reference clean + 101 * + 0000000000000000 0000000000000001 102 FPR0 EQU 0 + 0000000000000001 0000000000000001 103 FPR1 EQU 1 + ASMA Ver. 0.2.0 ieee-loadfpi.asm: Test IEEE Load FP Integer 31 Aug 2016 20:30:05 Page 3 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 0000000000000002 0000000000000001 104 FPR2 EQU 2 + 0000000000000003 0000000000000001 105 FPR3 EQU 3 + 0000000000000004 0000000000000001 106 FPR4 EQU 4 + 0000000000000005 0000000000000001 107 FPR5 EQU 5 + 0000000000000006 0000000000000001 108 FPR6 EQU 6 + 0000000000000007 0000000000000001 109 FPR7 EQU 7 + 0000000000000008 0000000000000001 110 FPR8 EQU 8 + 0000000000000009 0000000000000001 111 FPR9 EQU 9 + 000000000000000A 0000000000000001 112 FPR10 EQU 10 + 000000000000000B 0000000000000001 113 FPR11 EQU 11 + 000000000000000C 0000000000000001 114 FPR12 EQU 12 + 000000000000000D 0000000000000001 115 FPR13 EQU 13 + 000000000000000E 0000000000000001 116 FPR14 EQU 14 + 000000000000000F 0000000000000001 117 FPR15 EQU 15 + 118 * +0000000000000000 0000000000000000 119 USING *,R15 + 120 * Above works on real iron (R15=0 after sysclear) + 121 * and in z/CMS (R15 points to start of load module) + 122 * + + + 124 *********************************************************************** + 125 * + 126 * Low core definitions, Restart PSW, and Program Check Routine. + 127 * + 128 *********************************************************************** + + +0000000000000000 0000000000000000 000000000000008E 130 ORG BFPLDFPI+X'8E' Program check interrution code +000000000000008E 0000 131 PCINTCD DS H + 132 * + 0000000000000150 0000000000000000 133 PCOLDPSW EQU BFPLDFPI+X'150' z/Arch Program check old PSW + 134 * +0000000000000090 0000000000000090 00000000000001A0 135 ORG BFPLDFPI+X'1A0' z/Arch Restart PSW +00000000000001A0 00000001 80000000 136 DC X'0000000180000000',AD(START) + 137 * +00000000000001B0 00000000000001B0 00000000000001D0 138 ORG BFPLDFPI+X'1D0' z/Arch Program check old PSW +00000000000001D0 00000000 00000000 139 DC X'0000000000000000',AD(PROGCHK) + 140 * + 141 * Program check routine. If Data Exception, continue execution at + 142 * the instruction following the program check. Otherwise, hard wait. + 143 * No need to collect data. All interesting DXC stuff is captured + 144 * in the FPCR. + 145 * +00000000000001E0 146 PROGCHK DS 0H Program check occured... +00000000000001E0 9507 F08F 000000000000008F 147 CLI PCINTCD+1,X'07' Data Exception? +00000000000001E4 A774 0004 00000000000001EC 148 JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) +00000000000001E8 B2B2 F150 0000000000000150 149 LPSWE PCOLDPSW ..yes, resume program execution +00000000000001EC 150 PCNOTDTA DS 0H +00000000000001EC 12EE 151 LTR R14,R14 Return address provided? +00000000000001EE 077E 152 BNZR R14 Yes, return to z/CMS test rig. +00000000000001F0 B2B2 F248 0000000000000248 153 LPSWE HARDWAIT Not data exception, enter disabled wait. + ASMA Ver. 0.2.0 ieee-loadfpi.asm: Test IEEE Load FP Integer 31 Aug 2016 20:30:05 Page 4 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 155 *********************************************************************** + 156 * + 157 * Main program. Enable Advanced Floating Point, process test cases. + 158 * + 159 *********************************************************************** + + +00000000000001F4 161 START DS 0H +00000000000001F4 B600 F258 0000000000000258 162 STCTL R0,R0,CTLR0 Store CR0 to enable AFP +00000000000001F8 9604 F259 0000000000000259 163 OI CTLR0+1,X'04' Turn on AFP bit +00000000000001FC B700 F258 0000000000000258 164 LCTL R0,R0,CTLR0 Reload updated CR0 + 165 * +0000000000000200 41A0 F300 0000000000000300 166 LA R10,SHORTS Point to short BFP test inputs +0000000000000204 4DD0 F360 0000000000000360 167 BAS R13,FIEBR Convert short BFP to integer short BFP +0000000000000208 41A0 F330 0000000000000330 168 LA R10,RMSHORTS Point to short BFP rounding test data +000000000000020C 4DD0 F3A6 00000000000003A6 169 BAS R13,FIEBRA Convert using all rounding mode options + 170 * +0000000000000210 41A0 F310 0000000000000310 171 LA R10,LONGS Point to long BFP test inputs +0000000000000214 4DD0 F478 0000000000000478 172 BAS R13,FIDBR Convert long BFP to integer long BFP +0000000000000218 41A0 F340 0000000000000340 173 LA R10,RMLONGS Point to long BFP rounding test data +000000000000021C 4DD0 F4BE 00000000000004BE 174 BAS R13,FIDBRA Convert using all rounding mode options + 175 * +0000000000000220 41A0 F320 0000000000000320 176 LA R10,EXTDS Point to extended BFP test inputs +0000000000000224 4DD0 F590 0000000000000590 177 BAS R13,FIXBR Convert extd BFP to integer extd BFP +0000000000000228 41A0 F350 0000000000000350 178 LA R10,RMEXTDS Point to extended BFP rounding test data +000000000000022C 4DD0 F5E2 00000000000005E2 179 BAS R13,FIXBRA Convert using all rounding mode options + 180 * +0000000000000230 12EE 181 LTR R14,R14 Return address provided? +0000000000000232 077E 182 BNZR R14 ..Yes, return to z/CMS test rig. +0000000000000234 B2B2 F238 0000000000000238 183 LPSWE WAITPSW All done + 184 * +0000000000000238 185 DS 0D Ensure correct alignment for psw +0000000000000238 00020000 00000000 186 WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +0000000000000248 00020000 00000000 187 HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end + 188 * +0000000000000258 00000000 189 CTLR0 DS F +000000000000025C 00000000 190 FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +0000000000000260 F8000000 191 FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags + 192 * + 193 * Input values parameter list, four fullwords: + 194 * 1) Count, + 195 * 2) Address of inputs, + 196 * 3) Address to place results, and + 197 * 4) Address to place DXC/Flags/cc values. + 198 * +0000000000000264 0000000000000264 0000000000000300 199 ORG BFPLDFPI+X'300' +0000000000000300 200 SHORTS DS 0F Inputs for short BFP testing +0000000000000300 00000007 201 DC A(SBFPCT/4) +0000000000000304 000006E0 202 DC A(SBFPIN) +0000000000000308 00001000 203 DC A(SBFPOUT) +000000000000030C 00001080 204 DC A(SBFPFLGS) + 205 * + ASMA Ver. 0.2.0 ieee-loadfpi.asm: Test IEEE Load FP Integer 31 Aug 2016 20:30:05 Page 5 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000310 206 LONGS DS 0F Inputs for long BFP testing +0000000000000310 00000007 207 DC A(LBFPCT/8) +0000000000000314 0000072C 208 DC A(LBFPIN) +0000000000000318 00002000 209 DC A(LBFPOUT) +000000000000031C 00002100 210 DC A(LBFPFLGS) + 211 * +0000000000000320 212 EXTDS DS 0F Inputs for Extended BFP testing +0000000000000320 00000007 213 DC A(XBFPCT/16) +0000000000000324 000007C8 214 DC A(XBFPIN) +0000000000000328 00003000 215 DC A(XBFPOUT) +000000000000032C 00003200 216 DC A(XBFPFLGS) + 217 * +0000000000000330 218 RMSHORTS DS 0F Inputs for short BFP rounding testing +0000000000000330 0000000C 219 DC A(SBFPRMCT/4) +0000000000000334 000006FC 220 DC A(SBFPINRM) +0000000000000338 00001100 221 DC A(SBFPRMO) +000000000000033C 00001400 222 DC A(SBFPRMOF) + 223 * +0000000000000340 224 RMLONGS DS 0F Inputs for long BFP rounding testing +0000000000000340 0000000C 225 DC A(LBFPRMCT/8) +0000000000000344 00000764 226 DC A(LBFPINRM) +0000000000000348 00002200 227 DC A(LBFPRMO) +000000000000034C 00002800 228 DC A(LBFPRMOF) + 229 * +0000000000000350 230 RMEXTDS DS 0F Inputs for extd BFP rounding testing +0000000000000350 0000000C 231 DC A(XBFPRMCT/16) +0000000000000354 00000838 232 DC A(XBFPINRM) +0000000000000358 00003300 233 DC A(XBFPRMO) +000000000000035C 00003F00 234 DC A(XBFPRMOF) + ASMA Ver. 0.2.0 ieee-loadfpi.asm: Test IEEE Load FP Integer 31 Aug 2016 20:30:05 Page 6 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 236 *********************************************************************** + 237 * + 238 * Round short BFP inputs to integer short BFP. A pair of results is + 239 * generated for each input: one with all exceptions non-trappable, and + 240 * the second with all exceptions trappable. The FPCR is stored for + 241 * each result. + 242 * + 243 *********************************************************************** + + +0000000000000360 245 FIEBR DS 0H Round short BFP inputs to integer BFP +0000000000000360 9823 A000 0000000000000000 246 LM R2,R3,0(R10) Get count and address of test input values +0000000000000364 9878 A008 0000000000000008 247 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000368 1222 248 LTR R2,R2 Any test cases? +000000000000036A 078D 249 BZR R13 ..No, return to caller +000000000000036C 0DC0 250 BASR R12,0 Set top of loop + 251 * +000000000000036E 7800 3000 0000000000000000 252 LE FPR0,0(,R3) Get short BFP test value +0000000000000372 B29D F25C 000000000000025C 253 LFPC FPCREGNT Set exceptions non-trappable +0000000000000376 B357 0010 254 FIEBR FPR1,0,FPR0 Cvt float in FPR0 to int float in FPR1 +000000000000037A 7010 7000 0000000000000000 255 STE FPR1,0(,R7) Store short BFP result +000000000000037E B29C 8000 0000000000000000 256 STFPC 0(R8) Store resulting FPCR flags and DXC + 257 * +0000000000000382 B29D F260 0000000000000260 258 LFPC FPCREGTR Set exceptions trappable +0000000000000386 B374 0010 259 LZER FPR1 Eliminate any residual results +000000000000038A B357 0010 260 FIEBR FPR1,0,FPR0 Cvt float in FPR0 to int float in FPR1 +000000000000038E 7010 7004 0000000000000004 261 STE FPR1,4(,R7) Store short BFP result +0000000000000392 B29C 8004 0000000000000004 262 STFPC 4(R8) Store resulting FPCR flags and DXC + 263 * +0000000000000396 4130 3004 0000000000000004 264 LA R3,4(,R3) Point to next input value +000000000000039A 4170 7008 0000000000000008 265 LA R7,8(,R7) Point to next rounded rusult value pair +000000000000039E 4180 8008 0000000000000008 266 LA R8,8(,R8) Point to next FPCR result area +00000000000003A2 062C 267 BCTR R2,R12 Convert next input value. +00000000000003A4 07FD 268 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-loadfpi.asm: Test IEEE Load FP Integer 31 Aug 2016 20:30:05 Page 7 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 270 *********************************************************************** + 271 * + 272 * Convert short BFP to integer BFP using each possible rounding mode. + 273 * Ten test results are generated for each input. A 48-byte test result + 274 * section is used to keep results sets aligned on a quad-double word. + 275 * + 276 * The first four tests use rounding modes specified in the FPCR with + 277 * the IEEE Inexact exception supressed. SRNM (2-bit) is used for + 278 * the first two FPCR-controlled tests and SRNMB (3-bit) is used for + 279 * the last two To get full coverage of that instruction pair. + 280 * + 281 * The next six results use instruction-specified rounding modes. + 282 * + 283 * The default rounding mode (0 for RNTE) is not tested in this section; + 284 * prior tests used the default rounding mode. RNTE is tested + 285 * explicitly as a rounding mode in this section. + 286 * + 287 *********************************************************************** + + +00000000000003A6 9823 A000 0000000000000000 289 FIEBRA LM R2,R3,0(R10) Get count and address of test input values +00000000000003AA 9878 A008 0000000000000008 290 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000003AE 1222 291 LTR R2,R2 Any test cases? +00000000000003B0 078D 292 BZR R13 ..No, return to caller +00000000000003B2 0DC0 293 BASR R12,0 Set top of loop + 294 * +00000000000003B4 7800 3000 0000000000000000 295 LE FPR0,0(,R3) Get short BFP test value + 296 * + 297 * Test cases using rounding mode specified in the FPCR + 298 * +00000000000003B8 B29D F25C 000000000000025C 299 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000003BC B299 0001 0000000000000001 300 SRNM 1 SET FPCR to RZ, towards zero. +00000000000003C0 B357 0410 301 FIEBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked +00000000000003C4 7010 7000 0000000000000000 302 STE FPR1,0*4(,R7) Store integer BFP result +00000000000003C8 B29C 8000 0000000000000000 303 STFPC 0(R8) Store resulting FPCR flags and DXC + 304 * +00000000000003CC B29D F25C 000000000000025C 305 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000003D0 B299 0002 0000000000000002 306 SRNM 2 SET FPCR to RP, to +infinity +00000000000003D4 B357 0410 307 FIEBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked +00000000000003D8 7010 7004 0000000000000004 308 STE FPR1,1*4(,R7) Store integer BFP result +00000000000003DC B29C 8004 0000000000000004 309 STFPC 1*4(R8) Store resulting FPCR flags and DXC + 310 * +00000000000003E0 B29D F25C 000000000000025C 311 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000003E4 B2B8 0003 0000000000000003 312 SRNMB 3 SET FPCR to RM, to -infinity +00000000000003E8 B357 0410 313 FIEBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked +00000000000003EC 7010 7008 0000000000000008 314 STE FPR1,2*4(,R7) Store integer BFP result +00000000000003F0 B29C 8008 0000000000000008 315 STFPC 2*4(R8) Store resulting FPCR flags and DXC + 316 * +00000000000003F4 B29D F25C 000000000000025C 317 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000003F8 B2B8 0007 0000000000000007 318 SRNMB 7 RPS, Prepare for Shorter Precision +00000000000003FC B357 0410 319 FIEBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked +0000000000000400 7010 700C 000000000000000C 320 STE FPR1,3*4(,R7) Store integer BFP result + ASMA Ver. 0.2.0 ieee-loadfpi.asm: Test IEEE Load FP Integer 31 Aug 2016 20:30:05 Page 8 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000404 B29C 800C 000000000000000C 321 STFPC 3*4(R8) Store resulting FPCR flags and DXC + 322 * + 323 * Test cases using rounding mode specified in the instruction M3 field + 324 * +0000000000000408 B29D F25C 000000000000025C 325 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000040C B357 1010 326 FIEBRA FPR1,1,FPR0,B'0000' RNTA, to nearest, ties away +0000000000000410 7010 7010 0000000000000010 327 STE FPR1,4*4(,R7) Store integer BFP result +0000000000000414 B29C 8010 0000000000000010 328 STFPC 4*4(R8) Store resulting FPCR flags and DXC + 329 * +0000000000000418 B29D F25C 000000000000025C 330 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000041C B357 3010 331 FIEBRA FPR1,3,FPR0,B'0000' RFS, prepare for shorter precision +0000000000000420 7010 7014 0000000000000014 332 STE FPR1,5*4(,R7) Store integer BFP result +0000000000000424 B29C 8014 0000000000000014 333 STFPC 5*4(R8) Store resulting FPCR flags and DXC + 334 * +0000000000000428 B29D F25C 000000000000025C 335 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000042C B357 4010 336 FIEBRA FPR1,4,FPR0,B'0000' RNTE, to nearest, ties to even +0000000000000430 7010 7018 0000000000000018 337 STE FPR1,6*4(,R7) Store integer BFP result +0000000000000434 B29C 8018 0000000000000018 338 STFPC 6*4(R8) Store resulting FPCR flags and DXC + 339 * +0000000000000438 B29D F25C 000000000000025C 340 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000043C B357 5010 341 FIEBRA FPR1,5,FPR0,B'0000' RZ, toward zero +0000000000000440 7010 701C 000000000000001C 342 STE FPR1,7*4(,R7) Store integer BFP result +0000000000000444 B29C 801C 000000000000001C 343 STFPC 7*4(R8) Store resulting FPCR flags and DXC + 344 * +0000000000000448 B29D F25C 000000000000025C 345 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000044C B357 6010 346 FIEBRA FPR1,6,FPR0,B'0000' RP, to +inf +0000000000000450 7010 7020 0000000000000020 347 STE FPR1,8*4(,R7) Store integer BFP result +0000000000000454 B29C 8020 0000000000000020 348 STFPC 8*4(R8) Store resulting FPCR flags and DXC + 349 * +0000000000000458 B29D F25C 000000000000025C 350 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000045C B357 7010 351 FIEBRA FPR1,7,FPR0,B'0000' RM, to -inf +0000000000000460 7010 7024 0000000000000024 352 STE FPR1,9*4(,R7) Store integer BFP result +0000000000000464 B29C 8024 0000000000000024 353 STFPC 9*4(R8) Store resulting FPCR flags and DXC + 354 * +0000000000000468 4130 3004 0000000000000004 355 LA R3,4(,R3) Point to next input values +000000000000046C 4170 7030 0000000000000030 356 LA R7,12*4(,R7) Point to next short BFP converted values +0000000000000470 4180 8030 0000000000000030 357 LA R8,12*4(,R8) Point to next FPCR/CC result area +0000000000000474 062C 358 BCTR R2,R12 Convert next input value. +0000000000000476 07FD 359 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-loadfpi.asm: Test IEEE Load FP Integer 31 Aug 2016 20:30:05 Page 9 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 361 *********************************************************************** + 362 * + 363 * Round long BFP inputs to integer long BFP. A pair of results is + 364 * generated for each input: one with all exceptions non-trappable, and + 365 * the second with all exceptions trappable. The FPCR is stored for + 366 * each result. + 367 * + 368 *********************************************************************** + + +0000000000000478 9823 A000 0000000000000000 370 FIDBR LM R2,R3,0(R10) Get count and address of test input values +000000000000047C 9878 A008 0000000000000008 371 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000480 1222 372 LTR R2,R2 Any test cases? +0000000000000482 078D 373 BZR R13 ..No, return to caller +0000000000000484 0DC0 374 BASR R12,0 Set top of loop + 375 * +0000000000000486 6800 3000 0000000000000000 376 LD FPR0,0(,R3) Get long BFP test value +000000000000048A B29D F25C 000000000000025C 377 LFPC FPCREGNT Set exceptions non-trappable +000000000000048E B35F 0010 378 FIDBR FPR1,0,FPR0 Cvt float in FPR0 to int float in FPR1 +0000000000000492 6010 7000 0000000000000000 379 STD R1,0(,R7) Store long BFP result +0000000000000496 B29C 8000 0000000000000000 380 STFPC 0(R8) Store resulting FPCR flags and DXC + 381 * +000000000000049A B29D F260 0000000000000260 382 LFPC FPCREGTR Set exceptions trappable +000000000000049E B375 0010 383 LZDR FPR1 Eliminate any residual results +00000000000004A2 B35F 0010 384 FIDBR FPR1,0,FPR0 Cvt float in FPR0 to int float in FPR1 +00000000000004A6 6010 7008 0000000000000008 385 STD FPR1,8(,R7) Store int-32 result +00000000000004AA B29C 8004 0000000000000004 386 STFPC 4(R8) Store resulting FPCR flags and DXC + 387 * +00000000000004AE 4130 3008 0000000000000008 388 LA R3,8(,R3) Point to next input value +00000000000004B2 4170 7010 0000000000000010 389 LA R7,16(,R7) Point to next rounded long BFP result pair +00000000000004B6 4180 8008 0000000000000008 390 LA R8,8(,R8) Point to next FPCR result area +00000000000004BA 062C 391 BCTR R2,R12 Convert next input value. +00000000000004BC 07FD 392 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-loadfpi.asm: Test IEEE Load FP Integer 31 Aug 2016 20:30:05 Page 10 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 394 *********************************************************************** + 395 * + 396 * Convert long BFP to integers using each possible rounding mode. + 397 * Ten test results are generated for each input. A 48-byte test result + 398 * section is used to keep results sets aligned on a quad-double word. + 399 * + 400 * The first four tests use rounding modes specified in the FPCR with + 401 * the IEEE Inexact exception supressed. SRNM (2-bit) is used for + 402 * the first two FPCR-controlled tests and SRNMB (3-bit) is used for + 403 * the last two To get full coverage of that instruction pair. + 404 * + 405 * The next six results use instruction-specified rounding modes. + 406 * + 407 * The default rounding mode (0 for RNTE) is not tested in this section; + 408 * prior tests used the default rounding mode. RNTE is tested + 409 * explicitly as a rounding mode in this section. + 410 * + 411 *********************************************************************** + + +00000000000004BE 9823 A000 0000000000000000 413 FIDBRA LM R2,R3,0(R10) Get count and address of test input values +00000000000004C2 9878 A008 0000000000000008 414 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000004C6 1222 415 LTR R2,R2 Any test cases? +00000000000004C8 078D 416 BZR R13 ..No, return to caller +00000000000004CA 0DC0 417 BASR R12,0 Set top of loop + 418 * +00000000000004CC 6800 3000 0000000000000000 419 LD FPR0,0(,R3) Get long BFP test value + 420 * + 421 * Test cases using rounding mode specified in the FPCR + 422 * +00000000000004D0 B29D F25C 000000000000025C 423 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000004D4 B299 0001 0000000000000001 424 SRNM 1 SET FPCR to RZ, towards zero. +00000000000004D8 B35F 0410 425 FIDBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked +00000000000004DC 6010 7000 0000000000000000 426 STD FPR1,0*8(,R7) Store integer BFP result +00000000000004E0 B29C 8000 0000000000000000 427 STFPC 0(R8) Store resulting FPCR flags and DXC + 428 * +00000000000004E4 B29D F25C 000000000000025C 429 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000004E8 B299 0002 0000000000000002 430 SRNM 2 SET FPCR to RP, to +infinity +00000000000004EC B35F 0410 431 FIDBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked +00000000000004F0 6010 7008 0000000000000008 432 STD FPR1,1*8(,R7) Store integer BFP result +00000000000004F4 B29C 8004 0000000000000004 433 STFPC 1*4(R8) Store resulting FPCR flags and DXC + 434 * +00000000000004F8 B29D F25C 000000000000025C 435 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000004FC B2B8 0003 0000000000000003 436 SRNMB 3 SET FPCR to RM, to -infinity +0000000000000500 B35F 0410 437 FIDBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked +0000000000000504 6010 7010 0000000000000010 438 STD FPR1,2*8(,R7) Store integer BFP result +0000000000000508 B29C 8008 0000000000000008 439 STFPC 2*4(R8) Store resulting FPCR flags and DXC + 440 * +000000000000050C B29D F25C 000000000000025C 441 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000510 B2B8 0007 0000000000000007 442 SRNMB 7 RPS, Prepare for Shorter Precision +0000000000000514 B35F 0410 443 FIDBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked +0000000000000518 6010 7018 0000000000000018 444 STD FPR1,3*8(,R7) Store integer BFP result + ASMA Ver. 0.2.0 ieee-loadfpi.asm: Test IEEE Load FP Integer 31 Aug 2016 20:30:05 Page 11 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +000000000000051C B29C 800C 000000000000000C 445 STFPC 3*4(R8) Store resulting FPCR flags and DXC + 446 * + 447 * Test cases using rounding mode specified in the instruction M3 field + 448 * +0000000000000520 B29D F25C 000000000000025C 449 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000524 B35F 1010 450 FIDBRA FPR1,1,FPR0,B'0000' RNTA, to nearest, ties away +0000000000000528 6010 7020 0000000000000020 451 STD FPR1,4*8(,R7) Store integer BFP result +000000000000052C B29C 8010 0000000000000010 452 STFPC 4*4(R8) Store resulting FPCR flags and DXC + 453 * +0000000000000530 B29D F25C 000000000000025C 454 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000534 B35F 3010 455 FIDBRA FPR1,3,FPR0,B'0000' RFS, prepare for shorter precision +0000000000000538 6010 7028 0000000000000028 456 STD FPR1,5*8(,R7) Store integer BFP result +000000000000053C B29C 8014 0000000000000014 457 STFPC 5*4(R8) Store resulting FPCR flags and DXC + 458 * +0000000000000540 B29D F25C 000000000000025C 459 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000544 B35F 4010 460 FIDBRA FPR1,4,FPR0,B'0000' RNTE, to nearest, ties to even +0000000000000548 6010 7030 0000000000000030 461 STD FPR1,6*8(,R7) Store integer BFP result +000000000000054C B29C 8018 0000000000000018 462 STFPC 6*4(R8) Store resulting FPCR flags and DXC + 463 * +0000000000000550 B29D F25C 000000000000025C 464 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000554 B35F 5010 465 FIDBRA FPR1,5,FPR0,B'0000' RZ, toward zero +0000000000000558 6010 7038 0000000000000038 466 STD FPR1,7*8(,R7) Store integer BFP result +000000000000055C B29C 801C 000000000000001C 467 STFPC 7*4(R8) Store resulting FPCR flags and DXC + 468 * +0000000000000560 B29D F25C 000000000000025C 469 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000564 B35F 6010 470 FIDBRA FPR1,6,FPR0,B'0000' RP, to +inf +0000000000000568 6010 7040 0000000000000040 471 STD FPR1,8*8(,R7) Store integer BFP result +000000000000056C B29C 8020 0000000000000020 472 STFPC 8*4(R8) Store resulting FPCR flags and DXC + 473 * +0000000000000570 B29D F25C 000000000000025C 474 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000574 B35F 7010 475 FIDBRA FPR1,7,FPR0,B'0000' RM, to -inf +0000000000000578 6010 7048 0000000000000048 476 STD FPR1,9*8(,R7) Store integer BFP result +000000000000057C B29C 8024 0000000000000024 477 STFPC 9*4(R8) Store resulting FPCR flags and DXC + 478 * +0000000000000580 4130 3008 0000000000000008 479 LA R3,8(,R3) Point to next input values +0000000000000584 4170 7050 0000000000000050 480 LA R7,10*8(,R7) Point to next long BFP converted values +0000000000000588 4180 8030 0000000000000030 481 LA R8,12*4(,R8) Point to next FPCR/CC result area +000000000000058C 062C 482 BCTR R2,R12 Convert next input value. +000000000000058E 07FD 483 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-loadfpi.asm: Test IEEE Load FP Integer 31 Aug 2016 20:30:05 Page 12 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 485 *********************************************************************** + 486 * + 487 * Round extended BFP to integer extended BFP. A pair of results is + 488 * generated for each input: one with all exceptions non-trappable, and + 489 * the second with all exceptions trappable. The FPCR is stored for + 490 * each result. + 491 * + 492 *********************************************************************** + + +0000000000000590 9823 A000 0000000000000000 494 FIXBR LM R2,R3,0(R10) Get count and address of test input values +0000000000000594 9878 A008 0000000000000008 495 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000598 1222 496 LTR R2,R2 Any test cases? +000000000000059A 078D 497 BZR R13 ..No, return to caller +000000000000059C 0DC0 498 BASR R12,0 Set top of loop + 499 * +000000000000059E 6800 3000 0000000000000000 500 LD FPR0,0(,R3) Get extended BFP test value part 1 +00000000000005A2 6820 3008 0000000000000008 501 LD FPR2,8(,R3) Get extended BFP test value part 2 +00000000000005A6 B29D F25C 000000000000025C 502 LFPC FPCREGNT Set exceptions non-trappable +00000000000005AA B347 0010 503 FIXBR FPR1,0,FPR0 Cvt FPR0-FPR2 to int float in FPR1-FPR3 +00000000000005AE 6010 7000 0000000000000000 504 STD FPR1,0(,R7) Store integer BFP result part 1 +00000000000005B2 6030 7008 0000000000000008 505 STD FPR3,8(,R7) Store integer BFP result part 2 +00000000000005B6 B29C 8000 0000000000000000 506 STFPC 0(R8) Store resulting FPCR flags and DXC + 507 * +00000000000005BA B29D F260 0000000000000260 508 LFPC FPCREGTR Set exceptions trappable +00000000000005BE B376 0010 509 LZXR FPR1 Eliminate any residual results +00000000000005C2 B347 0010 510 FIXBR FPR1,0,FPR0 Cvt FPR0-FPR2 to int float in FPR1-FPR3 +00000000000005C6 6010 7010 0000000000000010 511 STD FPR1,16(,R7) Store integer BFP result part 1 +00000000000005CA 6030 7018 0000000000000018 512 STD FPR3,24(,R7) Store integer BFP result part 2 +00000000000005CE B29C 8004 0000000000000004 513 STFPC 4(R8) Store resulting FPCR flags and DXC + 514 * +00000000000005D2 4130 3010 0000000000000010 515 LA R3,16(,R3) Point to next extended BFP input value +00000000000005D6 4170 7020 0000000000000020 516 LA R7,32(,R7) Point to next extd BFP rounded result pair +00000000000005DA 4180 8008 0000000000000008 517 LA R8,8(,R8) Point to next FPCR/CC result area +00000000000005DE 062C 518 BCTR R2,R12 Convert next input value. +00000000000005E0 07FD 519 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-loadfpi.asm: Test IEEE Load FP Integer 31 Aug 2016 20:30:05 Page 13 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 521 *********************************************************************** + 522 * + 523 * Convert extended BFP to integers using each possible rounding mode. + 524 * Ten test results are generated for each input. A 48-byte test result + 525 * section is used to keep results sets aligned on a quad-double word. + 526 * + 527 * The first four tests use rounding modes specified in the FPCR with + 528 * the IEEE Inexact exception supressed. SRNM (2-bit) is used for + 529 * the first two FPCR-controlled tests and SRNMB (3-bit) is used for + 530 * the last two To get full coverage of that instruction pair. + 531 * + 532 * The next six results use instruction-specified rounding modes. + 533 * + 534 * The default rounding mode (0 for RNTE) is not tested in this section; + 535 * prior tests used the default rounding mode. RNTE is tested + 536 * explicitly as a rounding mode in this section. + 537 * + 538 *********************************************************************** + + +00000000000005E2 9823 A000 0000000000000000 540 FIXBRA LM R2,R3,0(R10) Get count and address of test input values +00000000000005E6 9878 A008 0000000000000008 541 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000005EA 1222 542 LTR R2,R2 Any test cases? +00000000000005EC 078D 543 BZR R13 ..No, return to caller +00000000000005EE 0DC0 544 BASR R12,0 Set top of loop + 545 * +00000000000005F0 6800 3000 0000000000000000 546 LD FPR0,0(,R3) Get extended BFP test value part 1 +00000000000005F4 6820 3008 0000000000000008 547 LD FPR2,8(,R3) Get extended BFP test value part 2 + 548 * + 549 * Test cases using rounding mode specified in the FPCR + 550 * +00000000000005F8 B29D F25C 000000000000025C 551 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000005FC B299 0001 0000000000000001 552 SRNM 1 SET FPCR to RZ, towards zero. +0000000000000600 B347 0410 553 FIXBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked +0000000000000604 6010 7000 0000000000000000 554 STD FPR1,0*16(,R7) Store integer BFP result part 1 +0000000000000608 6030 7008 0000000000000008 555 STD FPR3,(0*16)+8(,R7) Store integer BFP result part 2 +000000000000060C B29C 8000 0000000000000000 556 STFPC 0(R8) Store resulting FPCR flags and DXC + 557 * +0000000000000610 B29D F25C 000000000000025C 558 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000614 B299 0002 0000000000000002 559 SRNM 2 SET FPCR to RP, to +infinity +0000000000000618 B347 0410 560 FIXBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked +000000000000061C 6010 7010 0000000000000010 561 STD FPR1,1*16(,R7) Store integer BFP result part 1 +0000000000000620 6030 7018 0000000000000018 562 STD FPR3,(1*16)+8(,R7) Store integer BFP result part 2 +0000000000000624 B29C 8004 0000000000000004 563 STFPC 1*4(R8) Store resulting FPCR flags and DXC + 564 * +0000000000000628 B29D F25C 000000000000025C 565 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000062C B2B8 0003 0000000000000003 566 SRNMB 3 SET FPCR to RM, to -infinity +0000000000000630 B347 0410 567 FIXBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked +0000000000000634 6010 7020 0000000000000020 568 STD FPR1,2*16(,R7) Store integer BFP result part 1 +0000000000000638 6030 7028 0000000000000028 569 STD FPR3,(2*16)+8(,R7) Store integer BFP result part 2 +000000000000063C B29C 8008 0000000000000008 570 STFPC 2*4(R8) Store resulting FPCR flags and DXC + 571 * + ASMA Ver. 0.2.0 ieee-loadfpi.asm: Test IEEE Load FP Integer 31 Aug 2016 20:30:05 Page 14 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000640 B29D F25C 000000000000025C 572 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000644 B2B8 0007 0000000000000007 573 SRNMB 7 RFS, Prepare for Shorter Precision +0000000000000648 B347 0410 574 FIXBRA FPR1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked +000000000000064C 6010 7030 0000000000000030 575 STD FPR1,3*16(,R7) Store integer BFP result part 1 +0000000000000650 6030 7038 0000000000000038 576 STD FPR3,(3*16)+8(,R7) Store integer BFP result part 2 +0000000000000654 B29C 800C 000000000000000C 577 STFPC 3*4(R8) Store resulting FPCR flags and DXC + 578 * + 579 * Test cases using rounding mode specified in the instruction M3 field + 580 * +0000000000000658 B29D F25C 000000000000025C 581 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000065C B347 1010 582 FIXBRA FPR1,1,FPR0,B'0000' RNTA, to nearest, ties away +0000000000000660 6010 7040 0000000000000040 583 STD FPR1,4*16(,R7) Store integer BFP result part 1 +0000000000000664 6030 7048 0000000000000048 584 STD FPR3,(4*16)+8(,R7) Store integer BFP result part 2 +0000000000000668 B29C 8010 0000000000000010 585 STFPC 4*4(R8) Store resulting FPCR flags and DXC + 586 * +000000000000066C B29D F25C 000000000000025C 587 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000670 B347 3010 588 FIXBRA FPR1,3,FPR0,B'0000' RFS, prepare for shorter precision +0000000000000674 6010 7050 0000000000000050 589 STD FPR1,5*16(,R7) Store integer BFP result part 1 +0000000000000678 6030 7058 0000000000000058 590 STD FPR3,(5*16)+8(,R7) Store integer BFP result part 2 +000000000000067C B29C 8014 0000000000000014 591 STFPC 5*4(R8) Store resulting FPCR flags and DXC + 592 * +0000000000000680 B29D F25C 000000000000025C 593 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000684 B347 4010 594 FIXBRA FPR1,4,FPR0,B'0000' RNTE, to nearest, ties to even +0000000000000688 6010 7060 0000000000000060 595 STD FPR1,6*16(,R7) Store integer BFP result part 1 +000000000000068C 6030 7068 0000000000000068 596 STD FPR3,(6*16)+8(,R7) Store integer BFP result part 2 +0000000000000690 B29C 8018 0000000000000018 597 STFPC 6*4(R8) Store resulting FPCR flags and DXC + 598 * +0000000000000694 B29D F25C 000000000000025C 599 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000698 B347 5010 600 FIXBRA FPR1,5,FPR0,B'0000' RZ, toward zero +000000000000069C 6010 7070 0000000000000070 601 STD FPR1,7*16(,R7) Store integer BFP result part 1 +00000000000006A0 6030 7078 0000000000000078 602 STD FPR3,(7*16)+8(,R7) Store integer BFP result part 2 +00000000000006A4 B29C 801C 000000000000001C 603 STFPC 7*4(R8) Store resulting FPCR flags and DXC + 604 * +00000000000006A8 B29D F25C 000000000000025C 605 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000006AC B347 6010 606 FIXBRA FPR1,6,FPR0,B'0000' RP, to +inf +00000000000006B0 6010 7080 0000000000000080 607 STD FPR1,8*16(,R7) Store integer BFP result part 1 +00000000000006B4 6030 7088 0000000000000088 608 STD FPR3,(8*16)+8(,R7) Store integer BFP result part 2 +00000000000006B8 B29C 8020 0000000000000020 609 STFPC 8*4(R8) Store resulting FPCR flags and DXC + 610 * +00000000000006BC B29D F25C 000000000000025C 611 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000006C0 B347 7010 612 FIXBRA FPR1,7,FPR0,B'0000' RM, to -inf +00000000000006C4 6010 7090 0000000000000090 613 STD FPR1,9*16(,R7) Store integer BFP result part 1 +00000000000006C8 6030 7098 0000000000000098 614 STD FPR3,(9*16)+8(,R7) Store integer BFP result part 2 +00000000000006CC B29C 8024 0000000000000024 615 STFPC 9*4(R8) Store resulting FPCR flags and DXC + 616 * +00000000000006D0 4130 3010 0000000000000010 617 LA R3,16(,R3) Point to next input value +00000000000006D4 4170 70A0 00000000000000A0 618 LA R7,10*16(,R7) Point to next long BFP converted values +00000000000006D8 4180 8030 0000000000000030 619 LA R8,12*4(,R8) Point to next FPCR/CC result area +00000000000006DC 062C 620 BCTR R2,R12 Convert next input value. +00000000000006DE 07FD 621 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-loadfpi.asm: Test IEEE Load FP Integer 31 Aug 2016 20:30:05 Page 15 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 623 *********************************************************************** + 624 * + 625 * Short integer inputs for Load FP Integer testing. The same + 626 * values are used for short, long, and extended formats. + 627 * + 628 *********************************************************************** + + +00000000000006E0 630 SBFPIN DS 0F Inputs for short BFP testing +00000000000006E0 3F800000 631 DC X'3F800000' +1.0 Exact +00000000000006E4 BFC00000 632 DC X'BFC00000' -1.5 Inexact, incremented +00000000000006E8 40200000 633 DC X'40200000' +2.5 Inexact only +00000000000006EC 7F810000 634 DC X'7F810000' SNaN +00000000000006F0 7FC10000 635 DC X'7FC10000' QNaN +00000000000006F4 3F400000 636 DC X'3F400000' +.75 Inexact, incremented +00000000000006F8 BE800000 637 DC X'BE800000' -.25 Inexact + 000000000000001C 0000000000000001 638 SBFPCT EQU *-SBFPIN Count of short BFP in list * 4 + 639 * +00000000000006FC 640 SBFPINRM DS 0F Inputs for short BFP rounding testing +00000000000006FC C1180000 641 DC X'C1180000' -9.5 +0000000000000700 C0B00000 642 DC X'C0B00000' -5.5 +0000000000000704 C0200000 643 DC X'C0200000' -2.5 +0000000000000708 BFC00000 644 DC X'BFC00000' -1.5 +000000000000070C BF000000 645 DC X'BF000000' -0.5 +0000000000000710 3F000000 646 DC X'3F000000' +0.5 +0000000000000714 3FC00000 647 DC X'3FC00000' +1.5 +0000000000000718 40200000 648 DC X'40200000' +2.5 +000000000000071C 40B00000 649 DC X'40B00000' +5.5 +0000000000000720 41180000 650 DC X'41180000' +9.5 +0000000000000724 3F400000 651 DC X'3F400000' +.75 +0000000000000728 BE800000 652 DC X'BE800000' -.25 + 0000000000000030 0000000000000001 653 SBFPRMCT EQU *-SBFPINRM Count of short BFP rounding tests * 4 + 654 * +000000000000072C 655 LBFPIN DS 0F Inputs for long BFP testing +000000000000072C 3FF00000 00000000 656 DC X'3FF0000000000000' +1.0 +0000000000000734 BFF80000 00000000 657 DC X'BFF8000000000000' -1.5 +000000000000073C 40040000 00000000 658 DC X'4004000000000000' +2.5 +0000000000000744 7FF01000 00000000 659 DC X'7FF0100000000000' SNaN +000000000000074C 7FF81000 00000000 660 DC X'7FF8100000000000' QNaN +0000000000000754 3FE80000 00000000 661 DC X'3FE8000000000000' +.75 +000000000000075C BFD00000 00000000 662 DC X'BFD0000000000000' -.25 + 0000000000000038 0000000000000001 663 LBFPCT EQU *-LBFPIN Count of long BFP in list * 8 + 664 * +0000000000000764 665 LBFPINRM DS 0F +0000000000000764 C0230000 00000000 666 DC X'C023000000000000' -9.5 +000000000000076C C0160000 00000000 667 DC X'C016000000000000' -5.5 +0000000000000774 C0040000 00000000 668 DC X'C004000000000000' -2.5 +000000000000077C BFF80000 00000000 669 DC X'BFF8000000000000' -1.5 +0000000000000784 BFE00000 00000000 670 DC X'BFE0000000000000' -0.5 +000000000000078C 3FE00000 00000000 671 DC X'3FE0000000000000' +0.5 +0000000000000794 3FF80000 00000000 672 DC X'3FF8000000000000' +1.5 +000000000000079C 40040000 00000000 673 DC X'4004000000000000' +2.5 + ASMA Ver. 0.2.0 ieee-loadfpi.asm: Test IEEE Load FP Integer 31 Aug 2016 20:30:05 Page 16 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000007A4 40160000 00000000 674 DC X'4016000000000000' +5.5 +00000000000007AC 40230000 00000000 675 DC X'4023000000000000' +9.5 +00000000000007B4 3FE80000 00000000 676 DC X'3FE8000000000000' +.75 +00000000000007BC BFD00000 00000000 677 DC X'BFD0000000000000' -.25 + 0000000000000060 0000000000000001 678 LBFPRMCT EQU *-LBFPINRM Count of long BFP rounding tests * 8 + 679 * +00000000000007C8 680 XBFPIN DS 0D Inputs for long BFP testing +00000000000007C8 3FFF0000 00000000 681 DC X'3FFF0000000000000000000000000000' +1.0 +00000000000007D8 BFFF8000 00000000 682 DC X'BFFF8000000000000000000000000000' -1.5 +00000000000007E8 40004000 00000000 683 DC X'40004000000000000000000000000000' +2.5 +00000000000007F8 7FFF0100 00000000 684 DC X'7FFF0100000000000000000000000000' SNaN +0000000000000808 7FFF8100 00000000 685 DC X'7FFF8100000000000000000000000000' QNaN +0000000000000818 3FFE8000 00000000 686 DC X'3FFE8000000000000000000000000000' +0.75 +0000000000000828 BFFD0000 00000000 687 DC X'BFFD0000000000000000000000000000' -0.25 + 0000000000000070 0000000000000001 688 XBFPCT EQU *-XBFPIN Count of extended BFP in list * 16 + 689 * +0000000000000838 690 XBFPINRM DS 0D +0000000000000838 C0023000 00000000 691 DC X'C0023000000000000000000000000000' -9.5 +0000000000000848 C0016000 00000000 692 DC X'C0016000000000000000000000000000' -5.5 +0000000000000858 C0004000 00000000 693 DC X'C0004000000000000000000000000000' -2.5 +0000000000000868 BFFF8000 00000000 694 DC X'BFFF8000000000000000000000000000' -1.5 +0000000000000878 BFFE0000 00000000 695 DC X'BFFE0000000000000000000000000000' -0.5 +0000000000000888 3FFE0000 00000000 696 DC X'3FFE0000000000000000000000000000' +0.5 +0000000000000898 3FFF8000 00000000 697 DC X'3FFF8000000000000000000000000000' +1.5 +00000000000008A8 40004000 00000000 698 DC X'40004000000000000000000000000000' +2.5 +00000000000008B8 40016000 00000000 699 DC X'40016000000000000000000000000000' +5.5 +00000000000008C8 40023000 00000000 700 DC X'40023000000000000000000000000000' +9.5 +00000000000008D8 3FFE8000 00000000 701 DC X'3FFE8000000000000000000000000000' +0.75 +00000000000008E8 BFFD0000 00000000 702 DC X'BFFD0000000000000000000000000000' -0.25 + 00000000000000C0 0000000000000001 703 XBFPRMCT EQU *-XBFPINRM Count of extended BFP rounding tests * 16 + 704 * + 705 * Locations for results + 706 * + 0000000000001000 0000000000000000 707 SBFPOUT EQU BFPLDFPI+X'1000' Integer short BFP rounded results + 708 * ..7 used, room for 16 + 0000000000001080 0000000000000000 709 SBFPFLGS EQU BFPLDFPI+X'1080' FPCR flags and DXC from short BFP + 710 * ..7 used, room for 16 + 0000000000001100 0000000000000000 711 SBFPRMO EQU BFPLDFPI+X'1100' Short BFP rounding mode test results + 712 * ..12 used, room for 16 + 0000000000001400 0000000000000000 713 SBFPRMOF EQU BFPLDFPI+X'1400' Short BFP rounding mode FPCR results + 714 * ..12 used + 715 * + 0000000000002000 0000000000000000 716 LBFPOUT EQU BFPLDFPI+X'2000' Integer long BFP rounded results + 717 * ..7 used, room for 16 + 0000000000002100 0000000000000000 718 LBFPFLGS EQU BFPLDFPI+X'2100' FPCR flags and DXC from long BFP + 719 * ..7 used, room for 32 + 0000000000002200 0000000000000000 720 LBFPRMO EQU BFPLDFPI+X'2200' Long BFP rounding mode test results + 721 * ..12 used, room for 16 + 0000000000002800 0000000000000000 722 LBFPRMOF EQU BFPLDFPI+X'2800' Long BFP rounding mode FPCR results + 723 * ..12 used + 724 * + 0000000000003000 0000000000000000 725 XBFPOUT EQU BFPLDFPI+X'3000' Integer extended BFP rounded results + ASMA Ver. 0.2.0 ieee-loadfpi.asm: Test IEEE Load FP Integer 31 Aug 2016 20:30:05 Page 17 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 726 * ..7 used, room for 16 + 0000000000003200 0000000000000000 727 XBFPFLGS EQU BFPLDFPI+X'3200' FPCR flags and DXC from extended BFP + 728 * ..7 used, room for 32 + 0000000000003300 0000000000000000 729 XBFPRMO EQU BFPLDFPI+X'3300' Extd BFP rounding mode test results + 730 * ..12 used, room for 16 + 0000000000003F00 0000000000000000 731 XBFPRMOF EQU BFPLDFPI+X'3F00' Extd BFP rounding mode FPCR results + 732 * ..12 used + 733 * + 734 * + 0000000000004800 0000000000000000 735 ENDLABL EQU BFPLDFPI+X'4800' + 736 * Pad CSECT if not running on ASMA for a stand-alone environment + 737 PADCSECT ENDLABL + 738+ MNOTE *,'asma detected; no CSECT padding performed' +00000000000008F8 739 END + ASMA Ver. 0.2.0 ieee-loadfpi.asm: Test IEEE Load FP Integer 31 Aug 2016 20:30:05 Page 18 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +BFPLDFPI J 000000 2296 82 130 133 135 138 199 707 709 711 713 716 718 720 722 725 727 729 731 + 735 +CTLR0 F 000258 4 189 162 163 164 +ENDLABL U 004800 0 735 +EXTDS F 000320 4 212 176 +FIDBR I 000478 4 370 172 +FIDBRA I 0004BE 4 413 174 +FIEBR H 000360 2 245 167 +FIEBRA I 0003A6 4 289 169 +FIXBR I 000590 4 494 177 +FIXBRA I 0005E2 4 540 179 +FPCREGNT X 00025C 4 190 253 299 305 311 317 325 330 335 340 345 350 377 423 429 435 441 449 + 454 459 464 469 474 502 551 558 565 572 581 587 593 599 605 611 +FPCREGTR X 000260 4 191 258 382 508 +FPR0 U 000000 1 102 252 254 260 295 301 307 313 319 326 331 336 341 346 351 376 378 384 + 419 425 431 437 443 450 455 460 465 470 475 500 503 510 546 553 560 + 567 574 582 588 594 600 606 612 +FPR1 U 000001 1 103 254 255 259 260 261 301 302 307 308 313 314 319 320 326 327 331 332 + 336 337 341 342 346 347 351 352 378 383 384 385 425 426 431 432 437 + 438 443 444 450 451 455 456 460 461 465 466 470 471 475 476 503 504 + 509 510 511 553 554 560 561 567 568 574 575 582 583 588 589 594 595 + 600 601 606 607 612 613 +FPR10 U 00000A 1 112 +FPR11 U 00000B 1 113 +FPR12 U 00000C 1 114 +FPR13 U 00000D 1 115 +FPR14 U 00000E 1 116 +FPR15 U 00000F 1 117 +FPR2 U 000002 1 104 501 547 +FPR3 U 000003 1 105 505 512 555 562 569 576 584 590 596 602 608 614 +FPR4 U 000004 1 106 +FPR5 U 000005 1 107 +FPR6 U 000006 1 108 +FPR7 U 000007 1 109 +FPR8 U 000008 1 110 +FPR9 U 000009 1 111 +HARDWAIT X 000248 8 187 153 +IMAGE 1 000000 2296 0 +LBFPCT U 000038 1 663 207 +LBFPFLGS U 002100 0 718 210 +LBFPIN F 00072C 4 655 663 208 +LBFPINRM F 000764 4 665 678 226 +LBFPOUT U 002000 0 716 209 +LBFPRMCT U 000060 1 678 225 +LBFPRMO U 002200 0 720 227 +LBFPRMOF U 002800 0 722 228 +LONGS F 000310 4 206 171 +PCINTCD H 00008E 2 131 147 +PCNOTDTA H 0001EC 2 150 148 +PCOLDPSW U 000150 0 133 149 +PROGCHK H 0001E0 2 146 139 +R0 U 000000 1 83 162 164 + ASMA Ver. 0.2.0 ieee-loadfpi.asm: Test IEEE Load FP Integer 31 Aug 2016 20:30:05 Page 19 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +R1 U 000001 1 84 379 +R10 U 00000A 1 93 166 168 171 173 176 178 246 247 289 290 370 371 413 414 494 495 540 + 541 +R11 U 00000B 1 94 +R12 U 00000C 1 95 250 267 293 358 374 391 417 482 498 518 544 620 +R13 U 00000D 1 96 167 169 172 174 177 179 249 268 292 359 373 392 416 483 497 519 543 + 621 +R14 U 00000E 1 97 151 152 181 182 +R15 U 00000F 1 98 119 +R2 U 000002 1 85 246 248 267 289 291 358 370 372 391 413 415 482 494 496 518 540 542 + 620 +R3 U 000003 1 86 246 252 264 289 295 355 370 376 388 413 419 479 494 500 501 515 540 + 546 547 617 +R4 U 000004 1 87 +R5 U 000005 1 88 +R6 U 000006 1 89 +R7 U 000007 1 90 247 255 261 265 290 302 308 314 320 327 332 337 342 347 352 356 371 + 379 385 389 414 426 432 438 444 451 456 461 466 471 476 480 495 504 + 505 511 512 516 541 554 555 561 562 568 569 575 576 583 584 589 590 + 595 596 601 602 607 608 613 614 618 +R8 U 000008 1 91 247 256 262 266 290 303 309 315 321 328 333 338 343 348 353 357 371 + 380 386 390 414 427 433 439 445 452 457 462 467 472 477 481 495 506 + 513 517 541 556 563 570 577 585 591 597 603 609 615 619 +R9 U 000009 1 92 +RMEXTDS F 000350 4 230 178 +RMLONGS F 000340 4 224 173 +RMSHORTS F 000330 4 218 168 +SBFPCT U 00001C 1 638 201 +SBFPFLGS U 001080 0 709 204 +SBFPIN F 0006E0 4 630 638 202 +SBFPINRM F 0006FC 4 640 653 220 +SBFPOUT U 001000 0 707 203 +SBFPRMCT U 000030 1 653 219 +SBFPRMO U 001100 0 711 221 +SBFPRMOF U 001400 0 713 222 +SHORTS F 000300 4 200 166 +START H 0001F4 2 161 136 +WAITPSW X 000238 8 186 183 +XBFPCT U 000070 1 688 213 +XBFPFLGS U 003200 0 727 216 +XBFPIN D 0007C8 8 680 688 214 +XBFPINRM D 000838 8 690 703 232 +XBFPOUT U 003000 0 725 215 +XBFPRMCT U 0000C0 1 703 231 +XBFPRMO U 003300 0 729 233 +XBFPRMOF U 003F00 0 731 234 + ASMA Ver. 0.2.0 ieee-loadfpi.asm: Test IEEE Load FP Integer 31 Aug 2016 20:30:05 Page 20 + + MACRO DEFN REFERENCES + +PADCSECT 57 737 + ASMA Ver. 0.2.0 ieee-loadfpi.asm: Test IEEE Load FP Integer 31 Aug 2016 20:30:05 Page 21 + + DESC SYMBOL SIZE POS ADDR + +Entry: 0 + +Image IMAGE 2296 000-8F7 000-8F7 + Region 2296 000-8F7 000-8F7 + CSECT BFPLDFPI 2296 000-8F7 000-8F7 + ASMA Ver. 0.2.0 ieee-loadfpi.asm: Test IEEE Load FP Integer 31 Aug 2016 20:30:05 Page 22 + + STMT FILE NAME + +1 C:\Users\srorso\Documents\GitHub\hyperion\tests\bfp-003-loadfpi.asm + + +** NO ERRORS FOUND ** + +[738] MNOTE *,asma detected; no CSECT padding performed + \ No newline at end of file diff --git a/tests/bfp-003-loadfpi.tst b/tests/bfp-003-loadfpi.tst new file mode 100644 index 000000000..a428e7c37 --- /dev/null +++ b/tests/bfp-003-loadfpi.tst @@ -0,0 +1,858 @@ +*Testcase bfp-003-loadfpi.tst: CFEBR, CFEBRA, CFDBR, CFDBRA, CFXBR, CFXBRA + +#Testcase bfp-003-loadfpi.tst: IEEE Load FP Integer +#..Includes LOAD FP INTEGER (6). Tests traps, exceptions, results +#..from all rounding modes, and NaN propagation. + + +sysclear +archmode esame + +# +# Following suppresses logging of program checks. This test program, as part +# of its normal operation, generates 15 program check messages that have +# no value in the validation process. (The messages, not the program checks.) +# +ostailor quiet + +loadcore "$(testpath)/bfp-003-loadfpi.core" + +runtest 1.0 + +ostailor null # restore messages for subsequent tests + + +# Short BFP Inputs converted to integer short BFP +*Compare +r 1000.10 +*Want "CFEBR result pairs 1-2" 3F800000 3F800000 C0000000 C0000000 +r 1010.10 +*Want "CFEBR result pairs 3-4" 40000000 40000000 7FC10000 00000000 +r 1020.10 +*Want "CFEBR result pair 5-6" 7FC10000 7FC10000 3F800000 3F800000 +r 1030.8 +*Want "CFEBR result pair 7" 80000000 80000000 + +# Inputs converted to BFP Short - FPC +*Compare +r 1080.10 +*Want "CFEBR FPC pairs 1-2" 00000000 F8000000 00080000 F8000C00 +r 1090.10 +*Want "CFEBR FPC pairs 3-4" 00080000 F8000800 00800000 F8008000 +r 10A0.10 +*Want "CFEBR FPC pair 5-6" 00000000 F8000000 00080000 F8000C00 +r 10B0.08 +*Want "CFEBR FPC pair 7" 00080000 F8000800 + + +# rounding mode tests - short BFP - results from rounding +*Compare +r 1100.10 # RZ, RP, RM, RFS +*Want "CFEBRA -9.5 FPC modes 1-3, 7" C1100000 C1100000 C1200000 C1100000 +r 1110.10 # RNTA, RFS, RNTE, RZ +*Want "CFEBRA -9.5 M3 modes 1, 3-5" C1200000 C1100000 C1200000 C1100000 +r 1120.08 # RP, RM +*Want "CFEBRA -9.5 M3 modes 6, 7" C1100000 C1200000 + +r 1130.10 # RZ, RP, RM, RFS +*Want "CFEBRA -5.5 FPC modes 1-3, 7" C0A00000 C0A00000 C0C00000 C0A00000 +r 1140.10 # RNTA, RFS, RNTE, RZ +*Want "CFEBRA -5.5 M3 modes 1, 3-5" C0C00000 C0A00000 C0C00000 C0A00000 +r 1150.08 # RP, RM +*Want "CFEBRA -5.5 M3 modes 6, 7" C0A00000 C0C00000 + +r 1160.10 # RZ, RP, RM, RFS +*Want "CFEBRA -2.5 FPC modes 1-3, 7" C0000000 C0000000 C0400000 C0400000 +r 1170.10 # RNTA, RFS, RNTE, RZ +*Want "CFEBRA -2.5 M3 modes 1, 3-5" C0400000 C0400000 C0000000 C0000000 +r 1180.08 # RP, RM +*Want "CFEBRA -2.5 M3 modes 6, 7" C0000000 C0400000 + +r 1190.10 # RZ, RP, RM, RFS +*Want "CFEBRA -1.5 FPC modes 1-3, 7" BF800000 BF800000 C0000000 BF800000 +r 11A0.10 # RNTA, RFS, RNTE, RZ +*Want "CFEBRA -1.5 M3 modes 1, 3-5" C0000000 BF800000 C0000000 BF800000 +r 11B0.08 # RP, RM +*Want "CFEBRA -1.5 M3 modes 6, 7" BF800000 C0000000 + +r 11C0.10 # RZ, RP, RM, RFS +*Want "CFEBRA -0.5 FPC modes 1-3, 7" 80000000 80000000 BF800000 BF800000 +r 11D0.10 # RNTA, RFS, RNTE, RZ +*Want "CFEBRA -0.5 M3 modes 1, 3-5" BF800000 BF800000 80000000 80000000 +r 11E0.08 # RP, RM +*Want "CFEBRA -0.5 M3 modes 6, 7" 80000000 BF800000 + +r 11F0.10 # RZ, RP, RM, RFS +*Want "CFEBRA 0.5 FPC modes 1-3, 7" 00000000 3F800000 00000000 3F800000 +r 1200.10 # RNTA, RFS, RNTE, RZ +*Want "CFEBRA 0.5 M3 modes 1, 3-5" 3F800000 3F800000 00000000 00000000 +r 1210.08 # RP, RM +*Want "CFEBRA 0.5 M3 modes 6, 7" 3F800000 00000000 + +r 1220.10 # RZ, RP, RM, RFS +*Want "CFEBRA 1.5 FPC modes 1-3, 7" 3F800000 40000000 3F800000 3F800000 +r 1230.10 # RNTA, RFS, RNTE, RZ +*Want "CFEBRA 1.5 M3 modes 1, 3-5" 40000000 3F800000 40000000 3F800000 +r 1240.08 # RP, RM +*Want "CFEBRA 1.5 M3 modes 6, 7" 40000000 3F800000 + +r 1250.10 # RZ, RP, RM, RFS +*Want "CFEBRA 2.5 FPC modes 1-3, 7" 40000000 40400000 40000000 40400000 +r 1260.10 # RNTA, RFS, RNTE, RZ +*Want "CFEBRA 2.5 M3 modes 1, 3-5" 40400000 40400000 40000000 40000000 +r 1270.08 # RP, RM +*Want "CFEBRA 2.5 M3 modes 6, 7" 40400000 40000000 + +r 1280.10 # RZ, RP, RM, RFS +*Want "CFEBRA 5.5 FPC modes 1-3, 7" 40A00000 40C00000 40A00000 40A00000 +r 1290.10 # RNTA, RFS, RNTE, RZ +*Want "CFEBRA 5.5 M3 modes 1, 3-5" 40C00000 40A00000 40C00000 40A00000 +r 12A0.08 # RP, RM +*Want "CFEBRA 5.5 M3 modes 6, 7" 40C00000 40A00000 + +r 12B0.10 # RZ, RP, RM, RFS +*Want "CFEBRA 9.5 FPC modes 1-3, 7" 41100000 41200000 41100000 41100000 +r 12C0.10 # RNTA, RFS, RNTE, RZ +*Want "CFEBRA 9.5 M3 modes 1, 3-5" 41200000 41100000 41200000 41100000 +r 12D0.08 # RP, RM +*Want "CFEBRA 9.5 M3 modes 6, 7" 41200000 41100000 + +r 12E0.10 # RZ, RP, RM, RFS +*Want "CFEBRA +0.75 FPC modes 1-3, 7" 00000000 3F800000 00000000 3F800000 +r 12F0.10 # RNTA, RFS, RNTE, RZ +*Want "CFEBRA +0.75 M3 modes 1, 3-5" 3F800000 3F800000 3F800000 00000000 +r 1300.08 # RP, RM +*Want "CFEBRA +0.75 M3 modes 6, 7" 3F800000 00000000 + +r 1310.10 # RZ, RP, RM, RFS +*Want "CFEBRA -0.25 FPC modes 1-3, 7" 80000000 80000000 BF800000 BF800000 +r 1320.10 # RNTA, RFS, RNTE, RZ +*Want "CFEBRA -0.25 M3 modes 1, 3-5" 80000000 BF800000 80000000 80000000 +r 1330.08 # RP, RM +*Want "CFEBRA -0.25 M3 modes 6, 7" 80000000 BF800000 + +# rounding mode tests - short BFP - FPCR contents +*Compare +r 1400.10 +*Want "CFEBRA -9.5 FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 1410.10 +*Want "CFEBRA -9.5 M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 1420.08 +*Want "CFEBRA -9.5 M3 modes 5-7 - FCPR" 00080000 00080000 + +r 1430.10 +*Want "CFEBRA -5.5 FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 1440.10 +*Want "CFEBRA -5.5 M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 1450.08 +*Want "CFEBRA -5.5 M3 modes 6, 7 FCPR" 00080000 00080000 + +r 1460.10 +*Want "CFEBRA -2.5 FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 1470.10 +*Want "CFEBRA -2.5 M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 1480.08 +*Want "CFEBRA -2.5 M3 modes 6, 7 FCPR" 00080000 00080000 + +r 1490.10 +*Want "CFEBRA -1.5 FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 14A0.10 +*Want "CFEBRA -1.5 M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 14B0.08 +*Want "CFEBRA -1.5 M3 modes 6, 7 FCPR" 00080000 00080000 + +r 14C0.10 +*Want "CFEBRA -0.5 FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 14D0.10 +*Want "CFEBRA -0.5 M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 14E0.08 +*Want "CFEBRA -0.5 M3 modes 6, 7 FCPR" 00080000 00080000 + +r 14F0.10 +*Want "CFEBRA +0.5 FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 1500.10 +*Want "CFEBRA +0.5 M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 1510.08 +*Want "CFEBRA +0.5 M3 modes 6, 7 FCPR" 00080000 00080000 + +r 1520.10 +*Want "CFEBRA +1.5 FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 1530.10 +*Want "CFEBRA +1.5 M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 1540.08 +*Want "CFEBRA +1.5 M3 modes 6, 7 FCPR" 00080000 00080000 + +r 1550.10 +*Want "CFEBRA +2.5 FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 1560.10 +*Want "CFEBRA +2.5 M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 1570.08 +*Want "CFEBRA +2.5 M3 modes 6, 7 FCPR" 00080000 00080000 + +r 1580.10 +*Want "CFEBRA +5.5 FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 1590.10 +*Want "CFEBRA +5.5 M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 15A0.08 +*Want "CFEBRA +5.5 M3 modes 6, 7 FCPR" 00080000 00080000 + +r 15B0.10 +*Want "CFEBRA +9.5 FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 15C0.10 +*Want "CFEBRA +9.5 M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 15D0.08 +*Want "CFEBRA +9.5 M3 modes 6, 7 FCPR" 00080000 00080000 + +r 15E0.10 +*Want "CFEBRA +0.75 FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 15F0.10 +*Want "CFEBRA +0.75 M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 1600.08 +*Want "CFEBRA +0.75 M3 modes 6, 7 FCPR" 00080000 00080000 + +r 1610.10 +*Want "CFEBRA -0.25 FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 1620.10 +*Want "CFEBRA -0.25 M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 1630.08 +*Want "CFEBRA -0.25 M3 modes 6, 7 FCPR" 00080000 00080000 + + +# Results from long BFP rounded to long BFP integer +*Compare +R 2000.10 +*Want "CFDBR result pair 1" 3FF00000 00000000 3FF00000 00000000 +R 2010.10 +*Want "CFDBR result pair 2" C0000000 00000000 C0000000 00000000 +R 2020.10 +*Want "CFDBR result pair 3" 40000000 00000000 40000000 00000000 +R 2030.10 +*Want "CFDBR result pair 4" 7FF81000 00000000 00000000 00000000 +R 2040.10 +*Want "CFDBR result pair 5" 7FF81000 00000000 7FF81000 00000000 +R 2050.10 +*Want "CFDBR result pair 6" 3FF00000 00000000 3FF00000 00000000 +R 2060.10 +*Want "CFDBR result pair 7" 80000000 00000000 80000000 00000000 + +# Results from long BFP rounded to long BFP integer - FPCR +*Compare +R 2100.10 +*Want "CFDBR FPC pairs 1-2" 00000000 F8000000 00080000 F8000C00 +R 2110.10 +*Want "CFDBR FPC pairs 3-4" 00080000 F8000800 00800000 F8008000 +R 2120.10 +*Want "CFDBR FPC pairs 5-6" 00000000 F8000000 00080000 F8000C00 +R 2130.08 +*Want "CFDBR FPC pair 7" 00080000 F8000800 + + +# rounding mode tests - long BFP - results from rounding +*Compare +R 2200.10 # RZ, RP +*Want "CFDBRA -9.5 FPC modes 1, 2" C0220000 00000000 C0220000 00000000 +R 2210.10 # RM, RFS +*Want "CFDBRA -9.5 FPC modes 3, 7" C0240000 00000000 C0220000 00000000 +R 2220.10 # RNTA, RFS +*Want "CFDBRA -9.5 M3 modes 1, 3" C0240000 00000000 C0220000 00000000 +R 2230.10 # RNTE, RZ +*Want "CFDBRA -9.5 M3 modes 4, 5" C0240000 00000000 C0220000 00000000 +R 2240.10 # RP, RM +*Want "CFDBRA -9.5 M3 modes 6, 7" C0220000 00000000 C0240000 00000000 + +R 2250.10 # RZ, RP +*Want "CFDBRA -5.5 FPC modes 1, 2" C0140000 00000000 C0140000 00000000 +R 2260.10 # RM, RFS +*Want "CFDBRA -5.5 FPC modes 3, 7" C0180000 00000000 C0140000 00000000 +R 2270.10 # RNTA, RFS +*Want "CFDBRA -5.5 M3 modes 1, 3" C0180000 00000000 C0140000 00000000 +R 2280.10 # RNTE, RZ +*Want "CFDBRA -5.5 M3 modes 4, 5" C0180000 00000000 C0140000 00000000 +R 2290.10 # RP, RM +*Want "CFDBRA -5.5 M3 modes 6, 7" C0140000 00000000 C0180000 00000000 + +R 22A0.10 # RZ, RP +*Want "CFDBRA -2.5 FPC modes 1, 2" C0000000 00000000 C0000000 00000000 +R 22B0.10 # RM, RFS +*Want "CFDBRA -2.5 FPC modes 3, 7" C0080000 00000000 C0080000 00000000 +R 22C0.10 # RNTA, RFS +*Want "CFDBRA -2.5 M3 modes 1, 3" C0080000 00000000 C0080000 00000000 +R 22D0.10 # RNTE, RZ +*Want "CFDBRA -2.5 M3 modes 4, 5" C0000000 00000000 C0000000 00000000 +R 22E0.10 # RP, RM +*Want "CFDBRA -2.5 M3 modes 6, 7" C0000000 00000000 C0080000 00000000 + +R 22F0.10 # RZ, RP +*Want "CFDBRA -1.5 FPC modes 1, 2" BFF00000 00000000 BFF00000 00000000 +R 2300.10 # RM, RFS +*Want "CFDBRA -1.5 FPC modes 3, 7" C0000000 00000000 BFF00000 00000000 +R 2310.10 # RNTA, RFS +*Want "CFDBRA -1.5 M3 modes 1, 3" C0000000 00000000 BFF00000 00000000 +R 2320.10 # RNTE, RZ +*Want "CFDBRA -1.5 M3 modes 4, 5" C0000000 00000000 BFF00000 00000000 +R 2330.10 # RP, RM +*Want "CFDBRA -1.5 M3 modes 6, 7" BFF00000 00000000 C0000000 00000000 + +R 2340.10 # RZ, RP +*Want "CFDBRA -0.5 FPC modes 1, 2" 80000000 00000000 80000000 00000000 +R 2350.10 # RM, RFS +*Want "CFDBRA -0.5 FPC modes 3, 7" BFF00000 00000000 BFF00000 00000000 +R 2360.10 # RNTA, RFS +*Want "CFDBRA -0.5 M3 modes 1, 3" BFF00000 00000000 BFF00000 00000000 +R 2370.10 # RNTE, RZ +*Want "CFDBRA -0.5 M3 modes 4, 5" 80000000 00000000 80000000 00000000 +R 2380.10 # RP, RM +*Want "CFDBRA -0.5 M3 modes 6, 7" 80000000 00000000 BFF00000 00000000 + +R 2390.10 # RZ, RP +*Want "CFDBRA 0.5 FPC modes 1, 2" 00000000 00000000 3FF00000 00000000 +R 23A0.10 # RM, RFS +*Want "CFDBRA 0.5 FPC modes 3, 7" 00000000 00000000 3FF00000 00000000 +R 23B0.10 # RNTA, RFS +*Want "CFDBRA 0.5 M3 modes 1, 3" 3FF00000 00000000 3FF00000 00000000 +R 23C0.10 # RNTE, RZ +*Want "CFDBRA 0.5 M3 modes 4, 5" 00000000 00000000 00000000 00000000 +R 23D0.10 # RP, RM +*Want "CFDBRA 0.5 M3 modes 6, 7" 3FF00000 00000000 00000000 00000000 + +R 23E0.10 # RZ, RP +*Want "CFDBRA 1.5 FPC modes 1, 2" 3FF00000 00000000 40000000 00000000 +R 23F0.10 # RM, RFS +*Want "CFDBRA 1.5 FPC modes 3, 7" 3FF00000 00000000 3FF00000 00000000 +R 2400.10 # RNTA, RFS +*Want "CFDBRA 1.5 M3 modes 1, 3" 40000000 00000000 3FF00000 00000000 +R 2410.10 # RNTE, RZ +*Want "CFDBRA 1.5 M3 modes 4, 5" 40000000 00000000 3FF00000 00000000 +R 2420.10 # RP, RM +*Want "CFDBRA 1.5 M3 modes 6, 7" 40000000 00000000 3FF00000 00000000 + +R 2430.10 # RZ, RP +*Want "CFDBRA 2.5 FPC modes 1, 2" 40000000 00000000 40080000 00000000 +R 2440.10 # RM, RFS +*Want "CFDBRA 2.5 FPC modes 3, 7" 40000000 00000000 40080000 00000000 +R 2450.10 # RNTA, RFS +*Want "CFDBRA 2.5 M3 modes 1, 3" 40080000 00000000 40080000 00000000 +R 2460.10 # RNTE, RZ +*Want "CFDBRA 2.5 M3 modes 4, 5" 40000000 00000000 40000000 00000000 +R 2470.10 # RP, RM +*Want "CFDBRA 2.5 M3 modes 6, 7" 40080000 00000000 40000000 00000000 + +R 2480.10 # RZ, RP +*Want "CFDBRA 5.5 FPC modes 1, 2" 40140000 00000000 40180000 00000000 +R 2490.10 # RM, RFS +*Want "CFDBRA 5.5 FPC modes 3, 7" 40140000 00000000 40140000 00000000 +R 24A0.10 # RNTA, RFS +*Want "CFDBRA 5.5 M3 modes 1, 3" 40180000 00000000 40140000 00000000 +R 24B0.10 # RNTE, RZ +*Want "CFDBRA 5.5 M3 modes 4, 5" 40180000 00000000 40140000 00000000 +R 24C0.10 # RP, RM +*Want "CFDBRA 5.5 M3 modes 6, 7" 40180000 00000000 40140000 00000000 + +R 24D0.10 # RZ, RP +*Want "CFDBRA 9.5 FPC modes 1, 2" 40220000 00000000 40240000 00000000 +R 24E0.10 # RM, RFS +*Want "CFDBRA 9.5 FPC modes 3, 7" 40220000 00000000 40220000 00000000 +R 24F0.10 # RNTA, RFS +*Want "CFDBRA 9.5 M3 modes 1, 3" 40240000 00000000 40220000 00000000 +R 2500.10 # RNTE, RZ +*Want "CFDBRA 9.5 M3 modes 4, 5" 40240000 00000000 40220000 00000000 +R 2510.10 # RP, RM +*Want "CFDBRA 9.5 M3 modes 6, 7" 40240000 00000000 40220000 00000000 + +R 2520.10 # RZ, RP +*Want "CFDBRA +0.75 FPC modes 1, 2" 00000000 00000000 3FF00000 00000000 +R 2530.10 # RM, RFS +*Want "CFDBRA +0.75 FPC modes 3, 7" 00000000 00000000 3FF00000 00000000 +R 2540.10 # RNTA, RFS +*Want "CFDBRA +0.75 M3 modes 1, 3" 3FF00000 00000000 3FF00000 00000000 +R 2550.10 # RNTE, RZ +*Want "CFDBRA +0.75 M3 modes 4, 5" 3FF00000 00000000 00000000 00000000 +R 2560.10 # RP, RM +*Want "CFDBRA +0.75 M3 modes 6, 7" 3FF00000 00000000 00000000 00000000 + +R 2570.10 # RZ, RP +*Want "CFDBRA -0.25 FPC modes 1, 2" 80000000 00000000 80000000 00000000 +R 2580.10 # RM, RFS +*Want "CFDBRA -0.25 FPC modes 3, 7" BFF00000 00000000 BFF00000 00000000 +R 2590.10 # RNTA, RFS +*Want "CFDBRA -0.25 M3 modes 1, 3" 80000000 00000000 BFF00000 00000000 +R 25A0.10 # RNTE, RZ +*Want "CFDBRA -0.25 M3 modes 4, 5" 80000000 00000000 80000000 00000000 +R 25B0.10 # RP, RM +*Want "CFDBRA -0.25 M3 modes 6, 7" 80000000 00000000 BFF00000 00000000 + + +# rounding mode tests - long BFP - FPCR contents with cc in last byte +*Compare +R 2800.10 +*Want "CFDBRA -9.5 FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +R 2810.10 +*Want "CFDBRA -9.5 M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +R 2820.08 +*Want "CFDBRA -9.5 M3 modes 6, 7 FCPR" 00080000 00080000 + +R 2830.10 +*Want "CFDBRA -5.5 FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +R 2840.10 +*Want "CFDBRA -5.5 M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +R 2850.08 +*Want "CFDBRA -5.5 M3 modes 6, 7 FCPR" 00080000 00080000 + +R 2860.10 +*Want "CFDBRA -2.5 FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +R 2870.10 +*Want "CFDBRA -2.5 M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +R 2880.08 +*Want "CFDBRA -2.5 M3 modes 6, 7 FCPR" 00080000 00080000 + +R 2890.10 +*Want "CFDBRA -1.5 FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +R 28A0.10 +*Want "CFDBRA -1.5 M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +R 28B0.08 +*Want "CFDBRA -1.5 M3 modes 6, 7 FCPR" 00080000 00080000 + +R 28C0.10 +*Want "CFDBRA -0.5 FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +R 28D0.10 +*Want "CFDBRA -0.5 M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +R 28E0.08 +*Want "CFDBRA -0.5 M3 modes 6, 7 FCPR" 00080000 00080000 + +R 28F0.10 +*Want "CFDBRA +0.5 FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +R 2900.10 +*Want "CFDBRA +0.5 M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +R 2910.08 +*Want "CFDBRA +0.5 M3 modes 6, 7 FCPR" 00080000 00080000 + +R 2920.10 +*Want "CFDBRA +1.5 FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +R 2930.10 +*Want "CFDBRA +1.5 M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +R 2940.08 +*Want "CFDBRA +1.5 M3 modes 6, 7 FCPR" 00080000 00080000 + +R 2950.10 +*Want "CFDBRA +2.5 FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +R 2960.10 +*Want "CFDBRA +2.5 M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +R 2970.08 +*Want "CFDBRA +2.5 M3 modes 6, 7 FCPR" 00080000 00080000 + +R 2980.10 +*Want "CFDBRA +5.5 FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +R 2990.10 +*Want "CFDBRA +5.5 M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +R 29A0.08 +*Want "CFDBRA +5.5 M3 modes 6, 7 FCPR" 00080000 00080000 + +R 29B0.10 +*Want "CFDBRA +9.5 FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +R 29C0.10 +*Want "CFDBRA +9.5 M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +R 29D0.08 +*Want "CFDBRA +9.5 M3 modes 6, 7 FCPR" 00080000 00080000 + +R 29E0.10 +*Want "CFDBRA +0.75 FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +R 29F0.10 +*Want "CFDBRA +0.75 M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +R 2A00.08 +*Want "CFDBRA +0.75 M3 modes 6, 7 FCPR" 00080000 00080000 + +R 2A10.10 +*Want "CFDBRA -0.25 FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +R 2A20.10 +*Want "CFDBRA -0.25 M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +R 2A30.08 +*Want "CFDBRA -0.25 M3 modes 6, 7 FCPR" 00080000 00080000 + + +# Results from extended BFP rounded to extended BFP integer +*Compare +r 3000.10 +*Want "CFXBR result pair 1a" 3FFF0000 00000000 00000000 00000000 +r 3010.10 +*Want "CFXBR result pair 1b" 3FFF0000 00000000 00000000 00000000 +r 3020.10 +*Want "CFXBR result pair 2a" C0000000 00000000 00000000 00000000 +r 3030.10 +*Want "CFXBR result pair 2b" C0000000 00000000 00000000 00000000 +r 3040.10 +*Want "CFXBR result pair 3a" 40000000 00000000 00000000 00000000 +r 3050.10 +*Want "CFXBR result pair 3b" 40000000 00000000 00000000 00000000 +r 3060.10 +*Want "CFXBR result pair 4a" 7FFF8100 00000000 00000000 00000000 +r 3070.10 +*Want "CFXBR result pair 4b" 00000000 00000000 00000000 00000000 +r 3080.10 +*Want "CFXBR result pair 5a" 7FFF8100 00000000 00000000 00000000 +r 3090.10 +*Want "CFXBR result pair 5b" 7FFF8100 00000000 00000000 00000000 +r 30A0.10 +*Want "CFXBR result pair 6a" 3FFF0000 00000000 00000000 00000000 +r 30B0.10 +*Want "CFXBR result pair 6b" 3FFF0000 00000000 00000000 00000000 +r 30C0.10 +*Want "CFXBR result pair 7a" 80000000 00000000 00000000 00000000 +r 30D0.10 +*Want "CFXBR result pair 7b" 80000000 00000000 00000000 00000000 + +# Results from extended BFP rounded to extended BFP integer - FPC +*Compare +r 3200.10 +*Want "CFXBR FPC pairs 1-2" 00000000 F8000000 00080000 F8000C00 +r 3210.10 +*Want "CFXBR FPC pairs 3-4" 00080000 F8000800 00800000 F8008000 +r 3220.10 +*Want "CFXBR FPC pairs 5-6" 00000000 F8000000 00080000 F8000C00 +r 3230.08 +*Want "CFXBR FPC pair 7" 00080000 F8000800 + + +# rounding mode tests - extended BFP - results from rounding +*Compare +R 3300.10 # RZ +*Want "CFXBRA -9.5 FPC mode 1" C0022000 00000000 00000000 00000000 +R 3310.10 # RP +*Want "CFXBRA -9.5 FPC mode 2" C0022000 00000000 00000000 00000000 +R 3320.10 # RM +*Want "CFXBRA -9.5 FPC mode 3" C0024000 00000000 00000000 00000000 +R 3330.10 # RFS +*Want "CFXBRA -9.5 FPC mode 7" C0022000 00000000 00000000 00000000 +R 3340.10 # RP +*Want "CFXBRA -9.5 M3 mode 1" C0024000 00000000 00000000 00000000 +R 3350.10 # RP +*Want "CFXBRA -9.5 M3 mode 3" C0022000 00000000 00000000 00000000 +R 3360.10 # RM +*Want "CFXBRA -9.5 M3 mode 4" C0024000 00000000 00000000 00000000 +R 3370.10 # RFS +*Want "CFXBRA -9.5 M3 mode 5" C0022000 00000000 00000000 00000000 +R 3380.10 # RP +*Want "CFXBRA -9.5 M3 mode 6" C0022000 00000000 00000000 00000000 +R 3390.10 # RM +*Want "CFXBRA -9.5 M3 mode 7" C0024000 00000000 00000000 00000000 + +R 33A0.10 # RZ +*Want "CFXBRA -5.5 FPC mode 1" C0014000 00000000 00000000 00000000 +R 33B0.10 # RP +*Want "CFXBRA -5.5 FPC mode 2" C0014000 00000000 00000000 00000000 +R 33C0.10 # RM +*Want "CFXBRA -5.5 FPC mode 3" C0018000 00000000 00000000 00000000 +R 33D0.10 # RFS +*Want "CFXBRA -5.5 FPC mode 7" C0014000 00000000 00000000 00000000 +R 33E0.10 # RNTA +*Want "CFXBRA -5.5 M3 mode 1" C0018000 00000000 00000000 00000000 +R 33F0.10 # RFS +*Want "CFXBRA -5.5 M3 mode 3" C0014000 00000000 00000000 00000000 +R 3400.10 # RNTE +*Want "CFXBRA -5.5 M3 mode 4" C0018000 00000000 00000000 00000000 +R 3410.10 # RZ +*Want "CFXBRA -5.5 M3 mode 5" C0014000 00000000 00000000 00000000 +R 3420.10 # RP +*Want "CFXBRA -5.5 M3 mode 6" C0014000 00000000 00000000 00000000 +R 3430.10 # RM +*Want "CFXBRA -5.5 M3 mode 7" C0018000 00000000 00000000 00000000 + +R 3440.10 # RZ +*Want "CFXBRA -2.5 FPC mode 1" C0000000 00000000 00000000 00000000 +R 3450.10 # RP +*Want "CFXBRA -2.5 FPC mode 2" C0000000 00000000 00000000 00000000 +R 3460.10 # RM +*Want "CFXBRA -2.5 FPC mode 3" C0008000 00000000 00000000 00000000 +R 3470.10 # RFS +*Want "CFXBRA -2.5 FPC mode 7" C0008000 00000000 00000000 00000000 +R 3480.10 # RNTA +*Want "CFXBRA -2.5 M3 mode 1" C0008000 00000000 00000000 00000000 +R 3490.10 # RFS +*Want "CFXBRA -2.5 M3 mode 3" C0008000 00000000 00000000 00000000 +R 34A0.10 # RNTE +*Want "CFXBRA -2.5 M3 mode 4" C0000000 00000000 00000000 00000000 +R 34B0.10 # RZ +*Want "CFXBRA -2.5 M3 mode 5" C0000000 00000000 00000000 00000000 +R 34C0.10 # RP +*Want "CFXBRA -2.5 M3 mode 6" C0000000 00000000 00000000 00000000 +R 34D0.10 # RM +*Want "CFXBRA -2.5 M3 mode 7" C0008000 00000000 00000000 00000000 + +R 34E0.10 # RZ +*Want "CFXBRA -1.5 FPC mode 1" BFFF0000 00000000 00000000 00000000 +R 34F0.10 # RP +*Want "CFXBRA -1.5 FPC mode 2" BFFF0000 00000000 00000000 00000000 +R 3500.10 # RM +*Want "CFXBRA -1.5 FPC mode 3" C0000000 00000000 00000000 00000000 +R 3510.10 # RFS +*Want "CFXBRA -1.5 FPC mode 7" BFFF0000 00000000 00000000 00000000 +R 3520.10 # RNTA +*Want "CFXBRA -1.5 M3 mode 1" C0000000 00000000 00000000 00000000 +R 3530.10 # RFS +*Want "CFXBRA -1.5 M3 mode 3" BFFF0000 00000000 00000000 00000000 +R 3540.10 # RNTE +*Want "CFXBRA -1.5 M3 mode 4" C0000000 00000000 00000000 00000000 +R 3550.10 # RZ +*Want "CFXBRA -1.5 M3 mode 5" BFFF0000 00000000 00000000 00000000 +R 3560.10 # RP +*Want "CFXBRA -1.5 M3 mode 6" BFFF0000 00000000 00000000 00000000 +R 3570.10 # RM +*Want "CFXBRA -1.5 M3 mode 7" C0000000 00000000 00000000 00000000 + +R 3580.10 # RZ +*Want "CFXBRA -0.5 FPC mode 1" 80000000 00000000 00000000 00000000 +R 3590.10 # RP +*Want "CFXBRA -0.5 FPC mode 2" 80000000 00000000 00000000 00000000 +R 35A0.10 # RM +*Want "CFXBRA -0.5 FPC mode 3" BFFF0000 00000000 00000000 00000000 +R 35B0.10 # RFS +*Want "CFXBRA -0.5 FPC mode 7" BFFF0000 00000000 00000000 00000000 +R 35C0.10 # RNTA +*Want "CFXBRA -0.5 M3 mode 1" BFFF0000 00000000 00000000 00000000 +R 35D0.10 # RFS +*Want "CFXBRA -0.5 M3 mode 3" BFFF0000 00000000 00000000 00000000 +R 35E0.10 # RNTE +*Want "CFXBRA -0.5 M3 mode 4" 80000000 00000000 00000000 00000000 +R 35F0.10 # RZ +*Want "CFXBRA -0.5 M3 mode 5" 80000000 00000000 00000000 00000000 +R 3600.10 # RP +*Want "CFXBRA -0.5 M3 mode 6" 80000000 00000000 00000000 00000000 +R 3610.10 # RM +*Want "CFXBRA -0.5 M3 mode 7" BFFF0000 00000000 00000000 00000000 + +R 3620.10 # RZ +*Want "CFXBRA 0.5 FPC mode 1" 00000000 00000000 00000000 00000000 +R 3630.10 # RP +*Want "CFXBRA 0.5 FPC mode 2" 3FFF0000 00000000 00000000 00000000 +R 3640.10 # RM +*Want "CFXBRA 0.5 FPC mode 3" 00000000 00000000 00000000 00000000 +R 3650.10 # RFS +*Want "CFXBRA 0.5 FPC mode 7" 3FFF0000 00000000 00000000 00000000 +R 3660.10 # RNTA +*Want "CFXBRA 0.5 M3 mode 1" 3FFF0000 00000000 00000000 00000000 +R 3670.10 # RFS +*Want "CFXBRA 0.5 M3 mode 3" 3FFF0000 00000000 00000000 00000000 +R 3680.10 # RNTE +*Want "CFXBRA 0.5 M3 mode 4" 00000000 00000000 00000000 00000000 +R 3690.10 # RZ +*Want "CFXBRA 0.5 M3 mode 5" 00000000 00000000 00000000 00000000 +R 36A0.10 # RP +*Want "CFXBRA 0.5 M3 mode 6" 3FFF0000 00000000 00000000 00000000 +R 36B0.10 # RM +*Want "CFXBRA 0.5 M3 mode 7" 00000000 00000000 00000000 00000000 + +R 36C0.10 # RZ +*Want "CFXBRA 1.5 FPC mode 1" 3FFF0000 00000000 00000000 00000000 +R 36D0.10 # RP +*Want "CFXBRA 1.5 FPC mode 2" 40000000 00000000 00000000 00000000 +R 36E0.10 # RM +*Want "CFXBRA 1.5 FPC mode 3" 3FFF0000 00000000 00000000 00000000 +R 36F0.10 # RFS +*Want "CFXBRA 1.5 FPC mode 7" 3FFF0000 00000000 00000000 00000000 +R 3700.10 # RNTA +*Want "CFXBRA 1.5 M3 mode 1" 40000000 00000000 00000000 00000000 +R 3710.10 # RFS +*Want "CFXBRA 1.5 M3 mode 3" 3FFF0000 00000000 00000000 00000000 +R 3720.10 # RNTE +*Want "CFXBRA 1.5 M3 mode 4" 40000000 00000000 00000000 00000000 +R 3730.10 # RZ +*Want "CFXBRA 1.5 M3 mode 5" 3FFF0000 00000000 00000000 00000000 +R 3740.10 # RP +*Want "CFXBRA 1.5 M3 mode 6" 40000000 00000000 00000000 00000000 +R 3750.10 # RM +*Want "CFXBRA 1.5 M3 mode 7" 3FFF0000 00000000 00000000 00000000 + +R 3760.10 # RZ +*Want "CFXBRA 2.5 FPC mode 1" 40000000 00000000 00000000 00000000 +R 3770.10 # RP +*Want "CFXBRA 2.5 FPC mode 2" 40008000 00000000 00000000 00000000 +R 3780.10 # RM +*Want "CFXBRA 2.5 FPC mode 3" 40000000 00000000 00000000 00000000 +R 3790.10 # RFS +*Want "CFXBRA 2.5 FPC mode 7" 40008000 00000000 00000000 00000000 +R 37A0.10 # RNTA +*Want "CFXBRA 2.5 M3 mode 1" 40008000 00000000 00000000 00000000 +R 37B0.10 # RFS +*Want "CFXBRA 2.5 M3 mode 3" 40008000 00000000 00000000 00000000 +R 37C0.10 # RNTE +*Want "CFXBRA 2.5 M3 mode 4" 40000000 00000000 00000000 00000000 +R 37D0.10 # RZ +*Want "CFXBRA 2.5 M3 mode 5" 40000000 00000000 00000000 00000000 +R 37E0.10 # RP +*Want "CFXBRA 2.5 M3 mode 6" 40008000 00000000 00000000 00000000 +R 37F0.10 # RM +*Want "CFXBRA 2.5 M3 mode 7" 40000000 00000000 00000000 00000000 + +R 3800.10 # RZ +*Want "CFXBRA 5.5 FPC mode 1" 40014000 00000000 00000000 00000000 +R 3810.10 # RP +*Want "CFXBRA 5.5 FPC mode 2" 40018000 00000000 00000000 00000000 +R 3820.10 # RM +*Want "CFXBRA 5.5 FPC mode 3" 40014000 00000000 00000000 00000000 +R 3830.10 # RFS +*Want "CFXBRA 5.5 FPC mode 7" 40014000 00000000 00000000 00000000 +R 3840.10 # RNTA +*Want "CFXBRA 5.5 M3 mode 1" 40018000 00000000 00000000 00000000 +R 3850.10 # RFS +*Want "CFXBRA 5.5 M3 mode 3" 40014000 00000000 00000000 00000000 +R 3860.10 # RNTE +*Want "CFXBRA 5.5 M3 mode 4" 40018000 00000000 00000000 00000000 +R 3870.10 # RZ +*Want "CFXBRA 5.5 M3 mode 5" 40014000 00000000 00000000 00000000 +R 3880.10 # RP +*Want "CFXBRA 5.5 M3 mode 6" 40018000 00000000 00000000 00000000 +R 3890.10 # RM +*Want "CFXBRA 5.5 M3 mode 7" 40014000 00000000 00000000 00000000 + +R 38A0.10 # RZ +*Want "CFXBRA 9.5 FPC mode 1" 40022000 00000000 00000000 00000000 +R 38B0.10 # RP +*Want "CFXBRA 9.5 FPC mode 2" 40024000 00000000 00000000 00000000 +R 38C0.10 # RM +*Want "CFXBRA 9.5 FPC mode 3" 40022000 00000000 00000000 00000000 +R 38D0.10 # RFS +*Want "CFXBRA 9.5 FPC mode 7" 40022000 00000000 00000000 00000000 +R 38E0.10 # RNTA +*Want "CFXBRA 9.5 M3 mode 1" 40024000 00000000 00000000 00000000 +R 38F0.10 # RFS +*Want "CFXBRA 9.5 M3 mode 3" 40022000 00000000 00000000 00000000 +R 3900.10 # RNTE +*Want "CFXBRA 9.5 M3 mode 4" 40024000 00000000 00000000 00000000 +R 3910.10 # RZ +*Want "CFXBRA 9.5 M3 mode 5" 40022000 00000000 00000000 00000000 +R 3920.10 # RP +*Want "CFXBRA 9.5 M3 mode 6" 40024000 00000000 00000000 00000000 +R 3930.10 # RM +*Want "CFXBRA 9.5 M3 mode 7" 40022000 00000000 00000000 00000000 + +r 3940.10 # RZ +*Want "CFXBRA +0.75 FPC mode 1" 00000000 00000000 00000000 00000000 +r 3950.10 # RP +*Want "CFXBRA +0.75 FPC mode 2" 3FFF0000 00000000 00000000 00000000 +r 3960.10 # RM +*Want "CFXBRA +0.75 FPC mode 3" 00000000 00000000 00000000 00000000 +r 3970.10 # RFS +*Want "CFXBRA +0.75 FPC mode 7" 3FFF0000 00000000 00000000 00000000 +r 3980.10 # RNTA +*Want "CFXBRA +0.75 M3 mode 1" 3FFF0000 00000000 00000000 00000000 +r 3990.10 # RFS +*Want "CFXBRA +0.75 M3 mode 3" 3FFF0000 00000000 00000000 00000000 +R 39A0.10 # RNTE +*Want "CFXBRA +0.75 M3 mode 4" 3FFF0000 00000000 00000000 00000000 +R 39B0.10 # RZ +*Want "CFXBRA +0.75 M3 mode 5" 00000000 00000000 00000000 00000000 +R 39C0.10 # RP +*Want "CFXBRA +0.75 M3 mode 6" 3FFF0000 00000000 00000000 00000000 +R 39D0.10 # RM +*Want "CFXBRA +0.75 M3 mode 7" 00000000 00000000 00000000 00000000 + +r 39E0.10 # RZ +*Want "CFXBRA -0.25 FPC mode 1" 80000000 00000000 00000000 00000000 +r 39F0.10 # RP +*Want "CFXBRA -0.25 FPC mode 2" 80000000 00000000 00000000 00000000 +r 3A00.10 # RM +*Want "CFXBRA -0.25 FPC mode 3" BFFF0000 00000000 00000000 00000000 +r 3A10.10 # RFS +*Want "CFXBRA -0.25 FPC mode 7" BFFF0000 00000000 00000000 00000000 +r 3A20.10 # RNTA +*Want "CFXBRA -0.25 M3 mode 1" 80000000 00000000 00000000 00000000 +r 3A30.10 # RFS +*Want "CFXBRA -0.25 M3 mode 3" BFFF0000 00000000 00000000 00000000 +r 3A40.10 # RNTE +*Want "CFXBRA -0.25 M3 mode 4" 80000000 00000000 00000000 00000000 +r 3A50.10 # RZ +*Want "CFXBRA -0.25 M3 mode 5" 80000000 00000000 00000000 00000000 +r 3A60.10 # RP +*Want "CFXBRA -0.25 M3 mode 6" 80000000 00000000 00000000 00000000 +r 3A70.10 # RM +*Want "CFXBRA -0.25 M3 mode 7" BFFF0000 00000000 00000000 00000000 + + +# rounding mode tests - extended BFP - FPCR contents with cc in last byte +*Compare +R 3F00.10 +*Want "CFXBRA -9.5 FPC mode 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +R 3F10.10 +*Want "CFXBRA -9.5 M3 mode 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +R 3F20.08 +*Want "CFXBRA -9.5 M3 mode 6, 7 FCPR" 00080000 00080000 + +R 3F30.10 +*Want "CFXBRA -5.5 FPC mode 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +R 3F40.10 +*Want "CFXBRA -5.5 M3 mode 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +R 3F50.08 +*Want "CFXBRA -5.5 M3 mode 6, 7 FCPR" 00080000 00080000 + +R 3F60.10 +*Want "CFXBRA -2.5 FPC mode 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +R 3F70.10 +*Want "CFXBRA -2.5 M3 mode 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +R 3F80.08 +*Want "CFXBRA -2.5 M3 mode 6, 7 FCPR" 00080000 00080000 + +R 3F90.10 +*Want "CFXBRA -1.5 FPC mode 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +R 3FA0.10 +*Want "CFXBRA -1.5 M3 mode 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +R 3FB0.08 +*Want "CFXBRA -1.5 M3 mode 6, 7 FCPR" 00080000 00080000 + +R 3FC0.10 +*Want "CFXBRA -0.5 FPC mode 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +R 3FD0.10 +*Want "CFXBRA -0.5 M3 mode 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +R 3FE0.08 +*Want "CFXBRA -0.5 M3 mode 6, 7 FCPR" 00080000 00080000 + +R 3FF0.10 +*Want "CFXBRA +0.5 FPC mode 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +R 4000.10 +*Want "CFXBRA +0.5 M3 mode 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +R 4010.08 +*Want "CFXBRA +0.5 M3 mode 6, 7 FCPR" 00080000 00080000 + +R 4020.10 +*Want "CFXBRA +1.5 FPC mode 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +R 4030.10 +*Want "CFXBRA +1.5 M3 mode 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +R 4040.08 +*Want "CFXBRA +1.5 M3 mode 6, 7 FCPR" 00080000 00080000 + +R 4050.10 +*Want "CFXBRA +2.5 FPC mode 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +R 4060.10 +*Want "CFXBRA +2.5 M3 mode 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +R 4070.08 +*Want "CFXBRA +2.5 M3 mode 6, 7 FCPR" 00080000 00080000 + +R 4080.10 +*Want "CFXBRA +5.5 FPC mode 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +R 4090.10 +*Want "CFXBRA +5.5 M3 mode 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +R 40A0.08 +*Want "CFXBRA +5.5 M3 mode 6, 7 FCPR" 00080000 00080000 + +R 40B0.10 +*Want "CFXBRA +9.5 FPC mode 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +R 40C0.10 +*Want "CFXBRA +9.5 M3 mode 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +R 40D0.08 +*Want "CFXBRA +9.5 M3 mode 6, 7 FCPR" 00080000 00080000 + +R 40E0.10 +*Want "CFXBRA +0.75 FPC mode 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +R 40F0.10 +*Want "CFXBRA +0.75 M3 mode 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +R 4100.08 +*Want "CFXBRA +0.75 M3 mode 6, 7 FCPR" 00080000 00080000 + +R 4110.10 +*Want "CFXBRA -0.25 FPC mode 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +R 4120.10 +*Want "CFXBRA -0.25 M3 mode 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +R 4130.08 +*Want "CFXBRA -0.25 M3 mode 6, 7 FCPR" 00080000 00080000 + + +*Done + diff --git a/tests/bfp-004-cvttolog.asm b/tests/bfp-004-cvttolog.asm new file mode 100644 index 000000000..0e07b767a --- /dev/null +++ b/tests/bfp-004-cvttolog.asm @@ -0,0 +1,906 @@ + TITLE 'bfp-004-cvttolog.asm: Test IEEE Convert To Logical (uint-32)' +*********************************************************************** +* +*Testcase IEEE CONVERT TO LOGICAL 32 +* Test case capability includes ieee exceptions trappable and +* otherwise. Test results, FPCR flags, DXC, and condition codes are +* saved for all tests. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* bfp-004-cvttolog.asm +* +* This assembly-language source file is part of the +* Hercules Decimal Floating Point Validation Package +* by Stephen R. Orso +* +* Copyright 2016 by Stephen R Orso. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* +* 3. The name of the author may not be used to endorse or promote +* products derived from this software without specific prior written +* permission. +* +* DISCLAMER: THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* HOLDER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* Tests the following three conversion instructions +* CONVERT TO LOGICAL (short BFP to uint-32, RRF-e) +* CONVERT TO LOGICAL (long BFP to uint-32, RRF-e) +* CONVERT TO LOGICAL (extended BFP to uint-32, RRF-e) +* +* Test data is compiled into this program. The test script that runs +* this program can provide alternative test data through Hercules R +* commands. +* +* Test Case Order +* 1) Short BFP to uint-32 +* 2) Short BFP to uint-32 with all rounding modes +* 3) Long BFP uint-32 +* 3) Long BFP uint-32 with all rounding modes +* 4) Extended BFP to uint-32 +* 4) Extended BFP to uint-32 with all rounding modes +* +* Three input test data sets are provided, one each for short, long, +* and extended precision BFP. All are converted to uint-32. +* +* Provided test data is 1, 2, 4, 9, QNaN, SNaN, 4294967295.5. +* The last three values will trigger inexact exceptions when +* converted to uint-32. The last value is present only in the long +* and extended BFP test cases and should overflow a uint-32. +* Provided test data for rounding tests is taken from Table 9-11 on +* page 9-16 of SA22-7832-10. +* -1.5, -0.5, +0.5, +1.5, +2.5, +5.5, +9.5. +* While the table illustrates LOAD FP INTEGER, the same results +* should be generated when creating a uint-32 or uint-64 from BFP. +* For long BFP and extended BFP rounding mode tests, ond additional +* test case is included: 4294967294.5. This case rounds down to a +* maximum uint-32 and rounds up to overflow; it tests the case where +* the input is greater than a maximum uint-32 but rounds to a maximum +* uint-32. See Table 19-19 on page 19-26 of SA22-7832-10 for details +* on this boundary condition test. +* +* Also tests the following floating point support instructions +* LOAD (Short) +* LOAD (Long) +* LOAD FPC +* SRNMB (Set BFP Rounding Mode 2-bit) +* SRNMB (Set BFP Rounding Mode 3-bit) +* STORE (Short) +* STORE (Long) +* STORE FPC +* +* +*********************************************************************** + SPACE 2 + MACRO + PADCSECT &ENDLABL +.* +.* Macro to pad the CSECT to include result data areas if this test +.* program is not being assembled using asma. asma generates a core +.* image that is loaded by the loadcore command, and because the +.* core image is a binary stored in Github, it makes sense to make +.* this small effort to keep the core image small. +.* + AIF (D'&ENDLABL).GOODPAD + MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + MNOTE *,'No CSECT padding performed' + MEXIT +.* +.GOODPAD ANOP Label valid. See if we're on asma + AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + ORG &ENDLABL-1 Not ASMA. Pad CSECT + MEXIT +.* +.NOPAD ANOP + MNOTE *,'asma detected; no CSECT padding performed' + MEND +* +* Note: for compatibility with the z/CMS test rig, do not change +* or use R11, R14, or R15. Everything else is fair game. +* +BFPCVTTL START 0 +R0 EQU 0 +R1 EQU 1 +R2 EQU 2 +R3 EQU 3 +R4 EQU 4 +R5 EQU 5 +R6 EQU 6 +R7 EQU 7 +R8 EQU 8 +R9 EQU 9 +R10 EQU 10 +R11 EQU 11 +R12 EQU 12 +R13 EQU 13 +R14 EQU 14 +R15 EQU 15 +* +* Floating Point Register equates to keep the cross reference clean +* +FPR0 EQU 0 +FPR1 EQU 1 +FPR2 EQU 2 +FPR3 EQU 3 +FPR4 EQU 4 +FPR5 EQU 5 +FPR6 EQU 6 +FPR7 EQU 7 +FPR8 EQU 8 +FPR9 EQU 9 +FPR10 EQU 10 +FPR11 EQU 11 +FPR12 EQU 12 +FPR13 EQU 13 +FPR14 EQU 14 +FPR15 EQU 15 +* + USING *,R15 +* +* Above works on real iron (R15=0 after sysclear) +* and in z/CMS (R15 points to start of load module) +* + ORG BFPCVTTL+X'8E' Program check interrution code +PCINTCD DS H +* +PCOLDPSW EQU BFPCVTTL+X'150' z/Arch Program check old PSW +* + ORG BFPCVTTL+X'1A0' z/Arch Restart PSW + DC X'0000000180000000',AD(START) +* + ORG BFPCVTTL+X'1D0' z/Arch Program check old PSW + DC X'0000000000000000',AD(PROGCHK) +* +* Program check routine. If Data Exception, continue execution at +* the instruction following the program check. Otherwise, hard wait. +* No need to collect data. All interesting DXC stuff is captured +* in the FPCR. +* + ORG BFPCVTTL+X'200' +PROGCHK DS 0H Program check occured... + CLI PCINTCD+1,X'07' Data Exception? + JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) + LPSWE PCOLDPSW ..yes, resume program execution +PCNOTDTA DS 0H + LTR R14,R14 Return address provided? + BNZR R14 Yes, return to z/CMS test rig. + LPSWE HARDWAIT Not data exception, enter disabled wait + EJECT +*********************************************************************** +* +* Main program. Enable Advanced Floating Point, process test cases. +* +*********************************************************************** + SPACE 2 +START STCTL R0,R0,CTLR0 Store CR0 to enable AFP + OI CTLR0+1,X'04' Turn on AFP bit + LCTL R0,R0,CTLR0 Reload updated CR0 +* +* Short BFP Input testing +* + LA R10,SHORTS Point to short BFP test inputs + BAS R13,CLFEBR Convert values to uint-32 from short BFP + LA R10,RMSHORTS Point to inputs for rounding mode tests + BAS R13,CLFEBRA Convert using all rounding mode options +* +* Short BFP Input testing +* + LA R10,LONGS Point to long BFP test inputs + BAS R13,CLFDBR Convert values to uint-32 from long BFP + LA R10,RMLONGS Point to inputs for rounding mode tests + BAS R13,CLFDBRA Convert using all rounding mode options +* +* Short BFP Input testing +* + LA R10,EXTDS Point to extended BFP test inputs + BAS R13,CLFXBR Convert values to uint-32 from extended + LA R10,RMEXTDS Point to inputs for rounding mode tests + BAS R13,CLFXBRA Convert using all rounding mode options +* + LTR R14,R14 Return address provided? + BNZR R14 ..Yes, return to z/CMS test rig. + LPSWE WAITPSW All done +* + DS 0D Ensure correct alignment for psw +WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end +* +CTLR0 DS F +FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags +* +* Input values parameter list, four fullwords: +* 1) Count, +* 2) Address of inputs, +* 3) Address to place results, and +* 4) Address to place DXC/Flags/cc values. +* + ORG BFPCVTTL+X'300' +SHORTS DS 0F Inputs for short BFP testing + DC A(SBFPCT/4) + DC A(SBFPIN) + DC A(SINTOUT) + DC A(SINTFLGS) +* +LONGS DS 0F Inputs for long BFP testing + DC A(LBFPCT/8) + DC A(LBFPIN) + DC A(LINTOUT) + DC A(LINTFLGS) +* +EXTDS DS 0F Inputs for Extended BFP testing + DC A(XBFPCT/16) + DC A(XBFPIN) + DC A(XINTOUT) + DC A(XINTFLGS) +* +RMSHORTS DC A(SBFPRMCT/4) + DC A(SBFPINRM) Short BFP rounding mode test inputs + DC A(SINTRMO) Short BFP rounding mode test results + DC A(SINTRMOF) Short BFP rounding mode test flags +* +RMLONGS DC A(LBFPRMCT/8) + DC A(LBFPINRM) Long BFP rounding mode test inputs + DC A(LINTRMO) Long BFP rounding mode test results + DC A(LINTRMOF) Long BFP rounding mode test flags +* +RMEXTDS DC A(XBFPRMCT/16) + DC A(XBFPINRM) Extended BFP rounding mode test inputs + DC A(XINTRMO) Extended BFP rounding mode test results + DC A(XINTRMOF) Extended BFP rounding mode test flags + EJECT +*********************************************************************** +* +* Convert short BFP to uint-32 format. A pair of results is generated +* for each input: one with all exceptions non-trappable, and the second +* with all exceptions trappable. The FPCR and condition code is +* stored for each result. +* +*********************************************************************** + SPACE 2 +CLFEBR LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LE FPR0,0(,R3) Get short BFP test value + LFPC FPCREGNT Set exceptions non-trappable + CLFEBR R1,0,FPR0,0 Cvt float in FPR0 to uint-32 in GPR1 + ST R1,0(,R7) Store int-32 result + STFPC 0(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,3(,R8) Save condition code as low byte of FPCR +* + LFPC FPCREGTR Set exceptions trappable + XR R1,R1 Clear any residual result in R1 + SPM R1 Clear out any residual nz condition code + CLFEBR R1,0,FPR0,0 Cvt float in FPR0 to uint-32 in GPR1 + ST R1,4(,R7) Store short BFP result + STFPC 4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,7(,R8) Save condition code as low byte of FPCR +* + LA R3,4(,R3) Point to next input values + LA R7,8(,R7) Point to next int-32 converted value pair + LA R8,8(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert short BFP to integers using each possible rounding mode. +* Ten test results are generated for each input. A 48-byte test result +* section is used to keep results sets aligned on a quad-double word. +* +* The first four tests use rounding modes specified in the FPCR with +* the IEEE Inexact exception supressed. SRNM (2-bit) is used for +* the first two FPCR-controlled tests and SRNMB (3-bit) is used for +* the last two To get full coverage of that instruction pair. +* +* The next six results use instruction-specified rounding modes. +* +* The default rounding mode (0 for RNTE) is not tested in this section; +* prior tests used the default rounding mode. RNTE is tested +* explicitly as a rounding mode in this section. +* +*********************************************************************** + SPACE 2 +CLFEBRA LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LE FPR0,0(,R3) Get short BFP test value +* +* Test cases using rounding mode specified in the FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 1 SET FPCR to RZ, towards zero. + CLFEBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked + ST R1,0*4(,R7) Store uint-32 result + STFPC 0(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,3(,R8) Save condition code as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 2 SET FPCR to RP, to +infinity + CLFEBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked + ST R1,1*4(,R7) Store uint-32 result + STFPC 1*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(1*4)+3(,R8) Save condition code as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 3 SET FPCR to RM, to -infinity + CLFEBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked + ST R1,2*4(,R7) Store uint-32 result + STFPC 2*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(2*4)+3(,R8) Save condition code as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 7 RFS, Prepare for Shorter Precision + CLFEBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked + ST R1,3*4(,R7) Store uint-32 result + STFPC 3*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(3*4)+3(,R8) Save condition code as low byte of FPCR +* +* Test cases using rounding mode specified in the instruction M3 field +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLFEBR R1,1,FPR0,B'0000' RNTA, to nearest, ties away + ST R1,4*4(,R7) Store uint-32 result + STFPC 4*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(4*4)+3(,R8) Save condition code as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLFEBR R1,3,FPR0,B'0000' RFS, prepare for shorter precision + ST R1,5*4(,R7) Store uint-32 result + STFPC 5*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(5*4)+3(,R8) Save condition code as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLFEBR R1,4,FPR0,B'0000' RNTE, to nearest, ties to even + ST R1,6*4(,R7) Store uint-32 result + STFPC 6*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(6*4)+3(,R8) Save condition code as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLFEBR R1,5,FPR0,B'0000' RZ, toward zero + ST R1,7*4(,R7) Store uint-32 result + STFPC 7*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(7*4)+3(,R8) Save condition code as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLFEBR R1,6,FPR0,B'0000' RP, to +inf + ST R1,8*4(,R7) Store uint-32 result + STFPC 8*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(8*4)+3(,R8) Save condition code as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLFEBR R1,7,FPR0,B'0000' RM, to -inf + ST R1,9*4(,R7) Store uint-32 result + STFPC 9*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(9*4)+3(,R8) Save condition code as low byte of FPCR +* + LA R3,4(,R3) Point to next input value + LA R7,12*4(,R7) Point to next uint-32 result set + LA R8,12*4(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert long BFP inputs to uint-32. A pair of results is generated +* for each input: one with all exceptions non-trappable, and the second +* with all exceptions trappable. The FPCR and condition code is +* stored for each result. +* +*********************************************************************** + SPACE 2 +CLFDBR LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LD FPR0,0(,R3) Get long BFP test value + LFPC FPCREGNT Set exceptions non-trappable + CLFDBR R1,0,FPR0,0 Cvt float in FPR0 to uint-32 in GPR1 + ST R1,0(,R7) Store long BFP result + STFPC 0(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,3(,R8) Save condition code as low byte of FPCR +* + LFPC FPCREGTR Set exceptions trappable + XR R1,R1 Clear any residual result in R1 + SPM R1 Clear out any residual nz condition code + CLFDBR R1,0,FPR0,0 Cvt float in FPR0 to uint-32 in GPR1 + ST R1,4(,R7) Store int-32 result + STFPC 4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,7(,R8) Save condition code as low byte of FPCR +* + LA R3,8(,R3) Point to next input values + LA R7,8(,R7) Point to next uint-32 converted value pair + LA R8,8(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert long BFP to integers using each possible rounding mode. +* Ten test results are generated for each input. A 48-byte test result +* section is used to keep results sets aligned on a quad-double word. +* +* The first four tests use rounding modes specified in the FPCR with +* the IEEE Inexact exception supressed. SRNM (2-bit) is used for +* thefirst two FPCR-controlled tests and SRNMB (3-bit) is used for +* the last two To get full coverage of that instruction pair. +* +* The next six results use instruction-specified rounding modes. +* +* The default rounding mode (0 for RNTE) is not tested in this section; +* prior tests used the default rounding mode. RNTE is tested +* explicitly as a rounding mode in this section. +* +*********************************************************************** + SPACE 2 +CLFDBRA LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LD FPR0,0(,R3) Get long BFP test value +* +* Test cases using rounding mode specified in the FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 1 SET FPCR to RZ, towards zero. + CLFDBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked + ST R1,0*4(,R7) Store uint-32 result + STFPC 0(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,3(,R8) Save condition code as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 2 SET FPCR to RP, to +infinity + CLFDBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked + ST R1,1*4(,R7) Store uint-32 result + STFPC 1*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(1*4)+3(,R8) Save condition code as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 3 SET FPCR to RM, to -infinity + CLFDBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked + ST R1,2*4(,R7) Store uint-32 result + STFPC 2*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(2*4)+3(,R8) Save condition code as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 7 RFS, Prepare for Shorter Precision + CLFDBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked + ST R1,3*4(,R7) Store uint-32 result + STFPC 3*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(3*4)+3(,R8) Save condition code as low byte of FPCR +* +* Test cases using rounding mode specified in the instruction M3 field +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLFDBR R1,1,FPR0,B'0000' RNTA, to nearest, ties away + ST R1,4*4(,R7) Store uint-32 result + STFPC 4*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(4*4)+3(,R8) Save condition code as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLFDBR R1,3,FPR0,B'0000' RFS, prepare for shorter precision + ST R1,5*4(,R7) Store uint-32 result + STFPC 5*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(5*4)+3(,R8) Save condition code as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLFDBR R1,4,FPR0,B'0000' RNTE, to nearest, ties to even + ST R1,6*4(,R7) Store uint-32 result + STFPC 6*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(6*4)+3(,R8) Save condition code as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLFDBR R1,5,FPR0,B'0000' RZ, toward zero + ST R1,7*4(,R7) Store uint-32 result + STFPC 7*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(7*4)+3(,R8) Save condition code as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLFDBR R1,6,FPR0,B'0000' RP, to +inf + ST R1,8*4(,R7) Store uint-32 result + STFPC 8*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(8*4)+3(,R8) Save condition code as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLFDBR R1,7,FPR0,B'0000' RM, to -inf + ST R1,9*4(,R7) Store uint-32 result + STFPC 9*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(9*4)+3(,R8) Save condition code as low byte of FPCR +* + LA R3,8(,R3) Point to next input values + LA R7,12*4(,R7) Point to next long BFP converted values + LA R8,12*4(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert extended BFP to uint-32. A pair of results is generated +* for each input: one with all exceptions non-trappable, and the +* second with all exceptions trappable. The FPCR and condition code +* are stored for each result. +* +*********************************************************************** + SPACE 2 +CLFXBR LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LD FPR0,0(,R3) Get extended BFP test value part 1 + LD FPR2,8(,R3) Get extended BFP test value part 1 + LFPC FPCREGNT Set exceptions non-trappable + CLFXBR R1,0,FPR0,0 Cvt float in FPR0-FPR2 to uint-32 in GPR1 + ST R1,0(,R7) Store uint-32 result + STFPC 0(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,3(,R8) Save condition code as low byte of FPCR +* + LFPC FPCREGTR Set exceptions trappable + XR R1,R1 Clear any residual result in R1 + SPM R1 Clear out any residual nz condition code + CLFXBR R1,0,FPR0,0 Cvt float in FPR0-FPR2 to uint-32 in GPR1 + ST R1,4(,R7) Store uint-32 result + STFPC 4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,7(,R8) Save condition code as low byte of FPCR +* + LA R3,16(,R3) Point to next extended BFP input value + LA R7,8(,R7) Point to next uint-32 converted value pair + LA R8,8(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert extended BFP to integers using each possible rounding mode. +* Ten test results are generated for each input. A 48-byte test result +* section is used to keep results sets aligned on a quad-double word. +* +* The first four tests use rounding modes specified in the FPCR with +* the IEEE Inexact exception supressed. SRNM (2-bit) is used for the +* first two FPCR-controlled tests and SRNMB (3-bit) is used for the +* last two To get full coverage of that instruction pair. +* +* The next six results use instruction-specified rounding modes. +* +* The default rounding mode (0 for RNTE) is not tested in this section; +* prior tests used the default rounding mode. RNTE is tested +* explicitly as a rounding mode in this section. +* +*********************************************************************** + SPACE 2 +CLFXBRA LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LD FPR0,0(,R3) Get extended BFP test value part 1 + LD FPR2,8(,R3) Get extended BFP test value part 2 +* +* Test cases using rounding mode specified in the FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 1 Set FPCR to RZ, towards zero. + CLFXBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked + ST R1,0*4(,R7) Store uint-32 result + STFPC 0(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,3(,R8) Save condition code as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 2 SET FPCR to RP, to +infinity + CLFXBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked + ST R1,1*4(,R7) Store uint-32 result + STFPC 1*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(1*4)+3(,R8) Save condition code as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 3 SET FPCR to RM, to -infinity + CLFXBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked + ST R1,2*4(,R7) Store uint-32 result + STFPC 2*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(2*4)+3(,R8) Save condition code as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 7 RFS, Prepare for Shorter Precision + CLFXBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked + ST R1,3*4(,R7) Store uint-32 result + STFPC 3*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(3*4)+3(,R8) Save condition code as low byte of FPCR +* +* Test cases using rounding mode specified in the instruction M3 field +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLFXBR R1,1,FPR0,B'0000' RNTA, to nearest, ties away + ST R1,4*4(,R7) Store uint-32 result + STFPC 4*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(4*4)+3(,R8) Save condition code as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLFXBR R1,3,FPR0,B'0000' RFS, prepare for shorter precision + ST R1,5*4(,R7) Store uint-32 result + STFPC 5*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(5*4)+3(,R8) Save condition code as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLFXBR R1,4,FPR0,B'0000' RNTE, to nearest, ties to even + ST R1,6*4(,R7) Store uint-32 result + STFPC 6*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(6*4)+3(,R8) Save condition code as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLFXBR R1,5,FPR0,B'0000' RZ, toward zero + ST R1,7*4(,R7) Store uint-32 result + STFPC 7*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(7*4)+3(,R8) Save condition code as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLFXBR R1,6,FPR0,B'0000' RP, to +inf + ST R1,8*4(,R7) Store uint-32 result + STFPC 8*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(8*4)+3(,R8) Save condition code as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLFXBR R1,7,FPR0,B'0000' RM, to -inf + ST R1,9*4(,R7) Store uint-32 result + STFPC 9*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(9*4)+3(,R8) Save condition code as low byte of FPCR +* + LA R3,16(,R3) Point to next input value + LA R7,12*4(,R7) Point to next long BFP converted values + LA R8,12*4(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Floating point inputs for Convert From Fixed testing. The same test +* values in the appropriate input format are used for short, long, +* and extended format tests. The last four values should generate +* exceptions. +* +*********************************************************************** + SPACE 2 +* +* Inputs for short BFP testing of trap and non-trap results +* +SBFPIN DS 0F Inputs for short BFP testing + DC X'3F800000' +1.0 + DC X'40000000' +2.0 + DC X'40800000' +4.0 + DC X'7F810000' SNaN + DC X'7FC10000' QNaN + DC X'4F800000' Max uint-32 + 1 rounded to short BFP +* ...4 294 967 296 + DC X'4F7FFFFF' Max uint-32 value representable +* ...in short bfp (4 294 967 040) + DC X'3F400000' +0.75 + DC X'3E800000' +0.25 +SBFPCT EQU *-SBFPIN Count of short BFP in list * 4 +* +* Inputs for short BFP exhaustive rounding mode testing. +* +SBFPINRM DS 0F + DC X'BFC00000' -1.5 + DC X'BF000000' -0.5 + DC X'3F000000' +0.5 + DC X'3FC00000' +1.5 + DC X'40200000' +2.5 + DC X'40B00000' +5.5 + DC X'41180000' +9.5 + DC X'4F7FFFFF' largest uint-32 value representable +* ...in short bfp (4 294 967 040) + DC X'3F400000' +0.75 + DC X'3E800000' +0.25 +SBFPRMCT EQU *-SBFPINRM Count of short BFP for rounding tests * 4 +* +* Inputs for long BFP testing of trap and non-trap results +* +LBFPIN DS 0F Inputs for long BFP testing + DC X'3FF0000000000000' +1.0 + DC X'4000000000000000' +2.0 + DC X'4010000000000000' +4.0 + DC X'7FF0100000000000' SNaN + DC X'7FF8100000000000' QNaN + DC X'41EFFFFFFFF00000' max uint-32 + 0.5 +* ...4 294 967 295.5 +* Rounds up on RNTE, overflows + DC X'41EFFFFFFFECCCCD' max uint-32 + 0.4 +* ...4 294 967 295.4, exceeds +* uint-32, but rounds down to fit + DC X'3FE8000000000000' +0.75 + DC X'3FD0000000000000' +0.25 +LBFPCT EQU *-LBFPIN Count of long BFP in list * 8 +* +* Inputs for long BFP exhaustive rounding mode testing. +* +LBFPINRM DS 0F + DC X'BFF8000000000000' -1.5 + DC X'BFE0000000000000' -0.5 + DC X'3FE0000000000000' +0.5 + DC X'3FF8000000000000' +1.5 + DC X'4004000000000000' +2.5 + DC X'4016000000000000' +5.5 + DC X'4023000000000000' +9.5 + DC X'41EFFFFFFFF00000' max uint-32 + 0.5 +* ...4 294 967 295.5 + DC X'3FE8000000000000' +0.75 + DC X'3FD0000000000000' +0.25 +LBFPRMCT EQU *-LBFPINRM Count of long BFP for rounding tests * 8 +* +* Inputs for short BFP testing of trap and non-trap results +* +XBFPIN DS 0D Inputs for long BFP testing + DC X'3FFF0000000000000000000000000000' +1.0 + DC X'40000000000000000000000000000000' +2.0 + DC X'40010000000000000000000000000000' +4.0 + DC X'7FFF0100000000000000000000000000' SNaN + DC X'7FFF8100000000000000000000000000' QNaN + DC X'401EFFFFFFFF00000000000000000000' max uint-32+0.5 +* ...4 294 967 295.5 +* Rounds up on RNTE, overflows + DC X'401EFFFFFFFECCCCCCCCCCCCCCCCCCCD' max uint-32+0.4 +* ...4 294 967 295.4, exceeds +* uint-32, but rounds down to fit + DC X'3FFE8000000000000000000000000000' 0.75 + DC X'3FFD0000000000000000000000000000' 0.25 +XBFPCT EQU *-XBFPIN Count of extended BFP in list * 16 +* +* Inputs for extended BFP exhaustive rounding mode testing. +* +XBFPINRM DS 0D + DC X'BFFF8000000000000000000000000000' -1.5 + DC X'BFFE0000000000000000000000000000' -0.5 + DC X'3FFE0000000000000000000000000000' +0.5 + DC X'3FFF8000000000000000000000000000' +1.5 + DC X'40004000000000000000000000000000' +2.5 + DC X'40016000000000000000000000000000' +5.5 + DC X'40023000000000000000000000000000' +9.5 + DC X'401EFFFFFFFF00000000000000000000' max uint-32 + 0.5 +* (+4 294 967 295.5) +* Above is always inexact, and may overflow based on rounding mode + DC X'3FFE8000000000000000000000000000' 0.75 + DC X'3FFD0000000000000000000000000000' 0.25 +XBFPRMCT EQU *-XBFPINRM Count of extended BFP rounding tests * 16 +* +* Locations for results +* +SINTOUT EQU BFPCVTTL+X'1000' uint-32 values from short BFP +* ..9 pairs used, room for 16 +SINTFLGS EQU BFPCVTTL+X'1100' FPCR flags and DXC from short BFP +* ..9 pairs used, room for 16 +SINTRMO EQU BFPCVTTL+X'1200' Short rounding mode test results +* ..10 sets used, room for 20 +SINTRMOF EQU BFPCVTTL+X'1600' Short rounding mode FPCR contents +* ..10 sets used, room for 20 +* +LINTOUT EQU BFPCVTTL+X'2000' uint-32 values from long BFP +* ..9 pairs used, room for 16 +LINTFLGS EQU BFPCVTTL+X'2100' FPCR flags and DXC from long BFP +* ..9 pairs used, room for 16 +LINTRMO EQU BFPCVTTL+X'2200' Long rounding mode test results +* ..10 sets used, room for 20 +LINTRMOF EQU BFPCVTTL+X'2600' Long rounding mode FPCR contents +* ..10 sets used, room for 20 +* +XINTOUT EQU BFPCVTTL+X'3000' uint-32 values from extended BFP +* ..9 pairs used, room for 16 +XINTFLGS EQU BFPCVTTL+X'3100' FPCR flags and DXC from extended BFP +* ..9 pairs used, room for 16 +XINTRMO EQU BFPCVTTL+X'3200' Extended rounding mode test results +* ..10 sets used, room for 20 +XINTRMOF EQU BFPCVTTL+X'3600' Extended rounding mode FPCR contents +* ..10 sets used, room for 20 +* +ENDLABL EQU BFPCVTTL+X'3A00' end of test program + PADCSECT ENDLABL pad csect for non-asma assembly + END diff --git a/tests/bfp-004-cvttolog.core b/tests/bfp-004-cvttolog.core new file mode 100644 index 000000000..07d485ac2 Binary files /dev/null and b/tests/bfp-004-cvttolog.core differ diff --git a/tests/bfp-004-cvttolog.list b/tests/bfp-004-cvttolog.list new file mode 100644 index 000000000..a485f5aa9 --- /dev/null +++ b/tests/bfp-004-cvttolog.list @@ -0,0 +1,1090 @@ +ASMA Ver. 0.2.0 ieee-cvttolog.asm: Test IEEE Convert To Logical (uint-32) 01 Sep 2016 10:11:17 Page 1 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 2 *********************************************************************** + 3 * + 4 *Testcase IEEE CONVERT TO LOGICAL 32 + 5 * Test case capability includes ieee exceptions trappable and + 6 * otherwise. Test results, FPCR flags, DXC, and condition codes are + 7 * saved for all tests. + 8 * + 9 *********************************************************************** + + + 11 *********************************************************************** + 12 * + 13 * Tests the following three conversion instructions + 14 * CONVERT TO LOGICAL (short BFP to uint-32, RRF-e) + 15 * CONVERT TO LOGICAL (long BFP to uint-32, RRF-e) + 16 * CONVERT TO LOGICAL (extended BFP to uint-32, RRF-e) + 17 * + 18 * Test data is compiled into this program. The test script that runs + 19 * this program can provide alternative test data through Hercules R + 20 * commands. + 21 * + 22 * Test Case Order + 23 * 1) Short BFP to uint-32 + 24 * 2) Short BFP to uint-32 with all rounding modes + 25 * 3) Long BFP uint-32 + 26 * 3) Long BFP uint-32 with all rounding modes + 27 * 4) Extended BFP to uint-32 + 28 * 4) Extended BFP to uint-32 with all rounding modes + 29 * + 30 * Three input test data sets are provided, one each for short, long, + 31 * and extended precision BFP. All are converted to uint-32. + 32 * + 33 * Provided test data is 1, 2, 4, 9, QNaN, SNaN, 4294967295.5. + 34 * The last three values will trigger inexact exceptions when + 35 * converted to uint-32. The last value is present only in the long + 36 * and extended BFP test cases and should overflow a uint-32. + 37 * Provided test data for rounding tests is taken from Table 9-11 on + 38 * page 9-16 of SA22-7832-10. + 39 * -1.5, -0.5, +0.5, +1.5, +2.5, +5.5, +9.5. + 40 * While the table illustrates LOAD FP INTEGER, the same results + 41 * should be generated when creating a uint-32 or uint-64 from BFP. + 42 * For long BFP and extended BFP rounding mode tests, ond additional + 43 * test case is included: 4294967294.5. This case rounds down to a + 44 * maximum uint-32 and rounds up to overflow; it tests the case where + 45 * the input is greater than a maximum uint-32 but rounds to a maximum + 46 * uint-32. See Table 19-19 on page 19-26 of SA22-7832-10 for details + 47 * on this boundary condition test. + 48 * + 49 * Also tests the following floating point support instructions + 50 * LOAD (Short) + 51 * LOAD (Long) + 52 * LOAD FPC + ASMA Ver. 0.2.0 ieee-cvttolog.asm: Test IEEE Convert To Logical (uint-32) 01 Sep 2016 10:11:17 Page 2 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 53 * SRNMB (Set BFP Rounding Mode 2-bit) + 54 * SRNMB (Set BFP Rounding Mode 3-bit) + 55 * STORE (Short) + 56 * STORE (Long) + 57 * STORE FPC + 58 * + 59 * + 60 *********************************************************************** + + + 62 MACRO + 63 PADCSECT &ENDLABL + 64 .* + 65 .* Macro to pad the CSECT to include result data areas if this test + 66 .* program is not being assembled using asma. asma generates a core + 67 .* image that is loaded by the loadcore command, and because the + 68 .* core image is a binary stored in Github, it makes sense to make + 69 .* this small effort to keep the core image small. + 70 .* + 71 AIF (D'&ENDLABL).GOODPAD + 72 MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + 73 MNOTE *,'No CSECT padding performed' + 74 MEXIT + 75 .* + 76 .GOODPAD ANOP Label valid. See if we're on asma + 77 AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + 78 ORG &ENDLABL-1 Not ASMA. Pad CSECT + 79 MEXIT + 80 .* + 81 .NOPAD ANOP + 82 MNOTE *,'asma detected; no CSECT padding performed' + 83 MEND + 84 * + 85 * Note: for compatibility with the z/CMS test rig, do not change + 86 * or use R11, R14, or R15. Everything else is fair game. + 87 * + 0000000000000000 0000000000000A77 88 BFPCVTTL START 0 + 0000000000000000 0000000000000001 89 R0 EQU 0 + 0000000000000001 0000000000000001 90 R1 EQU 1 + 0000000000000002 0000000000000001 91 R2 EQU 2 + 0000000000000003 0000000000000001 92 R3 EQU 3 + 0000000000000004 0000000000000001 93 R4 EQU 4 + 0000000000000005 0000000000000001 94 R5 EQU 5 + 0000000000000006 0000000000000001 95 R6 EQU 6 + 0000000000000007 0000000000000001 96 R7 EQU 7 + 0000000000000008 0000000000000001 97 R8 EQU 8 + 0000000000000009 0000000000000001 98 R9 EQU 9 + 000000000000000A 0000000000000001 99 R10 EQU 10 + 000000000000000B 0000000000000001 100 R11 EQU 11 + 000000000000000C 0000000000000001 101 R12 EQU 12 + 000000000000000D 0000000000000001 102 R13 EQU 13 + 000000000000000E 0000000000000001 103 R14 EQU 14 + ASMA Ver. 0.2.0 ieee-cvttolog.asm: Test IEEE Convert To Logical (uint-32) 01 Sep 2016 10:11:17 Page 3 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 000000000000000F 0000000000000001 104 R15 EQU 15 + 105 * + 106 * Floating Point Register equates to keep the cross reference clean + 107 * + 0000000000000000 0000000000000001 108 FPR0 EQU 0 + 0000000000000001 0000000000000001 109 FPR1 EQU 1 + 0000000000000002 0000000000000001 110 FPR2 EQU 2 + 0000000000000003 0000000000000001 111 FPR3 EQU 3 + 0000000000000004 0000000000000001 112 FPR4 EQU 4 + 0000000000000005 0000000000000001 113 FPR5 EQU 5 + 0000000000000006 0000000000000001 114 FPR6 EQU 6 + 0000000000000007 0000000000000001 115 FPR7 EQU 7 + 0000000000000008 0000000000000001 116 FPR8 EQU 8 + 0000000000000009 0000000000000001 117 FPR9 EQU 9 + 000000000000000A 0000000000000001 118 FPR10 EQU 10 + 000000000000000B 0000000000000001 119 FPR11 EQU 11 + 000000000000000C 0000000000000001 120 FPR12 EQU 12 + 000000000000000D 0000000000000001 121 FPR13 EQU 13 + 000000000000000E 0000000000000001 122 FPR14 EQU 14 + 000000000000000F 0000000000000001 123 FPR15 EQU 15 + 124 * +0000000000000000 0000000000000000 125 USING *,R15 + 126 * + 127 * Above works on real iron (R15=0 after sysclear) + 128 * and in z/CMS (R15 points to start of load module) + 129 * +0000000000000000 0000000000000000 000000000000008E 130 ORG BFPCVTTL+X'8E' Program check interrution code +000000000000008E 0000 131 PCINTCD DS H + 132 * + 0000000000000150 0000000000000000 133 PCOLDPSW EQU BFPCVTTL+X'150' z/Arch Program check old PSW + 134 * +0000000000000090 0000000000000090 00000000000001A0 135 ORG BFPCVTTL+X'1A0' z/Arch Restart PSW +00000000000001A0 00000001 80000000 136 DC X'0000000180000000',AD(START) + 137 * +00000000000001B0 00000000000001B0 00000000000001D0 138 ORG BFPCVTTL+X'1D0' z/Arch Program check old PSW +00000000000001D0 00000000 00000000 139 DC X'0000000000000000',AD(PROGCHK) + 140 * + 141 * Program check routine. If Data Exception, continue execution at + 142 * the instruction following the program check. Otherwise, hard wait. + 143 * No need to collect data. All interesting DXC stuff is captured + 144 * in the FPCR. + 145 * +00000000000001E0 00000000000001E0 0000000000000200 146 ORG BFPCVTTL+X'200' +0000000000000200 147 PROGCHK DS 0H Program check occured... +0000000000000200 9507 F08F 000000000000008F 148 CLI PCINTCD+1,X'07' Data Exception? +0000000000000204 A774 0004 000000000000020C 149 JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) +0000000000000208 B2B2 F150 0000000000000150 150 LPSWE PCOLDPSW ..yes, resume program execution +000000000000020C 151 PCNOTDTA DS 0H +000000000000020C 12EE 152 LTR R14,R14 Return address provided? +000000000000020E 077E 153 BNZR R14 Yes, return to z/CMS test rig. +0000000000000210 B2B2 F268 0000000000000268 154 LPSWE HARDWAIT Not data exception, enter disabled wait + ASMA Ver. 0.2.0 ieee-cvttolog.asm: Test IEEE Convert To Logical (uint-32) 01 Sep 2016 10:11:17 Page 4 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 156 *********************************************************************** + 157 * + 158 * Main program. Enable Advanced Floating Point, process test cases. + 159 * + 160 *********************************************************************** + + +0000000000000214 B600 F278 0000000000000278 162 START STCTL R0,R0,CTLR0 Store CR0 to enable AFP +0000000000000218 9604 F279 0000000000000279 163 OI CTLR0+1,X'04' Turn on AFP bit +000000000000021C B700 F278 0000000000000278 164 LCTL R0,R0,CTLR0 Reload updated CR0 + 165 * + 166 * Short BFP Input testing + 167 * +0000000000000220 41A0 F300 0000000000000300 168 LA R10,SHORTS Point to short BFP test inputs +0000000000000224 4DD0 F360 0000000000000360 169 BAS R13,CLFEBR Convert values to uint-32 from short BFP +0000000000000228 41A0 F330 0000000000000330 170 LA R10,RMSHORTS Point to inputs for rounding mode tests +000000000000022C 4DD0 F3BE 00000000000003BE 171 BAS R13,CLFEBRA Convert using all rounding mode options + 172 * + 173 * Short BFP Input testing + 174 * +0000000000000230 41A0 F310 0000000000000310 175 LA R10,LONGS Point to long BFP test inputs +0000000000000234 4DD0 F508 0000000000000508 176 BAS R13,CLFDBR Convert values to uint-32 from long BFP +0000000000000238 41A0 F340 0000000000000340 177 LA R10,RMLONGS Point to inputs for rounding mode tests +000000000000023C 4DD0 F566 0000000000000566 178 BAS R13,CLFDBRA Convert using all rounding mode options + 179 * + 180 * Short BFP Input testing + 181 * +0000000000000240 41A0 F320 0000000000000320 182 LA R10,EXTDS Point to extended BFP test inputs +0000000000000244 4DD0 F6B0 00000000000006B0 183 BAS R13,CLFXBR Convert values to uint-32 from extended +0000000000000248 41A0 F350 0000000000000350 184 LA R10,RMEXTDS Point to inputs for rounding mode tests +000000000000024C 4DD0 F712 0000000000000712 185 BAS R13,CLFXBRA Convert using all rounding mode options + 186 * +0000000000000250 12EE 187 LTR R14,R14 Return address provided? +0000000000000252 077E 188 BNZR R14 ..Yes, return to z/CMS test rig. +0000000000000254 B2B2 F258 0000000000000258 189 LPSWE WAITPSW All done + 190 * +0000000000000258 191 DS 0D Ensure correct alignment for psw +0000000000000258 00020000 00000000 192 WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +0000000000000268 00020000 00000000 193 HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end + 194 * +0000000000000278 00000000 195 CTLR0 DS F +000000000000027C 00000000 196 FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +0000000000000280 F8000000 197 FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags + 198 * + 199 * Input values parameter list, four fullwords: + 200 * 1) Count, + 201 * 2) Address of inputs, + 202 * 3) Address to place results, and + 203 * 4) Address to place DXC/Flags/cc values. + 204 * +0000000000000284 0000000000000284 0000000000000300 205 ORG BFPCVTTL+X'300' +0000000000000300 206 SHORTS DS 0F Inputs for short BFP testing + ASMA Ver. 0.2.0 ieee-cvttolog.asm: Test IEEE Convert To Logical (uint-32) 01 Sep 2016 10:11:17 Page 5 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000300 00000009 207 DC A(SBFPCT/4) +0000000000000304 00000860 208 DC A(SBFPIN) +0000000000000308 00001000 209 DC A(SINTOUT) +000000000000030C 00001100 210 DC A(SINTFLGS) + 211 * +0000000000000310 212 LONGS DS 0F Inputs for long BFP testing +0000000000000310 00000009 213 DC A(LBFPCT/8) +0000000000000314 000008AC 214 DC A(LBFPIN) +0000000000000318 00002000 215 DC A(LINTOUT) +000000000000031C 00002100 216 DC A(LINTFLGS) + 217 * +0000000000000320 218 EXTDS DS 0F Inputs for Extended BFP testing +0000000000000320 00000009 219 DC A(XBFPCT/16) +0000000000000324 00000948 220 DC A(XBFPIN) +0000000000000328 00003000 221 DC A(XINTOUT) +000000000000032C 00003100 222 DC A(XINTFLGS) + 223 * +0000000000000330 0000000A 224 RMSHORTS DC A(SBFPRMCT/4) +0000000000000334 00000884 225 DC A(SBFPINRM) Short BFP rounding mode test inputs +0000000000000338 00001200 226 DC A(SINTRMO) Short BFP rounding mode test results +000000000000033C 00001600 227 DC A(SINTRMOF) Short BFP rounding mode test flags + 228 * +0000000000000340 0000000A 229 RMLONGS DC A(LBFPRMCT/8) +0000000000000344 000008F4 230 DC A(LBFPINRM) Long BFP rounding mode test inputs +0000000000000348 00002200 231 DC A(LINTRMO) Long BFP rounding mode test results +000000000000034C 00002600 232 DC A(LINTRMOF) Long BFP rounding mode test flags + 233 * +0000000000000350 0000000A 234 RMEXTDS DC A(XBFPRMCT/16) +0000000000000354 000009D8 235 DC A(XBFPINRM) Extended BFP rounding mode test inputs +0000000000000358 00003200 236 DC A(XINTRMO) Extended BFP rounding mode test results +000000000000035C 00003600 237 DC A(XINTRMOF) Extended BFP rounding mode test flags + ASMA Ver. 0.2.0 ieee-cvttolog.asm: Test IEEE Convert To Logical (uint-32) 01 Sep 2016 10:11:17 Page 6 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 239 *********************************************************************** + 240 * + 241 * Convert short BFP to uint-32 format. A pair of results is generated + 242 * for each input: one with all exceptions non-trappable, and the second + 243 * with all exceptions trappable. The FPCR and condition code is + 244 * stored for each result. + 245 * + 246 *********************************************************************** + + +0000000000000360 9823 A000 0000000000000000 248 CLFEBR LM R2,R3,0(R10) Get count and address of test input values +0000000000000364 9878 A008 0000000000000008 249 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000368 1222 250 LTR R2,R2 Any test cases? +000000000000036A 078D 251 BZR R13 ..No, return to caller +000000000000036C 0DC0 252 BASR R12,0 Set top of loop + 253 * +000000000000036E 7800 3000 0000000000000000 254 LE FPR0,0(,R3) Get short BFP test value +0000000000000372 B29D F27C 000000000000027C 255 LFPC FPCREGNT Set exceptions non-trappable +0000000000000376 B39C 0010 256 CLFEBR R1,0,FPR0,0 Cvt float in FPR0 to uint-32 in GPR1 +000000000000037A 5010 7000 0000000000000000 257 ST R1,0(,R7) Store int-32 result +000000000000037E B29C 8000 0000000000000000 258 STFPC 0(R8) Store resulting FPCR flags and DXC +0000000000000382 B222 0010 259 IPM R1 Get condition code and program mask +0000000000000386 8810 001C 000000000000001C 260 SRL R1,28 Isolate CC in low order byte +000000000000038A 4210 8003 0000000000000003 261 STC R1,3(,R8) Save condition code as low byte of FPCR + 262 * +000000000000038E B29D F280 0000000000000280 263 LFPC FPCREGTR Set exceptions trappable +0000000000000392 1711 264 XR R1,R1 Clear any residual result in R1 +0000000000000394 0410 265 SPM R1 Clear out any residual nz condition code +0000000000000396 B39C 0010 266 CLFEBR R1,0,FPR0,0 Cvt float in FPR0 to uint-32 in GPR1 +000000000000039A 5010 7004 0000000000000004 267 ST R1,4(,R7) Store short BFP result +000000000000039E B29C 8004 0000000000000004 268 STFPC 4(R8) Store resulting FPCR flags and DXC +00000000000003A2 B222 0010 269 IPM R1 Get condition code and program mask +00000000000003A6 8810 001C 000000000000001C 270 SRL R1,28 Isolate CC in low order byte +00000000000003AA 4210 8007 0000000000000007 271 STC R1,7(,R8) Save condition code as low byte of FPCR + 272 * +00000000000003AE 4130 3004 0000000000000004 273 LA R3,4(,R3) Point to next input values +00000000000003B2 4170 7008 0000000000000008 274 LA R7,8(,R7) Point to next int-32 converted value pair +00000000000003B6 4180 8008 0000000000000008 275 LA R8,8(,R8) Point to next FPCR/CC result area +00000000000003BA 062C 276 BCTR R2,R12 Convert next input value. +00000000000003BC 07FD 277 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvttolog.asm: Test IEEE Convert To Logical (uint-32) 01 Sep 2016 10:11:17 Page 7 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 279 *********************************************************************** + 280 * + 281 * Convert short BFP to integers using each possible rounding mode. + 282 * Ten test results are generated for each input. A 48-byte test result + 283 * section is used to keep results sets aligned on a quad-double word. + 284 * + 285 * The first four tests use rounding modes specified in the FPCR with + 286 * the IEEE Inexact exception supressed. SRNM (2-bit) is used for + 287 * the first two FPCR-controlled tests and SRNMB (3-bit) is used for + 288 * the last two To get full coverage of that instruction pair. + 289 * + 290 * The next six results use instruction-specified rounding modes. + 291 * + 292 * The default rounding mode (0 for RNTE) is not tested in this section; + 293 * prior tests used the default rounding mode. RNTE is tested + 294 * explicitly as a rounding mode in this section. + 295 * + 296 *********************************************************************** + + +00000000000003BE 9823 A000 0000000000000000 298 CLFEBRA LM R2,R3,0(R10) Get count and address of test input values +00000000000003C2 9878 A008 0000000000000008 299 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000003C6 1222 300 LTR R2,R2 Any test cases? +00000000000003C8 078D 301 BZR R13 ..No, return to caller +00000000000003CA 0DC0 302 BASR R12,0 Set top of loop + 303 * +00000000000003CC 7800 3000 0000000000000000 304 LE FPR0,0(,R3) Get short BFP test value + 305 * + 306 * Test cases using rounding mode specified in the FPCR + 307 * +00000000000003D0 B29D F27C 000000000000027C 308 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000003D4 B299 0001 0000000000000001 309 SRNM 1 SET FPCR to RZ, towards zero. +00000000000003D8 B39C 0410 310 CLFEBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked +00000000000003DC 5010 7000 0000000000000000 311 ST R1,0*4(,R7) Store uint-32 result +00000000000003E0 B29C 8000 0000000000000000 312 STFPC 0(R8) Store resulting FPCR flags and DXC +00000000000003E4 B222 0010 313 IPM R1 Get condition code and program mask +00000000000003E8 8810 001C 000000000000001C 314 SRL R1,28 Isolate CC in low order byte +00000000000003EC 4210 8003 0000000000000003 315 STC R1,3(,R8) Save condition code as low byte of FPCR + 316 * +00000000000003F0 B29D F27C 000000000000027C 317 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000003F4 B299 0002 0000000000000002 318 SRNM 2 SET FPCR to RP, to +infinity +00000000000003F8 B39C 0410 319 CLFEBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked +00000000000003FC 5010 7004 0000000000000004 320 ST R1,1*4(,R7) Store uint-32 result +0000000000000400 B29C 8004 0000000000000004 321 STFPC 1*4(R8) Store resulting FPCR flags and DXC +0000000000000404 B222 0010 322 IPM R1 Get condition code and program mask +0000000000000408 8810 001C 000000000000001C 323 SRL R1,28 Isolate CC in low order byte +000000000000040C 4210 8007 0000000000000007 324 STC R1,(1*4)+3(,R8) Save condition code as low byte of FPCR + 325 * +0000000000000410 B29D F27C 000000000000027C 326 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000414 B2B8 0003 0000000000000003 327 SRNMB 3 SET FPCR to RM, to -infinity +0000000000000418 B39C 0410 328 CLFEBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked +000000000000041C 5010 7008 0000000000000008 329 ST R1,2*4(,R7) Store uint-32 result + ASMA Ver. 0.2.0 ieee-cvttolog.asm: Test IEEE Convert To Logical (uint-32) 01 Sep 2016 10:11:17 Page 8 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000420 B29C 8008 0000000000000008 330 STFPC 2*4(R8) Store resulting FPCR flags and DXC +0000000000000424 B222 0010 331 IPM R1 Get condition code and program mask +0000000000000428 8810 001C 000000000000001C 332 SRL R1,28 Isolate CC in low order byte +000000000000042C 4210 800B 000000000000000B 333 STC R1,(2*4)+3(,R8) Save condition code as low byte of FPCR + 334 * +0000000000000430 B29D F27C 000000000000027C 335 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000434 B2B8 0007 0000000000000007 336 SRNMB 7 RFS, Prepare for Shorter Precision +0000000000000438 B39C 0410 337 CLFEBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked +000000000000043C 5010 700C 000000000000000C 338 ST R1,3*4(,R7) Store uint-32 result +0000000000000440 B29C 800C 000000000000000C 339 STFPC 3*4(R8) Store resulting FPCR flags and DXC +0000000000000444 B222 0010 340 IPM R1 Get condition code and program mask +0000000000000448 8810 001C 000000000000001C 341 SRL R1,28 Isolate CC in low order byte +000000000000044C 4210 800F 000000000000000F 342 STC R1,(3*4)+3(,R8) Save condition code as low byte of FPCR + 343 * + 344 * Test cases using rounding mode specified in the instruction M3 field + 345 * +0000000000000450 B29D F27C 000000000000027C 346 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000454 B39C 1010 347 CLFEBR R1,1,FPR0,B'0000' RNTA, to nearest, ties away +0000000000000458 5010 7010 0000000000000010 348 ST R1,4*4(,R7) Store uint-32 result +000000000000045C B29C 8010 0000000000000010 349 STFPC 4*4(R8) Store resulting FPCR flags and DXC +0000000000000460 B222 0010 350 IPM R1 Get condition code and program mask +0000000000000464 8810 001C 000000000000001C 351 SRL R1,28 Isolate CC in low order byte +0000000000000468 4210 8013 0000000000000013 352 STC R1,(4*4)+3(,R8) Save condition code as low byte of FPCR + 353 * +000000000000046C B29D F27C 000000000000027C 354 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000470 B39C 3010 355 CLFEBR R1,3,FPR0,B'0000' RFS, prepare for shorter precision +0000000000000474 5010 7014 0000000000000014 356 ST R1,5*4(,R7) Store uint-32 result +0000000000000478 B29C 8014 0000000000000014 357 STFPC 5*4(R8) Store resulting FPCR flags and DXC +000000000000047C B222 0010 358 IPM R1 Get condition code and program mask +0000000000000480 8810 001C 000000000000001C 359 SRL R1,28 Isolate CC in low order byte +0000000000000484 4210 8017 0000000000000017 360 STC R1,(5*4)+3(,R8) Save condition code as low byte of FPCR + 361 * +0000000000000488 B29D F27C 000000000000027C 362 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000048C B39C 4010 363 CLFEBR R1,4,FPR0,B'0000' RNTE, to nearest, ties to even +0000000000000490 5010 7018 0000000000000018 364 ST R1,6*4(,R7) Store uint-32 result +0000000000000494 B29C 8018 0000000000000018 365 STFPC 6*4(R8) Store resulting FPCR flags and DXC +0000000000000498 B222 0010 366 IPM R1 Get condition code and program mask +000000000000049C 8810 001C 000000000000001C 367 SRL R1,28 Isolate CC in low order byte +00000000000004A0 4210 801B 000000000000001B 368 STC R1,(6*4)+3(,R8) Save condition code as low byte of FPCR + 369 * +00000000000004A4 B29D F27C 000000000000027C 370 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000004A8 B39C 5010 371 CLFEBR R1,5,FPR0,B'0000' RZ, toward zero +00000000000004AC 5010 701C 000000000000001C 372 ST R1,7*4(,R7) Store uint-32 result +00000000000004B0 B29C 801C 000000000000001C 373 STFPC 7*4(R8) Store resulting FPCR flags and DXC +00000000000004B4 B222 0010 374 IPM R1 Get condition code and program mask +00000000000004B8 8810 001C 000000000000001C 375 SRL R1,28 Isolate CC in low order byte +00000000000004BC 4210 801F 000000000000001F 376 STC R1,(7*4)+3(,R8) Save condition code as low byte of FPCR + 377 * +00000000000004C0 B29D F27C 000000000000027C 378 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000004C4 B39C 6010 379 CLFEBR R1,6,FPR0,B'0000' RP, to +inf +00000000000004C8 5010 7020 0000000000000020 380 ST R1,8*4(,R7) Store uint-32 result +00000000000004CC B29C 8020 0000000000000020 381 STFPC 8*4(R8) Store resulting FPCR flags and DXC + ASMA Ver. 0.2.0 ieee-cvttolog.asm: Test IEEE Convert To Logical (uint-32) 01 Sep 2016 10:11:17 Page 9 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000004D0 B222 0010 382 IPM R1 Get condition code and program mask +00000000000004D4 8810 001C 000000000000001C 383 SRL R1,28 Isolate CC in low order byte +00000000000004D8 4210 8023 0000000000000023 384 STC R1,(8*4)+3(,R8) Save condition code as low byte of FPCR + 385 * +00000000000004DC B29D F27C 000000000000027C 386 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000004E0 B39C 7010 387 CLFEBR R1,7,FPR0,B'0000' RM, to -inf +00000000000004E4 5010 7024 0000000000000024 388 ST R1,9*4(,R7) Store uint-32 result +00000000000004E8 B29C 8024 0000000000000024 389 STFPC 9*4(R8) Store resulting FPCR flags and DXC +00000000000004EC B222 0010 390 IPM R1 Get condition code and program mask +00000000000004F0 8810 001C 000000000000001C 391 SRL R1,28 Isolate CC in low order byte +00000000000004F4 4210 8027 0000000000000027 392 STC R1,(9*4)+3(,R8) Save condition code as low byte of FPCR + 393 * +00000000000004F8 4130 3004 0000000000000004 394 LA R3,4(,R3) Point to next input value +00000000000004FC 4170 7030 0000000000000030 395 LA R7,12*4(,R7) Point to next uint-32 result set +0000000000000500 4180 8030 0000000000000030 396 LA R8,12*4(,R8) Point to next FPCR/CC result area +0000000000000504 062C 397 BCTR R2,R12 Convert next input value. +0000000000000506 07FD 398 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvttolog.asm: Test IEEE Convert To Logical (uint-32) 01 Sep 2016 10:11:17 Page 10 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 400 *********************************************************************** + 401 * + 402 * Convert long BFP inputs to uint-32. A pair of results is generated + 403 * for each input: one with all exceptions non-trappable, and the second + 404 * with all exceptions trappable. The FPCR and condition code is + 405 * stored for each result. + 406 * + 407 *********************************************************************** + + +0000000000000508 9823 A000 0000000000000000 409 CLFDBR LM R2,R3,0(R10) Get count and address of test input values +000000000000050C 9878 A008 0000000000000008 410 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000510 1222 411 LTR R2,R2 Any test cases? +0000000000000512 078D 412 BZR R13 ..No, return to caller +0000000000000514 0DC0 413 BASR R12,0 Set top of loop + 414 * +0000000000000516 6800 3000 0000000000000000 415 LD FPR0,0(,R3) Get long BFP test value +000000000000051A B29D F27C 000000000000027C 416 LFPC FPCREGNT Set exceptions non-trappable +000000000000051E B39D 0010 417 CLFDBR R1,0,FPR0,0 Cvt float in FPR0 to uint-32 in GPR1 +0000000000000522 5010 7000 0000000000000000 418 ST R1,0(,R7) Store long BFP result +0000000000000526 B29C 8000 0000000000000000 419 STFPC 0(R8) Store resulting FPCR flags and DXC +000000000000052A B222 0010 420 IPM R1 Get condition code and program mask +000000000000052E 8810 001C 000000000000001C 421 SRL R1,28 Isolate CC in low order byte +0000000000000532 4210 8003 0000000000000003 422 STC R1,3(,R8) Save condition code as low byte of FPCR + 423 * +0000000000000536 B29D F280 0000000000000280 424 LFPC FPCREGTR Set exceptions trappable +000000000000053A 1711 425 XR R1,R1 Clear any residual result in R1 +000000000000053C 0410 426 SPM R1 Clear out any residual nz condition code +000000000000053E B39D 0010 427 CLFDBR R1,0,FPR0,0 Cvt float in FPR0 to uint-32 in GPR1 +0000000000000542 5010 7004 0000000000000004 428 ST R1,4(,R7) Store int-32 result +0000000000000546 B29C 8004 0000000000000004 429 STFPC 4(R8) Store resulting FPCR flags and DXC +000000000000054A B222 0010 430 IPM R1 Get condition code and program mask +000000000000054E 8810 001C 000000000000001C 431 SRL R1,28 Isolate CC in low order byte +0000000000000552 4210 8007 0000000000000007 432 STC R1,7(,R8) Save condition code as low byte of FPCR + 433 * +0000000000000556 4130 3008 0000000000000008 434 LA R3,8(,R3) Point to next input values +000000000000055A 4170 7008 0000000000000008 435 LA R7,8(,R7) Point to next uint-32 converted value pair +000000000000055E 4180 8008 0000000000000008 436 LA R8,8(,R8) Point to next FPCR/CC result area +0000000000000562 062C 437 BCTR R2,R12 Convert next input value. +0000000000000564 07FD 438 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvttolog.asm: Test IEEE Convert To Logical (uint-32) 01 Sep 2016 10:11:17 Page 11 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 440 *********************************************************************** + 441 * + 442 * Convert long BFP to integers using each possible rounding mode. + 443 * Ten test results are generated for each input. A 48-byte test result + 444 * section is used to keep results sets aligned on a quad-double word. + 445 * + 446 * The first four tests use rounding modes specified in the FPCR with + 447 * the IEEE Inexact exception supressed. SRNM (2-bit) is used for + 448 * thefirst two FPCR-controlled tests and SRNMB (3-bit) is used for + 449 * the last two To get full coverage of that instruction pair. + 450 * + 451 * The next six results use instruction-specified rounding modes. + 452 * + 453 * The default rounding mode (0 for RNTE) is not tested in this section; + 454 * prior tests used the default rounding mode. RNTE is tested + 455 * explicitly as a rounding mode in this section. + 456 * + 457 *********************************************************************** + + +0000000000000566 9823 A000 0000000000000000 459 CLFDBRA LM R2,R3,0(R10) Get count and address of test input values +000000000000056A 9878 A008 0000000000000008 460 LM R7,R8,8(R10) Get address of result area and flag area. +000000000000056E 1222 461 LTR R2,R2 Any test cases? +0000000000000570 078D 462 BZR R13 ..No, return to caller +0000000000000572 0DC0 463 BASR R12,0 Set top of loop + 464 * +0000000000000574 6800 3000 0000000000000000 465 LD FPR0,0(,R3) Get long BFP test value + 466 * + 467 * Test cases using rounding mode specified in the FPCR + 468 * +0000000000000578 B29D F27C 000000000000027C 469 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000057C B299 0001 0000000000000001 470 SRNM 1 SET FPCR to RZ, towards zero. +0000000000000580 B39D 0410 471 CLFDBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked +0000000000000584 5010 7000 0000000000000000 472 ST R1,0*4(,R7) Store uint-32 result +0000000000000588 B29C 8000 0000000000000000 473 STFPC 0(R8) Store resulting FPCR flags and DXC +000000000000058C B222 0010 474 IPM R1 Get condition code and program mask +0000000000000590 8810 001C 000000000000001C 475 SRL R1,28 Isolate CC in low order byte +0000000000000594 4210 8003 0000000000000003 476 STC R1,3(,R8) Save condition code as low byte of FPCR + 477 * +0000000000000598 B29D F27C 000000000000027C 478 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000059C B299 0002 0000000000000002 479 SRNM 2 SET FPCR to RP, to +infinity +00000000000005A0 B39D 0410 480 CLFDBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked +00000000000005A4 5010 7004 0000000000000004 481 ST R1,1*4(,R7) Store uint-32 result +00000000000005A8 B29C 8004 0000000000000004 482 STFPC 1*4(R8) Store resulting FPCR flags and DXC +00000000000005AC B222 0010 483 IPM R1 Get condition code and program mask +00000000000005B0 8810 001C 000000000000001C 484 SRL R1,28 Isolate CC in low order byte +00000000000005B4 4210 8007 0000000000000007 485 STC R1,(1*4)+3(,R8) Save condition code as low byte of FPCR + 486 * +00000000000005B8 B29D F27C 000000000000027C 487 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000005BC B2B8 0003 0000000000000003 488 SRNMB 3 SET FPCR to RM, to -infinity +00000000000005C0 B39D 0410 489 CLFDBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked +00000000000005C4 5010 7008 0000000000000008 490 ST R1,2*4(,R7) Store uint-32 result + ASMA Ver. 0.2.0 ieee-cvttolog.asm: Test IEEE Convert To Logical (uint-32) 01 Sep 2016 10:11:17 Page 12 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000005C8 B29C 8008 0000000000000008 491 STFPC 2*4(R8) Store resulting FPCR flags and DXC +00000000000005CC B222 0010 492 IPM R1 Get condition code and program mask +00000000000005D0 8810 001C 000000000000001C 493 SRL R1,28 Isolate CC in low order byte +00000000000005D4 4210 800B 000000000000000B 494 STC R1,(2*4)+3(,R8) Save condition code as low byte of FPCR + 495 * +00000000000005D8 B29D F27C 000000000000027C 496 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000005DC B2B8 0007 0000000000000007 497 SRNMB 7 RFS, Prepare for Shorter Precision +00000000000005E0 B39D 0410 498 CLFDBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked +00000000000005E4 5010 700C 000000000000000C 499 ST R1,3*4(,R7) Store uint-32 result +00000000000005E8 B29C 800C 000000000000000C 500 STFPC 3*4(R8) Store resulting FPCR flags and DXC +00000000000005EC B222 0010 501 IPM R1 Get condition code and program mask +00000000000005F0 8810 001C 000000000000001C 502 SRL R1,28 Isolate CC in low order byte +00000000000005F4 4210 800F 000000000000000F 503 STC R1,(3*4)+3(,R8) Save condition code as low byte of FPCR + 504 * + 505 * Test cases using rounding mode specified in the instruction M3 field + 506 * +00000000000005F8 B29D F27C 000000000000027C 507 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000005FC B39D 1010 508 CLFDBR R1,1,FPR0,B'0000' RNTA, to nearest, ties away +0000000000000600 5010 7010 0000000000000010 509 ST R1,4*4(,R7) Store uint-32 result +0000000000000604 B29C 8010 0000000000000010 510 STFPC 4*4(R8) Store resulting FPCR flags and DXC +0000000000000608 B222 0010 511 IPM R1 Get condition code and program mask +000000000000060C 8810 001C 000000000000001C 512 SRL R1,28 Isolate CC in low order byte +0000000000000610 4210 8013 0000000000000013 513 STC R1,(4*4)+3(,R8) Save condition code as low byte of FPCR + 514 * +0000000000000614 B29D F27C 000000000000027C 515 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000618 B39D 3010 516 CLFDBR R1,3,FPR0,B'0000' RFS, prepare for shorter precision +000000000000061C 5010 7014 0000000000000014 517 ST R1,5*4(,R7) Store uint-32 result +0000000000000620 B29C 8014 0000000000000014 518 STFPC 5*4(R8) Store resulting FPCR flags and DXC +0000000000000624 B222 0010 519 IPM R1 Get condition code and program mask +0000000000000628 8810 001C 000000000000001C 520 SRL R1,28 Isolate CC in low order byte +000000000000062C 4210 8017 0000000000000017 521 STC R1,(5*4)+3(,R8) Save condition code as low byte of FPCR + 522 * +0000000000000630 B29D F27C 000000000000027C 523 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000634 B39D 4010 524 CLFDBR R1,4,FPR0,B'0000' RNTE, to nearest, ties to even +0000000000000638 5010 7018 0000000000000018 525 ST R1,6*4(,R7) Store uint-32 result +000000000000063C B29C 8018 0000000000000018 526 STFPC 6*4(R8) Store resulting FPCR flags and DXC +0000000000000640 B222 0010 527 IPM R1 Get condition code and program mask +0000000000000644 8810 001C 000000000000001C 528 SRL R1,28 Isolate CC in low order byte +0000000000000648 4210 801B 000000000000001B 529 STC R1,(6*4)+3(,R8) Save condition code as low byte of FPCR + 530 * +000000000000064C B29D F27C 000000000000027C 531 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000650 B39D 5010 532 CLFDBR R1,5,FPR0,B'0000' RZ, toward zero +0000000000000654 5010 701C 000000000000001C 533 ST R1,7*4(,R7) Store uint-32 result +0000000000000658 B29C 801C 000000000000001C 534 STFPC 7*4(R8) Store resulting FPCR flags and DXC +000000000000065C B222 0010 535 IPM R1 Get condition code and program mask +0000000000000660 8810 001C 000000000000001C 536 SRL R1,28 Isolate CC in low order byte +0000000000000664 4210 801F 000000000000001F 537 STC R1,(7*4)+3(,R8) Save condition code as low byte of FPCR + 538 * +0000000000000668 B29D F27C 000000000000027C 539 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000066C B39D 6010 540 CLFDBR R1,6,FPR0,B'0000' RP, to +inf +0000000000000670 5010 7020 0000000000000020 541 ST R1,8*4(,R7) Store uint-32 result +0000000000000674 B29C 8020 0000000000000020 542 STFPC 8*4(R8) Store resulting FPCR flags and DXC + ASMA Ver. 0.2.0 ieee-cvttolog.asm: Test IEEE Convert To Logical (uint-32) 01 Sep 2016 10:11:17 Page 13 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000678 B222 0010 543 IPM R1 Get condition code and program mask +000000000000067C 8810 001C 000000000000001C 544 SRL R1,28 Isolate CC in low order byte +0000000000000680 4210 8023 0000000000000023 545 STC R1,(8*4)+3(,R8) Save condition code as low byte of FPCR + 546 * +0000000000000684 B29D F27C 000000000000027C 547 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000688 B39D 7010 548 CLFDBR R1,7,FPR0,B'0000' RM, to -inf +000000000000068C 5010 7024 0000000000000024 549 ST R1,9*4(,R7) Store uint-32 result +0000000000000690 B29C 8024 0000000000000024 550 STFPC 9*4(R8) Store resulting FPCR flags and DXC +0000000000000694 B222 0010 551 IPM R1 Get condition code and program mask +0000000000000698 8810 001C 000000000000001C 552 SRL R1,28 Isolate CC in low order byte +000000000000069C 4210 8027 0000000000000027 553 STC R1,(9*4)+3(,R8) Save condition code as low byte of FPCR + 554 * +00000000000006A0 4130 3008 0000000000000008 555 LA R3,8(,R3) Point to next input values +00000000000006A4 4170 7030 0000000000000030 556 LA R7,12*4(,R7) Point to next long BFP converted values +00000000000006A8 4180 8030 0000000000000030 557 LA R8,12*4(,R8) Point to next FPCR/CC result area +00000000000006AC 062C 558 BCTR R2,R12 Convert next input value. +00000000000006AE 07FD 559 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvttolog.asm: Test IEEE Convert To Logical (uint-32) 01 Sep 2016 10:11:17 Page 14 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 561 *********************************************************************** + 562 * + 563 * Convert extended BFP to uint-32. A pair of results is generated + 564 * for each input: one with all exceptions non-trappable, and the + 565 * second with all exceptions trappable. The FPCR and condition code + 566 * are stored for each result. + 567 * + 568 *********************************************************************** + + +00000000000006B0 9823 A000 0000000000000000 570 CLFXBR LM R2,R3,0(R10) Get count and address of test input values +00000000000006B4 9878 A008 0000000000000008 571 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000006B8 1222 572 LTR R2,R2 Any test cases? +00000000000006BA 078D 573 BZR R13 ..No, return to caller +00000000000006BC 0DC0 574 BASR R12,0 Set top of loop + 575 * +00000000000006BE 6800 3000 0000000000000000 576 LD FPR0,0(,R3) Get extended BFP test value part 1 +00000000000006C2 6820 3008 0000000000000008 577 LD FPR2,8(,R3) Get extended BFP test value part 1 +00000000000006C6 B29D F27C 000000000000027C 578 LFPC FPCREGNT Set exceptions non-trappable +00000000000006CA B39E 0010 579 CLFXBR R1,0,FPR0,0 Cvt float in FPR0-FPR2 to uint-32 in GPR1 +00000000000006CE 5010 7000 0000000000000000 580 ST R1,0(,R7) Store uint-32 result +00000000000006D2 B29C 8000 0000000000000000 581 STFPC 0(R8) Store resulting FPCR flags and DXC +00000000000006D6 B222 0010 582 IPM R1 Get condition code and program mask +00000000000006DA 8810 001C 000000000000001C 583 SRL R1,28 Isolate CC in low order byte +00000000000006DE 4210 8003 0000000000000003 584 STC R1,3(,R8) Save condition code as low byte of FPCR + 585 * +00000000000006E2 B29D F280 0000000000000280 586 LFPC FPCREGTR Set exceptions trappable +00000000000006E6 1711 587 XR R1,R1 Clear any residual result in R1 +00000000000006E8 0410 588 SPM R1 Clear out any residual nz condition code +00000000000006EA B39E 0010 589 CLFXBR R1,0,FPR0,0 Cvt float in FPR0-FPR2 to uint-32 in GPR1 +00000000000006EE 5010 7004 0000000000000004 590 ST R1,4(,R7) Store uint-32 result +00000000000006F2 B29C 8004 0000000000000004 591 STFPC 4(R8) Store resulting FPCR flags and DXC +00000000000006F6 B222 0010 592 IPM R1 Get condition code and program mask +00000000000006FA 8810 001C 000000000000001C 593 SRL R1,28 Isolate CC in low order byte +00000000000006FE 4210 8007 0000000000000007 594 STC R1,7(,R8) Save condition code as low byte of FPCR + 595 * +0000000000000702 4130 3010 0000000000000010 596 LA R3,16(,R3) Point to next extended BFP input value +0000000000000706 4170 7008 0000000000000008 597 LA R7,8(,R7) Point to next uint-32 converted value pair +000000000000070A 4180 8008 0000000000000008 598 LA R8,8(,R8) Point to next FPCR/CC result area +000000000000070E 062C 599 BCTR R2,R12 Convert next input value. +0000000000000710 07FD 600 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvttolog.asm: Test IEEE Convert To Logical (uint-32) 01 Sep 2016 10:11:17 Page 15 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 602 *********************************************************************** + 603 * + 604 * Convert extended BFP to integers using each possible rounding mode. + 605 * Ten test results are generated for each input. A 48-byte test result + 606 * section is used to keep results sets aligned on a quad-double word. + 607 * + 608 * The first four tests use rounding modes specified in the FPCR with + 609 * the IEEE Inexact exception supressed. SRNM (2-bit) is used for the + 610 * first two FPCR-controlled tests and SRNMB (3-bit) is used for the + 611 * last two To get full coverage of that instruction pair. + 612 * + 613 * The next six results use instruction-specified rounding modes. + 614 * + 615 * The default rounding mode (0 for RNTE) is not tested in this section; + 616 * prior tests used the default rounding mode. RNTE is tested + 617 * explicitly as a rounding mode in this section. + 618 * + 619 *********************************************************************** + + +0000000000000712 9823 A000 0000000000000000 621 CLFXBRA LM R2,R3,0(R10) Get count and address of test input values +0000000000000716 9878 A008 0000000000000008 622 LM R7,R8,8(R10) Get address of result area and flag area. +000000000000071A 1222 623 LTR R2,R2 Any test cases? +000000000000071C 078D 624 BZR R13 ..No, return to caller +000000000000071E 0DC0 625 BASR R12,0 Set top of loop + 626 * +0000000000000720 6800 3000 0000000000000000 627 LD FPR0,0(,R3) Get extended BFP test value part 1 +0000000000000724 6820 3008 0000000000000008 628 LD FPR2,8(,R3) Get extended BFP test value part 2 + 629 * + 630 * Test cases using rounding mode specified in the FPCR + 631 * +0000000000000728 B29D F27C 000000000000027C 632 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000072C B299 0001 0000000000000001 633 SRNM 1 Set FPCR to RZ, towards zero. +0000000000000730 B39E 0410 634 CLFXBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked +0000000000000734 5010 7000 0000000000000000 635 ST R1,0*4(,R7) Store uint-32 result +0000000000000738 B29C 8000 0000000000000000 636 STFPC 0(R8) Store resulting FPCR flags and DXC +000000000000073C B222 0010 637 IPM R1 Get condition code and program mask +0000000000000740 8810 001C 000000000000001C 638 SRL R1,28 Isolate CC in low order byte +0000000000000744 4210 8003 0000000000000003 639 STC R1,3(,R8) Save condition code as low byte of FPCR + 640 * +0000000000000748 B29D F27C 000000000000027C 641 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000074C B299 0002 0000000000000002 642 SRNM 2 SET FPCR to RP, to +infinity +0000000000000750 B39E 0410 643 CLFXBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked +0000000000000754 5010 7004 0000000000000004 644 ST R1,1*4(,R7) Store uint-32 result +0000000000000758 B29C 8004 0000000000000004 645 STFPC 1*4(R8) Store resulting FPCR flags and DXC +000000000000075C B222 0010 646 IPM R1 Get condition code and program mask +0000000000000760 8810 001C 000000000000001C 647 SRL R1,28 Isolate CC in low order byte +0000000000000764 4210 8007 0000000000000007 648 STC R1,(1*4)+3(,R8) Save condition code as low byte of FPCR + 649 * +0000000000000768 B29D F27C 000000000000027C 650 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000076C B2B8 0003 0000000000000003 651 SRNMB 3 SET FPCR to RM, to -infinity +0000000000000770 B39E 0410 652 CLFXBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked + ASMA Ver. 0.2.0 ieee-cvttolog.asm: Test IEEE Convert To Logical (uint-32) 01 Sep 2016 10:11:17 Page 16 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000774 5010 7008 0000000000000008 653 ST R1,2*4(,R7) Store uint-32 result +0000000000000778 B29C 8008 0000000000000008 654 STFPC 2*4(R8) Store resulting FPCR flags and DXC +000000000000077C B222 0010 655 IPM R1 Get condition code and program mask +0000000000000780 8810 001C 000000000000001C 656 SRL R1,28 Isolate CC in low order byte +0000000000000784 4210 800B 000000000000000B 657 STC R1,(2*4)+3(,R8) Save condition code as low byte of FPCR + 658 * +0000000000000788 B29D F27C 000000000000027C 659 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000078C B2B8 0007 0000000000000007 660 SRNMB 7 RFS, Prepare for Shorter Precision +0000000000000790 B39E 0410 661 CLFXBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked +0000000000000794 5010 700C 000000000000000C 662 ST R1,3*4(,R7) Store uint-32 result +0000000000000798 B29C 800C 000000000000000C 663 STFPC 3*4(R8) Store resulting FPCR flags and DXC +000000000000079C B222 0010 664 IPM R1 Get condition code and program mask +00000000000007A0 8810 001C 000000000000001C 665 SRL R1,28 Isolate CC in low order byte +00000000000007A4 4210 800F 000000000000000F 666 STC R1,(3*4)+3(,R8) Save condition code as low byte of FPCR + 667 * + 668 * Test cases using rounding mode specified in the instruction M3 field + 669 * +00000000000007A8 B29D F27C 000000000000027C 670 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000007AC B39E 1010 671 CLFXBR R1,1,FPR0,B'0000' RNTA, to nearest, ties away +00000000000007B0 5010 7010 0000000000000010 672 ST R1,4*4(,R7) Store uint-32 result +00000000000007B4 B29C 8010 0000000000000010 673 STFPC 4*4(R8) Store resulting FPCR flags and DXC +00000000000007B8 B222 0010 674 IPM R1 Get condition code and program mask +00000000000007BC 8810 001C 000000000000001C 675 SRL R1,28 Isolate CC in low order byte +00000000000007C0 4210 8013 0000000000000013 676 STC R1,(4*4)+3(,R8) Save condition code as low byte of FPCR + 677 * +00000000000007C4 B29D F27C 000000000000027C 678 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000007C8 B39E 3010 679 CLFXBR R1,3,FPR0,B'0000' RFS, prepare for shorter precision +00000000000007CC 5010 7014 0000000000000014 680 ST R1,5*4(,R7) Store uint-32 result +00000000000007D0 B29C 8014 0000000000000014 681 STFPC 5*4(R8) Store resulting FPCR flags and DXC +00000000000007D4 B222 0010 682 IPM R1 Get condition code and program mask +00000000000007D8 8810 001C 000000000000001C 683 SRL R1,28 Isolate CC in low order byte +00000000000007DC 4210 8017 0000000000000017 684 STC R1,(5*4)+3(,R8) Save condition code as low byte of FPCR + 685 * +00000000000007E0 B29D F27C 000000000000027C 686 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000007E4 B39E 4010 687 CLFXBR R1,4,FPR0,B'0000' RNTE, to nearest, ties to even +00000000000007E8 5010 7018 0000000000000018 688 ST R1,6*4(,R7) Store uint-32 result +00000000000007EC B29C 8018 0000000000000018 689 STFPC 6*4(R8) Store resulting FPCR flags and DXC +00000000000007F0 B222 0010 690 IPM R1 Get condition code and program mask +00000000000007F4 8810 001C 000000000000001C 691 SRL R1,28 Isolate CC in low order byte +00000000000007F8 4210 801B 000000000000001B 692 STC R1,(6*4)+3(,R8) Save condition code as low byte of FPCR + 693 * +00000000000007FC B29D F27C 000000000000027C 694 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000800 B39E 5010 695 CLFXBR R1,5,FPR0,B'0000' RZ, toward zero +0000000000000804 5010 701C 000000000000001C 696 ST R1,7*4(,R7) Store uint-32 result +0000000000000808 B29C 801C 000000000000001C 697 STFPC 7*4(R8) Store resulting FPCR flags and DXC +000000000000080C B222 0010 698 IPM R1 Get condition code and program mask +0000000000000810 8810 001C 000000000000001C 699 SRL R1,28 Isolate CC in low order byte +0000000000000814 4210 801F 000000000000001F 700 STC R1,(7*4)+3(,R8) Save condition code as low byte of FPCR + 701 * +0000000000000818 B29D F27C 000000000000027C 702 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000081C B39E 6010 703 CLFXBR R1,6,FPR0,B'0000' RP, to +inf +0000000000000820 5010 7020 0000000000000020 704 ST R1,8*4(,R7) Store uint-32 result + ASMA Ver. 0.2.0 ieee-cvttolog.asm: Test IEEE Convert To Logical (uint-32) 01 Sep 2016 10:11:17 Page 17 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000824 B29C 8020 0000000000000020 705 STFPC 8*4(R8) Store resulting FPCR flags and DXC +0000000000000828 B222 0010 706 IPM R1 Get condition code and program mask +000000000000082C 8810 001C 000000000000001C 707 SRL R1,28 Isolate CC in low order byte +0000000000000830 4210 8023 0000000000000023 708 STC R1,(8*4)+3(,R8) Save condition code as low byte of FPCR + 709 * +0000000000000834 B29D F27C 000000000000027C 710 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000838 B39E 7010 711 CLFXBR R1,7,FPR0,B'0000' RM, to -inf +000000000000083C 5010 7024 0000000000000024 712 ST R1,9*4(,R7) Store uint-32 result +0000000000000840 B29C 8024 0000000000000024 713 STFPC 9*4(R8) Store resulting FPCR flags and DXC +0000000000000844 B222 0010 714 IPM R1 Get condition code and program mask +0000000000000848 8810 001C 000000000000001C 715 SRL R1,28 Isolate CC in low order byte +000000000000084C 4210 8027 0000000000000027 716 STC R1,(9*4)+3(,R8) Save condition code as low byte of FPCR + 717 * +0000000000000850 4130 3010 0000000000000010 718 LA R3,16(,R3) Point to next input value +0000000000000854 4170 7030 0000000000000030 719 LA R7,12*4(,R7) Point to next long BFP converted values +0000000000000858 4180 8030 0000000000000030 720 LA R8,12*4(,R8) Point to next FPCR/CC result area +000000000000085C 062C 721 BCTR R2,R12 Convert next input value. +000000000000085E 07FD 722 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvttolog.asm: Test IEEE Convert To Logical (uint-32) 01 Sep 2016 10:11:17 Page 18 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 724 *********************************************************************** + 725 * + 726 * Floating point inputs for Convert From Fixed testing. The same test + 727 * values in the appropriate input format are used for short, long, + 728 * and extended format tests. The last four values should generate + 729 * exceptions. + 730 * + 731 *********************************************************************** + + + 733 * + 734 * Inputs for short BFP testing of trap and non-trap results + 735 * +0000000000000860 736 SBFPIN DS 0F Inputs for short BFP testing +0000000000000860 3F800000 737 DC X'3F800000' +1.0 +0000000000000864 40000000 738 DC X'40000000' +2.0 +0000000000000868 40800000 739 DC X'40800000' +4.0 +000000000000086C 7F810000 740 DC X'7F810000' SNaN +0000000000000870 7FC10000 741 DC X'7FC10000' QNaN +0000000000000874 4F800000 742 DC X'4F800000' Max uint-32 + 1 rounded to short BFP + 743 * ...4 294 967 296 +0000000000000878 4F7FFFFF 744 DC X'4F7FFFFF' Max uint-32 value representable + 745 * ...in short bfp (4 294 967 040) +000000000000087C 3F400000 746 DC X'3F400000' +0.75 +0000000000000880 3E800000 747 DC X'3E800000' +0.25 + 0000000000000024 0000000000000001 748 SBFPCT EQU *-SBFPIN Count of short BFP in list * 4 + 749 * + 750 * Inputs for short BFP exhaustive rounding mode testing. + 751 * +0000000000000884 752 SBFPINRM DS 0F +0000000000000884 BFC00000 753 DC X'BFC00000' -1.5 +0000000000000888 BF000000 754 DC X'BF000000' -0.5 +000000000000088C 3F000000 755 DC X'3F000000' +0.5 +0000000000000890 3FC00000 756 DC X'3FC00000' +1.5 +0000000000000894 40200000 757 DC X'40200000' +2.5 +0000000000000898 40B00000 758 DC X'40B00000' +5.5 +000000000000089C 41180000 759 DC X'41180000' +9.5 +00000000000008A0 4F7FFFFF 760 DC X'4F7FFFFF' largest uint-32 value representable + 761 * ...in short bfp (4 294 967 040) +00000000000008A4 3F400000 762 DC X'3F400000' +0.75 +00000000000008A8 3E800000 763 DC X'3E800000' +0.25 + 0000000000000028 0000000000000001 764 SBFPRMCT EQU *-SBFPINRM Count of short BFP for rounding tests * 4 + 765 * + 766 * Inputs for long BFP testing of trap and non-trap results + 767 * +00000000000008AC 768 LBFPIN DS 0F Inputs for long BFP testing +00000000000008AC 3FF00000 00000000 769 DC X'3FF0000000000000' +1.0 +00000000000008B4 40000000 00000000 770 DC X'4000000000000000' +2.0 +00000000000008BC 40100000 00000000 771 DC X'4010000000000000' +4.0 +00000000000008C4 7FF01000 00000000 772 DC X'7FF0100000000000' SNaN +00000000000008CC 7FF81000 00000000 773 DC X'7FF8100000000000' QNaN +00000000000008D4 41EFFFFF FFF00000 774 DC X'41EFFFFFFFF00000' max uint-32 + 0.5 + ASMA Ver. 0.2.0 ieee-cvttolog.asm: Test IEEE Convert To Logical (uint-32) 01 Sep 2016 10:11:17 Page 19 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 775 * ...4 294 967 295.5 + 776 * Rounds up on RNTE, overflows +00000000000008DC 41EFFFFF FFECCCCD 777 DC X'41EFFFFFFFECCCCD' max uint-32 + 0.4 + 778 * ...4 294 967 295.4, exceeds + 779 * uint-32, but rounds down to fit +00000000000008E4 3FE80000 00000000 780 DC X'3FE8000000000000' +0.75 +00000000000008EC 3FD00000 00000000 781 DC X'3FD0000000000000' +0.25 + 0000000000000048 0000000000000001 782 LBFPCT EQU *-LBFPIN Count of long BFP in list * 8 + 783 * + 784 * Inputs for long BFP exhaustive rounding mode testing. + 785 * +00000000000008F4 786 LBFPINRM DS 0F +00000000000008F4 BFF80000 00000000 787 DC X'BFF8000000000000' -1.5 +00000000000008FC BFE00000 00000000 788 DC X'BFE0000000000000' -0.5 +0000000000000904 3FE00000 00000000 789 DC X'3FE0000000000000' +0.5 +000000000000090C 3FF80000 00000000 790 DC X'3FF8000000000000' +1.5 +0000000000000914 40040000 00000000 791 DC X'4004000000000000' +2.5 +000000000000091C 40160000 00000000 792 DC X'4016000000000000' +5.5 +0000000000000924 40230000 00000000 793 DC X'4023000000000000' +9.5 +000000000000092C 41EFFFFF FFF00000 794 DC X'41EFFFFFFFF00000' max uint-32 + 0.5 + 795 * ...4 294 967 295.5 +0000000000000934 3FE80000 00000000 796 DC X'3FE8000000000000' +0.75 +000000000000093C 3FD00000 00000000 797 DC X'3FD0000000000000' +0.25 + 0000000000000050 0000000000000001 798 LBFPRMCT EQU *-LBFPINRM Count of long BFP for rounding tests * 8 + 799 * + 800 * Inputs for short BFP testing of trap and non-trap results + 801 * +0000000000000948 802 XBFPIN DS 0D Inputs for long BFP testing +0000000000000948 3FFF0000 00000000 803 DC X'3FFF0000000000000000000000000000' +1.0 +0000000000000958 40000000 00000000 804 DC X'40000000000000000000000000000000' +2.0 +0000000000000968 40010000 00000000 805 DC X'40010000000000000000000000000000' +4.0 +0000000000000978 7FFF0100 00000000 806 DC X'7FFF0100000000000000000000000000' SNaN +0000000000000988 7FFF8100 00000000 807 DC X'7FFF8100000000000000000000000000' QNaN +0000000000000998 401EFFFF FFFF0000 808 DC X'401EFFFFFFFF00000000000000000000' max uint-32+0.5 + 809 * ...4 294 967 295.5 + 810 * Rounds up on RNTE, overflows +00000000000009A8 401EFFFF FFFECCCC 811 DC X'401EFFFFFFFECCCCCCCCCCCCCCCCCCCD' max uint-32+0.4 + 812 * ...4 294 967 295.4, exceeds + 813 * uint-32, but rounds down to fit +00000000000009B8 3FFE8000 00000000 814 DC X'3FFE8000000000000000000000000000' 0.75 +00000000000009C8 3FFD0000 00000000 815 DC X'3FFD0000000000000000000000000000' 0.25 + 0000000000000090 0000000000000001 816 XBFPCT EQU *-XBFPIN Count of extended BFP in list * 16 + 817 * + 818 * Inputs for extended BFP exhaustive rounding mode testing. + 819 * +00000000000009D8 820 XBFPINRM DS 0D +00000000000009D8 BFFF8000 00000000 821 DC X'BFFF8000000000000000000000000000' -1.5 +00000000000009E8 BFFE0000 00000000 822 DC X'BFFE0000000000000000000000000000' -0.5 +00000000000009F8 3FFE0000 00000000 823 DC X'3FFE0000000000000000000000000000' +0.5 +0000000000000A08 3FFF8000 00000000 824 DC X'3FFF8000000000000000000000000000' +1.5 +0000000000000A18 40004000 00000000 825 DC X'40004000000000000000000000000000' +2.5 +0000000000000A28 40016000 00000000 826 DC X'40016000000000000000000000000000' +5.5 + ASMA Ver. 0.2.0 ieee-cvttolog.asm: Test IEEE Convert To Logical (uint-32) 01 Sep 2016 10:11:17 Page 20 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000A38 40023000 00000000 827 DC X'40023000000000000000000000000000' +9.5 +0000000000000A48 401EFFFF FFFF0000 828 DC X'401EFFFFFFFF00000000000000000000' max uint-32 + 0.5 + 829 * (+4 294 967 295.5) + 830 * Above is always inexact, and may overflow based on rounding mode +0000000000000A58 3FFE8000 00000000 831 DC X'3FFE8000000000000000000000000000' 0.75 +0000000000000A68 3FFD0000 00000000 832 DC X'3FFD0000000000000000000000000000' 0.25 + 00000000000000A0 0000000000000001 833 XBFPRMCT EQU *-XBFPINRM Count of extended BFP rounding tests * 16 + 834 * + 835 * Locations for results + 836 * + 0000000000001000 0000000000000000 837 SINTOUT EQU BFPCVTTL+X'1000' uint-32 values from short BFP + 838 * ..7 pairs used, room for 16 + 0000000000001100 0000000000000000 839 SINTFLGS EQU BFPCVTTL+X'1100' FPCR flags and DXC from short BFP + 840 * ..7 pairs used, room for 16 + 0000000000001200 0000000000000000 841 SINTRMO EQU BFPCVTTL+X'1200' Short rounding mode test results + 842 * ..8 sets used, room for 20 + 0000000000001600 0000000000000000 843 SINTRMOF EQU BFPCVTTL+X'1600' Short rounding mode FPCR contents + 844 * ..8 sets used, room for 20 + 845 * + 0000000000002000 0000000000000000 846 LINTOUT EQU BFPCVTTL+X'2000' uint-32 values from long BFP + 847 * ..7 pairs used, room for 16 + 0000000000002100 0000000000000000 848 LINTFLGS EQU BFPCVTTL+X'2100' FPCR flags and DXC from long BFP + 849 * ..7 pairs used, room for 16 + 0000000000002200 0000000000000000 850 LINTRMO EQU BFPCVTTL+X'2200' Long rounding mode test results + 851 * ..8 sets used, room for 20 + 0000000000002600 0000000000000000 852 LINTRMOF EQU BFPCVTTL+X'2600' Long rounding mode FPCR contents + 853 * ..8 sets used, room for 20 + 854 * + 0000000000003000 0000000000000000 855 XINTOUT EQU BFPCVTTL+X'3000' uint-32 values from extended BFP + 856 * ..7 pairs used, room for 16 + 0000000000003100 0000000000000000 857 XINTFLGS EQU BFPCVTTL+X'3100' FPCR flags and DXC from extended BFP + 858 * ..7 pairs used, room for 16 + 0000000000003200 0000000000000000 859 XINTRMO EQU BFPCVTTL+X'3200' Extended rounding mode test results + 860 * ..8 sets used, room for 20 + 0000000000003600 0000000000000000 861 XINTRMOF EQU BFPCVTTL+X'3600' Extended rounding mode FPCR contents + 862 * ..8 sets used, room for 20 + 863 * + 0000000000003A00 0000000000000000 864 ENDLABL EQU BFPCVTTL+X'3A00' end of test program + 865 PADCSECT ENDLABL pad csect for non-asma assembly + 866+ MNOTE *,'asma detected; no CSECT padding performed' +0000000000000A78 867 END + ASMA Ver. 0.2.0 ieee-cvttolog.asm: Test IEEE Convert To Logical (uint-32) 01 Sep 2016 10:11:17 Page 21 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +BFPCVTTL J 000000 2680 88 130 133 135 138 146 205 837 839 841 843 846 848 850 852 855 857 859 + 861 864 +CLFDBR I 000508 4 409 176 +CLFDBRA I 000566 4 459 178 +CLFEBR I 000360 4 248 169 +CLFEBRA I 0003BE 4 298 171 +CLFXBR I 0006B0 4 570 183 +CLFXBRA I 000712 4 621 185 +CTLR0 F 000278 4 195 162 163 164 +ENDLABL U 003A00 0 864 +EXTDS F 000320 4 218 182 +FPCREGNT X 00027C 4 196 255 308 317 326 335 346 354 362 370 378 386 416 469 478 487 496 507 + 515 523 531 539 547 578 632 641 650 659 670 678 686 694 702 710 +FPCREGTR X 000280 4 197 263 424 586 +FPR0 U 000000 1 108 254 256 266 304 310 319 328 337 347 355 363 371 379 387 415 417 427 + 465 471 480 489 498 508 516 524 532 540 548 576 579 589 627 634 643 + 652 661 671 679 687 695 703 711 +FPR1 U 000001 1 109 +FPR10 U 00000A 1 118 +FPR11 U 00000B 1 119 +FPR12 U 00000C 1 120 +FPR13 U 00000D 1 121 +FPR14 U 00000E 1 122 +FPR15 U 00000F 1 123 +FPR2 U 000002 1 110 577 628 +FPR3 U 000003 1 111 +FPR4 U 000004 1 112 +FPR5 U 000005 1 113 +FPR6 U 000006 1 114 +FPR7 U 000007 1 115 +FPR8 U 000008 1 116 +FPR9 U 000009 1 117 +HARDWAIT X 000268 8 193 154 +IMAGE 1 000000 2680 0 +LBFPCT U 000048 1 782 213 +LBFPIN F 0008AC 4 768 782 214 +LBFPINRM F 0008F4 4 786 798 230 +LBFPRMCT U 000050 1 798 229 +LINTFLGS U 002100 0 848 216 +LINTOUT U 002000 0 846 215 +LINTRMO U 002200 0 850 231 +LINTRMOF U 002600 0 852 232 +LONGS F 000310 4 212 175 +PCINTCD H 00008E 2 131 148 +PCNOTDTA H 00020C 2 151 149 +PCOLDPSW U 000150 0 133 150 +PROGCHK H 000200 2 147 139 +R0 U 000000 1 89 162 164 +R1 U 000001 1 90 256 257 259 260 261 264 265 266 267 269 270 271 310 311 313 314 315 + 319 320 322 323 324 328 329 331 332 333 337 338 340 341 342 347 348 + 350 351 352 355 356 358 359 360 363 364 366 367 368 371 372 374 375 + 376 379 380 382 383 384 387 388 390 391 392 417 418 420 421 422 425 + ASMA Ver. 0.2.0 ieee-cvttolog.asm: Test IEEE Convert To Logical (uint-32) 01 Sep 2016 10:11:17 Page 22 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + + 426 427 428 430 431 432 471 472 474 475 476 480 481 483 484 485 489 + 490 492 493 494 498 499 501 502 503 508 509 511 512 513 516 517 519 + 520 521 524 525 527 528 529 532 533 535 536 537 540 541 543 544 545 + 548 549 551 552 553 579 580 582 583 584 587 588 589 590 592 593 594 + 634 635 637 638 639 643 644 646 647 648 652 653 655 656 657 661 662 + 664 665 666 671 672 674 675 676 679 680 682 683 684 687 688 690 691 + 692 695 696 698 699 700 703 704 706 707 708 711 712 714 715 716 +R10 U 00000A 1 99 168 170 175 177 182 184 248 249 298 299 409 410 459 460 570 571 621 + 622 +R11 U 00000B 1 100 +R12 U 00000C 1 101 252 276 302 397 413 437 463 558 574 599 625 721 +R13 U 00000D 1 102 169 171 176 178 183 185 251 277 301 398 412 438 462 559 573 600 624 + 722 +R14 U 00000E 1 103 152 153 187 188 +R15 U 00000F 1 104 125 +R2 U 000002 1 91 248 250 276 298 300 397 409 411 437 459 461 558 570 572 599 621 623 + 721 +R3 U 000003 1 92 248 254 273 298 304 394 409 415 434 459 465 555 570 576 577 596 621 + 627 628 718 +R4 U 000004 1 93 +R5 U 000005 1 94 +R6 U 000006 1 95 +R7 U 000007 1 96 249 257 267 274 299 311 320 329 338 348 356 364 372 380 388 395 410 + 418 428 435 460 472 481 490 499 509 517 525 533 541 549 556 571 580 + 590 597 622 635 644 653 662 672 680 688 696 704 712 719 +R8 U 000008 1 97 249 258 261 268 271 275 299 312 315 321 324 330 333 339 342 349 352 + 357 360 365 368 373 376 381 384 389 392 396 410 419 422 429 432 436 + 460 473 476 482 485 491 494 500 503 510 513 518 521 526 529 534 537 + 542 545 550 553 557 571 581 584 591 594 598 622 636 639 645 648 654 + 657 663 666 673 676 681 684 689 692 697 700 705 708 713 716 720 +R9 U 000009 1 98 +RMEXTDS A 000350 4 234 184 +RMLONGS A 000340 4 229 177 +RMSHORTS A 000330 4 224 170 +SBFPCT U 000024 1 748 207 +SBFPIN F 000860 4 736 748 208 +SBFPINRM F 000884 4 752 764 225 +SBFPRMCT U 000028 1 764 224 +SHORTS F 000300 4 206 168 +SINTFLGS U 001100 0 839 210 +SINTOUT U 001000 0 837 209 +SINTRMO U 001200 0 841 226 +SINTRMOF U 001600 0 843 227 +START I 000214 4 162 136 +WAITPSW X 000258 8 192 189 +XBFPCT U 000090 1 816 219 +XBFPIN D 000948 8 802 816 220 +XBFPINRM D 0009D8 8 820 833 235 +XBFPRMCT U 0000A0 1 833 234 +XINTFLGS U 003100 0 857 222 +XINTOUT U 003000 0 855 221 +XINTRMO U 003200 0 859 236 + ASMA Ver. 0.2.0 ieee-cvttolog.asm: Test IEEE Convert To Logical (uint-32) 01 Sep 2016 10:11:17 Page 23 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +XINTRMOF U 003600 0 861 237 + ASMA Ver. 0.2.0 ieee-cvttolog.asm: Test IEEE Convert To Logical (uint-32) 01 Sep 2016 10:11:17 Page 24 + + MACRO DEFN REFERENCES + +PADCSECT 63 865 + ASMA Ver. 0.2.0 ieee-cvttolog.asm: Test IEEE Convert To Logical (uint-32) 01 Sep 2016 10:11:17 Page 25 + + DESC SYMBOL SIZE POS ADDR + +Entry: 0 + +Image IMAGE 2680 000-A77 000-A77 + Region 2680 000-A77 000-A77 + CSECT BFPCVTTL 2680 000-A77 000-A77 + ASMA Ver. 0.2.0 ieee-cvttolog.asm: Test IEEE Convert To Logical (uint-32) 01 Sep 2016 10:11:17 Page 26 + + STMT FILE NAME + +1 C:\Users\srorso\Documents\GitHub\hyperion\tests\bfp-004-cvttolog.asm + + +** NO ERRORS FOUND ** + +[866] MNOTE *,asma detected; no CSECT padding performed + \ No newline at end of file diff --git a/tests/bfp-004-cvttolog.tst b/tests/bfp-004-cvttolog.tst new file mode 100644 index 000000000..87e99caa0 --- /dev/null +++ b/tests/bfp-004-cvttolog.tst @@ -0,0 +1,541 @@ +*Testcase bfp-004-cvttolog.tst: CLFEBR, CLFDBR, CLFXBR + +#Testcase bfp-004-cvttolog.tst: IEEE Convert To Logical +#..Includes CONVERT TO LOGICAL 32 (3). Tests traps, exceptions, +#..rounding modes, and NaN propagation. + +sysclear +archmode esame + +# +# Following suppresses logging of program checks. This test program, as part +# of its normal operation, generates 17program check messages that have no +# value in the validation process. (The messages, not the program checks.) +# +ostailor quiet + +loadcore "$(testpath)/bfp-004-cvttolog.core" +runtest 1.0 + +ostailor null # restore messages for subsequent tests + + +# BFP short inputs converted to uint-32 test results +*Compare +r 1000.10 +*Want "CLFEBR result pairs 1-2" 00000001 00000001 00000002 00000002 +r 1010.10 +*Want "CLFEBR result pairs 3-4" 00000004 00000004 00000000 00000000 +r 1020.10 +*Want "CLFEBR result pairs 5-6" 00000000 00000000 FFFFFFFF 00000000 +r 1030.10 +*Want "CLFEBR result pairs 7-8" FFFFFF00 FFFFFF00 00000001 00000001 +r 1040.08 +*Want "CLFEBR result pair 9" 00000000 00000000 + +# BFP short inputs converted to uint-32 FPCR contents, cc +*Compare +r 1100.10 +*Want "CLFEBR FPC pairs 1-2" 00000002 F8000002 00000002 F8000002 +r 1110.10 +*Want "CLFEBR FPC pairs 3-4" 00000002 F8000002 00880003 F8008000 +r 1120.10 +*Want "CLFEBR FPC pairs 5-6" 00880003 F8008000 00880003 F8008000 +r 1130.10 +*Want "CLFEBR FPC pairs 7-8" 00000002 F8000002 00080002 F8000C02 +r 1140.08 +*Want "CLFEBR FPC pair 9" 00080002 F8000802 + +# rounding mode tests - short BFP - results from rounding +*Compare +r 1200.10 # RZ, RP, RM, RFS +*Want "CLFEBR -1.5 FPC modes 1-3, 7" 00000000 00000000 00000000 00000000 +r 1210.10 # RNTA, RFS, RNTE, RZ +*Want "CLFEBR -1.5 M3 modes 1, 3-5" 00000000 00000000 00000000 00000000 +r 1220.08 # RP, RM +*Want "CLFEBR -1.5 M3 modes 6, 7" 00000000 00000000 + +r 1230.10 # RZ, RP, RM, RFS +*Want "CLFEBR -0.5 FPC modes 1-3, 7" 00000000 00000000 00000000 00000000 +r 1240.10 # RNTA, RFS, RNTE, RZ +*Want "CLFEBR -0.5 M3 modes 1, 3-5" 00000000 00000000 00000000 00000000 +r 1250.08 # RP, RM +*Want "CLFEBR -0.5 M3 modes 6, 7" 00000000 00000000 + +r 1260.10 # RZ, RP, RM, RFS +*Want "CLFEBR 0.5 FPC modes 1-3, 7" 00000000 00000001 00000000 00000001 +r 1270.10 # RNTA, RFS, RNTE, RZ +*Want "CLFEBR 0.5 M3 modes 1, 3-5" 00000001 00000001 00000000 00000000 +r 1280.08 # RP, RM +*Want "CLFEBR 0.5 M3 modes 6, 7" 00000001 00000000 + +r 1290.10 # RZ, RP, RM, RFS +*Want "CLFEBR 1.5 FPC modes 1-3, 7" 00000001 00000002 00000001 00000001 +r 12A0.10 # RNTA, RFS, RNTE, RZ +*Want "CLFEBR 1.5 M3 modes 1, 3-5" 00000002 00000001 00000002 00000001 +r 12B0.08 # RP, RM +*Want "CLFEBR 1.5 M3 modes 6, 7" 00000002 00000001 + +r 12C0.10 # RZ, RP, RM, RFS +*Want "CLFEBR 2.5 FPC modes 1-3, 7" 00000002 00000003 00000002 00000003 +r 12D0.10 # RNTA, RFS, RNTE, RZ +*Want "CLFEBR 2.5 M3 modes 1, 3-5" 00000003 00000003 00000002 00000002 +r 12E0.08 # RP, RM +*Want "CLFEBR 2.5 M3 modes 6, 7" 00000003 00000002 + +r 12F0.10 # RZ, RP, RM, RFS +*Want "CLFEBR 5.5 FPC modes 1-3, 7" 00000005 00000006 00000005 00000005 +r 1300.10 # RNTA, RFS, RNTE, RZ +*Want "CLFEBR 5.5 M3 modes 1, 3-5" 00000006 00000005 00000006 00000005 +r 1310.08 # RP, RM +*Want "CLFEBR 5.5 M3 modes 6, 7" 00000006 00000005 + +r 1320.10 # RZ, RP, RM, RFS +*Want "CLFEBR 9.5 FPC modes 1-3, 7" 00000009 0000000A 00000009 00000009 +r 1330.10 # RNTA, RFS, RNTE, RZ +*Want "CLFEBR 9.5 M3 modes 1, 3-5" 0000000A 00000009 0000000A 00000009 +r 1340.08 # RP, RM +*Want "CLFEBR 9.5 M3 modes 6, 7" 0000000A 00000009 + +r 1350.10 # RZ, RP, RM, RFS +*Want "CLFEBR max FPC modes 1-3, 7" FFFFFF00 FFFFFF00 FFFFFF00 FFFFFF00 +r 1360.10 # RNTA, RFS, RNTE, RZ +*Want "CLFEBR max M3 modes 1, 3-5" FFFFFF00 FFFFFF00 FFFFFF00 FFFFFF00 +r 1370.08 # RP, RM +*Want "CLFEBR max M3 modes 6, 7" FFFFFF00 FFFFFF00 + +r 1380.10 # RZ, RP, RM, RFS +*Want "CLFEBR 0.75 FPC modes 1-3, 7" 00000000 00000001 00000000 00000001 +r 1390.10 # RNTA, RFS, RNTE, RZ +*Want "CLFEBR 0.75 M3 modes 1, 3-5" 00000001 00000001 00000001 00000000 +r 13A0.08 # RP, RM +*Want "CLFEBR 0.75 M3 modes 6, 7" 00000001 00000000 + +r 13B0.10 # RZ, RP, RM, RFS +*Want "CLFEBR 0.25 FPC modes 1-3, 7" 00000000 00000001 00000000 00000001 +r 13C0.10 # RNTA, RFS, RNTE, RZ +*Want "CLFEBR 0.25 M3 modes 1, 3-5" 00000000 00000001 00000000 00000000 +r 13D0.08 # RP, RM +*Want "CLFEBR 0.25 M3 modes 6, 7" 00000001 00000000 + + +# rounding mode tests - short BFP - FPCR contents with cc in last byte +*Compare +r 1600.10 +*Want "CLFEBR -1.5 FPC modes 1-3, 7 FPCR" 00800003 00800003 00800003 00800003 +r 1610.10 +*Want "CLFEBR -1.5 M3 modes 1, 3-5 FPCR" 00880003 00880003 00880003 00880003 +r 1620.08 +*Want "CLFEBR -1.5 M3 modes 6, 7 FPCR" 00880003 00880003 + +r 1630.10 +*Want "CLFEBR -0.5 FPC modes 1-3, 7 FPCR" 00000001 00000001 00800003 00800003 +r 1640.10 +*Want "CLFEBR -0.5 M3 modes 1, 3-5 FPCR" 00880003 00880003 00080001 00080001 +r 1650.08 +*Want "CLFEBR -0.5 M3 modes 6, 7 FPCR" 00080001 00880003 + +r 1660.10 +*Want "CLFEBR +0.5 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 1670.10 +*Want "CLFEBR +0.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 1680.08 +*Want "CLFEBR +0.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 1690.10 +*Want "CLFEBR +1.5 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 16A0.10 +*Want "CLFEBR +1.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 16B0.08 +*Want "CLFEBR +1.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 16C0.10 +*Want "CLFEBR +2.5 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 16D0.10 +*Want "CLFEBR +2.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 16E0.08 +*Want "CLFEBR +2.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 16F0.10 +*Want "CLFEBR +5.5 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 1700.10 +*Want "CLFEBR +5.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 1710.08 +*Want "CLFEBR +5.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 1720.10 +*Want "CLFEBR +9.5 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 1730.10 +*Want "CLFEBR +9.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 1740.08 +*Want "CLFEBR +9.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 1750.10 +*Want "CLFEBR max FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 1760.10 +*Want "CLFEBR max M3 modes 1, 3-5 FPCR" 00000002 00000002 00000002 00000002 +r 1770.08 +*Want "CLFEBR max M3 modes 5-7" 00000002 00000002 + +r 1780.10 # RZ, RP, RM, RFS +*Want "CLFEBR +0.75 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 1790.10 # RNTA, RFS, RNTE, RZ +*Want "CLFEBR +0.75 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 17A0.08 # RP, RM +*Want "CLFEBR +0.75 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 17B0.10 +*Want "CLFEBR +0.25 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 17C0.10 +*Want "CLFEBR +0.25 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 17D0.08 +*Want "CLFEBR +0.25 M3 modes 6, 7 FPCR" 00080002 00080002 + + +# BFP short inputs converted to uint-32 test results +*Compare +r 2000.10 +*Want "CLFDBR result pairs 1-2" 00000001 00000001 00000002 00000002 +r 2010.10 +*Want "CLFDBR result pairs 3-4" 00000004 00000004 00000000 00000000 +r 2020.10 +*Want "CLFDBR result pairs 5-6" 00000000 00000000 FFFFFFFF 00000000 +r 2030.10 +*Want "CLFDBR result pairs 7-8" FFFFFFFF FFFFFFFF 00000001 00000001 +r 2040.08 +*Want "CLFDBR result pair 9" 00000000 00000000 + +# BFP long inputs converted to uint-32 FPCR contents, cc +*Compare +r 2100.10 +*Want "CLFDBR FPC pairs 1-2" 00000002 F8000002 00000002 F8000002 +r 2110.10 +*Want "CLFDBR FPC pairs 3-4" 00000002 F8000002 00880003 F8008000 +r 2120.10 +*Want "CLFDBR FPC pairs 5-6" 00880003 F8008000 00880003 F8008000 +r 2130.10 +*Want "CLFDBR FPC pairs 7-8" 00080002 F8000802 00080002 F8000C02 +r 2140.08 +*Want "CLFDBR FPC pair 9" 00080002 F8000802 + + +# rounding mode tests - long BFP - results from rounding +*Compare +r 2200.10 # RZ, RP, RM, RFS +*Want "CLFDBR -1.5 FPC modes 1-3, 7" 00000000 00000000 00000000 00000000 +r 2210.10 # RNTA, FS, RNTE, RZ +*Want "CLFDBR -1.5 M3 modes 1, 3-5" 00000000 00000000 00000000 00000000 +r 2220.08 # RP, RM +*Want "CLFDBR -1.5 M3 modes 6, 7" 00000000 00000000 + +r 2230.10 # RZ, RP, RM, RFS +*Want "CLFDBR -0.5 FPC modes 1-3, 7" 00000000 00000000 00000000 00000000 +r 2240.10 # RNTA, RFS, RNTE, RZ +*Want "CLFDBR -0.5 M3 modes 1, 3-5" 00000000 00000000 00000000 00000000 +r 2250.08 # RP, RM +*Want "CLFDBR -0.5 M3 modes 6, 7" 00000000 00000000 + +r 2260.10 # RZ, RP, RM, RFS +*Want "CLFDBR 0.5 FPC modes 1-3, 7" 00000000 00000001 00000000 00000001 +r 2270.10 # RNTA, RFS, RNTE, RZ +*Want "CLFDBR 0.5 M3 modes 1, 3-5" 00000001 00000001 00000000 00000000 +r 2280.08 # RP, RM +*Want "CLFDBR 0.5 M3 modes 6, 7" 00000001 00000000 + +r 2290.10 # RZ, RP, RM, RFS +*Want "CLFDBR 1.5 FPC modes 1-3, 7" 00000001 00000002 00000001 00000001 +r 22A0.10 # RNTA, RFS, RNTE, RZ +*Want "CLFDBR 1.5 M3 modes 1, 3-5" 00000002 00000001 00000002 00000001 +r 22B0.08 # RP, RM +*Want "CLFDBR 1.5 M3 modes 6, 7" 00000002 00000001 + +r 22C0.10 # RZ, RP, RM, RFS +*Want "CLFDBR 2.5 FPC modes 1-3, 7" 00000002 00000003 00000002 00000003 +r 22D0.10 # RNTA, RFS, RNTE, RZ +*Want "CLFDBR 2.5 M3 modes 1, 3-5" 00000003 00000003 00000002 00000002 +r 22E0.08 # RP, RM +*Want "CLFDBR 2.5 M3 modes 6, 7" 00000003 00000002 + +r 22F0.10 # RZ, RP, RM, RFS +*Want "CLFDBR 5.5 FPC modes 1-3, 7" 00000005 00000006 00000005 00000005 +r 2300.10 # RNTA, RFS, RNTE, RZ +*Want "CLFDBR 5.5 M3 modes 1, 3-5" 00000006 00000005 00000006 00000005 +r 2310.08 # RP, RM +*Want "CLFDBR 5.5 M3 modes 6, 7" 00000006 00000005 + +r 2320.10 # RZ, RP, RM, RFS +*Want "CLFDBR 9.5 FPC modes 1-3, 7" 00000009 0000000A 00000009 00000009 +r 2330.10 # RNTA, RFS, RNTE, RZ +*Want "CLFDBR 9.5 M3 modes 1, 3-5" 0000000A 00000009 0000000A 00000009 +r 2340.08 # RP, RM +*Want "CLFDBR 9.5 M3 modes 6, 7" 0000000A 00000009 + +r 2350.10 # RZ, RP, RM, RFS +*Want "CLFDBR max FPC modes 1-3, 7" FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 2360.10 # RNTA, RFS, RNTE, RZ +*Want "CLFDBR max M3 modes 1, 3-5" FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 2370.08 # RP, RM +*Want "CLFDBR max M3 modes 6, 7" FFFFFFFF FFFFFFFF + +r 2380.10 # RZ, RP, RM, RFS +*Want "CLFDBR 0.75 FPC modes 1-3, 7" 00000000 00000001 00000000 00000001 +r 2390.10 # RNTA, RFS, RNTE, RZ +*Want "CLFDBR 0.75 M3 modes 1, 3-5" 00000001 00000001 00000001 00000000 +r 23A0.08 # RP, RM +*Want "CLFDBR 0.75 M3 modes 6, 7" 00000001 00000000 + +r 23B0.10 # RZ, RP, RM, RFS +*Want "CLFDBR 0.25 FPC modes 1-3, 7" 00000000 00000001 00000000 00000001 +r 23C0.10 # RNTA, RFS, RNTE, RZ +*Want "CLFDBR 0.25 M3 modes 1, 3-5" 00000000 00000001 00000000 00000000 +r 23D0.08 # RP, RM +*Want "CLFDBR 0.25 M3 modes 6, 7" 00000001 00000000 + + +# rounding mode tests - long BFP - FPCR contents with cc in last byte +*Compare +r 2600.10 +*Want "CLFDBR -1.5 FPC modes 1-3, 7 FPCR" 00800003 00800003 00800003 00800003 +r 2610.10 +*Want "CLFDBR -1.5 M3 modes 1, 3-5 FPCR" 00880003 00880003 00880003 00880003 +r 2620.08 +*Want "CLFDBR -1.5 M3 modes 6, 7 FPCR" 00880003 00880003 + +r 2630.10 +*Want "CLFDBR -0.5 FPC modes 1-3, 7 FPCR" 00000001 00000001 00800003 00800003 +r 2640.10 +*Want "CLFDBR -0.5 M3 modes 1, 3-5 FPCR" 00880003 00880003 00080001 00080001 +r 2650.08 +*Want "CLFDBR -0.5 M3 modes 6, 7 FPCR" 00080001 00880003 + +r 2660.10 +*Want "CLFDBR +0.5 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 2670.10 +*Want "CLFDBR +0.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 2680.08 +*Want "CLFDBR +0.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 2690.10 +*Want "CLFDBR +1.5 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 26A0.10 +*Want "CLFDBR +1.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 26B0.08 +*Want "CLFDBR +1.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 26C0.10 +*Want "CLFDBR +2.5 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 26D0.10 +*Want "CLFDBR +2.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 26E0.08 +*Want "CLFDBR +2.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 26F0.10 +*Want "CLFDBR +5.5 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 2700.10 +*Want "CLFDBR +5.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 2710.08 +*Want "CLFDBR +5.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 2720.10 +*Want "CLFDBR +9.5 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 2730.10 +*Want "CLFDBR +9.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 2740.08 +*Want "CLFDBR +9.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 2750.10 +*Want "CLFDBR max FPC modes 1-3, 7 FPCR" 00000002 00800003 00000002 00000002 +r 2760.10 +*Want "CLFDBR max M3 modes 1, 3-5 FPCR" 00880003 00080002 00880003 00080002 +r 2770.08 +*Want "CLFDBR max M3 modes 6, 7 FPCR" 00880003 00080002 + +r 2780.10 +*Want "CLFDBR +0.75 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 2790.10 +*Want "CLFDBR +0.75 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 27A0.08 +*Want "CLFDBR +0.75 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 27B0.10 +*Want "CLFDBR +0.25 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 27C0.10 +*Want "CLFDBR +0.25 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 27D0.08 +*Want "CLFDBR +0.25 M3 modes 6, 7 FPCR" 00080002 00080002 + + +# BFP extended inputs converted to uint-32 test results +*Compare +r 3000.10 +*Want "CLFXBR result pairs 1-2" 00000001 00000001 00000002 00000002 +r 3010.10 +*Want "CLFXBR result pairs 3-4" 00000004 00000004 00000000 00000000 +r 3020.10 +*Want "CLFXBR result pairs 5-6" 00000000 00000000 FFFFFFFF 00000000 +r 3030.10 +*Want "CLFXBR result pairs 7-8" FFFFFFFF FFFFFFFF 00000001 00000001 +r 3040.08 +*Want "CLFXBR result pair 9" 00000000 00000000 + +# BFP extended inputs converted to uint-32 FPCR contents, cc +*Compare +r 3100.10 +*Want "CLFXBR FPC pairs 1-2" 00000002 F8000002 00000002 F8000002 +r 3110.10 +*Want "CLFXBR FPC pairs 3-4" 00000002 F8000002 00880003 F8008000 +r 3120.10 +*Want "CLFXBR FPC pairs 5-6" 00880003 F8008000 00880003 F8008000 +r 3130.10 +*Want "CLFXBR FPC pairs 7-8" 00080002 F8000802 00080002 F8000C02 +r 3140.08 +*Want "CLFXBR FPC pair 9" 00080002 F8000802 + + +# rounding mode tests - extended BFP - results from rounding +*Compare +r 3200.10 # RZ, RP, RM, RFS +*Want "CLFXBR -1.5 FPC modes 1-3, 7" 00000000 00000000 00000000 00000000 +r 3210.10 # RNTA, RFS, RNTE, RZ +*Want "CLFXBR -1.5 M3 modes 1, 3-5" 00000000 00000000 00000000 00000000 +r 3220.08 # RP, RM +*Want "CLFXBR -1.5 M3 modes 6, 7" 00000000 00000000 + +r 3230.10 # RZ, RP, RM, RFS +*Want "CLFXBR -0.5 FPC modes 1-3, 7" 00000000 00000000 00000000 00000000 +r 3240.10 # RNTA, RFS, RNTE, RZ +*Want "CLFXBR -0.5 M3 modes 1, 3-5" 00000000 00000000 00000000 00000000 +r 3250.08 # RP, RM +*Want "CLFXBR -0.5 M3 modes 6, 7" 00000000 00000000 + +r 3260.10 # RZ, RP, RM, RFS +*Want "CLFXBR 0.5 FPC modes 1-3, 7" 00000000 00000001 00000000 00000001 +r 3270.10 # RNTA, RFS, RNTE, RZ +*Want "CLFXBR 0.5 M3 modes 1, 3-5" 00000001 00000001 00000000 00000000 +r 3280.08 # RP, RM +*Want "CLFXBR 0.5 M3 modes 6, 7" 00000001 00000000 + +r 3290.10 # RZ, RP, RM, RFS +*Want "CLFXBR 1.5 FPC modes 1-3, 7" 00000001 00000002 00000001 00000001 +r 32A0.10 # RNTA, RFS, RNTE, RZ +*Want "CLFXBR 1.5 M3 modes 1, 3-5" 00000002 00000001 00000002 00000001 +r 32B0.08 # RP, RM +*Want "CLFXBR 1.5 M3 modes 6, 7" 00000002 00000001 + +r 32C0.10 # RZ, RP, RM, RFS +*Want "CLFXBR 2.5 FPC modes 1-3, 7" 00000002 00000003 00000002 00000003 +r 32D0.10 # RNTA, RFS, RNTE, RZ +*Want "CLFXBR 2.5 M3 modes 1, 3-5" 00000003 00000003 00000002 00000002 +r 32E0.08 # RP, RM +*Want "CLFXBR 2.5 M3 modes 6, 7" 00000003 00000002 + +r 32F0.10 # RZ, RP, RM, RFS +*Want "CLFXBR 5.5 FPC modes 1-3, 7" 00000005 00000006 00000005 00000005 +r 3300.10 # RNTA, RFS, RNTE, RZ +*Want "CLFXBR 5.5 M3 modes 1, 3-5" 00000006 00000005 00000006 00000005 +r 3310.08 # RP, RM +*Want "CLFXBR 5.5 M3 modes 6, 7" 00000006 00000005 + +r 3320.10 # RZ, RP, RM, RFS +*Want "CLFXBR 9.5 FPC modes 1-3, 7" 00000009 0000000A 00000009 00000009 +r 3330.10 # RNTA, RFS, RNTE, RZ +*Want "CLFXBR 9.5 M3 modes 1, 3-5" 0000000A 00000009 0000000A 00000009 +r 3340.08 # RP, RM +*Want "CLFXBR 9.5 M3 modes 6, 7" 0000000A 00000009 + +r 3350.10 # RZ, RP, RM, RFS +*Want "CLFXBR max FPC modes 1-3, 7" FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 3360.10 # RNTA, RFS, RNTE, RZ +*Want "CLFXBR max M3 modes 1, 3-5" FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 3370.08 # RP, RM +*Want "CLFXBR max M3 modes 6, 7" FFFFFFFF FFFFFFFF + +r 3380.10 # RZ, RP, RM, RFS +*Want "CLFXBR 0.75 FPC modes 1-3, 7" 00000000 00000001 00000000 00000001 +r 3390.10 # RNTA, RFS, RNTE, RZ +*Want "CLFXBR 0.75 M3 modes 1, 3-5" 00000001 00000001 00000001 00000000 +r 33A0.08 # RP, RM +*Want "CLFXBR 0.75 M3 modes 6, 7" 00000001 00000000 + +r 33B0.10 # RZ, RP, RM, RFS +*Want "CLFXBR 0.25 FPC modes 1-3, 7" 00000000 00000001 00000000 00000001 +r 33C0.10 # RNTA, RFS, RNTE, RZ +*Want "CLFXBR 0.25 M3 modes 1, 3-5" 00000000 00000001 00000000 00000000 +r 33D0.08 # RP, RM +*Want "CLFXBR 0.25 M3 modes 6, 7" 00000001 00000000 + + +r 3600.10 +*Want "CLFXBR -1.5 FPC modes 1-3, 7 FPCR" 00800003 00800003 00800003 00800003 +r 3610.10 +*Want "CLFXBR -1.5 M3 modes 1, 3-5 FPCR" 00880003 00880003 00880003 00880003 +r 3620.08 +*Want "CLFXBR -1.5 M3 modes 6, 7 FPCR" 00880003 00880003 + +r 3630.10 +*Want "CLFXBR -0.5 FPC modes 1-3, 7 FPCR" 00000001 00000001 00800003 00800003 +r 3640.10 +*Want "CLFXBR -0.5 M3 modes 1, 3-5 FPCR" 00880003 00880003 00080001 00080001 +r 3650.08 +*Want "CLFXBR -0.5 M3 modes 6, 7 FPCR" 00080001 00880003 + +r 3660.10 +*Want "CLFXBR +0.5 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 3670.10 +*Want "CLFXBR +0.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 3680.08 +*Want "CLFXBR +0.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 3690.10 +*Want "CLFXBR +1.5 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 36A0.10 +*Want "CLFXBR +1.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 36B0.08 +*Want "CLFXBR +1.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 36C0.10 +*Want "CLFXBR +2.5 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 36D0.10 +*Want "CLFXBR +2.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 36E0.08 +*Want "CLFXBR +2.5 M3 modes 5-7" 00080002 00080002 + +r 36F0.10 +*Want "CLFXBR +5.5 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 3700.10 +*Want "CLFXBR +5.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 3710.08 +*Want "CLFXBR +5.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 3720.10 +*Want "CLFXBR +9.5 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 3730.10 +*Want "CLFXBR +9.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 3740.08 +*Want "CLFXBR +9.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 3750.10 +*Want "CLFXBR max FPC modes 1-3, 7 FPCR" 00000002 00800003 00000002 00000002 +r 3760.10 +*Want "CLFXBR max M3 modes 1, 3-5 FPCR" 00880003 00080002 00880003 00080002 +r 3770.08 +*Want "CLFXBR max M3 modes 6, 7 FPCR" 00880003 00080002 + +r 3780.10 +*Want "CLFXBR +0.75 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 3790.10 +*Want "CLFXBR +0.75 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 37A0.08 +*Want "CLFXBR +0.75 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 37B0.10 +*Want "CLFXBR +0.25 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 37C0.10 +*Want "CLFXBR +0.25 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 37D0.08 +*Want "CLFXBR +0.25 M3 modes 6, 7 FPCR" 00080002 00080002 + + + +*Done + diff --git a/tests/bfp-005-cvttolog64.asm b/tests/bfp-005-cvttolog64.asm new file mode 100644 index 000000000..2233d3e1d --- /dev/null +++ b/tests/bfp-005-cvttolog64.asm @@ -0,0 +1,941 @@ + TITLE 'bfp-005-cvttolog64.asm: Test IEEE Cvt To Logical (uint-64)' +*********************************************************************** +* +*Testcase IEEE CONVERT TO LOGICAL 64 +* Test case capability includes ieee exceptions trappable and +* otherwise. Test results, FPCR flags, DXC, and condition codes are +* saved for all tests. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* bfp-005-cvttolog64.asm +* +* This assembly-language source file is part of the +* Hercules Decimal Floating Point Validation Package +* by Stephen R. Orso +* +* Copyright 2016 by Stephen R Orso. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* +* 3. The name of the author may not be used to endorse or promote +* products derived from this software without specific prior written +* permission. +* +* DISCLAMER: THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* HOLDER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* Tests the following three conversion instructions +* CONVERT TO LOGICAL (short BFP to uint-64, RRF-e) +* CONVERT TO LOGICAL (long BFP to uint-64, RRF-e) +* CONVERT TO LOGICAL (extended BFP to uint-64, RRF-e) +* +* Test data is compiled into this program. The test script that runs +* this program can provide alternative test data through Hercules R +* commands. +* +* Test Case Order +* 1) Short BFP to uint-64 +* 2) Short BFP to uint-64 with all rounding modes +* 3) Long BFP uint-64 +* 3) Long BFP uint-64 with all rounding modes +* 4) Extended BFP to uint-64 +* 4) Extended BFP to uint-64 with all rounding modes +* +* Provided test data is: +* 1, 2, 4, -2, QNaN, SNaN, max uint-64 + 1 +* The last value will trigger inexact exceptions when converted +* to uint-64. +* The same values are provided in each of the three input formats +* except for the last input. This is rounded up to the nearest +* value that can be represented in the input format. Extended +* BFP is the only format with an exact representation. +* Extended BFP: 403F0000000000000000000000000000 => +* 18 446 744 073 709 551 616 (exact) +* Long BFP 43F0000000000001 => +* 18 446 744 073 709 555 712 +* Short BFP: 5F800001 => 18 446 746 272 732 807 168 +* Provided test data for rounding tests: +* -1.5, -0.5, +0.5, +1.5, +2.5, +5.5, +9.5, max uint-64 +* This data is taken from Table 9-11 on page 9-16 of SA22-7832-10. +* While the table illustrates LOAD FP INTEGER, the same results +* should be generated when creating a uint-32 or uint-64 integer +* from a floating point value. The last value, max uint-64, +* is rounded down (truncated) to the input format. Extended is +* the only format with an exact representation. +* Extended BFP: 403EFFFFFFFFFFFFFFFF000000000000 => +* 18 446 744 073 709 551 615.5 (exact) +* Long BFP 43EFFFFFFFFFFFFF => +* 18 446 744 073 709 549 568 +* Short BFP: 5F7FFFFF => 18 446 742 974 197 923 840 +* These values are used so that rounding mode determines whether +* the result fits in a uint-64. +* +* Also tests the following floating point support instructions +* LOAD (Short) +* LOAD (Long) +* LOAD FPC +* SET BFP ROUNDING MODE 2-bit +* SET BFP ROUNDING MODE 3-bit +* STORE (Short) +* STORE (Long) +* STORE FPC +* +*********************************************************************** + SPACE 2 + MACRO + PADCSECT &ENDLABL +.* +.* Macro to pad the CSECT to include result data areas if this test +.* program is not being assembled using asma. asma generates a core +.* image that is loaded by the loadcore command, and because the +.* core image is a binary stored in Github, it makes sense to make +.* this small effort to keep the core image small. +.* + AIF (D'&ENDLABL).GOODPAD + MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + MNOTE *,'No CSECT padding performed' + MEXIT +.* +.GOODPAD ANOP Label valid. See if we're on asma + AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + ORG &ENDLABL-1 Not ASMA. Pad CSECT + MEXIT +.* +.NOPAD ANOP + MNOTE *,'asma detected; no CSECT padding performed' + MEND +* +* Note: for compatibility with the z/CMS test rig, do not change +* or use R11, R14, or R15. Everything else is fair game. +* +BFPCVTTL START 0 +R0 EQU 0 Work register for cc extraction +R1 EQU 1 +R2 EQU 2 Holds count of test input values +R3 EQU 3 Points to next test input value(s) +R4 EQU 4 Rounding tests inner loop control +R5 EQU 5 Rounding tests outer loop control +R6 EQU 6 Rounding tests top of inner loop +R7 EQU 7 Pointer to next result value(s) +R8 EQU 8 Pointer to next FPCR result +R9 EQU 9 Rounding tests top of outer loop +R10 EQU 10 Pointer to test address list +R11 EQU 11 **Reserved for z/CMS test rig +R12 EQU 12 Holds number of test cases in set +R13 EQU 13 Mainline return address +R14 EQU 14 **Return address for z/CMS test rig +R15 EQU 15 **Base register on z/CMS or Hyperion +* +* Floating Point Register equates to keep the cross reference clean +* +FPR0 EQU 0 +FPR1 EQU 1 +FPR2 EQU 2 +FPR3 EQU 3 +FPR4 EQU 4 +FPR5 EQU 5 +FPR6 EQU 6 +FPR7 EQU 7 +FPR8 EQU 8 +FPR9 EQU 9 +FPR10 EQU 10 +FPR11 EQU 11 +FPR12 EQU 12 +FPR13 EQU 13 +FPR14 EQU 14 +FPR15 EQU 15 +* + USING *,R15 +* +* Above works on real iron (R15=0 after sysclear) +* and in z/CMS (R15 points to start of load module) +* + ORG BFPCVTTL+X'8E' Program check interrution code +PCINTCD DS H +* +PCOLDPSW EQU BFPCVTTL+X'150' z/Arch Program check old PSW +* + ORG BFPCVTTL+X'1A0' z/Arch Restart PSW + DC X'0000000180000000',AD(START) +* + ORG BFPCVTTL+X'1D0' z/Arch Program check old PSW + DC X'0000000000000000',AD(PROGCHK) +* +* Program check routine. If Data Exception, continue execution at +* the instruction following the program check. Otherwise, hard wait. +* No need to collect data. All interesting DXC stuff is captured +* in the FPCR. +* + ORG BFPCVTTL+X'200' +PROGCHK DS 0H Program check occured... + CLI PCINTCD+1,X'07' Data Exception? + JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) + LPSWE PCOLDPSW ..yes, resume program execution +PCNOTDTA DS 0H + LTR R14,R14 Return address provided? + BNZR R14 Yes, return to z/CMS test rig. + LPSWE HARDWAIT Not data exception, enter disabled wait + EJECT +*********************************************************************** +* +* Main program. Enable Advanced Floating Point, process test cases. +* +*********************************************************************** + SPACE 2 +START STCTL R0,R0,CTLR0 Store CR0 to enable AFP + OI CTLR0+1,X'04' Turn on AFP bit + LCTL R0,R0,CTLR0 Reload updated CR0 +* +* Short BFP Input testing +* + LA R10,SHORTS Point to short BFP test inputs + BAS R13,CLGEBR Convert values to uint-64 from short BFP + LA R10,RMSHORTS Point to inputs for rounding mode tests + BAS R13,CLGEBRA Convert using all rounding mode options +* +* Short BFP Input testing +* + LA R10,LONGS Point to long BFP test inputs + BAS R13,CLGDBR Convert values to uint-64 from long BFP + LA R10,RMLONGS Point to inputs for rounding mode tests + BAS R13,CLGDBRA Convert using all rounding mode options +* +* Short BFP Input testing +* + LA R10,EXTDS Point to extended BFP test inputs + BAS R13,CLGXBR Convert values to uint-64 from extended + LA R10,RMEXTDS Point to inputs for rounding mode tests + BAS R13,CLGXBRA Convert using all rounding mode options +* + LTR R14,R14 Return address provided? + BNZR R14 ..Yes, return to z/CMS test rig. + LPSWE WAITPSW All done +* + DS 0D Ensure correct alignment for psw +WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end +* +CTLR0 DS F +FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags +* +* Input values parameter list, four fullwords: +* 1) Count, +* 2) Address of inputs, +* 3) Address to place results, and +* 4) Address to place DXC/Flags/cc values. +* + ORG BFPCVTTL+X'300' +SHORTS DS 0F Inputs for short BFP testing + DC A(SBFPCT/4) + DC A(SBFPIN) + DC A(SINTOUT) + DC A(SINTFLGS) +* +LONGS DS 0F Inputs for long BFP testing + DC A(LBFPCT/8) + DC A(LBFPIN) + DC A(LINTOUT) + DC A(LINTFLGS) +* +EXTDS DS 0F Inputs for Extended BFP testing + DC A(XBFPCT/16) + DC A(XBFPIN) + DC A(XINTOUT) + DC A(XINTFLGS) +* +RMSHORTS DS 0F Inputs for short BFP rounding testing + DC A(SBFPRMCT/4) + DC A(SBFPINRM) + DC A(SINTRMO) + DC A(SINTRMOF) +* +RMLONGS DS 0F Inputs for long BFP rounding testing + DC A(LBFPRMCT/8) + DC A(LBFPINRM) + DC A(LINTRMO) + DC A(LINTRMOF) +* +RMEXTDS DS 0F Inputs for extd BFP rounding testing + DC A(XBFPRMCT/16) + DC A(XBFPINRM) + DC A(XINTRMO) + DC A(XINTRMOF) + EJECT +*********************************************************************** +* +* Convert short BFP to uint-64 format. A pair of results is generated +* for each input: one with all exceptions non-trappable, and the second +* with all exceptions trappable. The FPCR and condition code is +* stored for each result. Rounding mode RNTE, round to nearest, ties +* to even is used for each of these tests +* +*********************************************************************** + SPACE 2 +CLGEBR LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LE FPR0,0(,R3) Get short BFP test value + LFPC FPCREGNT Set exceptions non-trappable + CLGEBR R1,0,FPR0,0 Cvt float in FPR0 to uint-64 in GPR1 + STG R1,0(,R7) Store uint-64 result + STFPC 0*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(0*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGTR Set exceptions trappable + XGR R1,R1 Clear any residual result in R1 + SPM R1 Clear out any residual nz condition code + CLGEBR R1,0,FPR0,0 Cvt float in FPR0 to uint-64 in GPR1 + STG R1,8(,R7) Store short BFP result + STFPC 4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(1*4)+3(,R8) Save CC as low byte of FPCR +* + LA R3,4(,R3) Point to next input value + LA R7,2*8(,R7) Point to next uint-64 converted value pair + LA R8,2*4(,R8) Point to next FPCR/CC result pair + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert short BFP to integers using each possible rounding mode. +* Ten test results are generated for each input. A 48-byte test result +* section is used to keep results sets aligned on a quad-double word. +* +* The first four tests use rounding modes specified in the FPCR with +* the IEEE Inexact exception supressed. SRNM (2-bit) is used for +* the first two FPCR-controlled tests and SRNMB (3-bit) is used for +* the last two To get full coverage of that instruction pair. +* +* The next six results use instruction-specified rounding modes. +* +* The default rounding mode (0 for RNTE) is not tested in this +* section; prior tests used the default rounding mode. RNTE is tested +* explicitly as a rounding mode in this section. +* +*********************************************************************** + SPACE 2 +CLGEBRA LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LE FPR0,0(,R3) Get short BFP test value +* +* Test cases using rounding mode specified in the FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 1 SET FPC to RZ, towards zero. + CLGEBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked + STG R1,0*8(,R7) Store uint-64 result + STFPC 0*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(0*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 2 SET FPC to RP, to +infinity + CLGEBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked + STG R1,1*8(,R7) Store uint-64 result + STFPC 1*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(1*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 3 SET FPC to RM, to -infinity + CLGEBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked + STG R1,2*8(,R7) Store uint-64 result + STFPC 2*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(2*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 7 RFS, Prepare for Shorter Precision + CLGEBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked + STG R1,3*8(,R7) Store uint-64 result + STFPC 3*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(3*4)+3(,R8) Save CC as low byte of FPCR +* +* Test cases using rounding mode specified in the instruction M3 field +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLGEBR R1,1,FPR0,B'0000' RNTA, to nearest, ties away + STG R1,4*8(,R7) Store uint-64 result + STFPC 4*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(4*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLGEBR R1,3,FPR0,B'0000' RFS, prepare for shorter precision + STG R1,5*8(,R7) Store uint-64 result + STFPC 5*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(5*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLGEBR R1,4,FPR0,B'0000' RNTE, to nearest, ties to even + STG R1,6*8(,R7) Store uint-64 result + STFPC 6*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(6*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLGEBR R1,5,FPR0,B'0000' RZ, toward zero + STG R1,7*8(,R7) Store uint-64 result + STFPC 7*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(7*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLGEBR R1,6,FPR0,B'0000' RP, to +inf + STG R1,8*8(,R7) Store uint-64 result + STFPC 8*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(8*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLGEBR R1,7,FPR0,B'0000' RM, to -inf + STG R1,9*8(,R7) Store uint-64 result + STFPC 9*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(9*4)+3(,R8) Save CC as low byte of FPCR +* + LA R3,4(,R3) Point to next input value + LA R7,10*8(,R7) Point to next uint-64 result set + LA R8,12*4(,R8) Point to next FPCR/CC result set + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert long BFP inputs to uint-64. A pair of results is generated +* for each input: one with all exceptions non-trappable, and the second +* with all exceptions trappable. The FPCR and condition code is +* stored for each result. +* +*********************************************************************** + SPACE 2 +CLGDBR LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LD FPR0,0(,R3) Get long BFP test value + LFPC FPCREGNT Set exceptions non-trappable + CLGDBR R1,0,FPR0,0 Cvt float in FPR0 to uint-64 in GPR1 + STG R1,0(,R7) Store long BFP result + STFPC 0*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(0*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGTR Set exceptions trappable + XGR R1,R1 Clear any residual result in R1 + SPM R1 Clear out any residual nz condition code + CLGDBR R1,0,FPR0,0 Cvt float in FPR0 to uint-64 in GPR1 + STG R1,8(,R7) Store uint-64 result + STFPC 1*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(1*4)+3(,R8) Save CC as low byte of FPCR +* + LA R3,8(,R3) Point to next input value + LA R7,16(,R7) Point to next uint-64 result pair + LA R8,8(,R8) Point to next FPCR/CC result pair + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert long BFP to integers using each possible rounding mode. +* Ten test results are generated for each input. A 48-byte test result +* section is used to keep results sets aligned on a quad-double word. +* +* The first four tests use rounding modes specified in the FPCR with +* the IEEE Inexact exception supressed. SRNM (2-bit) is used for +* the first two FPCR-controlled tests and SRNMB (3-bit) is used for +* the last two To get full coverage of that instruction pair. +* +* The next six results use instruction-specified rounding modes. +* +* The default rounding mode (0 for RNTE) is not tested in this section; +* prior tests used the default rounding mode. RNTE is tested +* explicitly as a rounding mode in this section. +* +*********************************************************************** + SPACE 2 +CLGDBRA LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LD FPR0,0(,R3) Get long BFP test value +* +* Test cases using rounding mode specified in the FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 1 SET FPC to RZ, towards zero. + CLGDBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked + STG R1,0*8(,R7) Store uint-64 result + STFPC 0(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 2 SET FPC to RP, to +infinity + CLGDBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked + STG R1,1*8(,R7) Store uint-64 result + STFPC 1*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(1*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 3 SET FPC to RM, to -infinity + CLGDBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked + STG R1,2*8(,R7) Store uint-64 result + STFPC 2*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(2*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 7 RFS, Prepare for Shorter Precision + CLGDBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked + STG R1,3*8(,R7) Store uint-64 result + STFPC 3*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(3*4)+3(,R8) Save CC as low byte of FPCR +* +* Test cases using rounding mode specified in the instruction M3 field +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLGDBR R1,1,FPR0,B'0000' RNTA, to nearest, ties away from 0 + STG R1,4*8(,R7) Store uint-64 result + STFPC 4*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(4*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLGDBR R1,3,FPR0,B'0000' RFS, prepare for shorter precision + STG R1,5*8(,R7) Store uint-64 result + STFPC 5*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(5*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLGDBR R1,4,FPR0,B'0000' RNTE, to nearest, ties to even + STG R1,6*8(,R7) Store uint-64 result + STFPC 6*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(6*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLGDBR R1,5,FPR0,B'0000' RZ, toward zero + STG R1,7*8(,R7) Store uint-64 result + STFPC 7*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(7*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLGDBR R1,6,FPR0,B'0000' RP, to +inf + STG R1,8*8(,R7) Store uint-64 result + STFPC 8*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(8*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLGDBR R1,7,FPR0,B'0000' RM, to -inf + STG R1,9*8(,R7) Store uint-64 result + STFPC 9*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(9*4)+3(,R8) Save CC as low byte of FPCR +* + LA R3,8(,R3) Point to next input value + LA R7,10*8(,R7) Point to next uint-64 result set + LA R8,12*4(,R8) Point to next FPCR/CC result set + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert extended BFP to uint-64. A pair of results is generated +* for each input: one with all exceptions non-trappable, and the +* second with all exceptions trappable. The FPCR and condition code +* are stored for each result. +* +*********************************************************************** + SPACE 2 +CLGXBR LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LD FPR0,0(,R3) Get extended BFP test value part 1 + LD R2,8(,R3) Get extended BFP test value part 1 + LFPC FPCREGNT Set exceptions non-trappable + CLGXBR R1,0,FPR0,0 Cvt float in FPR0-FPR2 to uint-64 in GPR1 + STG R1,0(,R7) Store uint-64 result + STFPC (0*4)(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(0*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGTR Set exceptions trappable + XGR R1,R1 Clear any residual result in R1 + SPM R1 Clear out any residual nz condition code + CLGXBR R1,0,FPR0,0 Cvt float in FPR0-FPR2 to uint-64 in GPR1 + STG R1,8(,R7) Store uint-64 result + STFPC (1*4)(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(1*4)+3(,R8) Save CC as low byte of FPCR +* + LA R3,16(,R3) Point to next extended BFP input value + LA R7,16(,R7) Point to next uint-64 result pair + LA R8,8(,R8) Point to next FPCR/CC result pair + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert extended BFP to integers using each possible rounding mode. +* Ten test results are generated for each input. A 48-byte test result +* section is used to keep results sets aligned on a quad-double word. +* +* The first four tests use rounding modes specified in the FPCR with +* the IEEE Inexact exception supressed. SRNM (2-bit) is used for +* the first two FPCR-controlled tests and SRNMB (3-bit) is used for +* the last two To get full coverage of that instruction pair. +* +* The next six results use instruction-specified rounding modes. +* +* The default rounding mode (0 for RNTE) is not tested in this section; +* prior tests used the default rounding mode. RNTE is tested +* explicitly as a rounding mode in this section. +* +*********************************************************************** + SPACE 2 +CLGXBRA LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LD R0,0(,R3) Get extended BFP test value part 1 + LD R2,8(,R3) Get extended BFP test value part 2 +* +* Test cases using rounding mode specified in the FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 1 SET FPC to RZ, towards zero. + CLGXBR R1,0,R0,B'0100' FPCR ctl'd rounding, inexact masked + STG R1,0*8(,R7) Store uint-64 result + STFPC 0(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 2 SET FPC to RP, to +infinity + CLGXBR R1,0,R0,B'0100' FPCR ctl'd rounding, inexact masked + STG R1,1*8(,R7) Store uint-64 result + STFPC 1*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(1*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 3 SET FPC to RM, to -infinity + CLGXBR R1,0,R0,B'0100' FPCR ctl'd rounding, inexact masked + STG R1,2*8(,R7) Store uint-64 result + STFPC 2*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(2*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 7 RFS, Prepare for Shorter Precision + CLGXBR R1,0,R0,B'0100' FPCR ctl'd rounding, inexact masked + STG R1,3*8(,R7) Store uint-64 result + STFPC 3*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(3*4)+3(,R8) Save CC as low byte of FPCR +* +* Test cases using rounding mode specified in the instruction M3 field +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLGXBR R1,1,R0,B'0000' RNTA, to nearest, ties away from zero + STG R1,4*8(,R7) Store uint-64 result + STFPC 4*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(4*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLGXBR R1,3,R0,B'0000' RFS, to prepare for shorter precision + STG R1,5*8(,R7) Store uint-64 result + STFPC 5*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(5*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLGXBR R1,4,R0,B'0000' RNTE, to nearest, ties to even + STG R1,6*8(,R7) Store uint-64 result + STFPC 6*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(6*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLGXBR R1,5,R0,B'0000' RZ, toward zero + STG R1,7*8(,R7) Store uint-64 result + STFPC 7*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(7*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLGXBR R1,6,R0,B'0000' RP, to +inf + STG R1,8*8(,R7) Store uint-64 result + STFPC 8*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(8*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CLGXBR R1,7,R0,B'0000' RM, to -inf + STG R1,9*8(,R7) Store uint-64 result + STFPC 9*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(9*4)+3(,R8) Save CC as low byte of FPCR +* + LA R3,16(,R3) Point to next input value + LA R7,10*8(,R7) Point to next uint-64 result set + LA R8,12*4(,R8) Point to next FPCR/CC result pair + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* BFP inputs for Convert To Logical testing. The same set of values +* are used for short, long, and extended formats, with the exception +* of the last value, which is rounded to fit the input format and +* for the needs of the test (conversion or rounding). +* +*********************************************************************** + SPACE 2 +* +* Short integer inputs for Convert From Fixed testing. The same set of +* inputs are used for short, long, and extended formats. The last two +* values are used for rounding mode tests for short only; conversion of +* uint-64 to long or extended are always exact. +* +SBFPIN DS 0F Inputs for short BFP testing + DC X'3F800000' +1.0 + DC X'40000000' +2.0 + DC X'40800000' +4.0 + DC X'7F810000' SNaN + DC X'7FC10000' QNaN + DC X'5F800001' max uint-64 + 1 rounded up to short BFP +* 18 446 746 272 732 807 168 +* Note: above value rounds to max uint-64. + DC X'5F7FFFFF' max uint-64 rounded down to short BFP +* 18 446 742 974 197 923 840 + DC X'3F400000' +0.75 + DC X'3E800000' +0.25 +SBFPCT EQU *-SBFPIN Count of short BFP in list * 4 +* +* +SBFPINRM DS 0F Inputs for short BFP rounding testing +* +* The following values correspond to Figure 9-11 on page 9-16 of the +* z/Arch POP, SA22-7832-10 +* + DC X'BFC00000' -1.5 + DC X'BF000000' -0.5 + DC X'3F000000' +0.5 + DC X'3FC00000' +1.5 + DC X'40200000' +2.5 + DC X'40B00000' +5.5 + DC X'41180000' +9.5 +* +* The following values ensure correct rounding for values that +* are not ties. +* + DC X'5F7FFFFF' max uint-64 rounded down to short BFP +* 18 446 742 974 197 923 840 + DC X'3F400000' +0.75 + DC X'3E800000' +0.25 +SBFPRMCT EQU *-SBFPINRM Count of rounding mode test short BFP * 4 +* +* +LBFPIN DS 0F Inputs for long BFP testing + DC X'3FF0000000000000' +1.0 + DC X'4000000000000000' +2.0 + DC X'4010000000000000' +4.0 + DC X'7FF0100000000000' SNaN + DC X'7FF8100000000000' QNaN + DC X'43F0000000000000' max uint-64 + 1 rounded up +* 18 446 744 073 709 555 712 + DC X'43EFFFFFFFFFFFFF' max uint-64 rounded down +* 18 446 744 073 709 549 568 + DC X'3FE8000000000000' +0.75 + DC X'3FD0000000000000' +0.25 +LBFPCT EQU *-LBFPIN Count of long BFP in list * 8 +* +* +LBFPINRM DS 0F Inputs for long BFP rounding testing +* +* The following values correspond to Figure 9-11 on page 9-16 of the +* z/Arch POP, SA22-7832-10 +* + DC X'BFF8000000000000' -1.5 + DC X'BFE0000000000000' -0.5 + DC X'3FE0000000000000' +0.5 + DC X'3FF8000000000000' +1.5 + DC X'4004000000000000' +2.5 + DC X'4016000000000000' +5.5 + DC X'4023000000000000' +9.5 +* +* The following values ensure correct rounding for values that +* are not ties. +* + DC X'43EFFFFFFFFFFFFF' max uint-64 rounded down +* 18 446 744 073 709 549 568 +* DC X'3FE8000000000000' 0.75 + DC X'3FD0000000000000' +0.25 +LBFPRMCT EQU *-LBFPINRM Count of roundinf test long BFP * 8 +* +* +XBFPIN DS 0D Inputs for extended BFP testing + DC X'3FFF0000000000000000000000000000' +1.0 + DC X'40000000000000000000000000000000' +2.0 + DC X'40010000000000000000000000000000' +4.0 + DC X'7FFF0100000000000000000000000000' SNaN + DC X'7FFF8100000000000000000000000000' QNaN + DC X'403F0000000000000000000000000000' max uint-64 + 1 +* 18 446 744 073 709 551 616 (exact) + DC X'403EFFFFFFFFFFFFFFFE000000000000' max uint-64 +* 18 446 744 073 709 551 615 (exact) + DC X'403EFFFFFFFFFFFFFFFF000000000000' max uint-64+0.5 +* 18 446 744 073 709 551 615.5 +* Above is always inexact, and may overflow based on rounding mode + DC X'3FFE8000000000000000000000000000' 0.75 + DC X'3FFD0000000000000000000000000000' 0.25 +XBFPCT EQU *-XBFPIN Count of extended BFP in list * 16 +* +* +XBFPINRM DS 0D Inputs for extended BFP rounding testing +* +* The following values correspond to Figure 9-11 on page 9-16 of the +* z/Arch POP, SA22-7832-10 +* + DC X'BFFF8000000000000000000000000000' -1.5 + DC X'BFFE0000000000000000000000000000' -0.5 + DC X'3FFE0000000000000000000000000000' +0.5 + DC X'3FFF8000000000000000000000000000' +1.5 + DC X'40004000000000000000000000000000' +2.5 + DC X'40016000000000000000000000000000' +5.5 + DC X'40023000000000000000000000000000' +9.5 +* +* The following values ensure correct rounding for values that +* are not ties. +* + DC X'403EFFFFFFFFFFFFFFFF000000000000' max uint-64+0.5 +* 18 446 744 073 709 551 615.5 +* Above is always inexact, and may overflow based on rounding mode + DC X'3FFE8000000000000000000000000000' 0.75 + DC X'3FFD0000000000000000000000000000' 0.25 +XBFPRMCT EQU *-XBFPINRM Count of rounding test extd BFP * 16 +* +* Locations for results +* +SINTOUT EQU BFPCVTTL+X'1000' Uint-64 values from short BFP +* ..6 pairs used, room for 32 +SINTFLGS EQU BFPCVTTL+X'1200' FPC flags and DXC from short BFP +* ..6 pairs used, room for 32 +SINTRMO EQU BFPCVTTL+X'1300' Short rounding mode test results +* ..8 sets used, room for 16 +SINTRMOF EQU BFPCVTTL+X'1800' Short rounding mode FPCR contents +* ..8 sets used, room for 16 +* +LINTOUT EQU BFPCVTTL+X'2000' Uint-64 values from long BFP +* ..6 pairs used, room for 32 +LINTFLGS EQU BFPCVTTL+X'2200' FPC flags and DXC from long BFP +* ..6 pairs used, room for 32 +LINTRMO EQU BFPCVTTL+X'2300' Long rounding mode test results +* ..8 sets used, room for 16 +LINTRMOF EQU BFPCVTTL+X'2800' Long rounding mode FPCR contents +* ..8 sets used, room for 16 +* +XINTOUT EQU BFPCVTTL+X'3000' Uint-64 values from extd BFP +* ..6 pairs used, room for 32 +XINTFLGS EQU BFPCVTTL+X'3200' FPC flags and DXC from extd BFP +* ..6 pairs used, room for 32 +XINTRMO EQU BFPCVTTL+X'3300' Extended rounding mode test results +* ..8 sets used, room for 16 +XINTRMOF EQU BFPCVTTL+X'3800' Long rounding mode FPCR contents +* ..8 sets used, room for 16 +* +ENDLABL EQU BFPCVTTL+X'3B00' next available result location + PADCSECT ENDLABL pad to end of results if not ASMA + END diff --git a/tests/bfp-005-cvttolog64.core b/tests/bfp-005-cvttolog64.core new file mode 100644 index 000000000..8be1f94a0 Binary files /dev/null and b/tests/bfp-005-cvttolog64.core differ diff --git a/tests/bfp-005-cvttolog64.list b/tests/bfp-005-cvttolog64.list new file mode 100644 index 000000000..532baa1ee --- /dev/null +++ b/tests/bfp-005-cvttolog64.list @@ -0,0 +1,1128 @@ +ASMA Ver. 0.2.0 ieee-cvttolog64.asm: Test IEEE Convert To Logical (uint-64) 01 Sep 2016 10:11:28 Page 1 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 2 *********************************************************************** + 3 * + 4 *Testcase IEEE CONVERT TO LOGICAL 64 + 5 * Test case capability includes ieee exceptions trappable and + 6 * otherwise. Test results, FPCR flags, DXC, and condition codes are + 7 * saved for all tests. + 8 * + 9 *********************************************************************** + + + 11 *********************************************************************** + 12 * + 13 * Tests the following three conversion instructions + 14 * CONVERT TO LOGICAL (short BFP to uint-64, RRF-e) + 15 * CONVERT TO LOGICAL (long BFP to uint-64, RRF-e) + 16 * CONVERT TO LOGICAL (extended BFP to uint-64, RRF-e) + 17 * + 18 * Test data is compiled into this program. The test script that runs + 19 * this program can provide alternative test data through Hercules R + 20 * commands. + 21 * + 22 * Test Case Order + 23 * 1) Short BFP to uint-64 + 24 * 2) Short BFP to uint-64 with all rounding modes + 25 * 3) Long BFP uint-64 + 26 * 3) Long BFP uint-64 with all rounding modes + 27 * 4) Extended BFP to uint-64 + 28 * 4) Extended BFP to uint-64 with all rounding modes + 29 * + 30 * Provided test data is: + 31 * 1, 2, 4, -2, QNaN, SNaN, max uint-64 + 1 + 32 * The last value will trigger inexact exceptions when converted + 33 * to uint-64. + 34 * The same values are provided in each of the three input formats + 35 * except for the last input. This is rounded up to the nearest + 36 * value that can be represented in the input format. Extended + 37 * BFP is the only format with an exact representation. + 38 * Extended BFP: 403F0000000000000000000000000000 => + 39 * 18 446 744 073 709 551 616 (exact) + 40 * Long BFP 43F0000000000001 => + 41 * 18 446 744 073 709 555 712 + 42 * Short BFP: 5F800001 => 18 446 746 272 732 807 168 + 43 * Provided test data for rounding tests: + 44 * -1.5, -0.5, +0.5, +1.5, +2.5, +5.5, +9.5, max uint-64 + 45 * This data is taken from Table 9-11 on page 9-16 of SA22-7832-10. + 46 * While the table illustrates LOAD FP INTEGER, the same results + 47 * should be generated when creating a uint-32 or uint-64 integer + 48 * from a floating point value. The last value, max uint-64, + 49 * is rounded down (truncated) to the input format. Extended is + 50 * the only format with an exact representation. + 51 * Extended BFP: 403EFFFFFFFFFFFFFFFF000000000000 => + 52 * 18 446 744 073 709 551 615.5 (exact) + ASMA Ver. 0.2.0 ieee-cvttolog64.asm: Test IEEE Convert To Logical (uint-64) 01 Sep 2016 10:11:28 Page 2 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 53 * Long BFP 43EFFFFFFFFFFFFF => + 54 * 18 446 744 073 709 549 568 + 55 * Short BFP: 5F7FFFFF => 18 446 742 974 197 923 840 + 56 * These values are used so that rounding mode determines whether + 57 * the result fits in a uint-64. + 58 * + 59 * Also tests the following floating point support instructions + 60 * LOAD (Short) + 61 * LOAD (Long) + 62 * LOAD FPC + 63 * SET BFP ROUNDING MODE 2-bit + 64 * SET BFP ROUNDING MODE 3-bit + 65 * STORE (Short) + 66 * STORE (Long) + 67 * STORE FPC + 68 * + 69 *********************************************************************** + + + 71 MACRO + 72 PADCSECT &ENDLABL + 73 .* + 74 .* Macro to pad the CSECT to include result data areas if this test + 75 .* program is not being assembled using asma. asma generates a core + 76 .* image that is loaded by the loadcore command, and because the + 77 .* core image is a binary stored in Github, it makes sense to make + 78 .* this small effort to keep the core image small. + 79 .* + 80 AIF (D'&ENDLABL).GOODPAD + 81 MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + 82 MNOTE *,'No CSECT padding performed' + 83 MEXIT + 84 .* + 85 .GOODPAD ANOP Label valid. See if we're on asma + 86 AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + 87 ORG &ENDLABL-1 Not ASMA. Pad CSECT + 88 MEXIT + 89 .* + 90 .NOPAD ANOP + 91 MNOTE *,'asma detected; no CSECT padding performed' + 92 MEND + 93 * + 94 * Note: for compatibility with the z/CMS test rig, do not change + 95 * or use R11, R14, or R15. Everything else is fair game. + 96 * + 0000000000000000 0000000000000ACF 97 BFPCVTTL START 0 + 0000000000000000 0000000000000001 98 R0 EQU 0 Work register for cc extraction + 0000000000000001 0000000000000001 99 R1 EQU 1 + 0000000000000002 0000000000000001 100 R2 EQU 2 Holds count of test input values + 0000000000000003 0000000000000001 101 R3 EQU 3 Points to next test input value(s) + 0000000000000004 0000000000000001 102 R4 EQU 4 Rounding tests inner loop control + 0000000000000005 0000000000000001 103 R5 EQU 5 Rounding tests outer loop control + ASMA Ver. 0.2.0 ieee-cvttolog64.asm: Test IEEE Convert To Logical (uint-64) 01 Sep 2016 10:11:28 Page 3 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 0000000000000006 0000000000000001 104 R6 EQU 6 Rounding tests top of inner loop + 0000000000000007 0000000000000001 105 R7 EQU 7 Pointer to next result value(s) + 0000000000000008 0000000000000001 106 R8 EQU 8 Pointer to next FPCR result + 0000000000000009 0000000000000001 107 R9 EQU 9 Rounding tests top of outer loop + 000000000000000A 0000000000000001 108 R10 EQU 10 Pointer to test address list + 000000000000000B 0000000000000001 109 R11 EQU 11 **Reserved for z/CMS test rig + 000000000000000C 0000000000000001 110 R12 EQU 12 Holds number of test cases in set + 000000000000000D 0000000000000001 111 R13 EQU 13 Mainline return address + 000000000000000E 0000000000000001 112 R14 EQU 14 **Return address for z/CMS test rig + 000000000000000F 0000000000000001 113 R15 EQU 15 **Base register on z/CMS or Hyperion + 114 * + 115 * Floating Point Register equates to keep the cross reference clean + 116 * + 0000000000000000 0000000000000001 117 FPR0 EQU 0 + 0000000000000001 0000000000000001 118 FPR1 EQU 1 + 0000000000000002 0000000000000001 119 FPR2 EQU 2 + 0000000000000003 0000000000000001 120 FPR3 EQU 3 + 0000000000000004 0000000000000001 121 FPR4 EQU 4 + 0000000000000005 0000000000000001 122 FPR5 EQU 5 + 0000000000000006 0000000000000001 123 FPR6 EQU 6 + 0000000000000007 0000000000000001 124 FPR7 EQU 7 + 0000000000000008 0000000000000001 125 FPR8 EQU 8 + 0000000000000009 0000000000000001 126 FPR9 EQU 9 + 000000000000000A 0000000000000001 127 FPR10 EQU 10 + 000000000000000B 0000000000000001 128 FPR11 EQU 11 + 000000000000000C 0000000000000001 129 FPR12 EQU 12 + 000000000000000D 0000000000000001 130 FPR13 EQU 13 + 000000000000000E 0000000000000001 131 FPR14 EQU 14 + 000000000000000F 0000000000000001 132 FPR15 EQU 15 + 133 * +0000000000000000 0000000000000000 134 USING *,R15 + 135 * + 136 * Above works on real iron (R15=0 after sysclear) + 137 * and in z/CMS (R15 points to start of load module) + 138 * +0000000000000000 0000000000000000 000000000000008E 139 ORG BFPCVTTL+X'8E' Program check interrution code +000000000000008E 0000 140 PCINTCD DS H + 141 * + 0000000000000150 0000000000000000 142 PCOLDPSW EQU BFPCVTTL+X'150' z/Arch Program check old PSW + 143 * +0000000000000090 0000000000000090 00000000000001A0 144 ORG BFPCVTTL+X'1A0' z/Arch Restart PSW +00000000000001A0 00000001 80000000 145 DC X'0000000180000000',AD(START) + 146 * +00000000000001B0 00000000000001B0 00000000000001D0 147 ORG BFPCVTTL+X'1D0' z/Arch Program check old PSW +00000000000001D0 00000000 00000000 148 DC X'0000000000000000',AD(PROGCHK) + 149 * + 150 * Program check routine. If Data Exception, continue execution at + 151 * the instruction following the program check. Otherwise, hard wait. + 152 * No need to collect data. All interesting DXC stuff is captured + 153 * in the FPCR. + 154 * +00000000000001E0 00000000000001E0 0000000000000200 155 ORG BFPCVTTL+X'200' + ASMA Ver. 0.2.0 ieee-cvttolog64.asm: Test IEEE Convert To Logical (uint-64) 01 Sep 2016 10:11:28 Page 4 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000200 156 PROGCHK DS 0H Program check occured... +0000000000000200 9507 F08F 000000000000008F 157 CLI PCINTCD+1,X'07' Data Exception? +0000000000000204 A774 0004 000000000000020C 158 JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) +0000000000000208 B2B2 F150 0000000000000150 159 LPSWE PCOLDPSW ..yes, resume program execution +000000000000020C 160 PCNOTDTA DS 0H +000000000000020C 12EE 161 LTR R14,R14 Return address provided? +000000000000020E 077E 162 BNZR R14 Yes, return to z/CMS test rig. +0000000000000210 B2B2 F268 0000000000000268 163 LPSWE HARDWAIT Not data exception, enter disabled wait + ASMA Ver. 0.2.0 ieee-cvttolog64.asm: Test IEEE Convert To Logical (uint-64) 01 Sep 2016 10:11:28 Page 5 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 165 *********************************************************************** + 166 * + 167 * Main program. Enable Advanced Floating Point, process test cases. + 168 * + 169 *********************************************************************** + + +0000000000000214 B600 F278 0000000000000278 171 START STCTL R0,R0,CTLR0 Store CR0 to enable AFP +0000000000000218 9604 F279 0000000000000279 172 OI CTLR0+1,X'04' Turn on AFP bit +000000000000021C B700 F278 0000000000000278 173 LCTL R0,R0,CTLR0 Reload updated CR0 + 174 * + 175 * Short BFP Input testing + 176 * +0000000000000220 41A0 F300 0000000000000300 177 LA R10,SHORTS Point to short BFP test inputs +0000000000000224 4DD0 F360 0000000000000360 178 BAS R13,CLGEBR Convert values to uint-64 from short BFP +0000000000000228 41A0 F330 0000000000000330 179 LA R10,RMSHORTS Point to inputs for rounding mode tests +000000000000022C 4DD0 F3C4 00000000000003C4 180 BAS R13,CLGEBRA Convert using all rounding mode options + 181 * + 182 * Short BFP Input testing + 183 * +0000000000000230 41A0 F310 0000000000000310 184 LA R10,LONGS Point to long BFP test inputs +0000000000000234 4DD0 F522 0000000000000522 185 BAS R13,CLGDBR Convert values to uint-64 from long BFP +0000000000000238 41A0 F340 0000000000000340 186 LA R10,RMLONGS Point to inputs for rounding mode tests +000000000000023C 4DD0 F586 0000000000000586 187 BAS R13,CLGDBRA Convert using all rounding mode options + 188 * + 189 * Short BFP Input testing + 190 * +0000000000000240 41A0 F320 0000000000000320 191 LA R10,EXTDS Point to extended BFP test inputs +0000000000000244 4DD0 F6E4 00000000000006E4 192 BAS R13,CLGXBR Convert values to uint-64 from extended +0000000000000248 41A0 F350 0000000000000350 193 LA R10,RMEXTDS Point to inputs for rounding mode tests +000000000000024C 4DD0 F74C 000000000000074C 194 BAS R13,CLGXBRA Convert using all rounding mode options + 195 * +0000000000000250 12EE 196 LTR R14,R14 Return address provided? +0000000000000252 077E 197 BNZR R14 ..Yes, return to z/CMS test rig. +0000000000000254 B2B2 F258 0000000000000258 198 LPSWE WAITPSW All done + 199 * +0000000000000258 200 DS 0D Ensure correct alignment for psw +0000000000000258 00020000 00000000 201 WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +0000000000000268 00020000 00000000 202 HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end + 203 * +0000000000000278 00000000 204 CTLR0 DS F +000000000000027C 00000000 205 FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +0000000000000280 F8000000 206 FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags + 207 * + 208 * Input values parameter list, four fullwords: + 209 * 1) Count, + 210 * 2) Address of inputs, + 211 * 3) Address to place results, and + 212 * 4) Address to place DXC/Flags/cc values. + 213 * +0000000000000284 0000000000000284 0000000000000300 214 ORG BFPCVTTL+X'300' +0000000000000300 215 SHORTS DS 0F Inputs for short BFP testing + ASMA Ver. 0.2.0 ieee-cvttolog64.asm: Test IEEE Convert To Logical (uint-64) 01 Sep 2016 10:11:28 Page 6 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000300 00000009 216 DC A(SBFPCT/4) +0000000000000304 000008B0 217 DC A(SBFPIN) +0000000000000308 00001000 218 DC A(SINTOUT) +000000000000030C 00001200 219 DC A(SINTFLGS) + 220 * +0000000000000310 221 LONGS DS 0F Inputs for long BFP testing +0000000000000310 00000009 222 DC A(LBFPCT/8) +0000000000000314 000008FC 223 DC A(LBFPIN) +0000000000000318 00002000 224 DC A(LINTOUT) +000000000000031C 00002200 225 DC A(LINTFLGS) + 226 * +0000000000000320 227 EXTDS DS 0F Inputs for Extended BFP testing +0000000000000320 0000000A 228 DC A(XBFPCT/16) +0000000000000324 00000990 229 DC A(XBFPIN) +0000000000000328 00003000 230 DC A(XINTOUT) +000000000000032C 00003200 231 DC A(XINTFLGS) + 232 * +0000000000000330 233 RMSHORTS DS 0F Inputs for short BFP rounding testing +0000000000000330 0000000A 234 DC A(SBFPRMCT/4) +0000000000000334 000008D4 235 DC A(SBFPINRM) +0000000000000338 00001300 236 DC A(SINTRMO) +000000000000033C 00001800 237 DC A(SINTRMOF) + 238 * +0000000000000340 239 RMLONGS DS 0F Inputs for long BFP rounding testing +0000000000000340 00000009 240 DC A(LBFPRMCT/8) +0000000000000344 00000944 241 DC A(LBFPINRM) +0000000000000348 00002300 242 DC A(LINTRMO) +000000000000034C 00002800 243 DC A(LINTRMOF) + 244 * +0000000000000350 245 RMEXTDS DS 0F Inputs for extd BFP rounding testing +0000000000000350 0000000A 246 DC A(XBFPRMCT/16) +0000000000000354 00000A30 247 DC A(XBFPINRM) +0000000000000358 00003300 248 DC A(XINTRMO) +000000000000035C 00003800 249 DC A(XINTRMOF) + ASMA Ver. 0.2.0 ieee-cvttolog64.asm: Test IEEE Convert To Logical (uint-64) 01 Sep 2016 10:11:28 Page 7 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 251 *********************************************************************** + 252 * + 253 * Convert short BFP to uint-64 format. A pair of results is generated + 254 * for each input: one with all exceptions non-trappable, and the second + 255 * with all exceptions trappable. The FPCR and condition code is + 256 * stored for each result. Rounding mode RNTE, round to nearest, ties + 257 * to even is used for each of these tests + 258 * + 259 *********************************************************************** + + +0000000000000360 9823 A000 0000000000000000 261 CLGEBR LM R2,R3,0(R10) Get count and address of test input values +0000000000000364 9878 A008 0000000000000008 262 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000368 1222 263 LTR R2,R2 Any test cases? +000000000000036A 078D 264 BZR R13 ..No, return to caller +000000000000036C 0DC0 265 BASR R12,0 Set top of loop + 266 * +000000000000036E 7800 3000 0000000000000000 267 LE FPR0,0(,R3) Get short BFP test value +0000000000000372 B29D F27C 000000000000027C 268 LFPC FPCREGNT Set exceptions non-trappable +0000000000000376 B3AC 0010 269 CLGEBR R1,0,FPR0,0 Cvt float in FPR0 to uint-64 in GPR1 +000000000000037A E310 7000 0024 0000000000000000 270 STG R1,0(,R7) Store uint-64 result +0000000000000380 B29C 8000 0000000000000000 271 STFPC 0*4(R8) Store resulting FPC flags and DXC +0000000000000384 B222 0010 272 IPM R1 Get condition code and program mask +0000000000000388 8810 001C 000000000000001C 273 SRL R1,28 Isolate CC in low order byte +000000000000038C 4210 8003 0000000000000003 274 STC R1,(0*4)+3(,R8) Save CC as low byte of FPCR + 275 * +0000000000000390 B29D F280 0000000000000280 276 LFPC FPCREGTR Set exceptions trappable +0000000000000394 B982 0011 277 XGR R1,R1 Clear any residual result in R1 +0000000000000398 0410 278 SPM R1 Clear out any residual nz condition code +000000000000039A B3AC 0010 279 CLGEBR R1,0,FPR0,0 Cvt float in FPR0 to uint-64 in GPR1 +000000000000039E E310 7008 0024 0000000000000008 280 STG R1,8(,R7) Store short BFP result +00000000000003A4 B29C 8004 0000000000000004 281 STFPC 4(R8) Store resulting FPC flags and DXC +00000000000003A8 B222 0010 282 IPM R1 Get condition code and program mask +00000000000003AC 8810 001C 000000000000001C 283 SRL R1,28 Isolate CC in low order byte +00000000000003B0 4210 8007 0000000000000007 284 STC R1,(1*4)+3(,R8) Save CC as low byte of FPCR + 285 * +00000000000003B4 4130 3004 0000000000000004 286 LA R3,4(,R3) Point to next input value +00000000000003B8 4170 7010 0000000000000010 287 LA R7,2*8(,R7) Point to next uint-64 converted value pair +00000000000003BC 4180 8008 0000000000000008 288 LA R8,2*4(,R8) Point to next FPCR/CC result pair +00000000000003C0 062C 289 BCTR R2,R12 Convert next input value. +00000000000003C2 07FD 290 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvttolog64.asm: Test IEEE Convert To Logical (uint-64) 01 Sep 2016 10:11:28 Page 8 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 292 *********************************************************************** + 293 * + 294 * Convert short BFP to integers using each possible rounding mode. + 295 * Ten test results are generated for each input. A 48-byte test result + 296 * section is used to keep results sets aligned on a quad-double word. + 297 * + 298 * The first four tests use rounding modes specified in the FPCR with + 299 * the IEEE Inexact exception supressed. SRNM (2-bit) is used for + 300 * the first two FPCR-controlled tests and SRNMB (3-bit) is used for + 301 * the last two To get full coverage of that instruction pair. + 302 * + 303 * The next six results use instruction-specified rounding modes. + 304 * + 305 * The default rounding mode (0 for RNTE) is not tested in this + 306 * section; prior tests used the default rounding mode. RNTE is tested + 307 * explicitly as a rounding mode in this section. + 308 * + 309 *********************************************************************** + + +00000000000003C4 9823 A000 0000000000000000 311 CLGEBRA LM R2,R3,0(R10) Get count and address of test input values +00000000000003C8 9878 A008 0000000000000008 312 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000003CC 1222 313 LTR R2,R2 Any test cases? +00000000000003CE 078D 314 BZR R13 ..No, return to caller +00000000000003D0 0DC0 315 BASR R12,0 Set top of loop + 316 * +00000000000003D2 7800 3000 0000000000000000 317 LE FPR0,0(,R3) Get short BFP test value + 318 * + 319 * Test cases using rounding mode specified in the FPCR + 320 * +00000000000003D6 B29D F27C 000000000000027C 321 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000003DA B299 0001 0000000000000001 322 SRNM 1 SET FPC to RZ, towards zero. +00000000000003DE B3AC 0410 323 CLGEBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked +00000000000003E2 E310 7000 0024 0000000000000000 324 STG R1,0*8(,R7) Store uint-64 result +00000000000003E8 B29C 8000 0000000000000000 325 STFPC 0*4(R8) Store resulting FPC flags and DXC +00000000000003EC B222 0010 326 IPM R1 Get condition code and program mask +00000000000003F0 8810 001C 000000000000001C 327 SRL R1,28 Isolate CC in low order byte +00000000000003F4 4210 8003 0000000000000003 328 STC R1,(0*4)+3(,R8) Save CC as low byte of FPCR + 329 * +00000000000003F8 B29D F27C 000000000000027C 330 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000003FC B299 0002 0000000000000002 331 SRNM 2 SET FPC to RP, to +infinity +0000000000000400 B3AC 0410 332 CLGEBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked +0000000000000404 E310 7008 0024 0000000000000008 333 STG R1,1*8(,R7) Store uint-64 result +000000000000040A B29C 8004 0000000000000004 334 STFPC 1*4(R8) Store resulting FPC flags and DXC +000000000000040E B222 0010 335 IPM R1 Get condition code and program mask +0000000000000412 8810 001C 000000000000001C 336 SRL R1,28 Isolate CC in low order byte +0000000000000416 4210 8007 0000000000000007 337 STC R1,(1*4)+3(,R8) Save CC as low byte of FPCR + 338 * +000000000000041A B29D F27C 000000000000027C 339 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000041E B2B8 0003 0000000000000003 340 SRNMB 3 SET FPC to RM, to -infinity +0000000000000422 B3AC 0410 341 CLGEBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked +0000000000000426 E310 7010 0024 0000000000000010 342 STG R1,2*8(,R7) Store uint-64 result + ASMA Ver. 0.2.0 ieee-cvttolog64.asm: Test IEEE Convert To Logical (uint-64) 01 Sep 2016 10:11:28 Page 9 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +000000000000042C B29C 8008 0000000000000008 343 STFPC 2*4(R8) Store resulting FPC flags and DXC +0000000000000430 B222 0010 344 IPM R1 Get condition code and program mask +0000000000000434 8810 001C 000000000000001C 345 SRL R1,28 Isolate CC in low order byte +0000000000000438 4210 800B 000000000000000B 346 STC R1,(2*4)+3(,R8) Save CC as low byte of FPCR + 347 * +000000000000043C B29D F27C 000000000000027C 348 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000440 B2B8 0007 0000000000000007 349 SRNMB 7 RFS, Prepare for Shorter Precision +0000000000000444 B3AC 0410 350 CLGEBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked +0000000000000448 E310 7018 0024 0000000000000018 351 STG R1,3*8(,R7) Store uint-64 result +000000000000044E B29C 800C 000000000000000C 352 STFPC 3*4(R8) Store resulting FPC flags and DXC +0000000000000452 B222 0010 353 IPM R1 Get condition code and program mask +0000000000000456 8810 001C 000000000000001C 354 SRL R1,28 Isolate CC in low order byte +000000000000045A 4210 800F 000000000000000F 355 STC R1,(3*4)+3(,R8) Save CC as low byte of FPCR + 356 * + 357 * Test cases using rounding mode specified in the instruction M3 field + 358 * +000000000000045E B29D F27C 000000000000027C 359 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000462 B3AC 1010 360 CLGEBR R1,1,FPR0,B'0000' RNTA, to nearest, ties away +0000000000000466 E310 7020 0024 0000000000000020 361 STG R1,4*8(,R7) Store uint-64 result +000000000000046C B29C 8010 0000000000000010 362 STFPC 4*4(R8) Store resulting FPC flags and DXC +0000000000000470 B222 0010 363 IPM R1 Get condition code and program mask +0000000000000474 8810 001C 000000000000001C 364 SRL R1,28 Isolate CC in low order byte +0000000000000478 4210 8013 0000000000000013 365 STC R1,(4*4)+3(,R8) Save CC as low byte of FPCR + 366 * +000000000000047C B29D F27C 000000000000027C 367 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000480 B3AC 3010 368 CLGEBR R1,3,FPR0,B'0000' RFS, prepare for shorter precision +0000000000000484 E310 7028 0024 0000000000000028 369 STG R1,5*8(,R7) Store uint-64 result +000000000000048A B29C 8014 0000000000000014 370 STFPC 5*4(R8) Store resulting FPC flags and DXC +000000000000048E B222 0010 371 IPM R1 Get condition code and program mask +0000000000000492 8810 001C 000000000000001C 372 SRL R1,28 Isolate CC in low order byte +0000000000000496 4210 8017 0000000000000017 373 STC R1,(5*4)+3(,R8) Save CC as low byte of FPCR + 374 * +000000000000049A B29D F27C 000000000000027C 375 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000049E B3AC 4010 376 CLGEBR R1,4,FPR0,B'0000' RNTE, to nearest, ties to even +00000000000004A2 E310 7030 0024 0000000000000030 377 STG R1,6*8(,R7) Store uint-64 result +00000000000004A8 B29C 8018 0000000000000018 378 STFPC 6*4(R8) Store resulting FPC flags and DXC +00000000000004AC B222 0010 379 IPM R1 Get condition code and program mask +00000000000004B0 8810 001C 000000000000001C 380 SRL R1,28 Isolate CC in low order byte +00000000000004B4 4210 801B 000000000000001B 381 STC R1,(6*4)+3(,R8) Save CC as low byte of FPCR + 382 * +00000000000004B8 B29D F27C 000000000000027C 383 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000004BC B3AC 5010 384 CLGEBR R1,5,FPR0,B'0000' RZ, toward zero +00000000000004C0 E310 7038 0024 0000000000000038 385 STG R1,7*8(,R7) Store uint-64 result +00000000000004C6 B29C 801C 000000000000001C 386 STFPC 7*4(R8) Store resulting FPC flags and DXC +00000000000004CA B222 0010 387 IPM R1 Get condition code and program mask +00000000000004CE 8810 001C 000000000000001C 388 SRL R1,28 Isolate CC in low order byte +00000000000004D2 4210 801F 000000000000001F 389 STC R1,(7*4)+3(,R8) Save CC as low byte of FPCR + 390 * +00000000000004D6 B29D F27C 000000000000027C 391 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000004DA B3AC 6010 392 CLGEBR R1,6,FPR0,B'0000' RP, to +inf +00000000000004DE E310 7040 0024 0000000000000040 393 STG R1,8*8(,R7) Store uint-64 result +00000000000004E4 B29C 8020 0000000000000020 394 STFPC 8*4(R8) Store resulting FPC flags and DXC + ASMA Ver. 0.2.0 ieee-cvttolog64.asm: Test IEEE Convert To Logical (uint-64) 01 Sep 2016 10:11:28 Page 10 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000004E8 B222 0010 395 IPM R1 Get condition code and program mask +00000000000004EC 8810 001C 000000000000001C 396 SRL R1,28 Isolate CC in low order byte +00000000000004F0 4210 8023 0000000000000023 397 STC R1,(8*4)+3(,R8) Save CC as low byte of FPCR + 398 * +00000000000004F4 B29D F27C 000000000000027C 399 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000004F8 B3AC 7010 400 CLGEBR R1,7,FPR0,B'0000' RM, to -inf +00000000000004FC E310 7048 0024 0000000000000048 401 STG R1,9*8(,R7) Store uint-64 result +0000000000000502 B29C 8024 0000000000000024 402 STFPC 9*4(R8) Store resulting FPC flags and DXC +0000000000000506 B222 0010 403 IPM R1 Get condition code and program mask +000000000000050A 8810 001C 000000000000001C 404 SRL R1,28 Isolate CC in low order byte +000000000000050E 4210 8027 0000000000000027 405 STC R1,(9*4)+3(,R8) Save CC as low byte of FPCR + 406 * +0000000000000512 4130 3004 0000000000000004 407 LA R3,4(,R3) Point to next input value +0000000000000516 4170 7050 0000000000000050 408 LA R7,10*8(,R7) Point to next uint-64 result set +000000000000051A 4180 8030 0000000000000030 409 LA R8,12*4(,R8) Point to next FPCR/CC result set +000000000000051E 062C 410 BCTR R2,R12 Convert next input value. +0000000000000520 07FD 411 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvttolog64.asm: Test IEEE Convert To Logical (uint-64) 01 Sep 2016 10:11:28 Page 11 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 413 *********************************************************************** + 414 * + 415 * Convert long BFP inputs to uint-64. A pair of results is generated + 416 * for each input: one with all exceptions non-trappable, and the second + 417 * with all exceptions trappable. The FPCR and condition code is + 418 * stored for each result. + 419 * + 420 *********************************************************************** + + +0000000000000522 9823 A000 0000000000000000 422 CLGDBR LM R2,R3,0(R10) Get count and address of test input values +0000000000000526 9878 A008 0000000000000008 423 LM R7,R8,8(R10) Get address of result area and flag area. +000000000000052A 1222 424 LTR R2,R2 Any test cases? +000000000000052C 078D 425 BZR R13 ..No, return to caller +000000000000052E 0DC0 426 BASR R12,0 Set top of loop + 427 * +0000000000000530 6800 3000 0000000000000000 428 LD FPR0,0(,R3) Get long BFP test value +0000000000000534 B29D F27C 000000000000027C 429 LFPC FPCREGNT Set exceptions non-trappable +0000000000000538 B3AD 0010 430 CLGDBR R1,0,FPR0,0 Cvt float in FPR0 to uint-64 in GPR1 +000000000000053C E310 7000 0024 0000000000000000 431 STG R1,0(,R7) Store long BFP result +0000000000000542 B29C 8000 0000000000000000 432 STFPC 0*4(R8) Store resulting FPC flags and DXC +0000000000000546 B222 0010 433 IPM R1 Get condition code and program mask +000000000000054A 8810 001C 000000000000001C 434 SRL R1,28 Isolate CC in low order byte +000000000000054E 4210 8003 0000000000000003 435 STC R1,(0*4)+3(,R8) Save CC as low byte of FPCR + 436 * +0000000000000552 B29D F280 0000000000000280 437 LFPC FPCREGTR Set exceptions trappable +0000000000000556 B982 0011 438 XGR R1,R1 Clear any residual result in R1 +000000000000055A 0410 439 SPM R1 Clear out any residual nz condition code +000000000000055C B3AD 0010 440 CLGDBR R1,0,FPR0,0 Cvt float in FPR0 to uint-64 in GPR1 +0000000000000560 E310 7008 0024 0000000000000008 441 STG R1,8(,R7) Store uint-64 result +0000000000000566 B29C 8004 0000000000000004 442 STFPC 1*4(R8) Store resulting FPC flags and DXC +000000000000056A B222 0010 443 IPM R1 Get condition code and program mask +000000000000056E 8810 001C 000000000000001C 444 SRL R1,28 Isolate CC in low order byte +0000000000000572 4210 8007 0000000000000007 445 STC R1,(1*4)+3(,R8) Save CC as low byte of FPCR + 446 * +0000000000000576 4130 3008 0000000000000008 447 LA R3,8(,R3) Point to next input value +000000000000057A 4170 7010 0000000000000010 448 LA R7,16(,R7) Point to next uint-64 result pair +000000000000057E 4180 8008 0000000000000008 449 LA R8,8(,R8) Point to next FPCR/CC result pair +0000000000000582 062C 450 BCTR R2,R12 Convert next input value. +0000000000000584 07FD 451 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvttolog64.asm: Test IEEE Convert To Logical (uint-64) 01 Sep 2016 10:11:28 Page 12 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 453 *********************************************************************** + 454 * + 455 * Convert long BFP to integers using each possible rounding mode. + 456 * Ten test results are generated for each input. A 48-byte test result + 457 * section is used to keep results sets aligned on a quad-double word. + 458 * + 459 * The first four tests use rounding modes specified in the FPCR with + 460 * the IEEE Inexact exception supressed. SRNM (2-bit) is used for + 461 * the first two FPCR-controlled tests and SRNMB (3-bit) is used for + 462 * the last two To get full coverage of that instruction pair. + 463 * + 464 * The next six results use instruction-specified rounding modes. + 465 * + 466 * The default rounding mode (0 for RNTE) is not tested in this section; + 467 * prior tests used the default rounding mode. RNTE is tested + 468 * explicitly as a rounding mode in this section. + 469 * + 470 *********************************************************************** + + +0000000000000586 9823 A000 0000000000000000 472 CLGDBRA LM R2,R3,0(R10) Get count and address of test input values +000000000000058A 9878 A008 0000000000000008 473 LM R7,R8,8(R10) Get address of result area and flag area. +000000000000058E 1222 474 LTR R2,R2 Any test cases? +0000000000000590 078D 475 BZR R13 ..No, return to caller +0000000000000592 0DC0 476 BASR R12,0 Set top of loop + 477 * +0000000000000594 6800 3000 0000000000000000 478 LD FPR0,0(,R3) Get long BFP test value + 479 * + 480 * Test cases using rounding mode specified in the FPCR + 481 * +0000000000000598 B29D F27C 000000000000027C 482 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000059C B299 0001 0000000000000001 483 SRNM 1 SET FPC to RZ, towards zero. +00000000000005A0 B3AD 0410 484 CLGDBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked +00000000000005A4 E310 7000 0024 0000000000000000 485 STG R1,0*8(,R7) Store uint-64 result +00000000000005AA B29C 8000 0000000000000000 486 STFPC 0(R8) Store resulting FPC flags and DXC +00000000000005AE B222 0010 487 IPM R1 Get condition code and program mask +00000000000005B2 8810 001C 000000000000001C 488 SRL R1,28 Isolate CC in low order byte +00000000000005B6 4210 8003 0000000000000003 489 STC R1,3(,R8) Save CC as low byte of FPCR + 490 * +00000000000005BA B29D F27C 000000000000027C 491 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000005BE B299 0002 0000000000000002 492 SRNM 2 SET FPC to RP, to +infinity +00000000000005C2 B3AD 0410 493 CLGDBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked +00000000000005C6 E310 7008 0024 0000000000000008 494 STG R1,1*8(,R7) Store uint-64 result +00000000000005CC B29C 8004 0000000000000004 495 STFPC 1*4(R8) Store resulting FPC flags and DXC +00000000000005D0 B222 0010 496 IPM R1 Get condition code and program mask +00000000000005D4 8810 001C 000000000000001C 497 SRL R1,28 Isolate CC in low order byte +00000000000005D8 4210 8007 0000000000000007 498 STC R1,(1*4)+3(,R8) Save CC as low byte of FPCR + 499 * +00000000000005DC B29D F27C 000000000000027C 500 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000005E0 B2B8 0003 0000000000000003 501 SRNMB 3 SET FPC to RM, to -infinity +00000000000005E4 B3AD 0410 502 CLGDBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked +00000000000005E8 E310 7010 0024 0000000000000010 503 STG R1,2*8(,R7) Store uint-64 result + ASMA Ver. 0.2.0 ieee-cvttolog64.asm: Test IEEE Convert To Logical (uint-64) 01 Sep 2016 10:11:28 Page 13 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000005EE B29C 8008 0000000000000008 504 STFPC 2*4(R8) Store resulting FPC flags and DXC +00000000000005F2 B222 0010 505 IPM R1 Get condition code and program mask +00000000000005F6 8810 001C 000000000000001C 506 SRL R1,28 Isolate CC in low order byte +00000000000005FA 4210 800B 000000000000000B 507 STC R1,(2*4)+3(,R8) Save CC as low byte of FPCR + 508 * +00000000000005FE B29D F27C 000000000000027C 509 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000602 B2B8 0007 0000000000000007 510 SRNMB 7 RFS, Prepare for Shorter Precision +0000000000000606 B3AD 0410 511 CLGDBR R1,0,FPR0,B'0100' FPCR ctl'd rounding, inexact masked +000000000000060A E310 7018 0024 0000000000000018 512 STG R1,3*8(,R7) Store uint-64 result +0000000000000610 B29C 800C 000000000000000C 513 STFPC 3*4(R8) Store resulting FPC flags and DXC +0000000000000614 B222 0010 514 IPM R1 Get condition code and program mask +0000000000000618 8810 001C 000000000000001C 515 SRL R1,28 Isolate CC in low order byte +000000000000061C 4210 800F 000000000000000F 516 STC R1,(3*4)+3(,R8) Save CC as low byte of FPCR + 517 * + 518 * Test cases using rounding mode specified in the instruction M3 field + 519 * +0000000000000620 B29D F27C 000000000000027C 520 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000624 B3AD 1010 521 CLGDBR R1,1,FPR0,B'0000' RNTA, to nearest, ties away from 0 +0000000000000628 E310 7020 0024 0000000000000020 522 STG R1,4*8(,R7) Store uint-64 result +000000000000062E B29C 8010 0000000000000010 523 STFPC 4*4(R8) Store resulting FPC flags and DXC +0000000000000632 B222 0010 524 IPM R1 Get condition code and program mask +0000000000000636 8810 001C 000000000000001C 525 SRL R1,28 Isolate CC in low order byte +000000000000063A 4210 8013 0000000000000013 526 STC R1,(4*4)+3(,R8) Save CC as low byte of FPCR + 527 * +000000000000063E B29D F27C 000000000000027C 528 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000642 B3AD 3010 529 CLGDBR R1,3,FPR0,B'0000' RFS, prepare for shorter precision +0000000000000646 E310 7028 0024 0000000000000028 530 STG R1,5*8(,R7) Store uint-64 result +000000000000064C B29C 8014 0000000000000014 531 STFPC 5*4(R8) Store resulting FPC flags and DXC +0000000000000650 B222 0010 532 IPM R1 Get condition code and program mask +0000000000000654 8810 001C 000000000000001C 533 SRL R1,28 Isolate CC in low order byte +0000000000000658 4210 8017 0000000000000017 534 STC R1,(5*4)+3(,R8) Save CC as low byte of FPCR + 535 * +000000000000065C B29D F27C 000000000000027C 536 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000660 B3AD 4010 537 CLGDBR R1,4,FPR0,B'0000' RNTE, to nearest, ties to even +0000000000000664 E310 7030 0024 0000000000000030 538 STG R1,6*8(,R7) Store uint-64 result +000000000000066A B29C 8018 0000000000000018 539 STFPC 6*4(R8) Store resulting FPC flags and DXC +000000000000066E B222 0010 540 IPM R1 Get condition code and program mask +0000000000000672 8810 001C 000000000000001C 541 SRL R1,28 Isolate CC in low order byte +0000000000000676 4210 801B 000000000000001B 542 STC R1,(6*4)+3(,R8) Save CC as low byte of FPCR + 543 * +000000000000067A B29D F27C 000000000000027C 544 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000067E B3AD 5010 545 CLGDBR R1,5,FPR0,B'0000' RZ, toward zero +0000000000000682 E310 7038 0024 0000000000000038 546 STG R1,7*8(,R7) Store uint-64 result +0000000000000688 B29C 801C 000000000000001C 547 STFPC 7*4(R8) Store resulting FPC flags and DXC +000000000000068C B222 0010 548 IPM R1 Get condition code and program mask +0000000000000690 8810 001C 000000000000001C 549 SRL R1,28 Isolate CC in low order byte +0000000000000694 4210 801F 000000000000001F 550 STC R1,(7*4)+3(,R8) Save CC as low byte of FPCR + 551 * +0000000000000698 B29D F27C 000000000000027C 552 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000069C B3AD 6010 553 CLGDBR R1,6,FPR0,B'0000' RP, to +inf +00000000000006A0 E310 7040 0024 0000000000000040 554 STG R1,8*8(,R7) Store uint-64 result +00000000000006A6 B29C 8020 0000000000000020 555 STFPC 8*4(R8) Store resulting FPC flags and DXC + ASMA Ver. 0.2.0 ieee-cvttolog64.asm: Test IEEE Convert To Logical (uint-64) 01 Sep 2016 10:11:28 Page 14 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000006AA B222 0010 556 IPM R1 Get condition code and program mask +00000000000006AE 8810 001C 000000000000001C 557 SRL R1,28 Isolate CC in low order byte +00000000000006B2 4210 8023 0000000000000023 558 STC R1,(8*4)+3(,R8) Save CC as low byte of FPCR + 559 * +00000000000006B6 B29D F27C 000000000000027C 560 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000006BA B3AD 7010 561 CLGDBR R1,7,FPR0,B'0000' RM, to -inf +00000000000006BE E310 7048 0024 0000000000000048 562 STG R1,9*8(,R7) Store uint-64 result +00000000000006C4 B29C 8024 0000000000000024 563 STFPC 9*4(R8) Store resulting FPC flags and DXC +00000000000006C8 B222 0010 564 IPM R1 Get condition code and program mask +00000000000006CC 8810 001C 000000000000001C 565 SRL R1,28 Isolate CC in low order byte +00000000000006D0 4210 8027 0000000000000027 566 STC R1,(9*4)+3(,R8) Save CC as low byte of FPCR + 567 * +00000000000006D4 4130 3008 0000000000000008 568 LA R3,8(,R3) Point to next input value +00000000000006D8 4170 7050 0000000000000050 569 LA R7,10*8(,R7) Point to next uint-64 result set +00000000000006DC 4180 8030 0000000000000030 570 LA R8,12*4(,R8) Point to next FPCR/CC result set +00000000000006E0 062C 571 BCTR R2,R12 Convert next input value. +00000000000006E2 07FD 572 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvttolog64.asm: Test IEEE Convert To Logical (uint-64) 01 Sep 2016 10:11:28 Page 15 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 574 *********************************************************************** + 575 * + 576 * Convert extended BFP to uint-64. A pair of results is generated + 577 * for each input: one with all exceptions non-trappable, and the + 578 * second with all exceptions trappable. The FPCR and condition code + 579 * are stored for each result. + 580 * + 581 *********************************************************************** + + +00000000000006E4 9823 A000 0000000000000000 583 CLGXBR LM R2,R3,0(R10) Get count and address of test input values +00000000000006E8 9878 A008 0000000000000008 584 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000006EC 1222 585 LTR R2,R2 Any test cases? +00000000000006EE 078D 586 BZR R13 ..No, return to caller +00000000000006F0 0DC0 587 BASR R12,0 Set top of loop + 588 * +00000000000006F2 6800 3000 0000000000000000 589 LD FPR0,0(,R3) Get extended BFP test value part 1 +00000000000006F6 6820 3008 0000000000000008 590 LD R2,8(,R3) Get extended BFP test value part 1 +00000000000006FA B29D F27C 000000000000027C 591 LFPC FPCREGNT Set exceptions non-trappable +00000000000006FE B3AE 0010 592 CLGXBR R1,0,FPR0,0 Cvt float in FPR0-FPR2 to uint-64 in GPR1 +0000000000000702 E310 7000 0024 0000000000000000 593 STG R1,0(,R7) Store uint-64 result +0000000000000708 B29C 8000 0000000000000000 594 STFPC (0*4)(R8) Store resulting FPC flags and DXC +000000000000070C B222 0010 595 IPM R1 Get condition code and program mask +0000000000000710 8810 001C 000000000000001C 596 SRL R1,28 Isolate CC in low order byte +0000000000000714 4210 8003 0000000000000003 597 STC R1,(0*4)+3(,R8) Save CC as low byte of FPCR + 598 * +0000000000000718 B29D F280 0000000000000280 599 LFPC FPCREGTR Set exceptions trappable +000000000000071C B982 0011 600 XGR R1,R1 Clear any residual result in R1 +0000000000000720 0410 601 SPM R1 Clear out any residual nz condition code +0000000000000722 B3AE 0010 602 CLGXBR R1,0,FPR0,0 Cvt float in FPR0-FPR2 to uint-64 in GPR1 +0000000000000726 E310 7008 0024 0000000000000008 603 STG R1,8(,R7) Store uint-64 result +000000000000072C B29C 8004 0000000000000004 604 STFPC (1*4)(R8) Store resulting FPC flags and DXC +0000000000000730 B222 0010 605 IPM R1 Get condition code and program mask +0000000000000734 8810 001C 000000000000001C 606 SRL R1,28 Isolate CC in low order byte +0000000000000738 4210 8007 0000000000000007 607 STC R1,(1*4)+3(,R8) Save CC as low byte of FPCR + 608 * +000000000000073C 4130 3010 0000000000000010 609 LA R3,16(,R3) Point to next extended BFP input value +0000000000000740 4170 7010 0000000000000010 610 LA R7,16(,R7) Point to next uint-64 result pair +0000000000000744 4180 8008 0000000000000008 611 LA R8,8(,R8) Point to next FPCR/CC result pair +0000000000000748 062C 612 BCTR R2,R12 Convert next input value. +000000000000074A 07FD 613 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvttolog64.asm: Test IEEE Convert To Logical (uint-64) 01 Sep 2016 10:11:28 Page 16 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 615 *********************************************************************** + 616 * + 617 * Convert extended BFP to integers using each possible rounding mode. + 618 * Ten test results are generated for each input. A 48-byte test result + 619 * section is used to keep results sets aligned on a quad-double word. + 620 * + 621 * The first four tests use rounding modes specified in the FPCR with + 622 * the IEEE Inexact exception supressed. SRNM (2-bit) is used for + 623 * the first two FPCR-controlled tests and SRNMB (3-bit) is used for + 624 * the last two To get full coverage of that instruction pair. + 625 * + 626 * The next six results use instruction-specified rounding modes. + 627 * + 628 * The default rounding mode (0 for RNTE) is not tested in this section; + 629 * prior tests used the default rounding mode. RNTE is tested + 630 * explicitly as a rounding mode in this section. + 631 * + 632 *********************************************************************** + + +000000000000074C 9823 A000 0000000000000000 634 CLGXBRA LM R2,R3,0(R10) Get count and address of test input values +0000000000000750 9878 A008 0000000000000008 635 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000754 1222 636 LTR R2,R2 Any test cases? +0000000000000756 078D 637 BZR R13 ..No, return to caller +0000000000000758 0DC0 638 BASR R12,0 Set top of loop + 639 * +000000000000075A 6800 3000 0000000000000000 640 LD R0,0(,R3) Get extended BFP test value part 1 +000000000000075E 6820 3008 0000000000000008 641 LD R2,8(,R3) Get extended BFP test value part 2 + 642 * + 643 * Test cases using rounding mode specified in the FPCR + 644 * +0000000000000762 B29D F27C 000000000000027C 645 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000766 B299 0001 0000000000000001 646 SRNM 1 SET FPC to RZ, towards zero. +000000000000076A B3AE 0410 647 CLGXBR R1,0,R0,B'0100' FPCR ctl'd rounding, inexact masked +000000000000076E E310 7000 0024 0000000000000000 648 STG R1,0*8(,R7) Store uint-64 result +0000000000000774 B29C 8000 0000000000000000 649 STFPC 0(R8) Store resulting FPC flags and DXC +0000000000000778 B222 0010 650 IPM R1 Get condition code and program mask +000000000000077C 8810 001C 000000000000001C 651 SRL R1,28 Isolate CC in low order byte +0000000000000780 4210 8003 0000000000000003 652 STC R1,3(,R8) Save CC as low byte of FPCR + 653 * +0000000000000784 B29D F27C 000000000000027C 654 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000788 B299 0002 0000000000000002 655 SRNM 2 SET FPC to RP, to +infinity +000000000000078C B3AE 0410 656 CLGXBR R1,0,R0,B'0100' FPCR ctl'd rounding, inexact masked +0000000000000790 E310 7008 0024 0000000000000008 657 STG R1,1*8(,R7) Store uint-64 result +0000000000000796 B29C 8004 0000000000000004 658 STFPC 1*4(R8) Store resulting FPC flags and DXC +000000000000079A B222 0010 659 IPM R1 Get condition code and program mask +000000000000079E 8810 001C 000000000000001C 660 SRL R1,28 Isolate CC in low order byte +00000000000007A2 4210 8007 0000000000000007 661 STC R1,(1*4)+3(,R8) Save CC as low byte of FPCR + 662 * +00000000000007A6 B29D F27C 000000000000027C 663 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000007AA B2B8 0003 0000000000000003 664 SRNMB 3 SET FPC to RM, to -infinity +00000000000007AE B3AE 0410 665 CLGXBR R1,0,R0,B'0100' FPCR ctl'd rounding, inexact masked + ASMA Ver. 0.2.0 ieee-cvttolog64.asm: Test IEEE Convert To Logical (uint-64) 01 Sep 2016 10:11:28 Page 17 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000007B2 E310 7010 0024 0000000000000010 666 STG R1,2*8(,R7) Store uint-64 result +00000000000007B8 B29C 8008 0000000000000008 667 STFPC 2*4(R8) Store resulting FPC flags and DXC +00000000000007BC B222 0010 668 IPM R1 Get condition code and program mask +00000000000007C0 8810 001C 000000000000001C 669 SRL R1,28 Isolate CC in low order byte +00000000000007C4 4210 800B 000000000000000B 670 STC R1,(2*4)+3(,R8) Save CC as low byte of FPCR + 671 * +00000000000007C8 B29D F27C 000000000000027C 672 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000007CC B2B8 0007 0000000000000007 673 SRNMB 7 RFS, Prepare for Shorter Precision +00000000000007D0 B3AE 0410 674 CLGXBR R1,0,R0,B'0100' FPCR ctl'd rounding, inexact masked +00000000000007D4 E310 7018 0024 0000000000000018 675 STG R1,3*8(,R7) Store uint-64 result +00000000000007DA B29C 800C 000000000000000C 676 STFPC 3*4(R8) Store resulting FPC flags and DXC +00000000000007DE B222 0010 677 IPM R1 Get condition code and program mask +00000000000007E2 8810 001C 000000000000001C 678 SRL R1,28 Isolate CC in low order byte +00000000000007E6 4210 800F 000000000000000F 679 STC R1,(3*4)+3(,R8) Save CC as low byte of FPCR + 680 * + 681 * Test cases using rounding mode specified in the instruction M3 field + 682 * +00000000000007EA B29D F27C 000000000000027C 683 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000007EE B3AE 1010 684 CLGXBR R1,1,R0,B'0000' RNTA, to nearest, ties away from zero +00000000000007F2 E310 7020 0024 0000000000000020 685 STG R1,4*8(,R7) Store uint-64 result +00000000000007F8 B29C 8010 0000000000000010 686 STFPC 4*4(R8) Store resulting FPC flags and DXC +00000000000007FC B222 0010 687 IPM R1 Get condition code and program mask +0000000000000800 8810 001C 000000000000001C 688 SRL R1,28 Isolate CC in low order byte +0000000000000804 4210 8013 0000000000000013 689 STC R1,(4*4)+3(,R8) Save CC as low byte of FPCR + 690 * +0000000000000808 B29D F27C 000000000000027C 691 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000080C B3AE 3010 692 CLGXBR R1,3,R0,B'0000' RFS, to prepare for shorter precision +0000000000000810 E310 7028 0024 0000000000000028 693 STG R1,5*8(,R7) Store uint-64 result +0000000000000816 B29C 8014 0000000000000014 694 STFPC 5*4(R8) Store resulting FPC flags and DXC +000000000000081A B222 0010 695 IPM R1 Get condition code and program mask +000000000000081E 8810 001C 000000000000001C 696 SRL R1,28 Isolate CC in low order byte +0000000000000822 4210 8017 0000000000000017 697 STC R1,(5*4)+3(,R8) Save CC as low byte of FPCR + 698 * +0000000000000826 B29D F27C 000000000000027C 699 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000082A B3AE 4010 700 CLGXBR R1,4,R0,B'0000' RNTE, to nearest, ties to even +000000000000082E E310 7030 0024 0000000000000030 701 STG R1,6*8(,R7) Store uint-64 result +0000000000000834 B29C 8018 0000000000000018 702 STFPC 6*4(R8) Store resulting FPC flags and DXC +0000000000000838 B222 0010 703 IPM R1 Get condition code and program mask +000000000000083C 8810 001C 000000000000001C 704 SRL R1,28 Isolate CC in low order byte +0000000000000840 4210 801B 000000000000001B 705 STC R1,(6*4)+3(,R8) Save CC as low byte of FPCR + 706 * +0000000000000844 B29D F27C 000000000000027C 707 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000848 B3AE 5010 708 CLGXBR R1,5,R0,B'0000' RZ, toward zero +000000000000084C E310 7038 0024 0000000000000038 709 STG R1,7*8(,R7) Store uint-64 result +0000000000000852 B29C 801C 000000000000001C 710 STFPC 7*4(R8) Store resulting FPC flags and DXC +0000000000000856 B222 0010 711 IPM R1 Get condition code and program mask +000000000000085A 8810 001C 000000000000001C 712 SRL R1,28 Isolate CC in low order byte +000000000000085E 4210 801F 000000000000001F 713 STC R1,(7*4)+3(,R8) Save CC as low byte of FPCR + 714 * +0000000000000862 B29D F27C 000000000000027C 715 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000866 B3AE 6010 716 CLGXBR R1,6,R0,B'0000' RP, to +inf +000000000000086A E310 7040 0024 0000000000000040 717 STG R1,8*8(,R7) Store uint-64 result + ASMA Ver. 0.2.0 ieee-cvttolog64.asm: Test IEEE Convert To Logical (uint-64) 01 Sep 2016 10:11:28 Page 18 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000870 B29C 8020 0000000000000020 718 STFPC 8*4(R8) Store resulting FPC flags and DXC +0000000000000874 B222 0010 719 IPM R1 Get condition code and program mask +0000000000000878 8810 001C 000000000000001C 720 SRL R1,28 Isolate CC in low order byte +000000000000087C 4210 8023 0000000000000023 721 STC R1,(8*4)+3(,R8) Save CC as low byte of FPCR + 722 * +0000000000000880 B29D F27C 000000000000027C 723 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000884 B3AE 7010 724 CLGXBR R1,7,R0,B'0000' RM, to -inf +0000000000000888 E310 7048 0024 0000000000000048 725 STG R1,9*8(,R7) Store uint-64 result +000000000000088E B29C 8024 0000000000000024 726 STFPC 9*4(R8) Store resulting FPC flags and DXC +0000000000000892 B222 0010 727 IPM R1 Get condition code and program mask +0000000000000896 8810 001C 000000000000001C 728 SRL R1,28 Isolate CC in low order byte +000000000000089A 4210 8027 0000000000000027 729 STC R1,(9*4)+3(,R8) Save CC as low byte of FPCR + 730 * +000000000000089E 4130 3010 0000000000000010 731 LA R3,16(,R3) Point to next input value +00000000000008A2 4170 7050 0000000000000050 732 LA R7,10*8(,R7) Point to next uint-64 result set +00000000000008A6 4180 8030 0000000000000030 733 LA R8,12*4(,R8) Point to next FPCR/CC result pair +00000000000008AA 062C 734 BCTR R2,R12 Convert next input value. +00000000000008AC 07FD 735 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvttolog64.asm: Test IEEE Convert To Logical (uint-64) 01 Sep 2016 10:11:28 Page 19 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 737 *********************************************************************** + 738 * + 739 * BFP inputs for Convert To Logical testing. The same set of values + 740 * are used for short, long, and extended formats, with the exception + 741 * of the last value, which is rounded to fit the input format and + 742 * for the needs of the test (conversion or rounding). + 743 * + 744 *********************************************************************** + + + 746 * + 747 * Short integer inputs for Convert From Fixed testing. The same set of + 748 * inputs are used for short, long, and extended formats. The last two + 749 * values are used for rounding mode tests for short only; conversion of + 750 * uint-64 to long or extended are always exact. + 751 * +00000000000008B0 752 SBFPIN DS 0F Inputs for short BFP testing +00000000000008B0 3F800000 753 DC X'3F800000' +1.0 +00000000000008B4 40000000 754 DC X'40000000' +2.0 +00000000000008B8 40800000 755 DC X'40800000' +4.0 +00000000000008BC 7F810000 756 DC X'7F810000' SNaN +00000000000008C0 7FC10000 757 DC X'7FC10000' QNaN +00000000000008C4 5F800001 758 DC X'5F800001' max uint-64 + 1 rounded up to short BFP + 759 * 18 446 746 272 732 807 168 + 760 * Note: above value rounds to max uint-64. +00000000000008C8 5F7FFFFF 761 DC X'5F7FFFFF' max uint-64 rounded down to short BFP + 762 * 18 446 742 974 197 923 840 +00000000000008CC 3F400000 763 DC X'3F400000' +0.75 +00000000000008D0 3E800000 764 DC X'3E800000' +0.25 + 0000000000000024 0000000000000001 765 SBFPCT EQU *-SBFPIN Count of short BFP in list * 4 + 766 * + 767 * +00000000000008D4 768 SBFPINRM DS 0F Inputs for short BFP rounding testing + 769 * + 770 * The following values correspond to Figure 9-11 on page 9-16 of the + 771 * z/Arch POP, SA22-7832-10 + 772 * +00000000000008D4 BFC00000 773 DC X'BFC00000' -1.5 +00000000000008D8 BF000000 774 DC X'BF000000' -0.5 +00000000000008DC 3F000000 775 DC X'3F000000' +0.5 +00000000000008E0 3FC00000 776 DC X'3FC00000' +1.5 +00000000000008E4 40200000 777 DC X'40200000' +2.5 +00000000000008E8 40B00000 778 DC X'40B00000' +5.5 +00000000000008EC 41180000 779 DC X'41180000' +9.5 + 780 * + 781 * The following values ensure correct rounding for values that + 782 * are not ties. + 783 * +00000000000008F0 5F7FFFFF 784 DC X'5F7FFFFF' max uint-64 rounded down to short BFP + 785 * 18 446 742 974 197 923 840 +00000000000008F4 3F400000 786 DC X'3F400000' +0.75 +00000000000008F8 3E800000 787 DC X'3E800000' +0.25 + ASMA Ver. 0.2.0 ieee-cvttolog64.asm: Test IEEE Convert To Logical (uint-64) 01 Sep 2016 10:11:28 Page 20 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 0000000000000028 0000000000000001 788 SBFPRMCT EQU *-SBFPINRM Count of rounding mode test short BFP * 4 + 789 * + 790 * +00000000000008FC 791 LBFPIN DS 0F Inputs for long BFP testing +00000000000008FC 3FF00000 00000000 792 DC X'3FF0000000000000' +1.0 +0000000000000904 40000000 00000000 793 DC X'4000000000000000' +2.0 +000000000000090C 40100000 00000000 794 DC X'4010000000000000' +4.0 +0000000000000914 7FF01000 00000000 795 DC X'7FF0100000000000' SNaN +000000000000091C 7FF81000 00000000 796 DC X'7FF8100000000000' QNaN +0000000000000924 43F00000 00000000 797 DC X'43F0000000000000' max uint-64 + 1 rounded up + 798 * 18 446 744 073 709 555 712 +000000000000092C 43EFFFFF FFFFFFFF 799 DC X'43EFFFFFFFFFFFFF' max uint-64 rounded down + 800 * 18 446 744 073 709 549 568 +0000000000000934 3FE80000 00000000 801 DC X'3FE8000000000000' +0.75 +000000000000093C 3FD00000 00000000 802 DC X'3FD0000000000000' +0.25 + 0000000000000048 0000000000000001 803 LBFPCT EQU *-LBFPIN Count of long BFP in list * 8 + 804 * + 805 * +0000000000000944 806 LBFPINRM DS 0F Inputs for long BFP rounding testing + 807 * + 808 * The following values correspond to Figure 9-11 on page 9-16 of the + 809 * z/Arch POP, SA22-7832-10 + 810 * +0000000000000944 BFF80000 00000000 811 DC X'BFF8000000000000' -1.5 +000000000000094C BFE00000 00000000 812 DC X'BFE0000000000000' -0.5 +0000000000000954 3FE00000 00000000 813 DC X'3FE0000000000000' +0.5 +000000000000095C 3FF80000 00000000 814 DC X'3FF8000000000000' +1.5 +0000000000000964 40040000 00000000 815 DC X'4004000000000000' +2.5 +000000000000096C 40160000 00000000 816 DC X'4016000000000000' +5.5 +0000000000000974 40230000 00000000 817 DC X'4023000000000000' +9.5 + 818 * + 819 * The following values ensure correct rounding for values that + 820 * are not ties. + 821 * +000000000000097C 43EFFFFF FFFFFFFF 822 DC X'43EFFFFFFFFFFFFF' max uint-64 rounded down + 823 * 18 446 744 073 709 549 568 + 824 * DC X'3FE8000000000000' 0.75 +0000000000000984 3FD00000 00000000 825 DC X'3FD0000000000000' +0.25 + 0000000000000048 0000000000000001 826 LBFPRMCT EQU *-LBFPINRM Count of roundinf test long BFP * 8 + 827 * + 828 * +0000000000000990 829 XBFPIN DS 0D Inputs for extended BFP testing +0000000000000990 3FFF0000 00000000 830 DC X'3FFF0000000000000000000000000000' +1.0 +00000000000009A0 40000000 00000000 831 DC X'40000000000000000000000000000000' +2.0 +00000000000009B0 40010000 00000000 832 DC X'40010000000000000000000000000000' +4.0 +00000000000009C0 7FFF0100 00000000 833 DC X'7FFF0100000000000000000000000000' SNaN +00000000000009D0 7FFF8100 00000000 834 DC X'7FFF8100000000000000000000000000' QNaN +00000000000009E0 403F0000 00000000 835 DC X'403F0000000000000000000000000000' max uint-64 + 1 + 836 * 18 446 744 073 709 551 616 (exact) +00000000000009F0 403EFFFF FFFFFFFF 837 DC X'403EFFFFFFFFFFFFFFFE000000000000' max uint-64 + 838 * 18 446 744 073 709 551 615 (exact) +0000000000000A00 403EFFFF FFFFFFFF 839 DC X'403EFFFFFFFFFFFFFFFF000000000000' max uint-64+0.5 + ASMA Ver. 0.2.0 ieee-cvttolog64.asm: Test IEEE Convert To Logical (uint-64) 01 Sep 2016 10:11:28 Page 21 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 840 * 18 446 744 073 709 551 615.5 + 841 * Above is always inexact, and may overflow based on rounding mode +0000000000000A10 3FFE8000 00000000 842 DC X'3FFE8000000000000000000000000000' 0.75 +0000000000000A20 3FFD0000 00000000 843 DC X'3FFD0000000000000000000000000000' 0.25 + 00000000000000A0 0000000000000001 844 XBFPCT EQU *-XBFPIN Count of extended BFP in list * 16 + 845 * + 846 * +0000000000000A30 847 XBFPINRM DS 0D Inputs for extended BFP rounding testing + 848 * + 849 * The following values correspond to Figure 9-11 on page 9-16 of the + 850 * z/Arch POP, SA22-7832-10 + 851 * +0000000000000A30 BFFF8000 00000000 852 DC X'BFFF8000000000000000000000000000' -1.5 +0000000000000A40 BFFE0000 00000000 853 DC X'BFFE0000000000000000000000000000' -0.5 +0000000000000A50 3FFE0000 00000000 854 DC X'3FFE0000000000000000000000000000' +0.5 +0000000000000A60 3FFF8000 00000000 855 DC X'3FFF8000000000000000000000000000' +1.5 +0000000000000A70 40004000 00000000 856 DC X'40004000000000000000000000000000' +2.5 +0000000000000A80 40016000 00000000 857 DC X'40016000000000000000000000000000' +5.5 +0000000000000A90 40023000 00000000 858 DC X'40023000000000000000000000000000' +9.5 + 859 * + 860 * The following values ensure correct rounding for values that + 861 * are not ties. + 862 * +0000000000000AA0 403EFFFF FFFFFFFF 863 DC X'403EFFFFFFFFFFFFFFFF000000000000' max uint-64+0.5 + 864 * 18 446 744 073 709 551 615.5 + 865 * Above is always inexact, and may overflow based on rounding mode +0000000000000AB0 3FFE8000 00000000 866 DC X'3FFE8000000000000000000000000000' 0.75 +0000000000000AC0 3FFD0000 00000000 867 DC X'3FFD0000000000000000000000000000' 0.25 + 00000000000000A0 0000000000000001 868 XBFPRMCT EQU *-XBFPINRM Count of rounding test extd BFP * 16 + 869 * + 870 * Locations for results + 871 * + 0000000000001000 0000000000000000 872 SINTOUT EQU BFPCVTTL+X'1000' Uint-64 values from short BFP + 873 * ..6 pairs used, room for 32 + 0000000000001200 0000000000000000 874 SINTFLGS EQU BFPCVTTL+X'1200' FPC flags and DXC from short BFP + 875 * ..6 pairs used, room for 32 + 0000000000001300 0000000000000000 876 SINTRMO EQU BFPCVTTL+X'1300' Short rounding mode test results + 877 * ..8 sets used, room for 16 + 0000000000001800 0000000000000000 878 SINTRMOF EQU BFPCVTTL+X'1800' Short rounding mode FPCR contents + 879 * ..8 sets used, room for 16 + 880 * + 0000000000002000 0000000000000000 881 LINTOUT EQU BFPCVTTL+X'2000' Uint-64 values from long BFP + 882 * ..6 pairs used, room for 32 + 0000000000002200 0000000000000000 883 LINTFLGS EQU BFPCVTTL+X'2200' FPC flags and DXC from long BFP + 884 * ..6 pairs used, room for 32 + 0000000000002300 0000000000000000 885 LINTRMO EQU BFPCVTTL+X'2300' Long rounding mode test results + 886 * ..8 sets used, room for 16 + 0000000000002800 0000000000000000 887 LINTRMOF EQU BFPCVTTL+X'2800' Long rounding mode FPCR contents + 888 * ..8 sets used, room for 16 + 889 * + 0000000000003000 0000000000000000 890 XINTOUT EQU BFPCVTTL+X'3000' Uint-64 values from extd BFP + 891 * ..6 pairs used, room for 32 + ASMA Ver. 0.2.0 ieee-cvttolog64.asm: Test IEEE Convert To Logical (uint-64) 01 Sep 2016 10:11:28 Page 22 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 0000000000003200 0000000000000000 892 XINTFLGS EQU BFPCVTTL+X'3200' FPC flags and DXC from extd BFP + 893 * ..6 pairs used, room for 32 + 0000000000003300 0000000000000000 894 XINTRMO EQU BFPCVTTL+X'3300' Extended rounding mode test results + 895 * ..8 sets used, room for 16 + 0000000000003800 0000000000000000 896 XINTRMOF EQU BFPCVTTL+X'3800' Long rounding mode FPCR contents + 897 * ..8 sets used, room for 16 + 898 * + 0000000000003B00 0000000000000000 899 ENDLABL EQU BFPCVTTL+X'3B00' next available result location + 900 PADCSECT ENDLABL pad to end of results if not ASMA + 901+ MNOTE *,'asma detected; no CSECT padding performed' +0000000000000AD0 902 END + ASMA Ver. 0.2.0 ieee-cvttolog64.asm: Test IEEE Convert To Logical (uint-64) 01 Sep 2016 10:11:28 Page 23 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +BFPCVTTL J 000000 2768 97 139 142 144 147 155 214 872 874 876 878 881 883 885 887 890 892 894 + 896 899 +CLGDBR I 000522 4 422 185 +CLGDBRA I 000586 4 472 187 +CLGEBR I 000360 4 261 178 +CLGEBRA I 0003C4 4 311 180 +CLGXBR I 0006E4 4 583 192 +CLGXBRA I 00074C 4 634 194 +CTLR0 F 000278 4 204 171 172 173 +ENDLABL U 003B00 0 899 +EXTDS F 000320 4 227 191 +FPCREGNT X 00027C 4 205 268 321 330 339 348 359 367 375 383 391 399 429 482 491 500 509 520 + 528 536 544 552 560 591 645 654 663 672 683 691 699 707 715 723 +FPCREGTR X 000280 4 206 276 437 599 +FPR0 U 000000 1 117 267 269 279 317 323 332 341 350 360 368 376 384 392 400 428 430 440 + 478 484 493 502 511 521 529 537 545 553 561 589 592 602 +FPR1 U 000001 1 118 +FPR10 U 00000A 1 127 +FPR11 U 00000B 1 128 +FPR12 U 00000C 1 129 +FPR13 U 00000D 1 130 +FPR14 U 00000E 1 131 +FPR15 U 00000F 1 132 +FPR2 U 000002 1 119 +FPR3 U 000003 1 120 +FPR4 U 000004 1 121 +FPR5 U 000005 1 122 +FPR6 U 000006 1 123 +FPR7 U 000007 1 124 +FPR8 U 000008 1 125 +FPR9 U 000009 1 126 +HARDWAIT X 000268 8 202 163 +IMAGE 1 000000 2768 0 +LBFPCT U 000048 1 803 222 +LBFPIN F 0008FC 4 791 803 223 +LBFPINRM F 000944 4 806 826 241 +LBFPRMCT U 000048 1 826 240 +LINTFLGS U 002200 0 883 225 +LINTOUT U 002000 0 881 224 +LINTRMO U 002300 0 885 242 +LINTRMOF U 002800 0 887 243 +LONGS F 000310 4 221 184 +PCINTCD H 00008E 2 140 157 +PCNOTDTA H 00020C 2 160 158 +PCOLDPSW U 000150 0 142 159 +PROGCHK H 000200 2 156 148 +R0 U 000000 1 98 171 173 640 647 656 665 674 684 692 700 708 716 724 +R1 U 000001 1 99 269 270 272 273 274 277 278 279 280 282 283 284 323 324 326 327 328 + 332 333 335 336 337 341 342 344 345 346 350 351 353 354 355 360 361 + 363 364 365 368 369 371 372 373 376 377 379 380 381 384 385 387 388 + 389 392 393 395 396 397 400 401 403 404 405 430 431 433 434 435 438 + 439 440 441 443 444 445 484 485 487 488 489 493 494 496 497 498 502 + ASMA Ver. 0.2.0 ieee-cvttolog64.asm: Test IEEE Convert To Logical (uint-64) 01 Sep 2016 10:11:28 Page 24 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + + 503 505 506 507 511 512 514 515 516 521 522 524 525 526 529 530 532 + 533 534 537 538 540 541 542 545 546 548 549 550 553 554 556 557 558 + 561 562 564 565 566 592 593 595 596 597 600 601 602 603 605 606 607 + 647 648 650 651 652 656 657 659 660 661 665 666 668 669 670 674 675 + 677 678 679 684 685 687 688 689 692 693 695 696 697 700 701 703 704 + 705 708 709 711 712 713 716 717 719 720 721 724 725 727 728 729 +R10 U 00000A 1 108 177 179 184 186 191 193 261 262 311 312 422 423 472 473 583 584 634 + 635 +R11 U 00000B 1 109 +R12 U 00000C 1 110 265 289 315 410 426 450 476 571 587 612 638 734 +R13 U 00000D 1 111 178 180 185 187 192 194 264 290 314 411 425 451 475 572 586 613 637 + 735 +R14 U 00000E 1 112 161 162 196 197 +R15 U 00000F 1 113 134 +R2 U 000002 1 100 261 263 289 311 313 410 422 424 450 472 474 571 583 585 590 612 634 + 636 641 734 +R3 U 000003 1 101 261 267 286 311 317 407 422 428 447 472 478 568 583 589 590 609 634 + 640 641 731 +R4 U 000004 1 102 +R5 U 000005 1 103 +R6 U 000006 1 104 +R7 U 000007 1 105 262 270 280 287 312 324 333 342 351 361 369 377 385 393 401 408 423 + 431 441 448 473 485 494 503 512 522 530 538 546 554 562 569 584 593 + 603 610 635 648 657 666 675 685 693 701 709 717 725 732 +R8 U 000008 1 106 262 271 274 281 284 288 312 325 328 334 337 343 346 352 355 362 365 + 370 373 378 381 386 389 394 397 402 405 409 423 432 435 442 445 449 + 473 486 489 495 498 504 507 513 516 523 526 531 534 539 542 547 550 + 555 558 563 566 570 584 594 597 604 607 611 635 649 652 658 661 667 + 670 676 679 686 689 694 697 702 705 710 713 718 721 726 729 733 +R9 U 000009 1 107 +RMEXTDS F 000350 4 245 193 +RMLONGS F 000340 4 239 186 +RMSHORTS F 000330 4 233 179 +SBFPCT U 000024 1 765 216 +SBFPIN F 0008B0 4 752 765 217 +SBFPINRM F 0008D4 4 768 788 235 +SBFPRMCT U 000028 1 788 234 +SHORTS F 000300 4 215 177 +SINTFLGS U 001200 0 874 219 +SINTOUT U 001000 0 872 218 +SINTRMO U 001300 0 876 236 +SINTRMOF U 001800 0 878 237 +START I 000214 4 171 145 +WAITPSW X 000258 8 201 198 +XBFPCT U 0000A0 1 844 228 +XBFPIN D 000990 8 829 844 229 +XBFPINRM D 000A30 8 847 868 247 +XBFPRMCT U 0000A0 1 868 246 +XINTFLGS U 003200 0 892 231 +XINTOUT U 003000 0 890 230 +XINTRMO U 003300 0 894 248 +XINTRMOF U 003800 0 896 249 + ASMA Ver. 0.2.0 ieee-cvttolog64.asm: Test IEEE Convert To Logical (uint-64) 01 Sep 2016 10:11:28 Page 25 + + MACRO DEFN REFERENCES + +PADCSECT 72 900 + ASMA Ver. 0.2.0 ieee-cvttolog64.asm: Test IEEE Convert To Logical (uint-64) 01 Sep 2016 10:11:28 Page 26 + + DESC SYMBOL SIZE POS ADDR + +Entry: 0 + +Image IMAGE 2768 000-ACF 000-ACF + Region 2768 000-ACF 000-ACF + CSECT BFPCVTTL 2768 000-ACF 000-ACF + ASMA Ver. 0.2.0 ieee-cvttolog64.asm: Test IEEE Convert To Logical (uint-64) 01 Sep 2016 10:11:28 Page 27 + + STMT FILE NAME + +1 C:\Users\srorso\Documents\GitHub\hyperion\tests\bfp-005-cvttolog64.asm + + +** NO ERRORS FOUND ** + +[901] MNOTE *,asma detected; no CSECT padding performed + \ No newline at end of file diff --git a/tests/bfp-005-cvttolog64.tst b/tests/bfp-005-cvttolog64.tst new file mode 100644 index 000000000..25e23475e --- /dev/null +++ b/tests/bfp-005-cvttolog64.tst @@ -0,0 +1,664 @@ +*Testcase bfp-005-cvttolog64.tst: CLGEBR, CLGDBR, CLGXBR + +#Testcase bfp-005-cvtfrLOG64.tst: IEEE Convert To Logical +#..Includes CONVERT TO LOGICAL 64 (3). Tests traps, exceptions, results +#..from different rounding modes, and NaN propagation. + + +sysclear +archmode esame + +# +# Following suppresses logging of program checks. This test program, as part +# of its normal operation, generates 16 program check messages that have no +# value in the validation process. (The messages, not the program checks.) +# +ostailor quiet + +loadcore "$(testpath)/bfp-005-cvttolog64.core" + +runtest 1.0 + +ostailor null # restore messages for subsequent tests + + +# BFP short inputs converted to uint-64 - results +*Compare +r 1000.10 +*Want "CLGEBR result pair 1" 00000000 00000001 00000000 00000001 +r 1010.10 +*Want "CLGEBR result pair 2" 00000000 00000002 00000000 00000002 +r 1020.10 +*Want "CLGEBR result pair 3" 00000000 00000004 00000000 00000004 +r 1030.10 +*Want "CLGEBR result pair 4" 00000000 00000000 00000000 00000000 +r 1040.10 +*Want "CLGEBR result pair 5" 00000000 00000000 00000000 00000000 +r 1050.10 +*Want "CLGEBR result pair 6" FFFFFFFF FFFFFFFF 00000000 00000000 +r 1060.10 +*Want "CLGEBR result pair 7" FFFFFF00 00000000 FFFFFF00 00000000 +r 1070.10 +*Want "CLGEBR result pair 8" 00000000 00000001 00000000 00000001 +r 1080.10 +*Want "CLGEBR result pair 9" 00000000 00000000 00000000 00000000 + +# I am not satisfied with test case 6 further investigation needed. +# It would appear that f32_to_uint64 is returning invalid and max uint-64. + +# Short BFP inputs converted to uint-64 - FPCR contents +*Compare +r 1200.10 +*Want "CLGEBR FPCR pairs 1-2" 00000002 F8000002 00000002 F8000002 +r 1210.10 +*Want "CLGEBR FPCR pairs 3-4" 00000002 F8000002 00880003 F8008000 +r 1220.10 +*Want "CLGEBR FPCR pairs 5-6" 00880003 F8008000 00880003 F8008000 +r 1230.10 +*Want "CLGEBR FPCR pairs 7-8" 00000002 F8000002 00080002 F8000C02 +r 1240.08 +*Want "CLGEBR FPCR pair 9" 00080002 F8000802 + + +# short BFP inputs converted to uint-64 - results from rounding +*Compare +r 1300.10 # RZ, RP +*Want "CLGEBR -1.5 FPC modes 1, 2" 00000000 00000000 00000000 00000000 +r 1310.10 # RM, RFS +*Want "CLGEBR -1.5 FPC modes 3, 7" 00000000 00000000 00000000 00000000 +r 1320.10 # RNTA, RFS +*Want "CLGEBR -1.5 M3 modes 1, 3" 00000000 00000000 00000000 00000000 +r 1330.10 # RNTE, RZ +*Want "CLGEBR -1.5 M3 modes 4, 5" 00000000 00000000 00000000 00000000 +r 1340.10 # RP, RM +*Want "CLGEBR -1.5 M3 modes 6, 7" 00000000 00000000 00000000 00000000 + +r 1350.10 # RZ, RP +*Want "CLGEBR -0.5 FPC modes 1, 2" 00000000 00000000 00000000 00000000 +r 1360.10 # RM, RFS +*Want "CLGEBR -0.5 FPC modes 3, 7" 00000000 00000000 00000000 00000000 +r 1370.10 # RNTA, RFS +*Want "CLGEBR -0.5 M3 modes 1, 3" 00000000 00000000 00000000 00000000 +r 1380.10 # RNTE, RZ +*Want "CLGEBR -0.5 M3 modes 4, 5" 00000000 00000000 00000000 00000000 +r 1390.10 # RP, RM +*Want "CLGEBR -0.5 M3 modes 6, 7" 00000000 00000000 00000000 00000000 + +r 13A0.10 # RZ, RP +*Want "CLGEBR +0.5 FPC modes 1, 2" 00000000 00000000 00000000 00000001 +r 13B0.10 # RM, RFS +*Want "CLGEBR +0.5 FPC modes 3, 7" 00000000 00000000 00000000 00000001 +r 13C0.10 # RNTA, RFS +*Want "CLGEBR +0.5 M3 modes 1, 3" 00000000 00000001 00000000 00000001 +r 13D0.10 # RNTE, RZ +*Want "CLGEBR +0.5 M3 modes 4, 5" 00000000 00000000 00000000 00000000 +r 13E0.10 # RP, RM +*Want "CLGEBR +0.5 M3 modes 6, 7" 00000000 00000001 00000000 00000000 + +r 13F0.10 # RZ, RP +*Want "CLGEBR +1.5 FPC modes 1, 2" 00000000 00000001 00000000 00000002 +r 1400.10 # RM, RFS +*Want "CLGEBR +1.5 FPC modes 3, 7" 00000000 00000001 00000000 00000001 +r 1410.10 # RNTA, RFS +*Want "CLGEBR +1.5 M3 modes 1, 3" 00000000 00000002 00000000 00000001 +r 1420.10 # RNTE, RZ +*Want "CLGEBR +1.5 M3 modes 4, 5" 00000000 00000002 00000000 00000001 +r 1430.10 # RP, RM +*Want "CLGEBR +1.5 M3 modes 6, 7" 00000000 00000002 00000000 00000001 + +r 1440.10 # RZ, RP +*Want "CLGEBR +2.5 FPC modes 1, 2" 00000000 00000002 00000000 00000003 +r 1450.10 # RM, RFS +*Want "CLGEBR +2.5 FPC modes 3, 7" 00000000 00000002 00000000 00000003 +r 1460.10 # RNTA, RFS +*Want "CLGEBR +2.5 M3 modes 1, 3" 00000000 00000003 00000000 00000003 +r 1470.10 # RNTE, RZ +*Want "CLGEBR +2.5 M3 modes 4, 5" 00000000 00000002 00000000 00000002 +r 1480.10 # RP, RM +*Want "CLGEBR +2.5 M3 modes 6, 7" 00000000 00000003 00000000 00000002 + +r 1490.10 # RZ, RP +*Want "CLGEBR +5.5 FPC modes 1, 2" 00000000 00000005 00000000 00000006 +r 14A0.10 # RM, RFS +*Want "CLGEBR +5.5 FPC modes 3, 7" 00000000 00000005 00000000 00000005 +r 14B0.10 # RNTA, RFS +*Want "CLGEBR +5.5 M3 modes 1, 3" 00000000 00000006 00000000 00000005 +r 14C0.10 # RNTE, RZ +*Want "CLGEBR +5.5 M3 modes 4, 5" 00000000 00000006 00000000 00000005 +r 14D0.10 # RP, RM +*Want "CLGEBR +5.5 M3 modes 6, 7" 00000000 00000006 00000000 00000005 + +r 14E0.10 # RZ, RP +*Want "CLGEBR +9.5 FPC modes 1, 2" 00000000 00000009 00000000 0000000A +r 14F0.10 # RM, RFS +*Want "CLGEBR +9.5 FPC modes 3, 7" 00000000 00000009 00000000 00000009 +r 1500.10 # RNTA, RFS +*Want "CLGEBR +9.5 M3 modes 1, 3" 00000000 0000000A 00000000 00000009 +r 1510.10 # RNTE, RZ +*Want "CLGEBR +9.5 M3 modes 4, 5" 00000000 0000000A 00000000 00000009 +r 1520.10 # RP, RM +*Want "CLGEBR +9.5 M3 modes 6, 7" 00000000 0000000A 00000000 00000009 + +r 1530.10 # RZ, RP +*Want "CLGEBR max FPC modes 1, 2" FFFFFF00 00000000 FFFFFF00 00000000 +r 1540.10 # RM, RFS +*Want "CLGEBR max FPC modes 3, 7" FFFFFF00 00000000 FFFFFF00 00000000 +r 1550.10 # RNTA, RFS +*Want "CLGEBR max M3 modes 1, 3" FFFFFF00 00000000 FFFFFF00 00000000 +r 1560.10 # RNTE, RZ +*Want "CLGEBR max M3 modes 4, 5" FFFFFF00 00000000 FFFFFF00 00000000 +r 1570.10 # RP, RM +*Want "CLGEBR max M3 modes 6, 7" FFFFFF00 00000000 FFFFFF00 00000000 + +r 1580.10 # RZ, RP +*Want "CLGEBR +0.75 FPC modes 1, 2" 00000000 00000000 00000000 00000001 +r 1590.10 # RM, RFS +*Want "CLGEBR +0.75 FPC modes 3, 7" 00000000 00000000 00000000 00000001 +r 15A0.10 # RNTA, RFS +*Want "CLGEBR +0.75 M3 modes 1, 3" 00000000 00000001 00000000 00000001 +r 15B0.10 # RNTE, RZ +*Want "CLGEBR +0.75 M3 modes 4, 5" 00000000 00000001 00000000 00000000 +r 15C0.10 # RP, RM +*Want "CLGEBR +0.75 M3 modes 6, 7" 00000000 00000001 00000000 00000000 + +r 15D0.10 # RZ, RP +*Want "CLGEBR +0.25 FPC modes 1, 2" 00000000 00000000 00000000 00000001 +r 15E0.10 # RM, RFS +*Want "CLGEBR +0.25 FPC modes 3, 7" 00000000 00000000 00000000 00000001 +r 15F0.10 # RNTA, RFS +*Want "CLGEBR +0.25 M3 modes 1, 3" 00000000 00000000 00000000 00000001 +r 1600.10 # RNTE, RZ +*Want "CLGEBR +0.25 M3 modes 4, 5" 00000000 00000000 00000000 00000000 +r 1610.10 # RP, RM +*Want "CLGEBR +0.25 M3 modes 6, 7" 00000000 00000001 00000000 00000000 + + +# short BFP inputs converted to uint-64 - FPCR with cc in last byte +*Compare +r 1800.10 +*Want "CLGEBR -1.5 FPC modes 1-3, 7 FPCR" 00800003 00800003 00800003 00800003 +r 1810.10 +*Want "CLGEBR -1.5 M3 modes 1, 3-5 FPCR" 00880003 00880003 00880003 00880003 +r 1820.08 +*Want "CLGEBR -1.5 M3 modes 6, 7 FPCR" 00880003 00880003 + +r 1830.10 +*Want "CLGEBR -0.5 FPC modes 1-3, 7 FPCR" 00000001 00000001 00800003 00800003 +r 1840.10 +*Want "CLGEBR -0.5 M3 modes 1, 3-5 FPCR" 00880003 00880003 00080001 00080001 +r 1850.08 +*Want "CLGEBR -0.5 M3 modes 6, 7 FPCR" 00080001 00880003 + +r 1860.10 +*Want "CLGEBR +0.5 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 1870.10 +*Want "CLGEBR +0.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 1880.08 +*Want "CLGEBR +0.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 1890.10 +*Want "CLGEBR +1.5 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 18A0.10 +*Want "CLGEBR +1.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 18B0.08 +*Want "CLGEBR +1.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 18C0.10 +*Want "CLGEBR +2.5 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 18D0.10 +*Want "CLGEBR +2.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 18E0.08 +*Want "CLGEBR +2.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 18F0.10 +*Want "CLGEBR +5.5 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 1900.10 +*Want "CLGEBR +5.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 1910.08 +*Want "CLGEBR +5.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 1920.10 +*Want "CLGEBR +9.5 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 1930.10 +*Want "CLGEBR +9.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 1940.08 +*Want "CLGEBR +9.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 1950.10 +*Want "CLGEBR max+1 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 1960.10 +*Want "CLGEBR max+1 M3 modes 1, 3-5 FPCR" 00000002 00000002 00000002 00000002 +r 1970.08 +*Want "CLGEBR max+1 M3 modes 6, 7 FPCR" 00000002 00000002 + +r 1950.10 +*Want "CLGEBR max FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 1960.10 +*Want "CLGEBR max M3 modes 1, 3-5 FPCR" 00000002 00000002 00000002 00000002 +r 1970.08 +*Want "CLGEBR max M3 modes 6, 7 FPCR" 00000002 00000002 + +r 1980.10 +*Want "CLGEBR +0.75 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 1990.10 +*Want "CLGEBR +0.75 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 19A0.08 +*Want "CLGEBR +0.75 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 19B0.10 +*Want "CLGEBR +0.25 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 19C0.10 +*Want "CLGEBR +0.25 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 19D0.08 +*Want "CLGEBR +0.5 M3 modes 6, 7 FPCR" 00080002 00080002 + + +# BFP long inputs converted to uint-64 - results +*Compare +r 2000.10 +*Want "CLGDBR result pair 1" 00000000 00000001 00000000 00000001 +r 2010.10 +*Want "CLGDBR result pair 2" 00000000 00000002 00000000 00000002 +r 2020.10 +*Want "CLGDBR result pair 3" 00000000 00000004 00000000 00000004 +r 2030.10 +*Want "CLGDBR result pair 4" 00000000 00000000 00000000 00000000 +r 2040.10 +*Want "CLGDBR result pair 5" 00000000 00000000 00000000 00000000 +r 2050.10 +*Want "CLGDBR result pair 6" FFFFFFFF FFFFFFFF 00000000 00000000 +r 2060.10 +*Want "CLGDBR result pair 7" FFFFFFFF FFFFF800 FFFFFFFF FFFFF800 +r 2070.10 +*Want "CLGDBR result pair 8" 00000000 00000001 00000000 00000001 +r 2080.10 +*Want "CLGDBR result pair 9" 00000000 00000000 00000000 00000000 + +*Compare +r 2200.10 +*Want "CLGDBR FPCR pairs 1-2" 00000002 F8000002 00000002 F8000002 +r 2210.10 +*Want "CLGDBR FPCR pairs 3-4" 00000002 F8000002 00880003 F8008000 +r 2220.10 +*Want "CLGDBR FPCR pairs 5-6" 00880003 F8008000 00880003 F8008000 +r 2230.10 +*Want "CLGDBR FPCR pairs 7-8" 00000002 F8000002 00080002 F8000C02 +r 2240.08 +*Want "CLGDBR FPCR pair 9" 00080002 F8000802 + + +# Long BFP inputs converted to uint-64 - results from rounding +*Compare +r 2300.10 # RZ, RP +*Want "CLGDBR -1.5 FPC modes 1, 2" 00000000 00000000 00000000 00000000 +r 2310.10 # RM, RFS +*Want "CLGDBR -1.5 FPC modes 3, 7" 00000000 00000000 00000000 00000000 +r 2320.10 # RNTA, RFS +*Want "CLGDBR -1.5 M3 modes 1, 3" 00000000 00000000 00000000 00000000 +r 2330.10 # RNTE, RZ +*Want "CLGDBR -1.5 M3 modes 4, 5" 00000000 00000000 00000000 00000000 +r 2340.10 # RP, RM +*Want "CLGDBR -1.5 M3 modes 6, 7" 00000000 00000000 00000000 00000000 + +r 2350.10 # RZ, RP +*Want "CLGDBR -0.5 FPC modes 1, 2" 00000000 00000000 00000000 00000000 +r 2360.10 # RM, RFS +*Want "CLGDBR -0.5 FPC modes 3, 7" 00000000 00000000 00000000 00000000 +r 2370.10 # RNTA, RFS +*Want "CLGDBR -0.5 M3 modes 1, 3" 00000000 00000000 00000000 00000000 +r 2380.10 # RNTE, RZ +*Want "CLGDBR -0.5 M3 modes 4, 5" 00000000 00000000 00000000 00000000 +r 2390.10 # RP, RM +*Want "CLGDBR -0.5 M3 modes 6, 7" 00000000 00000000 00000000 00000000 + +r 23A0.10 # RZ, RP +*Want "CLGDBR +0.5 FPC modes 1, 2" 00000000 00000000 00000000 00000001 +r 23B0.10 # RM, RFS +*Want "CLGDBR +0.5 FPC modes 3, 7" 00000000 00000000 00000000 00000001 +r 23C0.10 # RNTA, RFS +*Want "CLGDBR +0.5 M3 modes 1, 3" 00000000 00000001 00000000 00000001 +r 23D0.10 # RNTE, RZ +*Want "CLGDBR +0.5 M3 modes 4, 5" 00000000 00000000 00000000 00000000 +r 23E0.10 # RP, RM +*Want "CLGDBR +0.5 M3 modes 6, 7" 00000000 00000001 00000000 00000000 + +r 23F0.10 # RZ, RP +*Want "CLGDBR +1.5 FPC modes 1, 2" 00000000 00000001 00000000 00000002 +r 2400.10 # RM, RFS +*Want "CLGDBR +1.5 FPC modes 3, 7" 00000000 00000001 00000000 00000001 +r 2410.10 # RNTA, RFS +*Want "CLGDBR +1.5 M3 modes 1, 3" 00000000 00000002 00000000 00000001 +r 2420.10 # RNTE, RZ +*Want "CLGDBR +1.5 M3 modes 4, 5" 00000000 00000002 00000000 00000001 +r 2430.10 # RP, RM +*Want "CLGDBR +1.5 M3 modes 6, 7" 00000000 00000002 00000000 00000001 + +r 2440.10 # RZ, RP +*Want "CLGDBR +2.5 FPC modes 1, 2" 00000000 00000002 00000000 00000003 +r 2450.10 # RM, RFS +*Want "CLGDBR +2.5 FPC modes 3, 7" 00000000 00000002 00000000 00000003 +r 2460.10 # RNTA, RFS +*Want "CLGDBR +2.5 M3 modes 1, 3" 00000000 00000003 00000000 00000003 +r 2470.10 # RNTE, RZ +*Want "CLGDBR +2.5 M3 modes 4, 5" 00000000 00000002 00000000 00000002 +r 2480.10 # RP, RM +*Want "CLGDBR +2.5 M3 modes 6, 7" 00000000 00000003 00000000 00000002 + +r 2490.10 # RZ, RP +*Want "CLGDBR +5.5 FPC modes 1, 2" 00000000 00000005 00000000 00000006 +r 24A0.10 # RM, RFS +*Want "CLGDBR +5.5 FPC modes 3, 7" 00000000 00000005 00000000 00000005 +r 24B0.10 # RNTA, RFS +*Want "CLGDBR +5.5 M3 modes 1, 3" 00000000 00000006 00000000 00000005 +r 24C0.10 # RNTE, RZ +*Want "CLGDBR +5.5 M3 modes 4, 5" 00000000 00000006 00000000 00000005 +r 24D0.10 # RP, RM +*Want "CLGDBR +5.5 M3 modes 6, 7" 00000000 00000006 00000000 00000005 + +r 24E0.10 # RZ, RP +*Want "CLGDBR +9.5 FPC modes 1, 2" 00000000 00000009 00000000 0000000A +r 24F0.10 # RM, RFS +*Want "CLGDBR +9.5 FPC modes 3, 7" 00000000 00000009 00000000 00000009 +r 2500.10 # RNTA, RFS +*Want "CLGDBR +9.5 M3 modes 1, 3" 00000000 0000000A 00000000 00000009 +r 2510.10 # RNTE, RZ +*Want "CLGDBR +9.5 M3 modes 4, 5" 00000000 0000000A 00000000 00000009 +r 2520.10 # RP, RM +*Want "CLGDBR +9.5 M3 modes 6, 7" 00000000 0000000A 00000000 00000009 + +r 2530.10 # RZ, RP +*Want "CLGDBR max FPC modes 1, 2" FFFFFFFF FFFFF800 FFFFFFFF FFFFF800 +r 2540.10 # RM, RFS +*Want "CLGDBR max FPC modes 3, 7" FFFFFFFF FFFFF800 FFFFFFFF FFFFF800 +r 2550.10 # RNTA, RFS +*Want "CLGDBR max M3 modes 1, 3" FFFFFFFF FFFFF800 FFFFFFFF FFFFF800 +r 2560.10 # RNTE, RZ +*Want "CLGDBR max M3 modes 4, 5" FFFFFFFF FFFFF800 FFFFFFFF FFFFF800 +r 2570.10 # RP, RM +*Want "CLGDBR max M3 modes 6, 7" FFFFFFFF FFFFF800 FFFFFFFF FFFFF800 + + +# Long BFP inputs converted to uint-64 - FPCR contents with cc in last byte +*Compare +r 2800.10 +*Want "CLGDBR -1.5 FPC modes 1-3, 7 FPCR" 00800003 00800003 00800003 00800003 +r 2810.10 +*Want "CLGDBR -1.5 M3 modes 1, 3-5 FPCR" 00880003 00880003 00880003 00880003 +r 2820.08 +*Want "CLGDBR -1.5 M3 modes 6, 7 FPCR" 00880003 00880003 + +r 2830.10 +*Want "CLGDBR -0.5 FPC modes 1-3, 7 FPCR" 00000001 00000001 00800003 00800003 +r 2840.10 +*Want "CLGDBR -0.5 M3 modes 1, 3-5 FPCR" 00880003 00880003 00080001 00080001 +r 2850.08 +*Want "CLGDBR -0.5 M3 modes 6, 7 FPCR" 00080001 00880003 + +r 2860.10 +*Want "CLGDBR +0.5 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 2870.10 +*Want "CLGDBR +0.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 2880.08 +*Want "CLGDBR +0.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 2890.10 +*Want "CLGDBR +1.5 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 28A0.10 +*Want "CLGDBR +1.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 28B0.08 +*Want "CLGDBR +1.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 28C0.10 +*Want "CLGDBR +2.5 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 28D0.10 +*Want "CLGDBR +2.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 28E0.08 +*Want "CLGDBR +2.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 28F0.10 +*Want "CLGDBR +5.5 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 2900.10 +*Want "CLGDBR +5.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 2910.08 +*Want "CLGDBR +5.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 2920.10 +*Want "CLGDBR +9.5 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 2930.10 +*Want "CLGDBR +9.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 2940.08 +*Want "CLGDBR +9.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 2950.10 +*Want "CLGDBR max FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 2960.10 +*Want "CLGDBR max M3 modes 1, 3-5 FPCR" 00000002 00000002 00000002 00000002 +r 2970.08 +*Want "CLGDBR max M3 modes 6, 7 FPCR" 00000002 00000002 + + +# Extended BFP inputs converted to uint-64 - results +*Compare +r 3000.10 +*Want "CLGXBR result pair 1" 00000000 00000001 00000000 00000001 +r 3010.10 +*Want "CLGXBR result pair 2" 00000000 00000002 00000000 00000002 +r 3020.10 +*Want "CLGXBR result pair 3" 00000000 00000004 00000000 00000004 +r 3030.10 +*Want "CLGXBR result pair 4" 00000000 00000000 00000000 00000000 +r 3040.10 +*Want "CLGXBR result pair 5" 00000000 00000000 00000000 00000000 +r 3050.10 +*Want "CLGXBR result pair 6" FFFFFFFF FFFFFFFF 00000000 00000000 +r 3060.10 +*Want "CLGXBR result pair 7" FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 3070.10 +*Want "CLGXBR result pair 8" FFFFFFFF FFFFFFFF 00000000 00000000 +r 3080.10 +*Want "CLGXBR result pair 9" 00000000 00000001 00000000 00000001 +r 3090.10 +*Want "CLGXBR result pair 10" 00000000 00000000 00000000 00000000 + +*Compare +r 3200.10 +*Want "CLGXBR FPC pairs 1-2" 00000002 F8000002 00000002 F8000002 +r 3210.10 +*Want "CLGXBR FPC pairs 3-4" 00000002 F8000002 00880003 F8008000 +r 3220.10 +*Want "CLGXBR FPC pairs 5-6" 00880003 F8008000 00880003 F8008000 +r 3230.10 +*Want "CLGXBR FPC pairs 7-8" 00000002 F8000002 00880003 F8008000 +r 3240.10 +*Want "CLGXBR FPC pairs 9-10" 00080002 F8000C02 00080002 F8000802 + + +# Long BFP inputs converted to uint-64 - results from rounding +*Compare +r 3300.10 # RZ, RP +*Want "CLGXBR -1.5 FPC modes 1, 2" 00000000 00000000 00000000 00000000 +r 3310.10 # RM, RFS +*Want "CLGXBR -1.5 FPC modes 3, 7" 00000000 00000000 00000000 00000000 +r 3320.10 # RNTA, RFS +*Want "CLGXBR -1.5 M3 modes 1, 3" 00000000 00000000 00000000 00000000 +r 3330.10 # RNTE, RZ +*Want "CLGXBR -1.5 M3 modes 4, 5" 00000000 00000000 00000000 00000000 +r 3340.10 # RP, RM +*Want "CLGXBR -1.5 M3 modes 6, 7" 00000000 00000000 00000000 00000000 + +r 3350.10 # RZ, RP +*Want "CLGXBR -0.5 FPC modes 1, 2" 00000000 00000000 00000000 00000000 +r 3360.10 # RM, RFS +*Want "CLGXBR -0.5 FPC modes 3, 7" 00000000 00000000 00000000 00000000 +r 3370.10 # RNTA, RFS +*Want "CLGXBR -0.5 M3 modes 1, 3" 00000000 00000000 00000000 00000000 +r 3380.10 # RNTE, RZ +*Want "CLGXBR -0.5 M3 modes 4, 5" 00000000 00000000 00000000 00000000 +r 3390.10 # RP, RM +*Want "CLGXBR -0.5 M3 modes 6, 7" 00000000 00000000 00000000 00000000 + +r 33A0.10 # RZ, RP +*Want "CLGXBR +0.5 FPC modes 1, 2" 00000000 00000000 00000000 00000001 +r 33B0.10 # RM, RFS +*Want "CLGXBR +0.5 FPC modes 3, 7" 00000000 00000000 00000000 00000001 +r 33C0.10 # RNTA, RFS +*Want "CLGXBR +0.5 M3 modes 1, 3" 00000000 00000001 00000000 00000001 +r 33D0.10 # RNTE, RZ +*Want "CLGXBR +0.5 M3 modes 4, 5" 00000000 00000000 00000000 00000000 +r 33E0.10 # RP, RM +*Want "CLGXBR +0.5 M3 modes 6, 7" 00000000 00000001 00000000 00000000 + +r 33F0.10 # RZ, RP +*Want "CLGXBR +1.5 FPC modes 1, 2" 00000000 00000001 00000000 00000002 +r 3400.10 # RM, RFS +*Want "CLGXBR +1.5 FPC modes 3, 7" 00000000 00000001 00000000 00000001 +r 3410.10 # RNTA, RFS +*Want "CLGXBR +1.5 M3 modes 1, 3" 00000000 00000002 00000000 00000001 +r 3420.10 # RNTE, RZ +*Want "CLGXBR +1.5 M3 modes 4, 5" 00000000 00000002 00000000 00000001 +r 3430.10 # RP, RM +*Want "CLGXBR +1.5 M3 modes 6, 7" 00000000 00000002 00000000 00000001 + +r 3440.10 # RZ, RP +*Want "CLGXBR +2.5 FPC modes 1, 2" 00000000 00000002 00000000 00000003 +r 3450.10 # RM, RFS +*Want "CLGXBR +2.5 FPC modes 3, 7" 00000000 00000002 00000000 00000003 +r 3460.10 # RNTA, RFS +*Want "CLGXBR +2.5 M3 modes 1, 3" 00000000 00000003 00000000 00000003 +r 3470.10 # RNTE, RZ +*Want "CLGXBR +2.5 M3 modes 4, 5" 00000000 00000002 00000000 00000002 +r 3480.10 # RP, RM +*Want "CLGXBR +2.5 M3 modes 6, 7" 00000000 00000003 00000000 00000002 + +r 3490.10 # RZ, RP +*Want "CLGXBR +5.5 FPC modes 1, 2" 00000000 00000005 00000000 00000006 +r 34A0.10 # RM, RFS +*Want "CLGXBR +5.5 FPC modes 3, 7" 00000000 00000005 00000000 00000005 +r 34B0.10 # RNTA, RFS +*Want "CLGXBR +5.5 M3 modes 1, 3" 00000000 00000006 00000000 00000005 +r 34C0.10 # RNTE, RZ +*Want "CLGXBR +5.5 M3 modes 4, 5" 00000000 00000006 00000000 00000005 +r 34D0.10 # RP, RM +*Want "CLGXBR +5.5 M3 modes 6, 7" 00000000 00000006 00000000 00000005 + +r 34E0.10 # RZ, RP +*Want "CLGXBR +9.5 FPC modes 1, 2" 00000000 00000009 00000000 0000000A +r 34F0.10 # RM, RFS +*Want "CLGXBR +9.5 FPC modes 3, 7" 00000000 00000009 00000000 00000009 +r 3500.10 # RNTA, RFS +*Want "CLGXBR +9.5 M3 modes 1, 3" 00000000 0000000A 00000000 00000009 +r 3510.10 # RNTE, RZ +*Want "CLGXBR +9.5 M3 modes 4, 5" 00000000 0000000A 00000000 00000009 +r 3520.10 # RP, RM +*Want "CLGXBR +9.5 M3 modes 6, 7" 00000000 0000000A 00000000 00000009 + +r 3530.10 # RZ, RP +*Want "CLGXBR max+0.5 FPC modes 1, 2" FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 3540.10 # RM, RFS +*Want "CLGXBR max+0.5 FPC modes 3, 7" FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 3550.10 # RNTA, RFS +*Want "CLGXBR max+0.5 M3 modes 1, 3" FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 3560.10 # RNTE, RZ +*Want "CLGXBR max+0.5 M3 modes 4, 5" FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 3570.10 # RP, RM +*Want "CLGXBR max+0.5 M3 modes 6, 7" FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF + +r 3580.10 # RZ, RP +*Want "CLGXBR +0.75 FPC modes 1, 2" 00000000 00000000 00000000 00000001 +r 3590.10 # RM, RFS +*Want "CLGXBR +0.75 FPC modes 3, 7" 00000000 00000000 00000000 00000001 +r 35A0.10 # RNTA, RFS +*Want "CLGXBR +0.75 M3 modes 1, 3" 00000000 00000001 00000000 00000001 +r 35B0.10 # RNTE, RZ +*Want "CLGXBR +0.75 M3 modes 4, 5" 00000000 00000001 00000000 00000000 +r 35C0.10 # RP, RM +*Want "CLGXBR +0.75 M3 modes 6, 7" 00000000 00000001 00000000 00000000 + +r 35D0.10 # RZ, RP +*Want "CLGXBR +0.25 FPC modes 1, 2" 00000000 00000000 00000000 00000001 +r 35E0.10 # RM, RFS +*Want "CLGXBR +0.25 FPC modes 3, 7" 00000000 00000000 00000000 00000001 +r 35F0.10 # RNTA, RFS +*Want "CLGXBR +0.25 M3 modes 1, 3" 00000000 00000000 00000000 00000001 +r 3600.10 # RNTE, RZ +*Want "CLGXBR +0.25 M3 modes 4, 5" 00000000 00000000 00000000 00000000 +r 3610.10 # RP, RM +*Want "CLGXBR +0.25 M3 modes 6, 7" 00000000 00000001 00000000 00000000 + + + +# Extended BFP inputs converted to uint-64 - FPCR contents with cc in last byte +*Compare +r 3800.10 +*Want "CLGXBR -1.5 FPC modes 1-3, 7 FPCR" 00800003 00800003 00800003 00800003 +r 3810.10 +*Want "CLGXBR -1.5 M3 modes 1, 3-5 FPCR" 00880003 00880003 00880003 00880003 +r 3820.08 +*Want "CLGXBR -1.5 M3 modes 6, 7 FPCR" 00880003 00880003 + +r 3830.10 +*Want "CLGXBR -0.5 FPC modes 1-3, 7 FPCR" 00000001 00000001 00800003 00800003 +r 3840.10 +*Want "CLGXBR -0.5 M3 modes 1, 3-5 FPCR" 00880003 00880003 00080001 00080001 +r 3850.08 +*Want "CLGXBR -0.5 M3 modes 6, 7 FPCR" 00080001 00880003 + +r 3860.10 +*Want "CLGXBR +0.5 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 3870.10 +*Want "CLGXBR +0.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 3880.08 +*Want "CLGXBR +0.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 3890.10 +*Want "CLGXBR +1.5 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 38A0.10 +*Want "CLGXBR +1.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 38B0.08 +*Want "CLGXBR +1.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 38C0.10 +*Want "CLGXBR +2.5 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 38D0.10 +*Want "CLGXBR +2.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 38E0.08 +*Want "CLGXBR +2.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 38F0.10 +*Want "CLGXBR +5.5 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 3900.10 +*Want "CLGXBR +5.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 3910.08 +*Want "CLGXBR +5.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 3920.10 +*Want "CLGXBR +9.5 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 3930.10 +*Want "CLGXBR +9.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 3940.08 +*Want "CLGXBR +9.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 3950.10 +*Want "CLGXBR max+0.5 FPC modes 1-3, 7 FPCR" 00000002 00800003 00000002 00000002 +r 3960.10 +*Want "CLGXBR max+0.5 M3 modes 1, 3-5 FPCR" 00880003 00080002 00880003 00080002 +r 3970.08 +*Want "CLGXBR max+0.5 M3 modes 6, 7 FPCR" 00880003 00080002 + +r 3980.10 +*Want "CLGXBR 0.75 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 3990.10 +*Want "CLGXBR 0.75 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 39A0.08 +*Want "CLGXBR 0.75 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 39B0.10 +*Want "CLGXBR 0.25 FPC modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 39C0.10 +*Want "CLGXBR 0.25 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 39D0.08 +*Want "CLGXBR 0.25 M3 modes 6, 7 FPCR" 00080002 00080002 + + +*Done + diff --git a/tests/bfp-006-cvttofix.asm b/tests/bfp-006-cvttofix.asm new file mode 100644 index 000000000..b964db54b --- /dev/null +++ b/tests/bfp-006-cvttofix.asm @@ -0,0 +1,931 @@ + TITLE 'bfp-006-cvttofix.asm: Test IEEE Convert To Fixed (int-32)' +*********************************************************************** +* +*Testcase IEEE CONVERT TO FIXED 32 +* Test case capability includes ieee exceptions trappable and +* otherwise. Test result, FPC flags, DXC, and condition code are +* saved for all tests. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* bfp-006-cvttofix.asm +* +* This assembly-language source file is part of the +* Hercules Decimal Floating Point Validation Package +* by Stephen R. Orso +* +* Copyright 2016 by Stephen R Orso. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* +* 3. The name of the author may not be used to endorse or promote +* products derived from this software without specific prior written +* permission. +* +* DISCLAMER: THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* HOLDER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* Tests the following three conversion instructions +* CONVERT TO FIXED (short BFP to int-32, RRE) +* CONVERT TO FIXED (long BFP to int-32, RRE) +* CONVERT TO FIXED (extended BFP to int-32, RRE) +* CONVERT TO FIXED (short BFP to int-32, RRF-e) +* CONVERT TO FIXED (long BFP to int-32, RRF-e) +* CONVERT TO FIXED (extended BFP to int-32, RRF-e) +* +* Test data is compiled into this program. The test script that runs +* this program can provide alternative test data through Hercules R +* commands. +* +* Test Case Order +* 1) Short BFP to Int-32 +* 2) Short BFP to Int-32 with all rounding modes +* 3) Long BFP Int-32 +* 3) Long BFP Int-32 with all rounding modes +* 4) Extended BFP to Int-32 +* 4) Extended BFP to Int-32 with all rounding modes +* +* Provided test data is: +* 1, 2, 4, -2, QNaN, SNaN, 2 147 483 648, -2 147 483 648. +* The last two values will trigger inexact exceptions when converted +* To int-32. Underflow does not get raised during Convert to Fixed. +* Provided test data for rounding tests: +* -9.5, -5.5, -2.5, -1.5, -0.5, +0.5, +1.5, +2.5, +5.5, +9.5 +* This data is taken from Table 9-11 on page 9-16 of SA22-7832-10. +* While the table illustrates LOAD FP INTEGER, the same results +* should be generated when creating an int-32 or int-64 integer. +* +* Note that three input test data sets are provided, one each for +* short, long, and extended precision BFP. All are converted to +* int-32. +* +* Also tests the following floating point support instructions +* LOAD (Short) +* LOAD (Long) +* LOAD FPC +* SET BFP ROUNDING MODE 2-BIT +* SET BFP ROUNDING MODE 3-BIT +* STORE (Short) +* STORE (Long) +* STORE FPC +* +*********************************************************************** + SPACE 3 + MACRO + PADCSECT &ENDLABL +.* +.* Macro to pad the CSECT to include result data areas if this test +.* program is not being assembled using asma. asma generates a core +.* image that is loaded by the loadcore command, and because the +.* core image is a binary stored in Github, it makes sense to make +.* this small effort to keep the core image small. +.* + AIF (D'&ENDLABL).GOODPAD + MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + MNOTE *,'No CSECT padding performed' + MEXIT +.* +.GOODPAD ANOP Label valid. See if we're on asma + AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + ORG &ENDLABL-1 Not ASMA. Pad CSECT + MEXIT +.* +.NOPAD ANOP + MNOTE *,'asma detected; no CSECT padding performed' + MEND +* +* Note: for compatibility with the z/CMS test rig, do not change +* or use R11, R14, or R15. Everything else is fair game. +* +BFPCVTTF START 0 +R0 EQU 0 +R1 EQU 1 +R2 EQU 2 +R3 EQU 3 +R4 EQU 4 +R5 EQU 5 +R6 EQU 6 +R7 EQU 7 +R8 EQU 8 +R9 EQU 9 +R10 EQU 10 +R11 EQU 11 +R12 EQU 12 +R13 EQU 13 +R14 EQU 14 +R15 EQU 15 +* +* Floating Point Register equates to keep the cross reference clean +* +FPR0 EQU 0 +FPR1 EQU 1 +FPR2 EQU 2 +FPR3 EQU 3 +FPR4 EQU 4 +FPR5 EQU 5 +FPR6 EQU 6 +FPR7 EQU 7 +FPR8 EQU 8 +FPR9 EQU 9 +FPR10 EQU 10 +FPR11 EQU 11 +FPR12 EQU 12 +FPR13 EQU 13 +FPR14 EQU 14 +FPR15 EQU 15 +* + USING *,R15 +* +* Above works on real iron (R15=0 after sysclear) +* and in z/CMS (R15 points to start of load module) +* + SPACE 2 +*********************************************************************** +* +* Low core definitions, Restart PSW, and Program Check Routine. +* +*********************************************************************** + SPACE 2 + ORG BFPCVTTF+X'8E' Program check interrution code +PCINTCD DS H +* +PCOLDPSW EQU BFPCVTTF+X'150' z/Arch Program check old PSW +* + ORG BFPCVTTF+X'1A0' z/Arch Restart PSW + DC X'0000000180000000',AD(START) +* + ORG BFPCVTTF+X'1D0' z/Arch Program check old PSW + DC X'0000000000000000',AD(PROGCHK) +* +* Program check routine. If Data Exception, continue execution at +* the instruction following the program check. Otherwise, hard wait. +* No need to collect data. All interesting DXC stuff is captured +* in the FPCR. +* + ORG BFPCVTTF+X'200' +PROGCHK DS 0H Program check occured... + CLI PCINTCD+1,X'07' Data Exception? + JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) + LPSWE PCOLDPSW ..yes, resume program execution +PCNOTDTA DS 0H + LTR R14,R14 Return address provided? + BNZR R14 Yes, return to z/CMS test rig. + LPSWE HARDWAIT Not data exception, enter disabled wait + EJECT +*********************************************************************** +* +* Main program. Enable Advanced Floating Point, process test cases. +* +*********************************************************************** + SPACE 2 +START STCTL R0,R0,CTLR0 Store CR0 to enable AFP + OI CTLR0+1,X'04' Turn on AFP bit + LCTL R0,R0,CTLR0 Reload updated CR0 +* +* Short BFP Input testing +* + LA R10,SHORTS Point to short BFP test inputs + BAS R13,CFEBR Convert values to fixed from short BFP + LA R10,RMSHORTS Point to inputs for rounding mode tests + BAS R13,CFEBRA Convert using all rounding mode options +* +* Short BFP Input testing +* + LA R10,LONGS Point to long BFP test inputs + BAS R13,CFDBR Convert values to fixed from long BFP + LA R10,RMLONGS Point to inputs for rounding mode tests + BAS R13,CFDBRA Convert using all rounding mode options +* +* Short BFP Input testing +* + LA R10,EXTDS Point to extended BFP test inputs + BAS R13,CFXBR Convert values to fixed from extended + LA R10,RMEXTDS Point to inputs for rounding mode tests + BAS R13,CFXBRA Convert using all rounding mode options +* + LTR R14,R14 Return address provided? + BNZR R14 ..Yes, return to z/CMS test rig. + LPSWE WAITPSW All done +* + DS 0D Ensure correct alignment for psw +WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end +* +CTLR0 DS F +FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags +* +* Input values parameter list, four fullwords: +* 1) Count, +* 2) Address of inputs, +* 3) Address to place results, and +* 4) Address to place DXC/Flags/cc values. +* + ORG BFPCVTTF+X'300' +SHORTS DS 0F Inputs for short BFP testing + DC A(SBFPCT/4) + DC A(SBFPIN) + DC A(SINTOUT) + DC A(SINTFLGS) +* +LONGS DS 0F Inputs for long BFP testing + DC A(LBFPCT/8) + DC A(LBFPIN) + DC A(LINTOUT) + DC A(LINTFLGS) +* +EXTDS DS 0F Inputs for Extended BFP testing + DC A(XBFPCT/16) + DC A(XBFPIN) + DC A(XINTOUT) + DC A(XINTFLGS) +* +RMSHORTS DS 0F Inputs for long BFP rounding mode tests + DC A(SBFPRMCT/4) + DC A(SBFPINRM) Short BFP rounding mode test inputs + DC A(SINTRMO) Space for rounding mode test results + DC A(SINTRMOF) Space for rounding mode test flags +* +RMLONGS DS 0F Inputs for long BFP rounding mode tests + DC A(LBFPRMCT/8) + DC A(LBFPINRM) Long BFP rounding mode test inputs + DC A(LINTRMO) Space for rounding mode tests results + DC A(LINTRMOF) Space for rounding mode test flags +* +RMEXTDS DS 0F Inputs for ext'd BFP rounding mode tests + DC A(XBFPRMCT/16) + DC A(XBFPINRM) Extended BFP rounding mode test inputs + DC A(XINTRMO) Space for rounding mode results + DC A(XINTRMOF) Space for rounding mode test flags + EJECT +*********************************************************************** +* +* Convert short BFP to integer-32 format. A pair of results is +* generated for each input: one with all exceptions non-trappable, and +* the second with all exceptions trappable. The FPCR and condition +* code is stored for each result. +* +*********************************************************************** + SPACE 3 +CFEBR LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LE FPR8,0(,R3) Get short BFP test value + LFPC FPCREGNT Set exceptions non-trappable + CFEBR R1,0,FPR8 Cvt float in FPR8 to Int in GPR1 + ST R1,0(,R7) Store int-32 result + STFPC 0(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGTR Set exceptions trappable + XR R1,R1 Clear any residual result in R1 + SPM R1 Clear out any residual nz condition code + CFEBR R1,0,FPR8 Cvt float in FPR8 to Int in GPR1 + ST R1,4(,R7) Store short BFP result + STFPC 4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,7(,R8) Save CC as low byte of FPCR +* + LA R3,4(,R3) Point to next input value + LA R7,8(,R7) Point to next int-32 converted value pair + LA R8,8(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert short BFP to int-32 using each possible rounding mode. +* Ten test results are generated for each input. A 48-byte test +* result section is used to keep results sets aligned on a quad-double +* word. +* +* The first four tests use rounding modes specified in the FPC with +* the IEEE Inexact exception supressed. SRNM (2-bit) is used for the +* first two FPCR-controlled tests and SRNMB (3-bit) is used for the +* last two to get full coverage of that instruction pair. +* +* The next six results use instruction-specified rounding modes. +* +* The default rounding mode (0 for RNTE) is not tested in this section; +* prior tests used the default rounding mode. RNTE is tested +* explicitly as a rounding mode in this section. +* +*********************************************************************** + SPACE 2 +CFEBRA LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LE FPR8,0(,R3) Get short BFP test value +* +* Test cases using rounding mode specified in the FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 1 SET FPC to RZ, towards zero. + CFEBRA R1,0,FPR8,B'0100' FPC ctl'd rounding, inexact masked + ST R1,0*4(,R7) Store integer-32 result + STFPC 0(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 2 SET FPC to RP, to +infinity + CFEBRA R1,0,FPR8,B'0100' FPC ctl'd rounding inexact masked + ST R1,1*4(,R7) Store integer-32 result + STFPC 1*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(1*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 3 SET FPC to RM, to -infinity + CFEBRA R1,0,FPR8,B'0100' FPC ctl'd rounding inexact masked + ST R1,2*4(,R7) Store integer-32 result + STFPC 2*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(2*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 7 RFS, Prepare for Shorter Precision + CFEBRA R1,0,FPR8,B'0100' FPC ctl'd rounding inexact masked + ST R1,3*4(,R7) Store integer-32 result + STFPC 3*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(3*4)+3(,R8) Save CC as low byte of FPCR +* +* Test cases using rounding mode specified in the instruction M3 field +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CFEBRA R1,1,FPR8,B'0000' RNTA, to nearest, ties away + ST R1,4*4(,R7) Store integer-32 result + STFPC 4*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(4*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CFEBRA R1,3,FPR8,B'0000' RFS, prepare for shorter precision + ST R1,5*4(,R7) Store integer-32 result + STFPC 5*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(5*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CFEBRA R1,4,FPR8,B'0000' RNTE, to nearest, ties to even + ST R1,6*4(,R7) Store integer-32 result + STFPC 6*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(6*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CFEBRA R1,5,FPR8,B'0000' RZ, toward zero + ST R1,7*4(,R7) Store integer-32 result + STFPC 7*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(7*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CFEBRA R1,6,FPR8,B'0000' RP, to +inf + ST R1,8*4(,R7) Store integer-32 result + STFPC 8*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(8*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CFEBRA R1,7,FPR8,B'0000' RM, to -inf + ST R1,9*4(,R7) Store integer-32 result + STFPC 9*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(9*4)+3(,R8) Save CC as low byte of FPCR +* + LA R3,4(,R3) Point to next input value + LA R7,12*4(,R7) Point to next int-32 converted value set + LA R8,12*4(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert long BFP inputs to integer-32. A pair of results is +* generated for each input: one with all exceptions non-trappable, and +* the second with all exceptions trappable. The FPCR and condition +* code is stored for each result. +* +*********************************************************************** + SPACE 3 +CFDBR LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LD FPR8,0(,R3) Get long BFP test value + LFPC FPCREGNT Set exceptions non-trappable + CFDBR R1,0,FPR8 Cvt float in FPR8 to Int in GPR1 + ST R1,0(,R7) Store long BFP result + STFPC 0(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGTR Set exceptions trappable + XR R1,R1 Clear any residual result in R1 + SPM R1 Clear out any residual nz condition code + CFDBR R1,0,FPR8 Cvt float in FPR8 to Int in GPR1 + ST R1,4(,R7) Store int-32 result + STFPC 4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,7(,R8) Save CC as low byte of FPCR +* + LA R3,8(,R3) Point to next input value + LA R7,8(,R7) Point to next int-32 converted value pair + LA R8,8(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert long BFP to int-32 using each possible rounding mode. +* Ten test results are generated for each input. A 48-byte test result +* section is used to keep results sets aligned on a quad-double word. +* +* The first four tests use rounding modes specified in the FPC with the +* IEEE Inexact exception supressed. SRNM (2-bit) is used for the first +* two FPCR-controlled tests and SRNMB (3-bit) is used for the last two +* to get full coverage of that instruction pair. +* +* The next six results use instruction-specified rounding modes. +* +* The default rounding mode (0 for RNTE) is not tested in this section; +* prior tests used the default rounding mode. RNTE is tested explicitly +* as a rounding mode in this section. +* +*********************************************************************** + SPACE 2 +CFDBRA LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LD FPR8,0(,R3) Get long BFP test value +* +* Test cases using rounding mode specified in the FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 1 SET FPC to RZ, towards zero. + CFDBRA R1,0,FPR8,B'0100' FPC ctl'd rounding inexact masked + ST R1,0*4(,R7) Store integer-32 result + STFPC 0(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 2 SET FPC to RP, to +infinity + CFDBRA R1,0,FPR8,B'0100' FPC ctl'd rounding inexact masked + ST R1,1*4(,R7) Store integer-32 result + STFPC 1*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(1*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 3 SET FPC to RM, to -infinity + CFDBRA R1,0,FPR8,B'0100' FPC ctl'd rounding inexact masked + ST R1,2*4(,R7) Store integer-32 result + STFPC 2*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(2*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 7 RFS, Prepare for Shorter Precision + CFDBRA R1,0,FPR8,B'0100' FPC ctl'd rounding inexact masked + ST R1,3*4(,R7) Store integer-32 result + STFPC 3*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(3*4)+3(,R8) Save CC as low byte of FPCR +* +* Test cases using rounding mode specified in the instruction M3 field +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CFDBRA R1,1,FPR8,B'0000' RNTA, to nearest, ties away + ST R1,4*4(,R7) Store integer-32 result + STFPC 4*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(4*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CFDBRA R1,3,FPR8,B'0000' RFS, prepare for shorter precision + ST R1,5*4(,R7) Store integer-32 result + STFPC 5*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(5*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CFDBRA R1,4,FPR8,B'0000' RNTE, to nearest, ties to even + ST R1,6*4(,R7) Store integer-32 result + STFPC 6*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(6*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CFDBRA R1,5,FPR8,B'0000' RZ, toward zero + ST R1,7*4(,R7) Store integer-32 result + STFPC 7*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(7*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CFDBRA R1,6,FPR8,B'0000' RP, to +inf + ST R1,8*4(,R7) Store integer-32 result + STFPC 8*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(8*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CFDBRA R1,7,FPR8,B'0000' RM, to -inf + ST R1,9*4(,R7) Store integer-32 result + STFPC 9*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(9*4)+3(,R8) Save CC as low byte of FPCR +* + LA R3,8(,R3) Point to next input values + LA R7,12*4(,R7) Point to next int-32 converted value set + LA R8,12*4(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert extended BFP to integer-32. A pair of results is generated +* for each input: one with all exceptions non-trappable, and the +* second with all exceptions trappable. The FPCR and condition code +* are stored for each result. +* +*********************************************************************** + SPACE 3 +CFXBR LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LD FPR8,0(,R3) Get extended BFP test value part 1 + LD FPR10,8(,R3) Get extended BFP test value part 1 + LFPC FPCREGNT Set exceptions non-trappable + CFXBR R1,0,FPR8 Cvt float in FPR8-FPR10 to Int-32 in GPR1 + ST R1,0(,R7) Store integer-32 result + STFPC 0(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGTR Set exceptions trappable + XR R1,R1 Clear any residual result in R1 + SPM R1 Clear out any residual nz condition code + CFXBR R1,0,FPR8 Cvt float in FPR8-FPR10 to Int-32 in GPR1 + ST R1,4(,R7) Store integer-32 result + STFPC 4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,7(,R8) Save CC as low byte of FPCR +* + LA R3,16(,R3) Point to next extended BFP input value + LA R7,8(,R7) Point to next int-32 converted value pair + LA R8,8(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert extended BFP to int-32 using each possible rounding mode. +* Ten test results are generated for each input. A 48-byte test result +* section is used to keep results sets aligned on a quad-double word. +* +* The first four tests use rounding modes specified in the FPC with the +* IEEE Inexact exception supressed. SRNM (2-bit) is used for the +* first two FPCR-controlled tests and SRNMB (3-bit) is used for the +* last two To get full coverage of that instruction pair. +* +* The next six results use instruction-specified rounding modes. +* +* The default rounding mode (0 for RNTE) is not tested in this section; +* prior tests used the default rounding mode. RNTE is tested +* explicitly as a rounding mode in this section. +* +*********************************************************************** + SPACE 2 +CFXBRA LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LD FPR8,0(,R3) Get extended BFP test value part 1 + LD R2,8(,R3) Get extended BFP test value part 2 +* +* Test cases using rounding mode specified in the FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 1 SET FPC to RZ, towards zero. + CFXBRA R1,0,FPR8,B'0100' FPC ctl'd rounding inexact masked + ST R1,0*4(,R7) Store integer-32 result + STFPC 0(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 2 SET FPC to RP, to +infinity + CFXBRA R1,0,FPR8,B'0100' FPC ctl'd rounding inexact masked + ST R1,1*4(,R7) Store integer-32 result + STFPC 1*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(1*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 3 SET FPC to RM, to -infinity + CFXBRA R1,0,FPR8,B'0100' FPC ctl'd rounding inexact masked + ST R1,2*4(,R7) Store integer-32 result + STFPC 2*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(2*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 7 RFS, Prepare for Shorter Precision + CFXBRA R1,0,FPR8,B'0100' FPC ctl'd rounding inexact masked + ST R1,3*4(,R7) Store integer-32 result + STFPC 3*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(3*4)+3(,R8) Save CC as low byte of FPCR +* +* Test cases using rounding mode specified in the instruction M3 field +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CFXBRA R1,1,FPR8,B'0000' RNTA, to nearest, ties away + ST R1,4*4(,R7) Store integer-32 result + STFPC 4*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(4*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CFXBRA R1,3,FPR8,B'0000' RFS, prepare for shorter precision + ST R1,5*4(,R7) Store integer-32 result + STFPC 5*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(5*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CFXBRA R1,4,FPR8,B'0000' RNTE, to nearest, ties to even + ST R1,6*4(,R7) Store integer-32 result + STFPC 6*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(6*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CFXBRA R1,5,FPR8,B'0000' RZ, toward zero + ST R1,7*4(,R7) Store integer-32 result + STFPC 7*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(7*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CFXBRA R1,6,FPR8,B'0000' RP, to +inf + ST R1,8*4(,R7) Store integer-32 result + STFPC 8*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(8*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CFXBRA R1,7,FPR8,B'0000' RM, to -inf + ST R1,9*4(,R7) Store integer-32 result + STFPC 9*4(R8) Store resulting FPC flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(9*4)+3(,R8) Save CC as low byte of FPCR +* + LA R3,16(,R3) Point to next input value + LA R7,12*4(,R7) Point to next int-32 converted value set + LA R8,12*4(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Floating point inputs for Convert To Fixed testing. The same test +* values in the appropriate input format are used for short, long, +* and extended format tests. The last four values should generate +* exceptions. +* +*********************************************************************** + SPACE 3 +* +* Inputs for basic tests of short BFP to int-32 +* +SBFPIN DS 0F Inputs for short BFP testing + DC X'3F800000' +1.0 + DC X'40000000' +2.0 + DC X'40800000' +4.0 + DC X'C0000000' -2.0 + DC X'7F810000' SNaN + DC X'7FC10000' QNaN +* The following two will overflow int-32 regardless of rounding mode + DC X'4F000000' +max int-32 + 1. (2,147,483,647 + 1) + DC X'CF000001' -max int-32 - 2. (-2,147,483,647 - 2) + DC X'4EFFFFFF' Largest short bfp that fits in int-32 +* ..2,147,483,520 = 0x7FFFFF80 +* +SBFPCT EQU *-SBFPIN Count of short BFP in list * 4 +* +* Inputs for exhaustive rounding mode tests of short BFP to int-32 +* +SBFPINRM DS 0F + DC X'C1180000' -9.5 + DC X'C0B00000' -5.5 + DC X'C0200000' -2.5 + DC X'BFC00000' -1.5 + DC X'BF000000' -0.5 + DC X'3F000000' +0.5 + DC X'3FC00000' +1.5 + DC X'40200000' +2.5 + DC X'40B00000' +5.5 + DC X'41180000' +9.5 + DC X'3F400000' +0.75 + DC X'3E800000' +0.25 + DC X'BF400000' -0.75 + DC X'BE800000' -0.25 +* +* There is no short BFP represtation for values between 2,147,483,520 +* and 2,147,483,648, making it difficult to come up with a test case +* that overflows for only some of the rounding modes available. +* +SBFPRMCT EQU *-SBFPINRM Count of short BFP in list * 4 +* +* Inputs for basic tests of long BFP to int-32 +* +LBFPIN DS 0F Inputs for long BFP testing + DC X'3FF0000000000000' +1.0 + DC X'4000000000000000' +2.0 + DC X'4010000000000000' +4.0 + DC X'C000000000000000' -2.0 + DC X'7FF0100000000000' SNaN + DC X'7FF8100000000000' QNaN + DC X'41E0000000000000' +max int-32 + 1 (+2147483647 + 1) + DC X'C1E0000000200000' -max int-32 - 2 (-2147483647 - 2) + DC X'41DFFFFFFFC00000' Largest long bfp that fits in +* ..int-32: 2,147,483,647 = 0x7FFFFFFF + DC X'41DFFFFFFFE00000' 2,147,483,647.5 - overflows on +* RNTE; test of traps +LBFPCT EQU *-LBFPIN Count of long BFP in list * 8 +* +* Inputs for exhaustive rounding mode tests of long BFP to int-32 +* +LBFPINRM DS 0F + DC X'C023000000000000' -9.5 + DC X'C016000000000000' -5.5 + DC X'C004000000000000' -2.5 + DC X'BFF8000000000000' -1.5 + DC X'BFE0000000000000' -0.5 + DC X'3FE0000000000000' +0.5 + DC X'3FF8000000000000' +1.5 + DC X'4004000000000000' +2.5 + DC X'4016000000000000' +5.5 + DC X'4023000000000000' +9.5 + DC X'3FE8000000000000' +0.75 + DC X'3FD0000000000000' +0.25 + DC X'BFE8000000000000' -0.75 + DC X'BFD0000000000000' -0.25 + DC X'41DFFFFFFFE00000' 2,147,483,647.5 - overflows on +* some but not all rounding modes +LBFPRMCT EQU *-LBFPINRM Count of long BFP in list * 8 +* +* Inputs for basic tests of extended BFP to int-32 +* +XBFPIN DS 0D Inputs for extended BFP testing + DC X'3FFF0000000000000000000000000000' +1.0 + DC X'40000000000000000000000000000000' +2.0 + DC X'40010000000000000000000000000000' +4.0 + DC X'C0000000000000000000000000000000' -2.0 + DC X'7FFF0100000000000000000000000000' SNaN + DC X'7FFF8100000000000000000000000000' QNaN + DC X'401E0000000000000000000000000000' +max int-32 + 1 + DC X'C01E0000000200000000000000000000' -max int-32 - 2 + DC X'401DFFFFFFFC00000000000000000000' Largest long bfp +* that fits in int-32: 2,147,483,647 = 0x7FFFFFFF + DC X'401DFFFFFFFE00000000000000000000' 2,147,483,647.5 +* - overflows on RNTE; test of traps +XBFPCT EQU *-XBFPIN Count of extended BFP in list * 16 +* +* Inputs for exhaustive rounding mode tests of long BFP to int-32 +* +XBFPINRM DS 0D + DC X'C0023000000000000000000000000000' -9.5 + DC X'C0016000000000000000000000000000' -5.5 + DC X'C0004000000000000000000000000000' -2.5 + DC X'BFFF8000000000000000000000000000' -1.5 + DC X'BFFE0000000000000000000000000000' -0.5 + DC X'3FFE0000000000000000000000000000' +0.5 + DC X'3FFF8000000000000000000000000000' +1.5 + DC X'40004000000000000000000000000000' +2.5 + DC X'40016000000000000000000000000000' +5.5 + DC X'40023000000000000000000000000000' +9.5 + DC X'3FFE8000000000000000000000000000' +0.75 + DC X'3FFD0000000000000000000000000000' +0.25 + DC X'BFFE8000000000000000000000000000' -0.75 + DC X'BFFD0000000000000000000000000000' -0.25 + DC X'401DFFFFFFFE00000000000000000000' 2,147,483,647.5 +* - overflows on some but not all rounding modes +XBFPRMCT EQU *-XBFPINRM Count of extended BFP in list * 16 +* +* Locations for results +* +SINTOUT EQU BFPCVTTF+X'1000' uint-32 values from short BFP +* ..9 pairs used, room for 16 +SINTFLGS EQU BFPCVTTF+X'1100' FPCR flags and DXC from short BFP +* ..9 pairs used, room for 16 +SINTRMO EQU BFPCVTTF+X'1200' Short rounding mode test results +* ..14 sets used, room for 20 +SINTRMOF EQU BFPCVTTF+X'1600' Short rounding mode FPCR contents +* ..14 sets used, room for 20 +* +LINTOUT EQU BFPCVTTF+X'2000' uint-32 values from long BFP +* ..10 pairs used, room for 16 +LINTFLGS EQU BFPCVTTF+X'2100' FPCR flags and DXC from long BFP +* ..10 pairs used, room for 16 +LINTRMO EQU BFPCVTTF+X'2200' Long rounding mode test results +* ..14 sets used, room for 20 +LINTRMOF EQU BFPCVTTF+X'2600' Long rounding mode FPCR contents +* ..14 sets used, room for 20 +* +XINTOUT EQU BFPCVTTF+X'3000' uint-32 values from extended BFP +* ..10 pairs used, room for 16 +XINTFLGS EQU BFPCVTTF+X'3100' FPCR flags and DXC from extended BFP +* ..10 pairs used, room for 16 +XINTRMO EQU BFPCVTTF+X'3200' Extended rounding mode test results +* ..14 sets used, room for 20 +XINTRMOF EQU BFPCVTTF+X'3600' Extended rounding mode FPCR contents +* ..14 sets used, room for 20 +* +* +ENDLABL EQU BFPCVTTF+X'4000' + PADCSECT ENDLABL + END diff --git a/tests/bfp-006-cvttofix.core b/tests/bfp-006-cvttofix.core new file mode 100644 index 000000000..703ecdc21 Binary files /dev/null and b/tests/bfp-006-cvttofix.core differ diff --git a/tests/bfp-006-cvttofix.list b/tests/bfp-006-cvttofix.list new file mode 100644 index 000000000..1216948e3 --- /dev/null +++ b/tests/bfp-006-cvttofix.list @@ -0,0 +1,1113 @@ +ASMA Ver. 0.2.0 ieee-cvttofix.asm: Test IEEE Convert To Fixed (int-32) 02 Sep 2016 08:48:00 Page 1 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 2 *********************************************************************** + 3 * + 4 *Testcase IEEE CONVERT TO FIXED 32 + 5 * Test case capability includes ieee exceptions trappable and + 6 * otherwise. Test result, FPC flags, DXC, and condition code are + 7 * saved for all tests. + 8 * + 9 *********************************************************************** + + + 11 *********************************************************************** + 12 * + 13 * Tests the following three conversion instructions + 14 * CONVERT TO FIXED (short BFP to int-32, RRE) + 15 * CONVERT TO FIXED (long BFP to int-32, RRE) + 16 * CONVERT TO FIXED (extended BFP to int-32, RRE) + 17 * CONVERT TO FIXED (short BFP to int-32, RRF-e) + 18 * CONVERT TO FIXED (long BFP to int-32, RRF-e) + 19 * CONVERT TO FIXED (extended BFP to int-32, RRF-e) + 20 * + 21 * Test data is compiled into this program. The test script that runs + 22 * this program can provide alternative test data through Hercules R + 23 * commands. + 24 * + 25 * Test Case Order + 26 * 1) Short BFP to Int-32 + 27 * 2) Short BFP to Int-32 with all rounding modes + 28 * 3) Long BFP Int-32 + 29 * 3) Long BFP Int-32 with all rounding modes + 30 * 4) Extended BFP to Int-32 + 31 * 4) Extended BFP to Int-32 with all rounding modes + 32 * + 33 * Provided test data is: + 34 * 1, 2, 4, -2, QNaN, SNaN, 2 147 483 648, -2 147 483 648. + 35 * The last two values will trigger inexact exceptions when converted + 36 * TO int-32. Underflow cases are not included. + 37 * Provided test data for rounding tests: + 38 * -9.5, -5.5, -2.5, -1.5, -0.5, +0.5, +1.5, +2.5, +5.5, +9.5 + 39 * This data is taken from Table 9-11 on page 9-16 of SA22-7832-10. + 40 * While the table illustrates LOAD FP INTEGER, the same results + 41 * should be generated when creating an int-32 or int-64 integer. + 42 * + 43 * Note that three input test data sets are provided, one each for + 44 * short, long, and extended precision BFP. All are converted to + 45 * int-32. + 46 * + 47 * Also tests the following floating point support instructions + 48 * LOAD (Short) + 49 * LOAD (Long) + 50 * LOAD FPC + 51 * SET BFP ROUNDING MODE 2-BIT + 52 * SET BFP ROUNDING MODE 3-BIT + ASMA Ver. 0.2.0 ieee-cvttofix.asm: Test IEEE Convert To Fixed (int-32) 02 Sep 2016 08:48:00 Page 2 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 53 * STORE (Short) + 54 * STORE (Long) + 55 * STORE FPC + 56 * + 57 *********************************************************************** + + + + 59 MACRO + 60 PADCSECT &ENDLABL + 61 .* + 62 .* Macro to pad the CSECT to include result data areas if this test + 63 .* program is not being assembled using asma. asma generates a core + 64 .* image that is loaded by the loadcore command, and because the + 65 .* core image is a binary stored in Github, it makes sense to make + 66 .* this small effort to keep the core image small. + 67 .* + 68 AIF (D'&ENDLABL).GOODPAD + 69 MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + 70 MNOTE *,'No CSECT padding performed' + 71 MEXIT + 72 .* + 73 .GOODPAD ANOP Label valid. See if we're on asma + 74 AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + 75 ORG &ENDLABL-1 Not ASMA. Pad CSECT + 76 MEXIT + 77 .* + 78 .NOPAD ANOP + 79 MNOTE *,'asma detected; no CSECT padding performed' + 80 MEND + 81 * + 82 * Note: for compatibility with the z/CMS test rig, do not change + 83 * or use R11, R14, or R15. Everything else is fair game. + 84 * + 0000000000000000 0000000000000B17 85 BFPCVTTF START 0 + 0000000000000000 0000000000000001 86 R0 EQU 0 + 0000000000000001 0000000000000001 87 R1 EQU 1 + 0000000000000002 0000000000000001 88 R2 EQU 2 + 0000000000000003 0000000000000001 89 R3 EQU 3 + 0000000000000004 0000000000000001 90 R4 EQU 4 + 0000000000000005 0000000000000001 91 R5 EQU 5 + 0000000000000006 0000000000000001 92 R6 EQU 6 + 0000000000000007 0000000000000001 93 R7 EQU 7 + 0000000000000008 0000000000000001 94 R8 EQU 8 + 0000000000000009 0000000000000001 95 R9 EQU 9 + 000000000000000A 0000000000000001 96 R10 EQU 10 + 000000000000000B 0000000000000001 97 R11 EQU 11 + 000000000000000C 0000000000000001 98 R12 EQU 12 + 000000000000000D 0000000000000001 99 R13 EQU 13 + 000000000000000E 0000000000000001 100 R14 EQU 14 + 000000000000000F 0000000000000001 101 R15 EQU 15 + 102 * + ASMA Ver. 0.2.0 ieee-cvttofix.asm: Test IEEE Convert To Fixed (int-32) 02 Sep 2016 08:48:00 Page 3 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 103 * Floating Point Register equates to keep the cross reference clean + 104 * + 0000000000000000 0000000000000001 105 FPR0 EQU 0 + 0000000000000001 0000000000000001 106 FPR1 EQU 1 + 0000000000000002 0000000000000001 107 FPR2 EQU 2 + 0000000000000003 0000000000000001 108 FPR3 EQU 3 + 0000000000000004 0000000000000001 109 FPR4 EQU 4 + 0000000000000005 0000000000000001 110 FPR5 EQU 5 + 0000000000000006 0000000000000001 111 FPR6 EQU 6 + 0000000000000007 0000000000000001 112 FPR7 EQU 7 + 0000000000000008 0000000000000001 113 FPR8 EQU 8 + 0000000000000009 0000000000000001 114 FPR9 EQU 9 + 000000000000000A 0000000000000001 115 FPR10 EQU 10 + 000000000000000B 0000000000000001 116 FPR11 EQU 11 + 000000000000000C 0000000000000001 117 FPR12 EQU 12 + 000000000000000D 0000000000000001 118 FPR13 EQU 13 + 000000000000000E 0000000000000001 119 FPR14 EQU 14 + 000000000000000F 0000000000000001 120 FPR15 EQU 15 + 121 * +0000000000000000 0000000000000000 122 USING *,R15 + 123 * + 124 * Above works on real iron (R15=0 after sysclear) + 125 * and in z/CMS (R15 points to start of load module) + 126 * + + + 128 *********************************************************************** + 129 * + 130 * Low core definitions, Restart PSW, and Program Check Routine. + 131 * + 132 *********************************************************************** + + +0000000000000000 0000000000000000 000000000000008E 134 ORG BFPCVTTF+X'8E' Program check interrution code +000000000000008E 0000 135 PCINTCD DS H + 136 * + 0000000000000150 0000000000000000 137 PCOLDPSW EQU BFPCVTTF+X'150' z/Arch Program check old PSW + 138 * +0000000000000090 0000000000000090 00000000000001A0 139 ORG BFPCVTTF+X'1A0' z/Arch Restart PSW +00000000000001A0 00000001 80000000 140 DC X'0000000180000000',AD(START) + 141 * +00000000000001B0 00000000000001B0 00000000000001D0 142 ORG BFPCVTTF+X'1D0' z/Arch Program check old PSW +00000000000001D0 00000000 00000000 143 DC X'0000000000000000',AD(PROGCHK) + 144 * + 145 * Program check routine. If Data Exception, continue execution at + 146 * the instruction following the program check. Otherwise, hard wait. + 147 * No need to collect data. All interesting DXC stuff is captured + 148 * in the FPCR. + 149 * +00000000000001E0 00000000000001E0 0000000000000200 150 ORG BFPCVTTF+X'200' +0000000000000200 151 PROGCHK DS 0H Program check occured... +0000000000000200 9507 F08F 000000000000008F 152 CLI PCINTCD+1,X'07' Data Exception? + ASMA Ver. 0.2.0 ieee-cvttofix.asm: Test IEEE Convert To Fixed (int-32) 02 Sep 2016 08:48:00 Page 4 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000204 A774 0004 000000000000020C 153 JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) +0000000000000208 B2B2 F150 0000000000000150 154 LPSWE PCOLDPSW ..yes, resume program execution +000000000000020C 155 PCNOTDTA DS 0H +000000000000020C 12EE 156 LTR R14,R14 Return address provided? +000000000000020E 077E 157 BNZR R14 Yes, return to z/CMS test rig. +0000000000000210 B2B2 F268 0000000000000268 158 LPSWE HARDWAIT Not data exception, enter disabled wait + ASMA Ver. 0.2.0 ieee-cvttofix.asm: Test IEEE Convert To Fixed (int-32) 02 Sep 2016 08:48:00 Page 5 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 160 *********************************************************************** + 161 * + 162 * Main program. Enable Advanced Floating Point, process test cases. + 163 * + 164 *********************************************************************** + + +0000000000000214 B600 F278 0000000000000278 166 START STCTL R0,R0,CTLR0 Store CR0 to enable AFP +0000000000000218 9604 F279 0000000000000279 167 OI CTLR0+1,X'04' Turn on AFP bit +000000000000021C B700 F278 0000000000000278 168 LCTL R0,R0,CTLR0 Reload updated CR0 + 169 * + 170 * Short BFP Input testing + 171 * +0000000000000220 41A0 F300 0000000000000300 172 LA R10,SHORTS Point to short BFP test inputs +0000000000000224 4DD0 F360 0000000000000360 173 BAS R13,CFEBR Convert values to fixed from short BFP +0000000000000228 41A0 F330 0000000000000330 174 LA R10,RMSHORTS Point to inputs for rounding mode tests +000000000000022C 4DD0 F3BE 00000000000003BE 175 BAS R13,CFEBRA Convert using all rounding mode options + 176 * + 177 * Short BFP Input testing + 178 * +0000000000000230 41A0 F310 0000000000000310 179 LA R10,LONGS Point to long BFP test inputs +0000000000000234 4DD0 F508 0000000000000508 180 BAS R13,CFDBR Convert values to fixed from long BFP +0000000000000238 41A0 F340 0000000000000340 181 LA R10,RMLONGS Point to inputs for rounding mode tests +000000000000023C 4DD0 F566 0000000000000566 182 BAS R13,CFDBRA Convert using all rounding mode options + 183 * + 184 * Short BFP Input testing + 185 * +0000000000000240 41A0 F320 0000000000000320 186 LA R10,EXTDS Point to extended BFP test inputs +0000000000000244 4DD0 F6B0 00000000000006B0 187 BAS R13,CFXBR Convert values to fixed from extended +0000000000000248 41A0 F350 0000000000000350 188 LA R10,RMEXTDS Point to inputs for rounding mode tests +000000000000024C 4DD0 F712 0000000000000712 189 BAS R13,CFXBRA Convert using all rounding mode options + 190 * +0000000000000250 12EE 191 LTR R14,R14 Return address provided? +0000000000000252 077E 192 BNZR R14 ..Yes, return to z/CMS test rig. +0000000000000254 B2B2 F258 0000000000000258 193 LPSWE WAITPSW All done + 194 * +0000000000000258 195 DS 0D Ensure correct alignment for psw +0000000000000258 00020000 00000000 196 WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +0000000000000268 00020000 00000000 197 HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end + 198 * +0000000000000278 00000000 199 CTLR0 DS F +000000000000027C 00000000 200 FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +0000000000000280 F8000000 201 FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags + 202 * + 203 * Input values parameter list, four fullwords: + 204 * 1) Count, + 205 * 2) Address of inputs, + 206 * 3) Address to place results, and + 207 * 4) Address to place DXC/Flags/cc values. + 208 * +0000000000000284 0000000000000284 0000000000000300 209 ORG BFPCVTTF+X'300' +0000000000000300 210 SHORTS DS 0F Inputs for short BFP testing + ASMA Ver. 0.2.0 ieee-cvttofix.asm: Test IEEE Convert To Fixed (int-32) 02 Sep 2016 08:48:00 Page 6 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000300 00000009 211 DC A(SBFPCT/4) +0000000000000304 00000860 212 DC A(SBFPIN) +0000000000000308 00001000 213 DC A(SINTOUT) +000000000000030C 00001100 214 DC A(SINTFLGS) + 215 * +0000000000000310 216 LONGS DS 0F Inputs for long BFP testing +0000000000000310 0000000A 217 DC A(LBFPCT/8) +0000000000000314 000008BC 218 DC A(LBFPIN) +0000000000000318 00002000 219 DC A(LINTOUT) +000000000000031C 00002100 220 DC A(LINTFLGS) + 221 * +0000000000000320 222 EXTDS DS 0F Inputs for Extended BFP testing +0000000000000320 0000000A 223 DC A(XBFPCT/16) +0000000000000324 00000988 224 DC A(XBFPIN) +0000000000000328 00003000 225 DC A(XINTOUT) +000000000000032C 00003100 226 DC A(XINTFLGS) + 227 * +0000000000000330 228 RMSHORTS DS 0F Inputs for long BFP rounding mode tests +0000000000000330 0000000E 229 DC A(SBFPRMCT/4) +0000000000000334 00000884 230 DC A(SBFPINRM) Short BFP rounding mode test inputs +0000000000000338 00001200 231 DC A(SINTRMO) Space for rounding mode test results +000000000000033C 00001600 232 DC A(SINTRMOF) Space for rounding mode test flags + 233 * +0000000000000340 234 RMLONGS DS 0F Inputs for long BFP rounding mode tests +0000000000000340 0000000F 235 DC A(LBFPRMCT/8) +0000000000000344 0000090C 236 DC A(LBFPINRM) Long BFP rounding mode test inputs +0000000000000348 00002200 237 DC A(LINTRMO) Space for rounding mode tests results +000000000000034C 00002600 238 DC A(LINTRMOF) Space for rounding mode test flags + 239 * +0000000000000350 240 RMEXTDS DS 0F Inputs for ext'd BFP rounding mode tests +0000000000000350 0000000F 241 DC A(XBFPRMCT/16) +0000000000000354 00000A28 242 DC A(XBFPINRM) Extended BFP rounding mode test inputs +0000000000000358 00003200 243 DC A(XINTRMO) Space for rounding mode results +000000000000035C 00003600 244 DC A(XINTRMOF) Space for rounding mode test flags + ASMA Ver. 0.2.0 ieee-cvttofix.asm: Test IEEE Convert To Fixed (int-32) 02 Sep 2016 08:48:00 Page 7 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 246 *********************************************************************** + 247 * + 248 * Convert short BFP to integer-32 format. A pair of results is + 249 * generated for each input: one with all exceptions non-trappable, and + 250 * the second with all exceptions trappable. The FPCR and condition + 251 * code is stored for each result. + 252 * + 253 *********************************************************************** + + + +0000000000000360 9823 A000 0000000000000000 255 CFEBR LM R2,R3,0(R10) Get count and address of test input values +0000000000000364 9878 A008 0000000000000008 256 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000368 1222 257 LTR R2,R2 Any test cases? +000000000000036A 078D 258 BZR R13 ..No, return to caller +000000000000036C 0DC0 259 BASR R12,0 Set top of loop + 260 * +000000000000036E 7880 3000 0000000000000000 261 LE FPR8,0(,R3) Get short BFP test value +0000000000000372 B29D F27C 000000000000027C 262 LFPC FPCREGNT Set exceptions non-trappable +0000000000000376 B398 0018 263 CFEBR R1,0,FPR8 Cvt float in FPR8 to Int in GPR1 +000000000000037A 5010 7000 0000000000000000 264 ST R1,0(,R7) Store int-32 result +000000000000037E B29C 8000 0000000000000000 265 STFPC 0(R8) Store resulting FPC flags and DXC +0000000000000382 B222 0010 266 IPM R1 Get condition code and program mask +0000000000000386 8810 001C 000000000000001C 267 SRL R1,28 Isolate CC in low order byte +000000000000038A 4210 8003 0000000000000003 268 STC R1,3(,R8) Save CC as low byte of FPCR + 269 * +000000000000038E B29D F280 0000000000000280 270 LFPC FPCREGTR Set exceptions trappable +0000000000000392 1711 271 XR R1,R1 Clear any residual result in R1 +0000000000000394 0410 272 SPM R1 Clear out any residual nz condition code +0000000000000396 B398 0018 273 CFEBR R1,0,FPR8 Cvt float in FPR8 to Int in GPR1 +000000000000039A 5010 7004 0000000000000004 274 ST R1,4(,R7) Store short BFP result +000000000000039E B29C 8004 0000000000000004 275 STFPC 4(R8) Store resulting FPC flags and DXC +00000000000003A2 B222 0010 276 IPM R1 Get condition code and program mask +00000000000003A6 8810 001C 000000000000001C 277 SRL R1,28 Isolate CC in low order byte +00000000000003AA 4210 8007 0000000000000007 278 STC R1,7(,R8) Save CC as low byte of FPCR + 279 * +00000000000003AE 4130 3004 0000000000000004 280 LA R3,4(,R3) Point to next input value +00000000000003B2 4170 7008 0000000000000008 281 LA R7,8(,R7) Point to next int-32 converted value pair +00000000000003B6 4180 8008 0000000000000008 282 LA R8,8(,R8) Point to next FPCR/CC result area +00000000000003BA 062C 283 BCTR R2,R12 Convert next input value. +00000000000003BC 07FD 284 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvttofix.asm: Test IEEE Convert To Fixed (int-32) 02 Sep 2016 08:48:00 Page 8 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 286 *********************************************************************** + 287 * + 288 * Convert short BFP to int-32 using each possible rounding mode. + 289 * Ten test results are generated for each input. A 48-byte test + 290 * result section is used to keep results sets aligned on a quad-double + 291 * word. + 292 * + 293 * The first four tests use rounding modes specified in the FPC with + 294 * the IEEE Inexact exception supressed. SRNM (2-bit) is used for the + 295 * first two FPCR-controlled tests and SRNMB (3-bit) is used for the + 296 * last two to get full coverage of that instruction pair. + 297 * + 298 * The next six results use instruction-specified rounding modes. + 299 * + 300 * The default rounding mode (0 for RNTE) is not tested in this section; + 301 * prior tests used the default rounding mode. RNTE is tested + 302 * explicitly as a rounding mode in this section. + 303 * + 304 *********************************************************************** + + +00000000000003BE 9823 A000 0000000000000000 306 CFEBRA LM R2,R3,0(R10) Get count and address of test input values +00000000000003C2 9878 A008 0000000000000008 307 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000003C6 1222 308 LTR R2,R2 Any test cases? +00000000000003C8 078D 309 BZR R13 ..No, return to caller +00000000000003CA 0DC0 310 BASR R12,0 Set top of loop + 311 * +00000000000003CC 7880 3000 0000000000000000 312 LE FPR8,0(,R3) Get short BFP test value + 313 * + 314 * Test cases using rounding mode specified in the FPCR + 315 * +00000000000003D0 B29D F27C 000000000000027C 316 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000003D4 B299 0001 0000000000000001 317 SRNM 1 SET FPC to RZ, towards zero. +00000000000003D8 B398 0418 318 CFEBRA R1,0,FPR8,B'0100' FPC ctl'd rounding, inexact masked +00000000000003DC 5010 7000 0000000000000000 319 ST R1,0*4(,R7) Store integer-32 result +00000000000003E0 B29C 8000 0000000000000000 320 STFPC 0(R8) Store resulting FPC flags and DXC +00000000000003E4 B222 0010 321 IPM R1 Get condition code and program mask +00000000000003E8 8810 001C 000000000000001C 322 SRL R1,28 Isolate CC in low order byte +00000000000003EC 4210 8003 0000000000000003 323 STC R1,3(,R8) Save CC as low byte of FPCR + 324 * +00000000000003F0 B29D F27C 000000000000027C 325 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000003F4 B299 0002 0000000000000002 326 SRNM 2 SET FPC to RP, to +infinity +00000000000003F8 B398 0418 327 CFEBRA R1,0,FPR8,B'0100' FPC ctl'd rounding inexact masked +00000000000003FC 5010 7004 0000000000000004 328 ST R1,1*4(,R7) Store integer-32 result +0000000000000400 B29C 8004 0000000000000004 329 STFPC 1*4(R8) Store resulting FPC flags and DXC +0000000000000404 B222 0010 330 IPM R1 Get condition code and program mask +0000000000000408 8810 001C 000000000000001C 331 SRL R1,28 Isolate CC in low order byte +000000000000040C 4210 8007 0000000000000007 332 STC R1,(1*4)+3(,R8) Save CC as low byte of FPCR + 333 * +0000000000000410 B29D F27C 000000000000027C 334 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000414 B2B8 0003 0000000000000003 335 SRNMB 3 SET FPC to RM, to -infinity +0000000000000418 B398 0418 336 CFEBRA R1,0,FPR8,B'0100' FPC ctl'd rounding inexact masked + ASMA Ver. 0.2.0 ieee-cvttofix.asm: Test IEEE Convert To Fixed (int-32) 02 Sep 2016 08:48:00 Page 9 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +000000000000041C 5010 7008 0000000000000008 337 ST R1,2*4(,R7) Store integer-32 result +0000000000000420 B29C 8008 0000000000000008 338 STFPC 2*4(R8) Store resulting FPC flags and DXC +0000000000000424 B222 0010 339 IPM R1 Get condition code and program mask +0000000000000428 8810 001C 000000000000001C 340 SRL R1,28 Isolate CC in low order byte +000000000000042C 4210 800B 000000000000000B 341 STC R1,(2*4)+3(,R8) Save CC as low byte of FPCR + 342 * +0000000000000430 B29D F27C 000000000000027C 343 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000434 B2B8 0007 0000000000000007 344 SRNMB 7 RFS, Prepare for Shorter Precision +0000000000000438 B398 0418 345 CFEBRA R1,0,FPR8,B'0100' FPC ctl'd rounding inexact masked +000000000000043C 5010 700C 000000000000000C 346 ST R1,3*4(,R7) Store integer-32 result +0000000000000440 B29C 800C 000000000000000C 347 STFPC 3*4(R8) Store resulting FPC flags and DXC +0000000000000444 B222 0010 348 IPM R1 Get condition code and program mask +0000000000000448 8810 001C 000000000000001C 349 SRL R1,28 Isolate CC in low order byte +000000000000044C 4210 800F 000000000000000F 350 STC R1,(3*4)+3(,R8) Save CC as low byte of FPCR + 351 * + 352 * Test cases using rounding mode specified in the instruction M3 field + 353 * +0000000000000450 B29D F27C 000000000000027C 354 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000454 B398 1018 355 CFEBRA R1,1,FPR8,B'0000' RNTA, to nearest, ties away +0000000000000458 5010 7010 0000000000000010 356 ST R1,4*4(,R7) Store integer-32 result +000000000000045C B29C 8010 0000000000000010 357 STFPC 4*4(R8) Store resulting FPC flags and DXC +0000000000000460 B222 0010 358 IPM R1 Get condition code and program mask +0000000000000464 8810 001C 000000000000001C 359 SRL R1,28 Isolate CC in low order byte +0000000000000468 4210 8013 0000000000000013 360 STC R1,(4*4)+3(,R8) Save CC as low byte of FPCR + 361 * +000000000000046C B29D F27C 000000000000027C 362 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000470 B398 3018 363 CFEBRA R1,3,FPR8,B'0000' RFS, prepare for shorter precision +0000000000000474 5010 7014 0000000000000014 364 ST R1,5*4(,R7) Store integer-32 result +0000000000000478 B29C 8014 0000000000000014 365 STFPC 5*4(R8) Store resulting FPC flags and DXC +000000000000047C B222 0010 366 IPM R1 Get condition code and program mask +0000000000000480 8810 001C 000000000000001C 367 SRL R1,28 Isolate CC in low order byte +0000000000000484 4210 8017 0000000000000017 368 STC R1,(5*4)+3(,R8) Save CC as low byte of FPCR + 369 * +0000000000000488 B29D F27C 000000000000027C 370 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000048C B398 4018 371 CFEBRA R1,4,FPR8,B'0000' RNTE, to nearest, ties to even +0000000000000490 5010 7018 0000000000000018 372 ST R1,6*4(,R7) Store integer-32 result +0000000000000494 B29C 8018 0000000000000018 373 STFPC 6*4(R8) Store resulting FPC flags and DXC +0000000000000498 B222 0010 374 IPM R1 Get condition code and program mask +000000000000049C 8810 001C 000000000000001C 375 SRL R1,28 Isolate CC in low order byte +00000000000004A0 4210 801B 000000000000001B 376 STC R1,(6*4)+3(,R8) Save CC as low byte of FPCR + 377 * +00000000000004A4 B29D F27C 000000000000027C 378 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000004A8 B398 5018 379 CFEBRA R1,5,FPR8,B'0000' RZ, toward zero +00000000000004AC 5010 701C 000000000000001C 380 ST R1,7*4(,R7) Store integer-32 result +00000000000004B0 B29C 801C 000000000000001C 381 STFPC 7*4(R8) Store resulting FPC flags and DXC +00000000000004B4 B222 0010 382 IPM R1 Get condition code and program mask +00000000000004B8 8810 001C 000000000000001C 383 SRL R1,28 Isolate CC in low order byte +00000000000004BC 4210 801F 000000000000001F 384 STC R1,(7*4)+3(,R8) Save CC as low byte of FPCR + 385 * +00000000000004C0 B29D F27C 000000000000027C 386 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000004C4 B398 6018 387 CFEBRA R1,6,FPR8,B'0000' RP, to +inf +00000000000004C8 5010 7020 0000000000000020 388 ST R1,8*4(,R7) Store integer-32 result + ASMA Ver. 0.2.0 ieee-cvttofix.asm: Test IEEE Convert To Fixed (int-32) 02 Sep 2016 08:48:00 Page 10 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000004CC B29C 8020 0000000000000020 389 STFPC 8*4(R8) Store resulting FPC flags and DXC +00000000000004D0 B222 0010 390 IPM R1 Get condition code and program mask +00000000000004D4 8810 001C 000000000000001C 391 SRL R1,28 Isolate CC in low order byte +00000000000004D8 4210 8023 0000000000000023 392 STC R1,(8*4)+3(,R8) Save CC as low byte of FPCR + 393 * +00000000000004DC B29D F27C 000000000000027C 394 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000004E0 B398 7018 395 CFEBRA R1,7,FPR8,B'0000' RM, to -inf +00000000000004E4 5010 7024 0000000000000024 396 ST R1,9*4(,R7) Store integer-32 result +00000000000004E8 B29C 8024 0000000000000024 397 STFPC 9*4(R8) Store resulting FPC flags and DXC +00000000000004EC B222 0010 398 IPM R1 Get condition code and program mask +00000000000004F0 8810 001C 000000000000001C 399 SRL R1,28 Isolate CC in low order byte +00000000000004F4 4210 8027 0000000000000027 400 STC R1,(9*4)+3(,R8) Save CC as low byte of FPCR + 401 * +00000000000004F8 4130 3004 0000000000000004 402 LA R3,4(,R3) Point to next input value +00000000000004FC 4170 7030 0000000000000030 403 LA R7,12*4(,R7) Point to next int-32 converted value set +0000000000000500 4180 8030 0000000000000030 404 LA R8,12*4(,R8) Point to next FPCR/CC result area +0000000000000504 062C 405 BCTR R2,R12 Convert next input value. +0000000000000506 07FD 406 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvttofix.asm: Test IEEE Convert To Fixed (int-32) 02 Sep 2016 08:48:00 Page 11 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 408 *********************************************************************** + 409 * + 410 * Convert long BFP inputs to integer-32. A pair of results is + 411 * generated for each input: one with all exceptions non-trappable, and + 412 * the second with all exceptions trappable. The FPCR and condition + 413 * code is stored for each result. + 414 * + 415 *********************************************************************** + + + +0000000000000508 9823 A000 0000000000000000 417 CFDBR LM R2,R3,0(R10) Get count and address of test input values +000000000000050C 9878 A008 0000000000000008 418 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000510 1222 419 LTR R2,R2 Any test cases? +0000000000000512 078D 420 BZR R13 ..No, return to caller +0000000000000514 0DC0 421 BASR R12,0 Set top of loop + 422 * +0000000000000516 6880 3000 0000000000000000 423 LD FPR8,0(,R3) Get long BFP test value +000000000000051A B29D F27C 000000000000027C 424 LFPC FPCREGNT Set exceptions non-trappable +000000000000051E B399 0018 425 CFDBR R1,0,FPR8 Cvt float in FPR8 to Int in GPR1 +0000000000000522 5010 7000 0000000000000000 426 ST R1,0(,R7) Store long BFP result +0000000000000526 B29C 8000 0000000000000000 427 STFPC 0(R8) Store resulting FPC flags and DXC +000000000000052A B222 0010 428 IPM R1 Get condition code and program mask +000000000000052E 8810 001C 000000000000001C 429 SRL R1,28 Isolate CC in low order byte +0000000000000532 4210 8003 0000000000000003 430 STC R1,3(,R8) Save CC as low byte of FPCR + 431 * +0000000000000536 B29D F280 0000000000000280 432 LFPC FPCREGTR Set exceptions trappable +000000000000053A 1711 433 XR R1,R1 Clear any residual result in R1 +000000000000053C 0410 434 SPM R1 Clear out any residual nz condition code +000000000000053E B399 0018 435 CFDBR R1,0,FPR8 Cvt float in FPR8 to Int in GPR1 +0000000000000542 5010 7004 0000000000000004 436 ST R1,4(,R7) Store int-32 result +0000000000000546 B29C 8004 0000000000000004 437 STFPC 4(R8) Store resulting FPC flags and DXC +000000000000054A B222 0010 438 IPM R1 Get condition code and program mask +000000000000054E 8810 001C 000000000000001C 439 SRL R1,28 Isolate CC in low order byte +0000000000000552 4210 8007 0000000000000007 440 STC R1,7(,R8) Save CC as low byte of FPCR + 441 * +0000000000000556 4130 3008 0000000000000008 442 LA R3,8(,R3) Point to next input value +000000000000055A 4170 7008 0000000000000008 443 LA R7,8(,R7) Point to next int-32 converted value pair +000000000000055E 4180 8008 0000000000000008 444 LA R8,8(,R8) Point to next FPCR/CC result area +0000000000000562 062C 445 BCTR R2,R12 Convert next input value. +0000000000000564 07FD 446 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvttofix.asm: Test IEEE Convert To Fixed (int-32) 02 Sep 2016 08:48:00 Page 12 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 448 *********************************************************************** + 449 * + 450 * Convert long BFP to int-32 using each possible rounding mode. + 451 * Ten test results are generated for each input. A 48-byte test result + 452 * section is used to keep results sets aligned on a quad-double word. + 453 * + 454 * The first four tests use rounding modes specified in the FPC with the + 455 * IEEE Inexact exception supressed. SRNM (2-bit) is used for the first + 456 * two FPCR-controlled tests and SRNMB (3-bit) is used for the last two + 457 * to get full coverage of that instruction pair. + 458 * + 459 * The next six results use instruction-specified rounding modes. + 460 * + 461 * The default rounding mode (0 for RNTE) is not tested in this section; + 462 * prior tests used the default rounding mode. RNTE is tested explicitly + 463 * as a rounding mode in this section. + 464 * + 465 *********************************************************************** + + +0000000000000566 9823 A000 0000000000000000 467 CFDBRA LM R2,R3,0(R10) Get count and address of test input values +000000000000056A 9878 A008 0000000000000008 468 LM R7,R8,8(R10) Get address of result area and flag area. +000000000000056E 1222 469 LTR R2,R2 Any test cases? +0000000000000570 078D 470 BZR R13 ..No, return to caller +0000000000000572 0DC0 471 BASR R12,0 Set top of loop + 472 * +0000000000000574 6880 3000 0000000000000000 473 LD FPR8,0(,R3) Get long BFP test value + 474 * + 475 * Test cases using rounding mode specified in the FPCR + 476 * +0000000000000578 B29D F27C 000000000000027C 477 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000057C B299 0001 0000000000000001 478 SRNM 1 SET FPC to RZ, towards zero. +0000000000000580 B399 0418 479 CFDBRA R1,0,FPR8,B'0100' FPC ctl'd rounding inexact masked +0000000000000584 5010 7000 0000000000000000 480 ST R1,0*4(,R7) Store integer-32 result +0000000000000588 B29C 8000 0000000000000000 481 STFPC 0(R8) Store resulting FPC flags and DXC +000000000000058C B222 0010 482 IPM R1 Get condition code and program mask +0000000000000590 8810 001C 000000000000001C 483 SRL R1,28 Isolate CC in low order byte +0000000000000594 4210 8003 0000000000000003 484 STC R1,3(,R8) Save CC as low byte of FPCR + 485 * +0000000000000598 B29D F27C 000000000000027C 486 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000059C B299 0002 0000000000000002 487 SRNM 2 SET FPC to RP, to +infinity +00000000000005A0 B399 0418 488 CFDBRA R1,0,FPR8,B'0100' FPC ctl'd rounding inexact masked +00000000000005A4 5010 7004 0000000000000004 489 ST R1,1*4(,R7) Store integer-32 result +00000000000005A8 B29C 8004 0000000000000004 490 STFPC 1*4(R8) Store resulting FPC flags and DXC +00000000000005AC B222 0010 491 IPM R1 Get condition code and program mask +00000000000005B0 8810 001C 000000000000001C 492 SRL R1,28 Isolate CC in low order byte +00000000000005B4 4210 8007 0000000000000007 493 STC R1,(1*4)+3(,R8) Save CC as low byte of FPCR + 494 * +00000000000005B8 B29D F27C 000000000000027C 495 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000005BC B2B8 0003 0000000000000003 496 SRNMB 3 SET FPC to RM, to -infinity +00000000000005C0 B399 0418 497 CFDBRA R1,0,FPR8,B'0100' FPC ctl'd rounding inexact masked +00000000000005C4 5010 7008 0000000000000008 498 ST R1,2*4(,R7) Store integer-32 result + ASMA Ver. 0.2.0 ieee-cvttofix.asm: Test IEEE Convert To Fixed (int-32) 02 Sep 2016 08:48:00 Page 13 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000005C8 B29C 8008 0000000000000008 499 STFPC 2*4(R8) Store resulting FPC flags and DXC +00000000000005CC B222 0010 500 IPM R1 Get condition code and program mask +00000000000005D0 8810 001C 000000000000001C 501 SRL R1,28 Isolate CC in low order byte +00000000000005D4 4210 800B 000000000000000B 502 STC R1,(2*4)+3(,R8) Save CC as low byte of FPCR + 503 * +00000000000005D8 B29D F27C 000000000000027C 504 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000005DC B2B8 0007 0000000000000007 505 SRNMB 7 RFS, Prepare for Shorter Precision +00000000000005E0 B399 0418 506 CFDBRA R1,0,FPR8,B'0100' FPC ctl'd rounding inexact masked +00000000000005E4 5010 700C 000000000000000C 507 ST R1,3*4(,R7) Store integer-32 result +00000000000005E8 B29C 800C 000000000000000C 508 STFPC 3*4(R8) Store resulting FPC flags and DXC +00000000000005EC B222 0010 509 IPM R1 Get condition code and program mask +00000000000005F0 8810 001C 000000000000001C 510 SRL R1,28 Isolate CC in low order byte +00000000000005F4 4210 800F 000000000000000F 511 STC R1,(3*4)+3(,R8) Save CC as low byte of FPCR + 512 * + 513 * Test cases using rounding mode specified in the instruction M3 field + 514 * +00000000000005F8 B29D F27C 000000000000027C 515 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000005FC B399 1018 516 CFDBRA R1,1,FPR8,B'0000' RNTA, to nearest, ties away +0000000000000600 5010 7010 0000000000000010 517 ST R1,4*4(,R7) Store integer-32 result +0000000000000604 B29C 8010 0000000000000010 518 STFPC 4*4(R8) Store resulting FPC flags and DXC +0000000000000608 B222 0010 519 IPM R1 Get condition code and program mask +000000000000060C 8810 001C 000000000000001C 520 SRL R1,28 Isolate CC in low order byte +0000000000000610 4210 8013 0000000000000013 521 STC R1,(4*4)+3(,R8) Save CC as low byte of FPCR + 522 * +0000000000000614 B29D F27C 000000000000027C 523 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000618 B399 3018 524 CFDBRA R1,3,FPR8,B'0000' RFS, prepare for shorter precision +000000000000061C 5010 7014 0000000000000014 525 ST R1,5*4(,R7) Store integer-32 result +0000000000000620 B29C 8014 0000000000000014 526 STFPC 5*4(R8) Store resulting FPC flags and DXC +0000000000000624 B222 0010 527 IPM R1 Get condition code and program mask +0000000000000628 8810 001C 000000000000001C 528 SRL R1,28 Isolate CC in low order byte +000000000000062C 4210 8017 0000000000000017 529 STC R1,(5*4)+3(,R8) Save CC as low byte of FPCR + 530 * +0000000000000630 B29D F27C 000000000000027C 531 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000634 B399 4018 532 CFDBRA R1,4,FPR8,B'0000' RNTE, to nearest, ties to even +0000000000000638 5010 7018 0000000000000018 533 ST R1,6*4(,R7) Store integer-32 result +000000000000063C B29C 8018 0000000000000018 534 STFPC 6*4(R8) Store resulting FPC flags and DXC +0000000000000640 B222 0010 535 IPM R1 Get condition code and program mask +0000000000000644 8810 001C 000000000000001C 536 SRL R1,28 Isolate CC in low order byte +0000000000000648 4210 801B 000000000000001B 537 STC R1,(6*4)+3(,R8) Save CC as low byte of FPCR + 538 * +000000000000064C B29D F27C 000000000000027C 539 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000650 B399 5018 540 CFDBRA R1,5,FPR8,B'0000' RZ, toward zero +0000000000000654 5010 701C 000000000000001C 541 ST R1,7*4(,R7) Store integer-32 result +0000000000000658 B29C 801C 000000000000001C 542 STFPC 7*4(R8) Store resulting FPC flags and DXC +000000000000065C B222 0010 543 IPM R1 Get condition code and program mask +0000000000000660 8810 001C 000000000000001C 544 SRL R1,28 Isolate CC in low order byte +0000000000000664 4210 801F 000000000000001F 545 STC R1,(7*4)+3(,R8) Save CC as low byte of FPCR + 546 * +0000000000000668 B29D F27C 000000000000027C 547 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000066C B399 6018 548 CFDBRA R1,6,FPR8,B'0000' RP, to +inf +0000000000000670 5010 7020 0000000000000020 549 ST R1,8*4(,R7) Store integer-32 result +0000000000000674 B29C 8020 0000000000000020 550 STFPC 8*4(R8) Store resulting FPC flags and DXC + ASMA Ver. 0.2.0 ieee-cvttofix.asm: Test IEEE Convert To Fixed (int-32) 02 Sep 2016 08:48:00 Page 14 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000678 B222 0010 551 IPM R1 Get condition code and program mask +000000000000067C 8810 001C 000000000000001C 552 SRL R1,28 Isolate CC in low order byte +0000000000000680 4210 8023 0000000000000023 553 STC R1,(8*4)+3(,R8) Save CC as low byte of FPCR + 554 * +0000000000000684 B29D F27C 000000000000027C 555 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000688 B399 7018 556 CFDBRA R1,7,FPR8,B'0000' RM, to -inf +000000000000068C 5010 7024 0000000000000024 557 ST R1,9*4(,R7) Store integer-32 result +0000000000000690 B29C 8024 0000000000000024 558 STFPC 9*4(R8) Store resulting FPC flags and DXC +0000000000000694 B222 0010 559 IPM R1 Get condition code and program mask +0000000000000698 8810 001C 000000000000001C 560 SRL R1,28 Isolate CC in low order byte +000000000000069C 4210 8027 0000000000000027 561 STC R1,(9*4)+3(,R8) Save CC as low byte of FPCR + 562 * +00000000000006A0 4130 3008 0000000000000008 563 LA R3,8(,R3) Point to next input values +00000000000006A4 4170 7030 0000000000000030 564 LA R7,12*4(,R7) Point to next int-32 converted value set +00000000000006A8 4180 8030 0000000000000030 565 LA R8,12*4(,R8) Point to next FPCR/CC result area +00000000000006AC 062C 566 BCTR R2,R12 Convert next input value. +00000000000006AE 07FD 567 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvttofix.asm: Test IEEE Convert To Fixed (int-32) 02 Sep 2016 08:48:00 Page 15 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 569 *********************************************************************** + 570 * + 571 * Convert extended BFP to integer-32. A pair of results is generated + 572 * for each input: one with all exceptions non-trappable, and the + 573 * second with all exceptions trappable. The FPCR and condition code + 574 * are stored for each result. + 575 * + 576 *********************************************************************** + + + +00000000000006B0 9823 A000 0000000000000000 578 CFXBR LM R2,R3,0(R10) Get count and address of test input values +00000000000006B4 9878 A008 0000000000000008 579 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000006B8 1222 580 LTR R2,R2 Any test cases? +00000000000006BA 078D 581 BZR R13 ..No, return to caller +00000000000006BC 0DC0 582 BASR R12,0 Set top of loop + 583 * +00000000000006BE 6880 3000 0000000000000000 584 LD FPR8,0(,R3) Get extended BFP test value part 1 +00000000000006C2 68A0 3008 0000000000000008 585 LD FPR10,8(,R3) Get extended BFP test value part 1 +00000000000006C6 B29D F27C 000000000000027C 586 LFPC FPCREGNT Set exceptions non-trappable +00000000000006CA B39A 0018 587 CFXBR R1,0,FPR8 Cvt float in FPR8-FPR10 to Int-32 in GPR1 +00000000000006CE 5010 7000 0000000000000000 588 ST R1,0(,R7) Store integer-32 result +00000000000006D2 B29C 8000 0000000000000000 589 STFPC 0(R8) Store resulting FPC flags and DXC +00000000000006D6 B222 0010 590 IPM R1 Get condition code and program mask +00000000000006DA 8810 001C 000000000000001C 591 SRL R1,28 Isolate CC in low order byte +00000000000006DE 4210 8003 0000000000000003 592 STC R1,3(,R8) Save CC as low byte of FPCR + 593 * +00000000000006E2 B29D F280 0000000000000280 594 LFPC FPCREGTR Set exceptions trappable +00000000000006E6 1711 595 XR R1,R1 Clear any residual result in R1 +00000000000006E8 0410 596 SPM R1 Clear out any residual nz condition code +00000000000006EA B39A 0018 597 CFXBR R1,0,FPR8 Cvt float in FPR8-FPR10 to Int-32 in GPR1 +00000000000006EE 5010 7004 0000000000000004 598 ST R1,4(,R7) Store integer-32 result +00000000000006F2 B29C 8004 0000000000000004 599 STFPC 4(R8) Store resulting FPC flags and DXC +00000000000006F6 B222 0010 600 IPM R1 Get condition code and program mask +00000000000006FA 8810 001C 000000000000001C 601 SRL R1,28 Isolate CC in low order byte +00000000000006FE 4210 8007 0000000000000007 602 STC R1,7(,R8) Save CC as low byte of FPCR + 603 * +0000000000000702 4130 3010 0000000000000010 604 LA R3,16(,R3) Point to next extended BFP input value +0000000000000706 4170 7008 0000000000000008 605 LA R7,8(,R7) Point to next int-32 converted value pair +000000000000070A 4180 8008 0000000000000008 606 LA R8,8(,R8) Point to next FPCR/CC result area +000000000000070E 062C 607 BCTR R2,R12 Convert next input value. +0000000000000710 07FD 608 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvttofix.asm: Test IEEE Convert To Fixed (int-32) 02 Sep 2016 08:48:00 Page 16 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 610 *********************************************************************** + 611 * + 612 * Convert extended BFP to int-32 using each possible rounding mode. + 613 * Ten test results are generated for each input. A 48-byte test result + 614 * section is used to keep results sets aligned on a quad-double word. + 615 * + 616 * The first four tests use rounding modes specified in the FPC with the + 617 * IEEE Inexact exception supressed. SRNM (2-bit) is used for the + 618 * first two FPCR-controlled tests and SRNMB (3-bit) is used for the + 619 * last two To get full coverage of that instruction pair. + 620 * + 621 * The next six results use instruction-specified rounding modes. + 622 * + 623 * The default rounding mode (0 for RNTE) is not tested in this section; + 624 * prior tests used the default rounding mode. RNTE is tested + 625 * explicitly as a rounding mode in this section. + 626 * + 627 *********************************************************************** + + +0000000000000712 9823 A000 0000000000000000 629 CFXBRA LM R2,R3,0(R10) Get count and address of test input values +0000000000000716 9878 A008 0000000000000008 630 LM R7,R8,8(R10) Get address of result area and flag area. +000000000000071A 1222 631 LTR R2,R2 Any test cases? +000000000000071C 078D 632 BZR R13 ..No, return to caller +000000000000071E 0DC0 633 BASR R12,0 Set top of loop + 634 * +0000000000000720 6880 3000 0000000000000000 635 LD FPR8,0(,R3) Get extended BFP test value part 1 +0000000000000724 6820 3008 0000000000000008 636 LD R2,8(,R3) Get extended BFP test value part 2 + 637 * + 638 * Test cases using rounding mode specified in the FPCR + 639 * +0000000000000728 B29D F27C 000000000000027C 640 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000072C B2B8 0001 0000000000000001 641 SRNMB 1 SET FPC to RZ, towards zero. +0000000000000730 B39A 0418 642 CFXBRA R1,0,FPR8,B'0100' FPC ctl'd rounding inexact masked +0000000000000734 5010 7000 0000000000000000 643 ST R1,0*4(,R7) Store integer-32 result +0000000000000738 B29C 8000 0000000000000000 644 STFPC 0(R8) Store resulting FPC flags and DXC +000000000000073C B222 0010 645 IPM R1 Get condition code and program mask +0000000000000740 8810 001C 000000000000001C 646 SRL R1,28 Isolate CC in low order byte +0000000000000744 4210 8003 0000000000000003 647 STC R1,3(,R8) Save CC as low byte of FPCR + 648 * +0000000000000748 B29D F27C 000000000000027C 649 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000074C B2B8 0002 0000000000000002 650 SRNMB 2 SET FPC to RP, to +infinity +0000000000000750 B39A 0418 651 CFXBRA R1,0,FPR8,B'0100' FPC ctl'd rounding inexact masked +0000000000000754 5010 7004 0000000000000004 652 ST R1,1*4(,R7) Store integer-32 result +0000000000000758 B29C 8004 0000000000000004 653 STFPC 1*4(R8) Store resulting FPC flags and DXC +000000000000075C B222 0010 654 IPM R1 Get condition code and program mask +0000000000000760 8810 001C 000000000000001C 655 SRL R1,28 Isolate CC in low order byte +0000000000000764 4210 8007 0000000000000007 656 STC R1,(1*4)+3(,R8) Save CC as low byte of FPCR + 657 * +0000000000000768 B29D F27C 000000000000027C 658 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000076C B2B8 0003 0000000000000003 659 SRNMB 3 SET FPC to RM, to -infinity +0000000000000770 B39A 0418 660 CFXBRA R1,0,FPR8,B'0100' FPC ctl'd rounding inexact masked + ASMA Ver. 0.2.0 ieee-cvttofix.asm: Test IEEE Convert To Fixed (int-32) 02 Sep 2016 08:48:00 Page 17 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000774 5010 7008 0000000000000008 661 ST R1,2*4(,R7) Store integer-32 result +0000000000000778 B29C 8008 0000000000000008 662 STFPC 2*4(R8) Store resulting FPC flags and DXC +000000000000077C B222 0010 663 IPM R1 Get condition code and program mask +0000000000000780 8810 001C 000000000000001C 664 SRL R1,28 Isolate CC in low order byte +0000000000000784 4210 800B 000000000000000B 665 STC R1,(2*4)+3(,R8) Save CC as low byte of FPCR + 666 * +0000000000000788 B29D F27C 000000000000027C 667 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000078C B2B8 0007 0000000000000007 668 SRNMB 7 RFS, Prepare for Shorter Precision +0000000000000790 B39A 0418 669 CFXBRA R1,0,FPR8,B'0100' FPC ctl'd rounding inexact masked +0000000000000794 5010 700C 000000000000000C 670 ST R1,3*4(,R7) Store integer-32 result +0000000000000798 B29C 800C 000000000000000C 671 STFPC 3*4(R8) Store resulting FPC flags and DXC +000000000000079C B222 0010 672 IPM R1 Get condition code and program mask +00000000000007A0 8810 001C 000000000000001C 673 SRL R1,28 Isolate CC in low order byte +00000000000007A4 4210 800F 000000000000000F 674 STC R1,(3*4)+3(,R8) Save CC as low byte of FPCR + 675 * + 676 * Test cases using rounding mode specified in the instruction M3 field + 677 * +00000000000007A8 B29D F27C 000000000000027C 678 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000007AC B39A 1018 679 CFXBRA R1,1,FPR8,B'0000' RNTA, to nearest, ties away +00000000000007B0 5010 7010 0000000000000010 680 ST R1,4*4(,R7) Store integer-32 result +00000000000007B4 B29C 8010 0000000000000010 681 STFPC 4*4(R8) Store resulting FPC flags and DXC +00000000000007B8 B222 0010 682 IPM R1 Get condition code and program mask +00000000000007BC 8810 001C 000000000000001C 683 SRL R1,28 Isolate CC in low order byte +00000000000007C0 4210 8013 0000000000000013 684 STC R1,(4*4)+3(,R8) Save CC as low byte of FPCR + 685 * +00000000000007C4 B29D F27C 000000000000027C 686 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000007C8 B39A 3018 687 CFXBRA R1,3,FPR8,B'0000' RFS, prepare for shorter precision +00000000000007CC 5010 7014 0000000000000014 688 ST R1,5*4(,R7) Store integer-32 result +00000000000007D0 B29C 8014 0000000000000014 689 STFPC 5*4(R8) Store resulting FPC flags and DXC +00000000000007D4 B222 0010 690 IPM R1 Get condition code and program mask +00000000000007D8 8810 001C 000000000000001C 691 SRL R1,28 Isolate CC in low order byte +00000000000007DC 4210 8017 0000000000000017 692 STC R1,(5*4)+3(,R8) Save CC as low byte of FPCR + 693 * +00000000000007E0 B29D F27C 000000000000027C 694 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000007E4 B39A 4018 695 CFXBRA R1,4,FPR8,B'0000' RNTE, to nearest, ties to even +00000000000007E8 5010 7018 0000000000000018 696 ST R1,6*4(,R7) Store integer-32 result +00000000000007EC B29C 8018 0000000000000018 697 STFPC 6*4(R8) Store resulting FPC flags and DXC +00000000000007F0 B222 0010 698 IPM R1 Get condition code and program mask +00000000000007F4 8810 001C 000000000000001C 699 SRL R1,28 Isolate CC in low order byte +00000000000007F8 4210 801B 000000000000001B 700 STC R1,(6*4)+3(,R8) Save CC as low byte of FPCR + 701 * +00000000000007FC B29D F27C 000000000000027C 702 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000800 B39A 5018 703 CFXBRA R1,5,FPR8,B'0000' RZ, toward zero +0000000000000804 5010 701C 000000000000001C 704 ST R1,7*4(,R7) Store integer-32 result +0000000000000808 B29C 801C 000000000000001C 705 STFPC 7*4(R8) Store resulting FPC flags and DXC +000000000000080C B222 0010 706 IPM R1 Get condition code and program mask +0000000000000810 8810 001C 000000000000001C 707 SRL R1,28 Isolate CC in low order byte +0000000000000814 4210 801F 000000000000001F 708 STC R1,(7*4)+3(,R8) Save CC as low byte of FPCR + 709 * +0000000000000818 B29D F27C 000000000000027C 710 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000081C B39A 6018 711 CFXBRA R1,6,FPR8,B'0000' RP, to +inf +0000000000000820 5010 7020 0000000000000020 712 ST R1,8*4(,R7) Store integer-32 result + ASMA Ver. 0.2.0 ieee-cvttofix.asm: Test IEEE Convert To Fixed (int-32) 02 Sep 2016 08:48:00 Page 18 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000824 B29C 8020 0000000000000020 713 STFPC 8*4(R8) Store resulting FPC flags and DXC +0000000000000828 B222 0010 714 IPM R1 Get condition code and program mask +000000000000082C 8810 001C 000000000000001C 715 SRL R1,28 Isolate CC in low order byte +0000000000000830 4210 8023 0000000000000023 716 STC R1,(8*4)+3(,R8) Save CC as low byte of FPCR + 717 * +0000000000000834 B29D F27C 000000000000027C 718 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000838 B39A 7018 719 CFXBRA R1,7,FPR8,B'0000' RM, to -inf +000000000000083C 5010 7024 0000000000000024 720 ST R1,9*4(,R7) Store integer-32 result +0000000000000840 B29C 8024 0000000000000024 721 STFPC 9*4(R8) Store resulting FPC flags and DXC +0000000000000844 B222 0010 722 IPM R1 Get condition code and program mask +0000000000000848 8810 001C 000000000000001C 723 SRL R1,28 Isolate CC in low order byte +000000000000084C 4210 8027 0000000000000027 724 STC R1,(9*4)+3(,R8) Save CC as low byte of FPCR + 725 * +0000000000000850 4130 3010 0000000000000010 726 LA R3,16(,R3) Point to next input value +0000000000000854 4170 7030 0000000000000030 727 LA R7,12*4(,R7) Point to next int-32 converted value set +0000000000000858 4180 8030 0000000000000030 728 LA R8,12*4(,R8) Point to next FPCR/CC result area +000000000000085C 062C 729 BCTR R2,R12 Convert next input value. +000000000000085E 07FD 730 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvttofix.asm: Test IEEE Convert To Fixed (int-32) 02 Sep 2016 08:48:00 Page 19 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 732 *********************************************************************** + 733 * + 734 * Floating point inputs for Convert To Fixed testing. The same test + 735 * values in the appropriate input format are used for short, long, + 736 * and extended format tests. The last four values should generate + 737 * exceptions. + 738 * + 739 *********************************************************************** + + + +0000000000000860 741 SBFPIN DS 0F Inputs for short BFP testing +0000000000000860 3F800000 742 DC X'3F800000' +1.0 +0000000000000864 40000000 743 DC X'40000000' +2.0 +0000000000000868 40800000 744 DC X'40800000' +4.0 +000000000000086C C0000000 745 DC X'C0000000' -2.0 +0000000000000870 7F810000 746 DC X'7F810000' SNaN +0000000000000874 7FC10000 747 DC X'7FC10000' QNaN + 748 * The following two will overflow int-32 regardless of rounding mode +0000000000000878 4F000000 749 DC X'4F000000' +max int-32 + 1. (2,147,483,647 + 1) +000000000000087C CF000001 750 DC X'CF000001' -max int-32 - 2. (-2,147,483,647 - 2) +0000000000000880 4EFFFFFF 751 DC X'4EFFFFFF' Largest short bfp that fits in int-32 + 752 * ..2,147,483,520 = 0x7FFFFF80 + 753 * + 0000000000000024 0000000000000001 754 SBFPCT EQU *-SBFPIN Count of short BFP in list * 4 + 755 * +0000000000000884 756 SBFPINRM DS 0F +0000000000000884 C1180000 757 DC X'C1180000' -9.5 +0000000000000888 C0B00000 758 DC X'C0B00000' -5.5 +000000000000088C C0200000 759 DC X'C0200000' -2.5 +0000000000000890 BFC00000 760 DC X'BFC00000' -1.5 +0000000000000894 BF000000 761 DC X'BF000000' -0.5 +0000000000000898 3F000000 762 DC X'3F000000' +0.5 +000000000000089C 3FC00000 763 DC X'3FC00000' +1.5 +00000000000008A0 40200000 764 DC X'40200000' +2.5 +00000000000008A4 40B00000 765 DC X'40B00000' +5.5 +00000000000008A8 41180000 766 DC X'41180000' +9.5 +00000000000008AC 3F400000 767 DC X'3F400000' +0.75 +00000000000008B0 3E800000 768 DC X'3E800000' +0.25 +00000000000008B4 BF400000 769 DC X'BF400000' -0.75 +00000000000008B8 BE800000 770 DC X'BE800000' -0.25 + 771 * + 772 * There is no short BFP represtation for values between 2,147,483,520 + 773 * and 2,147,483,648, making it difficult to come up with a test case + 774 * that overflows for only some of the rounding modes available. + 775 * + 0000000000000038 0000000000000001 776 SBFPRMCT EQU *-SBFPINRM Count of short BFP in list * 4 + 777 * +00000000000008BC 778 LBFPIN DS 0F Inputs for long BFP testing +00000000000008BC 3FF00000 00000000 779 DC X'3FF0000000000000' +1.0 +00000000000008C4 40000000 00000000 780 DC X'4000000000000000' +2.0 +00000000000008CC 40100000 00000000 781 DC X'4010000000000000' +4.0 + ASMA Ver. 0.2.0 ieee-cvttofix.asm: Test IEEE Convert To Fixed (int-32) 02 Sep 2016 08:48:00 Page 20 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000008D4 C0000000 00000000 782 DC X'C000000000000000' -2.0 +00000000000008DC 7FF01000 00000000 783 DC X'7FF0100000000000' SNaN +00000000000008E4 7FF81000 00000000 784 DC X'7FF8100000000000' QNaN +00000000000008EC 41E00000 00000000 785 DC X'41E0000000000000' +max int-32 + 1 (+2147483647 + 1) +00000000000008F4 C1E00000 00200000 786 DC X'C1E0000000200000' -max int-32 - 2 (-2147483647 - 2) +00000000000008FC 41DFFFFF FFC00000 787 DC X'41DFFFFFFFC00000' Largest long bfp that fits in + 788 * ..int-32: 2,147,483,647 = 0x7FFFFFFF +0000000000000904 41DFFFFF FFE00000 789 DC X'41DFFFFFFFE00000' 2,147,483,647.5 - overflows on + 790 * RNTE; test of traps + 0000000000000050 0000000000000001 791 LBFPCT EQU *-LBFPIN Count of long BFP in list * 8 + 792 * +000000000000090C 793 LBFPINRM DS 0F +000000000000090C C0230000 00000000 794 DC X'C023000000000000' -9.5 +0000000000000914 C0160000 00000000 795 DC X'C016000000000000' -5.5 +000000000000091C C0040000 00000000 796 DC X'C004000000000000' -2.5 +0000000000000924 BFF80000 00000000 797 DC X'BFF8000000000000' -1.5 +000000000000092C BFE00000 00000000 798 DC X'BFE0000000000000' -0.5 +0000000000000934 3FE00000 00000000 799 DC X'3FE0000000000000' +0.5 +000000000000093C 3FF80000 00000000 800 DC X'3FF8000000000000' +1.5 +0000000000000944 40040000 00000000 801 DC X'4004000000000000' +2.5 +000000000000094C 40160000 00000000 802 DC X'4016000000000000' +5.5 +0000000000000954 40230000 00000000 803 DC X'4023000000000000' +9.5 +000000000000095C 3FE80000 00000000 804 DC X'3FE8000000000000' +0.75 +0000000000000964 3FD00000 00000000 805 DC X'3FD0000000000000' +0.25 +000000000000096C BFE80000 00000000 806 DC X'BFE8000000000000' -0.75 +0000000000000974 BFD00000 00000000 807 DC X'BFD0000000000000' -0.25 +000000000000097C 41DFFFFF FFE00000 808 DC X'41DFFFFFFFE00000' 2,147,483,647.5 - overflows on + 809 * some but not all rounding modes + 0000000000000078 0000000000000001 810 LBFPRMCT EQU *-LBFPINRM Count of long BFP in list * 8 + 811 * +0000000000000988 812 XBFPIN DS 0D Inputs for extended BFP testing +0000000000000988 3FFF0000 00000000 813 DC X'3FFF0000000000000000000000000000' +1.0 +0000000000000998 40000000 00000000 814 DC X'40000000000000000000000000000000' +2.0 +00000000000009A8 40010000 00000000 815 DC X'40010000000000000000000000000000' +4.0 +00000000000009B8 C0000000 00000000 816 DC X'C0000000000000000000000000000000' -2.0 +00000000000009C8 7FFF0100 00000000 817 DC X'7FFF0100000000000000000000000000' SNaN +00000000000009D8 7FFF8100 00000000 818 DC X'7FFF8100000000000000000000000000' QNaN +00000000000009E8 401E0000 00000000 819 DC X'401E0000000000000000000000000000' +max int-32 + 1 +00000000000009F8 C01E0000 00020000 820 DC X'C01E0000000200000000000000000000' -max int-32 - 2 +0000000000000A08 401DFFFF FFFC0000 821 DC X'401DFFFFFFFC00000000000000000000' Largest long bfp + 822 * that fits in int-32: 2,147,483,647 = 0x7FFFFFFF +0000000000000A18 401DFFFF FFFE0000 823 DC X'401DFFFFFFFE00000000000000000000' 2,147,483,647.5 + 824 * - overflows on RNTE; test of traps + 00000000000000A0 0000000000000001 825 XBFPCT EQU *-XBFPIN Count of extended BFP in list * 16 + 826 * +0000000000000A28 827 XBFPINRM DS 0D +0000000000000A28 C0023000 00000000 828 DC X'C0023000000000000000000000000000' -9.5 +0000000000000A38 C0016000 00000000 829 DC X'C0016000000000000000000000000000' -5.5 +0000000000000A48 C0004000 00000000 830 DC X'C0004000000000000000000000000000' -2.5 +0000000000000A58 BFFF8000 00000000 831 DC X'BFFF8000000000000000000000000000' -1.5 +0000000000000A68 BFFE0000 00000000 832 DC X'BFFE0000000000000000000000000000' -0.5 +0000000000000A78 3FFE0000 00000000 833 DC X'3FFE0000000000000000000000000000' +0.5 + ASMA Ver. 0.2.0 ieee-cvttofix.asm: Test IEEE Convert To Fixed (int-32) 02 Sep 2016 08:48:00 Page 21 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000A88 3FFF8000 00000000 834 DC X'3FFF8000000000000000000000000000' +1.5 +0000000000000A98 40004000 00000000 835 DC X'40004000000000000000000000000000' +2.5 +0000000000000AA8 40016000 00000000 836 DC X'40016000000000000000000000000000' +5.5 +0000000000000AB8 40023000 00000000 837 DC X'40023000000000000000000000000000' +9.5 +0000000000000AC8 3FFE8000 00000000 838 DC X'3FFE8000000000000000000000000000' +0.75 +0000000000000AD8 3FFD0000 00000000 839 DC X'3FFD0000000000000000000000000000' +0.25 +0000000000000AE8 BFFE8000 00000000 840 DC X'BFFE8000000000000000000000000000' -0.75 +0000000000000AF8 BFFD0000 00000000 841 DC X'BFFD0000000000000000000000000000' -0.25 +0000000000000B08 401DFFFF FFFE0000 842 DC X'401DFFFFFFFE00000000000000000000' 2,147,483,647.5 + 843 * - overflows on some but not all rounding modes + 00000000000000F0 0000000000000001 844 XBFPRMCT EQU *-XBFPINRM Count of extended BFP in list * 16 + 845 * + 846 * Locations for results + 847 * + 0000000000001000 0000000000000000 848 SINTOUT EQU BFPCVTTF+X'1000' uint-32 values from short BFP + 849 * ..9 pairs used, room for 16 + 0000000000001100 0000000000000000 850 SINTFLGS EQU BFPCVTTF+X'1100' FPCR flags and DXC from short BFP + 851 * ..9 pairs used, room for 16 + 0000000000001200 0000000000000000 852 SINTRMO EQU BFPCVTTF+X'1200' Short rounding mode test results + 853 * ..14 sets used, room for 20 + 0000000000001600 0000000000000000 854 SINTRMOF EQU BFPCVTTF+X'1600' Short rounding mode FPCR contents + 855 * ..14 sets used, room for 20 + 856 * + 0000000000002000 0000000000000000 857 LINTOUT EQU BFPCVTTF+X'2000' uint-32 values from long BFP + 858 * ..10 pairs used, room for 16 + 0000000000002100 0000000000000000 859 LINTFLGS EQU BFPCVTTF+X'2100' FPCR flags and DXC from long BFP + 860 * ..10 pairs used, room for 16 + 0000000000002200 0000000000000000 861 LINTRMO EQU BFPCVTTF+X'2200' Long rounding mode test results + 862 * ..14 sets used, room for 20 + 0000000000002600 0000000000000000 863 LINTRMOF EQU BFPCVTTF+X'2600' Long rounding mode FPCR contents + 864 * ..14 sets used, room for 20 + 865 * + 0000000000003000 0000000000000000 866 XINTOUT EQU BFPCVTTF+X'3000' uint-32 values from extended BFP + 867 * ..10 pairs used, room for 16 + 0000000000003100 0000000000000000 868 XINTFLGS EQU BFPCVTTF+X'3100' FPCR flags and DXC from extended BFP + 869 * ..10 pairs used, room for 16 + 0000000000003200 0000000000000000 870 XINTRMO EQU BFPCVTTF+X'3200' Extended rounding mode test results + 871 * ..14 sets used, room for 20 + 0000000000003600 0000000000000000 872 XINTRMOF EQU BFPCVTTF+X'3600' Extended rounding mode FPCR contents + 873 * ..14 sets used, room for 20 + 874 * + 875 * + 0000000000004000 0000000000000000 876 ENDLABL EQU BFPCVTTF+X'4000' + 877 PADCSECT ENDLABL + 878+ MNOTE *,'asma detected; no CSECT padding performed' +0000000000000B18 879 END + ASMA Ver. 0.2.0 ieee-cvttofix.asm: Test IEEE Convert To Fixed (int-32) 02 Sep 2016 08:48:00 Page 22 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +BFPCVTTF J 000000 2840 85 134 137 139 142 150 209 848 850 852 854 857 859 861 863 866 868 870 + 872 876 +CFDBR I 000508 4 417 180 +CFDBRA I 000566 4 467 182 +CFEBR I 000360 4 255 173 +CFEBRA I 0003BE 4 306 175 +CFXBR I 0006B0 4 578 187 +CFXBRA I 000712 4 629 189 +CTLR0 F 000278 4 199 166 167 168 +ENDLABL U 004000 0 876 +EXTDS F 000320 4 222 186 +FPCREGNT X 00027C 4 200 262 316 325 334 343 354 362 370 378 386 394 424 477 486 495 504 515 + 523 531 539 547 555 586 640 649 658 667 678 686 694 702 710 718 +FPCREGTR X 000280 4 201 270 432 594 +FPR0 U 000000 1 105 +FPR1 U 000001 1 106 +FPR10 U 00000A 1 115 585 +FPR11 U 00000B 1 116 +FPR12 U 00000C 1 117 +FPR13 U 00000D 1 118 +FPR14 U 00000E 1 119 +FPR15 U 00000F 1 120 +FPR2 U 000002 1 107 +FPR3 U 000003 1 108 +FPR4 U 000004 1 109 +FPR5 U 000005 1 110 +FPR6 U 000006 1 111 +FPR7 U 000007 1 112 +FPR8 U 000008 1 113 261 263 273 312 318 327 336 345 355 363 371 379 387 395 423 425 435 + 473 479 488 497 506 516 524 532 540 548 556 584 587 597 635 642 651 + 660 669 679 687 695 703 711 719 +FPR9 U 000009 1 114 +HARDWAIT X 000268 8 197 158 +IMAGE 1 000000 2840 0 +LBFPCT U 000050 1 791 217 +LBFPIN F 0008BC 4 778 791 218 +LBFPINRM F 00090C 4 793 810 236 +LBFPRMCT U 000078 1 810 235 +LINTFLGS U 002100 0 859 220 +LINTOUT U 002000 0 857 219 +LINTRMO U 002200 0 861 237 +LINTRMOF U 002600 0 863 238 +LONGS F 000310 4 216 179 +PCINTCD H 00008E 2 135 152 +PCNOTDTA H 00020C 2 155 153 +PCOLDPSW U 000150 0 137 154 +PROGCHK H 000200 2 151 143 +R0 U 000000 1 86 166 168 +R1 U 000001 1 87 263 264 266 267 268 271 272 273 274 276 277 278 318 319 321 322 323 + 327 328 330 331 332 336 337 339 340 341 345 346 348 349 350 355 356 + 358 359 360 363 364 366 367 368 371 372 374 375 376 379 380 382 383 + 384 387 388 390 391 392 395 396 398 399 400 425 426 428 429 430 433 + ASMA Ver. 0.2.0 ieee-cvttofix.asm: Test IEEE Convert To Fixed (int-32) 02 Sep 2016 08:48:00 Page 23 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + + 434 435 436 438 439 440 479 480 482 483 484 488 489 491 492 493 497 + 498 500 501 502 506 507 509 510 511 516 517 519 520 521 524 525 527 + 528 529 532 533 535 536 537 540 541 543 544 545 548 549 551 552 553 + 556 557 559 560 561 587 588 590 591 592 595 596 597 598 600 601 602 + 642 643 645 646 647 651 652 654 655 656 660 661 663 664 665 669 670 + 672 673 674 679 680 682 683 684 687 688 690 691 692 695 696 698 699 + 700 703 704 706 707 708 711 712 714 715 716 719 720 722 723 724 +R10 U 00000A 1 96 172 174 179 181 186 188 255 256 306 307 417 418 467 468 578 579 629 + 630 +R11 U 00000B 1 97 +R12 U 00000C 1 98 259 283 310 405 421 445 471 566 582 607 633 729 +R13 U 00000D 1 99 173 175 180 182 187 189 258 284 309 406 420 446 470 567 581 608 632 + 730 +R14 U 00000E 1 100 156 157 191 192 +R15 U 00000F 1 101 122 +R2 U 000002 1 88 255 257 283 306 308 405 417 419 445 467 469 566 578 580 607 629 631 + 636 729 +R3 U 000003 1 89 255 261 280 306 312 402 417 423 442 467 473 563 578 584 585 604 629 + 635 636 726 +R4 U 000004 1 90 +R5 U 000005 1 91 +R6 U 000006 1 92 +R7 U 000007 1 93 256 264 274 281 307 319 328 337 346 356 364 372 380 388 396 403 418 + 426 436 443 468 480 489 498 507 517 525 533 541 549 557 564 579 588 + 598 605 630 643 652 661 670 680 688 696 704 712 720 727 +R8 U 000008 1 94 256 265 268 275 278 282 307 320 323 329 332 338 341 347 350 357 360 + 365 368 373 376 381 384 389 392 397 400 404 418 427 430 437 440 444 + 468 481 484 490 493 499 502 508 511 518 521 526 529 534 537 542 545 + 550 553 558 561 565 579 589 592 599 602 606 630 644 647 653 656 662 + 665 671 674 681 684 689 692 697 700 705 708 713 716 721 724 728 +R9 U 000009 1 95 +RMEXTDS F 000350 4 240 188 +RMLONGS F 000340 4 234 181 +RMSHORTS F 000330 4 228 174 +SBFPCT U 000024 1 754 211 +SBFPIN F 000860 4 741 754 212 +SBFPINRM F 000884 4 756 776 230 +SBFPRMCT U 000038 1 776 229 +SHORTS F 000300 4 210 172 +SINTFLGS U 001100 0 850 214 +SINTOUT U 001000 0 848 213 +SINTRMO U 001200 0 852 231 +SINTRMOF U 001600 0 854 232 +START I 000214 4 166 140 +WAITPSW X 000258 8 196 193 +XBFPCT U 0000A0 1 825 223 +XBFPIN D 000988 8 812 825 224 +XBFPINRM D 000A28 8 827 844 242 +XBFPRMCT U 0000F0 1 844 241 +XINTFLGS U 003100 0 868 226 +XINTOUT U 003000 0 866 225 +XINTRMO U 003200 0 870 243 + ASMA Ver. 0.2.0 ieee-cvttofix.asm: Test IEEE Convert To Fixed (int-32) 02 Sep 2016 08:48:00 Page 24 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +XINTRMOF U 003600 0 872 244 + ASMA Ver. 0.2.0 ieee-cvttofix.asm: Test IEEE Convert To Fixed (int-32) 02 Sep 2016 08:48:00 Page 25 + + MACRO DEFN REFERENCES + +PADCSECT 60 877 + ASMA Ver. 0.2.0 ieee-cvttofix.asm: Test IEEE Convert To Fixed (int-32) 02 Sep 2016 08:48:00 Page 26 + + DESC SYMBOL SIZE POS ADDR + +Entry: 0 + +Image IMAGE 2840 000-B17 000-B17 + Region 2840 000-B17 000-B17 + CSECT BFPCVTTF 2840 000-B17 000-B17 + ASMA Ver. 0.2.0 ieee-cvttofix.asm: Test IEEE Convert To Fixed (int-32) 02 Sep 2016 08:48:00 Page 27 + + STMT FILE NAME + +1 C:\Users\srorso\Documents\GitHub\hyperion\tests\bfp-006-cvttofix.asm + + +** NO ERRORS FOUND ** + +[878] MNOTE *,asma detected; no CSECT padding performed + \ No newline at end of file diff --git a/tests/bfp-006-cvttofix.tst b/tests/bfp-006-cvttofix.tst new file mode 100644 index 000000000..9663d0d1f --- /dev/null +++ b/tests/bfp-006-cvttofix.tst @@ -0,0 +1,739 @@ +*Testcase bfp-006-cvttofix.tst: CFEBR, CFEBRA, CFDBR, CFDBRA, CFXBR, CFXBRA + +#Testcase bfp-006-cvttofix.tst: IEEE Convert To Fixed +#..Includes CONVERT TO FIXED 32 (6). Tests traps, exceptions, +#..results from different rounding modes, and NaN propagation. + +sysclear +archmode esame + +# +# Following suppresses logging of program checks. This test program, as part +# of its normal operation, generates 16 program check messages that have no +# value in the validation process. (The messages, not the program checks.) +# +ostailor quiet + +loadcore "$(testpath)/bfp-006-cvttofix.core" + +runtest 1.0 + +ostailor null # restore messages for subsequent tests + +# Convert short BFP to integer-32 results +*Compare +r 1000.10 +*Want "CFEBR result pairs 1-2" 00000001 00000001 00000002 00000002 +r 1010.10 +*Want "CFEBR result pairs 3-4" 00000004 00000004 FFFFFFFE FFFFFFFE +r 1020.10 +*Want "CFEBR result pairs 5-6" 80000000 00000000 80000000 00000000 +r 1030.10 +*Want "CFEBR result pairs 7-8" 7FFFFFFF 00000000 80000000 00000000 +r 1040.08 +*Want "CFEBR result pair 9" 7FFFFF80 7FFFFF80 + +# Convert short BFP to integer-32 FPCR contents +*Compare +r 1100.10 +*Want "CFEBR FPCR pairs 1-2" 00000002 F8000002 00000002 F8000002 +r 1110.10 +*Want "CFEBR FPCR pairs 3-4" 00000002 F8000002 00000001 F8000001 +r 1120.10 +*Want "CFEBR FPCR pairs 5-6" 00880003 F8008000 00880003 F8008000 +r 1130.10 +*Want "CFEBR FPCR pairs 7-8" 00880003 F8008000 00880003 F8008000 +r 1140.08 +*Want "CFEBR FPCR pair 9" 00000002 F8000002 + +# Short BFP rounding mode tests - results from rounding +*Compare +r 1200.10 # RZ, RP, RM, RFS +*Want "CFEBRA -9.5 FPCR modes 1-3, 7" FFFFFFF7 FFFFFFF7 FFFFFFF6 FFFFFFF7 +r 1210.10 # RNTA, RFS, RNTE, RZ +*Want "CFEBRA -9.5 M3 modes 1, 3-5" FFFFFFF6 FFFFFFF7 FFFFFFF6 FFFFFFF7 +r 1220.08 # RP, RM +*Want "CFEBRA -9.5 M3 modes 6, 7" FFFFFFF7 FFFFFFF6 + +r 1230.10 # RZ, RP, RM, RFS +*Want "CFEBRA -5.5 FPCR modes 1-3, 7" FFFFFFFB FFFFFFFB FFFFFFFA FFFFFFFB +r 1240.10 # RNTA, RFS, RNTE, RZ +*Want "CFEBRA -5.5 M3 modes 1, 3-5" FFFFFFFA FFFFFFFB FFFFFFFA FFFFFFFB +r 1250.08 # RP, RM +*Want "CFEBRA -5.5 M3 modes 6, 7" FFFFFFFB FFFFFFFA + +r 1260.10 # RZ, RP, RM, RFS +*Want "CFEBRA -2.5 FPCR modes 1-3, 7" FFFFFFFE FFFFFFFE FFFFFFFD FFFFFFFD +r 1270.10 # RNTA, RFS, RNTE, RZ +*Want "CFEBRA -2.5 M3 modes 1, 3-5" FFFFFFFD FFFFFFFD FFFFFFFE FFFFFFFE +r 1280.08 # RP, RM +*Want "CFEBRA -2.5 M3 modes 6, 7" FFFFFFFE FFFFFFFD + +r 1290.10 # RZ, RP, RM, RFS +*Want "CFEBRA -1.5 FPCR modes 1-3, 7" FFFFFFFF FFFFFFFF FFFFFFFE FFFFFFFF +r 12A0.10 # RNTA, RFS, RNTE, RZ +*Want "CFEBRA -1.5 M3 modes 1, 3-5" FFFFFFFE FFFFFFFF FFFFFFFE FFFFFFFF +r 12B0.08 # RP, RM +*Want "CFEBRA -1.5 M3 modes 6, 7" FFFFFFFF FFFFFFFE + +r 12C0.10 # RZ, RP, RM, RFS +*Want "CFEBRA -0.5 FPCR modes 1-3, 7" 00000000 00000000 FFFFFFFF FFFFFFFF +r 12D0.10 # RNTA, RFS, RNTE, RZ +*Want "CFEBRA -0.5 M3 modes 1, 3-5" FFFFFFFF FFFFFFFF 00000000 00000000 +r 12E0.08 # RP, RM +*Want "CFEBRA -0.5 M3 modes 6, 7" 00000000 FFFFFFFF + +r 12F0.10 # RZ, RP, RM, RFS +*Want "CFEBRA +0.5 FPCR modes 1-3, 7" 00000000 00000001 00000000 00000001 +r 1300.10 # RNTA, RFS, RNTE, RZ +*Want "CFEBRA +0.5 M3 modes 1, 3-5" 00000001 00000001 00000000 00000000 +r 1310.08 # RP, RM +*Want "CFEBRA +0.5 M3 modes 6, 7" 00000001 00000000 + +r 1320.10 # RZ, RP, RM, RFS +*Want "CFEBRA +1.5 FPCR modes 1-3, 7" 00000001 00000002 00000001 00000001 +r 1330.10 # RNTA, RFS, RNTE, RZ +*Want "CFEBRA +1.5 M3 modes 1, 3-5" 00000002 00000001 00000002 00000001 +r 1340.08 # RP, RM +*Want "CFEBRA +1.5 M3 modes 6, 7" 00000002 00000001 + +r 1350.10 # RZ, RP, RM, RFS +*Want "CFEBRA +2.5 FPCR modes 1-3, 7" 00000002 00000003 00000002 00000003 +r 1360.10 # RNTA, RFS, RNTE, RZ +*Want "CFEBRA +2.5 M3 modes 1, 3-5" 00000003 00000003 00000002 00000002 +r 1370.08 # RP, RM +*Want "CFEBRA +2.5 M3 modes 6, 7" 00000003 00000002 + +r 1380.10 # RZ, RP, RM, RFS +*Want "CFEBRA +5.5 FPCR modes 1-3, 7" 00000005 00000006 00000005 00000005 +r 1390.10 # RNTA, RFS, RNTE, RZ +*Want "CFEBRA +5.5 M3 modes 1, 3-5" 00000006 00000005 00000006 00000005 +r 13A0.08 # RP, RM +*Want "CFEBRA +5.5 M3 modes 6, 7" 00000006 00000005 + +r 13B0.10 # RZ, RP, RM, RFS +*Want "CFEBRA +9.5 FPCR modes 1-3, 7" 00000009 0000000A 00000009 00000009 +r 13C0.10 # RNTA, RFS, RNTE, RZ +*Want "CFEBRA +9.5 M3 modes 1, 3-5" 0000000A 00000009 0000000A 00000009 +r 13D0.08 # RP, RM +*Want "CFEBRA +9.5 M3 modes 6, 7" 0000000A 00000009 + +r 13E0.10 # RZ, RP, RM, RFS +*Want "CFEBRA +0.75 FPCR modes 1-3, 7" 00000000 00000001 00000000 00000001 +r 13F0.10 # RNTA, RFS, RNTE, RZ +*Want "CFEBRA +0.75 M3 modes 1, 3-5" 00000001 00000001 00000001 00000000 +r 1400.08 # RP, RM +*Want "CFEBRA +0.75 M3 modes 6, 7" 00000001 00000000 + +r 1410.10 # RZ, RP, RM, RFS +*Want "CFEBRA +0.25 FPCR modes 1-3, 7" 00000000 00000001 00000000 00000001 +r 1420.10 # RNTA, RFS, RNTE, RZ +*Want "CFEBRA +0.25 M3 modes 1, 3-5" 00000000 00000001 00000000 00000000 +r 1430.08 # RP, RM +*Want "CFEBRA +0.25 M3 modes 6, 7" 00000001 00000000 + +r 1440.10 # RZ, RP, RM, RFS +*Want "CFEBRA -0.75 FPCR modes 1-3, 7" 00000000 00000000 FFFFFFFF FFFFFFFF +r 1450.10 # RNTA, RFS, RNTE, RZ +*Want "CFEBRA -0.75 M3 modes 1, 3-5" FFFFFFFF FFFFFFFF FFFFFFFF 00000000 +r 1460.08 # RP, RM +*Want "CFEBRA -0.75 M3 modes 6, 7" 00000000 FFFFFFFF + +r 1470.10 # RZ, RP, RM, RFS +*Want "CFEBRA -0.25 FPCR modes 1-3, 7" 00000000 00000000 FFFFFFFF FFFFFFFF +r 1480.10 # RNTA, RFS, RNTE, RZ +*Want "CFEBRA -0.25 M3 modes 1, 3-5" 00000000 FFFFFFFF 00000000 00000000 +r 1490.08 # RP, RM +*Want "CFEBRA -0.25 M3 modes 6, 7" 00000000 FFFFFFFF + + +# rounding mode tests - short BFP - FPCR contents with cc in last byte +*Compare +r 1600.10 +*Want "CFEBRA -9.5 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 1610.10 +*Want "CFEBRA -9.5 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 1620.08 +*Want "CFEBRA -9.5 M3 modes 6, 7 FPCR" 00080001 00080001 + +r 1630.10 +*Want "CFEBRA -5.5 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 1640.10 +*Want "CFEBRA -5.5 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 1650.08 +*Want "CFEBRA -5.5 M3 modes 6, 7 FPCR" 00080001 00080001 + +r 1660.10 +*Want "CFEBRA -2.5 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 1670.10 +*Want "CFEBRA -2.5 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 1680.08 +*Want "CFEBRA -2.5 M3 modes 6, 7 FPCR" 00080001 00080001 + +r 1690.10 +*Want "CFEBRA -1.5 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 16A0.10 +*Want "CFEBRA -1.5 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 16B0.08 +*Want "CFEBRA -1.5 M3 modes 6, 7 FPCR" 00080001 00080001 + +r 16C0.10 +*Want "CFEBRA -0.5 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 16D0.10 +*Want "CFEBRA -0.5 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 16E0.08 +*Want "CFEBRA -0.5 M3 modes 6, 7 FPCR" 00080001 00080001 + +r 16F0.10 +*Want "CFEBRA +0.5 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 1700.10 +*Want "CFEBRA +0.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 1710.08 +*Want "CFEBRA +0.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 1720.10 +*Want "CFEBRA +1.5 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 1730.10 +*Want "CFEBRA +1.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 1740.08 +*Want "CFEBRA +1.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 1750.10 +*Want "CFEBRA +2.5 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 1760.10 +*Want "CFEBRA +2.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 1770.08 +*Want "CFEBRA +2.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 1780.10 +*Want "CFEBRA +5.5 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 1790.10 +*Want "CFEBRA +5.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 17A0.08 +*Want "CFEBRA +5.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 17B0.10 +*Want "CFEBRA +9.5 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 17C0.10 +*Want "CFEBRA +9.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 17D0.08 +*Want "CFEBRA +9.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 17E0.10 +*Want "CFEBRA +0.75 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 17F0.10 +*Want "CFEBRA +0.75 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 1800.08 +*Want "CFEBRA +0.75 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 1810.10 +*Want "CFEBRA +0.25 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 1820.10 +*Want "CFEBRA +0.25 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 1830.08 +*Want "CFEBRA +0.25 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 1840.10 +*Want "CFEBRA -0.75 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 1850.10 +*Want "CFEBRA -0.75 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 1860.08 +*Want "CFEBRA -0.75 M3 modes 6, 7 FPCR" 00080001 00080001 + +r 1870.10 +*Want "CFEBRA -0.25 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 1880.10 +*Want "CFEBRA -0.25 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 1890.08 +*Want "CFEBRA -0.25 M3 modes 6, 7 FPCR" 00080001 00080001 + + +# Long BFP converted to integer-32 - results +*Compare +r 2000.10 +*Want "CFDBR result pairs 1-2" 00000001 00000001 00000002 00000002 +r 2010.10 +*Want "CFDBR result pairs 3-4" 00000004 00000004 FFFFFFFE FFFFFFFE +r 2020.10 +*Want "CFDBR result pairs 5-6" 80000000 00000000 80000000 00000000 +r 2030.10 +*Want "CFDBR result pairs 7-8" 7FFFFFFF 00000000 80000000 00000000 +r 2040.10 +*Want "CFDBR result pairs 9-10" 7FFFFFFF 7FFFFFFF 7FFFFFFF 00000000 + +# Long BFP converted to integer-32 - FPCR contents +*Compare +r 2100.10 +*Want "CFDBR FPCR pairs 1-2" 00000002 F8000002 00000002 F8000002 +r 2110.10 +*Want "CFDBR FPCR pairs 3-4" 00000002 F8000002 00000001 F8000001 +r 2120.10 +*Want "CFDBR FPCR pairs 5-6" 00880003 F8008000 00880003 F8008000 +r 2130.10 +*Want "CFDBR FPCR pairs 7-8" 00880003 F8008000 00880003 F8008000 +r 2140.10 +*Want "CFDBR FPCR pairs 9-10" 00000002 F8000002 00880003 F8008000 + + +# rounding mode tests - long BFP - results from rounding +*Compare +r 2200.10 # RZ, RP, RM, RFS +*Want "CFDBRA -9.5 FPCR modes 1-3, 7" FFFFFFF7 FFFFFFF7 FFFFFFF6 FFFFFFF7 +r 2210.10 # RNTA, RFS, RNTE, RZ +*Want "CFDBRA -9.5 M3 modes 1, 3-5" FFFFFFF6 FFFFFFF7 FFFFFFF6 FFFFFFF7 +r 2220.08 # RP, RM +*Want "CFDBRA -9.5 M3 modes 6, 7" FFFFFFF7 FFFFFFF6 + +r 2230.10 # RZ, RP, RM, RFS +*Want "CFDBRA -5.5 FPCR modes 1-3, 7" FFFFFFFB FFFFFFFB FFFFFFFA FFFFFFFB +r 2240.10 # RNTA, RFS, RNTE, RZ +*Want "CFDBRA -5.5 M3 modes 1, 3-5" FFFFFFFA FFFFFFFB FFFFFFFA FFFFFFFB +r 2250.08 # RP, RM +*Want "CFDBRA -5.5 M3 modes 6, 7" FFFFFFFB FFFFFFFA + +r 2260.10 # RZ, RP, RM, RFS +*Want "CFDBRA -2.5 FPCR modes 1-3, 7" FFFFFFFE FFFFFFFE FFFFFFFD FFFFFFFD +r 2270.10 # RNTA, RFS, RNTE, RZ +*Want "CFDBRA -2.5 M3 modes 1, 3-5" FFFFFFFD FFFFFFFD FFFFFFFE FFFFFFFE +r 2280.08 # RP, RM +*Want "CFDBRA -2.5 M3 modes 6, 7" FFFFFFFE FFFFFFFD + +r 2290.10 # RZ, RP, RM, RFS +*Want "CFDBRA -1.5 FPCR modes 1-3, 7" FFFFFFFF FFFFFFFF FFFFFFFE FFFFFFFF +r 22A0.10 # RNTA, RFS, RNTE, RZ +*Want "CFDBRA -1.5 M3 modes 1, 3-5" FFFFFFFE FFFFFFFF FFFFFFFE FFFFFFFF +r 22B0.08 # RP, RM +*Want "CFDBRA -1.5 M3 modes 6, 7" FFFFFFFF FFFFFFFE + +r 22C0.10 # RZ, RP, RM, RFS +*Want "CFDBRA -0.5 FPCR modes 1-3, 7" 00000000 00000000 FFFFFFFF FFFFFFFF +r 22D0.10 # RNTA, RFS, RNTE, RZ +*Want "CFDBRA -0.5 M3 modes 1, 3-5" FFFFFFFF FFFFFFFF 00000000 00000000 +r 22E0.08 # RP, RM +*Want "CFDBRA -0.5 M3 modes 6, 7" 00000000 FFFFFFFF + +r 22F0.10 # RZ, RP, RM, RFS +*Want "CFDBRA +0.5 FPCR modes 1-3, 7" 00000000 00000001 00000000 00000001 +r 2300.10 # RNTA, RFS, RNTE, RZ +*Want "CFDBRA +0.5 M3 modes 1, 3-5" 00000001 00000001 00000000 00000000 +r 2310.08 # RP, RM +*Want "CFDBRA +0.5 M3 modes 6, 7" 00000001 00000000 + +r 2320.10 # RZ, RP, RM, RFS +*Want "CFDBRA +1.5 FPCR modes 1-3, 7" 00000001 00000002 00000001 00000001 +r 2330.10 # RNTA, RFS, RNTE, RZ +*Want "CFDBRA +1.5 M3 modes 1, 3-5" 00000002 00000001 00000002 00000001 +r 2340.08 # RP, RM +*Want "CFDBRA +1.5 M3 modes 6, 7" 00000002 00000001 + +r 2350.10 # RZ, RP, RM, RFS +*Want "CFDBRA +2.5 FPCR modes 1-3, 7" 00000002 00000003 00000002 00000003 +r 2360.10 # RNTA, RFS, RNTE, RZ +*Want "CFDBRA +2.5 M3 modes 1, 3-5" 00000003 00000003 00000002 00000002 +r 2370.08 # RP, RM +*Want "CFDBRA +2.5 M3 modes 6, 7" 00000003 00000002 + +r 2380.10 # RZ, RP, RM, RFS +*Want "CFDBRA +5.5 FPCR modes 1-3, 7" 00000005 00000006 00000005 00000005 +r 2390.10 # RNTA, RFS, RNTE, RZ +*Want "CFDBRA +5.5 M3 modes 1, 3-5" 00000006 00000005 00000006 00000005 +r 23A0.08 # RP, RM +*Want "CFDBRA +5.5 M3 modes 6, 7" 00000006 00000005 + +r 23B0.10 # RZ, RP, RM, RFS +*Want "CFDBRA +9.5 FPCR modes 1-3, 7" 00000009 0000000A 00000009 00000009 +r 23C0.10 # RNTA, RFS, RNTE, RZ +*Want "CFDBRA +9.5 M3 modes 1, 3-5" 0000000A 00000009 0000000A 00000009 +r 23D0.08 # RP, RM +*Want "CFDBRA +9.5 M3 modes 6, 7" 0000000A 00000009 + +r 23E0.10 # RZ, RP, RM, RFS +*Want "CFDBRA +0.75 FPCR modes 1-3, 7" 00000000 00000001 00000000 00000001 +r 23F0.10 # RNTA, RFS, RNTE, RZ +*Want "CFDBRA +0.75 M3 modes 1, 3-5" 00000001 00000001 00000001 00000000 +r 2400.08 # RP, RM +*Want "CFDBRA +0.75 M3 modes 6, 7" 00000001 00000000 + +r 2410.10 # RZ, RP, RM, RFS +*Want "CFDBRA +0.25 FPCR modes 1-3, 7" 00000000 00000001 00000000 00000001 +r 2420.10 # RNTA, RFS, RNTE, RZ +*Want "CFDBRA +0.25 M3 modes 1, 3-5" 00000000 00000001 00000000 00000000 +r 2430.08 # RP, RM +*Want "CFDBRA +0.25 M3 modes 6, 7" 00000001 00000000 + +r 2440.10 # RZ, RP, RM, RFS +*Want "CFDBRA -0.75 FPCR modes 1-3, 7" 00000000 00000000 FFFFFFFF FFFFFFFF +r 2450.10 # RNTA, RFS, RNTE, RZ +*Want "CFDBRA -0.75 M3 modes 1, 3-5" FFFFFFFF FFFFFFFF FFFFFFFF 00000000 +r 2460.08 # RP, RM +*Want "CFDBRA -0.75 M3 modes 6, 7" 00000000 FFFFFFFF + +r 2470.10 # RZ, RP, RM, RFS +*Want "CFDBRA -0.25 FPCR modes 1-3, 7" 00000000 00000000 FFFFFFFF FFFFFFFF +r 2480.10 # RNTA, RFS, RNTE, RZ +*Want "CFDBRA -0.25 M3 modes 1, 3-5" 00000000 FFFFFFFF 00000000 00000000 +r 2490.08 # RP, RM +*Want "CFDBRA -0.25 M3 modes 6, 7" 00000000 FFFFFFFF + +r 24A0.10 # RZ, RP, RM, RFS +*Want "CFDBRA max+0.5 FPCR modes 1-3, 7" 7FFFFFFF 7FFFFFFF 7FFFFFFF 7FFFFFFF +r 24B0.10 # RNTA, RFS, RNTE, RZ +*Want "CFDBRA max+0.5 M3 modes 1, 3-5" 7FFFFFFF 7FFFFFFF 7FFFFFFF 7FFFFFFF +r 24C0.08 # RP, RM +*Want "CFDBRA max+0.5 M3 modes 6, 7" 7FFFFFFF 7FFFFFFF + + + +# rounding mode tests - long BFP - FPCR contents with cc in last byte +*Compare +r 2600.10 +*Want "CFDBRA -9.5 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 2610.10 +*Want "CFDBRA -9.5 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 2620.08 +*Want "CFDBRA -9.5 M3 modes 6, 7 FPCR" 00080001 00080001 + +r 2630.10 +*Want "CFDBRA -5.5 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 2640.10 +*Want "CFDBRA -5.5 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 2650.08 +*Want "CFDBRA -5.5 M3 modes 6, 7 FPCR" 00080001 00080001 + +r 2660.10 +*Want "CFDBRA -2.5 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 2670.10 +*Want "CFDBRA -2.5 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 2680.08 +*Want "CFDBRA -2.5 M3 modes 6, 7 FPCR" 00080001 00080001 + +r 2690.10 +*Want "CFDBRA -1.5 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 26A0.10 +*Want "CFDBRA -1.5 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 26B0.08 +*Want "CFDBRA -1.5 M3 modes 6, 7 FPCR" 00080001 00080001 + +r 26C0.10 +*Want "CFDBRA -0.5 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 26D0.10 +*Want "CFDBRA -0.5 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 26E0.08 +*Want "CFDBRA -0.5 M3 modes 6, 7 FPCR" 00080001 00080001 + +r 26F0.10 +*Want "CFDBRA +0.5 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 2700.10 +*Want "CFDBRA +0.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 2710.08 +*Want "CFDBRA +0.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 2720.10 +*Want "CFDBRA +1.5 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 2730.10 +*Want "CFDBRA +1.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 2740.08 +*Want "CFDBRA +1.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 2750.10 +*Want "CFDBRA +2.5 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 2760.10 +*Want "CFDBRA +2.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 2770.08 +*Want "CFDBRA +2.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 2780.10 +*Want "CFDBRA +5.5 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 2790.10 +*Want "CFDBRA +5.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 27A0.08 +*Want "CFDBRA +5.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 27B0.10 +*Want "CFDBRA +9.5 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 27C0.10 +*Want "CFDBRA +9.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 27D0.08 +*Want "CFDBRA +9.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 27E0.10 +*Want "CFDBRA +0.75 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 27F0.10 +*Want "CFDBRA +0.75 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 2800.08 +*Want "CFDBRA +0.75 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 2810.10 +*Want "CFDBRA +0.25 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 2820.10 +*Want "CFDBRA +0.25 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 2830.08 +*Want "CFDBRA +0.25 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 2840.10 +*Want "CFDBRA -0.75 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 2850.10 +*Want "CFDBRA -0.75 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 2860.08 +*Want "CFDBRA -0.75 M3 modes 6, 7 FPCR" 00080001 00080001 + +r 2870.10 +*Want "CFDBRA -0.25 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 2880.10 +*Want "CFDBRA -0.25 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 2890.08 +*Want "CFDBRA -0.25 M3 modes 6, 7 FPCR" 00080001 00080001 + +r 28A0.10 +*Want "CFDBRA max+0.5 FPCR modes 1-3, 7 FPCR" 00000002 00800003 00000002 00000002 +r 28B0.10 +*Want "CFDBRA max+0.5 M3 modes 1, 3-5 FPCR" 00880003 00080002 00880003 00080002 +r 28C0.08 +*Want "CFDBRA max+0.5 M3 modes 6, 7 FPCR" 00880003 00080002 + + + +# Extended BFP to integer-32 - results +*Compare +r 3000.10 +*Want "CFXBR result pairs 1-2" 00000001 00000001 00000002 00000002 +r 3010.10 +*Want "CFXBR result pairs 3-4" 00000004 00000004 FFFFFFFE FFFFFFFE +r 3020.10 +*Want "CFXBR result pairs 5-6" 80000000 00000000 80000000 00000000 +r 2030.10 +*Want "CFXBR result pairs 7-8" 7FFFFFFF 00000000 80000000 00000000 +r 2040.10 +*Want "CFXBR result pairs 9-10" 7FFFFFFF 7FFFFFFF 7FFFFFFF 00000000 + +# Extended BFP to integer-32 - FPCR contents +*Compare +r 3100.10 +*Want "CFXBR FPCR pairs 1-2" 00000002 F8000002 00000002 F8000002 +r 3110.10 +*Want "CFXBR FPCR pairs 3-4" 00000002 F8000002 00000001 F8000001 +r 3120.10 +*Want "CFXBR FPCR pairs 5-6" 00880003 F8008000 00880003 F8008000 +r 3130.10 +*Want "CFXBR FPCR pairs 7-8" 00880003 F8008000 00880003 F8008000 +r 3140.10 +*Want "CFXBR FPCR pairs 9-10" 00000002 F8000002 00880003 F8008000 + + +# rounding mode tests - extended BFP - results from rounding +*Compare +r 3200.10 # RZ, RP, RM, RFS +*Want "CFXBRA -9.5 FPCR modes 1-3, 7" FFFFFFF7 FFFFFFF7 FFFFFFF6 FFFFFFF7 +r 3210.10 # RNTA, RFS, RNTE, RZ +*Want "CFXBRA -9.5 M3 modes 1, 3-5" FFFFFFF6 FFFFFFF7 FFFFFFF6 FFFFFFF7 +r 3220.08 # RP, RM +*Want "CFXBRA -9.5 M3 modes 6, 7" FFFFFFF7 FFFFFFF6 + +r 3230.10 # RZ, RP, RM, RFS +*Want "CFXBRA -5.5 FPCR modes 1-3, 7" FFFFFFFB FFFFFFFB FFFFFFFA FFFFFFFB +r 3240.10 # RNTA, RFS, RNTE, RZ +*Want "CFXBRA -5.5 M3 modes 1, 3-5" FFFFFFFA FFFFFFFB FFFFFFFA FFFFFFFB +r 3250.08 # RP, RM +*Want "CFXBRA -5.5 M3 modes 6, 7" FFFFFFFB FFFFFFFA + +r 3260.10 # RZ, RP, RM, RFS +*Want "CFXBRA -2.5 FPCR modes 1-3, 7" FFFFFFFE FFFFFFFE FFFFFFFD FFFFFFFD +r 3270.10 # RNTA, RFS, RNTE, RZ +*Want "CFXBRA -2.5 M3 modes 1, 3-5" FFFFFFFD FFFFFFFD FFFFFFFE FFFFFFFE +r 3280.08 # RP, RM +*Want "CFXBRA -2.5 M3 modes 6, 7" FFFFFFFE FFFFFFFD + +r 3290.10 # RZ, RP, RM, RFS +*Want "CFXBRA -1.5 FPCR modes 1-3, 7" FFFFFFFF FFFFFFFF FFFFFFFE FFFFFFFF +r 32A0.10 # RNTA, RFS, RNTE, RZ +*Want "CFXBRA -1.5 M3 modes 1, 3-5" FFFFFFFE FFFFFFFF FFFFFFFE FFFFFFFF +r 32B0.08 # RP, RM +*Want "CFXBRA -1.5 M3 modes 6, 7" FFFFFFFF FFFFFFFE + +r 32C0.10 # RZ, RP, RM, RFS +*Want "CFXBRA -0.5 FPCR modes 1-3, 7" 00000000 00000000 FFFFFFFF FFFFFFFF +r 32D0.10 # RNTA, RFS, RNTE, RZ +*Want "CFXBRA -0.5 M3 modes 1, 3-5" FFFFFFFF FFFFFFFF 00000000 00000000 +r 32E0.08 # RP, RM +*Want "CFXBRA -0.5 M3 modes 6, 7" 00000000 FFFFFFFF + +r 32F0.10 # RZ, RP, RM, RFS +*Want "CFXBRA +0.5 FPCR modes 1-3, 7" 00000000 00000001 00000000 00000001 +r 3300.10 # RNTA, RFS, RNTE, RZ +*Want "CFXBRA +0.5 M3 modes 1, 3-5" 00000001 00000001 00000000 00000000 +r 3310.08 # RP, RM +*Want "CFXBRA +0.5 M3 modes 6, 7" 00000001 00000000 + +r 3320.10 # RZ, RP, RM, RFS +*Want "CFXBRA +1.5 FPCR modes 1-3, 7" 00000001 00000002 00000001 00000001 +r 3330.10 # RNTA, RFS, RNTE, RZ +*Want "CFXBRA +1.5 M3 modes 1, 3-5" 00000002 00000001 00000002 00000001 +r 3340.08 # RP, RM +*Want "CFXBRA +1.5 M3 modes 6, 7" 00000002 00000001 + +r 3350.10 # RZ, RP, RM, RFS +*Want "CFXBRA +2.5 FPCR modes 1-3, 7" 00000002 00000003 00000002 00000003 +r 3360.10 # RNTA, RFS, RNTE, RZ +*Want "CFXBRA +2.5 M3 modes 1, 3-5" 00000003 00000003 00000002 00000002 +r 3370.08 # RP, RM +*Want "CFXBRA +2.5 M3 modes 6, 7" 00000003 00000002 + +r 3380.10 # RZ, RP, RM, RFS +*Want "CFXBRA +5.5 FPCR modes 1-3, 7" 00000005 00000006 00000005 00000005 +r 3390.10 # RNTA, RFS, RNTE, RZ +*Want "CFXBRA +5.5 M3 modes 1, 3-5" 00000006 00000005 00000006 00000005 +r 33A0.08 # RP, RM +*Want "CFXBRA +5.5 M3 modes 6, 7" 00000006 00000005 + +r 33B0.10 # RZ, RP, RM, RFS +*Want "CFXBRA +9.5 FPCR modes 1-3, 7" 00000009 0000000A 00000009 00000009 +r 33C0.10 # RNTA, RFS, RNTE, RZ +*Want "CFXBRA +9.5 M3 modes 1, 3-5" 0000000A 00000009 0000000A 00000009 +r 33D0.08 # RP, RM +*Want "CFXBRA +9.5 M3 modes 6, 7" 0000000A 00000009 + +r 33E0.10 # RZ, RP, RM, RFS +*Want "CFXBRA +0.75 FPCR modes 1-3, 7" 00000000 00000001 00000000 00000001 +r 33F0.10 # RNTA, RFS, RNTE, RZ +*Want "CFXBRA +0.75 M3 modes 1, 3-5" 00000001 00000001 00000001 00000000 +r 3400.08 # RP, RM +*Want "CFXBRA +0.75 M3 modes 6, 7" 00000001 00000000 + +r 3410.10 # RZ, RP, RM, RFS +*Want "CFXBRA +0.25 FPCR modes 1-3, 7" 00000000 00000001 00000000 00000001 +r 3420.10 # RNTA, RFS, RNTE, RZ +*Want "CFXBRA +0.25 M3 modes 1, 3-5" 00000000 00000001 00000000 00000000 +r 3430.08 # RP, RM +*Want "CFXBRA +0.25 M3 modes 6, 7" 00000001 00000000 + +r 3440.10 # RZ, RP, RM, RFS +*Want "CFXBRA -0.75 FPCR modes 1-3, 7" 00000000 00000000 FFFFFFFF FFFFFFFF +r 3450.10 # RNTA, RFS, RNTE, RZ +*Want "CFXBRA -0.75 M3 modes 1, 3-5" FFFFFFFF FFFFFFFF FFFFFFFF 00000000 +r 3460.08 # RP, RM +*Want "CFXBRA -0.75 M3 modes 6, 7" 00000000 FFFFFFFF + +r 3470.10 # RZ, RP, RM, RFS +*Want "CFXBRA -0.25 FPCR modes 1-3, 7" 00000000 00000000 FFFFFFFF FFFFFFFF +r 3480.10 # RNTA, RFS, RNTE, RZ +*Want "CFXBRA -0.25 M3 modes 1, 3-5" 00000000 FFFFFFFF 00000000 00000000 +r 3490.08 # RP, RM +*Want "CFXBRA -0.25 M3 modes 6, 7" 00000000 FFFFFFFF + +r 34A0.10 # RZ, RP, RM, RFS +*Want "CFXBRA max+0.5 FPCR modes 1-3, 7" 7FFFFFFF 7FFFFFFF 7FFFFFFF 7FFFFFFF +r 34B0.10 # RNTA, RFS, RNTE, RZ +*Want "CFXBRA max+0.5 M3 modes 1, 3-5" 7FFFFFFF 7FFFFFFF 7FFFFFFF 7FFFFFFF +r 34C0.08 # RP, RM +*Want "CFXBRA max+0.5 M3 modes 6, 7" 7FFFFFFF 7FFFFFFF + + +# rounding mode tests - extended BFP - FPCR contents with cc in last byte +*Compare +r 3600.10 +*Want "CFXBRA -9.5 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 3610.10 +*Want "CFXBRA -9.5 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 3620.08 +*Want "CFXBRA -9.5 M3 modes 6, 7 FPCR" 00080001 00080001 + +r 3630.10 +*Want "CFXBRA -5.5 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 3640.10 +*Want "CFXBRA -5.5 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 3650.08 +*Want "CFXBRA -5.5 M3 modes 6, 7 FPCR" 00080001 00080001 + +r 3660.10 +*Want "CFXBRA -2.5 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 3670.10 +*Want "CFXBRA -2.5 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 3680.08 +*Want "CFXBRA -2.5 M3 modes 6, 7 FPCR" 00080001 00080001 + +r 3690.10 +*Want "CFXBRA -1.5 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 36A0.10 +*Want "CFXBRA -1.5 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 36B0.08 +*Want "CFXBRA -1.5 M3 modes 6, 7 FPCR" 00080001 00080001 + +r 36C0.10 +*Want "CFXBRA -0.5 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 36D0.10 +*Want "CFXBRA -0.5 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 36E0.08 +*Want "CFXBRA -0.5 M3 modes 6, 7 FPCR" 00080001 00080001 + +r 36F0.10 +*Want "CFXBRA +0.5 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 3700.10 +*Want "CFXBRA +0.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 3710.08 +*Want "CFXBRA +0.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 3720.10 +*Want "CFXBRA +1.5 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 3730.10 +*Want "CFXBRA +1.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 3740.08 +*Want "CFXBRA +1.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 3750.10 +*Want "CFXBRA +2.5 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 3760.10 +*Want "CFXBRA +2.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 3770.08 +*Want "CFXBRA +2.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 3780.10 +*Want "CFXBRA +5.5 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 3790.10 +*Want "CFXBRA +5.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 37A0.08 +*Want "CFXBRA +5.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 37B0.10 +*Want "CFXBRA +9.5 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 37C0.10 +*Want "CFXBRA +9.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 37D0.08 +*Want "CFXBRA +9.5 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 37E0.10 +*Want "CFXBRA +0.75 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 37F0.10 +*Want "CFXBRA +0.75 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 3800.08 +*Want "CFXBRA +0.75 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 3810.10 +*Want "CFXBRA +0.25 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 3820.10 +*Want "CFXBRA +0.25 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 3830.08 +*Want "CFXBRA +0.25 M3 modes 6, 7 FPCR" 00080002 00080002 + +r 3840.10 +*Want "CFXBRA -0.75 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 3850.10 +*Want "CFXBRA -0.75 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 3860.08 +*Want "CFXBRA -0.75 M3 modes 6, 7 FPCR" 00080001 00080001 + +r 3870.10 +*Want "CFXBRA -0.25 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 3880.10 +*Want "CFXBRA -0.25 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 3890.08 +*Want "CFXBRA -0.25 M3 modes 6, 7 FPCR" 00080001 00080001 + +r 38A0.10 +*Want "CFXBRA max+0.5 FPCR modes 1-3, 7 FPCR" 00000002 00800003 00000002 00000002 +r 38B0.10 +*Want "CFXBRA max+0.5 M3 modes 1, 3-5 FPCR" 00880003 00080002 00880003 00080002 +r 38C0.08 +*Want "CFXBRA max+0.5 M3 modes 6, 7 FPCR" 00880003 00080002 + +*Done + diff --git a/tests/bfp-007-cvttofix64.asm b/tests/bfp-007-cvttofix64.asm new file mode 100644 index 000000000..893440441 --- /dev/null +++ b/tests/bfp-007-cvttofix64.asm @@ -0,0 +1,915 @@ + TITLE 'bfp-007-cvttofix64.asm: Test IEEE Convert To Fixed (int-64)' +*********************************************************************** +* +*Testcase IEEE CONVERT TO FIXED 64 +* Test case capability includes ieee exceptions trappable and +* otherwise. Test result, FPCR flags, and DXC saved for all tests. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* bfp-007-cvttofix64.asm +* +* This assembly-language source file is part of the +* Hercules Decimal Floating Point Validation Package +* by Stephen R. Orso +* +* Copyright 2016 by Stephen R Orso. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* +* 3. The name of the author may not be used to endorse or promote +* products derived from this software without specific prior written +* permission. +* +* DISCLAMER: THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* HOLDER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* Tests the following six conversion instructions +* CONVERT TO FIXED (short BFP to int-64, RRE) +* CONVERT TO FIXED (long BFP to int-64, RRE) +* CONVERT TO FIXED (extended BFP to int-64, RRE) +* CONVERT TO FIXED (short BFP to int-64, RRF-e) +* CONVERT TO FIXED (long BFP to int-64, RRF-e) +* CONVERT TO FIXED (extended BFP to int-64, RRF-e) +* +* Test data is compiled into this program. The test script that runs +* this program can provide alternative test data through Hercules R +* commands. +* +* Test Case Order +* 1) Short BFP to Int-64 +* 2) Short BFP to Int-64 with all rounding modes +* 3) Long BFP Int-64 +* 3) Long BFP Int-64 with all rounding modes +* 4) Extended BFP to Int-64 +* 4) Extended BFP to Int-64 with all rounding modes +* +* Provided test data is: +* 1, 2, 4, -2, QNaN, SNaN, 2 147 483 648, -2 147 483 648. +* The last two values will trigger inexact exceptions when converted +* to int-64. Underflow does not get raised during Convert To Fixed. +* Provided test data for rounding tests: +* -9.5, -5.5, -2.5, -1.5, -0.5, +0.5, +1.5, +2.5, +5.5, +9.5 +* This data is taken from Table 9-11 on page 9-16 of SA22-7832-10. +* While the table illustrates LOAD FP INTEGER, the same results +* should be generated when creating an int-32 or int-64 integer. +* Additional rounding test cases are provided to test boundary cases. +* +* Note that three input test data sets are provided, one each for +* short, long, and extended precision BFP. All are converted to +* int-64. +* +* Also tests the following floating point support instructions +* LOAD (Short) +* LOAD (Long) +* LOAD FPC +* SET BFP ROUNDING MODE 2-BIT +* SET BFP ROUNDING MODE 3-BIT +* STORE (Short) +* STORE (Long) +* STORE FPC +* +*********************************************************************** + SPACE 2 + MACRO + PADCSECT &ENDLABL +.* +.* Macro to pad the CSECT to include result data areas if this test +.* program is not being assembled using asma. asma generates a core +.* image that is loaded by the loadcore command, and because the +.* core image is a binary stored in Github, it makes sense to make +.* this small effort to keep the core image small. +.* + AIF (D'&ENDLABL).GOODPAD + MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + MNOTE *,'No CSECT padding performed' + MEXIT +.* +.GOODPAD ANOP Label valid. See if we're on asma + AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + ORG &ENDLABL-1 Not ASMA. Pad CSECT + MEXIT +.* +.NOPAD ANOP + MNOTE *,'asma detected; no CSECT padding performed' + MEND +* +* Note: for compatibility with the z/CMS test rig, do not change +* or use R11, R14, or R15. Everything else is fair game. +* +BFPCVTTF START 0 +R0 EQU 0 +R1 EQU 1 +R2 EQU 2 +R3 EQU 3 +R4 EQU 4 +R5 EQU 5 +R6 EQU 6 +R7 EQU 7 +R8 EQU 8 +R9 EQU 9 +R10 EQU 10 +R11 EQU 11 +R12 EQU 12 +R13 EQU 13 +R14 EQU 14 +R15 EQU 15 +* +* Floating Point Register equates to keep the cross reference clean +* +FPR0 EQU 0 +FPR1 EQU 1 +FPR2 EQU 2 +FPR3 EQU 3 +FPR4 EQU 4 +FPR5 EQU 5 +FPR6 EQU 6 +FPR7 EQU 7 +FPR8 EQU 8 +FPR9 EQU 9 +FPR10 EQU 10 +FPR11 EQU 11 +FPR12 EQU 12 +FPR13 EQU 13 +FPR14 EQU 14 +FPR15 EQU 15 +* + USING *,R15 +* +* Above works on real iron (R15=0 after sysclear) +* and in z/CMS (R15 points to start of load module) +* + SPACE 2 +*********************************************************************** +* +* Low core definitions, Restart PSW, and Program Check Routine. +* +*********************************************************************** + SPACE 2 + ORG BFPCVTTF+X'8E' Program check interrution code +PCINTCD DS H +* +PCOLDPSW EQU BFPCVTTF+X'150' z/Arch Program check old PSW +* + ORG BFPCVTTF+X'1A0' z/Arch Restart PSW + DC X'0000000180000000',AD(START) +* + ORG BFPCVTTF+X'1D0' z/Arch Program check old PSW + DC X'0000000000000000',AD(PROGCHK) +* +* Program check routine. If Data Exception, continue execution at +* the instruction following the program check. Otherwise, hard wait. +* No need to collect data. All interesting DXC stuff is captured +* in the FPCR. +* + ORG BFPCVTTF+X'200' +PROGCHK DS 0H Program check occured... + CLI PCINTCD+1,X'07' Data Exception? + JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) + LPSWE PCOLDPSW ..yes, resume program execution +PCNOTDTA DS 0H + LTR R14,R14 Return address provided? + BNZR R14 Yes, return to z/CMS test rig. + LPSWE HARDWAIT Not data exception, enter disabled wait + EJECT +*********************************************************************** +* +* Main program. Enable Advanced Floating Point, process test cases. +* +START STCTL R0,R0,CTLR0 Store CR0 to enable AFP + OI CTLR0+1,X'04' Turn on AFP bit + LCTL R0,R0,CTLR0 Reload updated CR0 +* +* Short BFP Input testing +* + LA R10,SHORTS Point to short BFP test inputs + BAS R13,CGEBR Convert values to fixed from short BFP + LA R10,RMSHORTS Point to inputs for rounding mode tests + BAS R13,CGEBRA Convert using all rounding mode options +* +* Short BFP Input testing +* + LA R10,LONGS Point to long BFP test inputs + BAS R13,CGDBR Convert values to fixed from long BFP + LA R10,RMLONGS Point to inputs for rounding mode tests + BAS R13,CGDBRA Convert using all rounding mode options +* +* Short BFP Input testing +* + LA R10,EXTDS Point to extended BFP test inputs + BAS R13,CGXBR Convert values to fixed from extended + LA R10,RMEXTDS Point to inputs for rounding mode tests + BAS R13,CGXBRA Convert using all rounding mode options +* + LTR R14,R14 Return address provided? + BNZR R14 ..Yes, return to z/CMS test rig. + LPSWE WAITPSW All done +* + DS 0D Ensure correct alignment for psw +WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end +* +CTLR0 DS F +FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags +* +* Input values parameter list, four fullwords: +* 1) Count, +* 2) Address of inputs, +* 3) Address to place results, and +* 4) Address to place DXC/Flags/cc values. +* + ORG BFPCVTTF+X'300' +SHORTS DS 0F Inputs for short BFP testing + DC A(SBFPCT/4) + DC A(SBFPIN) + DC A(SINTOUT) + DC A(SINTFLGS) +* +LONGS DS 0F Inputs for long BFP testing + DC A(LBFPCT/8) + DC A(LBFPIN) + DC A(LINTOUT) + DC A(LINTFLGS) +* +EXTDS DS 0F Inputs for Extended BFP testing + DC A(XBFPCT/16) + DC A(XBFPIN) + DC A(XINTOUT) + DC A(XINTFLGS) +* +RMSHORTS DC A(SBFPRMCT/4) + DC A(SBFPINRM) Short BFP rounding mode test inputs + DC A(SINTRMO) Short BFP rounding mode test results + DC A(SINTRMOF) Short BFP rounding mode test flags +* +RMLONGS DC A(LBFPRMCT/8) + DC A(LBFPINRM) Long BFP rounding mode test inputs + DC A(LINTRMO) Long BFP rounding mode test results + DC A(LINTRMOF) Long BFP rounding mode test flags +* +RMEXTDS DC A(XBFPRMCT/16) + DC A(XBFPINRM) Extended BFP rounding mode test inputs + DC A(XINTRMO) Extended BFP rounding mode test results + DC A(XINTRMOF) Space for rounding mode test flags + EJECT +*********************************************************************** +* +* Convert short BFP to integer-64 format. A pair of results is +* generated for each input: one with all exceptions non-trappable, and +* the second with all exceptions trappable. The FPCR and condition +* code is stored for each result. +* +*********************************************************************** + SPACE 2 +CGEBR LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LE FPR8,0(,R3) Get short BFP test value + LFPC FPCREGNT Set exceptions non-trappable + CGEBR R1,0,FPR8 Cvt float in FPR8 to Int in GPR1 + STG R1,0(,R7) Store int-64 result + STFPC 0*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(0*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGTR Set exceptions trappable + XGR R1,R1 Clear any residual result in R1 + SPM R1 Clear out any residual nz condition code + CGEBR R1,0,FPR8 Cvt float in FPR8 to Int in GPR1 + STG R1,8(,R7) Store short BFP result + STFPC 4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(1*4)+3(,R8) Save CC as low byte of FPCR +* + LA R3,4(,R3) Point to next input value + LA R7,2*8(,R7) Point to next int-64 converted value pair + LA R8,2*4(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert short BFP to integers using each possible rounding mode. +* Ten test results are generated for each input. A 48-byte test result +* section is used to keep results sets aligned on a quad-double word. +* +* The first four tests use rounding modes specified in the FPC with the +* IEEE Inexact exception supressed. SRNM (2-bit) is used for the +* first two FPCR-controlled tests and SRNMB (3-bit) is used for the +* last two To get full coverage of that instruction pair. +* +* The next six results use instruction-specified rounding modes. +* +* The default rounding mode (0 for RNTE) is not tested in this section; +* prior tests used the default rounding mode. RNTE is tested +* explicitly as a rounding mode in this section. +* +*********************************************************************** + SPACE 2 +CGEBRA LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LE FPR8,0(,R3) Get short BFP test value +* +* Test cases using rounding mode specified in the FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 1 SET FPCR to RZ, towards zero. + CGEBRA R1,0,FPR8,B'0100' FPCR ctl'd rounding, inexact masked + STG R1,0*8(,R7) Store integer-64 result + STFPC 0(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 2 SET FPCR to RP, to +infinity + CGEBRA R1,0,FPR8,B'0100' FPCR ctl'd rounding, inexact masked + STG R1,1*8(,R7) Store integer-64 result + STFPC 1*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(1*4)+3(,R8) Save cccas low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 3 SET FPCR to RM, to -infinity + CGEBRA R1,0,FPR8,B'0100' FPCR ctl'd rounding, inexact masked + STG R1,2*8(,R7) Store integer-64 result + STFPC 2*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(2*4)+3(,R8) Save cccas low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 7 RPS, Prepare for Shorter Precision + CGEBRA R1,0,FPR8,B'0100' FPCR ctl'd rounding, inexact masked + STG R1,3*8(,R7) Store integer-64 result + STFPC 3*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(3*4)+3(,R8) Save cccas low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CGEBRA R1,1,FPR8,B'0000' RNTA, to nearest, ties away + STG R1,4*8(,R7) Store integer-64 result + STFPC 4*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(4*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CGEBRA R1,3,FPR8,B'0000' RFS, prepare for shorter precision + STG R1,5*8(,R7) Store integer-64 result + STFPC 5*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(5*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CGEBRA R1,4,FPR8,B'0000' RNTE, to nearest, ties to even + STG R1,6*8(,R7) Store integer-64 result + STFPC 6*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(6*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CGEBRA R1,5,FPR8,B'0000' RZ, toward zero + STG R1,7*8(,R7) Store integer-64 result + STFPC 7*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(7*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CGEBRA R1,6,FPR8,B'0000' RP, to +inf + STG R1,8*8(,R7) Store integer-64 result + STFPC 8*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(8*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CGEBRA R1,7,FPR8,B'0000' RM, to -inf + STG R1,9*8(,R7) Store integer-64 result + STFPC 9*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(9*4)+3(,R8) Save CC as low byte of FPCR +* + LA R3,4(,R3) Point to next input value + LA R7,10*8(,R7) Point to next short BFP converted values + LA R8,12*4(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert long BFP inputs to integer-64. A pair of results is +* generated for each input: one with all exceptions non-trappable, and +* the second with all exceptions trappable. The FPCR and condition +* code is stored for each result. +* +*********************************************************************** + SPACE 2 +CGDBR LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LD FPR8,0(,R3) Get long BFP test value + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CGDBR R1,0,FPR8 Cvt float in FPR8 to Int in GPR1 + STG R1,0(,R7) Store integer-64 result + STFPC 0*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(0*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGTR Set exceptions trappable, clear flags + XGR R1,R1 Clear any residual result in R1 + SPM R1 Clear out any residual nz condition code + CGDBR R1,0,FPR8 Cvt float in FPR8 to Int in GPR1 + STG R1,8(,R7) Store integer-64 result + STFPC 1*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(1*4)+3(,R8) Save CC as low byte of FPCR +* + LA R3,8(,R3) Point to next input values + LA R7,16(,R7) Point to next int-64 converted value pair + LA R8,8(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert long BFP to integers using each possible rounding mode. +* Ten test results are generated for each input. A 48-byte test result +* section is used to keep results sets aligned on a quad-double word. +* +* The first four tests use rounding modes specified in the FPC with the +* IEEE Inexact exception supressed. SRNM (2-bit) is used for the +* first two FPCR-controlled tests and SRNMB (3-bit) is used for the +* last two To get full coverage of that instruction pair. +* +* The next six results use instruction-specified rounding modes. +* +* The default rounding mode (0 for RNTE) is not tested in this section; +* prior tests used the default rounding mode. RNTE is tested +* explicitly as a rounding mode in this section. +* +*********************************************************************** + SPACE 2 +CGDBRA LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LD FPR8,0(,R3) Get long BFP test value +* +* Cvt float in FPFPR8 to integer-64 +* +* Test cases using rounding mode specified in the FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 1 SET FPCR to RZ, towards zero. + CGDBRA R1,0,FPR8,B'0100' FPCR ctl'd rounding, inexact masked + STG R1,0*8(,R7) Store integer-64 result + STFPC 0(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 2 SET FPCR to RP, to +infinity + CGDBRA R1,0,FPR8,B'0100' FPCR ctl'd rounding, inexact masked + STG R1,1*8(,R7) Store integer-64 result + STFPC 1*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(1*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 3 SET FPCR to RM, to -infinity + CGDBRA R1,0,FPR8,B'0100' FPCR ctl'd rounding, inexact masked + STG R1,2*8(,R7) Store integer-64 result + STFPC 2*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(2*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 7 RPS, Prepare for Shorter Precision + CGDBRA R1,0,FPR8,B'0100' FPCR ctl'd rounding, inexact masked + STG R1,3*8(,R7) Store integer-64 result + STFPC 3*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(3*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CGDBRA R1,1,FPR8,B'0000' RNTA, to nearest, ties away + STG R1,4*8(,R7) Store integer-64 result + STFPC 4*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(4*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CGDBRA R1,3,FPR8,B'0000' RFS, prepare for shorter precision + STG R1,5*8(,R7) Store integer-64 result + STFPC 5*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(5*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CGDBRA R1,4,FPR8,B'0000' RNTE, to nearest, ties to even + STG R1,6*8(,R7) Store integer-64 result + STFPC 6*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(6*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CGDBRA R1,5,FPR8,B'0000' RZ, toward zero + STG R1,7*8(,R7) Store integer-64 result + STFPC 7*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(7*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CGDBRA R1,6,FPR8,B'0000' RP, to +inf + STG R1,8*8(,R7) Store integer-64 result + STFPC 8*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(8*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CGDBRA R1,7,FPR8,B'0000' RM, to -inf + STG R1,9*8(,R7) Store integer-64 result + STFPC 9*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(9*4)+3(,R8) Save CC as low byte of FPCR +* + LA R3,8(,R3) Point to next input value + LA R7,10*8(,R7) Point to next long BFP converted values + LA R8,12*4(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert extended BFP to integer-64. A pair of results is generated +* for each input: one with all exceptions non-trappable, and the +* second with all exceptions trappable. The FPCR and condition code +* are stored for each result. +* +*********************************************************************** + SPACE 2 +CGXBR LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LD FPR8,0(,R3) Get extended BFP test value part 1 + LD FPR10,8(,R3) Get extended BFP test value part 1 + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CGXBR R1,0,FPR8 Cvt float in FPR8-FPR10 to Int-64 in GPR1 + STG R1,0(,R7) Store integer-64 result + STFPC (0*4)(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(0*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGTR Set exceptions trappable, clear flags + XGR R1,R1 Clear any residual result in R1 + SPM R1 Clear out any residual nz condition code + CGXBR R1,0,FPR8 Cvt float in FPR8-FPR10 to Int-64 in GPR1 + STG R1,8(,R7) Store integer-64 result + STFPC (1*4)(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(1*4)+3(,R8) Save CC as low byte of FPCR +* + LA R3,16(,R3) Point to next extended BFP input value + LA R7,16(,R7) Point to next int-64 converted value pair + LA R8,8(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert extended BFP to integers using each possible rounding mode. +* Ten test results are generated for each input. A 48-byte test result +* section is used to keep results sets aligned on a quad-double word. +* +* The first four tests use rounding modes specified in the FPC with the +* IEEE Inexact exception supressed. SRNM (2-bit) is used for the +* first two FPCR-controlled tests and SRNMB (3-bit) is used for the +* last two To get full coverage of that instruction pair. +* +* The next six results use instruction-specified rounding modes. +* +* The default rounding mode (0 for RNTE) is not tested in this section; +* prior tests used the default rounding mode. RNTE is tested +* explicitly as a rounding mode in this section. +* +*********************************************************************** + SPACE 2 +CGXBRA LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LD FPR8,0(,R3) Get extended BFP test value part 1 + LD FPR10,8(,R3) Get extended BFP test value part 2 +* +* Test cases using rounding mode specified in the FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 1 SET FPCR to RZ, towards zero. + CGXBRA R1,0,FPR8,B'0100' FPCR ctl'd rounding, inexact masked + STG R1,0*8(,R7) Store integer-64 result + STFPC 0(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 2 SET FPCR to RP, to +infinity + CGXBRA R1,0,FPR8,B'0100' FPCR ctl'd rounding, inexact masked + STG R1,1*8(,R7) Store integer-64 result + STFPC 1*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(1*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 3 SET FPCR to RM, to -infinity + CGXBRA R1,0,FPR8,B'0100' FPCR ctl'd rounding, inexact masked + STG R1,2*8(,R7) Store integer-64 result + STFPC 2*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(2*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 7 RPS, Prepare for Shorter Precision + CGXBRA R1,0,FPR8,B'0100' FPCR ctl'd rounding, inexact masked + STG R1,3*8(,R7) Store integer-64 result + STFPC 3*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(3*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CGXBRA R1,1,FPR8,B'0000' RNTA, to nearest, ties away + STG R1,4*8(,R7) Store integer-64 result + STFPC 4*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(4*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CGXBRA R1,3,FPR8,B'0000' RFS, prepare for shorter precision + STG R1,5*8(,R7) Store integer-64 result + STFPC 5*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(5*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CGXBRA R1,4,FPR8,B'0000' RNTE to nearest, ties to even + STG R1,6*8(,R7) Store integer-64 result + STFPC 6*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(6*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CGXBRA R1,5,FPR8,B'0000' RZ toward zero + STG R1,7*8(,R7) Store integer-64 result + STFPC 7*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(7*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CGXBRA R1,6,FPR8,B'0000' to +inf + STG R1,8*8(,R7) Store integer-64 result + STFPC 8*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(8*4)+3(,R8) Save CC as low byte of FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CGXBRA R1,7,FPR8,B'0000' to -inf + STG R1,9*8(,R7) Store integer-64 result + STFPC 9*4(R8) Store resulting FPCR flags and DXC + IPM R1 Get condition code and program mask + SRL R1,28 Isolate CC in low order byte + STC R1,(9*4)+3(,R8) Save CC as low byte of FPCR +* + LA R3,16(,R3) Point to next input value + LA R7,10*8(,R7) Point to next long BFP converted values + LA R8,12*4(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Floating point inputs for Convert From Fixed testing. The same test +* values in the appropriate input format are used for short, long, +* and extended format tests. The last four values should generate +* exceptions. +* +*********************************************************************** + SPACE 2 +* +* Inputs for basic tests of short BFP to int-64 +* +SBFPIN DS 0F Inputs for short BFP testing + DC X'3F800000' +1.0 + DC X'40000000' +2.0 + DC X'40800000' +4.0 + DC X'C0000000' -2.0 + DC X'7F810000' SNaN + DC X'7FC10000' QNaN + DC X'5F000000' +max int-64 + 1 +* +9,223,372,036,854,775,807 + 1 + DC X'DF000001' -max int-64 - 2 +* -9,223,372,036,854,775,807 - 2 + DC X'5EFFFFFF' Largest short BFP that fits in int-64 +* +9,223,371,487,098,961,920 +* = 0x7FFFFF80000000000 +SBFPCT EQU *-SBFPIN Count of short BFP in list * 4 +* +* Inputs for exhaustive rounding mode tests of short BFP to int-64 +* +SBFPINRM DS 0F + DC X'C1180000' -9.5 + DC X'C0B00000' -5.5 + DC X'C0200000' -2.5 + DC X'BFC00000' -1.5 + DC X'BF000000' -0.5 + DC X'3F000000' +0.5 + DC X'3FC00000' +1.5 + DC X'40200000' +2.5 + DC X'40B00000' +5.5 + DC X'41180000' +9.5 + DC X'3F400000' +0.75 + DC X'3E800000' +0.25 + DC X'BF400000' -0.75 + DC X'BE800000' -0.25 +SBFPRMCT EQU *-SBFPINRM Count of short BFP * 4 for rounding tests +* +* Inputs for basic tests of long BFP to int-64 +* +LBFPIN DS 0F Inputs for long BFP testing + DC X'3FF0000000000000' +1.0 + DC X'4000000000000000' +2.0 + DC X'4010000000000000' +4.0 + DC X'C000000000000000' -2.0 + DC X'7FF0100000000000' SNaN + DC X'7FF8100000000000' QNaN + DC X'43E0000000000000' +max int-64 + 1. +* (+9,223,372,036,854,775,807 + 1) + DC X'C3E0000000100000' -max int-64 - 2 +* (-9,223,372,036,854,775,807 - 2) + DC X'43DFFFFFFFFFFFFF' Largest long BFP that fits in +* ..int-64: 9,223,372,036,854,774,784, +* .. 0x7FFFFFFFFFFFF800 +LBFPCT EQU *-LBFPIN Count of long BFP in list * 8 +* +* Inputs for exhaustive rounding mode tests of long BFP to int-64 +* +LBFPINRM DS 0F + DC X'C023000000000000' -9.5 + DC X'C016000000000000' -5.5 + DC X'C004000000000000' -2.5 + DC X'BFF8000000000000' -1.5 + DC X'BFE0000000000000' -0.5 + DC X'3FE0000000000000' +0.5 + DC X'3FF8000000000000' +1.5 + DC X'4004000000000000' +2.5 + DC X'4016000000000000' +5.5 + DC X'4023000000000000' +9.5 + DC X'3FE8000000000000' +0.75 + DC X'3FD0000000000000' +0.25 + DC X'BFE8000000000000' -0.75 + DC X'BFD0000000000000' -0.25 +LBFPRMCT EQU *-LBFPINRM Count of long BFP * 8 for rounding tests +* +* Inputs for basic tests of extended BFP to int-64 +* +XBFPIN DS 0D Inputs for long BFP testing + DC X'3FFF0000000000000000000000000000' +1.0 + DC X'40000000000000000000000000000000' +2.0 + DC X'40010000000000000000000000000000' +4.0 + DC X'C0000000000000000000000000000000' -2.0 + DC X'7FFF0100000000000000000000000000' SNaN + DC X'7FFF8100000000000000000000000000' QNaN + DC X'403E0000000000000000000000000000' +max int-64 + 1 +* (+9223372036854775807 + 1) + DC X'C03E0000000100000000000000000000' -max int-64 - 2 +* (-9223372036854775807 - 2) + DC X'403DFFFFFFFFFFFFFFFC000000000000' +max int-64 +XBFPCT EQU *-XBFPIN Count of extended BFP in list * 16 +* +* Inputs for exhaustive rounding mode tests of extended BFP to int-64 +* +XBFPINRM DS 0D + DC X'C0023000000000000000000000000000' -9.5 + DC X'C0016000000000000000000000000000' -5.5 + DC X'C0004000000000000000000000000000' -2.5 + DC X'BFFF8000000000000000000000000000' -1.5 + DC X'BFFE0000000000000000000000000000' -0.5 + DC X'3FFE0000000000000000000000000000' +0.5 + DC X'3FFF8000000000000000000000000000' +1.5 + DC X'40004000000000000000000000000000' +2.5 + DC X'40016000000000000000000000000000' +5.5 + DC X'40023000000000000000000000000000' +9.5 + DC X'3FFE8000000000000000000000000000' +0.75 + DC X'3FFD0000000000000000000000000000' +0.25 + DC X'BFFE8000000000000000000000000000' -0.75 + DC X'BFFD0000000000000000000000000000' -0.25 + DC X'403DFFFFFFFFFFFFFFFE000000000000' max int-64 + 0.5 +* 9,223,372,036,854,775,807.5, overflows on some +* ..but not all rounding modes +XBFPRMCT EQU *-XBFPINRM Count of ext'd BFP * 16 for rounding tests +* +* Locations for results +* +SINTOUT EQU BFPCVTTF+X'1000' Integer-64 values from short BFP +* ..8 pairs used, room for 32 +SINTFLGS EQU BFPCVTTF+X'1200' FPCR flags and DXC from short BFP +* ..8 pairs used,room for 32 +SINTRMO EQU BFPCVTTF+X'1300' Short rounding mode test results +* ..10 sets used, room for 16 +SINTRMOF EQU BFPCVTTF+X'1800' Short rounding mode FPCR contents +* ..10 sets used, room for 16 +* +LINTOUT EQU BFPCVTTF+X'2000' Integer-64 values from long BFP +* ..8 pairs used, room for 32 +LINTFLGS EQU BFPCVTTF+X'2200' FPCR flags and DXC from long BFP +* ..8 pairs used,room for 32 +LINTRMO EQU BFPCVTTF+X'2300' Long rounding mode test results +* ..10 sets used, room for 16 +LINTRMOF EQU BFPCVTTF+X'2800' Long rounding mode FPCR contents +* ..10 sets used, room for 16 +* +XINTOUT EQU BFPCVTTF+X'3000' Integer-64 values from extended BFP +* ..8 pairs used, room for 32 +XINTFLGS EQU BFPCVTTF+X'3200' FPCR flags and DXC from extended BFP +* ..8 pairs used, room for 32 +XINTRMO EQU BFPCVTTF+X'3300' Extended rounding mode test results +* ..10 sets used, room for 16 +XINTRMOF EQU BFPCVTTF+X'3800' Extended rndg mode FPCR contents +* ..10 sets used, room for 16 +* +ENDLABL EQU BFPCVTTF+X'3B00' Next available location + PADCSECT ENDLABL + END diff --git a/tests/bfp-007-cvttofix64.core b/tests/bfp-007-cvttofix64.core new file mode 100644 index 000000000..a7a55b77e Binary files /dev/null and b/tests/bfp-007-cvttofix64.core differ diff --git a/tests/bfp-007-cvttofix64.list b/tests/bfp-007-cvttofix64.list new file mode 100644 index 000000000..650da6a8b --- /dev/null +++ b/tests/bfp-007-cvttofix64.list @@ -0,0 +1,1104 @@ +ASMA Ver. 0.2.0 ieee-cvttofix64.asm: Test IEEE Convert To Fixed (int-64) 05 Sep 2016 08:21:23 Page 1 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 2 *********************************************************************** + 3 * + 4 *Testcase IEEE CONVERT TO FIXED 64 + 5 * Test case capability includes ieee exceptions trappable and + 6 * otherwise. Test result, FPCR flags, and DXC saved for all tests. + 7 * + 8 *********************************************************************** + + + 10 *********************************************************************** + 11 * + 12 * Tests the following six conversion instructions + 13 * CONVERT TO FIXED (short BFP to int-64, RRE) + 14 * CONVERT TO FIXED (long BFP to int-64, RRE) + 15 * CONVERT TO FIXED (extended BFP to int-64, RRE) + 16 * CONVERT TO FIXED (short BFP to int-64, RRF-e) + 17 * CONVERT TO FIXED (long BFP to int-64, RRF-e) + 18 * CONVERT TO FIXED (extended BFP to int-64, RRF-e) + 19 * + 20 * Test data is compiled into this program. The test script that runs + 21 * this program can provide alternative test data through Hercules R + 22 * commands. + 23 * + 24 * Test Case Order + 25 * 1) Short BFP to Int-64 + 26 * 2) Short BFP to Int-64 with all rounding modes + 27 * 3) Long BFP Int-64 + 28 * 3) Long BFP Int-64 with all rounding modes + 29 * 4) Extended BFP to Int-64 + 30 * 4) Extended BFP to Int-64 with all rounding modes + 31 * + 32 * Provided test data is: + 33 * 1, 2, 4, -2, QNaN, SNaN, 2 147 483 648, -2 147 483 648. + 34 * The last two values will trigger inexact exceptions when converted + 35 * to int-64. Underflow does not get raised during Convert To Fixed. + 36 * Provided test data for rounding tests: + 37 * -9.5, -5.5, -2.5, -1.5, -0.5, +0.5, +1.5, +2.5, +5.5, +9.5 + 38 * This data is taken from Table 9-11 on page 9-16 of SA22-7832-10. + 39 * While the table illustrates LOAD FP INTEGER, the same results + 40 * should be generated when creating an int-32 or int-64 integer. + 41 * Additional rounding test cases are provided to test boundary cases. + 42 * + 43 * Note that three input test data sets are provided, one each for + 44 * short, long, and extended precision BFP. All are converted to + 45 * int-64. + 46 * + 47 * Also tests the following floating point support instructions + 48 * LOAD (Short) + 49 * LOAD (Long) + 50 * LOAD FPC + 51 * SET BFP ROUNDING MODE 2-BIT + 52 * SET BFP ROUNDING MODE 3-BIT + ASMA Ver. 0.2.0 ieee-cvttofix64.asm: Test IEEE Convert To Fixed (int-64) 05 Sep 2016 08:21:23 Page 2 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 53 * STORE (Short) + 54 * STORE (Long) + 55 * STORE FPC + 56 * + 57 *********************************************************************** + + + 59 MACRO + 60 PADCSECT &ENDLABL + 61 .* + 62 .* Macro to pad the CSECT to include result data areas if this test + 63 .* program is not being assembled using asma. asma generates a core + 64 .* image that is loaded by the loadcore command, and because the + 65 .* core image is a binary stored in Github, it makes sense to make + 66 .* this small effort to keep the core image small. + 67 .* + 68 AIF (D'&ENDLABL).GOODPAD + 69 MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + 70 MNOTE *,'No CSECT padding performed' + 71 MEXIT + 72 .* + 73 .GOODPAD ANOP Label valid. See if we're on asma + 74 AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + 75 ORG &ENDLABL-1 Not ASMA. Pad CSECT + 76 MEXIT + 77 .* + 78 .NOPAD ANOP + 79 MNOTE *,'asma detected; no CSECT padding performed' + 80 MEND + 81 * + 82 * Note: for compatibility with the z/CMS test rig, do not change + 83 * or use R11, R14, or R15. Everything else is fair game. + 84 * + 0000000000000000 0000000000000B47 85 BFPCVTTF START 0 + 0000000000000000 0000000000000001 86 R0 EQU 0 + 0000000000000001 0000000000000001 87 R1 EQU 1 + 0000000000000002 0000000000000001 88 R2 EQU 2 + 0000000000000003 0000000000000001 89 R3 EQU 3 + 0000000000000004 0000000000000001 90 R4 EQU 4 + 0000000000000005 0000000000000001 91 R5 EQU 5 + 0000000000000006 0000000000000001 92 R6 EQU 6 + 0000000000000007 0000000000000001 93 R7 EQU 7 + 0000000000000008 0000000000000001 94 R8 EQU 8 + 0000000000000009 0000000000000001 95 R9 EQU 9 + 000000000000000A 0000000000000001 96 R10 EQU 10 + 000000000000000B 0000000000000001 97 R11 EQU 11 + 000000000000000C 0000000000000001 98 R12 EQU 12 + 000000000000000D 0000000000000001 99 R13 EQU 13 + 000000000000000E 0000000000000001 100 R14 EQU 14 + 000000000000000F 0000000000000001 101 R15 EQU 15 + 102 * + 103 * Floating Point Register equates to keep the cross reference clean + ASMA Ver. 0.2.0 ieee-cvttofix64.asm: Test IEEE Convert To Fixed (int-64) 05 Sep 2016 08:21:23 Page 3 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 104 * + 0000000000000000 0000000000000001 105 FPR0 EQU 0 + 0000000000000001 0000000000000001 106 FPR1 EQU 1 + 0000000000000002 0000000000000001 107 FPR2 EQU 2 + 0000000000000003 0000000000000001 108 FPR3 EQU 3 + 0000000000000004 0000000000000001 109 FPR4 EQU 4 + 0000000000000005 0000000000000001 110 FPR5 EQU 5 + 0000000000000006 0000000000000001 111 FPR6 EQU 6 + 0000000000000007 0000000000000001 112 FPR7 EQU 7 + 0000000000000008 0000000000000001 113 FPR8 EQU 8 + 0000000000000009 0000000000000001 114 FPR9 EQU 9 + 000000000000000A 0000000000000001 115 FPR10 EQU 10 + 000000000000000B 0000000000000001 116 FPR11 EQU 11 + 000000000000000C 0000000000000001 117 FPR12 EQU 12 + 000000000000000D 0000000000000001 118 FPR13 EQU 13 + 000000000000000E 0000000000000001 119 FPR14 EQU 14 + 000000000000000F 0000000000000001 120 FPR15 EQU 15 + 121 * +0000000000000000 0000000000000000 122 USING *,R15 + 123 * + 124 * Above works on real iron (R15=0 after sysclear) + 125 * and in z/CMS (R15 points to start of load module) + 126 * + + + 128 *********************************************************************** + 129 * + 130 * Low core definitions, Restart PSW, and Program Check Routine. + 131 * + 132 *********************************************************************** + + +0000000000000000 0000000000000000 000000000000008E 134 ORG BFPCVTTF+X'8E' Program check interrution code +000000000000008E 0000 135 PCINTCD DS H + 136 * + 0000000000000150 0000000000000000 137 PCOLDPSW EQU BFPCVTTF+X'150' z/Arch Program check old PSW + 138 * +0000000000000090 0000000000000090 00000000000001A0 139 ORG BFPCVTTF+X'1A0' z/Arch Restart PSW +00000000000001A0 00000001 80000000 140 DC X'0000000180000000',AD(START) + 141 * +00000000000001B0 00000000000001B0 00000000000001D0 142 ORG BFPCVTTF+X'1D0' z/Arch Program check old PSW +00000000000001D0 00000000 00000000 143 DC X'0000000000000000',AD(PROGCHK) + 144 * + 145 * Program check routine. If Data Exception, continue execution at + 146 * the instruction following the program check. Otherwise, hard wait. + 147 * No need to collect data. All interesting DXC stuff is captured + 148 * in the FPCR. + 149 * +00000000000001E0 00000000000001E0 0000000000000200 150 ORG BFPCVTTF+X'200' +0000000000000200 151 PROGCHK DS 0H Program check occured... +0000000000000200 9507 F08F 000000000000008F 152 CLI PCINTCD+1,X'07' Data Exception? +0000000000000204 A774 0004 000000000000020C 153 JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) + ASMA Ver. 0.2.0 ieee-cvttofix64.asm: Test IEEE Convert To Fixed (int-64) 05 Sep 2016 08:21:23 Page 4 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000208 B2B2 F150 0000000000000150 154 LPSWE PCOLDPSW ..yes, resume program execution +000000000000020C 155 PCNOTDTA DS 0H +000000000000020C 12EE 156 LTR R14,R14 Return address provided? +000000000000020E 077E 157 BNZR R14 Yes, return to z/CMS test rig. +0000000000000210 B2B2 F268 0000000000000268 158 LPSWE HARDWAIT Not data exception, enter disabled wait + ASMA Ver. 0.2.0 ieee-cvttofix64.asm: Test IEEE Convert To Fixed (int-64) 05 Sep 2016 08:21:23 Page 5 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 160 *********************************************************************** + 161 * + 162 * Main program. Enable Advanced Floating Point, process test cases. + 163 * +0000000000000214 B600 F278 0000000000000278 164 START STCTL R0,R0,CTLR0 Store CR0 to enable AFP +0000000000000218 9604 F279 0000000000000279 165 OI CTLR0+1,X'04' Turn on AFP bit +000000000000021C B700 F278 0000000000000278 166 LCTL R0,R0,CTLR0 Reload updated CR0 + 167 * + 168 * Short BFP Input testing + 169 * +0000000000000220 41A0 F300 0000000000000300 170 LA R10,SHORTS Point to short BFP test inputs +0000000000000224 4DD0 F360 0000000000000360 171 BAS R13,CGEBR Convert values to fixed from short BFP +0000000000000228 41A0 F330 0000000000000330 172 LA R10,RMSHORTS Point to inputs for rounding mode tests +000000000000022C 4DD0 F3C4 00000000000003C4 173 BAS R13,CGEBRA Convert using all rounding mode options + 174 * + 175 * Short BFP Input testing + 176 * +0000000000000230 41A0 F310 0000000000000310 177 LA R10,LONGS Point to long BFP test inputs +0000000000000234 4DD0 F522 0000000000000522 178 BAS R13,CGDBR Convert values to fixed from long BFP +0000000000000238 41A0 F340 0000000000000340 179 LA R10,RMLONGS Point to inputs for rounding mode tests +000000000000023C 4DD0 F586 0000000000000586 180 BAS R13,CGDBRA Convert using all rounding mode options + 181 * + 182 * Short BFP Input testing + 183 * +0000000000000240 41A0 F320 0000000000000320 184 LA R10,EXTDS Point to extended BFP test inputs +0000000000000244 4DD0 F6E4 00000000000006E4 185 BAS R13,CGXBR Convert values to fixed from extended +0000000000000248 41A0 F350 0000000000000350 186 LA R10,RMEXTDS Point to inputs for rounding mode tests +000000000000024C 4DD0 F74C 000000000000074C 187 BAS R13,CGXBRA Convert using all rounding mode options + 188 * +0000000000000250 12EE 189 LTR R14,R14 Return address provided? +0000000000000252 077E 190 BNZR R14 ..Yes, return to z/CMS test rig. +0000000000000254 B2B2 F258 0000000000000258 191 LPSWE WAITPSW All done + 192 * +0000000000000258 193 DS 0D Ensure correct alignment for psw +0000000000000258 00020000 00000000 194 WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +0000000000000268 00020000 00000000 195 HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end + 196 * +0000000000000278 00000000 197 CTLR0 DS F +000000000000027C 00000000 198 FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +0000000000000280 F8000000 199 FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags + 200 * + 201 * Input values parameter list, four fullwords: + 202 * 1) Count, + 203 * 2) Address of inputs, + 204 * 3) Address to place results, and + 205 * 4) Address to place DXC/Flags/cc values. + 206 * +0000000000000284 0000000000000284 0000000000000300 207 ORG BFPCVTTF+X'300' +0000000000000300 208 SHORTS DS 0F Inputs for short BFP testing +0000000000000300 00000009 209 DC A(SBFPCT/4) +0000000000000304 000008B0 210 DC A(SBFPIN) +0000000000000308 00001000 211 DC A(SINTOUT) + ASMA Ver. 0.2.0 ieee-cvttofix64.asm: Test IEEE Convert To Fixed (int-64) 05 Sep 2016 08:21:23 Page 6 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +000000000000030C 00001200 212 DC A(SINTFLGS) + 213 * +0000000000000310 214 LONGS DS 0F Inputs for long BFP testing +0000000000000310 00000009 215 DC A(LBFPCT/8) +0000000000000314 0000090C 216 DC A(LBFPIN) +0000000000000318 00002000 217 DC A(LINTOUT) +000000000000031C 00002200 218 DC A(LINTFLGS) + 219 * +0000000000000320 220 EXTDS DS 0F Inputs for Extended BFP testing +0000000000000320 00000009 221 DC A(XBFPCT/16) +0000000000000324 000009C8 222 DC A(XBFPIN) +0000000000000328 00003000 223 DC A(XINTOUT) +000000000000032C 00003200 224 DC A(XINTFLGS) + 225 * +0000000000000330 0000000E 226 RMSHORTS DC A(SBFPRMCT/4) +0000000000000334 000008D4 227 DC A(SBFPINRM) Short BFP rounding mode test inputs +0000000000000338 00001300 228 DC A(SINTRMO) Short BFP rounding mode test results +000000000000033C 00001800 229 DC A(SINTRMOF) Short BFP rounding mode test flags + 230 * +0000000000000340 0000000E 231 RMLONGS DC A(LBFPRMCT/8) +0000000000000344 00000954 232 DC A(LBFPINRM) Long BFP rounding mode test inputs +0000000000000348 00002300 233 DC A(LINTRMO) Long BFP rounding mode test results +000000000000034C 00002800 234 DC A(LINTRMOF) Long BFP rounding mode test flags + 235 * +0000000000000350 0000000F 236 RMEXTDS DC A(XBFPRMCT/16) +0000000000000354 00000A58 237 DC A(XBFPINRM) Extended BFP rounding mode test inputs +0000000000000358 00003300 238 DC A(XINTRMO) Extended BFP rounding mode test results +000000000000035C 00003800 239 DC A(XINTRMOF) Space for rounding mode test flags + ASMA Ver. 0.2.0 ieee-cvttofix64.asm: Test IEEE Convert To Fixed (int-64) 05 Sep 2016 08:21:23 Page 7 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 241 *********************************************************************** + 242 * + 243 * Convert short BFP to integer-64 format. A pair of results is + 244 * generated for each input: one with all exceptions non-trappable, and + 245 * the second with all exceptions trappable. The FPCR and condition + 246 * code is stored for each result. + 247 * + 248 *********************************************************************** + + +0000000000000360 9823 A000 0000000000000000 250 CGEBR LM R2,R3,0(R10) Get count and address of test input values +0000000000000364 9878 A008 0000000000000008 251 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000368 1222 252 LTR R2,R2 Any test cases? +000000000000036A 078D 253 BZR R13 ..No, return to caller +000000000000036C 0DC0 254 BASR R12,0 Set top of loop + 255 * +000000000000036E 7880 3000 0000000000000000 256 LE FPR8,0(,R3) Get short BFP test value +0000000000000372 B29D F27C 000000000000027C 257 LFPC FPCREGNT Set exceptions non-trappable +0000000000000376 B3A8 0018 258 CGEBR R1,0,FPR8 Cvt float in FPR8 to Int in GPR1 +000000000000037A E310 7000 0024 0000000000000000 259 STG R1,0(,R7) Store int-64 result +0000000000000380 B29C 8000 0000000000000000 260 STFPC 0*4(R8) Store resulting FPCR flags and DXC +0000000000000384 B222 0010 261 IPM R1 Get condition code and program mask +0000000000000388 8810 001C 000000000000001C 262 SRL R1,28 Isolate CC in low order byte +000000000000038C 4210 8003 0000000000000003 263 STC R1,(0*4)+3(,R8) Save CC as low byte of FPCR + 264 * +0000000000000390 B29D F280 0000000000000280 265 LFPC FPCREGTR Set exceptions trappable +0000000000000394 B982 0011 266 XGR R1,R1 Clear any residual result in R1 +0000000000000398 0410 267 SPM R1 Clear out any residual nz condition code +000000000000039A B3A8 0018 268 CGEBR R1,0,FPR8 Cvt float in FPR8 to Int in GPR1 +000000000000039E E310 7008 0024 0000000000000008 269 STG R1,8(,R7) Store short BFP result +00000000000003A4 B29C 8004 0000000000000004 270 STFPC 4(R8) Store resulting FPCR flags and DXC +00000000000003A8 B222 0010 271 IPM R1 Get condition code and program mask +00000000000003AC 8810 001C 000000000000001C 272 SRL R1,28 Isolate CC in low order byte +00000000000003B0 4210 8007 0000000000000007 273 STC R1,(1*4)+3(,R8) Save CC as low byte of FPCR + 274 * +00000000000003B4 4130 3004 0000000000000004 275 LA R3,4(,R3) Point to next input value +00000000000003B8 4170 7010 0000000000000010 276 LA R7,2*8(,R7) Point to next int-64 converted value pair +00000000000003BC 4180 8008 0000000000000008 277 LA R8,2*4(,R8) Point to next FPCR/CC result area +00000000000003C0 062C 278 BCTR R2,R12 Convert next input value. +00000000000003C2 07FD 279 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvttofix64.asm: Test IEEE Convert To Fixed (int-64) 05 Sep 2016 08:21:23 Page 8 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 281 *********************************************************************** + 282 * + 283 * Convert short BFP to integers using each possible rounding mode. + 284 * Ten test results are generated for each input. A 48-byte test result + 285 * section is used to keep results sets aligned on a quad-double word. + 286 * + 287 * The first four tests use rounding modes specified in the FPC with the + 288 * IEEE Inexact exception supressed. SRNM (2-bit) is used for the + 289 * first two FPCR-controlled tests and SRNMB (3-bit) is used for the + 290 * last two To get full coverage of that instruction pair. + 291 * + 292 * The next six results use instruction-specified rounding modes. + 293 * + 294 * The default rounding mode (0 for RNTE) is not tested in this section; + 295 * prior tests used the default rounding mode. RNTE is tested + 296 * explicitly as a rounding mode in this section. + 297 * + 298 *********************************************************************** + + +00000000000003C4 9823 A000 0000000000000000 300 CGEBRA LM R2,R3,0(R10) Get count and address of test input values +00000000000003C8 9878 A008 0000000000000008 301 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000003CC 1222 302 LTR R2,R2 Any test cases? +00000000000003CE 078D 303 BZR R13 ..No, return to caller +00000000000003D0 0DC0 304 BASR R12,0 Set top of loop + 305 * +00000000000003D2 7880 3000 0000000000000000 306 LE FPR8,0(,R3) Get short BFP test value + 307 * + 308 * Test cases using rounding mode specified in the FPCR + 309 * +00000000000003D6 B29D F27C 000000000000027C 310 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000003DA B2B8 0001 0000000000000001 311 SRNMB 1 SET FPCR to RZ, towards zero. +00000000000003DE B3A8 0418 312 CGEBRA R1,0,FPR8,B'0100' FPCR ctl'd rounding, inexact masked +00000000000003E2 E310 7000 0024 0000000000000000 313 STG R1,0*8(,R7) Store integer-64 result +00000000000003E8 B29C 8000 0000000000000000 314 STFPC 0(R8) Store resulting FPCR flags and DXC +00000000000003EC B222 0010 315 IPM R1 Get condition code and program mask +00000000000003F0 8810 001C 000000000000001C 316 SRL R1,28 Isolate CC in low order byte +00000000000003F4 4210 8003 0000000000000003 317 STC R1,3(,R8) Save CC as low byte of FPCR + 318 * +00000000000003F8 B29D F27C 000000000000027C 319 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000003FC B2B8 0002 0000000000000002 320 SRNMB 2 SET FPCR to RP, to +infinity +0000000000000400 B3A8 0418 321 CGEBRA R1,0,FPR8,B'0100' FPCR ctl'd rounding, inexact masked +0000000000000404 E310 7008 0024 0000000000000008 322 STG R1,1*8(,R7) Store integer-64 result +000000000000040A B29C 8004 0000000000000004 323 STFPC 1*4(R8) Store resulting FPCR flags and DXC +000000000000040E B222 0010 324 IPM R1 Get condition code and program mask +0000000000000412 8810 001C 000000000000001C 325 SRL R1,28 Isolate CC in low order byte +0000000000000416 4210 8007 0000000000000007 326 STC R1,(1*4)+3(,R8) Save cccas low byte of FPCR + 327 * +000000000000041A B29D F27C 000000000000027C 328 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000041E B2B8 0003 0000000000000003 329 SRNMB 3 SET FPCR to RM, to -infinity +0000000000000422 B3A8 0418 330 CGEBRA R1,0,FPR8,B'0100' FPCR ctl'd rounding, inexact masked +0000000000000426 E310 7010 0024 0000000000000010 331 STG R1,2*8(,R7) Store integer-64 result + ASMA Ver. 0.2.0 ieee-cvttofix64.asm: Test IEEE Convert To Fixed (int-64) 05 Sep 2016 08:21:23 Page 9 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +000000000000042C B29C 8008 0000000000000008 332 STFPC 2*4(R8) Store resulting FPCR flags and DXC +0000000000000430 B222 0010 333 IPM R1 Get condition code and program mask +0000000000000434 8810 001C 000000000000001C 334 SRL R1,28 Isolate CC in low order byte +0000000000000438 4210 800B 000000000000000B 335 STC R1,(2*4)+3(,R8) Save cccas low byte of FPCR + 336 * +000000000000043C B29D F27C 000000000000027C 337 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000440 B2B8 0007 0000000000000007 338 SRNMB 7 RPS, Prepare for Shorter Precision +0000000000000444 B3A8 0418 339 CGEBRA R1,0,FPR8,B'0100' FPCR ctl'd rounding, inexact masked +0000000000000448 E310 7018 0024 0000000000000018 340 STG R1,3*8(,R7) Store integer-64 result +000000000000044E B29C 800C 000000000000000C 341 STFPC 3*4(R8) Store resulting FPCR flags and DXC +0000000000000452 B222 0010 342 IPM R1 Get condition code and program mask +0000000000000456 8810 001C 000000000000001C 343 SRL R1,28 Isolate CC in low order byte +000000000000045A 4210 800F 000000000000000F 344 STC R1,(3*4)+3(,R8) Save cccas low byte of FPCR + 345 * +000000000000045E B29D F27C 000000000000027C 346 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000462 B3A8 1018 347 CGEBRA R1,1,FPR8,B'0000' RNTA, to nearest, ties away +0000000000000466 E310 7020 0024 0000000000000020 348 STG R1,4*8(,R7) Store integer-64 result +000000000000046C B29C 8010 0000000000000010 349 STFPC 4*4(R8) Store resulting FPCR flags and DXC +0000000000000470 B222 0010 350 IPM R1 Get condition code and program mask +0000000000000474 8810 001C 000000000000001C 351 SRL R1,28 Isolate CC in low order byte +0000000000000478 4210 8013 0000000000000013 352 STC R1,(4*4)+3(,R8) Save CC as low byte of FPCR + 353 * +000000000000047C B29D F27C 000000000000027C 354 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000480 B3A8 3018 355 CGEBRA R1,3,FPR8,B'0000' RFS, prepare for shorter precision +0000000000000484 E310 7028 0024 0000000000000028 356 STG R1,5*8(,R7) Store integer-64 result +000000000000048A B29C 8014 0000000000000014 357 STFPC 5*4(R8) Store resulting FPCR flags and DXC +000000000000048E B222 0010 358 IPM R1 Get condition code and program mask +0000000000000492 8810 001C 000000000000001C 359 SRL R1,28 Isolate CC in low order byte +0000000000000496 4210 8017 0000000000000017 360 STC R1,(5*4)+3(,R8) Save CC as low byte of FPCR + 361 * +000000000000049A B29D F27C 000000000000027C 362 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000049E B3A8 4018 363 CGEBRA R1,4,FPR8,B'0000' RNTE, to nearest, ties to even +00000000000004A2 E310 7030 0024 0000000000000030 364 STG R1,6*8(,R7) Store integer-64 result +00000000000004A8 B29C 8018 0000000000000018 365 STFPC 6*4(R8) Store resulting FPCR flags and DXC +00000000000004AC B222 0010 366 IPM R1 Get condition code and program mask +00000000000004B0 8810 001C 000000000000001C 367 SRL R1,28 Isolate CC in low order byte +00000000000004B4 4210 801B 000000000000001B 368 STC R1,(6*4)+3(,R8) Save CC as low byte of FPCR + 369 * +00000000000004B8 B29D F27C 000000000000027C 370 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000004BC B3A8 5018 371 CGEBRA R1,5,FPR8,B'0000' RZ, toward zero +00000000000004C0 E310 7038 0024 0000000000000038 372 STG R1,7*8(,R7) Store integer-64 result +00000000000004C6 B29C 801C 000000000000001C 373 STFPC 7*4(R8) Store resulting FPCR flags and DXC +00000000000004CA B222 0010 374 IPM R1 Get condition code and program mask +00000000000004CE 8810 001C 000000000000001C 375 SRL R1,28 Isolate CC in low order byte +00000000000004D2 4210 801F 000000000000001F 376 STC R1,(7*4)+3(,R8) Save CC as low byte of FPCR + 377 * +00000000000004D6 B29D F27C 000000000000027C 378 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000004DA B3A8 6018 379 CGEBRA R1,6,FPR8,B'0000' RP, to +inf +00000000000004DE E310 7040 0024 0000000000000040 380 STG R1,8*8(,R7) Store integer-64 result +00000000000004E4 B29C 8020 0000000000000020 381 STFPC 8*4(R8) Store resulting FPCR flags and DXC +00000000000004E8 B222 0010 382 IPM R1 Get condition code and program mask +00000000000004EC 8810 001C 000000000000001C 383 SRL R1,28 Isolate CC in low order byte + ASMA Ver. 0.2.0 ieee-cvttofix64.asm: Test IEEE Convert To Fixed (int-64) 05 Sep 2016 08:21:23 Page 10 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000004F0 4210 8023 0000000000000023 384 STC R1,(8*4)+3(,R8) Save CC as low byte of FPCR + 385 * +00000000000004F4 B29D F27C 000000000000027C 386 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000004F8 B3A8 7018 387 CGEBRA R1,7,FPR8,B'0000' RM, to -inf +00000000000004FC E310 7048 0024 0000000000000048 388 STG R1,9*8(,R7) Store integer-64 result +0000000000000502 B29C 8024 0000000000000024 389 STFPC 9*4(R8) Store resulting FPCR flags and DXC +0000000000000506 B222 0010 390 IPM R1 Get condition code and program mask +000000000000050A 8810 001C 000000000000001C 391 SRL R1,28 Isolate CC in low order byte +000000000000050E 4210 8027 0000000000000027 392 STC R1,(9*4)+3(,R8) Save CC as low byte of FPCR + 393 * +0000000000000512 4130 3004 0000000000000004 394 LA R3,4(,R3) Point to next input value +0000000000000516 4170 7050 0000000000000050 395 LA R7,10*8(,R7) Point to next short BFP converted values +000000000000051A 4180 8030 0000000000000030 396 LA R8,12*4(,R8) Point to next FPCR/CC result area +000000000000051E 062C 397 BCTR R2,R12 Convert next input value. +0000000000000520 07FD 398 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvttofix64.asm: Test IEEE Convert To Fixed (int-64) 05 Sep 2016 08:21:23 Page 11 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 400 *********************************************************************** + 401 * + 402 * Convert long BFP inputs to integer-64. A pair of results is + 403 * generated for each input: one with all exceptions non-trappable, and + 404 * the second with all exceptions trappable. The FPCR and condition + 405 * code is stored for each result. + 406 * + 407 *********************************************************************** + + +0000000000000522 9823 A000 0000000000000000 409 CGDBR LM R2,R3,0(R10) Get count and address of test input values +0000000000000526 9878 A008 0000000000000008 410 LM R7,R8,8(R10) Get address of result area and flag area. +000000000000052A 1222 411 LTR R2,R2 Any test cases? +000000000000052C 078D 412 BZR R13 ..No, return to caller +000000000000052E 0DC0 413 BASR R12,0 Set top of loop + 414 * +0000000000000530 6880 3000 0000000000000000 415 LD FPR8,0(,R3) Get long BFP test value +0000000000000534 B29D F27C 000000000000027C 416 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000538 B3A9 0018 417 CGDBR R1,0,FPR8 Cvt float in FPR8 to Int in GPR1 +000000000000053C E310 7000 0024 0000000000000000 418 STG R1,0(,R7) Store integer-64 result +0000000000000542 B29C 8000 0000000000000000 419 STFPC 0*4(R8) Store resulting FPCR flags and DXC +0000000000000546 B222 0010 420 IPM R1 Get condition code and program mask +000000000000054A 8810 001C 000000000000001C 421 SRL R1,28 Isolate CC in low order byte +000000000000054E 4210 8003 0000000000000003 422 STC R1,(0*4)+3(,R8) Save CC as low byte of FPCR + 423 * +0000000000000552 B29D F280 0000000000000280 424 LFPC FPCREGTR Set exceptions trappable, clear flags +0000000000000556 B982 0011 425 XGR R1,R1 Clear any residual result in R1 +000000000000055A 0410 426 SPM R1 Clear out any residual nz condition code +000000000000055C B3A9 0018 427 CGDBR R1,0,FPR8 Cvt float in FPR8 to Int in GPR1 +0000000000000560 E310 7008 0024 0000000000000008 428 STG R1,8(,R7) Store integer-64 result +0000000000000566 B29C 8004 0000000000000004 429 STFPC 1*4(R8) Store resulting FPCR flags and DXC +000000000000056A B222 0010 430 IPM R1 Get condition code and program mask +000000000000056E 8810 001C 000000000000001C 431 SRL R1,28 Isolate CC in low order byte +0000000000000572 4210 8007 0000000000000007 432 STC R1,(1*4)+3(,R8) Save CC as low byte of FPCR + 433 * +0000000000000576 4130 3008 0000000000000008 434 LA R3,8(,R3) Point to next input values +000000000000057A 4170 7010 0000000000000010 435 LA R7,16(,R7) Point to next int-64 converted value pair +000000000000057E 4180 8008 0000000000000008 436 LA R8,8(,R8) Point to next FPCR/CC result area +0000000000000582 062C 437 BCTR R2,R12 Convert next input value. +0000000000000584 07FD 438 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvttofix64.asm: Test IEEE Convert To Fixed (int-64) 05 Sep 2016 08:21:23 Page 12 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 440 *********************************************************************** + 441 * + 442 * Convert long BFP to integers using each possible rounding mode. + 443 * Ten test results are generated for each input. A 48-byte test result + 444 * section is used to keep results sets aligned on a quad-double word. + 445 * + 446 * The first four tests use rounding modes specified in the FPC with the + 447 * IEEE Inexact exception supressed. SRNM (2-bit) is used for the + 448 * first two FPCR-controlled tests and SRNMB (3-bit) is used for the + 449 * last two To get full coverage of that instruction pair. + 450 * + 451 * The next six results use instruction-specified rounding modes. + 452 * + 453 * The default rounding mode (0 for RNTE) is not tested in this section; + 454 * prior tests used the default rounding mode. RNTE is tested + 455 * explicitly as a rounding mode in this section. + 456 * + 457 *********************************************************************** + + +0000000000000586 9823 A000 0000000000000000 459 CGDBRA LM R2,R3,0(R10) Get count and address of test input values +000000000000058A 9878 A008 0000000000000008 460 LM R7,R8,8(R10) Get address of result area and flag area. +000000000000058E 1222 461 LTR R2,R2 Any test cases? +0000000000000590 078D 462 BZR R13 ..No, return to caller +0000000000000592 0DC0 463 BASR R12,0 Set top of loop + 464 * +0000000000000594 6880 3000 0000000000000000 465 LD FPR8,0(,R3) Get long BFP test value + 466 * + 467 * Cvt float in FPFPR8 to integer-64 + 468 * + 469 * Test cases using rounding mode specified in the FPCR + 470 * +0000000000000598 B29D F27C 000000000000027C 471 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000059C B2B8 0001 0000000000000001 472 SRNMB 1 SET FPCR to RZ, towards zero. +00000000000005A0 B3A9 0418 473 CGDBRA R1,0,FPR8,B'0100' FPCR ctl'd rounding, inexact masked +00000000000005A4 E310 7000 0024 0000000000000000 474 STG R1,0*8(,R7) Store integer-64 result +00000000000005AA B29C 8000 0000000000000000 475 STFPC 0(R8) Store resulting FPCR flags and DXC +00000000000005AE B222 0010 476 IPM R1 Get condition code and program mask +00000000000005B2 8810 001C 000000000000001C 477 SRL R1,28 Isolate CC in low order byte +00000000000005B6 4210 8003 0000000000000003 478 STC R1,3(,R8) Save CC as low byte of FPCR + 479 * +00000000000005BA B29D F27C 000000000000027C 480 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000005BE B2B8 0002 0000000000000002 481 SRNMB 2 SET FPCR to RP, to +infinity +00000000000005C2 B3A9 0418 482 CGDBRA R1,0,FPR8,B'0100' FPCR ctl'd rounding, inexact masked +00000000000005C6 E310 7008 0024 0000000000000008 483 STG R1,1*8(,R7) Store integer-64 result +00000000000005CC B29C 8004 0000000000000004 484 STFPC 1*4(R8) Store resulting FPCR flags and DXC +00000000000005D0 B222 0010 485 IPM R1 Get condition code and program mask +00000000000005D4 8810 001C 000000000000001C 486 SRL R1,28 Isolate CC in low order byte +00000000000005D8 4210 8007 0000000000000007 487 STC R1,(1*4)+3(,R8) Save CC as low byte of FPCR + 488 * +00000000000005DC B29D F27C 000000000000027C 489 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000005E0 B2B8 0003 0000000000000003 490 SRNMB 3 SET FPCR to RM, to -infinity + ASMA Ver. 0.2.0 ieee-cvttofix64.asm: Test IEEE Convert To Fixed (int-64) 05 Sep 2016 08:21:23 Page 13 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000005E4 B3A9 0418 491 CGDBRA R1,0,FPR8,B'0100' FPCR ctl'd rounding, inexact masked +00000000000005E8 E310 7010 0024 0000000000000010 492 STG R1,2*8(,R7) Store integer-64 result +00000000000005EE B29C 8008 0000000000000008 493 STFPC 2*4(R8) Store resulting FPCR flags and DXC +00000000000005F2 B222 0010 494 IPM R1 Get condition code and program mask +00000000000005F6 8810 001C 000000000000001C 495 SRL R1,28 Isolate CC in low order byte +00000000000005FA 4210 800B 000000000000000B 496 STC R1,(2*4)+3(,R8) Save CC as low byte of FPCR + 497 * +00000000000005FE B29D F27C 000000000000027C 498 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000602 B2B8 0007 0000000000000007 499 SRNMB 7 RPS, Prepare for Shorter Precision +0000000000000606 B3A9 0418 500 CGDBRA R1,0,FPR8,B'0100' FPCR ctl'd rounding, inexact masked +000000000000060A E310 7018 0024 0000000000000018 501 STG R1,3*8(,R7) Store integer-64 result +0000000000000610 B29C 800C 000000000000000C 502 STFPC 3*4(R8) Store resulting FPCR flags and DXC +0000000000000614 B222 0010 503 IPM R1 Get condition code and program mask +0000000000000618 8810 001C 000000000000001C 504 SRL R1,28 Isolate CC in low order byte +000000000000061C 4210 800F 000000000000000F 505 STC R1,(3*4)+3(,R8) Save CC as low byte of FPCR + 506 * +0000000000000620 B29D F27C 000000000000027C 507 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000624 B3A9 1018 508 CGDBRA R1,1,FPR8,B'0000' RNTA, to nearest, ties away +0000000000000628 E310 7020 0024 0000000000000020 509 STG R1,4*8(,R7) Store integer-64 result +000000000000062E B29C 8010 0000000000000010 510 STFPC 4*4(R8) Store resulting FPCR flags and DXC +0000000000000632 B222 0010 511 IPM R1 Get condition code and program mask +0000000000000636 8810 001C 000000000000001C 512 SRL R1,28 Isolate CC in low order byte +000000000000063A 4210 8013 0000000000000013 513 STC R1,(4*4)+3(,R8) Save CC as low byte of FPCR + 514 * +000000000000063E B29D F27C 000000000000027C 515 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000642 B3A9 3018 516 CGDBRA R1,3,FPR8,B'0000' RFS, prepare for shorter precision +0000000000000646 E310 7028 0024 0000000000000028 517 STG R1,5*8(,R7) Store integer-64 result +000000000000064C B29C 8014 0000000000000014 518 STFPC 5*4(R8) Store resulting FPCR flags and DXC +0000000000000650 B222 0010 519 IPM R1 Get condition code and program mask +0000000000000654 8810 001C 000000000000001C 520 SRL R1,28 Isolate CC in low order byte +0000000000000658 4210 8017 0000000000000017 521 STC R1,(5*4)+3(,R8) Save CC as low byte of FPCR + 522 * +000000000000065C B29D F27C 000000000000027C 523 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000660 B3A9 4018 524 CGDBRA R1,4,FPR8,B'0000' RNTE, to nearest, ties to even +0000000000000664 E310 7030 0024 0000000000000030 525 STG R1,6*8(,R7) Store integer-64 result +000000000000066A B29C 8018 0000000000000018 526 STFPC 6*4(R8) Store resulting FPCR flags and DXC +000000000000066E B222 0010 527 IPM R1 Get condition code and program mask +0000000000000672 8810 001C 000000000000001C 528 SRL R1,28 Isolate CC in low order byte +0000000000000676 4210 801B 000000000000001B 529 STC R1,(6*4)+3(,R8) Save CC as low byte of FPCR + 530 * +000000000000067A B29D F27C 000000000000027C 531 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000067E B3A9 5018 532 CGDBRA R1,5,FPR8,B'0000' RZ, toward zero +0000000000000682 E310 7038 0024 0000000000000038 533 STG R1,7*8(,R7) Store integer-64 result +0000000000000688 B29C 801C 000000000000001C 534 STFPC 7*4(R8) Store resulting FPCR flags and DXC +000000000000068C B222 0010 535 IPM R1 Get condition code and program mask +0000000000000690 8810 001C 000000000000001C 536 SRL R1,28 Isolate CC in low order byte +0000000000000694 4210 801F 000000000000001F 537 STC R1,(7*4)+3(,R8) Save CC as low byte of FPCR + 538 * +0000000000000698 B29D F27C 000000000000027C 539 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000069C B3A9 6018 540 CGDBRA R1,6,FPR8,B'0000' RP, to +inf +00000000000006A0 E310 7040 0024 0000000000000040 541 STG R1,8*8(,R7) Store integer-64 result +00000000000006A6 B29C 8020 0000000000000020 542 STFPC 8*4(R8) Store resulting FPCR flags and DXC + ASMA Ver. 0.2.0 ieee-cvttofix64.asm: Test IEEE Convert To Fixed (int-64) 05 Sep 2016 08:21:23 Page 14 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000006AA B222 0010 543 IPM R1 Get condition code and program mask +00000000000006AE 8810 001C 000000000000001C 544 SRL R1,28 Isolate CC in low order byte +00000000000006B2 4210 8023 0000000000000023 545 STC R1,(8*4)+3(,R8) Save CC as low byte of FPCR + 546 * +00000000000006B6 B29D F27C 000000000000027C 547 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000006BA B3A9 7018 548 CGDBRA R1,7,FPR8,B'0000' RM, to -inf +00000000000006BE E310 7048 0024 0000000000000048 549 STG R1,9*8(,R7) Store integer-64 result +00000000000006C4 B29C 8024 0000000000000024 550 STFPC 9*4(R8) Store resulting FPCR flags and DXC +00000000000006C8 B222 0010 551 IPM R1 Get condition code and program mask +00000000000006CC 8810 001C 000000000000001C 552 SRL R1,28 Isolate CC in low order byte +00000000000006D0 4210 8027 0000000000000027 553 STC R1,(9*4)+3(,R8) Save CC as low byte of FPCR + 554 * +00000000000006D4 4130 3008 0000000000000008 555 LA R3,8(,R3) Point to next input value +00000000000006D8 4170 7050 0000000000000050 556 LA R7,10*8(,R7) Point to next long BFP converted values +00000000000006DC 4180 8030 0000000000000030 557 LA R8,12*4(,R8) Point to next FPCR/CC result area +00000000000006E0 062C 558 BCTR R2,R12 Convert next input value. +00000000000006E2 07FD 559 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvttofix64.asm: Test IEEE Convert To Fixed (int-64) 05 Sep 2016 08:21:23 Page 15 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 561 *********************************************************************** + 562 * + 563 * Convert extended BFP to integer-64. A pair of results is generated + 564 * for each input: one with all exceptions non-trappable, and the + 565 * second with all exceptions trappable. The FPCR and condition code + 566 * are stored for each result. + 567 * + 568 *********************************************************************** + + +00000000000006E4 9823 A000 0000000000000000 570 CGXBR LM R2,R3,0(R10) Get count and address of test input values +00000000000006E8 9878 A008 0000000000000008 571 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000006EC 1222 572 LTR R2,R2 Any test cases? +00000000000006EE 078D 573 BZR R13 ..No, return to caller +00000000000006F0 0DC0 574 BASR R12,0 Set top of loop + 575 * +00000000000006F2 6880 3000 0000000000000000 576 LD FPR8,0(,R3) Get extended BFP test value part 1 +00000000000006F6 68A0 3008 0000000000000008 577 LD FPR10,8(,R3) Get extended BFP test value part 1 +00000000000006FA B29D F27C 000000000000027C 578 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000006FE B3AA 0018 579 CGXBR R1,0,FPR8 Cvt float in FPR8-FPR10 to Int-64 in GPR1 +0000000000000702 E310 7000 0024 0000000000000000 580 STG R1,0(,R7) Store integer-64 result +0000000000000708 B29C 8000 0000000000000000 581 STFPC (0*4)(R8) Store resulting FPCR flags and DXC +000000000000070C B222 0010 582 IPM R1 Get condition code and program mask +0000000000000710 8810 001C 000000000000001C 583 SRL R1,28 Isolate CC in low order byte +0000000000000714 4210 8003 0000000000000003 584 STC R1,(0*4)+3(,R8) Save CC as low byte of FPCR + 585 * +0000000000000718 B29D F280 0000000000000280 586 LFPC FPCREGTR Set exceptions trappable, clear flags +000000000000071C B982 0011 587 XGR R1,R1 Clear any residual result in R1 +0000000000000720 0410 588 SPM R1 Clear out any residual nz condition code +0000000000000722 B3AA 0018 589 CGXBR R1,0,FPR8 Cvt float in FPR8-FPR10 to Int-64 in GPR1 +0000000000000726 E310 7008 0024 0000000000000008 590 STG R1,8(,R7) Store integer-64 result +000000000000072C B29C 8004 0000000000000004 591 STFPC (1*4)(R8) Store resulting FPCR flags and DXC +0000000000000730 B222 0010 592 IPM R1 Get condition code and program mask +0000000000000734 8810 001C 000000000000001C 593 SRL R1,28 Isolate CC in low order byte +0000000000000738 4210 8007 0000000000000007 594 STC R1,(1*4)+3(,R8) Save CC as low byte of FPCR + 595 * +000000000000073C 4130 3010 0000000000000010 596 LA R3,16(,R3) Point to next extended BFP input value +0000000000000740 4170 7010 0000000000000010 597 LA R7,16(,R7) Point to next int-64 converted value pair +0000000000000744 4180 8008 0000000000000008 598 LA R8,8(,R8) Point to next FPCR/CC result area +0000000000000748 062C 599 BCTR R2,R12 Convert next input value. +000000000000074A 07FD 600 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvttofix64.asm: Test IEEE Convert To Fixed (int-64) 05 Sep 2016 08:21:23 Page 16 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 602 *********************************************************************** + 603 * + 604 * Convert extended BFP to integers using each possible rounding mode. + 605 * Ten test results are generated for each input. A 48-byte test result + 606 * section is used to keep results sets aligned on a quad-double word. + 607 * + 608 * The first four tests use rounding modes specified in the FPC with the + 609 * IEEE Inexact exception supressed. SRNM (2-bit) is used for the + 610 * first two FPCR-controlled tests and SRNMB (3-bit) is used for the + 611 * last two To get full coverage of that instruction pair. + 612 * + 613 * The next six results use instruction-specified rounding modes. + 614 * + 615 * The default rounding mode (0 for RNTE) is not tested in this section; + 616 * prior tests used the default rounding mode. RNTE is tested + 617 * explicitly as a rounding mode in this section. + 618 * + 619 *********************************************************************** + + +000000000000074C 9823 A000 0000000000000000 621 CGXBRA LM R2,R3,0(R10) Get count and address of test input values +0000000000000750 9878 A008 0000000000000008 622 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000754 1222 623 LTR R2,R2 Any test cases? +0000000000000756 078D 624 BZR R13 ..No, return to caller +0000000000000758 0DC0 625 BASR R12,0 Set top of loop + 626 * +000000000000075A 6880 3000 0000000000000000 627 LD FPR8,0(,R3) Get extended BFP test value part 1 +000000000000075E 68A0 3008 0000000000000008 628 LD FPR10,8(,R3) Get extended BFP test value part 2 + 629 * + 630 * Test cases using rounding mode specified in the FPCR + 631 * +0000000000000762 B29D F27C 000000000000027C 632 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000766 B2B8 0001 0000000000000001 633 SRNMB 1 SET FPCR to RZ, towards zero. +000000000000076A B3AA 0418 634 CGXBRA R1,0,FPR8,B'0100' FPCR ctl'd rounding, inexact masked +000000000000076E E310 7000 0024 0000000000000000 635 STG R1,0*8(,R7) Store integer-64 result +0000000000000774 B29C 8000 0000000000000000 636 STFPC 0(R8) Store resulting FPCR flags and DXC +0000000000000778 B222 0010 637 IPM R1 Get condition code and program mask +000000000000077C 8810 001C 000000000000001C 638 SRL R1,28 Isolate CC in low order byte +0000000000000780 4210 8003 0000000000000003 639 STC R1,3(,R8) Save CC as low byte of FPCR + 640 * +0000000000000784 B29D F27C 000000000000027C 641 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000788 B2B8 0002 0000000000000002 642 SRNMB 2 SET FPCR to RP, to +infinity +000000000000078C B3AA 0418 643 CGXBRA R1,0,FPR8,B'0100' FPCR ctl'd rounding, inexact masked +0000000000000790 E310 7008 0024 0000000000000008 644 STG R1,1*8(,R7) Store integer-64 result +0000000000000796 B29C 8004 0000000000000004 645 STFPC 1*4(R8) Store resulting FPCR flags and DXC +000000000000079A B222 0010 646 IPM R1 Get condition code and program mask +000000000000079E 8810 001C 000000000000001C 647 SRL R1,28 Isolate CC in low order byte +00000000000007A2 4210 8007 0000000000000007 648 STC R1,(1*4)+3(,R8) Save CC as low byte of FPCR + 649 * +00000000000007A6 B29D F27C 000000000000027C 650 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000007AA B2B8 0003 0000000000000003 651 SRNMB 3 SET FPCR to RM, to -infinity +00000000000007AE B3AA 0418 652 CGXBRA R1,0,FPR8,B'0100' FPCR ctl'd rounding, inexact masked + ASMA Ver. 0.2.0 ieee-cvttofix64.asm: Test IEEE Convert To Fixed (int-64) 05 Sep 2016 08:21:23 Page 17 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000007B2 E310 7010 0024 0000000000000010 653 STG R1,2*8(,R7) Store integer-64 result +00000000000007B8 B29C 8008 0000000000000008 654 STFPC 2*4(R8) Store resulting FPCR flags and DXC +00000000000007BC B222 0010 655 IPM R1 Get condition code and program mask +00000000000007C0 8810 001C 000000000000001C 656 SRL R1,28 Isolate CC in low order byte +00000000000007C4 4210 800B 000000000000000B 657 STC R1,(2*4)+3(,R8) Save CC as low byte of FPCR + 658 * +00000000000007C8 B29D F27C 000000000000027C 659 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000007CC B2B8 0007 0000000000000007 660 SRNMB 7 RPS, Prepare for Shorter Precision +00000000000007D0 B3AA 0418 661 CGXBRA R1,0,FPR8,B'0100' FPCR ctl'd rounding, inexact masked +00000000000007D4 E310 7018 0024 0000000000000018 662 STG R1,3*8(,R7) Store integer-64 result +00000000000007DA B29C 800C 000000000000000C 663 STFPC 3*4(R8) Store resulting FPCR flags and DXC +00000000000007DE B222 0010 664 IPM R1 Get condition code and program mask +00000000000007E2 8810 001C 000000000000001C 665 SRL R1,28 Isolate CC in low order byte +00000000000007E6 4210 800F 000000000000000F 666 STC R1,(3*4)+3(,R8) Save CC as low byte of FPCR + 667 * +00000000000007EA B29D F27C 000000000000027C 668 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000007EE B3AA 1018 669 CGXBRA R1,1,FPR8,B'0000' RNTA, to nearest, ties away +00000000000007F2 E310 7020 0024 0000000000000020 670 STG R1,4*8(,R7) Store integer-64 result +00000000000007F8 B29C 8010 0000000000000010 671 STFPC 4*4(R8) Store resulting FPCR flags and DXC +00000000000007FC B222 0010 672 IPM R1 Get condition code and program mask +0000000000000800 8810 001C 000000000000001C 673 SRL R1,28 Isolate CC in low order byte +0000000000000804 4210 8013 0000000000000013 674 STC R1,(4*4)+3(,R8) Save CC as low byte of FPCR + 675 * +0000000000000808 B29D F27C 000000000000027C 676 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000080C B3AA 3018 677 CGXBRA R1,3,FPR8,B'0000' RFS, prepare for shorter precision +0000000000000810 E310 7028 0024 0000000000000028 678 STG R1,5*8(,R7) Store integer-64 result +0000000000000816 B29C 8014 0000000000000014 679 STFPC 5*4(R8) Store resulting FPCR flags and DXC +000000000000081A B222 0010 680 IPM R1 Get condition code and program mask +000000000000081E 8810 001C 000000000000001C 681 SRL R1,28 Isolate CC in low order byte +0000000000000822 4210 8017 0000000000000017 682 STC R1,(5*4)+3(,R8) Save CC as low byte of FPCR + 683 * +0000000000000826 B29D F27C 000000000000027C 684 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000082A B3AA 4018 685 CGXBRA R1,4,FPR8,B'0000' RNTE to nearest, ties to even +000000000000082E E310 7030 0024 0000000000000030 686 STG R1,6*8(,R7) Store integer-64 result +0000000000000834 B29C 8018 0000000000000018 687 STFPC 6*4(R8) Store resulting FPCR flags and DXC +0000000000000838 B222 0010 688 IPM R1 Get condition code and program mask +000000000000083C 8810 001C 000000000000001C 689 SRL R1,28 Isolate CC in low order byte +0000000000000840 4210 801B 000000000000001B 690 STC R1,(6*4)+3(,R8) Save CC as low byte of FPCR + 691 * +0000000000000844 B29D F27C 000000000000027C 692 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000848 B3AA 5018 693 CGXBRA R1,5,FPR8,B'0000' RZ toward zero +000000000000084C E310 7038 0024 0000000000000038 694 STG R1,7*8(,R7) Store integer-64 result +0000000000000852 B29C 801C 000000000000001C 695 STFPC 7*4(R8) Store resulting FPCR flags and DXC +0000000000000856 B222 0010 696 IPM R1 Get condition code and program mask +000000000000085A 8810 001C 000000000000001C 697 SRL R1,28 Isolate CC in low order byte +000000000000085E 4210 801F 000000000000001F 698 STC R1,(7*4)+3(,R8) Save CC as low byte of FPCR + 699 * +0000000000000862 B29D F27C 000000000000027C 700 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000866 B3AA 6018 701 CGXBRA R1,6,FPR8,B'0000' to +inf +000000000000086A E310 7040 0024 0000000000000040 702 STG R1,8*8(,R7) Store integer-64 result +0000000000000870 B29C 8020 0000000000000020 703 STFPC 8*4(R8) Store resulting FPCR flags and DXC +0000000000000874 B222 0010 704 IPM R1 Get condition code and program mask + ASMA Ver. 0.2.0 ieee-cvttofix64.asm: Test IEEE Convert To Fixed (int-64) 05 Sep 2016 08:21:23 Page 18 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000878 8810 001C 000000000000001C 705 SRL R1,28 Isolate CC in low order byte +000000000000087C 4210 8023 0000000000000023 706 STC R1,(8*4)+3(,R8) Save CC as low byte of FPCR + 707 * +0000000000000880 B29D F27C 000000000000027C 708 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000884 B3AA 7018 709 CGXBRA R1,7,FPR8,B'0000' to -inf +0000000000000888 E310 7048 0024 0000000000000048 710 STG R1,9*8(,R7) Store integer-64 result +000000000000088E B29C 8024 0000000000000024 711 STFPC 9*4(R8) Store resulting FPCR flags and DXC +0000000000000892 B222 0010 712 IPM R1 Get condition code and program mask +0000000000000896 8810 001C 000000000000001C 713 SRL R1,28 Isolate CC in low order byte +000000000000089A 4210 8027 0000000000000027 714 STC R1,(9*4)+3(,R8) Save CC as low byte of FPCR + 715 * +000000000000089E 4130 3010 0000000000000010 716 LA R3,16(,R3) Point to next input value +00000000000008A2 4170 7050 0000000000000050 717 LA R7,10*8(,R7) Point to next long BFP converted values +00000000000008A6 4180 8030 0000000000000030 718 LA R8,12*4(,R8) Point to next FPCR/CC result area +00000000000008AA 062C 719 BCTR R2,R12 Convert next input value. +00000000000008AC 07FD 720 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvttofix64.asm: Test IEEE Convert To Fixed (int-64) 05 Sep 2016 08:21:23 Page 19 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 722 *********************************************************************** + 723 * + 724 * Floating point inputs for Convert From Fixed testing. The same test + 725 * values in the appropriate input format are used for short, long, + 726 * and extended format tests. The last four values should generate + 727 * exceptions. + 728 * + 729 *********************************************************************** + + + 731 * + 732 * Inputs for basic tests of short BFP to int-64 + 733 * +00000000000008B0 734 SBFPIN DS 0F Inputs for short BFP testing +00000000000008B0 3F800000 735 DC X'3F800000' +1.0 +00000000000008B4 40000000 736 DC X'40000000' +2.0 +00000000000008B8 40800000 737 DC X'40800000' +4.0 +00000000000008BC C0000000 738 DC X'C0000000' -2.0 +00000000000008C0 7F810000 739 DC X'7F810000' SNaN +00000000000008C4 7FC10000 740 DC X'7FC10000' QNaN +00000000000008C8 5F000000 741 DC X'5F000000' +max int-64 + 1 + 742 * +9,223,372,036,854,775,807 + 1 +00000000000008CC DF000001 743 DC X'DF000001' -max int-64 - 2 + 744 * -9,223,372,036,854,775,807 - 2 +00000000000008D0 5EFFFFFF 745 DC X'5EFFFFFF' Largest short BFP that fits in int-64 + 746 * +9,223,371,487,098,961,920 + 747 * = 0x7FFFFF80000000000 + 0000000000000024 0000000000000001 748 SBFPCT EQU *-SBFPIN Count of short BFP in list * 4 + 749 * + 750 * Inputs for exhaustive rounding mode tests of short BFP to int-64 + 751 * +00000000000008D4 752 SBFPINRM DS 0F +00000000000008D4 C1180000 753 DC X'C1180000' -9.5 +00000000000008D8 C0B00000 754 DC X'C0B00000' -5.5 +00000000000008DC C0200000 755 DC X'C0200000' -2.5 +00000000000008E0 BFC00000 756 DC X'BFC00000' -1.5 +00000000000008E4 BF000000 757 DC X'BF000000' -0.5 +00000000000008E8 3F000000 758 DC X'3F000000' +0.5 +00000000000008EC 3FC00000 759 DC X'3FC00000' +1.5 +00000000000008F0 40200000 760 DC X'40200000' +2.5 +00000000000008F4 40B00000 761 DC X'40B00000' +5.5 +00000000000008F8 41180000 762 DC X'41180000' +9.5 +00000000000008FC 3F400000 763 DC X'3F400000' +0.75 +0000000000000900 3E800000 764 DC X'3E800000' +0.25 +0000000000000904 BF400000 765 DC X'BF400000' -0.75 +0000000000000908 BE800000 766 DC X'BE800000' -0.25 + 0000000000000038 0000000000000001 767 SBFPRMCT EQU *-SBFPINRM Count of short BFP * 4 for rounding tests + 768 * + 769 * Inputs for basic tests of long BFP to int-64 + 770 * +000000000000090C 771 LBFPIN DS 0F Inputs for long BFP testing +000000000000090C 3FF00000 00000000 772 DC X'3FF0000000000000' +1.0 + ASMA Ver. 0.2.0 ieee-cvttofix64.asm: Test IEEE Convert To Fixed (int-64) 05 Sep 2016 08:21:23 Page 20 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000914 40000000 00000000 773 DC X'4000000000000000' +2.0 +000000000000091C 40100000 00000000 774 DC X'4010000000000000' +4.0 +0000000000000924 C0000000 00000000 775 DC X'C000000000000000' -2.0 +000000000000092C 7FF01000 00000000 776 DC X'7FF0100000000000' SNaN +0000000000000934 7FF81000 00000000 777 DC X'7FF8100000000000' QNaN +000000000000093C 43E00000 00000000 778 DC X'43E0000000000000' +max int-64 + 1. + 779 * (+9,223,372,036,854,775,807 + 1) +0000000000000944 C3E00000 00100000 780 DC X'C3E0000000100000' -max int-64 - 2 + 781 * (-9,223,372,036,854,775,807 - 2) +000000000000094C 43DFFFFF FFFFFFFF 782 DC X'43DFFFFFFFFFFFFF' Largest long BFP that fits in + 783 * ..int-64: 9,223,372,036,854,774,784, + 784 * .. 0x7FFFFFFFFFFFF800 + 0000000000000048 0000000000000001 785 LBFPCT EQU *-LBFPIN Count of long BFP in list * 8 + 786 * + 787 * Inputs for exhaustive rounding mode tests of long BFP to int-64 + 788 * +0000000000000954 789 LBFPINRM DS 0F +0000000000000954 C0230000 00000000 790 DC X'C023000000000000' -9.5 +000000000000095C C0160000 00000000 791 DC X'C016000000000000' -5.5 +0000000000000964 C0040000 00000000 792 DC X'C004000000000000' -2.5 +000000000000096C BFF80000 00000000 793 DC X'BFF8000000000000' -1.5 +0000000000000974 BFE00000 00000000 794 DC X'BFE0000000000000' -0.5 +000000000000097C 3FE00000 00000000 795 DC X'3FE0000000000000' +0.5 +0000000000000984 3FF80000 00000000 796 DC X'3FF8000000000000' +1.5 +000000000000098C 40040000 00000000 797 DC X'4004000000000000' +2.5 +0000000000000994 40160000 00000000 798 DC X'4016000000000000' +5.5 +000000000000099C 40230000 00000000 799 DC X'4023000000000000' +9.5 +00000000000009A4 3FE80000 00000000 800 DC X'3FE8000000000000' +0.75 +00000000000009AC 3FD00000 00000000 801 DC X'3FD0000000000000' +0.25 +00000000000009B4 BFE80000 00000000 802 DC X'BFE8000000000000' -0.75 +00000000000009BC BFD00000 00000000 803 DC X'BFD0000000000000' -0.25 + 0000000000000070 0000000000000001 804 LBFPRMCT EQU *-LBFPINRM Count of long BFP * 8 for rounding tests + 805 * + 806 * Inputs for basic tests of extended BFP to int-64 + 807 * +00000000000009C8 808 XBFPIN DS 0D Inputs for long BFP testing +00000000000009C8 3FFF0000 00000000 809 DC X'3FFF0000000000000000000000000000' +1.0 +00000000000009D8 40000000 00000000 810 DC X'40000000000000000000000000000000' +2.0 +00000000000009E8 40010000 00000000 811 DC X'40010000000000000000000000000000' +4.0 +00000000000009F8 C0000000 00000000 812 DC X'C0000000000000000000000000000000' -2.0 +0000000000000A08 7FFF0100 00000000 813 DC X'7FFF0100000000000000000000000000' SNaN +0000000000000A18 7FFF8100 00000000 814 DC X'7FFF8100000000000000000000000000' QNaN +0000000000000A28 403E0000 00000000 815 DC X'403E0000000000000000000000000000' +max int-64 + 1 + 816 * (+9223372036854775807 + 1) +0000000000000A38 C03E0000 00010000 817 DC X'C03E0000000100000000000000000000' -max int-64 - 2 + 818 * (-9223372036854775807 - 2) +0000000000000A48 403DFFFF FFFFFFFF 819 DC X'403DFFFFFFFFFFFFFFFC000000000000' +max int-64 + 0000000000000090 0000000000000001 820 XBFPCT EQU *-XBFPIN Count of extended BFP in list * 16 + 821 * + 822 * Inputs for exhaustive rounding mode tests of extended BFP to int-64 + 823 * +0000000000000A58 824 XBFPINRM DS 0D + ASMA Ver. 0.2.0 ieee-cvttofix64.asm: Test IEEE Convert To Fixed (int-64) 05 Sep 2016 08:21:23 Page 21 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000A58 C0023000 00000000 825 DC X'C0023000000000000000000000000000' -9.5 +0000000000000A68 C0016000 00000000 826 DC X'C0016000000000000000000000000000' -5.5 +0000000000000A78 C0004000 00000000 827 DC X'C0004000000000000000000000000000' -2.5 +0000000000000A88 BFFF8000 00000000 828 DC X'BFFF8000000000000000000000000000' -1.5 +0000000000000A98 BFFE0000 00000000 829 DC X'BFFE0000000000000000000000000000' -0.5 +0000000000000AA8 3FFE0000 00000000 830 DC X'3FFE0000000000000000000000000000' +0.5 +0000000000000AB8 3FFF8000 00000000 831 DC X'3FFF8000000000000000000000000000' +1.5 +0000000000000AC8 40004000 00000000 832 DC X'40004000000000000000000000000000' +2.5 +0000000000000AD8 40016000 00000000 833 DC X'40016000000000000000000000000000' +5.5 +0000000000000AE8 40023000 00000000 834 DC X'40023000000000000000000000000000' +9.5 +0000000000000AF8 3FFE8000 00000000 835 DC X'3FFE8000000000000000000000000000' +0.75 +0000000000000B08 3FFD0000 00000000 836 DC X'3FFD0000000000000000000000000000' +0.25 +0000000000000B18 BFFE8000 00000000 837 DC X'BFFE8000000000000000000000000000' -0.75 +0000000000000B28 BFFD0000 00000000 838 DC X'BFFD0000000000000000000000000000' -0.25 +0000000000000B38 403DFFFF FFFFFFFF 839 DC X'403DFFFFFFFFFFFFFFFE000000000000' max int-64 + 0.5 + 840 * 9,223,372,036,854,775,807.5, overflows on some + 841 * ..but not all rounding modes + 00000000000000F0 0000000000000001 842 XBFPRMCT EQU *-XBFPINRM Count of ext'd BFP * 16 for rounding tests + 843 * + 844 * Locations for results + 845 * + 0000000000001000 0000000000000000 846 SINTOUT EQU BFPCVTTF+X'1000' Integer-64 values from short BFP + 847 * ..8 pairs used, room for 32 + 0000000000001200 0000000000000000 848 SINTFLGS EQU BFPCVTTF+X'1200' FPCR flags and DXC from short BFP + 849 * ..8 pairs used,room for 32 + 0000000000001300 0000000000000000 850 SINTRMO EQU BFPCVTTF+X'1300' Short rounding mode test results + 851 * ..10 sets used, room for 16 + 0000000000001800 0000000000000000 852 SINTRMOF EQU BFPCVTTF+X'1800' Short rounding mode FPCR contents + 853 * ..10 sets used, room for 16 + 854 * + 0000000000002000 0000000000000000 855 LINTOUT EQU BFPCVTTF+X'2000' Integer-64 values from long BFP + 856 * ..8 pairs used, room for 32 + 0000000000002200 0000000000000000 857 LINTFLGS EQU BFPCVTTF+X'2200' FPCR flags and DXC from long BFP + 858 * ..8 pairs used,room for 32 + 0000000000002300 0000000000000000 859 LINTRMO EQU BFPCVTTF+X'2300' Long rounding mode test results + 860 * ..10 sets used, room for 16 + 0000000000002800 0000000000000000 861 LINTRMOF EQU BFPCVTTF+X'2800' Long rounding mode FPCR contents + 862 * ..10 sets used, room for 16 + 863 * + 0000000000003000 0000000000000000 864 XINTOUT EQU BFPCVTTF+X'3000' Integer-64 values from extended BFP + 865 * ..8 pairs used, room for 32 + 0000000000003200 0000000000000000 866 XINTFLGS EQU BFPCVTTF+X'3200' FPCR flags and DXC from extended BFP + 867 * ..8 pairs used, room for 32 + 0000000000003300 0000000000000000 868 XINTRMO EQU BFPCVTTF+X'3300' Extended rounding mode test results + 869 * ..10 sets used, room for 16 + 0000000000003800 0000000000000000 870 XINTRMOF EQU BFPCVTTF+X'3800' Extended rndg mode FPCR contents + 871 * ..10 sets used, room for 16 + 872 * + 0000000000003B00 0000000000000000 873 ENDLABL EQU BFPCVTTF+X'3B00' Next available location + 874 PADCSECT ENDLABL + 875+ MNOTE *,'asma detected; no CSECT padding performed' +0000000000000B48 876 END + ASMA Ver. 0.2.0 ieee-cvttofix64.asm: Test IEEE Convert To Fixed (int-64) 05 Sep 2016 08:21:23 Page 22 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +BFPCVTTF J 000000 2888 85 134 137 139 142 150 207 846 848 850 852 855 857 859 861 864 866 868 + 870 873 +CGDBR I 000522 4 409 178 +CGDBRA I 000586 4 459 180 +CGEBR I 000360 4 250 171 +CGEBRA I 0003C4 4 300 173 +CGXBR I 0006E4 4 570 185 +CGXBRA I 00074C 4 621 187 +CTLR0 F 000278 4 197 164 165 166 +ENDLABL U 003B00 0 873 +EXTDS F 000320 4 220 184 +FPCREGNT X 00027C 4 198 257 310 319 328 337 346 354 362 370 378 386 416 471 480 489 498 507 + 515 523 531 539 547 578 632 641 650 659 668 676 684 692 700 708 +FPCREGTR X 000280 4 199 265 424 586 +FPR0 U 000000 1 105 +FPR1 U 000001 1 106 +FPR10 U 00000A 1 115 577 628 +FPR11 U 00000B 1 116 +FPR12 U 00000C 1 117 +FPR13 U 00000D 1 118 +FPR14 U 00000E 1 119 +FPR15 U 00000F 1 120 +FPR2 U 000002 1 107 +FPR3 U 000003 1 108 +FPR4 U 000004 1 109 +FPR5 U 000005 1 110 +FPR6 U 000006 1 111 +FPR7 U 000007 1 112 +FPR8 U 000008 1 113 256 258 268 306 312 321 330 339 347 355 363 371 379 387 415 417 427 + 465 473 482 491 500 508 516 524 532 540 548 576 579 589 627 634 643 + 652 661 669 677 685 693 701 709 +FPR9 U 000009 1 114 +HARDWAIT X 000268 8 195 158 +IMAGE 1 000000 2888 0 +LBFPCT U 000048 1 785 215 +LBFPIN F 00090C 4 771 785 216 +LBFPINRM F 000954 4 789 804 232 +LBFPRMCT U 000070 1 804 231 +LINTFLGS U 002200 0 857 218 +LINTOUT U 002000 0 855 217 +LINTRMO U 002300 0 859 233 +LINTRMOF U 002800 0 861 234 +LONGS F 000310 4 214 177 +PCINTCD H 00008E 2 135 152 +PCNOTDTA H 00020C 2 155 153 +PCOLDPSW U 000150 0 137 154 +PROGCHK H 000200 2 151 143 +R0 U 000000 1 86 164 166 +R1 U 000001 1 87 258 259 261 262 263 266 267 268 269 271 272 273 312 313 315 316 317 + 321 322 324 325 326 330 331 333 334 335 339 340 342 343 344 347 348 + 350 351 352 355 356 358 359 360 363 364 366 367 368 371 372 374 375 + 376 379 380 382 383 384 387 388 390 391 392 417 418 420 421 422 425 + ASMA Ver. 0.2.0 ieee-cvttofix64.asm: Test IEEE Convert To Fixed (int-64) 05 Sep 2016 08:21:23 Page 23 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + + 426 427 428 430 431 432 473 474 476 477 478 482 483 485 486 487 491 + 492 494 495 496 500 501 503 504 505 508 509 511 512 513 516 517 519 + 520 521 524 525 527 528 529 532 533 535 536 537 540 541 543 544 545 + 548 549 551 552 553 579 580 582 583 584 587 588 589 590 592 593 594 + 634 635 637 638 639 643 644 646 647 648 652 653 655 656 657 661 662 + 664 665 666 669 670 672 673 674 677 678 680 681 682 685 686 688 689 + 690 693 694 696 697 698 701 702 704 705 706 709 710 712 713 714 +R10 U 00000A 1 96 170 172 177 179 184 186 250 251 300 301 409 410 459 460 570 571 621 + 622 +R11 U 00000B 1 97 +R12 U 00000C 1 98 254 278 304 397 413 437 463 558 574 599 625 719 +R13 U 00000D 1 99 171 173 178 180 185 187 253 279 303 398 412 438 462 559 573 600 624 + 720 +R14 U 00000E 1 100 156 157 189 190 +R15 U 00000F 1 101 122 +R2 U 000002 1 88 250 252 278 300 302 397 409 411 437 459 461 558 570 572 599 621 623 + 719 +R3 U 000003 1 89 250 256 275 300 306 394 409 415 434 459 465 555 570 576 577 596 621 + 627 628 716 +R4 U 000004 1 90 +R5 U 000005 1 91 +R6 U 000006 1 92 +R7 U 000007 1 93 251 259 269 276 301 313 322 331 340 348 356 364 372 380 388 395 410 + 418 428 435 460 474 483 492 501 509 517 525 533 541 549 556 571 580 + 590 597 622 635 644 653 662 670 678 686 694 702 710 717 +R8 U 000008 1 94 251 260 263 270 273 277 301 314 317 323 326 332 335 341 344 349 352 + 357 360 365 368 373 376 381 384 389 392 396 410 419 422 429 432 436 + 460 475 478 484 487 493 496 502 505 510 513 518 521 526 529 534 537 + 542 545 550 553 557 571 581 584 591 594 598 622 636 639 645 648 654 + 657 663 666 671 674 679 682 687 690 695 698 703 706 711 714 718 +R9 U 000009 1 95 +RMEXTDS A 000350 4 236 186 +RMLONGS A 000340 4 231 179 +RMSHORTS A 000330 4 226 172 +SBFPCT U 000024 1 748 209 +SBFPIN F 0008B0 4 734 748 210 +SBFPINRM F 0008D4 4 752 767 227 +SBFPRMCT U 000038 1 767 226 +SHORTS F 000300 4 208 170 +SINTFLGS U 001200 0 848 212 +SINTOUT U 001000 0 846 211 +SINTRMO U 001300 0 850 228 +SINTRMOF U 001800 0 852 229 +START I 000214 4 164 140 +WAITPSW X 000258 8 194 191 +XBFPCT U 000090 1 820 221 +XBFPIN D 0009C8 8 808 820 222 +XBFPINRM D 000A58 8 824 842 237 +XBFPRMCT U 0000F0 1 842 236 +XINTFLGS U 003200 0 866 224 +XINTOUT U 003000 0 864 223 +XINTRMO U 003300 0 868 238 + ASMA Ver. 0.2.0 ieee-cvttofix64.asm: Test IEEE Convert To Fixed (int-64) 05 Sep 2016 08:21:23 Page 24 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +XINTRMOF U 003800 0 870 239 + ASMA Ver. 0.2.0 ieee-cvttofix64.asm: Test IEEE Convert To Fixed (int-64) 05 Sep 2016 08:21:23 Page 25 + + MACRO DEFN REFERENCES + +PADCSECT 60 874 + ASMA Ver. 0.2.0 ieee-cvttofix64.asm: Test IEEE Convert To Fixed (int-64) 05 Sep 2016 08:21:23 Page 26 + + DESC SYMBOL SIZE POS ADDR + +Entry: 0 + +Image IMAGE 2888 000-B47 000-B47 + Region 2888 000-B47 000-B47 + CSECT BFPCVTTF 2888 000-B47 000-B47 + ASMA Ver. 0.2.0 ieee-cvttofix64.asm: Test IEEE Convert To Fixed (int-64) 05 Sep 2016 08:21:23 Page 27 + + STMT FILE NAME + +1 C:\Users\srorso\Documents\GitHub\hyperion\tests\bfp-007-cvttofix64.asm + + +** NO ERRORS FOUND ** + +[875] MNOTE *,asma detected; no CSECT padding performed + \ No newline at end of file diff --git a/tests/bfp-007-cvttofix64.tst b/tests/bfp-007-cvttofix64.tst new file mode 100644 index 000000000..f1cfc17f5 --- /dev/null +++ b/tests/bfp-007-cvttofix64.tst @@ -0,0 +1,922 @@ +*Testcase bfp-007-cvttofix64.tst: CGEBR, CGBRA, CGDBR, CGDBRA, CGXBR, CGXBRA + +#Testcase bfp-007-cvttofix64.tst: IEEE Convert To Fixed +#..Includes CONVERT TO FIXED 64 (6). Tests traps, exceptions +#..results from different rounding modes, and NaN propagation. + +sysclear +archmode esame + +# +# Following suppresses logging of program checks. This test program, as part +# of its normal operation, generates 12 program check messages that have no +# value in the validation process. (The messages, not the program checks.) +# +ostailor quiet + +loadcore "$(testpath)/bfp-007-cvttofix64.core" + +runtest 1.0 + +ostailor null # restore messages for subsequent tests + + +# Short BFP inputs to int-64 - results +*Compare +r 1000.10 +*Want "CGEBR result pair 1" 00000000 00000001 00000000 00000001 +r 1010.10 +*Want "CGEBR result pair 2" 00000000 00000002 00000000 00000002 +r 1020.10 +*Want "CGEBR result pair 3" 00000000 00000004 00000000 00000004 +r 1030.10 +*Want "CGEBR result pair 4" FFFFFFFF FFFFFFFE FFFFFFFF FFFFFFFE +r 1040.10 +*Want "CGEBR result pair 5" 80000000 00000000 00000000 00000000 +r 1050.10 +*Want "CGEBR result pair 6" 80000000 00000000 00000000 00000000 +r 1060.10 +*Want "CGEBR result pair 7" 7FFFFFFF FFFFFFFF 00000000 00000000 +r 1070.10 +*Want "CGEBR result pair 8" 80000000 00000000 00000000 00000000 +r 1080.10 +*Want "CGEBR result pair 9" 7FFFFF80 00000000 7FFFFF80 00000000 + +# Short BFP inputs to int-64 - FPCR contents +*Compare +r 1200.10 +*Want "CGEBR FPCR pairs 1-2" 00000002 F8000002 00000002 F8000002 +r 1210.10 +*Want "CGEBR FPCR pairs 3-4" 00000002 F8000002 00000001 F8000001 +r 1220.10 +*Want "CGEBR FPCR pairs 5-6" 00880003 F8008000 00880003 F8008000 +r 1230.10 +*Want "CGEBR FPCR pairs 7-8" 00880003 F8008000 00880003 F8008000 +r 1240.08 +*Want "CGEBR FPCR pair 9" 00000002 F8000002 + +# rounding mode tests - short BFP - results from rounding +*Compare +r 1300.10 # RZ, RP +*Want "CGEBRA -9.5 FPCR modes 1, 2" FFFFFFFF FFFFFFF7 FFFFFFFF FFFFFFF7 +r 1310.10 # RM, RFS +*Want "CGEBRA -9.5 FPCR modes 3, 7" FFFFFFFF FFFFFFF6 FFFFFFFF FFFFFFF7 +r 1320.10 # RNTA, RFS +*Want "CGEBRA -9.5 M3 modes 1, 3" FFFFFFFF FFFFFFF6 FFFFFFFF FFFFFFF7 +r 1330.10 # RNTE, RZ +*Want "CGEBRA -9.5 M3 modes 4, 5" FFFFFFFF FFFFFFF6 FFFFFFFF FFFFFFF7 +r 1340.10 # RP RM +*Want "CGEBRA -9.5 M3 modes 6, 7" FFFFFFFF FFFFFFF7 FFFFFFFF FFFFFFF6 + +r 1350.10 # RZ, RP +*Want "CGEBRA -5.5 FPCR modes 1, 2" FFFFFFFF FFFFFFFB FFFFFFFF FFFFFFFB +r 1360.10 # RM, RFS +*Want "CGEBRA -5.5 FPCR modes 3, 7" FFFFFFFF FFFFFFFA FFFFFFFF FFFFFFFB +r 1370.10 # RNTA, RFS +*Want "CGEBRA -5.5 M3 modes 1, 3" FFFFFFFF FFFFFFFA FFFFFFFF FFFFFFFB +r 1380.10 # RNTE, RZ +*Want "CGEBRA -5.5 M3 modes 4, 5" FFFFFFFF FFFFFFFA FFFFFFFF FFFFFFFB +r 1390.10 # RP, RM +*Want "CGEBRA -5.5 M3 modes 6, 7" FFFFFFFF FFFFFFFB FFFFFFFF FFFFFFFA + +r 13A0.10 # RZ, RP +*Want "CGEBRA -2.5 FPCR modes 1, 2" FFFFFFFF FFFFFFFE FFFFFFFF FFFFFFFE +r 13B0.10 # RM, RFS +*Want "CGEBRA -2.5 FPCR modes 3, 7" FFFFFFFF FFFFFFFD FFFFFFFF FFFFFFFD +r 13C0.10 # RNTA, RFS +*Want "CGEBRA -2.5 M3 modes 1, 3" FFFFFFFF FFFFFFFD FFFFFFFF FFFFFFFD +r 13D0.10 # RNTE, RZ +*Want "CGEBRA -2.5 M3 modes 4, 5" FFFFFFFF FFFFFFFE FFFFFFFF FFFFFFFE +r 13E0.10 # RP, RM +*Want "CGEBRA -2.5 M3 modes 6, 7" FFFFFFFF FFFFFFFE FFFFFFFF FFFFFFFD + +r 13F0.10 # RZ, RP +*Want "CGEBRA -1.5 FPCR modes 1, 2" FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 1400.10 # RM, RFS +*Want "CGEBRA -1.5 FPCR modes 3, 7" FFFFFFFF FFFFFFFE FFFFFFFF FFFFFFFF +r 1410.10 # RNTA, RFS +*Want "CGEBRA -1.5 M3 modes 1, 3" FFFFFFFF FFFFFFFE FFFFFFFF FFFFFFFF +r 1420.10 # RNTE, RZ +*Want "CGEBRA -1.5 M3 modes 4, 5" FFFFFFFF FFFFFFFE FFFFFFFF FFFFFFFF +r 1430.10 # RP, RM +*Want "CGEBRA -1.5 M3 modes 6, 7" FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFE + +r 1440.10 # RZ, RP +*Want "CGEBRA -0.5 FPCR modes 1, 2" 00000000 00000000 00000000 00000000 +r 1450.10 # RM, RFS +*Want "CGEBRA -0.5 FPCR modes 3, 7" FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 1460.10 # RNTA, RFS +*Want "CGEBRA -0.5 M3 modes 1, 3" FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 1470.10 # RNTE, RZ +*Want "CGEBRA -0.5 M3 modes 4, 5" 00000000 00000000 00000000 00000000 +r 1480.10 # RP, RM +*Want "CGEBRA -0.5 M3 modes 6, 7" 00000000 00000000 FFFFFFFF FFFFFFFF + +r 1490.10 # RZ, RP +*Want "CGEBRA 0.5 FPCR modes 1, 2" 00000000 00000000 00000000 00000001 +r 14A0.10 # RM, RFS +*Want "CGEBRA 0.5 FPCR modes 3, 7" 00000000 00000000 00000000 00000001 +r 14B0.10 # RNTA, RFS +*Want "CGEBRA 0.5 M3 modes 1, 3" 00000000 00000001 00000000 00000001 +r 14C0.10 # RNTE, RZ +*Want "CGEBRA 0.5 M3 modes 4, 5" 00000000 00000000 00000000 00000000 +r 14D0.10 # RP, RM +*Want "CGEBRA 0.5 M3 modes 6, 7" 00000000 00000001 00000000 00000000 + +r 14E0.10 # RZ, RP +*Want "CGEBRA 1.5 FPCR modes 1, 2" 00000000 00000001 00000000 00000002 +r 14F0.10 # RM, RFS +*Want "CGEBRA 1.5 FPCR modes 3, 7" 00000000 00000001 00000000 00000001 +r 1500.10 # RNTA, RFS +*Want "CGEBRA 1.5 M3 modes 1, 3" 00000000 00000002 00000000 00000001 +r 1510.10 # RNTE, RZ +*Want "CGEBRA 1.5 M3 modes 4, 5" 00000000 00000002 00000000 00000001 +r 1520.10 # RP, RM +*Want "CGEBRA 1.5 M3 modes 6, 7" 00000000 00000002 00000000 00000001 + +r 1530.10 # RZ, RP +*Want "CGEBRA 2.5 FPCR modes 1, 2" 00000000 00000002 00000000 00000003 +r 1540.10 # RM, RFS +*Want "CGEBRA 2.5 FPCR modes 3, 7" 00000000 00000002 00000000 00000003 +r 1550.10 # RNTA, RFS +*Want "CGEBRA 2.5 M3 modes 1, 3" 00000000 00000003 00000000 00000003 +r 1560.10 # RNTE, RZ +*Want "CGEBRA 2.5 M3 modes 4, 5" 00000000 00000002 00000000 00000002 +r 1570.10 # RP, RM +*Want "CGEBRA 2.5 M3 modes 6, 7" 00000000 00000003 00000000 00000002 + +r 1580.10 # RZ, RP +*Want "CGEBRA 5.5 FPCR modes 1, 2" 00000000 00000005 00000000 00000006 +r 1590.10 # RM, RFS +*Want "CGEBRA 5.5 FPCR modes 3, 7" 00000000 00000005 00000000 00000005 +r 15A0.10 # RNTA, RFS +*Want "CGEBRA 5.5 M3 modes 1, 3" 00000000 00000006 00000000 00000005 +r 15B0.10 # RNTE, RZ +*Want "CGEBRA 5.5 M3 modes 4, 5" 00000000 00000006 00000000 00000005 +r 15C0.10 # RP, RM +*Want "CGEBRA 5.5 M3 modes 6, 7" 00000000 00000006 00000000 00000005 + +r 15D0.10 # RZ, RP +*Want "CGEBRA 9.5 FPCR modes 1, 2" 00000000 00000009 00000000 0000000A +r 15E0.10 # RM, RFS +*Want "CGEBRA 9.5 FPCR modes 3, 7" 00000000 00000009 00000000 00000009 +r 15F0.10 # RNTA, RFS +*Want "CGEBRA 9.5 M3 modes 1, 3" 00000000 0000000A 00000000 00000009 +r 1600.10 # RNTE, RZ +*Want "CGEBRA 9.5 M3 modes 4, 5" 00000000 0000000A 00000000 00000009 +r 1610.10 # RP, RM +*Want "CGEBRA 9.5 M3 modes 6, 7" 00000000 0000000A 00000000 00000009 + +r 1620.10 # RZ, RP +*Want "CGEBRA +0.75 FPCR modes 1, 2" 00000000 00000000 00000000 00000001 +r 1630.10 # RM, RFS +*Want "CGEBRA +0.75 FPCR modes 3, 7" 00000000 00000000 00000000 00000001 +r 1640.10 # RNTA, RFS +*Want "CGEBRA +0.75 M3 modes 1, 3" 00000000 00000001 00000000 00000001 +r 1650.10 # RNTE, RZ +*Want "CGEBRA +0.75 M3 modes 4, 5" 00000000 00000001 00000000 00000000 +r 1660.10 # RP, RM +*Want "CGEBRA +0.75 M3 modes 6, 7" 00000000 00000001 00000000 00000000 + +r 1670.10 # RZ, RP +*Want "CGEBRA +0.25 FPCR modes 1, 2" 00000000 00000000 00000000 00000001 +r 1680.10 # RM, RFS +*Want "CGEBRA +0.25 FPCR modes 3, 7" 00000000 00000000 00000000 00000001 +r 1690.10 # RNTA, RFS +*Want "CGEBRA +0.25 M3 modes 1, 3" 00000000 00000000 00000000 00000001 +r 16A0.10 # RNTE, RZ +*Want "CGEBRA +0.25 M3 modes 4, 5" 00000000 00000000 00000000 00000000 +r 16B0.10 # RP, RM +*Want "CGEBRA +0.25 M3 modes 6, 7" 00000000 00000001 00000000 00000000 + +r 16C0.10 # RZ, RP +*Want "CGEBRA -0.75 FPCR modes 1, 2" 00000000 00000000 00000000 00000000 +r 16D0.10 # RM, RFS +*Want "CGEBRA -0.75 FPCR modes 3, 7" FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 16E0.10 # RNTA, RFS +*Want "CGEBRA -0.75 M3 modes 1, 3" FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 16F0.10 # RNTE, RZ +*Want "CGEBRA -0.75 M3 modes 4, 5" FFFFFFFF FFFFFFFF 00000000 00000000 +r 1700.10 # RP, RM +*Want "CGEBRA -0.75 M3 modes 6, 7" 00000000 00000000 FFFFFFFF FFFFFFFF + +r 1710.10 # RZ, RP +*Want "CGEBRA -0.25 FPCR modes 1, 2" 00000000 00000000 00000000 00000000 +r 1720.10 # RM, RFS +*Want "CGEBRA -0.25 FPCR modes 3, 7" FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 1730.10 # RNTA, RFS +*Want "CGEBRA -0.25 M3 modes 1, 3" 00000000 00000000 FFFFFFFF FFFFFFFF +r 1740.10 # RNTE, RZ +*Want "CGEBRA -0.25 M3 modes 4, 5" 00000000 00000000 00000000 00000000 +r 1750.10 # RP, RM +*Want "CGEBRA -0.25 M3 modes 6, 7" 00000000 00000000 FFFFFFFF FFFFFFFF + + +# rounding mode tests - short BFP - FPCR contents with cc in last byte +*Compare +r 1800.10 # Rounding Mode Tests - FPC +*Want "CGEBRA -9.5 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 1810.10 # Rounding Mode Tests - FPC +*Want "CGEBRA -9.5 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 1820.08 # Rounding Mode Tests - FPC +*Want "CGEBRA -9.5 M3 modes 6-7 FPCR" 00080001 00080001 + +r 1830.10 +*Want "CGEBRA -5.5 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 1840.10 +*Want "CGEBRA -5.5 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 1850.08 +*Want "CGEBRA -5.5 M3 modes 6-7 FPCR" 00080001 00080001 + +r 1860.10 +*Want "CGEBRA -2.5 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 1870.10 +*Want "CGEBRA -2.5 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 1880.08 +*Want "CGEBRA -2.5 M3 modes 6-7 FPCR" 00080001 00080001 + +r 1890.10 +*Want "CGEBRA -1.5 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 18A0.10 +*Want "CGEBRA -1.5 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 18B0.08 +*Want "CGEBRA -1.5 M3 modes 6-7 FPCR" 00080001 00080001 + +r 18C0.10 +*Want "CGEBRA -0.5 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 18D0.10 +*Want "CGEBRA -0.5 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 18E0.08 +*Want "CGEBRA -0.5 M3 modes 6-7 FPCR" 00080001 00080001 + +r 18F0.10 +*Want "CGEBRA +0.5 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 1900.10 +*Want "CGEBRA +0.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 1910.08 +*Want "CGEBRA +0.5 M3 modes 6-7 FPCR" 00080002 00080002 + +r 1920.10 +*Want "CGEBRA +1.5 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 1930.10 +*Want "CGEBRA +1.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 1940.08 +*Want "CGEBRA +1.5 M3 modes 6-7 FPCR" 00080002 00080002 + +r 1950.10 +*Want "CGEBRA +2.5 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 1960.10 +*Want "CGEBRA +2.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 1970.08 +*Want "CGEBRA +2.5 M3 modes 6-7 FPCR" 00080002 00080002 + +r 1980.10 +*Want "CGEBRA +5.5 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 1990.10 +*Want "CGEBRA +5.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 19A0.08 +*Want "CGEBRA +5.5 M3 modes 6-7 FPCR" 00080002 00080002 + +r 19B0.10 +*Want "CGEBRA +9.5 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 19C0.10 +*Want "CGEBRA +9.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 19D0.08 +*Want "CGEBRA +9.5 M3 modes 6-7 FPCR" 00080002 00080002 + +r 19E0.10 +*Want "CGEBRA +0.75 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 19F0.10 +*Want "CGEBRA +0.75 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 1A00.08 +*Want "CGEBRA +0.75 M3 modes 6-7 FPCR" 00080002 00080002 + +r 1A10.10 +*Want "CGEBRA +0.25 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 1A20.10 +*Want "CGEBRA +0.25 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 1A30.08 +*Want "CGEBRA +0.25 M3 modes 6-7 FPCR" 00080002 00080002 + +r 1A40.10 +*Want "CGEBRA -0.75 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 1A50.10 +*Want "CGEBRA -0.75 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 1A60.08 +*Want "CGEBRA -0.75 M3 modes 6-7 FPCR" 00080001 00080001 + +r 1A70.10 +*Want "CGEBRA -0.25 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 1A80.10 +*Want "CGEBRA -0.25 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 18E0.08 +*Want "CGEBRA -0.25 M3 modes 6-7 FPCR" 00080001 00080001 + + +# Long BFP inputs to int-64 - results +*Compare +r 2000.10 +*Want "CGDBR result pair 1" 00000000 00000001 00000000 00000001 +r 2010.10 +*Want "CGDBR result pair 2" 00000000 00000002 00000000 00000002 +r 2020.10 +*Want "CGDBR result pair 3" 00000000 00000004 00000000 00000004 +r 2030.10 +*Want "CGDBR result pair 4" FFFFFFFF FFFFFFFE FFFFFFFF FFFFFFFE +r 2040.10 +*Want "CGDBR result pair 5" 80000000 00000000 00000000 00000000 +r 2050.10 +*Want "CGDBR result pair 6" 80000000 00000000 00000000 00000000 +r 2060.10 +*Want "CGDBR result pair 7" 7FFFFFFF FFFFFFFF 00000000 00000000 +r 2070.10 +*Want "CGDBR result pair 8" 80000000 00000000 00000000 00000000 +r 2080.10 +*Want "CGDBR result pair 8" 7FFFFFFF FFFFFC00 7FFFFFFF FFFFFC00 + +# Long BFP inputs to int-64 - FPCR contents +*Compare +r 2200.10 +*Want "CGDBR FPCR pairs 1-2" 00000002 F8000002 00000002 F8000002 +r 2210.10 +*Want "CGDBR FPCR pairs 3-4" 00000002 F8000002 00000001 F8000001 +r 2220.10 +*Want "CGDBR FPCR pairs 5-6" 00880003 F8008000 00880003 F8008000 +r 2230.10 +*Want "CGDBR FPCR pairs 7-8" 00880003 F8008000 00880003 F8008000 +r 2240.08 +*Want "CGDBR FPCR pair 9" 00000002 F8000002 + + +# long BFP rounding mode tests - results +*Compare +r 2300.10 # RZ, RP +*Want "CGDBRA -9.5 FPCR modes 1, 2" FFFFFFFF FFFFFFF7 FFFFFFFF FFFFFFF7 +r 2310.10 # RM, RFS +*Want "CGDBRA -9.5 FPCR modes 3, 7" FFFFFFFF FFFFFFF6 FFFFFFFF FFFFFFF7 +r 2320.10 # RNTA, RFS +*Want "CGDBRA -9.5 M3 modes 1, 3" FFFFFFFF FFFFFFF6 FFFFFFFF FFFFFFF7 +r 2330.10 # RNTE, RZ +*Want "CGDBRA -9.5 M3 modes 4, 5" FFFFFFFF FFFFFFF6 FFFFFFFF FFFFFFF7 +r 2340.10 # RP RM +*Want "CGDBRA -9.5 M3 modes 6, 7" FFFFFFFF FFFFFFF7 FFFFFFFF FFFFFFF6 + +r 2350.10 # RZ, RP +*Want "CGDBRA -5.5 FPCR modes 1, 2" FFFFFFFF FFFFFFFB FFFFFFFF FFFFFFFB +r 2360.10 # RM, RFS +*Want "CGDBRA -5.5 FPCR modes 3, 7" FFFFFFFF FFFFFFFA FFFFFFFF FFFFFFFB +r 2370.10 # RNTA, RFS +*Want "CGDBRA -5.5 M3 modes 1, 3" FFFFFFFF FFFFFFFA FFFFFFFF FFFFFFFB +r 2380.10 # RNTE, RZ +*Want "CGDBRA -5.5 M3 modes 4, 5" FFFFFFFF FFFFFFFA FFFFFFFF FFFFFFFB +r 2390.10 # RP, RM +*Want "CGDBRA -5.5 M3 modes 6, 7" FFFFFFFF FFFFFFFB FFFFFFFF FFFFFFFA + +r 23A0.10 # RZ, RP +*Want "CGDBRA -2.5 FPCR modes 1, 2" FFFFFFFF FFFFFFFE FFFFFFFF FFFFFFFE +r 23B0.10 # RM, RFS +*Want "CGDBRA -2.5 FPCR modes 3, 7" FFFFFFFF FFFFFFFD FFFFFFFF FFFFFFFD +r 23C0.10 # RNTA, RFS +*Want "CGDBRA -2.5 M3 modes 1, 3" FFFFFFFF FFFFFFFD FFFFFFFF FFFFFFFD +r 23D0.10 # RNTE, RZ +*Want "CGDBRA -2.5 M3 modes 4, 5" FFFFFFFF FFFFFFFE FFFFFFFF FFFFFFFE +r 23E0.10 # RP, RM +*Want "CGDBRA -2.5 M3 modes 6, 7" FFFFFFFF FFFFFFFE FFFFFFFF FFFFFFFD + +r 23F0.10 # RZ, RP +*Want "CGDBRA -1.5 FPCR modes 1, 2" FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 2400.10 # RM, RFS +*Want "CGDBRA -1.5 FPCR modes 3, 7" FFFFFFFF FFFFFFFE FFFFFFFF FFFFFFFF +r 2410.10 # RNTA, RFS +*Want "CGDBRA -1.5 M3 modes 1, 3" FFFFFFFF FFFFFFFE FFFFFFFF FFFFFFFF +r 2420.10 # RNTE, RZ +*Want "CGDBRA -1.5 M3 modes 4, 5" FFFFFFFF FFFFFFFE FFFFFFFF FFFFFFFF +r 2430.10 # RP, RM +*Want "CGDBRA -1.5 M3 modes 6, 7" FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFE + +r 2440.10 # RZ, RP +*Want "CGDBRA -0.5 FPCR modes 1, 2" 00000000 00000000 00000000 00000000 +r 2450.10 # RM, RFS +*Want "CGDBRA -0.5 FPCR modes 3, 7" FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 2460.10 # RNTA, RFS +*Want "CGDBRA -0.5 M3 modes 1, 3" FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 2470.10 # RNTE, RZ +*Want "CGDBRA -0.5 M3 modes 4, 5" 00000000 00000000 00000000 00000000 +r 2480.10 # RP, RM +*Want "CGDBRA -0.5 M3 modes 6, 7" 00000000 00000000 FFFFFFFF FFFFFFFF + +r 2490.10 # RZ, RP +*Want "CGDBRA 0.5 FPCR modes 1, 2" 00000000 00000000 00000000 00000001 +r 24A0.10 # RM, RFS +*Want "CGDBRA 0.5 FPCR modes 3, 7" 00000000 00000000 00000000 00000001 +r 24B0.10 # RNTA, RFS +*Want "CGDBRA 0.5 M3 modes 1, 3" 00000000 00000001 00000000 00000001 +r 24C0.10 # RNTE, RZ +*Want "CGDBRA 0.5 M3 modes 4, 5" 00000000 00000000 00000000 00000000 +r 24D0.10 # RP, RM +*Want "CGDBRA 0.5 M3 modes 6, 7" 00000000 00000001 00000000 00000000 + +r 24E0.10 # RZ, RP +*Want "CGDBRA 1.5 FPCR modes 1, 2" 00000000 00000001 00000000 00000002 +r 24F0.10 # RM, RFS +*Want "CGDBRA 1.5 FPCR modes 3, 7" 00000000 00000001 00000000 00000001 +r 2500.10 # RNTA, RFS +*Want "CGDBRA 1.5 M3 modes 1, 3" 00000000 00000002 00000000 00000001 +r 2510.10 # RNTE, RZ +*Want "CGDBRA 1.5 M3 modes 4, 5" 00000000 00000002 00000000 00000001 +r 2520.10 # RP, RM +*Want "CGDBRA 1.5 M3 modes 6, 7" 00000000 00000002 00000000 00000001 + +r 2530.10 # RZ, RP +*Want "CGDBRA 2.5 FPCR modes 1, 2" 00000000 00000002 00000000 00000003 +r 2540.10 # RM, RFS +*Want "CGDBRA 2.5 FPCR modes 3, 7" 00000000 00000002 00000000 00000003 +r 2550.10 # RNTA, RFS +*Want "CGDBRA 2.5 M3 modes 1, 3" 00000000 00000003 00000000 00000003 +r 2560.10 # RNTE, RZ +*Want "CGDBRA 2.5 M3 modes 4, 5" 00000000 00000002 00000000 00000002 +r 2570.10 # RP, RM +*Want "CGDBRA 2.5 M3 modes 6, 7" 00000000 00000003 00000000 00000002 + +r 2580.10 # RZ, RP +*Want "CGDBRA 5.5 FPCR modes 1, 2" 00000000 00000005 00000000 00000006 +r 2590.10 # RM, RFS +*Want "CGDBRA 5.5 FPCR modes 3, 7" 00000000 00000005 00000000 00000005 +r 25A0.10 # RNTA, RFS +*Want "CGDBRA 5.5 M3 modes 1, 3" 00000000 00000006 00000000 00000005 +r 25B0.10 # RNTE, RZ +*Want "CGDBRA 5.5 M3 modes 4, 5" 00000000 00000006 00000000 00000005 +r 25C0.10 # RP, RM +*Want "CGDBRA 5.5 M3 modes 6, 7" 00000000 00000006 00000000 00000005 + +r 25D0.10 # RZ, RP +*Want "CGDBRA 9.5 FPCR modes 1, 2" 00000000 00000009 00000000 0000000A +r 25E0.10 # RM, RFS +*Want "CGDBRA 9.5 FPCR modes 3, 7" 00000000 00000009 00000000 00000009 +r 25F0.10 # RNTA, RFS +*Want "CGDBRA 9.5 M3 modes 1, 3" 00000000 0000000A 00000000 00000009 +r 2600.10 # RNTE, RZ +*Want "CGDBRA 9.5 M3 modes 4, 5" 00000000 0000000A 00000000 00000009 +r 2610.10 # RP, RM +*Want "CGDBRA 9.5 M3 modes 6, 7" 00000000 0000000A 00000000 00000009 + +r 2620.10 # RZ, RP +*Want "CGDBRA +0.75 FPCR modes 1, 2" 00000000 00000000 00000000 00000001 +r 2630.10 # RM, RFS +*Want "CGDBRA +0.75 FPCR modes 3, 7" 00000000 00000000 00000000 00000001 +r 2640.10 # RNTA, RFS +*Want "CGDBRA +0.75 M3 modes 1, 3" 00000000 00000001 00000000 00000001 +r 2650.10 # RNTE, RZ +*Want "CGDBRA +0.75 M3 modes 4, 5" 00000000 00000001 00000000 00000000 +r 2660.10 # RP, RM +*Want "CGDBRA +0.75 M3 modes 6, 7" 00000000 00000001 00000000 00000000 + +r 2670.10 # RZ, RP +*Want "CGDBRA +0.25 FPCR modes 1, 2" 00000000 00000000 00000000 00000001 +r 2680.10 # RM, RFS +*Want "CGDBRA +0.25 FPCR modes 3, 7" 00000000 00000000 00000000 00000001 +r 2690.10 # RNTA, RFS +*Want "CGDBRA +0.25 M3 modes 1, 3" 00000000 00000000 00000000 00000001 +r 26A0.10 # RNTE, RZ +*Want "CGDBRA +0.25 M3 modes 4, 5" 00000000 00000000 00000000 00000000 +r 26B0.10 # RP, RM +*Want "CGDBRA +0.25 M3 modes 6, 7" 00000000 00000001 00000000 00000000 + +r 26C0.10 # RZ, RP +*Want "CGDBRA -0.75 FPCR modes 1, 2" 00000000 00000000 00000000 00000000 +r 26D0.10 # RM, RFS +*Want "CGDBRA -0.75 FPCR modes 3, 7" FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 26E0.10 # RNTA, RFS +*Want "CGDBRA -0.75 M3 modes 1, 3" FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 26F0.10 # RNTE, RZ +*Want "CGDBRA -0.75 M3 modes 4, 5" FFFFFFFF FFFFFFFF 00000000 00000000 +r 2700.10 # RP, RM +*Want "CGDBRA -0.75 M3 modes 6, 7" 00000000 00000000 FFFFFFFF FFFFFFFF + +r 2710.10 # RZ, RP +*Want "CGDBRA -0.25 FPCR modes 1, 2" 00000000 00000000 00000000 00000000 +r 2720.10 # RM, RFS +*Want "CGDBRA -0.25 FPCR modes 3, 7" FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 2730.10 # RNTA, RFS +*Want "CGDBRA -0.25 M3 modes 1, 3" 00000000 00000000 FFFFFFFF FFFFFFFF +r 2740.10 # RNTE, RZ +*Want "CGDBRA -0.25 M3 modes 4, 5" 00000000 00000000 00000000 00000000 +r 2750.10 # RP, RM +*Want "CGDBRA -0.25 M3 modes 6, 7" 00000000 00000000 FFFFFFFF FFFFFFFF + + +# rounding mode tests - long BFP - FPCR contents with cc in last byte +*Compare +r 2800.10 +*Want "CGDBRA -9.5 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 2810.10 +*Want "CGDBRA -9.5 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 2820.08 +*Want "CGDBRA -9.5 M3 modes 6-7 FPCR" 00080001 00080001 + +r 2830.10 +*Want "CGDBRA -5.5 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 2840.10 +*Want "CGDBRA -5.5 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 2850.08 +*Want "CGDBRA -5.5 M3 modes 6-7 FPCR" 00080001 00080001 + +r 2860.10 +*Want "CGDBRA -2.5 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 2870.10 +*Want "CGDBRA -2.5 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 2880.08 +*Want "CGDBRA -2.5 M3 modes 6-7 FPCR" 00080001 00080001 + +r 2890.10 +*Want "CGDBRA -1.5 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 28A0.10 +*Want "CGDBRA -1.5 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 28B0.08 +*Want "CGDBRA -1.5 M3 modes 6-7 FPCR" 00080001 00080001 + +r 28C0.10 +*Want "CGDBRA -0.5 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 28D0.10 +*Want "CGDBRA -0.5 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 28E0.08 +*Want "CGDBRA -0.5 M3 modes 6-7 FPCR" 00080001 00080001 + +r 28F0.10 +*Want "CGDBRA +0.5 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 2900.10 +*Want "CGDBRA +0.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 2910.08 +*Want "CGDBRA +0.5 M3 modes 6-7 FPCR" 00080002 00080002 + +r 2920.10 +*Want "CGDBRA +1.5 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 2930.10 +*Want "CGDBRA +1.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 2940.08 +*Want "CGDBRA +1.5 M3 modes 6-7 FPCR" 00080002 00080002 + +r 2950.10 +*Want "CGDBRA +2.5 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 2960.10 +*Want "CGDBRA +2.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 2970.08 +*Want "CGDBRA +2.5 M3 modes 6-7 FPCR" 00080002 00080002 + +r 2980.10 +*Want "CGDBRA +5.5 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 2990.10 +*Want "CGDBRA +5.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 29A0.08 +*Want "CGDBRA +5.5 M3 modes 6-7 FPCR" 00080002 00080002 + +r 29B0.10 +*Want "CGDBRA +9.5 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 29C0.10 +*Want "CGDBRA +9.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 29D0.08 +*Want "CGDBRA +9.5 M3 modes 6-7 FPCR" 00080002 00080002 + +r 29E0.10 +*Want "CGDBRA +0.75 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 29F0.10 +*Want "CGDBRA +0.75 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 2A00.08 +*Want "CGDBRA +0.75 M3 modes 6-7 FPCR" 00080002 00080002 + +r 2A10.10 +*Want "CGDBRA +0.25 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 2A20.10 +*Want "CGDBRA +0.25 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 2A30.08 +*Want "CGDBRA +0.25 M3 modes 6-7 FPCR" 00080002 00080002 + +r 2A40.10 +*Want "CGDBRA -0.75 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 2A50.10 +*Want "CGDBRA -0.75 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 2A60.08 +*Want "CGDBRA -0.75 M3 modes 6-7 FPCR" 00080001 00080001 + +r 2A70.10 +*Want "CGDBRA -0.25 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 2A80.10 +*Want "CGDBRA -0.25 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 28E0.08 +*Want "CGDBRA -0.25 M3 modes 6-7 FPCR" 00080001 00080001 + + + +# Extended BFP inputs to int-64 - results +*Compare +r 3000.10 +*Want "CGXBR result pair 1" 00000000 00000001 00000000 00000001 +r 3010.10 +*Want "CGXBR result pair 2" 00000000 00000002 00000000 00000002 +r 3020.10 +*Want "CGXBR result pair 3" 00000000 00000004 00000000 00000004 +r 3030.10 +*Want "CGXBR result pair 4" FFFFFFFF FFFFFFFE FFFFFFFF FFFFFFFE +r 3040.10 +*Want "CGXBR result pair 5" 80000000 00000000 00000000 00000000 +r 3050.10 +*Want "CGXBR result pair 6" 80000000 00000000 00000000 00000000 +r 3060.10 +*Want "CGXBR result pair 7" 7FFFFFFF FFFFFFFF 00000000 00000000 +r 3070.10 +*Want "CGXBR result pair 8" 80000000 00000000 00000000 00000000 +r 3080.10 +*Want "CGXBR result pair 8" 7FFFFFFF FFFFFFFF 7FFFFFFF FFFFFFFF + +# Extended BFP inputs to int-64 - FPCR contents +*Compare +r 3200.10 +*Want "CGXBR FPCR pairs 1-2" 00000002 F8000002 00000002 F8000002 +r 3210.10 +*Want "CGXBR FPCR pairs 3-4" 00000002 F8000002 00000001 F8000001 +r 3220.10 +*Want "CGXBR FPCR pairs 5-6" 00880003 F8008000 00880003 F8008000 +r 3230.10 +*Want "CGXBR FPCR pairs 7-8" 00880003 F8008000 00880003 F8008000 +r 3240.08 +*Want "CGXBR FPCR pair 9" 00000002 F8000002 + + +# rounding mode tests - extended BFP - results from rounding +*Compare +r 3300.10 # RZ, RP +*Want "CGXBRA -9.5 FPCR modes 1, 2" FFFFFFFF FFFFFFF7 FFFFFFFF FFFFFFF7 +r 3310.10 # RM, RFS +*Want "CGXBRA -9.5 FPCR modes 3, 7" FFFFFFFF FFFFFFF6 FFFFFFFF FFFFFFF7 +r 3320.10 # RNTA, RFS +*Want "CGXBRA -9.5 M3 modes 1, 3" FFFFFFFF FFFFFFF6 FFFFFFFF FFFFFFF7 +r 3330.10 # RNTE, RZ +*Want "CGXBRA -9.5 M3 modes 4, 5" FFFFFFFF FFFFFFF6 FFFFFFFF FFFFFFF7 +r 3340.10 # RP RM +*Want "CGXBRA -9.5 M3 modes 6, 7" FFFFFFFF FFFFFFF7 FFFFFFFF FFFFFFF6 + +r 3350.10 # RZ, RP +*Want "CGXBRA -5.5 FPCR modes 1, 2" FFFFFFFF FFFFFFFB FFFFFFFF FFFFFFFB +r 3360.10 # RM, RFS +*Want "CGXBRA -5.5 FPCR modes 3, 7" FFFFFFFF FFFFFFFA FFFFFFFF FFFFFFFB +r 3370.10 # RNTA, RFS +*Want "CGXBRA -5.5 M3 modes 1, 3" FFFFFFFF FFFFFFFA FFFFFFFF FFFFFFFB +r 3380.10 # RNTE, RZ +*Want "CGXBRA -5.5 M3 modes 4, 5" FFFFFFFF FFFFFFFA FFFFFFFF FFFFFFFB +r 3390.10 # RP, RM +*Want "CGXBRA -5.5 M3 modes 6, 7" FFFFFFFF FFFFFFFB FFFFFFFF FFFFFFFA + +r 33A0.10 # RZ, RP +*Want "CGXBRA -2.5 FPCR modes 1, 2" FFFFFFFF FFFFFFFE FFFFFFFF FFFFFFFE +r 33B0.10 # RM, RFS +*Want "CGXBRA -2.5 FPCR modes 3, 7" FFFFFFFF FFFFFFFD FFFFFFFF FFFFFFFD +r 33C0.10 # RNTA, RFS +*Want "CGXBRA -2.5 M3 modes 1, 3" FFFFFFFF FFFFFFFD FFFFFFFF FFFFFFFD +r 33D0.10 # RNTE, RZ +*Want "CGXBRA -2.5 M3 modes 4, 5" FFFFFFFF FFFFFFFE FFFFFFFF FFFFFFFE +r 33E0.10 # RP, RM +*Want "CGXBRA -2.5 M3 modes 6, 7" FFFFFFFF FFFFFFFE FFFFFFFF FFFFFFFD + +r 33F0.10 # RZ, RP +*Want "CGXBRA -1.5 FPCR modes 1, 2" FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 3400.10 # RM, RFS +*Want "CGXBRA -1.5 FPCR modes 3, 7" FFFFFFFF FFFFFFFE FFFFFFFF FFFFFFFF +r 3410.10 # RNTA, RFS +*Want "CGXBRA -1.5 M3 modes 1, 3" FFFFFFFF FFFFFFFE FFFFFFFF FFFFFFFF +r 3420.10 # RNTE, RZ +*Want "CGXBRA -1.5 M3 modes 4, 5" FFFFFFFF FFFFFFFE FFFFFFFF FFFFFFFF +r 3430.10 # RP, RM +*Want "CGXBRA -1.5 M3 modes 6, 7" FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFE + +r 3440.10 # RZ, RP +*Want "CGXBRA -0.5 FPCR modes 1, 2" 00000000 00000000 00000000 00000000 +r 3450.10 # RM, RFS +*Want "CGXBRA -0.5 FPCR modes 3, 7" FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 3460.10 # RNTA, RFS +*Want "CGXBRA -0.5 M3 modes 1, 3" FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 3470.10 # RNTE, RZ +*Want "CGXBRA -0.5 M3 modes 4, 5" 00000000 00000000 00000000 00000000 +r 3480.10 # RP, RM +*Want "CGXBRA -0.5 M3 modes 6, 7" 00000000 00000000 FFFFFFFF FFFFFFFF + +r 3490.10 # RZ, RP +*Want "CGXBRA +0.5 FPCR modes 1, 2" 00000000 00000000 00000000 00000001 +r 34A0.10 # RM, RFS +*Want "CGXBRA +0.5 FPCR modes 3, 7" 00000000 00000000 00000000 00000001 +r 34B0.10 # RNTA, RFS +*Want "CGXBRA +0.5 M3 modes 1, 3" 00000000 00000001 00000000 00000001 +r 34C0.10 # RNTE, RZ +*Want "CGXBRA +0.5 M3 modes 4, 5" 00000000 00000000 00000000 00000000 +r 34D0.10 # RP, RM +*Want "CGXBRA +0.5 M3 modes 6, 7" 00000000 00000001 00000000 00000000 + +r 34E0.10 # RZ, RP +*Want "CGXBRA +1.5 FPCR modes 1, 2" 00000000 00000001 00000000 00000002 +r 34F0.10 # RM, RFS +*Want "CGXBRA +1.5 FPCR modes 3, 7" 00000000 00000001 00000000 00000001 +r 3500.10 # RNTA, RFS +*Want "CGXBRA +1.5 M3 modes 1, 3" 00000000 00000002 00000000 00000001 +r 3510.10 # RNTE, RZ +*Want "CGXBRA +1.5 M3 modes 4, 5" 00000000 00000002 00000000 00000001 +r 3520.10 # RP, RM +*Want "CGXBRA +1.5 M3 modes 6, 7" 00000000 00000002 00000000 00000001 + +r 3530.10 # RZ, RP +*Want "CGXBRA +2.5 FPCR modes 1, 2" 00000000 00000002 00000000 00000003 +r 3540.10 # RM, RFS +*Want "CGXBRA +2.5 FPCR modes 3, 7" 00000000 00000002 00000000 00000003 +r 3550.10 # RNTA, RFS +*Want "CGXBRA +2.5 M3 modes 1, 3" 00000000 00000003 00000000 00000003 +r 3560.10 # RNTE, RZ +*Want "CGXBRA +2.5 M3 modes 4, 5" 00000000 00000002 00000000 00000002 +r 3570.10 # RP, RM +*Want "CGXBRA +2.5 M3 modes 6, 7" 00000000 00000003 00000000 00000002 + +r 3580.10 # RZ, RP +*Want "CGXBRA +5.5 FPCR modes 1, 2" 00000000 00000005 00000000 00000006 +r 3590.10 # RM, RFS +*Want "CGXBRA +5.5 FPCR modes 3, 7" 00000000 00000005 00000000 00000005 +r 35A0.10 # RNTA, RFS +*Want "CGXBRA +5.5 M3 modes 1, 3" 00000000 00000006 00000000 00000005 +r 35B0.10 # RNTE, RZ +*Want "CGXBRA +5.5 M3 modes 4, 5" 00000000 00000006 00000000 00000005 +r 35C0.10 # RP, RM +*Want "CGXBRA +5.5 M3 modes 6, 7" 00000000 00000006 00000000 00000005 + +r 35D0.10 # RZ, RP +*Want "CGXBRA +9.5 FPCR modes 1, 2" 00000000 00000009 00000000 0000000A +r 35E0.10 # RM, RFS +*Want "CGXBRA +9.5 FPCR modes 3, 7" 00000000 00000009 00000000 00000009 +r 35F0.10 # RNTA, RFS +*Want "CGXBRA +9.5 M3 modes 1, 3" 00000000 0000000A 00000000 00000009 +r 3600.10 # RNTE, RZ +*Want "CGXBRA +9.5 M3 modes 4, 5" 00000000 0000000A 00000000 00000009 +r 3610.10 # RP, RM +*Want "CGXBRA +9.5 M3 modes 6, 7" 00000000 0000000A 00000000 00000009 + +r 3620.10 # RZ, RP +*Want "CGXBRA +0.75 FPCR modes 1, 2" 00000000 00000000 00000000 00000001 +r 3630.10 # RM, RFS +*Want "CGXBRA +0.75 FPCR modes 3, 7" 00000000 00000000 00000000 00000001 +r 3640.10 # RNTA, RFS +*Want "CGXBRA +0.75 M3 modes 1, 3" 00000000 00000001 00000000 00000001 +r 3650.10 # RNTE, RZ +*Want "CGXBRA +0.75 M3 modes 4, 5" 00000000 00000001 00000000 00000000 +r 3660.10 # RP, RM +*Want "CGXBRA +0.75 M3 modes 6, 7" 00000000 00000001 00000000 00000000 + +r 3670.10 # RZ, RP +*Want "CGXBRA +0.25 FPCR modes 1, 2" 00000000 00000000 00000000 00000001 +r 3680.10 # RM, RFS +*Want "CGXBRA +0.25 FPCR modes 3, 7" 00000000 00000000 00000000 00000001 +r 3690.10 # RNTA, RFS +*Want "CGXBRA +0.25 M3 modes 1, 3" 00000000 00000000 00000000 00000001 +r 36A0.10 # RNTE, RZ +*Want "CGXBRA +0.25 M3 modes 4, 5" 00000000 00000000 00000000 00000000 +r 36B0.10 # RP, RM +*Want "CGXBRA +0.25 M3 modes 6, 7" 00000000 00000001 00000000 00000000 + +r 36C0.10 # RZ, RP +*Want "CGXBRA -0.75 FPCR modes 1, 2" 00000000 00000000 00000000 00000000 +r 36D0.10 # RM, RFS +*Want "CGXBRA -0.75 FPCR modes 3, 7" FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 36E0.10 # RNTA, RFS +*Want "CGXBRA -0.75 M3 modes 1, 3" FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 36F0.10 # RNTE, RZ +*Want "CGXBRA -0.75 M3 modes 4, 5" FFFFFFFF FFFFFFFF 00000000 00000000 +r 3700.10 # RP, RM +*Want "CGXBRA -0.75 M3 modes 6, 7" 00000000 00000000 FFFFFFFF FFFFFFFF + +r 3710.10 # RZ, RP +*Want "CGXBRA -0.25 FPCR modes 1, 2" 00000000 00000000 00000000 00000000 +r 3720.10 # RM, RFS +*Want "CGXBRA -0.25 FPCR modes 3, 7" FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 3730.10 # RNTA, RFS +*Want "CGXBRA -0.25 M3 modes 1, 3" 00000000 00000000 FFFFFFFF FFFFFFFF +r 3740.10 # RNTE, RZ +*Want "CGXBRA -0.25 M3 modes 4, 5" 00000000 00000000 00000000 00000000 +r 3750.10 # RP, RM +*Want "CGXBRA -0.25 M3 modes 6, 7" 00000000 00000000 FFFFFFFF FFFFFFFF + +r 3760.10 # RZ, RP +*Want "CGXBRA maxint64+5 FPCR modes 1, 2" 7FFFFFFF FFFFFFFF 7FFFFFFF FFFFFFFF +r 3770.10 # RM, RFS +*Want "CGXBRA maxint64+5 FPCR modes 3, 7" 7FFFFFFF FFFFFFFF 7FFFFFFF FFFFFFFF +r 3780.10 # RNTA, RFS +*Want "CGXBRA maxint64+5 M3 modes 1, 3" 7FFFFFFF FFFFFFFF 7FFFFFFF FFFFFFFF +r 3790.10 # RNTE, RZ +*Want "CGXBRA maxint64+5 M3 modes 4, 5" 7FFFFFFF FFFFFFFF 7FFFFFFF FFFFFFFF +r 37A0.10 # RP, RM +*Want "CGXBRA maxint64+5 M3 modes 6, 7" 7FFFFFFF FFFFFFFF 7FFFFFFF FFFFFFFF + + +# rounding mode tests - extended BFP - FPCR contents with cc in last byte +*Compare +r 3800.10 +*Want "CGXBRA -9.5 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 3810.10 +*Want "CGXBRA -9.5 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 3820.08 +*Want "CGXBRA -9.5 M3 modes 6-7 FPCR" 00080001 00080001 + +r 3830.10 +*Want "CGXBRA -5.5 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 3840.10 +*Want "CGXBRA -5.5 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 3850.08 +*Want "CGXBRA -5.5 M3 modes 6-7 FPCR" 00080001 00080001 + +r 3860.10 +*Want "CGXBRA -2.5 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 3870.10 +*Want "CGXBRA -2.5 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 3880.08 +*Want "CGXBRA -2.5 M3 modes 6-7 FPCR" 00080001 00080001 + +r 3890.10 +*Want "CGXBRA -1.5 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 38A0.10 +*Want "CGXBRA -1.5 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 38B0.08 +*Want "CGXBRA -1.5 M3 modes 6-7 FPCR" 00080001 00080001 + +r 38C0.10 +*Want "CGXBRA -0.5 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 38D0.10 +*Want "CGXBRA -0.5 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 38E0.08 +*Want "CGXBRA -0.5 M3 modes 6-7 FPCR" 00080001 00080001 + +r 38F0.10 +*Want "CGXBRA +0.5 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 3900.10 +*Want "CGXBRA +0.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 3910.08 +*Want "CGXBRA +0.5 M3 modes 6-7 FPCR" 00080002 00080002 + +r 3920.10 +*Want "CGXBRA +1.5 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 3930.10 +*Want "CGXBRA +1.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 3940.08 +*Want "CGXBRA +1.5 M3 modes 6-7 FPCR" 00080002 00080002 + +r 3950.10 +*Want "CGXBRA +2.5 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 3960.10 +*Want "CGXBRA +2.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 3970.08 +*Want "CGXBRA +2.5 M3 modes 6-7 FPCR" 00080002 00080002 + +r 3980.10 +*Want "CGXBRA +5.5 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 3990.10 +*Want "CGXBRA +5.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 39A0.08 +*Want "CGXBRA +5.5 M3 modes 6-7 FPCR" 00080002 00080002 + +r 39B0.10 +*Want "CGXBRA +9.5 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 39C0.10 +*Want "CGXBRA +9.5 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 39D0.08 +*Want "CGXBRA +9.5 M3 modes 6-7 FPCR" 00080002 00080002 + +r 39E0.10 +*Want "CGDBRA +0.75 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 39F0.10 +*Want "CGDBRA +0.75 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 3A00.08 +*Want "CGDBRA +0.75 M3 modes 6-7 FPCR" 00080002 00080002 + +r 3A10.10 +*Want "CGDBRA +0.25 FPCR modes 1-3, 7 FPCR" 00000002 00000002 00000002 00000002 +r 3A20.10 +*Want "CGDBRA +0.25 M3 modes 1, 3-5 FPCR" 00080002 00080002 00080002 00080002 +r 3A30.08 +*Want "CGDBRA +0.25 M3 modes 6-7 FPCR" 00080002 00080002 + +r 3A40.10 +*Want "CGDBRA -0.75 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 3A50.10 +*Want "CGDBRA -0.75 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 3A60.08 +*Want "CGDBRA -0.75 M3 modes 6-7 FPCR" 00080001 00080001 + +r 3A70.10 +*Want "CGDBRA -0.25 FPCR modes 1-3, 7 FPCR" 00000001 00000001 00000001 00000001 +r 3A80.10 +*Want "CGDBRA -0.25 M3 modes 1, 3-5 FPCR" 00080001 00080001 00080001 00080001 +r 3A90.08 +*Want "CGDBRA -0.25 M3 modes 6-7 FPCR" 00080001 00080001 + +r 3AA0.10 +*Want "CGDBRA maxint64+5 FPCR modes 1-3, 7 FPCR" 00000002 00800003 00000002 00000002 +r 3AB0.10 +*Want "CGDBRA maxint64+5 M3 modes 1, 3-5 FPCR" 00880003 00080002 00880003 00080002 +r 3AC0.08 +*Want "CGDBRA maxint64+5 M3 modes 6-7 FPCR" 00880003 00080002 + + +*Done + diff --git a/tests/bfp-008-cvtfrlog.asm b/tests/bfp-008-cvtfrlog.asm new file mode 100644 index 000000000..3dc82b9b8 --- /dev/null +++ b/tests/bfp-008-cvtfrlog.asm @@ -0,0 +1,493 @@ + TITLE 'bfp-008-cvtfrlog.asm: Test IEEE Convert From Fixed (uint-32)' +*********************************************************************** +* +*Testcase IEEE CONVERT FROM LOGICAL 32 +* Test case capability includes ieee exceptions trappable and otherwise. +* Test result, FPCR flags, and DXC saved for all tests. (Convert From +* Fixed does not set the condition code.) +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* bfp-008-cvtfrlog.asm +* +* This assembly-language source file is part of the +* Hercules Decimal Floating Point Validation Package +* by Stephen R. Orso +* +* Copyright 2016 by Stephen R Orso. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* +* 3. The name of the author may not be used to endorse or promote +* products derived from this software without specific prior written +* permission. +* +* DISCLAMER: THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* HOLDER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* Tests the following three conversion instructions +* CONVERT FROM LOGICAL (32 to short BFP, RRF-e) +* CONVERT FROM LOGICAL (32 to long BFP, RRF-e) +* CONVERT FROM LOGICAL (32 to extended BFP, RRF-e) +* +* Test data is compiled into this program. The test script that runs +* this program can provide alternative test data through Hercules R +* commands. +* +* Test Case Order +* 1) Uint-32 to Short BFP +* 2) Uint-32 to Short BFP with all rounding modes +* 3) Uint-32 to Long BFP +* 4) Uint-32 to Extended BFP +* +* Conversion of uint-32 to long or extended is always exact because the +* number of bits in uint-32 is less than the number of bits in a long +* or extended significand. For this reason, exhaustive rounding +* testing is not performed for long or extended. +* +* Provided test data is +* 1, 2, 4, 9, +* 4 294 967 294 (0xFFFFFFFE) (note 1) +* 4 294 967 040 (0xFFFFFF00) (note 2) +* 4 294 967 168 (0xFFFFFF40) (note 3) +* The last three values will trigger inexact exceptions when +* converted to to short BFP and are used for exhaustive rounding mode +* testing for short BFP. Specifics for each: +* 1) Fits in short BFP but always results in loss of precision. +* Always reports incremented on trappable inexact. +* 2) Fits in short BFP with no loss of precision. +* 3) Fits in short BFP, always reports inexact, and sometimes +* incremented depending on rounding mode. +* +* Also tests the following floating point support instructions +* LOAD (Short) +* LOAD (Long) +* LOAD FPC +* SET BFP ROUNDING MODE 2-BIT +* SET BFP ROUNDING MODE 3-BIT +* STORE (Short) +* STORE (Long) +* STORE FPC +* +*********************************************************************** + SPACE 2 + MACRO + PADCSECT &ENDLABL +.* +.* Macro to pad the CSECT to include result data areas if this test +.* program is not being assembled using asma. asma generates a core +.* image that is loaded by the loadcore command, and because the +.* core image is a binary stored in Github, it makes sense to make +.* this small effort to keep the core image small. +.* + AIF (D'&ENDLABL).GOODPAD + MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + MNOTE *,'No CSECT padding performed' + MEXIT +.* +.GOODPAD ANOP Label valid. See if we're on asma + AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + ORG &ENDLABL-1 Not ASMA. Pad CSECT + MEXIT +.* +.NOPAD ANOP + MNOTE *,'asma detected; no CSECT padding performed' + MEND +* +* Note: for compatibility with the z/CMS test rig, do not change +* or use R11, R14, or R15. Everything else is fair game. +* + SPACE 3 +BFPCVTFL START 0 +STRTLABL EQU * +R0 EQU 0 Work register for cc extraction +R1 EQU 1 +R2 EQU 2 Holds count of test input values +R3 EQU 3 Points to next test input value(s) +R4 EQU 4 Available +R5 EQU 5 Available +R6 EQU 6 Available +R7 EQU 7 Pointer to next result value(s) +R8 EQU 8 Pointer to next FPCR result +R9 EQU 9 Rounding tests top of outer loop +R10 EQU 10 Pointer to test address list +R11 EQU 11 **Reserved for z/CMS test rig +R12 EQU 12 Holds number of test cases in set +R13 EQU 13 Mainline return address +R14 EQU 14 **Return address for z/CMS test rig +R15 EQU 15 **Base register on z/CMS or Hyperion +* +* Floating Point Register equates to keep the cross reference clean +* +FPR0 EQU 0 +FPR1 EQU 1 +FPR2 EQU 2 +FPR3 EQU 3 +FPR4 EQU 4 +FPR5 EQU 5 +FPR6 EQU 6 +FPR7 EQU 7 +FPR8 EQU 8 +FPR9 EQU 9 +FPR10 EQU 10 +FPR11 EQU 11 +FPR12 EQU 12 +FPR13 EQU 13 +FPR14 EQU 14 +FPR15 EQU 15 +* + USING *,R15 +* +* Above works on real iron (R15=0 after sysclear) +* and in z/CMS (R15 points to start of load module) +* + ORG STRTLABL+X'8E' Program check interrution code +PCINTCD DS H +* +PCOLDPSW EQU STRTLABL+X'150' z/Arch Program check old PSW +* + ORG STRTLABL+X'1A0' z/Arch Restart PSW + DC X'0000000180000000',AD(START) +* + ORG STRTLABL+X'1D0' z/Arch Program check old PSW + DC X'0000000000000000',AD(PROGCHK) +* +* Program check routine. If Data Exception, continue execution at +* the instruction following the program check. Otherwise, hard wait. +* No need to collect data. All interesting DXC stuff is captured +* in the FPCR. +* + ORG STRTLABL+X'200' +PROGCHK DS 0H Program check occured... + CLI PCINTCD+1,X'07' Data Exception? + JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) + LPSWE PCOLDPSW ..yes, resume program execution +PCNOTDTA DS 0H + LTR R14,R14 Return address provided? + BNZR R14 Yes, return to z/CMS test rig. + LPSWE HARDWAIT Not data exception, enter disabled wait + EJECT +*********************************************************************** +* +* Main program. Enable Advanced Floating Point, process test cases. +* +*********************************************************************** + SPACE 2 +START STCTL R0,R0,CTLR0 Store CR0 to enable AFP + OI CTLR0+1,X'04' Turn on AFP bit + LCTL R0,R0,CTLR0 Reload updated CR0 +* + LA R10,SHORTS Point to integer test inputs + BAS R13,CELFBR Convert values from uint-32 to short BFP + LA R10,RMSHORTS Point to inputs for rounding mode tests + BAS R13,CELFBRA Convert using all rounding mode options +* + LA R10,LONGS Point to integer test inputs + BAS R13,CDLFBR Convert values from uint-32 to long BFP +* + LA R10,EXTDS Point to integer test inputs + BAS R13,CXLFBR Convert values from uint-32 to ext'd BFP +* + LTR R14,R14 Return address provided? + BNZR R14 ..Yes, return to z/CMS test rig. + LPSWE WAITPSW All done +* + DS 0D Ensure correct alignment for psw +WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end +* +CTLR0 DS F +FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags +* +* Input values parameter list, four fullwords: +* 1) Count, +* 2) Address of inputs, +* 3) Address to place results, and +* 4) Address to place DXC/Flags/cc values. +* + ORG STRTLABL+X'300' +SHORTS DS 0F + DC A(INTCOUNT/4) + DC A(INTIN) + DC A(SBFPOUT) + DC A(SBFPFLGS) +* +LONGS DS 0F int-32 inputs for long BFP testing + DC A(INTCOUNT/4) + DC A(INTIN) + DC A(LBFPOUT) + DC A(LBFPFLGS) +* +EXTDS DS 0F int-32 inputs for Extended BFP testing + DC A(INTCOUNT/4) + DC A(INTIN) + DC A(XBFPOUT) + DC A(XBFPFLGS) +* +RMSHORTS DC A(INTRMCT/4) + DC A(INTINRM) Last two int-32 are only concerns + DC A(SBFPRMO) Space for rounding mode tests + DC A(SBFPRMOF) Space for rounding mode test flags + EJECT +*********************************************************************** +* +* Convert uint-32 to short BFP format. A pair of results is generated +* for each input: one with all exceptions non-trappable, and the second +* with all exceptions trappable. The FPCR is stored for each result. +* +*********************************************************************** + SPACE 2 +CELFBR LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + L R1,0(,R3) Get integer test value + LFPC FPCREGNT Set exceptions non-trappable + CELFBR FPR8,0,R1,0 Cvt uint-32 in GPR1 to float in FPR8 + STE FPR8,0(,R7) Store short BFP result + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + CELFBR FPR8,0,R1,0 Cvt uint-32 in GPR1 to float in FPR0 + STE FPR8,4(,R7) Store short BFP result + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LA R3,4(,R3) Foint to next input value + LA R7,8(,R7) Point to next short BFP result pair + LA R8,8(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert uint-32 to short BFP format using every rounding mode. +* Ten test results are generated for each input. A 48-byte test result +* section is used to keep results sets aligned on a quad-double word. +* +* The first four tests use rounding modes specified in the FPCR with +* the IEEE Inexact exception supressed. SRNM (2-bit) is used for the +* first two FPCR-controlled tests and SRNMB (3-bit) is used for the +* last two To get full coverage of that instruction pair. +* +* The next six results use instruction-specified rounding modes. +* +* The default rounding mode (0 for RNTE) is not tested in this section; +* prior tests used the default rounding mode. RNTE is tested +* explicitly as a rounding mode in this section. +* +*********************************************************************** + SPACE 2 +CELFBRA LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + L R1,0(,R3) Get integer test value +* +* Test cases using rounding mode specified in the FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 1 SET FPCR to RZ, towards zero. + CELFBR FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked + STE FPR8,0*4(,R7) Store short BFP result + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 2 SET FPCR to RP, to +infinity + CELFBR FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked + STE FPR8,1*4(,R7) Store short BFP result + STFPC 1*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 3 SET FPCR to RM, to -infinity + CELFBR FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked + STE FPR8,2*4(,R7) Store short BFP result + STFPC 2*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 7 RFS, Prepare for Shorter Precision + CELFBR FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked + STE FPR8,3*4(,R7) Store short BFP result + STFPC 3*4(R8) Store resulting FPCR flags and DXC +* +* Test cases using rounding mode specified in the instruction M3 field +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CELFBR FPR8,1,R1,B'0000' RNTA, to nearest, ties away + STE FPR8,4*4(,R7) Store short BFP result + STFPC 4*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CELFBR FPR8,3,R1,B'0000' RFS, prepare for shorter precision + STE FPR8,5*4(,R7) Store short BFP result + STFPC 5*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CELFBR FPR8,4,R1,B'0000' RNTE, to nearest, ties to even + STE FPR8,6*4(,R7) Store short BFP result + STFPC 6*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CELFBR FPR8,5,R1,B'0000' RZ, toward zero + STE FPR8,7*4(,R7) Store short BFP result + STFPC 7*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CELFBR FPR8,6,R1,B'0000' RP, to +inf + STE FPR8,8*4(,R7) Store short BFP result + STFPC 8*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CELFBR FPR8,7,R1,B'0000' RM, to -inf + STE FPR8,9*4(,R7) Store short BFP result + STFPC 9*4(R8) Store resulting FPCR flags and DXC +* + LA R3,4(,R3) Point to next input values + LA R7,12*4(,R7) Point to next short BFP converted values + LA R8,12*4(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert integers to long BFP format. A pair of results is generated +* for each input: one with all exceptions non-trappable, and the second +* with all exceptions trappable. The FPCR is stored for each result. +* Conversion of a 32-bit integer to long is always exact; no exceptions +* are expected +* +*********************************************************************** + SPACE 2 +CDLFBR LM R2,R3,0(R10) Get count and addr of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + L R1,0(,R3) Get integer test value + LFPC FPCREGNT Set exceptions non-trappable + CDLFBR FPR8,0,R1,0 Cvt uint-32 in GPR1 to float in FPR8 + STD FPR8,0(,R7) Store long BFP result + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + CDLFBR FPR8,0,R1,0 Cvt uint-32 in GPR1 to float in FPR0 + STD FPR8,8(,R7) Store long BFP result + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LA R3,4(,R3) Point to next input value + LA R7,16(,R7) Point to next long BFP result pair + LA R8,8(,R8) Point to next FPCR/CC result pair + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert integers to extended BFP format. A pair of results is +* generated for each input: one with all exceptions non-trappable, +* and the second with all exceptions trappable. The FPCR is +* stored for each result. Conversion of a 32-bit integer to +* extended is always exact; no exceptions are expected +* +*********************************************************************** + SPACE 2 +CXLFBR LM R2,R3,0(R10) Get count and addr of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + L R1,0(,R3) Get integer test value + LFPC FPCREGNT Set exceptions non-trappable + CXLFBR FPR8,0,R1,0 Cvt uint-32 in GPR1 to float in FPR8-FPR10 + STD FPR8,0(,R7) Store extended BFP result part 1 + STD FPR10,8(,R7) Store extended BFP result part 1 + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + CXLFBR FPR8,0,R1,0 Cvt uint-32 in GPR1 to float in FPR8-FPR10 + STD FPR8,16(,R7) Store extended BFP result part 1 + STD FPR10,24(,R7) Store extended BFP result part 2 + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LA R3,4(,R3) Point to next input value + LA R7,32(,R7) Point to next extended BFP result pair + LA R8,8(,R8) Point to next FPCR/CC result pair + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Short integer inputs for Convert From Logical testing. The same set +* of inputs are used for short, long, and extended formats. The last +* two values are used for rounding mode and exception tests for short +* only; conversion of uint-32 to long or extended are always exact. +* +*********************************************************************** + SPACE 2 +INTIN DS 0F + DC F'U1' + DC F'U2' + DC F'U4' +INTINRM DC F'U4294967294' X'FFFFFFFE' - fits in short BFP +* ..with loss of precision. Short BFP +* ..result is 4,294,967,296 + DC F'U4294967040' X'FFFFFF00' - fits in short BFP +* ..with no loss of precision + DC F'U4294967168' X'FFFFFF40' - short BFP precision +* ..may be lost based on rounding mode + DS 0F required by asma for following EQU to work. +INTCOUNT EQU *-INTIN Count of uint-32 in list * 4 +INTRMCT EQU *-INTINRM Count of uint-32 for rounding tests * 4 +* +SBFPOUT EQU STRTLABL+X'1000' Short BFP from uint-32 inputs +* ..7 pairs used, room for 32 pairs +SBFPFLGS EQU STRTLABL+X'1100' FPCR flags and DXC from short BFP +* ..7 pairs used, room for 32 pairs +SBFPRMO EQU STRTLABL+X'1200' Short BFP rounding mode results +* ..3 sets used, room for 16 +SBFPRMOF EQU STRTLABL+X'1500' Short BFP rndg mode FPCR contents +* ..3 sets used, 16+ +* +LBFPOUT EQU STRTLABL+X'2000' Long BFP values from uint-32 inputs +* ..7 pairs used, room for 16 pairs +LBFPFLGS EQU STRTLABL+X'2100' FPCR flags and DXC from long BFP +* ..7 pairs used, room for 16 pairs +* +XBFPOUT EQU STRTLABL+X'3000' Extended BFP values from uint-32 +* ..7 pairs used, room for 16 pairs +XBFPFLGS EQU STRTLABL+X'3200' FPCR flags and DXC from long BFP +* ..7 pairs used, room for 16 pairs +* +ENDLABL EQU STRTLABL+X'3300' Next location available for results + PADCSECT ENDLABL Pad CSECT if not on ASMA + END diff --git a/tests/bfp-008-cvtfrlog.core b/tests/bfp-008-cvtfrlog.core new file mode 100644 index 000000000..42f5a6c09 Binary files /dev/null and b/tests/bfp-008-cvtfrlog.core differ diff --git a/tests/bfp-008-cvtfrlog.list b/tests/bfp-008-cvtfrlog.list new file mode 100644 index 000000000..1e99c69ed --- /dev/null +++ b/tests/bfp-008-cvtfrlog.list @@ -0,0 +1,601 @@ +ASMA Ver. 0.2.0 ieee-cvtfrlog.asm: Test IEEE Convert From Fixed (uint-32) 06 Sep 2016 09:55:24 Page 1 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 2 *********************************************************************** + 3 * + 4 *Testcase IEEE CONVERT FROM LOGICAL 32 + 5 * Test case capability includes ieee exceptions trappable and otherwise. + 6 * Test result, FPCR flags, and DXC saved for all tests. (Convert From + 7 * Fixed does not set the condition code.) + 8 * + 9 *********************************************************************** + + + 11 *********************************************************************** + 12 * + 13 * Tests the following three conversion instructions + 14 * CONVERT FROM LOGICAL (32 to short BFP, RRF-e) + 15 * CONVERT FROM LOGICAL (32 to long BFP, RRF-e) + 16 * CONVERT FROM LOGICAL (32 to extended BFP, RRF-e) + 17 * + 18 * Test data is compiled into this program. The test script that runs + 19 * this program can provide alternative test data through Hercules R + 20 * commands. + 21 * + 22 * Test Case Order + 23 * 1) Uint-32 to Short BFP + 24 * 2) Uint-32 to Short BFP with all rounding modes + 25 * 3) Uint-32 to Long BFP + 26 * 4) Uint-32 to Extended BFP + 27 * + 28 * Conversion of uint-32 to long or extended is always exact because the + 29 * number of bits in uint-32 is less than the number of bits in a long + 30 * or extended significand. For this reason, exhaustive rounding + 31 * testing is not performed for long or extended. + 32 * + 33 * Provided test data is + 34 * 1, 2, 4, 9, + 35 * 4 294 967 294 (0xFFFFFFFE) (note 1) + 36 * 4 294 967 040 (0xFFFFFF00) (note 2) + 37 * 4 294 967 168 (0xFFFFFF40) (note 3) + 38 * The last three values will trigger inexact exceptions when + 39 * converted to to short BFP and are used for exhaustive rounding mode + 40 * testing for short BFP. Specifics for each: + 41 * 1) Fits in short BFP but always results in loss of precision. + 42 * Always reports incremented on trappable inexact. + 43 * 2) Fits in short BFP with no loss of precision. + 44 * 3) Fits in short BFP, always reports inexact, and sometimes + 45 * incremented depending on rounding mode. + 46 * + 47 * Also tests the following floating point support instructions + 48 * LOAD (Short) + 49 * LOAD (Long) + 50 * LOAD FPC + 51 * SET BFP ROUNDING MODE 2-BIT + 52 * SET BFP ROUNDING MODE 3-BIT + ASMA Ver. 0.2.0 ieee-cvtfrlog.asm: Test IEEE Convert From Fixed (uint-32) 06 Sep 2016 09:55:24 Page 2 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 53 * STORE (Short) + 54 * STORE (Long) + 55 * STORE FPC + 56 * + 57 *********************************************************************** + + + 59 MACRO + 60 PADCSECT &ENDLABL + 61 .* + 62 .* Macro to pad the CSECT to include result data areas if this test + 63 .* program is not being assembled using asma. asma generates a core + 64 .* image that is loaded by the loadcore command, and because the + 65 .* core image is a binary stored in Github, it makes sense to make + 66 .* this small effort to keep the core image small. + 67 .* + 68 AIF (D'&ENDLABL).GOODPAD + 69 MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + 70 MNOTE *,'No CSECT padding performed' + 71 MEXIT + 72 .* + 73 .GOODPAD ANOP Label valid. See if we're on asma + 74 AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + 75 ORG &ENDLABL-1 Not ASMA. Pad CSECT + 76 MEXIT + 77 .* + 78 .NOPAD ANOP + 79 MNOTE *,'asma detected; no CSECT padding performed' + 80 MEND + 81 * + 82 * Note: for compatibility with the z/CMS test rig, do not change + 83 * or use R11, R14, or R15. Everything else is fair game. + 84 * + + + + 0000000000000000 00000000000004F7 86 BFPCVTFL START 0 + 0000000000000000 0000000000000001 87 STRTLABL EQU * + 0000000000000000 0000000000000001 88 R0 EQU 0 Work register for cc extraction + 0000000000000001 0000000000000001 89 R1 EQU 1 + 0000000000000002 0000000000000001 90 R2 EQU 2 Holds count of test input values + 0000000000000003 0000000000000001 91 R3 EQU 3 Points to next test input value(s) + 0000000000000004 0000000000000001 92 R4 EQU 4 Available + 0000000000000005 0000000000000001 93 R5 EQU 5 Available + 0000000000000006 0000000000000001 94 R6 EQU 6 Available + 0000000000000007 0000000000000001 95 R7 EQU 7 Pointer to next result value(s) + 0000000000000008 0000000000000001 96 R8 EQU 8 Pointer to next FPCR result + 0000000000000009 0000000000000001 97 R9 EQU 9 Rounding tests top of outer loop + 000000000000000A 0000000000000001 98 R10 EQU 10 Pointer to test address list + 000000000000000B 0000000000000001 99 R11 EQU 11 **Reserved for z/CMS test rig + 000000000000000C 0000000000000001 100 R12 EQU 12 Holds number of test cases in set + 000000000000000D 0000000000000001 101 R13 EQU 13 Mainline return address + ASMA Ver. 0.2.0 ieee-cvtfrlog.asm: Test IEEE Convert From Fixed (uint-32) 06 Sep 2016 09:55:24 Page 3 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 000000000000000E 0000000000000001 102 R14 EQU 14 **Return address for z/CMS test rig + 000000000000000F 0000000000000001 103 R15 EQU 15 **Base register on z/CMS or Hyperion + 104 * + 105 * Floating Point Register equates to keep the cross reference clean + 106 * + 0000000000000000 0000000000000001 107 FPR0 EQU 0 + 0000000000000001 0000000000000001 108 FPR1 EQU 1 + 0000000000000002 0000000000000001 109 FPR2 EQU 2 + 0000000000000003 0000000000000001 110 FPR3 EQU 3 + 0000000000000004 0000000000000001 111 FPR4 EQU 4 + 0000000000000005 0000000000000001 112 FPR5 EQU 5 + 0000000000000006 0000000000000001 113 FPR6 EQU 6 + 0000000000000007 0000000000000001 114 FPR7 EQU 7 + 0000000000000008 0000000000000001 115 FPR8 EQU 8 + 0000000000000009 0000000000000001 116 FPR9 EQU 9 + 000000000000000A 0000000000000001 117 FPR10 EQU 10 + 000000000000000B 0000000000000001 118 FPR11 EQU 11 + 000000000000000C 0000000000000001 119 FPR12 EQU 12 + 000000000000000D 0000000000000001 120 FPR13 EQU 13 + 000000000000000E 0000000000000001 121 FPR14 EQU 14 + 000000000000000F 0000000000000001 122 FPR15 EQU 15 + 123 * +0000000000000000 0000000000000000 124 USING *,R15 + 125 * + 126 * Above works on real iron (R15=0 after sysclear) + 127 * and in z/CMS (R15 points to start of load module) + 128 * +0000000000000000 0000000000000000 000000000000008E 129 ORG STRTLABL+X'8E' Program check interrution code +000000000000008E 0000 130 PCINTCD DS H + 131 * + 0000000000000150 0000000000000001 132 PCOLDPSW EQU STRTLABL+X'150' z/Arch Program check old PSW + 133 * +0000000000000090 0000000000000090 00000000000001A0 134 ORG STRTLABL+X'1A0' z/Arch Restart PSW +00000000000001A0 00000001 80000000 135 DC X'0000000180000000',AD(START) + 136 * +00000000000001B0 00000000000001B0 00000000000001D0 137 ORG STRTLABL+X'1D0' z/Arch Program check old PSW +00000000000001D0 00000000 00000000 138 DC X'0000000000000000',AD(PROGCHK) + 139 * + 140 * Program check routine. If Data Exception, continue execution at + 141 * the instruction following the program check. Otherwise, hard wait. + 142 * No need to collect data. All interesting DXC stuff is captured + 143 * in the FPCR. + 144 * +00000000000001E0 00000000000001E0 0000000000000200 145 ORG STRTLABL+X'200' +0000000000000200 146 PROGCHK DS 0H Program check occured... +0000000000000200 9507 F08F 000000000000008F 147 CLI PCINTCD+1,X'07' Data Exception? +0000000000000204 A774 0004 000000000000020C 148 JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) +0000000000000208 B2B2 F150 0000000000000150 149 LPSWE PCOLDPSW ..yes, resume program execution +000000000000020C 150 PCNOTDTA DS 0H +000000000000020C 12EE 151 LTR R14,R14 Return address provided? +000000000000020E 077E 152 BNZR R14 Yes, return to z/CMS test rig. +0000000000000210 B2B2 F258 0000000000000258 153 LPSWE HARDWAIT Not data exception, enter disabled wait + ASMA Ver. 0.2.0 ieee-cvtfrlog.asm: Test IEEE Convert From Fixed (uint-32) 06 Sep 2016 09:55:24 Page 4 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 155 *********************************************************************** + 156 * + 157 * Main program. Enable Advanced Floating Point, process test cases. + 158 * +0000000000000214 B600 F268 0000000000000268 159 START STCTL R0,R0,CTLR0 Store CR0 to enable AFP +0000000000000218 9604 F269 0000000000000269 160 OI CTLR0+1,X'04' Turn on AFP bit +000000000000021C B700 F268 0000000000000268 161 LCTL R0,R0,CTLR0 Reload updated CR0 + 162 * +0000000000000220 41A0 F300 0000000000000300 163 LA R10,SHORTS Point to integer test inputs +0000000000000224 4DD0 F340 0000000000000340 164 BAS R13,CELFBR Convert values from uint-32 to short BFP +0000000000000228 41A0 F330 0000000000000330 165 LA R10,RMSHORTS Point to inputs for rounding mode tests +000000000000022C 4DD0 F382 0000000000000382 166 BAS R13,CELFBRA Convert using all rounding mode options + 167 * +0000000000000230 41A0 F310 0000000000000310 168 LA R10,LONGS Point to integer test inputs +0000000000000234 4DD0 F454 0000000000000454 169 BAS R13,CDLFBR Convert values from uint-32 to long BFP + 170 * +0000000000000238 41A0 F320 0000000000000320 171 LA R10,EXTDS Point to integer test inputs +000000000000023C 4DD0 F496 0000000000000496 172 BAS R13,CXLFBR Convert values from uint-32 to ext'd BFP + 173 * +0000000000000240 12EE 174 LTR R14,R14 Return address provided? +0000000000000242 077E 175 BNZR R14 ..Yes, return to z/CMS test rig. +0000000000000244 B2B2 F248 0000000000000248 176 LPSWE WAITPSW All done + 177 * +0000000000000248 178 DS 0D Ensure correct alignment for psw +0000000000000248 00020000 00000000 179 WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +0000000000000258 00020000 00000000 180 HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end + 181 * +0000000000000268 00000000 182 CTLR0 DS F +000000000000026C 00000000 183 FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +0000000000000270 F8000000 184 FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags + 185 * + 186 * Input values parameter list, four fullwords: + 187 * 1) Count, + 188 * 2) Address of inputs, + 189 * 3) Address to place results, and + 190 * 4) Address to place DXC/Flags/cc values. + 191 * +0000000000000274 0000000000000274 0000000000000300 192 ORG STRTLABL+X'300' +0000000000000300 193 SHORTS DS 0F +0000000000000300 00000006 194 DC A(INTCOUNT/4) +0000000000000304 000004E0 195 DC A(INTIN) +0000000000000308 00001000 196 DC A(SBFPOUT) +000000000000030C 00001100 197 DC A(SBFPFLGS) + 198 * +0000000000000310 199 LONGS DS 0F int-32 inputs for long BFP testing +0000000000000310 00000006 200 DC A(INTCOUNT/4) +0000000000000314 000004E0 201 DC A(INTIN) +0000000000000318 00002000 202 DC A(LBFPOUT) +000000000000031C 00002100 203 DC A(LBFPFLGS) + 204 * +0000000000000320 205 EXTDS DS 0F int-32 inputs for Extended BFP testing +0000000000000320 00000006 206 DC A(INTCOUNT/4) + ASMA Ver. 0.2.0 ieee-cvtfrlog.asm: Test IEEE Convert From Fixed (uint-32) 06 Sep 2016 09:55:24 Page 5 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000324 000004E0 207 DC A(INTIN) +0000000000000328 00003000 208 DC A(XBFPOUT) +000000000000032C 00003200 209 DC A(XBFPFLGS) + 210 * +0000000000000330 00000003 211 RMSHORTS DC A(INTRMCT/4) +0000000000000334 000004EC 212 DC A(INTINRM) Last two int-32 are only concerns +0000000000000338 00001200 213 DC A(SBFPRMO) Space for rounding mode tests +000000000000033C 00001500 214 DC A(SBFPRMOF) Space for rounding mode test flags + ASMA Ver. 0.2.0 ieee-cvtfrlog.asm: Test IEEE Convert From Fixed (uint-32) 06 Sep 2016 09:55:24 Page 6 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 216 *********************************************************************** + 217 * + 218 * Convert uint-32 to short BFP format. A pair of results is generated + 219 * for each input: one with all exceptions non-trappable, and the second + 220 * with all exceptions trappable. The FPCR is stored for each result. + 221 * + 222 *********************************************************************** + + +0000000000000340 9823 A000 0000000000000000 224 CELFBR LM R2,R3,0(R10) Get count and address of test input values +0000000000000344 9878 A008 0000000000000008 225 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000348 1222 226 LTR R2,R2 Any test cases? +000000000000034A 078D 227 BZR R13 ..No, return to caller +000000000000034C 0DC0 228 BASR R12,0 Set top of loop + 229 * +000000000000034E 5810 3000 0000000000000000 230 L R1,0(,R3) Get integer test value +0000000000000352 B29D F26C 000000000000026C 231 LFPC FPCREGNT Set exceptions non-trappable +0000000000000356 B390 0081 232 CELFBR FPR8,0,R1,0 Cvt uint-32 in GPR1 to float in FPR8 +000000000000035A 7080 7000 0000000000000000 233 STE FPR8,0(,R7) Store short BFP result +000000000000035E B29C 8000 0000000000000000 234 STFPC 0(R8) Store resulting FPCR flags and DXC + 235 * +0000000000000362 B29D F270 0000000000000270 236 LFPC FPCREGTR Set exceptions trappable +0000000000000366 B390 0081 237 CELFBR FPR8,0,R1,0 Cvt uint-32 in GPR1 to float in FPR0 +000000000000036A 7080 7004 0000000000000004 238 STE FPR8,4(,R7) Store short BFP result +000000000000036E B29C 8004 0000000000000004 239 STFPC 4(R8) Store resulting FPCR flags and DXC + 240 * +0000000000000372 4130 3004 0000000000000004 241 LA R3,4(,R3) Foint to next input value +0000000000000376 4170 7008 0000000000000008 242 LA R7,8(,R7) Point to next short BFP result pair +000000000000037A 4180 8008 0000000000000008 243 LA R8,8(,R8) Point to next FPCR/CC result area +000000000000037E 062C 244 BCTR R2,R12 Convert next input value. +0000000000000380 07FD 245 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvtfrlog.asm: Test IEEE Convert From Fixed (uint-32) 06 Sep 2016 09:55:24 Page 7 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 247 *********************************************************************** + 248 * + 249 * Convert uint-32 to short BFP format using every rounding mode. + 250 * Ten test results are generated for each input. A 48-byte test result + 251 * section is used to keep results sets aligned on a quad-double word. + 252 * + 253 * The first four tests use rounding modes specified in the FPCR with + 254 * the IEEE Inexact exception supressed. SRNM (2-bit) is used for the + 255 * first two FPCR-controlled tests and SRNMB (3-bit) is used for the + 256 * last two To get full coverage of that instruction pair. + 257 * + 258 * The next six results use instruction-specified rounding modes. + 259 * + 260 * The default rounding mode (0 for RNTE) is not tested in this section; + 261 * prior tests used the default rounding mode. RNTE is tested + 262 * explicitly as a rounding mode in this section. + 263 * + 264 *********************************************************************** + + +0000000000000382 9823 A000 0000000000000000 266 CELFBRA LM R2,R3,0(R10) Get count and address of test input values +0000000000000386 9878 A008 0000000000000008 267 LM R7,R8,8(R10) Get address of result area and flag area. +000000000000038A 1222 268 LTR R2,R2 Any test cases? +000000000000038C 078D 269 BZR R13 ..No, return to caller +000000000000038E 0DC0 270 BASR R12,0 Set top of loop + 271 * +0000000000000390 5810 3000 0000000000000000 272 L R1,0(,R3) Get integer test value + 273 * + 274 * Test cases using rounding mode specified in the FPCR + 275 * +0000000000000394 B29D F26C 000000000000026C 276 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000398 B299 0001 0000000000000001 277 SRNM 1 SET FPCR to RZ, towards zero. +000000000000039C B390 0481 278 CELFBR FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked +00000000000003A0 7080 7000 0000000000000000 279 STE FPR8,0*4(,R7) Store short BFP result +00000000000003A4 B29C 8000 0000000000000000 280 STFPC 0(R8) Store resulting FPCR flags and DXC + 281 * +00000000000003A8 B29D F26C 000000000000026C 282 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000003AC B299 0002 0000000000000002 283 SRNM 2 SET FPCR to RP, to +infinity +00000000000003B0 B390 0481 284 CELFBR FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked +00000000000003B4 7080 7004 0000000000000004 285 STE FPR8,1*4(,R7) Store short BFP result +00000000000003B8 B29C 8004 0000000000000004 286 STFPC 1*4(R8) Store resulting FPCR flags and DXC + 287 * +00000000000003BC B29D F26C 000000000000026C 288 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000003C0 B2B8 0003 0000000000000003 289 SRNMB 3 SET FPCR to RM, to -infinity +00000000000003C4 B390 0481 290 CELFBR FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked +00000000000003C8 7080 7008 0000000000000008 291 STE FPR8,2*4(,R7) Store short BFP result +00000000000003CC B29C 8008 0000000000000008 292 STFPC 2*4(R8) Store resulting FPCR flags and DXC + 293 * +00000000000003D0 B29D F26C 000000000000026C 294 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000003D4 B2B8 0007 0000000000000007 295 SRNMB 7 RFS, Prepare for Shorter Precision +00000000000003D8 B390 0481 296 CELFBR FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked +00000000000003DC 7080 700C 000000000000000C 297 STE FPR8,3*4(,R7) Store short BFP result + ASMA Ver. 0.2.0 ieee-cvtfrlog.asm: Test IEEE Convert From Fixed (uint-32) 06 Sep 2016 09:55:24 Page 8 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000003E0 B29C 800C 000000000000000C 298 STFPC 3*4(R8) Store resulting FPCR flags and DXC + 299 * + 300 * Test cases using rounding mode specified in the instruction M3 field + 301 * +00000000000003E4 B29D F26C 000000000000026C 302 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000003E8 B390 1081 303 CELFBR FPR8,1,R1,B'0000' RNTA, to nearest, ties away +00000000000003EC 7080 7010 0000000000000010 304 STE FPR8,4*4(,R7) Store short BFP result +00000000000003F0 B29C 8010 0000000000000010 305 STFPC 4*4(R8) Store resulting FPCR flags and DXC + 306 * +00000000000003F4 B29D F26C 000000000000026C 307 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000003F8 B390 3081 308 CELFBR FPR8,3,R1,B'0000' RFS, prepare for shorter precision +00000000000003FC 7080 7014 0000000000000014 309 STE FPR8,5*4(,R7) Store short BFP result +0000000000000400 B29C 8014 0000000000000014 310 STFPC 5*4(R8) Store resulting FPCR flags and DXC + 311 * +0000000000000404 B29D F26C 000000000000026C 312 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000408 B390 4081 313 CELFBR FPR8,4,R1,B'0000' RNTE, to nearest, ties to even +000000000000040C 7080 7018 0000000000000018 314 STE FPR8,6*4(,R7) Store short BFP result +0000000000000410 B29C 8018 0000000000000018 315 STFPC 6*4(R8) Store resulting FPCR flags and DXC + 316 * +0000000000000414 B29D F26C 000000000000026C 317 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000418 B390 5081 318 CELFBR FPR8,5,R1,B'0000' RZ, toward zero +000000000000041C 7080 701C 000000000000001C 319 STE FPR8,7*4(,R7) Store short BFP result +0000000000000420 B29C 801C 000000000000001C 320 STFPC 7*4(R8) Store resulting FPCR flags and DXC + 321 * +0000000000000424 B29D F26C 000000000000026C 322 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000428 B390 6081 323 CELFBR FPR8,6,R1,B'0000' RP, to +inf +000000000000042C 7080 7020 0000000000000020 324 STE FPR8,8*4(,R7) Store short BFP result +0000000000000430 B29C 8020 0000000000000020 325 STFPC 8*4(R8) Store resulting FPCR flags and DXC + 326 * +0000000000000434 B29D F26C 000000000000026C 327 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000438 B390 7081 328 CELFBR FPR8,7,R1,B'0000' RM, to -inf +000000000000043C 7080 7024 0000000000000024 329 STE FPR8,9*4(,R7) Store short BFP result +0000000000000440 B29C 8024 0000000000000024 330 STFPC 9*4(R8) Store resulting FPCR flags and DXC + 331 * +0000000000000444 4130 3004 0000000000000004 332 LA R3,4(,R3) Point to next input values +0000000000000448 4170 7030 0000000000000030 333 LA R7,12*4(,R7) Point to next short BFP converted values +000000000000044C 4180 8030 0000000000000030 334 LA R8,12*4(,R8) Point to next FPCR/CC result area +0000000000000450 062C 335 BCTR R2,R12 Convert next input value. +0000000000000452 07FD 336 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvtfrlog.asm: Test IEEE Convert From Fixed (uint-32) 06 Sep 2016 09:55:24 Page 9 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 338 *********************************************************************** + 339 * + 340 * Convert integers to long BFP format. A pair of results is generated + 341 * for each input: one with all exceptions non-trappable, and the second + 342 * with all exceptions trappable. The FPCR is stored for each result. + 343 * Conversion of a 32-bit integer to long is always exact; no exceptions + 344 * are expected + 345 * + 346 *********************************************************************** + + +0000000000000454 9823 A000 0000000000000000 348 CDLFBR LM R2,R3,0(R10) Get count and addr of test input values +0000000000000458 9878 A008 0000000000000008 349 LM R7,R8,8(R10) Get address of result area and flag area. +000000000000045C 1222 350 LTR R2,R2 Any test cases? +000000000000045E 078D 351 BZR R13 ..No, return to caller +0000000000000460 0DC0 352 BASR R12,0 Set top of loop + 353 * +0000000000000462 5810 3000 0000000000000000 354 L R1,0(,R3) Get integer test value +0000000000000466 B29D F26C 000000000000026C 355 LFPC FPCREGNT Set exceptions non-trappable +000000000000046A B391 0081 356 CDLFBR FPR8,0,R1,0 Cvt uint-32 in GPR1 to float in FPR8 +000000000000046E 6080 7000 0000000000000000 357 STD FPR8,0(,R7) Store long BFP result +0000000000000472 B29C 8000 0000000000000000 358 STFPC 0(R8) Store resulting FPCR flags and DXC + 359 * +0000000000000476 B29D F270 0000000000000270 360 LFPC FPCREGTR Set exceptions trappable +000000000000047A B391 0081 361 CDLFBR FPR8,0,R1,0 Cvt uint-32 in GPR1 to float in FPR0 +000000000000047E 6080 7008 0000000000000008 362 STD FPR8,8(,R7) Store long BFP result +0000000000000482 B29C 8004 0000000000000004 363 STFPC 4(R8) Store resulting FPCR flags and DXC + 364 * +0000000000000486 4130 3004 0000000000000004 365 LA R3,4(,R3) Point to next input value +000000000000048A 4170 7010 0000000000000010 366 LA R7,16(,R7) Point to next long BFP result pair +000000000000048E 4180 8008 0000000000000008 367 LA R8,8(,R8) Point to next FPCR/CC result pair +0000000000000492 062C 368 BCTR R2,R12 Convert next input value. +0000000000000494 07FD 369 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvtfrlog.asm: Test IEEE Convert From Fixed (uint-32) 06 Sep 2016 09:55:24 Page 10 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 371 *********************************************************************** + 372 * + 373 * Convert integers to extended BFP format. A pair of results is + 374 * generated for each input: one with all exceptions non-trappable, + 375 * and the second with all exceptions trappable. The FPCR is + 376 * stored for each result. Conversion of a 32-bit integer to + 377 * extended is always exact; no exceptions are expected + 378 * + 379 *********************************************************************** + + +0000000000000496 9823 A000 0000000000000000 381 CXLFBR LM R2,R3,0(R10) Get count and addr of test input values +000000000000049A 9878 A008 0000000000000008 382 LM R7,R8,8(R10) Get address of result area and flag area. +000000000000049E 1222 383 LTR R2,R2 Any test cases? +00000000000004A0 078D 384 BZR R13 ..No, return to caller +00000000000004A2 0DC0 385 BASR R12,0 Set top of loop + 386 * +00000000000004A4 5810 3000 0000000000000000 387 L R1,0(,R3) Get integer test value +00000000000004A8 B29D F26C 000000000000026C 388 LFPC FPCREGNT Set exceptions non-trappable +00000000000004AC B392 0081 389 CXLFBR FPR8,0,R1,0 Cvt uint-32 in GPR1 to float in FPR8-FPR10 +00000000000004B0 6080 7000 0000000000000000 390 STD FPR8,0(,R7) Store extended BFP result part 1 +00000000000004B4 60A0 7008 0000000000000008 391 STD FPR10,8(,R7) Store extended BFP result part 1 +00000000000004B8 B29C 8000 0000000000000000 392 STFPC 0(R8) Store resulting FPCR flags and DXC + 393 * +00000000000004BC B29D F270 0000000000000270 394 LFPC FPCREGTR Set exceptions trappable +00000000000004C0 B392 0081 395 CXLFBR FPR8,0,R1,0 Cvt uint-32 in GPR1 to float in FPR8-FPR10 +00000000000004C4 6080 7010 0000000000000010 396 STD FPR8,16(,R7) Store extended BFP result part 1 +00000000000004C8 60A0 7018 0000000000000018 397 STD FPR10,24(,R7) Store extended BFP result part 2 +00000000000004CC B29C 8004 0000000000000004 398 STFPC 4(R8) Store resulting FPCR flags and DXC + 399 * +00000000000004D0 4130 3004 0000000000000004 400 LA R3,4(,R3) Point to next input value +00000000000004D4 4170 7020 0000000000000020 401 LA R7,32(,R7) Point to next extended BFP result pair +00000000000004D8 4180 8008 0000000000000008 402 LA R8,8(,R8) Point to next FPCR/CC result pair +00000000000004DC 062C 403 BCTR R2,R12 Convert next input value. +00000000000004DE 07FD 404 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvtfrlog.asm: Test IEEE Convert From Fixed (uint-32) 06 Sep 2016 09:55:24 Page 11 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 406 *********************************************************************** + 407 * + 408 * Short integer inputs for Convert From Logical testing. The same set + 409 * of inputs are used for short, long, and extended formats. The last + 410 * two values are used for rounding mode and exception tests for short + 411 * only; conversion of uint-32 to long or extended are always exact. + 412 * + 413 *********************************************************************** + + +00000000000004E0 415 INTIN DS 0F +00000000000004E0 00000001 416 DC F'U1' +00000000000004E4 00000002 417 DC F'U2' +00000000000004E8 00000004 418 DC F'U4' +00000000000004EC FFFFFFFE 419 INTINRM DC F'U4294967294' X'FFFFFFFE' - fits in short BFP + 420 * ..with loss of precision. Short BFP + 421 * ..result is 4,294,967,296 +00000000000004F0 FFFFFF00 422 DC F'U4294967040' X'FFFFFF00' - fits in short BFP + 423 * ..with no loss of precision +00000000000004F4 FFFFFF80 424 DC F'U4294967168' X'FFFFFF40' - short BFP precision + 425 * ..may be lost based on rounding mode +00000000000004F8 426 DS 0F required by asma for following EQU to work. + 0000000000000018 0000000000000001 427 INTCOUNT EQU *-INTIN Count of uint-32 in list * 4 + 000000000000000C 0000000000000001 428 INTRMCT EQU *-INTINRM Count of uint-32 for rounding tests * 4 + 429 * + 0000000000001000 0000000000000001 430 SBFPOUT EQU STRTLABL+X'1000' Short BFP from uint-32 inputs + 431 * ..7 pairs used, room for 32 pairs + 0000000000001100 0000000000000001 432 SBFPFLGS EQU STRTLABL+X'1100' FPCR flags and DXC from short BFP + 433 * ..7 pairs used, room for 32 pairs + 0000000000001200 0000000000000001 434 SBFPRMO EQU STRTLABL+X'1200' Short BFP rounding mode results + 435 * ..3 sets used, room for 16 + 0000000000001500 0000000000000001 436 SBFPRMOF EQU STRTLABL+X'1500' Short BFP rndg mode FPCR contents + 437 * ..3 sets used, 16+ + 438 * + 0000000000002000 0000000000000001 439 LBFPOUT EQU STRTLABL+X'2000' Long BFP values from uint-32 inputs + 440 * ..7 pairs used, room for 16 pairs + 0000000000002100 0000000000000001 441 LBFPFLGS EQU STRTLABL+X'2100' FPCR flags and DXC from long BFP + 442 * ..7 pairs used, room for 16 pairs + 443 * + 0000000000003000 0000000000000001 444 XBFPOUT EQU STRTLABL+X'3000' Extended BFP values from uint-32 + 445 * ..7 pairs used, room for 16 pairs + 0000000000003200 0000000000000001 446 XBFPFLGS EQU STRTLABL+X'3200' FPCR flags and DXC from long BFP + 447 * ..7 pairs used, room for 16 pairs + 448 * + 0000000000003300 0000000000000001 449 ENDLABL EQU STRTLABL+X'3300' Next location available for results + 450 PADCSECT ENDLABL Pad CSECT if not on ASMA + 451+ MNOTE *,'asma detected; no CSECT padding performed' +00000000000004F8 452 END + ASMA Ver. 0.2.0 ieee-cvtfrlog.asm: Test IEEE Convert From Fixed (uint-32) 06 Sep 2016 09:55:24 Page 12 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +BFPCVTFL J 000000 1272 86 +CDLFBR I 000454 4 348 169 +CELFBR I 000340 4 224 164 +CELFBRA I 000382 4 266 166 +CTLR0 F 000268 4 182 159 160 161 +CXLFBR I 000496 4 381 172 +ENDLABL U 003300 1 449 +EXTDS F 000320 4 205 171 +FPCREGNT X 00026C 4 183 231 276 282 288 294 302 307 312 317 322 327 355 388 +FPCREGTR X 000270 4 184 236 360 394 +FPR0 U 000000 1 107 +FPR1 U 000001 1 108 +FPR10 U 00000A 1 117 391 397 +FPR11 U 00000B 1 118 +FPR12 U 00000C 1 119 +FPR13 U 00000D 1 120 +FPR14 U 00000E 1 121 +FPR15 U 00000F 1 122 +FPR2 U 000002 1 109 +FPR3 U 000003 1 110 +FPR4 U 000004 1 111 +FPR5 U 000005 1 112 +FPR6 U 000006 1 113 +FPR7 U 000007 1 114 +FPR8 U 000008 1 115 232 233 237 238 278 279 284 285 290 291 296 297 303 304 308 309 313 + 314 318 319 323 324 328 329 356 357 361 362 389 390 395 396 +FPR9 U 000009 1 116 +HARDWAIT X 000258 8 180 153 +IMAGE 1 000000 1272 0 +INTCOUNT U 000018 1 427 194 200 206 +INTIN F 0004E0 4 415 427 195 201 207 +INTINRM F 0004EC 4 419 428 212 +INTRMCT U 00000C 1 428 211 +LBFPFLGS U 002100 1 441 203 +LBFPOUT U 002000 1 439 202 +LONGS F 000310 4 199 168 +PCINTCD H 00008E 2 130 147 +PCNOTDTA H 00020C 2 150 148 +PCOLDPSW U 000150 1 132 149 +PROGCHK H 000200 2 146 138 +R0 U 000000 1 88 159 161 +R1 U 000001 1 89 230 232 237 272 278 284 290 296 303 308 313 318 323 328 354 356 361 + 387 389 395 +R10 U 00000A 1 98 163 165 168 171 224 225 266 267 348 349 381 382 +R11 U 00000B 1 99 +R12 U 00000C 1 100 228 244 270 335 352 368 385 403 +R13 U 00000D 1 101 164 166 169 172 227 245 269 336 351 369 384 404 +R14 U 00000E 1 102 151 152 174 175 +R15 U 00000F 1 103 124 +R2 U 000002 1 90 224 226 244 266 268 335 348 350 368 381 383 403 +R3 U 000003 1 91 224 230 241 266 272 332 348 354 365 381 387 400 +R4 U 000004 1 92 + ASMA Ver. 0.2.0 ieee-cvtfrlog.asm: Test IEEE Convert From Fixed (uint-32) 06 Sep 2016 09:55:24 Page 13 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +R5 U 000005 1 93 +R6 U 000006 1 94 +R7 U 000007 1 95 225 233 238 242 267 279 285 291 297 304 309 314 319 324 329 333 349 + 357 362 366 382 390 391 396 397 401 +R8 U 000008 1 96 225 234 239 243 267 280 286 292 298 305 310 315 320 325 330 334 349 + 358 363 367 382 392 398 402 +R9 U 000009 1 97 +RMSHORTS A 000330 4 211 165 +SBFPFLGS U 001100 1 432 197 +SBFPOUT U 001000 1 430 196 +SBFPRMO U 001200 1 434 213 +SBFPRMOF U 001500 1 436 214 +SHORTS F 000300 4 193 163 +START I 000214 4 159 135 +STRTLABL U 000000 1 87 129 132 134 137 145 192 430 432 434 436 439 441 444 446 449 +WAITPSW X 000248 8 179 176 +XBFPFLGS U 003200 1 446 209 +XBFPOUT U 003000 1 444 208 + ASMA Ver. 0.2.0 ieee-cvtfrlog.asm: Test IEEE Convert From Fixed (uint-32) 06 Sep 2016 09:55:24 Page 14 + + MACRO DEFN REFERENCES + +PADCSECT 60 450 + ASMA Ver. 0.2.0 ieee-cvtfrlog.asm: Test IEEE Convert From Fixed (uint-32) 06 Sep 2016 09:55:24 Page 15 + + DESC SYMBOL SIZE POS ADDR + +Entry: 0 + +Image IMAGE 1272 000-4F7 000-4F7 + Region 1272 000-4F7 000-4F7 + CSECT BFPCVTFL 1272 000-4F7 000-4F7 + ASMA Ver. 0.2.0 ieee-cvtfrlog.asm: Test IEEE Convert From Fixed (uint-32) 06 Sep 2016 09:55:24 Page 16 + + STMT FILE NAME + +1 C:\Users\srorso\Documents\GitHub\hyperion\tests\bfp-008-cvtfrlog.asm + + +** NO ERRORS FOUND ** + +[451] MNOTE *,asma detected; no CSECT padding performed + \ No newline at end of file diff --git a/tests/bfp-008-cvtfrlog.tst b/tests/bfp-008-cvtfrlog.tst new file mode 100644 index 000000000..e855b91d0 --- /dev/null +++ b/tests/bfp-008-cvtfrlog.tst @@ -0,0 +1,154 @@ +*Testcase bfp-008-cvtfrlog.tst: CELFBR, CDLFBR, CXLFBR + +#Testcase bfp-008-cvtfrlog.tst: IEEE Convert From Logical +#..Includes CONVERT FROM LOGICAL 32 (3). Also tests traps and exceptions +#..and results from different rounding modes (CELFBR only). + +sysclear +archmode esame + +# +# Following suppresses logging of program checks. This test program, as part +# of its normal operation, generates 2 program check messages that have no +# value in the validation process. (The messages, not the program checks.) +# +ostailor quiet + +loadcore "$(testpath)/bfp-008-cvtfrlog.core" + +runtest 1.0 + +ostailor null # restore messages for subsequent tests + + +# inputs converted to BFP short - result values +*Compare +r 1000.10 +*Want "CELFBR result pairs 1-2" 3F800000 3F800000 40000000 40000000 +r 1010.10 +*Want "CELFBR result pairs 3-4" 40800000 40800000 4F800000 4F800000 +r 1020.10 +*Want "CELFBR result pairs 5-6" 4F7FFFFF 4F7FFFFF 4F800000 4F800000 + +# inputs converted to BFP short - FPCR contents +*Compare +r 1100.10 +*Want "CELFBR FPC pairs 1-2" 00000000 F8000000 00000000 F8000000 +r 1110.10 +*Want "CELFBR FPC pairs 3-4" 00000000 F8000000 00080000 F8000C00 +r 1120.10 +*Want "CELFBR FPC pairs 5-6" 00000000 F8000000 00080000 F8000C00 + + +# inputs converted to BFP short - rounding mode test results +*Compare +r 1200.10 +*Want "CELFBR maxint-32 result FPC modes 1-3, 7" 4F7FFFFF 4F800000 4F7FFFFF 4F7FFFFF +r 1210.10 +*Want "CELFBR maxint-32 result M3 modes 1, 3-5" 4F800000 4F7FFFFF 4F800000 4F7FFFFF +r 1220.08 +*Want "CELFBR maxint-32 result M3 modes 6, 7" 4F800000 4F7FFFFF + +r 1230.10 +*Want "CELFBR 0xFFFFFF00 result FPC modes 1-3, 7" 4F7FFFFF 4F7FFFFF 4F7FFFFF 4F7FFFFF +r 1240.10 +*Want "CELFBR 0xFFFFFF00 result M3 modes 1, 3-5" 4F7FFFFF 4F7FFFFF 4F7FFFFF 4F7FFFFF +r 1250.08 +*Want "CELFBR 0xFFFFFF00 result M3 modes 6, 7" 4F7FFFFF 4F7FFFFF + +r 1260.10 +*Want "CELFBR 0xFFFFFF40 result FPC modes 1-3, 7" 4F7FFFFF 4F800000 4F7FFFFF 4F7FFFFF +r 1270.10 +*Want "CELFBR 0xFFFFFF40 result M3 modes 1, 3-5" 4F800000 4F7FFFFF 4F800000 4F7FFFFF +r 1280.08 +*Want "CELFBR 0xFFFFFF40 result M3 modes 6, 7" 4F800000 4F7FFFFF + + +# inputs converted to BFP short - rounding mode test FPCR contents +*Compare +r 1500.10 +*Want "CELFBR maxint-32 FPC modes 1-3, 7 FPCR" 00000001 00000002 00000003 00000007 +r 1510.10 +*Want "CELFBR maxint-32 M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 1520.08 +*Want "CELFBR maxint-32 M3 modes 5-7" 00080000 00080000 + +r 1530.10 +*Want "CELFBR 0xFFFFFF00 FPC modes 1-3, 7 FPCR" 00000001 00000002 00000003 00000007 +r 1540.10 +*Want "CELFBR 0xFFFFFF00 M3 modes 1, 3-5 FPCR" 00000000 00000000 00000000 00000000 +r 1550.08 +*Want "CELFBR 0xFFFFFF00 M3 modes 6-7" 00000000 00000000 + +r 1560.10 +*Want "CELFBR 0xFFFFFF40 FPC modes 1-3, 7 FPCR" 00000001 00000002 00000003 00000007 +r 1570.10 +*Want "CELFBR 0xFFFFFF40 M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 1580.08 +*Want "CELFBR 0xFFFFFF40 M3 modes 6-7" 00080000 00080000 + + +# inputs converted to BFP long - result values +*Compare +r 2000.10 +*Want "CDLFBR result pair 1" 3FF00000 00000000 3FF00000 00000000 +r 2010.10 +*Want "CDLFBR result pair 2" 40000000 00000000 40000000 00000000 +r 2020.10 +*Want "CDLFBR result pair 3" 40100000 00000000 40100000 00000000 +r 2030.10 +*Want "CDLFBR result pair 4" 41EFFFFF FFC00000 41EFFFFF FFC00000 +r 2040.10 +*Want "CDLFBR result pair 5" 41EFFFFF E0000000 41EFFFFF E0000000 +r 2050.10 +*Want "CDLFBR result pair 6" 41EFFFFF F0000000 41EFFFFF F0000000 + +# Inputs converted to BFP long - FPCR contents +*Compare +r 2100.10 +*Want "CDLFBR FPC pairs 1-2" 00000000 F8000000 00000000 F8000000 +r 2110.10 +*Want "CDLFBR FPC pairs 3-4" 00000000 F8000000 00000000 F8000000 +r 2120.10 +*Want "CDLFBR FPC pairs 5-6" 00000000 F8000000 00000000 F8000000 + + +# Inputs converted to BFP extended - result values +*Compare +r 3000.10 +*Want "CXLFBR result 1a" 3FFF0000 00000000 00000000 00000000 +r 3010.10 +*Want "CXLFBR result 1b" 3FFF0000 00000000 00000000 00000000 +r 3020.10 +*Want "CXLFBR result 2a" 40000000 00000000 00000000 00000000 +r 3030.10 +*Want "CXLFBR result 2b" 40000000 00000000 00000000 00000000 +r 3040.10 +*Want "CXLFBR result 3a" 40010000 00000000 00000000 00000000 +r 3050.10 +*Want "CXLFBR result 3b" 40010000 00000000 00000000 00000000 +r 3060.10 +*Want "CXLFBR result 4a" 401EFFFF FFFC0000 00000000 00000000 +r 3070.10 +*Want "CXLFBR result 4b" 401EFFFF FFFC0000 00000000 00000000 +r 3080.10 +*Want "CXLFBR result 5a" 401EFFFF FE000000 00000000 00000000 +r 3090.10 +*Want "CXLFBR result 5b" 401EFFFF FE000000 00000000 00000000 +r 30A0.10 +*Want "CXLFBR result 6a" 401EFFFF FF000000 00000000 00000000 +r 30B0.10 +*Want "CXLFBR result 6b" 401EFFFF FF000000 00000000 00000000 + +# Inputs converted to BFP extended - FPCR contents +*Compare +r 3200.10 +*Want "CXLFBR FPC pairs 1-2" 00000000 F8000000 00000000 F8000000 +r 3210.10 +*Want "CXLFBR FPC pairs 3-4" 00000000 F8000000 00000000 F8000000 +r 3220.10 +*Want "CXLFBR FPC pairs 5-6" 00000000 F8000000 00000000 F8000000 + + +*Done + diff --git a/tests/bfp-009-cvtfrlog64.asm b/tests/bfp-009-cvtfrlog64.asm new file mode 100644 index 000000000..2f4c7e7d5 --- /dev/null +++ b/tests/bfp-009-cvtfrlog64.asm @@ -0,0 +1,600 @@ + TITLE 'bfp-009-cvtfrlog64.asm: Test IEEE Cvt From Fixed (uint-64)' +*********************************************************************** +* +*Testcase IEEE CONVERT FROM LOGICAL 64 +* Test case capability includes ieee exceptions trappable and otherwise. +* Test result, FPC flags, and DXC saved for all tests. (Convert From +* Logical does not set the condition code.) +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* bfp-009-cvtfrlog64.asm +* +* This assembly-language source file is part of the +* Hercules Decimal Floating Point Validation Package +* by Stephen R. Orso +* +* Copyright 2016 by Stephen R Orso. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* +* 3. The name of the author may not be used to endorse or promote +* products derived from this software without specific prior written +* permission. +* +* DISCLAMER: THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* HOLDER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* Tests the following three conversion instructions +* CONVERT FROM LOGICAL (64 to short BFP, RRF-e) +* CONVERT FROM LOGICAL (64 to long BFP, RRF-e) +* CONVERT FROM LOGICAL (64 to extended BFP, RRF-e) +* +* Limited test data is compiled into this program. The test script +* that runs this program can provide alternative test data through +* Hercules R commands. +* +* Test Case Order +* 1) Uint-64 to Short BFP +* 2) Uint-64 to Short BFP with all rounding modes +* 3) Uint-64 to Long BFP +* 4) Uint-64 to Long BFP with all rounding modes +* 5) Uint-64 to Extended BFP +* +* Provided test data is: +* 1, 2, 4, +* 9 007 199 254 740 991(0x001FFFFFFFFFFFFF) +* 18 014 398 509 481 983(0x003FFFFFFFFFFFFF) +* 18 446 744 073 709 551 615 (0xFFFFFFFFFFFFFFFF) +* +* The fourth value oveflows a short BFP but fits in a long BFP. +* The fifth value oveflows both short BFP and long BFP. The +* last value also overflows both, but fits in an extended BFP. +* +* Also tests the following floating point support instructions +* LOAD (Short) +* LOAD (Long) +* LOAD FPC +* SET BFP ROUNDING MODE 2-BIT +* SET BFP ROUNDING MODE 3-BIT +* STORE (Short) +* STORE (Long) +* STORE FPC +* +*********************************************************************** + SPACE 3 + SPACE 2 + MACRO + PADCSECT &ENDLABL +.* +.* Macro to pad the CSECT to include result data areas if this test +.* program is not being assembled using asma. asma generates a core +.* image that is loaded by the loadcore command, and because the +.* core image is a binary stored in Github, it makes sense to make +.* this small effort to keep the core image small. +.* + AIF (D'&ENDLABL).GOODPAD + MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + MNOTE *,'No CSECT padding performed' + MEXIT +.* +.GOODPAD ANOP Label valid. See if we're on asma + AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + ORG &ENDLABL-1 Not ASMA. Pad CSECT + MEXIT +.* +.NOPAD ANOP + MNOTE *,'asma detected; no CSECT padding performed' + MEND +* +* Note: for compatibility with the z/CMS test rig, do not change +* or use R11, R14, or R15. Everything else is fair game. +* + SPACE 3 +BFPCVTFL START 0 +STRTLABL EQU * +R0 EQU 0 Work register for cc extraction +R1 EQU 1 +R2 EQU 2 Holds count of test input values +R3 EQU 3 Points to next test input value(s) +R4 EQU 4 Available +R5 EQU 5 Available +R6 EQU 6 Available +R7 EQU 7 Pointer to next result value(s) +R8 EQU 8 Pointer to next FPCR result +R9 EQU 9 Rounding tests top of outer loop +R10 EQU 10 Pointer to test address list +R11 EQU 11 **Reserved for z/CMS test rig +R12 EQU 12 Holds number of test cases in set +R13 EQU 13 Mainline return address +R14 EQU 14 **Return address for z/CMS test rig +R15 EQU 15 **Base register on z/CMS or Hyperion +* +* Floating Point Register equates to keep the cross reference clean +* +FPR0 EQU 0 +FPR1 EQU 1 +FPR2 EQU 2 +FPR3 EQU 3 +FPR4 EQU 4 +FPR5 EQU 5 +FPR6 EQU 6 +FPR7 EQU 7 +FPR8 EQU 8 +FPR9 EQU 9 +FPR10 EQU 10 +FPR11 EQU 11 +FPR12 EQU 12 +FPR13 EQU 13 +FPR14 EQU 14 +FPR15 EQU 15 +* + USING *,R15 +* +* Above works on real iron (R15=0 after sysclear) +* and in z/CMS (R15 points to start of load module) +* + ORG STRTLABL+X'8E' Program check interrution code +PCINTCD DS H +* +PCOLDPSW EQU STRTLABL+X'150' z/Arch Program check old PSW +* + ORG STRTLABL+X'1A0' z/Arch Restart PSW + DC X'0000000180000000',AD(START) +* + ORG STRTLABL+X'1D0' z/Arch Program check old PSW + DC X'0000000000000000',AD(PROGCHK) +* +* Program check routine. If Data Exception, continue execution at +* the instruction following the program check. Otherwise, hard wait. +* No need to collect data. All interesting DXC stuff is captured +* in the FPCR. +* + ORG STRTLABL+X'200' +PROGCHK DS 0H Program check occured... + CLI PCINTCD+1,X'07' Data Exception? + JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) + LPSWE PCOLDPSW ..yes, resume program execution +PCNOTDTA DS 0H + LTR R14,R14 Return address provided? + BNZR R14 Yes, return to z/CMS test rig. + LPSWE HARDWAIT Not data exception, enter disabled wait + EJECT +*********************************************************************** +* +* Main program. Enable Advanced Floating Point, process test cases. +* +*********************************************************************** + SPACE 2 +START STCTL R0,R0,CTLR0 Store CR0 to enable AFP + OI CTLR0+1,X'04' Turn on AFP bit + LCTL R0,R0,CTLR0 Reload updated CR0 +* + LA R10,SHORTS Point to uint-64 test inputs + BAS R13,CELGBR Convert values from fixed to short BFP + LA R10,RMSHORTS Point to inputs for rounding mode tests + BAS R13,CELGBRA Convert using all rounding mode options +* + LA R10,LONGS Point to uint-64 test inputs + BAS R13,CDLGBR Convert values from fixed to long + LA R10,RMLONGS Point to inputs for rounding mode tests + BAS R13,CDLGBRA Convert using all rounding mode options +* + LA R10,EXTDS Point to uint-64 test inputs + BAS R13,CXLGBR Convert values from fixed to extended +* +* uint-64 always fits in extended BFP exactly. No rounding nor +* loss of precision, so no need for exhaustive rounding tests +* + LTR R14,R14 Return address provided? + BNZR R14 ..Yes, return to z/CMS test rig. + LPSWE WAITPSW All done +* + DS 0D Ensure correct alignment for psw +WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end +* +CTLR0 DS F +FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags +* +* Input values parameter list, four fullwords: +* 1) Count, +* 2) Address of inputs, +* 3) Address to place results, and +* 4) Address to place DXC/Flags/cc values. +* + ORG STRTLABL+X'300' +SHORTS DS 0F + DC A(INTCOUNT/8) + DC A(INTIN) + DC A(SBFPOUT) + DC A(SBFPFLGS) +* +LONGS DS 0F uint-64 inputs for long BFP testing + DC A(INTCOUNT/8) + DC A(INTIN) + DC A(LBFPOUT) + DC A(LBFPFLGS) +* +EXTDS DS 0F uint-64 inputs for Extended BFP testing + DC A(INTCOUNT/8) + DC A(INTIN) + DC A(XBFPOUT) + DC A(XBFPFLGS) +* +RMSHORTS DC A(SINTRMCT/8) + DC A(SINTRMIN) + DC A(SBFPRMO) Space for rounding mode tests + DC A(SBFPRMOF) Space for rounding mode test flags +* +RMLONGS DC A(LINTRMCT/8) + DC A(LINTRMIN) Last two uint-64 are only concerns + DC A(LBFPRMO) Space for rounding mode tests + DC A(LBFPRMOF) Space for rounding mode test flags + EJECT +*********************************************************************** +* +* Convert integers to short BFP format. A pair of results is generated +* for each input: one with all exceptions non-trappable, and the second +* with all exceptions trappable. The FPCR is stored for each result. +* +*********************************************************************** + SPACE 2 +CELGBR LM R2,R3,0(R10) Get count and address of test input values + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + LM R7,R8,8(R10) Get address of result area and flag area. + BASR R12,0 Set top of loop +* + LG R1,0(,R3) Get integer test value + LFPC FPCREGNT Set exceptions non-trappable + CELGBR FPR8,0,R1,0 Cvt uint in GPR1 to float in FPR8 + STE FPR8,0(,R7) Store short BFP result + STFPC 0(R8) Store resulting FPC flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + CELGBR FPR8,0,R1,0 Cvt uint in GPR1 to float in FPR8 + STE FPR8,4(,R7) Store short BFP result + STFPC 4(R8) Store resulting FPC flags and DXC + LA R3,8(,R3) Point to next input values + LA R7,8(,R7) Point to next short BFP converted values + LA R8,8(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert uint-64 to short BFP format using every rounding mode. +* Ten test results are generated for each input. A 48-byte test result +* section is used to keep results sets aligned on a quad-double word. +* +* The first four tests use rounding modes specified in the FPCR with +* the IEEE Inexact exception supressed. SRNM (2-bit) is used for the +* first two FPCR-controlled tests and SRNMB (3-bit) is used for the +* last two To get full coverage of that instruction pair. +* +* The next six results use instruction-specified rounding modes. +* +* The default rounding mode (0 for RNTE) is not tested in this section; +* prior tests used the default rounding mode. RNTE is tested +* explicitly as a rounding mode in this section. +* +*********************************************************************** + SPACE 2 +CELGBRA LM R2,R3,0(R10) Get count and address of test input values + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + LM R7,R8,8(R10) Get address of result area and flag area. + BASR R12,0 Set top of loop +* + LG R1,0(,R3) Get uint-64 test value +* +* Test cases using rounding mode specified in the FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 1 SET FPC to RZ, towards zero. + CELGBR FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked + STD FPR8,0*4(,R7) Store short BFP result + STFPC 0(R8) Store resulting FPC flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 2 SET FPC to RP, to +infinity + CELGBR FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked + STD FPR8,1*4(,R7) Store short BFP result + STFPC 1*4(R8) Store resulting FPC flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 3 SET FPC to RM, to -infinity + CELGBR FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked + STD FPR8,2*4(,R7) Store short BFP result + STFPC 2*4(R8) Store resulting FPC flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 7 RFS, Prepare for Shorter Precision + CELGBR FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked + STD FPR8,3*4(,R7) Store short BFP result + STFPC 3*4(R8) Store resulting FPC flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CELGBR FPR8,1,R1,B'0000' RNTA, to nearest, ties away + STE FPR8,4*4(,R7) Store short BFP result + STFPC 4*4(R8) Store resulting FPC flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CELGBR FPR8,3,R1,B'0000' RFS, prepare for shorter precision + STE FPR8,5*4(,R7) Store short BFP result + STFPC 5*4(R8) Store resulting FPC flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CELGBR FPR8,4,R1,B'0000' RNTE, to nearest, ties to even + STE FPR8,6*4(,R7) Store short BFP result + STFPC 6*4(R8) Store resulting FPC flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CELGBR FPR8,5,R1,B'0000' RZ, toward zero + STE FPR8,7*4(,R7) Store short BFP result + STFPC 7*4(R8) Store resulting FPC flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CELGBR FPR8,6,R1,B'0000' RP, to +inf + STE FPR8,8*4(,R7) Store short BFP result + STFPC 8*4(R8) Store resulting FPC flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CELGBR FPR8,7,R1,B'0000' RM, to -inf + STE FPR8,9*4(,R7) Store short BFP result + STFPC 9*4(R8) Store resulting FPC flags and DXC +* + LA R3,8(,R3) Point to next input values + LA R7,12*4(,R7) Point to next short BFP converted values + LA R8,12*4(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert integers to long BFP format. A pair of results is generated +* for each input: one with all exceptions non-trappable, and the second +* with all exceptions trappable. The FPCR is stored for each result. +* Conversion of a 64-bit integer to long is always exact; no exceptions +* are expected +* +*********************************************************************** + SPACE 2 +CDLGBR LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LG R1,0(,R3) Get integer test value + LFPC FPCREGNT Set exceptions non-trappable + CDLGBR FPR8,0,R1,0 Cvt uint in GPR1 to float in FPR8 + STD FPR8,0(,R7) Store long BFP result + STFPC 0(R8) Store resulting FPC flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + CDLGBR FPR8,0,R1,0 Cvt uint in GPR1 to float in FPR8 + STD FPR8,8(,R7) Store long BFP result + STFPC 4(R8) Store resulting FPC flags and DXC + LA R3,8(,R3) Point to next input value + LA R7,16(,R7) Point to next long BFP result pair + LA R8,8(,R8) Point to next FPCR/CC contents pair + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert uint-64 to short BFP format using every rounding mode. +* Ten test results are generated for each input. A 48-byte test result +* section is used to keep results sets aligned on a quad-double word. +* +* The first four tests use rounding modes specified in the FPCR with +* the IEEE Inexact exception supressed. SRNM (2-bit) is used for the +* first two FPCR-controlled tests and SRNMB (3-bit) is used for the +* last two To get full coverage of that instruction pair. +* +* The next six results use instruction-specified rounding modes. +* +* The default rounding mode (0 for RNTE) is not tested in this section; +* prior tests used the default rounding mode. RNTE is tested +* explicitly as a rounding mode in this section. +* +*********************************************************************** + SPACE 2 +CDLGBRA LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LG R1,0(,R3) Get uint-64 test value +* +* Test cases using rounding mode specified in the FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 1 SET FPC to RZ, towards zero. + CDLGBR FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked + STD FPR8,0*8(,R7) Store short BFP result + STFPC 0(R8) Store resulting FPC flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 2 SET FPC to RP, to +infinity + CDLGBR FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked + STD FPR8,1*8(,R7) Store short BFP result + STFPC 1*4(R8) Store resulting FPC flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 3 SET FPC to RM, to -infinity + CDLGBR FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked + STD FPR8,2*8(,R7) Store short BFP result + STFPC 2*4(R8) Store resulting FPC flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 7 RFS, Prepare for Shorter Precision + CDLGBR FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked + STD FPR8,3*8(,R7) Store short BFP result + STFPC 3*4(R8) Store resulting FPC flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CDLGBR FPR8,1,R1,B'0000' RNTA, to nearest, ties away + STD FPR8,4*8(,R7) Store short BFP result + STFPC 4*4(R8) Store resulting FPC flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CDLGBR FPR8,3,R1,B'0000' RFS, prepare for shorter precision + STD FPR8,5*8(,R7) Store short BFP result + STFPC 5*4(R8) Store resulting FPC flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CDLGBR FPR8,4,R1,B'0000' RNTE, to nearest, ties to even + STD FPR8,6*8(,R7) Store short BFP result + STFPC 6*4(R8) Store resulting FPC flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CDLGBR FPR8,5,R1,B'0000' RZ, toward zero + STD FPR8,7*8(,R7) Store short BFP result + STFPC 7*4(R8) Store resulting FPC flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CDLGBR FPR8,6,R1,B'0000' RP, to +inf + STD FPR8,8*8(,R7) Store short BFP result + STFPC 8*4(R8) Store resulting FPC flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CDLGBR FPR8,7,R1,B'0000' RM, to -inf + STD FPR8,9*8(,R7) Store short BFP result + STFPC 9*4(R8) Store resulting FPC flags and DXC +* + LA R3,8(,R3) Point to next input values + LA R7,10*8(,R7) Point to next long BFP converted values + LA R8,12*4(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert integers to extended BFP format. A pair of results is +* generated for each input: one with all exceptions non-trappable, +* and the second with all exceptions trappable. The FPCR is +* stored for each result. Conversion of a 64-bit integer to +* extended is always exact; no exceptions are expected +* +*********************************************************************** + SPACE 2 +CXLGBR LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LG R1,0(,R3) Get integer test value + LFPC FPCREGNT Set exceptions non-trappable + CXLGBR FPR8,0,R1,0 Cvt uint in GPR1 to float in FPR8-FPR10 + STD FPR8,0(,R7) Store extended BFP result part 1 + STD FPR10,8(,R7) Store extended BFP result part 2 + STFPC 0(R8) Store resulting FPC flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + CXLGBR FPR8,0,R1,0 Cvt uint in GPR1 to float in FPR8-FPR10 + STD FPR8,16(,R7) Store extended BFP result part 1 + STD FPR10,24(,R7) Store extended BFP result part 2 + STFPC 4(R8) Store resulting FPC flags and DXC + LA R3,8(,R3) Point to next input value + LA R7,32(,R7) Point to next extended BFP result pair + LA R8,8(,R8) Point to next FPCR/CC result pair + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* long integer inputs for Convert From Fixed testing. The same set of +* inputs are used for short, long, and extended formats. The last two +* values are used for rounding mode tests for short and long only; +* conversion of uint-64 to extended is always exact. +* +*********************************************************************** + SPACE 2 +* +* int-64 inputs for basic tests +* +INTIN DS 0D + DC FD'U1' + DC FD'U2' + DC FD'U4' + DC XL8'FFFFFF0000000000' Exact long and short BFP + DC XL8'FFFFFFFFFFFFF800' Exact long BFP, inexact short bfp + DC XL8'FFFFFFFFFFFFFFFF' Inexact short & long BFP, +* ..exact extended BFP +INTCOUNT EQU *-INTIN Count of integers in list +* +* uint-64 inputs for exhaustive short BFP rounding mode tests +* +SINTRMIN DC XL8'FFFFFFC000000000' Rounds nearest up + DC XL8'FFFFFF8000000000' Tie + DC XL8'FFFFFF4000000000' Rounds nearest down + DS 0F required by asma for following EQU to work. +SINTRMCT EQU *-SINTRMIN Count of integers for rounding mode tests +* +* uint-64 inputs for exhaustive long BFP rounding mode tests +* +LINTRMIN DC XL8'FFFFFFFFFFFFFE00' Rounds nearest up + DC XL8'FFFFFFFFFFFFFC00' Tie + DC XL8'FFFFFFFFFFFFFA00' Rounds nearest down +LINTRMCT EQU *-LINTRMIN Count of integers for rounding mode tests +* +SBFPOUT EQU STRTLABL+X'1000' Short BFP values from uint-64 +* ..6 pairs used, room for 16 pairs +SBFPFLGS EQU STRTLABL+X'1100' FPCR flags and DXC from short BFP +* ..6 pairs used, room for 32 pairs +SBFPRMO EQU STRTLABL+X'1200' Short BFP rounding mode results +* ..2 sets used, room for 16 sets +SBFPRMOF EQU STRTLABL+X'1500' Short BFP rounding mode FPCR +* ..2 sets used, room for 16+ sets +* ..16 sets ends x'2A00' +* +LBFPOUT EQU STRTLABL+X'2000' Long BFP values from uint-64 +* ..6 pairs used, room for 16 pairs +LBFPFLGS EQU STRTLABL+X'2100' FPCR flags and DXC from long BFP +* ..6 pairs used, room for 32 pairs +LBFPRMO EQU STRTLABL+X'2200' Long BFP rounding mode results +* ..2 sets used, room for 16 sets +LBFPRMOF EQU STRTLABL+X'2700' Long BFP rounding mode FPCR +* ..2 sets used, room for 16+ sets +* ..16 sets ends x'2A00' +* +XBFPOUT EQU STRTLABL+X'3000' Extended BFP values from uint-64 +* ..6 pairs used, room for 16 pairs +XBFPFLGS EQU STRTLABL+X'3200' Extended BFP rounding mode FPCR +* ..6 pairs used, room for 32 pairs +* +* +ENDLABL EQU STRTLABL+X'3300' Next location available for results + PADCSECT ENDLABL + END diff --git a/tests/bfp-009-cvtfrlog64.core b/tests/bfp-009-cvtfrlog64.core new file mode 100644 index 000000000..69635fe21 Binary files /dev/null and b/tests/bfp-009-cvtfrlog64.core differ diff --git a/tests/bfp-009-cvtfrlog64.list b/tests/bfp-009-cvtfrlog64.list new file mode 100644 index 000000000..f1a2ff4dd --- /dev/null +++ b/tests/bfp-009-cvtfrlog64.list @@ -0,0 +1,733 @@ +ASMA Ver. 0.2.0 ieee-cvtfrlog64.asm: Test IEEE Convert From Fixed (uint-64) 06 Sep 2016 22:20:44 Page 1 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 2 *********************************************************************** + 3 * + 4 *Testcase IEEE CONVERT FROM LOGICAL 64 + 5 * Test case capability includes ieee exceptions trappable and otherwise. + 6 * Test result, FPC flags, and DXC saved for all tests. (Convert From + 7 * Logical does not set the condition code.) + 8 * + 9 *********************************************************************** + + + 11 *********************************************************************** + 12 * + 13 * Tests the following three conversion instructions + 14 * CONVERT FROM LOGICAL (64 to short BFP, RRF-e) + 15 * CONVERT FROM LOGICAL (64 to long BFP, RRF-e) + 16 * CONVERT FROM LOGICAL (64 to extended BFP, RRF-e) + 17 * + 18 * Limited test data is compiled into this program. The test script that runs + 19 * this program can provide alternative test data through Hercules R commands. + 20 * + 21 * Test Case Order + 22 * 1) Uint-64 to Short BFP + 23 * 2) Uint-64 to Short BFP with all rounding modes + 24 * 3) Uint-64 to Long BFP + 25 * 4) Uint-64 to Long BFP with all rounding modes + 26 * 5) Uint-64 to Extended BFP + 27 * + 28 * Provided test data is: + 29 * 1, 2, 4, + 30 * 9 007 199 254 740 991(0x001FFFFFFFFFFFFF) + 31 * 18 014 398 509 481 983(0x003FFFFFFFFFFFFF) + 32 * 18 446 744 073 709 551 615 (0xFFFFFFFFFFFFFFFF) + 33 * + 34 * The fourth value oveflows a short BFP but fits in a long BFP. + 35 * The fifth value oveflows both short BFP and long BFP. The + 36 * last value also overflows both, but fits in an extended BFP. + 37 * + 38 * Also tests the following floating point support instructions + 39 * LOAD (Short) + 40 * LOAD (Long) + 41 * LOAD FPC + 42 * SET BFP ROUNDING MODE 2-BIT + 43 * SET BFP ROUNDING MODE 3-BIT + 44 * STORE (Short) + 45 * STORE (Long) + 46 * STORE FPC + 47 * + 48 *********************************************************************** + + + + ASMA Ver. 0.2.0 ieee-cvtfrlog64.asm: Test IEEE Convert From Fixed (uint-64) 06 Sep 2016 22:20:44 Page 2 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 51 MACRO + 52 PADCSECT &ENDLABL + 53 .* + 54 .* Macro to pad the CSECT to include result data areas if this test + 55 .* program is not being assembled using asma. asma generates a core + 56 .* image that is loaded by the loadcore command, and because the + 57 .* core image is a binary stored in Github, it makes sense to make + 58 .* this small effort to keep the core image small. + 59 .* + 60 AIF (D'&ENDLABL).GOODPAD + 61 MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + 62 MNOTE *,'No CSECT padding performed' + 63 MEXIT + 64 .* + 65 .GOODPAD ANOP Label valid. See if we're on asma + 66 AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + 67 ORG &ENDLABL-1 Not ASMA. Pad CSECT + 68 MEXIT + 69 .* + 70 .NOPAD ANOP + 71 MNOTE *,'asma detected; no CSECT padding performed' + 72 MEND + 73 * + 74 * Note: for compatibility with the z/CMS test rig, do not change + 75 * or use R11, R14, or R15. Everything else is fair game. + 76 * + + + + 0000000000000000 000000000000062F 78 BFPCVTFL START 0 + 0000000000000000 0000000000000001 79 STRTLABL EQU * + 0000000000000000 0000000000000001 80 R0 EQU 0 Work register for cc extraction + 0000000000000001 0000000000000001 81 R1 EQU 1 + 0000000000000002 0000000000000001 82 R2 EQU 2 Holds count of test input values + 0000000000000003 0000000000000001 83 R3 EQU 3 Points to next test input value(s) + 0000000000000004 0000000000000001 84 R4 EQU 4 Available + 0000000000000005 0000000000000001 85 R5 EQU 5 Available + 0000000000000006 0000000000000001 86 R6 EQU 6 Available + 0000000000000007 0000000000000001 87 R7 EQU 7 Pointer to next result value(s) + 0000000000000008 0000000000000001 88 R8 EQU 8 Pointer to next FPCR result + 0000000000000009 0000000000000001 89 R9 EQU 9 Rounding tests top of outer loop + 000000000000000A 0000000000000001 90 R10 EQU 10 Pointer to test address list + 000000000000000B 0000000000000001 91 R11 EQU 11 **Reserved for z/CMS test rig + 000000000000000C 0000000000000001 92 R12 EQU 12 Holds number of test cases in set + 000000000000000D 0000000000000001 93 R13 EQU 13 Mainline return address + 000000000000000E 0000000000000001 94 R14 EQU 14 **Return address for z/CMS test rig + 000000000000000F 0000000000000001 95 R15 EQU 15 **Base register on z/CMS or Hyperion + 96 * + 97 * Floating Point Register equates to keep the cross reference clean + 98 * + 0000000000000000 0000000000000001 99 FPR0 EQU 0 + 0000000000000001 0000000000000001 100 FPR1 EQU 1 + ASMA Ver. 0.2.0 ieee-cvtfrlog64.asm: Test IEEE Convert From Fixed (uint-64) 06 Sep 2016 22:20:44 Page 3 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 0000000000000002 0000000000000001 101 FPR2 EQU 2 + 0000000000000003 0000000000000001 102 FPR3 EQU 3 + 0000000000000004 0000000000000001 103 FPR4 EQU 4 + 0000000000000005 0000000000000001 104 FPR5 EQU 5 + 0000000000000006 0000000000000001 105 FPR6 EQU 6 + 0000000000000007 0000000000000001 106 FPR7 EQU 7 + 0000000000000008 0000000000000001 107 FPR8 EQU 8 + 0000000000000009 0000000000000001 108 FPR9 EQU 9 + 000000000000000A 0000000000000001 109 FPR10 EQU 10 + 000000000000000B 0000000000000001 110 FPR11 EQU 11 + 000000000000000C 0000000000000001 111 FPR12 EQU 12 + 000000000000000D 0000000000000001 112 FPR13 EQU 13 + 000000000000000E 0000000000000001 113 FPR14 EQU 14 + 000000000000000F 0000000000000001 114 FPR15 EQU 15 + 115 * +0000000000000000 0000000000000000 116 USING *,R15 + 117 * + 118 * Above works on real iron (R15=0 after sysclear) + 119 * and in z/CMS (R15 points to start of load module) + 120 * +0000000000000000 0000000000000000 000000000000008E 121 ORG STRTLABL+X'8E' Program check interrution code +000000000000008E 0000 122 PCINTCD DS H + 123 * + 0000000000000150 0000000000000001 124 PCOLDPSW EQU STRTLABL+X'150' z/Arch Program check old PSW + 125 * +0000000000000090 0000000000000090 00000000000001A0 126 ORG STRTLABL+X'1A0' z/Arch Restart PSW +00000000000001A0 00000001 80000000 127 DC X'0000000180000000',AD(START) + 128 * +00000000000001B0 00000000000001B0 00000000000001D0 129 ORG STRTLABL+X'1D0' z/Arch Program check old PSW +00000000000001D0 00000000 00000000 130 DC X'0000000000000000',AD(PROGCHK) + 131 * + 132 * Program check routine. If Data Exception, continue execution at + 133 * the instruction following the program check. Otherwise, hard wait. + 134 * No need to collect data. All interesting DXC stuff is captured + 135 * in the FPCR. + 136 * +00000000000001E0 00000000000001E0 0000000000000200 137 ORG STRTLABL+X'200' +0000000000000200 138 PROGCHK DS 0H Program check occured... +0000000000000200 9507 F08F 000000000000008F 139 CLI PCINTCD+1,X'07' Data Exception? +0000000000000204 A774 0004 000000000000020C 140 JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) +0000000000000208 B2B2 F150 0000000000000150 141 LPSWE PCOLDPSW ..yes, resume program execution +000000000000020C 142 PCNOTDTA DS 0H +000000000000020C 12EE 143 LTR R14,R14 Return address provided? +000000000000020E 077E 144 BNZR R14 Yes, return to z/CMS test rig. +0000000000000210 B2B2 F260 0000000000000260 145 LPSWE HARDWAIT Not data exception, enter disabled wait + ASMA Ver. 0.2.0 ieee-cvtfrlog64.asm: Test IEEE Convert From Fixed (uint-64) 06 Sep 2016 22:20:44 Page 4 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 147 *********************************************************************** + 148 * + 149 * Main program. Enable Advanced Floating Point, process test cases. + 150 * + 151 *********************************************************************** + + +0000000000000214 B600 F270 0000000000000270 153 START STCTL R0,R0,CTLR0 Store CR0 to enable AFP +0000000000000218 9604 F271 0000000000000271 154 OI CTLR0+1,X'04' Turn on AFP bit +000000000000021C B700 F270 0000000000000270 155 LCTL R0,R0,CTLR0 Reload updated CR0 + 156 * +0000000000000220 41A0 F300 0000000000000300 157 LA R10,SHORTS Point to uint-64 test inputs +0000000000000224 4DD0 F350 0000000000000350 158 BAS R13,CELGBR Convert values from fixed to short BFP +0000000000000228 41A0 F330 0000000000000330 159 LA R10,RMSHORTS Point to inputs for rounding mode tests +000000000000022C 4DD0 F394 0000000000000394 160 BAS R13,CELGBRA Convert using all rounding mode options + 161 * +0000000000000230 41A0 F310 0000000000000310 162 LA R10,LONGS Point to uint-64 test inputs +0000000000000234 4DD0 F468 0000000000000468 163 BAS R13,CDLGBR Convert values from fixed to long +0000000000000238 41A0 F340 0000000000000340 164 LA R10,RMLONGS Point to inputs for rounding mode tests +000000000000023C 4DD0 F4AC 00000000000004AC 165 BAS R13,CDLGBRA Convert using all rounding mode options + 166 * +0000000000000240 41A0 F320 0000000000000320 167 LA R10,EXTDS Point to uint-64 test inputs +0000000000000244 4DD0 F580 0000000000000580 168 BAS R13,CXLGBR Convert values from fixed to extended + 169 * + 170 * uint-64 always fits in extended BFP exactly. No rounding nor + 171 * loss of precision, so no need for exhaustive rounding tests + 172 * +0000000000000248 12EE 173 LTR R14,R14 Return address provided? +000000000000024A 077E 174 BNZR R14 ..Yes, return to z/CMS test rig. +000000000000024C B2B2 F250 0000000000000250 175 LPSWE WAITPSW All done + 176 * +0000000000000250 177 DS 0D Ensure correct alignment for psw +0000000000000250 00020000 00000000 178 WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +0000000000000260 00020000 00000000 179 HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end + 180 * +0000000000000270 00000000 181 CTLR0 DS F +0000000000000274 00000000 182 FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +0000000000000278 F8000000 183 FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags + 184 * + 185 * Input values parameter list, four fullwords: + 186 * 1) Count, + 187 * 2) Address of inputs, + 188 * 3) Address to place results, and + 189 * 4) Address to place DXC/Flags/cc values. + 190 * +000000000000027C 000000000000027C 0000000000000300 191 ORG STRTLABL+X'300' +0000000000000300 192 SHORTS DS 0F +0000000000000300 00000006 193 DC A(INTCOUNT/8) +0000000000000304 000005D0 194 DC A(INTIN) +0000000000000308 00001000 195 DC A(SBFPOUT) +000000000000030C 00001100 196 DC A(SBFPFLGS) + 197 * + ASMA Ver. 0.2.0 ieee-cvtfrlog64.asm: Test IEEE Convert From Fixed (uint-64) 06 Sep 2016 22:20:44 Page 5 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000310 198 LONGS DS 0F uint-64 inputs for long BFP testing +0000000000000310 00000006 199 DC A(INTCOUNT/8) +0000000000000314 000005D0 200 DC A(INTIN) +0000000000000318 00002000 201 DC A(LBFPOUT) +000000000000031C 00002100 202 DC A(LBFPFLGS) + 203 * +0000000000000320 204 EXTDS DS 0F uint-64 inputs for Extended BFP testing +0000000000000320 00000006 205 DC A(INTCOUNT/8) +0000000000000324 000005D0 206 DC A(INTIN) +0000000000000328 00003000 207 DC A(XBFPOUT) +000000000000032C 00003200 208 DC A(XBFPFLGS) + 209 * +0000000000000330 00000003 210 RMSHORTS DC A(SINTRMCT/8) +0000000000000334 00000600 211 DC A(SINTRMIN) +0000000000000338 00001200 212 DC A(SBFPRMO) Space for rounding mode tests +000000000000033C 00001500 213 DC A(SBFPRMOF) Space for rounding mode test flags + 214 * +0000000000000340 00000003 215 RMLONGS DC A(LINTRMCT/8) +0000000000000344 00000618 216 DC A(LINTRMIN) Last two uint-64 are only concerns +0000000000000348 00002200 217 DC A(LBFPRMO) Space for rounding mode tests +000000000000034C 00002700 218 DC A(LBFPRMOF) Space for rounding mode test flags + ASMA Ver. 0.2.0 ieee-cvtfrlog64.asm: Test IEEE Convert From Fixed (uint-64) 06 Sep 2016 22:20:44 Page 6 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 220 *********************************************************************** + 221 * + 222 * Convert integers to short BFP format. A pair of results is generated + 223 * for each input: one with all exceptions non-trappable, and the second + 224 * with all exceptions trappable. The FPCR is stored for each result. + 225 * + 226 *********************************************************************** + + +0000000000000350 9823 A000 0000000000000000 228 CELGBR LM R2,R3,0(R10) Get count and address of test input values +0000000000000354 1222 229 LTR R2,R2 Any test cases? +0000000000000356 078D 230 BZR R13 ..No, return to caller +0000000000000358 9878 A008 0000000000000008 231 LM R7,R8,8(R10) Get address of result area and flag area. +000000000000035C 0DC0 232 BASR R12,0 Set top of loop + 233 * +000000000000035E E310 3000 0004 0000000000000000 234 LG R1,0(,R3) Get integer test value +0000000000000364 B29D F274 0000000000000274 235 LFPC FPCREGNT Set exceptions non-trappable +0000000000000368 B3A0 0081 236 CELGBR FPR8,0,R1,0 Cvt uint in GPR1 to float in FPR8 +000000000000036C 7080 7000 0000000000000000 237 STE FPR8,0(,R7) Store short BFP result +0000000000000370 B29C 8000 0000000000000000 238 STFPC 0(R8) Store resulting FPC flags and DXC + 239 * +0000000000000374 B29D F278 0000000000000278 240 LFPC FPCREGTR Set exceptions trappable +0000000000000378 B3A0 0081 241 CELGBR FPR8,0,R1,0 Cvt uint in GPR1 to float in FPR8 +000000000000037C 7080 7004 0000000000000004 242 STE FPR8,4(,R7) Store short BFP result +0000000000000380 B29C 8004 0000000000000004 243 STFPC 4(R8) Store resulting FPC flags and DXC +0000000000000384 4130 3008 0000000000000008 244 LA R3,8(,R3) Point to next input values +0000000000000388 4170 7008 0000000000000008 245 LA R7,8(,R7) Point to next short BFP converted values +000000000000038C 4180 8008 0000000000000008 246 LA R8,8(,R8) Point to next FPCR/CC result area +0000000000000390 062C 247 BCTR R2,R12 Convert next input value. +0000000000000392 07FD 248 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvtfrlog64.asm: Test IEEE Convert From Fixed (uint-64) 06 Sep 2016 22:20:44 Page 7 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 250 *********************************************************************** + 251 * + 252 * Convert uint-64 to short BFP format using every rounding mode. + 253 * Ten test results are generated for each input. A 48-byte test result + 254 * section is used to keep results sets aligned on a quad-double word. + 255 * + 256 * The first four tests use rounding modes specified in the FPCR with + 257 * the IEEE Inexact exception supressed. SRNM (2-bit) is used for the + 258 * first two FPCR-controlled tests and SRNMB (3-bit) is used for the + 259 * last two To get full coverage of that instruction pair. + 260 * + 261 * The next six results use instruction-specified rounding modes. + 262 * + 263 * The default rounding mode (0 for RNTE) is not tested in this section; + 264 * prior tests used the default rounding mode. RNTE is tested + 265 * explicitly as a rounding mode in this section. + 266 * + 267 *********************************************************************** + + +0000000000000394 9823 A000 0000000000000000 269 CELGBRA LM R2,R3,0(R10) Get count and address of test input values +0000000000000398 1222 270 LTR R2,R2 Any test cases? +000000000000039A 078D 271 BZR R13 ..No, return to caller +000000000000039C 9878 A008 0000000000000008 272 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000003A0 0DC0 273 BASR R12,0 Set top of loop + 274 * +00000000000003A2 E310 3000 0004 0000000000000000 275 LG R1,0(,R3) Get uint-64 test value + 276 * + 277 * Test cases using rounding mode specified in the FPCR + 278 * +00000000000003A8 B29D F274 0000000000000274 279 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000003AC B2B8 0001 0000000000000001 280 SRNMB 1 SET FPC to RZ, towards zero. +00000000000003B0 B3A0 0481 281 CELGBR FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked +00000000000003B4 6080 7000 0000000000000000 282 STD FPR8,0*4(,R7) Store short BFP result +00000000000003B8 B29C 8000 0000000000000000 283 STFPC 0(R8) Store resulting FPC flags and DXC + 284 * +00000000000003BC B29D F274 0000000000000274 285 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000003C0 B2B8 0002 0000000000000002 286 SRNMB 2 SET FPC to RP, to +infinity +00000000000003C4 B3A0 0481 287 CELGBR FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked +00000000000003C8 6080 7004 0000000000000004 288 STD FPR8,1*4(,R7) Store short BFP result +00000000000003CC B29C 8004 0000000000000004 289 STFPC 1*4(R8) Store resulting FPC flags and DXC + 290 * +00000000000003D0 B29D F274 0000000000000274 291 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000003D4 B2B8 0003 0000000000000003 292 SRNMB 3 SET FPC to RM, to -infinity +00000000000003D8 B3A0 0481 293 CELGBR FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked +00000000000003DC 6080 7008 0000000000000008 294 STD FPR8,2*4(,R7) Store short BFP result +00000000000003E0 B29C 8008 0000000000000008 295 STFPC 2*4(R8) Store resulting FPC flags and DXC + 296 * +00000000000003E4 B29D F274 0000000000000274 297 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000003E8 B2B8 0007 0000000000000007 298 SRNMB 7 RFS, Prepare for Shorter Precision +00000000000003EC B3A0 0481 299 CELGBR FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked +00000000000003F0 6080 700C 000000000000000C 300 STD FPR8,3*4(,R7) Store short BFP result + ASMA Ver. 0.2.0 ieee-cvtfrlog64.asm: Test IEEE Convert From Fixed (uint-64) 06 Sep 2016 22:20:44 Page 8 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000003F4 B29C 800C 000000000000000C 301 STFPC 3*4(R8) Store resulting FPC flags and DXC + 302 * +00000000000003F8 B29D F274 0000000000000274 303 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000003FC B3A0 1081 304 CELGBR FPR8,1,R1,B'0000' RNTA, to nearest, ties away +0000000000000400 7080 7010 0000000000000010 305 STE FPR8,4*4(,R7) Store short BFP result +0000000000000404 B29C 8010 0000000000000010 306 STFPC 4*4(R8) Store resulting FPC flags and DXC + 307 * +0000000000000408 B29D F274 0000000000000274 308 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000040C B3A0 3081 309 CELGBR FPR8,3,R1,B'0000' RFS, prepare for shorter precision +0000000000000410 7080 7014 0000000000000014 310 STE FPR8,5*4(,R7) Store short BFP result +0000000000000414 B29C 8014 0000000000000014 311 STFPC 5*4(R8) Store resulting FPC flags and DXC + 312 * +0000000000000418 B29D F274 0000000000000274 313 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000041C B3A0 4081 314 CELGBR FPR8,4,R1,B'0000' RNTE, to nearest, ties to even +0000000000000420 7080 7018 0000000000000018 315 STE FPR8,6*4(,R7) Store short BFP result +0000000000000424 B29C 8018 0000000000000018 316 STFPC 6*4(R8) Store resulting FPC flags and DXC + 317 * +0000000000000428 B29D F274 0000000000000274 318 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000042C B3A0 5081 319 CELGBR FPR8,5,R1,B'0000' RZ, toward zero +0000000000000430 7080 701C 000000000000001C 320 STE FPR8,7*4(,R7) Store short BFP result +0000000000000434 B29C 801C 000000000000001C 321 STFPC 7*4(R8) Store resulting FPC flags and DXC + 322 * +0000000000000438 B29D F274 0000000000000274 323 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000043C B3A0 6081 324 CELGBR FPR8,6,R1,B'0000' RP, to +inf +0000000000000440 7080 7020 0000000000000020 325 STE FPR8,8*4(,R7) Store short BFP result +0000000000000444 B29C 8020 0000000000000020 326 STFPC 8*4(R8) Store resulting FPC flags and DXC + 327 * +0000000000000448 B29D F274 0000000000000274 328 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000044C B3A0 7081 329 CELGBR FPR8,7,R1,B'0000' RM, to -inf +0000000000000450 7080 7024 0000000000000024 330 STE FPR8,9*4(,R7) Store short BFP result +0000000000000454 B29C 8024 0000000000000024 331 STFPC 9*4(R8) Store resulting FPC flags and DXC + 332 * +0000000000000458 4130 3008 0000000000000008 333 LA R3,8(,R3) Point to next input values +000000000000045C 4170 7030 0000000000000030 334 LA R7,12*4(,R7) Point to next short BFP converted values +0000000000000460 4180 8030 0000000000000030 335 LA R8,12*4(,R8) Point to next FPCR/CC result area +0000000000000464 062C 336 BCTR R2,R12 Convert next input value. +0000000000000466 07FD 337 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvtfrlog64.asm: Test IEEE Convert From Fixed (uint-64) 06 Sep 2016 22:20:44 Page 9 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 339 *********************************************************************** + 340 * + 341 * Convert integers to long BFP format. A pair of results is generated + 342 * for each input: one with all exceptions non-trappable, and the second + 343 * with all exceptions trappable. The FPCR is stored for each result. + 344 * Conversion of a 64-bit integer to long is always exact; no exceptions + 345 * are expected + 346 * + 347 *********************************************************************** + + +0000000000000468 9823 A000 0000000000000000 349 CDLGBR LM R2,R3,0(R10) Get count and address of test input values +000000000000046C 9878 A008 0000000000000008 350 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000470 1222 351 LTR R2,R2 Any test cases? +0000000000000472 078D 352 BZR R13 ..No, return to caller +0000000000000474 0DC0 353 BASR R12,0 Set top of loop + 354 * +0000000000000476 E310 3000 0004 0000000000000000 355 LG R1,0(,R3) Get integer test value +000000000000047C B29D F274 0000000000000274 356 LFPC FPCREGNT Set exceptions non-trappable +0000000000000480 B3A1 0081 357 CDLGBR FPR8,0,R1,0 Cvt uint in GPR1 to float in FPR8 +0000000000000484 6080 7000 0000000000000000 358 STD FPR8,0(,R7) Store long BFP result +0000000000000488 B29C 8000 0000000000000000 359 STFPC 0(R8) Store resulting FPC flags and DXC + 360 * +000000000000048C B29D F278 0000000000000278 361 LFPC FPCREGTR Set exceptions trappable +0000000000000490 B3A1 0081 362 CDLGBR FPR8,0,R1,0 Cvt uint in GPR1 to float in FPR8 +0000000000000494 6080 7008 0000000000000008 363 STD FPR8,8(,R7) Store long BFP result +0000000000000498 B29C 8004 0000000000000004 364 STFPC 4(R8) Store resulting FPC flags and DXC +000000000000049C 4130 3008 0000000000000008 365 LA R3,8(,R3) Point to next input value +00000000000004A0 4170 7010 0000000000000010 366 LA R7,16(,R7) Point to next long BFP result pair +00000000000004A4 4180 8008 0000000000000008 367 LA R8,8(,R8) Point to next FPCR/CC contents pair +00000000000004A8 062C 368 BCTR R2,R12 Convert next input value. +00000000000004AA 07FD 369 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvtfrlog64.asm: Test IEEE Convert From Fixed (uint-64) 06 Sep 2016 22:20:44 Page 10 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 371 *********************************************************************** + 372 * + 373 * Convert uint-64 to short BFP format using every rounding mode. + 374 * Ten test results are generated for each input. A 48-byte test result + 375 * section is used to keep results sets aligned on a quad-double word. + 376 * + 377 * The first four tests use rounding modes specified in the FPCR with + 378 * the IEEE Inexact exception supressed. SRNM (2-bit) is used for the + 379 * first two FPCR-controlled tests and SRNMB (3-bit) is used for the + 380 * last two To get full coverage of that instruction pair. + 381 * + 382 * The next six results use instruction-specified rounding modes. + 383 * + 384 * The default rounding mode (0 for RNTE) is not tested in this section; + 385 * prior tests used the default rounding mode. RNTE is tested + 386 * explicitly as a rounding mode in this section. + 387 * + 388 *********************************************************************** + + +00000000000004AC 9823 A000 0000000000000000 390 CDLGBRA LM R2,R3,0(R10) Get count and address of test input values +00000000000004B0 9878 A008 0000000000000008 391 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000004B4 1222 392 LTR R2,R2 Any test cases? +00000000000004B6 078D 393 BZR R13 ..No, return to caller +00000000000004B8 0DC0 394 BASR R12,0 Set top of loop + 395 * +00000000000004BA E310 3000 0004 0000000000000000 396 LG R1,0(,R3) Get uint-64 test value + 397 * + 398 * Test cases using rounding mode specified in the FPCR + 399 * +00000000000004C0 B29D F274 0000000000000274 400 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000004C4 B2B8 0001 0000000000000001 401 SRNMB 1 SET FPC to RZ, towards zero. +00000000000004C8 B3A1 0481 402 CDLGBR FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked +00000000000004CC 6080 7000 0000000000000000 403 STD FPR8,0*8(,R7) Store short BFP result +00000000000004D0 B29C 8000 0000000000000000 404 STFPC 0(R8) Store resulting FPC flags and DXC + 405 * +00000000000004D4 B29D F274 0000000000000274 406 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000004D8 B2B8 0002 0000000000000002 407 SRNMB 2 SET FPC to RP, to +infinity +00000000000004DC B3A1 0481 408 CDLGBR FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked +00000000000004E0 6080 7008 0000000000000008 409 STD FPR8,1*8(,R7) Store short BFP result +00000000000004E4 B29C 8004 0000000000000004 410 STFPC 1*4(R8) Store resulting FPC flags and DXC + 411 * +00000000000004E8 B29D F274 0000000000000274 412 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000004EC B2B8 0003 0000000000000003 413 SRNMB 3 SET FPC to RM, to -infinity +00000000000004F0 B3A1 0481 414 CDLGBR FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked +00000000000004F4 6080 7010 0000000000000010 415 STD FPR8,2*8(,R7) Store short BFP result +00000000000004F8 B29C 8008 0000000000000008 416 STFPC 2*4(R8) Store resulting FPC flags and DXC + 417 * +00000000000004FC B29D F274 0000000000000274 418 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000500 B2B8 0007 0000000000000007 419 SRNMB 7 RFS, Prepare for Shorter Precision +0000000000000504 B3A1 0481 420 CDLGBR FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked +0000000000000508 6080 7018 0000000000000018 421 STD FPR8,3*8(,R7) Store short BFP result + ASMA Ver. 0.2.0 ieee-cvtfrlog64.asm: Test IEEE Convert From Fixed (uint-64) 06 Sep 2016 22:20:44 Page 11 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +000000000000050C B29C 800C 000000000000000C 422 STFPC 3*4(R8) Store resulting FPC flags and DXC + 423 * +0000000000000510 B29D F274 0000000000000274 424 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000514 B3A1 1081 425 CDLGBR FPR8,1,R1,B'0000' RNTA, to nearest, ties away +0000000000000518 6080 7020 0000000000000020 426 STD FPR8,4*8(,R7) Store short BFP result +000000000000051C B29C 8010 0000000000000010 427 STFPC 4*4(R8) Store resulting FPC flags and DXC + 428 * +0000000000000520 B29D F274 0000000000000274 429 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000524 B3A1 3081 430 CDLGBR FPR8,3,R1,B'0000' RFS, prepare for shorter precision +0000000000000528 6080 7028 0000000000000028 431 STD FPR8,5*8(,R7) Store short BFP result +000000000000052C B29C 8014 0000000000000014 432 STFPC 5*4(R8) Store resulting FPC flags and DXC + 433 * +0000000000000530 B29D F274 0000000000000274 434 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000534 B3A1 4081 435 CDLGBR FPR8,4,R1,B'0000' RNTE, to nearest, ties to even +0000000000000538 6080 7030 0000000000000030 436 STD FPR8,6*8(,R7) Store short BFP result +000000000000053C B29C 8018 0000000000000018 437 STFPC 6*4(R8) Store resulting FPC flags and DXC + 438 * +0000000000000540 B29D F274 0000000000000274 439 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000544 B3A1 5081 440 CDLGBR FPR8,5,R1,B'0000' RZ, toward zero +0000000000000548 6080 7038 0000000000000038 441 STD FPR8,7*8(,R7) Store short BFP result +000000000000054C B29C 801C 000000000000001C 442 STFPC 7*4(R8) Store resulting FPC flags and DXC + 443 * +0000000000000550 B29D F274 0000000000000274 444 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000554 B3A1 6081 445 CDLGBR FPR8,6,R1,B'0000' RP, to +inf +0000000000000558 6080 7040 0000000000000040 446 STD FPR8,8*8(,R7) Store short BFP result +000000000000055C B29C 8020 0000000000000020 447 STFPC 8*4(R8) Store resulting FPC flags and DXC + 448 * +0000000000000560 B29D F274 0000000000000274 449 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000564 B3A1 7081 450 CDLGBR FPR8,7,R1,B'0000' RM, to -inf +0000000000000568 6080 7048 0000000000000048 451 STD FPR8,9*8(,R7) Store short BFP result +000000000000056C B29C 8024 0000000000000024 452 STFPC 9*4(R8) Store resulting FPC flags and DXC + 453 * +0000000000000570 4130 3008 0000000000000008 454 LA R3,8(,R3) Point to next input values +0000000000000574 4170 7050 0000000000000050 455 LA R7,10*8(,R7) Point to next long BFP converted values +0000000000000578 4180 8030 0000000000000030 456 LA R8,12*4(,R8) Point to next FPCR/CC result area +000000000000057C 062C 457 BCTR R2,R12 Convert next input value. +000000000000057E 07FD 458 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvtfrlog64.asm: Test IEEE Convert From Fixed (uint-64) 06 Sep 2016 22:20:44 Page 12 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 460 *********************************************************************** + 461 * + 462 * Convert integers to extended BFP format. A pair of results is + 463 * generated for each input: one with all exceptions non-trappable, + 464 * and the second with all exceptions trappable. The FPCR is + 465 * stored for each result. Conversion of a 64-bit integer to + 466 * extended is always exact; no exceptions are expected + 467 * + 468 *********************************************************************** + + +0000000000000580 9823 A000 0000000000000000 470 CXLGBR LM R2,R3,0(R10) Get count and address of test input values +0000000000000584 9878 A008 0000000000000008 471 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000588 1222 472 LTR R2,R2 Any test cases? +000000000000058A 078D 473 BZR R13 ..No, return to caller +000000000000058C 0DC0 474 BASR R12,0 Set top of loop + 475 * +000000000000058E E310 3000 0004 0000000000000000 476 LG R1,0(,R3) Get integer test value +0000000000000594 B29D F274 0000000000000274 477 LFPC FPCREGNT Set exceptions non-trappable +0000000000000598 B3A2 0081 478 CXLGBR FPR8,0,R1,0 Cvt uint in GPR1 to float in FPR8-FPR10 +000000000000059C 6080 7000 0000000000000000 479 STD FPR8,0(,R7) Store extended BFP result part 1 +00000000000005A0 60A0 7008 0000000000000008 480 STD FPR10,8(,R7) Store extended BFP result part 2 +00000000000005A4 B29C 8000 0000000000000000 481 STFPC 0(R8) Store resulting FPC flags and DXC + 482 * +00000000000005A8 B29D F278 0000000000000278 483 LFPC FPCREGTR Set exceptions trappable +00000000000005AC B3A2 0081 484 CXLGBR FPR8,0,R1,0 Cvt uint in GPR1 to float in FPR8-FPR10 +00000000000005B0 6080 7010 0000000000000010 485 STD FPR8,16(,R7) Store extended BFP result part 1 +00000000000005B4 60A0 7018 0000000000000018 486 STD FPR10,24(,R7) Store extended BFP result part 2 +00000000000005B8 B29C 8004 0000000000000004 487 STFPC 4(R8) Store resulting FPC flags and DXC +00000000000005BC 4130 3008 0000000000000008 488 LA R3,8(,R3) Point to next input value +00000000000005C0 4170 7020 0000000000000020 489 LA R7,32(,R7) Point to next extended BFP result pair +00000000000005C4 4180 8008 0000000000000008 490 LA R8,8(,R8) Point to next FPCR/CC result pair +00000000000005C8 062C 491 BCTR R2,R12 Convert next input value. +00000000000005CA 07FD 492 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvtfrlog64.asm: Test IEEE Convert From Fixed (uint-64) 06 Sep 2016 22:20:44 Page 13 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 494 *********************************************************************** + 495 * + 496 * long integer inputs for Convert From Fixed testing. The same set of + 497 * inputs are used for short, long, and extended formats. The last two + 498 * values are used for rounding mode tests for short and long only; + 499 * conversion of uint-64 to extended is always exact. + 500 * + 501 *********************************************************************** + + + 503 * + 504 * int-64 inputs for basic tests + 505 * +00000000000005D0 506 INTIN DS 0D +00000000000005D0 00000000 00000001 507 DC FD'U1' +00000000000005D8 00000000 00000002 508 DC FD'U2' +00000000000005E0 00000000 00000004 509 DC FD'U4' +00000000000005E8 FFFFFF00 00000000 510 DC XL8'FFFFFF0000000000' Exact long and short BFP +00000000000005F0 FFFFFFFF FFFFF800 511 DC XL8'FFFFFFFFFFFFF800' Exact long BFP, inexact short bfp +00000000000005F8 FFFFFFFF FFFFFFFF 512 DC XL8'FFFFFFFFFFFFFFFF' Inexact short & long BFP, + 513 * ..exact extended BFP + 0000000000000030 0000000000000001 514 INTCOUNT EQU *-INTIN Count of integers in list + 515 * + 516 * int-64 inputs for exhaustive short BFP rounding mode tests + 517 * +0000000000000600 FFFFFFC0 00000000 518 SINTRMIN DC XL8'FFFFFFC000000000' Rounds nearest up +0000000000000608 FFFFFF80 00000000 519 DC XL8'FFFFFF8000000000' Tie +0000000000000610 FFFFFF40 00000000 520 DC XL8'FFFFFF4000000000' Rounds nearest down +0000000000000618 521 DS 0F required by asma for following EQU to work. + 0000000000000018 0000000000000001 522 SINTRMCT EQU *-SINTRMIN Count of integers for rounding mode tests + 523 * + 524 * int-64 inputs for exhaustive long BFP rounding mode tests + 525 * +0000000000000618 FFFFFFFF FFFFFE00 526 LINTRMIN DC XL8'FFFFFFFFFFFFFE00' Exact/inexact based on rounding +0000000000000620 FFFFFFFF FFFFFC00 527 DC XL8'FFFFFFFFFFFFFC00' Exact/inexact based on rounding +0000000000000628 FFFFFFFF FFFFFA00 528 DC XL8'FFFFFFFFFFFFFA00' Exact/inexact based on rounding + 0000000000000018 0000000000000001 529 LINTRMCT EQU *-LINTRMIN Count of integers for rounding mode tests + 530 * + 0000000000001000 0000000000000001 531 SBFPOUT EQU STRTLABL+X'1000' Short BFP values from uint-64 + 532 * ..6 pairs used, room for 16 pairs + 0000000000001100 0000000000000001 533 SBFPFLGS EQU STRTLABL+X'1100' FPCR flags and DXC from short BFP + 534 * ..6 pairs used, room for 32 pairs + 0000000000001200 0000000000000001 535 SBFPRMO EQU STRTLABL+X'1200' Short BFP rounding mode results + 536 * ..2 sets used, room for 16 sets + 0000000000001500 0000000000000001 537 SBFPRMOF EQU STRTLABL+X'1500' Short BFP rounding mode FPCR + 538 * ..2 sets used, room for 16+ sets + 539 * ..16 sets ends x'2A00' + 540 * + 0000000000002000 0000000000000001 541 LBFPOUT EQU STRTLABL+X'2000' Long BFP values from uint-64 + 542 * ..6 pairs used, room for 16 pairs + 0000000000002100 0000000000000001 543 LBFPFLGS EQU STRTLABL+X'2100' FPCR flags and DXC from long BFP + 544 * ..6 pairs used, room for 32 pairs + ASMA Ver. 0.2.0 ieee-cvtfrlog64.asm: Test IEEE Convert From Fixed (uint-64) 06 Sep 2016 22:20:44 Page 14 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 0000000000002200 0000000000000001 545 LBFPRMO EQU STRTLABL+X'2200' Long BFP rounding mode results + 546 * ..2 sets used, room for 16 sets + 0000000000002700 0000000000000001 547 LBFPRMOF EQU STRTLABL+X'2700' Long BFP rounding mode FPCR + 548 * ..2 sets used, room for 16+ sets + 549 * ..16 sets ends x'2A00' + 550 * + 0000000000003000 0000000000000001 551 XBFPOUT EQU STRTLABL+X'3000' Extended BFP values from uint-64 + 552 * ..6 pairs used, room for 16 pairs + 0000000000003200 0000000000000001 553 XBFPFLGS EQU STRTLABL+X'3200' Extended BFP rounding mode FPCR + 554 * ..6 pairs used, room for 32 pairs + 555 * + 556 * + 0000000000003300 0000000000000001 557 ENDLABL EQU STRTLABL+X'3300' Next location available for results + 558 PADCSECT ENDLABL + 559+ MNOTE *,'asma detected; no CSECT padding performed' +0000000000000630 560 END + ASMA Ver. 0.2.0 ieee-cvtfrlog64.asm: Test IEEE Convert From Fixed (uint-64) 06 Sep 2016 22:20:44 Page 15 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +BFPCVTFL J 000000 1584 78 +CDLGBR I 000468 4 349 163 +CDLGBRA I 0004AC 4 390 165 +CELGBR I 000350 4 228 158 +CELGBRA I 000394 4 269 160 +CTLR0 F 000270 4 181 153 154 155 +CXLGBR I 000580 4 470 168 +ENDLABL U 003300 1 557 +EXTDS F 000320 4 204 167 +FPCREGNT X 000274 4 182 235 279 285 291 297 303 308 313 318 323 328 356 400 406 412 418 424 + 429 434 439 444 449 477 +FPCREGTR X 000278 4 183 240 361 483 +FPR0 U 000000 1 99 +FPR1 U 000001 1 100 +FPR10 U 00000A 1 109 480 486 +FPR11 U 00000B 1 110 +FPR12 U 00000C 1 111 +FPR13 U 00000D 1 112 +FPR14 U 00000E 1 113 +FPR15 U 00000F 1 114 +FPR2 U 000002 1 101 +FPR3 U 000003 1 102 +FPR4 U 000004 1 103 +FPR5 U 000005 1 104 +FPR6 U 000006 1 105 +FPR7 U 000007 1 106 +FPR8 U 000008 1 107 236 237 241 242 281 282 287 288 293 294 299 300 304 305 309 310 314 + 315 319 320 324 325 329 330 357 358 362 363 402 403 408 409 414 415 + 420 421 425 426 430 431 435 436 440 441 445 446 450 451 478 479 484 + 485 +FPR9 U 000009 1 108 +HARDWAIT X 000260 8 179 145 +IMAGE 1 000000 1584 0 +INTCOUNT U 000030 1 514 193 199 205 +INTIN D 0005D0 8 506 514 194 200 206 +LBFPFLGS U 002100 1 543 202 +LBFPOUT U 002000 1 541 201 +LBFPRMO U 002200 1 545 217 +LBFPRMOF U 002700 1 547 218 +LINTRMCT U 000018 1 529 215 +LINTRMIN X 000618 8 526 529 216 +LONGS F 000310 4 198 162 +PCINTCD H 00008E 2 122 139 +PCNOTDTA H 00020C 2 142 140 +PCOLDPSW U 000150 1 124 141 +PROGCHK H 000200 2 138 130 +R0 U 000000 1 80 153 155 +R1 U 000001 1 81 234 236 241 275 281 287 293 299 304 309 314 319 324 329 355 357 362 + 396 402 408 414 420 425 430 435 440 445 450 476 478 484 +R10 U 00000A 1 90 157 159 162 164 167 228 231 269 272 349 350 390 391 470 471 +R11 U 00000B 1 91 +R12 U 00000C 1 92 232 247 273 336 353 368 394 457 474 491 + ASMA Ver. 0.2.0 ieee-cvtfrlog64.asm: Test IEEE Convert From Fixed (uint-64) 06 Sep 2016 22:20:44 Page 16 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +R13 U 00000D 1 93 158 160 163 165 168 230 248 271 337 352 369 393 458 473 492 +R14 U 00000E 1 94 143 144 173 174 +R15 U 00000F 1 95 116 +R2 U 000002 1 82 228 229 247 269 270 336 349 351 368 390 392 457 470 472 491 +R3 U 000003 1 83 228 234 244 269 275 333 349 355 365 390 396 454 470 476 488 +R4 U 000004 1 84 +R5 U 000005 1 85 +R6 U 000006 1 86 +R7 U 000007 1 87 231 237 242 245 272 282 288 294 300 305 310 315 320 325 330 334 350 + 358 363 366 391 403 409 415 421 426 431 436 441 446 451 455 471 479 + 480 485 486 489 +R8 U 000008 1 88 231 238 243 246 272 283 289 295 301 306 311 316 321 326 331 335 350 + 359 364 367 391 404 410 416 422 427 432 437 442 447 452 456 471 481 + 487 490 +R9 U 000009 1 89 +RMLONGS A 000340 4 215 164 +RMSHORTS A 000330 4 210 159 +SBFPFLGS U 001100 1 533 196 +SBFPOUT U 001000 1 531 195 +SBFPRMO U 001200 1 535 212 +SBFPRMOF U 001500 1 537 213 +SHORTS F 000300 4 192 157 +SINTRMCT U 000018 1 522 210 +SINTRMIN X 000600 8 518 522 211 +START I 000214 4 153 127 +STRTLABL U 000000 1 79 121 124 126 129 137 191 531 533 535 537 541 543 545 547 551 553 557 +WAITPSW X 000250 8 178 175 +XBFPFLGS U 003200 1 553 208 +XBFPOUT U 003000 1 551 207 + ASMA Ver. 0.2.0 ieee-cvtfrlog64.asm: Test IEEE Convert From Fixed (uint-64) 06 Sep 2016 22:20:44 Page 17 + + MACRO DEFN REFERENCES + +PADCSECT 52 558 + ASMA Ver. 0.2.0 ieee-cvtfrlog64.asm: Test IEEE Convert From Fixed (uint-64) 06 Sep 2016 22:20:44 Page 18 + + DESC SYMBOL SIZE POS ADDR + +Entry: 0 + +Image IMAGE 1584 000-62F 000-62F + Region 1584 000-62F 000-62F + CSECT BFPCVTFL 1584 000-62F 000-62F + ASMA Ver. 0.2.0 ieee-cvtfrlog64.asm: Test IEEE Convert From Fixed (uint-64) 06 Sep 2016 22:20:44 Page 19 + + STMT FILE NAME + +1 C:\Users\srorso\Documents\GitHub\hyperion\tests\bfp-009-cvtfrlog64.asm + + +** NO ERRORS FOUND ** + +[559] MNOTE *,asma detected; no CSECT padding performed + \ No newline at end of file diff --git a/tests/bfp-009-cvtfrlog64.tst b/tests/bfp-009-cvtfrlog64.tst new file mode 100644 index 000000000..013315d10 --- /dev/null +++ b/tests/bfp-009-cvtfrlog64.tst @@ -0,0 +1,212 @@ +*Testcase bfp-009-cvtfrlog64.tst: CELGBR, CDLGBR, CXLGBR + +#Testcase bfp-009-cvtfrlog64.tst: IEEE Convert From Logical (64-bit) +#..Includes CONVERT FROM LOGICAL 64 (3). Also tests traps and +#..exceptions and results from different rounding modes. + +sysclear +archmode esame + +# +# Following suppresses logging of program checks. This test program, as part +# of its normal operation, generates 3 program check messages that have no +# value in the validation process. (The messages, not the program checks.) +# +ostailor quiet + +loadcore "$(testpath)/bfp-009-cvtfrlog64.core" + +runtest 1.0 + +ostailor null # restore messages for subsequent tests + + +# Inputs converted to BFP Short - Results +*Compare +r 1000.10 +*Want "CELGBR result pairs 1-2" 3F800000 3F800000 40000000 40000000 +r 1010.10 +*Want "CELGBR result pairs 3-4" 40800000 40800000 5F7FFFFF 5F7FFFFF +r 1020.10 +*Want "CELGBR result pairs 5-6" 5F800000 5F800000 5F800000 5F800000 + +# Inputs converted to BFP short FPCR Contents +r 1100.10 +*Want "CELGBR FPC pairs 1-2" 00000000 F8000000 00000000 F8000000 +r 1110.10 +*Want "CELGBR FPC pairs 3-4" 00000000 F8000000 00000000 F8000000 +r 1120.10 +*Want "CELGBR FPC pairs 5-6" 00080000 F8000C00 00080000 F8000C00 + + +# Inputs converted to BFP short rounding mode test results +*Compare +r 1200.10 +*Want "CELGBR + result FPC modes 1-3, 7" 5F7FFFFF 5F800000 5F7FFFFF 5F7FFFFF +r 1210.10 +*Want "CELGBR + result M3 modes 1, 3-5" 5F800000 5F7FFFFF 5F800000 5F7FFFFF +r 1220.08 +*Want "CELGBR + result M3 modes 6, 7" 5F800000 5F7FFFFF + +r 1230.10 +*Want "CELGBR - result FPC modes 1-3, 7" 5F7FFFFF 5F800000 5F7FFFFF 5F7FFFFF +r 1240.10 +*Want "CELGBR - result M3 modes 1, 3-5" 5F800000 5F7FFFFF 5F800000 5F7FFFFF +r 1250.08 +*Want "CELGBR - result M3 modes 6, 7" 5F800000 5F7FFFFF + +r 1260.10 +*Want "CELGBR - result FPC modes 1-3, 7" 5F7FFFFF 5F800000 5F7FFFFF 5F7FFFFF +r 1270.10 +*Want "CELGBR - result M3 modes 1, 3-5" 5F7FFFFF 5F7FFFFF 5F7FFFFF 5F7FFFFF +r 1280.08 +*Want "CELGBR - result M3 modes 6, 7" 5F800000 5F7FFFFF + + +# Inputs converted to BFP short rounding mode test FPCR Contents +*Compare +r 1500.10 +*Want "CELGBR + FPC modes 1-3, 7 FPCR" 00000001 00000002 00000003 00000007 +r 1510.10 +*Want "CELGBR + M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 1520.08 +*Want "CELGBR + M3 modes 6, 7 FPCR" 00080000 00080000 + +r 1530.10 +*Want "CELGBR - FPC modes 1-3, 7 FPCR" 00000001 00000002 00000003 00000007 +r 1540.10 +*Want "CELGBR - M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 1550.08 +*Want "CELGBR - M3 modes 6, 7 FPCR" 00080000 00080000 + +r 1560.10 +*Want "CELGBR - FPC modes 1-3, 7 FPCR" 00000001 00000002 00000003 00000007 +r 1570.10 +*Want "CELGBR - M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 1580.08 +*Want "CELGBR - M3 modes 6, 7 FPCR" 00080000 00080000 + + +# Inputs converted to BFP Long - Results +*Compare +r 2000.10 +*Want "CDLGBR result pair 1" 3FF00000 00000000 3FF00000 00000000 +r 2010.10 +*Want "CDLGBR result pair 2" 40000000 00000000 40000000 00000000 +r 2020.10 +*Want "CDLGBR result pair 3" 40100000 00000000 40100000 00000000 +r 2030.10 +*Want "CDLGBR result pair 4" 43EFFFFF E0000000 43EFFFFF E0000000 +r 2040.10 +*Want "CDLGBR result pair 5" 43EFFFFF FFFFFFFF 43EFFFFF FFFFFFFF +r 2050.10 +*Want "CDLGBR result pair 6" 43F00000 00000000 43F00000 00000000 + +# Inputs converted to BFP Long - FPCR Contents +*Compare +r 2100.10 +*Want "CDLGBR FPC pairs 1-2" 00000000 F8000000 00000000 F8000000 +r 2110.10 +*Want "CDLGBR FPC pairs 3-4" 00000000 F8000000 00000000 F8000000 +r 2120.10 +*Want "CDLGBR FPC pairs 5-6" 00000000 F8000000 00080000 F8000C00 + + +# Inputs converted to BFP long rounding mode test results +*Compare +r 2200.10 +*Want "CDLGBR + FPC modes 1, 2" 43EFFFFF FFFFFFFF 43F00000 00000000 +r 2210.10 +*Want "CDLGBR + FPC modes 3, 7" 43EFFFFF FFFFFFFF 43EFFFFF FFFFFFFF +r 2220.10 +*Want "CDLGBR + M3 modes 1, 3" 43F00000 00000000 43EFFFFF FFFFFFFF +r 2230.10 +*Want "CDLGBR + M3 modes 4, 5" 43F00000 00000000 43EFFFFF FFFFFFFF +r 2240.10 +*Want "CDLGBR + M3 modes 6, 7" 43F00000 00000000 43EFFFFF FFFFFFFF + +r 2250.10 +*Want "CDLGBR - FPC modes 1, 2" 43EFFFFF FFFFFFFF 43F00000 00000000 +r 2260.10 +*Want "CDLGBR - FPC modes 3, 7" 43EFFFFF FFFFFFFF 43EFFFFF FFFFFFFF +r 2270.10 +*Want "CDLGBR - M3 modes 1, 3" 43F00000 00000000 43EFFFFF FFFFFFFF +r 2280.10 +*Want "CDLGBR - M3 modes 4, 5" 43F00000 00000000 43EFFFFF FFFFFFFF +r 2290.10 +*Want "CDLGBR - M3 modes 6, 7" 43F00000 00000000 43EFFFFF FFFFFFFF + +r 22A0.10 +*Want "CDLGBR - FPC modes 1, 2" 43EFFFFF FFFFFFFF 43F00000 00000000 +r 22B0.10 +*Want "CDLGBR - FPC modes 3, 7" 43EFFFFF FFFFFFFF 43EFFFFF FFFFFFFF +r 22C0.10 +*Want "CDLGBR - M3 modes 1, 3" 43EFFFFF FFFFFFFF 43EFFFFF FFFFFFFF +r 22D0.10 +*Want "CDLGBR - M3 modes 4, 5" 43EFFFFF FFFFFFFF 43EFFFFF FFFFFFFF +r 22E0.10 +*Want "CDLGBR - M3 modes 6, 7" 43F00000 00000000 43EFFFFF FFFFFFFF + + +# Inputs converted to BFP long rounding mode test FPCR contents +*Compare +r 2700.10 +*Want "CDLGBR + FPC modes 1-3, 7 FPCR" 00000001 00000002 00000003 00000007 +r 2710.10 +*Want "CDLGBR + M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 2720.08 +*Want "CDLGBR + M3 modes 6, 7 FPCR" 00080000 00080000 + +r 2730.10 +*Want "CDLGBR - FPC modes 1-3, 7 FPCR" 00000001 00000002 00000003 00000007 +r 2740.10 +*Want "CDLGBR - M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 2750.08 +*Want "CDLGBR - M3 modes 6, 7 FPCR" 00080000 00080000 + +r 2760.10 +*Want "CDLGBR - FPC modes 1-3, 7 FPCR" 00000001 00000002 00000003 00000007 +r 2770.10 +*Want "CDLGBR - M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 2780.08 +*Want "CDLGBR - M3 modes 6, 7 FPCR" 00080000 00080000 + + +# Inputs converted to BFP Extended - Results +*Compare +r 3000.10 +*Want "CXLGBR result 1a" 3FFF0000 00000000 00000000 00000000 +r 3010.10 +*Want "CXLGBR result 1b" 3FFF0000 00000000 00000000 00000000 +r 3020.10 +*Want "CXLGBR result 2a" 40000000 00000000 00000000 00000000 +r 3030.10 +*Want "CXLGBR result 2b" 40000000 00000000 00000000 00000000 +r 3040.10 +*Want "CXLGBR result 3a" 40010000 00000000 00000000 00000000 +r 3050.10 +*Want "CXLGBR result 3b" 40010000 00000000 00000000 00000000 +r 3060.10 +*Want "CXLGBR result 4a" 403EFFFF FE000000 00000000 00000000 +r 3070.10 +*Want "CXLGBR result 4b" 403EFFFF FE000000 00000000 00000000 +r 3080.10 +*Want "CXLGBR result 5a" 403EFFFF FFFFFFFF F0000000 00000000 +r 3090.10 +*Want "CXLGBR result 5b" 403EFFFF FFFFFFFF F0000000 00000000 +r 30A0.10 +*Want "CXLGBR result 6a" 403EFFFF FFFFFFFF FFFE0000 00000000 +r 30B0.10 +*Want "CXLGBR result 6b" 403EFFFF FFFFFFFF FFFE0000 00000000 + +# Inputs converted to BFP Extended- FPCR Contents +*Compare +r 3200.10 +*Want "CXLGBR FPC pairs 1-2" 00000000 F8000000 00000000 F8000000 +r 3210.10 +*Want "CXLGBR FPC pairs 3-4" 00000000 F8000000 00000000 F8000000 +r 3220.10 +*Want "CXLGBR FPC pairs 5-6" 00000000 F8000000 00000000 F8000000 + +*Done + diff --git a/tests/bfp-010-cvtfrfix.asm b/tests/bfp-010-cvtfrfix.asm new file mode 100644 index 000000000..e1328e702 --- /dev/null +++ b/tests/bfp-010-cvtfrfix.asm @@ -0,0 +1,487 @@ + TITLE 'bfp-010-cvtfrfix.asm: Test IEEE Convert From Fixed (int-32)' +*********************************************************************** +* +*Testcase IEEE CONVERT FROM FIXED 32 +* Test case capability includes IEEE exceptions trappable and +* otherwise. Test result, FPC flags, and DXC saved for all tests. +* Convert From Fixed does not set the condition code. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* bfp-010-cvtfrfix.asm +* +* This assembly-language source file is part of the +* Hercules Decimal Floating Point Validation Package +* by Stephen R. Orso +* +* Copyright 2016 by Stephen R Orso. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* +* 3. The name of the author may not be used to endorse or promote +* products derived from this software without specific prior written +* permission. +* +* DISCLAMER: THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* HOLDER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* Tests the following six conversion instructions +* CONVERT FROM FIXED (32 to short BFP, RRE) +* CONVERT FROM FIXED (32 to long BFP, RRE) +* CONVERT FROM FIXED (32 to extended BFP, RRE) +* CONVERT FROM FIXED (32 to short BFP, RRF-e) +* CONVERT FROM FIXED (32 to long BFP, RRF-e) +* CONVERT FROM FIXED (32 to extended BFP, RRF-e) +* +* Test data is compiled into this program. The test script that runs +* this program can provide alternative test data through Hercules R +* commands. +* +* Test Case Order +* 1) Int-32 to Short BFP +* 2) Int-32 to Short BFP with all rounding modes +* 3) Int-32 to Long BFP +* 4) Int-32 to Extended BFP +* +* Provided test data is 1, 2, 4, -2, 2 147 483 647, -2 147 483 647. +* The last two values will trigger inexact exceptions when converted +* to short BFP. The last two values are also used to test rounding +* mode and inexact supression in the CEFBRA instruction. +* +* Also tests the following floating point support instructions +* LOAD (Short) +* LOAD (Long) +* LOAD FPC +* SET BFP ROUNDING MODE 2-BIT +* SET BFP ROUNDING MODE 3-BIT +* STORE (Short) +* STORE (Long) +* STORE FPC +* +*********************************************************************** + SPACE 2 + MACRO + PADCSECT &ENDLABL +.* +.* Macro to pad the CSECT to include result data areas if this test +.* program is not being assembled using asma. asma generates a core +.* image that is loaded by the loadcore command, and because the +.* core image is a binary stored in Github, it makes sense to make +.* this small effort to keep the core image small. +.* + AIF (D'&ENDLABL).GOODPAD + MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + MNOTE *,'No CSECT padding performed' + MEXIT +.* +.GOODPAD ANOP Label valid. See if we're on asma + AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + ORG &ENDLABL-1 Not ASMA. Pad CSECT + MEXIT +.* +.NOPAD ANOP + MNOTE *,'asma detected; no CSECT padding performed' + MEND +* +* Note: for compatibility with the z/CMS test rig, do not change +* or use R11, R14, or R15. Everything else is fair game. +* + SPACE 3 +BFPCVTFF START 0 +STRTLABL EQU * +R0 EQU 0 Work register for cc extraction +R1 EQU 1 +R2 EQU 2 Holds count of test input values +R3 EQU 3 Points to next test input value(s) +R4 EQU 4 Available +R5 EQU 5 Available +R6 EQU 6 Available +R7 EQU 7 Pointer to next result value(s) +R8 EQU 8 Pointer to next FPCR result +R9 EQU 9 Rounding tests top of outer loop +R10 EQU 10 Pointer to test address list +R11 EQU 11 **Reserved for z/CMS test rig +R12 EQU 12 Holds number of test cases in set +R13 EQU 13 Mainline return address +R14 EQU 14 **Return address for z/CMS test rig +R15 EQU 15 **Base register on z/CMS or Hyperion +* +* Floating Point Register equates to keep the cross reference clean +* +FPR0 EQU 0 +FPR1 EQU 1 +FPR2 EQU 2 +FPR3 EQU 3 +FPR4 EQU 4 +FPR5 EQU 5 +FPR6 EQU 6 +FPR7 EQU 7 +FPR8 EQU 8 +FPR9 EQU 9 +FPR10 EQU 10 +FPR11 EQU 11 +FPR12 EQU 12 +FPR13 EQU 13 +FPR14 EQU 14 +FPR15 EQU 15 +* + USING *,R15 +* +* Above works on real iron (R15=0 after sysclear) +* and in z/CMS (R15 points to start of load module) +* + ORG STRTLABL+X'8E' Program check interrution code +PCINTCD DS H +* +PCOLDPSW EQU STRTLABL+X'150' z/Arch Program check old PSW +* + ORG STRTLABL+X'1A0' z/Arch Restart PSW + DC X'0000000180000000',AD(START) +* + ORG STRTLABL+X'1D0' z/Arch Program check old PSW + DC X'0000000000000000',AD(PROGCHK) +* +* Program check routine. If Data Exception, continue execution at +* the instruction following the program check. Otherwise, hard wait. +* No need to collect data. All interesting DXC stuff is captured +* in the FPCR. +* + ORG STRTLABL+X'200' +PROGCHK DS 0H Program check occured... + CLI PCINTCD+1,X'07' Data Exception? + JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) + LPSWE PCOLDPSW ..yes, resume program execution +PCNOTDTA DS 0H + LTR R14,R14 Return address provided? + BNZR R14 Yes, return to z/CMS test rig. + LPSWE HARDWAIT Not data exception, enter disabled wait + EJECT +*********************************************************************** +* +* Main program. Enable Advanced Floating Point, process test cases. +* +*********************************************************************** + SPACE 2 +START STCTL R0,R0,CTLR0 Store CR0 to enable AFP + OI CTLR0+1,X'04' Turn on AFP bit + LCTL R0,R0,CTLR0 Reload updated CR0 +* + LA R10,SHORTS Point to integer test inputs + BAS R13,CEFBR Convert values from fixed to short BFP +* + LA R10,RMSHORTS Point to inputs for rounding mode tests + BAS R13,CEFBRA Convert using all rounding mode options +* + LA R10,LONGS Point to integer test inputs + BAS R13,CDFBR Convert values from fixed to long BFP +* + LA R10,EXTDS Point to integer test inputs + BAS R13,CXFBR Convert values from fixed to extended +* + LTR R14,R14 Return address provided? + BNZR R14 ..Yes, return to z/CMS test rig. + LPSWE WAITPSW All done +* + DS 0D Ensure correct alignment for psw +WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end +* +CTLR0 DS F +FPCREGNT DC X'00000000' FPC Reg IEEE exceptions Not Trappable +FPCREGTR DC X'F8000000' FPC Reg IEEE exceptions TRappable +* +* Input values parameter list, four fullwords: +* 1) Count, +* 2) Address of inputs, +* 3) Address to place results, and +* 4) Address to place DXC/Flags/cc values. +* + ORG STRTLABL+X'300' +SHORTS DS 0F + DC A(INTCOUNT) + DC A(INTIN) + DC A(SBFPOUT) + DC A(SBFPFLGS) +* +LONGS DS 0F int-32 inputs for long BFP testing + DC A(INTCOUNT) + DC A(INTIN) + DC A(LBFPOUT) + DC A(LBFPFLGS) +* +EXTDS DS 0F int-32 inputs for Extended BFP testing + DC A(INTCOUNT) + DC A(INTIN) + DC A(XBFPOUT) + DC A(XBFPFLGS) +* +RMSHORTS DC A(INTRMCT) + DC A(INTINRM) Last two int-32 are only concerns + DC A(SBFPRMO) Space for rounding mode tests + DC A(SBFPRMOF) Space for rounding mode test flags + EJECT +*********************************************************************** +* +* Convert int-32 to short BFP format. A pair of results is generated +* for each input: one with all exceptions non-trappable, and the second +* with all exceptions trappable. The FPCR is stored for each result. +* +*********************************************************************** + SPACE 3 +CEFBR LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + L R1,0(,R3) Get integer test value + LFPC FPCREGNT Set exceptions non-trappable + CEFBR FPR8,R1 Cvt Int in GPR1 to float in FPR8 + STE FPR8,0(,R7) Store short BFP result + STFPC 0(R8) Store resulting FPC flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + CEFBR FPR8,R1 Cvt Int in GPR1 to float in FPR8 + STE FPR8,4(,R7) Store short BFP result + STFPC 4(R8) Store resulting FPC flags and DXC + LA R3,4(,R3) Foint to next input values + LA R7,8(,R7) Point to next short BFP converted values + LA R8,8(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert int-32 to short BFP format using each possible rounding mode. +* Ten test results are generated for each input. A 48-byte test result +* section is used to keep results sets aligned on a quad-double word. +* +* The first four tests use rounding modes specified in the FPC with the +* IEEE Inexact exception supressed. SRNM (2-bit) is used for the +* first two FPCR-controlled tests and SRNMB (3-bit) is used for the +* last two to get full coverage of that instruction pair. +* +* The next six results use instruction-specified rounding modes. +* +* The default rounding mode (0 for RNTE) is not tested in this section; +* prior tests used the default rounding mode. RNTE is tested +* explicitly as a rounding mode in this section. +* +*********************************************************************** + SPACE 2 +CEFBRA LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + L R1,0(,R3) Get integer test value +* +* Test cases using rounding mode specified in the FPCR +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 1 SET FPCR to RZ, towards zero + CEFBRA FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked + STE FPR8,0*4(,R7) Store short BFP result + STFPC 0(R8) Store resulting FPC flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 2 SET FPCR to RP, to +infinity + CEFBRA FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked + STE FPR8,1*4(,R7) Store short BFP result + STFPC 1*4(R8) Store resulting FPC flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 3 SET FPCR to RM, to -infinity + CEFBRA FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked + STE FPR8,2*4(,R7) Store short BFP result + STFPC 2*4(R8) Store resulting FPC flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 7 RFS, Prepare For Shorter Precision + CEFBRA FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked + STE FPR8,3*4(,R7) Store short BFP result + STFPC 3*4(R8) Store resulting FPC flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CEFBRA FPR8,1,R1,B'0000' RNTA, to nearest, ties away + STE FPR8,4*4(,R7) Store short BFP result + STFPC 4*4(R8) Store resulting FPC flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CEFBRA FPR8,3,R1,B'0000' RPS, prepare for shorter precision + STE FPR8,5*4(,R7) Store short BFP result + STFPC 5*4(R8) Store resulting FPC flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CEFBRA FPR8,4,R1,B'0000' RNTE to nearest, ties to even + STE FPR8,6*4(,R7) Store short BFP result + STFPC 6*4(R8) Store resulting FPC flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CEFBRA FPR8,5,R1,B'0000' RZ, toward zero + STE FPR8,7*4(,R7) Store short BFP result + STFPC 7*4(R8) Store resulting FPC flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CEFBRA FPR8,6,R1,B'0000' RP, to +inf + STE FPR8,8*4(,R7) Store short BFP result + STFPC 8*4(R8) Store resulting FPC flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CEFBRA FPR8,7,R1,B'0000' RM, to -inf + STE FPR8,9*4(,R7) Store short BFP result + STFPC 9*4(R8) Store resulting FPC flags and DXC +* + LA R3,4(,R3) Point to next input values + LA R7,12*4(,R7) Point to next short BFP converted values + LA R8,12*4(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert int-32 to long BFP format. A pair of results is generated +* for each input: one with all exceptions non-trappable, and the second +* with all exceptions trappable. The FPCR is stored for each result. +* Conversion of a 32-bit integer to long is always exact; no exceptions +* are expected +* +*********************************************************************** + SPACE 2 +CDFBR LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + L R1,0(,R3) Get integer test value + LFPC FPCREGNT Set exceptions non-trappable + CDFBR FPR8,R1 Cvt Int in GPR1 to float in FPR8 + STD FPR8,0(,R7) Store long BFP result + STFPC 0(R8) Store resulting FPC flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + CDFBR FPR8,R1 Cvt Int in GPR1 to float in FPR8 + STD FPR8,8(,R7) Store long BFP result + STFPC 4(R8) Store resulting FPC flags and DXC +* + LA R3,4(,R3) Point to next input values + LA R7,16(,R7) Point to next long BFP converted value + LA R8,8(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert int-32 to extended BFP format. A pair of results is +* generated for each input: one with all exceptions non-trappable, +* and the second with all exceptions trappable. The FPCR is +* stored for each result. Conversion of a 32-bit integer to +* extended is always exact; no exceptions are expected +* +*********************************************************************** + SPACE 2 +CXFBR LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + L R1,0(,R3) Get integer test value + LFPC FPCREGNT Set exceptions non-trappable + CXFBR FPR8,R1 Cvt Int in GPR1 to float in FPR8-FPR10 + STD FPR8,0(,R7) Store extended BFP result part 1 + STD FPR10,8(,R7) Store extended BFP result part 2 + STFPC 0(R8) Store resulting FPC flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + CXFBR FPR8,R1 Cvt Int in GPR1 to float in FPR8-FPR10 + STD FPR8,16(,R7) Store extended BFP result part 1 + STD FPR10,24(,R7) Store extended BFP result part 2 + STFPC 4(R8) Store resulting FPC flags and DXC +* + LA R3,4(,R3) Point to next input values + LA R7,32(,R7) Point to next extended BFP converted value + LA R8,8(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Short integer inputs for Convert From Fixed testing. The same set of +* inputs are used for short, long, and extended formats. The last two +* values are used for rounding mode tests for short only; conversion of +* int-32 to long or extended are always exact. +* +*********************************************************************** + SPACE 3 +INTIN DS 0F + DC F'1' + DC F'2' + DC F'4' + DC F'-2' + DC F'2147483647' should compile to X'7FFFFFFF' - inexact + DC F'-2147483647' should compile to X'80000001' - inexact + DC XL4'7FFFFF80' Fits in short BFP +INTCOUNT EQU (*-INTIN)/4 Count of integers in list +* +* Short BFP Exhaustive rounding mode tests. int-32 always fits in +* long BFP or extended BFP with no loss of precision, so no basis for +* exhaustive rounding tests for long or extended +* +INTINRM DS 0F + DC XL4'7FFFFFE0' Inexact, normally rounds up + DC XL4'7FFFFFC0' Inexact, Tie + DC XL4'7FFFFFA0' Inexact, normally rounds down +INTRMCT EQU (*-INTINRM)/4 Count of rounding mode test inputs +* +SBFPOUT EQU STRTLABL+X'1000' Short BFP results from Int-32 inputs +* ..6 pairs used, room for 32 pairs +SBFPFLGS EQU STRTLABL+X'1100' FPCR flags and DXC from short BFP +* ..6 pairs used, room for 32 pairs +SBFPRMO EQU STRTLABL+X'1200' Short BFP rounding mode results +* ..2 sets used, room for 16 +SBFPRMOF EQU STRTLABL+X'1500' Short BFP rndg mode FPCR contents +* ..2 sets used, room for +16 +* ..next set at X'1800' +* +LBFPOUT EQU STRTLABL+X'2000' Long BFP results from Int-32 inputs +* ..6 pairs used, room for 16 pairs +LBFPFLGS EQU STRTLABL+X'2100' Long BFP FPCR contents +* ..6 pairs used, room for 32+ pairs +* ..next pair at X'2200' +* +XBFPOUT EQU STRTLABL+X'3000' Extended BFP results from Int-32 +* ..6 pairs used, room for 16 pairs +XBFPFLGS EQU STRTLABL+X'3200' Extended BFP FPCR contents +* ..6 pairs used, room for 16 pairs +* +ENDLABL EQU STRTLABL+X'3300' Next result area available + PADCSECT ENDLABL + END diff --git a/tests/bfp-010-cvtfrfix.core b/tests/bfp-010-cvtfrfix.core new file mode 100644 index 000000000..a14bd4107 Binary files /dev/null and b/tests/bfp-010-cvtfrfix.core differ diff --git a/tests/bfp-010-cvtfrfix.list b/tests/bfp-010-cvtfrfix.list new file mode 100644 index 000000000..257db3cba --- /dev/null +++ b/tests/bfp-010-cvtfrfix.list @@ -0,0 +1,605 @@ +ASMA Ver. 0.2.0 ieee-cvtfrfix.asm: Test IEEE Convert From Fixed (int-32) 08 Sep 2016 08:40:02 Page 1 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 2 *********************************************************************** + 3 * + 4 *Testcase IEEE CONVERT FROM FIXED 32 + 5 * Test case capability includes IEEE exceptions trappable and + 6 * otherwise. Test result, FPC flags, and DXC saved for all tests. + 7 * Convert From Fixed does not set the condition code. + 8 * + 9 *********************************************************************** + + + 11 *********************************************************************** + 12 * + 13 * Tests the following six conversion instructions + 14 * CONVERT FROM FIXED (32 to short BFP, RRE) + 15 * CONVERT FROM FIXED (32 to long BFP, RRE) + 16 * CONVERT FROM FIXED (32 to extended BFP, RRE) + 17 * CONVERT FROM FIXED (32 to short BFP, RRF-e) + 18 * CONVERT FROM FIXED (32 to long BFP, RRF-e) + 19 * CONVERT FROM FIXED (32 to extended BFP, RRF-e) + 20 * + 21 * Test data is compiled into this program. The test script that runs + 22 * this program can provide alternative test data through Hercules R + 23 * commands. + 24 * + 25 * Test Case Order + 26 * 1) Int-32 to Short BFP + 27 * 2) Int-32 to Short BFP with all rounding modes + 28 * 3) Int-32 to Long BFP + 29 * 4) Int-32 to Extended BFP + 30 * + 31 * Provided test data is 1, 2, 4, -2, 2 147 483 647, -2 147 483 647. + 32 * The last two values will trigger inexact exceptions when converted + 33 * to short BFP. The last two values are also used to test rounding + 34 * mode and inexact supression in the CEFBRA instruction. + 35 * + 36 * Also tests the following floating point support instructions + 37 * LOAD (Short) + 38 * LOAD (Long) + 39 * LOAD FPC + 40 * SET BFP ROUNDING MODE 2-BIT + 41 * SET BFP ROUNDING MODE 3-BIT + 42 * STORE (Short) + 43 * STORE (Long) + 44 * STORE FPC + 45 * + 46 *********************************************************************** + + + 48 MACRO + 49 PADCSECT &ENDLABL + 50 .* + 51 .* Macro to pad the CSECT to include result data areas if this test + ASMA Ver. 0.2.0 ieee-cvtfrfix.asm: Test IEEE Convert From Fixed (int-32) 08 Sep 2016 08:40:02 Page 2 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 52 .* program is not being assembled using asma. asma generates a core + 53 .* image that is loaded by the loadcore command, and because the + 54 .* core image is a binary stored in Github, it makes sense to make + 55 .* this small effort to keep the core image small. + 56 .* + 57 AIF (D'&ENDLABL).GOODPAD + 58 MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + 59 MNOTE *,'No CSECT padding performed' + 60 MEXIT + 61 .* + 62 .GOODPAD ANOP Label valid. See if we're on asma + 63 AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + 64 ORG &ENDLABL-1 Not ASMA. Pad CSECT + 65 MEXIT + 66 .* + 67 .NOPAD ANOP + 68 MNOTE *,'asma detected; no CSECT padding performed' + 69 MEND + 70 * + 71 * Note: for compatibility with the z/CMS test rig, do not change + 72 * or use R11, R14, or R15. Everything else is fair game. + 73 * + + + + 0000000000000000 0000000000000507 75 BFPCVTFF START 0 + 0000000000000000 0000000000000001 76 STRTLABL EQU * + 0000000000000000 0000000000000001 77 R0 EQU 0 Work register for cc extraction + 0000000000000001 0000000000000001 78 R1 EQU 1 + 0000000000000002 0000000000000001 79 R2 EQU 2 Holds count of test input values + 0000000000000003 0000000000000001 80 R3 EQU 3 Points to next test input value(s) + 0000000000000004 0000000000000001 81 R4 EQU 4 Available + 0000000000000005 0000000000000001 82 R5 EQU 5 Available + 0000000000000006 0000000000000001 83 R6 EQU 6 Available + 0000000000000007 0000000000000001 84 R7 EQU 7 Pointer to next result value(s) + 0000000000000008 0000000000000001 85 R8 EQU 8 Pointer to next FPCR result + 0000000000000009 0000000000000001 86 R9 EQU 9 Rounding tests top of outer loop + 000000000000000A 0000000000000001 87 R10 EQU 10 Pointer to test address list + 000000000000000B 0000000000000001 88 R11 EQU 11 **Reserved for z/CMS test rig + 000000000000000C 0000000000000001 89 R12 EQU 12 Holds number of test cases in set + 000000000000000D 0000000000000001 90 R13 EQU 13 Mainline return address + 000000000000000E 0000000000000001 91 R14 EQU 14 **Return address for z/CMS test rig + 000000000000000F 0000000000000001 92 R15 EQU 15 **Base register on z/CMS or Hyperion + 93 * + 94 * Floating Point Register equates to keep the cross reference clean + 95 * + 0000000000000000 0000000000000001 96 FPR0 EQU 0 + 0000000000000001 0000000000000001 97 FPR1 EQU 1 + 0000000000000002 0000000000000001 98 FPR2 EQU 2 + 0000000000000003 0000000000000001 99 FPR3 EQU 3 + 0000000000000004 0000000000000001 100 FPR4 EQU 4 + 0000000000000005 0000000000000001 101 FPR5 EQU 5 + ASMA Ver. 0.2.0 ieee-cvtfrfix.asm: Test IEEE Convert From Fixed (int-32) 08 Sep 2016 08:40:02 Page 3 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 0000000000000006 0000000000000001 102 FPR6 EQU 6 + 0000000000000007 0000000000000001 103 FPR7 EQU 7 + 0000000000000008 0000000000000001 104 FPR8 EQU 8 + 0000000000000009 0000000000000001 105 FPR9 EQU 9 + 000000000000000A 0000000000000001 106 FPR10 EQU 10 + 000000000000000B 0000000000000001 107 FPR11 EQU 11 + 000000000000000C 0000000000000001 108 FPR12 EQU 12 + 000000000000000D 0000000000000001 109 FPR13 EQU 13 + 000000000000000E 0000000000000001 110 FPR14 EQU 14 + 000000000000000F 0000000000000001 111 FPR15 EQU 15 + 112 * +0000000000000000 0000000000000000 113 USING *,R15 + 114 * + 115 * Above works on real iron (R15=0 after sysclear) + 116 * and in z/CMS (R15 points to start of load module) + 117 * +0000000000000000 0000000000000000 000000000000008E 118 ORG STRTLABL+X'8E' Program check interrution code +000000000000008E 0000 119 PCINTCD DS H + 120 * + 0000000000000150 0000000000000001 121 PCOLDPSW EQU STRTLABL+X'150' z/Arch Program check old PSW + 122 * +0000000000000090 0000000000000090 00000000000001A0 123 ORG STRTLABL+X'1A0' z/Arch Restart PSW +00000000000001A0 00000001 80000000 124 DC X'0000000180000000',AD(START) + 125 * +00000000000001B0 00000000000001B0 00000000000001D0 126 ORG STRTLABL+X'1D0' z/Arch Program check old PSW +00000000000001D0 00000000 00000000 127 DC X'0000000000000000',AD(PROGCHK) + 128 * + 129 * Program check routine. If Data Exception, continue execution at + 130 * the instruction following the program check. Otherwise, hard wait. + 131 * No need to collect data. All interesting DXC stuff is captured + 132 * in the FPCR. + 133 * +00000000000001E0 00000000000001E0 0000000000000200 134 ORG STRTLABL+X'200' +0000000000000200 135 PROGCHK DS 0H Program check occured... +0000000000000200 9507 F08F 000000000000008F 136 CLI PCINTCD+1,X'07' Data Exception? +0000000000000204 A774 0004 000000000000020C 137 JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) +0000000000000208 B2B2 F150 0000000000000150 138 LPSWE PCOLDPSW ..yes, resume program execution +000000000000020C 139 PCNOTDTA DS 0H +000000000000020C 12EE 140 LTR R14,R14 Return address provided? +000000000000020E 077E 141 BNZR R14 Yes, return to z/CMS test rig. +0000000000000210 B2B2 F258 0000000000000258 142 LPSWE HARDWAIT Not data exception, enter disabled wait + ASMA Ver. 0.2.0 ieee-cvtfrfix.asm: Test IEEE Convert From Fixed (int-32) 08 Sep 2016 08:40:02 Page 4 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 144 *********************************************************************** + 145 * + 146 * Main program. Enable Advanced Floating Point, process test cases. + 147 * + 148 *********************************************************************** + + +0000000000000214 B600 F268 0000000000000268 150 START STCTL R0,R0,CTLR0 Store CR0 to enable AFP +0000000000000218 9604 F269 0000000000000269 151 OI CTLR0+1,X'04' Turn on AFP bit +000000000000021C B700 F268 0000000000000268 152 LCTL R0,R0,CTLR0 Reload updated CR0 + 153 * +0000000000000220 41A0 F300 0000000000000300 154 LA R10,SHORTS Point to integer test inputs +0000000000000224 4DD0 F340 0000000000000340 155 BAS R13,CEFBR Convert values from fixed to short BFP + 156 *2345678901234567890123456789012345678901234567890123456789012345678901 + 157 +0000000000000228 41A0 F330 0000000000000330 158 LA R10,RMSHORTS Point to inputs for rounding mode tests +000000000000022C 4DD0 F382 0000000000000382 159 BAS R13,CEFBRA Convert using all rounding mode options + 160 * +0000000000000230 41A0 F310 0000000000000310 161 LA R10,LONGS Point to integer test inputs +0000000000000234 4DD0 F454 0000000000000454 162 BAS R13,CDFBR Convert values from fixed to long BFP + 163 * +0000000000000238 41A0 F320 0000000000000320 164 LA R10,EXTDS Point to integer test inputs +000000000000023C 4DD0 F496 0000000000000496 165 BAS R13,CXFBR Convert values from fixed to extended + 166 * +0000000000000240 12EE 167 LTR R14,R14 Return address provided? +0000000000000242 077E 168 BNZR R14 ..Yes, return to z/CMS test rig. +0000000000000244 B2B2 F248 0000000000000248 169 LPSWE WAITPSW All done + 170 * +0000000000000248 171 DS 0D Ensure correct alignment for psw +0000000000000248 00020000 00000000 172 WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +0000000000000258 00020000 00000000 173 HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end + 174 * +0000000000000268 00000000 175 CTLR0 DS F +000000000000026C 00000000 176 FPCREGNT DC X'00000000' FPC Reg IEEE exceptions Not Trappable +0000000000000270 F8000000 177 FPCREGTR DC X'F8000000' FPC Reg IEEE exceptions TRappable + 178 * + 179 * Input values parameter list, four fullwords: + 180 * 1) Count, + 181 * 2) Address of inputs, + 182 * 3) Address to place results, and + 183 * 4) Address to place DXC/Flags/cc values. + 184 * +0000000000000274 0000000000000274 0000000000000300 185 ORG STRTLABL+X'300' +0000000000000300 186 SHORTS DS 0F +0000000000000300 00000007 187 DC A(INTCOUNT) +0000000000000304 000004E0 188 DC A(INTIN) +0000000000000308 00001000 189 DC A(SBFPOUT) +000000000000030C 00001100 190 DC A(SBFPFLGS) + 191 * +0000000000000310 192 LONGS DS 0F int-32 inputs for long BFP testing +0000000000000310 00000007 193 DC A(INTCOUNT) +0000000000000314 000004E0 194 DC A(INTIN) + ASMA Ver. 0.2.0 ieee-cvtfrfix.asm: Test IEEE Convert From Fixed (int-32) 08 Sep 2016 08:40:02 Page 5 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000318 00002000 195 DC A(LBFPOUT) +000000000000031C 00002100 196 DC A(LBFPFLGS) + 197 * +0000000000000320 198 EXTDS DS 0F int-32 inputs for Extended BFP testing +0000000000000320 00000007 199 DC A(INTCOUNT) +0000000000000324 000004E0 200 DC A(INTIN) +0000000000000328 00003000 201 DC A(XBFPOUT) +000000000000032C 00003200 202 DC A(XBFPFLGS) + 203 * +0000000000000330 00000003 204 RMSHORTS DC A(INTRMCT) +0000000000000334 000004FC 205 DC A(INTINRM) Last two int-32 are only concerns +0000000000000338 00001200 206 DC A(SBFPRMO) Space for rounding mode tests +000000000000033C 00001500 207 DC A(SBFPRMOF) Space for rounding mode test flags + ASMA Ver. 0.2.0 ieee-cvtfrfix.asm: Test IEEE Convert From Fixed (int-32) 08 Sep 2016 08:40:02 Page 6 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 209 *********************************************************************** + 210 * + 211 * Convert int-32 to short BFP format. A pair of results is generated + 212 * for each input: one with all exceptions non-trappable, and the second + 213 * with all exceptions trappable. The FPCR is stored for each result. + 214 * + 215 *********************************************************************** + + + +0000000000000340 9823 A000 0000000000000000 217 CEFBR LM R2,R3,0(R10) Get count and address of test input values +0000000000000344 9878 A008 0000000000000008 218 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000348 1222 219 LTR R2,R2 Any test cases? +000000000000034A 078D 220 BZR R13 ..No, return to caller +000000000000034C 0DC0 221 BASR R12,0 Set top of loop + 222 * +000000000000034E 5810 3000 0000000000000000 223 L R1,0(,R3) Get integer test value +0000000000000352 B29D F26C 000000000000026C 224 LFPC FPCREGNT Set exceptions non-trappable +0000000000000356 B394 0081 225 CEFBR FPR8,R1 Cvt Int in GPR1 to float in FPR8 +000000000000035A 7080 7000 0000000000000000 226 STE FPR8,0(,R7) Store short BFP result +000000000000035E B29C 8000 0000000000000000 227 STFPC 0(R8) Store resulting FPC flags and DXC + 228 * +0000000000000362 B29D F270 0000000000000270 229 LFPC FPCREGTR Set exceptions trappable +0000000000000366 B394 0081 230 CEFBR FPR8,R1 Cvt Int in GPR1 to float in FPR8 +000000000000036A 7080 7004 0000000000000004 231 STE FPR8,4(,R7) Store short BFP result +000000000000036E B29C 8004 0000000000000004 232 STFPC 4(R8) Store resulting FPC flags and DXC +0000000000000372 4130 3004 0000000000000004 233 LA R3,4(,R3) Foint to next input values +0000000000000376 4170 7008 0000000000000008 234 LA R7,8(,R7) Point to next short BFP converted values +000000000000037A 4180 8008 0000000000000008 235 LA R8,8(,R8) Point to next FPCR/CC result area +000000000000037E 062C 236 BCTR R2,R12 Convert next input value. +0000000000000380 07FD 237 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvtfrfix.asm: Test IEEE Convert From Fixed (int-32) 08 Sep 2016 08:40:02 Page 7 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 239 *********************************************************************** + 240 * + 241 * Convert int-32 to short BFP format using each possible rounding mode. + 242 * Ten test results are generated for each input. A 48-byte test result + 243 * section is used to keep results sets aligned on a quad-double word. + 244 * + 245 * The first four tests use rounding modes specified in the FPC with the + 246 * IEEE Inexact exception supressed. SRNM (2-bit) is used for the first + 247 * two FPCR-controlled tests and SRNMB (3-bit) is used for the last two + 248 * to get full coverage of that instruction pair. + 249 * + 250 * The next six results use instruction-specified rounding modes. + 251 * + 252 * The default rounding mode (0 for RNTE) is not tested in this section; + 253 * prior tests used the default rounding mode. RNTE is tested explicitly + 254 * as a rounding mode in this section. + 255 * + 256 *********************************************************************** + + +0000000000000382 9823 A000 0000000000000000 258 CEFBRA LM R2,R3,0(R10) Get count and address of test input values +0000000000000386 9878 A008 0000000000000008 259 LM R7,R8,8(R10) Get address of result area and flag area. +000000000000038A 1222 260 LTR R2,R2 Any test cases? +000000000000038C 078D 261 BZR R13 ..No, return to caller +000000000000038E 0DC0 262 BASR R12,0 Set top of loop + 263 * +0000000000000390 5810 3000 0000000000000000 264 L R1,0(,R3) Get integer test value + 265 * + 266 * Test cases using rounding mode specified in the FPCR + 267 * +0000000000000394 B29D F26C 000000000000026C 268 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000398 B299 0001 0000000000000001 269 SRNM 1 SET FPCR to RZ, towards zero +000000000000039C B394 0481 270 CEFBRA FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked +00000000000003A0 7080 7000 0000000000000000 271 STE FPR8,0*4(,R7) Store short BFP result +00000000000003A4 B29C 8000 0000000000000000 272 STFPC 0(R8) Store resulting FPC flags and DXC + 273 * +00000000000003A8 B29D F26C 000000000000026C 274 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000003AC B299 0002 0000000000000002 275 SRNM 2 SET FPCR to RP, to +infinity +00000000000003B0 B394 0481 276 CEFBRA FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked +00000000000003B4 7080 7004 0000000000000004 277 STE FPR8,1*4(,R7) Store short BFP result +00000000000003B8 B29C 8004 0000000000000004 278 STFPC 1*4(R8) Store resulting FPC flags and DXC + 279 * +00000000000003BC B29D F26C 000000000000026C 280 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000003C0 B2B8 0003 0000000000000003 281 SRNMB 3 SET FPCR to RM, to -infinity +00000000000003C4 B394 0481 282 CEFBRA FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked +00000000000003C8 7080 7008 0000000000000008 283 STE FPR8,2*4(,R7) Store short BFP result +00000000000003CC B29C 8008 0000000000000008 284 STFPC 2*4(R8) Store resulting FPC flags and DXC + 285 * +00000000000003D0 B29D F26C 000000000000026C 286 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000003D4 B2B8 0007 0000000000000007 287 SRNMB 7 RFS, Prepare For Shorter Precision +00000000000003D8 B394 0481 288 CEFBRA FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked +00000000000003DC 7080 700C 000000000000000C 289 STE FPR8,3*4(,R7) Store short BFP result + ASMA Ver. 0.2.0 ieee-cvtfrfix.asm: Test IEEE Convert From Fixed (int-32) 08 Sep 2016 08:40:02 Page 8 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000003E0 B29C 800C 000000000000000C 290 STFPC 3*4(R8) Store resulting FPC flags and DXC + 291 * +00000000000003E4 B29D F26C 000000000000026C 292 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000003E8 B394 1081 293 CEFBRA FPR8,1,R1,B'0000' RNTA, to nearest, ties away from zero +00000000000003EC 7080 7010 0000000000000010 294 STE FPR8,4*4(,R7) Store short BFP result +00000000000003F0 B29C 8010 0000000000000010 295 STFPC 4*4(R8) Store resulting FPC flags and DXC + 296 * +00000000000003F4 B29D F26C 000000000000026C 297 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000003F8 B394 3081 298 CEFBRA FPR8,3,R1,B'0000' RPS, to prepare for shorter precision +00000000000003FC 7080 7014 0000000000000014 299 STE FPR8,5*4(,R7) Store short BFP result +0000000000000400 B29C 8014 0000000000000014 300 STFPC 5*4(R8) Store resulting FPC flags and DXC + 301 * +0000000000000404 B29D F26C 000000000000026C 302 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000408 B394 4081 303 CEFBRA FPR8,4,R1,B'0000' RNTE to nearest, ties to even +000000000000040C 7080 7018 0000000000000018 304 STE FPR8,6*4(,R7) Store short BFP result +0000000000000410 B29C 8018 0000000000000018 305 STFPC 6*4(R8) Store resulting FPC flags and DXC + 306 * +0000000000000414 B29D F26C 000000000000026C 307 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000418 B394 5081 308 CEFBRA FPR8,5,R1,B'0000' RZ, toward zero +000000000000041C 7080 701C 000000000000001C 309 STE FPR8,7*4(,R7) Store short BFP result +0000000000000420 B29C 801C 000000000000001C 310 STFPC 7*4(R8) Store resulting FPC flags and DXC + 311 * +0000000000000424 B29D F26C 000000000000026C 312 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000428 B394 6081 313 CEFBRA FPR8,6,R1,B'0000' RP, to +inf +000000000000042C 7080 7020 0000000000000020 314 STE FPR8,8*4(,R7) Store short BFP result +0000000000000430 B29C 8020 0000000000000020 315 STFPC 8*4(R8) Store resulting FPC flags and DXC + 316 * +0000000000000434 B29D F26C 000000000000026C 317 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000438 B394 7081 318 CEFBRA FPR8,7,R1,B'0000' RM, to -inf +000000000000043C 7080 7024 0000000000000024 319 STE FPR8,9*4(,R7) Store short BFP result +0000000000000440 B29C 8024 0000000000000024 320 STFPC 9*4(R8) Store resulting FPC flags and DXC + 321 * +0000000000000444 4130 3004 0000000000000004 322 LA R3,4(,R3) Point to next input values +0000000000000448 4170 7030 0000000000000030 323 LA R7,12*4(,R7) Point to next short BFP converted values +000000000000044C 4180 8030 0000000000000030 324 LA R8,12*4(,R8) Point to next FPCR/CC result area +0000000000000450 062C 325 BCTR R2,R12 Convert next input value. +0000000000000452 07FD 326 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvtfrfix.asm: Test IEEE Convert From Fixed (int-32) 08 Sep 2016 08:40:02 Page 9 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 328 *********************************************************************** + 329 * + 330 * Convert int-32 to long BFP format. A pair of results is generated + 331 * for each input: one with all exceptions non-trappable, and the second + 332 * with all exceptions trappable. The FPCR is stored for each result. + 333 * Conversion of a 32-bit integer to long is always exact; no exceptions + 334 * are expected + 335 * + 336 *********************************************************************** + + +0000000000000454 9823 A000 0000000000000000 338 CDFBR LM R2,R3,0(R10) Get count and address of test input values +0000000000000458 9878 A008 0000000000000008 339 LM R7,R8,8(R10) Get address of result area and flag area. +000000000000045C 1222 340 LTR R2,R2 Any test cases? +000000000000045E 078D 341 BZR R13 ..No, return to caller +0000000000000460 0DC0 342 BASR R12,0 Set top of loop + 343 * +0000000000000462 5810 3000 0000000000000000 344 L R1,0(,R3) Get integer test value +0000000000000466 B29D F26C 000000000000026C 345 LFPC FPCREGNT Set exceptions non-trappable +000000000000046A B395 0081 346 CDFBR FPR8,R1 Cvt Int in GPR1 to float in FPR8 +000000000000046E 6080 7000 0000000000000000 347 STD FPR8,0(,R7) Store long BFP result +0000000000000472 B29C 8000 0000000000000000 348 STFPC 0(R8) Store resulting FPC flags and DXC + 349 * +0000000000000476 B29D F270 0000000000000270 350 LFPC FPCREGTR Set exceptions trappable +000000000000047A B395 0081 351 CDFBR FPR8,R1 Cvt Int in GPR1 to float in FPR8 +000000000000047E 6080 7008 0000000000000008 352 STD FPR8,8(,R7) Store long BFP result +0000000000000482 B29C 8004 0000000000000004 353 STFPC 4(R8) Store resulting FPC flags and DXC + 354 * +0000000000000486 4130 3004 0000000000000004 355 LA R3,4(,R3) Point to next input values +000000000000048A 4170 7010 0000000000000010 356 LA R7,16(,R7) Point to next long BFP converted value +000000000000048E 4180 8008 0000000000000008 357 LA R8,8(,R8) Point to next FPCR/CC result area +0000000000000492 062C 358 BCTR R2,R12 Convert next input value. +0000000000000494 07FD 359 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvtfrfix.asm: Test IEEE Convert From Fixed (int-32) 08 Sep 2016 08:40:02 Page 10 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 361 *********************************************************************** + 362 * + 363 * Convert int-32 to extended BFP format. A pair of results is + 364 * generated for each input: one with all exceptions non-trappable, + 365 * and the second with all exceptions trappable. The FPCR is + 366 * stored for each result. Conversion of a 32-bit integer to + 367 * extended is always exact; no exceptions are expected + 368 * + 369 *********************************************************************** + + +0000000000000496 9823 A000 0000000000000000 371 CXFBR LM R2,R3,0(R10) Get count and address of test input values +000000000000049A 9878 A008 0000000000000008 372 LM R7,R8,8(R10) Get address of result area and flag area. +000000000000049E 1222 373 LTR R2,R2 Any test cases? +00000000000004A0 078D 374 BZR R13 ..No, return to caller +00000000000004A2 0DC0 375 BASR R12,0 Set top of loop + 376 * +00000000000004A4 5810 3000 0000000000000000 377 L R1,0(,R3) Get integer test value +00000000000004A8 B29D F26C 000000000000026C 378 LFPC FPCREGNT Set exceptions non-trappable +00000000000004AC B396 0081 379 CXFBR FPR8,R1 Cvt Int in GPR1 to float in FPR8-FPR10 +00000000000004B0 6080 7000 0000000000000000 380 STD FPR8,0(,R7) Store extended BFP result part 1 +00000000000004B4 60A0 7008 0000000000000008 381 STD FPR10,8(,R7) Store extended BFP result part 2 +00000000000004B8 B29C 8000 0000000000000000 382 STFPC 0(R8) Store resulting FPC flags and DXC + 383 * +00000000000004BC B29D F270 0000000000000270 384 LFPC FPCREGTR Set exceptions trappable +00000000000004C0 B396 0081 385 CXFBR FPR8,R1 Cvt Int in GPR1 to float in FPR8-FPR10 +00000000000004C4 6080 7010 0000000000000010 386 STD FPR8,16(,R7) Store extended BFP result part 1 +00000000000004C8 60A0 7018 0000000000000018 387 STD FPR10,24(,R7) Store extended BFP result part 2 +00000000000004CC B29C 8004 0000000000000004 388 STFPC 4(R8) Store resulting FPC flags and DXC + 389 * +00000000000004D0 4130 3004 0000000000000004 390 LA R3,4(,R3) Point to next input values +00000000000004D4 4170 7020 0000000000000020 391 LA R7,32(,R7) Point to next extended BFP converted value +00000000000004D8 4180 8008 0000000000000008 392 LA R8,8(,R8) Point to next FPCR/CC result area +00000000000004DC 062C 393 BCTR R2,R12 Convert next input value. +00000000000004DE 07FD 394 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvtfrfix.asm: Test IEEE Convert From Fixed (int-32) 08 Sep 2016 08:40:02 Page 11 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 396 *********************************************************************** + 397 * + 398 * Short integer inputs for Convert From Fixed testing. The same set of + 399 * inputs are used for short, long, and extended formats. The last two + 400 * values are used for rounding mode tests for short only; conversion of + 401 * int-32 to long or extended are always exact. + 402 * + 403 *********************************************************************** + + + +00000000000004E0 405 INTIN DS 0F +00000000000004E0 00000001 406 DC F'1' +00000000000004E4 00000002 407 DC F'2' +00000000000004E8 00000004 408 DC F'4' +00000000000004EC FFFFFFFE 409 DC F'-2' +00000000000004F0 7FFFFFFF 410 DC F'2147483647' should compile to X'7FFFFFFF' - inexact +00000000000004F4 80000001 411 DC F'-2147483647' should compile to X'80000001' - inexact +00000000000004F8 7FFFFF80 412 DC XL4'7FFFFF80' Fits in short BFP + 0000000000000007 0000000000000001 413 INTCOUNT EQU (*-INTIN)/4 Count of integers in list + 414 * + 415 * Short BFP Exhaustive rounding mode tests. int-32 always fits in + 416 * long BFP or extended BFP with no loss of precision, so no basis for + 417 * exhaustive rounding tests for long or extended + 418 * +00000000000004FC 419 INTINRM DS 0F +00000000000004FC 7FFFFFE0 420 DC XL4'7FFFFFE0' Inexact, normally rounds up +0000000000000500 7FFFFFC0 421 DC XL4'7FFFFFC0' Inexact, Tie +0000000000000504 7FFFFFA0 422 DC XL4'7FFFFFA0' Inexact, normally rounds down + 0000000000000003 0000000000000001 423 INTRMCT EQU (*-INTINRM)/4 Count of rounding mode test inputs + 424 * + 0000000000001000 0000000000000001 425 SBFPOUT EQU STRTLABL+X'1000' Short BFP results from Int-32 inputs + 426 * ..6 pairs used, room for 32 pairs + 0000000000001100 0000000000000001 427 SBFPFLGS EQU STRTLABL+X'1100' FPCR flags and DXC from short BFP + 428 * ..6 pairs used, room for 32 pairs + 0000000000001200 0000000000000001 429 SBFPRMO EQU STRTLABL+X'1200' Short BFP rounding mode results + 430 * ..2 sets used, room for 16 + 0000000000001500 0000000000000001 431 SBFPRMOF EQU STRTLABL+X'1500' Short BFP rndg mode FPCR contents + 432 * ..2 sets used, room for +16 + 433 * ..next set at X'1800' + 434 * + 0000000000002000 0000000000000001 435 LBFPOUT EQU STRTLABL+X'2000' Long BFP results from Int-32 inputs + 436 * ..6 pairs used, room for 16 pairs + 0000000000002100 0000000000000001 437 LBFPFLGS EQU STRTLABL+X'2100' Long BFP FPCR contents + 438 * ..6 pairs used, room for 32+ pairs + 439 * ..next pair at X'2200' + 440 * + 0000000000003000 0000000000000001 441 XBFPOUT EQU STRTLABL+X'3000' Extended BFP results from Int-32 + 442 * ..6 pairs used, room for 16 pairs + 0000000000003200 0000000000000001 443 XBFPFLGS EQU STRTLABL+X'3200' Extended BFP FPCR contents + 444 * ..6 pairs used, room for 16 pairs + 445 * + ASMA Ver. 0.2.0 ieee-cvtfrfix.asm: Test IEEE Convert From Fixed (int-32) 08 Sep 2016 08:40:02 Page 12 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 0000000000003300 0000000000000001 446 ENDLABL EQU STRTLABL+X'3300' Next result area available + 447 PADCSECT ENDLABL + 448+ MNOTE *,'asma detected; no CSECT padding performed' +0000000000000508 449 END + ASMA Ver. 0.2.0 ieee-cvtfrfix.asm: Test IEEE Convert From Fixed (int-32) 08 Sep 2016 08:40:02 Page 13 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +BFPCVTFF J 000000 1288 75 +CDFBR I 000454 4 338 162 +CEFBR I 000340 4 217 155 +CEFBRA I 000382 4 258 159 +CTLR0 F 000268 4 175 150 151 152 +CXFBR I 000496 4 371 165 +ENDLABL U 003300 1 446 +EXTDS F 000320 4 198 164 +FPCREGNT X 00026C 4 176 224 268 274 280 286 292 297 302 307 312 317 345 378 +FPCREGTR X 000270 4 177 229 350 384 +FPR0 U 000000 1 96 +FPR1 U 000001 1 97 +FPR10 U 00000A 1 106 381 387 +FPR11 U 00000B 1 107 +FPR12 U 00000C 1 108 +FPR13 U 00000D 1 109 +FPR14 U 00000E 1 110 +FPR15 U 00000F 1 111 +FPR2 U 000002 1 98 +FPR3 U 000003 1 99 +FPR4 U 000004 1 100 +FPR5 U 000005 1 101 +FPR6 U 000006 1 102 +FPR7 U 000007 1 103 +FPR8 U 000008 1 104 225 226 230 231 270 271 276 277 282 283 288 289 293 294 298 299 303 + 304 308 309 313 314 318 319 346 347 351 352 379 380 385 386 +FPR9 U 000009 1 105 +HARDWAIT X 000258 8 173 142 +IMAGE 1 000000 1288 0 +INTCOUNT U 000007 1 413 187 193 199 +INTIN F 0004E0 4 405 413 188 194 200 +INTINRM F 0004FC 4 419 423 205 +INTRMCT U 000003 1 423 204 +LBFPFLGS U 002100 1 437 196 +LBFPOUT U 002000 1 435 195 +LONGS F 000310 4 192 161 +PCINTCD H 00008E 2 119 136 +PCNOTDTA H 00020C 2 139 137 +PCOLDPSW U 000150 1 121 138 +PROGCHK H 000200 2 135 127 +R0 U 000000 1 77 150 152 +R1 U 000001 1 78 223 225 230 264 270 276 282 288 293 298 303 308 313 318 344 346 351 + 377 379 385 +R10 U 00000A 1 87 154 158 161 164 217 218 258 259 338 339 371 372 +R11 U 00000B 1 88 +R12 U 00000C 1 89 221 236 262 325 342 358 375 393 +R13 U 00000D 1 90 155 159 162 165 220 237 261 326 341 359 374 394 +R14 U 00000E 1 91 140 141 167 168 +R15 U 00000F 1 92 113 +R2 U 000002 1 79 217 219 236 258 260 325 338 340 358 371 373 393 +R3 U 000003 1 80 217 223 233 258 264 322 338 344 355 371 377 390 +R4 U 000004 1 81 + ASMA Ver. 0.2.0 ieee-cvtfrfix.asm: Test IEEE Convert From Fixed (int-32) 08 Sep 2016 08:40:02 Page 14 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +R5 U 000005 1 82 +R6 U 000006 1 83 +R7 U 000007 1 84 218 226 231 234 259 271 277 283 289 294 299 304 309 314 319 323 339 + 347 352 356 372 380 381 386 387 391 +R8 U 000008 1 85 218 227 232 235 259 272 278 284 290 295 300 305 310 315 320 324 339 + 348 353 357 372 382 388 392 +R9 U 000009 1 86 +RMSHORTS A 000330 4 204 158 +SBFPFLGS U 001100 1 427 190 +SBFPOUT U 001000 1 425 189 +SBFPRMO U 001200 1 429 206 +SBFPRMOF U 001500 1 431 207 +SHORTS F 000300 4 186 154 +START I 000214 4 150 124 +STRTLABL U 000000 1 76 118 121 123 126 134 185 425 427 429 431 435 437 441 443 446 +WAITPSW X 000248 8 172 169 +XBFPFLGS U 003200 1 443 202 +XBFPOUT U 003000 1 441 201 + ASMA Ver. 0.2.0 ieee-cvtfrfix.asm: Test IEEE Convert From Fixed (int-32) 08 Sep 2016 08:40:02 Page 15 + + MACRO DEFN REFERENCES + +PADCSECT 49 447 + ASMA Ver. 0.2.0 ieee-cvtfrfix.asm: Test IEEE Convert From Fixed (int-32) 08 Sep 2016 08:40:02 Page 16 + + DESC SYMBOL SIZE POS ADDR + +Entry: 0 + +Image IMAGE 1288 000-507 000-507 + Region 1288 000-507 000-507 + CSECT BFPCVTFF 1288 000-507 000-507 + ASMA Ver. 0.2.0 ieee-cvtfrfix.asm: Test IEEE Convert From Fixed (int-32) 08 Sep 2016 08:40:02 Page 17 + + STMT FILE NAME + +1 C:\Users\srorso\Documents\GitHub\hyperion\tests\bfp-010-cvtfrfix.asm + + +** NO ERRORS FOUND ** + +[448] MNOTE *,asma detected; no CSECT padding performed + \ No newline at end of file diff --git a/tests/bfp-010-cvtfrfix.tst b/tests/bfp-010-cvtfrfix.tst new file mode 100644 index 000000000..935505ff6 --- /dev/null +++ b/tests/bfp-010-cvtfrfix.tst @@ -0,0 +1,166 @@ +*Testcase bfp-010-cvtfrfix.tst: CEFBR, CEFBRA, CDFBR, CDFBRA, CXFBR, CXFBRA + +#Testcase bfp-010-cvtfrfix.tst: IEEE Convert From Fixed +#..Includes CONVERT FROM FIXED 32 (6). Also tests traps and +#..exceptions and results from different rounding modes. + +sysclear +archmode esame + +# +# Following suppresses logging of program checks. This test program, as part +# of its normal operation, generates 2 program check messages that have no +# value in the validation process. (The messages, not the program checks.) +# +ostailor quiet + +loadcore "$(testpath)/bfp-010-cvtfrfix.core" + +runtest 1.0 + +ostailor null # restore messages for subsequent tests + + +# Inputs converted to short BFP +*Compare +r 1000.10 +*Want "CEFBR result pairs 1-2" 3F800000 3F800000 40000000 40000000 +r 1010.10 +*Want "CEFBR result pairs 3-4" 40800000 40800000 C0000000 C0000000 +r 1020.10 +*Want "CEFBR result pairs 5-6" 4F000000 4F000000 CF000000 CF000000 +r 1030.08 +*Want "CEFBR result pair 7" 4EFFFFFF 4EFFFFFF + +# Inputs converted to short BFP - FPCR contents +*Compare +r 1100.10 +*Want "CEFBR FPC pairs 1-2" 00000000 F8000000 00000000 F8000000 +r 1110.10 +*Want "CEFBR FPC pairs 3-4" 00000000 F8000000 00000000 F8000000 +r 1120.10 +*Want "CEFBR FPC pairs 5-6" 00080000 F8000C00 00080000 F8000C00 +r 1130.08 +*Want "CEFBR FPC pair 7" 00000000 F8000000 + + +# Short BFP rounding mode tests - FPCR & M3 modes, positive & negative inputs +*Compare +r 1200.10 # RZ RP RM RFS +*Want "CEFBRA RU FPC modes 1-3, 7" 4EFFFFFF 4F000000 4EFFFFFF 4EFFFFFF +r 1210.10 # RNTA RFS RNTE RZ +*Want "CEFBRA RU M3 modes 1, 3-5" 4F000000 4EFFFFFF 4F000000 4EFFFFFF +r 1220.08 # RP RM +*Want "CEFBRA RU M3 modes 6, 7" 4F000000 4EFFFFFF + +r 1230.10 # RZ RP RM RFS +*Want "CEFBRA Tie FPC modes 1-3, 7" 4EFFFFFF 4F000000 4EFFFFFF 4EFFFFFF +r 1240.10 # RNTA RFS RNTE RZ +*Want "CEFBRA Tie M3 modes 1, 3-5" 4F000000 4EFFFFFF 4F000000 4EFFFFFF +r 1250.08 # RP RM +*Want "CEFBRA Tie M3 modes 6, 7" 4F000000 4EFFFFFF + +r 1260.10 # RZ RP RM RFS +*Want "CEFBRA RD FPC modes 1-3, 7" 4EFFFFFF 4F000000 4EFFFFFF 4EFFFFFF +r 1270.10 # RNTA RFS RNTE RZ +*Want "CEFBRA RD M3 modes 1, 3-5" 4EFFFFFF 4EFFFFFF 4EFFFFFF 4EFFFFFF +r 1280.08 # RP RM +*Want "CEFBRA RD M3 modes 6, 7" 4F000000 4EFFFFFF + +*Compare +r 1500.10 # RZ RP RM RFS +*Want "CEFBRA RU FPC modes 1-3, 7 FCPR" 00000001 00000002 00000003 00000007 +r 1510.10 # RNTA RFS RNTE RZ +*Want "CEFBRA RU M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 1520.08 # RP RM +*Want "CEFBRA RU M3 modes 6, 7 FPCR" 00080000 00080000 + +r 1530.10 # RZ RP RM RFS +*Want "CEFBRA Tie FPC modes 1-3, 7 FPCR" 00000001 00000002 00000003 00000007 +r 1540.10 # RNTA RFS RNTE RZ +*Want "CEFBRA Tie M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 1550.08 # RP RM +*Want "CEFBRA Tie M3 modes 6, 7 FPCR" 00080000 00080000 + +r 1560.10 # RZ RP RM RFS +*Want "CEFBRA RD FPC modes 1-3, 7 FPCR" 00000001 00000002 00000003 00000007 +r 1570.10 # RNTA RFS RNTE RZ +*Want "CEFBRA RD M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 1580.08 # RP RM +*Want "CEFBRA RD M3 modes 6, 7 FPCR" 00080000 00080000 + + +# Inputs converted to long BFP +*Compare +r 2000.10 +*Want "CDFBR result pair 1" 3FF00000 00000000 3FF00000 00000000 +r 2010.10 +*Want "CDFBR result pair 2" 40000000 00000000 40000000 00000000 +r 2020.10 +*Want "CDFBR result pair 3" 40100000 00000000 40100000 00000000 +r 2030.10 +*Want "CDFBR result pair 4" C0000000 00000000 C0000000 00000000 +r 2040.10 +*Want "CDFBR result pair 5" 41DFFFFF FFC00000 41DFFFFF FFC00000 +r 2050.10 +*Want "CDFBR result pair 6" C1DFFFFF FFC00000 C1DFFFFF FFC00000 +r 2060.10 +*Want "CDFBR result pair 7" 41DFFFFF E0000000 41DFFFFF E0000000 + +# Inputs converted to long BFP - FPCR contents +*Compare +r 2100.10 +*Want "CDFBR FPC pairs 1-2" 00000000 F8000000 00000000 F8000000 +r 2110.10 +*Want "CDFBR FPC pairs 3-4" 00000000 F8000000 00000000 F8000000 +r 2120.10 +*Want "CDFBR FPC pairs 5-6" 00000000 F8000000 00000000 F8000000 +r 2130.08 +*Want "CDFBR FPC pair 7" 00000000 F8000000 + + +# Inputs converted to extended BFP +*Compare +r 3000.10 +*Want "CXFBR result 1a" 3FFF0000 00000000 00000000 00000000 +r 3010.10 +*Want "CXFBR result 1b" 3FFF0000 00000000 00000000 00000000 +r 3020.10 +*Want "CXFBR result 2a" 40000000 00000000 00000000 00000000 +r 3030.10 +*Want "CXFBR result 2b" 40000000 00000000 00000000 00000000 +r 3040.10 +*Want "CXFBR result 3a" 40010000 00000000 00000000 00000000 +r 3050.10 +*Want "CXFBR result 3b" 40010000 00000000 00000000 00000000 +r 3060.10 +*Want "CXFBR result 4a" C0000000 00000000 00000000 00000000 +r 3070.10 +*Want "CXFBR result 4b" C0000000 00000000 00000000 00000000 +r 3080.10 +*Want "CXFBR result 5a" 401DFFFF FFFC0000 00000000 00000000 +r 3090.10 +*Want "CXFBR result 5b" 401DFFFF FFFC0000 00000000 00000000 +r 30A0.10 +*Want "CXFBR result 6a" C01DFFFF FFFC0000 00000000 00000000 +r 30B0.10 +*Want "CXFBR result 6b" C01DFFFF FFFC0000 00000000 00000000 +r 30C0.10 +*Want "CXFBR result 7a" 401DFFFF FE000000 00000000 00000000 +r 30D0.10 +*Want "CXFBR result 7b" 401DFFFF FE000000 00000000 00000000 + +# Inputs converted to extended BFP - FPCR contents +*Compare +r 3200.10 +*Want "CXFBR FPC pairs 1-2" 00000000 F8000000 00000000 F8000000 +r 3210.10 +*Want "CXFBR FPC pairs 3-4" 00000000 F8000000 00000000 F8000000 +r 3220.10 +*Want "CXFBR FPC pairs 5-6" 00000000 F8000000 00000000 F8000000 +r 3230.08 +*Want "CXFBR FPC pair 7" 00000000 F8000000 + + +*Done + diff --git a/tests/bfp-011-cvtfrfix64.asm b/tests/bfp-011-cvtfrfix64.asm new file mode 100644 index 000000000..129dc1c1e --- /dev/null +++ b/tests/bfp-011-cvtfrfix64.asm @@ -0,0 +1,628 @@ + TITLE 'bfp-011-cvtfrfix64.asm: Test IEEE Cvt From Fixed (int-64)' +*********************************************************************** +* +*Testcase IEEE CONVERT FROM FIXED 64 +* Test case capability includes ieee exceptions trappable and +* otherwise. Test result, FPCR flags, and DXC saved for all tests. +* Convert From Fixed does not set the condition code. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* bfp-011-cvtfrfix64.asm +* +* This assembly-language source file is part of the +* Hercules Decimal Floating Point Validation Package +* by Stephen R. Orso +* +* Copyright 2016 by Stephen R Orso. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* +* 3. The name of the author may not be used to endorse or promote +* products derived from this software without specific prior written +* permission. +* +* DISCLAMER: THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* HOLDER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* Tests the following six conversion instructions +* CONVERT FROM FIXED (64 to short BFP, RRE) +* CONVERT FROM FIXED (64 to long BFP, RRE) +* CONVERT FROM FIXED (64 to extended BFP, RRE) +* CONVERT FROM FIXED (64 to short BFP, RRF-e) +* CONVERT FROM FIXED (64 to long BFP, RRF-e) +* CONVERT FROM FIXED (64 to extended BFP, RRF-e) +* +* Test data is compiled into this program. The test script that runs +* this program can provide alternative test data through Hercules R +* commands. +* +* Test Case Order +* 1) Int-32 to Short BFP +* 2) Int-32 to Short BFP with all rounding modes +* 3) Int-32 to Long BFP +* 4) Int-32 to Long BFP with all rounding modes +* 5) Int-32 to Extended BFP +* +* Provided test data: +* 1, 2, 4, -2, +* 9 223 372 036 854 775 807 (0x7FFFFFFFFFFF) +* -9 223 372 036 854 775 807 (0x800000000000) +* The last two values trigger inexact exceptions when converted +* to long or short BFP and are used to exhaustively test +* operation of the various rounding modes. Int-64 to extended +* BFP is always exact. +* +* Also tests the following floating point support instructions +* LOAD (Short) +* LOAD (Long) +* LOAD FPC +* SET BFP ROUNDING MODE 2-BIT +* SET BFP ROUNDING MODE 3-BIT +* STORE (Short) +* STORE (Long) +* STORE FPC +* +*********************************************************************** + SPACE 3 + SPACE 2 + MACRO + PADCSECT &ENDLABL +.* +.* Macro to pad the CSECT to include result data areas if this test +.* program is not being assembled using asma. asma generates a core +.* image that is loaded by the loadcore command, and because the +.* core image is a binary stored in Github, it makes sense to make +.* this small effort to keep the core image small. +.* + AIF (D'&ENDLABL).GOODPAD + MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + MNOTE *,'No CSECT padding performed' + MEXIT +.* +.GOODPAD ANOP Label valid. See if we're on asma + AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + ORG &ENDLABL-1 Not ASMA. Pad CSECT + MEXIT +.* +.NOPAD ANOP + MNOTE *,'asma detected; no CSECT padding performed' + MEND +* +* Note: for compatibility with the z/CMS test rig, do not change +* or use R11, R14, or R15. Everything else is fair game. +* +BFPCVTFF START 0 +STRTLABL EQU * +R0 EQU 0 Work register for cc extraction +R1 EQU 1 +R2 EQU 2 Holds count of test input values +R3 EQU 3 Points to next test input value(s) +R4 EQU 4 Available +R5 EQU 5 Available +R6 EQU 6 Available +R7 EQU 7 Pointer to next result value(s) +R8 EQU 8 Pointer to next FPCR result +R9 EQU 9 Rounding tests top of outer loop +R10 EQU 10 Pointer to test address list +R11 EQU 11 **Reserved for z/CMS test rig +R12 EQU 12 Holds number of test cases in set +R13 EQU 13 Mainline return address +R14 EQU 14 **Return address for z/CMS test rig +R15 EQU 15 **Base register on z/CMS or Hyperion +* +* Floating Point Register equates to keep the cross reference clean +* +FPR0 EQU 0 +FPR1 EQU 1 +FPR2 EQU 2 +FPR3 EQU 3 +FPR4 EQU 4 +FPR5 EQU 5 +FPR6 EQU 6 +FPR7 EQU 7 +FPR8 EQU 8 +FPR9 EQU 9 +FPR10 EQU 10 +FPR11 EQU 11 +FPR12 EQU 12 +FPR13 EQU 13 +FPR14 EQU 14 +FPR15 EQU 15 +* + USING *,R15 +* +* Above works on real iron (R15=0 after sysclear) +* and in z/CMS (R15 points to start of load module) +* + SPACE 2 +*********************************************************************** +* +* Low core definitions, Restart PSW, and Program Check Routine. +* +*********************************************************************** + SPACE 2 + ORG STRTLABL+X'8E' Program check interrution code +PCINTCD DS H +* +PCOLDPSW EQU STRTLABL+X'150' z/Arch Program check old PSW +* + ORG STRTLABL+X'1A0' z/Arch Restart PSW + DC X'0000000180000000',AD(START) +* + ORG STRTLABL+X'1D0' z/Arch Program check old PSW + DC X'0000000000000000',AD(PROGCHK) +* +* Program check routine. If Data Exception, continue execution at +* the instruction following the program check. Otherwise, hard wait. +* No need to collect data. All interesting DXC stuff is captured +* in the FPCR. +* + ORG STRTLABL+X'200' +PROGCHK DS 0H Program check occured... + CLI PCINTCD+1,X'07' Data Exception? + JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) + LPSWE PCOLDPSW ..yes, resume program execution +PCNOTDTA DS 0H + LTR R14,R14 Return address provided? + BNZR R14 Yes, return to z/CMS test rig. + LPSWE HARDWAIT Not data exception, enter disabled wait + EJECT +*********************************************************************** +* +* Main program. Enable Advanced Floating Point, process test cases. +* +START STCTL R0,R0,CTLR0 Store CR0 to enable AFP + OI CTLR0+1,X'04' Turn on AFP bit + LCTL R0,R0,CTLR0 Reload updated CR0 +* + LA R10,SHORTS Point to int-64 test inputs + BAS R13,CEGBR Convert values from fixed to short BFP + LA R10,RMSHORTS Point to inputs for rounding mode tests + BAS R13,CEGBRA Convert to short BFP using rm options +* + LA R10,LONGS Point to int-64 test inputs + BAS R13,CDGBR Convert values from fixed to long BFP + LA R10,RMLONGS Point to inputs for rounding mode tests + BAS R13,CDGBRA Convert to long BFP using rm options +* + LA R10,EXTDS Point to int-64 test inputs + BAS R13,CXGBR Convert values from fixed to extended +* + LTR R14,R14 Return address provided? + BNZR R14 ..Yes, return to z/CMS test rig. + LPSWE WAITPSW All done +* + DS 0D Ensure correct alignment for psw +WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end +* +CTLR0 DS F +FPCREGNT DC X'00000000' FPCR Reg IEEE exceptions Not Trappable +FPCREGTR DC X'F8000000' FPCR Reg IEEE exceptions TRappable +* +* Input values parameter list, four fullwords: +* 1) Count, +* 2) Address of inputs, +* 3) Address to place results, and +* 4) Address to place DXC/Flags/cc values. +* + ORG STRTLABL+X'280' +SHORTS DS 0F int-64 inputs for short BFP testing + DC A(INTCOUNT) + DC A(INTIN) + DC A(SBFPOUT) + DC A(SBFPFLGS) +* +LONGS DS 0F int-64 inputs for long BFP testing + DC A(INTCOUNT) + DC A(INTIN) + DC A(LBFPOUT) + DC A(LBFPFLGS) +* +EXTDS DS 0F int-64 inputs for Extended BFP testing + DC A(INTCOUNT) + DC A(INTIN) + DC A(XBFPOUT) + DC A(XBFPFLGS) +* +RMSHORTS DS 0F int-64's for short BFP rounding mode tests + DC A(SINTRMCT) + DC A(SINTRMIN) Last two int-64 are only concerns + DC A(SBFPRMO) Space for rounding mode results + DC A(SBFPRMOF) Space for rounding mode FPCR contents +* +RMLONGS DS 0F int-64's for long BFP rounding mode tests + DC A(LINTRMCT) + DC A(LINTRMIN) Last two int-64 are only concerns + DC A(LBFPRMO) Space for rounding mode results + DC A(LBFPRMOF) Space for rounding mode FPCR contents + EJECT +*********************************************************************** +* +* Convert int-64 to short BFP format. A pair of results is generated +* for each input: one with all exceptions non-trappable, and the second +* with all exceptions trappable. The FPCR is stored for each result. +* +*********************************************************************** + SPACE 3 + +CEGBR LM R2,R3,0(R10) Get count and address of test input values + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + LM R7,R8,8(R10) Get address of result area and flag area. + BASR R12,0 Set top of loop +* + LG R1,0(,R3) Get integer test value + LFPC FPCREGNT Set exceptions non-trappable + CEGBR FPR8,R1 Cvt Int in GPR1 to float in FPFPR8 + STE FPR8,0(,R7) Store short BFP result + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + CEGBR FPR8,R1 Cvt Int in GPR1 to float in FPFPR8 + STE FPR8,4(,R7) Store short BFP result + STFPC 4(R8) Store resulting FPCR flags and DXC + LA R3,8(,R3) Point to next input values + LA R7,8(,R7) Point to next short BFP converted values + LA R8,8(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. +* +* Convert int-64 to short BFP format using each possible rounding mode. +* Ten test results are generated for each input. A 48-byte test result +* section is used to keep results sets aligned on a quad-double word. +* +* The first four tests use rounding modes specified in the FPCR with +* the IEEE Inexact exception supressed. SRNM (2-bit) is used for the +* first two FPCR-controlled tests and SRNMB (3-bit) is used for the +* last two to get full coverage of that instruction pair. +* +* The next six results use instruction-specified rounding modes. +* +* The default rounding mode (0 for RNTE) is not tested in this section; +* prior tests used the default rounding mode. RNTE is tested +* explicitly as a rounding mode in this section. +* +CEGBRA LM R2,R3,0(R10) Get count and address of test input values + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + LM R7,R8,8(R10) Get address of result area and flag area. + BASR R12,0 Set top of loop +* + LG R1,0(,R3) Get int-64 test value +* +* Convert the Int-64 in GPR1 to float-64 in FPR8 using the rounding +* mode specified in the FPCR. Mask inexact exceptions. +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 1 SET FPCR to RZ, towards zero. + CEGBRA FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked + STD FPR8,0*4(,R7) Store short BFP result + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 2 SET FPCR to RP, to +infinity + CEGBRA FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked + STD FPR8,1*4(,R7) Store short BFP result + STFPC 1*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 3 SET FPCR to RM, to -infinity + CEGBRA FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked + STD FPR8,2*4(,R7) Store short BFP result + STFPC 2*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 7 RPS, Prepare for Shorter Precision + CEGBRA FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked + STD FPR8,3*4(,R7) Store short BFP result + STFPC 3*4(R8) Store resulting FPCR flags and DXC +* +* Convert the Int-64 in GPR1 to float-64 in FPFPR8 using the rounding +* mode specified in the M3 field of the instruction. +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CEGBRA FPR8,1,R1,B'0000' RNTA, to nearest, ties away + STE FPR8,4*4(,R7) Store short BFP result + STFPC 4*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CEGBRA FPR8,3,R1,B'0000' RPS, prepare for shorter precision + STE FPR8,5*4(,R7) Store short BFP result + STFPC 5*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CEGBRA FPR8,4,R1,B'0000' RNTE, to nearest, ties to even + STE FPR8,6*4(,R7) Store short BFP result + STFPC 6*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CEGBRA FPR8,5,R1,B'0000' RZ, toward zero + STE FPR8,7*4(,R7) Store short BFP result + STFPC 7*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CEGBRA FPR8,6,R1,B'0000' RP, to +inf + STE FPR8,8*4(,R7) Store short BFP result + STFPC 8*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CEGBRA FPR8,7,R1,B'0000' RM, to -inf + STE FPR8,9*4(,R7) Store short BFP result + STFPC 9*4(R8) Store resulting FPCR flags and DXC +* + LA R3,8(,R3) Point to next input value + LA R7,12*4(,R7) Point to next short BFP rounded set + LA R8,12*4(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert int-64 to long BFP format. A pair of results is generated +* for each input: one with all exceptions non-trappable, and the second +* with all exceptions trappable. The FPCR is stored for each result. +* Conversion of a 32-bit integer to long is always exact; no exceptions +* are expected +* +*********************************************************************** + SPACE 3 +CDGBR LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LG R1,0(,R3) Get integer test value + LFPC FPCREGNT Set exceptions non-trappable + CDGBR FPR8,R1 Cvt Int in GPR1 to float in FPFPR8 + STD FPR8,0(,R7) Store long BFP result + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + CDGBR FPR8,R1 Cvt Int in GPR1 to float in FPFPR8 + STD FPR8,8(,R7) Store long BFP result + STFPC 4(R8) Store resulting FPCR flags and DXC + LA R3,8(,R3) point to next input value + LA R7,16(,R7) Point to next long BFP converted value + LA R8,8(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. +* +* Convert int-64 to long BFP format using each possible rounding mode. +* Ten test results are generated for each input. A 48-byte test result +* section is used to keep results sets aligned on a quad-double word. +* +* The first four tests use rounding modes specified in the FPCR with +* the IEEE Inexact exception supressed. SRNM (2-bit) is used for the +* first two FPCR-controlled tests and SRNMB (3-bit) is used for the +* last two to get full coverage of that instruction pair. +* +* The next six results use instruction-specified rounding modes. +* +* The default rounding mode (0 for RNTE) is not tested in this section; +* prior tests used the default rounding mode. RNTE is tested +* explicitly as a rounding mode in this section. +* +CDGBRA LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LG R1,0(,R3) Get int-64 test value +* +* Convert the Int-64 in GPR1 to float-64 in FPR8 using the rounding +* mode specified in the FPCR. Mask inexact exceptions. +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 1 SET FPCR to RZ, towards zero. + CDGBRA FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked + STD FPR8,0*8(,R7) Store long BFP result + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNM 2 SET FPCR to RP, to +infinity + CDGBRA FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked + STD FPR8,1*8(,R7) Store long BFP result + STFPC 1*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 3 SET FPCR to RM, to -infinity + CDGBRA FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked + STD FPR8,2*8(,R7) Store long BFP result + STFPC 2*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 7 RPS, Prepare for Shorter Precision + CDGBRA FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked + STD FPR8,3*8(,R7) Store long BFP result + STFPC 3*4(R8) Store resulting FPCR flags and DXC +* +* Convert the Int-64 in GPR1 to float-64 in FPFPR8 using the rounding +* mode specified in the M3 field of the instruction. +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CDGBRA FPR8,1,R1,B'0000' RNTA, to nearest, ties away + STD FPR8,4*8(,R7) Store long BFP result + STFPC 4*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CDGBRA FPR8,3,R1,B'0000' RPS, prepare for shorter precision + STD FPR8,5*8(,R7) Store long BFP result + STFPC 5*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CDGBRA FPR8,4,R1,B'0000' RNTE, to nearest, ties to even + STD FPR8,6*8(,R7) Store long BFP result + STFPC 6*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CDGBRA FPR8,5,R1,B'0000' RZ, toward zero + STD FPR8,7*8(,R7) Store long BFP result + STFPC 7*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CDGBRA FPR8,6,R1,B'0000' RP, to +inf + STD FPR8,8*8(,R7) Store long BFP result + STFPC 8*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + CDGBRA FPR8,7,R1,B'0000' RM, to -inf + STD FPR8,9*8(,R7) Store long BFP result + STFPC 9*4(R8) Store resulting FPCR flags and DXC +* + LA R3,8(,R3) Point to next input value + LA R7,10*8(,R7) Point to next long BFP rounded value set + LA R8,12*4(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert int-64 to extended BFP format. A pair of results is +* generated * for each input: one with all exceptions non-trappable, +* and the second with all exceptions trappable. The FPCR is stored +* for each result. Conversion of an int-64to extended is always exact; +* no exceptions are expected. +* +*********************************************************************** + SPACE 3 +CXGBR LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LG R1,0(,R3) Get integer test value + LFPC FPCREGNT Set exceptions non-trappable + CXGBR FPR8,R1 Cvt Int in GPR1 to float in FPR8-FPR10 + STD FPR8,0(,R7) Store extended BFP result part 1 + STD FPR10,8(,R7) Store extended BFP result part 2 + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + CXGBR FPR8,R1 Cvt Int in GPR1 to float in FPR8-FPR10 + STD FPR8,16(,R7) Store extended BFP result part 1 + STD FPR10,24(,R7) Store extended BFP result part 2 + STFPC 4(R8) Store resulting FPCR flags and DXC + LA R3,8(,R3) Point to next input value + LA R7,32(,R7) Point to next extended BFP converted value + LA R8,8(,R8) Point to next FPCR/CC result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Int-64 inputs for Convert From Fixed testing. The same set of +* inputs are used for short, long, and extended formats. The last two +* values are used for rounding mode tests for short and long only; +* conversion of int-64 to extended is always exact. +* +*********************************************************************** + SPACE 3 +INTIN DS 0D + DC FD'1' + DC FD'2' + DC FD'4' + DC FD'-2' X'FFFFFFFF FFFFFFFE' +* +* Below inexact and incre. for short & long + DC FD'9223372036854775807' X'7FFFFFFF FFFFFFFF' + DC FD'-9223372036854775807' X'80000000 00000001' +* +* Below exact for all + DC FD'9223371487098961920' X'7FFFFF80 00000000' + DC FD'-9223371487098961920' X'80000080 00000000' +* +* Below exact for long and extended + DC FD'9223372036854774784' X'7FFFFFFF FFFFFC00' + DC FD'-9223372036854774784' X'80000000 00000400' +INTCOUNT EQU (*-INTIN)/8 Count of int-64 input values +* +* int-64 inputs for exhaustive short BFP rounding mode tests +* +SINTRMIN DS 0D Values for short BFP rounding tests +* Below rounds nearest away from zero + DC FD'9223371899415822336' X'7FFFFFE0 00000000' + DC FD'-9223371899415822336' X'80000020 00000000' +* Below rounds nearest tie + DC FD'9223371761976868864' X'7FFFFFC0 00000000' + DC FD'-9223371761976868864' X'80000040 00000000' +* Below rounds nearest toward zero + DC FD'9223371624537915392' X'7FFFFFA0 00000000' + DC FD'-9223371624537915392' X'80000060 00000000' +SINTRMCT EQU (*-SINTRMIN)/8 Count of int-64 for rounding tests +* +* int-64 inputs for exhaustive long BFP rounding mode tests +* +LINTRMIN DS 0D Values for short BFP rounding mode tests +* Below rounds nearest away from zero + DC FD'9223372036854775552' X'7FFFFFFF FFFFFF00' + DC FD'-9223372036854775552' X'80000000 00000100' +* Below rounds nearest tie + DC FD'9223372036854775296' X'7FFFFFFF FFFFFE00' + DC FD'-9223372036854775296' X'80000000 00000200' +* Below rounds nearest toward zero + DC FD'9223372036854775040' X'7FFFFFFF FFFFFD00' + DC FD'-9223372036854775040' X'80000000 00000300' +LINTRMCT EQU (*-LINTRMIN)/8 Count of int-64 for rounding tests +* +* Areas for resulting values and FPCR contents. +* +SBFPOUT EQU STRTLABL+X'1000' Int-64 results from short BFP inputs +* ..6 pairs used, room for 32 pairs +SBFPFLGS EQU STRTLABL+X'1100' FPCR flags and DXC from short BFP +* ..6 pairs used, room for 32 pairs +SBFPRMO EQU STRTLABL+X'1200' Short BFP rounding mode results +* ..2 sets used, room for 16 +SBFPRMOF EQU STRTLABL+X'1500' Short BFP rndg mode FPCR contents +* ..2 sets used, room for 32 +* ..next available location X'1600' +* +LBFPOUT EQU STRTLABL+X'2000' Int-64 results from long BFP inputs +* ..6 pairs used, room for 16 pairs +LBFPFLGS EQU STRTLABL+X'2100' Long BFP FPCR contents +* ..6 pairs used, room for 32 pairs +LBFPRMO EQU STRTLABL+X'2200' Long BFP rounding mode results +* ..2 sets used, room for 16 sets +LBFPRMOF EQU STRTLABL+X'2700' Long BFP rndg mode FPCR contents +* ..2 sets used, room for 16 sets +* ..next available location X'2A00' +* +XBFPOUT EQU STRTLABL+X'3000' Int-64 results from extended BFP +* ..6 pairs used, room for 16 pairs +XBFPFLGS EQU STRTLABL+X'3200' CLXBR restulting FPCR contents +* ..6 pairs used, room for 16 pairs +* ..next available location X'3300' +* +* +ENDLABL EQU STRTLABL+X'3200' + PADCSECT ENDLABL + END diff --git a/tests/bfp-011-cvtfrfix64.core b/tests/bfp-011-cvtfrfix64.core new file mode 100644 index 000000000..de6a7491e Binary files /dev/null and b/tests/bfp-011-cvtfrfix64.core differ diff --git a/tests/bfp-011-cvtfrfix64.list b/tests/bfp-011-cvtfrfix64.list new file mode 100644 index 000000000..45fee831b --- /dev/null +++ b/tests/bfp-011-cvtfrfix64.list @@ -0,0 +1,768 @@ +ASMA Ver. 0.2.0 ieee-cvtfrfix64.asm: Test IEEE Convert From Fixed (int-64) 13 Sep 2016 09:13:43 Page 1 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 2 *********************************************************************** + 3 * + 4 *Testcase IEEE CONVERT FROM FIXED 64 + 5 * Test case capability includes ieee exceptions trappable and + 6 * otherwise. Test result, FPCR flags, and DXC saved for all tests. + 7 * Convert From Fixed does not set the condition code. + 8 * + 9 *********************************************************************** + + + 11 *********************************************************************** + 12 * + 13 * Tests the following six conversion instructions + 14 * CONVERT FROM FIXED (64 to short BFP, RRE) + 15 * CONVERT FROM FIXED (64 to long BFP, RRE) + 16 * CONVERT FROM FIXED (64 to extended BFP, RRE) + 17 * CONVERT FROM FIXED (64 to short BFP, RRF-e) + 18 * CONVERT FROM FIXED (64 to long BFP, RRF-e) + 19 * CONVERT FROM FIXED (64 to extended BFP, RRF-e) + 20 * + 21 * Test data is compiled into this program. The test script that runs + 22 * this program can provide alternative test data through Hercules R + 23 * commands. + 24 * + 25 * Test Case Order + 26 * 1) Int-32 to Short BFP + 27 * 2) Int-32 to Short BFP with all rounding modes + 28 * 3) Int-32 to Long BFP + 29 * 4) Int-32 to Long BFP with all rounding modes + 30 * 5) Int-32 to Extended BFP + 31 * + 32 * Provided test data: + 33 * 1, 2, 4, -2, + 34 * 9 223 372 036 854 775 807 (0x7FFFFFFFFFFF) + 35 * -9 223 372 036 854 775 807 (0x800000000000) + 36 * The last two values trigger inexact exceptions when converted + 37 * to long or short BFP and are used to exhaustively test + 38 * operation of the various rounding modes. Int-64 to extended + 39 * BFP is always exact. + 40 * + 41 * Also tests the following floating point support instructions + 42 * LOAD (Short) + 43 * LOAD (Long) + 44 * LOAD FPC + 45 * SET BFP ROUNDING MODE 2-BIT + 46 * SET BFP ROUNDING MODE 3-BIT + 47 * STORE (Short) + 48 * STORE (Long) + 49 * STORE FPC + 50 * + 51 *********************************************************************** + ASMA Ver. 0.2.0 ieee-cvtfrfix64.asm: Test IEEE Convert From Fixed (int-64) 13 Sep 2016 09:13:43 Page 2 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + + + 54 MACRO + 55 PADCSECT &ENDLABL + 56 .* + 57 .* Macro to pad the CSECT to include result data areas if this test + 58 .* program is not being assembled using asma. asma generates a core + 59 .* image that is loaded by the loadcore command, and because the + 60 .* core image is a binary stored in Github, it makes sense to make + 61 .* this small effort to keep the core image small. + 62 .* + 63 AIF (D'&ENDLABL).GOODPAD + 64 MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + 65 MNOTE *,'No CSECT padding performed' + 66 MEXIT + 67 .* + 68 .GOODPAD ANOP Label valid. See if we're on asma + 69 AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + 70 ORG &ENDLABL-1 Not ASMA. Pad CSECT + 71 MEXIT + 72 .* + 73 .NOPAD ANOP + 74 MNOTE *,'asma detected; no CSECT padding performed' + 75 MEND + 76 * + 77 * Note: for compatibility with the z/CMS test rig, do not change + 78 * or use R11, R14, or R15. Everything else is fair game. + 79 * + 0000000000000000 00000000000005FF 80 BFPCVTFF START 0 + 0000000000000000 0000000000000001 81 STRTLABL EQU * + 0000000000000000 0000000000000001 82 R0 EQU 0 Work register for cc extraction + 0000000000000001 0000000000000001 83 R1 EQU 1 + 0000000000000002 0000000000000001 84 R2 EQU 2 Holds count of test input values + 0000000000000003 0000000000000001 85 R3 EQU 3 Points to next test input value(s) + 0000000000000004 0000000000000001 86 R4 EQU 4 Available + 0000000000000005 0000000000000001 87 R5 EQU 5 Available + 0000000000000006 0000000000000001 88 R6 EQU 6 Available + 0000000000000007 0000000000000001 89 R7 EQU 7 Pointer to next result value(s) + 0000000000000008 0000000000000001 90 R8 EQU 8 Pointer to next FPCR result + 0000000000000009 0000000000000001 91 R9 EQU 9 Rounding tests top of outer loop + 000000000000000A 0000000000000001 92 R10 EQU 10 Pointer to test address list + 000000000000000B 0000000000000001 93 R11 EQU 11 **Reserved for z/CMS test rig + 000000000000000C 0000000000000001 94 R12 EQU 12 Holds number of test cases in set + 000000000000000D 0000000000000001 95 R13 EQU 13 Mainline return address + 000000000000000E 0000000000000001 96 R14 EQU 14 **Return address for z/CMS test rig + 000000000000000F 0000000000000001 97 R15 EQU 15 **Base register on z/CMS or Hyperion + 98 * + 99 * Floating Point Register equates to keep the cross reference clean + 100 * + 0000000000000000 0000000000000001 101 FPR0 EQU 0 + 0000000000000001 0000000000000001 102 FPR1 EQU 1 + 0000000000000002 0000000000000001 103 FPR2 EQU 2 + ASMA Ver. 0.2.0 ieee-cvtfrfix64.asm: Test IEEE Convert From Fixed (int-64) 13 Sep 2016 09:13:43 Page 3 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 0000000000000003 0000000000000001 104 FPR3 EQU 3 + 0000000000000004 0000000000000001 105 FPR4 EQU 4 + 0000000000000005 0000000000000001 106 FPR5 EQU 5 + 0000000000000006 0000000000000001 107 FPR6 EQU 6 + 0000000000000007 0000000000000001 108 FPR7 EQU 7 + 0000000000000008 0000000000000001 109 FPR8 EQU 8 + 0000000000000009 0000000000000001 110 FPR9 EQU 9 + 000000000000000A 0000000000000001 111 FPR10 EQU 10 + 000000000000000B 0000000000000001 112 FPR11 EQU 11 + 000000000000000C 0000000000000001 113 FPR12 EQU 12 + 000000000000000D 0000000000000001 114 FPR13 EQU 13 + 000000000000000E 0000000000000001 115 FPR14 EQU 14 + 000000000000000F 0000000000000001 116 FPR15 EQU 15 + 117 * +0000000000000000 0000000000000000 118 USING *,R15 + 119 * + 120 * Above works on real iron (R15=0 after sysclear) + 121 * and in z/CMS (R15 points to start of load module) + 122 * + + + 124 *********************************************************************** + 125 * + 126 * Low core definitions, Restart PSW, and Program Check Routine. + 127 * + 128 *********************************************************************** + + +0000000000000000 0000000000000000 000000000000008E 130 ORG STRTLABL+X'8E' Program check interrution code +000000000000008E 0000 131 PCINTCD DS H + 132 * + 0000000000000150 0000000000000001 133 PCOLDPSW EQU STRTLABL+X'150' z/Arch Program check old PSW + 134 * +0000000000000090 0000000000000090 00000000000001A0 135 ORG STRTLABL+X'1A0' z/Arch Restart PSW +00000000000001A0 00000001 80000000 136 DC X'0000000180000000',AD(START) + 137 * +00000000000001B0 00000000000001B0 00000000000001D0 138 ORG STRTLABL+X'1D0' z/Arch Program check old PSW +00000000000001D0 00000000 00000000 139 DC X'0000000000000000',AD(PROGCHK) + 140 * + 141 * Program check routine. If Data Exception, continue execution at + 142 * the instruction following the program check. Otherwise, hard wait. + 143 * No need to collect data. All interesting DXC stuff is captured + 144 * in the FPCR. + 145 * +00000000000001E0 00000000000001E0 0000000000000200 146 ORG STRTLABL+X'200' +0000000000000200 147 PROGCHK DS 0H Program check occured... +0000000000000200 9507 F08F 000000000000008F 148 CLI PCINTCD+1,X'07' Data Exception? +0000000000000204 A774 0004 000000000000020C 149 JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) +0000000000000208 B2B2 F150 0000000000000150 150 LPSWE PCOLDPSW ..yes, resume program execution +000000000000020C 151 PCNOTDTA DS 0H +000000000000020C 12EE 152 LTR R14,R14 Return address provided? +000000000000020E 077E 153 BNZR R14 Yes, return to z/CMS test rig. + ASMA Ver. 0.2.0 ieee-cvtfrfix64.asm: Test IEEE Convert From Fixed (int-64) 13 Sep 2016 09:13:43 Page 4 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000210 B2B2 F260 0000000000000260 154 LPSWE HARDWAIT Not data exception, enter disabled wait + ASMA Ver. 0.2.0 ieee-cvtfrfix64.asm: Test IEEE Convert From Fixed (int-64) 13 Sep 2016 09:13:43 Page 5 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 156 *********************************************************************** + 157 * + 158 * Main program. Enable Advanced Floating Point, process test cases. + 159 * +0000000000000214 B600 F270 0000000000000270 160 START STCTL R0,R0,CTLR0 Store CR0 to enable AFP +0000000000000218 9604 F271 0000000000000271 161 OI CTLR0+1,X'04' Turn on AFP bit +000000000000021C B700 F270 0000000000000270 162 LCTL R0,R0,CTLR0 Reload updated CR0 + 163 * +0000000000000220 41A0 F280 0000000000000280 164 LA R10,SHORTS Point to int-64 test inputs +0000000000000224 4DD0 F2D0 00000000000002D0 165 BAS R13,CEGBR Convert values from fixed to short BFP +0000000000000228 41A0 F2B0 00000000000002B0 166 LA R10,RMSHORTS Point to inputs for rounding mode tests +000000000000022C 4DD0 F314 0000000000000314 167 BAS R13,CEGBRA Convert to short BFP using rm options + 168 * +0000000000000230 41A0 F290 0000000000000290 169 LA R10,LONGS Point to int-64 test inputs +0000000000000234 4DD0 F3E8 00000000000003E8 170 BAS R13,CDGBR Convert values from fixed to long BFP +0000000000000238 41A0 F2C0 00000000000002C0 171 LA R10,RMLONGS Point to inputs for rounding mode tests +000000000000023C 4DD0 F42C 000000000000042C 172 BAS R13,CDGBRA Convert to long BFP using rm options + 173 * +0000000000000240 41A0 F2A0 00000000000002A0 174 LA R10,EXTDS Point to int-64 test inputs +0000000000000244 4DD0 F500 0000000000000500 175 BAS R13,CXGBR Convert values from fixed to extended + 176 * +0000000000000248 12EE 177 LTR R14,R14 Return address provided? +000000000000024A 077E 178 BNZR R14 ..Yes, return to z/CMS test rig. +000000000000024C B2B2 F250 0000000000000250 179 LPSWE WAITPSW All done + 180 * +0000000000000250 181 DS 0D Ensure correct alignment for psw +0000000000000250 00020000 00000000 182 WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +0000000000000260 00020000 00000000 183 HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end + 184 * +0000000000000270 00000000 185 CTLR0 DS F +0000000000000274 00000000 186 FPCREGNT DC X'00000000' FPCR Reg IEEE exceptions Not Trappable +0000000000000278 F8000000 187 FPCREGTR DC X'F8000000' FPCR Reg IEEE exceptions TRappable + 188 * + 189 * Input values parameter list, four fullwords: + 190 * 1) Count, + 191 * 2) Address of inputs, + 192 * 3) Address to place results, and + 193 * 4) Address to place DXC/Flags/cc values. + 194 * +000000000000027C 000000000000027C 0000000000000280 195 ORG STRTLABL+X'280' +0000000000000280 196 SHORTS DS 0F int-64 inputs for short BFP testing +0000000000000280 0000000A 197 DC A(INTCOUNT) +0000000000000284 00000550 198 DC A(INTIN) +0000000000000288 00001000 199 DC A(SBFPOUT) +000000000000028C 00001100 200 DC A(SBFPFLGS) + 201 * +0000000000000290 202 LONGS DS 0F int-64 inputs for long BFP testing +0000000000000290 0000000A 203 DC A(INTCOUNT) +0000000000000294 00000550 204 DC A(INTIN) +0000000000000298 00002000 205 DC A(LBFPOUT) +000000000000029C 00002100 206 DC A(LBFPFLGS) + 207 * + ASMA Ver. 0.2.0 ieee-cvtfrfix64.asm: Test IEEE Convert From Fixed (int-64) 13 Sep 2016 09:13:43 Page 6 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000002A0 208 EXTDS DS 0F int-64 inputs for Extended BFP testing +00000000000002A0 0000000A 209 DC A(INTCOUNT) +00000000000002A4 00000550 210 DC A(INTIN) +00000000000002A8 00003000 211 DC A(XBFPOUT) +00000000000002AC 00003200 212 DC A(XBFPFLGS) + 213 * +00000000000002B0 214 RMSHORTS DS 0F int-64's for short BFP rounding mode tests +00000000000002B0 00000006 215 DC A(SINTRMCT) +00000000000002B4 000005A0 216 DC A(SINTRMIN) Last two int-64 are only concerns +00000000000002B8 00001200 217 DC A(SBFPRMO) Space for rounding mode results +00000000000002BC 00001500 218 DC A(SBFPRMOF) Space for rounding mode FPCR contents + 219 * +00000000000002C0 220 RMLONGS DS 0F int-64's for long BFP rounding mode tests +00000000000002C0 00000006 221 DC A(LINTRMCT) +00000000000002C4 000005D0 222 DC A(LINTRMIN) Last two int-64 are only concerns +00000000000002C8 00002200 223 DC A(LBFPRMO) Space for rounding mode results +00000000000002CC 00002700 224 DC A(LBFPRMOF) Space for rounding mode FPCR contents + ASMA Ver. 0.2.0 ieee-cvtfrfix64.asm: Test IEEE Convert From Fixed (int-64) 13 Sep 2016 09:13:43 Page 7 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 226 *********************************************************************** + 227 * + 228 * Convert int-64 to short BFP format. A pair of results is generated + 229 * for each input: one with all exceptions non-trappable, and the second + 230 * with all exceptions trappable. The FPCR is stored for each result. + 231 * + 232 *********************************************************************** + + + + 234 +00000000000002D0 9823 A000 0000000000000000 235 CEGBR LM R2,R3,0(R10) Get count and address of test input values +00000000000002D4 1222 236 LTR R2,R2 Any test cases? +00000000000002D6 078D 237 BZR R13 ..No, return to caller +00000000000002D8 9878 A008 0000000000000008 238 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000002DC 0DC0 239 BASR R12,0 Set top of loop + 240 * +00000000000002DE E310 3000 0004 0000000000000000 241 LG R1,0(,R3) Get integer test value +00000000000002E4 B29D F274 0000000000000274 242 LFPC FPCREGNT Set exceptions non-trappable +00000000000002E8 B3A4 0081 243 CEGBR FPR8,R1 Cvt Int in GPR1 to float in FPFPR8 +00000000000002EC 7080 7000 0000000000000000 244 STE FPR8,0(,R7) Store short BFP result +00000000000002F0 B29C 8000 0000000000000000 245 STFPC 0(R8) Store resulting FPCR flags and DXC + 246 * +00000000000002F4 B29D F278 0000000000000278 247 LFPC FPCREGTR Set exceptions trappable +00000000000002F8 B3A4 0081 248 CEGBR FPR8,R1 Cvt Int in GPR1 to float in FPFPR8 +00000000000002FC 7080 7004 0000000000000004 249 STE FPR8,4(,R7) Store short BFP result +0000000000000300 B29C 8004 0000000000000004 250 STFPC 4(R8) Store resulting FPCR flags and DXC +0000000000000304 4130 3008 0000000000000008 251 LA R3,8(,R3) Point to next input values +0000000000000308 4170 7008 0000000000000008 252 LA R7,8(,R7) Point to next short BFP converted values +000000000000030C 4180 8008 0000000000000008 253 LA R8,8(,R8) Point to next FPCR/CC result area +0000000000000310 062C 254 BCTR R2,R12 Convert next input value. +0000000000000312 07FD 255 BR R13 All converted; return. + 256 * + 257 * Convert int-64 to short BFP format using each possible rounding mode. + 258 * Ten test results are generated for each input. A 48-byte test result + 259 * section is used to keep results sets aligned on a quad-double word. + 260 * + 261 * The first four tests use rounding modes specified in the FPCR with + 262 * the IEEE Inexact exception supressed. SRNM (2-bit) is used for the + 263 * first two FPCR-controlled tests and SRNMB (3-bit) is used for the + 264 * last two to get full coverage of that instruction pair. + 265 * + 266 * The next six results use instruction-specified rounding modes. + 267 * + 268 * The default rounding mode (0 for RNTE) is not tested in this section; + 269 * prior tests used the default rounding mode. RNTE is tested + 270 * explicitly as a rounding mode in this section. + 271 * +0000000000000314 9823 A000 0000000000000000 272 CEGBRA LM R2,R3,0(R10) Get count and address of test input values +0000000000000318 1222 273 LTR R2,R2 Any test cases? +000000000000031A 078D 274 BZR R13 ..No, return to caller +000000000000031C 9878 A008 0000000000000008 275 LM R7,R8,8(R10) Get address of result area and flag area. + ASMA Ver. 0.2.0 ieee-cvtfrfix64.asm: Test IEEE Convert From Fixed (int-64) 13 Sep 2016 09:13:43 Page 8 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000320 0DC0 276 BASR R12,0 Set top of loop + 277 * +0000000000000322 E310 3000 0004 0000000000000000 278 LG R1,0(,R3) Get int-64 test value + 279 * + 280 * Convert the Int-64 in GPR1 to float-64 in FPR8 using the rounding + 281 * mode specified in the FPCR. Mask inexact exceptions. + 282 * +0000000000000328 B29D F274 0000000000000274 283 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000032C B299 0001 0000000000000001 284 SRNM 1 SET FPCR to RZ, towards zero. +0000000000000330 B3A4 0481 285 CEGBRA FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked +0000000000000334 6080 7000 0000000000000000 286 STD FPR8,0*4(,R7) Store short BFP result +0000000000000338 B29C 8000 0000000000000000 287 STFPC 0(R8) Store resulting FPCR flags and DXC + 288 * +000000000000033C B29D F274 0000000000000274 289 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000340 B299 0002 0000000000000002 290 SRNM 2 SET FPCR to RP, to +infinity +0000000000000344 B3A4 0481 291 CEGBRA FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked +0000000000000348 6080 7004 0000000000000004 292 STD FPR8,1*4(,R7) Store short BFP result +000000000000034C B29C 8004 0000000000000004 293 STFPC 1*4(R8) Store resulting FPCR flags and DXC + 294 * +0000000000000350 B29D F274 0000000000000274 295 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000354 B2B8 0003 0000000000000003 296 SRNMB 3 SET FPCR to RM, to -infinity +0000000000000358 B3A4 0481 297 CEGBRA FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked +000000000000035C 6080 7008 0000000000000008 298 STD FPR8,2*4(,R7) Store short BFP result +0000000000000360 B29C 8008 0000000000000008 299 STFPC 2*4(R8) Store resulting FPCR flags and DXC + 300 * +0000000000000364 B29D F274 0000000000000274 301 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000368 B2B8 0007 0000000000000007 302 SRNMB 7 RPS, Prepare for Shorter Precision +000000000000036C B3A4 0481 303 CEGBRA FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked +0000000000000370 6080 700C 000000000000000C 304 STD FPR8,3*4(,R7) Store short BFP result +0000000000000374 B29C 800C 000000000000000C 305 STFPC 3*4(R8) Store resulting FPCR flags and DXC + 306 * + 307 * Convert the Int-64 in GPR1 to float-64 in FPFPR8 using the rounding + 308 * mode specified in the M3 field of the instruction. + 309 * +0000000000000378 B29D F274 0000000000000274 310 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000037C B3A4 1081 311 CEGBRA FPR8,1,R1,B'0000' RNTA, to nearest, ties away +0000000000000380 7080 7010 0000000000000010 312 STE FPR8,4*4(,R7) Store short BFP result +0000000000000384 B29C 8010 0000000000000010 313 STFPC 4*4(R8) Store resulting FPCR flags and DXC + 314 * +0000000000000388 B29D F274 0000000000000274 315 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000038C B3A4 3081 316 CEGBRA FPR8,3,R1,B'0000' RPS, prepare for shorter precision +0000000000000390 7080 7014 0000000000000014 317 STE FPR8,5*4(,R7) Store short BFP result +0000000000000394 B29C 8014 0000000000000014 318 STFPC 5*4(R8) Store resulting FPCR flags and DXC + 319 * +0000000000000398 B29D F274 0000000000000274 320 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000039C B3A4 4081 321 CEGBRA FPR8,4,R1,B'0000' RNTE, to nearest, ties to even +00000000000003A0 7080 7018 0000000000000018 322 STE FPR8,6*4(,R7) Store short BFP result +00000000000003A4 B29C 8018 0000000000000018 323 STFPC 6*4(R8) Store resulting FPCR flags and DXC + 324 * +00000000000003A8 B29D F274 0000000000000274 325 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000003AC B3A4 5081 326 CEGBRA FPR8,5,R1,B'0000' RZ, toward zero +00000000000003B0 7080 701C 000000000000001C 327 STE FPR8,7*4(,R7) Store short BFP result + ASMA Ver. 0.2.0 ieee-cvtfrfix64.asm: Test IEEE Convert From Fixed (int-64) 13 Sep 2016 09:13:43 Page 9 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000003B4 B29C 801C 000000000000001C 328 STFPC 7*4(R8) Store resulting FPCR flags and DXC + 329 * +00000000000003B8 B29D F274 0000000000000274 330 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000003BC B3A4 6081 331 CEGBRA FPR8,6,R1,B'0000' RP, to +inf +00000000000003C0 7080 7020 0000000000000020 332 STE FPR8,8*4(,R7) Store short BFP result +00000000000003C4 B29C 8020 0000000000000020 333 STFPC 8*4(R8) Store resulting FPCR flags and DXC + 334 * +00000000000003C8 B29D F274 0000000000000274 335 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000003CC B3A4 7081 336 CEGBRA FPR8,7,R1,B'0000' RM, to -inf +00000000000003D0 7080 7024 0000000000000024 337 STE FPR8,9*4(,R7) Store short BFP result +00000000000003D4 B29C 8024 0000000000000024 338 STFPC 9*4(R8) Store resulting FPCR flags and DXC + 339 * +00000000000003D8 4130 3008 0000000000000008 340 LA R3,8(,R3) Point to next input value +00000000000003DC 4170 7030 0000000000000030 341 LA R7,12*4(,R7) Point to next short BFP rounded set +00000000000003E0 4180 8030 0000000000000030 342 LA R8,12*4(,R8) Point to next FPCR/CC result area +00000000000003E4 062C 343 BCTR R2,R12 Convert next input value. +00000000000003E6 07FD 344 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvtfrfix64.asm: Test IEEE Convert From Fixed (int-64) 13 Sep 2016 09:13:43 Page 10 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 346 *********************************************************************** + 347 * + 348 * Convert int-64 to long BFP format. A pair of results is generated + 349 * for each input: one with all exceptions non-trappable, and the second + 350 * with all exceptions trappable. The FPCR is stored for each result. + 351 * Conversion of a 32-bit integer to long is always exact; no exceptions + 352 * are expected + 353 * + 354 *********************************************************************** + + + +00000000000003E8 9823 A000 0000000000000000 356 CDGBR LM R2,R3,0(R10) Get count and address of test input values +00000000000003EC 9878 A008 0000000000000008 357 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000003F0 1222 358 LTR R2,R2 Any test cases? +00000000000003F2 078D 359 BZR R13 ..No, return to caller +00000000000003F4 0DC0 360 BASR R12,0 Set top of loop + 361 * +00000000000003F6 E310 3000 0004 0000000000000000 362 LG R1,0(,R3) Get integer test value +00000000000003FC B29D F274 0000000000000274 363 LFPC FPCREGNT Set exceptions non-trappable +0000000000000400 B3A5 0081 364 CDGBR FPR8,R1 Cvt Int in GPR1 to float in FPFPR8 +0000000000000404 6080 7000 0000000000000000 365 STD FPR8,0(,R7) Store long BFP result +0000000000000408 B29C 8000 0000000000000000 366 STFPC 0(R8) Store resulting FPCR flags and DXC + 367 * +000000000000040C B29D F278 0000000000000278 368 LFPC FPCREGTR Set exceptions trappable +0000000000000410 B3A5 0081 369 CDGBR FPR8,R1 Cvt Int in GPR1 to float in FPFPR8 +0000000000000414 6080 7008 0000000000000008 370 STD FPR8,8(,R7) Store long BFP result +0000000000000418 B29C 8004 0000000000000004 371 STFPC 4(R8) Store resulting FPCR flags and DXC +000000000000041C 4130 3008 0000000000000008 372 LA R3,8(,R3) point to next input value +0000000000000420 4170 7010 0000000000000010 373 LA R7,16(,R7) Point to next long BFP converted value +0000000000000424 4180 8008 0000000000000008 374 LA R8,8(,R8) Point to next FPCR/CC result area +0000000000000428 062C 375 BCTR R2,R12 Convert next input value. +000000000000042A 07FD 376 BR R13 All converted; return. + 377 * + 378 * Convert int-64 to long BFP format using each possible rounding mode. + 379 * Ten test results are generated for each input. A 48-byte test result + 380 * section is used to keep results sets aligned on a quad-double word. + 381 * + 382 * The first four tests use rounding modes specified in the FPCR with + 383 * the IEEE Inexact exception supressed. SRNM (2-bit) is used for the + 384 * first two FPCR-controlled tests and SRNMB (3-bit) is used for the + 385 * last two to get full coverage of that instruction pair. + 386 * + 387 * The next six results use instruction-specified rounding modes. + 388 * + 389 * The default rounding mode (0 for RNTE) is not tested in this section; + 390 * prior tests used the default rounding mode. RNTE is tested + 391 * explicitly as a rounding mode in this section. + 392 * +000000000000042C 9823 A000 0000000000000000 393 CDGBRA LM R2,R3,0(R10) Get count and address of test input values +0000000000000430 9878 A008 0000000000000008 394 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000434 1222 395 LTR R2,R2 Any test cases? + ASMA Ver. 0.2.0 ieee-cvtfrfix64.asm: Test IEEE Convert From Fixed (int-64) 13 Sep 2016 09:13:43 Page 11 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000436 078D 396 BZR R13 ..No, return to caller +0000000000000438 0DC0 397 BASR R12,0 Set top of loop + 398 * +000000000000043A E310 3000 0004 0000000000000000 399 LG R1,0(,R3) Get int-64 test value + 400 * + 401 * Convert the Int-64 in GPR1 to float-64 in FPR8 using the rounding + 402 * mode specified in the FPCR. Mask inexact exceptions. + 403 * +0000000000000440 B29D F274 0000000000000274 404 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000444 B299 0001 0000000000000001 405 SRNM 1 SET FPCR to RZ, towards zero. +0000000000000448 B3A5 0481 406 CDGBRA FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked +000000000000044C 6080 7000 0000000000000000 407 STD FPR8,0*8(,R7) Store long BFP result +0000000000000450 B29C 8000 0000000000000000 408 STFPC 0(R8) Store resulting FPCR flags and DXC + 409 * +0000000000000454 B29D F274 0000000000000274 410 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000458 B299 0002 0000000000000002 411 SRNM 2 SET FPCR to RP, to +infinity +000000000000045C B3A5 0481 412 CDGBRA FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked +0000000000000460 6080 7008 0000000000000008 413 STD FPR8,1*8(,R7) Store long BFP result +0000000000000464 B29C 8004 0000000000000004 414 STFPC 1*4(R8) Store resulting FPCR flags and DXC + 415 * +0000000000000468 B29D F274 0000000000000274 416 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000046C B2B8 0003 0000000000000003 417 SRNMB 3 SET FPCR to RM, to -infinity +0000000000000470 B3A5 0481 418 CDGBRA FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked +0000000000000474 6080 7010 0000000000000010 419 STD FPR8,2*8(,R7) Store long BFP result +0000000000000478 B29C 8008 0000000000000008 420 STFPC 2*4(R8) Store resulting FPCR flags and DXC + 421 * +000000000000047C B29D F274 0000000000000274 422 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000480 B2B8 0007 0000000000000007 423 SRNMB 7 RPS, Prepare for Shorter Precision +0000000000000484 B3A5 0481 424 CDGBRA FPR8,0,R1,B'0100' FPCR ctl'd rounding, inexact masked +0000000000000488 6080 7018 0000000000000018 425 STD FPR8,3*8(,R7) Store long BFP result +000000000000048C B29C 800C 000000000000000C 426 STFPC 3*4(R8) Store resulting FPCR flags and DXC + 427 * + 428 * Convert the Int-64 in GPR1 to float-64 in FPFPR8 using the rounding + 429 * mode specified in the M3 field of the instruction. + 430 * +0000000000000490 B29D F274 0000000000000274 431 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000494 B3A5 1081 432 CDGBRA FPR8,1,R1,B'0000' RNTA, to nearest, ties away +0000000000000498 6080 7020 0000000000000020 433 STD FPR8,4*8(,R7) Store long BFP result +000000000000049C B29C 8010 0000000000000010 434 STFPC 4*4(R8) Store resulting FPCR flags and DXC + 435 * +00000000000004A0 B29D F274 0000000000000274 436 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000004A4 B3A5 3081 437 CDGBRA FPR8,3,R1,B'0000' RPS, prepare for shorter precision +00000000000004A8 6080 7028 0000000000000028 438 STD FPR8,5*8(,R7) Store long BFP result +00000000000004AC B29C 8014 0000000000000014 439 STFPC 5*4(R8) Store resulting FPCR flags and DXC + 440 * +00000000000004B0 B29D F274 0000000000000274 441 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000004B4 B3A5 4081 442 CDGBRA FPR8,4,R1,B'0000' RNTE, to nearest, ties to even +00000000000004B8 6080 7030 0000000000000030 443 STD FPR8,6*8(,R7) Store long BFP result +00000000000004BC B29C 8018 0000000000000018 444 STFPC 6*4(R8) Store resulting FPCR flags and DXC + 445 * +00000000000004C0 B29D F274 0000000000000274 446 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000004C4 B3A5 5081 447 CDGBRA FPR8,5,R1,B'0000' RZ, toward zero + ASMA Ver. 0.2.0 ieee-cvtfrfix64.asm: Test IEEE Convert From Fixed (int-64) 13 Sep 2016 09:13:43 Page 12 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000004C8 6080 7038 0000000000000038 448 STD FPR8,7*8(,R7) Store long BFP result +00000000000004CC B29C 801C 000000000000001C 449 STFPC 7*4(R8) Store resulting FPCR flags and DXC + 450 * +00000000000004D0 B29D F274 0000000000000274 451 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000004D4 B3A5 6081 452 CDGBRA FPR8,6,R1,B'0000' RP, to +inf +00000000000004D8 6080 7040 0000000000000040 453 STD FPR8,8*8(,R7) Store long BFP result +00000000000004DC B29C 8020 0000000000000020 454 STFPC 8*4(R8) Store resulting FPCR flags and DXC + 455 * +00000000000004E0 B29D F274 0000000000000274 456 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000004E4 B3A5 7081 457 CDGBRA FPR8,7,R1,B'0000' RM, to -inf +00000000000004E8 6080 7048 0000000000000048 458 STD FPR8,9*8(,R7) Store long BFP result +00000000000004EC B29C 8024 0000000000000024 459 STFPC 9*4(R8) Store resulting FPCR flags and DXC + 460 * +00000000000004F0 4130 3008 0000000000000008 461 LA R3,8(,R3) Point to next input value +00000000000004F4 4170 7050 0000000000000050 462 LA R7,10*8(,R7) Point to next long BFP rounded value set +00000000000004F8 4180 8030 0000000000000030 463 LA R8,12*4(,R8) Point to next FPCR/CC result area +00000000000004FC 062C 464 BCTR R2,R12 Convert next input value. +00000000000004FE 07FD 465 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvtfrfix64.asm: Test IEEE Convert From Fixed (int-64) 13 Sep 2016 09:13:43 Page 13 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 467 *********************************************************************** + 468 * + 469 * Convert int-64 to extended BFP format. A pair of results is + 470 * generated * for each input: one with all exceptions non-trappable, + 471 * and the second with all exceptions trappable. The FPCR is stored + 472 * for each result. Conversion of an int-64to extended is always exact; + 473 * no exceptions are expected. + 474 * + 475 *********************************************************************** + + + +0000000000000500 9823 A000 0000000000000000 477 CXGBR LM R2,R3,0(R10) Get count and address of test input values +0000000000000504 9878 A008 0000000000000008 478 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000508 1222 479 LTR R2,R2 Any test cases? +000000000000050A 078D 480 BZR R13 ..No, return to caller +000000000000050C 0DC0 481 BASR R12,0 Set top of loop + 482 * +000000000000050E E310 3000 0004 0000000000000000 483 LG R1,0(,R3) Get integer test value +0000000000000514 B29D F274 0000000000000274 484 LFPC FPCREGNT Set exceptions non-trappable +0000000000000518 B3A6 0081 485 CXGBR FPR8,R1 Cvt Int in GPR1 to float in FPR8-FPR10 +000000000000051C 6080 7000 0000000000000000 486 STD FPR8,0(,R7) Store extended BFP result part 1 +0000000000000520 60A0 7008 0000000000000008 487 STD FPR10,8(,R7) Store extended BFP result part 2 +0000000000000524 B29C 8000 0000000000000000 488 STFPC 0(R8) Store resulting FPCR flags and DXC + 489 * +0000000000000528 B29D F278 0000000000000278 490 LFPC FPCREGTR Set exceptions trappable +000000000000052C B3A6 0081 491 CXGBR FPR8,R1 Cvt Int in GPR1 to float in FPR8-FPR10 +0000000000000530 6080 7010 0000000000000010 492 STD FPR8,16(,R7) Store extended BFP result part 1 +0000000000000534 60A0 7018 0000000000000018 493 STD FPR10,24(,R7) Store extended BFP result part 2 +0000000000000538 B29C 8004 0000000000000004 494 STFPC 4(R8) Store resulting FPCR flags and DXC +000000000000053C 4130 3008 0000000000000008 495 LA R3,8(,R3) Point to next input value +0000000000000540 4170 7020 0000000000000020 496 LA R7,32(,R7) Point to next extended BFP converted value +0000000000000544 4180 8008 0000000000000008 497 LA R8,8(,R8) Point to next FPCR/CC result area +0000000000000548 062C 498 BCTR R2,R12 Convert next input value. +000000000000054A 07FD 499 BR R13 All converted; return. + ASMA Ver. 0.2.0 ieee-cvtfrfix64.asm: Test IEEE Convert From Fixed (int-64) 13 Sep 2016 09:13:43 Page 14 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 501 *********************************************************************** + 502 * + 503 * Int-64 inputs for Convert From Fixed testing. The same set of + 504 * inputs are used for short, long, and extended formats. The last two + 505 * values are used for rounding mode tests for short and long only; + 506 * conversion of int-64 to extended is always exact. + 507 * + 508 *********************************************************************** + + + +0000000000000550 510 INTIN DS 0D +0000000000000550 00000000 00000001 511 DC FD'1' +0000000000000558 00000000 00000002 512 DC FD'2' +0000000000000560 00000000 00000004 513 DC FD'4' +0000000000000568 FFFFFFFF FFFFFFFE 514 DC FD'-2' X'FFFFFFFF FFFFFFFE' + 515 * + 516 * Below inexact and incre. for short & long +0000000000000570 7FFFFFFF FFFFFFFF 517 DC FD'9223372036854775807' X'7FFFFFFF FFFFFFFF' +0000000000000578 80000000 00000001 518 DC FD'-9223372036854775807' X'80000000 00000001' + 519 * + 520 * Below exact for all +0000000000000580 7FFFFF80 00000000 521 DC FD'9223371487098961920' X'7FFFFF80 00000000' +0000000000000588 80000080 00000000 522 DC FD'-9223371487098961920' X'80000080 00000000' + 523 * + 524 * Below exact for long and extended +0000000000000590 7FFFFFFF FFFFFC00 525 DC FD'9223372036854774784' X'7FFFFFFF FFFFFC00' +0000000000000598 80000000 00000400 526 DC FD'-9223372036854774784' X'80000000 00000400' + 000000000000000A 0000000000000001 527 INTCOUNT EQU (*-INTIN)/8 Count of int-64 input values + 528 * + 529 * int-64 inputs for exhaustive short BFP rounding mode tests + 530 * +00000000000005A0 531 SINTRMIN DS 0D Values for short BFP rounding tests + 532 * Below rounds nearest away from zero +00000000000005A0 7FFFFFE0 00000000 533 DC FD'9223371899415822336' X'7FFFFFE0 00000000' +00000000000005A8 80000020 00000000 534 DC FD'-9223371899415822336' X'80000020 00000000' + 535 * Below rounds nearest tie +00000000000005B0 7FFFFFC0 00000000 536 DC FD'9223371761976868864' X'7FFFFFC0 00000000' +00000000000005B8 80000040 00000000 537 DC FD'-9223371761976868864' X'80000040 00000000' + 538 * Below rounds nearest toward zero +00000000000005C0 7FFFFFA0 00000000 539 DC FD'9223371624537915392' X'7FFFFFA0 00000000' +00000000000005C8 80000060 00000000 540 DC FD'-9223371624537915392' X'80000060 00000000' + 0000000000000006 0000000000000001 541 SINTRMCT EQU (*-SINTRMIN)/8 Count of int-64 for rounding tests + 542 * + 543 * int-64 inputs for exhaustive long BFP rounding mode tests + 544 * +00000000000005D0 545 LINTRMIN DS 0D Values for short BFP rounding mode tests + 546 * Below rounds nearest away from zero +00000000000005D0 7FFFFFFF FFFFFF00 547 DC FD'9223372036854775552' X'7FFFFFFF FFFFFF00' +00000000000005D8 80000000 00000100 548 DC FD'-9223372036854775552' X'80000000 00000100' + 549 * Below rounds nearest tie +00000000000005E0 7FFFFFFF FFFFFE00 550 DC FD'9223372036854775296' X'7FFFFFFF FFFFFE00' + ASMA Ver. 0.2.0 ieee-cvtfrfix64.asm: Test IEEE Convert From Fixed (int-64) 13 Sep 2016 09:13:43 Page 15 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000005E8 80000000 00000200 551 DC FD'-9223372036854775296' X'80000000 00000200' + 552 * Below rounds nearest toward zero +00000000000005F0 7FFFFFFF FFFFFD00 553 DC FD'9223372036854775040' X'7FFFFFFF FFFFFD00' +00000000000005F8 80000000 00000300 554 DC FD'-9223372036854775040' X'80000000 00000300' + 0000000000000006 0000000000000001 555 LINTRMCT EQU (*-LINTRMIN)/8 Count of int-64 for rounding tests + 556 * + 557 * Areas for resulting values and FPCR contents. + 558 * + 0000000000001000 0000000000000001 559 SBFPOUT EQU STRTLABL+X'1000' Int-64 results from short BFP inputs + 560 * ..6 pairs used, room for 32 pairs + 0000000000001100 0000000000000001 561 SBFPFLGS EQU STRTLABL+X'1100' FPCR flags and DXC from short BFP + 562 * ..6 pairs used, room for 32 pairs + 0000000000001200 0000000000000001 563 SBFPRMO EQU STRTLABL+X'1200' Short BFP rounding mode results + 564 * ..2 sets used, room for 16 + 0000000000001500 0000000000000001 565 SBFPRMOF EQU STRTLABL+X'1500' Short BFP rndg mode FPCR contents + 566 * ..2 sets used, room for 32 + 567 * ..next available location X'1600' + 568 * + 0000000000002000 0000000000000001 569 LBFPOUT EQU STRTLABL+X'2000' Int-64 results from long BFP inputs + 570 * ..6 pairs used, room for 16 pairs + 0000000000002100 0000000000000001 571 LBFPFLGS EQU STRTLABL+X'2100' Long BFP FPCR contents + 572 * ..6 pairs used, room for 32 pairs + 0000000000002200 0000000000000001 573 LBFPRMO EQU STRTLABL+X'2200' Long BFP rounding mode results + 574 * ..2 sets used, room for 16 sets + 0000000000002700 0000000000000001 575 LBFPRMOF EQU STRTLABL+X'2700' Long BFP rndg mode FPCR contents + 576 * ..2 sets used, room for 16 sets + 577 * ..next available location X'2A00' + 578 * + 0000000000003000 0000000000000001 579 XBFPOUT EQU STRTLABL+X'3000' Int-64 results from extended BFP + 580 * ..6 pairs used, room for 16 pairs + 0000000000003200 0000000000000001 581 XBFPFLGS EQU STRTLABL+X'3200' CLXBR restulting FPCR contents + 582 * ..6 pairs used, room for 16 pairs + 583 * ..next available location X'3300' + 584 * + 585 * + 0000000000003200 0000000000000001 586 ENDLABL EQU STRTLABL+X'3200' + 587 PADCSECT ENDLABL + 588+ MNOTE *,'asma detected; no CSECT padding performed' +0000000000000600 589 END + ASMA Ver. 0.2.0 ieee-cvtfrfix64.asm: Test IEEE Convert From Fixed (int-64) 13 Sep 2016 09:13:43 Page 16 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +BFPCVTFF J 000000 1536 80 +CDGBR I 0003E8 4 356 170 +CDGBRA I 00042C 4 393 172 +CEGBR I 0002D0 4 235 165 +CEGBRA I 000314 4 272 167 +CTLR0 F 000270 4 185 160 161 162 +CXGBR I 000500 4 477 175 +ENDLABL U 003200 1 586 +EXTDS F 0002A0 4 208 174 +FPCREGNT X 000274 4 186 242 283 289 295 301 310 315 320 325 330 335 363 404 410 416 422 431 + 436 441 446 451 456 484 +FPCREGTR X 000278 4 187 247 368 490 +FPR0 U 000000 1 101 +FPR1 U 000001 1 102 +FPR10 U 00000A 1 111 487 493 +FPR11 U 00000B 1 112 +FPR12 U 00000C 1 113 +FPR13 U 00000D 1 114 +FPR14 U 00000E 1 115 +FPR15 U 00000F 1 116 +FPR2 U 000002 1 103 +FPR3 U 000003 1 104 +FPR4 U 000004 1 105 +FPR5 U 000005 1 106 +FPR6 U 000006 1 107 +FPR7 U 000007 1 108 +FPR8 U 000008 1 109 243 244 248 249 285 286 291 292 297 298 303 304 311 312 316 317 321 + 322 326 327 331 332 336 337 364 365 369 370 406 407 412 413 418 419 + 424 425 432 433 437 438 442 443 447 448 452 453 457 458 485 486 491 + 492 +FPR9 U 000009 1 110 +HARDWAIT X 000260 8 183 154 +IMAGE 1 000000 1536 0 +INTCOUNT U 00000A 1 527 197 203 209 +INTIN D 000550 8 510 527 198 204 210 +LBFPFLGS U 002100 1 571 206 +LBFPOUT U 002000 1 569 205 +LBFPRMO U 002200 1 573 223 +LBFPRMOF U 002700 1 575 224 +LINTRMCT U 000006 1 555 221 +LINTRMIN D 0005D0 8 545 555 222 +LONGS F 000290 4 202 169 +PCINTCD H 00008E 2 131 148 +PCNOTDTA H 00020C 2 151 149 +PCOLDPSW U 000150 1 133 150 +PROGCHK H 000200 2 147 139 +R0 U 000000 1 82 160 162 +R1 U 000001 1 83 241 243 248 278 285 291 297 303 311 316 321 326 331 336 362 364 369 + 399 406 412 418 424 432 437 442 447 452 457 483 485 491 +R10 U 00000A 1 92 164 166 169 171 174 235 238 272 275 356 357 393 394 477 478 +R11 U 00000B 1 93 +R12 U 00000C 1 94 239 254 276 343 360 375 397 464 481 498 + ASMA Ver. 0.2.0 ieee-cvtfrfix64.asm: Test IEEE Convert From Fixed (int-64) 13 Sep 2016 09:13:43 Page 17 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +R13 U 00000D 1 95 165 167 170 172 175 237 255 274 344 359 376 396 465 480 499 +R14 U 00000E 1 96 152 153 177 178 +R15 U 00000F 1 97 118 +R2 U 000002 1 84 235 236 254 272 273 343 356 358 375 393 395 464 477 479 498 +R3 U 000003 1 85 235 241 251 272 278 340 356 362 372 393 399 461 477 483 495 +R4 U 000004 1 86 +R5 U 000005 1 87 +R6 U 000006 1 88 +R7 U 000007 1 89 238 244 249 252 275 286 292 298 304 312 317 322 327 332 337 341 357 + 365 370 373 394 407 413 419 425 433 438 443 448 453 458 462 478 486 + 487 492 493 496 +R8 U 000008 1 90 238 245 250 253 275 287 293 299 305 313 318 323 328 333 338 342 357 + 366 371 374 394 408 414 420 426 434 439 444 449 454 459 463 478 488 + 494 497 +R9 U 000009 1 91 +RMLONGS F 0002C0 4 220 171 +RMSHORTS F 0002B0 4 214 166 +SBFPFLGS U 001100 1 561 200 +SBFPOUT U 001000 1 559 199 +SBFPRMO U 001200 1 563 217 +SBFPRMOF U 001500 1 565 218 +SHORTS F 000280 4 196 164 +SINTRMCT U 000006 1 541 215 +SINTRMIN D 0005A0 8 531 541 216 +START I 000214 4 160 136 +STRTLABL U 000000 1 81 130 133 135 138 146 195 559 561 563 565 569 571 573 575 579 581 586 +WAITPSW X 000250 8 182 179 +XBFPFLGS U 003200 1 581 212 +XBFPOUT U 003000 1 579 211 + ASMA Ver. 0.2.0 ieee-cvtfrfix64.asm: Test IEEE Convert From Fixed (int-64) 13 Sep 2016 09:13:43 Page 18 + + MACRO DEFN REFERENCES + +PADCSECT 55 587 + ASMA Ver. 0.2.0 ieee-cvtfrfix64.asm: Test IEEE Convert From Fixed (int-64) 13 Sep 2016 09:13:43 Page 19 + + DESC SYMBOL SIZE POS ADDR + +Entry: 0 + +Image IMAGE 1536 000-5FF 000-5FF + Region 1536 000-5FF 000-5FF + CSECT BFPCVTFF 1536 000-5FF 000-5FF + ASMA Ver. 0.2.0 ieee-cvtfrfix64.asm: Test IEEE Convert From Fixed (int-64) 13 Sep 2016 09:13:43 Page 20 + + STMT FILE NAME + +1 C:\Users\srorso\Documents\GitHub\hyperion\tests\bfp-011-cvtfrfix64.asm + + +** NO ERRORS FOUND ** + +[588] MNOTE *,asma detected; no CSECT padding performed + \ No newline at end of file diff --git a/tests/bfp-011-cvtfrfix64.tst b/tests/bfp-011-cvtfrfix64.tst new file mode 100644 index 000000000..692b9fa28 --- /dev/null +++ b/tests/bfp-011-cvtfrfix64.tst @@ -0,0 +1,306 @@ +*Testcase bfp-011-cvtfrfix64.tst: CEGBR, CEGBRA, CDGBR, CDGBRA, CXGBR, CXGBRA + +#Testcase bfp-011-cvtfrfix64.tst: IEEE Convert From Fixed (64-bit) +#..Includes CONVERT FROM FIXED 64 (6). Also tests traps and +#..exceptions and results from different rounding modes. + +sysclear +archmode esame + +# +# Following suppresses logging of program checks. This test program, as part +# of its normal operation, generates 6 program check messages that have no +# value in the validation process. (The messages, not the program checks.) +# +ostailor quiet + +loadcore "$(testpath)/bfp-011-cvtfrfix64.core" + +runtest 1.0 + +ostailor null # restore messages for subsequent tests + + +# Inputs converted to BFP short - results +*Compare +r 1000.10 +*Want "CEGBR result pairs 1-2" 3F800000 3F800000 40000000 40000000 +r 1010.10 +*Want "CEGBR result pairs 3-4" 40800000 40800000 C0000000 C0000000 +r 1020.10 +*Want "CEGBR result pairs 5-6" 5F000000 5F000000 DF000000 DF000000 +r 1030.10 +*Want "CEGBR result pairs 7-8" 5EFFFFFF 5EFFFFFF DEFFFFFF DEFFFFFF +r 1040.10 +*Want "CEGBR result pairs 9-10" 5F000000 5F000000 DF000000 DF000000 + +# Inputs converted to BFP short - FPCR contents +*Compare +r 1100.10 +*Want "CEGBR FPCR pairs 1-2" 00000000 F8000000 00000000 F8000000 +r 1110.10 +*Want "CEGBR FPCR pairs 3-4" 00000000 F8000000 00000000 F8000000 +r 1120.10 +*Want "CEGBR FPCR pairs 5-6" 00080000 F8000C00 00080000 F8000C00 +r 1130.10 +*Want "CEGBR FPCR pairs 7-8" 00000000 F8000000 00000000 F8000000 +r 1140.10 +*Want "CEGBR FPCR pairs 9-10" 00080000 F8000C00 00080000 F8000C00 + + +# Int-64 to BFP short rounding mode tests - results +r 1200.10 +*Want "CEGBRA +away result FPCRmodes 1-3, 7" 5EFFFFFF 5F000000 5EFFFFFF 5EFFFFFF +r 1210.10 +*Want "CEGBRA +away result M3 modes 1, 3-5" 5F000000 5EFFFFFF 5F000000 5EFFFFFF +r 1220.08 +*Want "CEGBRA +away result M3 modes 6, 7" 5F000000 5EFFFFFF +r 1230.10 +*Want "CEGBRA -away result FPCRmodes 1-3, 7" DEFFFFFF DEFFFFFF DF000000 DEFFFFFF +r 1240.10 +*Want "CEGBRA -away result M3 modes 1, 3-5" DF000000 DEFFFFFF DF000000 DEFFFFFF +r 1250.08 +*Want "CEGBRA -away result M3 modes 6, 7" DEFFFFFF DF000000 + +# Int-64 to BFP short rounding mode tests - results +r 1260.10 +*Want "CEGBRA +tie result FPCRmodes 1-3, 7" 5EFFFFFF 5F000000 5EFFFFFF 5EFFFFFF +r 1270.10 +*Want "CEGBRA +tie result M3 modes 1, 3-5" 5F000000 5EFFFFFF 5F000000 5EFFFFFF +r 1280.08 +*Want "CEGBRA +tie result M3 modes 6, 7" 5F000000 5EFFFFFF +r 1290.10 +*Want "CEGBRA -tie result FPCRmodes 1-3, 7" DEFFFFFF DEFFFFFF DF000000 DEFFFFFF +r 12A0.10 +*Want "CEGBRA -tie result M3 modes 1, 3-5" DF000000 DEFFFFFF DF000000 DEFFFFFF +r 12B0.08 +*Want "CEGBRA -tie result M3 modes 6, 7" DEFFFFFF DF000000 + +# Int-64 to BFP short rounding mode tests - results +r 12C0.10 +*Want "CEGBRA +tozero result FPCRmodes 1-3, 7" 5EFFFFFF 5F000000 5EFFFFFF 5EFFFFFF +r 12D0.10 +*Want "CEGBRA +tozero result M3 modes 1, 3-5" 5EFFFFFF 5EFFFFFF 5EFFFFFF 5EFFFFFF +r 12E0.08 +*Want "CEGBRA +tozero result M3 modes 6, 7" 5F000000 5EFFFFFF +r 12F0.10 +*Want "CEGBRA -tozero result FPCRmodes 1-3, 7" DEFFFFFF DEFFFFFF DF000000 DEFFFFFF +r 1300.10 +*Want "CEGBRA -tozero result M3 modes 1, 3-5" DEFFFFFF DEFFFFFF DEFFFFFF DEFFFFFF +r 1310.08 +*Want "CEGBRA -tozero result M3 modes 6, 7" DEFFFFFF DF000000 + +# Int-64 to BFP short rounding mode tests - FPCR contents +*Compare +r 1500.10 +*Want "CEGBRA +away FPCRmodes 1-3, 7 FPCR" 00000001 00000002 00000003 00000007 +r 1510.10 +*Want "CEGBRA +away M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 1520.08 +*Want "CEGBRA +away M3 modes 6, 7 FPCR" 00080000 00080000 +r 1530.10 +*Want "CEGBRA -away FPCRmodes 1-3, 7 FPCR" 00000001 00000002 00000003 00000007 +r 1540.10 +*Want "CEGBRA -away M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 1550.08 +*Want "CEGBRA -away M3 modes 6, 7 FPCR" 00080000 00080000 + +r 1560.10 +*Want "CEGBRA +tie FPCRmodes 1-3, 7 FPCR" 00000001 00000002 00000003 00000007 +r 1570.10 +*Want "CEGBRA +tie M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 1580.08 +*Want "CEGBRA +tie M3 modes 6, 7 FPCR" 00080000 00080000 +r 1590.10 +*Want "CEGBRA -tie FPCRmodes 1-3, 7 FPCR" 00000001 00000002 00000003 00000007 +r 15A0.10 +*Want "CEGBRA -tie M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 15B0.08 +*Want "CEGBRA -tie M3 modes 6, 7 FPCR" 00080000 00080000 + +r 15C0.10 +*Want "CEGBRA +tozero FPCRmodes 1-3, 7 FPCR" 00000001 00000002 00000003 00000007 +r 15D0.10 +*Want "CEGBRA +tozero M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 15E0.08 +*Want "CEGBRA +tozero M3 modes 6, 7 FPCR" 00080000 00080000 +r 15F0.10 +*Want "CEGBRA -tozero FPCRmodes 1-3, 7 FPCR" 00000001 00000002 00000003 00000007 +r 1600.10 +*Want "CEGBRA -tozero M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 1610.08 +*Want "CEGBRA -tozero M3 modes 6, 7 FPCR" 00080000 00080000 + + +# Inputs converted to BFP long - Results +*Compare +r 2000.10 +*Want "CDGBR result pair 1" 3FF00000 00000000 3FF00000 00000000 +r 2010.10 +*Want "CDGBR result pair 2" 40000000 00000000 40000000 00000000 +r 2020.10 +*Want "CDGBR result pair 3" 40100000 00000000 40100000 00000000 +r 2030.10 +*Want "CDGBR result pair 4" C0000000 00000000 C0000000 00000000 +r 2040.10 +*Want "CDGBR result pair 5" 43E00000 00000000 43E00000 00000000 +r 2050.10 +*Want "CDGBR result pair 6" C3E00000 00000000 C3E00000 00000000 + +# Inputs converted to BFP long - FPCR contents +*Compare +r 2100.10 +*Want "CDGBR FPCR pairs 1-2" 00000000 F8000000 00000000 F8000000 +r 2110.10 +*Want "CDGBR FPCR pairs 3-4" 00000000 F8000000 00000000 F8000000 +r 2120.10 +*Want "CDGBR FPCR pairs 5-6" 00080000 F8000C00 00080000 F8000C00 + + +# BFP long rounding mode tests - positive input results +*Compare +r 2200.10 +*Want "CDGBRA +away FPCRmodes 1, 2" 43DFFFFF FFFFFFFF 43E00000 00000000 +r 2210.10 +*Want "CDGBRA +away FPCRmodes 3, 7" 43DFFFFF FFFFFFFF 43DFFFFF FFFFFFFF +r 2220.10 +*Want "CDGBRA +away M3 modes 1, 3" 43E00000 00000000 43DFFFFF FFFFFFFF +r 2230.10 +*Want "CDGBRA +away M3 modes 4, 5" 43E00000 00000000 43DFFFFF FFFFFFFF +r 2240.10 +*Want "CDGBRA +away M3 modes 6, 7" 43E00000 00000000 43DFFFFF FFFFFFFF +r 2250.10 +*Want "CDGBRA -away FPCRmodes 1, 2" C3DFFFFF FFFFFFFF C3DFFFFF FFFFFFFF +r 2260.10 +*Want "CDGBRA -away FPCRmodes 3, 7" C3E00000 00000000 C3DFFFFF FFFFFFFF +r 2270.10 +*Want "CDGBRA -away M3 modes 1, 3" C3E00000 00000000 C3DFFFFF FFFFFFFF +r 2280.10 +*Want "CDGBRA -away M3 modes 4, 5" C3E00000 00000000 C3DFFFFF FFFFFFFF +r 2290.10 +*Want "CDGBRA -away M3 modes 6, 7" C3DFFFFF FFFFFFFF C3E00000 00000000 + +r 22A0.10 +*Want "CDGBRA +tie FPCRmodes 1, 2" 43DFFFFF FFFFFFFF 43E00000 00000000 +r 22B0.10 +*Want "CDGBRA +tie FPCRmodes 3, 7" 43DFFFFF FFFFFFFF 43DFFFFF FFFFFFFF +r 22C0.10 +*Want "CDGBRA +tie M3 modes 1, 3" 43E00000 00000000 43DFFFFF FFFFFFFF +r 22D0.10 +*Want "CDGBRA +tie M3 modes 4, 5" 43E00000 00000000 43DFFFFF FFFFFFFF +r 22E0.10 +*Want "CDGBRA +tie M3 modes 6, 7" 43E00000 00000000 43DFFFFF FFFFFFFF +r 22F0.10 +*Want "CDGBRA -tie FPCRmodes 1, 2" C3DFFFFF FFFFFFFF C3DFFFFF FFFFFFFF +r 2300.10 +*Want "CDGBRA -tie FPCRmodes 3, 7" C3E00000 00000000 C3DFFFFF FFFFFFFF +r 2310.10 +*Want "CDGBRA -tie M3 modes 1, 3" C3E00000 00000000 C3DFFFFF FFFFFFFF +r 2320.10 +*Want "CDGBRA -tie M3 modes 4, 5" C3E00000 00000000 C3DFFFFF FFFFFFFF +r 2330.10 +*Want "CDGBRA -tie M3 modes 6, 7" C3DFFFFF FFFFFFFF C3E00000 00000000 + +r 2340.10 +*Want "CDGBRA +tozero FPCRmodes 1, 2" 43DFFFFF FFFFFFFF 43E00000 00000000 +r 2350.10 +*Want "CDGBRA +tozero FPCRmodes 3, 7" 43DFFFFF FFFFFFFF 43DFFFFF FFFFFFFF +r 2360.10 +*Want "CDGBRA +tozero M3 modes 1, 3" 43DFFFFF FFFFFFFF 43DFFFFF FFFFFFFF +r 2370.10 +*Want "CDGBRA +tozero M3 modes 4, 5" 43DFFFFF FFFFFFFF 43DFFFFF FFFFFFFF +r 2380.10 +*Want "CDGBRA +tozero M3 modes 6, 7" 43E00000 00000000 43DFFFFF FFFFFFFF +r 2390.10 +*Want "CDGBRA -tozero FPCRmodes 1, 2" C3DFFFFF FFFFFFFF C3DFFFFF FFFFFFFF +r 23A0.10 +*Want "CDGBRA -tozero FPCRmodes 3, 7" C3E00000 00000000 C3DFFFFF FFFFFFFF +r 23B0.10 +*Want "CDGBRA -tozero M3 modes 1, 3" C3DFFFFF FFFFFFFF C3DFFFFF FFFFFFFF +r 23C0.10 +*Want "CDGBRA -tozero M3 modes 4, 5" C3DFFFFF FFFFFFFF C3DFFFFF FFFFFFFF +r 23D0.10 +*Want "CDGBRA -tozero M3 modes 6, 7" C3DFFFFF FFFFFFFF C3E00000 00000000 + + +# BFP long rounding mode tests - positive input FPCR contents +*Compare +r 2700.10 +*Want "CDGBRA +away FPCRmodes 1-3, 7 FPCR" 00000001 00000002 00000003 00000007 +r 2710.10 +*Want "CDGBRA +away M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 2720.08 +*Want "CDGBRA +away M3 modes 6, 7 FPCR" 00080000 00080000 +r 2730.10 +*Want "CDGBRA -away FPCRmodes 1-3, 7 FPCR" 00000001 00000002 00000003 00000007 +r 2740.10 +*Want "CDGBRA -away M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 2750.08 +*Want "CDGBRA -away M3 modes 6, 7 FPCR" 00080000 00080000 + +r 2760.10 +*Want "CDGBRA +tie FPCRmodes 1-3, 7 FPCR" 00000001 00000002 00000003 00000007 +r 2770.10 +*Want "CDGBRA +tie M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 2780.08 +*Want "CDGBRA +tie M3 modes 6, 7 FPCR" 00080000 00080000 +r 2790.10 +*Want "CDGBRA -tie FPCRmodes 1-3, 7 FPCR" 00000001 00000002 00000003 00000007 +r 27A0.10 +*Want "CDGBRA -tie M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 27B0.08 +*Want "CDGBRA -tie M3 modes 6, 7 FPCR" 00080000 00080000 + +r 27C0.10 +*Want "CDGBRA +tozero FPCRmodes 1-3, 7 FPCR" 00000001 00000002 00000003 00000007 +r 27D0.10 +*Want "CDGBRA +tozero M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 27E0.08 +*Want "CDGBRA +tozero M3 modes 6, 7 FPCR" 00080000 00080000 +r 27F0.10 +*Want "CDGBRA -tozero FPCRmodes 1-3, 7 FPCR" 00000001 00000002 00000003 00000007 +r 2800.10 +*Want "CDGBRA -tozero M3 modes 1, 3-5 FPCR" 00080000 00080000 00080000 00080000 +r 2810.08 +*Want "CDGBRA -tozero M3 modes 6, 7 FPCR" 00080000 00080000 + + +# Inputs converted to BFP Extended - Results +*Compare +r 3000.10 +*Want "CXGBR result 1a" 3FFF0000 00000000 00000000 00000000 +r 3010.10 +*Want "CXGBR result 1b" 3FFF0000 00000000 00000000 00000000 +r 3020.10 +*Want "CXGBR result 2a" 40000000 00000000 00000000 00000000 +r 3030.10 +*Want "CXGBR result 2b" 40000000 00000000 00000000 00000000 +r 3040.10 +*Want "CXGBR result 3a" 40010000 00000000 00000000 00000000 +r 3050.10 +*Want "CXGBR result 3b" 40010000 00000000 00000000 00000000 +r 3060.10 +*Want "CXGBR result 4a" C0000000 00000000 00000000 00000000 +r 3070.10 +*Want "CXGBR result 4b" C0000000 00000000 00000000 00000000 +r 3080.10 +*Want "CXGBR result 5a" 403DFFFF FFFFFFFF FFFC0000 00000000 +r 3090.10 +*Want "CXGBR result 5b" 403DFFFF FFFFFFFF FFFC0000 00000000 +r 30A0.10 +*Want "CXGBR result 6a" C03DFFFF FFFFFFFF FFFC0000 00000000 +r 30B0.10 +*Want "CXGBR result 6b" C03DFFFF FFFFFFFF FFFC0000 00000000 + +# Inputs converted to BFP extended - FPCR Contents +*Compare +r 3200.10 +*Want "CXGBR FPCRpairs 1-2" 00000000 F8000000 00000000 F8000000 +r 3210.10 +*Want "CXGBR FPCRpairs 3-4" 00000000 F8000000 00000000 F8000000 +r 3220.10 +*Want "CXGBR FPCRpairs 5-6" 00000000 F8000000 00000000 F8000000 + + +*Done + diff --git a/tests/bfp-012-loadtest.asm b/tests/bfp-012-loadtest.asm new file mode 100644 index 000000000..2da9e33ad --- /dev/null +++ b/tests/bfp-012-loadtest.asm @@ -0,0 +1,568 @@ + TITLE 'bfp-012-loadtest.asm: Test IEEE Test Data Class, Load And Test' +*********************************************************************** +* +*Testcase IEEE Test Data Classs and Load And Test +* Exhaustively test results from the Test Data Class instruction. +* Exhaustively test condition code setting from Load And Test. +* The Condition Code, the only result from either instruction, is +* saved for comparison with reference values. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* bfp-012-loadtest.asm +* +* This assembly-language source file is part of the +* Hercules Decimal Floating Point Validation Package +* by Stephen R. Orso +* +* Copyright 2016 by Stephen R Orso. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* +* 3. The name of the author may not be used to endorse or promote +* products derived from this software without specific prior written +* permission. +* +* DISCLAMER: THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* HOLDER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* Neither Load And Test nor Test Data Class can result in IEEE +* exceptions. All tests are performed with the FPC set to not trap +* on any exception. +* +* The same test data are used for both Load And Test and Test Data +* Class. +* +* For Load And Test, the result value and condition code are stored. +* For all but SNaN inputs, the result should be the same as the input. +* For SNaN inputs, the result is the corresponding QNaN. +* +* For Test Data Class, 13 Condition codes are stored. The first +* 12 correspond to a one-bit in each of 12 positions of the Test Data +* class second operand mask, and the thirteenth is generated with a +* mask of zero. Test Data Class mask bits: +* +* 1 0 0 0 | 0 0 0 0 | 0 0 0 0 + zero +* 0 1 0 0 | 0 0 0 0 | 0 0 0 0 - zero +* 0 0 1 0 | 0 0 0 0 | 0 0 0 0 + finite +* 0 0 0 1 | 0 0 0 0 | 0 0 0 0 - finite +* 0 0 0 0 | 1 0 0 0 | 0 0 0 0 + tiny +* 0 0 0 0 | 0 1 0 0 | 0 0 0 0 - tiny +* 0 0 0 0 | 0 0 1 0 | 0 0 0 0 + inf +* 0 0 0 0 | 0 0 0 1 | 0 0 0 0 - inf +* 0 0 0 0 | 0 0 0 0 | 1 0 0 0 + QNaN +* 0 0 0 0 | 0 0 0 0 | 0 1 0 0 - QNaN +* 0 0 0 0 | 0 0 0 0 | 0 0 1 0 + SNaN +* 0 0 0 0 | 0 0 0 0 | 0 0 0 1 - SNaN +* +* Tests 3 LOAD AND TEST and 3 TEST DATA CLASS instructions +* LOAD AND TEST (BFP short, RRE) LTEBR +* LOAD AND TEST (BFP long, RRE) LTDBR +* LOAD AND TEST (BFP extended, RRE) LTXBR +* TEST DATA CLASS (BFP short, RRE) LTEBR +* TEST DATA CLASS (BFP long, RRE) LTDBR +* TEST DATA CLASS (BFP extended, RRE) LTXBR +* +* Also tests the following floating point support instructions +* EXTRACT FPC +* LOAD (Short) +* LOAD (Long) +* LOAD ZERO (Long) +* STORE (Short) +* STORE (Long) +* SET FPC +* +*********************************************************************** + SPACE 2 + MACRO + PADCSECT &ENDLABL +.* +.* Macro to pad the CSECT to include result data areas if this test +.* program is not being assembled using asma. asma generates a core +.* image that is loaded by the loadcore command, and because the +.* core image is a binary stored in Github, it makes sense to make +.* this small effort to keep the core image small. +.* + AIF (D'&ENDLABL).GOODPAD + MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + MNOTE *,'No CSECT padding performed' + MEXIT +.* +.GOODPAD ANOP Label valid. See if we're on asma + AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + ORG &ENDLABL-1 Not ASMA. Pad CSECT + MEXIT +.* +.NOPAD ANOP + MNOTE *,'asma detected; no CSECT padding performed' + MEND +* +* Note: for compatibility with the z/CMS test rig, do not change +* or use R11, R14, or R15. Everything else is fair game. +* +BFPLTTDC START 0 +STRTLABL EQU * +R0 EQU 0 Work register for cc extraction +R1 EQU 1 Current Test Data Class mask +R2 EQU 2 Holds count of test input values +R3 EQU 3 Points to next test input value(s) +R4 EQU 4 Available +R5 EQU 5 Available +R6 EQU 6 Test Data Class top of loop +R7 EQU 7 Ptr to next result for Load And Test +R8 EQU 8 Ptr to next CC for Load And Test +R9 EQU 9 Ptr to next CC for Test Data Class +R10 EQU 10 Pointer to test address list +R11 EQU 11 **Reserved for z/CMS test rig +R12 EQU 12 Test value top of loop +R13 EQU 13 Mainline return address +R14 EQU 14 **Return address for z/CMS test rig +R15 EQU 15 **Base register on z/CMS or Hyperion +* +* Floating Point Register equates to keep the cross reference clean +* +FPR0 EQU 0 +FPR1 EQU 1 +FPR2 EQU 2 +FPR3 EQU 3 +FPR4 EQU 4 +FPR5 EQU 5 +FPR6 EQU 6 +FPR7 EQU 7 +FPR8 EQU 8 +FPR9 EQU 9 +FPR10 EQU 10 +FPR11 EQU 11 +FPR12 EQU 12 +FPR13 EQU 13 +FPR14 EQU 14 +FPR15 EQU 15 +* + USING *,R15 +* +* Above works on real iron (R15=0 after sysclear) +* and in z/CMS (R15 points to start of load module) +* + SPACE 2 +*********************************************************************** +* +* Low core definitions, Restart PSW, and Program Check Routine. +* +*********************************************************************** + SPACE 2 + ORG STRTLABL+X'8E' Program check interrution code +PCINTCD DS H +* +PCOLDPSW EQU STRTLABL+X'150' z/Arch Program check old PSW +* + ORG STRTLABL+X'1A0' z/Arch Restart PSW + DC X'0000000180000000',AD(START) +* + ORG STRTLABL+X'1D0' z/Arch Program check old PSW + DC X'0000000000000000',AD(PROGCHK) +* +* Program check routine. If Data Exception, continue execution at +* the instruction following the program check. Otherwise, hard wait. +* No need to collect data. All interesting DXC stuff is captured +* in the FPCR. +* + ORG STRTLABL+X'200' +PROGCHK DS 0H Program check occured... + CLI PCINTCD+1,X'07' Data Exception? + JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) + LPSWE PCOLDPSW ..yes, resume program execution +PCNOTDTA DS 0H + LTR R14,R14 Return address provided? + BNZR R14 Yes, return to z/CMS test rig. + LPSWE HARDWAIT Not data exception, enter disabled wait + EJECT +*********************************************************************** +* +* Main program. Enable Advanced Floating Point, process test cases. +* +*********************************************************************** + SPACE 2 +START DS 0H + STCTL R0,R0,CTLR0 Store CR0 to enable AFP + OI CTLR0+1,X'04' Turn on AFP bit + LCTL R0,R0,CTLR0 Reload updated CR0 +* + LA R10,SHORTS Point to short BFP test inputs + BAS R13,TESTSBFP Perform short BFP tests +* + LA R10,LONGS Point to long BFP test inputs + BAS R13,TESTLBFP Perform long BFP tests +* + LA R10,EXTDS Point to extended BFP test inputs + BAS R13,TESTXBFP Perform short BFP tests +* + LTR R14,R14 Return address provided? + BNZR R14 ..Yes, return to z/CMS test rig. + LPSWE WAITPSW All done +* + DS 0D Ensure correct alignment for psw +WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end +* +CTLR0 DS F +FPCREGNT DC X'00000000' FPCR, trap no IEEE exceptions, zero flags +FPCREGTR DC X'F8000000' FPCR, trap all IEEE exceptions, zero flags +* +* Input values parameter list, four fullwords for each test data set +* 1) Count, +* 2) Address of inputs, +* 3) Address to place results, and +* 4) Address to place DXC/Flags/cc values. +* + ORG STRTLABL+X'300' Enable run-time replacement +SHORTS DS 0F Input pairs for short BFP ests + DC A(SBFPINCT) + DC A(SBFPIN) + DC A(SBFPOUT) + DC A(SBFPOCC) +* +LONGS DS 0F Input pairs for long BFP testing + DC A(LBFPINCT) + DC A(LBFPIN) + DC A(LBFPOUT) + DC A(LBFPOCC) +* +EXTDS DS 0F Input pairs for extendedd BFP testing + DC A(XBFPINCT) + DC A(XBFPIN) + DC A(XBFPOUT) + DC A(XBFPOCC) + EJECT +*********************************************************************** +* Perform Short BFP Tests. This includes one execution of Load And +* Test, followed by 13 executions of Test Data Class. The result value +* and Condition code are saved for Load And Test, and the Condition +* Code is saved for each execution of Test Data Class. +* +*********************************************************************** + SPACE 2 +TESTSBFP DS 0H Test short BFP input values + LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result and CC areas. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LE FPR8,0(,R3) Get short BFP test value +* Polute the CC result area. Correct +* ..results will clean it up. + MVC 0(16,R8),=X'FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF' +* + LFPC FPCREGNT Set exceptions non-trappable + LE FPR1,SBFPINVL Ensure an unchanged FPR1 is detectable + IPM R0 Get current program mask and CC + N R0,=X'CFFFFFFF' Turn off condition code bits + O R0,=X'20000000' Force condition code two + SPM R0 Set PSW CC to two + LTEBR FPR1,FPR8 Load and Test into FPR1 + STE FPR1,0(,R7) Store short BFP result + IPM R0 Retrieve condition code + SRL R0,28 Move CC to low-order r0, dump prog mask + STC R0,0(,R8) Store in CC result area +* + LFPC FPCREGTR Set exceptions non-trappable + LE FPR1,SBFPINVL Ensure an unchanged FPR1 is detectable + IPM R0 Get current program mask and CC + N R0,=X'CFFFFFFF' Turn off condition code bits + O R0,=X'20000000' Force condition code two + SPM R0 Set PSW CC to two + LTEBR FPR1,FPR8 Load and Test into FPR1 + STE FPR1,4(,R7) Store short BFP result + IPM R0 Retrieve condition code + SRL R0,28 Move CC to low-order r0, dump prog mask + STC R0,1(,R8) Store in CC result area + EFPC R0 Extract FPC contents to R0 + STCM R0,B'0010',2(R8) Store any DXC code +* + LHI R1,4096 Load Test Data Class mask starting point + LA R9,3(,R8) Point to first Test Data Class CC + BASR R6,0 Set start of Test Data Class loop +* + SRL R1,1 Shift to get next class mask value + TCEB FPR8,0(,R1) Test value against class mask + IPM R0 Retrieve condition code + SRL R0,28 Move CC to low-order r0, dump prog mask + STC R0,0(,R9) Store in CC result area + LA R9,1(,R9) Point to next CC slot + LTR R1,R1 Have we tested all masks including zero + BNZR R6 ..no, at least one more to test + + LA R3,4(,R3) Point to next short BFP test value + LA R7,8(,R7) Point to next Load And Test result pair + LA R8,16(,R8) Point to next CC result set + BCTR R2,R12 Loop through all test cases +* + BR R13 Tests done, return to mainline + EJECT +*********************************************************************** +* Perform long BFP Tests. This includes one execution of Load And +* Test, followed by 13 executions of Test Data Class. The result value +* and Condition code are saved for Load And Test, and the Condition +* Code is saved for each execution of Test Data Class. +* +*********************************************************************** + SPACE 2 +TESTLBFP DS 0H Test long BFP input values + LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result and CC areas. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LD FPR8,0(,R3) Get long BFP test value +* Polute the CC result area. Correct +* ..results will clean it up. + MVC 0(16,R8),=X'FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF' +* + LFPC FPCREGNT Set exceptions non-trappable + LD FPR1,LBFPINVL Ensure an unchanged FPR1 is detectable + IPM R0 Get current program mask and CC + N R0,=X'CFFFFFFF' Turn off condition code bits + O R0,=X'10000000' Force condition code one + SPM R0 Set PSW CC to one + LTDBR FPR1,FPR8 Load and Test into FPR1 + STD FPR1,0(,R7) Store long BFP result + IPM R0 Retrieve condition code + SRL R0,28 Move CC to low-order r0, dump prog mask + STC R0,0(,R8) Store in CC result area +* + LFPC FPCREGTR Set exceptions trappable + LD FPR1,LBFPINVL Ensure an unchanged FPR1 is detectable + IPM R0 Get current program mask and CC + N R0,=X'CFFFFFFF' Turn off condition code bits + O R0,=X'10000000' Force condition code one + SPM R0 Set PSW CC to one + LTDBR FPR1,FPR8 Load and Test into FPR1 + STD FPR1,8(,R7) Store long BFP result + IPM R0 Retrieve condition code + SRL R0,28 Move CC to low-order r0, dump prog mask + STC R0,1(,R8) Store in CC result area + EFPC R0 Extract FPC contents to R0 + STCM R0,B'0010',2(R8) Store any DXC code +* + LHI R1,4096 Load Test Data Class mask starting point + LA R9,3(,R8) Point to first Test Data Class CC + BASR R6,0 Set start of Test Data Class loop + + SRL R1,1 Shift to get next class mask value + TCDB FPR8,0(,R1) Test value against class mask + IPM R0 Retrieve condition code + SRL R0,28 Move CC to low-order r0, dump prog mask + STC R0,0(,R9) Store in CC result area + LA R9,1(,R9) Point to next CC slot + LTR R1,R1 Have we tested all masks including zero + BNZR R6 ..no, at least one more to test + + LA R3,8(,R3) Point to next long BFP test value + LA R7,16(,R7) Point to next Load And Test result pair + LA R8,16(,R8) Point to next CC result set + BCTR R2,R12 Loop through all test cases +* + BR R13 Tests done, return to mainline + EJECT +*********************************************************************** +* Perform extended BFP Tests. This includes one execution of Load And +* Test, followed by 13 executions of Test Data Class. The result value +* and Condition code are saved for Load And Test, and the Condition +* Code is saved for each execution of Test Data Class. +* +*********************************************************************** + SPACE 2 +TESTXBFP DS 0H Test extended BFP input values + LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result and CC areas. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LD FPR8,0(,R3) Get extended BFP test value part 1 + LD FPR10,8(,R3) Get extended BFP test value part 2 +* Polute the CC result area. Correct +* ..results will clean it up. + MVC 0(16,R8),=X'FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF' +* + LFPC FPCREGNT Set exceptions non-trappable + LD FPR1,XBFPINVL Ensure an unchanged FPR1-3 is detectable + LD FPR3,XBFPINVL+8 ..part 2 of load FPR pair + IPM R0 Get current program mask and CC + N R0,=X'CFFFFFFF' Turn off condition code bits + SPM R0 Set PSW CC to zero + LTXBR FPR1,FPR8 Load and Test into FPR1 + STD FPR1,0(,R7) Store extended BFP result part 1 + STD FPR3,8(,R7) Store extended BFP result part 2 + IPM R0 Retrieve condition code + SRL R0,28 Move CC to low-order r0, dump prog mask + STC R0,0(,R8) Store in CC result area +* + LFPC FPCREGTR Set exceptions trappable + LD FPR1,XBFPINVL Ensure an unchanged FPR1-3 is detectable + LD FPR3,XBFPINVL+8 ..part 2 of load FPR pair + IPM R0 Get current program mask and CC + N R0,=X'CFFFFFFF' Turn off condition code bits + SPM R0 Set PSW CC to zero + LTXBR FPR1,FPR8 Load and Test into FPR1 + STD FPR1,16(,R7) Store extended BFP result part 1 + STD FPR3,24(,R7) Store extended BFP result part 2 + IPM R0 Retrieve condition code + SRL R0,28 Move CC to low-order r0, dump prog mask + STC R0,1(,R8) Store in CC result area + EFPC R0 Extract FPC contents to R0 + STCM R0,B'0010',2(R8) Store any DXC code +* + LHI R1,4096 Load Test Data Class mask starting point + LA R9,3(,R8) Point to first Test Data Class CC + BASR R6,0 Set start of Test Data Class loop + + SRL R1,1 Shift to get next class mask value + TCXB FPR8,0(,R1) Test value against class mask + IPM R0 Retrieve condition code + SRL R0,28 Move CC to low-order r0, dump prog mask + STC R0,0(,R9) Store in last byte of FPCR + LA R9,1(,R9) Point to next CC slot + LTR R1,R1 Have we tested all masks including zero + BNZR R6 ..no, at least one more to test + + LA R3,16(,R3) Point to next extended BFP test value + LA R7,32(,R7) Point to next Load And Test result pair + LA R8,16(,R8) Point to next CC result set + BCTR R2,R12 Loop through all test cases +* + BR R13 Tests done, return to mainline +* + LTORG + EJECT +*********************************************************************** +* +* Short integer inputs for Load And Test and Test Data Class. The same +* values are used for short, long, and extended formats. +* +*********************************************************************** + SPACE 2 +SBFPIN DS 0F Ensure fullword alignment for input table + DC X'00000000' +0 + DC X'80000000' -0 + DC X'3F800000' +1 + DC X'BF800000' -1 + DC X'007FFFFF' +subnormal + DC X'807FFFFF' -subnormal + DC X'7F800000' +infinity + DC X'FF800000' -infinity + DC X'7FC00000' +QNaN + DC X'FFC00000' -QNaN + DC X'7F810000' +SNaN + DC X'FF810000' -SNaN +SBFPINCT EQU (*-SBFPIN)/4 count of short BFP test values +* +SBFPINVL DC X'0000DEAD' Invalid result, used to polute result FPR + SPACE 3 +*********************************************************************** +* +* Long integer inputs for Load And Test and Test Data Class. The same +* values are used for short, long, and extended formats. +* +*********************************************************************** + SPACE 2 +LBFPIN DS 0D + DC X'0000000000000000' +0 + DC X'8000000000000000' -0 + DC X'3FF0000000000000' +1 + DC X'BFF0000000000000' -1 + DC X'000FFFFFFFFFFFFF' +subnormal + DC X'800FFFFFFFFFFFFF' -subnormal + DC X'7FF0000000000000' +infinity + DC X'FFF0000000000000' -infinity + DC X'7FF8000000000000' +QNaN + DC X'FFF8000000000000' -QNaN + DC X'7FF0100000000000' +SNaN + DC X'FFF0100000000000' -SNaN +LBFPINCT EQU (*-LBFPIN)/8 count of long BFP test values +* +LBFPINVL DC X'0000DEAD00000000' Invalid result, used to +* ..polute result FPR + SPACE 3 +*********************************************************************** +* +* Extended integer inputs for Load And Test and Test Data Class. The +* same values are used for short, long, and extended formats. +* +*********************************************************************** + SPACE 2 +XBFPIN DS 0D + DC X'00000000000000000000000000000000' +0 + DC X'80000000000000000000000000000000' -0 + DC X'3FFF0000000000000000000000000000' +1 + DC X'BFFF0000000000000000000000000000' -1 + DC X'0000FFFFFFFFFFFFFFFFFFFFFFFFFFFF' +subnormal + DC X'8000FFFFFFFFFFFFFFFFFFFFFFFFFFFF' -subnormal + DC X'7FFF0000000000000000000000000000' +infinity + DC X'FFFF0000000000000000000000000000' -infinity + DC X'7FFF8000000000000000000000000000' +QNaN + DC X'FFFF8000000000000000000000000000' -QNaN + DC X'7FFF0100000000000000000000000000' +SNaN + DC X'FFFF0100000000000000000000000000' -SNaN +XBFPINCT EQU (*-XBFPIN)/16 count of extended BFP test values +* +XBFPINVL DC X'0000DEAD000000000000000000000000' Invalid result, used to +* ..used to polute result FPR + SPACE 3 +*********************************************************************** +* +* Locations for results +* +*********************************************************************** + SPACE 2 +SBFPOUT EQU STRTLABL+X'1000' Integer short BFP Load and Test +* ..12 used, room for 60 tests +SBFPOCC EQU STRTLABL+X'1100' Condition codes from Load and Test +* ..and Test Data Class. +* ..12 sets used, room for 60 sets +* ..next available is X'1500' +* +LBFPOUT EQU STRTLABL+X'2000' Integer long BFP Load And Test +* ..12 used, room for 32 tests, +LBFPOCC EQU STRTLABL+X'2100' Condition codes from Load and Test +* ..and Test Data Class. +* ..12 sets used, room for 32 sets +* ..next available is X'2300' +* +XBFPOUT EQU STRTLABL+X'3000' Integer extended BFP Load And Test +* ..12 used, room for 32 tests, +XBFPOCC EQU STRTLABL+X'3200' Condition codes from Load and Test +* ..and Test Data Class. +* ..12 sets used, room for 32 sets +* ..next available is X'3400' +* +ENDLABL EQU STRTLABL+X'3400' + PADCSECT ENDLABL +* + END \ No newline at end of file diff --git a/tests/bfp-012-loadtest.core b/tests/bfp-012-loadtest.core new file mode 100644 index 000000000..23c266f6f Binary files /dev/null and b/tests/bfp-012-loadtest.core differ diff --git a/tests/bfp-012-loadtest.list b/tests/bfp-012-loadtest.list new file mode 100644 index 000000000..7b9d43a62 --- /dev/null +++ b/tests/bfp-012-loadtest.list @@ -0,0 +1,715 @@ +ASMA Ver. 0.2.0 bfp-012-loadtest.asm: Test IEEE Test Data Class, Load And Test 27 Sep 2016 15:36:20 Page 1 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 2 *********************************************************************** + 3 * + 4 *Testcase IEEE Test Data Classs and Load And Test + 5 * Exhaustively test results from the Test Data Class instruction. + 6 * Exhaustively test condition code setting from Load And Test. + 7 * The Condition Code, the only result from either instruction, is + 8 * saved for comparison with reference values. + 9 * + 10 *********************************************************************** + + + 12 *********************************************************************** + 13 * + 14 * Neither Load And Test nor Test Data Class can result in IEEE + 15 * exceptions. All tests are performed with the FPC set to not trap + 16 * on any exception. + 17 * + 18 * The same test data are used for both Load And Test and Test Data + 19 * Class. + 20 * + 21 * For Load And Test, the result value and condition code are stored. + 22 * For all but SNaN inputs, the result should be the same as the input. + 23 * For SNaN inputs, the result is the corresponding QNaN. + 24 * + 25 * For Test Data Class, 13 Condition codes are stored. The first + 26 * 12 correspond to a one-bit in each of 12 positions of the Test Data + 27 * class second operand mask, and the thirteenth is generated with a + 28 * mask of zero. Test Data Class mask bits: + 29 * + 30 * 1 0 0 0 | 0 0 0 0 | 0 0 0 0 + zero + 31 * 0 1 0 0 | 0 0 0 0 | 0 0 0 0 - zero + 32 * 0 0 1 0 | 0 0 0 0 | 0 0 0 0 + finite + 33 * 0 0 0 1 | 0 0 0 0 | 0 0 0 0 - finite + 34 * 0 0 0 0 | 1 0 0 0 | 0 0 0 0 + tiny + 35 * 0 0 0 0 | 0 1 0 0 | 0 0 0 0 - tiny + 36 * 0 0 0 0 | 0 0 1 0 | 0 0 0 0 + inf + 37 * 0 0 0 0 | 0 0 0 1 | 0 0 0 0 - inf + 38 * 0 0 0 0 | 0 0 0 0 | 1 0 0 0 + QNaN + 39 * 0 0 0 0 | 0 0 0 0 | 0 1 0 0 - QNaN + 40 * 0 0 0 0 | 0 0 0 0 | 0 0 1 0 + SNaN + 41 * 0 0 0 0 | 0 0 0 0 | 0 0 0 1 - SNaN + 42 * + 43 * Tests 3 LOAD AND TEST and 3 TEST DATA CLASS instructions + 44 * LOAD AND TEST (BFP short, RRE) LTEBR + 45 * LOAD AND TEST (BFP long, RRE) LTDBR + 46 * LOAD AND TEST (BFP extended, RRE) LTXBR + 47 * TEST DATA CLASS (BFP short, RRE) LTEBR + 48 * TEST DATA CLASS (BFP long, RRE) LTDBR + 49 * TEST DATA CLASS (BFP extended, RRE) LTXBR + 50 * + 51 * Also tests the following floating point support instructions + 52 * EXTRACT FPC + ASMA Ver. 0.2.0 bfp-012-loadtest.asm: Test IEEE Test Data Class, Load And Test 27 Sep 2016 15:36:20 Page 2 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 53 * LOAD (Short) + 54 * LOAD (Long) + 55 * LOAD ZERO (Long) + 56 * STORE (Short) + 57 * STORE (Long) + 58 * SET FPC + 59 * + 60 *********************************************************************** + + + 62 MACRO + 63 PADCSECT &ENDLABL + 64 .* + 65 .* Macro to pad the CSECT to include result data areas if this test + 66 .* program is not being assembled using asma. asma generates a core + 67 .* image that is loaded by the loadcore command, and because the + 68 .* core image is a binary stored in Github, it makes sense to make + 69 .* this small effort to keep the core image small. + 70 .* + 71 AIF (D'&ENDLABL).GOODPAD + 72 MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + 73 MNOTE *,'No CSECT padding performed' + 74 MEXIT + 75 .* + 76 .GOODPAD ANOP Label valid. See if we're on asma + 77 AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + 78 ORG &ENDLABL-1 Not ASMA. Pad CSECT + 79 MEXIT + 80 .* + 81 .NOPAD ANOP + 82 MNOTE *,'asma detected; no CSECT padding performed' + 83 MEND + 84 * + 85 * Note: for compatibility with the z/CMS test rig, do not change + 86 * or use R11, R14, or R15. Everything else is fair game. + 87 * + 0000000000000000 00000000000006C7 88 BFPLTTDC START 0 + 0000000000000000 0000000000000001 89 STRTLABL EQU * + 0000000000000000 0000000000000001 90 R0 EQU 0 Work register for cc extraction + 0000000000000001 0000000000000001 91 R1 EQU 1 Current Test Data Class mask + 0000000000000002 0000000000000001 92 R2 EQU 2 Holds count of test input values + 0000000000000003 0000000000000001 93 R3 EQU 3 Points to next test input value(s) + 0000000000000004 0000000000000001 94 R4 EQU 4 Available + 0000000000000005 0000000000000001 95 R5 EQU 5 Available + 0000000000000006 0000000000000001 96 R6 EQU 6 Test Data Class top of loop + 0000000000000007 0000000000000001 97 R7 EQU 7 Ptr to next result for Load And Test + 0000000000000008 0000000000000001 98 R8 EQU 8 Ptr to next CC for Load And Test + 0000000000000009 0000000000000001 99 R9 EQU 9 Ptr to next CC for Test Data Class + 000000000000000A 0000000000000001 100 R10 EQU 10 Pointer to test address list + 000000000000000B 0000000000000001 101 R11 EQU 11 **Reserved for z/CMS test rig + 000000000000000C 0000000000000001 102 R12 EQU 12 Test value top of loop + 000000000000000D 0000000000000001 103 R13 EQU 13 Mainline return address + ASMA Ver. 0.2.0 bfp-012-loadtest.asm: Test IEEE Test Data Class, Load And Test 27 Sep 2016 15:36:20 Page 3 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 000000000000000E 0000000000000001 104 R14 EQU 14 **Return address for z/CMS test rig + 000000000000000F 0000000000000001 105 R15 EQU 15 **Base register on z/CMS or Hyperion + 106 * + 107 * Floating Point Register equates to keep the cross reference clean + 108 * + 0000000000000000 0000000000000001 109 FPR0 EQU 0 + 0000000000000001 0000000000000001 110 FPR1 EQU 1 + 0000000000000002 0000000000000001 111 FPR2 EQU 2 + 0000000000000003 0000000000000001 112 FPR3 EQU 3 + 0000000000000004 0000000000000001 113 FPR4 EQU 4 + 0000000000000005 0000000000000001 114 FPR5 EQU 5 + 0000000000000006 0000000000000001 115 FPR6 EQU 6 + 0000000000000007 0000000000000001 116 FPR7 EQU 7 + 0000000000000008 0000000000000001 117 FPR8 EQU 8 + 0000000000000009 0000000000000001 118 FPR9 EQU 9 + 000000000000000A 0000000000000001 119 FPR10 EQU 10 + 000000000000000B 0000000000000001 120 FPR11 EQU 11 + 000000000000000C 0000000000000001 121 FPR12 EQU 12 + 000000000000000D 0000000000000001 122 FPR13 EQU 13 + 000000000000000E 0000000000000001 123 FPR14 EQU 14 + 000000000000000F 0000000000000001 124 FPR15 EQU 15 + 125 * +0000000000000000 0000000000000000 126 USING *,R15 + 127 * + 128 * Above works on real iron (R15=0 after sysclear) + 129 * and in z/CMS (R15 points to start of load module) + 130 * + + + 132 *********************************************************************** + 133 * + 134 * Low core definitions, Restart PSW, and Program Check Routine. + 135 * + 136 *********************************************************************** + + +0000000000000000 0000000000000000 000000000000008E 138 ORG STRTLABL+X'8E' Program check interrution code +000000000000008E 0000 139 PCINTCD DS H + 140 * + 0000000000000150 0000000000000001 141 PCOLDPSW EQU STRTLABL+X'150' z/Arch Program check old PSW + 142 * +0000000000000090 0000000000000090 00000000000001A0 143 ORG STRTLABL+X'1A0' z/Arch Restart PSW +00000000000001A0 00000001 80000000 144 DC X'0000000180000000',AD(START) + 145 * +00000000000001B0 00000000000001B0 00000000000001D0 146 ORG STRTLABL+X'1D0' z/Arch Program check old PSW +00000000000001D0 00000000 00000000 147 DC X'0000000000000000',AD(PROGCHK) + 148 * + 149 * Program check routine. If Data Exception, continue execution at + 150 * the instruction following the program check. Otherwise, hard wait. + 151 * No need to collect data. All interesting DXC stuff is captured + 152 * in the FPCR. + 153 * + ASMA Ver. 0.2.0 bfp-012-loadtest.asm: Test IEEE Test Data Class, Load And Test 27 Sep 2016 15:36:20 Page 4 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000001E0 00000000000001E0 0000000000000200 154 ORG STRTLABL+X'200' +0000000000000200 155 PROGCHK DS 0H Program check occured... +0000000000000200 9507 F08F 000000000000008F 156 CLI PCINTCD+1,X'07' Data Exception? +0000000000000204 A774 0004 000000000000020C 157 JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) +0000000000000208 B2B2 F150 0000000000000150 158 LPSWE PCOLDPSW ..yes, resume program execution +000000000000020C 159 PCNOTDTA DS 0H +000000000000020C 12EE 160 LTR R14,R14 Return address provided? +000000000000020E 077E 161 BNZR R14 Yes, return to z/CMS test rig. +0000000000000210 B2B2 F250 0000000000000250 162 LPSWE HARDWAIT Not data exception, enter disabled wait + ASMA Ver. 0.2.0 bfp-012-loadtest.asm: Test IEEE Test Data Class, Load And Test 27 Sep 2016 15:36:20 Page 5 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 164 *********************************************************************** + 165 * + 166 * Main program. Enable Advanced Floating Point, process test cases. + 167 * + 168 *********************************************************************** + + +0000000000000214 170 START DS 0H +0000000000000214 B600 F260 0000000000000260 171 STCTL R0,R0,CTLR0 Store CR0 to enable AFP +0000000000000218 9604 F261 0000000000000261 172 OI CTLR0+1,X'04' Turn on AFP bit +000000000000021C B700 F260 0000000000000260 173 LCTL R0,R0,CTLR0 Reload updated CR0 + 174 * +0000000000000220 41A0 F300 0000000000000300 175 LA R10,SHORTS Point to short BFP test inputs +0000000000000224 4DD0 F330 0000000000000330 176 BAS R13,TESTSBFP Perform short BFP tests + 177 * +0000000000000228 41A0 F310 0000000000000310 178 LA R10,LONGS Point to long BFP test inputs +000000000000022C 4DD0 F3DC 00000000000003DC 179 BAS R13,TESTLBFP Perform long BFP tests + 180 * +0000000000000230 41A0 F320 0000000000000320 181 LA R10,EXTDS Point to extended BFP test inputs +0000000000000234 4DD0 F488 0000000000000488 182 BAS R13,TESTXBFP Perform short BFP tests + 183 * +0000000000000238 12EE 184 LTR R14,R14 Return address provided? +000000000000023A 077E 185 BNZR R14 ..Yes, return to z/CMS test rig. +000000000000023C B2B2 F240 0000000000000240 186 LPSWE WAITPSW All done + 187 * +0000000000000240 188 DS 0D Ensure correct alignment for psw +0000000000000240 00020000 00000000 189 WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +0000000000000250 00020000 00000000 190 HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end + 191 * +0000000000000260 00000000 192 CTLR0 DS F +0000000000000264 00000000 193 FPCREGNT DC X'00000000' FPCR, trap no IEEE exceptions, zero flags +0000000000000268 F8000000 194 FPCREGTR DC X'F8000000' FPCR, trap all IEEE exceptions, zero flags + 195 * + 196 * Input values parameter list, four fullwords for each test data set + 197 * 1) Count, + 198 * 2) Address of inputs, + 199 * 3) Address to place results, and + 200 * 4) Address to place DXC/Flags/cc values. + 201 * +000000000000026C 000000000000026C 0000000000000300 202 ORG STRTLABL+X'300' Enable run-time replacement +0000000000000300 203 SHORTS DS 0F Input pairs for short BFP ests +0000000000000300 0000000C 204 DC A(SBFPINCT) +0000000000000304 0000055C 205 DC A(SBFPIN) +0000000000000308 00001000 206 DC A(SBFPOUT) +000000000000030C 00001100 207 DC A(SBFPOCC) + 208 * +0000000000000310 209 LONGS DS 0F Input pairs for long BFP testing +0000000000000310 0000000C 210 DC A(LBFPINCT) +0000000000000314 00000590 211 DC A(LBFPIN) +0000000000000318 00002000 212 DC A(LBFPOUT) +000000000000031C 00002100 213 DC A(LBFPOCC) + 214 * + ASMA Ver. 0.2.0 bfp-012-loadtest.asm: Test IEEE Test Data Class, Load And Test 27 Sep 2016 15:36:20 Page 6 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000320 215 EXTDS DS 0F Input pairs for extendedd BFP testing +0000000000000320 0000000C 216 DC A(XBFPINCT) +0000000000000324 000005F8 217 DC A(XBFPIN) +0000000000000328 00003000 218 DC A(XBFPOUT) +000000000000032C 00003200 219 DC A(XBFPOCC) + ASMA Ver. 0.2.0 bfp-012-loadtest.asm: Test IEEE Test Data Class, Load And Test 27 Sep 2016 15:36:20 Page 7 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 221 *********************************************************************** + 222 * Perform Short BFP Tests. This includes one execution of Load And + 223 * Test, followed by 13 executions of Test Data Class. The result value + 224 * and Condition code are saved for Load And Test, and the Condition + 225 * Code is saved for each execution of Test Data Class. + 226 * + 227 *********************************************************************** + + +0000000000000330 229 TESTSBFP DS 0H Test short BFP input values +0000000000000330 9823 A000 0000000000000000 230 LM R2,R3,0(R10) Get count and address of test input values +0000000000000334 9878 A008 0000000000000008 231 LM R7,R8,8(R10) Get address of result and CC areas. +0000000000000338 1222 232 LTR R2,R2 Any test cases? +000000000000033A 078D 233 BZR R13 ..No, return to caller +000000000000033C 0DC0 234 BASR R12,0 Set top of loop + 235 * +000000000000033E 7880 3000 0000000000000000 236 LE FPR8,0(,R3) Get short BFP test value + 237 * Polute the CC result area. Correct + 238 * ..results will clean it up. +0000000000000342 D20F 8000 F540 0000000000000000 0000000000000540 239 MVC 0(16,R8),=X'FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF' + 240 * +0000000000000348 B29D F264 0000000000000264 241 LFPC FPCREGNT Set exceptions non-trappable +000000000000034C 7810 F58C 000000000000058C 242 LE FPR1,SBFPINVL Ensure an unchanged FPR1 is detectable +0000000000000350 B222 0000 243 IPM R0 Get current program mask and CC +0000000000000354 5400 F550 0000000000000550 244 N R0,=X'CFFFFFFF' Turn off condition code bits +0000000000000358 5600 F554 0000000000000554 245 O R0,=X'20000000' Force condition code two +000000000000035C 0400 246 SPM R0 Set PSW CC to two +000000000000035E B302 0018 247 LTEBR FPR1,FPR8 Load and Test into FPR1 +0000000000000362 7010 7000 0000000000000000 248 STE FPR1,0(,R7) Store short BFP result +0000000000000366 B222 0000 249 IPM R0 Retrieve condition code +000000000000036A 8800 001C 000000000000001C 250 SRL R0,28 Move CC to low-order r0, dump prog mask +000000000000036E 4200 8000 0000000000000000 251 STC R0,0(,R8) Store in CC result area + 252 * +0000000000000372 B29D F268 0000000000000268 253 LFPC FPCREGTR Set exceptions non-trappable +0000000000000376 7810 F58C 000000000000058C 254 LE FPR1,SBFPINVL Ensure an unchanged FPR1 is detectable +000000000000037A B222 0000 255 IPM R0 Get current program mask and CC +000000000000037E 5400 F550 0000000000000550 256 N R0,=X'CFFFFFFF' Turn off condition code bits +0000000000000382 5600 F554 0000000000000554 257 O R0,=X'20000000' Force condition code two +0000000000000386 0400 258 SPM R0 Set PSW CC to two +0000000000000388 B302 0018 259 LTEBR FPR1,FPR8 Load and Test into FPR1 +000000000000038C 7010 7004 0000000000000004 260 STE FPR1,4(,R7) Store short BFP result +0000000000000390 B222 0000 261 IPM R0 Retrieve condition code +0000000000000394 8800 001C 000000000000001C 262 SRL R0,28 Move CC to low-order r0, dump prog mask +0000000000000398 4200 8001 0000000000000001 263 STC R0,1(,R8) Store in CC result area +000000000000039C B38C 0000 264 EFPC R0 Extract FPC contents to R0 +00000000000003A0 BE02 8002 0000000000000002 265 STCM R0,B'0010',2(R8) Store any DXC code + 266 * +00000000000003A4 A718 1000 267 LHI R1,4096 Load Test Data Class mask starting point +00000000000003A8 4190 8003 0000000000000003 268 LA R9,3(,R8) Point to first Test Data Class CC +00000000000003AC 0D60 269 BASR R6,0 Set start of Test Data Class loop + 270 * +00000000000003AE 8810 0001 0000000000000001 271 SRL R1,1 Shift to get next class mask value + ASMA Ver. 0.2.0 bfp-012-loadtest.asm: Test IEEE Test Data Class, Load And Test 27 Sep 2016 15:36:20 Page 8 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000003B2 ED80 1000 0010 0000000000000000 272 TCEB FPR8,0(,R1) Test value against class mask +00000000000003B8 B222 0000 273 IPM R0 Retrieve condition code +00000000000003BC 8800 001C 000000000000001C 274 SRL R0,28 Move CC to low-order r0, dump prog mask +00000000000003C0 4200 9000 0000000000000000 275 STC R0,0(,R9) Store in CC result area +00000000000003C4 4190 9001 0000000000000001 276 LA R9,1(,R9) Point to next CC slot +00000000000003C8 1211 277 LTR R1,R1 Have we tested all masks including zero +00000000000003CA 0776 278 BNZR R6 ..no, at least one more to test + 279 +00000000000003CC 4130 3004 0000000000000004 280 LA R3,4(,R3) Point to next short BFP test value +00000000000003D0 4170 7008 0000000000000008 281 LA R7,8(,R7) Point to next Load And Test result pair +00000000000003D4 4180 8010 0000000000000010 282 LA R8,16(,R8) Point to next CC result set +00000000000003D8 062C 283 BCTR R2,R12 Loop through all test cases + 284 * +00000000000003DA 07FD 285 BR R13 Tests done, return to mainline + ASMA Ver. 0.2.0 bfp-012-loadtest.asm: Test IEEE Test Data Class, Load And Test 27 Sep 2016 15:36:20 Page 9 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 287 *********************************************************************** + 288 * Perform long BFP Tests. This includes one execution of Load And + 289 * Test, followed by 13 executions of Test Data Class. The result value + 290 * and Condition code are saved for Load And Test, and the Condition + 291 * Code is saved for each execution of Test Data Class. + 292 * + 293 *********************************************************************** + + +00000000000003DC 295 TESTLBFP DS 0H Test long BFP input values +00000000000003DC 9823 A000 0000000000000000 296 LM R2,R3,0(R10) Get count and address of test input values +00000000000003E0 9878 A008 0000000000000008 297 LM R7,R8,8(R10) Get address of result and CC areas. +00000000000003E4 1222 298 LTR R2,R2 Any test cases? +00000000000003E6 078D 299 BZR R13 ..No, return to caller +00000000000003E8 0DC0 300 BASR R12,0 Set top of loop + 301 * +00000000000003EA 6880 3000 0000000000000000 302 LD FPR8,0(,R3) Get long BFP test value + 303 * Polute the CC result area. Correct + 304 * ..results will clean it up. +00000000000003EE D20F 8000 F540 0000000000000000 0000000000000540 305 MVC 0(16,R8),=X'FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF' + 306 * +00000000000003F4 B29D F264 0000000000000264 307 LFPC FPCREGNT Set exceptions non-trappable +00000000000003F8 6810 F5F0 00000000000005F0 308 LD FPR1,LBFPINVL Ensure an unchanged FPR1 is detectable +00000000000003FC B222 0000 309 IPM R0 Get current program mask and CC +0000000000000400 5400 F550 0000000000000550 310 N R0,=X'CFFFFFFF' Turn off condition code bits +0000000000000404 5600 F558 0000000000000558 311 O R0,=X'10000000' Force condition code one +0000000000000408 0400 312 SPM R0 Set PSW CC to one +000000000000040A B312 0018 313 LTDBR FPR1,FPR8 Load and Test into FPR1 +000000000000040E 6010 7000 0000000000000000 314 STD FPR1,0(,R7) Store long BFP result +0000000000000412 B222 0000 315 IPM R0 Retrieve condition code +0000000000000416 8800 001C 000000000000001C 316 SRL R0,28 Move CC to low-order r0, dump prog mask +000000000000041A 4200 8000 0000000000000000 317 STC R0,0(,R8) Store in CC result area + 318 * +000000000000041E B29D F268 0000000000000268 319 LFPC FPCREGTR Set exceptions trappable +0000000000000422 6810 F5F0 00000000000005F0 320 LD FPR1,LBFPINVL Ensure an unchanged FPR1 is detectable +0000000000000426 B222 0000 321 IPM R0 Get current program mask and CC +000000000000042A 5400 F550 0000000000000550 322 N R0,=X'CFFFFFFF' Turn off condition code bits +000000000000042E 5600 F558 0000000000000558 323 O R0,=X'10000000' Force condition code one +0000000000000432 0400 324 SPM R0 Set PSW CC to one +0000000000000434 B312 0018 325 LTDBR FPR1,FPR8 Load and Test into FPR1 +0000000000000438 6010 7008 0000000000000008 326 STD FPR1,8(,R7) Store long BFP result +000000000000043C B222 0000 327 IPM R0 Retrieve condition code +0000000000000440 8800 001C 000000000000001C 328 SRL R0,28 Move CC to low-order r0, dump prog mask +0000000000000444 4200 8001 0000000000000001 329 STC R0,1(,R8) Store in CC result area +0000000000000448 B38C 0000 330 EFPC R0 Extract FPC contents to R0 +000000000000044C BE02 8002 0000000000000002 331 STCM R0,B'0010',2(R8) Store any DXC code + 332 * +0000000000000450 A718 1000 333 LHI R1,4096 Load Test Data Class mask starting point +0000000000000454 4190 8003 0000000000000003 334 LA R9,3(,R8) Point to first Test Data Class CC +0000000000000458 0D60 335 BASR R6,0 Set start of Test Data Class loop + 336 +000000000000045A 8810 0001 0000000000000001 337 SRL R1,1 Shift to get next class mask value + ASMA Ver. 0.2.0 bfp-012-loadtest.asm: Test IEEE Test Data Class, Load And Test 27 Sep 2016 15:36:20 Page 10 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +000000000000045E ED80 1000 0011 0000000000000000 338 TCDB FPR8,0(,R1) Test value against class mask +0000000000000464 B222 0000 339 IPM R0 Retrieve condition code +0000000000000468 8800 001C 000000000000001C 340 SRL R0,28 Move CC to low-order r0, dump prog mask +000000000000046C 4200 9000 0000000000000000 341 STC R0,0(,R9) Store in CC result area +0000000000000470 4190 9001 0000000000000001 342 LA R9,1(,R9) Point to next CC slot +0000000000000474 1211 343 LTR R1,R1 Have we tested all masks including zero +0000000000000476 0776 344 BNZR R6 ..no, at least one more to test + 345 +0000000000000478 4130 3008 0000000000000008 346 LA R3,8(,R3) Point to next long BFP test value +000000000000047C 4170 7010 0000000000000010 347 LA R7,16(,R7) Point to next Load And Test result pair +0000000000000480 4180 8010 0000000000000010 348 LA R8,16(,R8) Point to next CC result set +0000000000000484 062C 349 BCTR R2,R12 Loop through all test cases + 350 * +0000000000000486 07FD 351 BR R13 Tests done, return to mainline + ASMA Ver. 0.2.0 bfp-012-loadtest.asm: Test IEEE Test Data Class, Load And Test 27 Sep 2016 15:36:20 Page 11 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 353 *********************************************************************** + 354 * Perform extended BFP Tests. This includes one execution of Load And + 355 * Test, followed by 13 executions of Test Data Class. The result value + 356 * and Condition code are saved for Load And Test, and the Condition + 357 * Code is saved for each execution of Test Data Class. + 358 * + 359 *********************************************************************** + + +0000000000000488 361 TESTXBFP DS 0H Test extended BFP input values +0000000000000488 9823 A000 0000000000000000 362 LM R2,R3,0(R10) Get count and address of test input values +000000000000048C 9878 A008 0000000000000008 363 LM R7,R8,8(R10) Get address of result and CC areas. +0000000000000490 1222 364 LTR R2,R2 Any test cases? +0000000000000492 078D 365 BZR R13 ..No, return to caller +0000000000000494 0DC0 366 BASR R12,0 Set top of loop + 367 * +0000000000000496 6880 3000 0000000000000000 368 LD FPR8,0(,R3) Get extended BFP test value part 1 +000000000000049A 68A0 3008 0000000000000008 369 LD FPR10,8(,R3) Get extended BFP test value part 2 + 370 * Polute the CC result area. Correct + 371 * ..results will clean it up. +000000000000049E D20F 8000 F540 0000000000000000 0000000000000540 372 MVC 0(16,R8),=X'FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF' + 373 * +00000000000004A4 B29D F264 0000000000000264 374 LFPC FPCREGNT Set exceptions non-trappable +00000000000004A8 6810 F6B8 00000000000006B8 375 LD FPR1,XBFPINVL Ensure an unchanged FPR1-3 is detectable +00000000000004AC 6830 F6C0 00000000000006C0 376 LD FPR3,XBFPINVL+8 ..part 2 of load FPR pair +00000000000004B0 B222 0000 377 IPM R0 Get current program mask and CC +00000000000004B4 5400 F550 0000000000000550 378 N R0,=X'CFFFFFFF' Turn off condition code bits +00000000000004B8 0400 379 SPM R0 Set PSW CC to zero +00000000000004BA B342 0018 380 LTXBR FPR1,FPR8 Load and Test into FPR1 +00000000000004BE 6010 7000 0000000000000000 381 STD FPR1,0(,R7) Store extended BFP result part 1 +00000000000004C2 6030 7008 0000000000000008 382 STD FPR3,8(,R7) Store extended BFP result part 2 +00000000000004C6 B222 0000 383 IPM R0 Retrieve condition code +00000000000004CA 8800 001C 000000000000001C 384 SRL R0,28 Move CC to low-order r0, dump prog mask +00000000000004CE 4200 8000 0000000000000000 385 STC R0,0(,R8) Store in CC result area + 386 * +00000000000004D2 B29D F268 0000000000000268 387 LFPC FPCREGTR Set exceptions trappable +00000000000004D6 6810 F6B8 00000000000006B8 388 LD FPR1,XBFPINVL Ensure an unchanged FPR1-3 is detectable +00000000000004DA 6830 F6C0 00000000000006C0 389 LD FPR3,XBFPINVL+8 ..part 2 of load FPR pair +00000000000004DE B222 0000 390 IPM R0 Get current program mask and CC +00000000000004E2 5400 F550 0000000000000550 391 N R0,=X'CFFFFFFF' Turn off condition code bits +00000000000004E6 0400 392 SPM R0 Set PSW CC to zero +00000000000004E8 B342 0018 393 LTXBR FPR1,FPR8 Load and Test into FPR1 +00000000000004EC 6010 7010 0000000000000010 394 STD FPR1,16(,R7) Store extended BFP result part 1 +00000000000004F0 6030 7018 0000000000000018 395 STD FPR3,24(,R7) Store extended BFP result part 2 +00000000000004F4 B222 0000 396 IPM R0 Retrieve condition code +00000000000004F8 8800 001C 000000000000001C 397 SRL R0,28 Move CC to low-order r0, dump prog mask +00000000000004FC 4200 8001 0000000000000001 398 STC R0,1(,R8) Store in CC result area +0000000000000500 B38C 0000 399 EFPC R0 Extract FPC contents to R0 +0000000000000504 BE02 8002 0000000000000002 400 STCM R0,B'0010',2(R8) Store any DXC code + 401 * +0000000000000508 A718 1000 402 LHI R1,4096 Load Test Data Class mask starting point +000000000000050C 4190 8003 0000000000000003 403 LA R9,3(,R8) Point to first Test Data Class CC + ASMA Ver. 0.2.0 bfp-012-loadtest.asm: Test IEEE Test Data Class, Load And Test 27 Sep 2016 15:36:20 Page 12 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000510 0D60 404 BASR R6,0 Set start of Test Data Class loop + 405 +0000000000000512 8810 0001 0000000000000001 406 SRL R1,1 Shift to get next class mask value +0000000000000516 ED80 1000 0012 0000000000000000 407 TCXB FPR8,0(,R1) Test value against class mask +000000000000051C B222 0000 408 IPM R0 Retrieve condition code +0000000000000520 8800 001C 000000000000001C 409 SRL R0,28 Move CC to low-order r0, dump prog mask +0000000000000524 4200 9000 0000000000000000 410 STC R0,0(,R9) Store in last byte of FPCR +0000000000000528 4190 9001 0000000000000001 411 LA R9,1(,R9) Point to next CC slot +000000000000052C 1211 412 LTR R1,R1 Have we tested all masks including zero +000000000000052E 0776 413 BNZR R6 ..no, at least one more to test + 414 +0000000000000530 4130 3010 0000000000000010 415 LA R3,16(,R3) Point to next extended BFP test value +0000000000000534 4170 7020 0000000000000020 416 LA R7,32(,R7) Point to next Load And Test result pair +0000000000000538 4180 8010 0000000000000010 417 LA R8,16(,R8) Point to next CC result set +000000000000053C 062C 418 BCTR R2,R12 Loop through all test cases + 419 * +000000000000053E 07FD 420 BR R13 Tests done, return to mainline + 421 * +0000000000000540 422 LTORG +0000000000000540 FFFFFFFF FFFFFFFF 423 =X'FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF' +0000000000000550 CFFFFFFF 424 =X'CFFFFFFF' +0000000000000554 20000000 425 =X'20000000' +0000000000000558 10000000 426 =X'10000000' + ASMA Ver. 0.2.0 bfp-012-loadtest.asm: Test IEEE Test Data Class, Load And Test 27 Sep 2016 15:36:20 Page 13 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 428 *********************************************************************** + 429 * + 430 * Short integer inputs for Load And Test and Test Data Class. The same + 431 * values are used for short, long, and extended formats. + 432 * + 433 *********************************************************************** + + +000000000000055C 435 SBFPIN DS 0F Ensure fullword alignment for input table +000000000000055C 00000000 436 DC X'00000000' +0 +0000000000000560 80000000 437 DC X'80000000' -0 +0000000000000564 3F800000 438 DC X'3F800000' +1 +0000000000000568 BF800000 439 DC X'BF800000' -1 +000000000000056C 007FFFFF 440 DC X'007FFFFF' +subnormal +0000000000000570 807FFFFF 441 DC X'807FFFFF' -subnormal +0000000000000574 7F800000 442 DC X'7F800000' +infinity +0000000000000578 FF800000 443 DC X'FF800000' -infinity +000000000000057C 7FC00000 444 DC X'7FC00000' +QNaN +0000000000000580 FFC00000 445 DC X'FFC00000' -QNaN +0000000000000584 7F810000 446 DC X'7F810000' +SNaN +0000000000000588 FF810000 447 DC X'FF810000' -SNaN + 000000000000000C 0000000000000001 448 SBFPINCT EQU (*-SBFPIN)/4 count of short BFP test values + 449 * +000000000000058C 0000DEAD 450 SBFPINVL DC X'0000DEAD' Invalid result, used to polute result FPR + + + + 452 *********************************************************************** + 453 * + 454 * Long integer inputs for Load And Test and Test Data Class. The same + 455 * values are used for short, long, and extended formats. + 456 * + 457 *********************************************************************** + + +0000000000000590 459 LBFPIN DS 0D +0000000000000590 00000000 00000000 460 DC X'0000000000000000' +0 +0000000000000598 80000000 00000000 461 DC X'8000000000000000' -0 +00000000000005A0 3FF00000 00000000 462 DC X'3FF0000000000000' +1 +00000000000005A8 BFF00000 00000000 463 DC X'BFF0000000000000' -1 +00000000000005B0 000FFFFF FFFFFFFF 464 DC X'000FFFFFFFFFFFFF' +subnormal +00000000000005B8 800FFFFF FFFFFFFF 465 DC X'800FFFFFFFFFFFFF' -subnormal +00000000000005C0 7FF00000 00000000 466 DC X'7FF0000000000000' +infinity +00000000000005C8 FFF00000 00000000 467 DC X'FFF0000000000000' -infinity +00000000000005D0 7FF80000 00000000 468 DC X'7FF8000000000000' +QNaN +00000000000005D8 FFF80000 00000000 469 DC X'FFF8000000000000' -QNaN +00000000000005E0 7FF01000 00000000 470 DC X'7FF0100000000000' +SNaN +00000000000005E8 FFF01000 00000000 471 DC X'FFF0100000000000' -SNaN + 000000000000000C 0000000000000001 472 LBFPINCT EQU (*-LBFPIN)/8 count of long BFP test values + 473 * +00000000000005F0 0000DEAD 00000000 474 LBFPINVL DC X'0000DEAD00000000' Invalid result, used to + 475 * ..polute result FPR + ASMA Ver. 0.2.0 bfp-012-loadtest.asm: Test IEEE Test Data Class, Load And Test 27 Sep 2016 15:36:20 Page 14 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + + + + 477 *********************************************************************** + 478 * + 479 * Extended integer inputs for Load And Test and Test Data Class. The + 480 * same values are used for short, long, and extended formats. + 481 * + 482 *********************************************************************** + + +00000000000005F8 484 XBFPIN DS 0D +00000000000005F8 00000000 00000000 485 DC X'00000000000000000000000000000000' +0 +0000000000000608 80000000 00000000 486 DC X'80000000000000000000000000000000' -0 +0000000000000618 3FFF0000 00000000 487 DC X'3FFF0000000000000000000000000000' +1 +0000000000000628 BFFF0000 00000000 488 DC X'BFFF0000000000000000000000000000' -1 +0000000000000638 0000FFFF FFFFFFFF 489 DC X'0000FFFFFFFFFFFFFFFFFFFFFFFFFFFF' +subnormal +0000000000000648 8000FFFF FFFFFFFF 490 DC X'8000FFFFFFFFFFFFFFFFFFFFFFFFFFFF' -subnormal +0000000000000658 7FFF0000 00000000 491 DC X'7FFF0000000000000000000000000000' +infinity +0000000000000668 FFFF0000 00000000 492 DC X'FFFF0000000000000000000000000000' -infinity +0000000000000678 7FFF8000 00000000 493 DC X'7FFF8000000000000000000000000000' +QNaN +0000000000000688 FFFF8000 00000000 494 DC X'FFFF8000000000000000000000000000' -QNaN +0000000000000698 7FFF0100 00000000 495 DC X'7FFF0100000000000000000000000000' +SNaN +00000000000006A8 FFFF0100 00000000 496 DC X'FFFF0100000000000000000000000000' -SNaN + 000000000000000C 0000000000000001 497 XBFPINCT EQU (*-XBFPIN)/16 count of extended BFP test values + 498 * +00000000000006B8 0000DEAD 00000000 499 XBFPINVL DC X'0000DEAD000000000000000000000000' Invalid result, used to + 500 * ..used to polute result FPR + + + + 502 *********************************************************************** + 503 * + 504 * Locations for results + 505 * + 506 *********************************************************************** + + + 0000000000001000 0000000000000001 508 SBFPOUT EQU STRTLABL+X'1000' Integer short BFP Load and Test + 509 * ..12 used, room for 60 tests + 0000000000001100 0000000000000001 510 SBFPOCC EQU STRTLABL+X'1100' Condition codes from Load and Test + 511 * ..and Test Data Class. + 512 * ..12 sets used, room for 60 sets + 513 * ..next available is X'1500' + 514 * + 0000000000002000 0000000000000001 515 LBFPOUT EQU STRTLABL+X'2000' Integer long BFP Load And Test + 516 * ..12 used, room for 32 tests, + 0000000000002100 0000000000000001 517 LBFPOCC EQU STRTLABL+X'2100' Condition codes from Load and Test + 518 * ..and Test Data Class. + 519 * ..12 sets used, room for 32 sets + 520 * ..next available is X'2300' + 521 * + ASMA Ver. 0.2.0 bfp-012-loadtest.asm: Test IEEE Test Data Class, Load And Test 27 Sep 2016 15:36:20 Page 15 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 0000000000003000 0000000000000001 522 XBFPOUT EQU STRTLABL+X'3000' Integer extended BFP Load And Test + 523 * ..12 used, room for 32 tests, + 0000000000003200 0000000000000001 524 XBFPOCC EQU STRTLABL+X'3200' Condition codes from Load and Test + 525 * ..and Test Data Class. + 526 * ..12 sets used, room for 32 sets + 527 * ..next available is X'3400' + 528 * + 0000000000003400 0000000000000001 529 ENDLABL EQU STRTLABL+X'3400' + 530 PADCSECT ENDLABL + 531+ MNOTE *,'asma detected; no CSECT padding performed' + 532 * +00000000000006C8 533 END + ASMA Ver. 0.2.0 bfp-012-loadtest.asm: Test IEEE Test Data Class, Load And Test 27 Sep 2016 15:36:20 Page 16 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +BFPLTTDC J 000000 1736 88 +CTLR0 F 000260 4 192 171 172 173 +ENDLABL U 003400 1 529 +EXTDS F 000320 4 215 181 +FPCREGNT X 000264 4 193 241 307 374 +FPCREGTR X 000268 4 194 253 319 387 +FPR0 U 000000 1 109 +FPR1 U 000001 1 110 242 247 248 254 259 260 308 313 314 320 325 326 375 380 381 388 393 + 394 +FPR10 U 00000A 1 119 369 +FPR11 U 00000B 1 120 +FPR12 U 00000C 1 121 +FPR13 U 00000D 1 122 +FPR14 U 00000E 1 123 +FPR15 U 00000F 1 124 +FPR2 U 000002 1 111 +FPR3 U 000003 1 112 376 382 389 395 +FPR4 U 000004 1 113 +FPR5 U 000005 1 114 +FPR6 U 000006 1 115 +FPR7 U 000007 1 116 +FPR8 U 000008 1 117 236 247 259 272 302 313 325 338 368 380 393 407 +FPR9 U 000009 1 118 +HARDWAIT X 000250 8 190 162 +IMAGE 1 000000 1736 0 +LBFPIN D 000590 8 459 472 211 +LBFPINCT U 00000C 1 472 210 +LBFPINVL X 0005F0 8 474 308 320 +LBFPOCC U 002100 1 517 213 +LBFPOUT U 002000 1 515 212 +LONGS F 000310 4 209 178 +PCINTCD H 00008E 2 139 156 +PCNOTDTA H 00020C 2 159 157 +PCOLDPSW U 000150 1 141 158 +PROGCHK H 000200 2 155 147 +R0 U 000000 1 90 171 173 243 244 245 246 249 250 251 255 256 257 258 261 262 263 264 + 265 273 274 275 309 310 311 312 315 316 317 321 322 323 324 327 328 + 329 330 331 339 340 341 377 378 379 383 384 385 390 391 392 396 397 + 398 399 400 408 409 410 +R1 U 000001 1 91 267 271 272 277 333 337 338 343 402 406 407 412 +R10 U 00000A 1 100 175 178 181 230 231 296 297 362 363 +R11 U 00000B 1 101 +R12 U 00000C 1 102 234 283 300 349 366 418 +R13 U 00000D 1 103 176 179 182 233 285 299 351 365 420 +R14 U 00000E 1 104 160 161 184 185 +R15 U 00000F 1 105 126 +R2 U 000002 1 92 230 232 283 296 298 349 362 364 418 +R3 U 000003 1 93 230 236 280 296 302 346 362 368 369 415 +R4 U 000004 1 94 +R5 U 000005 1 95 +R6 U 000006 1 96 269 278 335 344 404 413 +R7 U 000007 1 97 231 248 260 281 297 314 326 347 363 381 382 394 395 416 + ASMA Ver. 0.2.0 bfp-012-loadtest.asm: Test IEEE Test Data Class, Load And Test 27 Sep 2016 15:36:20 Page 17 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +R8 U 000008 1 98 231 239 251 263 265 268 282 297 305 317 329 331 334 348 363 372 385 + 398 400 403 417 +R9 U 000009 1 99 268 275 276 334 341 342 403 410 411 +SBFPIN F 00055C 4 435 448 205 +SBFPINCT U 00000C 1 448 204 +SBFPINVL X 00058C 4 450 242 254 +SBFPOCC U 001100 1 510 207 +SBFPOUT U 001000 1 508 206 +SHORTS F 000300 4 203 175 +START H 000214 2 170 144 +STRTLABL U 000000 1 89 138 141 143 146 154 202 508 510 515 517 522 524 529 +TESTLBFP H 0003DC 2 295 179 +TESTSBFP H 000330 2 229 176 +TESTXBFP H 000488 2 361 182 +WAITPSW X 000240 8 189 186 +XBFPIN D 0005F8 8 484 497 217 +XBFPINCT U 00000C 1 497 216 +XBFPINVL X 0006B8 16 499 375 376 388 389 +XBFPOCC U 003200 1 524 219 +XBFPOUT U 003000 1 522 218 +=X'10000000' X 000558 4 426 311 323 +=X'20000000' X 000554 4 425 245 257 +=X'CFFFFFFF' X 000550 4 424 244 256 310 322 378 391 +=X'FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF' + X 000540 16 423 239 305 372 + ASMA Ver. 0.2.0 bfp-012-loadtest.asm: Test IEEE Test Data Class, Load And Test 27 Sep 2016 15:36:20 Page 18 + + MACRO DEFN REFERENCES + +PADCSECT 63 530 + ASMA Ver. 0.2.0 bfp-012-loadtest.asm: Test IEEE Test Data Class, Load And Test 27 Sep 2016 15:36:20 Page 19 + + DESC SYMBOL SIZE POS ADDR + +Entry: 0 + +Image IMAGE 1736 000-6C7 000-6C7 + Region 1736 000-6C7 000-6C7 + CSECT BFPLTTDC 1736 000-6C7 000-6C7 + ASMA Ver. 0.2.0 bfp-012-loadtest.asm: Test IEEE Test Data Class, Load And Test 27 Sep 2016 15:36:20 Page 20 + + STMT FILE NAME + +1 C:\Users\srorso\Documents\GitHub\hyperion\tests\bfp-012-loadtest.asm + + +** NO ERRORS FOUND ** + +[531] MNOTE *,asma detected; no CSECT padding performed + \ No newline at end of file diff --git a/tests/bfp-012-loadtest.tst b/tests/bfp-012-loadtest.tst new file mode 100644 index 000000000..910502f49 --- /dev/null +++ b/tests/bfp-012-loadtest.tst @@ -0,0 +1,213 @@ +*Testcase bfp-012-loadtest.tst: LTEBR, LTDBR, LTXBR, TCEB, TCDB, TCXB + +#Testcase bfp-012-loadtest.tst: IEEE Load and Test, Test Data Class +#..Includes LOAD AND TEST (3), TEST DATA CLASS (3), 6 instructions total. +#..Test case values exhaustively test above instructions. + +sysclear +archmode esame + +# +# Following suppresses logging of program checks. This test program, as part +# of its normal operation, generates 6 program check messages that have no +# value in the validation process. (The messages, not the program checks.) +# +ostailor quiet + +loadcore "$(testpath)/bfp-012-loadtest.core" +runtest 1.0 + +ostailor null # restore messages for subsequent tests + + +# Test Results - Load and Test +# Operand 1 from Load and Test is stored (one pair, non-trap and trap) +# Condition code is stored in first two bytes of condition codes, +# ..followed by DXC from trappable execution in byte three. + +# Test Results - Test Data Class +# 13 Condition codes are stored starting at byte four (displacement three) +# of the condition code table. + + + +# Short BFP test results - Load and Test +*Compare +r 1000.10 +*Want "LTEBR +/-0" 00000000 00000000 80000000 80000000 +r 1010.10 +*Want "LTEBR +/-1" 3F800000 3F800000 BF800000 BF800000 +r 1020.10 +*Want "LTEBR +/-tiny" 007FFFFF 007FFFFF 807FFFFF 807FFFFF +r 1030.10 +*Want "LTEBR +/-inf" 7F800000 7F800000 FF800000 FF800000 +r 1040.10 +*Want "LTEBR +/-QNaN" 7FC00000 7FC00000 FFC00000 FFC00000 +r 1050.10 +*Want "LTEBR +/-SNaN" 7FC10000 0000DEAD FFC10000 0000DEAD + +# Short BFP test results - Test Data Class +*Compare +r 1100.10 +*Want "TCEB CC +0" 00000001 00000000 00000000 00000000 +r 1110.10 +*Want "TCEB CC -0" 00000000 01000000 00000000 00000000 +r 1120.10 +*Want "TCEB CC +1" 02020000 00010000 00000000 00000000 +r 1130.10 +*Want "TCEB CC -1" 01010000 00000100 00000000 00000000 +r 1140.10 +*Want "TCEB CC +tiny" 02020000 00000001 00000000 00000000 +r 1150.10 +*Want "TCEB CC -tiny" 01010000 00000000 01000000 00000000 +r 1160.10 +*Want "TCEB CC +inf" 02020000 00000000 00010000 00000000 +r 1170.10 +*Want "TCEB CC -inf" 01010000 00000000 00000100 00000000 +r 1180.10 +*Want "TCEB CC +QNaN" 03030000 00000000 00000001 00000000 +r 1190.10 +*Want "TCEB CC -QNaN" 03030000 00000000 00000000 01000000 +r 11A0.10 +*Want "TCEB CC +SNaN" 03028000 00000000 00000000 00010000 +r 11B0.10 +*Want "TCEB CC -SNaN" 03028000 00000000 00000000 00000100 + + +# Long BFP test results - Load and Test +*Compare +r 2000.10 +*Want "LTDBR +0" 00000000 00000000 00000000 00000000 +r 2010.10 +*Want "LTDBR -0" 80000000 00000000 80000000 00000000 +r 2020.10 +*Want "LTDBR +1" 3FF00000 00000000 3FF00000 00000000 +r 2030.10 +*Want "LTDBR -1" BFF00000 00000000 BFF00000 00000000 +r 2040.10 +*Want "LTDBR +tiny" 000FFFFF FFFFFFFF 000FFFFF FFFFFFFF +r 2050.10 +*Want "LTDBR -tiny" 800FFFFF FFFFFFFF 800FFFFF FFFFFFFF +r 2060.10 +*Want "LTDBR +inf" 7FF00000 00000000 7FF00000 00000000 +r 2070.10 +*Want "LTDBR -inf" FFF00000 00000000 FFF00000 00000000 +r 2080.10 +*Want "LTDBR +QNaN" 7FF80000 00000000 7FF80000 00000000 +r 2090.10 +*Want "LTDBR -QNaN" FFF80000 00000000 FFF80000 00000000 +r 20A0.10 +*Want "LTDBR +SNaN" 7FF81000 00000000 0000DEAD 00000000 +r 20B0.10 +*Want "LTDBR -SNaN" FFF81000 00000000 0000DEAD 00000000 + + +# Long BFP test results - Test Data Class +*Compare +r 2100.10 +*Want "TCDB CC +0" 00000001 00000000 00000000 00000000 +r 2110.10 +*Want "TCDB CC -0" 00000000 01000000 00000000 00000000 +r 2120.10 +*Want "TCDB CC +1" 02020000 00010000 00000000 00000000 +r 2130.10 +*Want "TCDB CC -1" 01010000 00000100 00000000 00000000 +r 2140.10 +*Want "TCDB CC +tiny" 02020000 00000001 00000000 00000000 +r 2150.10 +*Want "TCDB CC -tiny" 01010000 00000000 01000000 00000000 +r 2160.10 +*Want "TCDB CC +inf" 02020000 00000000 00010000 00000000 +r 2170.10 +*Want "TCDB CC -inf" 01010000 00000000 00000100 00000000 +r 2180.10 +*Want "TCDB CC +QNaN" 03030000 00000000 00000001 00000000 +r 2190.10 +*Want "TCDB CC -QNaN" 03030000 00000000 00000000 01000000 +r 21A0.10 +*Want "TCDB CC +SNaN" 03018000 00000000 00000000 00010000 +r 21B0.10 +*Want "TCDB CC -SNaN" 03018000 00000000 00000000 00000100 + + +# Extended BFP test results - Load and Test +*Compare +r 3000.10 +*Want "LTXBR +/0 NT" 00000000 00000000 00000000 00000000 +r 3010.10 +*Want "LTXBR +/0 TR" 00000000 00000000 00000000 00000000 +r 3020.10 +*Want "LTXBR -0 NT" 80000000 00000000 00000000 00000000 +r 3030.10 +*Want "LTXBR -0 TR" 80000000 00000000 00000000 00000000 +r 3040.10 +*Want "LTXBR +1 NT" 3FFF0000 00000000 00000000 00000000 +r 3050.10 +*Want "LTXBR +1 TR" 3FFF0000 00000000 00000000 00000000 +r 3060.10 +*Want "LTXBR -1 NT" BFFF0000 00000000 00000000 00000000 +r 3070.10 +*Want "LTXBR -1 TR" BFFF0000 00000000 00000000 00000000 +r 3080.10 +*Want "LTXBR +tiny NT" 0000FFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 3090.10 +*Want "LTXBR +tiny" 0000FFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 30A0.10 +*Want "LTXBR -tiny NT" 8000FFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 30B0.10 +*Want "LTXBR -tiny TR" 8000FFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 30C0.10 +*Want "LTXBR +inf NT" 7FFF0000 00000000 00000000 00000000 +r 30D0.10 +*Want "LTXBR +inf TR" 7FFF0000 00000000 00000000 00000000 +r 30E0.10 +*Want "LTXBR -inf NT" FFFF0000 00000000 00000000 00000000 +r 30F0.10 +*Want "LTXBR -inf TR" FFFF0000 00000000 00000000 00000000 +r 3100.10 +*Want "LTXBR +QNaN NT" 7FFF8000 00000000 00000000 00000000 +r 3110.10 +*Want "LTXBR +QNaN" 7FFF8000 00000000 00000000 00000000 +r 3120.10 +*Want "LTXBR -QNaN NT" FFFF8000 00000000 00000000 00000000 +r 3130.10 +*Want "LTXBR -QNaN TR" FFFF8000 00000000 00000000 00000000 +r 3140.10 +*Want "LTXBR +SNaN NT" 7FFF8100 00000000 00000000 00000000 +r 3150.10 +*Want "LTXBR +SNaN TR" 0000DEAD 00000000 00000000 00000000 +r 3160.10 +*Want "LTXBR -SNaN NT" FFFF8100 00000000 00000000 00000000 +r 3170.10 +*Want "LTXBR -SNaN TR" 0000DEAD 00000000 00000000 00000000 + + +# Extended BFP test results - Test Data Class +*Compare +r 3200.10 +*Want "TCXB CC +0" 00000001 00000000 00000000 00000000 +r 3210.10 +*Want "TCXB CC -0" 00000000 01000000 00000000 00000000 +r 3220.10 +*Want "TCXB CC +1" 02020000 00010000 00000000 00000000 +r 3230.10 +*Want "TCXB CC -1" 01010000 00000100 00000000 00000000 +r 3240.10 +*Want "TCXB CC +tiny" 02020000 00000001 00000000 00000000 +r 3250.10 +*Want "TCXB CC -tiny" 01010000 00000000 01000000 00000000 +r 3260.10 +*Want "TCXB CC +inf" 02020000 00000000 00010000 00000000 +r 3270.10 +*Want "TCXB CC -inf" 01010000 00000000 00000100 00000000 +r 3280.10 +*Want "TCXB CC +QNaN" 03030000 00000000 00000001 00000000 +r 3290.10 +*Want "TCXB CC -QNaN" 03030000 00000000 00000000 01000000 +r 32A0.10 +*Want "TCXB CC +SNaN" 03008000 00000000 00000000 00010000 +r 32B0.10 +*Want "TCXB CC -SNaN" 03008000 00000000 00000000 00000100 + + +*Done diff --git a/tests/bfp-013-comps.asm b/tests/bfp-013-comps.asm new file mode 100644 index 000000000..bd1f4c0ed --- /dev/null +++ b/tests/bfp-013-comps.asm @@ -0,0 +1,604 @@ + TITLE 'bfp-013-comps.asm: Test IEEE Compare, Compare And Signal' +*********************************************************************** +* +*Testcase IEEE Compare and Compare And Signal. +* Exhaustively test results from the Compare and Compare And Signal +* instructions. The Condition Code and FPC flags are saved for each +* test value pair. If an IEEE trap occurs, the DXC code is saved +* instead of the Condition Code. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* bfp-013-comps.asm +* +* This assembly-language source file is part of the +* Hercules Decimal Floating Point Validation Package +* by Stephen R. Orso +* +* Copyright 2016 by Stephen R Orso. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* +* 3. The name of the author may not be used to endorse or promote +* products derived from this software without specific prior written +* permission. +* +* DISCLAMER: THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* HOLDER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* Each possible comparison class is tested, for a total of 64 test +* value pairs for each of the five instruction precisions and formats. +* Each instruction precision and format is tested twice, once with +* exceptions non-trappable and once with exceptions trappable. +* +* One list of input values is provided. Each value is tested against +* every other value in the same list. +* +* Each result is two bytes, one for the CC and one for FPC flags. If +* a trap occurs, the DXC code replaces the CC. +* +* Tests 5 COMPARE, 5 COMPARE AND SIGNAL +* COMPARE (BFP short, RRE) CEBR +* COMPARE (BFP short, RXE) CEB +* COMPARE (BFP long, RRE) CDBR +* COMPARE (BFP long, RXE) CDB +* COMPARE (BFP extended, RRE) CXBR +* COMPARE AND SIGNAL (BFP short, RRE) KEBR +* COMPARE AND SIGNAL (BFP short, RXE) KEB +* COMPARE AND SIGNAL (BFP long, RRE) KDBR +* COMPARE AND SIGNAL (BFP long, RXE) KDB +* COMPARE AND SIGNAL (BFP extended, RRE) KXBR +* +* Also tests the following floating point support instructions +* EXTRACT FPC +* LOAD (Short) +* LOAD (Long) +* LOAD ZERO (Long) +* STORE (Short) +* STORE (Long) +* SET FPC +* +*********************************************************************** + SPACE 2 + MACRO + PADCSECT &ENDLABL +.* +.* Macro to pad the CSECT to include result data areas if this test +.* program is not being assembled using asma. asma generates a core +.* image that is loaded by the loadcore command, and because the +.* core image is a binary stored in Github, it makes sense to make +.* this small effort to keep the core image small. +.* + AIF (D'&ENDLABL).GOODPAD + MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + MNOTE *,'No CSECT padding performed' + MEXIT +.* +.GOODPAD ANOP Label valid. See if we're on asma + AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + ORG &ENDLABL-1 Not ASMA. Pad CSECT + MEXIT +.* +.NOPAD ANOP + MNOTE *,'asma detected; no CSECT padding performed' + MEND +* +* Note: for compatibility with the z/CMS test rig, do not change +* or use R11, R14, or R15. Everything else is fair game. +* +BFPCOMPS START 0 +STRTLABL EQU * +R0 EQU 0 Work register for cc extraction +R1 EQU 1 Current Test Data Class mask +R2 EQU 2 Holds count of test input values +R3 EQU 3 Points to next test input value(s) +R4 EQU 4 Available +R5 EQU 5 Available +R6 EQU 6 Available +R7 EQU 7 Ptr to next Compare result +R8 EQU 8 Ptr to next Compare and Signal reslt +R9 EQU 9 Available +R10 EQU 10 Pointer to test address list +R11 EQU 11 **Reserved for z/CMS test rig +R12 EQU 12 Test value top of loop +R13 EQU 13 Mainline return address +R14 EQU 14 **Return address for z/CMS test rig +R15 EQU 15 **Base register on z/CMS or Hyperion +* +* Floating Point Register equates to keep the cross reference clean +* +FPR0 EQU 0 +FPR1 EQU 1 +FPR2 EQU 2 +FPR3 EQU 3 +FPR4 EQU 4 +FPR5 EQU 5 +FPR6 EQU 6 +FPR7 EQU 7 +FPR8 EQU 8 +FPR9 EQU 9 +FPR10 EQU 10 +FPR11 EQU 11 +FPR12 EQU 12 +FPR13 EQU 13 +FPR14 EQU 14 +FPR15 EQU 15 +* + USING *,R15 +* +* Above works on real iron (R15=0 after sysclear) +* and in z/CMS (R15 points to start of load module) +* + SPACE 2 +*********************************************************************** +* +* Low core definitions, Restart PSW, and Program Check Routine. +* +*********************************************************************** + SPACE 2 + ORG STRTLABL+X'8E' Program check interrution code +PCINTCD DS H +* +PCOLDPSW EQU STRTLABL+X'150' z/Arch Program check old PSW +* + ORG STRTLABL+X'1A0' z/Arch Restart PSW + DC X'0000000180000000',AD(START) +* + ORG STRTLABL+X'1D0' z/Arch Program check old PSW + DC X'0000000000000000',AD(PROGCHK) +* +* Program check routine. If Data Exception, continue execution at +* the instruction following the program check. Otherwise, hard wait. +* No need to collect data. All interesting DXC stuff is captured +* in the FPCR. +* + ORG STRTLABL+X'200' +PROGCHK DS 0H Program check occured... + CLI PCINTCD+1,X'07' Data Exception? + JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) + LPSWE PCOLDPSW ..yes, resume program execution +PCNOTDTA DS 0H + LTR R14,R14 Return address provided? + BNZR R14 Yes, return to z/CMS test rig. + LPSWE HARDWAIT Not data exception, enter disabled wait + EJECT +*********************************************************************** +* +* Main program. Enable Advanced Floating Point, process test cases. +* +*********************************************************************** + SPACE 2 +START DS 0H + STCTL R0,R0,CTLR0 Store CR0 to enable AFP + OI CTLR0+1,X'04' Turn on AFP bit + LCTL R0,R0,CTLR0 Reload updated CR0 +* + LA R10,SHORTC Point to short BFP parameters + BAS R13,SBFPCOMP Perform short BFP Compare +* + LA R10,LONGC Point to long BFP parameters + BAS R13,LBFPCOMP Perform long BFP Compare +* + LA R10,XTNDC Point to extended BFP parameters + BAS R13,XBFPCOMP Perform extended BFP Compare +* + LTR R14,R14 Return address provided? + BNZR R14 ..Yes, return to z/CMS test rig. + LPSWE WAITPSW All done +* + DS 0D Ensure correct alignment for psw +WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end +* +CTLR0 DS F +FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags +* +* Input values parameter list, four fullwords for each test data set +* 1) Count, +* 2) Address of inputs, +* 3) Address to place results, and +* 4) Address to place DXC/Flags/cc values. +* + ORG STRTLABL+X'300' Enable run-time replacement +SHORTC DS 0F Inputs for short BFP Compare + DC A(SBFPCT) + DC A(SBFPIN) + DC A(SBFPCCC) + DC A(SBFPCSCC) +* +LONGC DS 0F Inputs for long BFP Compare + DC A(LBFPCT) + DC A(LBFPIN) + DC A(LBFPCCC) + DC A(LBFPCSCC) +* +XTNDC DS 0F Inputs for extended BFP Compare + DC A(XBFPCT) + DC A(XBFPIN) + DC A(XBFPCCC) + DC A(XBFPCSCC) + EJECT +*********************************************************************** +* +* Compare short BFP inputs to each possible class of short BFP. Eight +* pairs of results are generated for each input: one with all +* exceptions non-trappable, and the second with all exceptions +* trappable. The CC and FPC flags are stored for each result that +* does not cause a trap. The DXC code and FPC flags are stored for +* each result that traps. +* +*********************************************************************** + SPACE 2 +SBFPCOMP DS 0H Compare short BFP inputs + LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LE FPR8,0(,R3) Get short BFP left-hand test value + LM R4,R5,0(R10) Get count and start of right-hand side + XR R9,R9 Reference zero value for Set Program Mask + BASR R6,0 Set top of inner loop +* +* top of loop to test left-hand value against each input +* + LE FPR1,0(,R5) Get right-hand side of compare +* + LFPC FPCREGNT Set exceptions non-trappable + SPM R9 Clear condition code + CEBR FPR8,FPR1 Compare And Signal floating point nrs RRE + STFPC 0(R7) Store FPC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,3(,R7) Save condition code in results table +* + LFPC FPCREGTR Set exceptions trappable + SPM R9 Clear condition code + CEBR FPR8,FPR1 Compare And Signal floating point nrs RRE + STFPC 4(R7) Store FPC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,7(,R7) Save condition code in results table +* + LFPC FPCREGNT Set exceptions non-trappable + SPM R9 Clear condition code + CEB FPR8,0(,R5) Compare And Signal floating point nrs RXE + STFPC 8(R7) Store FPC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,11(,R7) Save condition code in results table +* + LFPC FPCREGTR Set exceptions trappable + SPM R9 Clear condition code + CEB FPR8,0(,R5) Compare And Signal floating point nrs RXE + STFPC 12(R7) Store FPC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,15(,R7) Save condition code in results table +* + LFPC FPCREGNT Set exceptions non-trappable + SPM R9 Clear condition code + KEBR FPR8,FPR1 Compare And Signal floating point nrs RRE + STFPC 0(R8) Store FPC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,3(,R8) Save condition code in results table +* + LFPC FPCREGTR Set exceptions trappable + SPM R9 Clear condition code + KEBR FPR8,FPR1 Compare And Signal floating point nrs RRE + STFPC 4(R8) Store FPC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,7(,R8) Save condition code in results table +* + LFPC FPCREGNT Set exceptions non-trappable + SPM R9 Clear condition code + KEB FPR8,0(,R5) Compare And Signal floating point nrs RXE + STFPC 8(R8) Store FPC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,11(,R8) Save condition code in results table +* + LFPC FPCREGTR Set exceptions trappable + SPM R9 Clear condition code + KEB FPR8,0(,R5) Compare And Signal floating point nrs RXE + STFPC 12(R8) Store FPC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,15(,R8) Save condition code in results table +* + LA R5,4(,R5) Point to next right-hand value + LA R7,16(,R7) Point to next CC/DXC/FPR CEB result area + LA R8,16(,R8) Point to next CC/DXC/FPR KEB result area + BCTR R4,R6 Loop through right-hand values +* + LA R3,4(,R3) Point to next left-hand value + BCTR R2,R12 Loop through left-hand values +* + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Compare long BFP inputs to each possible class of long BFP. Eight +* pairs of results are generated for each input: one with all +* exceptions non-trappable, and the second with all exceptions +* trappable. The CC and FPC flags are stored for each result that +* does not cause a trap. The DXC code and FPC flags are stored for +* each result that traps. +* +*********************************************************************** + SPACE 2 +LBFPCOMP DS 0H Compare long BFP inputs + LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LD FPR8,0(,R3) Get long BFP left-hand test value + LM R4,R5,0(R10) Get count and start of right-hand side + XR R9,R9 Reference zero value for Set Program Mask + BASR R6,0 Set top of inner loop +* +* top of loop to test left-hand value against each input +* + LD FPR1,0(,R5) Get right-hand side of compare +* + LFPC FPCREGNT Set exceptions non-trappable + SPM R9 Clear condition code + CDBR FPR8,FPR1 Compare And Signal floating point nrs RRE + STFPC 0(R7) Store FPC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,3(,R7) Save condition code in results table +* + LFPC FPCREGTR Set exceptions trappable + SPM R9 Clear condition code + CDBR FPR8,FPR1 Compare And Signal floating point nrs RRE + STFPC 4(R7) Store FPC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,7(,R7) Save condition code in results table +* + LFPC FPCREGNT Set exceptions non-trappable + SPM R9 Clear condition code + CDB FPR8,0(,R5) Compare And Signal floating point nrs RXE + STFPC 8(R7) Store FPC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,11(,R7) Save condition code in results table +* + LFPC FPCREGTR Set exceptions trappable + SPM R9 Clear condition code + CDB FPR8,0(,R5) Compare And Signal floating point nrs RXE + STFPC 12(R7) Store FPC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,15(,R7) Save condition code in results table +* + LFPC FPCREGNT Set exceptions non-trappable + SPM R9 Clear condition code + KDBR FPR8,FPR1 Compare And Signal floating point nrs RRE + STFPC 0(R8) Store FPC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,3(,R8) Save condition code in results table +* + LFPC FPCREGTR Set exceptions trappable + SPM R9 Clear condition code + KDBR FPR8,FPR1 Compare And Signal floating point nrs RRE + STFPC 4(R8) Store FPC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,7(,R8) Save condition code in results table +* + LFPC FPCREGNT Set exceptions non-trappable + SPM R9 Clear condition code + KDB FPR8,0(,R5) Compare And Signal floating point nrs RXE + STFPC 8(R8) Store FPC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,11(,R8) Save condition code in results table +* + LFPC FPCREGTR Set exceptions trappable + SPM R9 Clear condition code + KDB FPR8,0(,R5) Compare And Signal floating point nrs RXE + STFPC 12(R8) Store FPC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,15(,R8) Save condition code in results table +* + LA R5,8(,R5) Point to next right-hand value + LA R7,16(,R7) Point to next CC/DXC/FPR CDB result area + LA R8,16(,R8) Point to next CC/DXC/FPR KDB result area + BCTR R4,R6 Loop through right-hand values +* + LA R3,8(,R3) Point to next left-hand value + BCTR R2,R12 Loop through left-hand values +* + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Compare long BFP inputs to each possible class of long BFP. Eight +* pairs of results are generated for each input: one with all +* exceptions non-trappable, and the second with all exceptions +* trappable. The CC and FPC flags are stored for each result that +* does not cause a trap. The DXC code and FPC flags are stored for +* each result that traps. +* +*********************************************************************** + SPACE 2 +XBFPCOMP DS 0H Compare long BFP inputs + LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LD FPR8,0(,R3) Get long BFP left-hand test value part 1 + LD FPR10,8(,R3) Get long BFP left-hand test value part 2 + LM R4,R5,0(R10) Get count and start of right-hand side + XR R9,R9 Reference zero value for Set Program Mask + BASR R6,0 Set top of inner loop +* +* top of loop to test left-hand value against each input +* + LD FPR1,0(,R5) Get right-hand side of compare part 1 + LD FPR3,8(,R5) Get right-hand side of compare part 2 +* + LFPC FPCREGNT Set exceptions non-trappable + SPM R9 Clear condition code + CXBR FPR8,FPR1 Compare And Signal floating point nrs RRE + STFPC 0(R7) Store FPC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,3(,R7) Save condition code in results table +* + LFPC FPCREGTR Set exceptions trappable + SPM R9 Clear condition code + CXBR FPR8,FPR1 Compare And Signal floating point nrs RRE + STFPC 4(R7) Store FPC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,7(,R7) Save condition code in results table +* + LFPC FPCREGNT Set exceptions non-trappable + SPM R9 Clear condition code + KXBR FPR8,FPR1 Compare And Signal floating point nrs RRE + STFPC 0(R8) Store FPC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,3(,R8) Save condition code in results table +* + LFPC FPCREGTR Set exceptions trappable + SPM R9 Clear condition code + KXBR FPR8,FPR1 Compare And Signal floating point nrs RRE + STFPC 4(R8) Store FPC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,7(,R8) Save condition code in results table +* + LA R5,16(,R5) Point to next right-hand value + LA R7,16(,R7) Point to next CC/DXC/FPR CDB result area + LA R8,16(,R8) Point to next CC/DXC/FPR KDB result area + BCTR R4,R6 Loop through right-hand values +* + LA R3,16(,R3) Point to next left-hand value + BCTR R2,R12 Loop through left-hand values +* + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Input test values. Each input is tested against every input in the +* list, which means the eight values result in 64 tests. +* +*********************************************************************** + SPACE 2 +* +* Short BFP Input values +* +SBFPIN DS 0F Ensure fullword alignment for input table + DC X'FF800000' -infinity + DC X'BF800000' -1 + DC X'80000000' -0 + DC X'00000000' +0 + DC X'3F800000' +1 + DC X'7F800000' +infinity + DC X'FFC00000' -QNaN + DC X'7F810000' +SNaN +SBFPCT EQU (*-SBFPIN)/4 Count of input values +* +* Long BFP Input values +* +LBFPIN DS 0D Ensure doubleword alignment for inputs + DC X'FFF0000000000000' -infinity + DC X'BFF0000000000000' -1 + DC X'8000000000000000' -0 + DC X'0000000000000000' +0 + DC X'3FF0000000000000' +1 + DC X'7FF0000000000000' +infinity + DC X'7FF8000000000000' -QNaN + DC X'7FF0100000000000' +SNaN +LBFPCT EQU (*-LBFPIN)/8 Count of input values +* +* Long BFP Input values +* +XBFPIN DS 0D Ensure doubleword alignment for inputs + DC X'FFFF0000000000000000000000000000' -infinity + DC X'BFFF0000000000000000000000000000' -1 + DC X'80000000000000000000000000000000' -0 + DC X'00000000000000000000000000000000' +0 + DC X'3FFF0000000000000000000000000000' +1 + DC X'7FFF0000000000000000000000000000' +infinity + DC X'FFFF8000000000000000000000000000' -QNaN + DC X'7FFF0100000000000000000000000000' +SNaN +XBFPCT EQU (*-XBFPIN)/16 Count of input values +* +* Locations for test results +* +* For each test result, four bytes are generated as follows +* 1 - non-trap CC +* 2 - non-trap FPC flags +* 3 - trappable CC +* 4 - trappable FPC flags +* +* Only for Compare involving SNaN and Compare And Signal involving any +* NaN will the trappable and non-trap results be different. +* +* For short and long instruction precisions, the RRE format is tested +* first, followed by the RXE format. Extended precision only exists in +* RRE format. +* +SBFPCCC EQU STRTLABL+X'1000' Integer short Compare results +* ..room for 64 tests, all used +* +SBFPCSCC EQU STRTLABL+X'1400' Integer short Compare & Sig. results +* ..room for 64 tests, all used +* +LBFPCCC EQU STRTLABL+X'2000' Integer long Compare results +* ..room for 64 tests, all used +* +LBFPCSCC EQU STRTLABL+X'2400' Integer lon Compare & Sig. results +* ..room for 64 tests, all used +* +XBFPCCC EQU STRTLABL+X'3000' Integer extended Compare results +* ..room for 64 tests, all used +* +XBFPCSCC EQU STRTLABL+X'3400' Integer ext'd Compare & Sig. results +* ..room for 64 tests, all used +* +* +ENDLABL EQU STRTLABL+X'3400' + PADCSECT ENDLABL +* + END \ No newline at end of file diff --git a/tests/bfp-013-comps.core b/tests/bfp-013-comps.core new file mode 100644 index 000000000..d8f22ab3b Binary files /dev/null and b/tests/bfp-013-comps.core differ diff --git a/tests/bfp-013-comps.list b/tests/bfp-013-comps.list new file mode 100644 index 000000000..af8193dd6 --- /dev/null +++ b/tests/bfp-013-comps.list @@ -0,0 +1,725 @@ +ASMA Ver. 0.2.0 bfp-013-comps.asm: Test IEEE Compare, Compare And Signal 19 Sep 2016 07:27:21 Page 1 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 2 *********************************************************************** + 3 * + 4 *Testcase IEEE Compare and Compare And Signal. + 5 * Exhaustively test results from the Compare and Compare And Signal + 6 * instructions. The Condition Code and FPC flags are saved for each + 7 * test value pair. If an IEEE trap occurs, the DXC code is saved + 8 * instead of the Condition Code. + 9 * + 10 *********************************************************************** + + + 12 *********************************************************************** + 13 * + 14 * Each possible comparison class is tested, for a total of 64 test + 15 * value pairs for each of the five instruction precisions and formats. + 16 * Each instruction precision and format is tested twice, once with + 17 * exceptions non-trappable and once with exceptions trappable. + 18 * + 19 * One list of input values is provided. Each value is tested against + 20 * every other value in the same list. + 21 * + 22 * Each result is two bytes, one for the CC and one for FPC flags. If + 23 * a trap occurs, the DXC code replaces the CC. + 24 * + 25 * Tests 5 COMPARE, 5 COMPARE AND SIGNAL + 26 * COMPARE (BFP short, RRE) CEBR + 27 * COMPARE (BFP short, RXE) CEB + 28 * COMPARE (BFP long, RRE) CDBR + 29 * COMPARE (BFP long, RXE) CDB + 30 * COMPARE (BFP extended, RRE) CXBR + 31 * COMPARE AND SIGNAL (BFP short, RRE) KEBR + 32 * COMPARE AND SIGNAL (BFP short, RXE) KEB + 33 * COMPARE AND SIGNAL (BFP long, RRE) KDBR + 34 * COMPARE AND SIGNAL (BFP long, RXE) KDB + 35 * COMPARE AND SIGNAL (BFP extended, RRE) KXBR + 36 * + 37 * Also tests the following floating point support instructions + 38 * EXTRACT FPC + 39 * LOAD (Short) + 40 * LOAD (Long) + 41 * LOAD ZERO (Long) + 42 * STORE (Short) + 43 * STORE (Long) + 44 * SET FPC + 45 * + 46 *********************************************************************** + + + 48 MACRO + 49 PADCSECT &ENDLABL + 50 .* + 51 .* Macro to pad the CSECT to include result data areas if this test + ASMA Ver. 0.2.0 bfp-013-comps.asm: Test IEEE Compare, Compare And Signal 19 Sep 2016 07:27:21 Page 2 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 52 .* program is not being assembled using asma. asma generates a core + 53 .* image that is loaded by the loadcore command, and because the + 54 .* core image is a binary stored in Github, it makes sense to make + 55 .* this small effort to keep the core image small. + 56 .* + 57 AIF (D'&ENDLABL).GOODPAD + 58 MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + 59 MNOTE *,'No CSECT padding performed' + 60 MEXIT + 61 .* + 62 .GOODPAD ANOP Label valid. See if we're on asma + 63 AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + 64 ORG &ENDLABL-1 Not ASMA. Pad CSECT + 65 MEXIT + 66 .* + 67 .NOPAD ANOP + 68 MNOTE *,'asma detected; no CSECT padding performed' + 69 MEND + 70 * + 71 * Note: for compatibility with the z/CMS test rig, do not change + 72 * or use R11, R14, or R15. Everything else is fair game. + 73 * + 0000000000000000 00000000000006CF 74 BFPCOMPS START 0 + 0000000000000000 0000000000000001 75 STRTLABL EQU * + 0000000000000000 0000000000000001 76 R0 EQU 0 Work register for cc extraction + 0000000000000001 0000000000000001 77 R1 EQU 1 Current Test Data Class mask + 0000000000000002 0000000000000001 78 R2 EQU 2 Holds count of test input values + 0000000000000003 0000000000000001 79 R3 EQU 3 Points to next test input value(s) + 0000000000000004 0000000000000001 80 R4 EQU 4 Available + 0000000000000005 0000000000000001 81 R5 EQU 5 Available + 0000000000000006 0000000000000001 82 R6 EQU 6 Available + 0000000000000007 0000000000000001 83 R7 EQU 7 Ptr to next Compare result + 0000000000000008 0000000000000001 84 R8 EQU 8 Ptr to next Compare and Signal reslt + 0000000000000009 0000000000000001 85 R9 EQU 9 Available + 000000000000000A 0000000000000001 86 R10 EQU 10 Pointer to test address list + 000000000000000B 0000000000000001 87 R11 EQU 11 **Reserved for z/CMS test rig + 000000000000000C 0000000000000001 88 R12 EQU 12 Test value top of loop + 000000000000000D 0000000000000001 89 R13 EQU 13 Mainline return address + 000000000000000E 0000000000000001 90 R14 EQU 14 **Return address for z/CMS test rig + 000000000000000F 0000000000000001 91 R15 EQU 15 **Base register on z/CMS or Hyperion + 92 * + 93 * Floating Point Register equates to keep the cross reference clean + 94 * + 0000000000000000 0000000000000001 95 FPR0 EQU 0 + 0000000000000001 0000000000000001 96 FPR1 EQU 1 + 0000000000000002 0000000000000001 97 FPR2 EQU 2 + 0000000000000003 0000000000000001 98 FPR3 EQU 3 + 0000000000000004 0000000000000001 99 FPR4 EQU 4 + 0000000000000005 0000000000000001 100 FPR5 EQU 5 + 0000000000000006 0000000000000001 101 FPR6 EQU 6 + 0000000000000007 0000000000000001 102 FPR7 EQU 7 + 0000000000000008 0000000000000001 103 FPR8 EQU 8 + ASMA Ver. 0.2.0 bfp-013-comps.asm: Test IEEE Compare, Compare And Signal 19 Sep 2016 07:27:21 Page 3 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 0000000000000009 0000000000000001 104 FPR9 EQU 9 + 000000000000000A 0000000000000001 105 FPR10 EQU 10 + 000000000000000B 0000000000000001 106 FPR11 EQU 11 + 000000000000000C 0000000000000001 107 FPR12 EQU 12 + 000000000000000D 0000000000000001 108 FPR13 EQU 13 + 000000000000000E 0000000000000001 109 FPR14 EQU 14 + 000000000000000F 0000000000000001 110 FPR15 EQU 15 + 111 * +0000000000000000 0000000000000000 112 USING *,R15 + 113 * + 114 * Above works on real iron (R15=0 after sysclear) + 115 * and in z/CMS (R15 points to start of load module) + 116 * + + + 118 *********************************************************************** + 119 * + 120 * Low core definitions, Restart PSW, and Program Check Routine. + 121 * + 122 *********************************************************************** + + +0000000000000000 0000000000000000 000000000000008E 124 ORG STRTLABL+X'8E' Program check interrution code +000000000000008E 0000 125 PCINTCD DS H + 126 * + 0000000000000150 0000000000000001 127 PCOLDPSW EQU STRTLABL+X'150' z/Arch Program check old PSW + 128 * +0000000000000090 0000000000000090 00000000000001A0 129 ORG STRTLABL+X'1A0' z/Arch Restart PSW +00000000000001A0 00000001 80000000 130 DC X'0000000180000000',AD(START) + 131 * +00000000000001B0 00000000000001B0 00000000000001D0 132 ORG STRTLABL+X'1D0' z/Arch Program check old PSW +00000000000001D0 00000000 00000000 133 DC X'0000000000000000',AD(PROGCHK) + 134 * + 135 * Program check routine. If Data Exception, continue execution at + 136 * the instruction following the program check. Otherwise, hard wait. + 137 * No need to collect data. All interesting DXC stuff is captured + 138 * in the FPCR. + 139 * +00000000000001E0 00000000000001E0 0000000000000200 140 ORG STRTLABL+X'200' +0000000000000200 141 PROGCHK DS 0H Program check occured... +0000000000000200 9507 F08F 000000000000008F 142 CLI PCINTCD+1,X'07' Data Exception? +0000000000000204 A774 0004 000000000000020C 143 JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) +0000000000000208 B2B2 F150 0000000000000150 144 LPSWE PCOLDPSW ..yes, resume program execution +000000000000020C 145 PCNOTDTA DS 0H +000000000000020C 12EE 146 LTR R14,R14 Return address provided? +000000000000020E 077E 147 BNZR R14 Yes, return to z/CMS test rig. +0000000000000210 B2B2 F250 0000000000000250 148 LPSWE HARDWAIT Not data exception, enter disabled wait + ASMA Ver. 0.2.0 bfp-013-comps.asm: Test IEEE Compare, Compare And Signal 19 Sep 2016 07:27:21 Page 4 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 150 *********************************************************************** + 151 * + 152 * Main program. Enable Advanced Floating Point, process test cases. + 153 * + 154 *********************************************************************** + + +0000000000000214 156 START DS 0H +0000000000000214 B600 F260 0000000000000260 157 STCTL R0,R0,CTLR0 Store CR0 to enable AFP +0000000000000218 9604 F261 0000000000000261 158 OI CTLR0+1,X'04' Turn on AFP bit +000000000000021C B700 F260 0000000000000260 159 LCTL R0,R0,CTLR0 Reload updated CR0 + 160 * +0000000000000220 41A0 F300 0000000000000300 161 LA R10,SHORTC Point to short BFP parameters +0000000000000224 4DD0 F330 0000000000000330 162 BAS R13,SBFPCOMP Perform short BFP Compare + 163 * +0000000000000228 41A0 F310 0000000000000310 164 LA R10,LONGC Point to long BFP parameters +000000000000022C 4DD0 F43C 000000000000043C 165 BAS R13,LBFPCOMP Perform long BFP Compare + 166 * +0000000000000230 41A0 F320 0000000000000320 167 LA R10,XTNDC Point to extended BFP parameters +0000000000000234 4DD0 F548 0000000000000548 168 BAS R13,XBFPCOMP Perform extended BFP Compare + 169 * +0000000000000238 12EE 170 LTR R14,R14 Any value in R14? +000000000000023A 077E 171 BNZR R14 ..yes, running on z/CMS, take graceful exit +000000000000023C B2B2 F240 0000000000000240 172 LPSWE WAITPSW ..no, on bare iron, load disabled wait PSW + 173 * +0000000000000240 174 DS 0D Ensure correct alignment for psw +0000000000000240 00020000 00000000 175 WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +0000000000000250 00020000 00000000 176 HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end + 177 * +0000000000000260 00000000 178 CTLR0 DS F +0000000000000264 00000000 179 FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +0000000000000268 F8000000 180 FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags + 181 * + 182 * Input values parameter list, four fullwords for each test data set + 183 * 1) Count, + 184 * 2) Address of inputs, + 185 * 3) Address to place results, and + 186 * 4) Address to place DXC/Flags/cc values. + 187 * +000000000000026C 000000000000026C 0000000000000300 188 ORG STRTLABL+X'300' Enable run-time replacement +0000000000000300 189 SHORTC DS 0F Inputs for short BFP Compare +0000000000000300 00000008 190 DC A(SBFPCT) +0000000000000304 000005EC 191 DC A(SBFPIN) +0000000000000308 00001000 192 DC A(SBFPCCC) +000000000000030C 00001400 193 DC A(SBFPCSCC) + 194 * +0000000000000310 195 LONGC DS 0F Inputs for long BFP Compare +0000000000000310 00000008 196 DC A(LBFPCT) +0000000000000314 00000610 197 DC A(LBFPIN) +0000000000000318 00002000 198 DC A(LBFPCCC) +000000000000031C 00002400 199 DC A(LBFPCSCC) + 200 * + ASMA Ver. 0.2.0 bfp-013-comps.asm: Test IEEE Compare, Compare And Signal 19 Sep 2016 07:27:21 Page 5 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000320 201 XTNDC DS 0F Inputs for extended BFP Compare +0000000000000320 00000008 202 DC A(XBFPCT) +0000000000000324 00000650 203 DC A(XBFPIN) +0000000000000328 00003000 204 DC A(XBFPCCC) +000000000000032C 00003400 205 DC A(XBFPCSCC) + ASMA Ver. 0.2.0 bfp-013-comps.asm: Test IEEE Compare, Compare And Signal 19 Sep 2016 07:27:21 Page 6 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 207 *********************************************************************** + 208 * + 209 * Compare short BFP inputs to each possible class of short BFP. Eight + 210 * pairs of results are generated for each input: one with all + 211 * exceptions non-trappable, and the second with all exceptions + 212 * trappable. The CC and FPC flags are stored for each result that + 213 * does not cause a trap. The DXC code and FPC flags are stored for + 214 * each result that traps. + 215 * + 216 *********************************************************************** + + +0000000000000330 218 SBFPCOMP DS 0H Compare short BFP inputs +0000000000000330 9823 A000 0000000000000000 219 LM R2,R3,0(R10) Get count and address of test input values +0000000000000334 9878 A008 0000000000000008 220 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000338 1222 221 LTR R2,R2 Any test cases? +000000000000033A 078D 222 BZR R13 ..No, return to caller +000000000000033C 0DC0 223 BASR R12,0 Set top of loop + 224 * +000000000000033E 7880 3000 0000000000000000 225 LE FPR8,0(,R3) Get short BFP left-hand test value +0000000000000342 9845 A000 0000000000000000 226 LM R4,R5,0(R10) Get count and start of right-hand side +0000000000000346 1799 227 XR R9,R9 Reference zero value for Set Program Mask +0000000000000348 0D60 228 BASR R6,0 Set top of inner loop + 229 * + 230 * top of loop to test left-hand value against each input + 231 * +000000000000034A 7810 5000 0000000000000000 232 LE FPR1,0(,R5) Get right-hand side of compare + 233 * +000000000000034E B29D F264 0000000000000264 234 LFPC FPCREGNT Set exceptions non-trappable +0000000000000352 0490 235 SPM R9 Clear condition code +0000000000000354 B309 0081 236 CEBR FPR8,FPR1 Compare And Signal floating point nrs RRE +0000000000000358 B29C 7000 0000000000000000 237 STFPC 0(R7) Store FPC +000000000000035C B222 0000 238 IPM R0 Get condition code and program mask +0000000000000360 8800 001C 000000000000001C 239 SRL R0,28 Isolate CC in low order byte +0000000000000364 4200 7003 0000000000000003 240 STC R0,3(,R7) Save condition code in results table + 241 * +0000000000000368 B29D F268 0000000000000268 242 LFPC FPCREGTR Set exceptions trappable +000000000000036C 0490 243 SPM R9 Clear condition code +000000000000036E B309 0081 244 CEBR FPR8,FPR1 Compare And Signal floating point nrs RRE +0000000000000372 B29C 7004 0000000000000004 245 STFPC 4(R7) Store FPC +0000000000000376 B222 0000 246 IPM R0 Get condition code and program mask +000000000000037A 8800 001C 000000000000001C 247 SRL R0,28 Isolate CC in low order byte +000000000000037E 4200 7007 0000000000000007 248 STC R0,7(,R7) Save condition code in results table + 249 * +0000000000000382 B29D F264 0000000000000264 250 LFPC FPCREGNT Set exceptions non-trappable +0000000000000386 0490 251 SPM R9 Clear condition code +0000000000000388 ED80 5000 0009 0000000000000000 252 CEB FPR8,0(,R5) Compare And Signal floating point nrs RXE +000000000000038E B29C 7008 0000000000000008 253 STFPC 8(R7) Store FPC +0000000000000392 B222 0000 254 IPM R0 Get condition code and program mask +0000000000000396 8800 001C 000000000000001C 255 SRL R0,28 Isolate CC in low order byte +000000000000039A 4200 700B 000000000000000B 256 STC R0,11(,R7) Save condition code in results table + 257 * + ASMA Ver. 0.2.0 bfp-013-comps.asm: Test IEEE Compare, Compare And Signal 19 Sep 2016 07:27:21 Page 7 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +000000000000039E B29D F268 0000000000000268 258 LFPC FPCREGTR Set exceptions trappable +00000000000003A2 0490 259 SPM R9 Clear condition code +00000000000003A4 ED80 5000 0009 0000000000000000 260 CEB FPR8,0(,R5) Compare And Signal floating point nrs RXE +00000000000003AA B29C 700C 000000000000000C 261 STFPC 12(R7) Store FPC +00000000000003AE B222 0000 262 IPM R0 Get condition code and program mask +00000000000003B2 8800 001C 000000000000001C 263 SRL R0,28 Isolate CC in low order byte +00000000000003B6 4200 700F 000000000000000F 264 STC R0,15(,R7) Save condition code in results table + 265 * +00000000000003BA B29D F264 0000000000000264 266 LFPC FPCREGNT Set exceptions non-trappable +00000000000003BE 0490 267 SPM R9 Clear condition code +00000000000003C0 B308 0081 268 KEBR FPR8,FPR1 Compare And Signal floating point nrs RRE +00000000000003C4 B29C 8000 0000000000000000 269 STFPC 0(R8) Store FPC +00000000000003C8 B222 0000 270 IPM R0 Get condition code and program mask +00000000000003CC 8800 001C 000000000000001C 271 SRL R0,28 Isolate CC in low order byte +00000000000003D0 4200 8003 0000000000000003 272 STC R0,3(,R8) Save condition code in results table + 273 * +00000000000003D4 B29D F268 0000000000000268 274 LFPC FPCREGTR Set exceptions trappable +00000000000003D8 0490 275 SPM R9 Clear condition code +00000000000003DA B308 0081 276 KEBR FPR8,FPR1 Compare And Signal floating point nrs RRE +00000000000003DE B29C 8004 0000000000000004 277 STFPC 4(R8) Store FPC +00000000000003E2 B222 0000 278 IPM R0 Get condition code and program mask +00000000000003E6 8800 001C 000000000000001C 279 SRL R0,28 Isolate CC in low order byte +00000000000003EA 4200 8007 0000000000000007 280 STC R0,7(,R8) Save condition code in results table + 281 * +00000000000003EE B29D F264 0000000000000264 282 LFPC FPCREGNT Set exceptions non-trappable +00000000000003F2 0490 283 SPM R9 Clear condition code +00000000000003F4 ED80 5000 0008 0000000000000000 284 KEB FPR8,0(,R5) Compare And Signal floating point nrs RXE +00000000000003FA B29C 8008 0000000000000008 285 STFPC 8(R8) Store FPC +00000000000003FE B222 0000 286 IPM R0 Get condition code and program mask +0000000000000402 8800 001C 000000000000001C 287 SRL R0,28 Isolate CC in low order byte +0000000000000406 4200 800B 000000000000000B 288 STC R0,11(,R8) Save condition code in results table + 289 * +000000000000040A B29D F268 0000000000000268 290 LFPC FPCREGTR Set exceptions trappable +000000000000040E 0490 291 SPM R9 Clear condition code +0000000000000410 ED80 5000 0008 0000000000000000 292 KEB FPR8,0(,R5) Compare And Signal floating point nrs RXE +0000000000000416 B29C 800C 000000000000000C 293 STFPC 12(R8) Store FPC +000000000000041A B222 0000 294 IPM R0 Get condition code and program mask +000000000000041E 8800 001C 000000000000001C 295 SRL R0,28 Isolate CC in low order byte +0000000000000422 4200 800F 000000000000000F 296 STC R0,15(,R8) Save condition code in results table + 297 * +0000000000000426 4150 5004 0000000000000004 298 LA R5,4(,R5) Point to next right-hand value +000000000000042A 4170 7010 0000000000000010 299 LA R7,16(,R7) Point to next CC/DXC/FPR CEB result area +000000000000042E 4180 8010 0000000000000010 300 LA R8,16(,R8) Point to next CC/DXC/FPR KEB result area +0000000000000432 0646 301 BCTR R4,R6 Loop through right-hand values + 302 * +0000000000000434 4130 3004 0000000000000004 303 LA R3,4(,R3) Point to next left-hand value +0000000000000438 062C 304 BCTR R2,R12 Loop through left-hand values + 305 * +000000000000043A 07FD 306 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-013-comps.asm: Test IEEE Compare, Compare And Signal 19 Sep 2016 07:27:21 Page 8 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 308 *********************************************************************** + 309 * + 310 * Compare long BFP inputs to each possible class of long BFP. Eight + 311 * pairs of results are generated for each input: one with all + 312 * exceptions non-trappable, and the second with all exceptions + 313 * trappable. The CC and FPC flags are stored for each result that + 314 * does not cause a trap. The DXC code and FPC flags are stored for + 315 * each result that traps. + 316 * + 317 *********************************************************************** + + +000000000000043C 319 LBFPCOMP DS 0H Compare long BFP inputs +000000000000043C 9823 A000 0000000000000000 320 LM R2,R3,0(R10) Get count and address of test input values +0000000000000440 9878 A008 0000000000000008 321 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000444 1222 322 LTR R2,R2 Any test cases? +0000000000000446 078D 323 BZR R13 ..No, return to caller +0000000000000448 0DC0 324 BASR R12,0 Set top of loop + 325 * +000000000000044A 6880 3000 0000000000000000 326 LD FPR8,0(,R3) Get long BFP left-hand test value +000000000000044E 9845 A000 0000000000000000 327 LM R4,R5,0(R10) Get count and start of right-hand side +0000000000000452 1799 328 XR R9,R9 Reference zero value for Set Program Mask +0000000000000454 0D60 329 BASR R6,0 Set top of inner loop + 330 * + 331 * top of loop to test left-hand value against each input + 332 * +0000000000000456 6810 5000 0000000000000000 333 LD FPR1,0(,R5) Get right-hand side of compare + 334 * +000000000000045A B29D F264 0000000000000264 335 LFPC FPCREGNT Set exceptions non-trappable +000000000000045E 0490 336 SPM R9 Clear condition code +0000000000000460 B319 0081 337 CDBR FPR8,FPR1 Compare And Signal floating point nrs RRE +0000000000000464 B29C 7000 0000000000000000 338 STFPC 0(R7) Store FPC +0000000000000468 B222 0000 339 IPM R0 Get condition code and program mask +000000000000046C 8800 001C 000000000000001C 340 SRL R0,28 Isolate CC in low order byte +0000000000000470 4200 7003 0000000000000003 341 STC R0,3(,R7) Save condition code in results table + 342 * +0000000000000474 B29D F268 0000000000000268 343 LFPC FPCREGTR Set exceptions trappable +0000000000000478 0490 344 SPM R9 Clear condition code +000000000000047A B319 0081 345 CDBR FPR8,FPR1 Compare And Signal floating point nrs RRE +000000000000047E B29C 7004 0000000000000004 346 STFPC 4(R7) Store FPC +0000000000000482 B222 0000 347 IPM R0 Get condition code and program mask +0000000000000486 8800 001C 000000000000001C 348 SRL R0,28 Isolate CC in low order byte +000000000000048A 4200 7007 0000000000000007 349 STC R0,7(,R7) Save condition code in results table + 350 * +000000000000048E B29D F264 0000000000000264 351 LFPC FPCREGNT Set exceptions non-trappable +0000000000000492 0490 352 SPM R9 Clear condition code +0000000000000494 ED80 5000 0019 0000000000000000 353 CDB FPR8,0(,R5) Compare And Signal floating point nrs RXE +000000000000049A B29C 7008 0000000000000008 354 STFPC 8(R7) Store FPC +000000000000049E B222 0000 355 IPM R0 Get condition code and program mask +00000000000004A2 8800 001C 000000000000001C 356 SRL R0,28 Isolate CC in low order byte +00000000000004A6 4200 700B 000000000000000B 357 STC R0,11(,R7) Save condition code in results table + 358 * + ASMA Ver. 0.2.0 bfp-013-comps.asm: Test IEEE Compare, Compare And Signal 19 Sep 2016 07:27:21 Page 9 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000004AA B29D F268 0000000000000268 359 LFPC FPCREGTR Set exceptions trappable +00000000000004AE 0490 360 SPM R9 Clear condition code +00000000000004B0 ED80 5000 0019 0000000000000000 361 CDB FPR8,0(,R5) Compare And Signal floating point nrs RXE +00000000000004B6 B29C 700C 000000000000000C 362 STFPC 12(R7) Store FPC +00000000000004BA B222 0000 363 IPM R0 Get condition code and program mask +00000000000004BE 8800 001C 000000000000001C 364 SRL R0,28 Isolate CC in low order byte +00000000000004C2 4200 700F 000000000000000F 365 STC R0,15(,R7) Save condition code in results table + 366 * +00000000000004C6 B29D F264 0000000000000264 367 LFPC FPCREGNT Set exceptions non-trappable +00000000000004CA 0490 368 SPM R9 Clear condition code +00000000000004CC B318 0081 369 KDBR FPR8,FPR1 Compare And Signal floating point nrs RRE +00000000000004D0 B29C 8000 0000000000000000 370 STFPC 0(R8) Store FPC +00000000000004D4 B222 0000 371 IPM R0 Get condition code and program mask +00000000000004D8 8800 001C 000000000000001C 372 SRL R0,28 Isolate CC in low order byte +00000000000004DC 4200 8003 0000000000000003 373 STC R0,3(,R8) Save condition code in results table + 374 * +00000000000004E0 B29D F268 0000000000000268 375 LFPC FPCREGTR Set exceptions trappable +00000000000004E4 0490 376 SPM R9 Clear condition code +00000000000004E6 B318 0081 377 KDBR FPR8,FPR1 Compare And Signal floating point nrs RRE +00000000000004EA B29C 8004 0000000000000004 378 STFPC 4(R8) Store FPC +00000000000004EE B222 0000 379 IPM R0 Get condition code and program mask +00000000000004F2 8800 001C 000000000000001C 380 SRL R0,28 Isolate CC in low order byte +00000000000004F6 4200 8007 0000000000000007 381 STC R0,7(,R8) Save condition code in results table + 382 * +00000000000004FA B29D F264 0000000000000264 383 LFPC FPCREGNT Set exceptions non-trappable +00000000000004FE 0490 384 SPM R9 Clear condition code +0000000000000500 ED80 5000 0018 0000000000000000 385 KDB FPR8,0(,R5) Compare And Signal floating point nrs RXE +0000000000000506 B29C 8008 0000000000000008 386 STFPC 8(R8) Store FPC +000000000000050A B222 0000 387 IPM R0 Get condition code and program mask +000000000000050E 8800 001C 000000000000001C 388 SRL R0,28 Isolate CC in low order byte +0000000000000512 4200 800B 000000000000000B 389 STC R0,11(,R8) Save condition code in results table + 390 * +0000000000000516 B29D F268 0000000000000268 391 LFPC FPCREGTR Set exceptions trappable +000000000000051A 0490 392 SPM R9 Clear condition code +000000000000051C ED80 5000 0018 0000000000000000 393 KDB FPR8,0(,R5) Compare And Signal floating point nrs RXE +0000000000000522 B29C 800C 000000000000000C 394 STFPC 12(R8) Store FPC +0000000000000526 B222 0000 395 IPM R0 Get condition code and program mask +000000000000052A 8800 001C 000000000000001C 396 SRL R0,28 Isolate CC in low order byte +000000000000052E 4200 800F 000000000000000F 397 STC R0,15(,R8) Save condition code in results table + 398 * +0000000000000532 4150 5008 0000000000000008 399 LA R5,8(,R5) Point to next right-hand value +0000000000000536 4170 7010 0000000000000010 400 LA R7,16(,R7) Point to next CC/DXC/FPR CDB result area +000000000000053A 4180 8010 0000000000000010 401 LA R8,16(,R8) Point to next CC/DXC/FPR KDB result area +000000000000053E 0646 402 BCTR R4,R6 Loop through right-hand values + 403 * +0000000000000540 4130 3008 0000000000000008 404 LA R3,8(,R3) Point to next left-hand value +0000000000000544 062C 405 BCTR R2,R12 Loop through left-hand values + 406 * +0000000000000546 07FD 407 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-013-comps.asm: Test IEEE Compare, Compare And Signal 19 Sep 2016 07:27:21 Page 10 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 409 *********************************************************************** + 410 * + 411 * Compare long BFP inputs to each possible class of long BFP. Eight + 412 * pairs of results are generated for each input: one with all + 413 * exceptions non-trappable, and the second with all exceptions + 414 * trappable. The CC and FPC flags are stored for each result that + 415 * does not cause a trap. The DXC code and FPC flags are stored for + 416 * each result that traps. + 417 * + 418 *********************************************************************** + + +0000000000000548 420 XBFPCOMP DS 0H Compare long BFP inputs +0000000000000548 9823 A000 0000000000000000 421 LM R2,R3,0(R10) Get count and address of test input values +000000000000054C 9878 A008 0000000000000008 422 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000550 1222 423 LTR R2,R2 Any test cases? +0000000000000552 078D 424 BZR R13 ..No, return to caller +0000000000000554 0DC0 425 BASR R12,0 Set top of loop + 426 * +0000000000000556 6880 3000 0000000000000000 427 LD FPR8,0(,R3) Get long BFP left-hand test value part 1 +000000000000055A 68A0 3008 0000000000000008 428 LD FPR10,8(,R3) Get long BFP left-hand test value part 2 +000000000000055E 9845 A000 0000000000000000 429 LM R4,R5,0(R10) Get count and start of right-hand side +0000000000000562 1799 430 XR R9,R9 Reference zero value for Set Program Mask +0000000000000564 0D60 431 BASR R6,0 Set top of inner loop + 432 * + 433 * top of loop to test left-hand value against each input + 434 * +0000000000000566 6810 5000 0000000000000000 435 LD FPR1,0(,R5) Get right-hand side of compare part 1 +000000000000056A 6830 5008 0000000000000008 436 LD FPR3,8(,R5) Get right-hand side of compare part 2 + 437 * +000000000000056E B29D F264 0000000000000264 438 LFPC FPCREGNT Set exceptions non-trappable +0000000000000572 0490 439 SPM R9 Clear condition code +0000000000000574 B349 0081 440 CXBR FPR8,FPR1 Compare And Signal floating point nrs RRE +0000000000000578 B29C 7000 0000000000000000 441 STFPC 0(R7) Store FPC +000000000000057C B222 0000 442 IPM R0 Get condition code and program mask +0000000000000580 8800 001C 000000000000001C 443 SRL R0,28 Isolate CC in low order byte +0000000000000584 4200 7003 0000000000000003 444 STC R0,3(,R7) Save condition code in results table + 445 * +0000000000000588 B29D F268 0000000000000268 446 LFPC FPCREGTR Set exceptions trappable +000000000000058C 0490 447 SPM R9 Clear condition code +000000000000058E B349 0081 448 CXBR FPR8,FPR1 Compare And Signal floating point nrs RRE +0000000000000592 B29C 7004 0000000000000004 449 STFPC 4(R7) Store FPC +0000000000000596 B222 0000 450 IPM R0 Get condition code and program mask +000000000000059A 8800 001C 000000000000001C 451 SRL R0,28 Isolate CC in low order byte +000000000000059E 4200 7007 0000000000000007 452 STC R0,7(,R7) Save condition code in results table + 453 * +00000000000005A2 B29D F264 0000000000000264 454 LFPC FPCREGNT Set exceptions non-trappable +00000000000005A6 0490 455 SPM R9 Clear condition code +00000000000005A8 B348 0081 456 KXBR FPR8,FPR1 Compare And Signal floating point nrs RRE +00000000000005AC B29C 8000 0000000000000000 457 STFPC 0(R8) Store FPC +00000000000005B0 B222 0000 458 IPM R0 Get condition code and program mask +00000000000005B4 8800 001C 000000000000001C 459 SRL R0,28 Isolate CC in low order byte + ASMA Ver. 0.2.0 bfp-013-comps.asm: Test IEEE Compare, Compare And Signal 19 Sep 2016 07:27:21 Page 11 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000005B8 4200 8003 0000000000000003 460 STC R0,3(,R8) Save condition code in results table + 461 * +00000000000005BC B29D F268 0000000000000268 462 LFPC FPCREGTR Set exceptions trappable +00000000000005C0 0490 463 SPM R9 Clear condition code +00000000000005C2 B348 0081 464 KXBR FPR8,FPR1 Compare And Signal floating point nrs RRE +00000000000005C6 B29C 8004 0000000000000004 465 STFPC 4(R8) Store FPC +00000000000005CA B222 0000 466 IPM R0 Get condition code and program mask +00000000000005CE 8800 001C 000000000000001C 467 SRL R0,28 Isolate CC in low order byte +00000000000005D2 4200 8007 0000000000000007 468 STC R0,7(,R8) Save condition code in results table + 469 * +00000000000005D6 4150 5010 0000000000000010 470 LA R5,16(,R5) Point to next right-hand value +00000000000005DA 4170 7010 0000000000000010 471 LA R7,16(,R7) Point to next CC/DXC/FPR CDB result area +00000000000005DE 4180 8010 0000000000000010 472 LA R8,16(,R8) Point to next CC/DXC/FPR KDB result area +00000000000005E2 0646 473 BCTR R4,R6 Loop through right-hand values + 474 * +00000000000005E4 4130 3010 0000000000000010 475 LA R3,16(,R3) Point to next left-hand value +00000000000005E8 062C 476 BCTR R2,R12 Loop through left-hand values + 477 * +00000000000005EA 07FD 478 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-013-comps.asm: Test IEEE Compare, Compare And Signal 19 Sep 2016 07:27:21 Page 12 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 480 *********************************************************************** + 481 * + 482 * Input test values. Each input is tested against every input in the + 483 * list, which means the eight values result in 64 tests. + 484 * + 485 *********************************************************************** + + + 487 * + 488 * Short BFP Input values + 489 * +00000000000005EC 490 SBFPIN DS 0F Ensure fullword alignment for input table +00000000000005EC FF800000 491 DC X'FF800000' -infinity +00000000000005F0 BF800000 492 DC X'BF800000' -1 +00000000000005F4 80000000 493 DC X'80000000' -0 +00000000000005F8 00000000 494 DC X'00000000' +0 +00000000000005FC 3F800000 495 DC X'3F800000' +1 +0000000000000600 7F800000 496 DC X'7F800000' +infinity +0000000000000604 FFC00000 497 DC X'FFC00000' -QNaN +0000000000000608 7F810000 498 DC X'7F810000' +SNaN + 0000000000000008 0000000000000001 499 SBFPCT EQU (*-SBFPIN)/4 Count of input values + 500 * + 501 * Long BFP Input values + 502 * +0000000000000610 503 LBFPIN DS 0D Ensure doubleword alignment for inputs +0000000000000610 FFF00000 00000000 504 DC X'FFF0000000000000' -infinity +0000000000000618 BFF00000 00000000 505 DC X'BFF0000000000000' -1 +0000000000000620 80000000 00000000 506 DC X'8000000000000000' -0 +0000000000000628 00000000 00000000 507 DC X'0000000000000000' +0 +0000000000000630 3FF00000 00000000 508 DC X'3FF0000000000000' +1 +0000000000000638 7FF00000 00000000 509 DC X'7FF0000000000000' +infinity +0000000000000640 7FF80000 00000000 510 DC X'7FF8000000000000' -QNaN +0000000000000648 7FF01000 00000000 511 DC X'7FF0100000000000' +SNaN + 0000000000000008 0000000000000001 512 LBFPCT EQU (*-LBFPIN)/8 Count of input values + 513 * + 514 * Long BFP Input values + 515 * +0000000000000650 516 XBFPIN DS 0D Ensure doubleword alignment for inputs +0000000000000650 FFFF0000 00000000 517 DC X'FFFF0000000000000000000000000000' -infinity +0000000000000660 BFFF0000 00000000 518 DC X'BFFF0000000000000000000000000000' -1 +0000000000000670 80000000 00000000 519 DC X'80000000000000000000000000000000' -0 +0000000000000680 00000000 00000000 520 DC X'00000000000000000000000000000000' +0 +0000000000000690 3FFF0000 00000000 521 DC X'3FFF0000000000000000000000000000' +1 +00000000000006A0 7FFF0000 00000000 522 DC X'7FFF0000000000000000000000000000' +infinity +00000000000006B0 FFFF8000 00000000 523 DC X'FFFF8000000000000000000000000000' -QNaN +00000000000006C0 7FFF0100 00000000 524 DC X'7FFF0100000000000000000000000000' +SNaN + 0000000000000008 0000000000000001 525 XBFPCT EQU (*-XBFPIN)/16 Count of input values + 526 * + 527 * Locations for test results + 528 * + 529 * For each test result, four bytes are generated as follows + 530 * 1 - non-trap CC + ASMA Ver. 0.2.0 bfp-013-comps.asm: Test IEEE Compare, Compare And Signal 19 Sep 2016 07:27:21 Page 13 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 531 * 2 - non-trap FPC flags + 532 * 3 - trappable CC + 533 * 4 - trappable FPC flags + 534 * + 535 * Only for Compare involving SNaN and Compare And Signal involving any + 536 * NaN will the trappable and non-trap results be different. + 537 * + 538 * For short and long instruction precisions, the RRE format is tested + 539 * first, followed by the RXE format. Extended precision only exists in + 540 * RRE format. + 541 * + 0000000000001000 0000000000000001 542 SBFPCCC EQU STRTLABL+X'1000' Integer short Compare results + 543 * ..room for 64 tests, all used + 544 * + 0000000000001400 0000000000000001 545 SBFPCSCC EQU STRTLABL+X'1400' Integer short Compare & Sig. results + 546 * ..room for 64 tests, all used + 547 * + 0000000000002000 0000000000000001 548 LBFPCCC EQU STRTLABL+X'2000' Integer long Compare results + 549 * ..room for 64 tests, all used + 550 * + 0000000000002400 0000000000000001 551 LBFPCSCC EQU STRTLABL+X'2400' Integer lon Compare & Sig. results + 552 * ..room for 64 tests, all used + 553 * + 0000000000003000 0000000000000001 554 XBFPCCC EQU STRTLABL+X'3000' Integer extended Compare results + 555 * ..room for 64 tests, all used + 556 * + 0000000000003400 0000000000000001 557 XBFPCSCC EQU STRTLABL+X'3400' Integer ext'd Compare & Sig. results + 558 * ..room for 64 tests, all used + 559 * + 560 * + 0000000000003400 0000000000000001 561 ENDLABL EQU STRTLABL+X'3400' + 562 PADCSECT ENDLABL + 563+ MNOTE *,'asma detected; no CSECT padding performed' + 564 * +00000000000006D0 565 END + ASMA Ver. 0.2.0 bfp-013-comps.asm: Test IEEE Compare, Compare And Signal 19 Sep 2016 07:27:21 Page 14 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +BFPCOMPS J 000000 1744 74 +CTLR0 F 000260 4 178 157 158 159 +ENDLABL U 003400 1 561 +FPCREGNT X 000264 4 179 234 250 266 282 335 351 367 383 438 454 +FPCREGTR X 000268 4 180 242 258 274 290 343 359 375 391 446 462 +FPR0 U 000000 1 95 +FPR1 U 000001 1 96 232 236 244 268 276 333 337 345 369 377 435 440 448 456 464 +FPR10 U 00000A 1 105 428 +FPR11 U 00000B 1 106 +FPR12 U 00000C 1 107 +FPR13 U 00000D 1 108 +FPR14 U 00000E 1 109 +FPR15 U 00000F 1 110 +FPR2 U 000002 1 97 +FPR3 U 000003 1 98 436 +FPR4 U 000004 1 99 +FPR5 U 000005 1 100 +FPR6 U 000006 1 101 +FPR7 U 000007 1 102 +FPR8 U 000008 1 103 225 236 244 252 260 268 276 284 292 326 337 345 353 361 369 377 385 + 393 427 440 448 456 464 +FPR9 U 000009 1 104 +HARDWAIT X 000250 8 176 148 +IMAGE 1 000000 1744 0 +LBFPCCC U 002000 1 548 198 +LBFPCOMP H 00043C 2 319 165 +LBFPCSCC U 002400 1 551 199 +LBFPCT U 000008 1 512 196 +LBFPIN D 000610 8 503 512 197 +LONGC F 000310 4 195 164 +PCINTCD H 00008E 2 125 142 +PCNOTDTA H 00020C 2 145 143 +PCOLDPSW U 000150 1 127 144 +PROGCHK H 000200 2 141 133 +R0 U 000000 1 76 157 159 238 239 240 246 247 248 254 255 256 262 263 264 270 271 272 + 278 279 280 286 287 288 294 295 296 339 340 341 347 348 349 355 356 + 357 363 364 365 371 372 373 379 380 381 387 388 389 395 396 397 442 + 443 444 450 451 452 458 459 460 466 467 468 +R1 U 000001 1 77 +R10 U 00000A 1 86 161 164 167 219 220 226 320 321 327 421 422 429 +R11 U 00000B 1 87 +R12 U 00000C 1 88 223 304 324 405 425 476 +R13 U 00000D 1 89 162 165 168 222 306 323 407 424 478 +R14 U 00000E 1 90 146 147 170 171 +R15 U 00000F 1 91 112 +R2 U 000002 1 78 219 221 304 320 322 405 421 423 476 +R3 U 000003 1 79 219 225 303 320 326 404 421 427 428 475 +R4 U 000004 1 80 226 301 327 402 429 473 +R5 U 000005 1 81 226 232 252 260 284 292 298 327 333 353 361 385 393 399 429 435 436 + 470 +R6 U 000006 1 82 228 301 329 402 431 473 +R7 U 000007 1 83 220 237 240 245 248 253 256 261 264 299 321 338 341 346 349 354 357 + ASMA Ver. 0.2.0 bfp-013-comps.asm: Test IEEE Compare, Compare And Signal 19 Sep 2016 07:27:21 Page 15 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + + 362 365 400 422 441 444 449 452 471 +R8 U 000008 1 84 220 269 272 277 280 285 288 293 296 300 321 370 373 378 381 386 389 + 394 397 401 422 457 460 465 468 472 +R9 U 000009 1 85 227 235 243 251 259 267 275 283 291 328 336 344 352 360 368 376 384 + 392 430 439 447 455 463 +SBFPCCC U 001000 1 542 192 +SBFPCOMP H 000330 2 218 162 +SBFPCSCC U 001400 1 545 193 +SBFPCT U 000008 1 499 190 +SBFPIN F 0005EC 4 490 499 191 +SHORTC F 000300 4 189 161 +START H 000214 2 156 130 +STRTLABL U 000000 1 75 124 127 129 132 140 188 542 545 548 551 554 557 561 +WAITPSW X 000240 8 175 172 +XBFPCCC U 003000 1 554 204 +XBFPCOMP H 000548 2 420 168 +XBFPCSCC U 003400 1 557 205 +XBFPCT U 000008 1 525 202 +XBFPIN D 000650 8 516 525 203 +XTNDC F 000320 4 201 167 + ASMA Ver. 0.2.0 bfp-013-comps.asm: Test IEEE Compare, Compare And Signal 19 Sep 2016 07:27:21 Page 16 + + MACRO DEFN REFERENCES + +PADCSECT 49 562 + ASMA Ver. 0.2.0 bfp-013-comps.asm: Test IEEE Compare, Compare And Signal 19 Sep 2016 07:27:21 Page 17 + + DESC SYMBOL SIZE POS ADDR + +Entry: 0 + +Image IMAGE 1744 000-6CF 000-6CF + Region 1744 000-6CF 000-6CF + CSECT BFPCOMPS 1744 000-6CF 000-6CF + ASMA Ver. 0.2.0 bfp-013-comps.asm: Test IEEE Compare, Compare And Signal 19 Sep 2016 07:27:21 Page 18 + + STMT FILE NAME + +1 C:\Users\srorso\Documents\GitHub\hyperion\tests\bfp-013-comps.asm + + +** NO ERRORS FOUND ** + +[563] MNOTE *,asma detected; no CSECT padding performed + \ No newline at end of file diff --git a/tests/bfp-013-comps.tst b/tests/bfp-013-comps.tst new file mode 100644 index 000000000..585d19963 --- /dev/null +++ b/tests/bfp-013-comps.tst @@ -0,0 +1,819 @@ +*Testcase bfp-013-comps.tst: CEBR, CEB, CDBR, CDB, CXBR, KEBR, KEB, KDBR, KDB, KXBR + +#Testcase bfp-013-comps.tst: IEEE Compare and Compare And Signal +#..Includes COMPARE (5), COMPARE AND SIGNAL (5) +#..Test case values exhaustively test comparisons and traps + + +sysclear +archmode esame + +# +# Following suppresses logging of program checks. This test program, as part +# of its normal operation, generates 215 program check messages that have no +# value in the validation process. (The messages, not the program checks.) +# +ostailor quiet + +loadcore "$(testpath)/bfp-013-comps.core" + +runtest 1.0 + +ostailor null # restore messages for subsequent tests + + +# Compare short BFP results - FPCR contents and CC +*Compare +r 1000.10 +*Want "CEBR/CEB -infinity / -infinity" 00000000 F8000000 00000000 F8000000 +r 1010.10 +*Want "CEBR/CEB -infinity / -1" 00000001 F8000001 00000001 F8000001 +r 1020.10 +*Want "CEBR/CEB -infinity / -0" 00000001 F8000001 00000001 F8000001 +r 1030.10 +*Want "CEBR/CEB -infinity / +0" 00000001 F8000001 00000001 F8000001 +r 1040.10 +*Want "CEBR/CEB -infinity / +1" 00000001 F8000001 00000001 F8000001 +r 1050.10 +*Want "CEBR/CEB -infinity / +infinity" 00000001 F8000001 00000001 F8000001 +r 1060.10 +*Want "CEBR/CEB -infinity / -QNaN" 00000003 F8000003 00000003 F8000003 +r 1070.10 +*Want "CEBR/CEB -infinity / +SNaN" 00800003 F8008000 00800003 F8008000 +r 1080.10 +*Want "CEBR/CEB -1 / -infinity" 00000002 F8000002 00000002 F8000002 +r 1090.10 +*Want "CEBR/CEB -1 / -1" 00000000 F8000000 00000000 F8000000 +r 10A0.10 +*Want "CEBR/CEB -1 / -0" 00000001 F8000001 00000001 F8000001 +r 10B0.10 +*Want "CEBR/CEB -1 / +0" 00000001 F8000001 00000001 F8000001 +r 10C0.10 +*Want "CEBR/CEB -1 / +1" 00000001 F8000001 00000001 F8000001 +r 10D0.10 +*Want "CEBR/CEB -1 / +infinity" 00000001 F8000001 00000001 F8000001 +r 10E0.10 +*Want "CEBR/CEB -1 / -QNaN" 00000003 F8000003 00000003 F8000003 +r 10F0.10 +*Want "CEBR/CEB -1 / +SNaN" 00800003 F8008000 00800003 F8008000 +r 1100.10 +*Want "CEBR/CEB -0 / -infinity" 00000002 F8000002 00000002 F8000002 +r 1110.10 +*Want "CEBR/CEB -0 / -1" 00000002 F8000002 00000002 F8000002 +r 1120.10 +*Want "CEBR/CEB -0 / -0" 00000000 F8000000 00000000 F8000000 +r 1130.10 +*Want "CEBR/CEB -0 / +0" 00000000 F8000000 00000000 F8000000 +r 1140.10 +*Want "CEBR/CEB -0 / +1" 00000001 F8000001 00000001 F8000001 +r 1150.10 +*Want "CEBR/CEB -0 / +infinity" 00000001 F8000001 00000001 F8000001 +r 1160.10 +*Want "CEBR/CEB -0 / -QNaN" 00000003 F8000003 00000003 F8000003 +r 1170.10 +*Want "CEBR/CEB -0 / +SNaN" 00800003 F8008000 00800003 F8008000 +r 1180.10 +*Want "CEBR/CEB +0 / -infinity" 00000002 F8000002 00000002 F8000002 +r 1190.10 +*Want "CEBR/CEB +0 / -1" 00000002 F8000002 00000002 F8000002 +r 11A0.10 +*Want "CEBR/CEB +0 / -0" 00000000 F8000000 00000000 F8000000 +r 11B0.10 +*Want "CEBR/CEB +0 / +0" 00000000 F8000000 00000000 F8000000 +r 11C0.10 +*Want "CEBR/CEB +0 / +1" 00000001 F8000001 00000001 F8000001 +r 11D0.10 +*Want "CEBR/CEB +0 / +infinity" 00000001 F8000001 00000001 F8000001 +r 11E0.10 +*Want "CEBR/CEB +0 / -QNaN" 00000003 F8000003 00000003 F8000003 +r 11F0.10 +*Want "CEBR/CEB +0 / +SNaN" 00800003 F8008000 00800003 F8008000 +r 1200.10 +*Want "CEBR/CEB +1 / -infinity" 00000002 F8000002 00000002 F8000002 +r 1210.10 +*Want "CEBR/CEB +1 / -1" 00000002 F8000002 00000002 F8000002 +r 1220.10 +*Want "CEBR/CEB +1 / -0" 00000002 F8000002 00000002 F8000002 +r 1230.10 +*Want "CEBR/CEB +1 / +0" 00000002 F8000002 00000002 F8000002 +r 1240.10 +*Want "CEBR/CEB +1 / +1" 00000000 F8000000 00000000 F8000000 +r 1250.10 +*Want "CEBR/CEB +1 / +infinity" 00000001 F8000001 00000001 F8000001 +r 1260.10 +*Want "CEBR/CEB +1 / -QNaN" 00000003 F8000003 00000003 F8000003 +r 1270.10 +*Want "CEBR/CEB +1 / +SNaN" 00800003 F8008000 00800003 F8008000 +r 1280.10 +*Want "CEBR/CEB +infinity / -infinity" 00000002 F8000002 00000002 F8000002 +r 1290.10 +*Want "CEBR/CEB +infinity / -1" 00000002 F8000002 00000002 F8000002 +r 12A0.10 +*Want "CEBR/CEB +infinity / -0" 00000002 F8000002 00000002 F8000002 +r 12B0.10 +*Want "CEBR/CEB +infinity / +0" 00000002 F8000002 00000002 F8000002 +r 12C0.10 +*Want "CEBR/CEB +infinity / +1" 00000002 F8000002 00000002 F8000002 +r 12D0.10 +*Want "CEBR/CEB +infinity / +infinity" 00000000 F8000000 00000000 F8000000 +r 12E0.10 +*Want "CEBR/CEB +infinity / -QNaN" 00000003 F8000003 00000003 F8000003 +r 12F0.10 +*Want "CEBR/CEB +infinity / +SNaN" 00800003 F8008000 00800003 F8008000 +r 1300.10 +*Want "CEBR/CEB -QNaN / -infinity" 00000003 F8000003 00000003 F8000003 +r 1310.10 +*Want "CEBR/CEB -QNaN / -1" 00000003 F8000003 00000003 F8000003 +r 1320.10 +*Want "CEBR/CEB -QNaN / -0" 00000003 F8000003 00000003 F8000003 +r 1330.10 +*Want "CEBR/CEB -QNaN / +0" 00000003 F8000003 00000003 F8000003 +r 1340.10 +*Want "CEBR/CEB -QNaN / +1" 00000003 F8000003 00000003 F8000003 +r 1350.10 +*Want "CEBR/CEB -QNaN / +infinity" 00000003 F8000003 00000003 F8000003 +r 1360.10 +*Want "CEBR/CEB -QNaN / -QNaN" 00000003 F8000003 00000003 F8000003 +r 1370.10 +*Want "CEBR/CEB -QNaN / +SNaN" 00800003 F8008000 00800003 F8008000 +r 1380.10 +*Want "CEBR/CEB +SNaN / -infinity" 00800003 F8008000 00800003 F8008000 +r 1390.10 +*Want "CEBR/CEB +SNaN / -1" 00800003 F8008000 00800003 F8008000 +r 13A0.10 +*Want "CEBR/CEB +SNaN / -0" 00800003 F8008000 00800003 F8008000 +r 13B0.10 +*Want "CEBR/CEB +SNaN / +0" 00800003 F8008000 00800003 F8008000 +r 13C0.10 +*Want "CEBR/CEB +SNaN / +1" 00800003 F8008000 00800003 F8008000 +r 13D0.10 +*Want "CEBR/CEB +SNaN / +infinity" 00800003 F8008000 00800003 F8008000 +r 13E0.10 +*Want "CEBR/CEB +SNaN / -QNaN" 00800003 F8008000 00800003 F8008000 +r 13F0.10 +*Want "CEBR/CEB +SNaN / +SNaN" 00800003 F8008000 00800003 F8008000 + + + +# Compare and Signal results - FPCR contents and CC +r 1400.10 +*Want "KEBR/KEB -infinity / -infinity" 00000000 F8000000 00000000 F8000000 +r 1410.10 +*Want "KEBR/KEB -infinity / -1" 00000001 F8000001 00000001 F8000001 +r 1420.10 +*Want "KEBR/KEB -infinity / -0" 00000001 F8000001 00000001 F8000001 +r 1430.10 +*Want "KEBR/KEB -infinity / +0" 00000001 F8000001 00000001 F8000001 +r 1440.10 +*Want "KEBR/KEB -infinity / +1" 00000001 F8000001 00000001 F8000001 +r 1450.10 +*Want "KEBR/KEB -infinity / +infinity" 00000001 F8000001 00000001 F8000001 +r 1460.10 +*Want "KEBR/KEB -infinity / -QNaN" 00800003 F8008000 00800003 F8008000 +r 1470.10 +*Want "KEBR/KEB -infinity / +SNaN" 00800003 F8008000 00800003 F8008000 +r 1480.10 +*Want "KEBR/KEB -1 / -infinity" 00000002 F8000002 00000002 F8000002 +r 1490.10 +*Want "KEBR/KEB -1 / -1" 00000000 F8000000 00000000 F8000000 +r 14A0.10 +*Want "KEBR/KEB -1 / -0" 00000001 F8000001 00000001 F8000001 +r 14B0.10 +*Want "KEBR/KEB -1 / +0" 00000001 F8000001 00000001 F8000001 +r 14C0.10 +*Want "KEBR/KEB -1 / +1" 00000001 F8000001 00000001 F8000001 +r 14D0.10 +*Want "KEBR/KEB -1 / +infinity" 00000001 F8000001 00000001 F8000001 +r 14E0.10 +*Want "KEBR/KEB -1 / -QNaN" 00800003 F8008000 00800003 F8008000 +r 14F0.10 +*Want "KEBR/KEB -1 / +SNaN" 00800003 F8008000 00800003 F8008000 +r 1500.10 +*Want "KEBR/KEB -0 / -infinity" 00000002 F8000002 00000002 F8000002 +r 1510.10 +*Want "KEBR/KEB -0 / -1" 00000002 F8000002 00000002 F8000002 +r 1520.10 +*Want "KEBR/KEB -0 / -0" 00000000 F8000000 00000000 F8000000 +r 1530.10 +*Want "KEBR/KEB -0 / +0" 00000000 F8000000 00000000 F8000000 +r 1540.10 +*Want "KEBR/KEB -0 / +1" 00000001 F8000001 00000001 F8000001 +r 1550.10 +*Want "KEBR/KEB -0 / +infinity" 00000001 F8000001 00000001 F8000001 +r 1560.10 +*Want "KEBR/KEB -0 / -QNaN" 00800003 F8008000 00800003 F8008000 +r 1570.10 +*Want "KEBR/KEB -0 / +SNaN" 00800003 F8008000 00800003 F8008000 +r 1580.10 +*Want "KEBR/KEB +0 / -infinity" 00000002 F8000002 00000002 F8000002 +r 1590.10 +*Want "KEBR/KEB +0 / -1" 00000002 F8000002 00000002 F8000002 +r 15A0.10 +*Want "KEBR/KEB +0 / -0" 00000000 F8000000 00000000 F8000000 +r 15B0.10 +*Want "KEBR/KEB +0 / +0" 00000000 F8000000 00000000 F8000000 +r 15C0.10 +*Want "KEBR/KEB +0 / +1" 00000001 F8000001 00000001 F8000001 +r 15D0.10 +*Want "KEBR/KEB +0 / +infinity" 00000001 F8000001 00000001 F8000001 +r 15E0.10 +*Want "KEBR/KEB +0 / -QNaN" 00800003 F8008000 00800003 F8008000 +r 15F0.10 +*Want "KEBR/KEB +0 / +SNaN" 00800003 F8008000 00800003 F8008000 +r 1600.10 +*Want "KEBR/KEB +1 / -infinity" 00000002 F8000002 00000002 F8000002 +r 1610.10 +*Want "KEBR/KEB +1 / -1" 00000002 F8000002 00000002 F8000002 +r 1620.10 +*Want "KEBR/KEB +1 / -0" 00000002 F8000002 00000002 F8000002 +r 1630.10 +*Want "KEBR/KEB +1 / +0" 00000002 F8000002 00000002 F8000002 +r 1640.10 +*Want "KEBR/KEB +1 / +1" 00000000 F8000000 00000000 F8000000 +r 1650.10 +*Want "KEBR/KEB +1 / +infinity" 00000001 F8000001 00000001 F8000001 +r 1660.10 +*Want "KEBR/KEB +1 / -QNaN" 00800003 F8008000 00800003 F8008000 +r 1670.10 +*Want "KEBR/KEB +1 / +SNaN" 00800003 F8008000 00800003 F8008000 +r 1680.10 +*Want "KEBR/KEB +infinity / -infinity" 00000002 F8000002 00000002 F8000002 +r 1690.10 +*Want "KEBR/KEB +infinity / -1" 00000002 F8000002 00000002 F8000002 +r 16A0.10 +*Want "KEBR/KEB +infinity / -0" 00000002 F8000002 00000002 F8000002 +r 16B0.10 +*Want "KEBR/KEB +infinity / +0" 00000002 F8000002 00000002 F8000002 +r 16C0.10 +*Want "KEBR/KEB +infinity / +1" 00000002 F8000002 00000002 F8000002 +r 16D0.10 +*Want "KEBR/KEB +infinity / +infinity" 00000000 F8000000 00000000 F8000000 +r 16E0.10 +*Want "KEBR/KEB +infinity / -QNaN" 00800003 F8008000 00800003 F8008000 +r 16F0.10 +*Want "KEBR/KEB +infinity / +SNaN" 00800003 F8008000 00800003 F8008000 +r 1700.10 +*Want "KEBR/KEB -QNaN / -infinity" 00800003 F8008000 00800003 F8008000 +r 1710.10 +*Want "KEBR/KEB -QNaN / -1" 00800003 F8008000 00800003 F8008000 +r 1720.10 +*Want "KEBR/KEB -QNaN / -0" 00800003 F8008000 00800003 F8008000 +r 1730.10 +*Want "KEBR/KEB -QNaN / +0" 00800003 F8008000 00800003 F8008000 +r 1740.10 +*Want "KEBR/KEB -QNaN / +1" 00800003 F8008000 00800003 F8008000 +r 1750.10 +*Want "KEBR/KEB -QNaN / +infinity" 00800003 F8008000 00800003 F8008000 +r 1760.10 +*Want "KEBR/KEB -QNaN / -QNaN" 00800003 F8008000 00800003 F8008000 +r 1770.10 +*Want "KEBR/KEB -QNaN / +SNaN" 00800003 F8008000 00800003 F8008000 +r 1780.10 +*Want "KEBR/KEB +SNaN / -infinity" 00800003 F8008000 00800003 F8008000 +r 1790.10 +*Want "KEBR/KEB +SNaN / -1" 00800003 F8008000 00800003 F8008000 +r 17A0.10 +*Want "KEBR/KEB +SNaN / -0" 00800003 F8008000 00800003 F8008000 +r 17B0.10 +*Want "KEBR/KEB +SNaN / +0" 00800003 F8008000 00800003 F8008000 +r 17C0.10 +*Want "KEBR/KEB +SNaN / +1" 00800003 F8008000 00800003 F8008000 +r 17D0.10 +*Want "KEBR/KEB +SNaN / +infinity" 00800003 F8008000 00800003 F8008000 +r 17E0.10 +*Want "KEBR/KEB +SNaN / -QNaN" 00800003 F8008000 00800003 F8008000 +r 17F0.10 +*Want "KEBR/KEB +SNaN / +SNaN" 00800003 F8008000 00800003 F8008000 + + +# Compare long BFP results - FPCR contents and CC +*Compare +r 2000.10 +*Want "CDBR/CDB -infinity / -infinity" 00000000 F8000000 00000000 F8000000 +r 2010.10 +*Want "CDBR/CDB -infinity / -1" 00000001 F8000001 00000001 F8000001 +r 2020.10 +*Want "CDBR/CDB -infinity / -0" 00000001 F8000001 00000001 F8000001 +r 2030.10 +*Want "CDBR/CDB -infinity / +0" 00000001 F8000001 00000001 F8000001 +r 2040.10 +*Want "CDBR/CDB -infinity / +1" 00000001 F8000001 00000001 F8000001 +r 2050.10 +*Want "CDBR/CDB -infinity / +infinity" 00000001 F8000001 00000001 F8000001 +r 2060.10 +*Want "CDBR/CDB -infinity / -QNaN" 00000003 F8000003 00000003 F8000003 +r 2070.10 +*Want "CDBR/CDB -infinity / +SNaN" 00800003 F8008000 00800003 F8008000 +r 2080.10 +*Want "CDBR/CDB -1 / -infinity" 00000002 F8000002 00000002 F8000002 +r 2090.10 +*Want "CDBR/CDB -1 / -1" 00000000 F8000000 00000000 F8000000 +r 20A0.10 +*Want "CDBR/CDB -1 / -0" 00000001 F8000001 00000001 F8000001 +r 20B0.10 +*Want "CDBR/CDB -1 / +0" 00000001 F8000001 00000001 F8000001 +r 20C0.10 +*Want "CDBR/CDB -1 / +1" 00000001 F8000001 00000001 F8000001 +r 20D0.10 +*Want "CDBR/CDB -1 / +infinity" 00000001 F8000001 00000001 F8000001 +r 20E0.10 +*Want "CDBR/CDB -1 / -QNaN" 00000003 F8000003 00000003 F8000003 +r 20F0.10 +*Want "CDBR/CDB -1 / +SNaN" 00800003 F8008000 00800003 F8008000 +r 2100.10 +*Want "CDBR/CDB -0 / -infinity" 00000002 F8000002 00000002 F8000002 +r 2110.10 +*Want "CDBR/CDB -0 / -1" 00000002 F8000002 00000002 F8000002 +r 2120.10 +*Want "CDBR/CDB -0 / -0" 00000000 F8000000 00000000 F8000000 +r 2130.10 +*Want "CDBR/CDB -0 / +0" 00000000 F8000000 00000000 F8000000 +r 2140.10 +*Want "CDBR/CDB -0 / +1" 00000001 F8000001 00000001 F8000001 +r 2150.10 +*Want "CDBR/CDB -0 / +infinity" 00000001 F8000001 00000001 F8000001 +r 2160.10 +*Want "CDBR/CDB -0 / -QNaN" 00000003 F8000003 00000003 F8000003 +r 2170.10 +*Want "CDBR/CDB -0 / +SNaN" 00800003 F8008000 00800003 F8008000 +r 2180.10 +*Want "CDBR/CDB +0 / -infinity" 00000002 F8000002 00000002 F8000002 +r 2190.10 +*Want "CDBR/CDB +0 / -1" 00000002 F8000002 00000002 F8000002 +r 21A0.10 +*Want "CDBR/CDB +0 / -0" 00000000 F8000000 00000000 F8000000 +r 21B0.10 +*Want "CDBR/CDB +0 / +0" 00000000 F8000000 00000000 F8000000 +r 21C0.10 +*Want "CDBR/CDB +0 / +1" 00000001 F8000001 00000001 F8000001 +r 21D0.10 +*Want "CDBR/CDB +0 / +infinity" 00000001 F8000001 00000001 F8000001 +r 21E0.10 +*Want "CDBR/CDB +0 / -QNaN" 00000003 F8000003 00000003 F8000003 +r 21F0.10 +*Want "CDBR/CDB +0 / +SNaN" 00800003 F8008000 00800003 F8008000 +r 2200.10 +*Want "CDBR/CDB +1 / -infinity" 00000002 F8000002 00000002 F8000002 +r 2210.10 +*Want "CDBR/CDB +1 / -1" 00000002 F8000002 00000002 F8000002 +r 2220.10 +*Want "CDBR/CDB +1 / -0" 00000002 F8000002 00000002 F8000002 +r 2230.10 +*Want "CDBR/CDB +1 / +0" 00000002 F8000002 00000002 F8000002 +r 2240.10 +*Want "CDBR/CDB +1 / +1" 00000000 F8000000 00000000 F8000000 +r 2250.10 +*Want "CDBR/CDB +1 / +infinity" 00000001 F8000001 00000001 F8000001 +r 2260.10 +*Want "CDBR/CDB +1 / -QNaN" 00000003 F8000003 00000003 F8000003 +r 2270.10 +*Want "CDBR/CDB +1 / +SNaN" 00800003 F8008000 00800003 F8008000 +r 2280.10 +*Want "CDBR/CDB +infinity / -infinity" 00000002 F8000002 00000002 F8000002 +r 2290.10 +*Want "CDBR/CDB +infinity / -1" 00000002 F8000002 00000002 F8000002 +r 22A0.10 +*Want "CDBR/CDB +infinity / -0" 00000002 F8000002 00000002 F8000002 +r 22B0.10 +*Want "CDBR/CDB +infinity / +0" 00000002 F8000002 00000002 F8000002 +r 22C0.10 +*Want "CDBR/CDB +infinity / +1" 00000002 F8000002 00000002 F8000002 +r 22D0.10 +*Want "CDBR/CDB +infinity / +infinity" 00000000 F8000000 00000000 F8000000 +r 22E0.10 +*Want "CDBR/CDB +infinity / -QNaN" 00000003 F8000003 00000003 F8000003 +r 22F0.10 +*Want "CDBR/CDB +infinity / +SNaN" 00800003 F8008000 00800003 F8008000 +r 2300.10 +*Want "CDBR/CDB -QNaN / -infinity" 00000003 F8000003 00000003 F8000003 +r 2310.10 +*Want "CDBR/CDB -QNaN / -1" 00000003 F8000003 00000003 F8000003 +r 2320.10 +*Want "CDBR/CDB -QNaN / -0" 00000003 F8000003 00000003 F8000003 +r 2330.10 +*Want "CDBR/CDB -QNaN / +0" 00000003 F8000003 00000003 F8000003 +r 2340.10 +*Want "CDBR/CDB -QNaN / +1" 00000003 F8000003 00000003 F8000003 +r 2350.10 +*Want "CDBR/CDB -QNaN / +infinity" 00000003 F8000003 00000003 F8000003 +r 2360.10 +*Want "CDBR/CDB -QNaN / -QNaN" 00000003 F8000003 00000003 F8000003 +r 2370.10 +*Want "CDBR/CDB -QNaN / +SNaN" 00800003 F8008000 00800003 F8008000 +r 2380.10 +*Want "CDBR/CDB +SNaN / -infinity" 00800003 F8008000 00800003 F8008000 +r 2390.10 +*Want "CDBR/CDB +SNaN / -1" 00800003 F8008000 00800003 F8008000 +r 23A0.10 +*Want "CDBR/CDB +SNaN / -0" 00800003 F8008000 00800003 F8008000 +r 23B0.10 +*Want "CDBR/CDB +SNaN / +0" 00800003 F8008000 00800003 F8008000 +r 23C0.10 +*Want "CDBR/CDB +SNaN / +1" 00800003 F8008000 00800003 F8008000 +r 23D0.10 +*Want "CDBR/CDB +SNaN / +infinity" 00800003 F8008000 00800003 F8008000 +r 23E0.10 +*Want "CDBR/CDB +SNaN / -QNaN" 00800003 F8008000 00800003 F8008000 +r 23F0.10 +*Want "CDBR/CDB +SNaN / +SNaN" 00800003 F8008000 00800003 F8008000 + + +# Compare and Signal results- FPCR contents and CC +r 2400.10 +*Want "KDBR/KDB -infinity / -infinity" 00000000 F8000000 00000000 F8000000 +r 2410.10 +*Want "KDBR/KDB -infinity / -1" 00000001 F8000001 00000001 F8000001 +r 2420.10 +*Want "KDBR/KDB -infinity / -0" 00000001 F8000001 00000001 F8000001 +r 2430.10 +*Want "KDBR/KDB -infinity / +0" 00000001 F8000001 00000001 F8000001 +r 2440.10 +*Want "KDBR/KDB -infinity / +1" 00000001 F8000001 00000001 F8000001 +r 2450.10 +*Want "KDBR/KDB -infinity / +infinity" 00000001 F8000001 00000001 F8000001 +r 2460.10 +*Want "KDBR/KDB -infinity / -QNaN" 00800003 F8008000 00800003 F8008000 +r 2470.10 +*Want "KDBR/KDB -infinity / +SNaN" 00800003 F8008000 00800003 F8008000 +r 2480.10 +*Want "KDBR/KDB -1 / -infinity" 00000002 F8000002 00000002 F8000002 +r 2490.10 +*Want "KDBR/KDB -1 / -1" 00000000 F8000000 00000000 F8000000 +r 24A0.10 +*Want "KDBR/KDB -1 / -0" 00000001 F8000001 00000001 F8000001 +r 24B0.10 +*Want "KDBR/KDB -1 / +0" 00000001 F8000001 00000001 F8000001 +r 24C0.10 +*Want "KDBR/KDB -1 / +1" 00000001 F8000001 00000001 F8000001 +r 24D0.10 +*Want "KDBR/KDB -1 / +infinity" 00000001 F8000001 00000001 F8000001 +r 24E0.10 +*Want "KDBR/KDB -1 / -QNaN" 00800003 F8008000 00800003 F8008000 +r 24F0.10 +*Want "KDBR/KDB -1 / +SNaN" 00800003 F8008000 00800003 F8008000 +r 2500.10 +*Want "KDBR/KDB -0 / -infinity" 00000002 F8000002 00000002 F8000002 +r 2510.10 +*Want "KDBR/KDB -0 / -1" 00000002 F8000002 00000002 F8000002 +r 2520.10 +*Want "KDBR/KDB -0 / -0" 00000000 F8000000 00000000 F8000000 +r 2530.10 +*Want "KDBR/KDB -0 / +0" 00000000 F8000000 00000000 F8000000 +r 2540.10 +*Want "KDBR/KDB -0 / +1" 00000001 F8000001 00000001 F8000001 +r 2550.10 +*Want "KDBR/KDB -0 / +infinity" 00000001 F8000001 00000001 F8000001 +r 2560.10 +*Want "KDBR/KDB -0 / -QNaN" 00800003 F8008000 00800003 F8008000 +r 2570.10 +*Want "KDBR/KDB -0 / +SNaN" 00800003 F8008000 00800003 F8008000 +r 2580.10 +*Want "KDBR/KDB +0 / -infinity" 00000002 F8000002 00000002 F8000002 +r 2590.10 +*Want "KDBR/KDB +0 / -1" 00000002 F8000002 00000002 F8000002 +r 25A0.10 +*Want "KDBR/KDB +0 / -0" 00000000 F8000000 00000000 F8000000 +r 25B0.10 +*Want "KDBR/KDB +0 / +0" 00000000 F8000000 00000000 F8000000 +r 25C0.10 +*Want "KDBR/KDB +0 / +1" 00000001 F8000001 00000001 F8000001 +r 25D0.10 +*Want "KDBR/KDB +0 / +infinity" 00000001 F8000001 00000001 F8000001 +r 25E0.10 +*Want "KDBR/KDB +0 / -QNaN" 00800003 F8008000 00800003 F8008000 +r 25F0.10 +*Want "KDBR/KDB +0 / +SNaN" 00800003 F8008000 00800003 F8008000 +r 2600.10 +*Want "KDBR/KDB +1 / -infinity" 00000002 F8000002 00000002 F8000002 +r 2610.10 +*Want "KDBR/KDB +1 / -1" 00000002 F8000002 00000002 F8000002 +r 2620.10 +*Want "KDBR/KDB +1 / -0" 00000002 F8000002 00000002 F8000002 +r 2630.10 +*Want "KDBR/KDB +1 / +0" 00000002 F8000002 00000002 F8000002 +r 2640.10 +*Want "KDBR/KDB +1 / +1" 00000000 F8000000 00000000 F8000000 +r 2650.10 +*Want "KDBR/KDB +1 / +infinity" 00000001 F8000001 00000001 F8000001 +r 2660.10 +*Want "KDBR/KDB +1 / -QNaN" 00800003 F8008000 00800003 F8008000 +r 2670.10 +*Want "KDBR/KDB +1 / +SNaN" 00800003 F8008000 00800003 F8008000 +r 2680.10 +*Want "KDBR/KDB +infinity / -infinity" 00000002 F8000002 00000002 F8000002 +r 2690.10 +*Want "KDBR/KDB +infinity / -1" 00000002 F8000002 00000002 F8000002 +r 26A0.10 +*Want "KDBR/KDB +infinity / -0" 00000002 F8000002 00000002 F8000002 +r 26B0.10 +*Want "KDBR/KDB +infinity / +0" 00000002 F8000002 00000002 F8000002 +r 26C0.10 +*Want "KDBR/KDB +infinity / +1" 00000002 F8000002 00000002 F8000002 +r 26D0.10 +*Want "KDBR/KDB +infinity / +infinity" 00000000 F8000000 00000000 F8000000 +r 26E0.10 +*Want "KDBR/KDB +infinity / -QNaN" 00800003 F8008000 00800003 F8008000 +r 26F0.10 +*Want "KDBR/KDB +infinity / +SNaN" 00800003 F8008000 00800003 F8008000 +r 2700.10 +*Want "KDBR/KDB -QNaN / -infinity" 00800003 F8008000 00800003 F8008000 +r 2710.10 +*Want "KDBR/KDB -QNaN / -1" 00800003 F8008000 00800003 F8008000 +r 2720.10 +*Want "KDBR/KDB -QNaN / -0" 00800003 F8008000 00800003 F8008000 +r 2730.10 +*Want "KDBR/KDB -QNaN / +0" 00800003 F8008000 00800003 F8008000 +r 2740.10 +*Want "KDBR/KDB -QNaN / +1" 00800003 F8008000 00800003 F8008000 +r 2750.10 +*Want "KDBR/KDB -QNaN / +infinity" 00800003 F8008000 00800003 F8008000 +r 2760.10 +*Want "KDBR/KDB -QNaN / -QNaN" 00800003 F8008000 00800003 F8008000 +r 2770.10 +*Want "KDBR/KDB -QNaN / +SNaN" 00800003 F8008000 00800003 F8008000 +r 2780.10 +*Want "KDBR/KDB +SNaN / -infinity" 00800003 F8008000 00800003 F8008000 +r 2790.10 +*Want "KDBR/KDB +SNaN / -1" 00800003 F8008000 00800003 F8008000 +r 27A0.10 +*Want "KDBR/KDB +SNaN / -0" 00800003 F8008000 00800003 F8008000 +r 27B0.10 +*Want "KDBR/KDB +SNaN / +0" 00800003 F8008000 00800003 F8008000 +r 27C0.10 +*Want "KDBR/KDB +SNaN / +1" 00800003 F8008000 00800003 F8008000 +r 27D0.10 +*Want "KDBR/KDB +SNaN / +infinity" 00800003 F8008000 00800003 F8008000 +r 27E0.10 +*Want "KDBR/KDB +SNaN / -QNaN" 00800003 F8008000 00800003 F8008000 +r 27F0.10 +*Want "KDBR/KDB +SNaN / +SNaN" 00800003 F8008000 00800003 F8008000 + + +# Compare extended BFP results - FPCR contents and CC +*Compare +r 3000.08 +*Want "CXBR -infinity / -infinity" 00000000 F8000000 +r 3010.08 +*Want "CXBR -infinity / -1" 00000001 F8000001 +r 3020.08 +*Want "CXBR -infinity / -0" 00000001 F8000001 +r 3030.08 +*Want "CXBR -infinity / +0" 00000001 F8000001 +r 3040.08 +*Want "CXBR -infinity / +1" 00000001 F8000001 +r 3050.08 +*Want "CXBR -infinity / +infinity" 00000001 F8000001 +r 3060.08 +*Want "CXBR -infinity / -QNaN" 00000003 F8000003 +r 3070.08 +*Want "CXBR -infinity / +SNaN" 00800003 F8008000 +r 3080.08 +*Want "CXBR -1 / -infinity" 00000002 F8000002 +r 3090.08 +*Want "CXBR -1 / -1" 00000000 F8000000 +r 30A0.08 +*Want "CXBR -1 / -0" 00000001 F8000001 +r 30B0.08 +*Want "CXBR -1 / +0" 00000001 F8000001 +r 30C0.08 +*Want "CXBR -1 / +1" 00000001 F8000001 +r 30D0.08 +*Want "CXBR -1 / +infinity" 00000001 F8000001 +r 30E0.08 +*Want "CXBR -1 / -QNaN" 00000003 F8000003 +r 30F0.08 +*Want "CXBR -1 / +SNaN" 00800003 F8008000 +r 3100.08 +*Want "CXBR -0 / -infinity" 00000002 F8000002 +r 3110.08 +*Want "CXBR -0 / -1" 00000002 F8000002 +r 3120.08 +*Want "CXBR -0 / -0" 00000000 F8000000 +r 3130.08 +*Want "CXBR -0 / +0" 00000000 F8000000 +r 3140.08 +*Want "CXBR -0 / +1" 00000001 F8000001 +r 3150.08 +*Want "CXBR -0 / +infinity" 00000001 F8000001 +r 3160.08 +*Want "CXBR -0 / -QNaN" 00000003 F8000003 +r 3170.08 +*Want "CXBR -0 / +SNaN" 00800003 F8008000 +r 3180.08 +*Want "CXBR +0 / -infinity" 00000002 F8000002 +r 3190.08 +*Want "CXBR +0 / -1" 00000002 F8000002 +r 31A0.08 +*Want "CXBR +0 / -0" 00000000 F8000000 +r 31B0.08 +*Want "CXBR +0 / +0" 00000000 F8000000 +r 31C0.08 +*Want "CXBR +0 / +1" 00000001 F8000001 +r 31D0.08 +*Want "CXBR +0 / +infinity" 00000001 F8000001 +r 31E0.08 +*Want "CXBR +0 / -QNaN" 00000003 F8000003 +r 31F0.08 +*Want "CXBR +0 / +SNaN" 00800003 F8008000 +r 3200.08 +*Want "CXBR +1 / -infinity" 00000002 F8000002 +r 3210.08 +*Want "CXBR +1 / -1" 00000002 F8000002 +r 3220.08 +*Want "CXBR +1 / -0" 00000002 F8000002 +r 3230.08 +*Want "CXBR +1 / +0" 00000002 F8000002 +r 3240.08 +*Want "CXBR +1 / +1" 00000000 F8000000 +r 3250.08 +*Want "CXBR +1 / +infinity" 00000001 F8000001 +r 3260.08 +*Want "CXBR +1 / -QNaN" 00000003 F8000003 +r 3270.08 +*Want "CXBR +1 / +SNaN" 00800003 F8008000 +r 3280.08 +*Want "CXBR +infinity / -infinity" 00000002 F8000002 +r 3290.08 +*Want "CXBR +infinity / -1" 00000002 F8000002 +r 32A0.08 +*Want "CXBR +infinity / -0" 00000002 F8000002 +r 32B0.08 +*Want "CXBR +infinity / +0" 00000002 F8000002 +r 32C0.08 +*Want "CXBR +infinity / +1" 00000002 F8000002 +r 32D0.08 +*Want "CXBR +infinity / +infinity" 00000000 F8000000 +r 32E0.08 +*Want "CXBR +infinity / -QNaN" 00000003 F8000003 +r 32F0.08 +*Want "CXBR +infinity / +SNaN" 00800003 F8008000 +r 3300.08 +*Want "CXBR -QNaN / -infinity" 00000003 F8000003 +r 3310.08 +*Want "CXBR -QNaN / -1" 00000003 F8000003 +r 3320.08 +*Want "CXBR -QNaN / -0" 00000003 F8000003 +r 3330.08 +*Want "CXBR -QNaN / +0" 00000003 F8000003 +r 3340.08 +*Want "CXBR -QNaN / +1" 00000003 F8000003 +r 3350.08 +*Want "CXBR -QNaN / +infinity" 00000003 F8000003 +r 3360.08 +*Want "CXBR -QNaN / -QNaN" 00000003 F8000003 +r 3370.08 +*Want "CXBR -QNaN / +SNaN" 00800003 F8008000 +r 3380.08 +*Want "CXBR +SNaN / -infinity" 00800003 F8008000 +r 3390.08 +*Want "CXBR +SNaN / -1" 00800003 F8008000 +r 33A0.08 +*Want "CXBR +SNaN / -0" 00800003 F8008000 +r 33B0.08 +*Want "CXBR +SNaN / +0" 00800003 F8008000 +r 33C0.08 +*Want "CXBR +SNaN / +1" 00800003 F8008000 +r 33D0.08 +*Want "CXBR +SNaN / +infinity" 00800003 F8008000 +r 33E0.08 +*Want "CXBR +SNaN / -QNaN" 00800003 F8008000 +r 33F0.08 +*Want "CXBR +SNaN / +SNaN" 00800003 F8008000 + + +# Compare And Signal extended BFP results - FPCR contents and CC +*Compare +r 3400.08 +*Want "KXBR -infinity / -infinity" 00000000 F8000000 +r 3410.08 +*Want "KXBR -infinity / -1" 00000001 F8000001 +r 3420.08 +*Want "KXBR -infinity / -0" 00000001 F8000001 +r 3430.08 +*Want "KXBR -infinity / +0" 00000001 F8000001 +r 3440.08 +*Want "KXBR -infinity / +1" 00000001 F8000001 +r 3450.08 +*Want "KXBR -infinity / +infinity" 00000001 F8000001 +r 3460.08 +*Want "KXBR -infinity / -QNaN" 00800003 F8008000 +r 3470.08 +*Want "KXBR -infinity / +SNaN" 00800003 F8008000 +r 3480.08 +*Want "KXBR -1 / -infinity" 00000002 F8000002 +r 3490.08 +*Want "KXBR -1 / -1" 00000000 F8000000 +r 34A0.08 +*Want "KXBR -1 / -0" 00000001 F8000001 +r 34B0.08 +*Want "KXBR -1 / +0" 00000001 F8000001 +r 34C0.08 +*Want "KXBR -1 / +1" 00000001 F8000001 +r 34D0.08 +*Want "KXBR -1 / +infinity" 00000001 F8000001 +r 34E0.08 +*Want "KXBR -1 / -QNaN" 00800003 F8008000 +r 34F0.08 +*Want "KXBR -1 / +SNaN" 00800003 F8008000 +r 3500.08 +*Want "KXBR -0 / -infinity" 00000002 F8000002 +r 3510.08 +*Want "KXBR -0 / -1" 00000002 F8000002 +r 3520.08 +*Want "KXBR -0 / -0" 00000000 F8000000 +r 3530.08 +*Want "KXBR -0 / +0" 00000000 F8000000 +r 3540.08 +*Want "KXBR -0 / +1" 00000001 F8000001 +r 3550.08 +*Want "KXBR -0 / +infinity" 00000001 F8000001 +r 3560.08 +*Want "KXBR -0 / -QNaN" 00800003 F8008000 +r 3570.08 +*Want "KXBR -0 / +SNaN" 00800003 F8008000 +r 3580.08 +*Want "KXBR +0 / -infinity" 00000002 F8000002 +r 3590.08 +*Want "KXBR +0 / -1" 00000002 F8000002 +r 35A0.08 +*Want "KXBR +0 / -0" 00000000 F8000000 +r 35B0.08 +*Want "KXBR +0 / +0" 00000000 F8000000 +r 35C0.08 +*Want "KXBR +0 / +1" 00000001 F8000001 +r 35D0.08 +*Want "KXBR +0 / +infinity" 00000001 F8000001 +r 35E0.08 +*Want "KXBR +0 / -QNaN" 00800003 F8008000 +r 35F0.08 +*Want "KXBR +0 / +SNaN" 00800003 F8008000 +r 3600.08 +*Want "KXBR +1 / -infinity" 00000002 F8000002 +r 3610.08 +*Want "KXBR +1 / -1" 00000002 F8000002 +r 3620.08 +*Want "KXBR +1 / -0" 00000002 F8000002 +r 3630.08 +*Want "KXBR +1 / +0" 00000002 F8000002 +r 3640.08 +*Want "KXBR +1 / +1" 00000000 F8000000 +r 3650.08 +*Want "KXBR +1 / +infinity" 00000001 F8000001 +r 3660.08 +*Want "KXBR +1 / -QNaN" 00800003 F8008000 +r 3670.08 +*Want "KXBR +1 / +SNaN" 00800003 F8008000 +r 3680.08 +*Want "KXBR +infinity / -infinity" 00000002 F8000002 +r 3690.08 +*Want "KXBR +infinity / -1" 00000002 F8000002 +r 36A0.08 +*Want "KXBR +infinity / -0" 00000002 F8000002 +r 36B0.08 +*Want "KXBR +infinity / +0" 00000002 F8000002 +r 36C0.08 +*Want "KXBR +infinity / +1" 00000002 F8000002 +r 36D0.08 +*Want "KXBR +infinity / +infinity" 00000000 F8000000 +r 36E0.08 +*Want "KXBR +infinity / -QNaN" 00800003 F8008000 +r 36F0.08 +*Want "KXBR +infinity / +SNaN" 00800003 F8008000 +r 3700.08 +*Want "KXBR -QNaN / -infinity" 00800003 F8008000 +r 3710.08 +*Want "KXBR -QNaN / -1" 00800003 F8008000 +r 3720.08 +*Want "KXBR -QNaN / -0" 00800003 F8008000 +r 3730.08 +*Want "KXBR -QNaN / +0" 00800003 F8008000 +r 3740.08 +*Want "KXBR -QNaN / +1" 00800003 F8008000 +r 3750.08 +*Want "KXBR -QNaN / +infinity" 00800003 F8008000 +r 3760.08 +*Want "KXBR -QNaN / -QNaN" 00800003 F8008000 +r 3770.08 +*Want "KXBR -QNaN / +SNaN" 00800003 F8008000 +r 3780.08 +*Want "KXBR +SNaN / -infinity" 00800003 F8008000 +r 3790.08 +*Want "KXBR +SNaN / -1" 00800003 F8008000 +r 37A0.08 +*Want "KXBR +SNaN / -0" 00800003 F8008000 +r 37B0.08 +*Want "KXBR +SNaN / +0" 00800003 F8008000 +r 37C0.08 +*Want "KXBR +SNaN / +1" 00800003 F8008000 +r 37D0.08 +*Want "KXBR +SNaN / +infinity" 00800003 F8008000 +r 37E0.08 +*Want "KXBR +SNaN / -QNaN" 00800003 F8008000 +r 37F0.08 +*Want "KXBR +SNaN / +SNaN" 00800003 F8008000 + + + + +*Done + diff --git a/tests/bfp-014-divide.asm b/tests/bfp-014-divide.asm new file mode 100644 index 000000000..6b751d56b --- /dev/null +++ b/tests/bfp-014-divide.asm @@ -0,0 +1,1274 @@ + TITLE 'bfp-014-divide.asm: Test IEEE Divide' +*********************************************************************** +* +*Testcase IEEE DIVIDE +* Test case capability includes IEEE exceptions trappable and +* otherwise. Test results, FPCR flags, and any DXC are saved for all +* tests. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* bfp-014-divide.asm +* +* This assembly-language source file is part of the +* Hercules Decimal Floating Point Validation Package +* by Stephen R. Orso +* +* Copyright 2016 by Stephen R Orso. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* +* 3. The name of the author may not be used to endorse or promote +* products derived from this software without specific prior written +* permission. +* +* DISCLAMER: THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* HOLDER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* Tests the following three conversion instructions +* DIVIDE (short BFP, RRE) +* DIVIDE (long BFP, RRE) +* DIVIDE (extended BFP, RRE) +* DIVIDE (short BFP, RXE) +* DIVIDE (long BFP, RXE) +* +* Test data is compiled into this program. The test script that runs +* this program can provide alternative test data through Hercules R +* commands. +* +* Test Case Order +* 1) Short BFP basic tests, including traps and NaN propagation +* 2) Short BFP finite number tests, incl. traps and scaling +* 3) Short BFP FPC-controlled rounding mode exhaustive tests +* 4) Long BFP basic tests, including traps and NaN propagation +* 5) Long BFP finite number tests, incl. traps and scaling +* 6) Long BFP FPC-controlled rounding mode exhaustive tests +* 7) Extended BFP basic tests, including traps and NaN propagation +* 8) Extended BFP finite number tests, incl. traps and scaling +* 9) Extended BFP FPC-controlled rounding mode exhaustive tests +* +* Three input test sets are provided each for short, long, and +* extended BFP inputs. Test values are the same for each precision +* for most tests. Overflow and underflow each require precision- +* dependent test values. +* +* Also tests the following floating point support instructions +* LOAD (Short) +* LOAD (Long) +* LFPC (Load Floating Point Control Register) +* SRNMB (Set BFP Rounding Mode 3-bit) +* STORE (Short) +* STORE (Long) +* STFPC (Store Floating Point Control Register) +* +*********************************************************************** + SPACE 2 + MACRO + PADCSECT &ENDLABL +.* +.* Macro to pad the CSECT to include result data areas if this test +.* program is not being assembled using asma. asma generates a core +.* image that is loaded by the loadcore command, and because the +.* core image is a binary stored in Github, it makes sense to make +.* this small effort to keep the core image small. +.* + AIF (D'&ENDLABL).GOODPAD + MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + MNOTE *,'No CSECT padding performed' + MEXIT +.* +.GOODPAD ANOP Label valid. See if we're on asma + AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + ORG &ENDLABL-1 Not ASMA. Pad CSECT + MEXIT +.* +.NOPAD ANOP + MNOTE *,'asma detected; no CSECT padding performed' + MEND +* +* Note: for compatibility with the z/CMS test rig, do not change +* or use R11, R14, or R15. Everything else is fair game. +* +BFPDIV START 0 +STRTLABL EQU * +R0 EQU 0 Work register for cc extraction +R1 EQU 1 +R2 EQU 2 Holds count of test input values +R3 EQU 3 Points to next test input value(s) +R4 EQU 4 Rounding tests inner loop control +R5 EQU 5 Rounding tests outer loop control +R6 EQU 6 Rounding tests top of inner loop +R7 EQU 7 Pointer to next result value(s) +R8 EQU 8 Pointer to next FPCR result +R9 EQU 9 Rounding tests top of outer loop +R10 EQU 10 Pointer to test address list +R11 EQU 11 **Reserved for z/CMS test rig +R12 EQU 12 Holds number of test cases in set +R13 EQU 13 Mainline return address +R14 EQU 14 **Return address for z/CMS test rig +R15 EQU 15 **Base register on z/CMS or Hyperion +* +* Floating Point Register equates to keep the cross reference clean +* +FPR0 EQU 0 +FPR1 EQU 1 +FPR2 EQU 2 +FPR3 EQU 3 +FPR4 EQU 4 +FPR5 EQU 5 +FPR6 EQU 6 +FPR7 EQU 7 +FPR8 EQU 8 +FPR9 EQU 9 +FPR10 EQU 10 +FPR11 EQU 11 +FPR12 EQU 12 +FPR13 EQU 13 +FPR14 EQU 14 +FPR15 EQU 15 +* + USING *,R15 +* +* Above works on real iron (R15=0 after sysclear) +* and in z/CMS (R15 points to start of load module) +* + SPACE 2 +*********************************************************************** +* +* Low core definitions, Restart PSW, and Program Check Routine. +* +*********************************************************************** + SPACE 2 + ORG STRTLABL+X'8E' Program check interrution code +PCINTCD DS H +* +PCOLDPSW EQU STRTLABL+X'150' z/Arch Program check old PSW +* + ORG STRTLABL+X'1A0' z/Arch Restart PSW + DC X'0000000180000000',AD(START) +* + ORG STRTLABL+X'1D0' z/Arch Program check old PSW + DC X'0000000000000000',AD(PROGCHK) +* +* Program check routine. If Data Exception, continue execution at +* the instruction following the program check. Otherwise, hard wait. +* No need to collect data. All interesting DXC stuff is captured +* in the FPCR. +* + ORG STRTLABL+X'200' +PROGCHK DS 0H Program check occured... + CLI PCINTCD+1,X'07' Data Exception? + JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) + LPSWE PCOLDPSW ..yes, resume program execution +PCNOTDTA DS 0H + LTR R14,R14 Return address provided? + BNZR R14 Yes, return to z/CMS test rig. + LPSWE HARDWAIT Not data exception, enter disabled wait + EJECT +*********************************************************************** +* +* Main program. Enable Advanced Floating Point, process test cases. +* +*********************************************************************** + SPACE 2 +START DS 0H + STCTL R0,R0,CTLR0 Store CR0 to enable AFP + OI CTLR0+1,X'04' Turn on AFP bit + LCTL R0,R0,CTLR0 Reload updated CR0 +* + LA R10,SHORTNF Point to short BFP non-finite inputs + BAS R13,SBFPNF Divide short BFP non-finites + LA R10,SHORTF Point to short BFP finite inputs + BAS R13,SBFPF Divide short BFP finites + LA R10,RMSHORTS Point to short BFP rounding mode tests + BAS R13,SBFPRM Divide short BFP for rounding tests +* + LA R10,LONGNF Point to long BFP non-finite inputs + BAS R13,LBFPNF Divide long BFP non-finites + LA R10,LONGF Point to long BFP finite inputs + BAS R13,LBFPF Divide long BFP finites + LA R10,RMLONGS Point to long BFP rounding mode tests + BAS R13,LBFPRM Divide long BFP for rounding tests +* + LA R10,XTNDNF Point to extended BFP non-finite inputs + BAS R13,XBFPNF Divide extended BFP non-finites + LA R10,XTNDF Point to ext'd BFP finite inputs + BAS R13,XBFPF Divide ext'd BFP finites + LA R10,RMXTNDS Point to ext'd BFP rounding mode tests + BAS R13,XBFPRM Divide ext'd BFP for rounding tests +* + LTR R14,R14 Return address provided? + BNZR R14 ..Yes, return to z/CMS test rig. + LPSWE WAITPSW All done +* + DS 0D Ensure correct alignment for psw +WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end +* +CTLR0 DS F +FPCREGNT DC X'00000000' FPCR, trap no IEEE exceptions, zero flags +FPCREGTR DC X'F8000000' FPCR, trap all IEEE exceptions, zero flags +* +* Input values parameter list, four fullwords for each test data set +* 1) Count, +* 2) Address of inputs, +* 3) Address to place results, and +* 4) Address to place DXC/Flags/cc values. +* + ORG STRTLABL+X'300' Enable run-time replacement +SHORTNF DS 0F Input pairs for short BFP non-finite tests + DC A(SBFPNFCT) + DC A(SBFPNFIN) + DC A(SBFPNFOT) + DC A(SBFPNFFL) +* +SHORTF DS 0F Input pairs for short BFP finite tests + DC A(SBFPCT) + DC A(SBFPIN) + DC A(SBFPOUT) + DC A(SBFPFLGS) +* +RMSHORTS DS 0F Input pairs for short BFP rounding testing + DC A(SBFPRMCT) + DC A(SBFPINRM) + DC A(SBFPRMO) + DC A(SBFPRMOF) +* +LONGNF DS 0F Input pairs for long BFP non-finite testing + DC A(LBFPNFCT) + DC A(LBFPNFIN) + DC A(LBFPNFOT) + DC A(LBFPNFFL) +* +LONGF DS 0F Input pairs for long BFP finite testing + DC A(LBFPCT) + DC A(LBFPIN) + DC A(LBFPOUT) + DC A(LBFPFLGS) +* +RMLONGS DS 0F Input pairs for long BFP rounding testing + DC A(LBFPRMCT) + DC A(LBFPINRM) + DC A(LBFPRMO) + DC A(LBFPRMOF) +* +XTNDNF DS 0F Inputs for ext'd BFP non-finite testing + DC A(XBFPNFCT) + DC A(XBFPNFIN) + DC A(XBFPNFOT) + DC A(XBFPNFFL) +* +XTNDF DS 0F Inputs for ext'd BFP finite testing + DC A(XBFPCT) + DC A(XBFPIN) + DC A(XBFPOUT) + DC A(XBFPFLGS) +* +RMXTNDS DS 0F Inputs for ext'd BFP non-finite testing + DC A(XBFPRMCT) + DC A(XBFPINRM) + DC A(XBFPRMO) + DC A(XBFPRMOF) +* + EJECT +*********************************************************************** +* +* Perform Divide using provided short BFP inputs. This set of tests +* checks NaN propagation, operations on values that are not finite +* numbers, and other basic tests. This set generates results that can +* be validated against Figure 19-20 on page 19-27 of SA22-7832-10. +* +* Four results are generated for each input: one RRE with all +* exceptions non-trappable, a second RRE with all exceptions trappable, +* a third RXE with all exceptions non-trappable, a fourth RXE with all +* exceptions trappable, +* +* The quotient and FPCR are stored for each result. +* +*********************************************************************** + SPACE 2 +SBFPNF DS 0H BFP Short non-finite values tests + LM R2,R3,0(R10) Get count and address of divide values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LM R4,R5,0(R10) Get count and start of divisor values +* ..which are the same as the dividends + BASR R6,0 Set top of inner loop +* + LE FPR8,0(,R3) Get short BFP dividend + LE FPR1,0(,R5) Get short BFP divisor + LFPC FPCREGNT Set exceptions non-trappable + DEBR FPR8,FPR1 Divide FPR0/FPR1 RRE + STE FPR8,0(,R7) Store short BFP quotient + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LE FPR8,0(,R3) Get short BFP dividend + LE FPR1,0(,R5) Get short BFP divisor + LFPC FPCREGTR Set exceptions trappable + DEBR FPR8,FPR1 Divide FPR0/FPR1 RRE + STE FPR8,4(,R7) Store short BFP quotient + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LE FPR8,0(,R3) Get short BFP dividend + LE FPR1,0(,R5) Get short BFP divisor + LFPC FPCREGNT Set exceptions non-trappable + DEB FPR8,0(,R5) Divide FPR0/FPR1 RXE + STE FPR8,8(,R7) Store short BFP quotient + STFPC 8(R8) Store resulting FPCR flags and DXC +* + LE FPR8,0(,R3) Get short BFP dividend + LFPC FPCREGTR Set exceptions trappable + DEB FPR8,0(,R5) Divide FPR0/FPR1 RXE + STE FPR8,12(,R7) Store short BFP quotient + STFPC 12(R8) Store resulting FPCR flags and DXC +* + LA R5,4(,R5) Point to next divisor value + LA R7,16(,R7) Point to next Divide result area + LA R8,16(,R8) Point to next Divide FPCR area + BCTR R4,R6 Loop through right-hand values +* + LA R3,4(,R3) Point to next input dividend + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Divide using provided short BFP input pairs. This set of +* tests triggers IEEE exceptions Overflow, Underflow, and Inexact and +* collects results when the exceptions do not result in a trap and when +* they do. +* +* Four results are generated for each input: one RRE with all +* exceptions non-trappable, a second RRE with all exceptions trappable, +* a third RXE with all exceptions non-trappable, a fourth RXE with all +* exceptions trappable, +* +* The quotient and FPCR are stored for each result. +* +*********************************************************************** + SPACE 2 +SBFPF LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LFPC FPCREGNT Set exceptions non-trappable + LE FPR8,0(,R3) Get short BFP dividend + LE FPR1,4(,R3) Get short BFP divisor + DEBR FPR8,FPR1 Divide FPR8/FPR1 RRE non-trappable + STE FPR8,0(,R7) Store short BFP quotient + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LE FPR8,0(,R3) Reload short BFP dividend +* ..divisor is still in FPR1 + DEBR FPR8,FPR1 Divide FPR8/FPR1 RRE trappable + STE FPR8,4(,R7) Store short BFP quotient + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable + LE FPR8,0(,R3) Reload short BFP dividend + DEB FPR8,4(,R3) Divide FPR8 by divisor RXE non-trappable + STE FPR8,8(,R7) Store short BFP quotient + STFPC 8(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LE FPR8,0(,R3) Reload short BFP dividend + DEB FPR8,4(,R3) Divide FPR8 by divisor RXE trappable + STE FPR8,12(,R7) Store short BFP quotient + STFPC 12(R8) Store resulting FPCR flags and DXC +* + LA R3,8(,R3) Point to next input value pair + LA R7,16(,R7) Point to next quotient pair + LA R8,16(,R8) Point to next FPCR result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Divide using provided short BFP input pairs. This set of +* tests exhaustively tests all rounding modes available for Divide. +* The rounding mode can only be specified in the FPC. +* +* All five FPC rounding modes are tested because the preceeding tests, +* using rounding mode RNTE, do not often create results that require +* rounding. +* +* Two results are generated for each input and rounding mode: one RRE +* and one RXE. Traps are disabled for all rounding mode tests. +* +* The quotient and FPCR contents are stored for each test. +* +*********************************************************************** + SPACE 2 +SBFPRM LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + XR R1,R1 Zero register 1 for use in IC/STC/indexing + BASR R12,0 Set top of test case loop + + LA R5,FPCMCT Get count of FPC modes to be tested + BASR R9,0 Set top of rounding mode outer loop +* + IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 0(R1) Set FPC Rounding Mode + LE FPR8,0(,R3) Get short BFP dividend + LE FPR1,4(,R3) Get short BFP divisor + DEBR FPR8,FPR1 Divide RRE FPR8/FPR1 non-trappable + STE FPR8,0(,R7) Store short BFP quotient + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 0(R1) Set FPC Rounding Mode + LE FPR8,0(,R3) Get short BFP dividend + DEB FPR8,4(,R3) Divide RXE FPR8 by divisor non-trappable + STE FPR8,4(,R7) Store short BFP quotient + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LA R7,8(,R7) Point to next quotient result set + LA R8,8(,R8) Point to next FPCR result area +* + BCTR R5,R9 Iterate to next FPC mode +* +* End of FPC modes to be tested. Advance to next test case. +* + LA R3,8(,R3) Point to next input value pair + LA R7,8(,R7) Skip to start of next result area + LA R8,8(,R8) Skip to start of next FPCR result area + BCTR R2,R12 Divide next input value lots of times +* + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Divide using provided long BFP inputs. This set of tests +* checks NaN propagation, operations on values that are not finite +* numbers, and other basic tests. This set generates results that can +* be validated against Figure 19-20 on page 19-27 of SA22-7832-10. +* +* Four results are generated for each input: one RRE with all +* exceptions non-trappable, a second RRE with all exceptions trappable, +* a third RXE with all exceptions non-trappable, a fourth RXE with all +* exceptions trappable, +* +* The quotient and FPCR are stored for each result. +* +*********************************************************************** + SPACE 2 +LBFPNF DS 0H BFP long non-finite values tests + LM R2,R3,0(R10) Get count and address of dividend values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LM R4,R5,0(R10) Get count and start of divisor values +* ..which are the same as the dividends + BASR R6,0 Set top of inner loop +* + LD FPR8,0(,R3) Get long BFP dividend + LD FPR1,0(,R5) Get long BFP divisor + LFPC FPCREGNT Set exceptions non-trappable + DDBR FPR8,FPR1 Divide FPR0/FPR1 RRE + STD FPR8,0(,R7) Store long BFP quotient + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LD FPR8,0(,R3) Get long BFP dividend + LD FPR1,0(,R5) Get long BFP divisor + LFPC FPCREGTR Set exceptions trappable + DDBR FPR8,FPR1 Divide FPR0/FPR1 RRE + STD FPR8,8(,R7) Store long BFP remainder + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LD FPR8,0(,R3) Get long BFP dividend + LFPC FPCREGNT Set exceptions non-trappable + DDB FPR8,0(,R5) Divide FPR0/FPR1 RXE + STD FPR8,16(,R7) Store long BFP quotient + STFPC 8(R8) Store resulting FPCR flags and DXC +* + LD FPR8,0(,R3) Get long BFP dividend + LFPC FPCREGTR Set exceptions trappable + DDB FPR8,0(,R5) Divide FPR0/FPR1 RXE + STD FPR8,24(,R7) Store long BFP remainder + STFPC 12(R8) Store resulting FPCR flags and DXC +* + LA R5,8(,R5) Point to next divisor value + LA R7,32(,R7) Point to next Divide result area + LA R8,16(,R8) Point to next Divide FPCR area + BCTR R4,R6 Loop through right-hand values +* + LA R3,8(,R3) Point to next dividend value + BCTR R2,R12 Divide until all cases tested + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Divide using provided long BFP input pairs. This set of +* tests triggers IEEE exceptions Overflow, Underflow, and Inexact and +* collects results when the exceptions do not result in a trap and when +* they do. +* +* Four results are generated for each input: one RRE with all +* exceptions non-trappable, a second RRE with all exceptions trappable, +* a third RXE with all exceptions non-trappable, a fourth RXE with all +* exceptions trappable, +* +* The result and FPCR are stored for each result. +* +*********************************************************************** + SPACE 2 +LBFPF LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LFPC FPCREGNT Set exceptions non-trappable + LD FPR8,0(,R3) Get short BFP dividend + LD FPR1,8(,R3) Get short BFP divisor + DDBR FPR8,FPR1 Divide FPR8/FPR1 RRE non-trappable + STD FPR8,0(,R7) Store short BFP quotient + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LD FPR8,0(,R3) Reload short BFP dividend +* ..divisor is still in FPR1 + DDBR FPR8,FPR1 Divide FPR8/FPR1 RRE trappable + STD FPR8,8(,R7) Store short BFP quotient + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable + LD FPR8,0(,R3) Reload short BFP dividend + DDB FPR8,8(,R3) Divide FPR8/FPR1 RXE non-trappable + STD FPR8,16(,R7) Store short BFP quotient + STFPC 8(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LD FPR8,0(,R3) Reload short BFP dividend + DDB FPR8,8(,R3) Divide FPR8/FPR1 RXE trappable + STD FPR8,24(,R7) Store short BFP quotient + STFPC 12(R8) Store resulting FPCR flags and DXC +* + LA R3,16(,R3) Point to next input value pair + LA R7,32(,R7) Point to next quotent result pair + LA R8,16(,R8) Point to next FPCR result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Divide using provided long BFP input pairs. This set of +* tests exhaustively tests all rounding modes available for Divide. +* The rounding mode can only be specified in the FPC. +* +* All five FPC rounding modes are tested because the preceeding tests, +* using rounding mode RNTE, do not often create results that require +* rounding. +* +* Two results are generated for each input and rounding mode: one RRE +* and one RXE. Traps are disabled for all rounding mode tests. +* +* The quotient and FPCR contents are stored for each test. +* +*********************************************************************** + SPACE 2 +LBFPRM LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + XR R1,R1 Zero register 1 for use in IC/STC/indexing + BASR R12,0 Set top of test case loop + + LA R5,FPCMCT Get count of FPC modes to be tested + BASR R9,0 Set top of rounding mode loop +* + IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 0(R1) Set FPC Rounding Mode + LD FPR8,0(,R3) Get long BFP dividend + LD FPR1,8(,R3) Get long BFP divisor + DDBR FPR8,FPR1 Divide RRE FPR8/FPR1 non-trappable + STD FPR8,0(,R7) Store long BFP quotient + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 0(R1) Set FPC Rounding Mode + LD FPR8,0(,R3) Reload long BFP dividend + DDB FPR8,8(,R3) Divide RXE FPR8 by divisor non-trappable + STD FPR8,8(,R7) Store long BFP quotient + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LA R7,16(,R7) Point to next quotient result set + LA R8,8(,R8) Point to next FPCR result area +* + BCTR R5,R9 Iterate to next FPC mode +* +* End of FPC modes to be tested. Advance to next test case. +* + LA R3,16(,R3) Point to next input value pair + LA R8,8(,R8) Skip to start of next FPCR result area + BCTR R2,R12 Divide next input value lots of times +* + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Divide using provided extended BFP inputs. This set of tests +* checks NaN propagation, operations on values that are not finite +* numbers, and other basic tests. This set generates results that can +* be validated against Figure 19-20 on page 19-27 of SA22-7832-10. +* +* Two results are generated for each input: one RRE with all +* exceptions non-trappable, and a second RRE with all exceptions +* trappable. Extended BFP Divide does not have an RXE format. +* +* The quotient and FPCR are stored for each result. +* +*********************************************************************** + SPACE 2 +XBFPNF DS 0H BFP extended non-finite values tests + LM R2,R3,0(R10) Get count and address of dividend values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LM R4,R5,0(R10) Get count and start of divisor values +* ..which are the same as the dividends + BASR R6,0 Set top of inner loop +* + LD FPR8,0(,R3) Get extended BFP dividend part 1 + LD FPR10,8(,R3) Get extended BFP dividend part 2 + LD FPR1,0(,R5) Get extended BFP divisor part 1 + LD FPR3,8(,R5) Get extended BFP divisor part 2 + LFPC FPCREGNT Set exceptions non-trappable + DXBR FPR8,FPR1 Divide FPR0/FPR1 RRE + STD FPR8,0(,R7) Store extended BFP quotient part 1 + STD FPR10,8(,R7) Store extended BFP quotient part 2 + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LD FPR8,0(,R3) Get extended BFP dividend part 1 + LD FPR10,8(,R3) Get extended BFP dividend part 2 + LD FPR1,0(,R5) Get extended BFP divisor part 1 + LD FPR3,8(,R5) Get extended BFP divisor part 2 + LFPC FPCREGTR Set exceptions trappable + DXBR FPR8,FPR1 Divide FPR0/FPR1 RRE + STD FPR8,16(,R7) Store extended BFP quotient part 1 + STD FPR10,24(,R7) Store extended BFP quotient part 2 + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LA R5,16(,R5) Point to next divisor value + LA R7,32(,R7) Point to next Divide result area + LA R8,16(,R8) Point to next Divide FPCR area + BCTR R4,R6 Loop through right-hand values +* + LA R3,16(,R3) Point to next dividend value + BCTR R2,R12 Divide until all cases tested + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Divide using provided extended BFP input pairs. This set of +* tests triggers IEEE exceptions Overflow, Underflow, and Inexact and +* collects results when the exceptions do not result in a trap and when +* they do. +* +* Two results are generated for each input: one RRE with all +* exceptions non-trappable and a second RRE with all exceptions +* trappable. There is no RXE format for Divide in extended precision. +* +* The result and FPCR are stored for each result. +* +*********************************************************************** + SPACE 2 +XBFPF LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LFPC FPCREGNT Set exceptions non-trappable + LD FPR13,0(,R3) Get extended BFP dividend part 1 + LD FPR15,8(,R3) Get extended BFP dividend part 2 + LD FPR1,16(,R3) Get extended BFP divisor part 1 + LD FPR3,24(,R3) Get extended BFP divisor part 2 + DXBR FPR13,FPR1 Divide FPR8-10/FPR1-3 RRE non-trappable + STD FPR13,0(,R7) Store extended BFP quotient part 1 + STD FPR15,8(,R7) Store extended BFP quotient part 2 + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LD FPR13,0(,R3) Reload extended BFP dividend part 1 + LD FPR15,8(,R3) Reload extended BFP dividend part 2 +* ..divisor is still in FPR1-FPR3 + DXBR FPR13,FPR1 Divide FPR13-15/FPR1-3 RRE trappable + STD FPR13,16(,R7) Store extended BFP quotient part 1 + STD FPR15,24(,R7) Store extended BFP quotient part 2 + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LA R3,32(,R3) Point to next input value pair + LA R7,32(,R7) Point to next quotent result pair + LA R8,16(,R8) Point to next FPCR result area + BCTR R2,R12 Convert next input value. +* + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Divide using provided long BFP input pairs. This set of +* tests exhaustively tests all rounding modes available for Divide. +* The rounding mode can only be specified in the FPC. +* +* All five FPC rounding modes are tested because the preceeding tests, +* using rounding mode RNTE, do not often create results that require +* rounding. +* +* Two results are generated for each input and rounding mode: one RRE +* and one RXE. Traps are disabled for all rounding mode tests. +* +* The quotient and FPCR contents are stored for each test. +* +*********************************************************************** + SPACE 2 +XBFPRM LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + XR R1,R1 Zero register 1 for use in IC/STC/indexing + BASR R12,0 Set top of test case loop + + LA R5,FPCMCT Get count of FPC modes to be tested + BASR R9,0 Set top of rounding mode loop +* + IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 0(R1) Set FPC Rounding Mode + LD FPR8,0(,R3) Get extended BFP dividend part 1 + LD FPR10,8(,R3) Get extended BFP dividend part 2 + LD FPR1,16(,R3) Get extended BFP divisor part 1 + LD FPR3,24(,R3) Get extended BFP divisor part 2 + DXBR FPR8,FPR1 Divide RRE FPR8/FPR1 non-trappable + STD FPR8,0(,R7) Store extended BFP quotient part 1 + STD FPR10,8(,R7) Store extended BFP quotient part 2 + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LA R7,16(,R7) Point to next quotient result set + LA R8,4(,R8) Point to next FPCR result area +* + BCTR R5,R9 Iterate to next FPC mode +* +* End of FPC modes to be tested. Advance to next test case. +* + LA R3,32(,R3) Point to next input value pair + LA R8,12(,R8) Skip to start of next FPCR result area + BCTR R2,R12 Divide next input value lots of times +* + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Table of FPC rounding modes to test quotient rounding modes. +* +* The Set BFP Rounding Mode does allow specification of the FPC +* rounding mode as an address, so we shall index into a table of +* BFP rounding modes without bothering with Execute. +* +*********************************************************************** + SPACE 2 +* +* Rounding modes that may be set in the FPCR. The FPCR controls +* rounding of the quotient. +* +* These are indexed directly by the loop counter, which counts down. +* So the modes are listed in reverse order here. +* +FPCMODES DS 0C + DC AL1(7) RFS, Round for shorter precision + DC AL1(3) RM, Round to -infinity + DC AL1(2) RP, Round to +infinity + DC AL1(1) RZ, Round to zero + DC AL1(0) RNTE, Round to Nearest, ties to even +FPCMCT EQU *-FPCMODES Count of FPC Modes to be tested +* + EJECT +*********************************************************************** +* +* Short BFP test data sets for Divide testing. +* +* The first test data set is used for tests of basic functionality, +* NaN propagation, and results from operations involving other than +* finite numbers. +* +* The second test data set is used for testing boundary conditions +* using two finite non-zero values. Each possible condition code +* and type of result (normal, scaled, etc) is created by members of +* this test data set. +* +* The third test data set is used for exhaustive testing of final +* results across the five rounding modes available for the Divide +* instruction. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* First input test data set, to test operations using non-finite or +* zero inputs. Member values chosen to validate part 1 of Figure 19-21 +* on page 19-29 of SA22-7832-10. Each value in this table is tested +* against every other value in the table. +* +*********************************************************************** + SPACE 2 +SBFPNFIN DS 0F Inputs for short BFP non-finite tests + DC X'FF800000' -inf + DC X'C0000000' -2.0 + DC X'80000000' -0 + DC X'00000000' +0 + DC X'40000000' +2.0 + DC X'7F800000' +inf + DC X'FFCB0000' -QNaN + DC X'7F8A0000' +SNaN +SBFPNFCT EQU (*-SBFPNFIN)/4 Count of short BFP in list + SPACE 3 +*********************************************************************** +* +* Second input test data set. These are finite pairs intended to +* trigger overflow, underflow, and inexact exceptions. Each pair is +* divided twice, once non-trappable and once trappable. Trappable +* overflow or underflow yields a scaled result. Trappable inexact +* will show whether the Incremented DXC code is returned. +* +* The following test cases are required: +* 1. Overflow +* 2. Underflow +* 3. Inexact - incremented +* 4. Inexact - truncated +* +*********************************************************************** + SPACE 2 +SBFPIN DS 0F Inputs for short BFP finite tests +* +* Following forces quotient overflow. +* + DC X'7F7FFFFF' +maxvalue + DC X'00000001' +minvalue (tiny) +* +* Divide the smallest possible normal by 2.0 to get the largest +* possible tiny, and get underflow in the process. +* + DC X'00800000' smallest possible normal + DC X'40000000' divide by 2.0, force underflow +* +* Divide 1.0 by 10.0 to get 0.1, a repeating fraction that must be +* rounded in any precision. Inexact, Incremented. +* + DC X'3F800000' +1 + DC X'41200000' +10.0 +* +* Divide 7.0 by 10.0 to get 0.7, a repeating fraction that must be +* rounded in any precision. But this one rounds down. Inexact only. +* + DC X'40100000' 7.0 + DC X'41200000' +10.0 +* +* Divide 1.0 by -10.0 to get -0.1, a repeating fraction that must be +* rounded in any precision. Inexact, Incremented. +* + DC X'3F800000' +1 + DC X'C1200000' -10.0 +* +* Divide 7.0 by -10.0 to get 0.7, a repeating fraction that must be +* rounded in any precision. But this one rounds down. Inexact only. +* + DC X'40100000' 7.0 + DC X'C1200000' -10.0 +* +SBFPCT EQU (*-SBFPIN)/4/2 Count of short BFP in list + SPACE 3 +*********************************************************************** +* +* Third input test data set. These are finite pairs intended to +* test all combinations of rounding mode for the quotient and the +* remainder. Values are chosen to create a requirement to round +* to the target precision after the computation +* +*********************************************************************** + SPACE 2 +SBFPINRM DS 0F Inputs for short BFP rounding testing +* +* Divide 1.0 by 10.0 to get 0.1, a repeating fraction that must be +* rounded in any precision. Inexact, Incremented. +* + DC X'3F800000' +1 + DC X'41200000' +10.0 +* +* Divide 7.0 by 10.0 to get 0.7, a repeating fraction that must be +* rounded in any precision. But this one rounds down. Inexact only. +* + DC X'40100000' 7.0 + DC X'41200000' +10.0 +* +* Divide 1.0 by -10.0 to get -0.1, a repeating fraction that must be +* rounded in any precision. Inexact, Incremented. +* + DC X'3F800000' +1 + DC X'C1200000' -10.0 +* +* Divide 7.0 by -10.0 to get 0.7, a repeating fraction that must be +* rounded in any precision. But this one rounds down. Inexact only. +* + DC X'40100000' 7.0 + DC X'C1200000' -10.0 +* +SBFPRMCT EQU (*-SBFPINRM)/4/2 Count of short BFP rounding tests + EJECT +*********************************************************************** +* +* Long BFP test data sets for Divide testing. +* +* The first test data set is used for tests of basic functionality, +* NaN propagation, and results from operations involving other than +* finite numbers. +* +* The second test data set is used for testing boundary conditions +* using two finite non-zero values. Each possible condition code +* and type of result (normal, scaled, etc) is created by members of +* this test data set. +* +* The third test data set is used for exhaustive testing of final +* results across the five rounding modes available for the Divide +* instruction. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* First input test data set, to test operations using non-finite or +* zero inputs. Member values chosen to validate part 1 of Figure 19-21 +* on page 19-29 of SA22-7832-10. Each value in this table is tested +* against every other value in the table. +* +*********************************************************************** + SPACE 2 +LBFPNFIN DS 0F Inputs for long BFP testing + DC X'FFF0000000000000' -inf + DC X'C000000000000000' -2.0 + DC X'8000000000000000' -0 + DC X'0000000000000000' +0 + DC X'4000000000000000' +2.0 + DC X'7FF0000000000000' +inf + DC X'FFF8B00000000000' -QNaN + DC X'7FF0A00000000000' +SNaN +LBFPNFCT EQU (*-LBFPNFIN)/8 Count of long BFP in list + SPACE 3 +*********************************************************************** +* +* Second input test data set. These are finite pairs intended to +* trigger overflow, underflow, and inexact exceptions. Each pair is +* divided twice, once non-trappable and once trappable. Trappable +* overflow or underflow yields a scaled result. Trappable inexact +* will show whether the Incremented DXC code is returned. +* +* The following test cases are required: +* 1. Overflow +* 2. Underflow +* 3. Inexact - incremented +* 4. Inexact - truncated +* +*********************************************************************** + SPACE 2 +LBFPIN DS 0D Inputs for long BFP finite tests +* +* Following forces quotient overflow. +* + DC X'7FEFFFFFFFFFFFFF' +maxvalue + DC X'0000000000000001' +minvalue (tiny) +* +* Divide the smallest possible normal by 2.0 to get the largest +* possible tiny, and get underflow in the process. +* + DC X'0010000000000000' smallest possible normal + DC X'4000000000000000' divide by 2.0, force underflow +* +* Divide 1.0 by 10.0 to get 0.1, a repeating fraction that must be +* rounded in any precision. Inexact, Incremented. +* + DC X'3FF0000000000000' +1 + DC X'4024000000000000' +10.0 +* +* Divide 7.0 by 10.0 to get 0.7, a repeating fraction that must be +* rounded in any precision. But this one rounds down. Inexact only. +* + DC X'401C000000000000' 7.0 + DC X'4024000000000000' +10.0 +* +* Divide 1.0 by -10.0 to get -0.1, a repeating fraction that must be +* rounded in any precision. Inexact, Incremented. +* + DC X'3FF0000000000000' +1 + DC X'C024000000000000' -10.0 +* +* Divide 7.0 by -10.0 to get -0.7, a repeating fraction that must be +* rounded in any precision. But this one rounds down. Inexact only. +* + DC X'401C000000000000' 7.0 + DC X'C024000000000000' -10.0 +* +LBFPCT EQU (*-LBFPIN)/8/2 Count of long BFP in list * 8 + SPACE 3 +*********************************************************************** +* +* Third input test data set. These are finite pairs intended to +* test all combinations of rounding mode for the quotient and the +* remainder. Values are chosen to create a requirement to round +* to the target precision after the computation +* +*********************************************************************** + SPACE 2 +LBFPINRM DS 0F +* +* Divide 1.0 by 10.0 to get 0.1, a repeating fraction that must be +* rounded in any precision. Inexact, Incremented. +* + DC X'3FF0000000000000' +1 + DC X'4024000000000000' +10.0 +* +* Divide 7.0 by 10.0 to get 0.7, a repeating fraction that must be +* rounded in any precision. But this one rounds down. Inexact only. +* + DC X'401C000000000000' 7.0 + DC X'4024000000000000' +10.0 +* +* Divide 1.0 by -10.0 to get -0.1, a repeating fraction that must be +* rounded in any precision. Inexact, Incremented. +* + DC X'3FF0000000000000' +1 + DC X'C024000000000000' -10.0 +* +* Divide 7.0 by -10.0 to get -0.7, a repeating fraction that must be +* rounded in any precision. But this one rounds down. Inexact only. +* + DC X'401C000000000000' 7.0 + DC X'C024000000000000' -10.0 +* +LBFPRMCT EQU (*-LBFPINRM)/8/2 Count of long BFP rounding tests * 8 + EJECT +*********************************************************************** +* +* Extended BFP test data sets for Divide testing. +* +* The first test data set is used for tests of basic functionality, +* NaN propagation, and results from operations involving other than +* finite numbers. +* +* The second test data set is used for testing boundary conditions +* using two finite non-zero values. Each possible condition code +* and type of result (normal, scaled, etc) is created by members of +* this test data set. +* +* The third test data set is used for exhaustive testing of final +* results across the five rounding modes available for the Divide +* instruction. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* First input test data set, to test operations using non-finite or +* zero inputs. Member values chosen to validate part 1 of Figure 19-21 +* on page 19-29 of SA22-7832-10. Each value in this table is tested +* against every other value in the table. +* +*********************************************************************** + SPACE 2 +XBFPNFIN DS 0F Inputs for extended BFP testing + DC X'FFFF0000000000000000000000000000' -inf + DC X'C0000000000000000000000000000000' -2.0 + DC X'80000000000000000000000000000000' -0 + DC X'00000000000000000000000000000000' +0 + DC X'40000000000000000000000000000000' +2.0 + DC X'7FFF0000000000000000000000000000' +inf + DC X'FFFF8B00000000000000000000000000' -QNaN + DC X'7FFF0A00000000000000000000000000' +SNaN +XBFPNFCT EQU (*-XBFPNFIN)/16 Count of extended BFP in list + SPACE 3 +*********************************************************************** +* +* Second input test data set. These are finite pairs intended to +* trigger overflow, underflow, and inexact exceptions. Each pair is +* divided twice, once non-trappable and once trappable. Trappable +* overflow or underflow yields a scaled result. Trappable inexact +* will show whether the Incremented DXC code is returned. +* +* The following test cases are required: +* 1. Overflow +* 2. Underflow +* 3. Inexact - incremented +* 4. Inexact - truncated +* +*********************************************************************** + SPACE 2 +XBFPIN DS 0F Inputs for long BFP finite tests +* +* Following forces quotient overflow. +* + DC X'7FFEFFFFFFFFFFFFFFFFFFFFFFFFFFFF' +maxvalue + DC X'00000000000000000000000000000001' +minvalue (tiny) +* +* Divide the smallest possible normal by 2.0 to get the largest +* possible tiny, and get underflow in the process. +* + DC X'00010000000000000000000000000000' smallest normal + DC X'40000000000000000000000000000000' divide by 2.0 +* +* Divide 1.0 by 10.0 to get 0.1, a repeating fraction that must be +* rounded in any precision. Inexact, Incremented. +* + DC X'3FFF0000000000000000000000000000' +1 + DC X'40024000000000000000000000000000' +10.0 +* +* Divide 7.0 by 10.0 to get 0.7, a repeating fraction that must be +* rounded in any precision. But this one rounds down. Inexact only. +* + DC X'4001C000000000000000000000000000' +7.0 + DC X'40024000000000000000000000000000' +10.0 +* +* Divide 1.0 by -10.0 to get -0.1, a repeating fraction that must be +* rounded in any precision. Inexact, Incremented. +* + DC X'3FFF0000000000000000000000000000' +1 + DC X'C0024000000000000000000000000000' -10.0 +* +* Divide 7.0 by -10.0 to get -0.7, a repeating fraction that must be +* rounded in any precision. But this one rounds down. Inexact only. +* + DC X'4001C000000000000000000000000000' +7.0 + DC X'C0024000000000000000000000000000' -10.0 +* +XBFPCT EQU (*-XBFPIN)/16/2 Count of long BFP in list * 8 + SPACE 3 +*********************************************************************** +* +* Third input test data set. These are finite pairs intended to +* test all combinations of rounding mode for the quotient and the +* remainder. Values are chosen to create a requirement to round +* to the target precision after the computation +* +*********************************************************************** + SPACE 2 +XBFPINRM DS 0D +* +* Divide 1.0 by 10.0 to get 0.1, a repeating fraction that must be +* rounded in any precision. Inexact, Incremented. +* + DC X'3FFF0000000000000000000000000000' +1 + DC X'40024000000000000000000000000000' +10.0 +* +* Divide 7.0 by 10.0 to get 0.7, a repeating fraction that must be +* rounded in any precision. But this one rounds down. Inexact only. +* + DC X'4001C000000000000000000000000000' +7.0 + DC X'40024000000000000000000000000000' +10.0 +* +* Divide 1.0 by -10.0 to get -0.1, a repeating fraction that must be +* rounded in any precision. Inexact, Incremented. +* + DC X'3FFF0000000000000000000000000000' +1 + DC X'C0024000000000000000000000000000' -10.0 +* +* Divide 7.0 by -10.0 to get -0.7, a repeating fraction that must be +* rounded in any precision. But this one rounds down. Inexact only. +* + DC X'4001C000000000000000000000000000' +7.0 + DC X'C0024000000000000000000000000000' -10.0 +* +XBFPRMCT EQU (*-XBFPINRM)/16/2 Count of long BFP rounding tests + EJECT +* +* Locations for results +* +SBFPNFOT EQU STRTLABL+X'1000' Integer short non-finite BFP results +* ..room for 64 tests, 64 used +SBFPNFFL EQU STRTLABL+X'1400' FPCR flags and DXC from short BFP +* ..room for 64 tests, 64 used +* +SBFPOUT EQU STRTLABL+X'1800' Integer short BFP finite results +* ..room for 16 tests, 6 used +SBFPFLGS EQU STRTLABL+X'1900' FPCR flags and DXC from short BFP +* ..room for 16 tests, 6 used +* +SBFPRMO EQU STRTLABL+X'1A00' Short BFP rounding mode test results +* ..Room for 16, 4 used. +SBFPRMOF EQU STRTLABL+X'1D00' Short BFP rounding mode FPCR results +* ..Room for 16, 4 used. +* ..next location starts at X'2000' +* +LBFPNFOT EQU STRTLABL+X'3000' Integer long non-finite BFP results +* ..room for 64 tests, 64 used +LBFPNFFL EQU STRTLABL+X'3800' FPCR flags and DXC from long BFP +* ..room for 64 tests, 64 used +* +LBFPOUT EQU STRTLABL+X'3C00' Integer long BFP finite results +* ..room for 16 tests, 6 used +LBFPFLGS EQU STRTLABL+X'3E00' FPCR flags and DXC from long BFP +* ..room for 16 tests, 6 used +* +LBFPRMO EQU STRTLABL+X'4000' Long BFP rounding mode test results +* ..Room for 16, 4 used. +LBFPRMOF EQU STRTLABL+X'4500' Long BFP rounding mode FPCR results +* ..Room for 16, 4 used. +* ..next location starts at X'4800' +* +XBFPNFOT EQU STRTLABL+X'5000' Integer ext'd non-finite BFP results +* ..room for 64 tests, 64 used +XBFPNFFL EQU STRTLABL+X'5800' FPCR flags and DXC from ext'd BFP +* ..room for 64 tests, 64 used +* +XBFPOUT EQU STRTLABL+X'5C00' Extended BFP finite results +* ..room for 16 tests, 6 used +XBFPFLGS EQU STRTLABL+X'5E00' FPCR flags and DXC from ext'd BFP +* ..room for 16 tests, 6 used +* +XBFPRMO EQU STRTLABL+X'6000' Ext'd BFP rounding mode test results +* ..Room for 16, 4 used. +XBFPRMOF EQU STRTLABL+X'6A00' Ext'd BFP rounding mode FPCR results +* ..Room for 16, 4 used. +* ..next location starts at X'6D00' +* +ENDLABL EQU STRTLABL+X'6D00' + PADCSECT ENDLABL + END diff --git a/tests/bfp-014-divide.core b/tests/bfp-014-divide.core new file mode 100644 index 000000000..c8e9c20e3 Binary files /dev/null and b/tests/bfp-014-divide.core differ diff --git a/tests/bfp-014-divide.list b/tests/bfp-014-divide.list new file mode 100644 index 000000000..559da8360 --- /dev/null +++ b/tests/bfp-014-divide.list @@ -0,0 +1,1560 @@ +ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 1 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 2 *********************************************************************** + 3 * + 4 *Testcase IEEE DIVIDE + 5 * Test case capability includes IEEE exceptions trappable and + 6 * otherwise. Test results, FPCR flags, and any DXC are saved for all + 7 * tests. + 8 * + 9 *********************************************************************** + + + 11 *********************************************************************** + 12 * + 13 * Tests the following three conversion instructions + 14 * DIVIDE (short BFP, RRE) + 15 * DIVIDE (long BFP, RRE) + 16 * DIVIDE (extended BFP, RRE) + 17 * DIVIDE (short BFP, RXE) + 18 * DIVIDE (long BFP, RXE) + 19 * + 20 * Test data is compiled into this program. The test script that runs + 21 * this program can provide alternative test data through Hercules R + 22 * commands. + 23 * + 24 * Test Case Order + 25 * 1) Short BFP basic tests, including traps and NaN propagation + 26 * 2) Short BFP finite number tests, incl. traps and scaling + 27 * 3) Short BFP FPC-controlled rounding mode exhaustive tests + 28 * 4) Long BFP basic tests, including traps and NaN propagation + 29 * 5) Long BFP finite number tests, incl. traps and scaling + 30 * 6) Long BFP FPC-controlled rounding mode exhaustive tests + 31 * 7) Extended BFP basic tests, including traps and NaN propagation + 32 * 8) Extended BFP finite number tests, incl. traps and scaling + 33 * 9) Extended BFP FPC-controlled rounding mode exhaustive tests + 34 * + 35 * Three input test sets are provided each for short, long, and + 36 * extended BFP inputs. Test values are the same for each precision + 37 * for most tests. Overflow and underflow each require precision- + 38 * dependent test values. + 39 * + 40 * Also tests the following floating point support instructions + 41 * LOAD (Short) + 42 * LOAD (Long) + 43 * LFPC (Load Floating Point Control Register) + 44 * SRNMB (Set BFP Rounding Mode 3-bit) + 45 * STORE (Short) + 46 * STORE (Long) + 47 * STFPC (Store Floating Point Control Register) + 48 * + 49 *********************************************************************** + + + 51 MACRO + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 2 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 52 PADCSECT &ENDLABL + 53 .* + 54 .* Macro to pad the CSECT to include result data areas if this test + 55 .* program is not being assembled using asma. asma generates a core + 56 .* image that is loaded by the loadcore command, and because the + 57 .* core image is a binary stored in Github, it makes sense to make + 58 .* this small effort to keep the core image small. + 59 .* + 60 AIF (D'&ENDLABL).GOODPAD + 61 MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + 62 MNOTE *,'No CSECT padding performed' + 63 MEXIT + 64 .* + 65 .GOODPAD ANOP Label valid. See if we're on asma + 66 AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + 67 ORG &ENDLABL-1 Not ASMA. Pad CSECT + 68 MEXIT + 69 .* + 70 .NOPAD ANOP + 71 MNOTE *,'asma detected; no CSECT padding performed' + 72 MEND + 73 * + 74 * Note: for compatibility with the z/CMS test rig, do not change + 75 * or use R11, R14, or R15. Everything else is fair game. + 76 * + 0000000000000000 0000000000000A9F 77 BFPDIV START 0 + 0000000000000000 0000000000000001 78 STRTLABL EQU * + 0000000000000000 0000000000000001 79 R0 EQU 0 Work register for cc extraction + 0000000000000001 0000000000000001 80 R1 EQU 1 + 0000000000000002 0000000000000001 81 R2 EQU 2 Holds count of test input values + 0000000000000003 0000000000000001 82 R3 EQU 3 Points to next test input value(s) + 0000000000000004 0000000000000001 83 R4 EQU 4 Rounding tests inner loop control + 0000000000000005 0000000000000001 84 R5 EQU 5 Rounding tests outer loop control + 0000000000000006 0000000000000001 85 R6 EQU 6 Rounding tests top of inner loop + 0000000000000007 0000000000000001 86 R7 EQU 7 Pointer to next result value(s) + 0000000000000008 0000000000000001 87 R8 EQU 8 Pointer to next FPCR result + 0000000000000009 0000000000000001 88 R9 EQU 9 Rounding tests top of outer loop + 000000000000000A 0000000000000001 89 R10 EQU 10 Pointer to test address list + 000000000000000B 0000000000000001 90 R11 EQU 11 **Reserved for z/CMS test rig + 000000000000000C 0000000000000001 91 R12 EQU 12 Holds number of test cases in set + 000000000000000D 0000000000000001 92 R13 EQU 13 Mainline return address + 000000000000000E 0000000000000001 93 R14 EQU 14 **Return address for z/CMS test rig + 000000000000000F 0000000000000001 94 R15 EQU 15 **Base register on z/CMS or Hyperion + 95 * + 96 * Floating Point Register equates to keep the cross reference clean + 97 * + 0000000000000000 0000000000000001 98 FPR0 EQU 0 + 0000000000000001 0000000000000001 99 FPR1 EQU 1 + 0000000000000002 0000000000000001 100 FPR2 EQU 2 + 0000000000000003 0000000000000001 101 FPR3 EQU 3 + 0000000000000004 0000000000000001 102 FPR4 EQU 4 + 0000000000000005 0000000000000001 103 FPR5 EQU 5 + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 3 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 0000000000000006 0000000000000001 104 FPR6 EQU 6 + 0000000000000007 0000000000000001 105 FPR7 EQU 7 + 0000000000000008 0000000000000001 106 FPR8 EQU 8 + 0000000000000009 0000000000000001 107 FPR9 EQU 9 + 000000000000000A 0000000000000001 108 FPR10 EQU 10 + 000000000000000B 0000000000000001 109 FPR11 EQU 11 + 000000000000000C 0000000000000001 110 FPR12 EQU 12 + 000000000000000D 0000000000000001 111 FPR13 EQU 13 + 000000000000000E 0000000000000001 112 FPR14 EQU 14 + 000000000000000F 0000000000000001 113 FPR15 EQU 15 + 114 * +0000000000000000 0000000000000000 115 USING *,R15 + 116 * + 117 * Above works on real iron (R15=0 after sysclear) + 118 * and in z/CMS (R15 points to start of load module) + 119 * + + + 121 *********************************************************************** + 122 * + 123 * Low core definitions, Restart PSW, and Program Check Routine. + 124 * + 125 *********************************************************************** + + +0000000000000000 0000000000000000 000000000000008E 127 ORG STRTLABL+X'8E' Program check interrution code +000000000000008E 0000 128 PCINTCD DS H + 129 * + 0000000000000150 0000000000000001 130 PCOLDPSW EQU STRTLABL+X'150' z/Arch Program check old PSW + 131 * +0000000000000090 0000000000000090 00000000000001A0 132 ORG STRTLABL+X'1A0' z/Arch Restart PSW +00000000000001A0 00000001 80000000 133 DC X'0000000180000000',AD(START) + 134 * +00000000000001B0 00000000000001B0 00000000000001D0 135 ORG STRTLABL+X'1D0' z/Arch Program check old PSW +00000000000001D0 00000000 00000000 136 DC X'0000000000000000',AD(PROGCHK) + 137 * + 138 * Program check routine. If Data Exception, continue execution at + 139 * the instruction following the program check. Otherwise, hard wait. + 140 * No need to collect data. All interesting DXC stuff is captured + 141 * in the FPCR. + 142 * +00000000000001E0 00000000000001E0 0000000000000200 143 ORG STRTLABL+X'200' +0000000000000200 144 PROGCHK DS 0H Program check occured... +0000000000000200 9507 F08F 000000000000008F 145 CLI PCINTCD+1,X'07' Data Exception? +0000000000000204 A774 0004 000000000000020C 146 JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) +0000000000000208 B2B2 F150 0000000000000150 147 LPSWE PCOLDPSW ..yes, resume program execution +000000000000020C 148 PCNOTDTA DS 0H +000000000000020C 12EE 149 LTR R14,R14 Return address provided? +000000000000020E 077E 150 BNZR R14 Yes, return to z/CMS test rig. +0000000000000210 B2B2 F280 0000000000000280 151 LPSWE HARDWAIT Not data exception, enter disabled wait + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 4 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 153 *********************************************************************** + 154 * + 155 * Main program. Enable Advanced Floating Point, process test cases. + 156 * + 157 *********************************************************************** + + +0000000000000214 159 START DS 0H +0000000000000214 B600 F290 0000000000000290 160 STCTL R0,R0,CTLR0 Store CR0 to enable AFP +0000000000000218 9604 F291 0000000000000291 161 OI CTLR0+1,X'04' Turn on AFP bit +000000000000021C B700 F290 0000000000000290 162 LCTL R0,R0,CTLR0 Reload updated CR0 + 163 * +0000000000000220 41A0 F300 0000000000000300 164 LA R10,SHORTNF Point to short BFP non-finite inputs +0000000000000224 4DD0 F390 0000000000000390 165 BAS R13,SBFPNF Divide short BFP non-finites +0000000000000228 41A0 F310 0000000000000310 166 LA R10,SHORTF Point to short BFP finite inputs +000000000000022C 4DD0 F41A 000000000000041A 167 BAS R13,SBFPF Divide short BFP finites +0000000000000230 41A0 F320 0000000000000320 168 LA R10,RMSHORTS Point to short BFP rounding mode tests +0000000000000234 4DD0 F490 0000000000000490 169 BAS R13,SBFPRM Divide short BFP for rounding tests + 170 * +0000000000000238 41A0 F330 0000000000000330 171 LA R10,LONGNF Point to long BFP non-finite inputs +000000000000023C 4DD0 F4FA 00000000000004FA 172 BAS R13,LBFPNF Divide long BFP non-finites +0000000000000240 41A0 F340 0000000000000340 173 LA R10,LONGF Point to long BFP finite inputs +0000000000000244 4DD0 F580 0000000000000580 174 BAS R13,LBFPF Divide long BFP finites +0000000000000248 41A0 F350 0000000000000350 175 LA R10,RMLONGS Point to long BFP rounding mode tests +000000000000024C 4DD0 F5F6 00000000000005F6 176 BAS R13,LBFPRM Divide long BFP for rounding tests + 177 * +0000000000000250 41A0 F360 0000000000000360 178 LA R10,XTNDNF Point to extended BFP non-finite inputs +0000000000000254 4DD0 F65C 000000000000065C 179 BAS R13,XBFPNF Divide extended BFP non-finites +0000000000000258 41A0 F370 0000000000000370 180 LA R10,XTNDF Point to ext'd BFP finite inputs +000000000000025C 4DD0 F6CE 00000000000006CE 181 BAS R13,XBFPF Divide ext'd BFP finites +0000000000000260 41A0 F380 0000000000000380 182 LA R10,RMXTNDS Point to ext'd BFP rounding mode tests +0000000000000264 4DD0 F72C 000000000000072C 183 BAS R13,XBFPRM Divide ext'd BFP for rounding tests + 184 * +0000000000000268 12EE 185 LTR R14,R14 Return address provided? +000000000000026A 077E 186 BNZR R14 ..Yes, return to z/CMS test rig. +000000000000026C B2B2 F270 0000000000000270 187 LPSWE WAITPSW All done + 188 * +0000000000000270 189 DS 0D Ensure correct alignment for psw +0000000000000270 00020000 00000000 190 WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +0000000000000280 00020000 00000000 191 HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end + 192 * +0000000000000290 00000000 193 CTLR0 DS F +0000000000000294 00000000 194 FPCREGNT DC X'00000000' FPCR, trap no IEEE exceptions, zero flags +0000000000000298 F8000000 195 FPCREGTR DC X'F8000000' FPCR, trap all IEEE exceptions, zero flags + 196 * + 197 * Input values parameter list, four fullwords for each test data set + 198 * 1) Count, + 199 * 2) Address of inputs, + 200 * 3) Address to place results, and + 201 * 4) Address to place DXC/Flags/cc values. + 202 * +000000000000029C 000000000000029C 0000000000000300 203 ORG STRTLABL+X'300' Enable run-time replacement + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 5 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000300 204 SHORTNF DS 0F Input pairs for short BFP non-finite tests +0000000000000300 00000008 205 DC A(SBFPNFCT) +0000000000000304 0000078C 206 DC A(SBFPNFIN) +0000000000000308 00001000 207 DC A(SBFPNFOT) +000000000000030C 00001400 208 DC A(SBFPNFFL) + 209 * +0000000000000310 210 SHORTF DS 0F Input pairs for short BFP finite tests +0000000000000310 00000006 211 DC A(SBFPCT) +0000000000000314 000007AC 212 DC A(SBFPIN) +0000000000000318 00001800 213 DC A(SBFPOUT) +000000000000031C 00001900 214 DC A(SBFPFLGS) + 215 * +0000000000000320 216 RMSHORTS DS 0F Input pairs for short BFP rounding testing +0000000000000320 00000004 217 DC A(SBFPRMCT) +0000000000000324 000007DC 218 DC A(SBFPINRM) +0000000000000328 00001A00 219 DC A(SBFPRMO) +000000000000032C 00001D00 220 DC A(SBFPRMOF) + 221 * +0000000000000330 222 LONGNF DS 0F Input pairs for long BFP non-finite testing +0000000000000330 00000008 223 DC A(LBFPNFCT) +0000000000000334 000007FC 224 DC A(LBFPNFIN) +0000000000000338 00003000 225 DC A(LBFPNFOT) +000000000000033C 00003800 226 DC A(LBFPNFFL) + 227 * +0000000000000340 228 LONGF DS 0F Input pairs for long BFP finite testing +0000000000000340 00000006 229 DC A(LBFPCT) +0000000000000344 00000840 230 DC A(LBFPIN) +0000000000000348 00003C00 231 DC A(LBFPOUT) +000000000000034C 00003E00 232 DC A(LBFPFLGS) + 233 * +0000000000000350 234 RMLONGS DS 0F Input pairs for long BFP rounding testing +0000000000000350 00000004 235 DC A(LBFPRMCT) +0000000000000354 000008A0 236 DC A(LBFPINRM) +0000000000000358 00004000 237 DC A(LBFPRMO) +000000000000035C 00004500 238 DC A(LBFPRMOF) + 239 * +0000000000000360 240 XTNDNF DS 0F Inputs for ext'd BFP non-finite testing +0000000000000360 00000008 241 DC A(XBFPNFCT) +0000000000000364 000008E0 242 DC A(XBFPNFIN) +0000000000000368 00005000 243 DC A(XBFPNFOT) +000000000000036C 00005800 244 DC A(XBFPNFFL) + 245 * +0000000000000370 246 XTNDF DS 0F Inputs for ext'd BFP finite testing +0000000000000370 00000006 247 DC A(XBFPCT) +0000000000000374 00000960 248 DC A(XBFPIN) +0000000000000378 00005C00 249 DC A(XBFPOUT) +000000000000037C 00005E00 250 DC A(XBFPFLGS) + 251 * +0000000000000380 252 RMXTNDS DS 0F Inputs for ext'd BFP non-finite testing +0000000000000380 00000004 253 DC A(XBFPRMCT) +0000000000000384 00000A20 254 DC A(XBFPINRM) +0000000000000388 00006000 255 DC A(XBFPRMO) + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 6 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +000000000000038C 00006A00 256 DC A(XBFPRMOF) + 257 * + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 7 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 259 *********************************************************************** + 260 * + 261 * Perform Divide using provided short BFP inputs. This set of tests + 262 * checks NaN propagation, operations on values that are not finite + 263 * numbers, and other basic tests. This set generates results that can + 264 * be validated against Figure 19-20 on page 19-27 of SA22-7832-10. + 265 * + 266 * Four results are generated for each input: one RRE with all + 267 * exceptions non-trappable, a second RRE with all exceptions trappable, + 268 * a third RXE with all exceptions non-trappable, a fourth RXE with all + 269 * exceptions trappable, + 270 * + 271 * The quotient and FPCR are stored for each result. + 272 * + 273 *********************************************************************** + + +0000000000000390 275 SBFPNF DS 0H BFP Short non-finite values tests +0000000000000390 9823 A000 0000000000000000 276 LM R2,R3,0(R10) Get count and address of divide values +0000000000000394 9878 A008 0000000000000008 277 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000398 1222 278 LTR R2,R2 Any test cases? +000000000000039A 078D 279 BZR R13 ..No, return to caller +000000000000039C 0DC0 280 BASR R12,0 Set top of loop + 281 * +000000000000039E 9845 A000 0000000000000000 282 LM R4,R5,0(R10) Get count and start of divisor values + 283 * ..which are the same as the dividends +00000000000003A2 0D60 284 BASR R6,0 Set top of inner loop + 285 * +00000000000003A4 7880 3000 0000000000000000 286 LE FPR8,0(,R3) Get short BFP dividend +00000000000003A8 7810 5000 0000000000000000 287 LE FPR1,0(,R5) Get short BFP divisor +00000000000003AC B29D F294 0000000000000294 288 LFPC FPCREGNT Set exceptions non-trappable +00000000000003B0 B30D 0081 289 DEBR FPR8,FPR1 Divide FPR0/FPR1 RRE +00000000000003B4 7080 7000 0000000000000000 290 STE FPR8,0(,R7) Store short BFP quotient +00000000000003B8 B29C 8000 0000000000000000 291 STFPC 0(R8) Store resulting FPCR flags and DXC + 292 * +00000000000003BC 7880 3000 0000000000000000 293 LE FPR8,0(,R3) Get short BFP dividend +00000000000003C0 7810 5000 0000000000000000 294 LE FPR1,0(,R5) Get short BFP divisor +00000000000003C4 B29D F298 0000000000000298 295 LFPC FPCREGTR Set exceptions trappable +00000000000003C8 B30D 0081 296 DEBR FPR8,FPR1 Divide FPR0/FPR1 RRE +00000000000003CC 7080 7004 0000000000000004 297 STE FPR8,4(,R7) Store short BFP quotient +00000000000003D0 B29C 8004 0000000000000004 298 STFPC 4(R8) Store resulting FPCR flags and DXC + 299 * +00000000000003D4 7880 3000 0000000000000000 300 LE FPR8,0(,R3) Get short BFP dividend +00000000000003D8 7810 5000 0000000000000000 301 LE FPR1,0(,R5) Get short BFP divisor +00000000000003DC B29D F294 0000000000000294 302 LFPC FPCREGNT Set exceptions non-trappable +00000000000003E0 ED80 5000 000D 0000000000000000 303 DEB FPR8,0(,R5) Divide FPR0/FPR1 RXE +00000000000003E6 7080 7008 0000000000000008 304 STE FPR8,8(,R7) Store short BFP quotient +00000000000003EA B29C 8008 0000000000000008 305 STFPC 8(R8) Store resulting FPCR flags and DXC + 306 * +00000000000003EE 7880 3000 0000000000000000 307 LE FPR8,0(,R3) Get short BFP dividend +00000000000003F2 B29D F298 0000000000000298 308 LFPC FPCREGTR Set exceptions trappable +00000000000003F6 ED80 5000 000D 0000000000000000 309 DEB FPR8,0(,R5) Divide FPR0/FPR1 RXE + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 8 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000003FC 7080 700C 000000000000000C 310 STE FPR8,12(,R7) Store short BFP quotient +0000000000000400 B29C 800C 000000000000000C 311 STFPC 12(R8) Store resulting FPCR flags and DXC + 312 * +0000000000000404 4150 5004 0000000000000004 313 LA R5,4(,R5) Point to next divisor value +0000000000000408 4170 7010 0000000000000010 314 LA R7,16(,R7) Point to next Divide result area +000000000000040C 4180 8010 0000000000000010 315 LA R8,16(,R8) Point to next Divide FPCR area +0000000000000410 0646 316 BCTR R4,R6 Loop through right-hand values + 317 * +0000000000000412 4130 3004 0000000000000004 318 LA R3,4(,R3) Point to next input dividend +0000000000000416 062C 319 BCTR R2,R12 Convert next input value. +0000000000000418 07FD 320 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 9 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 322 *********************************************************************** + 323 * + 324 * Perform Divide using provided short BFP input pairs. This set of + 325 * tests triggers IEEE exceptions Overflow, Underflow, and Inexact and + 326 * collects results when the exceptions do not result in a trap and when + 327 * they do. + 328 * + 329 * Four results are generated for each input: one RRE with all + 330 * exceptions non-trappable, a second RRE with all exceptions trappable, + 331 * a third RXE with all exceptions non-trappable, a fourth RXE with all + 332 * exceptions trappable, + 333 * + 334 * The quotient and FPCR are stored for each result. + 335 * + 336 *********************************************************************** + + +000000000000041A 9823 A000 0000000000000000 338 SBFPF LM R2,R3,0(R10) Get count and address of test input values +000000000000041E 9878 A008 0000000000000008 339 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000422 1222 340 LTR R2,R2 Any test cases? +0000000000000424 078D 341 BZR R13 ..No, return to caller +0000000000000426 0DC0 342 BASR R12,0 Set top of loop + 343 * +0000000000000428 B29D F294 0000000000000294 344 LFPC FPCREGNT Set exceptions non-trappable +000000000000042C 7880 3000 0000000000000000 345 LE FPR8,0(,R3) Get short BFP dividend +0000000000000430 7810 3004 0000000000000004 346 LE FPR1,4(,R3) Get short BFP divisor +0000000000000434 B30D 0081 347 DEBR FPR8,FPR1 Divide FPR8/FPR1 RRE non-trappable +0000000000000438 7080 7000 0000000000000000 348 STE FPR8,0(,R7) Store short BFP quotient +000000000000043C B29C 8000 0000000000000000 349 STFPC 0(R8) Store resulting FPCR flags and DXC + 350 * +0000000000000440 B29D F298 0000000000000298 351 LFPC FPCREGTR Set exceptions trappable +0000000000000444 7880 3000 0000000000000000 352 LE FPR8,0(,R3) Reload short BFP dividend + 353 * ..divisor is still in FPR1 +0000000000000448 B30D 0081 354 DEBR FPR8,FPR1 Divide FPR8/FPR1 RRE trappable +000000000000044C 7080 7004 0000000000000004 355 STE FPR8,4(,R7) Store short BFP quotient +0000000000000450 B29C 8004 0000000000000004 356 STFPC 4(R8) Store resulting FPCR flags and DXC + 357 * +0000000000000454 B29D F294 0000000000000294 358 LFPC FPCREGNT Set exceptions non-trappable +0000000000000458 7880 3000 0000000000000000 359 LE FPR8,0(,R3) Reload short BFP dividend +000000000000045C ED80 3004 000D 0000000000000004 360 DEB FPR8,4(,R3) Divide FPR8 by divisor RXE non-trappable +0000000000000462 7080 7008 0000000000000008 361 STE FPR8,8(,R7) Store short BFP quotient +0000000000000466 B29C 8008 0000000000000008 362 STFPC 8(R8) Store resulting FPCR flags and DXC + 363 * +000000000000046A B29D F298 0000000000000298 364 LFPC FPCREGTR Set exceptions trappable +000000000000046E 7880 3000 0000000000000000 365 LE FPR8,0(,R3) Reload short BFP dividend +0000000000000472 ED80 3004 000D 0000000000000004 366 DEB FPR8,4(,R3) Divide FPR8 by divisor RXE trappable +0000000000000478 7080 700C 000000000000000C 367 STE FPR8,12(,R7) Store short BFP quotient +000000000000047C B29C 800C 000000000000000C 368 STFPC 12(R8) Store resulting FPCR flags and DXC + 369 * +0000000000000480 4130 3008 0000000000000008 370 LA R3,8(,R3) Point to next input value pair +0000000000000484 4170 7010 0000000000000010 371 LA R7,16(,R7) Point to next quotient pair +0000000000000488 4180 8010 0000000000000010 372 LA R8,16(,R8) Point to next FPCR result area + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 10 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +000000000000048C 062C 373 BCTR R2,R12 Convert next input value. +000000000000048E 07FD 374 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 11 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 376 *********************************************************************** + 377 * + 378 * Perform Divide using provided short BFP input pairs. This set of + 379 * tests exhaustively tests all rounding modes available for Divide. + 380 * The rounding mode can only be specified in the FPC. + 381 * + 382 * All five FPC rounding modes are tested because the preceeding tests, + 383 * using rounding mode RNTE, do not often create results that require + 384 * rounding. + 385 * + 386 * Two results are generated for each input and rounding mode: one RRE + 387 * and one RXE. Traps are disabled for all rounding mode tests. + 388 * + 389 * The quotient and FPCR contents are stored for each test. + 390 * + 391 *********************************************************************** + + +0000000000000490 9823 A000 0000000000000000 393 SBFPRM LM R2,R3,0(R10) Get count and address of test input values +0000000000000494 9878 A008 0000000000000008 394 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000498 1222 395 LTR R2,R2 Any test cases? +000000000000049A 078D 396 BZR R13 ..No, return to caller +000000000000049C 1711 397 XR R1,R1 Zero register 1 for use in IC/STC/indexing +000000000000049E 0DC0 398 BASR R12,0 Set top of test case loop + 399 +00000000000004A0 4150 0005 0000000000000005 400 LA R5,FPCMCT Get count of FPC modes to be tested +00000000000004A4 0D90 401 BASR R9,0 Set top of rounding mode outer loop + 402 * +00000000000004A6 4315 F783 0000000000000783 403 IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode + 404 * +00000000000004AA B29D F294 0000000000000294 405 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000004AE B2B8 1000 0000000000000000 406 SRNMB 0(R1) Set FPC Rounding Mode +00000000000004B2 7880 3000 0000000000000000 407 LE FPR8,0(,R3) Get short BFP dividend +00000000000004B6 7810 3004 0000000000000004 408 LE FPR1,4(,R3) Get short BFP divisor +00000000000004BA B30D 0081 409 DEBR FPR8,FPR1 Divide RRE FPR8/FPR1 non-trappable +00000000000004BE 7080 7000 0000000000000000 410 STE FPR8,0(,R7) Store short BFP quotient +00000000000004C2 B29C 8000 0000000000000000 411 STFPC 0(R8) Store resulting FPCR flags and DXC + 412 * +00000000000004C6 B29D F294 0000000000000294 413 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000004CA B2B8 1000 0000000000000000 414 SRNMB 0(R1) Set FPC Rounding Mode +00000000000004CE 7880 3000 0000000000000000 415 LE FPR8,0(,R3) Get short BFP dividend +00000000000004D2 ED80 3004 000D 0000000000000004 416 DEB FPR8,4(,R3) Divide RXE FPR8 by divisor non-trappable +00000000000004D8 7080 7004 0000000000000004 417 STE FPR8,4(,R7) Store short BFP quotient +00000000000004DC B29C 8004 0000000000000004 418 STFPC 4(R8) Store resulting FPCR flags and DXC + 419 * +00000000000004E0 4170 7008 0000000000000008 420 LA R7,8(,R7) Point to next quotient result set +00000000000004E4 4180 8008 0000000000000008 421 LA R8,8(,R8) Point to next FPCR result area + 422 * +00000000000004E8 0659 423 BCTR R5,R9 Iterate to next FPC mode + 424 * + 425 * End of FPC modes to be tested. Advance to next test case. + 426 * + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 12 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000004EA 4130 3008 0000000000000008 427 LA R3,8(,R3) Point to next input value pair +00000000000004EE 4170 7008 0000000000000008 428 LA R7,8(,R7) Skip to start of next result area +00000000000004F2 4180 8008 0000000000000008 429 LA R8,8(,R8) Skip to start of next FPCR result area +00000000000004F6 062C 430 BCTR R2,R12 Divide next input value lots of times + 431 * +00000000000004F8 07FD 432 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 13 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 434 *********************************************************************** + 435 * + 436 * Perform Divide using provided long BFP inputs. This set of tests + 437 * checks NaN propagation, operations on values that are not finite + 438 * numbers, and other basic tests. This set generates results that can + 439 * be validated against Figure 19-20 on page 19-27 of SA22-7832-10. + 440 * + 441 * Four results are generated for each input: one RRE with all + 442 * exceptions non-trappable, a second RRE with all exceptions trappable, + 443 * a third RXE with all exceptions non-trappable, a fourth RXE with all + 444 * exceptions trappable, + 445 * + 446 * The quotient and FPCR are stored for each result. + 447 * + 448 *********************************************************************** + + +00000000000004FA 450 LBFPNF DS 0H BFP long non-finite values tests +00000000000004FA 9823 A000 0000000000000000 451 LM R2,R3,0(R10) Get count and address of dividend values +00000000000004FE 9878 A008 0000000000000008 452 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000502 1222 453 LTR R2,R2 Any test cases? +0000000000000504 078D 454 BZR R13 ..No, return to caller +0000000000000506 0DC0 455 BASR R12,0 Set top of loop + 456 * +0000000000000508 9845 A000 0000000000000000 457 LM R4,R5,0(R10) Get count and start of divisor values + 458 * ..which are the same as the dividends +000000000000050C 0D60 459 BASR R6,0 Set top of inner loop + 460 * +000000000000050E 6880 3000 0000000000000000 461 LD FPR8,0(,R3) Get long BFP dividend +0000000000000512 6810 5000 0000000000000000 462 LD FPR1,0(,R5) Get long BFP divisor +0000000000000516 B29D F294 0000000000000294 463 LFPC FPCREGNT Set exceptions non-trappable +000000000000051A B31D 0081 464 DDBR FPR8,FPR1 Divide FPR0/FPR1 RRE +000000000000051E 6080 7000 0000000000000000 465 STD FPR8,0(,R7) Store long BFP quotient +0000000000000522 B29C 8000 0000000000000000 466 STFPC 0(R8) Store resulting FPCR flags and DXC + 467 * +0000000000000526 6880 3000 0000000000000000 468 LD FPR8,0(,R3) Get long BFP dividend +000000000000052A 6810 5000 0000000000000000 469 LD FPR1,0(,R5) Get long BFP divisor +000000000000052E B29D F298 0000000000000298 470 LFPC FPCREGTR Set exceptions trappable +0000000000000532 B31D 0081 471 DDBR FPR8,FPR1 Divide FPR0/FPR1 RRE +0000000000000536 6080 7008 0000000000000008 472 STD FPR8,8(,R7) Store long BFP remainder +000000000000053A B29C 8004 0000000000000004 473 STFPC 4(R8) Store resulting FPCR flags and DXC + 474 * +000000000000053E 6880 3000 0000000000000000 475 LD FPR8,0(,R3) Get long BFP dividend +0000000000000542 B29D F294 0000000000000294 476 LFPC FPCREGNT Set exceptions non-trappable +0000000000000546 ED80 5000 001D 0000000000000000 477 DDB FPR8,0(,R5) Divide FPR0/FPR1 RXE +000000000000054C 6080 7010 0000000000000010 478 STD FPR8,16(,R7) Store long BFP quotient +0000000000000550 B29C 8008 0000000000000008 479 STFPC 8(R8) Store resulting FPCR flags and DXC + 480 * +0000000000000554 6880 3000 0000000000000000 481 LD FPR8,0(,R3) Get long BFP dividend +0000000000000558 B29D F298 0000000000000298 482 LFPC FPCREGTR Set exceptions trappable +000000000000055C ED80 5000 001D 0000000000000000 483 DDB FPR8,0(,R5) Divide FPR0/FPR1 RXE +0000000000000562 6080 7018 0000000000000018 484 STD FPR8,24(,R7) Store long BFP remainder + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 14 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000566 B29C 800C 000000000000000C 485 STFPC 12(R8) Store resulting FPCR flags and DXC + 486 * +000000000000056A 4150 5008 0000000000000008 487 LA R5,8(,R5) Point to next divisor value +000000000000056E 4170 7020 0000000000000020 488 LA R7,32(,R7) Point to next Divide result area +0000000000000572 4180 8010 0000000000000010 489 LA R8,16(,R8) Point to next Divide FPCR area +0000000000000576 0646 490 BCTR R4,R6 Loop through right-hand values + 491 * +0000000000000578 4130 3008 0000000000000008 492 LA R3,8(,R3) Point to next dividend value +000000000000057C 062C 493 BCTR R2,R12 Divide until all cases tested +000000000000057E 07FD 494 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 15 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 496 *********************************************************************** + 497 * + 498 * Perform Divide using provided long BFP input pairs. This set of + 499 * tests triggers IEEE exceptions Overflow, Underflow, and Inexact and + 500 * collects results when the exceptions do not result in a trap and when + 501 * they do. + 502 * + 503 * Four results are generated for each input: one RRE with all + 504 * exceptions non-trappable, a second RRE with all exceptions trappable, + 505 * a third RXE with all exceptions non-trappable, a fourth RXE with all + 506 * exceptions trappable, + 507 * + 508 * The result and FPCR are stored for each result. + 509 * + 510 *********************************************************************** + + +0000000000000580 9823 A000 0000000000000000 512 LBFPF LM R2,R3,0(R10) Get count and address of test input values +0000000000000584 9878 A008 0000000000000008 513 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000588 1222 514 LTR R2,R2 Any test cases? +000000000000058A 078D 515 BZR R13 ..No, return to caller +000000000000058C 0DC0 516 BASR R12,0 Set top of loop + 517 * +000000000000058E B29D F294 0000000000000294 518 LFPC FPCREGNT Set exceptions non-trappable +0000000000000592 6880 3000 0000000000000000 519 LD FPR8,0(,R3) Get short BFP dividend +0000000000000596 6810 3008 0000000000000008 520 LD FPR1,8(,R3) Get short BFP divisor +000000000000059A B31D 0081 521 DDBR FPR8,FPR1 Divide FPR8/FPR1 RRE non-trappable +000000000000059E 6080 7000 0000000000000000 522 STD FPR8,0(,R7) Store short BFP quotient +00000000000005A2 B29C 8000 0000000000000000 523 STFPC 0(R8) Store resulting FPCR flags and DXC + 524 * +00000000000005A6 B29D F298 0000000000000298 525 LFPC FPCREGTR Set exceptions trappable +00000000000005AA 6880 3000 0000000000000000 526 LD FPR8,0(,R3) Reload short BFP dividend + 527 * ..divisor is still in FPR1 +00000000000005AE B31D 0081 528 DDBR FPR8,FPR1 Divide FPR8/FPR1 RRE trappable +00000000000005B2 6080 7008 0000000000000008 529 STD FPR8,8(,R7) Store short BFP quotient +00000000000005B6 B29C 8004 0000000000000004 530 STFPC 4(R8) Store resulting FPCR flags and DXC + 531 * +00000000000005BA B29D F294 0000000000000294 532 LFPC FPCREGNT Set exceptions non-trappable +00000000000005BE 6880 3000 0000000000000000 533 LD FPR8,0(,R3) Reload short BFP dividend +00000000000005C2 ED80 3008 001D 0000000000000008 534 DDB FPR8,8(,R3) Divide FPR8/FPR1 RXE non-trappable +00000000000005C8 6080 7010 0000000000000010 535 STD FPR8,16(,R7) Store short BFP quotient +00000000000005CC B29C 8008 0000000000000008 536 STFPC 8(R8) Store resulting FPCR flags and DXC + 537 * +00000000000005D0 B29D F298 0000000000000298 538 LFPC FPCREGTR Set exceptions trappable +00000000000005D4 6880 3000 0000000000000000 539 LD FPR8,0(,R3) Reload short BFP dividend +00000000000005D8 ED80 3008 001D 0000000000000008 540 DDB FPR8,8(,R3) Divide FPR8/FPR1 RXE trappable +00000000000005DE 6080 7018 0000000000000018 541 STD FPR8,24(,R7) Store short BFP quotient +00000000000005E2 B29C 800C 000000000000000C 542 STFPC 12(R8) Store resulting FPCR flags and DXC + 543 * +00000000000005E6 4130 3010 0000000000000010 544 LA R3,16(,R3) Point to next input value pair +00000000000005EA 4170 7020 0000000000000020 545 LA R7,32(,R7) Point to next quotent result pair +00000000000005EE 4180 8010 0000000000000010 546 LA R8,16(,R8) Point to next FPCR result area + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 16 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000005F2 062C 547 BCTR R2,R12 Convert next input value. +00000000000005F4 07FD 548 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 17 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 550 *********************************************************************** + 551 * + 552 * Perform Divide using provided long BFP input pairs. This set of + 553 * tests exhaustively tests all rounding modes available for Divide. + 554 * The rounding mode can only be specified in the FPC. + 555 * + 556 * All five FPC rounding modes are tested because the preceeding tests, + 557 * using rounding mode RNTE, do not often create results that require + 558 * rounding. + 559 * + 560 * Two results are generated for each input and rounding mode: one RRE + 561 * and one RXE. Traps are disabled for all rounding mode tests. + 562 * + 563 * The quotient and FPCR contents are stored for each test. + 564 * + 565 *********************************************************************** + + +00000000000005F6 9823 A000 0000000000000000 567 LBFPRM LM R2,R3,0(R10) Get count and address of test input values +00000000000005FA 9878 A008 0000000000000008 568 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000005FE 1222 569 LTR R2,R2 Any test cases? +0000000000000600 078D 570 BZR R13 ..No, return to caller +0000000000000602 1711 571 XR R1,R1 Zero register 1 for use in IC/STC/indexing +0000000000000604 0DC0 572 BASR R12,0 Set top of test case loop + 573 +0000000000000606 4150 0005 0000000000000005 574 LA R5,FPCMCT Get count of FPC modes to be tested +000000000000060A 0D90 575 BASR R9,0 Set top of rounding mode loop + 576 * +000000000000060C 4315 F783 0000000000000783 577 IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode + 578 * +0000000000000610 B29D F294 0000000000000294 579 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000614 B2B8 1000 0000000000000000 580 SRNMB 0(R1) Set FPC Rounding Mode +0000000000000618 6880 3000 0000000000000000 581 LD FPR8,0(,R3) Get long BFP dividend +000000000000061C 6810 3008 0000000000000008 582 LD FPR1,8(,R3) Get long BFP divisor +0000000000000620 B31D 0081 583 DDBR FPR8,FPR1 Divide RRE FPR8/FPR1 non-trappable +0000000000000624 6080 7000 0000000000000000 584 STD FPR8,0(,R7) Store long BFP quotient +0000000000000628 B29C 8000 0000000000000000 585 STFPC 0(R8) Store resulting FPCR flags and DXC + 586 * +000000000000062C B29D F294 0000000000000294 587 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000630 B2B8 1000 0000000000000000 588 SRNMB 0(R1) Set FPC Rounding Mode +0000000000000634 6880 3000 0000000000000000 589 LD FPR8,0(,R3) Reload long BFP dividend +0000000000000638 ED80 3008 001D 0000000000000008 590 DDB FPR8,8(,R3) Divide RXE FPR8 by divisor non-trappable +000000000000063E 6080 7008 0000000000000008 591 STD FPR8,8(,R7) Store long BFP quotient +0000000000000642 B29C 8004 0000000000000004 592 STFPC 4(R8) Store resulting FPCR flags and DXC + 593 * +0000000000000646 4170 7010 0000000000000010 594 LA R7,16(,R7) Point to next quotient result set +000000000000064A 4180 8008 0000000000000008 595 LA R8,8(,R8) Point to next FPCR result area + 596 * +000000000000064E 0659 597 BCTR R5,R9 Iterate to next FPC mode + 598 * + 599 * End of FPC modes to be tested. Advance to next test case. + 600 * + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 18 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000650 4130 3010 0000000000000010 601 LA R3,16(,R3) Point to next input value pair +0000000000000654 4180 8008 0000000000000008 602 LA R8,8(,R8) Skip to start of next FPCR result area +0000000000000658 062C 603 BCTR R2,R12 Divide next input value lots of times + 604 * +000000000000065A 07FD 605 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 19 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 607 *********************************************************************** + 608 * + 609 * Perform Divide using provided extended BFP inputs. This set of tests + 610 * checks NaN propagation, operations on values that are not finite + 611 * numbers, and other basic tests. This set generates results that can + 612 * be validated against Figure 19-20 on page 19-27 of SA22-7832-10. + 613 * + 614 * Two results are generated for each input: one RRE with all + 615 * exceptions non-trappable, and a second RRE with all exceptions + 616 * trappable. Extended BFP Divide does not have an RXE format. + 617 * + 618 * The quotient and FPCR are stored for each result. + 619 * + 620 *********************************************************************** + + +000000000000065C 622 XBFPNF DS 0H BFP extended non-finite values tests +000000000000065C 9823 A000 0000000000000000 623 LM R2,R3,0(R10) Get count and address of dividend values +0000000000000660 9878 A008 0000000000000008 624 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000664 1222 625 LTR R2,R2 Any test cases? +0000000000000666 078D 626 BZR R13 ..No, return to caller +0000000000000668 0DC0 627 BASR R12,0 Set top of loop + 628 * +000000000000066A 9845 A000 0000000000000000 629 LM R4,R5,0(R10) Get count and start of divisor values + 630 * ..which are the same as the dividends +000000000000066E 0D60 631 BASR R6,0 Set top of inner loop + 632 * +0000000000000670 6880 3000 0000000000000000 633 LD FPR8,0(,R3) Get extended BFP dividend part 1 +0000000000000674 68A0 3008 0000000000000008 634 LD FPR10,8(,R3) Get extended BFP dividend part 2 +0000000000000678 6810 5000 0000000000000000 635 LD FPR1,0(,R5) Get extended BFP divisor part 1 +000000000000067C 6830 5008 0000000000000008 636 LD FPR3,8(,R5) Get extended BFP divisor part 2 +0000000000000680 B29D F294 0000000000000294 637 LFPC FPCREGNT Set exceptions non-trappable +0000000000000684 B34D 0081 638 DXBR FPR8,FPR1 Divide FPR0/FPR1 RRE +0000000000000688 6080 7000 0000000000000000 639 STD FPR8,0(,R7) Store extended BFP quotient part 1 +000000000000068C 60A0 7008 0000000000000008 640 STD FPR10,8(,R7) Store extended BFP quotient part 2 +0000000000000690 B29C 8000 0000000000000000 641 STFPC 0(R8) Store resulting FPCR flags and DXC + 642 * +0000000000000694 6880 3000 0000000000000000 643 LD FPR8,0(,R3) Get extended BFP dividend part 1 +0000000000000698 68A0 3008 0000000000000008 644 LD FPR10,8(,R3) Get extended BFP dividend part 2 +000000000000069C 6810 5000 0000000000000000 645 LD FPR1,0(,R5) Get extended BFP divisor part 1 +00000000000006A0 6830 5008 0000000000000008 646 LD FPR3,8(,R5) Get extended BFP divisor part 2 +00000000000006A4 B29D F298 0000000000000298 647 LFPC FPCREGTR Set exceptions trappable +00000000000006A8 B34D 0081 648 DXBR FPR8,FPR1 Divide FPR0/FPR1 RRE +00000000000006AC 6080 7010 0000000000000010 649 STD FPR8,16(,R7) Store extended BFP quotient part 1 +00000000000006B0 60A0 7018 0000000000000018 650 STD FPR10,24(,R7) Store extended BFP quotient part 2 +00000000000006B4 B29C 8004 0000000000000004 651 STFPC 4(R8) Store resulting FPCR flags and DXC + 652 * +00000000000006B8 4150 5010 0000000000000010 653 LA R5,16(,R5) Point to next divisor value +00000000000006BC 4170 7020 0000000000000020 654 LA R7,32(,R7) Point to next Divide result area +00000000000006C0 4180 8010 0000000000000010 655 LA R8,16(,R8) Point to next Divide FPCR area +00000000000006C4 0646 656 BCTR R4,R6 Loop through right-hand values + 657 * + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 20 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000006C6 4130 3010 0000000000000010 658 LA R3,16(,R3) Point to next dividend value +00000000000006CA 062C 659 BCTR R2,R12 Divide until all cases tested +00000000000006CC 07FD 660 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 21 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 662 *********************************************************************** + 663 * + 664 * Perform Divide using provided extended BFP input pairs. This set of + 665 * tests triggers IEEE exceptions Overflow, Underflow, and Inexact and + 666 * collects results when the exceptions do not result in a trap and when + 667 * they do. + 668 * + 669 * Two results are generated for each input: one RRE with all + 670 * exceptions non-trappable and a second RRE with all exceptions + 671 * trappable. There is no RXE format for Divide in extended precision. + 672 * + 673 * The result and FPCR are stored for each result. + 674 * + 675 *********************************************************************** + + +00000000000006CE 9823 A000 0000000000000000 677 XBFPF LM R2,R3,0(R10) Get count and address of test input values +00000000000006D2 9878 A008 0000000000000008 678 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000006D6 1222 679 LTR R2,R2 Any test cases? +00000000000006D8 078D 680 BZR R13 ..No, return to caller +00000000000006DA 0DC0 681 BASR R12,0 Set top of loop + 682 * +00000000000006DC B29D F294 0000000000000294 683 LFPC FPCREGNT Set exceptions non-trappable +00000000000006E0 68D0 3000 0000000000000000 684 LD FPR13,0(,R3) Get extended BFP dividend part 1 +00000000000006E4 68F0 3008 0000000000000008 685 LD FPR15,8(,R3) Get extended BFP dividend part 2 +00000000000006E8 6810 3010 0000000000000010 686 LD FPR1,16(,R3) Get extended BFP divisor part 1 +00000000000006EC 6830 3018 0000000000000018 687 LD FPR3,24(,R3) Get extended BFP divisor part 2 +00000000000006F0 B34D 00D1 688 DXBR FPR13,FPR1 Divide FPR8-10/FPR1-3 RRE non-trappable +00000000000006F4 60D0 7000 0000000000000000 689 STD FPR13,0(,R7) Store extended BFP quotient part 1 +00000000000006F8 60F0 7008 0000000000000008 690 STD FPR15,8(,R7) Store extended BFP quotient part 2 +00000000000006FC B29C 8000 0000000000000000 691 STFPC 0(R8) Store resulting FPCR flags and DXC + 692 * +0000000000000700 B29D F298 0000000000000298 693 LFPC FPCREGTR Set exceptions trappable +0000000000000704 68D0 3000 0000000000000000 694 LD FPR13,0(,R3) Reload extended BFP dividend part 1 +0000000000000708 68F0 3008 0000000000000008 695 LD FPR15,8(,R3) Reload extended BFP dividend part 2 + 696 * ..divisor is still in FPR1-FPR3 +000000000000070C B34D 00D1 697 DXBR FPR13,FPR1 Divide FPR13-15/FPR1-3 RRE trappable +0000000000000710 60D0 7010 0000000000000010 698 STD FPR13,16(,R7) Store extended BFP quotient part 1 +0000000000000714 60F0 7018 0000000000000018 699 STD FPR15,24(,R7) Store extended BFP quotient part 2 +0000000000000718 B29C 8004 0000000000000004 700 STFPC 4(R8) Store resulting FPCR flags and DXC + 701 * +000000000000071C 4130 3020 0000000000000020 702 LA R3,32(,R3) Point to next input value pair +0000000000000720 4170 7020 0000000000000020 703 LA R7,32(,R7) Point to next quotent result pair +0000000000000724 4180 8010 0000000000000010 704 LA R8,16(,R8) Point to next FPCR result area +0000000000000728 062C 705 BCTR R2,R12 Convert next input value. + 706 * +000000000000072A 07FD 707 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 22 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 709 *********************************************************************** + 710 * + 711 * Perform Divide using provided long BFP input pairs. This set of + 712 * tests exhaustively tests all rounding modes available for Divide. + 713 * The rounding mode can only be specified in the FPC. + 714 * + 715 * All five FPC rounding modes are tested because the preceeding tests, + 716 * using rounding mode RNTE, do not often create results that require + 717 * rounding. + 718 * + 719 * Two results are generated for each input and rounding mode: one RRE + 720 * and one RXE. Traps are disabled for all rounding mode tests. + 721 * + 722 * The quotient and FPCR contents are stored for each test. + 723 * + 724 *********************************************************************** + + +000000000000072C 9823 A000 0000000000000000 726 XBFPRM LM R2,R3,0(R10) Get count and address of test input values +0000000000000730 9878 A008 0000000000000008 727 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000734 1222 728 LTR R2,R2 Any test cases? +0000000000000736 078D 729 BZR R13 ..No, return to caller +0000000000000738 1711 730 XR R1,R1 Zero register 1 for use in IC/STC/indexing +000000000000073A 0DC0 731 BASR R12,0 Set top of test case loop + 732 +000000000000073C 4150 0005 0000000000000005 733 LA R5,FPCMCT Get count of FPC modes to be tested +0000000000000740 0D90 734 BASR R9,0 Set top of rounding mode loop + 735 * +0000000000000742 4315 F783 0000000000000783 736 IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode + 737 * +0000000000000746 B29D F294 0000000000000294 738 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000074A B2B8 1000 0000000000000000 739 SRNMB 0(R1) Set FPC Rounding Mode +000000000000074E 6880 3000 0000000000000000 740 LD FPR8,0(,R3) Get extended BFP dividend part 1 +0000000000000752 68A0 3008 0000000000000008 741 LD FPR10,8(,R3) Get extended BFP dividend part 2 +0000000000000756 6810 3010 0000000000000010 742 LD FPR1,16(,R3) Get extended BFP divisor part 1 +000000000000075A 6830 3018 0000000000000018 743 LD FPR3,24(,R3) Get extended BFP divisor part 2 +000000000000075E B34D 0081 744 DXBR FPR8,FPR1 Divide RRE FPR8/FPR1 non-trappable +0000000000000762 6080 7000 0000000000000000 745 STD FPR8,0(,R7) Store extended BFP quotient part 1 +0000000000000766 60A0 7008 0000000000000008 746 STD FPR10,8(,R7) Store extended BFP quotient part 2 +000000000000076A B29C 8000 0000000000000000 747 STFPC 0(R8) Store resulting FPCR flags and DXC + 748 * +000000000000076E 4170 7010 0000000000000010 749 LA R7,16(,R7) Point to next quotient result set +0000000000000772 4180 8004 0000000000000004 750 LA R8,4(,R8) Point to next FPCR result area + 751 * +0000000000000776 0659 752 BCTR R5,R9 Iterate to next FPC mode + 753 * + 754 * End of FPC modes to be tested. Advance to next test case. + 755 * +0000000000000778 4130 3020 0000000000000020 756 LA R3,32(,R3) Point to next input value pair +000000000000077C 4180 800C 000000000000000C 757 LA R8,12(,R8) Skip to start of next FPCR result area +0000000000000780 062C 758 BCTR R2,R12 Divide next input value lots of times + 759 * + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 23 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000782 07FD 760 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 24 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 762 *********************************************************************** + 763 * + 764 * Table of FPC rounding modes to test quotient rounding modes. + 765 * + 766 * The Set BFP Rounding Mode does allow specification of the FPC + 767 * rounding mode as an address, so we shall index into a table of + 768 * BFP rounding modes without bothering with Execute. + 769 * + 770 *********************************************************************** + + + 772 * + 773 * Rounding modes that may be set in the FPCR. The FPCR controls + 774 * rounding of the quotient. + 775 * + 776 * These are indexed directly by the loop counter, which counts down. + 777 * So the modes are listed in reverse order here. + 778 * +0000000000000784 779 FPCMODES DS 0C +0000000000000784 07 780 DC AL1(7) RFS, Round for shorter precision +0000000000000785 03 781 DC AL1(3) RM, Round to -infinity +0000000000000786 02 782 DC AL1(2) RP, Round to +infinity +0000000000000787 01 783 DC AL1(1) RZ, Round to zero +0000000000000788 00 784 DC AL1(0) RNTE, Round to Nearest, ties to even + 0000000000000005 0000000000000001 785 FPCMCT EQU *-FPCMODES Count of FPC Modes to be tested + 786 * + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 25 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 788 *********************************************************************** + 789 * + 790 * Short BFP test data sets for Divide testing. + 791 * + 792 * The first test data set is used for tests of basic functionality, + 793 * NaN propagation, and results from operations involving other than + 794 * finite numbers. + 795 * + 796 * The second test data set is used for testing boundary conditions + 797 * using two finite non-zero values. Each possible condition code + 798 * and type of result (normal, scaled, etc) is created by members of + 799 * this test data set. + 800 * + 801 * The third test data set is used for exhaustive testing of final + 802 * results across the five rounding modes available for the Divide + 803 * instruction. + 804 * + 805 *********************************************************************** + + + 807 *********************************************************************** + 808 * + 809 * First input test data set, to test operations using non-finite or + 810 * zero inputs. Member values chosen to validate part 1 of Figure 19-21 + 811 * on page 19-29 of SA22-7832-10. Each value in this table is tested + 812 * against every other value in the table. + 813 * + 814 *********************************************************************** + + +000000000000078C 816 SBFPNFIN DS 0F Inputs for short BFP non-finite tests +000000000000078C FF800000 817 DC X'FF800000' -inf +0000000000000790 C0000000 818 DC X'C0000000' -2.0 +0000000000000794 80000000 819 DC X'80000000' -0 +0000000000000798 00000000 820 DC X'00000000' +0 +000000000000079C 40000000 821 DC X'40000000' +2.0 +00000000000007A0 7F800000 822 DC X'7F800000' +inf +00000000000007A4 FFCB0000 823 DC X'FFCB0000' -QNaN +00000000000007A8 7F8A0000 824 DC X'7F8A0000' +SNaN + 0000000000000008 0000000000000001 825 SBFPNFCT EQU (*-SBFPNFIN)/4 Count of short BFP in list + + + + 827 *********************************************************************** + 828 * + 829 * Second input test data set. These are finite pairs intended to + 830 * trigger overflow, underflow, and inexact exceptions. Each pair is + 831 * divided twice, once non-trappable and once trappable. Trappable + 832 * overflow or underflow yields a scaled result. Trappable inexact + 833 * will show whether the Incremented DXC code is returned. + 834 * + 835 * The following test cases are required: + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 26 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 836 * 1. Overflow + 837 * 2. Underflow + 838 * 3. Inexact - incremented + 839 * 4. Inexact - truncated + 840 * + 841 *********************************************************************** + + +00000000000007AC 843 SBFPIN DS 0F Inputs for short BFP finite tests + 844 * + 845 * Following forces quotient overflow. + 846 * +00000000000007AC 7F7FFFFF 847 DC X'7F7FFFFF' +maxvalue +00000000000007B0 00000001 848 DC X'00000001' +minvalue (tiny) + 849 * + 850 * Divide the smallest possible normal by 2.0 to get the largest + 851 * possible tiny, and get underflow in the process. + 852 * +00000000000007B4 00800000 853 DC X'00800000' smallest possible normal +00000000000007B8 40000000 854 DC X'40000000' divide by 2.0, force underflow + 855 * + 856 * Divide 1.0 by 10.0 to get 0.1, a repeating fraction that must be + 857 * rounded in any precision. Inexact, Incremented. + 858 * +00000000000007BC 3F800000 859 DC X'3F800000' +1 +00000000000007C0 41200000 860 DC X'41200000' +10.0 + 861 * + 862 * Divide 7.0 by 10.0 to get 0.7, a repeating fraction that must be + 863 * rounded in any precision. But this one rounds down. Inexact only. + 864 * +00000000000007C4 40100000 865 DC X'40100000' 7.0 +00000000000007C8 41200000 866 DC X'41200000' +10.0 + 867 * + 868 * Divide 1.0 by -10.0 to get -0.1, a repeating fraction that must be + 869 * rounded in any precision. Inexact, Incremented. + 870 * +00000000000007CC 3F800000 871 DC X'3F800000' +1 +00000000000007D0 C1200000 872 DC X'C1200000' -10.0 + 873 * + 874 * Divide 7.0 by -10.0 to get 0.7, a repeating fraction that must be + 875 * rounded in any precision. But this one rounds down. Inexact only. + 876 * +00000000000007D4 40100000 877 DC X'40100000' 7.0 +00000000000007D8 C1200000 878 DC X'C1200000' -10.0 + 879 * + 0000000000000006 0000000000000001 880 SBFPCT EQU (*-SBFPIN)/4/2 Count of short BFP in list + + + + 882 *********************************************************************** + 883 * + 884 * Third input test data set. These are finite pairs intended to + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 27 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 885 * test all combinations of rounding mode for the quotient and the + 886 * remainder. Values are chosen to create a requirement to round + 887 * to the target precision after the computation + 888 * + 889 *********************************************************************** + + +00000000000007DC 891 SBFPINRM DS 0F Inputs for short BFP rounding testing + 892 * + 893 * Divide 1.0 by 10.0 to get 0.1, a repeating fraction that must be + 894 * rounded in any precision. Inexact, Incremented. + 895 * +00000000000007DC 3F800000 896 DC X'3F800000' +1 +00000000000007E0 41200000 897 DC X'41200000' +10.0 + 898 * + 899 * Divide 7.0 by 10.0 to get 0.7, a repeating fraction that must be + 900 * rounded in any precision. But this one rounds down. Inexact only. + 901 * +00000000000007E4 40100000 902 DC X'40100000' 7.0 +00000000000007E8 41200000 903 DC X'41200000' +10.0 + 904 * + 905 * Divide 1.0 by -10.0 to get -0.1, a repeating fraction that must be + 906 * rounded in any precision. Inexact, Incremented. + 907 * +00000000000007EC 3F800000 908 DC X'3F800000' +1 +00000000000007F0 C1200000 909 DC X'C1200000' -10.0 + 910 * + 911 * Divide 7.0 by -10.0 to get 0.7, a repeating fraction that must be + 912 * rounded in any precision. But this one rounds down. Inexact only. + 913 * +00000000000007F4 40100000 914 DC X'40100000' 7.0 +00000000000007F8 C1200000 915 DC X'C1200000' -10.0 + 916 * + 0000000000000004 0000000000000001 917 SBFPRMCT EQU (*-SBFPINRM)/4/2 Count of short BFP rounding tests + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 28 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 919 *********************************************************************** + 920 * + 921 * Long BFP test data sets for Divide testing. + 922 * + 923 * The first test data set is used for tests of basic functionality, + 924 * NaN propagation, and results from operations involving other than + 925 * finite numbers. + 926 * + 927 * The second test data set is used for testing boundary conditions + 928 * using two finite non-zero values. Each possible condition code + 929 * and type of result (normal, scaled, etc) is created by members of + 930 * this test data set. + 931 * + 932 * The third test data set is used for exhaustive testing of final + 933 * results across the five rounding modes available for the Divide + 934 * instruction. + 935 * + 936 *********************************************************************** + + + 938 *********************************************************************** + 939 * + 940 * First input test data set, to test operations using non-finite or + 941 * zero inputs. Member values chosen to validate part 1 of Figure 19-21 + 942 * on page 19-29 of SA22-7832-10. Each value in this table is tested + 943 * against every other value in the table. + 944 * + 945 *********************************************************************** + + +00000000000007FC 947 LBFPNFIN DS 0F Inputs for long BFP testing +00000000000007FC FFF00000 00000000 948 DC X'FFF0000000000000' -inf +0000000000000804 C0000000 00000000 949 DC X'C000000000000000' -2.0 +000000000000080C 80000000 00000000 950 DC X'8000000000000000' -0 +0000000000000814 00000000 00000000 951 DC X'0000000000000000' +0 +000000000000081C 40000000 00000000 952 DC X'4000000000000000' +2.0 +0000000000000824 7FF00000 00000000 953 DC X'7FF0000000000000' +inf +000000000000082C FFF8B000 00000000 954 DC X'FFF8B00000000000' -QNaN +0000000000000834 7FF0A000 00000000 955 DC X'7FF0A00000000000' +SNaN + 0000000000000008 0000000000000001 956 LBFPNFCT EQU (*-LBFPNFIN)/8 Count of long BFP in list + + + + 958 *********************************************************************** + 959 * + 960 * Second input test data set. These are finite pairs intended to + 961 * trigger overflow, underflow, and inexact exceptions. Each pair is + 962 * divided twice, once non-trappable and once trappable. Trappable + 963 * overflow or underflow yields a scaled result. Trappable inexact + 964 * will show whether the Incremented DXC code is returned. + 965 * + 966 * The following test cases are required: + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 29 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 967 * 1. Overflow + 968 * 2. Underflow + 969 * 3. Inexact - incremented + 970 * 4. Inexact - truncated + 971 * + 972 *********************************************************************** + + +0000000000000840 974 LBFPIN DS 0D Inputs for long BFP finite tests + 975 * + 976 * Following forces quotient overflow. + 977 * +0000000000000840 7FEFFFFF FFFFFFFF 978 DC X'7FEFFFFFFFFFFFFF' +maxvalue +0000000000000848 00000000 00000001 979 DC X'0000000000000001' +minvalue (tiny) + 980 * + 981 * Divide the smallest possible normal by 2.0 to get the largest + 982 * possible tiny, and get underflow in the process. + 983 * +0000000000000850 00100000 00000000 984 DC X'0010000000000000' smallest possible normal +0000000000000858 40000000 00000000 985 DC X'4000000000000000' divide by 2.0, force underflow + 986 * + 987 * Divide 1.0 by 10.0 to get 0.1, a repeating fraction that must be + 988 * rounded in any precision. Inexact, Incremented. + 989 * +0000000000000860 3FF00000 00000000 990 DC X'3FF0000000000000' +1 +0000000000000868 40240000 00000000 991 DC X'4024000000000000' +10.0 + 992 * + 993 * Divide 7.0 by 10.0 to get 0.7, a repeating fraction that must be + 994 * rounded in any precision. But this one rounds down. Inexact only. + 995 * +0000000000000870 401C0000 00000000 996 DC X'401C000000000000' 7.0 +0000000000000878 40240000 00000000 997 DC X'4024000000000000' +10.0 + 998 * + 999 * Divide 1.0 by -10.0 to get -0.1, a repeating fraction that must be + 1000 * rounded in any precision. Inexact, Incremented. + 1001 * +0000000000000880 3FF00000 00000000 1002 DC X'3FF0000000000000' +1 +0000000000000888 C0240000 00000000 1003 DC X'C024000000000000' -10.0 + 1004 * + 1005 * Divide 7.0 by -10.0 to get -0.7, a repeating fraction that must be + 1006 * rounded in any precision. But this one rounds down. Inexact only. + 1007 * +0000000000000890 401C0000 00000000 1008 DC X'401C000000000000' 7.0 +0000000000000898 C0240000 00000000 1009 DC X'C024000000000000' -10.0 + 1010 * + 0000000000000006 0000000000000001 1011 LBFPCT EQU (*-LBFPIN)/8/2 Count of long BFP in list * 8 + + + + 1013 *********************************************************************** + 1014 * + 1015 * Third input test data set. These are finite pairs intended to + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 30 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1016 * test all combinations of rounding mode for the quotient and the + 1017 * remainder. Values are chosen to create a requirement to round + 1018 * to the target precision after the computation + 1019 * + 1020 *********************************************************************** + + +00000000000008A0 1022 LBFPINRM DS 0F + 1023 * + 1024 * Divide 1.0 by 10.0 to get 0.1, a repeating fraction that must be + 1025 * rounded in any precision. Inexact, Incremented. + 1026 * +00000000000008A0 3FF00000 00000000 1027 DC X'3FF0000000000000' +1 +00000000000008A8 40240000 00000000 1028 DC X'4024000000000000' +10.0 + 1029 * + 1030 * Divide 7.0 by 10.0 to get 0.7, a repeating fraction that must be + 1031 * rounded in any precision. But this one rounds down. Inexact only. + 1032 * +00000000000008B0 401C0000 00000000 1033 DC X'401C000000000000' 7.0 +00000000000008B8 40240000 00000000 1034 DC X'4024000000000000' +10.0 + 1035 * + 1036 * Divide 1.0 by -10.0 to get -0.1, a repeating fraction that must be + 1037 * rounded in any precision. Inexact, Incremented. + 1038 * +00000000000008C0 3FF00000 00000000 1039 DC X'3FF0000000000000' +1 +00000000000008C8 C0240000 00000000 1040 DC X'C024000000000000' -10.0 + 1041 * + 1042 * Divide 7.0 by -10.0 to get -0.7, a repeating fraction that must be + 1043 * rounded in any precision. But this one rounds down. Inexact only. + 1044 * +00000000000008D0 401C0000 00000000 1045 DC X'401C000000000000' 7.0 +00000000000008D8 C0240000 00000000 1046 DC X'C024000000000000' -10.0 + 1047 * + 0000000000000004 0000000000000001 1048 LBFPRMCT EQU (*-LBFPINRM)/8/2 Count of long BFP rounding tests * 8 + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 31 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1050 *********************************************************************** + 1051 * + 1052 * Extended BFP test data sets for Divide testing. + 1053 * + 1054 * The first test data set is used for tests of basic functionality, + 1055 * NaN propagation, and results from operations involving other than + 1056 * finite numbers. + 1057 * + 1058 * The second test data set is used for testing boundary conditions + 1059 * using two finite non-zero values. Each possible condition code + 1060 * and type of result (normal, scaled, etc) is created by members of + 1061 * this test data set. + 1062 * + 1063 * The third test data set is used for exhaustive testing of final + 1064 * results across the five rounding modes available for the Divide + 1065 * instruction. + 1066 * + 1067 *********************************************************************** + + + 1069 *********************************************************************** + 1070 * + 1071 * First input test data set, to test operations using non-finite or + 1072 * zero inputs. Member values chosen to validate part 1 of Figure 19-21 + 1073 * on page 19-29 of SA22-7832-10. Each value in this table is tested + 1074 * against every other value in the table. + 1075 * + 1076 *********************************************************************** + + +00000000000008E0 1078 XBFPNFIN DS 0F Inputs for extended BFP testing +00000000000008E0 FFFF0000 00000000 1079 DC X'FFFF0000000000000000000000000000' -inf +00000000000008F0 C0000000 00000000 1080 DC X'C0000000000000000000000000000000' -2.0 +0000000000000900 80000000 00000000 1081 DC X'80000000000000000000000000000000' -0 +0000000000000910 00000000 00000000 1082 DC X'00000000000000000000000000000000' +0 +0000000000000920 40000000 00000000 1083 DC X'40000000000000000000000000000000' +2.0 +0000000000000930 7FFF0000 00000000 1084 DC X'7FFF0000000000000000000000000000' +inf +0000000000000940 FFFF8B00 00000000 1085 DC X'FFFF8B00000000000000000000000000' -QNaN +0000000000000950 7FFF0A00 00000000 1086 DC X'7FFF0A00000000000000000000000000' +SNaN + 0000000000000008 0000000000000001 1087 XBFPNFCT EQU (*-XBFPNFIN)/16 Count of extended BFP in list + + + + 1089 *********************************************************************** + 1090 * + 1091 * Second input test data set. These are finite pairs intended to + 1092 * trigger overflow, underflow, and inexact exceptions. Each pair is + 1093 * divided twice, once non-trappable and once trappable. Trappable + 1094 * overflow or underflow yields a scaled result. Trappable inexact + 1095 * will show whether the Incremented DXC code is returned. + 1096 * + 1097 * The following test cases are required: + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 32 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1098 * 1. Overflow + 1099 * 2. Underflow + 1100 * 3. Inexact - incremented + 1101 * 4. Inexact - truncated + 1102 * + 1103 *********************************************************************** + + +0000000000000960 1105 XBFPIN DS 0F Inputs for long BFP finite tests + 1106 * + 1107 * Following forces quotient overflow. + 1108 * +0000000000000960 7FFEFFFF FFFFFFFF 1109 DC X'7FFEFFFFFFFFFFFFFFFFFFFFFFFFFFFF' +maxvalue +0000000000000970 00000000 00000000 1110 DC X'00000000000000000000000000000001' +minvalue (tiny) + 1111 * + 1112 * Divide the smallest possible normal by 2.0 to get the largest + 1113 * possible tiny, and get underflow in the process. + 1114 * +0000000000000980 00010000 00000000 1115 DC X'00010000000000000000000000000000' smallest normal +0000000000000990 40000000 00000000 1116 DC X'40000000000000000000000000000000' divide by 2.0 + 1117 * + 1118 * Divide 1.0 by 10.0 to get 0.1, a repeating fraction that must be + 1119 * rounded in any precision. Inexact, Incremented. + 1120 * +00000000000009A0 3FFF0000 00000000 1121 DC X'3FFF0000000000000000000000000000' +1 +00000000000009B0 40024000 00000000 1122 DC X'40024000000000000000000000000000' +10.0 + 1123 * + 1124 * Divide 7.0 by 10.0 to get 0.7, a repeating fraction that must be + 1125 * rounded in any precision. But this one rounds down. Inexact only. + 1126 * +00000000000009C0 4001C000 00000000 1127 DC X'4001C000000000000000000000000000' +7.0 +00000000000009D0 40024000 00000000 1128 DC X'40024000000000000000000000000000' +10.0 + 1129 * + 1130 * Divide 1.0 by -10.0 to get -0.1, a repeating fraction that must be + 1131 * rounded in any precision. Inexact, Incremented. + 1132 * +00000000000009E0 3FFF0000 00000000 1133 DC X'3FFF0000000000000000000000000000' +1 +00000000000009F0 C0024000 00000000 1134 DC X'C0024000000000000000000000000000' -10.0 + 1135 * + 1136 * Divide 7.0 by -10.0 to get -0.7, a repeating fraction that must be + 1137 * rounded in any precision. But this one rounds down. Inexact only. + 1138 * +0000000000000A00 4001C000 00000000 1139 DC X'4001C000000000000000000000000000' +7.0 +0000000000000A10 C0024000 00000000 1140 DC X'C0024000000000000000000000000000' -10.0 + 1141 * + 0000000000000006 0000000000000001 1142 XBFPCT EQU (*-XBFPIN)/16/2 Count of long BFP in list * 8 + + + + 1144 *********************************************************************** + 1145 * + 1146 * Third input test data set. These are finite pairs intended to + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 33 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1147 * test all combinations of rounding mode for the quotient and the + 1148 * remainder. Values are chosen to create a requirement to round + 1149 * to the target precision after the computation + 1150 * + 1151 *********************************************************************** + + +0000000000000A20 1153 XBFPINRM DS 0D + 1154 * + 1155 * Divide 1.0 by 10.0 to get 0.1, a repeating fraction that must be + 1156 * rounded in any precision. Inexact, Incremented. + 1157 * +0000000000000A20 3FFF0000 00000000 1158 DC X'3FFF0000000000000000000000000000' +1 +0000000000000A30 40024000 00000000 1159 DC X'40024000000000000000000000000000' +10.0 + 1160 * + 1161 * Divide 7.0 by 10.0 to get 0.7, a repeating fraction that must be + 1162 * rounded in any precision. But this one rounds down. Inexact only. + 1163 * +0000000000000A40 4001C000 00000000 1164 DC X'4001C000000000000000000000000000' +7.0 +0000000000000A50 40024000 00000000 1165 DC X'40024000000000000000000000000000' +10.0 + 1166 * + 1167 * Divide 1.0 by -10.0 to get -0.1, a repeating fraction that must be + 1168 * rounded in any precision. Inexact, Incremented. + 1169 * +0000000000000A60 3FFF0000 00000000 1170 DC X'3FFF0000000000000000000000000000' +1 +0000000000000A70 C0024000 00000000 1171 DC X'C0024000000000000000000000000000' -10.0 + 1172 * + 1173 * Divide 7.0 by -10.0 to get -0.7, a repeating fraction that must be + 1174 * rounded in any precision. But this one rounds down. Inexact only. + 1175 * +0000000000000A80 4001C000 00000000 1176 DC X'4001C000000000000000000000000000' +7.0 +0000000000000A90 C0024000 00000000 1177 DC X'C0024000000000000000000000000000' -10.0 + 1178 * + 0000000000000004 0000000000000001 1179 XBFPRMCT EQU (*-XBFPINRM)/16/2 Count of long BFP rounding tests + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 34 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1181 * + 1182 * Locations for results + 1183 * + 0000000000001000 0000000000000001 1184 SBFPNFOT EQU STRTLABL+X'1000' Integer short non-finite BFP results + 1185 * ..room for 64 tests, 64 used + 0000000000001400 0000000000000001 1186 SBFPNFFL EQU STRTLABL+X'1400' FPCR flags and DXC from short BFP + 1187 * ..room for 64 tests, 64 used + 1188 * + 0000000000001800 0000000000000001 1189 SBFPOUT EQU STRTLABL+X'1800' Integer short BFP finite results + 1190 * ..room for 16 tests, 6 used + 0000000000001900 0000000000000001 1191 SBFPFLGS EQU STRTLABL+X'1900' FPCR flags and DXC from short BFP + 1192 * ..room for 16 tests, 6 used + 1193 * + 0000000000001A00 0000000000000001 1194 SBFPRMO EQU STRTLABL+X'1A00' Short BFP rounding mode test results + 1195 * ..Room for 16, 4 used. + 0000000000001D00 0000000000000001 1196 SBFPRMOF EQU STRTLABL+X'1D00' Short BFP rounding mode FPCR results + 1197 * ..Room for 16, 4 used. + 1198 * ..next location starts at X'2000' + 1199 * + 0000000000003000 0000000000000001 1200 LBFPNFOT EQU STRTLABL+X'3000' Integer long non-finite BFP results + 1201 * ..room for 64 tests, 64 used + 0000000000003800 0000000000000001 1202 LBFPNFFL EQU STRTLABL+X'3800' FPCR flags and DXC from long BFP + 1203 * ..room for 64 tests, 64 used + 1204 * + 0000000000003C00 0000000000000001 1205 LBFPOUT EQU STRTLABL+X'3C00' Integer long BFP finite results + 1206 * ..room for 16 tests, 6 used + 0000000000003E00 0000000000000001 1207 LBFPFLGS EQU STRTLABL+X'3E00' FPCR flags and DXC from long BFP + 1208 * ..room for 16 tests, 6 used + 1209 * + 0000000000004000 0000000000000001 1210 LBFPRMO EQU STRTLABL+X'4000' Long BFP rounding mode test results + 1211 * ..Room for 16, 4 used. + 0000000000004500 0000000000000001 1212 LBFPRMOF EQU STRTLABL+X'4500' Long BFP rounding mode FPCR results + 1213 * ..Room for 16, 4 used. + 1214 * ..next location starts at X'4800' + 1215 * + 0000000000005000 0000000000000001 1216 XBFPNFOT EQU STRTLABL+X'5000' Integer ext'd non-finite BFP results + 1217 * ..room for 64 tests, 64 used + 0000000000005800 0000000000000001 1218 XBFPNFFL EQU STRTLABL+X'5800' FPCR flags and DXC from ext'd BFP + 1219 * ..room for 64 tests, 64 used + 1220 * + 0000000000005C00 0000000000000001 1221 XBFPOUT EQU STRTLABL+X'5C00' Extended BFP finite results + 1222 * ..room for 16 tests, 6 used + 0000000000005E00 0000000000000001 1223 XBFPFLGS EQU STRTLABL+X'5E00' FPCR flags and DXC from ext'd BFP + 1224 * ..room for 16 tests, 6 used + 1225 * + 0000000000006000 0000000000000001 1226 XBFPRMO EQU STRTLABL+X'6000' Ext'd BFP rounding mode test results + 1227 * ..Room for 16, 4 used. + 0000000000006A00 0000000000000001 1228 XBFPRMOF EQU STRTLABL+X'6A00' Ext'd BFP rounding mode FPCR results + 1229 * ..Room for 16, 4 used. + 1230 * ..next location starts at X'6D00' + 1231 * + 0000000000006D00 0000000000000001 1232 ENDLABL EQU STRTLABL+X'6D00' + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 35 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1233 PADCSECT ENDLABL + 1234+ MNOTE *,'asma detected; no CSECT padding performed' +0000000000000AA0 1235 END + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 36 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +BFPDIV J 000000 2720 77 +CTLR0 F 000290 4 193 160 161 162 +ENDLABL U 006D00 1 1232 +FPCMCT U 000005 1 785 400 574 733 +FPCMODES C 000784 1 779 785 403 577 736 +FPCREGNT X 000294 4 194 288 302 344 358 405 413 463 476 518 532 579 587 637 683 + 738 +FPCREGTR X 000298 4 195 295 308 351 364 470 482 525 538 647 693 +FPR0 U 000000 1 98 +FPR1 U 000001 1 99 287 289 294 296 301 346 347 354 408 409 462 464 469 471 + 520 521 528 582 583 635 638 645 648 686 688 697 742 744 +FPR10 U 00000A 1 108 634 640 644 650 741 746 +FPR11 U 00000B 1 109 +FPR12 U 00000C 1 110 +FPR13 U 00000D 1 111 684 688 689 694 697 698 +FPR14 U 00000E 1 112 +FPR15 U 00000F 1 113 685 690 695 699 +FPR2 U 000002 1 100 +FPR3 U 000003 1 101 636 646 687 743 +FPR4 U 000004 1 102 +FPR5 U 000005 1 103 +FPR6 U 000006 1 104 +FPR7 U 000007 1 105 +FPR8 U 000008 1 106 286 289 290 293 296 297 300 303 304 307 309 310 345 347 + 348 352 354 355 359 360 361 365 366 367 407 409 410 415 + 416 417 461 464 465 468 471 472 475 477 478 481 483 484 + 519 521 522 526 528 529 533 534 535 539 540 541 581 583 + 584 589 590 591 633 638 639 643 648 649 740 744 745 +FPR9 U 000009 1 107 +HARDWAIT X 000280 8 191 151 +IMAGE 1 000000 2720 0 +LBFPCT U 000006 1 1011 229 +LBFPF I 000580 4 512 174 +LBFPFLGS U 003E00 1 1207 232 +LBFPIN D 000840 8 974 1011 230 +LBFPINRM F 0008A0 4 1022 1048 236 +LBFPNF H 0004FA 2 450 172 +LBFPNFCT U 000008 1 956 223 +LBFPNFFL U 003800 1 1202 226 +LBFPNFIN F 0007FC 4 947 956 224 +LBFPNFOT U 003000 1 1200 225 +LBFPOUT U 003C00 1 1205 231 +LBFPRM I 0005F6 4 567 176 +LBFPRMCT U 000004 1 1048 235 +LBFPRMO U 004000 1 1210 237 +LBFPRMOF U 004500 1 1212 238 +LONGF F 000340 4 228 173 +LONGNF F 000330 4 222 171 +PCINTCD H 00008E 2 128 145 +PCNOTDTA H 00020C 2 148 146 +PCOLDPSW U 000150 1 130 147 +PROGCHK H 000200 2 144 136 + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 37 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +R0 U 000000 1 79 160 162 +R1 U 000001 1 80 397 403 406 414 571 577 580 588 730 736 739 +R10 U 00000A 1 89 164 166 168 171 173 175 178 180 182 276 277 282 338 339 + 393 394 451 452 457 512 513 567 568 623 624 629 677 678 + 726 727 +R11 U 00000B 1 90 +R12 U 00000C 1 91 280 319 342 373 398 430 455 493 516 547 572 603 627 659 + 681 705 731 758 +R13 U 00000D 1 92 165 167 169 172 174 176 179 181 183 279 320 341 374 396 + 432 454 494 515 548 570 605 626 660 680 707 729 760 +R14 U 00000E 1 93 149 150 185 186 +R15 U 00000F 1 94 115 +R2 U 000002 1 81 276 278 319 338 340 373 393 395 430 451 453 493 512 514 + 547 567 569 603 623 625 659 677 679 705 726 728 758 +R3 U 000003 1 82 276 286 293 300 307 318 338 345 346 352 359 360 365 366 + 370 393 407 408 415 416 427 451 461 468 475 481 492 512 + 519 520 526 533 534 539 540 544 567 581 582 589 590 601 + 623 633 634 643 644 658 677 684 685 686 687 694 695 702 + 726 740 741 742 743 756 +R4 U 000004 1 83 282 316 457 490 629 656 +R5 U 000005 1 84 282 287 294 301 303 309 313 400 403 423 457 462 469 477 + 483 487 574 577 597 629 635 636 645 646 653 733 736 752 +R6 U 000006 1 85 284 316 459 490 631 656 +R7 U 000007 1 86 277 290 297 304 310 314 339 348 355 361 367 371 394 410 + 417 420 428 452 465 472 478 484 488 513 522 529 535 541 + 545 568 584 591 594 624 639 640 649 650 654 678 689 690 + 698 699 703 727 745 746 749 +R8 U 000008 1 87 277 291 298 305 311 315 339 349 356 362 368 372 394 411 + 418 421 429 452 466 473 479 485 489 513 523 530 536 542 + 546 568 585 592 595 602 624 641 651 655 678 691 700 704 + 727 747 750 757 +R9 U 000009 1 88 401 423 575 597 734 752 +RMLONGS F 000350 4 234 175 +RMSHORTS F 000320 4 216 168 +RMXTNDS F 000380 4 252 182 +SBFPCT U 000006 1 880 211 +SBFPF I 00041A 4 338 167 +SBFPFLGS U 001900 1 1191 214 +SBFPIN F 0007AC 4 843 880 212 +SBFPINRM F 0007DC 4 891 917 218 +SBFPNF H 000390 2 275 165 +SBFPNFCT U 000008 1 825 205 +SBFPNFFL U 001400 1 1186 208 +SBFPNFIN F 00078C 4 816 825 206 +SBFPNFOT U 001000 1 1184 207 +SBFPOUT U 001800 1 1189 213 +SBFPRM I 000490 4 393 169 +SBFPRMCT U 000004 1 917 217 +SBFPRMO U 001A00 1 1194 219 +SBFPRMOF U 001D00 1 1196 220 +SHORTF F 000310 4 210 166 +SHORTNF F 000300 4 204 164 + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 38 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +START H 000214 2 159 133 +STRTLABL U 000000 1 78 127 130 132 135 143 203 1184 1186 1189 1191 1194 1196 1200 1202 + 1205 1207 1210 1212 1216 1218 1221 1223 1226 1228 1232 +WAITPSW X 000270 8 190 187 +XBFPCT U 000006 1 1142 247 +XBFPF I 0006CE 4 677 181 +XBFPFLGS U 005E00 1 1223 250 +XBFPIN F 000960 4 1105 1142 248 +XBFPINRM D 000A20 8 1153 1179 254 +XBFPNF H 00065C 2 622 179 +XBFPNFCT U 000008 1 1087 241 +XBFPNFFL U 005800 1 1218 244 +XBFPNFIN F 0008E0 4 1078 1087 242 +XBFPNFOT U 005000 1 1216 243 +XBFPOUT U 005C00 1 1221 249 +XBFPRM I 00072C 4 726 183 +XBFPRMCT U 000004 1 1179 253 +XBFPRMO U 006000 1 1226 255 +XBFPRMOF U 006A00 1 1228 256 +XTNDF F 000370 4 246 180 +XTNDNF F 000360 4 240 178 + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 39 + + MACRO DEFN REFERENCES + +PADCSECT 52 1233 + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 40 + + DESC SYMBOL SIZE POS ADDR + +Entry: 0 + +Image IMAGE 2720 000-A9F 000-A9F + Region 2720 000-A9F 000-A9F + CSECT BFPDIV 2720 000-A9F 000-A9F + ASMA Ver. 0.2.0 bfp-014-divide.asm: Test IEEE Divide 28 Sep 2016 07:27:04 Page 41 + + STMT FILE NAME + +1 C:\Users\srorso\Documents\GitHub\hyperion\tests\bfp-014-divide.asm + + +** NO ERRORS FOUND ** + +[1234] MNOTE *,asma detected; no CSECT padding performed + \ No newline at end of file diff --git a/tests/bfp-014-divide.tst b/tests/bfp-014-divide.tst new file mode 100644 index 000000000..bd459080b --- /dev/null +++ b/tests/bfp-014-divide.tst @@ -0,0 +1,1387 @@ +*Testcase bfp-014-divide.tst: DEBR, DEB, DDBR, DDB, DXBR + +#Testcase bfp-014-divide.tst: IEEE Divide tests DIVIDE (5) +#..Test cases evaluate NaN propagation, NaN generation, operations +#..using non-finite values, trappable and non-trappable IEEE +#..exceptions, result scaling, and exhaustive rounding testing. + +sysclear +archmode esame + +# +# Following suppresses logging of program checks. This test program, as part +# of its normal operation, generates 165 program check messages that have no +# value in the validation process. +# +ostailor quiet + +loadcore "$(testpath)/bfp-014-divide.core" + +runtest 1.0 + +ostailor null # restore messages for subsequent tests + + +# Short BFP Non-finite test results +*Compare +r 1000.10 +*Want "DEBR/DEB NF -inf/-inf" 7FC00000 FF800000 7FC00000 FF800000 +r 1010.10 +*Want "DEBR/DEB NF -inf/-2" 7F800000 7F800000 7F800000 7F800000 +r 1020.10 +*Want "DEBR/DEB NF -inf/-0" 7F800000 7F800000 7F800000 7F800000 +r 1030.10 +*Want "DEBR/DEB NF -inf/+0" FF800000 FF800000 FF800000 FF800000 +r 1040.10 +*Want "DEBR/DEB NF -inf/+2" FF800000 FF800000 FF800000 FF800000 +r 1050.10 +*Want "DEBR/DEB NF -inf/+inf" 7FC00000 FF800000 7FC00000 FF800000 +r 1060.10 +*Want "DEBR/DEB NF -inf/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1070.10 +*Want "DEBR/DEB NF -inf/+SNaN" 7FCA0000 FF800000 7FCA0000 FF800000 +r 1080.10 +*Want "DEBR/DEB NF -2/-inf" 00000000 00000000 00000000 00000000 +r 1090.10 +*Want "DEBR/DEB NF -2/-2" 3F800000 3F800000 3F800000 3F800000 +r 10A0.10 +*Want "DEBR/DEB NF -2/-0" 7F800000 C0000000 7F800000 C0000000 +r 10B0.10 +*Want "DEBR/DEB NF -2/+0" FF800000 C0000000 FF800000 C0000000 +r 10C0.10 +*Want "DEBR/DEB NF -2/+2" BF800000 BF800000 BF800000 BF800000 +r 10D0.10 +*Want "DEBR/DEB NF -2/+inf" 80000000 80000000 80000000 80000000 +r 10E0.10 +*Want "DEBR/DEB NF -2/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 10F0.10 +*Want "DEBR/DEB NF -2/+SNaN" 7FCA0000 C0000000 7FCA0000 C0000000 +r 1100.10 +*Want "DEBR/DEB NF -0/-inf" 00000000 00000000 00000000 00000000 +r 1110.10 +*Want "DEBR/DEB NF -0/-2" 00000000 00000000 00000000 00000000 +r 1120.10 +*Want "DEBR/DEB NF -0/-0" 7FC00000 80000000 7FC00000 80000000 +r 1130.10 +*Want "DEBR/DEB NF -0/+0" 7FC00000 80000000 7FC00000 80000000 +r 1140.10 +*Want "DEBR/DEB NF -0/+2" 80000000 80000000 80000000 80000000 +r 1150.10 +*Want "DEBR/DEB NF -0/+inf" 80000000 80000000 80000000 80000000 +r 1160.10 +*Want "DEBR/DEB NF -0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1170.10 +*Want "DEBR/DEB NF -0/+SNaN" 7FCA0000 80000000 7FCA0000 80000000 +r 1180.10 +*Want "DEBR/DEB NF +0/-inf" 80000000 80000000 80000000 80000000 +r 1190.10 +*Want "DEBR/DEB NF +0/-2" 80000000 80000000 80000000 80000000 +r 11A0.10 +*Want "DEBR/DEB NF +0/-0" 7FC00000 00000000 7FC00000 00000000 +r 11B0.10 +*Want "DEBR/DEB NF +0/+0" 7FC00000 00000000 7FC00000 00000000 +r 11C0.10 +*Want "DEBR/DEB NF +0/+2" 00000000 00000000 00000000 00000000 +r 11D0.10 +*Want "DEBR/DEB NF +0/+inf" 00000000 00000000 00000000 00000000 +r 11E0.10 +*Want "DEBR/DEB NF +0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 11F0.10 +*Want "DEBR/DEB NF +0/+SNaN" 7FCA0000 00000000 7FCA0000 00000000 +r 1200.10 +*Want "DEBR/DEB NF +2/-inf" 80000000 80000000 80000000 80000000 +r 1210.10 +*Want "DEBR/DEB NF +2/-2" BF800000 BF800000 BF800000 BF800000 +r 1220.10 +*Want "DEBR/DEB NF +2/-0" FF800000 40000000 FF800000 40000000 +r 1230.10 +*Want "DEBR/DEB NF +2/+0" 7F800000 40000000 7F800000 40000000 +r 1240.10 +*Want "DEBR/DEB NF +2/+2" 3F800000 3F800000 3F800000 3F800000 +r 1250.10 +*Want "DEBR/DEB NF +2/+inf" 00000000 00000000 00000000 00000000 +r 1260.10 +*Want "DEBR/DEB NF +2/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1270.10 +*Want "DEBR/DEB NF +2/+SNaN" 7FCA0000 40000000 7FCA0000 40000000 +r 1280.10 +*Want "DEBR/DEB NF +inf/-inf" 7FC00000 7F800000 7FC00000 7F800000 +r 1290.10 +*Want "DEBR/DEB NF +inf/-2" FF800000 FF800000 FF800000 FF800000 +r 12A0.10 +*Want "DEBR/DEB NF +inf/-0" FF800000 FF800000 FF800000 FF800000 +r 12B0.10 +*Want "DEBR/DEB NF +inf/+0" 7F800000 7F800000 7F800000 7F800000 +r 12C0.10 +*Want "DEBR/DEB NF +inf/+2" 7F800000 7F800000 7F800000 7F800000 +r 12D0.10 +*Want "DEBR/DEB NF +inf/+inf" 7FC00000 7F800000 7FC00000 7F800000 +r 12E0.10 +*Want "DEBR/DEB NF +inf/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 12F0.10 +*Want "DEBR/DEB NF +inf/+SNaN" 7FCA0000 7F800000 7FCA0000 7F800000 +r 1300.10 +*Want "DEBR/DEB NF -QNaN/-inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1310.10 +*Want "DEBR/DEB NF -QNaN/-2" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1320.10 +*Want "DEBR/DEB NF -QNaN/-0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1330.10 +*Want "DEBR/DEB NF -QNaN/+0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1340.10 +*Want "DEBR/DEB NF -QNaN/+2" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1350.10 +*Want "DEBR/DEB NF -QNaN/+inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1360.10 +*Want "DEBR/DEB NF -QNaN/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1370.10 +*Want "DEBR/DEB NF -QNaN/+SNaN" 7FCA0000 FFCB0000 7FCA0000 FFCB0000 +r 1380.10 +*Want "DEBR/DEB NF +SNaN/-inf" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1390.10 +*Want "DEBR/DEB NF +SNaN/-2" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 13A0.10 +*Want "DEBR/DEB NF +SNaN/-0" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 13B0.10 +*Want "DEBR/DEB NF +SNaN/+0" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 13C0.10 +*Want "DEBR/DEB NF +SNaN/+2" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 13D0.10 +*Want "DEBR/DEB NF +SNaN/+inf" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 13E0.10 +*Want "DEBR/DEB NF +SNaN/-QNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 13F0.10 +*Want "DEBR/DEB NF +SNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 + + +# Short BFP Non-finite test results FPCR contents +*Compare +r 1400.10 +*Want "DEBR/DEB NF -inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 1410.10 +*Want "DEBR/DEB NF -inf/-2 FPCR" 00000000 F8000000 00000000 F8000000 +r 1420.10 +*Want "DEBR/DEB NF -inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1430.10 +*Want "DEBR/DEB NF -inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1440.10 +*Want "DEBR/DEB NF -inf/+2 FPCR" 00000000 F8000000 00000000 F8000000 +r 1450.10 +*Want "DEBR/DEB NF -inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 1460.10 +*Want "DEBR/DEB NF -inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 1470.10 +*Want "DEBR/DEB NF -inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 1480.10 +*Want "DEBR/DEB NF -2/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 1490.10 +*Want "DEBR/DEB NF -2/-2 FPCR" 00000000 F8000000 00000000 F8000000 +r 14A0.10 +*Want "DEBR/DEB NF -2/-0 FPCR" 00400000 F8004000 00400000 F8004000 +r 14B0.10 +*Want "DEBR/DEB NF -2/+0 FPCR" 00400000 F8004000 00400000 F8004000 +r 14C0.10 +*Want "DEBR/DEB NF -2/+2 FPCR" 00000000 F8000000 00000000 F8000000 +r 14D0.10 +*Want "DEBR/DEB NF -2/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 14E0.10 +*Want "DEBR/DEB NF -2/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 14F0.10 +*Want "DEBR/DEB NF -2/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 1500.10 +*Want "DEBR/DEB NF -0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 1510.10 +*Want "DEBR/DEB NF -0/-2 FPCR" 00000000 F8000000 00000000 F8000000 +r 1520.10 +*Want "DEBR/DEB NF -0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 1530.10 +*Want "DEBR/DEB NF -0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 1540.10 +*Want "DEBR/DEB NF -0/+2 FPCR" 00000000 F8000000 00000000 F8000000 +r 1550.10 +*Want "DEBR/DEB NF -0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 1560.10 +*Want "DEBR/DEB NF -0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 1570.10 +*Want "DEBR/DEB NF -0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 1580.10 +*Want "DEBR/DEB NF +0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 1590.10 +*Want "DEBR/DEB NF +0/-2 FPCR" 00000000 F8000000 00000000 F8000000 +r 15A0.10 +*Want "DEBR/DEB NF +0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 15B0.10 +*Want "DEBR/DEB NF +0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 15C0.10 +*Want "DEBR/DEB NF +0/+2 FPCR" 00000000 F8000000 00000000 F8000000 +r 15D0.10 +*Want "DEBR/DEB NF +0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 15E0.10 +*Want "DEBR/DEB NF +0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 15F0.10 +*Want "DEBR/DEB NF +0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 1600.10 +*Want "DEBR/DEB NF +2/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 1610.10 +*Want "DEBR/DEB NF +2/-2 FPCR" 00000000 F8000000 00000000 F8000000 +r 1620.10 +*Want "DEBR/DEB NF +2/-0 FPCR" 00400000 F8004000 00400000 F8004000 +r 1630.10 +*Want "DEBR/DEB NF +2/+0 FPCR" 00400000 F8004000 00400000 F8004000 +r 1640.10 +*Want "DEBR/DEB NF +2/+2 FPCR" 00000000 F8000000 00000000 F8000000 +r 1650.10 +*Want "DEBR/DEB NF +2/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 1660.10 +*Want "DEBR/DEB NF +2/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 1670.10 +*Want "DEBR/DEB NF +2/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 1680.10 +*Want "DEBR/DEB NF +inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 1690.10 +*Want "DEBR/DEB NF +inf/-2 FPCR" 00000000 F8000000 00000000 F8000000 +r 16A0.10 +*Want "DEBR/DEB NF +inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 16B0.10 +*Want "DEBR/DEB NF +inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 16C0.10 +*Want "DEBR/DEB NF +inf/+2 FPCR" 00000000 F8000000 00000000 F8000000 +r 16D0.10 +*Want "DEBR/DEB NF +inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 16E0.10 +*Want "DEBR/DEB NF +inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 16F0.10 +*Want "DEBR/DEB NF +inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 1700.10 +*Want "DEBR/DEB NF -QNaN/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 1710.10 +*Want "DEBR/DEB NF -QNaN/-2 FPCR" 00000000 F8000000 00000000 F8000000 +r 1720.10 +*Want "DEBR/DEB NF -QNaN/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1730.10 +*Want "DEBR/DEB NF -QNaN/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1740.10 +*Want "DEBR/DEB NF -QNaN/+2 FPCR" 00000000 F8000000 00000000 F8000000 +r 1750.10 +*Want "DEBR/DEB NF -QNaN/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 1760.10 +*Want "DEBR/DEB NF -QNaN/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 1770.10 +*Want "DEBR/DEB NF -QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 1780.10 +*Want "DEBR/DEB NF +SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 1790.10 +*Want "DEBR/DEB NF +SNaN/-2 FPCR" 00800000 F8008000 00800000 F8008000 +r 17A0.10 +*Want "DEBR/DEB NF +SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 17B0.10 +*Want "DEBR/DEB NF +SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 17C0.10 +*Want "DEBR/DEB NF +SNaN/+2 FPCR" 00800000 F8008000 00800000 F8008000 +r 17D0.10 +*Want "DEBR/DEB NF +SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 17E0.10 +*Want "DEBR/DEB NF +SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 17F0.10 +*Want "DEBR/DEB NF +SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 + + +# Short BFP finite test results +*Compare +r 1800.10 +*Want "DEBR/DEB max/min" 7F800000 69FFFFFF 7F800000 69FFFFFF +r 1810.10 +*Want "DEBR/DEB min/2.0" 00400000 60000000 00400000 60000000 +r 1820.10 +*Want "DEBR/DEB 1.0/10.0" 3DCCCCCD 3DCCCCCD 3DCCCCCD 3DCCCCCD +r 1830.10 +*Want "DEBR/DEB 7.0/10.0" 3E666666 3E666666 3E666666 3E666666 +r 1840.10 +*Want "DEBR/DEB 1.0/-10.0" BDCCCCCD BDCCCCCD BDCCCCCD BDCCCCCD +r 1850.10 +*Want "DEBR/DEB 7.0/-10.0" BE666666 BE666666 BE666666 BE666666 + + +# Short BFP finite test results - FPCR contents +*Compare +r 1900.10 +*Want "DEBR/DEB max/min FPCR" 00280000 F8002000 00280000 F8002000 +r 1910.10 +*Want "DEBR/DEB min/2.0 FPCR" 00000000 F8001000 00000000 F8001000 +r 1920.10 +*Want "DEBR/DEB 1.0/10.0 FPCR" 00080000 F8000C00 00080000 F8000C00 +r 1930.10 +*Want "DEBR/DEB 7.0/10.0 FPCR" 00080000 F8000800 00080000 F8000800 +r 1940.10 +*Want "DEBR/DEB 1.0/-10.0 FPCR" 00080000 F8000C00 00080000 F8000C00 +r 1950.10 +*Want "DEBR/DEB 7.0/-10.0 FPCR" 00080000 F8000800 00080000 F8000800 + + +# Short BFP rounding mode test results +*Compare +r 1A00.10 +*Want "DEBR/DEB RM RNTE,RZ 1/10" 3DCCCCCD 3DCCCCCD 3DCCCCCC 3DCCCCCC +r 1A10.10 +*Want "DEBR/DEB RM RP,RM 1/10" 3DCCCCCD 3DCCCCCD 3DCCCCCC 3DCCCCCC +r 1A20.08 +*Want "DEBR/DEB RM RFS 1/10" 3DCCCCCD 3DCCCCCD +r 1A30.10 +*Want "DEBR/DEB RM RNTE,RZ 7/10" 3E666666 3E666666 3E666666 3E666666 +r 1A40.10 +*Want "DEBR/DEB RM RP,RM 7/10" 3E666667 3E666667 3E666666 3E666666 +r 1A50.08 +*Want "DEBR/DEB RM RFS 7/10" 3E666667 3E666667 +r 1A60.10 +*Want "DEBR/DEB RM RNTE,RZ 1/-10" BDCCCCCD BDCCCCCD BDCCCCCC BDCCCCCC +r 1A70.10 +*Want "DEBR/DEB RM RP,RM 1/-10" BDCCCCCC BDCCCCCC BDCCCCCD BDCCCCCD +r 1A80.08 +*Want "DEBR/DEB RM RFS 1/-10" BDCCCCCD BDCCCCCD +r 1A90.10 +*Want "DEBR/DEB RM RNTE,RZ 7/-10" BE666666 BE666666 BE666666 BE666666 +r 1AA0.10 +*Want "DEBR/DEB RM RP,RM 7/-10" BE666666 BE666666 BE666667 BE666667 +r 1AB0.08 +*Want "DEBR/DEB RM RFS 7/-10" BE666667 BE666667 + + +# Short BFP rounding mode test results - FPCR contents +*Compare +r 1D00.10 +*Want "DEBR/DEB RM RNTE,RZ 1/10 FPCR" 00080000 00080000 00080001 00080001 +r 1D10.10 +*Want "DEBR/DEB RM RP,RM 1/10 FPCR" 00080002 00080002 00080003 00080003 +r 1D20.08 +*Want "DEBR/DEB RM RFS 1/10 FPCR" 00080007 00080007 +r 1D30.10 +*Want "DEBR/DEB RM RNTE,RZ 7/10 FPCR" 00080000 00080000 00080001 00080001 +r 1D40.10 +*Want "DEBR/DEB RM RP,RM 7/10 FPCR" 00080002 00080002 00080003 00080003 +r 1D50.08 +*Want "DEBR/DEB RM RFS 7/10 FPCR" 00080007 00080007 +r 1D60.10 +*Want "DEBR/DEB RM RNTE,RZ 1/-10 FPCR" 00080000 00080000 00080001 00080001 +r 1D70.10 +*Want "DEBR/DEB RM RP,RM 1/-10 FPCR" 00080002 00080002 00080003 00080003 +r 1D80.08 +*Want "DEBR/DEB RM RFS 1/-10 FPCR" 00080007 00080007 +r 1D90.10 +*Want "DEBR/DEB RM RNTE,RZ 7/-10 FPCR" 00080000 00080000 00080001 00080001 +r 1DA0.10 +*Want "DEBR/DEB RM RP,RM 7/-10 FPCR" 00080002 00080002 00080003 00080003 +r 1DB0.08 +*Want "DEBR/DEB RM RFS 7/-10 FPCR" 00080007 00080007 + + + +# Long BFP Non-finite test results +*Compare +r 3000.10 +*Want "DDBR NF -inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 3010.10 +*Want "DDB NF -inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 3020.10 +*Want "DDBR NF -inf/-2" 7FF00000 00000000 7FF00000 00000000 +r 3030.10 +*Want "DDB NF -inf/-2" 7FF00000 00000000 7FF00000 00000000 +r 3040.10 +*Want "DDBR NF -inf/-0" 7FF00000 00000000 7FF00000 00000000 +r 3050.10 +*Want "DDB NF -inf/-0" 7FF00000 00000000 7FF00000 00000000 +r 3060.10 +*Want "DDBR NF -inf/+0" FFF00000 00000000 FFF00000 00000000 +r 3070.10 +*Want "DDB NF -inf/+0" FFF00000 00000000 FFF00000 00000000 +r 3080.10 +*Want "DDBR NF -inf/+2" FFF00000 00000000 FFF00000 00000000 +r 3090.10 +*Want "DDB NF -inf/+2" FFF00000 00000000 FFF00000 00000000 +r 30A0.10 +*Want "DDBR NF -inf/+inf" 7FF80000 00000000 FFF00000 00000000 +r 30B0.10 +*Want "DDB NF -inf/+inf" 7FF80000 00000000 FFF00000 00000000 +r 30C0.10 +*Want "DDBR NF -inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 30D0.10 +*Want "DDB NF -inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 30E0.10 +*Want "DDBR NF -inf/+SNaN" 7FF8A000 00000000 FFF00000 00000000 +r 30F0.10 +*Want "DDB NF -inf/+SNaN" 7FF8A000 00000000 FFF00000 00000000 +r 3100.10 +*Want "DDBR NF -2/-inf" 00000000 00000000 00000000 00000000 +r 3110.10 +*Want "DDB NF -2/-inf" 00000000 00000000 00000000 00000000 +r 3120.10 +*Want "DDBR NF -2/-2" 3FF00000 00000000 3FF00000 00000000 +r 3130.10 +*Want "DDB NF -2/-2" 3FF00000 00000000 3FF00000 00000000 +r 3140.10 +*Want "DDBR NF -2/-0" 7FF00000 00000000 C0000000 00000000 +r 3150.10 +*Want "DDB NF -2/-0" 7FF00000 00000000 C0000000 00000000 +r 3160.10 +*Want "DDBR NF -2/+0" FFF00000 00000000 C0000000 00000000 +r 3170.10 +*Want "DDB NF -2/+0" FFF00000 00000000 C0000000 00000000 +r 3180.10 +*Want "DDBR NF -2/+2" BFF00000 00000000 BFF00000 00000000 +r 3190.10 +*Want "DDB NF -2/+2" BFF00000 00000000 BFF00000 00000000 +r 31A0.10 +*Want "DDBR NF -2/+inf" 80000000 00000000 80000000 00000000 +r 31B0.10 +*Want "DDB NF -2/+inf" 80000000 00000000 80000000 00000000 +r 31C0.10 +*Want "DDBR NF -2/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 31D0.10 +*Want "DDB NF -2/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 31E0.10 +*Want "DDBR NF -2/+SNaN" 7FF8A000 00000000 C0000000 00000000 +r 31F0.10 +*Want "DDB NF -2/+SNaN" 7FF8A000 00000000 C0000000 00000000 +r 3200.10 +*Want "DDBR NF -0/-inf" 00000000 00000000 00000000 00000000 +r 3210.10 +*Want "DDB NF -0/-inf" 00000000 00000000 00000000 00000000 +r 3220.10 +*Want "DDBR NF -0/-2" 00000000 00000000 00000000 00000000 +r 3230.10 +*Want "DDB NF -0/-2" 00000000 00000000 00000000 00000000 +r 3240.10 +*Want "DDBR NF -0/-0" 7FF80000 00000000 80000000 00000000 +r 3250.10 +*Want "DDB NF -0/-0" 7FF80000 00000000 80000000 00000000 +r 3260.10 +*Want "DDBR NF -0/+0" 7FF80000 00000000 80000000 00000000 +r 3270.10 +*Want "DDB NF -0/+0" 7FF80000 00000000 80000000 00000000 +r 3280.10 +*Want "DDBR NF -0/+2" 80000000 00000000 80000000 00000000 +r 3290.10 +*Want "DDB NF -0/+2" 80000000 00000000 80000000 00000000 +r 32A0.10 +*Want "DDBR NF -0/+inf" 80000000 00000000 80000000 00000000 +r 32B0.10 +*Want "DDB NF -0/+inf" 80000000 00000000 80000000 00000000 +r 32C0.10 +*Want "DDBR NF -0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 32D0.10 +*Want "DDB NF -0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 32E0.10 +*Want "DDBR NF -0/+SNaN" 7FF8A000 00000000 80000000 00000000 +r 32F0.10 +*Want "DDB NF -0/+SNaN" 7FF8A000 00000000 80000000 00000000 +r 3300.10 +*Want "DDBR NF +0/-inf" 80000000 00000000 80000000 00000000 +r 3310.10 +*Want "DDB NF +0/-inf" 80000000 00000000 80000000 00000000 +r 3320.10 +*Want "DDBR NF +0/-2" 80000000 00000000 80000000 00000000 +r 3330.10 +*Want "DDB NF +0/-2" 80000000 00000000 80000000 00000000 +r 3340.10 +*Want "DDBR NF +0/-0" 7FF80000 00000000 00000000 00000000 +r 3350.10 +*Want "DDB NF +0/-0" 7FF80000 00000000 00000000 00000000 +r 3360.10 +*Want "DDBR NF +0/+0" 7FF80000 00000000 00000000 00000000 +r 3370.10 +*Want "DDB NF +0/+0" 7FF80000 00000000 00000000 00000000 +r 3380.10 +*Want "DDBR NF +0/+2" 00000000 00000000 00000000 00000000 +r 3390.10 +*Want "DDB NF +0/+2" 00000000 00000000 00000000 00000000 +r 33A0.10 +*Want "DDBR NF +0/+inf" 00000000 00000000 00000000 00000000 +r 33B0.10 +*Want "DDB NF +0/+inf" 00000000 00000000 00000000 00000000 +r 33C0.10 +*Want "DDBR NF +0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 33D0.10 +*Want "DDB NF +0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 33E0.10 +*Want "DDBR NF +0/+SNaN" 7FF8A000 00000000 00000000 00000000 +r 33F0.10 +*Want "DDB NF +0/+SNaN" 7FF8A000 00000000 00000000 00000000 +r 3400.10 +*Want "DDBR NF +2/-inf" 80000000 00000000 80000000 00000000 +r 3410.10 +*Want "DDB NF +2/-inf" 80000000 00000000 80000000 00000000 +r 3420.10 +*Want "DDBR NF +2/-2" BFF00000 00000000 BFF00000 00000000 +r 3430.10 +*Want "DDB NF +2/-2" BFF00000 00000000 BFF00000 00000000 +r 3440.10 +*Want "DDBR NF +2/-0" FFF00000 00000000 40000000 00000000 +r 3450.10 +*Want "DDB NF +2/-0" FFF00000 00000000 40000000 00000000 +r 3460.10 +*Want "DDBR NF +2/+0" 7FF00000 00000000 40000000 00000000 +r 3470.10 +*Want "DDB NF +2/+0" 7FF00000 00000000 40000000 00000000 +r 3480.10 +*Want "DDBR NF +2/+2" 3FF00000 00000000 3FF00000 00000000 +r 3490.10 +*Want "DDB NF +2/+2" 3FF00000 00000000 3FF00000 00000000 +r 34A0.10 +*Want "DDBR NF +2/+inf" 00000000 00000000 00000000 00000000 +r 34B0.10 +*Want "DDB NF +2/+inf" 00000000 00000000 00000000 00000000 +r 34C0.10 +*Want "DDBR NF +2/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 34D0.10 +*Want "DDB NF +2/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 34E0.10 +*Want "DDBR NF +2/+SNaN" 7FF8A000 00000000 40000000 00000000 +r 34F0.10 +*Want "DDB NF +2/+SNaN" 7FF8A000 00000000 40000000 00000000 +r 3500.10 +*Want "DDBR NF +inf/-inf" 7FF80000 00000000 7FF00000 00000000 +r 3510.10 +*Want "DDB NF +inf/-inf" 7FF80000 00000000 7FF00000 00000000 +r 3520.10 +*Want "DDBR NF +inf/-2" FFF00000 00000000 FFF00000 00000000 +r 3530.10 +*Want "DDB NF +inf/-2" FFF00000 00000000 FFF00000 00000000 +r 3540.10 +*Want "DDBR NF +inf/-0" FFF00000 00000000 FFF00000 00000000 +r 3550.10 +*Want "DDB NF +inf/-0" FFF00000 00000000 FFF00000 00000000 +r 3560.10 +*Want "DDBR NF +inf/+0" 7FF00000 00000000 7FF00000 00000000 +r 3570.10 +*Want "DDB NF +inf/+0" 7FF00000 00000000 7FF00000 00000000 +r 3580.10 +*Want "DDBR NF +inf/+2" 7FF00000 00000000 7FF00000 00000000 +r 3590.10 +*Want "DDB NF +inf/+2" 7FF00000 00000000 7FF00000 00000000 +r 35A0.10 +*Want "DDBR NF +inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 35B0.10 +*Want "DDB NF +inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 35C0.10 +*Want "DDBR NF +inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 35D0.10 +*Want "DDB NF +inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 35E0.10 +*Want "DDBR NF +inf/+SNaN" 7FF8A000 00000000 7FF00000 00000000 +r 35F0.10 +*Want "DDB NF +inf/+SNaN" 7FF8A000 00000000 7FF00000 00000000 +r 3600.10 +*Want "DDBR NF -QNaN/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 3610.10 +*Want "DDB NF -QNaN/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 3620.10 +*Want "DDBR NF -QNaN/-2" FFF8B000 00000000 FFF8B000 00000000 +r 3630.10 +*Want "DDB NF -QNaN/-2" FFF8B000 00000000 FFF8B000 00000000 +r 3640.10 +*Want "DDBR NF -QNaN/-0" FFF8B000 00000000 FFF8B000 00000000 +r 3650.10 +*Want "DDB NF -QNaN/-0" FFF8B000 00000000 FFF8B000 00000000 +r 3660.10 +*Want "DDBR NF -QNaN/+0" FFF8B000 00000000 FFF8B000 00000000 +r 3670.10 +*Want "DDB NF -QNaN/+0" FFF8B000 00000000 FFF8B000 00000000 +r 3680.10 +*Want "DDBR NF -QNaN/+2" FFF8B000 00000000 FFF8B000 00000000 +r 3690.10 +*Want "DDB NF -QNaN/+2" FFF8B000 00000000 FFF8B000 00000000 +r 36A0.10 +*Want "DDBR NF -QNaN/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 36B0.10 +*Want "DDB NF -QNaN/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 36C0.10 +*Want "DDBR NF -QNaN/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 36D0.10 +*Want "DDB NF -QNaN/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 36E0.10 +*Want "DDBR NF -QNaN/+SNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 36F0.10 +*Want "DDB NF -QNaN/+SNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 3700.10 +*Want "DDBR NF +SNaN/-inf" 7FF8A000 00000000 7FF0A000 00000000 +r 3710.10 +*Want "DDB NF +SNaN/-inf" 7FF8A000 00000000 7FF0A000 00000000 +r 3720.10 +*Want "DDBR NF +SNaN/-2" 7FF8A000 00000000 7FF0A000 00000000 +r 3730.10 +*Want "DDB NF +SNaN/-2" 7FF8A000 00000000 7FF0A000 00000000 +r 3740.10 +*Want "DDBR NF +SNaN/-0" 7FF8A000 00000000 7FF0A000 00000000 +r 3750.10 +*Want "DDB NF +SNaN/-0" 7FF8A000 00000000 7FF0A000 00000000 +r 3760.10 +*Want "DDBR NF +SNaN/+0" 7FF8A000 00000000 7FF0A000 00000000 +r 3770.10 +*Want "DDB NF +SNaN/+0" 7FF8A000 00000000 7FF0A000 00000000 +r 3780.10 +*Want "DDBR NF +SNaN/+2" 7FF8A000 00000000 7FF0A000 00000000 +r 3790.10 +*Want "DDB NF +SNaN/+2" 7FF8A000 00000000 7FF0A000 00000000 +r 37A0.10 +*Want "DDBR NF +SNaN/+inf" 7FF8A000 00000000 7FF0A000 00000000 +r 37B0.10 +*Want "DDB NF +SNaN/+inf" 7FF8A000 00000000 7FF0A000 00000000 +r 37C0.10 +*Want "DDBR NF +SNaN/-QNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 37D0.10 +*Want "DDB NF +SNaN/-QNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 37E0.10 +*Want "DDBR NF +SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 37F0.10 +*Want "DDB NF +SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 + + +# Long BFP Non-finite test results FPCR contents +*Compare +r 3800.10 +*Want "DDBR/DDB NF -inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3810.10 +*Want "DDBR/DDB NF -inf/-2 FPCR" 00000000 F8000000 00000000 F8000000 +r 3820.10 +*Want "DDBR/DDB NF -inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3830.10 +*Want "DDBR/DDB NF -inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3840.10 +*Want "DDBR/DDB NF -inf/+2 FPCR" 00000000 F8000000 00000000 F8000000 +r 3850.10 +*Want "DDBR/DDB NF -inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3860.10 +*Want "DDBR/DDB NF -inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3870.10 +*Want "DDBR/DDB NF -inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3880.10 +*Want "DDBR/DDB NF -2/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3890.10 +*Want "DDBR/DDB NF -2/-2 FPCR" 00000000 F8000000 00000000 F8000000 +r 38A0.10 +*Want "DDBR/DDB NF -2/-0 FPCR" 00400000 F8004000 00400000 F8004000 +r 38B0.10 +*Want "DDBR/DDB NF -2/+0 FPCR" 00400000 F8004000 00400000 F8004000 +r 38C0.10 +*Want "DDBR/DDB NF -2/+2 FPCR" 00000000 F8000000 00000000 F8000000 +r 38D0.10 +*Want "DDBR/DDB NF -2/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 38E0.10 +*Want "DDBR/DDB NF -2/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 38F0.10 +*Want "DDBR/DDB NF -2/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3900.10 +*Want "DDBR/DDB NF -0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3910.10 +*Want "DDBR/DDB NF -0/-2 FPCR" 00000000 F8000000 00000000 F8000000 +r 3920.10 +*Want "DDBR/DDB NF -0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3930.10 +*Want "DDBR/DDB NF -0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3940.10 +*Want "DDBR/DDB NF -0/+2 FPCR" 00000000 F8000000 00000000 F8000000 +r 3950.10 +*Want "DDBR/DDB NF -0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3960.10 +*Want "DDBR/DDB NF -0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3970.10 +*Want "DDBR/DDB NF -0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3980.10 +*Want "DDBR/DDB NF +0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3990.10 +*Want "DDBR/DDB NF +0/-2 FPCR" 00000000 F8000000 00000000 F8000000 +r 39A0.10 +*Want "DDBR/DDB NF +0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 39B0.10 +*Want "DDBR/DDB NF +0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 39C0.10 +*Want "DDBR/DDB NF +0/+2 FPCR" 00000000 F8000000 00000000 F8000000 +r 39D0.10 +*Want "DDBR/DDB NF +0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 39E0.10 +*Want "DDBR/DDB NF +0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 39F0.10 +*Want "DDBR/DDB NF +0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3A00.10 +*Want "DDBR/DDB NF +2/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3A10.10 +*Want "DDBR/DDB NF +2/-2 FPCR" 00000000 F8000000 00000000 F8000000 +r 3A20.10 +*Want "DDBR/DDB NF +2/-0 FPCR" 00400000 F8004000 00400000 F8004000 +r 3A30.10 +*Want "DDBR/DDB NF +2/+0 FPCR" 00400000 F8004000 00400000 F8004000 +r 3A40.10 +*Want "DDBR/DDB NF +2/+2 FPCR" 00000000 F8000000 00000000 F8000000 +r 3A50.10 +*Want "DDBR/DDB NF +2/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3A60.10 +*Want "DDBR/DDB NF +2/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3A70.10 +*Want "DDBR/DDB NF +2/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3A80.10 +*Want "DDBR/DDB NF +inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3A90.10 +*Want "DDBR/DDB NF +inf/-2 FPCR" 00000000 F8000000 00000000 F8000000 +r 3AA0.10 +*Want "DDBR/DDB NF +inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3AB0.10 +*Want "DDBR/DDB NF +inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3AC0.10 +*Want "DDBR/DDB NF +inf/+2 FPCR" 00000000 F8000000 00000000 F8000000 +r 3AD0.10 +*Want "DDBR/DDB NF +inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3AE0.10 +*Want "DDBR/DDB NF +inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3AF0.10 +*Want "DDBR/DDB NF +inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3B00.10 +*Want "DDBR/DDB NF -QNaN/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3B10.10 +*Want "DDBR/DDB NF -QNaN/-2 FPCR" 00000000 F8000000 00000000 F8000000 +r 3B20.10 +*Want "DDBR/DDB NF -QNaN/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3B30.10 +*Want "DDBR/DDB NF -QNaN/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3B40.10 +*Want "DDBR/DDB NF -QNaN/+2 FPCR" 00000000 F8000000 00000000 F8000000 +r 3B50.10 +*Want "DDBR/DDB NF -QNaN/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3B60.10 +*Want "DDBR/DDB NF -QNaN/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3B70.10 +*Want "DDBR/DDB NF -QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3B80.10 +*Want "DDBR/DDB NF +SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3B90.10 +*Want "DDBR/DDB NF +SNaN/-2 FPCR" 00800000 F8008000 00800000 F8008000 +r 3BA0.10 +*Want "DDBR/DDB NF +SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3BB0.10 +*Want "DDBR/DDB NF +SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3BC0.10 +*Want "DDBR/DDB NF +SNaN/+2 FPCR" 00800000 F8008000 00800000 F8008000 +r 3BD0.10 +*Want "DDBR/DDB NF +SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3BE0.10 +*Want "DDBR/DDB NF +SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3BF0.10 +*Want "DDBR/DDB NF +SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 + + +r 3C00.10 +*Want "DDBR max/min" 7FF00000 00000000 630FFFFF FFFFFFFF +r 3C10.10 +*Want "DDB max/min" 7FF00000 00000000 630FFFFF FFFFFFFF +r 3C20.10 +*Want "DDBR min/2.0" 00080000 00000000 60000000 00000000 +r 3C30.10 +*Want "DDB min/2.0" 00080000 00000000 60000000 00000000 +r 3C40.10 +*Want "DDBR 1.0/10.0" 3FB99999 9999999A 3FB99999 9999999A +r 3C50.10 +*Want "DDB 1.0/10.0" 3FB99999 9999999A 3FB99999 9999999A +r 3C60.10 +*Want "DDBR 7.0/10.0" 3FE66666 66666666 3FE66666 66666666 +r 3C70.10 +*Want "DDB 7.0/10.0" 3FE66666 66666666 3FE66666 66666666 +r 3C80.10 +*Want "DDBR 1.0/-10.0" BFB99999 9999999A BFB99999 9999999A +r 3C90.10 +*Want "DDB 1.0/-10.0" BFB99999 9999999A BFB99999 9999999A +r 3CA0.10 +*Want "DDBR 7.0/-10.0" BFE66666 66666666 BFE66666 66666666 +r 3CB0.10 +*Want "DDB 7.0/-10.0" BFE66666 66666666 BFE66666 66666666 + + +# Long BFP finite test results - FPCR contents +*Compare +r 3E00.10 +*Want "DDBR/DDB max/min FPCR" 00280000 F8002000 00280000 F8002000 +r 3E10.10 +*Want "DDBR/DDB min/2.0 FPCR" 00000000 F8001000 00000000 F8001000 +r 3E20.10 +*Want "DDBR/DDB 1.0/10.0 FPCR" 00080000 F8000C00 00080000 F8000C00 +r 3E30.10 +*Want "DDBR/DDB 7.0/10.0 FPCR" 00080000 F8000800 00080000 F8000800 +r 3E40.10 +*Want "DDBR/DDB 1.0/-10.0 FPCR" 00080000 F8000C00 00080000 F8000C00 +r 3E50.10 +*Want "DDBR/DDB 7.0/-10.0 FPCR" 00080000 F8000800 00080000 F8000800 + + +# Long BFP rounding mode test results +*Compare +r 4000.10 +*Want "DDBR/DDB RM RNTE 1/10" 3FB99999 9999999A 3FB99999 9999999A +r 4010.10 +*Want "DDBR/DDB RM RZ 1/10" 3FB99999 99999999 3FB99999 99999999 +r 4020.10 +*Want "DDBR/DDB RM RP 1/10" 3FB99999 9999999A 3FB99999 9999999A +r 4030.10 +*Want "DDBR/DDB RM RM 1/10" 3FB99999 99999999 3FB99999 99999999 +r 4040.10 +*Want "DDBR/DDB RM RFS 1/10" 3FB99999 99999999 3FB99999 99999999 +r 4050.10 +*Want "DDBR/DDB RM RNTE 7/10" 3FE66666 66666666 3FE66666 66666666 +r 4060.10 +*Want "DDBR/DDB RM RZ 7/10" 3FE66666 66666666 3FE66666 66666666 +r 4070.10 +*Want "DDBR/DDB RM RP 7/10" 3FE66666 66666667 3FE66666 66666667 +r 4080.10 +*Want "DDBR/DDB RM RM 7/10" 3FE66666 66666666 3FE66666 66666666 +r 4090.10 +*Want "DDBR/DDB RM RFS 7/10" 3FE66666 66666667 3FE66666 66666667 +r 40A0.10 +*Want "DDBR/DDB RM RNTE 1/-10" BFB99999 9999999A BFB99999 9999999A +r 40B0.10 +*Want "DDBR/DDB RM RZ 1/-10" BFB99999 99999999 BFB99999 99999999 +r 40C0.10 +*Want "DDBR/DDB RM RP 1/-10" BFB99999 99999999 BFB99999 99999999 +r 40D0.10 +*Want "DDBR/DDB RM RM 1/-10" BFB99999 9999999A BFB99999 9999999A +r 40E0.10 +*Want "DDBR/DDB RM RFS 1/-10" BFB99999 99999999 BFB99999 99999999 +r 40F0.10 +*Want "DDBR/DDB RM RNTE 7/-10" BFE66666 66666666 BFE66666 66666666 +r 4100.10 +*Want "DDBR/DDB RM RZ 7/-10" BFE66666 66666666 BFE66666 66666666 +r 4110.10 +*Want "DDBR/DDB RM RP 7/-10" BFE66666 66666666 BFE66666 66666666 +r 4120.10 +*Want "DDBR/DDB RM RM 7/-10" BFE66666 66666667 BFE66666 66666667 +r 4130.10 +*Want "DDBR/DDB RM RFS 7/-10" BFE66666 66666667 BFE66666 66666667 + + + +# Long BFP rounding mode test results - FPCR contents +*Compare +r 4500.10 +*Want "DDBR/DDB RM RNTE,RZ 1/10 FPCR" 00080000 00080000 00080001 00080001 +r 4510.10 +*Want "DDBR/DDB RM RP,RM 1/10 FPCR" 00080002 00080002 00080003 00080003 +r 4520.08 +*Want "DDBR/DDB RM RFS 1/10 FPCR" 00080007 00080007 +r 4530.10 +*Want "DDBR/DDB RM RNTE,RZ 7/10 FPCR" 00080000 00080000 00080001 00080001 +r 4540.10 +*Want "DDBR/DDB RM RP,RM 7/10 FPCR" 00080002 00080002 00080003 00080003 +r 4550.08 +*Want "DDBR/DDB RM RFS 7/10 FPCR" 00080007 00080007 +r 4560.10 +*Want "DDBR/DDB RM RNTE,RZ 1/-10 FPCR" 00080000 00080000 00080001 00080001 +r 4570.10 +*Want "DDBR/DDB RM RP,RM 1/-10 FPCR" 00080002 00080002 00080003 00080003 +r 4580.08 +*Want "DDBR/DDB RM RFS 1/-10 FPCR" 00080007 00080007 +r 4590.10 +*Want "DDBR/DDB RM RNTE,RZ 7/-10 FPCR" 00080000 00080000 00080001 00080001 +r 45A0.10 +*Want "DDBR/DDB RM RP,RM 7/-10 FPCR" 00080002 00080002 00080003 00080003 +r 45B0.08 +*Want "DDBR/DDB RM RFS 7/-10 FPCR" 00080007 00080007 + +# Extended BFP Non-finite test results +*Compare +r 5000.10 +*Want "DXBR NT NF -inf/-inf" 7FFF8000 00000000 00000000 00000000 +r 5010.10 +*Want "DXBR Tr NF -inf/-inf" FFFF0000 00000000 00000000 00000000 +r 5020.10 +*Want "DXBR NT NF -inf/-2" 7FFF0000 00000000 00000000 00000000 +r 5030.10 +*Want "DXBR Tr NF -inf/-2" 7FFF0000 00000000 00000000 00000000 +r 5040.10 +*Want "DXBR NT NF -inf/-0" 7FFF0000 00000000 00000000 00000000 +r 5050.10 +*Want "DXBR Tr NF -inf/-0" 7FFF0000 00000000 00000000 00000000 +r 5060.10 +*Want "DXBR NT NF -inf/+0" FFFF0000 00000000 00000000 00000000 +r 5070.10 +*Want "DXBR Tr NF -inf/+0" FFFF0000 00000000 00000000 00000000 +r 5080.10 +*Want "DXBR NT NF -inf/+2" FFFF0000 00000000 00000000 00000000 +r 5090.10 +*Want "DXBR Tr NF -inf/+2" FFFF0000 00000000 00000000 00000000 +r 50A0.10 +*Want "DXBR NT NF -inf/+inf" 7FFF8000 00000000 00000000 00000000 +r 50B0.10 +*Want "DXBR Tr NF -inf/+inf" FFFF0000 00000000 00000000 00000000 +r 50C0.10 +*Want "DXBR NT NF -inf/-QNaN" FFFF8B00 00000000 00000000 00000000 +r 50D0.10 +*Want "DXBR Tr NF -inf/-QNaN" FFFF8B00 00000000 00000000 00000000 +r 50E0.10 +*Want "DXBR NT NF -inf/+SNaN" 7FFF8A00 00000000 00000000 00000000 +r 50F0.10 +*Want "DXBR Tr NF -inf/+SNaN" FFFF0000 00000000 00000000 00000000 +r 5100.10 +*Want "DXBR NT NF -2/-inf" 00000000 00000000 00000000 00000000 +r 5110.10 +*Want "DXBR Tr NF -2/-inf" 00000000 00000000 00000000 00000000 +r 5120.10 +*Want "DXBR NT NF -2/-2" 3FFF0000 00000000 00000000 00000000 +r 5130.10 +*Want "DXBR Tr NF -2/-2" 3FFF0000 00000000 00000000 00000000 +r 5140.10 +*Want "DXBR NT NF -2/-0" 7FFF0000 00000000 00000000 00000000 +r 5150.10 +*Want "DXBR Tr NF -2/-0" C0000000 00000000 00000000 00000000 +r 5160.10 +*Want "DXBR NT NF -2/+0" FFFF0000 00000000 00000000 00000000 +r 5170.10 +*Want "DXBR Tr NF -2/+0" C0000000 00000000 00000000 00000000 +r 5180.10 +*Want "DXBR NT NF -2/+2" BFFF0000 00000000 00000000 00000000 +r 5190.10 +*Want "DXBR Tr NF -2/+2" BFFF0000 00000000 00000000 00000000 +r 51A0.10 +*Want "DXBR NT NF -2/+inf" 80000000 00000000 00000000 00000000 +r 51B0.10 +*Want "DXBR Tr NF -2/+inf" 80000000 00000000 00000000 00000000 +r 51C0.10 +*Want "DXBR NT NF -2/-QNaN" FFFF8B00 00000000 00000000 00000000 +r 51D0.10 +*Want "DXBR Tr NF -2/-QNaN" FFFF8B00 00000000 00000000 00000000 +r 51E0.10 +*Want "DXBR NT NF -2/+SNaN" 7FFF8A00 00000000 00000000 00000000 +r 51F0.10 +*Want "DXBR Tr NF -2/+SNaN" C0000000 00000000 00000000 00000000 +r 5200.10 +*Want "DXBR NT NF -0/-inf" 00000000 00000000 00000000 00000000 +r 5210.10 +*Want "DXBR Tr NF -0/-inf" 00000000 00000000 00000000 00000000 +r 5220.10 +*Want "DXBR NT NF -0/-2" 00000000 00000000 00000000 00000000 +r 5230.10 +*Want "DXBR Tr NF -0/-2" 00000000 00000000 00000000 00000000 +r 5240.10 +*Want "DXBR NT NF -0/-0" 7FFF8000 00000000 00000000 00000000 +r 5250.10 +*Want "DXBR Tr NF -0/-0" 80000000 00000000 00000000 00000000 +r 5260.10 +*Want "DXBR NT NF -0/+0" 7FFF8000 00000000 00000000 00000000 +r 5270.10 +*Want "DXBR Tr NF -0/+0" 80000000 00000000 00000000 00000000 +r 5280.10 +*Want "DXBR NT NF -0/+2" 80000000 00000000 00000000 00000000 +r 5290.10 +*Want "DXBR Tr NF -0/+2" 80000000 00000000 00000000 00000000 +r 52A0.10 +*Want "DXBR NT NF -0/+inf" 80000000 00000000 00000000 00000000 +r 52B0.10 +*Want "DXBR Tr NF -0/+inf" 80000000 00000000 00000000 00000000 +r 52C0.10 +*Want "DXBR NT NF -0/-QNaN" FFFF8B00 00000000 00000000 00000000 +r 52D0.10 +*Want "DXBR Tr NF -0/-QNaN" FFFF8B00 00000000 00000000 00000000 +r 52E0.10 +*Want "DXBR NT NF -0/+SNaN" 7FFF8A00 00000000 00000000 00000000 +r 52F0.10 +*Want "DXBR Tr NF -0/+SNaN" 80000000 00000000 00000000 00000000 +r 5300.10 +*Want "DXBR NT NF +0/-inf" 80000000 00000000 00000000 00000000 +r 5310.10 +*Want "DXBR Tr NF +0/-inf" 80000000 00000000 00000000 00000000 +r 5320.10 +*Want "DXBR NT NF +0/-2" 80000000 00000000 00000000 00000000 +r 5330.10 +*Want "DXBR Tr NF +0/-2" 80000000 00000000 00000000 00000000 +r 5340.10 +*Want "DXBR NT NF +0/-0" 7FFF8000 00000000 00000000 00000000 +r 5350.10 +*Want "DXBR Tr NF +0/-0" 00000000 00000000 00000000 00000000 +r 5360.10 +*Want "DXBR NT NF +0/+0" 7FFF8000 00000000 00000000 00000000 +r 5370.10 +*Want "DXBR Tr NF +0/+0" 00000000 00000000 00000000 00000000 +r 5380.10 +*Want "DXBR NT NF +0/+2" 00000000 00000000 00000000 00000000 +r 5390.10 +*Want "DXBR Tr NF +0/+2" 00000000 00000000 00000000 00000000 +r 53A0.10 +*Want "DXBR NT NF +0/+inf" 00000000 00000000 00000000 00000000 +r 53B0.10 +*Want "DXBR Tr NF +0/+inf" 00000000 00000000 00000000 00000000 +r 53C0.10 +*Want "DXBR NT NF +0/-QNaN" FFFF8B00 00000000 00000000 00000000 +r 53D0.10 +*Want "DXBR Tr NF +0/-QNaN" FFFF8B00 00000000 00000000 00000000 +r 53E0.10 +*Want "DXBR NT NF +0/+SNaN" 7FFF8A00 00000000 00000000 00000000 +r 53F0.10 +*Want "DXBR Tr NF +0/+SNaN" 00000000 00000000 00000000 00000000 +r 5400.10 +*Want "DXBR NT NF +2/-inf" 80000000 00000000 00000000 00000000 +r 5410.10 +*Want "DXBR Tr NF +2/-inf" 80000000 00000000 00000000 00000000 +r 5420.10 +*Want "DXBR NT NF +2/-2" BFFF0000 00000000 00000000 00000000 +r 5430.10 +*Want "DXBR Tr NF +2/-2" BFFF0000 00000000 00000000 00000000 +r 5440.10 +*Want "DXBR NT NF +2/-0" FFFF0000 00000000 00000000 00000000 +r 5450.10 +*Want "DXBR Tr NF +2/-0" 40000000 00000000 00000000 00000000 +r 5460.10 +*Want "DXBR NT NF +2/+0" 7FFF0000 00000000 00000000 00000000 +r 5470.10 +*Want "DXBR Tr NF +2/+0" 40000000 00000000 00000000 00000000 +r 5480.10 +*Want "DXBR NT NF +2/+2" 3FFF0000 00000000 00000000 00000000 +r 5490.10 +*Want "DXBR Tr NF +2/+2" 3FFF0000 00000000 00000000 00000000 +r 54A0.10 +*Want "DXBR NT NF +2/+inf" 00000000 00000000 00000000 00000000 +r 54B0.10 +*Want "DXBR Tr NF +2/+inf" 00000000 00000000 00000000 00000000 +r 54C0.10 +*Want "DXBR NT NF +2/-QNaN" FFFF8B00 00000000 00000000 00000000 +r 54D0.10 +*Want "DXBR Tr NF +2/-QNaN" FFFF8B00 00000000 00000000 00000000 +r 54E0.10 +*Want "DXBR NT NF +2/+SNaN" 7FFF8A00 00000000 00000000 00000000 +r 54F0.10 +*Want "DXBR Tr NF +2/+SNaN" 40000000 00000000 00000000 00000000 +r 5500.10 +*Want "DXBR NT NF +inf/-inf" 7FFF8000 00000000 00000000 00000000 +r 5510.10 +*Want "DXBR Tr NF +inf/-inf" 7FFF0000 00000000 00000000 00000000 +r 5520.10 +*Want "DXBR NT NF +inf/-2" FFFF0000 00000000 00000000 00000000 +r 5530.10 +*Want "DXBR Tr NF +inf/-2" FFFF0000 00000000 00000000 00000000 +r 5540.10 +*Want "DXBR NT NF +inf/-0" FFFF0000 00000000 00000000 00000000 +r 5550.10 +*Want "DXBR Tr NF +inf/-0" FFFF0000 00000000 00000000 00000000 +r 5560.10 +*Want "DXBR NT NF +inf/+0" 7FFF0000 00000000 00000000 00000000 +r 5570.10 +*Want "DXBR Tr NF +inf/+0" 7FFF0000 00000000 00000000 00000000 +r 5580.10 +*Want "DXBR NT NF +inf/+2" 7FFF0000 00000000 00000000 00000000 +r 5590.10 +*Want "DXBR Tr NF +inf/+2" 7FFF0000 00000000 00000000 00000000 +r 55A0.10 +*Want "DXBR NT NF +inf/+inf" 7FFF8000 00000000 00000000 00000000 +r 55B0.10 +*Want "DXBR Tr NF +inf/+inf" 7FFF0000 00000000 00000000 00000000 +r 55C0.10 +*Want "DXBR NT NF +inf/-QNaN" FFFF8B00 00000000 00000000 00000000 +r 55D0.10 +*Want "DXBR Tr NF +inf/-QNaN" FFFF8B00 00000000 00000000 00000000 +r 55E0.10 +*Want "DXBR NT NF +inf/+SNaN" 7FFF8A00 00000000 00000000 00000000 +r 55F0.10 +*Want "DXBR Tr NF +inf/+SNaN" 7FFF0000 00000000 00000000 00000000 +r 5600.10 +*Want "DXBR NT NF -QNaN/-inf" FFFF8B00 00000000 00000000 00000000 +r 5610.10 +*Want "DXBR Tr NF -QNaN/-inf" FFFF8B00 00000000 00000000 00000000 +r 5620.10 +*Want "DXBR NT NF -QNaN/-2" FFFF8B00 00000000 00000000 00000000 +r 5630.10 +*Want "DXBR Tr NF -QNaN/-2" FFFF8B00 00000000 00000000 00000000 +r 5640.10 +*Want "DXBR NT NF -QNaN/-0" FFFF8B00 00000000 00000000 00000000 +r 5650.10 +*Want "DXBR Tr NF -QNaN/-0" FFFF8B00 00000000 00000000 00000000 +r 5660.10 +*Want "DXBR NT NF -QNaN/+0" FFFF8B00 00000000 00000000 00000000 +r 5670.10 +*Want "DXBR Tr NF -QNaN/+0" FFFF8B00 00000000 00000000 00000000 +r 5680.10 +*Want "DXBR NT NF -QNaN/+2" FFFF8B00 00000000 00000000 00000000 +r 5690.10 +*Want "DXBR Tr NF -QNaN/+2" FFFF8B00 00000000 00000000 00000000 +r 56A0.10 +*Want "DXBR NT NF -QNaN/+inf" FFFF8B00 00000000 00000000 00000000 +r 56B0.10 +*Want "DXBR Tr NF -QNaN/+inf" FFFF8B00 00000000 00000000 00000000 +r 56C0.10 +*Want "DXBR NT NF -QNaN/-QNaN" FFFF8B00 00000000 00000000 00000000 +r 56D0.10 +*Want "DXBR Tr NF -QNaN/-QNaN" FFFF8B00 00000000 00000000 00000000 +r 56E0.10 +*Want "DXBR NT NF -QNaN/+SNaN" 7FFF8A00 00000000 00000000 00000000 +r 56F0.10 +*Want "DXBR Tr NF -QNaN/+SNaN" FFFF8B00 00000000 00000000 00000000 +r 5700.10 +*Want "DXBR NT NF +SNaN/-inf" 7FFF8A00 00000000 00000000 00000000 +r 5710.10 +*Want "DXBR Tr NF +SNaN/-inf" 7FFF0A00 00000000 00000000 00000000 +r 5720.10 +*Want "DXBR NT NF +SNaN/-2" 7FFF8A00 00000000 00000000 00000000 +r 5730.10 +*Want "DXBR Tr NF +SNaN/-2" 7FFF0A00 00000000 00000000 00000000 +r 5740.10 +*Want "DXBR NT NF +SNaN/-0" 7FFF8A00 00000000 00000000 00000000 +r 5750.10 +*Want "DXBR Tr NF +SNaN/-0" 7FFF0A00 00000000 00000000 00000000 +r 5760.10 +*Want "DXBR NT NF +SNaN/+0" 7FFF8A00 00000000 00000000 00000000 +r 5770.10 +*Want "DXBR Tr NF +SNaN/+0" 7FFF0A00 00000000 00000000 00000000 +r 5780.10 +*Want "DXBR NT NF +SNaN/+2" 7FFF8A00 00000000 00000000 00000000 +r 5790.10 +*Want "DXBR Tr NF +SNaN/+2" 7FFF0A00 00000000 00000000 00000000 +r 57A0.10 +*Want "DXBR NT NF +SNaN/+inf" 7FFF8A00 00000000 00000000 00000000 +r 57B0.10 +*Want "DXBR Tr NF +SNaN/+inf" 7FFF0A00 00000000 00000000 00000000 +r 57C0.10 +*Want "DXBR NT NF +SNaN/-QNaN" 7FFF8A00 00000000 00000000 00000000 +r 57D0.10 +*Want "DXBR Tr NF +SNaN/-QNaN" 7FFF0A00 00000000 00000000 00000000 +r 57E0.10 +*Want "DXBR NT NF +SNaN/+SNaN" 7FFF8A00 00000000 00000000 00000000 +r 57F0.10 +*Want "DXBR Tr NF +SNaN/+SNaN" 7FFF0A00 00000000 00000000 00000000 + + + +# Extended BFP Non-finite test results FPCR contents +*Compare +r 5800.08 +*Want "DXBR NF -inf/-inf FPCR" 00800000 F8008000 +r 5810.08 +*Want "DXBR NF -inf/-2 FPCR" 00000000 F8000000 +r 5820.08 +*Want "DXBR NF -inf/-0 FPCR" 00000000 F8000000 +r 5830.08 +*Want "DXBR NF -inf/+0 FPCR" 00000000 F8000000 +r 5840.08 +*Want "DXBR NF -inf/+2 FPCR" 00000000 F8000000 +r 5850.08 +*Want "DXBR NF -inf/+inf FPCR" 00800000 F8008000 +r 5860.08 +*Want "DXBR NF -inf/-QNaN FPCR" 00000000 F8000000 +r 5870.08 +*Want "DXBR NF -inf/+SNaN FPCR" 00800000 F8008000 +r 5880.08 +*Want "DXBR NF -2/-inf FPCR" 00000000 F8000000 +r 5890.08 +*Want "DXBR NF -2/-2 FPCR" 00000000 F8000000 +r 58A0.08 +*Want "DXBR NF -2/-0 FPCR" 00400000 F8004000 +r 58B0.08 +*Want "DXBR NF -2/+0 FPCR" 00400000 F8004000 +r 58C0.08 +*Want "DXBR NF -2/+2 FPCR" 00000000 F8000000 +r 58D0.08 +*Want "DXBR NF -2/+inf FPCR" 00000000 F8000000 +r 58E0.08 +*Want "DXBR NF -2/-QNaN FPCR" 00000000 F8000000 +r 58F0.08 +*Want "DXBR NF -2/+SNaN FPCR" 00800000 F8008000 +r 5900.08 +*Want "DXBR NF -0/-inf FPCR" 00000000 F8000000 +r 5910.08 +*Want "DXBR NF -0/-2 FPCR" 00000000 F8000000 +r 5920.08 +*Want "DXBR NF -0/-0 FPCR" 00800000 F8008000 +r 5930.08 +*Want "DXBR NF -0/+0 FPCR" 00800000 F8008000 +r 5940.08 +*Want "DXBR NF -0/+2 FPCR" 00000000 F8000000 +r 5950.08 +*Want "DXBR NF -0/+inf FPCR" 00000000 F8000000 +r 5960.08 +*Want "DXBR NF -0/-QNaN FPCR" 00000000 F8000000 +r 5970.08 +*Want "DXBR NF -0/+SNaN FPCR" 00800000 F8008000 +r 5980.08 +*Want "DXBR NF +0/-inf FPCR" 00000000 F8000000 +r 5990.08 +*Want "DXBR NF +0/-2 FPCR" 00000000 F8000000 +r 59A0.08 +*Want "DXBR NF +0/-0 FPCR" 00800000 F8008000 +r 59B0.08 +*Want "DXBR NF +0/+0 FPCR" 00800000 F8008000 +r 59C0.08 +*Want "DXBR NF +0/+2 FPCR" 00000000 F8000000 +r 59D0.08 +*Want "DXBR NF +0/+inf FPCR" 00000000 F8000000 +r 59E0.08 +*Want "DXBR NF +0/-QNaN FPCR" 00000000 F8000000 +r 59F0.08 +*Want "DXBR NF +0/+SNaN FPCR" 00800000 F8008000 +r 5A00.08 +*Want "DXBR NF +2/-inf FPCR" 00000000 F8000000 +r 5A10.08 +*Want "DXBR NF +2/-2 FPCR" 00000000 F8000000 +r 5A20.08 +*Want "DXBR NF +2/-0 FPCR" 00400000 F8004000 +r 5A30.08 +*Want "DXBR NF +2/+0 FPCR" 00400000 F8004000 +r 5A40.08 +*Want "DXBR NF +2/+2 FPCR" 00000000 F8000000 +r 5A50.08 +*Want "DXBR NF +2/+inf FPCR" 00000000 F8000000 +r 5A60.08 +*Want "DXBR NF +2/-QNaN FPCR" 00000000 F8000000 +r 5A70.08 +*Want "DXBR NF +2/+SNaN FPCR" 00800000 F8008000 +r 5A80.08 +*Want "DXBR NF +inf/-inf FPCR" 00800000 F8008000 +r 5A90.08 +*Want "DXBR NF +inf/-2 FPCR" 00000000 F8000000 +r 5AA0.08 +*Want "DXBR NF +inf/-0 FPCR" 00000000 F8000000 +r 5AB0.08 +*Want "DXBR NF +inf/+0 FPCR" 00000000 F8000000 +r 5AC0.08 +*Want "DXBR NF +inf/+2 FPCR" 00000000 F8000000 +r 5AD0.08 +*Want "DXBR NF +inf/+inf FPCR" 00800000 F8008000 +r 5AE0.08 +*Want "DXBR NF +inf/-QNaN FPCR" 00000000 F8000000 +r 5AF0.08 +*Want "DXBR NF +inf/+SNaN FPCR" 00800000 F8008000 +r 5B00.08 +*Want "DXBR NF -QNaN/-inf FPCR" 00000000 F8000000 +r 5B10.08 +*Want "DXBR NF -QNaN/-2 FPCR" 00000000 F8000000 +r 5B20.08 +*Want "DXBR NF -QNaN/-0 FPCR" 00000000 F8000000 +r 5B30.08 +*Want "DXBR NF -QNaN/+0 FPCR" 00000000 F8000000 +r 5B40.08 +*Want "DXBR NF -QNaN/+2 FPCR" 00000000 F8000000 +r 5B50.08 +*Want "DXBR NF -QNaN/+inf FPCR" 00000000 F8000000 +r 5B60.08 +*Want "DXBR NF -QNaN/-QNaN FPCR" 00000000 F8000000 +r 5B70.08 +*Want "DXBR NF -QNaN/+SNaN FPCR" 00800000 F8008000 +r 5B80.08 +*Want "DXBR NF +SNaN/-inf FPCR" 00800000 F8008000 +r 5B90.08 +*Want "DXBR NF +SNaN/-2 FPCR" 00800000 F8008000 +r 5BA0.08 +*Want "DXBR NF +SNaN/-0 FPCR" 00800000 F8008000 +r 5BB0.08 +*Want "DXBR NF +SNaN/+0 FPCR" 00800000 F8008000 +r 5BC0.08 +*Want "DXBR NF +SNaN/+2 FPCR" 00800000 F8008000 +r 5BD0.08 +*Want "DXBR NF +SNaN/+inf FPCR" 00800000 F8008000 +r 5BE0.08 +*Want "DXBR NF +SNaN/-QNaN FPCR" 00800000 F8008000 +r 5BF0.08 +*Want "DXBR NF +SNaN/+SNaN FPCR" 00800000 F8008000 + + +# Extended BFP finite test results +*Compare +r 5C00.10 +*Want "DXBR NT max/min" 7FFF0000 00000000 00000000 00000000 +r 5C10.10 +*Want "DXBR Tr max/min" 606CFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 5C20.10 +*Want "DXBR NT min/2.0" 00008000 00000000 00000000 00000000 +r 5C30.10 +*Want "DXBR Tr min/2.0" 60000000 00000000 00000000 00000000 +r 5C40.10 +*Want "DXBR NT 1.0/10.0" 3FFB9999 99999999 99999999 9999999A +r 5C50.10 +*Want "DXBR Tr 1.0/10.0" 3FFB9999 99999999 99999999 9999999A +r 5C60.10 +*Want "DXBR NT 7.0/10.0" 3FFE6666 66666666 66666666 66666666 +r 5C70.10 +*Want "DXBR Tr 7.0/10.0" 3FFE6666 66666666 66666666 66666666 +r 5C80.10 +*Want "DXBR NT 1.0/-10.0" BFFB9999 99999999 99999999 9999999A +r 5C90.10 +*Want "DXBR Tr 1.0/-10.0" BFFB9999 99999999 99999999 9999999A +r 5CA0.10 +*Want "DXBR NT 7.0/-10.0" BFFE6666 66666666 66666666 66666666 +r 5CB0.10 +*Want "DXBR Tr 7.0/-10.0" BFFE6666 66666666 66666666 66666666 + + +# Extended BFP finite test results - FPCR contents +*Compare +r 5E00.08 +*Want "DXBR max/min FPCR" 00280000 F8002000 +r 5E10.08 +*Want "DXBR min/2.0 FPCR" 00000000 F8001000 +r 5E20.08 +*Want "DXBR 1.0/10.0 FPCR" 00080000 F8000C00 +r 5E30.08 +*Want "DXBR 7.0/10.0 FPCR" 00080000 F8000800 +r 5E40.08 +*Want "DXBR 1.0/-10.0 FPCR" 00080000 F8000C00 +r 5E50.08 +*Want "DXBR 7.0/-10.0 FPCR" 00080000 F8000800 + + +# Extended BFP rounding mode test results +*Compare +r 6000.10 +*Want "DXBR RM RNTE 1/10" 3FFB9999 99999999 99999999 9999999A +r 6010.10 +*Want "DXBR RM RZ 1/10" 3FFB9999 99999999 99999999 99999999 +r 6020.10 +*Want "DXBR RM RP 1/10" 3FFB9999 99999999 99999999 9999999A +r 6030.10 +*Want "DXBR RM RM 1/10" 3FFB9999 99999999 99999999 99999999 +r 6040.10 +*Want "DXBR RM RFS 1/10" 3FFB9999 99999999 99999999 99999999 +r 6050.10 +*Want "DXBR RM RNTE 7/10" 3FFE6666 66666666 66666666 66666666 +r 6060.10 +*Want "DXBR RM RZ 7/10" 3FFE6666 66666666 66666666 66666666 +r 6070.10 +*Want "DXBR RM RP 7/10" 3FFE6666 66666666 66666666 66666667 +r 6080.10 +*Want "DXBR RM RM 7/10" 3FFE6666 66666666 66666666 66666666 +r 6090.10 +*Want "DXBR RM RFS 7/10" 3FFE6666 66666666 66666666 66666667 +r 60A0.10 +*Want "DXBR RM RNTE 1/-10" BFFB9999 99999999 99999999 9999999A +r 60B0.10 +*Want "DXBR RM RZ 1/-10" BFFB9999 99999999 99999999 99999999 +r 60C0.10 +*Want "DXBR RM RP 1/-10" BFFB9999 99999999 99999999 99999999 +r 60D0.10 +*Want "DXBR RM RM 1/-10" BFFB9999 99999999 99999999 9999999A +r 60E0.10 +*Want "DXBR RM RFS 1/-10" BFFB9999 99999999 99999999 99999999 +r 60F0.10 +*Want "DXBR RM RNTE 7/-10" BFFE6666 66666666 66666666 66666666 +r 6100.10 +*Want "DXBR RM RZ 7/-10" BFFE6666 66666666 66666666 66666666 +r 6110.10 +*Want "DXBR RM RP 7/-10" BFFE6666 66666666 66666666 66666666 +r 6120.10 +*Want "DXBR RM RM 7/-10" BFFE6666 66666666 66666666 66666667 +r 6130.10 +*Want "DXBR RM RFS 7/-10" BFFE6666 66666666 66666666 66666667 + + + +# Extended BFP rounding mode test results - FPCR contents +*Compare +r 6A00.10 +*Want "DXBR RM RTNE,RZ,RP,RM 1/10 FPCR" 00080000 00080001 00080002 00080003 +r 6A10.04 +*Want "DXBR RM RFS 1/10 FPCR" 00080007 +r 6A20.10 +*Want "DXBR RM RTNE,RZ,RP,RM 7/10 FPCR" 00080000 00080001 00080002 00080003 +r 6A30.04 +*Want "DXBR RM RFS 7/10 FPCR" 00080007 +r 6A40.10 +*Want "DXBR RM RTNE,RZ,RP,RM 1/-10 FPCR" 00080000 00080001 00080002 00080003 +r 6A50.04 +*Want "DXBR RM RFS 1/-10 FPCR" 00080007 +r 6A60.10 +*Want "DXBR RM RTNE,RZ,RP,RM 7/-10 FPCR" 00080000 00080001 00080002 00080003 +r 6A70.04 +*Want "DXBR RM RFS 7/-10 FPCR" 00080007 + + +*Done + diff --git a/tests/bfp-015-sqrt.asm b/tests/bfp-015-sqrt.asm new file mode 100644 index 000000000..005de9502 --- /dev/null +++ b/tests/bfp-015-sqrt.asm @@ -0,0 +1,842 @@ + TITLE 'bfp-015-sqrt.asm: Test IEEE Square Root' +*********************************************************************** +* +*Testcase IEEE SQUARE ROOT +* Test case capability includes IEEE exceptions trappable and +* otherwise. Test results, FPCR flags, and any DXC are saved for all +* tests. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* bfp-015-sqrt.asm +* +* This assembly-language source file is part of the +* Hercules Decimal Floating Point Validation Package +* by Stephen R. Orso +* +* Copyright 2016 by Stephen R Orso. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* +* 3. The name of the author may not be used to endorse or promote +* products derived from this software without specific prior written +* permission. +* +* DISCLAMER: THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* HOLDER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* +* Tests five square root instructions: +* SQUARE ROOT (extended BFP, RRE) +* SQUARE ROOT (long BFP, RRE) +* SQUARE ROOT (long BFP, RXE) +* SQUARE ROOT (short BFP, RRE) +* SQUARE ROOT (short BFP, RXE) +* +* Test data is compiled into this program. The test script that runs +* this program can provide alternative test data through Hercules R +* commands. +* +* Test Case Order +* 1) Short BFP basic tests, including traps and NaN propagation +* 2) Short BFP FPC-controlled rounding mode exhaustive tests +* 3) Long BFP basic tests, including traps and NaN propagation +* 4) Long BFP FPC-controlled rounding mode exhaustive tests +* 5) Extended BFP basic tests, including traps and NaN propagation +* 6) Extended BFP FPC-controlled rounding mode exhaustive tests +* +* Two input test sets are provided each for short, long, and extended +* BFP inputs. The first set covers non-finites, negatives, NaNs, and +* traps on inexact and inexact-incremented. The second more limited +* set exhaustively tests Square Root with each rounding mode that can +* be specified in the FPC. Test values are the same for each +* precision. Interestingly, the square root of 3 is nearer to a lower +* magnitude for all three precisions, while the square root of 5 is +* nearer to a larger magnitude for all three precisions. The square +* root of 2 does not have this property. +* +* Note: Square Root recognizes only the IEEE exceptions Invalid and +* Inexact. Neither overflow nor underflow can occur with Square Root. +* For values greater than 1, the result from Square Root is smaller +* than the input. For values less than 1 and greater than zero, the +* result from square root is larger than the input value. +* +* Also tests the following floating point support instructions +* LOAD (Short) +* LOAD (Long) +* LFPC (Load Floating Point Control Register) +* SRNMB (Set BFP Rounding Mode 3-bit) +* STORE (Short) +* STORE (Long) +* STFPC (Store Floating Point Control Register) +* +* +*********************************************************************** + SPACE 2 + MACRO + PADCSECT &ENDLABL +.* +.* Macro to pad the CSECT to include result data areas if this test +.* program is not being assembled using asma. asma generates a core +.* image that is loaded by the loadcore command, and because the +.* core image is a binary stored in Github, it makes sense to make +.* this small effort to keep the core image small. +.* + AIF (D'&ENDLABL).GOODPAD + MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + MNOTE *,'No CSECT padding performed' + MEXIT +.* +.GOODPAD ANOP Label valid. See if we're on asma + AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + ORG &ENDLABL-1 Not ASMA. Pad CSECT + MEXIT +.* +.NOPAD ANOP + MNOTE *,'asma detected; no CSECT padding performed' + MEND +* +* Note: for compatibility with the z/CMS test rig, do not change +* or use R11, R14, or R15. Everything else is fair game. +* +BFPSQRTS START 0 +STRTLABL EQU * +R0 EQU 0 Work register for cc extraction +R1 EQU 1 +R2 EQU 2 Holds count of test input values +R3 EQU 3 Points to next test input value(s) +R4 EQU 4 Rounding tests inner loop control +R5 EQU 5 Rounding tests outer loop control +R6 EQU 6 Rounding tests top of inner loop +R7 EQU 7 Pointer to next result value(s) +R8 EQU 8 Pointer to next FPCR result +R9 EQU 9 Rounding tests top of inner loop +R10 EQU 10 Pointer to test address list +R11 EQU 11 **Reserved for z/CMS test rig +R12 EQU 12 Top of outer loop address in tests +R13 EQU 13 Mainline return address +R14 EQU 14 **Return address for z/CMS test rig +R15 EQU 15 **Base register on z/CMS or Hyperion +* +* Floating Point Register equates to keep the cross reference clean +* +FPR0 EQU 0 +FPR1 EQU 1 Input value for RRE instructions +FPR2 EQU 2 +FPR3 EQU 3 ..Paired with FPR1 for RRE extended +FPR4 EQU 4 +FPR5 EQU 5 +FPR6 EQU 6 +FPR7 EQU 7 +FPR8 EQU 8 Result value from Square Root +FPR9 EQU 9 +FPR10 EQU 10 ..Paired with FPR8 for RRE extended +FPR11 EQU 11 +FPR12 EQU 12 +FPR13 EQU 13 +FPR14 EQU 14 +FPR15 EQU 15 +* + USING *,R15 +* +* Above works on real iron (R15=0 after sysclear) +* and in z/CMS (R15 points to start of load module) +* + SPACE 2 +*********************************************************************** +* +* Low core definitions, Restart PSW, and Program Check Routine. +* +*********************************************************************** + SPACE 2 + ORG STRTLABL+X'8E' Program check interrution code +PCINTCD DS H +* +PCOLDPSW EQU STRTLABL+X'150' z/Arch Program check old PSW +* + ORG STRTLABL+X'1A0' z/Arch Restart PSW + DC X'0000000180000000',AD(START) +* + ORG STRTLABL+X'1D0' z/Arch Program check old PSW + DC X'0000000000000000',AD(PROGCHK) +* +* Program check routine. If Data Exception, continue execution at +* the instruction following the program check. Otherwise, hard wait. +* No need to collect data. All interesting DXC stuff is captured +* in the FPCR. +* + ORG STRTLABL+X'200' +PROGCHK DS 0H Program check occured... + CLI PCINTCD+1,X'07' Data Exception? + JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) + LPSWE PCOLDPSW ..yes, resume program execution +PCNOTDTA DS 0H + LTR R14,R14 Return address provided? + BNZR R14 Yes, return to z/CMS test rig. + LPSWE HARDWAIT Not data exception, enter disabled wait + EJECT +*********************************************************************** +* +* Main program. Enable Advanced Floating Point, process test cases. +* +*********************************************************************** + SPACE 2 +START DS 0H + STCTL R0,R0,CTLR0 Store CR0 to enable AFP + OI CTLR0+1,X'04' Turn on AFP bit + LCTL R0,R0,CTLR0 Reload updated CR0 +* + LA R10,SHORTB Point to short BFP inputs + BAS R13,SBFPB Take square root of short BFP values + LA R10,RMSHORTS Point to short BFP rounding mode tests + BAS R13,SBFPRM Take sqrt of short BFP for rounding tests +* + LA R10,LONGB Point to long BFP inputs + BAS R13,LBFPB Take square root of long BFP values + LA R10,RMLONGS Point to long BFP rounding mode tests + BAS R13,LBFPRM Take sqrt of long BFP for rounding tests +* + LA R10,XTNDB Point to extended BFP inputs + BAS R13,XBFPB Take square root of extended BFP values + LA R10,RMXTNDS Point to ext'd BFP rounding mode tests + BAS R13,XBFPRM Take sqrt of ext'd BFP for rounding tests +* + LTR R14,R14 Return address provided? + BNZR R14 ..Yes, return to z/CMS test rig. + LPSWE WAITPSW All done, load enabled wait PSW +* +* + DS 0D Ensure correct alignment for PSW +WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end +* +CTLR0 DS F +FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags +* +* Input values parameter list, four fullwords for each test data set +* 1) Count, +* 2) Address of inputs, +* 3) Address to place results, and +* 4) Address to place DXC/Flags/cc values. +* + ORG BFPSQRTS+X'480' + ORG STRTLABL+X'300' Enable run-time replacement +SHORTB DS 0F Input pairs for short BFP basic tests + DC A(SBFPBCT) + DC A(SBFPBIN) + DC A(SBFPBOT) + DC A(SBFPBFL) +* +RMSHORTS DS 0F Input pairs for short BFP rounding testing + DC A(SBFPRMCT) + DC A(SBFPINRM) + DC A(SBFPRMO) + DC A(SBFPRMOF) +* +LONGB DS 0F Input pairs for long BFP basic testing + DC A(LBFPBCT) + DC A(LBFPBIN) + DC A(LBFPBOT) + DC A(LBFPBFL) +* +RMLONGS DS 0F Input pairs for long BFP rounding testing + DC A(LBFPRMCT) + DC A(LBFPINRM) + DC A(LBFPRMO) + DC A(LBFPRMOF) +* +XTNDB DS 0F Inputs for extended BFP basic testing + DC A(XBFPBCT) + DC A(XBFPBIN) + DC A(XBFPBOT) + DC A(XBFPBFL) +* +RMXTNDS DS 0F Inputs for ext'd BFP non-finite testing + DC A(XBFPRMCT) + DC A(XBFPINRM) + DC A(XBFPRMO) + DC A(XBFPRMOF) +* + EJECT +*********************************************************************** +* +* Take square roots using provided short BFP inputs. This set of tests +* checks NaN propagation, operations on values that are not finite +* numbers, and other basic tests. This set generates results that can +* be validated against Figure 19-17 on page 19-21 of SA22-7832-10. +* +* Four results are generated for each input: one RRE with all +* exceptions non-trappable, a second RRE with all exceptions trappable, +* a third RXE with all exceptions non-trappable, a fourth RXE with all +* exceptions trappable, +* +* The square root and FPCR are stored for each result. +* +*********************************************************************** + SPACE 2 +SBFPB DS 0H BFP Short basic tests + LM R2,R3,0(R10) Get count and address of dividendd values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LZER FPR8 Zero result register + LE FPR1,0(,R3) Get short BFP input + LFPC FPCREGNT Set exceptions non-trappable + SQEBR FPR8,FPR1 Take square root of FPR1 into FPR8 RRE + STE FPR8,0(,R7) Store short BFP square root + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LZER FPR8 Zero result register + LFPC FPCREGTR Set exceptions trappable + SQEBR FPR8,FPR1 Take square root of FPR1 into FPR8 RRE + STE FPR8,4(,R7) Store short BFP square root + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LZER FPR8 Zero result register + LFPC FPCREGNT Set exceptions non-trappable + SQEB FPR8,0(,R3) Take square root, place in FPR8 RXE + STE FPR8,8(,R7) Store short BFP square root + STFPC 8(R8) Store resulting FPCR flags and DXC +* + LZER FPR8 Zero result register + LFPC FPCREGTR Set exceptions trappable + SQEB FPR8,0(,R3) Take square root, place in FPR8 RXE + STE FPR8,12(,R7) Store short BFP square root + STFPC 12(R8) Store resulting FPCR flags and DXC +* + LA R7,16(,R7) Point to next Square Root result area + LA R8,16(,R8) Point to next Square Root FPCR area + LA R3,4(,R3) Point to next input value + BCTR R2,R12 Convert next input value. +* + BR R13 All converted; return. +* + EJECT +*********************************************************************** +* +* Perform Square Root using provided short BFP inputs. This set of +* tests exhaustively tests all rounding modes available for Square +* Root. The rounding mode can only be specified in the FPC. +* +* All five FPC rounding modes are tested because the preceeding tests, +* using rounding mode RNTE, do not often create results that require +* rounding. +* +* Two results are generated for each input and rounding mode: one RRE +* and one RXE. Traps are disabled for all rounding mode tests. +* +* The quotient and FPCR contents are stored for each test. +* +*********************************************************************** + SPACE 2 +SBFPRM LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + XR R1,R1 Zero register 1 for use in IC/STC/indexing + BASR R12,0 Set top of test case loop + + LA R5,FPCMCT Get count of FPC modes to be tested + BASR R9,0 Set top of rounding mode outer loop +* + IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 0(R1) Set FPC Rounding Mode + LE FPR1,0(,R3) Get short BFP input value + SQEBR FPR8,FPR1 Take square root of FPR1 into FPR8 RRE + STE FPR8,0(,R7) Store short BFP quotient + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 0(R1) Set FPC Rounding Mode + SQEB FPR8,0(,R3) Take square root of value into FPR8 RXE + STE FPR8,4(,R7) Store short BFP quotient + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LA R7,8(,R7) Point to next square root result + LA R8,8(,R8) Point to next FPCR result area +* + BCTR R5,R9 Iterate to next FPC mode +* +* End of FPC modes to be tested. Advance to next test case. +* + LA R3,4(,R3) Point to next input value + LA R7,8(,R7) Skip to start of next result area + LA R8,8(,R8) Skip to start of next FPCR result area + BCTR R2,R12 Divide next input value lots of times +* + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Take square roots using provided long BFP inputs. This set of tests +* checks NaN propagation, operations on values that are not finite +* numbers, and other basic tests. This set generates results that can +* be validated against Figure 19-17 on page 19-21 of SA22-7832-10. +* +* Four results are generated for each input: one RRE with all +* exceptions non-trappable, a second RRE with all exceptions trappable, +* a third RXE with all exceptions non-trappable, a fourth RXE with all +* exceptions trappable, +* +* The square root and FPCR are stored for each result. +* +*********************************************************************** + SPACE 2 +LBFPB DS 0H BFP long basic tests + LM R2,R3,0(R10) Get count and address of dividendd values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LZDR FPR8 Zero result register + LD FPR1,0(,R3) Get long BFP input + LFPC FPCREGNT Set exceptions non-trappable + SQDBR FPR8,FPR1 Take square root of FPR1 into FPR8 RRE + STD FPR8,0(,R7) Store long BFP square root + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LZDR FPR8 Zero result register + LFPC FPCREGTR Set exceptions trappable + SQDBR FPR8,FPR1 Take square root of FPR1 into FPR8 RRE + STD FPR8,8(,R7) Store long BFP square root + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LZDR FPR8 Zero result register + LFPC FPCREGNT Set exceptions non-trappable + SQDB FPR8,0(,R3) Take square root, place in FPR8 RXE + STD FPR8,16(,R7) Store long BFP square root + STFPC 8(R8) Store resulting FPCR flags and DXC +* + LZDR FPR8 Zero result register + LFPC FPCREGTR Set exceptions trappable + SQDB FPR8,0(,R3) Take square root, place in FPR8 RXE + STD FPR8,24(,R7) Store short BFP square root + STFPC 12(R8) Store resulting FPCR flags and DXC +* + LA R7,32(,R7) Point to next Square Root result area + LA R8,16(,R8) Point to next Square Root FPCR area + LA R3,8(,R3) Point to next input value + BCTR R2,R12 Convert next input value. +* + BR R13 All converted; return. +* + EJECT +*********************************************************************** +* +* Perform Square Root using provided long BFP inputs. This set of +* tests exhaustively tests all rounding modes available for Square +* Root. The rounding mode can only be specified in the FPC. +* +* All five FPC rounding modes are tested because the preceeding tests, +* using rounding mode RNTE, do not often create results that require +* rounding. +* +* Two results are generated for each input and rounding mode: one RRE +* and one RXE. Traps are disabled for all rounding mode tests. +* +* The quotient and FPCR contents are stored for each test. +* +*********************************************************************** + SPACE 2 +LBFPRM LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + XR R1,R1 Zero register 1 for use in IC/STC/indexing + BASR R12,0 Set top of test case loop + + LA R5,FPCMCT Get count of FPC modes to be tested + BASR R9,0 Set top of rounding mode outer loop +* + IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 0(R1) Set FPC Rounding Mode + LD FPR1,0(,R3) Get long BFP input value + SQDBR FPR8,FPR1 Take square root of FPR1 into FPR8 RRE + STD FPR8,0(,R7) Store long BFP quotient + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 0(R1) Set FPC Rounding Mode + SQDB FPR8,0(,R3) Take square root of value into FPR8 RXE + STD FPR8,8(,R7) Store short BFP quotient + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LA R7,16(,R7) Point to next square root result + LA R8,8(,R8) Point to next FPCR result area +* + BCTR R5,R9 Iterate to next FPC mode +* +* End of FPC modes to be tested. Advance to next test case. +* + LA R3,8(,R3) Point to next input value + LA R8,8(,R8) Skip to start of next FPCR result area + BCTR R2,R12 Divide next input value lots of times +* + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Take square roots using provided extended BFP inputs. This set of +* tests checks NaN propagation, operations on values that are not +* finite numbers, and other basic tests. This set generates results +* that can be validated against Figure 19-17 on page 19-21 of +* SA22-7832-10. +* +* Four results are generated for each input: one RRE with all +* exceptions non-trappable, a second RRE with all exceptions trappable, +* a third RXE with all exceptions non-trappable, a fourth RXE with all +* exceptions trappable, +* +* The square root and FPCR are stored for each result. +* +*********************************************************************** + SPACE 2 +XBFPB DS 0H BFP extended basic tests + LM R2,R3,0(R10) Get count and address of dividendd values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LZXR FPR8 Zero result register + LD FPR1,0(,R3) Get extended BFP input part 1 + LD FPR3,8(,R3) Get extended BFP input part 2 + LFPC FPCREGNT Set exceptions non-trappable + SQXBR FPR8,FPR1 Take square root of FPR1 into FPR8-10 RRE + STD FPR8,0(,R7) Store extended BFP square root part 1 + STD FPR10,8(,R7) Store extended BFP square root part 2 + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LZXR FPR8 Zero result register + LFPC FPCREGTR Set exceptions trappable + SQXBR FPR8,FPR1 Take square root of FPR1 into FPR8-10 RRE + STD FPR8,16(,R7) Store extended BFP square root part 1 + STD FPR10,24(,R7) Store extended BFP square root part 2 + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LA R7,32(,R7) Point to next Square Root result area + LA R8,16(,R8) Point to next Square Root FPCR area + LA R3,16(,R3) Point to next input value + BCTR R2,R12 Convert next input value. +* + BR R13 All converted; return. +* + EJECT +*********************************************************************** +* +* Perform Square Root using provided extended BFP inputs. This set of +* tests exhaustively tests all rounding modes available for Square +* Root. The rounding mode can only be specified in the FPC. +* +* All five FPC rounding modes are tested because the preceeding tests, +* using rounding mode RNTE, do not often create results that require +* rounding. +* +* Two results are generated for each input and rounding mode: one RRE +* and one RXE. Traps are disabled for all rounding mode tests. +* +* The quotient and FPCR contents are stored for each test. +* +*********************************************************************** + SPACE 2 +XBFPRM LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + XR R1,R1 Zero register 1 for use in IC/STC/indexing + BASR R12,0 Set top of test case loop + + LA R5,FPCMCT Get count of FPC modes to be tested + BASR R9,0 Set top of rounding mode outer loop +* + IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 0(R1) Set FPC Rounding Mode + LD FPR1,0(,R3) Get long BFP input value part 1 + LD FPR3,8(,R3) Get long BFP input value part 2 + SQXBR FPR8,FPR1 Take square root of FPR1 into FPR8 RRE + STD FPR8,0(,R7) Store extended BFP root part 1 + STD FPR10,8(,R7) Store extended BFP root part 2 + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LA R7,16(,R7) Point to next square root result + LA R8,4(,R8) Point to next FPCR result area +* + BCTR R5,R9 Iterate to next FPC mode +* +* End of FPC modes to be tested. Advance to next test case. +* + LA R3,16(,R3) Point to next input value + LA R8,12(,R8) Skip to start of next FPCR result area + BCTR R2,R12 Divide next input value lots of times +* + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Table of FPC rounding modes to test quotient rounding modes. +* +* The Set BFP Rounding Mode does allow specification of the FPC +* rounding mode as an address, so we shall index into a table of +* BFP rounding modes without bothering with Execute. +* +*********************************************************************** + SPACE 2 +* +* Rounding modes that may be set in the FPCR. The FPCR controls +* rounding of the quotient. +* +* These are indexed directly by the loop counter, which counts down. +* So the modes are listed in reverse order here. +* +FPCMODES DS 0C + DC AL1(7) RFS, Round for shorter precision + DC AL1(3) RM, Round to -infinity + DC AL1(2) RP, Round to +infinity + DC AL1(1) RZ, Round to zero + DC AL1(0) RNTE, Round to Nearest, ties to even +FPCMCT EQU *-FPCMODES Count of FPC Modes to be tested +* + EJECT +*********************************************************************** +* +* Short BFP test data sets for Square Root testing. +* +* The first test data set is used for tests of basic functionality, +* NaN propagation, and results from operations involving other than +* finite numbers. +* +* The second test data set is used for testing boundary conditions +* using finite non-zero values. Each possible type of result (normal, +* scaled, etc) is created by members of this test data set. +* +* The third test data set is used for exhaustive testing of final +* results across the five rounding modes available for the Square Root +* instruction. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* First input test data set, to test operations using non-finite or +* zero inputs. Member values chosen to validate part 1 of Figure 19-17 +* on page 19-21 of SA22-7832-10. +* +*********************************************************************** + SPACE 2 +SBFPBIN DS 0F Inputs for short BFP basic tests + DC X'FF800000' -inf + DC X'C0800000' -4.0 + DC X'80000000' -0 + DC X'00000000' +0 + DC X'40800000' +4.0 + DC X'7F800000' +inf + DC X'FFCB0000' -QNaN + DC X'7F8A0000' +SNaN + DC X'40400000' +3.0 Inexact, truncated + DC X'40A00000' +5.0 Inexact, incremented + DC X'3D800000' +0.0625 exact, expect 0.25 +SBFPBCT EQU (*-SBFPBIN)/4 Count of short BFP in list + SPACE 3 +*********************************************************************** +* +* Second input test data set. These are finite positive values +* intended to test all combinations of rounding mode for a given +* result. Values are chosen to create a requirement to round to the +* target precision after the computation +* +*********************************************************************** + SPACE 2 +SBFPINRM DS 0F Inputs for short BFP rounding testing +* + DC X'40400000' +3.0 Inexact, truncated + DC X'40A00000' +5.0 Inexact, incremented +* +SBFPRMCT EQU (*-SBFPINRM)/4 Count of short BFP rounding tests + EJECT +*********************************************************************** +* +* Long BFP test data sets for Divide testing. +* +* The first test data set is used for tests of basic functionality, +* NaN propagation, and results from operations involving other than +* finite numbers. +* +* The second test data set is used for testing boundary conditions +* using finite non-zero values. Each possible type of result (normal, +* scaled, etc) is created by members of this test data set. +* +* The third test data set is used for exhaustive testing of final +* results across the five rounding modes available for the Square Root +* instruction. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* First input test data set, to test operations using non-finite or +* zero inputs. Member values chosen to validate part 1 of Figure 19-17 +* on page 19-21 of SA22-7832-10. +* +*********************************************************************** + SPACE 2 +LBFPBIN DS 0D Inputs for long BFP testing + DC X'FFF0000000000000' -inf + DC X'C010000000000000' -4.0 + DC X'8000000000000000' -0 + DC X'0000000000000000' +0 + DC X'4010000000000000' +4.0 + DC X'7FF0000000000000' +inf + DC X'FFF8B00000000000' -QNaN + DC X'7FF0A00000000000' +SNaN + DC X'4008000000000000' +3.0 Inexact, truncated + DC X'4014000000000000' +5.0 Inexact, incremented + DC X'3FB0000000000000' +0.0625 exact, expect 0.25 +LBFPBCT EQU (*-LBFPBIN)/8 Count of long BFP in list + SPACE 3 +*********************************************************************** +* +* Second input test data set. These are finite positive values +* intended to test all combinations of rounding mode for a given +* result. Values are chosen to create a requirement to round to the +* target precision after the computation +* +*********************************************************************** + SPACE 2 +LBFPINRM DS 0F +* + DC X'4008000000000000' +3.0 Inexact, truncated + DC X'4014000000000000' +5.0 Inexact, incremented +* +LBFPRMCT EQU (*-LBFPINRM)/8 Count of long BFP rounding tests * 8 + EJECT +*********************************************************************** +* +* Extended BFP test data sets for Divide testing. +* +* The first test data set is used for tests of basic functionality, +* NaN propagation, and results from operations involving other than +* finite numbers. +* +* The second test data set is used for testing boundary conditions +* using finite non-zero values. Each possible type of result (normal, +* scaled, etc) is created by members of this test data set. +* +* The third test data set is used for exhaustive testing of final +* results across the five rounding modes available for the Square Root +* instruction. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* First input test data set, to test operations using non-finite or +* zero inputs. Member values chosen to validate part 1 of Figure 19-17 +* on page 19-21 of SA22-7832-10. +* +*********************************************************************** + SPACE 2 +XBFPBIN DS 0D Inputs for extended BFP testing + DC X'FFFF0000000000000000000000000000' -inf + DC X'C0010000000000000000000000000000' -4.0 + DC X'80000000000000000000000000000000' -0 + DC X'00000000000000000000000000000000' +0 + DC X'40010000000000000000000000000000' +4.0 + DC X'7FFF0000000000000000000000000000' +inf + DC X'FFFF8B00000000000000000000000000' -QNaN + DC X'7FFF0A00000000000000000000000000' +SNaN + DC X'40008000000000000000000000000000' +3.0 Inexact, trunc. + DC X'40014000000000000000000000000000' +5.0 Inexact, incre. + DC X'3FFB0000000000000000000000000000' +0.0625 expect 0.25 +XBFPBCT EQU (*-XBFPBIN)/16 Count of extended BFP in list + SPACE 3 +*********************************************************************** +* +* Second input test data set. These are finite positive values +* intended to test all combinations of rounding mode for a given +* result. Values are chosen to create a requirement to round to the +* target precision after the computation +* +*********************************************************************** + SPACE 2 +XBFPINRM DS 0D +* + DC X'40008000000000000000000000000000' +3.0 Inexact, trunc. + DC X'40014000000000000000000000000000' +5.0 Inexact, incre. +* +XBFPRMCT EQU (*-XBFPINRM)/16 Count of long BFP rounding tests + EJECT +* +* Locations for results +* +SBFPBOT EQU STRTLABL+X'1000' Integer short non-finite BFP results +* ..room for 16 tests, 8 used +SBFPBFL EQU STRTLABL+X'1100' FPCR flags and DXC from short BFP +* ..room for 16 tests, 8 used +* +SBFPRMO EQU STRTLABL+X'1200' Short BFP rounding mode test results +* ..Room for 16, 2 used. +SBFPRMOF EQU STRTLABL+X'1400' Short BFP rounding mode FPCR results +* ..Room for 16, 2 used. +* ..next location starts at X'1600' +* +LBFPBOT EQU STRTLABL+X'3000' Integer long non-finite BFP results +* ..room for 16 tests, 8 used +LBFPBFL EQU STRTLABL+X'3200' FPCR flags and DXC from long BFP +* ..room for 16 tests, 8 used +* +LBFPRMO EQU STRTLABL+X'3400' Long BFP rounding mode test results +* ..Room for 16, 4 used. +LBFPRMOF EQU STRTLABL+X'3700' Long BFP rounding mode FPCR results +* ..Room for 16, 4 used. +* ..next location starts at X'3800' +* +XBFPBOT EQU STRTLABL+X'5000' Integer ext'd non-finite BFP results +* ..room for 16 tests, 8 used +XBFPBFL EQU STRTLABL+X'5400' FPCR flags and DXC from ext'd BFP +* ..room for 16 tests, 8 used +* +XBFPRMO EQU STRTLABL+X'5500' Ext'd BFP rounding mode test results +* ..Room for 16, 4 used. +XBFPRMOF EQU STRTLABL+X'5A00' Ext'd BFP rounding mode FPCR results +* ..Room for 16, 4 used. +* ..next location starts at X'5B00' +* +ENDLABL EQU STRTLABL+X'5B00' + PADCSECT ENDLABL +* + END \ No newline at end of file diff --git a/tests/bfp-015-sqrt.core b/tests/bfp-015-sqrt.core new file mode 100644 index 000000000..f4a85d8a6 Binary files /dev/null and b/tests/bfp-015-sqrt.core differ diff --git a/tests/bfp-015-sqrt.list b/tests/bfp-015-sqrt.list new file mode 100644 index 000000000..5a5984928 --- /dev/null +++ b/tests/bfp-015-sqrt.list @@ -0,0 +1,1039 @@ +ASMA Ver. 0.2.0 bfp-015-sqrt.asm: Test IEEE Square Root 23 Sep 2016 12:38:52 Page 1 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 2 *********************************************************************** + 3 * + 4 *Testcase IEEE SQUARE ROOT + 5 * Test case capability includes IEEE exceptions trappable and + 6 * otherwise. Test results, FPCR flags, and any DXC are saved for all + 7 * tests. + 8 * + 9 *********************************************************************** + + + 11 *********************************************************************** + 12 * + 13 * + 14 * Tests five square root instructions: + 15 * SQUARE ROOT (extended BFP, RRE) + 16 * SQUARE ROOT (long BFP, RRE) + 17 * SQUARE ROOT (long BFP, RXE) + 18 * SQUARE ROOT (short BFP, RRE) + 19 * SQUARE ROOT (short BFP, RXE) + 20 * + 21 * Test data is compiled into this program. The test script that runs + 22 * this program can provide alternative test data through Hercules R + 23 * commands. + 24 * + 25 * Test Case Order + 26 * 1) Short BFP basic tests, including traps and NaN propagation + 27 * 2) Short BFP FPC-controlled rounding mode exhaustive tests + 28 * 3) Long BFP basic tests, including traps and NaN propagation + 29 * 4) Long BFP FPC-controlled rounding mode exhaustive tests + 30 * 5) Extended BFP basic tests, including traps and NaN propagation + 31 * 6) Extended BFP FPC-controlled rounding mode exhaustive tests + 32 * + 33 * Two input test sets are provided each for short, long, and extended + 34 * BFP inputs. The first set covers non-finites, negatives, NaNs, and + 35 * traps on inexact and inexact-incremented. The second more limited + 36 * set exhaustively tests Square Root with each rounding mode that can + 37 * be specified in the FPC. Test values are the same for each + 38 * precision. Interestingly, the square root of 3 is nearer to a lower + 39 * magnitude for all three precisions, while the square root of 5 is + 40 * nearer to a larger magnitude for all three precisions. The square + 41 * root of 2 does not have this property. + 42 * + 43 * Note: Square Root recognizes only the IEEE exceptions Invalid and + 44 * Inexact. Neither overflow nor underflow can occur with Square Root. + 45 * For values greater than 1, the result from Square Root is smaller + 46 * than the input. For values less than 1 and greater than zero, the + 47 * result from square root is larger than the input value. + 48 * + 49 * Also tests the following floating point support instructions + 50 * LOAD (Short) + 51 * LOAD (Long) + 52 * LFPC (Load Floating Point Control Register) + ASMA Ver. 0.2.0 bfp-015-sqrt.asm: Test IEEE Square Root 23 Sep 2016 12:38:52 Page 2 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 53 * SRNMB (Set BFP Rounding Mode 3-bit) + 54 * STORE (Short) + 55 * STORE (Long) + 56 * STFPC (Store Floating Point Control Register) + 57 * + 58 * + 59 *********************************************************************** + + + 61 MACRO + 62 PADCSECT &ENDLABL + 63 .* + 64 .* Macro to pad the CSECT to include result data areas if this test + 65 .* program is not being assembled using asma. asma generates a core + 66 .* image that is loaded by the loadcore command, and because the + 67 .* core image is a binary stored in Github, it makes sense to make + 68 .* this small effort to keep the core image small. + 69 .* + 70 AIF (D'&ENDLABL).GOODPAD + 71 MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + 72 MNOTE *,'No CSECT padding performed' + 73 MEXIT + 74 .* + 75 .GOODPAD ANOP Label valid. See if we're on asma + 76 AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + 77 ORG &ENDLABL-1 Not ASMA. Pad CSECT + 78 MEXIT + 79 .* + 80 .NOPAD ANOP + 81 MNOTE *,'asma detected; no CSECT padding performed' + 82 MEND + 83 * + 84 * Note: for compatibility with the z/CMS test rig, do not change + 85 * or use R11, R14, or R15. Everything else is fair game. + 86 * + 0000000000000000 0000000000000727 87 BFPSQRTS START 0 + 0000000000000000 0000000000000001 88 STRTLABL EQU * + 0000000000000000 0000000000000001 89 R0 EQU 0 Work register for cc extraction + 0000000000000001 0000000000000001 90 R1 EQU 1 + 0000000000000002 0000000000000001 91 R2 EQU 2 Holds count of test input values + 0000000000000003 0000000000000001 92 R3 EQU 3 Points to next test input value(s) + 0000000000000004 0000000000000001 93 R4 EQU 4 Rounding tests inner loop control + 0000000000000005 0000000000000001 94 R5 EQU 5 Rounding tests outer loop control + 0000000000000006 0000000000000001 95 R6 EQU 6 Rounding tests top of inner loop + 0000000000000007 0000000000000001 96 R7 EQU 7 Pointer to next result value(s) + 0000000000000008 0000000000000001 97 R8 EQU 8 Pointer to next FPCR result + 0000000000000009 0000000000000001 98 R9 EQU 9 Rounding tests top of inner loop + 000000000000000A 0000000000000001 99 R10 EQU 10 Pointer to test address list + 000000000000000B 0000000000000001 100 R11 EQU 11 **Reserved for z/CMS test rig + 000000000000000C 0000000000000001 101 R12 EQU 12 Top of outer loop address in tests + 000000000000000D 0000000000000001 102 R13 EQU 13 Mainline return address + 000000000000000E 0000000000000001 103 R14 EQU 14 **Return address for z/CMS test rig + ASMA Ver. 0.2.0 bfp-015-sqrt.asm: Test IEEE Square Root 23 Sep 2016 12:38:52 Page 3 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 000000000000000F 0000000000000001 104 R15 EQU 15 **Base register on z/CMS or Hyperion + 105 * + 106 * Floating Point Register equates to keep the cross reference clean + 107 * + 0000000000000000 0000000000000001 108 FPR0 EQU 0 + 0000000000000001 0000000000000001 109 FPR1 EQU 1 Input value for RRE instructions + 0000000000000002 0000000000000001 110 FPR2 EQU 2 + 0000000000000003 0000000000000001 111 FPR3 EQU 3 ..Paired with FPR1 for RRE extended + 0000000000000004 0000000000000001 112 FPR4 EQU 4 + 0000000000000005 0000000000000001 113 FPR5 EQU 5 + 0000000000000006 0000000000000001 114 FPR6 EQU 6 + 0000000000000007 0000000000000001 115 FPR7 EQU 7 + 0000000000000008 0000000000000001 116 FPR8 EQU 8 Result value from Square Root + 0000000000000009 0000000000000001 117 FPR9 EQU 9 + 000000000000000A 0000000000000001 118 FPR10 EQU 10 ..Paired with FPR8 for RRE extended + 000000000000000B 0000000000000001 119 FPR11 EQU 11 + 000000000000000C 0000000000000001 120 FPR12 EQU 12 + 000000000000000D 0000000000000001 121 FPR13 EQU 13 + 000000000000000E 0000000000000001 122 FPR14 EQU 14 + 000000000000000F 0000000000000001 123 FPR15 EQU 15 + 124 * +0000000000000000 0000000000000000 125 USING *,R15 + 126 * + 127 * Above works on real iron (R15=0 after sysclear) + 128 * and in z/CMS (R15 points to start of load module) + 129 * + + + 131 *********************************************************************** + 132 * + 133 * Low core definitions, Restart PSW, and Program Check Routine. + 134 * + 135 *********************************************************************** + + +0000000000000000 0000000000000000 000000000000008E 137 ORG STRTLABL+X'8E' Program check interrution code +000000000000008E 0000 138 PCINTCD DS H + 139 * + 0000000000000150 0000000000000001 140 PCOLDPSW EQU STRTLABL+X'150' z/Arch Program check old PSW + 141 * +0000000000000090 0000000000000090 00000000000001A0 142 ORG STRTLABL+X'1A0' z/Arch Restart PSW +00000000000001A0 00000001 80000000 143 DC X'0000000180000000',AD(START) + 144 * +00000000000001B0 00000000000001B0 00000000000001D0 145 ORG STRTLABL+X'1D0' z/Arch Program check old PSW +00000000000001D0 00000000 00000000 146 DC X'0000000000000000',AD(PROGCHK) + 147 * + 148 * Program check routine. If Data Exception, continue execution at + 149 * the instruction following the program check. Otherwise, hard wait. + 150 * No need to collect data. All interesting DXC stuff is captured + 151 * in the FPCR. + 152 * +00000000000001E0 00000000000001E0 0000000000000200 153 ORG STRTLABL+X'200' + ASMA Ver. 0.2.0 bfp-015-sqrt.asm: Test IEEE Square Root 23 Sep 2016 12:38:52 Page 4 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000200 154 PROGCHK DS 0H Program check occured... +0000000000000200 9507 F08F 000000000000008F 155 CLI PCINTCD+1,X'07' Data Exception? +0000000000000204 A774 0004 000000000000020C 156 JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) +0000000000000208 B2B2 F150 0000000000000150 157 LPSWE PCOLDPSW ..yes, resume program execution +000000000000020C 158 PCNOTDTA DS 0H +000000000000020C 12EE 159 LTR R14,R14 Return address provided? +000000000000020E 077E 160 BNZR R14 Yes, return to z/CMS test rig. +0000000000000210 B2B2 F268 0000000000000268 161 LPSWE HARDWAIT Not data exception, enter disabled wait + ASMA Ver. 0.2.0 bfp-015-sqrt.asm: Test IEEE Square Root 23 Sep 2016 12:38:52 Page 5 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 163 *********************************************************************** + 164 * + 165 * Main program. Enable Advanced Floating Point, process test cases. + 166 * + 167 *********************************************************************** + + +0000000000000214 169 START DS 0H +0000000000000214 B600 F278 0000000000000278 170 STCTL R0,R0,CTLR0 Store CR0 to enable AFP +0000000000000218 9604 F279 0000000000000279 171 OI CTLR0+1,X'04' Turn on AFP bit +000000000000021C B700 F278 0000000000000278 172 LCTL R0,R0,CTLR0 Reload updated CR0 + 173 * +0000000000000220 41A0 F300 0000000000000300 174 LA R10,SHORTB Point to short BFP inputs +0000000000000224 4DD0 F360 0000000000000360 175 BAS R13,SBFPB Take square root of short BFP values +0000000000000228 41A0 F310 0000000000000310 176 LA R10,RMSHORTS Point to short BFP rounding mode tests +000000000000022C 4DD0 F3D6 00000000000003D6 177 BAS R13,SBFPRM Take sqrt of short BFP for rounding tests + 178 * +0000000000000230 41A0 F320 0000000000000320 179 LA R10,LONGB Point to long BFP inputs +0000000000000234 4DD0 F438 0000000000000438 180 BAS R13,LBFPB Take square root of long BFP values +0000000000000238 41A0 F330 0000000000000330 181 LA R10,RMLONGS Point to long BFP rounding mode tests +000000000000023C 4DD0 F4AE 00000000000004AE 182 BAS R13,LBFPRM Take sqrt of long BFP for rounding tests + 183 * +0000000000000240 41A0 F340 0000000000000340 184 LA R10,XTNDB Point to extended BFP inputs +0000000000000244 4DD0 F50C 000000000000050C 185 BAS R13,XBFPB Take square root of extended BFP values +0000000000000248 41A0 F350 0000000000000350 186 LA R10,RMXTNDS Point to ext'd BFP rounding mode tests +000000000000024C 4DD0 F562 0000000000000562 187 BAS R13,XBFPRM Take sqrt of ext'd BFP for rounding tests + 188 * +0000000000000250 12EE 189 LTR R14,R14 Return address provided? +0000000000000252 077E 190 BNZR R14 ..Yes, return to z/CMS test rig. +0000000000000254 B2B2 F258 0000000000000258 191 LPSWE WAITPSW All done, load enabled wait PSW + 192 * + 193 * +0000000000000258 194 DS 0D Ensure correct alignment for PSW +0000000000000258 00020000 00000000 195 WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +0000000000000268 00020000 00000000 196 HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end + 197 * +0000000000000278 00000000 198 CTLR0 DS F +000000000000027C 00000000 199 FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +0000000000000280 F8000000 200 FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags + 201 * + 202 * Input values parameter list, four fullwords for each test data set + 203 * 1) Count, + 204 * 2) Address of inputs, + 205 * 3) Address to place results, and + 206 * 4) Address to place DXC/Flags/cc values. + 207 * +0000000000000284 0000000000000284 0000000000000480 208 ORG BFPSQRTS+X'480' +0000000000000480 0000000000000480 0000000000000300 209 ORG STRTLABL+X'300' Enable run-time replacement +0000000000000300 210 SHORTB DS 0F Input pairs for short BFP basic tests +0000000000000300 0000000B 211 DC A(SBFPBCT) +0000000000000304 000005B8 212 DC A(SBFPBIN) +0000000000000308 00001000 213 DC A(SBFPBOT) + ASMA Ver. 0.2.0 bfp-015-sqrt.asm: Test IEEE Square Root 23 Sep 2016 12:38:52 Page 6 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +000000000000030C 00001100 214 DC A(SBFPBFL) + 215 * +0000000000000310 216 RMSHORTS DS 0F Input pairs for short BFP rounding testing +0000000000000310 00000002 217 DC A(SBFPRMCT) +0000000000000314 000005E4 218 DC A(SBFPINRM) +0000000000000318 00001200 219 DC A(SBFPRMO) +000000000000031C 00001400 220 DC A(SBFPRMOF) + 221 * +0000000000000320 222 LONGB DS 0F Input pairs for long BFP basic testing +0000000000000320 0000000B 223 DC A(LBFPBCT) +0000000000000324 000005F0 224 DC A(LBFPBIN) +0000000000000328 00003000 225 DC A(LBFPBOT) +000000000000032C 00003200 226 DC A(LBFPBFL) + 227 * +0000000000000330 228 RMLONGS DS 0F Input pairs for long BFP rounding testing +0000000000000330 00000002 229 DC A(LBFPRMCT) +0000000000000334 00000648 230 DC A(LBFPINRM) +0000000000000338 00003400 231 DC A(LBFPRMO) +000000000000033C 00003700 232 DC A(LBFPRMOF) + 233 * +0000000000000340 234 XTNDB DS 0F Inputs for extended BFP basic testing +0000000000000340 0000000B 235 DC A(XBFPBCT) +0000000000000344 00000658 236 DC A(XBFPBIN) +0000000000000348 00005000 237 DC A(XBFPBOT) +000000000000034C 00005400 238 DC A(XBFPBFL) + 239 * +0000000000000350 240 RMXTNDS DS 0F Inputs for ext'd BFP non-finite testing +0000000000000350 00000002 241 DC A(XBFPRMCT) +0000000000000354 00000708 242 DC A(XBFPINRM) +0000000000000358 00005500 243 DC A(XBFPRMO) +000000000000035C 00005A00 244 DC A(XBFPRMOF) + 245 * + ASMA Ver. 0.2.0 bfp-015-sqrt.asm: Test IEEE Square Root 23 Sep 2016 12:38:52 Page 7 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 247 *********************************************************************** + 248 * + 249 * Take square roots using provided short BFP inputs. This set of tests + 250 * checks NaN propagation, operations on values that are not finite + 251 * numbers, and other basic tests. This set generates results that can + 252 * be validated against Figure 19-17 on page 19-21 of SA22-7832-10. + 253 * + 254 * Four results are generated for each input: one RRE with all + 255 * exceptions non-trappable, a second RRE with all exceptions trappable, + 256 * a third RXE with all exceptions non-trappable, a fourth RXE with all + 257 * exceptions trappable, + 258 * + 259 * The square root and FPCR are stored for each result. + 260 * + 261 *********************************************************************** + + +0000000000000360 263 SBFPB DS 0H BFP Short basic tests +0000000000000360 9823 A000 0000000000000000 264 LM R2,R3,0(R10) Get count and address of dividendd values +0000000000000364 9878 A008 0000000000000008 265 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000368 1222 266 LTR R2,R2 Any test cases? +000000000000036A 078D 267 BZR R13 ..No, return to caller +000000000000036C 0DC0 268 BASR R12,0 Set top of loop + 269 * +000000000000036E B374 0080 270 LZER FPR8 Zero result register +0000000000000372 7810 3000 0000000000000000 271 LE FPR1,0(,R3) Get short BFP input +0000000000000376 B29D F27C 000000000000027C 272 LFPC FPCREGNT Set exceptions non-trappable +000000000000037A B314 0081 273 SQEBR FPR8,FPR1 Take square root of FPR1 into FPR8 RRE +000000000000037E 7080 7000 0000000000000000 274 STE FPR8,0(,R7) Store short BFP square root +0000000000000382 B29C 8000 0000000000000000 275 STFPC 0(R8) Store resulting FPCR flags and DXC + 276 * +0000000000000386 B374 0080 277 LZER FPR8 Zero result register +000000000000038A B29D F280 0000000000000280 278 LFPC FPCREGTR Set exceptions trappable +000000000000038E B314 0081 279 SQEBR FPR8,FPR1 Take square root of FPR1 into FPR8 RRE +0000000000000392 7080 7004 0000000000000004 280 STE FPR8,4(,R7) Store short BFP square root +0000000000000396 B29C 8004 0000000000000004 281 STFPC 4(R8) Store resulting FPCR flags and DXC + 282 * +000000000000039A B374 0080 283 LZER FPR8 Zero result register +000000000000039E B29D F27C 000000000000027C 284 LFPC FPCREGNT Set exceptions non-trappable +00000000000003A2 ED80 3000 0014 0000000000000000 285 SQEB FPR8,0(,R3) Take square root, place in FPR8 RXE +00000000000003A8 7080 7008 0000000000000008 286 STE FPR8,8(,R7) Store short BFP square root +00000000000003AC B29C 8008 0000000000000008 287 STFPC 8(R8) Store resulting FPCR flags and DXC + 288 * +00000000000003B0 B374 0080 289 LZER FPR8 Zero result register +00000000000003B4 B29D F280 0000000000000280 290 LFPC FPCREGTR Set exceptions trappable +00000000000003B8 ED80 3000 0014 0000000000000000 291 SQEB FPR8,0(,R3) Take square root, place in FPR8 RXE +00000000000003BE 7080 700C 000000000000000C 292 STE FPR8,12(,R7) Store short BFP square root +00000000000003C2 B29C 800C 000000000000000C 293 STFPC 12(R8) Store resulting FPCR flags and DXC + 294 * +00000000000003C6 4170 7010 0000000000000010 295 LA R7,16(,R7) Point to next Square Root result area +00000000000003CA 4180 8010 0000000000000010 296 LA R8,16(,R8) Point to next Square Root FPCR area +00000000000003CE 4130 3004 0000000000000004 297 LA R3,4(,R3) Point to next input value + ASMA Ver. 0.2.0 bfp-015-sqrt.asm: Test IEEE Square Root 23 Sep 2016 12:38:52 Page 8 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000003D2 062C 298 BCTR R2,R12 Convert next input value. + 299 * +00000000000003D4 07FD 300 BR R13 All converted; return. + 301 * + ASMA Ver. 0.2.0 bfp-015-sqrt.asm: Test IEEE Square Root 23 Sep 2016 12:38:52 Page 9 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 303 *********************************************************************** + 304 * + 305 * Perform Square Root using provided short BFP inputs. This set of + 306 * tests exhaustively tests all rounding modes available for Square + 307 * Root. The rounding mode can only be specified in the FPC. + 308 * + 309 * All five FPC rounding modes are tested because the preceeding tests, + 310 * using rounding mode RNTE, do not often create results that require + 311 * rounding. + 312 * + 313 * Two results are generated for each input and rounding mode: one RRE + 314 * and one RXE. Traps are disabled for all rounding mode tests. + 315 * + 316 * The quotient and FPCR contents are stored for each test. + 317 * + 318 *********************************************************************** + + +00000000000003D6 9823 A000 0000000000000000 320 SBFPRM LM R2,R3,0(R10) Get count and address of test input values +00000000000003DA 9878 A008 0000000000000008 321 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000003DE 1222 322 LTR R2,R2 Any test cases? +00000000000003E0 078D 323 BZR R13 ..No, return to caller +00000000000003E2 1711 324 XR R1,R1 Zero register 1 for use in IC/STC/indexing +00000000000003E4 0DC0 325 BASR R12,0 Set top of test case loop + 326 +00000000000003E6 4150 0005 0000000000000005 327 LA R5,FPCMCT Get count of FPC modes to be tested +00000000000003EA 0D90 328 BASR R9,0 Set top of rounding mode outer loop + 329 * +00000000000003EC 4315 F5B1 00000000000005B1 330 IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode + 331 * +00000000000003F0 B29D F27C 000000000000027C 332 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000003F4 B2B8 1000 0000000000000000 333 SRNMB 0(R1) Set FPC Rounding Mode +00000000000003F8 7810 3000 0000000000000000 334 LE FPR1,0(,R3) Get short BFP input value +00000000000003FC B314 0081 335 SQEBR FPR8,FPR1 Take square root of FPR1 into FPR8 RRE +0000000000000400 7080 7000 0000000000000000 336 STE FPR8,0(,R7) Store short BFP quotient +0000000000000404 B29C 8000 0000000000000000 337 STFPC 0(R8) Store resulting FPCR flags and DXC + 338 * +0000000000000408 B29D F27C 000000000000027C 339 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000040C B2B8 1000 0000000000000000 340 SRNMB 0(R1) Set FPC Rounding Mode +0000000000000410 ED80 3000 0014 0000000000000000 341 SQEB FPR8,0(,R3) Take square root of value into FPR8 RXE +0000000000000416 7080 7004 0000000000000004 342 STE FPR8,4(,R7) Store short BFP quotient +000000000000041A B29C 8004 0000000000000004 343 STFPC 4(R8) Store resulting FPCR flags and DXC + 344 * +000000000000041E 4170 7008 0000000000000008 345 LA R7,8(,R7) Point to next square root result +0000000000000422 4180 8008 0000000000000008 346 LA R8,8(,R8) Point to next FPCR result area + 347 * +0000000000000426 0659 348 BCTR R5,R9 Iterate to next FPC mode + 349 * + 350 * End of FPC modes to be tested. Advance to next test case. + 351 * +0000000000000428 4130 3004 0000000000000004 352 LA R3,4(,R3) Point to next input value +000000000000042C 4170 7008 0000000000000008 353 LA R7,8(,R7) Skip to start of next result area + ASMA Ver. 0.2.0 bfp-015-sqrt.asm: Test IEEE Square Root 23 Sep 2016 12:38:52 Page 10 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000430 4180 8008 0000000000000008 354 LA R8,8(,R8) Skip to start of next FPCR result area +0000000000000434 062C 355 BCTR R2,R12 Divide next input value lots of times + 356 * +0000000000000436 07FD 357 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-015-sqrt.asm: Test IEEE Square Root 23 Sep 2016 12:38:52 Page 11 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 359 *********************************************************************** + 360 * + 361 * Take square roots using provided long BFP inputs. This set of tests + 362 * checks NaN propagation, operations on values that are not finite + 363 * numbers, and other basic tests. This set generates results that can + 364 * be validated against Figure 19-17 on page 19-21 of SA22-7832-10. + 365 * + 366 * Four results are generated for each input: one RRE with all + 367 * exceptions non-trappable, a second RRE with all exceptions trappable, + 368 * a third RXE with all exceptions non-trappable, a fourth RXE with all + 369 * exceptions trappable, + 370 * + 371 * The square root and FPCR are stored for each result. + 372 * + 373 *********************************************************************** + + +0000000000000438 375 LBFPB DS 0H BFP long basic tests +0000000000000438 9823 A000 0000000000000000 376 LM R2,R3,0(R10) Get count and address of dividendd values +000000000000043C 9878 A008 0000000000000008 377 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000440 1222 378 LTR R2,R2 Any test cases? +0000000000000442 078D 379 BZR R13 ..No, return to caller +0000000000000444 0DC0 380 BASR R12,0 Set top of loop + 381 * +0000000000000446 B375 0080 382 LZDR FPR8 Zero result register +000000000000044A 6810 3000 0000000000000000 383 LD FPR1,0(,R3) Get long BFP input +000000000000044E B29D F27C 000000000000027C 384 LFPC FPCREGNT Set exceptions non-trappable +0000000000000452 B315 0081 385 SQDBR FPR8,FPR1 Take square root of FPR1 into FPR8 RRE +0000000000000456 6080 7000 0000000000000000 386 STD FPR8,0(,R7) Store long BFP square root +000000000000045A B29C 8000 0000000000000000 387 STFPC 0(R8) Store resulting FPCR flags and DXC + 388 * +000000000000045E B375 0080 389 LZDR FPR8 Zero result register +0000000000000462 B29D F280 0000000000000280 390 LFPC FPCREGTR Set exceptions trappable +0000000000000466 B315 0081 391 SQDBR FPR8,FPR1 Take square root of FPR1 into FPR8 RRE +000000000000046A 6080 7008 0000000000000008 392 STD FPR8,8(,R7) Store long BFP square root +000000000000046E B29C 8004 0000000000000004 393 STFPC 4(R8) Store resulting FPCR flags and DXC + 394 * +0000000000000472 B375 0080 395 LZDR FPR8 Zero result register +0000000000000476 B29D F27C 000000000000027C 396 LFPC FPCREGNT Set exceptions non-trappable +000000000000047A ED80 3000 0015 0000000000000000 397 SQDB FPR8,0(,R3) Take square root, place in FPR8 RXE +0000000000000480 6080 7010 0000000000000010 398 STD FPR8,16(,R7) Store long BFP square root +0000000000000484 B29C 8008 0000000000000008 399 STFPC 8(R8) Store resulting FPCR flags and DXC + 400 * +0000000000000488 B375 0080 401 LZDR FPR8 Zero result register +000000000000048C B29D F280 0000000000000280 402 LFPC FPCREGTR Set exceptions trappable +0000000000000490 ED80 3000 0015 0000000000000000 403 SQDB FPR8,0(,R3) Take square root, place in FPR8 RXE +0000000000000496 6080 7018 0000000000000018 404 STD FPR8,24(,R7) Store short BFP square root +000000000000049A B29C 800C 000000000000000C 405 STFPC 12(R8) Store resulting FPCR flags and DXC + 406 * +000000000000049E 4170 7020 0000000000000020 407 LA R7,32(,R7) Point to next Square Root result area +00000000000004A2 4180 8010 0000000000000010 408 LA R8,16(,R8) Point to next Square Root FPCR area +00000000000004A6 4130 3008 0000000000000008 409 LA R3,8(,R3) Point to next input value + ASMA Ver. 0.2.0 bfp-015-sqrt.asm: Test IEEE Square Root 23 Sep 2016 12:38:52 Page 12 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000004AA 062C 410 BCTR R2,R12 Convert next input value. + 411 * +00000000000004AC 07FD 412 BR R13 All converted; return. + 413 * + ASMA Ver. 0.2.0 bfp-015-sqrt.asm: Test IEEE Square Root 23 Sep 2016 12:38:52 Page 13 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 415 *********************************************************************** + 416 * + 417 * Perform Square Root using provided long BFP inputs. This set of + 418 * tests exhaustively tests all rounding modes available for Square + 419 * Root. The rounding mode can only be specified in the FPC. + 420 * + 421 * All five FPC rounding modes are tested because the preceeding tests, + 422 * using rounding mode RNTE, do not often create results that require + 423 * rounding. + 424 * + 425 * Two results are generated for each input and rounding mode: one RRE + 426 * and one RXE. Traps are disabled for all rounding mode tests. + 427 * + 428 * The quotient and FPCR contents are stored for each test. + 429 * + 430 *********************************************************************** + + +00000000000004AE 9823 A000 0000000000000000 432 LBFPRM LM R2,R3,0(R10) Get count and address of test input values +00000000000004B2 9878 A008 0000000000000008 433 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000004B6 1222 434 LTR R2,R2 Any test cases? +00000000000004B8 078D 435 BZR R13 ..No, return to caller +00000000000004BA 1711 436 XR R1,R1 Zero register 1 for use in IC/STC/indexing +00000000000004BC 0DC0 437 BASR R12,0 Set top of test case loop + 438 +00000000000004BE 4150 0005 0000000000000005 439 LA R5,FPCMCT Get count of FPC modes to be tested +00000000000004C2 0D90 440 BASR R9,0 Set top of rounding mode outer loop + 441 * +00000000000004C4 4315 F5B1 00000000000005B1 442 IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode + 443 * +00000000000004C8 B29D F27C 000000000000027C 444 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000004CC B2B8 1000 0000000000000000 445 SRNMB 0(R1) Set FPC Rounding Mode +00000000000004D0 6810 3000 0000000000000000 446 LD FPR1,0(,R3) Get long BFP input value +00000000000004D4 B315 0081 447 SQDBR FPR8,FPR1 Take square root of FPR1 into FPR8 RRE +00000000000004D8 6080 7000 0000000000000000 448 STD FPR8,0(,R7) Store long BFP quotient +00000000000004DC B29C 8000 0000000000000000 449 STFPC 0(R8) Store resulting FPCR flags and DXC + 450 * +00000000000004E0 B29D F27C 000000000000027C 451 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000004E4 B2B8 1000 0000000000000000 452 SRNMB 0(R1) Set FPC Rounding Mode +00000000000004E8 ED80 3000 0015 0000000000000000 453 SQDB FPR8,0(,R3) Take square root of value into FPR8 RXE +00000000000004EE 6080 7008 0000000000000008 454 STD FPR8,8(,R7) Store short BFP quotient +00000000000004F2 B29C 8004 0000000000000004 455 STFPC 4(R8) Store resulting FPCR flags and DXC + 456 * +00000000000004F6 4170 7010 0000000000000010 457 LA R7,16(,R7) Point to next square root result +00000000000004FA 4180 8008 0000000000000008 458 LA R8,8(,R8) Point to next FPCR result area + 459 * +00000000000004FE 0659 460 BCTR R5,R9 Iterate to next FPC mode + 461 * + 462 * End of FPC modes to be tested. Advance to next test case. + 463 * +0000000000000500 4130 3008 0000000000000008 464 LA R3,8(,R3) Point to next input value +0000000000000504 4180 8008 0000000000000008 465 LA R8,8(,R8) Skip to start of next FPCR result area + ASMA Ver. 0.2.0 bfp-015-sqrt.asm: Test IEEE Square Root 23 Sep 2016 12:38:52 Page 14 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000508 062C 466 BCTR R2,R12 Divide next input value lots of times + 467 * +000000000000050A 07FD 468 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-015-sqrt.asm: Test IEEE Square Root 23 Sep 2016 12:38:52 Page 15 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 470 *********************************************************************** + 471 * + 472 * Take square roots using provided extended BFP inputs. This set of + 473 * tests checks NaN propagation, operations on values that are not + 474 * finite numbers, and other basic tests. This set generates results + 475 * that can be validated against Figure 19-17 on page 19-21 of + 476 * SA22-7832-10. + 477 * + 478 * Four results are generated for each input: one RRE with all + 479 * exceptions non-trappable, a second RRE with all exceptions trappable, + 480 * a third RXE with all exceptions non-trappable, a fourth RXE with all + 481 * exceptions trappable, + 482 * + 483 * The square root and FPCR are stored for each result. + 484 * + 485 *********************************************************************** + + +000000000000050C 487 XBFPB DS 0H BFP extended basic tests +000000000000050C 9823 A000 0000000000000000 488 LM R2,R3,0(R10) Get count and address of dividendd values +0000000000000510 9878 A008 0000000000000008 489 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000514 1222 490 LTR R2,R2 Any test cases? +0000000000000516 078D 491 BZR R13 ..No, return to caller +0000000000000518 0DC0 492 BASR R12,0 Set top of loop + 493 * +000000000000051A B376 0080 494 LZXR FPR8 Zero result register +000000000000051E 6810 3000 0000000000000000 495 LD FPR1,0(,R3) Get extended BFP input part 1 +0000000000000522 6830 3008 0000000000000008 496 LD FPR3,8(,R3) Get extended BFP input part 2 +0000000000000526 B29D F27C 000000000000027C 497 LFPC FPCREGNT Set exceptions non-trappable +000000000000052A B316 0081 498 SQXBR FPR8,FPR1 Take square root of FPR1 into FPR8-10 RRE +000000000000052E 6080 7000 0000000000000000 499 STD FPR8,0(,R7) Store extended BFP square root part 1 +0000000000000532 60A0 7008 0000000000000008 500 STD FPR10,8(,R7) Store extended BFP square root part 2 +0000000000000536 B29C 8000 0000000000000000 501 STFPC 0(R8) Store resulting FPCR flags and DXC + 502 * +000000000000053A B376 0080 503 LZXR FPR8 Zero result register +000000000000053E B29D F280 0000000000000280 504 LFPC FPCREGTR Set exceptions trappable +0000000000000542 B316 0081 505 SQXBR FPR8,FPR1 Take square root of FPR1 into FPR8-10 RRE +0000000000000546 6080 7010 0000000000000010 506 STD FPR8,16(,R7) Store extended BFP square root part 1 +000000000000054A 60A0 7018 0000000000000018 507 STD FPR10,24(,R7) Store extended BFP square root part 2 +000000000000054E B29C 8004 0000000000000004 508 STFPC 4(R8) Store resulting FPCR flags and DXC + 509 * +0000000000000552 4170 7020 0000000000000020 510 LA R7,32(,R7) Point to next Square Root result area +0000000000000556 4180 8010 0000000000000010 511 LA R8,16(,R8) Point to next Square Root FPCR area +000000000000055A 4130 3010 0000000000000010 512 LA R3,16(,R3) Point to next input value +000000000000055E 062C 513 BCTR R2,R12 Convert next input value. + 514 * +0000000000000560 07FD 515 BR R13 All converted; return. + 516 * + ASMA Ver. 0.2.0 bfp-015-sqrt.asm: Test IEEE Square Root 23 Sep 2016 12:38:52 Page 16 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 518 *********************************************************************** + 519 * + 520 * Perform Square Root using provided extended BFP inputs. This set of + 521 * tests exhaustively tests all rounding modes available for Square + 522 * Root. The rounding mode can only be specified in the FPC. + 523 * + 524 * All five FPC rounding modes are tested because the preceeding tests, + 525 * using rounding mode RNTE, do not often create results that require + 526 * rounding. + 527 * + 528 * Two results are generated for each input and rounding mode: one RRE + 529 * and one RXE. Traps are disabled for all rounding mode tests. + 530 * + 531 * The quotient and FPCR contents are stored for each test. + 532 * + 533 *********************************************************************** + + +0000000000000562 9823 A000 0000000000000000 535 XBFPRM LM R2,R3,0(R10) Get count and address of test input values +0000000000000566 9878 A008 0000000000000008 536 LM R7,R8,8(R10) Get address of result area and flag area. +000000000000056A 1222 537 LTR R2,R2 Any test cases? +000000000000056C 078D 538 BZR R13 ..No, return to caller +000000000000056E 1711 539 XR R1,R1 Zero register 1 for use in IC/STC/indexing +0000000000000570 0DC0 540 BASR R12,0 Set top of test case loop + 541 +0000000000000572 4150 0005 0000000000000005 542 LA R5,FPCMCT Get count of FPC modes to be tested +0000000000000576 0D90 543 BASR R9,0 Set top of rounding mode outer loop + 544 * +0000000000000578 4315 F5B1 00000000000005B1 545 IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode + 546 * +000000000000057C B29D F27C 000000000000027C 547 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000580 B2B8 1000 0000000000000000 548 SRNMB 0(R1) Set FPC Rounding Mode +0000000000000584 6810 3000 0000000000000000 549 LD FPR1,0(,R3) Get long BFP input value part 1 +0000000000000588 6830 3008 0000000000000008 550 LD FPR3,8(,R3) Get long BFP input value part 2 +000000000000058C B316 0081 551 SQXBR FPR8,FPR1 Take square root of FPR1 into FPR8 RRE +0000000000000590 6080 7000 0000000000000000 552 STD FPR8,0(,R7) Store extended BFP root part 1 +0000000000000594 60A0 7008 0000000000000008 553 STD FPR10,8(,R7) Store extended BFP root part 2 +0000000000000598 B29C 8000 0000000000000000 554 STFPC 0(R8) Store resulting FPCR flags and DXC + 555 * +000000000000059C 4170 7010 0000000000000010 556 LA R7,16(,R7) Point to next square root result +00000000000005A0 4180 8004 0000000000000004 557 LA R8,4(,R8) Point to next FPCR result area + 558 * +00000000000005A4 0659 559 BCTR R5,R9 Iterate to next FPC mode + 560 * + 561 * End of FPC modes to be tested. Advance to next test case. + 562 * +00000000000005A6 4130 3010 0000000000000010 563 LA R3,16(,R3) Point to next input value +00000000000005AA 4180 800C 000000000000000C 564 LA R8,12(,R8) Skip to start of next FPCR result area +00000000000005AE 062C 565 BCTR R2,R12 Divide next input value lots of times + 566 * +00000000000005B0 07FD 567 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-015-sqrt.asm: Test IEEE Square Root 23 Sep 2016 12:38:52 Page 17 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 569 *********************************************************************** + 570 * + 571 * Table of FPC rounding modes to test quotient rounding modes. + 572 * + 573 * The Set BFP Rounding Mode does allow specification of the FPC + 574 * rounding mode as an address, so we shall index into a table of + 575 * BFP rounding modes without bothering with Execute. + 576 * + 577 *********************************************************************** + + + 579 * + 580 * Rounding modes that may be set in the FPCR. The FPCR controls + 581 * rounding of the quotient. + 582 * + 583 * These are indexed directly by the loop counter, which counts down. + 584 * So the modes are listed in reverse order here. + 585 * +00000000000005B2 586 FPCMODES DS 0C +00000000000005B2 07 587 DC AL1(7) RFS, Round for shorter precision +00000000000005B3 03 588 DC AL1(3) RM, Round to -infinity +00000000000005B4 02 589 DC AL1(2) RP, Round to +infinity +00000000000005B5 01 590 DC AL1(1) RZ, Round to zero +00000000000005B6 00 591 DC AL1(0) RNTE, Round to Nearest, ties to even + 0000000000000005 0000000000000001 592 FPCMCT EQU *-FPCMODES Count of FPC Modes to be tested + 593 * + ASMA Ver. 0.2.0 bfp-015-sqrt.asm: Test IEEE Square Root 23 Sep 2016 12:38:52 Page 18 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 595 *********************************************************************** + 596 * + 597 * Short BFP test data sets for Square Root testing. + 598 * + 599 * The first test data set is used for tests of basic functionality, + 600 * NaN propagation, and results from operations involving other than + 601 * finite numbers. + 602 * + 603 * The second test data set is used for testing boundary conditions + 604 * using finite non-zero values. Each possible type of result (normal, + 605 * scaled, etc) is created by members of this test data set. + 606 * + 607 * The third test data set is used for exhaustive testing of final + 608 * results across the five rounding modes available for the Square Root + 609 * instruction. + 610 * + 611 *********************************************************************** + + + 613 *********************************************************************** + 614 * + 615 * First input test data set, to test operations using non-finite or + 616 * zero inputs. Member values chosen to validate part 1 of Figure 19-17 + 617 * on page 19-21 of SA22-7832-10. + 618 * + 619 *********************************************************************** + + +00000000000005B8 621 SBFPBIN DS 0F Inputs for short BFP basic tests +00000000000005B8 FF800000 622 DC X'FF800000' -inf +00000000000005BC C0800000 623 DC X'C0800000' -4.0 +00000000000005C0 80000000 624 DC X'80000000' -0 +00000000000005C4 00000000 625 DC X'00000000' +0 +00000000000005C8 40800000 626 DC X'40800000' +4.0 +00000000000005CC 7F800000 627 DC X'7F800000' +inf +00000000000005D0 FFCB0000 628 DC X'FFCB0000' -QNaN +00000000000005D4 7F8A0000 629 DC X'7F8A0000' +SNaN +00000000000005D8 40400000 630 DC X'40400000' +3.0 Inexact, truncated +00000000000005DC 40A00000 631 DC X'40A00000' +5.0 Inexact, incremented +00000000000005E0 3D800000 632 DC X'3D800000' +0.0625 exact, expect 0.25 + 000000000000000B 0000000000000001 633 SBFPBCT EQU (*-SBFPBIN)/4 Count of short BFP in list + + + + 635 *********************************************************************** + 636 * + 637 * Second input test data set. These are finite positive values + 638 * intended to test all combinations of rounding mode for a given + 639 * result. Values are chosen to create a requirement to round to the + 640 * target precision after the computation + 641 * + 642 *********************************************************************** + ASMA Ver. 0.2.0 bfp-015-sqrt.asm: Test IEEE Square Root 23 Sep 2016 12:38:52 Page 19 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + + +00000000000005E4 644 SBFPINRM DS 0F Inputs for short BFP rounding testing + 645 * +00000000000005E4 40400000 646 DC X'40400000' +3.0 Inexact, truncated +00000000000005E8 40A00000 647 DC X'40A00000' +5.0 Inexact, incremented + 648 * + 0000000000000002 0000000000000001 649 SBFPRMCT EQU (*-SBFPINRM)/4 Count of short BFP rounding tests + ASMA Ver. 0.2.0 bfp-015-sqrt.asm: Test IEEE Square Root 23 Sep 2016 12:38:52 Page 20 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 651 *********************************************************************** + 652 * + 653 * Long BFP test data sets for Divide testing. + 654 * + 655 * The first test data set is used for tests of basic functionality, + 656 * NaN propagation, and results from operations involving other than + 657 * finite numbers. + 658 * + 659 * The second test data set is used for testing boundary conditions + 660 * using finite non-zero values. Each possible type of result (normal, + 661 * scaled, etc) is created by members of this test data set. + 662 * + 663 * The third test data set is used for exhaustive testing of final + 664 * results across the five rounding modes available for the Square Root + 665 * instruction. + 666 * + 667 *********************************************************************** + + + 669 *********************************************************************** + 670 * + 671 * First input test data set, to test operations using non-finite or + 672 * zero inputs. Member values chosen to validate part 1 of Figure 19-17 + 673 * on page 19-21 of SA22-7832-10. + 674 * + 675 *********************************************************************** + + +00000000000005F0 677 LBFPBIN DS 0D Inputs for long BFP testing +00000000000005F0 FFF00000 00000000 678 DC X'FFF0000000000000' -inf +00000000000005F8 C0100000 00000000 679 DC X'C010000000000000' -4.0 +0000000000000600 80000000 00000000 680 DC X'8000000000000000' -0 +0000000000000608 00000000 00000000 681 DC X'0000000000000000' +0 +0000000000000610 40100000 00000000 682 DC X'4010000000000000' +4.0 +0000000000000618 7FF00000 00000000 683 DC X'7FF0000000000000' +inf +0000000000000620 FFF8B000 00000000 684 DC X'FFF8B00000000000' -QNaN +0000000000000628 7FF0A000 00000000 685 DC X'7FF0A00000000000' +SNaN +0000000000000630 40080000 00000000 686 DC X'4008000000000000' +3.0 Inexact, truncated +0000000000000638 40140000 00000000 687 DC X'4014000000000000' +5.0 Inexact, incremented +0000000000000640 3FB00000 00000000 688 DC X'3FB0000000000000' +0.0625 exact, expect 0.25 + 000000000000000B 0000000000000001 689 LBFPBCT EQU (*-LBFPBIN)/8 Count of long BFP in list + + + + 691 *********************************************************************** + 692 * + 693 * Second input test data set. These are finite positive values + 694 * intended to test all combinations of rounding mode for a given + 695 * result. Values are chosen to create a requirement to round to the + 696 * target precision after the computation + 697 * + 698 *********************************************************************** + ASMA Ver. 0.2.0 bfp-015-sqrt.asm: Test IEEE Square Root 23 Sep 2016 12:38:52 Page 21 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + + +0000000000000648 700 LBFPINRM DS 0F + 701 * +0000000000000648 40080000 00000000 702 DC X'4008000000000000' +3.0 Inexact, truncated +0000000000000650 40140000 00000000 703 DC X'4014000000000000' +5.0 Inexact, incremented + 704 * + 0000000000000002 0000000000000001 705 LBFPRMCT EQU (*-LBFPINRM)/8 Count of long BFP rounding tests * 8 + ASMA Ver. 0.2.0 bfp-015-sqrt.asm: Test IEEE Square Root 23 Sep 2016 12:38:52 Page 22 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 707 *********************************************************************** + 708 * + 709 * Extended BFP test data sets for Divide testing. + 710 * + 711 * The first test data set is used for tests of basic functionality, + 712 * NaN propagation, and results from operations involving other than + 713 * finite numbers. + 714 * + 715 * The second test data set is used for testing boundary conditions + 716 * using finite non-zero values. Each possible type of result (normal, + 717 * scaled, etc) is created by members of this test data set. + 718 * + 719 * The third test data set is used for exhaustive testing of final + 720 * results across the five rounding modes available for the Square Root + 721 * instruction. + 722 * + 723 *********************************************************************** + + + 725 *********************************************************************** + 726 * + 727 * First input test data set, to test operations using non-finite or + 728 * zero inputs. Member values chosen to validate part 1 of Figure 19-17 + 729 * on page 19-21 of SA22-7832-10. + 730 * + 731 *********************************************************************** + + +0000000000000658 733 XBFPBIN DS 0D Inputs for extended BFP testing +0000000000000658 FFFF0000 00000000 734 DC X'FFFF0000000000000000000000000000' -inf +0000000000000668 C0010000 00000000 735 DC X'C0010000000000000000000000000000' -4.0 +0000000000000678 80000000 00000000 736 DC X'80000000000000000000000000000000' -0 +0000000000000688 00000000 00000000 737 DC X'00000000000000000000000000000000' +0 +0000000000000698 40010000 00000000 738 DC X'40010000000000000000000000000000' +4.0 +00000000000006A8 7FFF0000 00000000 739 DC X'7FFF0000000000000000000000000000' +inf +00000000000006B8 FFFF8B00 00000000 740 DC X'FFFF8B00000000000000000000000000' -QNaN +00000000000006C8 7FFF0A00 00000000 741 DC X'7FFF0A00000000000000000000000000' +SNaN +00000000000006D8 40008000 00000000 742 DC X'40008000000000000000000000000000' +3.0 Inexact, trunc. +00000000000006E8 40014000 00000000 743 DC X'40014000000000000000000000000000' +5.0 Inexact, incre. +00000000000006F8 3FFB0000 00000000 744 DC X'3FFB0000000000000000000000000000' +0.0625 expect 0.25 + 000000000000000B 0000000000000001 745 XBFPBCT EQU (*-XBFPBIN)/16 Count of extended BFP in list + + + + 747 *********************************************************************** + 748 * + 749 * Second input test data set. These are finite positive values + 750 * intended to test all combinations of rounding mode for a given + 751 * result. Values are chosen to create a requirement to round to the + 752 * target precision after the computation + 753 * + 754 *********************************************************************** + ASMA Ver. 0.2.0 bfp-015-sqrt.asm: Test IEEE Square Root 23 Sep 2016 12:38:52 Page 23 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + + +0000000000000708 756 XBFPINRM DS 0D + 757 * +0000000000000708 40008000 00000000 758 DC X'40008000000000000000000000000000' +3.0 Inexact, trunc. +0000000000000718 40014000 00000000 759 DC X'40014000000000000000000000000000' +5.0 Inexact, incre. + 760 * + 0000000000000002 0000000000000001 761 XBFPRMCT EQU (*-XBFPINRM)/16 Count of long BFP rounding tests + ASMA Ver. 0.2.0 bfp-015-sqrt.asm: Test IEEE Square Root 23 Sep 2016 12:38:52 Page 24 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 763 * + 764 * Locations for results + 765 * + 0000000000001000 0000000000000001 766 SBFPBOT EQU STRTLABL+X'1000' Integer short non-finite BFP results + 767 * ..room for 16 tests, 8 used + 0000000000001100 0000000000000001 768 SBFPBFL EQU STRTLABL+X'1100' FPCR flags and DXC from short BFP + 769 * ..room for 16 tests, 8 used + 770 * + 0000000000001200 0000000000000001 771 SBFPRMO EQU STRTLABL+X'1200' Short BFP rounding mode test results + 772 * ..Room for 16, 2 used. + 0000000000001400 0000000000000001 773 SBFPRMOF EQU STRTLABL+X'1400' Short BFP rounding mode FPCR results + 774 * ..Room for 16, 2 used. + 775 * ..next location starts at X'1600' + 776 * + 0000000000003000 0000000000000001 777 LBFPBOT EQU STRTLABL+X'3000' Integer long non-finite BFP results + 778 * ..room for 16 tests, 8 used + 0000000000003200 0000000000000001 779 LBFPBFL EQU STRTLABL+X'3200' FPCR flags and DXC from long BFP + 780 * ..room for 16 tests, 8 used + 781 * + 0000000000003400 0000000000000001 782 LBFPRMO EQU STRTLABL+X'3400' Long BFP rounding mode test results + 783 * ..Room for 16, 4 used. + 0000000000003700 0000000000000001 784 LBFPRMOF EQU STRTLABL+X'3700' Long BFP rounding mode FPCR results + 785 * ..Room for 16, 4 used. + 786 * ..next location starts at X'3800' + 787 * + 0000000000005000 0000000000000001 788 XBFPBOT EQU STRTLABL+X'5000' Integer ext'd non-finite BFP results + 789 * ..room for 16 tests, 8 used + 0000000000005400 0000000000000001 790 XBFPBFL EQU STRTLABL+X'5400' FPCR flags and DXC from ext'd BFP + 791 * ..room for 16 tests, 8 used + 792 * + 0000000000005500 0000000000000001 793 XBFPRMO EQU STRTLABL+X'5500' Ext'd BFP rounding mode test results + 794 * ..Room for 16, 4 used. + 0000000000005A00 0000000000000001 795 XBFPRMOF EQU STRTLABL+X'5A00' Ext'd BFP rounding mode FPCR results + 796 * ..Room for 16, 4 used. + 797 * ..next location starts at X'5B00' + 798 * + 0000000000005B00 0000000000000001 799 ENDLABL EQU STRTLABL+X'5B00' + 800 PADCSECT ENDLABL + 801+ MNOTE *,'asma detected; no CSECT padding performed' + 802 * +0000000000000728 803 END + ASMA Ver. 0.2.0 bfp-015-sqrt.asm: Test IEEE Square Root 23 Sep 2016 12:38:52 Page 25 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +BFPSQRTS J 000000 1832 87 208 +CTLR0 F 000278 4 198 170 171 172 +ENDLABL U 005B00 1 799 +FPCMCT U 000005 1 592 327 439 542 +FPCMODES C 0005B2 1 586 592 330 442 545 +FPCREGNT X 00027C 4 199 272 284 332 339 384 396 444 451 497 547 +FPCREGTR X 000280 4 200 278 290 390 402 504 +FPR0 U 000000 1 108 +FPR1 U 000001 1 109 271 273 279 334 335 383 385 391 446 447 495 498 505 549 551 +FPR10 U 00000A 1 118 500 507 553 +FPR11 U 00000B 1 119 +FPR12 U 00000C 1 120 +FPR13 U 00000D 1 121 +FPR14 U 00000E 1 122 +FPR15 U 00000F 1 123 +FPR2 U 000002 1 110 +FPR3 U 000003 1 111 496 550 +FPR4 U 000004 1 112 +FPR5 U 000005 1 113 +FPR6 U 000006 1 114 +FPR7 U 000007 1 115 +FPR8 U 000008 1 116 270 273 274 277 279 280 283 285 286 289 291 292 335 336 341 342 382 + 385 386 389 391 392 395 397 398 401 403 404 447 448 453 454 494 498 + 499 503 505 506 551 552 +FPR9 U 000009 1 117 +HARDWAIT X 000268 8 196 161 +IMAGE 1 000000 1832 0 +LBFPB H 000438 2 375 180 +LBFPBCT U 00000B 1 689 223 +LBFPBFL U 003200 1 779 226 +LBFPBIN D 0005F0 8 677 689 224 +LBFPBOT U 003000 1 777 225 +LBFPINRM F 000648 4 700 705 230 +LBFPRM I 0004AE 4 432 182 +LBFPRMCT U 000002 1 705 229 +LBFPRMO U 003400 1 782 231 +LBFPRMOF U 003700 1 784 232 +LONGB F 000320 4 222 179 +PCINTCD H 00008E 2 138 155 +PCNOTDTA H 00020C 2 158 156 +PCOLDPSW U 000150 1 140 157 +PROGCHK H 000200 2 154 146 +R0 U 000000 1 89 170 172 +R1 U 000001 1 90 324 330 333 340 436 442 445 452 539 545 548 +R10 U 00000A 1 99 174 176 179 181 184 186 264 265 320 321 376 377 432 433 488 489 535 + 536 +R11 U 00000B 1 100 +R12 U 00000C 1 101 268 298 325 355 380 410 437 466 492 513 540 565 +R13 U 00000D 1 102 175 177 180 182 185 187 267 300 323 357 379 412 435 468 491 515 538 + 567 +R14 U 00000E 1 103 159 160 189 190 +R15 U 00000F 1 104 125 + ASMA Ver. 0.2.0 bfp-015-sqrt.asm: Test IEEE Square Root 23 Sep 2016 12:38:52 Page 26 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +R2 U 000002 1 91 264 266 298 320 322 355 376 378 410 432 434 466 488 490 513 535 537 + 565 +R3 U 000003 1 92 264 271 285 291 297 320 334 341 352 376 383 397 403 409 432 446 453 + 464 488 495 496 512 535 549 550 563 +R4 U 000004 1 93 +R5 U 000005 1 94 327 330 348 439 442 460 542 545 559 +R6 U 000006 1 95 +R7 U 000007 1 96 265 274 280 286 292 295 321 336 342 345 353 377 386 392 398 404 407 + 433 448 454 457 489 499 500 506 507 510 536 552 553 556 +R8 U 000008 1 97 265 275 281 287 293 296 321 337 343 346 354 377 387 393 399 405 408 + 433 449 455 458 465 489 501 508 511 536 554 557 564 +R9 U 000009 1 98 328 348 440 460 543 559 +RMLONGS F 000330 4 228 181 +RMSHORTS F 000310 4 216 176 +RMXTNDS F 000350 4 240 186 +SBFPB H 000360 2 263 175 +SBFPBCT U 00000B 1 633 211 +SBFPBFL U 001100 1 768 214 +SBFPBIN F 0005B8 4 621 633 212 +SBFPBOT U 001000 1 766 213 +SBFPINRM F 0005E4 4 644 649 218 +SBFPRM I 0003D6 4 320 177 +SBFPRMCT U 000002 1 649 217 +SBFPRMO U 001200 1 771 219 +SBFPRMOF U 001400 1 773 220 +SHORTB F 000300 4 210 174 +START H 000214 2 169 143 +STRTLABL U 000000 1 88 137 140 142 145 153 209 766 768 771 773 777 779 782 784 788 790 793 + 795 799 +WAITPSW X 000258 8 195 191 +XBFPB H 00050C 2 487 185 +XBFPBCT U 00000B 1 745 235 +XBFPBFL U 005400 1 790 238 +XBFPBIN D 000658 8 733 745 236 +XBFPBOT U 005000 1 788 237 +XBFPINRM D 000708 8 756 761 242 +XBFPRM I 000562 4 535 187 +XBFPRMCT U 000002 1 761 241 +XBFPRMO U 005500 1 793 243 +XBFPRMOF U 005A00 1 795 244 +XTNDB F 000340 4 234 184 + ASMA Ver. 0.2.0 bfp-015-sqrt.asm: Test IEEE Square Root 23 Sep 2016 12:38:52 Page 27 + + MACRO DEFN REFERENCES + +PADCSECT 62 800 + ASMA Ver. 0.2.0 bfp-015-sqrt.asm: Test IEEE Square Root 23 Sep 2016 12:38:52 Page 28 + + DESC SYMBOL SIZE POS ADDR + +Entry: 0 + +Image IMAGE 1832 000-727 000-727 + Region 1832 000-727 000-727 + CSECT BFPSQRTS 1832 000-727 000-727 + ASMA Ver. 0.2.0 bfp-015-sqrt.asm: Test IEEE Square Root 23 Sep 2016 12:38:52 Page 29 + + STMT FILE NAME + +1 C:\Users\srorso\Documents\GitHub\hyperion\tests\bfp-015-sqrt.asm + + +** NO ERRORS FOUND ** + +[801] MNOTE *,asma detected; no CSECT padding performed + \ No newline at end of file diff --git a/tests/bfp-015-sqrt.tst b/tests/bfp-015-sqrt.tst new file mode 100644 index 000000000..0113b9370 --- /dev/null +++ b/tests/bfp-015-sqrt.tst @@ -0,0 +1,333 @@ +*Testcase bfp-015-sqrt.tst: SQEBR, SQEB, SQDBR, SQDB, SQXBR + +#Testcase bfp-015-sqrts.tst: IEEE Square Root +#..Includes SQUARE ROOT (5), 5 instructions total. Test cases cover +#..NaN propagation, non-finite and negative input values, rounding, +#..invalid and inexact traps, and DXC codes for incremented. + +sysclear +archmode esame + +# +# Following suppresses logging of program checks. This test program, as part +# of its normal operation, generates 25 program check messages that have no +# value in the validation process. +# +ostailor quiet + +loadcore "$(testpath)/bfp-015-sqrt.core" +runtest 1.0 + +ostailor null # restore messages for subsequent tests + + +# Short BFP Basic test results +*Compare +r 1000.10 +*Want "SQEBR/SQEB -inf" 7FC00000 00000000 7FC00000 00000000 +r 1010.10 +*Want "SQEBR/SQEB -4" 7FC00000 00000000 7FC00000 00000000 +r 1020.10 +*Want "SQEBR/SQEB -0" 80000000 80000000 80000000 80000000 +r 1030.10 +*Want "SQEBR/SQEB +0" 00000000 00000000 00000000 00000000 +r 1040.10 +*Want "SQEBR/SQEB +4" 40000000 40000000 40000000 40000000 +r 1050.10 +*Want "SQEBR/SQEB +inf" 7F800000 7F800000 7F800000 7F800000 +r 1060.10 +*Want "SQEBR/SQEB -QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1070.10 +*Want "SQEBR/SQEB +SNaN" 7FCA0000 00000000 7FCA0000 00000000 +r 1080.10 +*Want "SQEBR/SQEB +3" 3FDDB3D7 3FDDB3D7 3FDDB3D7 3FDDB3D7 +r 1090.10 +*Want "SQEBR/SQEB +5" 400F1BBD 400F1BBD 400F1BBD 400F1BBD +r 10A0.10 +*Want "SQEBR/SQEB +0.0625" 3E800000 3E800000 3E800000 3E800000 + + +# Short BFP Basic test results - FPCR contents +*Compare +r 1100.10 +*Want "SQEBR/SQEB -inf FPCR" 00800000 F8008000 00800000 F8008000 +r 1110.10 +*Want "SQEBR/SQEB -4 FPCR" 00800000 F8008000 00800000 F8008000 +r 1120.10 +*Want "SQEBR/SQEB -0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1130.10 +*Want "SQEBR/SQEB +0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1140.10 +*Want "SQEBR/SQEB +4 FPCR" 00000000 F8000000 00000000 F8000000 +r 1150.10 +*Want "SQEBR/SQEB +inf FPCR" 00000000 F8000000 00000000 F8000000 +r 1160.10 +*Want "SQEBR/SQEB -QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 1170.10 +*Want "SQEBR/SQEB +SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 1180.10 +*Want "SQEBR/SQEB +3 FPCR" 00080000 F8000800 00080000 F8000800 +r 1190.10 +*Want "SQEBR/SQEB +5 FPCR" 00080000 F8000C00 00080000 F8000C00 +r 11A0.10 +*Want "SQEBR/SQEB +0.0625 FPCR" 00000000 F8000000 00000000 F8000000 + + +# Short BFP rounding mode test results +*Compare +r 1200.10 +*Want "SQEBR/SQEB RM RNTE,RZ +3" 3FDDB3D7 3FDDB3D7 3FDDB3D7 3FDDB3D7 +r 1210.10 +*Want "SQEBR/SQEB RM RP,RM +3" 3FDDB3D8 3FDDB3D8 3FDDB3D7 3FDDB3D7 +r 1220.08 +*Want "SQEBR/SQEB RM RFS +3" 3FDDB3D7 3FDDB3D7 +r 1230.10 +*Want "SQEBR/SQEB RM RNTE,RZ +5" 400F1BBD 400F1BBD 400F1BBC 400F1BBC +r 1240.10 +*Want "SQEBR/SQEB RM RP,RM +5" 400F1BBD 400F1BBD 400F1BBC 400F1BBC +r 1250.08 +*Want "SQEBR/SQEB RM RFS +5" 400F1BBD 400F1BBD + + +# Short BFP rounding mode test results - FPCR contents +*Compare +r 1400.10 +*Want "SQEBR/SQEB RM RNTE,RZ +3 FPCR" 00080000 00080000 00080001 00080001 +r 1410.10 +*Want "SQEBR/SQEB RM RP,RM +3 FPCR" 00080002 00080002 00080003 00080003 +r 1420.08 +*Want "SQEBR/SQEB RM RFS +3 FPCR" 00080007 00080007 +r 1430.10 +*Want "SQEBR/SQEB RM RNTE,RZ +5 FPCR" 00080000 00080000 00080001 00080001 +r 1440.10 +*Want "SQEBR/SQEB RM RP,RM +5 FPCR" 00080002 00080002 00080003 00080003 +r 1450.08 +*Want "SQEBR/SQEB RM RFS +5 FPCR" 00080007 00080007 + + +# Long BFP basic test results +*Compare +r 3000.10 +*Want "SQDBR -inf" 7FF80000 00000000 00000000 00000000 +r 3010.10 +*Want "SQDB -inf" 7FF80000 00000000 00000000 00000000 +r 3020.10 +*Want "SQDBR -4" 7FF80000 00000000 00000000 00000000 +r 3030.10 +*Want "SQDB -4" 7FF80000 00000000 00000000 00000000 +r 3040.10 +*Want "SQDBR -0" 80000000 00000000 80000000 00000000 +r 3050.10 +*Want "SQDB -0" 80000000 00000000 80000000 00000000 +r 3060.10 +*Want "SQDBR +0" 00000000 00000000 00000000 00000000 +r 3070.10 +*Want "SQDB +0" 00000000 00000000 00000000 00000000 +r 3080.10 +*Want "SQDBR +4" 40000000 00000000 40000000 00000000 +r 3090.10 +*Want "SQDB +4" 40000000 00000000 40000000 00000000 +r 30A0.10 +*Want "SQDBR +inf" 7FF00000 00000000 7FF00000 00000000 +r 30B0.10 +*Want "SQDB +inf" 7FF00000 00000000 7FF00000 00000000 +r 30C0.10 +*Want "SQDBR -QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 30D0.10 +*Want "SQDB -QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 30E0.10 +*Want "SQDBR +SNaN" 7FF8A000 00000000 00000000 00000000 +r 30F0.10 +*Want "SQDB +SNaN" 7FF8A000 00000000 00000000 00000000 +r 3100.10 +*Want "SQDBR +3" 3FFBB67A E8584CAA 3FFBB67A E8584CAA +r 3110.10 +*Want "SQDB +3" 3FFBB67A E8584CAA 3FFBB67A E8584CAA +r 3120.10 +*Want "SQDBR +5" 4001E377 9B97F4A8 4001E377 9B97F4A8 +r 3130.10 +*Want "SQDB +5" 4001E377 9B97F4A8 4001E377 9B97F4A8 +r 3140.10 +*Want "SQDBR 0.0625" 3FD00000 00000000 3FD00000 00000000 +r 3150.10 +*Want "SQDB 0.0625" 3FD00000 00000000 3FD00000 00000000 + + +# Long BFP Basic test results - FPCR contents +*Compare +r 3200.10 +*Want "SQDBR/SQDB -inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3210.10 +*Want "SQDBR/SQDB -4 FPCR" 00800000 F8008000 00800000 F8008000 +r 3220.10 +*Want "SQDBR/SQDB -0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3230.10 +*Want "SQDBR/SQDB +0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3240.10 +*Want "SQDBR/SQDB +4 FPCR" 00000000 F8000000 00000000 F8000000 +r 3250.10 +*Want "SQDBR/SQDB +inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3260.10 +*Want "SQDBR/SQDB -QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3270.10 +*Want "SQDBR/SQDB +SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3280.10 +*Want "SQDBR/SQDB +3 FPCR" 00080000 F8000800 00080000 F8000800 +r 3290.10 +*Want "SQDBR/SQDB +5 FPCR" 00080000 F8000C00 00080000 F8000C00 +r 32A0.10 +*Want "SQDBR/SQDB +0.0625 FPCR" 00000000 F8000000 00000000 F8000000 + + +# Long BFP rounding mode tests +*Compare +r 3400.10 +*Want "SQDBR/SQDB RM RNTE +3" 3FFBB67A E8584CAA 3FFBB67A E8584CAA +r 3410.10 +*Want "SQDBR/SQDB RM RZ +3" 3FFBB67A E8584CAA 3FFBB67A E8584CAA +r 3420.10 +*Want "SQDBR/SQDB RM RP +3" 3FFBB67A E8584CAB 3FFBB67A E8584CAB +r 3430.10 +*Want "SQDBR/SQDB RM RM +3" 3FFBB67A E8584CAA 3FFBB67A E8584CAA +r 3440.10 +*Want "SQDBR/SQDB RM RFS +3" 3FFBB67A E8584CAB 3FFBB67A E8584CAB +r 3450.10 +*Want "SQDBR/SQDB RM RNTE +5" 4001E377 9B97F4A8 4001E377 9B97F4A8 +r 3460.10 +*Want "SQDBR/SQDB RM RZ +5" 4001E377 9B97F4A7 4001E377 9B97F4A7 +r 3470.10 +*Want "SQDBR/SQDB RM RP +5" 4001E377 9B97F4A8 4001E377 9B97F4A8 +r 3480.10 +*Want "SQDBR/SQDB RM RM +5" 4001E377 9B97F4A7 4001E377 9B97F4A7 +r 3490.10 +*Want "SQDBR/SQDB RM RFS +5" 4001E377 9B97F4A7 4001E377 9B97F4A7 + + +# Long BFP rounding mode tests - FPCR contents +*Compare +r 3700.10 +*Want "SQEBR/SQEB RM RNTE,RZ +3 FPCR" 00080000 00080000 00080001 00080001 +r 3710.10 +*Want "SQEBR/SQEB RM RP,RM +3 FPCR" 00080002 00080002 00080003 00080003 +r 3720.08 +*Want "SQEBR/SQEB RM RFS +3 FPCR" 00080007 00080007 +r 3730.10 +*Want "SQEBR/SQEB RM RNTE,RZ +5 FPCR" 00080000 00080000 00080001 00080001 +r 3740.10 +*Want "SQEBR/SQEB RM RP,RM +5 FPCR" 00080002 00080002 00080003 00080003 +r 3750.08 +*Want "SQEBR/SQEB RM RFS +5 FPCR" 00080007 00080007 + + +# Extended BFP basic test results +*Compare +r 5000.10 +*Want "SQXBR NT -inf" 7FFF8000 00000000 00000000 00000000 +r 5010.10 +*Want "SQXBR Tr -inf" 00000000 00000000 00000000 00000000 +r 5020.10 +*Want "SQXBR NT -4" 7FFF8000 00000000 00000000 00000000 +r 5030.10 +*Want "SQXBR Tr -4" 00000000 00000000 00000000 00000000 +r 5040.10 +*Want "SQXBR NT -0" 80000000 00000000 00000000 00000000 +r 5050.10 +*Want "SQXBR Tr -0" 80000000 00000000 00000000 00000000 +r 5060.10 +*Want "SQXBR NT +0" 00000000 00000000 00000000 00000000 +r 5070.10 +*Want "SQXBR Tr +0" 00000000 00000000 00000000 00000000 +r 5080.10 +*Want "SQXBR NT +4" 40000000 00000000 00000000 00000000 +r 5090.10 +*Want "SQXBR Tr +4" 40000000 00000000 00000000 00000000 +r 50A0.10 +*Want "SQXBR NT +inf" 7FFF0000 00000000 00000000 00000000 +r 50B0.10 +*Want "SQXBR Tr +inf" 7FFF0000 00000000 00000000 00000000 +r 50C0.10 +*Want "SQXBR NT -QNaN" FFFF8B00 00000000 00000000 00000000 +r 50D0.10 +*Want "SQXBR Tr -QNaN" FFFF8B00 00000000 00000000 00000000 +r 50E0.10 +*Want "SQXBR NT +SNaN" 7FFF8A00 00000000 00000000 00000000 +r 50F0.10 +*Want "SQXBR Tr +SNaN" 00000000 00000000 00000000 00000000 +r 5100.10 +*Want "SQXBR NT +3" 3FFFBB67 AE8584CA A73B2574 2D7078B8 +r 5110.10 +*Want "SQXBR Tr +3" 3FFFBB67 AE8584CA A73B2574 2D7078B8 +r 5120.10 +*Want "SQXBR NT +5" 40001E37 79B97F4A 7C15F39C C0605CEE +r 5130.10 +*Want "SQXBR Tr +5" 40001E37 79B97F4A 7C15F39C C0605CEE +r 5140.10 +*Want "SQXBR NT 0.0625" 3FFD0000 00000000 00000000 00000000 +r 5150.10 +*Want "SQXBR Tr 0.0625" 3FFD0000 00000000 00000000 00000000 + + +# Extended BFP Basic test results - FPCR contents +*Compare +r 5400.08 +*Want "SQXBR -inf FPCR" 00800000 F8008000 +r 5410.08 +*Want "SQXBR -4 FPCR" 00800000 F8008000 +r 5420.08 +*Want "SQXBR -0 FPCR" 00000000 F8000000 +r 5430.08 +*Want "SQXBR +0 FPCR" 00000000 F8000000 +r 5440.08 +*Want "SQXBR +4 FPCR" 00000000 F8000000 +r 5450.08 +*Want "SQXBR +inf FPCR" 00000000 F8000000 +r 5460.08 +*Want "SQXBR -QNaN FPCR" 00000000 F8000000 +r 5470.08 +*Want "SQXBR +SNaN FPCR" 00800000 F8008000 +r 5480.08 +*Want "SQXBR +3 FPCR" 00080000 F8000800 +r 5490.08 +*Want "SQXBR +5 FPCR" 00080000 F8000C00 +r 54A0.08 +*Want "SQXBR +0.0625 FPCR" 00000000 F8000000 + + +# Extended BFP rounding mode test results +*Compare +r 5500.10 +*Want "SQXBR RM RNTE +3" 3FFFBB67 AE8584CA A73B2574 2D7078B8 +r 5510.10 +*Want "SQXBR RM RZ +3" 3FFFBB67 AE8584CA A73B2574 2D7078B8 +r 5520.10 +*Want "SQXBR RM RP +3" 3FFFBB67 AE8584CA A73B2574 2D7078B9 +r 5530.10 +*Want "SQXBR RM RM +3" 3FFFBB67 AE8584CA A73B2574 2D7078B8 +r 5540.10 +*Want "SQXBR RM RFS +3" 3FFFBB67 AE8584CA A73B2574 2D7078B9 +r 5550.10 +*Want "SQXBR RM RNTE +5" 40001E37 79B97F4A 7C15F39C C0605CEE +r 5560.10 +*Want "SQXBR RM RZ +5" 40001E37 79B97F4A 7C15F39C C0605CED +r 5570.10 +*Want "SQXBR RM RP +5" 40001E37 79B97F4A 7C15F39C C0605CEE +r 5580.10 +*Want "SQXBR RM RM +5" 40001E37 79B97F4A 7C15F39C C0605CED +r 5590.10 +*Want "SQXBR RM RFS +5" 40001E37 79B97F4A 7C15F39C C0605CED + + +# Extended BFP rounding mode test results - FPCR contents +*Compare +r 5A00.10 +*Want "SQXBR RM RTNE,RZ,RP,RM +3 FPCR" 00080000 00080001 00080002 00080003 +r 5A10.04 +*Want "SQXBR RM RFS +3 FPCR" 00080007 +r 5A20.10 +*Want "SQXBR RM RTNE,RZ,RP,RM +5 FPCR" 00080000 00080001 00080002 00080003 +r 5A30.04 +*Want "SQXBR RM RFS +5 FPCR" 00080007 + + +*Done + diff --git a/tests/bfp-016-add.asm b/tests/bfp-016-add.asm new file mode 100644 index 000000000..f148f9de6 --- /dev/null +++ b/tests/bfp-016-add.asm @@ -0,0 +1,1469 @@ + TITLE 'bfp-016-add.asm: Test IEEE Add' +*********************************************************************** +* +*Testcase IEEE ADD +* Test case capability includes IEEE exceptions trappable and +* otherwise. Test results, FPCR flags, the Condition code, and any +* DXC are saved for all tests. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* bfp-016-add.asm +* +* This assembly-language source file is part of the +* Hercules Decimal Floating Point Validation Package +* by Stephen R. Orso +* +* Copyright 2016 by Stephen R Orso. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* +* 3. The name of the author may not be used to endorse or promote +* products derived from this software without specific prior written +* permission. +* +* DISCLAMER: THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* HOLDER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* Tests the following three conversion instructions +* ADD (short BFP, RRE) +* ADD (long BFP, RRE) +* ADD (extended BFP, RRE) +* ADD (short BFP, RXE) +* ADD (long BFP, RXE) +* +* Test data is compiled into this program. The test script that runs +* this program can provide alternative test data through Hercules R +* commands. +* +* Test Case Order +* 1) Short BFP basic tests, including traps and NaN propagation +* 2) Short BFP finite number tests, incl. traps and scaling +* 3) Short BFP FPC-controlled rounding mode exhaustive tests +* 4) Long BFP basic tests, including traps and NaN propagation +* 5) Long BFP finite number tests, incl. traps and scaling +* 6) Long BFP FPC-controlled rounding mode exhaustive tests +* 7) Extended BFP basic tests, including traps and NaN propagation +* 8) Extended BFP finite number tests, incl. traps and scaling +* 9) Extended BFP FPC-controlled rounding mode exhaustive tests +* +* Three input test sets are provided each for short, long, and +* extended BFP inputs. Test values are the same for each precision +* for most tests. Overflow and underflow each require precision- +* dependent test values. +* +* Also tests the following floating point support instructions +* LOAD (Short) +* LOAD (Long) +* LFPC (Load Floating Point Control Register) +* SRNMB (Set BFP Rounding Mode 3-bit) +* STORE (Short) +* STORE (Long) +* STFPC (Store Floating Point Control Register) +* +*********************************************************************** + SPACE 2 + MACRO + PADCSECT &ENDLABL +.* +.* Macro to pad the CSECT to include result data areas if this test +.* program is not being assembled using asma. asma generates a core +.* image that is loaded by the loadcore command, and because the +.* core image is a binary stored in Github, it makes sense to make +.* this small effort to keep the core image small. +.* + AIF (D'&ENDLABL).GOODPAD + MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + MNOTE *,'No CSECT padding performed' + MEXIT +.* +.GOODPAD ANOP Label valid. See if we're on asma + AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + ORG &ENDLABL-1 Not ASMA. Pad CSECT + MEXIT +.* +.NOPAD ANOP + MNOTE *,'asma detected; no CSECT padding performed' + MEND +* +* Note: for compatibility with the z/CMS test rig, do not change +* or use R11, R14, or R15. Everything else is fair game. +* +BFPADD START 0 +STRTLABL EQU * +R0 EQU 0 Work register for cc extraction +R1 EQU 1 +R2 EQU 2 Holds count of test input values +R3 EQU 3 Points to next test input value(s) +R4 EQU 4 Rounding tests inner loop control +R5 EQU 5 Rounding tests outer loop control +R6 EQU 6 Rounding tests top of inner loop +R7 EQU 7 Pointer to next result value(s) +R8 EQU 8 Pointer to next FPCR result +R9 EQU 9 Rounding tests top of outer loop +R10 EQU 10 Pointer to test address list +R11 EQU 11 **Reserved for z/CMS test rig +R12 EQU 12 Holds number of test cases in set +R13 EQU 13 Mainline return address +R14 EQU 14 **Return address for z/CMS test rig +R15 EQU 15 **Base register on z/CMS or Hyperion +* +* Floating Point Register equates to keep the cross reference clean +* +FPR0 EQU 0 +FPR1 EQU 1 +FPR2 EQU 2 +FPR3 EQU 3 +FPR4 EQU 4 +FPR5 EQU 5 +FPR6 EQU 6 +FPR7 EQU 7 +FPR8 EQU 8 +FPR9 EQU 9 +FPR10 EQU 10 +FPR11 EQU 11 +FPR12 EQU 12 +FPR13 EQU 13 +FPR14 EQU 14 +FPR15 EQU 15 +* + USING *,R15 +* +* Above works on real iron (R15=0 after sysclear) +* and in z/CMS (R15 points to start of load module) +* + SPACE 2 +*********************************************************************** +* +* Low core definitions, Restart PSW, and Program Check Routine. +* +*********************************************************************** + SPACE 2 + ORG STRTLABL+X'8E' Program check interrution code +PCINTCD DS H +* +PCOLDPSW EQU STRTLABL+X'150' z/Arch Program check old PSW +* + ORG STRTLABL+X'1A0' z/Arch Restart PSW + DC X'0000000180000000',AD(START) +* + ORG STRTLABL+X'1D0' z/Arch Program check old PSW + DC X'0000000000000000',AD(PROGCHK) +* +* Program check routine. If Data Exception, continue execution at +* the instruction following the program check. Otherwise, hard wait. +* No need to collect data. All interesting DXC stuff is captured +* in the FPCR. +* + ORG STRTLABL+X'200' +PROGCHK DS 0H Program check occured... + CLI PCINTCD+1,X'07' Data Exception? + JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) + LPSWE PCOLDPSW ..yes, resume program execution +PCNOTDTA DS 0H + LTR R14,R14 Return address provided? + BNZR R14 Yes, return to z/CMS test rig. + LPSWE HARDWAIT Not data exception, enter disabled wait + EJECT +*********************************************************************** +* +* Main program. Enable Advanced Floating Point, process test cases. +* +*********************************************************************** + SPACE 2 +START DS 0H + STCTL R0,R0,CTLR0 Store CR0 to enable AFP + OI CTLR0+1,X'04' Turn on AFP bit + LCTL R0,R0,CTLR0 Reload updated CR0 +* + LA R10,SHORTNF Point to short BFP non-finite inputs + BAS R13,SBFPNF Add short BFP non-finites + LA R10,SHORTF Point to short BFP finite inputs + BAS R13,SBFPF Add short BFP finites + LA R10,RMSHORTS Point to short BFP rounding mode tests + BAS R13,SBFPRM Add short BFP for rounding tests +* + LA R10,LONGNF Point to long BFP non-finite inputs + BAS R13,LBFPNF Add long BFP non-finites + LA R10,LONGF Point to long BFP finite inputs + BAS R13,LBFPF Add long BFP finites + LA R10,RMLONGS Point to long BFP rounding mode tests + BAS R13,LBFPRM Add long BFP for rounding tests +* + LA R10,XTNDNF Point to extended BFP non-finite inputs + BAS R13,XBFPNF Add extended BFP non-finites + LA R10,XTNDF Point to ext'd BFP finite inputs + BAS R13,XBFPF Add ext'd BFP finites + LA R10,RMXTNDS Point to ext'd BFP rounding mode tests + BAS R13,XBFPRM Add ext'd BFP for rounding tests +* + LTR R14,R14 Return address provided? + BNZR R14 ..Yes, return to z/CMS test rig. + LPSWE WAITPSW All done +* + DS 0D Ensure correct alignment for psw +WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end +* +CTLR0 DS F +FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags +* +* Input values parameter list, four fullwords for each test data set +* 1) Count, +* 2) Address of inputs, +* 3) Address to place results, and +* 4) Address to place DXC/Flags/cc values. +* + ORG STRTLABL+X'300' Enable run-time replacement +SHORTNF DS 0F Input pairs for short BFP non-finite tests + DC A(SBFPNFCT) + DC A(SBFPNFIN) + DC A(SBFPNFOT) + DC A(SBFPNFFL) +* +SHORTF DS 0F Input pairs for short BFP finite tests + DC A(SBFPCT) + DC A(SBFPIN) + DC A(SBFPOUT) + DC A(SBFPFLGS) +* +RMSHORTS DS 0F Input pairs for short BFP rounding testing + DC A(SBFPRMCT) + DC A(SBFPINRM) + DC A(SBFPRMO) + DC A(SBFPRMOF) +* +LONGNF DS 0F Input pairs for long BFP non-finite testing + DC A(LBFPNFCT) + DC A(LBFPNFIN) + DC A(LBFPNFOT) + DC A(LBFPNFFL) +* +LONGF DS 0F Input pairs for long BFP finite testing + DC A(LBFPCT) + DC A(LBFPIN) + DC A(LBFPOUT) + DC A(LBFPFLGS) +* +RMLONGS DS 0F Input pairs for long BFP rounding testing + DC A(LBFPRMCT) + DC A(LBFPINRM) + DC A(LBFPRMO) + DC A(LBFPRMOF) +* +XTNDNF DS 0F Inputs for ext'd BFP non-finite testing + DC A(XBFPNFCT) + DC A(XBFPNFIN) + DC A(XBFPNFOT) + DC A(XBFPNFFL) +* +XTNDF DS 0F Inputs for ext'd BFP finite testing + DC A(XBFPCT) + DC A(XBFPIN) + DC A(XBFPOUT) + DC A(XBFPFLGS) +* +RMXTNDS DS 0F Inputs for ext'd BFP non-finite testing + DC A(XBFPRMCT) + DC A(XBFPINRM) + DC A(XBFPRMO) + DC A(XBFPRMOF) +* + EJECT +*********************************************************************** +* +* Perform Add using provided short BFP inputs. This set of tests +* checks NaN propagation, operations on values that are not finite +* numbers, and other basic tests. This set generates results that can +* be validated against Figure 19-13 on page 19-16 of SA22-7832-10. +* +* That Figure has separate rows and colums for Normal and Tiny +* operands. Although the results are effectively the same for Normal +* and Tiny in any combination, the input data includes Normal and +* Tiny values. +* +* Four results are generated for each input: one RRE with all +* exceptions non-trappable, a second RRE with all exceptions trappable, +* a third RXE with all exceptions non-trappable, a fourth RXE with all +* exceptions trappable, +* +* The sum, FPCR, and condition code are stored for each result. +* +*********************************************************************** + SPACE 2 +SBFPNF DS 0H BFP Short non-finite values tests + LM R2,R3,0(R10) Get count and address of add values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LM R4,R5,0(R10) Get count and start of addend values +* ..which are the same as the augends + BASR R6,0 Set top of inner loop +* + LE FPR8,0(,R3) Get short BFP augend + LE FPR1,0(,R5) Get short BFP addend + LFPC FPCREGNT Set exceptions non-trappable + AEBR FPR8,FPR1 Add FPR0/FPR1 RRE + STE FPR8,0(,R7) Store short BFP sum + STFPC 0(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,3(,R8) Save condition code in results table +* + LE FPR8,0(,R3) Get short BFP augend + LE FPR1,0(,R5) Get short BFP addend + LFPC FPCREGTR Set exceptions trappable + AEBR FPR8,FPR1 Add FPR0/FPR1 RRE + STE FPR8,4(,R7) Store short BFP sum + STFPC 4(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,7(,R8) Save condition code in results table +* + LE FPR8,0(,R3) Get short BFP augend + LE FPR1,0(,R5) Get short BFP addend + LFPC FPCREGNT Set exceptions non-trappable + AEB FPR8,0(,R5) Add FPR0/FPR1 RXE + STE FPR8,8(,R7) Store short BFP sum + STFPC 8(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,11(,R8) Save condition code in results table +* + LE FPR8,0(,R3) Get short BFP augend + LFPC FPCREGTR Set exceptions trappable + AEB FPR8,0(,R5) Add FPR0/FPR1 RXE + STE FPR8,12(,R7) Store short BFP sum + STFPC 12(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,15(,R8) Save condition code in results table +* + LA R5,4(,R5) Point to next addend value + LA R7,4*4(,R7) Point to next Add result area + LA R8,4*4(,R8) Point to next Add FPCR area + BCTR R4,R6 Loop through right-hand values +* + LA R3,4(,R3) Point to next input augend + BCTR R2,R12 Loop through left-hand values + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Add using provided short BFP input pairs. This set of +* tests triggers IEEE exceptions Overflow, Underflow, and Inexact and +* collects both trap and non-trap results. +* +* Four results are generated for each input: one RRE with all +* exceptions non-trappable, a second RRE with all exceptions trappable, +* a third RXE with all exceptions non-trappable, a fourth RXE with all +* exceptions trappable, +* +* The sum, FPCR, and condition code are stored for each result. +* +*********************************************************************** + SPACE 2 +SBFPF LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LFPC FPCREGNT Set exceptions non-trappable + LE FPR8,0(,R3) Get short BFP augend + LE FPR1,4(,R3) Get short BFP addend + AEBR FPR8,FPR1 Add FPR8/FPR1 RRE non-trappable + STE FPR8,0(,R7) Store short BFP sum + STFPC 0(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,3(,R8) Save condition code in results table +* + LFPC FPCREGTR Set exceptions trappable + LE FPR8,0(,R3) Reload short BFP augend +* ..addend is still in FPR1 + AEBR FPR8,FPR1 Add FPR8/FPR1 RRE trappable + STE FPR8,4(,R7) Store short BFP sum + STFPC 4(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,7(,R8) Save condition code in results table +* + LFPC FPCREGNT Set exceptions non-trappable + LE FPR8,0(,R3) Reload short BFP augend + AEB FPR8,4(,R3) Add FPR8 by addend RXE non-trappable + STE FPR8,8(,R7) Store short BFP sum + STFPC 8(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,11(,R8) Save condition code in results table +* + LFPC FPCREGTR Set exceptions trappable + LE FPR8,0(,R3) Reload short BFP augend + AEB FPR8,4(,R3) Add FPR8 by addend RXE trappable + STE FPR8,12(,R7) Store short BFP sum + STFPC 12(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,15(,R8) Save condition code in results table +* + LA R3,2*4(,R3) Point to next input value pair + LA R7,4*4(,R7) Point to next sum result set + LA R8,4*4(,R8) Point to next FPCR result set + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Add using provided short BFP input pairs. This set of +* tests exhaustively tests all rounding modes available for Add. +* The rounding mode can only be specified in the FPC. +* +* All five FPC rounding modes are tested because the preceeding tests, +* using rounding mode RNTE, do not often create results that require +* rounding. +* +* Two results are generated for each input and rounding mode: one RRE +* and one RXE. Traps are disabled for all rounding mode tests. +* +* The sum, FPCR, and condition code are stored for each test. +* +*********************************************************************** + SPACE 2 +SBFPRM LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + XR R1,R1 Zero register 1 for use in IC/STC/indexing + BASR R12,0 Set top of test case loop + + LA R5,FPCMCT Get count of FPC modes to be tested + BASR R9,0 Set top of rounding mode outer loop +* + IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 0(R1) Set FPC Rounding Mode + LE FPR8,0(,R3) Get short BFP augend + LE FPR1,4(,R3) Get short BFP addend + AEBR FPR8,FPR1 Add RRE FPR8/FPR1 non-trappable + STE FPR8,0(,R7) Store short BFP sum + STFPC 0(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,3(,R8) Save condition code in results table +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 0(R1) Set FPC Rounding Mode + LE FPR8,0(,R3) Get short BFP augend + AEB FPR8,4(,R3) Add RXE FPR8 by addend non-trappable + STE FPR8,4(,R7) Store short BFP sum + STFPC 4(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,7(,R8) Save condition code in results table +* + LA R7,2*4(,R7) Point to next sum result set + LA R8,2*4(,R8) Point to next FPCR result area +* + BCTR R5,R9 Iterate to next FPC mode for this input +* +* End of FPC modes to be tested. Advance to next test case. We will +* skip eight bytes of result area so that each set of five result +* value pairs starts at a memory address ending in zero for the +* convenience of memory dump review. +* + LA R3,2*4(,R3) Point to next input value pair + LA R7,8(,R7) Skip to start of next result set + LA R8,8(,R8) Skip to start of next FPCR result set + BCTR R2,R12 Advance to the next input pair +* + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Add using provided long BFP inputs. This set of tests +* checks NaN propagation, operations on values that are not finite +* numbers, and other basic tests. This set generates results that can +* be validated against Figure 19-13 on page 19-16 of SA22-7832-10. +* +* That Figure has separate rows and colums for Normal and Tiny +* operands. Although the results are effectively the same for Normal +* and Tiny in any combination, the input data includes Normal and +* Tiny values. +* +* Four results are generated for each input: one RRE with all +* exceptions non-trappable, a second RRE with all exceptions trappable, +* a third RXE with all exceptions non-trappable, a fourth RXE with all +* exceptions trappable, +* +* The sum, FPCR, and condition code are stored for each result. +* +*********************************************************************** + SPACE 2 +LBFPNF DS 0H BFP long non-finite values tests + LM R2,R3,0(R10) Get count and address of augend values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LM R4,R5,0(R10) Get count and start of addend values +* ..which are the same as the augends + BASR R6,0 Set top of inner loop +* + LD FPR8,0(,R3) Get long BFP augend + LD FPR1,0(,R5) Get long BFP addend + LFPC FPCREGNT Set exceptions non-trappable + ADBR FPR8,FPR1 Add FPR0/FPR1 RRE + STD FPR8,0(,R7) Store long BFP sum + STFPC 0(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,3(,R8) Save condition code in results table +* + LD FPR8,0(,R3) Get long BFP augend + LD FPR1,0(,R5) Get long BFP addend + LFPC FPCREGTR Set exceptions trappable + ADBR FPR8,FPR1 Add FPR0/FPR1 RRE + STD FPR8,8(,R7) Store long BFP remainder + STFPC 4(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,7(,R8) Save condition code in results table +* + LD FPR8,0(,R3) Get long BFP augend + LFPC FPCREGNT Set exceptions non-trappable + ADB FPR8,0(,R5) Add FPR0/FPR1 RXE + STD FPR8,16(,R7) Store long BFP sum + STFPC 8(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,11(,R8) Save condition code in results table +* + LD FPR8,0(,R3) Get long BFP augend + LFPC FPCREGTR Set exceptions trappable + ADB FPR8,0(,R5) Add FPR0/FPR1 RXE + STD FPR8,24(,R7) Store long BFP remainder + STFPC 12(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,15(,R8) Save condition code in results table +* + LA R5,8(,R5) Point to next addend value + LA R7,4*8(,R7) Point to next Add result area + LA R8,4*4(,R8) Point to next Add FPCR area + BCTR R4,R6 Loop through right-hand values +* + LA R3,8(,R3) Point to next augend value + BCTR R2,R12 Add until all cases tested + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Add using provided long BFP input pairs. This set of +* tests triggers IEEE exceptions Overflow, Underflow, and Inexact and +* collects non-trap and trap results. +* +* Four results are generated for each input: one RRE with all +* exceptions non-trappable, a second RRE with all exceptions trappable, +* a third RXE with all exceptions non-trappable, a fourth RXE with all +* exceptions trappable, +* +* The sum, FPCR, and condition code are stored for each result. +* +*********************************************************************** + SPACE 2 +LBFPF LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LFPC FPCREGNT Set exceptions non-trappable + LD FPR8,0(,R3) Get short BFP augend + LD FPR1,8(,R3) Get short BFP addend + ADBR FPR8,FPR1 Add FPR8/FPR1 RRE non-trappable + STD FPR8,0(,R7) Store short BFP sum + STFPC 0(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,3(,R8) Save condition code in results table +* + LFPC FPCREGTR Set exceptions trappable + LD FPR8,0(,R3) Reload short BFP augend +* ..addend is still in FPR1 + ADBR FPR8,FPR1 Add FPR8/FPR1 RRE trappable + STD FPR8,8(,R7) Store short BFP sum + STFPC 4(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,7(,R8) Save condition code in results table +* + LFPC FPCREGNT Set exceptions non-trappable + LD FPR8,0(,R3) Reload short BFP augend + ADB FPR8,8(,R3) Add FPR8/FPR1 RXE non-trappable + STD FPR8,16(,R7) Store short BFP sum + STFPC 8(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,11(,R8) Save condition code in results table +* + LFPC FPCREGTR Set exceptions trappable + LD FPR8,0(,R3) Reload short BFP augend + ADB FPR8,8(,R3) Add FPR8/FPR1 RXE trappable + STD FPR8,24(,R7) Store short BFP sum + STFPC 12(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,15(,R8) Save condition code in results table +* + LA R3,2*8(,R3) Point to next input value pair + LA R7,4*8(,R7) Point to next quotent result pair + LA R8,4*4(,R8) Point to next FPCR result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Add using provided long BFP input pairs. This set of +* tests exhaustively tests all rounding modes available for Add. +* The rounding mode can only be specified in the FPC. +* +* All five FPC rounding modes are tested because the preceeding tests, +* using rounding mode RNTE, do not often create results that require +* rounding. +* +* Two results are generated for each input and rounding mode: one RRE +* and one RXE. Traps are disabled for all rounding mode tests. +* +* The sum, FPCR, and condition code are stored for each result. +* +*********************************************************************** + SPACE 2 +LBFPRM LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + XR R1,R1 Zero register 1 for use in IC/STC/indexing + BASR R12,0 Set top of test case loop + + LA R5,FPCMCT Get count of FPC modes to be tested + BASR R9,0 Set top of rounding mode loop +* + IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 0(R1) Set FPC Rounding Mode + LD FPR8,0(,R3) Get long BFP augend + LD FPR1,8(,R3) Get long BFP addend + ADBR FPR8,FPR1 Add RRE FPR8/FPR1 non-trappable + STD FPR8,0(,R7) Store long BFP sum + STFPC 0(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,3(,R8) Save condition code in results table +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 0(R1) Set FPC Rounding Mode + LD FPR8,0(,R3) Reload long BFP augend + ADB FPR8,8(,R3) Add RXE FPR8 by addend non-trappable + STD FPR8,8(,R7) Store long BFP sum + STFPC 4(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,7(,R8) Save condition code in results table +* + LA R7,2*8(,R7) Point to next sum result set + LA R8,2*4(,R8) Point to next FPCR result area +* + BCTR R5,R9 Iterate to next FPC mode +* +* End of FPC modes to be tested. Advance to next test case. We will +* skip eight bytes of FPCR result area so that each set of five result +* FPCR contents pairs starts at a memory address ending in zero for the +* convenience of memory dump review. +* + LA R3,2*8(,R3) Point to next input value pair + LA R8,8(,R8) Skip to start of next FPCR result area + BCTR R2,R12 Add next input value lots of times +* + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Add using provided extended BFP inputs. This set of tests +* checks NaN propagation, operations on values that are not finite +* numbers, and other basic tests. This set generates results that can +* be validated against Figure 19-13 on page 19-16 of SA22-7832-10. +* +* That Figure has separate rows and colums for Normal and Tiny +* operands. Although the results are effectively the same for Normal +* and Tiny in any combination, the input data includes Normal and +* Tiny values. +* +* Two results are generated for each input: one RRE with all +* exceptions non-trappable, and a second RRE with all exceptions +* trappable. Extended BFP Add does not have an RXE format. +* +* The sum, FPCR, and condition code are stored for each result. +* +*********************************************************************** + SPACE 2 +XBFPNF DS 0H BFP extended non-finite values tests + LM R2,R3,0(R10) Get count and address of augend values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LM R4,R5,0(R10) Get count and start of addend values +* ..which are the same as the augends + BASR R6,0 Set top of inner loop +* + LD FPR8,0(,R3) Get extended BFP augend part 1 + LD FPR10,8(,R3) Get extended BFP augend part 2 + LD FPR1,0(,R5) Get extended BFP addend part 1 + LD FPR3,8(,R5) Get extended BFP addend part 2 + LFPC FPCREGNT Set exceptions non-trappable + AXBR FPR8,FPR1 Add FPR0/FPR1 RRE + STD FPR8,0(,R7) Store extended BFP sum part 1 + STD FPR10,8(,R7) Store extended BFP sum part 2 + STFPC 0(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,3(,R8) Save condition code in results table +* + LD FPR8,0(,R3) Get extended BFP augend part 1 + LD FPR10,8(,R3) Get extended BFP augend part 2 + LD FPR1,0(,R5) Get extended BFP addend part 1 + LD FPR3,8(,R5) Get extended BFP addend part 2 + LFPC FPCREGTR Set exceptions trappable + AXBR FPR8,FPR1 Add FPR0/FPR1 RRE + STD FPR8,16(,R7) Store extended BFP sum part 1 + STD FPR10,24(,R7) Store extended BFP sum part 2 + STFPC 4(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,7(,R8) Save condition code in results table +* + LA R5,16(,R5) Point to next addend value + LA R7,32(,R7) Point to next Add result area + LA R8,16(,R8) Point to next Add FPCR area + BCTR R4,R6 Loop through right-hand values +* + LA R3,16(,R3) Point to next augend value + BCTR R2,R12 Add until all cases tested + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Add using provided extended BFP input pairs. This set of +* tests triggers IEEE exceptions Overflow, Underflow, and Inexact and +* collects results when the exceptions do not result in a trap and when +* they do. +* +* Two results are generated for each input: one RRE with all +* exceptions non-trappable and a second RRE with all exceptions +* trappable. There is no RXE format for Add in extended precision. +* +* The sum, FPCR, and condition code are stored for each result. +* +*********************************************************************** + SPACE 2 +XBFPF LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LFPC FPCREGNT Set exceptions non-trappable + LD FPR8,0(,R3) Get extended BFP augend part 1 + LD FPR10,8(,R3) Get extended BFP augend part 2 + LD FPR1,16(,R3) Get extended BFP addend part 1 + LD FPR3,24(,R3) Get extended BFP addend part 2 + AXBR FPR8,FPR1 Add FPR8-10/FPR1-3 RRE non-trappable + STD FPR8,0(,R7) Store extended BFP sum part 1 + STD FPR10,8(,R7) Store extended BFP sum part 2 + STFPC 0(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,3(,R8) Save condition code in results table +* + LFPC FPCREGTR Set exceptions trappable + LD FPR8,0(,R3) Reload extended BFP augend part 1 + LD FPR10,8(,R3) Reload extended BFP augend part 2 +* ..addend is still in FPR1-FPR3 + AXBR FPR8,FPR1 Add FPR8-10/FPR1-3 RRE trappable + STD FPR8,16(,R7) Store extended BFP sum part 1 + STD FPR10,24(,R7) Store extended BFP sum part 2 + STFPC 4(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,7(,R8) Save condition code in results table +* + LA R3,32(,R3) Point to next input value pair + LA R7,32(,R7) Point to next quotent result pair + LA R8,16(,R8) Point to next FPCR result area + BCTR R2,R12 Convert next input value. +* + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Add using provided extended BFP input pairs. This set of +* tests exhaustively tests all rounding modes available for Add. +* The rounding mode can only be specified in the FPC. +* +* All five FPC rounding modes are tested because the preceeding tests, +* using rounding mode RNTE, do not often create results that require +* rounding. +* +* Two results are generated for each input and rounding mode: one RRE +* and one RXE. Traps are disabled for all rounding mode tests. +* +* The sum, FPCR, and condition code are stored for each result. +* +*********************************************************************** + SPACE 2 +XBFPRM LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + XR R1,R1 Zero register 1 for use in IC/STC/indexing + BASR R12,0 Set top of test case loop + + LA R5,FPCMCT Get count of FPC modes to be tested + BASR R9,0 Set top of rounding mode loop +* + IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 0(R1) Set FPC Rounding Mode + LD FPR8,0(,R3) Get extended BFP augend part 1 + LD FPR10,8(,R3) Get extended BFP augend part 2 + LD FPR1,16(,R3) Get extended BFP addend part 1 + LD FPR3,24(,R3) Get extended BFP addend part 2 + AXBR FPR8,FPR1 Add RRE FPR8/FPR1 non-trappable + STD FPR8,0(,R7) Store extended BFP sum part 1 + STD FPR10,8(,R7) Store extended BFP sum part 2 + STFPC 0(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,3(,R8) Save condition code in results table +* + LA R7,16(,R7) Point to next sum result set + LA R8,4(,R8) Point to next FPCR result area +* + BCTR R5,R9 Iterate to next FPC mode +* +* End of FPC modes to be tested. Advance to next test case. We will +* skip eight bytes of FPCR result area so that each set of five result +* FPCR contents pairs starts at a memory address ending in zero for the +* convenience of memory dump review. +* + LA R3,2*16(,R3) Point to next input value pair + LA R8,12(,R8) Skip to start of next FPCR result area + BCTR R2,R12 Add next input value lots of times +* + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Table of FPC rounding modes to test sum rounding modes. +* +* The Set BFP Rounding Mode does allow specification of the FPC +* rounding mode as an address, so we shall index into a table of +* BFP rounding modes without bothering with Execute. +* +*********************************************************************** + SPACE 2 +* +* Rounding modes that may be set in the FPCR. The FPCR controls +* rounding of the sum. +* +* These are indexed directly by the loop counter, which counts down. +* So the modes are listed in reverse order here. +* +FPCMODES DS 0C + DC AL1(7) RFS, Round for shorter precision + DC AL1(3) RM, Round to -infinity + DC AL1(2) RP, Round to +infinity + DC AL1(1) RZ, Round to zero + DC AL1(0) RNTE, Round to Nearest, ties to even +FPCMCT EQU *-FPCMODES Count of FPC Modes to be tested +* + EJECT +*********************************************************************** +* +* Short BFP test data sets for Add testing. +* +* The first test data set is used for tests of basic functionality, +* NaN propagation, and results from operations involving other than +* finite numbers. +* +* The second test data set is used for testing boundary conditions +* using two finite non-zero values. Each possible condition code +* and type of result (normal, scaled, etc) is created by members of +* this test data set. +* +* The third test data set is used for exhaustive testing of final +* results across the five rounding modes available for the Add +* instruction. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* First input test data set, to test operations using non-finite or +* zero inputs. Member values chosen to validate Figure 19-13 on page +* 19-16 of SA22-7832-10. Each value in this table is tested against +* every other value in the table. Ten entries means 100 result sets. +* +*********************************************************************** + SPACE 2 +SBFPNFIN DS 0F Inputs for short BFP non-finite tests + DC X'FF800000' -inf + DC X'C0000000' -2.0 + DC X'80010000' -Dnice + DC X'80000000' -0 + DC X'00000000' +0 + DC X'00010000' -Dnice + DC X'40000000' +2.0 + DC X'7F800000' +inf + DC X'FFCB0000' -QNaN + DC X'7F8A0000' +SNaN +SBFPNFCT EQU (*-SBFPNFIN)/4 Count of short BFP in list + SPACE 3 +*********************************************************************** +* +* Second input test data set. These are finite pairs intended to +* trigger overflow, underflow, and inexact exceptions. Each pair is +* added twice, once non-trappable and once trappable. Trappable +* overflow or underflow yields a scaled result. Trappable inexact +* will show whether the Incremented DXC code is returned. +* +* The following test cases are required: +* 1. Overflow +* 2. Underflow - normal inputs +* 3. Underflow - subnormal inputs +* 4. Normal - from subnormal inputs +* 5. Inexact - incremented +* 6. Inexact - truncated +* +*********************************************************************** + SPACE 2 +SBFPIN DS 0F Inputs for short BFP finite tests +* +* Overflow on addition +* + DC X'7F7FFFFF' +Nmax + DC X'7F7FFFFF' +Nmax +* +* Underflow from sum of normals. We will add a small normal to a +* negative smaller normal to generate a subnormal. +* + DC X'00FFFFFF' Very small normal number + DC X'80800000' Smaller normal negative +* +* Underflow from sum of subnormals. We will add two subnormals. +* + DC X'00040000' Subnormal, < +Dmax + DC X'00000F0F' Smaller subnormal +* +* Normal result from sum of subnormals. We will add two subnormals. +* The result will be greater than +Nmin +* + DC X'007FFFFF' +Dmax + DC X'00000001' +Dmin, result will be +Nmin +* +* Add a value to 1.0 such that the added digits are to the right of +* the right-most bit in the stored significand. The result will be +* inexact, and incremented will be determined by the value of the +* bits in the addend. +* + DC X'3F800000' Augend +1, aka 1.0b0 + DC X'33F80000' Addend 1.1111b-24 +* ..Above addend is 1.154839992523193359375E-7 +* ..nearest is away from zero, incremented. +* + DC X'3F800000' Augend +1, aka 1.0b0 + DC X'33780000' Addend 1.1111b-25 +* ..Above addend is 5.774199962615966796875E-8 +* ..nearest is toward zero, truncated +* +SBFPCT EQU (*-SBFPIN)/4/2 Count of short BFP in list + SPACE 3 +*********************************************************************** +* +* Third input test data set. These are finite pairs intended to +* test all combinations of rounding mode for the sum and the +* remainder. Values are chosen to create a requirement to round +* to the target precision after the computation and to generate +* varying results depending on the rounding mode in the FPCR. +* +* The result set will have cases that represent each of the following +* +* 1. Positive, nearest magnitude is toward zero. +* 2. Negative, nearest magnitude is toward zero. +* 3. Positive, nearest magnitude is away from zero. +* 4. Negative, nearest magnitude is away from zero. +* 5. Positive, tie, nearest even has greater magnitude +* 6. Negative, tie, nearest even has greater magnitude +* 7. Positive, tie, nearest even has lower magnitude +* 8. Negative, tie, nearest even has lower magnitude +* +* Round For Shorter precision correctness can be determined from the +* above test cases. +* +*********************************************************************** + SPACE 2 +SBFPINRM DS 0F Inputs for short BFP rounding testing +* +* Add a value to 1.0 such that the added digits are to the right of +* the right-most bit in the stored significand. The result will be +* inexact, and incremented will be determined by the value of the +* bits in the addend. +* + DC X'3F800000' Augend +1, aka +1.0b0 + DC X'337E0000' Addend +1.111111b-25 + DC X'BF800000' Augend -1, aka -1.0b0 + DC X'B37E0000' Addend -1.111111b-25 +* ..Above addend is 5.91389834880828857421875E-8 +* ..nearest is toward zero, truncated +* + DC X'3F800000' Augend +1, aka 1.0b0 + DC X'33FF0000' Addend +1.1111111b-24 + DC X'BF800000' Augend -1, aka -1.0b0 + DC X'B3FF0000' Addend -1.1111111b-24 +* ..Above addend is 1.187436282634735107421875E-7 +* ..nearest is away from zero, incremented. +* + DC X'3F800000' Augend +1, aka +1.0b0 + DC X'33800000' Addend +1.0b-24 + DC X'BF800000' Augend -1, aka -1.0b0 + DC X'B3800000' Addend -1.0b-24 +* ..Above addend is 5.9604644775390625E-8 +* ..nearest is a tie, nearest even has lower magnitude +* + DC X'3F800000' Augend +1, aka +1.0b0 + DC X'34400000' Addend +1.1b-23 + DC X'BF800000' Augend -1, aka -1.0b0 + DC X'B4400000' Addend -1.1b-23 +* ..Above addend is 1.78813934326171875E-7 +* ..nearest is a tie, nearest even has greater magnitude +SBFPRMCT EQU (*-SBFPINRM)/4/2 Count of short BFP rounding tests + EJECT +*********************************************************************** +* +* Long BFP test data sets for Add testing. +* +* The first test data set is used for tests of basic functionality, +* NaN propagation, and results from operations involving other than +* finite numbers. +* +* The second test data set is used for testing boundary conditions +* using two finite non-zero values. Each possible condition code +* and type of result (normal, scaled, etc) is created by members of +* this test data set. +* +* The third test data set is used for exhaustive testing of final +* results across the five rounding modes available for the Add +* instruction. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* First input test data set, to test operations using non-finite or +* zero inputs. Member values chosen to validate Figure 19-13 on page +* 19-16 of SA22-7832-10. Each value in this table is tested against +* every other value in the table. Ten entries means 100 result sets. +* +*********************************************************************** + SPACE 2 +LBFPNFIN DS 0F Inputs for long BFP testing + DC X'FFF0000000000000' -inf + DC X'C000000000000000' -2.0 + DC X'8001000000000000' -Dnice + DC X'8000000000000000' -0 + DC X'0000000000000000' +0 + DC X'0001000000000000' +Dnice + DC X'4000000000000000' +2.0 + DC X'7FF0000000000000' +inf + DC X'FFF8B00000000000' -QNaN + DC X'7FF0A00000000000' +SNaN +LBFPNFCT EQU (*-LBFPNFIN)/8 Count of long BFP in list + SPACE 3 +*********************************************************************** +* +* Second input test data set. These are finite pairs intended to +* trigger overflow, underflow, and inexact exceptions. Each pair is +* added twice, once non-trappable and once trappable. Trappable +* overflow or underflow yields a scaled result. Trappable inexact +* will show whether the Incremented DXC code is returned. +* +* The following test cases are required: +* 1. Overflow +* 2. Underflow - normal inputs +* 3. Underflow - subnormal inputs +* 4. Normal - from subnormal inputs +* 5. Inexact - incremented +* 6. Inexact - truncated +* +*********************************************************************** + SPACE 2 +LBFPIN DS 0D Inputs for long BFP finite tests +* +* Overflow on addition +* + DC X'7FFFFFFFFFFFFFFF' +Nmax + DC X'7FFFFFFFFFFFFFFF' +Nmax +* +* Underflow from sum of normals. We will add a small normal to a +* negative smaller normal to generate a subnormal. +* + DC X'001FFFFFFFFFFFFF' Very small normal number + DC X'8010000000000000' Smaller normal negative +* +* Underflow from sum of subnormals. We will add two subnormals. +* + DC X'0008000000000000' Subnormal, < +Dmax + DC X'0000F0F000000000' Smaller subnormal +* +* Normal result from sum of subnormals. We will add two subnormals. +* The result will be greater than +Nmin +* + DC X'000FFFFFFFFFFFFF' +Dmax + DC X'0000000000000001' +Dmin, result will be +Nmin +* +* Add a value to 1.0 such that the added digits are to the right of +* the right-most bit in the stored significand. The result will be +* inexact, and incremented will be determined by the value of the +* bits in the addend. +* + DC X'3FF0000000000000' Augend +1, aka 1.0b0 + DC X'3CAF000000000000' Addend 1.1111b-53 +* ..Above addend is 2.15105711021124079707078635692596435546875E-16 +* ..nearest is away from zero, incremented. +* + DC X'3FF0000000000000' Augend +1, aka 1.0b0 + DC X'3C9F000000000000' Addend 1.1111b-54 +* ..Above addend is 1.075528555105620398535393178462982177734375E-16 +* ..nearest is toward zero, truncated. +* +LBFPCT EQU (*-LBFPIN)/8/2 Count of long BFP in list + SPACE 3 +*********************************************************************** +* +* Third input test data set. These are finite pairs intended to +* test all combinations of rounding mode for the sum and the +* remainder. Values are chosen to create a requirement to round +* to the target precision after the computation and to generate +* varying results depending on the rounding mode in the FPCR. +* +* The result set will have cases that represent each of the following +* +* 1. Positive, nearest magnitude is toward zero. +* 2. Negative, nearest magnitude is toward zero. +* 3. Positive, nearest magnitude is away from zero. +* 4. Negative, nearest magnitude is away from zero. +* 5. Positive, tie, nearest even has greater magnitude +* 6. Negative, tie, nearest even has greater magnitude +* 7. Positive, tie, nearest even has lower magnitude +* 8. Negative, tie, nearest even has lower magnitude +* +* Round For Shorter precision correctness can be determined from the +* above test cases. +* +*********************************************************************** + SPACE 2 +LBFPINRM DS 0F +* +* Add a value to 1.0 such that the added digits are to the right of +* the right-most bit in the stored significand. The result will be +* inexact, and incremented will be determined by the value of the +* bits in the addend. +* + DC X'3FF0000000000000' Augend +1, aka +1.0b0 + DC X'3C9FC00000000000' Addend +1.111111b-54 + DC X'BFF0000000000000' Augend -1, aka -1.0b0 + DC X'BC9FC00000000000' Addend -1.111111b-54 +* ..Above addend is 1.10154940724527250495157204568386077880859375E-16 +* ..nearest is toward zero, truncated. +* + DC X'3FF0000000000000' Augend +1, aka +1.0b0 + DC X'3CAFE00000000000' Addend +1.1111111b-53 + DC X'BFF0000000000000' Augend -1, aka -1.0b0 + DC X'BCAFE00000000000' Addend -1.1111111b-53 +* ..Above addend is 2.21177243187042904537520371377468109130859375E-16 +* ..nearest is away from zero, incremented. +* + DC X'3FF0000000000000' Augend +1, aka +1.0b0 + DC X'3CA0000000000000' Addend +1.0b-53 + DC X'BFF0000000000000' Augend -1, aka -1.0b0 + DC X'BCA0000000000000' Addend -1.0b-53 +* ..Above addend is 1.1102230246251565404236316680908203125E-16 +* ..nearest is a tie, nearest even has lower magnitude +* + DC X'3FF0000000000000' Augend +1, aka +1.0b0 + DC X'3CB8000000000000' Addend +1.1b-52 + DC X'BFF0000000000000' Augend -1, aka -1.0b0 + DC X'BCB8000000000000' Addend -1.1b-52 +* ..Above addend is 3.3306690738754696212708950042724609375E-16 +* ..nearest is a tie, nearest even has greater magnitude +* +* +LBFPRMCT EQU (*-LBFPINRM)/8/2 Count of long BFP rounding tests + EJECT +*********************************************************************** +* +* Extended BFP test data sets for Add testing. +* +* The first test data set is used for tests of basic functionality, +* NaN propagation, and results from operations involving other than +* finite numbers. +* +* The second test data set is used for testing boundary conditions +* using two finite non-zero values. Each possible condition code +* and type of result (normal, scaled, etc) is created by members of +* this test data set. +* +* The third test data set is used for exhaustive testing of final +* results across the five rounding modes available for the Add +* instruction. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* First input test data set, to test operations using non-finite or +* zero inputs. Member values chosen to validate Figure 19-13 on page +* 19-16 of SA22-7832-10. Each value in this table is tested against +* every other value in the table. Ten entries means 100 result sets. +* +*********************************************************************** + SPACE 2 +XBFPNFIN DS 0F Inputs for extended BFP testing + DC X'FFFF0000000000000000000000000000' -inf + DC X'C0000000000000000000000000000000' -2.0 + DC X'80001000000000000000000000000000' -Dnice + DC X'80000000000000000000000000000000' -0 + DC X'00000000000000000000000000000000' +0 + DC X'00001000000000000000000000000000' +Dnice + DC X'40000000000000000000000000000000' +2.0 + DC X'7FFF0000000000000000000000000000' +inf + DC X'FFFF8B00000000000000000000000000' -QNaN + DC X'7FFF0A00000000000000000000000000' +SNaN +XBFPNFCT EQU (*-XBFPNFIN)/16 Count of extended BFP in list + SPACE 3 +*********************************************************************** +* +* Second input test data set. These are finite pairs intended to +* trigger overflow, underflow, and inexact exceptions. Each pair is +* added twice, once non-trappable and once trappable. Trappable +* overflow or underflow yields a scaled result. Trappable inexact +* will show whether the Incremented DXC code is returned. +* +* The following test cases are required: +* The following test cases are required: +* 1. Overflow +* 2. Underflow - normal inputs +* 3. Underflow - subnormal inputs +* 4. Normal - from subnormal inputs +* 5. Inexact - incremented +* 6. Inexact - truncated +* +*********************************************************************** + SPACE 2 +XBFPIN DS 0F Inputs for extended BFP finite tests +* +* Overflow on addition +* + DC X'7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF' +Nmax + DC X'7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF' +Nmax +* +* Underflow from sum of normals. We will add a small normal to a +* negative smaller normal to generate a subnormal. +* + DC X'0001FFFFFFFFFFFFFFFFFFFFFFFFFFFF' Very small normal + DC X'80010000000000000000000000000000' Smaller normal +* +* Underflow from sum of subnormals. We will add two subnormals. +* + DC X'00008000000000000000000000000000' Subnormal, < +Dmax + DC X'00000F0F000000000000000000000000' Smaller subnormal +* +* Normal result from sum of subnormals. We will add two subnormals. +* The result will be greater than +Nmin +* + DC X'0000FFFFFFFFFFFFFFFFFFFFFFFFFFFF' +Dmax + DC X'00000000000000000000000000000001' +Dmin +* ...result will be +Nmin +* +* Add a value to 1.0 such that the added digits are to the right of +* the right-most bit in the stored significand. The result will be +* inexact, and incremented will be determined by the value of the +* bits in the addend. +* + DC X'3FFF0000000000000000000000000000' +1, aka 1.0b0 + DC X'3F8EF000000000000000000000000000' 1.1111b-113 +* ..Above addend is 1.865744633625134732647978631879148339833785... +* ...97170865731413869070820510387420654296875E-34 +* ..nearest is away from zero, incremented. +* + DC X'3FFF0000000000000000000000000000' +1, aka 1.0b0 + DC X'3F8DF000000000000000000000000000' 1.1111b-114 +* ..Above addend is 9.328723168125673663239893159395741699168929... +* ...85854328657069345354102551937103271484375E-35 +* ..nearest is toward zero, truncated +* +XBFPCT EQU (*-XBFPIN)/16/2 Count of extended BFP in list + SPACE 3 +*********************************************************************** +* +* Third input test data set. These are finite pairs intended to +* test all combinations of rounding mode for the sum and the +* remainder. Values are chosen to create a requirement to round +* to the target precision after the computation and to generate +* varying results depending on the rounding mode in the FPCR. +* +* The result set will have cases that represent each of the following +* +* 1. Positive, nearest magnitude is toward zero. +* 2. Negative, nearest magnitude is toward zero. +* 3. Positive, nearest magnitude is away from zero. +* 4. Negative, nearest magnitude is away from zero. +* 5. Positive, tie, nearest even has greater magnitude +* 6. Negative, tie, nearest even has greater magnitude +* 7. Positive, tie, nearest even has lower magnitude +* 8. Negative, tie, nearest even has lower magnitude +* +* Round For Shorter precision correctness can be determined from the +* above test cases. +* +*********************************************************************** + SPACE 2 +XBFPINRM DS 0D +* +* Add a value to 1.0 such that the added digits are to the right of +* the right-most bit in the stored significand. The result will be +* inexact, and incremented will be determined by the value of the +* bits in the addend. +* + DC X'3FFF0000000000000000000000000000' +1, aka +1.0b0 + DC X'3F8DFC00000000000000000000000000' +1.111111b-114 + DC X'BFFF0000000000000000000000000000' -1, aka -1.0b0 + DC X'BF8DFC00000000000000000000000000' -1.111111b-114 +* ..Above addend is 9.554418083483552864769890574542412869310113... +* ...6454435273748231338686309754848480224609375E-35 +* ..nearest is toward zero +* + DC X'3FFF0000000000000000000000000000' +1, aka +1.0b0 + DC X'3F8EFE00000000000000000000000000' +1.1111111b-113 + DC X'BFFF0000000000000000000000000000' -1, aka -1.0b0 + DC X'BF8EFE00000000000000000000000000' -1.1111111b-113 +* ..Above addend is 1.918406780541973213004978028746704946200062... +* ...18865204683510228278464637696743011474609375E-34 +* ..nearest is away from zero +* + DC X'3FFF0000000000000000000000000000' +1, aka +1.0b0 + DC X'3F8E0000000000000000000000000000' +1.0000b-113 + DC X'BFFF0000000000000000000000000000' -1, aka -1.0b0 + DC X'BF8E0000000000000000000000000000' -1.0000b-113 +* ..Above addend is 9.629649721936179265279889712924636592690508... +* ...241076940976199693977832794189453125E-35 +* ..nearest is a tie, nearest even has lower magnitude +* + DC X'3FFF0000000000000000000000000000' +1, aka +1.0b0 + DC X'3F8F8000000000000000000000000000' +1.1b-112 + DC X'BFFF0000000000000000000000000000' -1, aka -1.0b0 + DC X'BF8F8000000000000000000000000000' -1.1b-112 +* ..Above addend is 9.629649721936179265279889712924636592690508... +* ...241076940976199693977832794189453125E-35 +* ..nearest is a tie, nearest even has greater magnitude +* +XBFPRMCT EQU (*-XBFPINRM)/16/2 Count of long BFP rounding tests + EJECT +* +* Locations for results +* +SBFPNFOT EQU STRTLABL+X'1000' Integer short non-finite BFP results +* ..room for 110 tests, 100 used +SBFPNFFL EQU STRTLABL+X'1700' FPCR flags and DXC from short BFP +* ..room for 110 tests, 100 used +* +SBFPOUT EQU STRTLABL+X'1E00' Integer short BFP finite results +* ..room for 16 tests, 6 used +SBFPFLGS EQU STRTLABL+X'1F00' FPCR flags and DXC from short BFP +* ..room for 16 tests, 6 used +* +SBFPRMO EQU STRTLABL+X'2000' Short BFP rounding mode test results +* ..Room for 16, 8 used. +SBFPRMOF EQU STRTLABL+X'2300' Short BFP rounding mode FPCR results +* ..Room for 16, 8 used. +* ..next location starts at X'2500' +* +LBFPNFOT EQU STRTLABL+X'4000' Integer long non-finite BFP results +* ..room for 100 tests, 100 used +LBFPNFFL EQU STRTLABL+X'4D00' FPCR flags and DXC from long BFP +* ..room for 100 tests, 100 used +* +LBFPOUT EQU STRTLABL+X'5400' Integer long BFP finite results +* ..room for 16 tests, 6 used +LBFPFLGS EQU STRTLABL+X'5600' FPCR flags and DXC from long BFP +* ..room for 16 tests, 6 used +* +LBFPRMO EQU STRTLABL+X'5700' Long BFP rounding mode test results +* ..Room for 16, 8 used. +LBFPRMOF EQU STRTLABL+X'5C00' Long BFP rounding mode FPCR results +* ..Room for 16, 8 used. +* ..next location starts at X'5E00' +* +XBFPNFOT EQU STRTLABL+X'8000' Integer ext'd non-finite BFP results +* ..room for 100 tests, 100 used +XBFPNFFL EQU STRTLABL+X'8D00' FPCR flags and DXC from ext'd BFP +* ..room for 100 tests, 100 used +* +XBFPOUT EQU STRTLABL+X'9400' Extended BFP finite results +* ..room for 16 tests, 6 used +XBFPFLGS EQU STRTLABL+X'9600' FPCR flags and DXC from ext'd BFP +* ..room for 16 tests, 6 used +* +XBFPRMO EQU STRTLABL+X'9700' Ext'd BFP rounding mode test results +* ..Room for 16, 8 used. +XBFPRMOF EQU STRTLABL+X'9C00' Ext'd BFP rounding mode FPCR results +* ..Room for 16, 8 used. +* ..next location starts at X'9E00' +* +ENDLABL EQU STRTLABL+X'9E00' + PADCSECT ENDLABL + END diff --git a/tests/bfp-016-add.core b/tests/bfp-016-add.core new file mode 100644 index 000000000..a01b8f99c Binary files /dev/null and b/tests/bfp-016-add.core differ diff --git a/tests/bfp-016-add.list b/tests/bfp-016-add.list new file mode 100644 index 000000000..31cc912cb --- /dev/null +++ b/tests/bfp-016-add.list @@ -0,0 +1,1779 @@ +ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 1 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 2 *********************************************************************** + 3 * + 4 *Testcase IEEE ADD + 5 * Test case capability includes IEEE exceptions trappable and + 6 * otherwise. Test results, FPCR flags, the Condition code, and any + 7 * DXC are saved for all tests. + 8 * + 9 *********************************************************************** + + + 11 *********************************************************************** + 12 * + 13 * Tests the following three conversion instructions + 14 * ADD (short BFP, RRE) + 15 * ADD (long BFP, RRE) + 16 * ADD (extended BFP, RRE) + 17 * ADD (short BFP, RXE) + 18 * ADD (long BFP, RXE) + 19 * + 20 * Test data is compiled into this program. The test script that runs + 21 * this program can provide alternative test data through Hercules R + 22 * commands. + 23 * + 24 * Test Case Order + 25 * 1) Short BFP basic tests, including traps and NaN propagation + 26 * 2) Short BFP finite number tests, incl. traps and scaling + 27 * 3) Short BFP FPC-controlled rounding mode exhaustive tests + 28 * 4) Long BFP basic tests, including traps and NaN propagation + 29 * 5) Long BFP finite number tests, incl. traps and scaling + 30 * 6) Long BFP FPC-controlled rounding mode exhaustive tests + 31 * 7) Extended BFP basic tests, including traps and NaN propagation + 32 * 8) Extended BFP finite number tests, incl. traps and scaling + 33 * 9) Extended BFP FPC-controlled rounding mode exhaustive tests + 34 * + 35 * Three input test sets are provided each for short, long, and + 36 * extended BFP inputs. Test values are the same for each precision + 37 * for most tests. Overflow and underflow each require precision- + 38 * dependent test values. + 39 * + 40 * Also tests the following floating point support instructions + 41 * LOAD (Short) + 42 * LOAD (Long) + 43 * LFPC (Load Floating Point Control Register) + 44 * SRNMB (Set BFP Rounding Mode 3-bit) + 45 * STORE (Short) + 46 * STORE (Long) + 47 * STFPC (Store Floating Point Control Register) + 48 * + 49 *********************************************************************** + + + 51 MACRO + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 2 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 52 PADCSECT &ENDLABL + 53 .* + 54 .* Macro to pad the CSECT to include result data areas if this test + 55 .* program is not being assembled using asma. asma generates a core + 56 .* image that is loaded by the loadcore command, and because the + 57 .* core image is a binary stored in Github, it makes sense to make + 58 .* this small effort to keep the core image small. + 59 .* + 60 AIF (D'&ENDLABL).GOODPAD + 61 MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + 62 MNOTE *,'No CSECT padding performed' + 63 MEXIT + 64 .* + 65 .GOODPAD ANOP Label valid. See if we're on asma + 66 AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + 67 ORG &ENDLABL-1 Not ASMA. Pad CSECT + 68 MEXIT + 69 .* + 70 .NOPAD ANOP + 71 MNOTE *,'asma detected; no CSECT padding performed' + 72 MEND + 73 * + 74 * Note: for compatibility with the z/CMS test rig, do not change + 75 * or use R11, R14, or R15. Everything else is fair game. + 76 * + 0000000000000000 0000000000000CDF 77 BFPADD START 0 + 0000000000000000 0000000000000001 78 STRTLABL EQU * + 0000000000000000 0000000000000001 79 R0 EQU 0 Work register for cc extraction + 0000000000000001 0000000000000001 80 R1 EQU 1 + 0000000000000002 0000000000000001 81 R2 EQU 2 Holds count of test input values + 0000000000000003 0000000000000001 82 R3 EQU 3 Points to next test input value(s) + 0000000000000004 0000000000000001 83 R4 EQU 4 Rounding tests inner loop control + 0000000000000005 0000000000000001 84 R5 EQU 5 Rounding tests outer loop control + 0000000000000006 0000000000000001 85 R6 EQU 6 Rounding tests top of inner loop + 0000000000000007 0000000000000001 86 R7 EQU 7 Pointer to next result value(s) + 0000000000000008 0000000000000001 87 R8 EQU 8 Pointer to next FPCR result + 0000000000000009 0000000000000001 88 R9 EQU 9 Rounding tests top of outer loop + 000000000000000A 0000000000000001 89 R10 EQU 10 Pointer to test address list + 000000000000000B 0000000000000001 90 R11 EQU 11 **Reserved for z/CMS test rig + 000000000000000C 0000000000000001 91 R12 EQU 12 Holds number of test cases in set + 000000000000000D 0000000000000001 92 R13 EQU 13 Mainline return address + 000000000000000E 0000000000000001 93 R14 EQU 14 **Return address for z/CMS test rig + 000000000000000F 0000000000000001 94 R15 EQU 15 **Base register on z/CMS or Hyperion + 95 * + 96 * Floating Point Register equates to keep the cross reference clean + 97 * + 0000000000000000 0000000000000001 98 FPR0 EQU 0 + 0000000000000001 0000000000000001 99 FPR1 EQU 1 + 0000000000000002 0000000000000001 100 FPR2 EQU 2 + 0000000000000003 0000000000000001 101 FPR3 EQU 3 + 0000000000000004 0000000000000001 102 FPR4 EQU 4 + 0000000000000005 0000000000000001 103 FPR5 EQU 5 + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 3 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 0000000000000006 0000000000000001 104 FPR6 EQU 6 + 0000000000000007 0000000000000001 105 FPR7 EQU 7 + 0000000000000008 0000000000000001 106 FPR8 EQU 8 + 0000000000000009 0000000000000001 107 FPR9 EQU 9 + 000000000000000A 0000000000000001 108 FPR10 EQU 10 + 000000000000000B 0000000000000001 109 FPR11 EQU 11 + 000000000000000C 0000000000000001 110 FPR12 EQU 12 + 000000000000000D 0000000000000001 111 FPR13 EQU 13 + 000000000000000E 0000000000000001 112 FPR14 EQU 14 + 000000000000000F 0000000000000001 113 FPR15 EQU 15 + 114 * +0000000000000000 0000000000000000 115 USING *,R15 + 116 * + 117 * Above works on real iron (R15=0 after sysclear) + 118 * and in z/CMS (R15 points to start of load module) + 119 * + + + 121 *********************************************************************** + 122 * + 123 * Low core definitions, Restart PSW, and Program Check Routine. + 124 * + 125 *********************************************************************** + + +0000000000000000 0000000000000000 000000000000008E 127 ORG STRTLABL+X'8E' Program check interrution code +000000000000008E 0000 128 PCINTCD DS H + 129 * + 0000000000000150 0000000000000001 130 PCOLDPSW EQU STRTLABL+X'150' z/Arch Program check old PSW + 131 * +0000000000000090 0000000000000090 00000000000001A0 132 ORG STRTLABL+X'1A0' z/Arch Restart PSW +00000000000001A0 00000001 80000000 133 DC X'0000000180000000',AD(START) + 134 * +00000000000001B0 00000000000001B0 00000000000001D0 135 ORG STRTLABL+X'1D0' z/Arch Program check old PSW +00000000000001D0 00000000 00000000 136 DC X'0000000000000000',AD(PROGCHK) + 137 * + 138 * Program check routine. If Data Exception, continue execution at + 139 * the instruction following the program check. Otherwise, hard wait. + 140 * No need to collect data. All interesting DXC stuff is captured + 141 * in the FPCR. + 142 * +00000000000001E0 00000000000001E0 0000000000000200 143 ORG STRTLABL+X'200' +0000000000000200 144 PROGCHK DS 0H Program check occured... +0000000000000200 9507 F08F 000000000000008F 145 CLI PCINTCD+1,X'07' Data Exception? +0000000000000204 A774 0004 000000000000020C 146 JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) +0000000000000208 B2B2 F150 0000000000000150 147 LPSWE PCOLDPSW ..yes, resume program execution +000000000000020C 148 PCNOTDTA DS 0H +000000000000020C 12EE 149 LTR R14,R14 Return address provided? +000000000000020E 077E 150 BNZR R14 Yes, return to z/CMS test rig. +0000000000000210 B2B2 F280 0000000000000280 151 LPSWE HARDWAIT Not data exception, enter disabled wait + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 4 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 153 *********************************************************************** + 154 * + 155 * Main program. Enable Advanced Floating Point, process test cases. + 156 * + 157 *********************************************************************** + + +0000000000000214 159 START DS 0H +0000000000000214 B600 F290 0000000000000290 160 STCTL R0,R0,CTLR0 Store CR0 to enable AFP +0000000000000218 9604 F291 0000000000000291 161 OI CTLR0+1,X'04' Turn on AFP bit +000000000000021C B700 F290 0000000000000290 162 LCTL R0,R0,CTLR0 Reload updated CR0 + 163 * +0000000000000220 41A0 F300 0000000000000300 164 LA R10,SHORTNF Point to short BFP non-finite inputs +0000000000000224 4DD0 F390 0000000000000390 165 BAS R13,SBFPNF Add short BFP non-finites +0000000000000228 41A0 F310 0000000000000310 166 LA R10,SHORTF Point to short BFP finite inputs +000000000000022C 4DD0 F44A 000000000000044A 167 BAS R13,SBFPF Add short BFP finites +0000000000000230 41A0 F320 0000000000000320 168 LA R10,RMSHORTS Point to short BFP rounding mode tests +0000000000000234 4DD0 F4F0 00000000000004F0 169 BAS R13,SBFPRM Add short BFP for rounding tests + 170 * +0000000000000238 41A0 F330 0000000000000330 171 LA R10,LONGNF Point to long BFP non-finite inputs +000000000000023C 4DD0 F572 0000000000000572 172 BAS R13,LBFPNF Add long BFP non-finites +0000000000000240 41A0 F340 0000000000000340 173 LA R10,LONGF Point to long BFP finite inputs +0000000000000244 4DD0 F628 0000000000000628 174 BAS R13,LBFPF Add long BFP finites +0000000000000248 41A0 F350 0000000000000350 175 LA R10,RMLONGS Point to long BFP rounding mode tests +000000000000024C 4DD0 F6CE 00000000000006CE 176 BAS R13,LBFPRM Add long BFP for rounding tests + 177 * +0000000000000250 41A0 F360 0000000000000360 178 LA R10,XTNDNF Point to extended BFP non-finite inputs +0000000000000254 4DD0 F74C 000000000000074C 179 BAS R13,XBFPNF Add extended BFP non-finites +0000000000000258 41A0 F370 0000000000000370 180 LA R10,XTNDF Point to ext'd BFP finite inputs +000000000000025C 4DD0 F7D6 00000000000007D6 181 BAS R13,XBFPF Add ext'd BFP finites +0000000000000260 41A0 F380 0000000000000380 182 LA R10,RMXTNDS Point to ext'd BFP rounding mode tests +0000000000000264 4DD0 F84C 000000000000084C 183 BAS R13,XBFPRM Add ext'd BFP for rounding tests + 184 * +0000000000000268 12EE 185 LTR R14,R14 Return address provided? +000000000000026A 077E 186 BNZR R14 ..Yes, return to z/CMS test rig. +000000000000026C B2B2 F270 0000000000000270 187 LPSWE WAITPSW All done + 188 * +0000000000000270 189 DS 0D Ensure correct alignment for psw +0000000000000270 00020000 00000000 190 WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +0000000000000280 00020000 00000000 191 HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end + 192 * +0000000000000290 00000000 193 CTLR0 DS F +0000000000000294 00000000 194 FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +0000000000000298 F8000000 195 FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags + 196 * + 197 * Input values parameter list, four fullwords for each test data set + 198 * 1) Count, + 199 * 2) Address of inputs, + 200 * 3) Address to place results, and + 201 * 4) Address to place DXC/Flags/cc values. + 202 * +000000000000029C 000000000000029C 0000000000000300 203 ORG STRTLABL+X'300' Enable run-time replacement + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 5 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000300 204 SHORTNF DS 0F Input pairs for short BFP non-finite tests +0000000000000300 0000000A 205 DC A(SBFPNFCT) +0000000000000304 000008B8 206 DC A(SBFPNFIN) +0000000000000308 00001000 207 DC A(SBFPNFOT) +000000000000030C 00001700 208 DC A(SBFPNFFL) + 209 * +0000000000000310 210 SHORTF DS 0F Input pairs for short BFP finite tests +0000000000000310 00000006 211 DC A(SBFPCT) +0000000000000314 000008E0 212 DC A(SBFPIN) +0000000000000318 00001E00 213 DC A(SBFPOUT) +000000000000031C 00001F00 214 DC A(SBFPFLGS) + 215 * +0000000000000320 216 RMSHORTS DS 0F Input pairs for short BFP rounding testing +0000000000000320 00000008 217 DC A(SBFPRMCT) +0000000000000324 00000910 218 DC A(SBFPINRM) +0000000000000328 00002000 219 DC A(SBFPRMO) +000000000000032C 00002300 220 DC A(SBFPRMOF) + 221 * +0000000000000330 222 LONGNF DS 0F Input pairs for long BFP non-finite testing +0000000000000330 0000000A 223 DC A(LBFPNFCT) +0000000000000334 00000950 224 DC A(LBFPNFIN) +0000000000000338 00004000 225 DC A(LBFPNFOT) +000000000000033C 00004D00 226 DC A(LBFPNFFL) + 227 * +0000000000000340 228 LONGF DS 0F Input pairs for long BFP finite testing +0000000000000340 00000006 229 DC A(LBFPCT) +0000000000000344 000009A0 230 DC A(LBFPIN) +0000000000000348 00005400 231 DC A(LBFPOUT) +000000000000034C 00005600 232 DC A(LBFPFLGS) + 233 * +0000000000000350 234 RMLONGS DS 0F Input pairs for long BFP rounding testing +0000000000000350 00000008 235 DC A(LBFPRMCT) +0000000000000354 00000A00 236 DC A(LBFPINRM) +0000000000000358 00005700 237 DC A(LBFPRMO) +000000000000035C 00005C00 238 DC A(LBFPRMOF) + 239 * +0000000000000360 240 XTNDNF DS 0F Inputs for ext'd BFP non-finite testing +0000000000000360 0000000A 241 DC A(XBFPNFCT) +0000000000000364 00000A80 242 DC A(XBFPNFIN) +0000000000000368 00008000 243 DC A(XBFPNFOT) +000000000000036C 00008D00 244 DC A(XBFPNFFL) + 245 * +0000000000000370 246 XTNDF DS 0F Inputs for ext'd BFP finite testing +0000000000000370 00000006 247 DC A(XBFPCT) +0000000000000374 00000B20 248 DC A(XBFPIN) +0000000000000378 00009400 249 DC A(XBFPOUT) +000000000000037C 00009600 250 DC A(XBFPFLGS) + 251 * +0000000000000380 252 RMXTNDS DS 0F Inputs for ext'd BFP non-finite testing +0000000000000380 00000008 253 DC A(XBFPRMCT) +0000000000000384 00000BE0 254 DC A(XBFPINRM) +0000000000000388 00009700 255 DC A(XBFPRMO) + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 6 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +000000000000038C 00009C00 256 DC A(XBFPRMOF) + 257 * + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 7 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 259 *********************************************************************** + 260 * + 261 * Perform Add using provided short BFP inputs. This set of tests + 262 * checks NaN propagation, operations on values that are not finite + 263 * numbers, and other basic tests. This set generates results that can + 264 * be validated against Figure 19-13 on page 19-16 of SA22-7832-10. + 265 * + 266 * That Figure has separate rows and colums for Normal and Tiny + 267 * operands. Although the results are effectively the same for Normal + 268 * and Tiny in any combination, the input data includes Normal and + 269 * Tiny values. + 270 * + 271 * Four results are generated for each input: one RRE with all + 272 * exceptions non-trappable, a second RRE with all exceptions trappable, + 273 * a third RXE with all exceptions non-trappable, a fourth RXE with all + 274 * exceptions trappable, + 275 * + 276 * The sum, FPCR, and condition code are stored for each result. + 277 * + 278 *********************************************************************** + + +0000000000000390 280 SBFPNF DS 0H BFP Short non-finite values tests +0000000000000390 9823 A000 0000000000000000 281 LM R2,R3,0(R10) Get count and address of add values +0000000000000394 9878 A008 0000000000000008 282 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000398 1222 283 LTR R2,R2 Any test cases? +000000000000039A 078D 284 BZR R13 ..No, return to caller +000000000000039C 0DC0 285 BASR R12,0 Set top of loop + 286 * +000000000000039E 9845 A000 0000000000000000 287 LM R4,R5,0(R10) Get count and start of addend values + 288 * ..which are the same as the augends +00000000000003A2 0D60 289 BASR R6,0 Set top of inner loop + 290 * +00000000000003A4 7880 3000 0000000000000000 291 LE FPR8,0(,R3) Get short BFP augend +00000000000003A8 7810 5000 0000000000000000 292 LE FPR1,0(,R5) Get short BFP addend +00000000000003AC B29D F294 0000000000000294 293 LFPC FPCREGNT Set exceptions non-trappable +00000000000003B0 B30A 0081 294 AEBR FPR8,FPR1 Add FPR0/FPR1 RRE +00000000000003B4 7080 7000 0000000000000000 295 STE FPR8,0(,R7) Store short BFP sum +00000000000003B8 B29C 8000 0000000000000000 296 STFPC 0(R8) Store resulting FPCR flags and DXC +00000000000003BC B222 0000 297 IPM R0 Get condition code and program mask +00000000000003C0 8800 001C 000000000000001C 298 SRL R0,28 Isolate CC in low order byte +00000000000003C4 4200 8003 0000000000000003 299 STC R0,3(,R8) Save condition code in results table + 300 * +00000000000003C8 7880 3000 0000000000000000 301 LE FPR8,0(,R3) Get short BFP augend +00000000000003CC 7810 5000 0000000000000000 302 LE FPR1,0(,R5) Get short BFP addend +00000000000003D0 B29D F298 0000000000000298 303 LFPC FPCREGTR Set exceptions trappable +00000000000003D4 B30A 0081 304 AEBR FPR8,FPR1 Add FPR0/FPR1 RRE +00000000000003D8 7080 7004 0000000000000004 305 STE FPR8,4(,R7) Store short BFP sum +00000000000003DC B29C 8004 0000000000000004 306 STFPC 4(R8) Store resulting FPCR flags and DXC +00000000000003E0 B222 0000 307 IPM R0 Get condition code and program mask +00000000000003E4 8800 001C 000000000000001C 308 SRL R0,28 Isolate CC in low order byte +00000000000003E8 4200 8007 0000000000000007 309 STC R0,7(,R8) Save condition code in results table + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 8 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 310 * +00000000000003EC 7880 3000 0000000000000000 311 LE FPR8,0(,R3) Get short BFP augend +00000000000003F0 7810 5000 0000000000000000 312 LE FPR1,0(,R5) Get short BFP addend +00000000000003F4 B29D F294 0000000000000294 313 LFPC FPCREGNT Set exceptions non-trappable +00000000000003F8 ED80 5000 000A 0000000000000000 314 AEB FPR8,0(,R5) Add FPR0/FPR1 RXE +00000000000003FE 7080 7008 0000000000000008 315 STE FPR8,8(,R7) Store short BFP sum +0000000000000402 B29C 8008 0000000000000008 316 STFPC 8(R8) Store resulting FPCR flags and DXC +0000000000000406 B222 0000 317 IPM R0 Get condition code and program mask +000000000000040A 8800 001C 000000000000001C 318 SRL R0,28 Isolate CC in low order byte +000000000000040E 4200 800B 000000000000000B 319 STC R0,11(,R8) Save condition code in results table + 320 * +0000000000000412 7880 3000 0000000000000000 321 LE FPR8,0(,R3) Get short BFP augend +0000000000000416 B29D F298 0000000000000298 322 LFPC FPCREGTR Set exceptions trappable +000000000000041A ED80 5000 000A 0000000000000000 323 AEB FPR8,0(,R5) Add FPR0/FPR1 RXE +0000000000000420 7080 700C 000000000000000C 324 STE FPR8,12(,R7) Store short BFP sum +0000000000000424 B29C 800C 000000000000000C 325 STFPC 12(R8) Store resulting FPCR flags and DXC +0000000000000428 B222 0000 326 IPM R0 Get condition code and program mask +000000000000042C 8800 001C 000000000000001C 327 SRL R0,28 Isolate CC in low order byte +0000000000000430 4200 800F 000000000000000F 328 STC R0,15(,R8) Save condition code in results table + 329 * +0000000000000434 4150 5004 0000000000000004 330 LA R5,4(,R5) Point to next addend value +0000000000000438 4170 7010 0000000000000010 331 LA R7,4*4(,R7) Point to next Add result area +000000000000043C 4180 8010 0000000000000010 332 LA R8,4*4(,R8) Point to next Add FPCR area +0000000000000440 0646 333 BCTR R4,R6 Loop through right-hand values + 334 * +0000000000000442 4130 3004 0000000000000004 335 LA R3,4(,R3) Point to next input augend +0000000000000446 062C 336 BCTR R2,R12 Loop through left-hand values +0000000000000448 07FD 337 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 9 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 339 *********************************************************************** + 340 * + 341 * Perform Add using provided short BFP input pairs. This set of + 342 * tests triggers IEEE exceptions Overflow, Underflow, and Inexact and + 343 * collects both trap and non-trap results. + 344 * + 345 * Four results are generated for each input: one RRE with all + 346 * exceptions non-trappable, a second RRE with all exceptions trappable, + 347 * a third RXE with all exceptions non-trappable, a fourth RXE with all + 348 * exceptions trappable, + 349 * + 350 * The sum, FPCR, and condition code are stored for each result. + 351 * + 352 *********************************************************************** + + +000000000000044A 9823 A000 0000000000000000 354 SBFPF LM R2,R3,0(R10) Get count and address of test input values +000000000000044E 9878 A008 0000000000000008 355 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000452 1222 356 LTR R2,R2 Any test cases? +0000000000000454 078D 357 BZR R13 ..No, return to caller +0000000000000456 0DC0 358 BASR R12,0 Set top of loop + 359 * +0000000000000458 B29D F294 0000000000000294 360 LFPC FPCREGNT Set exceptions non-trappable +000000000000045C 7880 3000 0000000000000000 361 LE FPR8,0(,R3) Get short BFP augend +0000000000000460 7810 3004 0000000000000004 362 LE FPR1,4(,R3) Get short BFP addend +0000000000000464 B30A 0081 363 AEBR FPR8,FPR1 Add FPR8/FPR1 RRE non-trappable +0000000000000468 7080 7000 0000000000000000 364 STE FPR8,0(,R7) Store short BFP sum +000000000000046C B29C 8000 0000000000000000 365 STFPC 0(R8) Store resulting FPCR flags and DXC +0000000000000470 B222 0000 366 IPM R0 Get condition code and program mask +0000000000000474 8800 001C 000000000000001C 367 SRL R0,28 Isolate CC in low order byte +0000000000000478 4200 8003 0000000000000003 368 STC R0,3(,R8) Save condition code in results table + 369 * +000000000000047C B29D F298 0000000000000298 370 LFPC FPCREGTR Set exceptions trappable +0000000000000480 7880 3000 0000000000000000 371 LE FPR8,0(,R3) Reload short BFP augend + 372 * ..addend is still in FPR1 +0000000000000484 B30A 0081 373 AEBR FPR8,FPR1 Add FPR8/FPR1 RRE trappable +0000000000000488 7080 7004 0000000000000004 374 STE FPR8,4(,R7) Store short BFP sum +000000000000048C B29C 8004 0000000000000004 375 STFPC 4(R8) Store resulting FPCR flags and DXC +0000000000000490 B222 0000 376 IPM R0 Get condition code and program mask +0000000000000494 8800 001C 000000000000001C 377 SRL R0,28 Isolate CC in low order byte +0000000000000498 4200 8007 0000000000000007 378 STC R0,7(,R8) Save condition code in results table + 379 * +000000000000049C B29D F294 0000000000000294 380 LFPC FPCREGNT Set exceptions non-trappable +00000000000004A0 7880 3000 0000000000000000 381 LE FPR8,0(,R3) Reload short BFP augend +00000000000004A4 ED80 3004 000A 0000000000000004 382 AEB FPR8,4(,R3) Add FPR8 by addend RXE non-trappable +00000000000004AA 7080 7008 0000000000000008 383 STE FPR8,8(,R7) Store short BFP sum +00000000000004AE B29C 8008 0000000000000008 384 STFPC 8(R8) Store resulting FPCR flags and DXC +00000000000004B2 B222 0000 385 IPM R0 Get condition code and program mask +00000000000004B6 8800 001C 000000000000001C 386 SRL R0,28 Isolate CC in low order byte +00000000000004BA 4200 800B 000000000000000B 387 STC R0,11(,R8) Save condition code in results table + 388 * +00000000000004BE B29D F298 0000000000000298 389 LFPC FPCREGTR Set exceptions trappable + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 10 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000004C2 7880 3000 0000000000000000 390 LE FPR8,0(,R3) Reload short BFP augend +00000000000004C6 ED80 3004 000A 0000000000000004 391 AEB FPR8,4(,R3) Add FPR8 by addend RXE trappable +00000000000004CC 7080 700C 000000000000000C 392 STE FPR8,12(,R7) Store short BFP sum +00000000000004D0 B29C 800C 000000000000000C 393 STFPC 12(R8) Store resulting FPCR flags and DXC +00000000000004D4 B222 0000 394 IPM R0 Get condition code and program mask +00000000000004D8 8800 001C 000000000000001C 395 SRL R0,28 Isolate CC in low order byte +00000000000004DC 4200 800F 000000000000000F 396 STC R0,15(,R8) Save condition code in results table + 397 * +00000000000004E0 4130 3008 0000000000000008 398 LA R3,2*4(,R3) Point to next input value pair +00000000000004E4 4170 7010 0000000000000010 399 LA R7,4*4(,R7) Point to next sum result set +00000000000004E8 4180 8010 0000000000000010 400 LA R8,4*4(,R8) Point to next FPCR result set +00000000000004EC 062C 401 BCTR R2,R12 Convert next input value. +00000000000004EE 07FD 402 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 11 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 404 *********************************************************************** + 405 * + 406 * Perform Add using provided short BFP input pairs. This set of + 407 * tests exhaustively tests all rounding modes available for Add. + 408 * The rounding mode can only be specified in the FPC. + 409 * + 410 * All five FPC rounding modes are tested because the preceeding tests, + 411 * using rounding mode RNTE, do not often create results that require + 412 * rounding. + 413 * + 414 * Two results are generated for each input and rounding mode: one RRE + 415 * and one RXE. Traps are disabled for all rounding mode tests. + 416 * + 417 * The sum, FPCR, and condition code are stored for each test. + 418 * + 419 *********************************************************************** + + +00000000000004F0 9823 A000 0000000000000000 421 SBFPRM LM R2,R3,0(R10) Get count and address of test input values +00000000000004F4 9878 A008 0000000000000008 422 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000004F8 1222 423 LTR R2,R2 Any test cases? +00000000000004FA 078D 424 BZR R13 ..No, return to caller +00000000000004FC 1711 425 XR R1,R1 Zero register 1 for use in IC/STC/indexing +00000000000004FE 0DC0 426 BASR R12,0 Set top of test case loop + 427 +0000000000000500 4150 0005 0000000000000005 428 LA R5,FPCMCT Get count of FPC modes to be tested +0000000000000504 0D90 429 BASR R9,0 Set top of rounding mode outer loop + 430 * +0000000000000506 4315 F8AF 00000000000008AF 431 IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode + 432 * +000000000000050A B29D F294 0000000000000294 433 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000050E B2B8 1000 0000000000000000 434 SRNMB 0(R1) Set FPC Rounding Mode +0000000000000512 7880 3000 0000000000000000 435 LE FPR8,0(,R3) Get short BFP augend +0000000000000516 7810 3004 0000000000000004 436 LE FPR1,4(,R3) Get short BFP addend +000000000000051A B30A 0081 437 AEBR FPR8,FPR1 Add RRE FPR8/FPR1 non-trappable +000000000000051E 7080 7000 0000000000000000 438 STE FPR8,0(,R7) Store short BFP sum +0000000000000522 B29C 8000 0000000000000000 439 STFPC 0(R8) Store resulting FPCR flags and DXC +0000000000000526 B222 0000 440 IPM R0 Get condition code and program mask +000000000000052A 8800 001C 000000000000001C 441 SRL R0,28 Isolate CC in low order byte +000000000000052E 4200 8003 0000000000000003 442 STC R0,3(,R8) Save condition code in results table + 443 * +0000000000000532 B29D F294 0000000000000294 444 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000536 B2B8 1000 0000000000000000 445 SRNMB 0(R1) Set FPC Rounding Mode +000000000000053A 7880 3000 0000000000000000 446 LE FPR8,0(,R3) Get short BFP augend +000000000000053E ED80 3004 000A 0000000000000004 447 AEB FPR8,4(,R3) Add RXE FPR8 by addend non-trappable +0000000000000544 7080 7004 0000000000000004 448 STE FPR8,4(,R7) Store short BFP sum +0000000000000548 B29C 8004 0000000000000004 449 STFPC 4(R8) Store resulting FPCR flags and DXC +000000000000054C B222 0000 450 IPM R0 Get condition code and program mask +0000000000000550 8800 001C 000000000000001C 451 SRL R0,28 Isolate CC in low order byte +0000000000000554 4200 8007 0000000000000007 452 STC R0,7(,R8) Save condition code in results table + 453 * +0000000000000558 4170 7008 0000000000000008 454 LA R7,2*4(,R7) Point to next sum result set + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 12 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +000000000000055C 4180 8008 0000000000000008 455 LA R8,2*4(,R8) Point to next FPCR result area + 456 * +0000000000000560 0659 457 BCTR R5,R9 Iterate to next FPC mode for this input + 458 * + 459 * End of FPC modes to be tested. Advance to next test case. We will + 460 * skip eight bytes of result area so that each set of five result + 461 * value pairs starts at a memory address ending in zero for the + 462 * convenience of memory dump review. + 463 * +0000000000000562 4130 3008 0000000000000008 464 LA R3,2*4(,R3) Point to next input value pair +0000000000000566 4170 7008 0000000000000008 465 LA R7,8(,R7) Skip to start of next result set +000000000000056A 4180 8008 0000000000000008 466 LA R8,8(,R8) Skip to start of next FPCR result set +000000000000056E 062C 467 BCTR R2,R12 Advance to the next input pair + 468 * +0000000000000570 07FD 469 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 13 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 471 *********************************************************************** + 472 * + 473 * Perform Add using provided long BFP inputs. This set of tests + 474 * checks NaN propagation, operations on values that are not finite + 475 * numbers, and other basic tests. This set generates results that can + 476 * be validated against Figure 19-13 on page 19-16 of SA22-7832-10. + 477 * + 478 * That Figure has separate rows and colums for Normal and Tiny + 479 * operands. Although the results are effectively the same for Normal + 480 * and Tiny in any combination, the input data includes Normal and + 481 * Tiny values. + 482 * + 483 * Four results are generated for each input: one RRE with all + 484 * exceptions non-trappable, a second RRE with all exceptions trappable, + 485 * a third RXE with all exceptions non-trappable, a fourth RXE with all + 486 * exceptions trappable, + 487 * + 488 * The sum, FPCR, and condition code are stored for each result. + 489 * + 490 *********************************************************************** + + +0000000000000572 492 LBFPNF DS 0H BFP long non-finite values tests +0000000000000572 9823 A000 0000000000000000 493 LM R2,R3,0(R10) Get count and address of augend values +0000000000000576 9878 A008 0000000000000008 494 LM R7,R8,8(R10) Get address of result area and flag area. +000000000000057A 1222 495 LTR R2,R2 Any test cases? +000000000000057C 078D 496 BZR R13 ..No, return to caller +000000000000057E 0DC0 497 BASR R12,0 Set top of loop + 498 * +0000000000000580 9845 A000 0000000000000000 499 LM R4,R5,0(R10) Get count and start of addend values + 500 * ..which are the same as the augends +0000000000000584 0D60 501 BASR R6,0 Set top of inner loop + 502 * +0000000000000586 6880 3000 0000000000000000 503 LD FPR8,0(,R3) Get long BFP augend +000000000000058A 6810 5000 0000000000000000 504 LD FPR1,0(,R5) Get long BFP addend +000000000000058E B29D F294 0000000000000294 505 LFPC FPCREGNT Set exceptions non-trappable +0000000000000592 B31A 0081 506 ADBR FPR8,FPR1 Add FPR0/FPR1 RRE +0000000000000596 6080 7000 0000000000000000 507 STD FPR8,0(,R7) Store long BFP sum +000000000000059A B29C 8000 0000000000000000 508 STFPC 0(R8) Store resulting FPCR flags and DXC +000000000000059E B222 0000 509 IPM R0 Get condition code and program mask +00000000000005A2 8800 001C 000000000000001C 510 SRL R0,28 Isolate CC in low order byte +00000000000005A6 4200 8003 0000000000000003 511 STC R0,3(,R8) Save condition code in results table + 512 * +00000000000005AA 6880 3000 0000000000000000 513 LD FPR8,0(,R3) Get long BFP augend +00000000000005AE 6810 5000 0000000000000000 514 LD FPR1,0(,R5) Get long BFP addend +00000000000005B2 B29D F298 0000000000000298 515 LFPC FPCREGTR Set exceptions trappable +00000000000005B6 B31A 0081 516 ADBR FPR8,FPR1 Add FPR0/FPR1 RRE +00000000000005BA 6080 7008 0000000000000008 517 STD FPR8,8(,R7) Store long BFP remainder +00000000000005BE B29C 8004 0000000000000004 518 STFPC 4(R8) Store resulting FPCR flags and DXC +00000000000005C2 B222 0000 519 IPM R0 Get condition code and program mask +00000000000005C6 8800 001C 000000000000001C 520 SRL R0,28 Isolate CC in low order byte +00000000000005CA 4200 8007 0000000000000007 521 STC R0,7(,R8) Save condition code in results table + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 14 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 522 * +00000000000005CE 6880 3000 0000000000000000 523 LD FPR8,0(,R3) Get long BFP augend +00000000000005D2 B29D F294 0000000000000294 524 LFPC FPCREGNT Set exceptions non-trappable +00000000000005D6 ED80 5000 001A 0000000000000000 525 ADB FPR8,0(,R5) Add FPR0/FPR1 RXE +00000000000005DC 6080 7010 0000000000000010 526 STD FPR8,16(,R7) Store long BFP sum +00000000000005E0 B29C 8008 0000000000000008 527 STFPC 8(R8) Store resulting FPCR flags and DXC +00000000000005E4 B222 0000 528 IPM R0 Get condition code and program mask +00000000000005E8 8800 001C 000000000000001C 529 SRL R0,28 Isolate CC in low order byte +00000000000005EC 4200 800B 000000000000000B 530 STC R0,11(,R8) Save condition code in results table + 531 * +00000000000005F0 6880 3000 0000000000000000 532 LD FPR8,0(,R3) Get long BFP augend +00000000000005F4 B29D F298 0000000000000298 533 LFPC FPCREGTR Set exceptions trappable +00000000000005F8 ED80 5000 001A 0000000000000000 534 ADB FPR8,0(,R5) Add FPR0/FPR1 RXE +00000000000005FE 6080 7018 0000000000000018 535 STD FPR8,24(,R7) Store long BFP remainder +0000000000000602 B29C 800C 000000000000000C 536 STFPC 12(R8) Store resulting FPCR flags and DXC +0000000000000606 B222 0000 537 IPM R0 Get condition code and program mask +000000000000060A 8800 001C 000000000000001C 538 SRL R0,28 Isolate CC in low order byte +000000000000060E 4200 800F 000000000000000F 539 STC R0,15(,R8) Save condition code in results table + 540 * +0000000000000612 4150 5008 0000000000000008 541 LA R5,8(,R5) Point to next addend value +0000000000000616 4170 7020 0000000000000020 542 LA R7,4*8(,R7) Point to next Add result area +000000000000061A 4180 8010 0000000000000010 543 LA R8,4*4(,R8) Point to next Add FPCR area +000000000000061E 0646 544 BCTR R4,R6 Loop through right-hand values + 545 * +0000000000000620 4130 3008 0000000000000008 546 LA R3,8(,R3) Point to next augend value +0000000000000624 062C 547 BCTR R2,R12 Add until all cases tested +0000000000000626 07FD 548 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 15 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 550 *********************************************************************** + 551 * + 552 * Perform Add using provided long BFP input pairs. This set of + 553 * tests triggers IEEE exceptions Overflow, Underflow, and Inexact and + 554 * collects non-trap and trap results. + 555 * + 556 * Four results are generated for each input: one RRE with all + 557 * exceptions non-trappable, a second RRE with all exceptions trappable, + 558 * a third RXE with all exceptions non-trappable, a fourth RXE with all + 559 * exceptions trappable, + 560 * + 561 * The sum, FPCR, and condition code are stored for each result. + 562 * + 563 *********************************************************************** + + +0000000000000628 9823 A000 0000000000000000 565 LBFPF LM R2,R3,0(R10) Get count and address of test input values +000000000000062C 9878 A008 0000000000000008 566 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000630 1222 567 LTR R2,R2 Any test cases? +0000000000000632 078D 568 BZR R13 ..No, return to caller +0000000000000634 0DC0 569 BASR R12,0 Set top of loop + 570 * +0000000000000636 B29D F294 0000000000000294 571 LFPC FPCREGNT Set exceptions non-trappable +000000000000063A 6880 3000 0000000000000000 572 LD FPR8,0(,R3) Get short BFP augend +000000000000063E 6810 3008 0000000000000008 573 LD FPR1,8(,R3) Get short BFP addend +0000000000000642 B31A 0081 574 ADBR FPR8,FPR1 Add FPR8/FPR1 RRE non-trappable +0000000000000646 6080 7000 0000000000000000 575 STD FPR8,0(,R7) Store short BFP sum +000000000000064A B29C 8000 0000000000000000 576 STFPC 0(R8) Store resulting FPCR flags and DXC +000000000000064E B222 0000 577 IPM R0 Get condition code and program mask +0000000000000652 8800 001C 000000000000001C 578 SRL R0,28 Isolate CC in low order byte +0000000000000656 4200 8003 0000000000000003 579 STC R0,3(,R8) Save condition code in results table + 580 * +000000000000065A B29D F298 0000000000000298 581 LFPC FPCREGTR Set exceptions trappable +000000000000065E 6880 3000 0000000000000000 582 LD FPR8,0(,R3) Reload short BFP augend + 583 * ..addend is still in FPR1 +0000000000000662 B31A 0081 584 ADBR FPR8,FPR1 Add FPR8/FPR1 RRE trappable +0000000000000666 6080 7008 0000000000000008 585 STD FPR8,8(,R7) Store short BFP sum +000000000000066A B29C 8004 0000000000000004 586 STFPC 4(R8) Store resulting FPCR flags and DXC +000000000000066E B222 0000 587 IPM R0 Get condition code and program mask +0000000000000672 8800 001C 000000000000001C 588 SRL R0,28 Isolate CC in low order byte +0000000000000676 4200 8007 0000000000000007 589 STC R0,7(,R8) Save condition code in results table + 590 * +000000000000067A B29D F294 0000000000000294 591 LFPC FPCREGNT Set exceptions non-trappable +000000000000067E 6880 3000 0000000000000000 592 LD FPR8,0(,R3) Reload short BFP augend +0000000000000682 ED80 3008 001A 0000000000000008 593 ADB FPR8,8(,R3) Add FPR8/FPR1 RXE non-trappable +0000000000000688 6080 7010 0000000000000010 594 STD FPR8,16(,R7) Store short BFP sum +000000000000068C B29C 8008 0000000000000008 595 STFPC 8(R8) Store resulting FPCR flags and DXC +0000000000000690 B222 0000 596 IPM R0 Get condition code and program mask +0000000000000694 8800 001C 000000000000001C 597 SRL R0,28 Isolate CC in low order byte +0000000000000698 4200 800B 000000000000000B 598 STC R0,11(,R8) Save condition code in results table + 599 * +000000000000069C B29D F298 0000000000000298 600 LFPC FPCREGTR Set exceptions trappable + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 16 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000006A0 6880 3000 0000000000000000 601 LD FPR8,0(,R3) Reload short BFP augend +00000000000006A4 ED80 3008 001A 0000000000000008 602 ADB FPR8,8(,R3) Add FPR8/FPR1 RXE trappable +00000000000006AA 6080 7018 0000000000000018 603 STD FPR8,24(,R7) Store short BFP sum +00000000000006AE B29C 800C 000000000000000C 604 STFPC 12(R8) Store resulting FPCR flags and DXC +00000000000006B2 B222 0000 605 IPM R0 Get condition code and program mask +00000000000006B6 8800 001C 000000000000001C 606 SRL R0,28 Isolate CC in low order byte +00000000000006BA 4200 800F 000000000000000F 607 STC R0,15(,R8) Save condition code in results table + 608 * +00000000000006BE 4130 3010 0000000000000010 609 LA R3,2*8(,R3) Point to next input value pair +00000000000006C2 4170 7020 0000000000000020 610 LA R7,4*8(,R7) Point to next quotent result pair +00000000000006C6 4180 8010 0000000000000010 611 LA R8,4*4(,R8) Point to next FPCR result area +00000000000006CA 062C 612 BCTR R2,R12 Convert next input value. +00000000000006CC 07FD 613 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 17 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 615 *********************************************************************** + 616 * + 617 * Perform Add using provided long BFP input pairs. This set of + 618 * tests exhaustively tests all rounding modes available for Add. + 619 * The rounding mode can only be specified in the FPC. + 620 * + 621 * All five FPC rounding modes are tested because the preceeding tests, + 622 * using rounding mode RNTE, do not often create results that require + 623 * rounding. + 624 * + 625 * Two results are generated for each input and rounding mode: one RRE + 626 * and one RXE. Traps are disabled for all rounding mode tests. + 627 * + 628 * The sum, FPCR, and condition code are stored for each result. + 629 * + 630 *********************************************************************** + + +00000000000006CE 9823 A000 0000000000000000 632 LBFPRM LM R2,R3,0(R10) Get count and address of test input values +00000000000006D2 9878 A008 0000000000000008 633 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000006D6 1222 634 LTR R2,R2 Any test cases? +00000000000006D8 078D 635 BZR R13 ..No, return to caller +00000000000006DA 1711 636 XR R1,R1 Zero register 1 for use in IC/STC/indexing +00000000000006DC 0DC0 637 BASR R12,0 Set top of test case loop + 638 +00000000000006DE 4150 0005 0000000000000005 639 LA R5,FPCMCT Get count of FPC modes to be tested +00000000000006E2 0D90 640 BASR R9,0 Set top of rounding mode loop + 641 * +00000000000006E4 4315 F8AF 00000000000008AF 642 IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode + 643 * +00000000000006E8 B29D F294 0000000000000294 644 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000006EC B2B8 1000 0000000000000000 645 SRNMB 0(R1) Set FPC Rounding Mode +00000000000006F0 6880 3000 0000000000000000 646 LD FPR8,0(,R3) Get long BFP augend +00000000000006F4 6810 3008 0000000000000008 647 LD FPR1,8(,R3) Get long BFP addend +00000000000006F8 B31A 0081 648 ADBR FPR8,FPR1 Add RRE FPR8/FPR1 non-trappable +00000000000006FC 6080 7000 0000000000000000 649 STD FPR8,0(,R7) Store long BFP sum +0000000000000700 B29C 8000 0000000000000000 650 STFPC 0(R8) Store resulting FPCR flags and DXC +0000000000000704 B222 0000 651 IPM R0 Get condition code and program mask +0000000000000708 8800 001C 000000000000001C 652 SRL R0,28 Isolate CC in low order byte +000000000000070C 4200 8003 0000000000000003 653 STC R0,3(,R8) Save condition code in results table + 654 * +0000000000000710 B29D F294 0000000000000294 655 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000714 B2B8 1000 0000000000000000 656 SRNMB 0(R1) Set FPC Rounding Mode +0000000000000718 6880 3000 0000000000000000 657 LD FPR8,0(,R3) Reload long BFP augend +000000000000071C ED80 3008 001A 0000000000000008 658 ADB FPR8,8(,R3) Add RXE FPR8 by addend non-trappable +0000000000000722 6080 7008 0000000000000008 659 STD FPR8,8(,R7) Store long BFP sum +0000000000000726 B29C 8004 0000000000000004 660 STFPC 4(R8) Store resulting FPCR flags and DXC +000000000000072A B222 0000 661 IPM R0 Get condition code and program mask +000000000000072E 8800 001C 000000000000001C 662 SRL R0,28 Isolate CC in low order byte +0000000000000732 4200 8007 0000000000000007 663 STC R0,7(,R8) Save condition code in results table + 664 * +0000000000000736 4170 7010 0000000000000010 665 LA R7,2*8(,R7) Point to next sum result set + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 18 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +000000000000073A 4180 8008 0000000000000008 666 LA R8,2*4(,R8) Point to next FPCR result area + 667 * +000000000000073E 0659 668 BCTR R5,R9 Iterate to next FPC mode + 669 * + 670 * End of FPC modes to be tested. Advance to next test case. We will + 671 * skip eight bytes of FPCR result area so that each set of five result + 672 * FPCR contents pairs starts at a memory address ending in zero for the + 673 * convenience of memory dump review. + 674 * +0000000000000740 4130 3010 0000000000000010 675 LA R3,2*8(,R3) Point to next input value pair +0000000000000744 4180 8008 0000000000000008 676 LA R8,8(,R8) Skip to start of next FPCR result area +0000000000000748 062C 677 BCTR R2,R12 Add next input value lots of times + 678 * +000000000000074A 07FD 679 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 19 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 681 *********************************************************************** + 682 * + 683 * Perform Add using provided extended BFP inputs. This set of tests + 684 * checks NaN propagation, operations on values that are not finite + 685 * numbers, and other basic tests. This set generates results that can + 686 * be validated against Figure 19-13 on page 19-16 of SA22-7832-10. + 687 * + 688 * That Figure has separate rows and colums for Normal and Tiny + 689 * operands. Although the results are effectively the same for Normal + 690 * and Tiny in any combination, the input data includes Normal and + 691 * Tiny values. + 692 * + 693 * Two results are generated for each input: one RRE with all + 694 * exceptions non-trappable, and a second RRE with all exceptions + 695 * trappable. Extended BFP Add does not have an RXE format. + 696 * + 697 * The sum, FPCR, and condition code are stored for each result. + 698 * + 699 *********************************************************************** + + +000000000000074C 701 XBFPNF DS 0H BFP extended non-finite values tests +000000000000074C 9823 A000 0000000000000000 702 LM R2,R3,0(R10) Get count and address of augend values +0000000000000750 9878 A008 0000000000000008 703 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000754 1222 704 LTR R2,R2 Any test cases? +0000000000000756 078D 705 BZR R13 ..No, return to caller +0000000000000758 0DC0 706 BASR R12,0 Set top of loop + 707 * +000000000000075A 9845 A000 0000000000000000 708 LM R4,R5,0(R10) Get count and start of addend values + 709 * ..which are the same as the augends +000000000000075E 0D60 710 BASR R6,0 Set top of inner loop + 711 * +0000000000000760 6880 3000 0000000000000000 712 LD FPR8,0(,R3) Get extended BFP augend part 1 +0000000000000764 68A0 3008 0000000000000008 713 LD FPR10,8(,R3) Get extended BFP augend part 2 +0000000000000768 6810 5000 0000000000000000 714 LD FPR1,0(,R5) Get extended BFP addend part 1 +000000000000076C 6830 5008 0000000000000008 715 LD FPR3,8(,R5) Get extended BFP addend part 2 +0000000000000770 B29D F294 0000000000000294 716 LFPC FPCREGNT Set exceptions non-trappable +0000000000000774 B34A 0081 717 AXBR FPR8,FPR1 Add FPR0/FPR1 RRE +0000000000000778 6080 7000 0000000000000000 718 STD FPR8,0(,R7) Store extended BFP sum part 1 +000000000000077C 60A0 7008 0000000000000008 719 STD FPR10,8(,R7) Store extended BFP sum part 2 +0000000000000780 B29C 8000 0000000000000000 720 STFPC 0(R8) Store resulting FPCR flags and DXC +0000000000000784 B222 0000 721 IPM R0 Get condition code and program mask +0000000000000788 8800 001C 000000000000001C 722 SRL R0,28 Isolate CC in low order byte +000000000000078C 4200 8003 0000000000000003 723 STC R0,3(,R8) Save condition code in results table + 724 * +0000000000000790 6880 3000 0000000000000000 725 LD FPR8,0(,R3) Get extended BFP augend part 1 +0000000000000794 68A0 3008 0000000000000008 726 LD FPR10,8(,R3) Get extended BFP augend part 2 +0000000000000798 6810 5000 0000000000000000 727 LD FPR1,0(,R5) Get extended BFP addend part 1 +000000000000079C 6830 5008 0000000000000008 728 LD FPR3,8(,R5) Get extended BFP addend part 2 +00000000000007A0 B29D F298 0000000000000298 729 LFPC FPCREGTR Set exceptions trappable +00000000000007A4 B34A 0081 730 AXBR FPR8,FPR1 Add FPR0/FPR1 RRE +00000000000007A8 6080 7010 0000000000000010 731 STD FPR8,16(,R7) Store extended BFP sum part 1 + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 20 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000007AC 60A0 7018 0000000000000018 732 STD FPR10,24(,R7) Store extended BFP sum part 2 +00000000000007B0 B29C 8004 0000000000000004 733 STFPC 4(R8) Store resulting FPCR flags and DXC +00000000000007B4 B222 0000 734 IPM R0 Get condition code and program mask +00000000000007B8 8800 001C 000000000000001C 735 SRL R0,28 Isolate CC in low order byte +00000000000007BC 4200 8007 0000000000000007 736 STC R0,7(,R8) Save condition code in results table + 737 * +00000000000007C0 4150 5010 0000000000000010 738 LA R5,16(,R5) Point to next addend value +00000000000007C4 4170 7020 0000000000000020 739 LA R7,32(,R7) Point to next Add result area +00000000000007C8 4180 8010 0000000000000010 740 LA R8,16(,R8) Point to next Add FPCR area +00000000000007CC 0646 741 BCTR R4,R6 Loop through right-hand values + 742 * +00000000000007CE 4130 3010 0000000000000010 743 LA R3,16(,R3) Point to next augend value +00000000000007D2 062C 744 BCTR R2,R12 Add until all cases tested +00000000000007D4 07FD 745 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 21 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 747 *********************************************************************** + 748 * + 749 * Perform Add using provided extended BFP input pairs. This set of + 750 * tests triggers IEEE exceptions Overflow, Underflow, and Inexact and + 751 * collects results when the exceptions do not result in a trap and when + 752 * they do. + 753 * + 754 * Two results are generated for each input: one RRE with all + 755 * exceptions non-trappable and a second RRE with all exceptions + 756 * trappable. There is no RXE format for Add in extended precision. + 757 * + 758 * The sum, FPCR, and condition code are stored for each result. + 759 * + 760 *********************************************************************** + + +00000000000007D6 9823 A000 0000000000000000 762 XBFPF LM R2,R3,0(R10) Get count and address of test input values +00000000000007DA 9878 A008 0000000000000008 763 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000007DE 1222 764 LTR R2,R2 Any test cases? +00000000000007E0 078D 765 BZR R13 ..No, return to caller +00000000000007E2 0DC0 766 BASR R12,0 Set top of loop + 767 * +00000000000007E4 B29D F294 0000000000000294 768 LFPC FPCREGNT Set exceptions non-trappable +00000000000007E8 6880 3000 0000000000000000 769 LD FPR8,0(,R3) Get extended BFP augend part 1 +00000000000007EC 68A0 3008 0000000000000008 770 LD FPR10,8(,R3) Get extended BFP augend part 2 +00000000000007F0 6810 3010 0000000000000010 771 LD FPR1,16(,R3) Get extended BFP addend part 1 +00000000000007F4 6830 3018 0000000000000018 772 LD FPR3,24(,R3) Get extended BFP addend part 2 +00000000000007F8 B34A 0081 773 AXBR FPR8,FPR1 Add FPR8-10/FPR1-3 RRE non-trappable +00000000000007FC 6080 7000 0000000000000000 774 STD FPR8,0(,R7) Store extended BFP sum part 1 +0000000000000800 60A0 7008 0000000000000008 775 STD FPR10,8(,R7) Store extended BFP sum part 2 +0000000000000804 B29C 8000 0000000000000000 776 STFPC 0(R8) Store resulting FPCR flags and DXC +0000000000000808 B222 0000 777 IPM R0 Get condition code and program mask +000000000000080C 8800 001C 000000000000001C 778 SRL R0,28 Isolate CC in low order byte +0000000000000810 4200 8003 0000000000000003 779 STC R0,3(,R8) Save condition code in results table + 780 * +0000000000000814 B29D F298 0000000000000298 781 LFPC FPCREGTR Set exceptions trappable +0000000000000818 6880 3000 0000000000000000 782 LD FPR8,0(,R3) Reload extended BFP augend part 1 +000000000000081C 68A0 3008 0000000000000008 783 LD FPR10,8(,R3) Reload extended BFP augend part 2 + 784 * ..addend is still in FPR1-FPR3 +0000000000000820 B34A 0081 785 AXBR FPR8,FPR1 Add FPR8-10/FPR1-3 RRE trappable +0000000000000824 6080 7010 0000000000000010 786 STD FPR8,16(,R7) Store extended BFP sum part 1 +0000000000000828 60A0 7018 0000000000000018 787 STD FPR10,24(,R7) Store extended BFP sum part 2 +000000000000082C B29C 8004 0000000000000004 788 STFPC 4(R8) Store resulting FPCR flags and DXC +0000000000000830 B222 0000 789 IPM R0 Get condition code and program mask +0000000000000834 8800 001C 000000000000001C 790 SRL R0,28 Isolate CC in low order byte +0000000000000838 4200 8007 0000000000000007 791 STC R0,7(,R8) Save condition code in results table + 792 * +000000000000083C 4130 3020 0000000000000020 793 LA R3,32(,R3) Point to next input value pair +0000000000000840 4170 7020 0000000000000020 794 LA R7,32(,R7) Point to next quotent result pair +0000000000000844 4180 8010 0000000000000010 795 LA R8,16(,R8) Point to next FPCR result area +0000000000000848 062C 796 BCTR R2,R12 Convert next input value. + 797 * + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 22 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +000000000000084A 07FD 798 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 23 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 800 *********************************************************************** + 801 * + 802 * Perform Add using provided extended BFP input pairs. This set of + 803 * tests exhaustively tests all rounding modes available for Add. + 804 * The rounding mode can only be specified in the FPC. + 805 * + 806 * All five FPC rounding modes are tested because the preceeding tests, + 807 * using rounding mode RNTE, do not often create results that require + 808 * rounding. + 809 * + 810 * Two results are generated for each input and rounding mode: one RRE + 811 * and one RXE. Traps are disabled for all rounding mode tests. + 812 * + 813 * The sum, FPCR, and condition code are stored for each result. + 814 * + 815 *********************************************************************** + + +000000000000084C 9823 A000 0000000000000000 817 XBFPRM LM R2,R3,0(R10) Get count and address of test input values +0000000000000850 9878 A008 0000000000000008 818 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000854 1222 819 LTR R2,R2 Any test cases? +0000000000000856 078D 820 BZR R13 ..No, return to caller +0000000000000858 1711 821 XR R1,R1 Zero register 1 for use in IC/STC/indexing +000000000000085A 0DC0 822 BASR R12,0 Set top of test case loop + 823 +000000000000085C 4150 0005 0000000000000005 824 LA R5,FPCMCT Get count of FPC modes to be tested +0000000000000860 0D90 825 BASR R9,0 Set top of rounding mode loop + 826 * +0000000000000862 4315 F8AF 00000000000008AF 827 IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode + 828 * +0000000000000866 B29D F294 0000000000000294 829 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000086A B2B8 1000 0000000000000000 830 SRNMB 0(R1) Set FPC Rounding Mode +000000000000086E 6880 3000 0000000000000000 831 LD FPR8,0(,R3) Get extended BFP augend part 1 +0000000000000872 68A0 3008 0000000000000008 832 LD FPR10,8(,R3) Get extended BFP augend part 2 +0000000000000876 6810 3010 0000000000000010 833 LD FPR1,16(,R3) Get extended BFP addend part 1 +000000000000087A 6830 3018 0000000000000018 834 LD FPR3,24(,R3) Get extended BFP addend part 2 +000000000000087E B34A 0081 835 AXBR FPR8,FPR1 Add RRE FPR8/FPR1 non-trappable +0000000000000882 6080 7000 0000000000000000 836 STD FPR8,0(,R7) Store extended BFP sum part 1 +0000000000000886 60A0 7008 0000000000000008 837 STD FPR10,8(,R7) Store extended BFP sum part 2 +000000000000088A B29C 8000 0000000000000000 838 STFPC 0(R8) Store resulting FPCR flags and DXC +000000000000088E B222 0000 839 IPM R0 Get condition code and program mask +0000000000000892 8800 001C 000000000000001C 840 SRL R0,28 Isolate CC in low order byte +0000000000000896 4200 8003 0000000000000003 841 STC R0,3(,R8) Save condition code in results table + 842 * +000000000000089A 4170 7010 0000000000000010 843 LA R7,16(,R7) Point to next sum result set +000000000000089E 4180 8004 0000000000000004 844 LA R8,4(,R8) Point to next FPCR result area + 845 * +00000000000008A2 0659 846 BCTR R5,R9 Iterate to next FPC mode + 847 * + 848 * End of FPC modes to be tested. Advance to next test case. We will + 849 * skip eight bytes of FPCR result area so that each set of five result + 850 * FPCR contents pairs starts at a memory address ending in zero for the + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 24 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 851 * convenience of memory dump review. + 852 * +00000000000008A4 4130 3020 0000000000000020 853 LA R3,2*16(,R3) Point to next input value pair +00000000000008A8 4180 800C 000000000000000C 854 LA R8,12(,R8) Skip to start of next FPCR result area +00000000000008AC 062C 855 BCTR R2,R12 Add next input value lots of times + 856 * +00000000000008AE 07FD 857 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 25 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 859 *********************************************************************** + 860 * + 861 * Table of FPC rounding modes to test sum rounding modes. + 862 * + 863 * The Set BFP Rounding Mode does allow specification of the FPC + 864 * rounding mode as an address, so we shall index into a table of + 865 * BFP rounding modes without bothering with Execute. + 866 * + 867 *********************************************************************** + + + 869 * + 870 * Rounding modes that may be set in the FPCR. The FPCR controls + 871 * rounding of the sum. + 872 * + 873 * These are indexed directly by the loop counter, which counts down. + 874 * So the modes are listed in reverse order here. + 875 * +00000000000008B0 876 FPCMODES DS 0C +00000000000008B0 07 877 DC AL1(7) RFS, Round for shorter precision +00000000000008B1 03 878 DC AL1(3) RM, Round to -infinity +00000000000008B2 02 879 DC AL1(2) RP, Round to +infinity +00000000000008B3 01 880 DC AL1(1) RZ, Round to zero +00000000000008B4 00 881 DC AL1(0) RNTE, Round to Nearest, ties to even + 0000000000000005 0000000000000001 882 FPCMCT EQU *-FPCMODES Count of FPC Modes to be tested + 883 * + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 26 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 885 *********************************************************************** + 886 * + 887 * Short BFP test data sets for Add testing. + 888 * + 889 * The first test data set is used for tests of basic functionality, + 890 * NaN propagation, and results from operations involving other than + 891 * finite numbers. + 892 * + 893 * The second test data set is used for testing boundary conditions + 894 * using two finite non-zero values. Each possible condition code + 895 * and type of result (normal, scaled, etc) is created by members of + 896 * this test data set. + 897 * + 898 * The third test data set is used for exhaustive testing of final + 899 * results across the five rounding modes available for the Add + 900 * instruction. + 901 * + 902 *********************************************************************** + + + 904 *********************************************************************** + 905 * + 906 * First input test data set, to test operations using non-finite or + 907 * zero inputs. Member values chosen to validate Figure 19-13 on page + 908 * 19-16 of SA22-7832-10. Each value in this table is tested against + 909 * every other value in the table. Ten entries means 100 result sets. + 910 * + 911 *********************************************************************** + + +00000000000008B8 913 SBFPNFIN DS 0F Inputs for short BFP non-finite tests +00000000000008B8 FF800000 914 DC X'FF800000' -inf +00000000000008BC C0000000 915 DC X'C0000000' -2.0 +00000000000008C0 80010000 916 DC X'80010000' -Dnice +00000000000008C4 80000000 917 DC X'80000000' -0 +00000000000008C8 00000000 918 DC X'00000000' +0 +00000000000008CC 00010000 919 DC X'00010000' -Dnice +00000000000008D0 40000000 920 DC X'40000000' +2.0 +00000000000008D4 7F800000 921 DC X'7F800000' +inf +00000000000008D8 FFCB0000 922 DC X'FFCB0000' -QNaN +00000000000008DC 7F8A0000 923 DC X'7F8A0000' +SNaN + 000000000000000A 0000000000000001 924 SBFPNFCT EQU (*-SBFPNFIN)/4 Count of short BFP in list + + + + 926 *********************************************************************** + 927 * + 928 * Second input test data set. These are finite pairs intended to + 929 * trigger overflow, underflow, and inexact exceptions. Each pair is + 930 * added twice, once non-trappable and once trappable. Trappable + 931 * overflow or underflow yields a scaled result. Trappable inexact + 932 * will show whether the Incremented DXC code is returned. + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 27 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 933 * + 934 * The following test cases are required: + 935 * 1. Overflow + 936 * 2. Underflow - normal inputs + 937 * 3. Underflow - subnormal inputs + 938 * 4. Normal - from subnormal inputs + 939 * 5. Inexact - incremented + 940 * 6. Inexact - truncated + 941 * + 942 *********************************************************************** + + +00000000000008E0 944 SBFPIN DS 0F Inputs for short BFP finite tests + 945 * + 946 * Overflow on addition + 947 * +00000000000008E0 7F7FFFFF 948 DC X'7F7FFFFF' +Nmax +00000000000008E4 7F7FFFFF 949 DC X'7F7FFFFF' +Nmax + 950 * + 951 * Underflow from sum of normals. We will add a small normal to a + 952 * negative smaller normal to generate a subnormal. + 953 * +00000000000008E8 00FFFFFF 954 DC X'00FFFFFF' Very small normal number +00000000000008EC 80800000 955 DC X'80800000' Smaller normal negative + 956 * + 957 * Underflow from sum of subnormals. We will add two subnormals. + 958 * +00000000000008F0 00040000 959 DC X'00040000' Subnormal, < +Dmax +00000000000008F4 00000F0F 960 DC X'00000F0F' Smaller subnormal + 961 * + 962 * Normal result from sum of subnormals. We will add two subnormals. + 963 * The result will be greater than +Nmin + 964 * +00000000000008F8 007FFFFF 965 DC X'007FFFFF' +Dmax +00000000000008FC 00000001 966 DC X'00000001' +Dmin, result will be +Nmin + 967 * + 968 * Add a value to 1.0 such that the added digits are to the right of + 969 * the right-most bit in the stored significand. The result will be + 970 * inexact, and incremented will be determined by the value of the + 971 * bits in the addend. + 972 * +0000000000000900 3F800000 973 DC X'3F800000' Augend +1, aka 1.0b0 +0000000000000904 33F80000 974 DC X'33F80000' Addend 1.1111b-24 + 975 * ..Above addend is 1.154839992523193359375E-7 + 976 * ..nearest is away from zero, incremented. + 977 * +0000000000000908 3F800000 978 DC X'3F800000' Augend +1, aka 1.0b0 +000000000000090C 33780000 979 DC X'33780000' Addend 1.1111b-25 + 980 * ..Above addend is 5.774199962615966796875E-8 + 981 * ..nearest is toward zero, truncated + 982 * + 0000000000000006 0000000000000001 983 SBFPCT EQU (*-SBFPIN)/4/2 Count of short BFP in list + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 28 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + + + + 985 *********************************************************************** + 986 * + 987 * Third input test data set. These are finite pairs intended to + 988 * test all combinations of rounding mode for the sum and the + 989 * remainder. Values are chosen to create a requirement to round + 990 * to the target precision after the computation and to generate + 991 * varying results depending on the rounding mode in the FPCR. + 992 * + 993 * The result set will have cases that represent each of the following + 994 * + 995 * 1. Positive, nearest magnitude is toward zero. + 996 * 2. Negative, nearest magnitude is toward zero. + 997 * 3. Positive, nearest magnitude is away from zero. + 998 * 4. Negative, nearest magnitude is away from zero. + 999 * 5. Positive, tie, nearest even has greater magnitude + 1000 * 6. Negative, tie, nearest even has greater magnitude + 1001 * 7. Positive, tie, nearest even has lower magnitude + 1002 * 8. Negative, tie, nearest even has lower magnitude + 1003 * + 1004 * Round For Shorter precision correctness can be determined from the + 1005 * above test cases. + 1006 * + 1007 *********************************************************************** + + +0000000000000910 1009 SBFPINRM DS 0F Inputs for short BFP rounding testing + 1010 * + 1011 * Add a value to 1.0 such that the added digits are to the right of + 1012 * the right-most bit in the stored significand. The result will be + 1013 * inexact, and incremented will be determined by the value of the + 1014 * bits in the addend. + 1015 * +0000000000000910 3F800000 1016 DC X'3F800000' Augend +1, aka +1.0b0 +0000000000000914 337E0000 1017 DC X'337E0000' Addend +1.111111b-25 +0000000000000918 BF800000 1018 DC X'BF800000' Augend -1, aka -1.0b0 +000000000000091C B37E0000 1019 DC X'B37E0000' Addend -1.111111b-25 + 1020 * ..Above addend is 5.91389834880828857421875E-8 + 1021 * ..nearest is toward zero, truncated + 1022 * +0000000000000920 3F800000 1023 DC X'3F800000' Augend +1, aka 1.0b0 +0000000000000924 33FF0000 1024 DC X'33FF0000' Addend +1.1111111b-24 +0000000000000928 BF800000 1025 DC X'BF800000' Augend -1, aka -1.0b0 +000000000000092C B3FF0000 1026 DC X'B3FF0000' Addend -1.1111111b-24 + 1027 * ..Above addend is 1.187436282634735107421875E-7 + 1028 * ..nearest is away from zero, incremented. + 1029 * +0000000000000930 3F800000 1030 DC X'3F800000' Augend +1, aka +1.0b0 +0000000000000934 33800000 1031 DC X'33800000' Addend +1.0b-24 +0000000000000938 BF800000 1032 DC X'BF800000' Augend -1, aka -1.0b0 + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 29 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +000000000000093C B3800000 1033 DC X'B3800000' Addend -1.0b-24 + 1034 * ..Above addend is 5.9604644775390625E-8 + 1035 * ..nearest is a tie, nearest even has lower magnitude + 1036 * +0000000000000940 3F800000 1037 DC X'3F800000' Augend +1, aka +1.0b0 +0000000000000944 34400000 1038 DC X'34400000' Addend +1.1b-23 +0000000000000948 BF800000 1039 DC X'BF800000' Augend -1, aka -1.0b0 +000000000000094C B4400000 1040 DC X'B4400000' Addend -1.1b-23 + 1041 * ..Above addend is 1.78813934326171875E-7 + 1042 * ..nearest is a tie, nearest even has greater magnitude + 0000000000000008 0000000000000001 1043 SBFPRMCT EQU (*-SBFPINRM)/4/2 Count of short BFP rounding tests + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 30 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1045 *********************************************************************** + 1046 * + 1047 * Long BFP test data sets for Add testing. + 1048 * + 1049 * The first test data set is used for tests of basic functionality, + 1050 * NaN propagation, and results from operations involving other than + 1051 * finite numbers. + 1052 * + 1053 * The second test data set is used for testing boundary conditions + 1054 * using two finite non-zero values. Each possible condition code + 1055 * and type of result (normal, scaled, etc) is created by members of + 1056 * this test data set. + 1057 * + 1058 * The third test data set is used for exhaustive testing of final + 1059 * results across the five rounding modes available for the Add + 1060 * instruction. + 1061 * + 1062 *********************************************************************** + + + 1064 *********************************************************************** + 1065 * + 1066 * First input test data set, to test operations using non-finite or + 1067 * zero inputs. Member values chosen to validate Figure 19-13 on page + 1068 * 19-16 of SA22-7832-10. Each value in this table is tested against + 1069 * every other value in the table. Ten entries means 100 result sets. + 1070 * + 1071 *********************************************************************** + + +0000000000000950 1073 LBFPNFIN DS 0F Inputs for long BFP testing +0000000000000950 FFF00000 00000000 1074 DC X'FFF0000000000000' -inf +0000000000000958 C0000000 00000000 1075 DC X'C000000000000000' -2.0 +0000000000000960 80010000 00000000 1076 DC X'8001000000000000' -Dnice +0000000000000968 80000000 00000000 1077 DC X'8000000000000000' -0 +0000000000000970 00000000 00000000 1078 DC X'0000000000000000' +0 +0000000000000978 00010000 00000000 1079 DC X'0001000000000000' +Dnice +0000000000000980 40000000 00000000 1080 DC X'4000000000000000' +2.0 +0000000000000988 7FF00000 00000000 1081 DC X'7FF0000000000000' +inf +0000000000000990 FFF8B000 00000000 1082 DC X'FFF8B00000000000' -QNaN +0000000000000998 7FF0A000 00000000 1083 DC X'7FF0A00000000000' +SNaN + 000000000000000A 0000000000000001 1084 LBFPNFCT EQU (*-LBFPNFIN)/8 Count of long BFP in list + + + + 1086 *********************************************************************** + 1087 * + 1088 * Second input test data set. These are finite pairs intended to + 1089 * trigger overflow, underflow, and inexact exceptions. Each pair is + 1090 * added twice, once non-trappable and once trappable. Trappable + 1091 * overflow or underflow yields a scaled result. Trappable inexact + 1092 * will show whether the Incremented DXC code is returned. + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 31 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1093 * + 1094 * The following test cases are required: + 1095 * 1. Overflow + 1096 * 2. Underflow - normal inputs + 1097 * 3. Underflow - subnormal inputs + 1098 * 4. Normal - from subnormal inputs + 1099 * 5. Inexact - incremented + 1100 * 6. Inexact - truncated + 1101 * + 1102 *********************************************************************** + + +00000000000009A0 1104 LBFPIN DS 0D Inputs for long BFP finite tests + 1105 * + 1106 * Overflow on addition + 1107 * +00000000000009A0 7FFFFFFF FFFFFFFF 1108 DC X'7FFFFFFFFFFFFFFF' +Nmax +00000000000009A8 7FFFFFFF FFFFFFFF 1109 DC X'7FFFFFFFFFFFFFFF' +Nmax + 1110 * + 1111 * Underflow from sum of normals. We will add a small normal to a + 1112 * negative smaller normal to generate a subnormal. + 1113 * +00000000000009B0 001FFFFF FFFFFFFF 1114 DC X'001FFFFFFFFFFFFF' Very small normal number +00000000000009B8 80100000 00000000 1115 DC X'8010000000000000' Smaller normal negative + 1116 * + 1117 * Underflow from sum of subnormals. We will add two subnormals. + 1118 * +00000000000009C0 00080000 00000000 1119 DC X'0008000000000000' Subnormal, < +Dmax +00000000000009C8 0000F0F0 00000000 1120 DC X'0000F0F000000000' Smaller subnormal + 1121 * + 1122 * Normal result from sum of subnormals. We will add two subnormals. + 1123 * The result will be greater than +Nmin + 1124 * +00000000000009D0 000FFFFF FFFFFFFF 1125 DC X'000FFFFFFFFFFFFF' +Dmax +00000000000009D8 00000000 00000001 1126 DC X'0000000000000001' +Dmin, result will be +Nmin + 1127 * + 1128 * Add a value to 1.0 such that the added digits are to the right of + 1129 * the right-most bit in the stored significand. The result will be + 1130 * inexact, and incremented will be determined by the value of the + 1131 * bits in the addend. + 1132 * +00000000000009E0 3FF00000 00000000 1133 DC X'3FF0000000000000' Augend +1, aka 1.0b0 +00000000000009E8 3CAF0000 00000000 1134 DC X'3CAF000000000000' Addend 1.1111b-53 + 1135 * ..Above addend is 2.15105711021124079707078635692596435546875E-16 + 1136 * ..nearest is away from zero, incremented. + 1137 * +00000000000009F0 3FF00000 00000000 1138 DC X'3FF0000000000000' Augend +1, aka 1.0b0 +00000000000009F8 3C9F0000 00000000 1139 DC X'3C9F000000000000' Addend 1.1111b-54 + 1140 * ..Above addend is 1.075528555105620398535393178462982177734375E-16 + 1141 * ..nearest is toward zero, truncated. + 1142 * + 0000000000000006 0000000000000001 1143 LBFPCT EQU (*-LBFPIN)/8/2 Count of long BFP in list + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 32 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + + + + 1145 *********************************************************************** + 1146 * + 1147 * Third input test data set. These are finite pairs intended to + 1148 * test all combinations of rounding mode for the sum and the + 1149 * remainder. Values are chosen to create a requirement to round + 1150 * to the target precision after the computation and to generate + 1151 * varying results depending on the rounding mode in the FPCR. + 1152 * + 1153 * The result set will have cases that represent each of the following + 1154 * + 1155 * 1. Positive, nearest magnitude is toward zero. + 1156 * 2. Negative, nearest magnitude is toward zero. + 1157 * 3. Positive, nearest magnitude is away from zero. + 1158 * 4. Negative, nearest magnitude is away from zero. + 1159 * 5. Positive, tie, nearest even has greater magnitude + 1160 * 6. Negative, tie, nearest even has greater magnitude + 1161 * 7. Positive, tie, nearest even has lower magnitude + 1162 * 8. Negative, tie, nearest even has lower magnitude + 1163 * + 1164 * Round For Shorter precision correctness can be determined from the + 1165 * above test cases. + 1166 * + 1167 *********************************************************************** + + +0000000000000A00 1169 LBFPINRM DS 0F + 1170 * + 1171 * Add a value to 1.0 such that the added digits are to the right of + 1172 * the right-most bit in the stored significand. The result will be + 1173 * inexact, and incremented will be determined by the value of the + 1174 * bits in the addend. + 1175 * +0000000000000A00 3FF00000 00000000 1176 DC X'3FF0000000000000' Augend +1, aka +1.0b0 +0000000000000A08 3C9FC000 00000000 1177 DC X'3C9FC00000000000' Addend +1.111111b-54 +0000000000000A10 BFF00000 00000000 1178 DC X'BFF0000000000000' Augend -1, aka -1.0b0 +0000000000000A18 BC9FC000 00000000 1179 DC X'BC9FC00000000000' Addend -1.111111b-54 + 1180 * ..Above addend is 1.10154940724527250495157204568386077880859375E-16 + 1181 * ..nearest is toward zero, truncated. + 1182 * +0000000000000A20 3FF00000 00000000 1183 DC X'3FF0000000000000' Augend +1, aka +1.0b0 +0000000000000A28 3CAFE000 00000000 1184 DC X'3CAFE00000000000' Addend +1.1111111b-53 +0000000000000A30 BFF00000 00000000 1185 DC X'BFF0000000000000' Augend -1, aka -1.0b0 +0000000000000A38 BCAFE000 00000000 1186 DC X'BCAFE00000000000' Addend -1.1111111b-53 + 1187 * ..Above addend is 2.21177243187042904537520371377468109130859375E-16 + 1188 * ..nearest is away from zero, incremented. + 1189 * +0000000000000A40 3FF00000 00000000 1190 DC X'3FF0000000000000' Augend +1, aka +1.0b0 +0000000000000A48 3CA00000 00000000 1191 DC X'3CA0000000000000' Addend +1.0b-53 +0000000000000A50 BFF00000 00000000 1192 DC X'BFF0000000000000' Augend -1, aka -1.0b0 + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 33 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000A58 BCA00000 00000000 1193 DC X'BCA0000000000000' Addend -1.0b-53 + 1194 * ..Above addend is 1.1102230246251565404236316680908203125E-16 + 1195 * ..nearest is a tie, nearest even has lower magnitude + 1196 * +0000000000000A60 3FF00000 00000000 1197 DC X'3FF0000000000000' Augend +1, aka +1.0b0 +0000000000000A68 3CB80000 00000000 1198 DC X'3CB8000000000000' Addend +1.1b-52 +0000000000000A70 BFF00000 00000000 1199 DC X'BFF0000000000000' Augend -1, aka -1.0b0 +0000000000000A78 BCB80000 00000000 1200 DC X'BCB8000000000000' Addend -1.1b-52 + 1201 * ..Above addend is 3.3306690738754696212708950042724609375E-16 + 1202 * ..nearest is a tie, nearest even has greater magnitude + 1203 * + 1204 * + 0000000000000008 0000000000000001 1205 LBFPRMCT EQU (*-LBFPINRM)/8/2 Count of long BFP rounding tests + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 34 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1207 *********************************************************************** + 1208 * + 1209 * Extended BFP test data sets for Add testing. + 1210 * + 1211 * The first test data set is used for tests of basic functionality, + 1212 * NaN propagation, and results from operations involving other than + 1213 * finite numbers. + 1214 * + 1215 * The second test data set is used for testing boundary conditions + 1216 * using two finite non-zero values. Each possible condition code + 1217 * and type of result (normal, scaled, etc) is created by members of + 1218 * this test data set. + 1219 * + 1220 * The third test data set is used for exhaustive testing of final + 1221 * results across the five rounding modes available for the Add + 1222 * instruction. + 1223 * + 1224 *********************************************************************** + + + 1226 *********************************************************************** + 1227 * + 1228 * First input test data set, to test operations using non-finite or + 1229 * zero inputs. Member values chosen to validate Figure 19-13 on page + 1230 * 19-16 of SA22-7832-10. Each value in this table is tested against + 1231 * every other value in the table. Ten entries means 100 result sets. + 1232 * + 1233 *********************************************************************** + + +0000000000000A80 1235 XBFPNFIN DS 0F Inputs for extended BFP testing +0000000000000A80 FFFF0000 00000000 1236 DC X'FFFF0000000000000000000000000000' -inf +0000000000000A90 C0000000 00000000 1237 DC X'C0000000000000000000000000000000' -2.0 +0000000000000AA0 80001000 00000000 1238 DC X'80001000000000000000000000000000' -Dnice +0000000000000AB0 80000000 00000000 1239 DC X'80000000000000000000000000000000' -0 +0000000000000AC0 00000000 00000000 1240 DC X'00000000000000000000000000000000' +0 +0000000000000AD0 00001000 00000000 1241 DC X'00001000000000000000000000000000' +Dnice +0000000000000AE0 40000000 00000000 1242 DC X'40000000000000000000000000000000' +2.0 +0000000000000AF0 7FFF0000 00000000 1243 DC X'7FFF0000000000000000000000000000' +inf +0000000000000B00 FFFF8B00 00000000 1244 DC X'FFFF8B00000000000000000000000000' -QNaN +0000000000000B10 7FFF0A00 00000000 1245 DC X'7FFF0A00000000000000000000000000' +SNaN + 000000000000000A 0000000000000001 1246 XBFPNFCT EQU (*-XBFPNFIN)/16 Count of extended BFP in list + + + + 1248 *********************************************************************** + 1249 * + 1250 * Second input test data set. These are finite pairs intended to + 1251 * trigger overflow, underflow, and inexact exceptions. Each pair is + 1252 * added twice, once non-trappable and once trappable. Trappable + 1253 * overflow or underflow yields a scaled result. Trappable inexact + 1254 * will show whether the Incremented DXC code is returned. + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 35 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1255 * + 1256 * The following test cases are required: + 1257 * The following test cases are required: + 1258 * 1. Overflow + 1259 * 2. Underflow - normal inputs + 1260 * 3. Underflow - subnormal inputs + 1261 * 4. Normal - from subnormal inputs + 1262 * 5. Inexact - incremented + 1263 * 6. Inexact - truncated + 1264 * + 1265 *********************************************************************** + + +0000000000000B20 1267 XBFPIN DS 0F Inputs for extended BFP finite tests + 1268 * + 1269 * Overflow on addition + 1270 * +0000000000000B20 7FFFFFFF FFFFFFFF 1271 DC X'7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF' +Nmax +0000000000000B30 7FFFFFFF FFFFFFFF 1272 DC X'7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF' +Nmax + 1273 * + 1274 * Underflow from sum of normals. We will add a small normal to a + 1275 * negative smaller normal to generate a subnormal. + 1276 * +0000000000000B40 0001FFFF FFFFFFFF 1277 DC X'0001FFFFFFFFFFFFFFFFFFFFFFFFFFFF' Very small normal +0000000000000B50 80010000 00000000 1278 DC X'80010000000000000000000000000000' Smaller normal + 1279 * + 1280 * Underflow from sum of subnormals. We will add two subnormals. + 1281 * +0000000000000B60 00008000 00000000 1282 DC X'00008000000000000000000000000000' Subnormal, < +Dmax +0000000000000B70 00000F0F 00000000 1283 DC X'00000F0F000000000000000000000000' Smaller subnormal + 1284 * + 1285 * Normal result from sum of subnormals. We will add two subnormals. + 1286 * The result will be greater than +Nmin + 1287 * +0000000000000B80 0000FFFF FFFFFFFF 1288 DC X'0000FFFFFFFFFFFFFFFFFFFFFFFFFFFF' +Dmax +0000000000000B90 00000000 00000000 1289 DC X'00000000000000000000000000000001' +Dmin + 1290 * ...result will be +Nmin + 1291 * + 1292 * Add a value to 1.0 such that the added digits are to the right of + 1293 * the right-most bit in the stored significand. The result will be + 1294 * inexact, and incremented will be determined by the value of the + 1295 * bits in the addend. + 1296 * +0000000000000BA0 3FFF0000 00000000 1297 DC X'3FFF0000000000000000000000000000' +1, aka 1.0b0 +0000000000000BB0 3F8EF000 00000000 1298 DC X'3F8EF000000000000000000000000000' 1.1111b-113 + 1299 * ..Above addend is 1.865744633625134732647978631879148339833785... + 1300 * ...97170865731413869070820510387420654296875E-34 + 1301 * ..nearest is away from zero, incremented. + 1302 * +0000000000000BC0 3FFF0000 00000000 1303 DC X'3FFF0000000000000000000000000000' +1, aka 1.0b0 +0000000000000BD0 3F8DF000 00000000 1304 DC X'3F8DF000000000000000000000000000' 1.1111b-114 + 1305 * ..Above addend is 9.328723168125673663239893159395741699168929... + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 36 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1306 * ...85854328657069345354102551937103271484375E-35 + 1307 * ..nearest is toward zero, truncated + 1308 * + 0000000000000006 0000000000000001 1309 XBFPCT EQU (*-XBFPIN)/16/2 Count of extended BFP in list + + + + 1311 *********************************************************************** + 1312 * + 1313 * Third input test data set. These are finite pairs intended to + 1314 * test all combinations of rounding mode for the sum and the + 1315 * remainder. Values are chosen to create a requirement to round + 1316 * to the target precision after the computation and to generate + 1317 * varying results depending on the rounding mode in the FPCR. + 1318 * + 1319 * The result set will have cases that represent each of the following + 1320 * + 1321 * 1. Positive, nearest magnitude is toward zero. + 1322 * 2. Negative, nearest magnitude is toward zero. + 1323 * 3. Positive, nearest magnitude is away from zero. + 1324 * 4. Negative, nearest magnitude is away from zero. + 1325 * 5. Positive, tie, nearest even has greater magnitude + 1326 * 6. Negative, tie, nearest even has greater magnitude + 1327 * 7. Positive, tie, nearest even has lower magnitude + 1328 * 8. Negative, tie, nearest even has lower magnitude + 1329 * + 1330 * Round For Shorter precision correctness can be determined from the + 1331 * above test cases. + 1332 * + 1333 *********************************************************************** + + +0000000000000BE0 1335 XBFPINRM DS 0D + 1336 * + 1337 * Add a value to 1.0 such that the added digits are to the right of + 1338 * the right-most bit in the stored significand. The result will be + 1339 * inexact, and incremented will be determined by the value of the + 1340 * bits in the addend. + 1341 * +0000000000000BE0 3FFF0000 00000000 1342 DC X'3FFF0000000000000000000000000000' +1, aka +1.0b0 +0000000000000BF0 3F8DFC00 00000000 1343 DC X'3F8DFC00000000000000000000000000' +1.111111b-114 +0000000000000C00 BFFF0000 00000000 1344 DC X'BFFF0000000000000000000000000000' -1, aka -1.0b0 +0000000000000C10 BF8DFC00 00000000 1345 DC X'BF8DFC00000000000000000000000000' -1.111111b-114 + 1346 * ..Above addend is 9.554418083483552864769890574542412869310113... + 1347 * ...6454435273748231338686309754848480224609375E-35 + 1348 * ..nearest is toward zero + 1349 * +0000000000000C20 3FFF0000 00000000 1350 DC X'3FFF0000000000000000000000000000' +1, aka +1.0b0 +0000000000000C30 3F8EFE00 00000000 1351 DC X'3F8EFE00000000000000000000000000' +1.1111111b-113 +0000000000000C40 BFFF0000 00000000 1352 DC X'BFFF0000000000000000000000000000' -1, aka -1.0b0 +0000000000000C50 BF8EFE00 00000000 1353 DC X'BF8EFE00000000000000000000000000' -1.1111111b-113 + 1354 * ..Above addend is 1.918406780541973213004978028746704946200062... + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 37 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1355 * ...18865204683510228278464637696743011474609375E-34 + 1356 * ..nearest is away from zero + 1357 * +0000000000000C60 3FFF0000 00000000 1358 DC X'3FFF0000000000000000000000000000' +1, aka +1.0b0 +0000000000000C70 3F8E0000 00000000 1359 DC X'3F8E0000000000000000000000000000' +1.0000b-113 +0000000000000C80 BFFF0000 00000000 1360 DC X'BFFF0000000000000000000000000000' -1, aka -1.0b0 +0000000000000C90 BF8E0000 00000000 1361 DC X'BF8E0000000000000000000000000000' -1.0000b-113 + 1362 * ..Above addend is 9.629649721936179265279889712924636592690508... + 1363 * ...241076940976199693977832794189453125E-35 + 1364 * ..nearest is a tie, nearest even has lower magnitude + 1365 * +0000000000000CA0 3FFF0000 00000000 1366 DC X'3FFF0000000000000000000000000000' +1, aka +1.0b0 +0000000000000CB0 3F8F8000 00000000 1367 DC X'3F8F8000000000000000000000000000' +1.1b-112 +0000000000000CC0 BFFF0000 00000000 1368 DC X'BFFF0000000000000000000000000000' -1, aka -1.0b0 +0000000000000CD0 BF8F8000 00000000 1369 DC X'BF8F8000000000000000000000000000' -1.1b-112 + 1370 * ..Above addend is 9.629649721936179265279889712924636592690508... + 1371 * ...241076940976199693977832794189453125E-35 + 1372 * ..nearest is a tie, nearest even has greater magnitude + 1373 * + 0000000000000008 0000000000000001 1374 XBFPRMCT EQU (*-XBFPINRM)/16/2 Count of long BFP rounding tests + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 38 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1376 * + 1377 * Locations for results + 1378 * + 0000000000001000 0000000000000001 1379 SBFPNFOT EQU STRTLABL+X'1000' Integer short non-finite BFP results + 1380 * ..room for 110 tests, 100 used + 0000000000001700 0000000000000001 1381 SBFPNFFL EQU STRTLABL+X'1700' FPCR flags and DXC from short BFP + 1382 * ..room for 110 tests, 100 used + 1383 * + 0000000000001E00 0000000000000001 1384 SBFPOUT EQU STRTLABL+X'1E00' Integer short BFP finite results + 1385 * ..room for 16 tests, 6 used + 0000000000001F00 0000000000000001 1386 SBFPFLGS EQU STRTLABL+X'1F00' FPCR flags and DXC from short BFP + 1387 * ..room for 16 tests, 6 used + 1388 * + 0000000000002000 0000000000000001 1389 SBFPRMO EQU STRTLABL+X'2000' Short BFP rounding mode test results + 1390 * ..Room for 16, 8 used. + 0000000000002300 0000000000000001 1391 SBFPRMOF EQU STRTLABL+X'2300' Short BFP rounding mode FPCR results + 1392 * ..Room for 16, 8 used. + 1393 * ..next location starts at X'2500' + 1394 * + 0000000000004000 0000000000000001 1395 LBFPNFOT EQU STRTLABL+X'4000' Integer long non-finite BFP results + 1396 * ..room for 100 tests, 100 used + 0000000000004D00 0000000000000001 1397 LBFPNFFL EQU STRTLABL+X'4D00' FPCR flags and DXC from long BFP + 1398 * ..room for 100 tests, 100 used + 1399 * + 0000000000005400 0000000000000001 1400 LBFPOUT EQU STRTLABL+X'5400' Integer long BFP finite results + 1401 * ..room for 16 tests, 6 used + 0000000000005600 0000000000000001 1402 LBFPFLGS EQU STRTLABL+X'5600' FPCR flags and DXC from long BFP + 1403 * ..room for 16 tests, 6 used + 1404 * + 0000000000005700 0000000000000001 1405 LBFPRMO EQU STRTLABL+X'5700' Long BFP rounding mode test results + 1406 * ..Room for 16, 8 used. + 0000000000005C00 0000000000000001 1407 LBFPRMOF EQU STRTLABL+X'5C00' Long BFP rounding mode FPCR results + 1408 * ..Room for 16, 8 used. + 1409 * ..next location starts at X'5E00' + 1410 * + 0000000000008000 0000000000000001 1411 XBFPNFOT EQU STRTLABL+X'8000' Integer ext'd non-finite BFP results + 1412 * ..room for 100 tests, 100 used + 0000000000008D00 0000000000000001 1413 XBFPNFFL EQU STRTLABL+X'8D00' FPCR flags and DXC from ext'd BFP + 1414 * ..room for 100 tests, 100 used + 1415 * + 0000000000009400 0000000000000001 1416 XBFPOUT EQU STRTLABL+X'9400' Extended BFP finite results + 1417 * ..room for 16 tests, 6 used + 0000000000009600 0000000000000001 1418 XBFPFLGS EQU STRTLABL+X'9600' FPCR flags and DXC from ext'd BFP + 1419 * ..room for 16 tests, 6 used + 1420 * + 0000000000009700 0000000000000001 1421 XBFPRMO EQU STRTLABL+X'9700' Ext'd BFP rounding mode test results + 1422 * ..Room for 16, 8 used. + 0000000000009C00 0000000000000001 1423 XBFPRMOF EQU STRTLABL+X'9C00' Ext'd BFP rounding mode FPCR results + 1424 * ..Room for 16, 8 used. + 1425 * ..next location starts at X'9E00' + 1426 * + 0000000000009E00 0000000000000001 1427 ENDLABL EQU STRTLABL+X'9E00' + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 39 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1428 PADCSECT ENDLABL + 1429+ MNOTE *,'asma detected; no CSECT padding performed' +0000000000000CE0 1430 END + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 40 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +BFPADD J 000000 3296 77 +CTLR0 F 000290 4 193 160 161 162 +ENDLABL U 009E00 1 1427 +FPCMCT U 000005 1 882 428 639 824 +FPCMODES C 0008B0 1 876 882 431 642 827 +FPCREGNT X 000294 4 194 293 313 360 380 433 444 505 524 571 591 644 655 716 768 + 829 +FPCREGTR X 000298 4 195 303 322 370 389 515 533 581 600 729 781 +FPR0 U 000000 1 98 +FPR1 U 000001 1 99 292 294 302 304 312 362 363 373 436 437 504 506 514 516 + 573 574 584 647 648 714 717 727 730 771 773 785 833 835 +FPR10 U 00000A 1 108 713 719 726 732 770 775 783 787 832 837 +FPR11 U 00000B 1 109 +FPR12 U 00000C 1 110 +FPR13 U 00000D 1 111 +FPR14 U 00000E 1 112 +FPR15 U 00000F 1 113 +FPR2 U 000002 1 100 +FPR3 U 000003 1 101 715 728 772 834 +FPR4 U 000004 1 102 +FPR5 U 000005 1 103 +FPR6 U 000006 1 104 +FPR7 U 000007 1 105 +FPR8 U 000008 1 106 291 294 295 301 304 305 311 314 315 321 323 324 361 363 + 364 371 373 374 381 382 383 390 391 392 435 437 438 446 + 447 448 503 506 507 513 516 517 523 525 526 532 534 535 + 572 574 575 582 584 585 592 593 594 601 602 603 646 648 + 649 657 658 659 712 717 718 725 730 731 769 773 774 782 + 785 786 831 835 836 +FPR9 U 000009 1 107 +HARDWAIT X 000280 8 191 151 +IMAGE 1 000000 3296 0 +LBFPCT U 000006 1 1143 229 +LBFPF I 000628 4 565 174 +LBFPFLGS U 005600 1 1402 232 +LBFPIN D 0009A0 8 1104 1143 230 +LBFPINRM F 000A00 4 1169 1205 236 +LBFPNF H 000572 2 492 172 +LBFPNFCT U 00000A 1 1084 223 +LBFPNFFL U 004D00 1 1397 226 +LBFPNFIN F 000950 4 1073 1084 224 +LBFPNFOT U 004000 1 1395 225 +LBFPOUT U 005400 1 1400 231 +LBFPRM I 0006CE 4 632 176 +LBFPRMCT U 000008 1 1205 235 +LBFPRMO U 005700 1 1405 237 +LBFPRMOF U 005C00 1 1407 238 +LONGF F 000340 4 228 173 +LONGNF F 000330 4 222 171 +PCINTCD H 00008E 2 128 145 +PCNOTDTA H 00020C 2 148 146 +PCOLDPSW U 000150 1 130 147 + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 41 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +PROGCHK H 000200 2 144 136 +R0 U 000000 1 79 160 162 297 298 299 307 308 309 317 318 319 326 327 328 + 366 367 368 376 377 378 385 386 387 394 395 396 440 441 + 442 450 451 452 509 510 511 519 520 521 528 529 530 537 + 538 539 577 578 579 587 588 589 596 597 598 605 606 607 + 651 652 653 661 662 663 721 722 723 734 735 736 777 778 + 779 789 790 791 839 840 841 +R1 U 000001 1 80 425 431 434 445 636 642 645 656 821 827 830 +R10 U 00000A 1 89 164 166 168 171 173 175 178 180 182 281 282 287 354 355 + 421 422 493 494 499 565 566 632 633 702 703 708 762 763 + 817 818 +R11 U 00000B 1 90 +R12 U 00000C 1 91 285 336 358 401 426 467 497 547 569 612 637 677 706 744 + 766 796 822 855 +R13 U 00000D 1 92 165 167 169 172 174 176 179 181 183 284 337 357 402 424 + 469 496 548 568 613 635 679 705 745 765 798 820 857 +R14 U 00000E 1 93 149 150 185 186 +R15 U 00000F 1 94 115 +R2 U 000002 1 81 281 283 336 354 356 401 421 423 467 493 495 547 565 567 + 612 632 634 677 702 704 744 762 764 796 817 819 855 +R3 U 000003 1 82 281 291 301 311 321 335 354 361 362 371 381 382 390 391 + 398 421 435 436 446 447 464 493 503 513 523 532 546 565 + 572 573 582 592 593 601 602 609 632 646 647 657 658 675 + 702 712 713 725 726 743 762 769 770 771 772 782 783 793 + 817 831 832 833 834 853 +R4 U 000004 1 83 287 333 499 544 708 741 +R5 U 000005 1 84 287 292 302 312 314 323 330 428 431 457 499 504 514 525 + 534 541 639 642 668 708 714 715 727 728 738 824 827 846 +R6 U 000006 1 85 289 333 501 544 710 741 +R7 U 000007 1 86 282 295 305 315 324 331 355 364 374 383 392 399 422 438 + 448 454 465 494 507 517 526 535 542 566 575 585 594 603 + 610 633 649 659 665 703 718 719 731 732 739 763 774 775 + 786 787 794 818 836 837 843 +R8 U 000008 1 87 282 296 299 306 309 316 319 325 328 332 355 365 368 375 + 378 384 387 393 396 400 422 439 442 449 452 455 466 494 + 508 511 518 521 527 530 536 539 543 566 576 579 586 589 + 595 598 604 607 611 633 650 653 660 663 666 676 703 720 + 723 733 736 740 763 776 779 788 791 795 818 838 841 844 + 854 +R9 U 000009 1 88 429 457 640 668 825 846 +RMLONGS F 000350 4 234 175 +RMSHORTS F 000320 4 216 168 +RMXTNDS F 000380 4 252 182 +SBFPCT U 000006 1 983 211 +SBFPF I 00044A 4 354 167 +SBFPFLGS U 001F00 1 1386 214 +SBFPIN F 0008E0 4 944 983 212 +SBFPINRM F 000910 4 1009 1043 218 +SBFPNF H 000390 2 280 165 +SBFPNFCT U 00000A 1 924 205 +SBFPNFFL U 001700 1 1381 208 +SBFPNFIN F 0008B8 4 913 924 206 + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 42 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +SBFPNFOT U 001000 1 1379 207 +SBFPOUT U 001E00 1 1384 213 +SBFPRM I 0004F0 4 421 169 +SBFPRMCT U 000008 1 1043 217 +SBFPRMO U 002000 1 1389 219 +SBFPRMOF U 002300 1 1391 220 +SHORTF F 000310 4 210 166 +SHORTNF F 000300 4 204 164 +START H 000214 2 159 133 +STRTLABL U 000000 1 78 127 130 132 135 143 203 1379 1381 1384 1386 1389 1391 1395 1397 + 1400 1402 1405 1407 1411 1413 1416 1418 1421 1423 1427 +WAITPSW X 000270 8 190 187 +XBFPCT U 000006 1 1309 247 +XBFPF I 0007D6 4 762 181 +XBFPFLGS U 009600 1 1418 250 +XBFPIN F 000B20 4 1267 1309 248 +XBFPINRM D 000BE0 8 1335 1374 254 +XBFPNF H 00074C 2 701 179 +XBFPNFCT U 00000A 1 1246 241 +XBFPNFFL U 008D00 1 1413 244 +XBFPNFIN F 000A80 4 1235 1246 242 +XBFPNFOT U 008000 1 1411 243 +XBFPOUT U 009400 1 1416 249 +XBFPRM I 00084C 4 817 183 +XBFPRMCT U 000008 1 1374 253 +XBFPRMO U 009700 1 1421 255 +XBFPRMOF U 009C00 1 1423 256 +XTNDF F 000370 4 246 180 +XTNDNF F 000360 4 240 178 + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 43 + + MACRO DEFN REFERENCES + +PADCSECT 52 1428 + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 44 + + DESC SYMBOL SIZE POS ADDR + +Entry: 0 + +Image IMAGE 3296 000-CDF 000-CDF + Region 3296 000-CDF 000-CDF + CSECT BFPADD 3296 000-CDF 000-CDF + ASMA Ver. 0.2.0 bfp-016-add.asm: Test IEEE Add 02 Oct 2016 09:24:30 Page 45 + + STMT FILE NAME + +1 C:\Users\srorso\Documents\GitHub\hyperion\tests\bfp-016-add.asm + + +** NO ERRORS FOUND ** + +[1429] MNOTE *,asma detected; no CSECT padding performed + \ No newline at end of file diff --git a/tests/bfp-016-add.tst b/tests/bfp-016-add.tst new file mode 100644 index 000000000..be11db2cb --- /dev/null +++ b/tests/bfp-016-add.tst @@ -0,0 +1,2100 @@ +*Testcase bfp-016-add.tst: AEBR, AEB, ADBR, ADB, AXBR + +#Testcase bfp-016-add.tst: Add tests ADD (5) +#..Test cases evaluate NaN propagation, NaN generation, operations +#..using non-finite values, trappable and non-trappable IEEE +#..exceptions, result scaling, and exhaustive rounding testing. + +sysclear +archmode esame + +# +# Following suppresses logging of program checks. This test program, as part +# of its normal operation, generates 230 program check messages that have no +# value in the validation process. (The messages, not the program checks.) +# +ostailor quiet + +loadcore "$(testpath)/bfp-016-add.core" + +runtest 1.0 + +ostailor null # restore messages for subsequent tests + + +*Compare +r 1000.10 +*Want "AEBR/AEB NF -inf/-inf" FF800000 FF800000 FF800000 FF800000 +r 1010.10 +*Want "AEBR/AEB NF -inf/-2.0" FF800000 FF800000 FF800000 FF800000 +r 1020.10 +*Want "AEBR/AEB NF -inf/-Dnice" FF800000 FF800000 FF800000 FF800000 +r 1030.10 +*Want "AEBR/AEB NF -inf/-0" FF800000 FF800000 FF800000 FF800000 +r 1040.10 +*Want "AEBR/AEB NF -inf/+0" FF800000 FF800000 FF800000 FF800000 +r 1050.10 +*Want "AEBR/AEB NF -inf/+Dnice" FF800000 FF800000 FF800000 FF800000 +r 1060.10 +*Want "AEBR/AEB NF -inf/+2.0" FF800000 FF800000 FF800000 FF800000 +r 1070.10 +*Want "AEBR/AEB NF -inf/+inf" 7FC00000 FF800000 7FC00000 FF800000 +r 1080.10 +*Want "AEBR/AEB NF -inf/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1090.10 +*Want "AEBR/AEB NF -inf/+SNaN" 7FCA0000 FF800000 7FCA0000 FF800000 +r 10A0.10 +*Want "AEBR/AEB NF -2.0/-inf" FF800000 FF800000 FF800000 FF800000 +r 10B0.10 +*Want "AEBR/AEB NF -2.0/-2.0" C0800000 C0800000 C0800000 C0800000 +r 10C0.10 +*Want "AEBR/AEB NF -2.0/-Dnice" C0000000 C0000000 C0000000 C0000000 +r 10D0.10 +*Want "AEBR/AEB NF -2.0/-0" C0000000 C0000000 C0000000 C0000000 +r 10E0.10 +*Want "AEBR/AEB NF -2.0/+0" C0000000 C0000000 C0000000 C0000000 +r 10F0.10 +*Want "AEBR/AEB NF -2.0/+Dnice" C0000000 C0000000 C0000000 C0000000 +r 1100.10 +*Want "AEBR/AEB NF -2.0/+2.0" 00000000 00000000 00000000 00000000 +r 1110.10 +*Want "AEBR/AEB NF -2.0/+inf" 7F800000 7F800000 7F800000 7F800000 +r 1120.10 +*Want "AEBR/AEB NF -2.0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1130.10 +*Want "AEBR/AEB NF -2.0/+SNaN" 7FCA0000 C0000000 7FCA0000 C0000000 +r 1140.10 +*Want "AEBR/AEB NF -Dnice/-inf" FF800000 FF800000 FF800000 FF800000 +r 1150.10 +*Want "AEBR/AEB NF -Dnice/-2.0" C0000000 C0000000 C0000000 C0000000 +r 1160.10 +*Want "AEBR/AEB NF -Dnice/-Dnice" 80020000 DD800000 80020000 DD800000 +r 1170.10 +*Want "AEBR/AEB NF -Dnice/-0" 80010000 DD000000 80010000 DD000000 +r 1180.10 +*Want "AEBR/AEB NF -Dnice/+0" 80010000 DD000000 80010000 DD000000 +r 1190.10 +*Want "AEBR/AEB NF -Dnice/+Dnice" 00000000 00000000 00000000 00000000 +r 11A0.10 +*Want "AEBR/AEB NF -Dnice/+2.0" 40000000 40000000 40000000 40000000 +r 11B0.10 +*Want "AEBR/AEB NF -Dnice/+inf" 7F800000 7F800000 7F800000 7F800000 +r 11C0.10 +*Want "AEBR/AEB NF -Dnice/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 11D0.10 +*Want "AEBR/AEB NF -Dnice/+SNaN" 7FCA0000 80010000 7FCA0000 80010000 +r 11E0.10 +*Want "AEBR/AEB NF -0/-inf" FF800000 FF800000 FF800000 FF800000 +r 11F0.10 +*Want "AEBR/AEB NF -0/-2.0" C0000000 C0000000 C0000000 C0000000 +r 1200.10 +*Want "AEBR/AEB NF -0/-Dnice" 80010000 DD000000 80010000 DD000000 +r 1210.10 +*Want "AEBR/AEB NF -0/-0" 80000000 80000000 80000000 80000000 +r 1220.10 +*Want "AEBR/AEB NF -0/+0" 00000000 00000000 00000000 00000000 +r 1230.10 +*Want "AEBR/AEB NF -0/+Dnice" 00010000 5D000000 00010000 5D000000 +r 1240.10 +*Want "AEBR/AEB NF -0/+2.0" 40000000 40000000 40000000 40000000 +r 1250.10 +*Want "AEBR/AEB NF -0/+inf" 7F800000 7F800000 7F800000 7F800000 +r 1260.10 +*Want "AEBR/AEB NF -0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1270.10 +*Want "AEBR/AEB NF -0/+SNaN" 7FCA0000 80000000 7FCA0000 80000000 +r 1280.10 +*Want "AEBR/AEB NF +0/-inf" FF800000 FF800000 FF800000 FF800000 +r 1290.10 +*Want "AEBR/AEB NF +0/-2.0" C0000000 C0000000 C0000000 C0000000 +r 12A0.10 +*Want "AEBR/AEB NF +0/-Dnice" 80010000 DD000000 80010000 DD000000 +r 12B0.10 +*Want "AEBR/AEB NF +0/-0" 00000000 00000000 00000000 00000000 +r 12C0.10 +*Want "AEBR/AEB NF +0/+0" 00000000 00000000 00000000 00000000 +r 12D0.10 +*Want "AEBR/AEB NF +0/+Dnice" 00010000 5D000000 00010000 5D000000 +r 12E0.10 +*Want "AEBR/AEB NF +0/+2.0" 40000000 40000000 40000000 40000000 +r 12F0.10 +*Want "AEBR/AEB NF +0/+inf" 7F800000 7F800000 7F800000 7F800000 +r 1300.10 +*Want "AEBR/AEB NF +0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1310.10 +*Want "AEBR/AEB NF +0/+SNaN" 7FCA0000 00000000 7FCA0000 00000000 +r 1320.10 +*Want "AEBR/AEB NF +Dnice/-inf" FF800000 FF800000 FF800000 FF800000 +r 1330.10 +*Want "AEBR/AEB NF +Dnice/-2.0" C0000000 C0000000 C0000000 C0000000 +r 1340.10 +*Want "AEBR/AEB NF +Dnice/-Dnice" 00000000 00000000 00000000 00000000 +r 1350.10 +*Want "AEBR/AEB NF +Dnice/-0" 00010000 5D000000 00010000 5D000000 +r 1360.10 +*Want "AEBR/AEB NF +Dnice/+0" 00010000 5D000000 00010000 5D000000 +r 1370.10 +*Want "AEBR/AEB NF +Dnice/+Dnice" 00020000 5D800000 00020000 5D800000 +r 1380.10 +*Want "AEBR/AEB NF +Dnice/+2.0" 40000000 40000000 40000000 40000000 +r 1390.10 +*Want "AEBR/AEB NF +Dnice/+inf" 7F800000 7F800000 7F800000 7F800000 +r 13A0.10 +*Want "AEBR/AEB NF +Dnice/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 13B0.10 +*Want "AEBR/AEB NF +Dnice/+SNaN" 7FCA0000 00010000 7FCA0000 00010000 +r 13C0.10 +*Want "AEBR/AEB NF +2.0/-inf" FF800000 FF800000 FF800000 FF800000 +r 13D0.10 +*Want "AEBR/AEB NF +2.0/-2.0" 00000000 00000000 00000000 00000000 +r 13E0.10 +*Want "AEBR/AEB NF +2.0/-Dnice" 40000000 40000000 40000000 40000000 +r 13F0.10 +*Want "AEBR/AEB NF +2.0/-0" 40000000 40000000 40000000 40000000 +r 1400.10 +*Want "AEBR/AEB NF +2.0/+0" 40000000 40000000 40000000 40000000 +r 1410.10 +*Want "AEBR/AEB NF +2.0/+Dnice" 40000000 40000000 40000000 40000000 +r 1420.10 +*Want "AEBR/AEB NF +2.0/+2.0" 40800000 40800000 40800000 40800000 +r 1430.10 +*Want "AEBR/AEB NF +2.0/+inf" 7F800000 7F800000 7F800000 7F800000 +r 1440.10 +*Want "AEBR/AEB NF +2.0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1450.10 +*Want "AEBR/AEB NF +2.0/+SNaN" 7FCA0000 40000000 7FCA0000 40000000 +r 1460.10 +*Want "AEBR/AEB NF +inf/-inf" 7FC00000 7F800000 7FC00000 7F800000 +r 1470.10 +*Want "AEBR/AEB NF +inf/-2.0" 7F800000 7F800000 7F800000 7F800000 +r 1480.10 +*Want "AEBR/AEB NF +inf/-Dnice" 7F800000 7F800000 7F800000 7F800000 +r 1490.10 +*Want "AEBR/AEB NF +inf/-0" 7F800000 7F800000 7F800000 7F800000 +r 14A0.10 +*Want "AEBR/AEB NF +inf/+0" 7F800000 7F800000 7F800000 7F800000 +r 14B0.10 +*Want "AEBR/AEB NF +inf/+Dnice" 7F800000 7F800000 7F800000 7F800000 +r 14C0.10 +*Want "AEBR/AEB NF +inf/+2.0" 7F800000 7F800000 7F800000 7F800000 +r 14D0.10 +*Want "AEBR/AEB NF +inf/+inf" 7F800000 7F800000 7F800000 7F800000 +r 14E0.10 +*Want "AEBR/AEB NF +inf/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 14F0.10 +*Want "AEBR/AEB NF +inf/+SNaN" 7FCA0000 7F800000 7FCA0000 7F800000 +r 1500.10 +*Want "AEBR/AEB NF -QNaN/-inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1510.10 +*Want "AEBR/AEB NF -QNaN/-2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1520.10 +*Want "AEBR/AEB NF -QNaN/-Dnice" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1530.10 +*Want "AEBR/AEB NF -QNaN/-0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1540.10 +*Want "AEBR/AEB NF -QNaN/+0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1550.10 +*Want "AEBR/AEB NF -QNaN/+Dnice" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1560.10 +*Want "AEBR/AEB NF -QNaN/+2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1570.10 +*Want "AEBR/AEB NF -QNaN/+inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1580.10 +*Want "AEBR/AEB NF -QNaN/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1590.10 +*Want "AEBR/AEB NF -QNaN/+SNaN" 7FCA0000 FFCB0000 7FCA0000 FFCB0000 +r 15A0.10 +*Want "AEBR/AEB NF +SNaN/-inf" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 15B0.10 +*Want "AEBR/AEB NF +SNaN/-2.0" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 15C0.10 +*Want "AEBR/AEB NF +SNaN/-Dnice" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 15D0.10 +*Want "AEBR/AEB NF +SNaN/-0" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 15E0.10 +*Want "AEBR/AEB NF +SNaN/+0" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 15F0.10 +*Want "AEBR/AEB NF +SNaN/+Dnice" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1600.10 +*Want "AEBR/AEB NF +SNaN/+2.0" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1610.10 +*Want "AEBR/AEB NF +SNaN/+inf" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1620.10 +*Want "AEBR/AEB NF +SNaN/-QNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1630.10 +*Want "AEBR/AEB NF +SNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 + + +r 1700.10 +*Want "AEBR/AEB NF -inf/-inf FPCR" 00000001 F8000001 00000001 F8000001 +r 1710.10 +*Want "AEBR/AEB NF -inf/-2.0 FPCR" 00000001 F8000001 00000001 F8000001 +r 1720.10 +*Want "AEBR/AEB NF -inf/-Dnice FPCR" 00000001 F8000001 00000001 F8000001 +r 1730.10 +*Want "AEBR/AEB NF -inf/-0 FPCR" 00000001 F8000001 00000001 F8000001 +r 1740.10 +*Want "AEBR/AEB NF -inf/+0 FPCR" 00000001 F8000001 00000001 F8000001 +r 1750.10 +*Want "AEBR/AEB NF -inf/+Dnice FPCR" 00000001 F8000001 00000001 F8000001 +r 1760.10 +*Want "AEBR/AEB NF -inf/+2.0 FPCR" 00000001 F8000001 00000001 F8000001 +r 1770.10 +*Want "AEBR/AEB NF -inf/+inf FPCR" 00800003 F8008003 00800003 F8008003 +r 1780.10 +*Want "AEBR/AEB NF -inf/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 1790.10 +*Want "AEBR/AEB NF -inf/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 17A0.10 +*Want "AEBR/AEB NF -2.0/-inf FPCR" 00000001 F8000001 00000001 F8000001 +r 17B0.10 +*Want "AEBR/AEB NF -2.0/-2.0 FPCR" 00000001 F8000001 00000001 F8000001 +r 17C0.10 +*Want "AEBR/AEB NF -2.0/-Dnice FPCR" 00080001 F8000801 00080001 F8000801 +r 17D0.10 +*Want "AEBR/AEB NF -2.0/-0 FPCR" 00000001 F8000001 00000001 F8000001 +r 17E0.10 +*Want "AEBR/AEB NF -2.0/+0 FPCR" 00000001 F8000001 00000001 F8000001 +r 17F0.10 +*Want "AEBR/AEB NF -2.0/+Dnice FPCR" 00080001 F8000C01 00080001 F8000C01 +r 1800.10 +*Want "AEBR/AEB NF -2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1810.10 +*Want "AEBR/AEB NF -2.0/+inf FPCR" 00000002 F8000002 00000002 F8000002 +r 1820.10 +*Want "AEBR/AEB NF -2.0/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 1830.10 +*Want "AEBR/AEB NF -2.0/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 1840.10 +*Want "AEBR/AEB NF -Dnice/-inf FPCR" 00000001 F8000001 00000001 F8000001 +r 1850.10 +*Want "AEBR/AEB NF -Dnice/-2.0 FPCR" 00080001 F8000801 00080001 F8000801 +r 1860.10 +*Want "AEBR/AEB NF -Dnice/-Dnice FPCR" 00000001 F8001001 00000001 F8001001 +r 1870.10 +*Want "AEBR/AEB NF -Dnice/-0 FPCR" 00000001 F8001001 00000001 F8001001 +r 1880.10 +*Want "AEBR/AEB NF -Dnice/+0 FPCR" 00000001 F8001001 00000001 F8001001 +r 1890.10 +*Want "AEBR/AEB NF -Dnice/+Dnice FPCR" 00000000 F8000000 00000000 F8000000 +r 18A0.10 +*Want "AEBR/AEB NF -Dnice/+2.0 FPCR" 00080002 F8000C02 00080002 F8000C02 +r 18B0.10 +*Want "AEBR/AEB NF -Dnice/+inf FPCR" 00000002 F8000002 00000002 F8000002 +r 18C0.10 +*Want "AEBR/AEB NF -Dnice/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 18D0.10 +*Want "AEBR/AEB NF -Dnice/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 18E0.10 +*Want "AEBR/AEB NF -0/-inf FPCR" 00000001 F8000001 00000001 F8000001 +r 18F0.10 +*Want "AEBR/AEB NF -0/-2.0 FPCR" 00000001 F8000001 00000001 F8000001 +r 1900.10 +*Want "AEBR/AEB NF -0/-Dnice FPCR" 00000001 F8001001 00000001 F8001001 +r 1910.10 +*Want "AEBR/AEB NF -0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1920.10 +*Want "AEBR/AEB NF -0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1930.10 +*Want "AEBR/AEB NF -0/+Dnice FPCR" 00000002 F8001002 00000002 F8001002 +r 1940.10 +*Want "AEBR/AEB NF -0/+2.0 FPCR" 00000002 F8000002 00000002 F8000002 +r 1950.10 +*Want "AEBR/AEB NF -0/+inf FPCR" 00000002 F8000002 00000002 F8000002 +r 1960.10 +*Want "AEBR/AEB NF -0/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 1970.10 +*Want "AEBR/AEB NF -0/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 1980.10 +*Want "AEBR/AEB NF +0/-inf FPCR" 00000001 F8000001 00000001 F8000001 +r 1990.10 +*Want "AEBR/AEB NF +0/-2.0 FPCR" 00000001 F8000001 00000001 F8000001 +r 19A0.10 +*Want "AEBR/AEB NF +0/-Dnice FPCR" 00000001 F8001001 00000001 F8001001 +r 19B0.10 +*Want "AEBR/AEB NF +0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 19C0.10 +*Want "AEBR/AEB NF +0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 19D0.10 +*Want "AEBR/AEB NF +0/+Dnice FPCR" 00000002 F8001002 00000002 F8001002 +r 19E0.10 +*Want "AEBR/AEB NF +0/+2.0 FPCR" 00000002 F8000002 00000002 F8000002 +r 19F0.10 +*Want "AEBR/AEB NF +0/+inf FPCR" 00000002 F8000002 00000002 F8000002 +r 1A00.10 +*Want "AEBR/AEB NF +0/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 1A10.10 +*Want "AEBR/AEB NF +0/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 1A20.10 +*Want "AEBR/AEB NF +Dnice/-inf FPCR" 00000001 F8000001 00000001 F8000001 +r 1A30.10 +*Want "AEBR/AEB NF +Dnice/-2.0 FPCR" 00080001 F8000C01 00080001 F8000C01 +r 1A40.10 +*Want "AEBR/AEB NF +Dnice/-Dnice FPCR" 00000000 F8000000 00000000 F8000000 +r 1A50.10 +*Want "AEBR/AEB NF +Dnice/-0 FPCR" 00000002 F8001002 00000002 F8001002 +r 1A60.10 +*Want "AEBR/AEB NF +Dnice/+0 FPCR" 00000002 F8001002 00000002 F8001002 +r 1A70.10 +*Want "AEBR/AEB NF +Dnice/+Dnice FPCR" 00000002 F8001002 00000002 F8001002 +r 1A80.10 +*Want "AEBR/AEB NF +Dnice/+2.0 FPCR" 00080002 F8000802 00080002 F8000802 +r 1A90.10 +*Want "AEBR/AEB NF +Dnice/+inf FPCR" 00000002 F8000002 00000002 F8000002 +r 1AA0.10 +*Want "AEBR/AEB NF +Dnice/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 1AB0.10 +*Want "AEBR/AEB NF +Dnice/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 1AC0.10 +*Want "AEBR/AEB NF +2.0/-inf FPCR" 00000001 F8000001 00000001 F8000001 +r 1AD0.10 +*Want "AEBR/AEB NF +2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1AE0.10 +*Want "AEBR/AEB NF +2.0/-Dnice FPCR" 00080002 F8000C02 00080002 F8000C02 +r 1AF0.10 +*Want "AEBR/AEB NF +2.0/-0 FPCR" 00000002 F8000002 00000002 F8000002 +r 1B00.10 +*Want "AEBR/AEB NF +2.0/+0 FPCR" 00000002 F8000002 00000002 F8000002 +r 1B10.10 +*Want "AEBR/AEB NF +2.0/+Dnice FPCR" 00080002 F8000802 00080002 F8000802 +r 1B20.10 +*Want "AEBR/AEB NF +2.0/+2.0 FPCR" 00000002 F8000002 00000002 F8000002 +r 1B30.10 +*Want "AEBR/AEB NF +2.0/+inf FPCR" 00000002 F8000002 00000002 F8000002 +r 1B40.10 +*Want "AEBR/AEB NF +2.0/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 1B50.10 +*Want "AEBR/AEB NF +2.0/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 1B60.10 +*Want "AEBR/AEB NF +inf/-inf FPCR" 00800003 F8008003 00800003 F8008003 +r 1B70.10 +*Want "AEBR/AEB NF +inf/-2.0 FPCR" 00000002 F8000002 00000002 F8000002 +r 1B80.10 +*Want "AEBR/AEB NF +inf/-Dnice FPCR" 00000002 F8000002 00000002 F8000002 +r 1B90.10 +*Want "AEBR/AEB NF +inf/-0 FPCR" 00000002 F8000002 00000002 F8000002 +r 1BA0.10 +*Want "AEBR/AEB NF +inf/+0 FPCR" 00000002 F8000002 00000002 F8000002 +r 1BB0.10 +*Want "AEBR/AEB NF +inf/+Dnice FPCR" 00000002 F8000002 00000002 F8000002 +r 1BC0.10 +*Want "AEBR/AEB NF +inf/+2.0 FPCR" 00000002 F8000002 00000002 F8000002 +r 1BD0.10 +*Want "AEBR/AEB NF +inf/+inf FPCR" 00000002 F8000002 00000002 F8000002 +r 1BE0.10 +*Want "AEBR/AEB NF +inf/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 1BF0.10 +*Want "AEBR/AEB NF +inf/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 1C00.10 +*Want "AEBR/AEB NF -QNaN/-inf FPCR" 00000003 F8000003 00000003 F8000003 +r 1C10.10 +*Want "AEBR/AEB NF -QNaN/-2.0 FPCR" 00000003 F8000003 00000003 F8000003 +r 1C20.10 +*Want "AEBR/AEB NF -QNaN/-Dnice FPCR" 00000003 F8000003 00000003 F8000003 +r 1C30.10 +*Want "AEBR/AEB NF -QNaN/-0 FPCR" 00000003 F8000003 00000003 F8000003 +r 1C40.10 +*Want "AEBR/AEB NF -QNaN/+0 FPCR" 00000003 F8000003 00000003 F8000003 +r 1C50.10 +*Want "AEBR/AEB NF -QNaN/+Dnice FPCR" 00000003 F8000003 00000003 F8000003 +r 1C60.10 +*Want "AEBR/AEB NF -QNaN/+2.0 FPCR" 00000003 F8000003 00000003 F8000003 +r 1C70.10 +*Want "AEBR/AEB NF -QNaN/+inf FPCR" 00000003 F8000003 00000003 F8000003 +r 1C80.10 +*Want "AEBR/AEB NF -QNaN/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 1C90.10 +*Want "AEBR/AEB NF -QNaN/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 1CA0.10 +*Want "AEBR/AEB NF +SNaN/-inf FPCR" 00800003 F8008003 00800003 F8008003 +r 1CB0.10 +*Want "AEBR/AEB NF +SNaN/-2.0 FPCR" 00800003 F8008003 00800003 F8008003 +r 1CC0.10 +*Want "AEBR/AEB NF +SNaN/-Dnice FPCR" 00800003 F8008003 00800003 F8008003 +r 1CD0.10 +*Want "AEBR/AEB NF +SNaN/-0 FPCR" 00800003 F8008003 00800003 F8008003 +r 1CE0.10 +*Want "AEBR/AEB NF +SNaN/+0 FPCR" 00800003 F8008003 00800003 F8008003 +r 1CF0.10 +*Want "AEBR/AEB NF +SNaN/+Dnice FPCR" 00800003 F8008003 00800003 F8008003 +r 1D00.10 +*Want "AEBR/AEB NF +SNaN/+2.0 FPCR" 00800003 F8008003 00800003 F8008003 +r 1D10.10 +*Want "AEBR/AEB NF +SNaN/+inf FPCR" 00800003 F8008003 00800003 F8008003 +r 1D20.10 +*Want "AEBR/AEB NF +SNaN/-QNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 1D30.10 +*Want "AEBR/AEB NF +SNaN/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 + + +r 1E00.10 +*Want "AEBR/AEB F Ovfl" 7F800000 1FFFFFFF 7F800000 1FFFFFFF +r 1E10.10 +*Want "AEBR/AEB F Ufl 1" 007FFFFF 607FFFFE 007FFFFF 607FFFFE +r 1E20.10 +*Want "AEBR/AEB F Ufl 2" 00040F0F 5E01E1E0 00040F0F 5E01E1E0 +r 1E30.10 +*Want "AEBR/AEB F Nmin" 00800000 00800000 00800000 00800000 +r 1E40.10 +*Want "AEBR/AEB F Incr" 3F800001 3F800001 3F800001 3F800001 +r 1E50.10 +*Want "AEBR/AEB F Trun" 3F800000 3F800000 3F800000 3F800000 + + +r 1F00.10 +*Want "AEBR/AEB F Ovfl FPCR" 00280002 F8002002 00280002 F8002002 +r 1F10.10 +*Want "AEBR/AEB F Ufl 1 FPCR" 00000002 F8001002 00000002 F8001002 +r 1F20.10 +*Want "AEBR/AEB F Ufl 2 FPCR" 00000002 F8001002 00000002 F8001002 +r 1F30.10 +*Want "AEBR/AEB F Nmin FPCR" 00000002 F8000002 00000002 F8000002 +r 1F40.10 +*Want "AEBR/AEB F Incr FPCR" 00080002 F8000C02 00080002 F8000C02 +r 1F50.10 +*Want "AEBR/AEB F Trun FPCR" 00080002 F8000802 00080002 F8000802 + + +r 2000.10 +*Want "AEBR/AEB RM +NZ RNTE, RZ" 3F800000 3F800000 3F800000 3F800000 +r 2010.10 +*Want "AEBR/AEB RM +NZ RP, RM" 3F800001 3F800001 3F800000 3F800000 +r 2020.8 +*Want "AEBR/AEB RM +NZ RFS" 3F800001 3F800001 +r 2030.10 +*Want "AEBR/AEB RM -NZ RNTE, RZ" BF800000 BF800000 BF800000 BF800000 +r 2040.10 +*Want "AEBR/AEB RM -NZ RP, RM" BF800000 BF800000 BF800001 BF800001 +r 2050.8 +*Want "AEBR/AEB RM -NZ RFS" BF800001 BF800001 +r 2060.10 +*Want "AEBR/AEB RM +NA RNTE, RZ" 3F800001 3F800001 3F800000 3F800000 +r 2070.10 +*Want "AEBR/AEB RM +NA RP, RM" 3F800001 3F800001 3F800000 3F800000 +r 2080.8 +*Want "AEBR/AEB RM +NA RFS" 3F800001 3F800001 +r 2090.10 +*Want "AEBR/AEB RM -NA RNTE, RZ" BF800001 BF800001 BF800000 BF800000 +r 20A0.10 +*Want "AEBR/AEB RM -NA RP, RM" BF800000 BF800000 BF800001 BF800001 +r 20B0.8 +*Want "AEBR/AEB RM -NA RFS" BF800001 BF800001 +r 20C0.10 +*Want "AEBR/AEB RM +TZ RNTE, RZ" 3F800000 3F800000 3F800000 3F800000 +r 20D0.10 +*Want "AEBR/AEB RM +TZ RP, RM" 3F800001 3F800001 3F800000 3F800000 +r 20E0.8 +*Want "AEBR/AEB RM +TZ RFS" 3F800001 3F800001 +r 20F0.10 +*Want "AEBR/AEB RM -TZ RNTE, RZ" BF800000 BF800000 BF800000 BF800000 +r 2100.10 +*Want "AEBR/AEB RM -TZ RP, RM" BF800000 BF800000 BF800001 BF800001 +r 2110.8 +*Want "AEBR/AEB RM -TZ RFS" BF800001 BF800001 +r 2120.10 +*Want "AEBR/AEB RM +TA RNTE, RZ" 3F800002 3F800002 3F800001 3F800001 +r 2130.10 +*Want "AEBR/AEB RM +TA RP, RM" 3F800002 3F800002 3F800001 3F800001 +r 2140.8 +*Want "AEBR/AEB RM +TA RFS" 3F800001 3F800001 +r 2150.10 +*Want "AEBR/AEB RM -TA RNTE, RZ" BF800002 BF800002 BF800001 BF800001 +r 2160.10 +*Want "AEBR/AEB RM -TA RP, RM" BF800001 BF800001 BF800002 BF800002 +r 2170.8 +*Want "AEBR/AEB RM -TA RFS" BF800001 BF800001 + + + + +r 2300.10 +*Want "AEBR/AEB RM +NZ FPCR" 00080002 00080002 00080002 00080002 +r 2310.10 +*Want "AEBR/AEB RM +NZ FPCR" 00080002 00080002 00080002 00080002 +r 2320.08 +*Want "AEBR/AEB RM +NZ FPCR" 00080002 00080002 +r 2330.10 +*Want "AEBR/AEB RM -NZ FPCR" 00080001 00080001 00080001 00080001 +r 2340.10 +*Want "AEBR/AEB RM -NZ FPCR" 00080001 00080001 00080001 00080001 +r 2350.08 +*Want "AEBR/AEB RM -NZ FPCR" 00080001 00080001 +r 2360.10 +*Want "AEBR/AEB RM +NA FPCR" 00080002 00080002 00080002 00080002 +r 2370.10 +*Want "AEBR/AEB RM +NA FPCR" 00080002 00080002 00080002 00080002 +r 2380.08 +*Want "AEBR/AEB RM +NA FPCR" 00080002 00080002 +r 2390.10 +*Want "AEBR/AEB RM -NA FPCR" 00080001 00080001 00080001 00080001 +r 23A0.10 +*Want "AEBR/AEB RM -NA FPCR" 00080001 00080001 00080001 00080001 +r 23B0.08 +*Want "AEBR/AEB RM -NA FPCR" 00080001 00080001 +r 23C0.10 +*Want "AEBR/AEB RM +TZ FPCR" 00080002 00080002 00080002 00080002 +r 23D0.10 +*Want "AEBR/AEB RM +TZ FPCR" 00080002 00080002 00080002 00080002 +r 23E0.08 +*Want "AEBR/AEB RM +TZ FPCR" 00080002 00080002 +r 23F0.10 +*Want "AEBR/AEB RM -TZ FPCR" 00080001 00080001 00080001 00080001 +r 2400.10 +*Want "AEBR/AEB RM -TZ FPCR" 00080001 00080001 00080001 00080001 +r 2410.08 +*Want "AEBR/AEB RM -TZ FPCR" 00080001 00080001 +r 2420.10 +*Want "AEBR/AEB RM +TA FPCR" 00080002 00080002 00080002 00080002 +r 2430.10 +*Want "AEBR/AEB RM +TA FPCR" 00080002 00080002 00080002 00080002 +r 2440.08 +*Want "AEBR/AEB RM +TA FPCR" 00080002 00080002 +r 2450.10 +*Want "AEBR/AEB RM -TA FPCR" 00080001 00080001 00080001 00080001 +r 2460.10 +*Want "AEBR/AEB RM -TA FPCR" 00080001 00080001 00080001 00080001 +r 2470.08 +*Want "AEBR/AEB RM -TA FPCR" 00080001 00080001 + + +r 4000.10 +*Want "ADBR NF -inf/-inf" FFF00000 00000000 FFF00000 00000000 +r 4010.10 +*Want "ADB NF -inf/-inf" FFF00000 00000000 FFF00000 00000000 +r 4020.10 +*Want "ADBR NF -inf/-2.0" FFF00000 00000000 FFF00000 00000000 +r 4030.10 +*Want "ADB NF -inf/-2.0" FFF00000 00000000 FFF00000 00000000 +r 4040.10 +*Want "ADBR NF -inf/-Dnice" FFF00000 00000000 FFF00000 00000000 +r 4050.10 +*Want "ADB NF -inf/-Dnice" FFF00000 00000000 FFF00000 00000000 +r 4060.10 +*Want "ADBR NF -inf/-0" FFF00000 00000000 FFF00000 00000000 +r 4070.10 +*Want "ADB NF -inf/-0" FFF00000 00000000 FFF00000 00000000 +r 4080.10 +*Want "ADBR NF -inf/+0" FFF00000 00000000 FFF00000 00000000 +r 4090.10 +*Want "ADB NF -inf/+0" FFF00000 00000000 FFF00000 00000000 +r 40A0.10 +*Want "ADBR NF -inf/+Dnice" FFF00000 00000000 FFF00000 00000000 +r 40B0.10 +*Want "ADB NF -inf/+Dnice" FFF00000 00000000 FFF00000 00000000 +r 40C0.10 +*Want "ADBR NF -inf/+2.0" FFF00000 00000000 FFF00000 00000000 +r 40D0.10 +*Want "ADB NF -inf/+2.0" FFF00000 00000000 FFF00000 00000000 +r 40E0.10 +*Want "ADBR NF -inf/+inf" 7FF80000 00000000 FFF00000 00000000 +r 40F0.10 +*Want "ADB NF -inf/+inf" 7FF80000 00000000 FFF00000 00000000 +r 4100.10 +*Want "ADBR NF -inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 4110.10 +*Want "ADB NF -inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 4120.10 +*Want "ADBR NF -inf/+SNaN" 7FF8A000 00000000 FFF00000 00000000 +r 4130.10 +*Want "ADB NF -inf/+SNaN" 7FF8A000 00000000 FFF00000 00000000 +r 4140.10 +*Want "ADBR NF -2.0/-inf" FFF00000 00000000 FFF00000 00000000 +r 4150.10 +*Want "ADB NF -2.0/-inf" FFF00000 00000000 FFF00000 00000000 +r 4160.10 +*Want "ADBR NF -2.0/-2.0" C0100000 00000000 C0100000 00000000 +r 4170.10 +*Want "ADB NF -2.0/-2.0" C0100000 00000000 C0100000 00000000 +r 4180.10 +*Want "ADBR NF -2.0/-Dnice" C0000000 00000000 C0000000 00000000 +r 4190.10 +*Want "ADB NF -2.0/-Dnice" C0000000 00000000 C0000000 00000000 +r 41A0.10 +*Want "ADBR NF -2.0/-0" C0000000 00000000 C0000000 00000000 +r 41B0.10 +*Want "ADB NF -2.0/-0" C0000000 00000000 C0000000 00000000 +r 41C0.10 +*Want "ADBR NF -2.0/+0" C0000000 00000000 C0000000 00000000 +r 41D0.10 +*Want "ADB NF -2.0/+0" C0000000 00000000 C0000000 00000000 +r 41E0.10 +*Want "ADBR NF -2.0/+Dnice" C0000000 00000000 C0000000 00000000 +r 41F0.10 +*Want "ADB NF -2.0/+Dnice" C0000000 00000000 C0000000 00000000 +r 4200.10 +*Want "ADBR NF -2.0/+2.0" 00000000 00000000 00000000 00000000 +r 4210.10 +*Want "ADB NF -2.0/+2.0" 00000000 00000000 00000000 00000000 +r 4220.10 +*Want "ADBR NF -2.0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 4230.10 +*Want "ADB NF -2.0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 4240.10 +*Want "ADBR NF -2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 4250.10 +*Want "ADB NF -2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 4260.10 +*Want "ADBR NF -2.0/+SNaN" 7FF8A000 00000000 C0000000 00000000 +r 4270.10 +*Want "ADB NF -2.0/+SNaN" 7FF8A000 00000000 C0000000 00000000 +r 4280.10 +*Want "ADBR NF -Dnice/-inf" FFF00000 00000000 FFF00000 00000000 +r 4290.10 +*Want "ADB NF -Dnice/-inf" FFF00000 00000000 FFF00000 00000000 +r 42A0.10 +*Want "ADBR NF -Dnice/-2.0" C0000000 00000000 C0000000 00000000 +r 42B0.10 +*Want "ADB NF -Dnice/-2.0" C0000000 00000000 C0000000 00000000 +r 42C0.10 +*Want "ADBR NF -Dnice/-Dnice" 80020000 00000000 DFE00000 00000000 +r 42D0.10 +*Want "ADB NF -Dnice/-Dnice" 80020000 00000000 DFE00000 00000000 +r 42E0.10 +*Want "ADBR NF -Dnice/-0" 80010000 00000000 DFD00000 00000000 +r 42F0.10 +*Want "ADB NF -Dnice/-0" 80010000 00000000 DFD00000 00000000 +r 4300.10 +*Want "ADBR NF -Dnice/+0" 80010000 00000000 DFD00000 00000000 +r 4310.10 +*Want "ADB NF -Dnice/+0" 80010000 00000000 DFD00000 00000000 +r 4320.10 +*Want "ADBR NF -Dnice/+Dnice" 00000000 00000000 00000000 00000000 +r 4330.10 +*Want "ADB NF -Dnice/+Dnice" 00000000 00000000 00000000 00000000 +r 4340.10 +*Want "ADBR NF -Dnice/+2.0" 40000000 00000000 40000000 00000000 +r 4350.10 +*Want "ADB NF -Dnice/+2.0" 40000000 00000000 40000000 00000000 +r 4360.10 +*Want "ADBR NF -Dnice/+inf" 7FF00000 00000000 7FF00000 00000000 +r 4370.10 +*Want "ADB NF -Dnice/+inf" 7FF00000 00000000 7FF00000 00000000 +r 4380.10 +*Want "ADBR NF -Dnice/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 4390.10 +*Want "ADB NF -Dnice/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 43A0.10 +*Want "ADBR NF -Dnice/+SNaN" 7FF8A000 00000000 80010000 00000000 +r 43B0.10 +*Want "ADB NF -Dnice/+SNaN" 7FF8A000 00000000 80010000 00000000 +r 43C0.10 +*Want "ADBR NF -0/-inf" FFF00000 00000000 FFF00000 00000000 +r 43D0.10 +*Want "ADB NF -0/-inf" FFF00000 00000000 FFF00000 00000000 +r 43E0.10 +*Want "ADBR NF -0/-2.0" C0000000 00000000 C0000000 00000000 +r 43F0.10 +*Want "ADB NF -0/-2.0" C0000000 00000000 C0000000 00000000 +r 4400.10 +*Want "ADBR NF -0/-Dnice" 80010000 00000000 DFD00000 00000000 +r 4410.10 +*Want "ADB NF -0/-Dnice" 80010000 00000000 DFD00000 00000000 +r 4420.10 +*Want "ADBR NF -0/-0" 80000000 00000000 80000000 00000000 +r 4430.10 +*Want "ADB NF -0/-0" 80000000 00000000 80000000 00000000 +r 4440.10 +*Want "ADBR NF -0/+0" 00000000 00000000 00000000 00000000 +r 4450.10 +*Want "ADB NF -0/+0" 00000000 00000000 00000000 00000000 +r 4460.10 +*Want "ADBR NF -0/+Dnice" 00010000 00000000 5FD00000 00000000 +r 4470.10 +*Want "ADB NF -0/+Dnice" 00010000 00000000 5FD00000 00000000 +r 4480.10 +*Want "ADBR NF -0/+2.0" 40000000 00000000 40000000 00000000 +r 4490.10 +*Want "ADB NF -0/+2.0" 40000000 00000000 40000000 00000000 +r 44A0.10 +*Want "ADBR NF -0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 44B0.10 +*Want "ADB NF -0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 44C0.10 +*Want "ADBR NF -0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 44D0.10 +*Want "ADB NF -0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 44E0.10 +*Want "ADBR NF -0/+SNaN" 7FF8A000 00000000 80000000 00000000 +r 44F0.10 +*Want "ADB NF -0/+SNaN" 7FF8A000 00000000 80000000 00000000 +r 4500.10 +*Want "ADBR NF +0/-inf" FFF00000 00000000 FFF00000 00000000 +r 4510.10 +*Want "ADB NF +0/-inf" FFF00000 00000000 FFF00000 00000000 +r 4520.10 +*Want "ADBR NF +0/-2.0" C0000000 00000000 C0000000 00000000 +r 4530.10 +*Want "ADB NF +0/-2.0" C0000000 00000000 C0000000 00000000 +r 4540.10 +*Want "ADBR NF +0/-Dnice" 80010000 00000000 DFD00000 00000000 +r 4550.10 +*Want "ADB NF +0/-Dnice" 80010000 00000000 DFD00000 00000000 +r 4560.10 +*Want "ADBR NF +0/-0" 00000000 00000000 00000000 00000000 +r 4570.10 +*Want "ADB NF +0/-0" 00000000 00000000 00000000 00000000 +r 4580.10 +*Want "ADBR NF +0/+0" 00000000 00000000 00000000 00000000 +r 4590.10 +*Want "ADB NF +0/+0" 00000000 00000000 00000000 00000000 +r 45A0.10 +*Want "ADBR NF +0/+Dnice" 00010000 00000000 5FD00000 00000000 +r 45B0.10 +*Want "ADB NF +0/+Dnice" 00010000 00000000 5FD00000 00000000 +r 45C0.10 +*Want "ADBR NF +0/+2.0" 40000000 00000000 40000000 00000000 +r 45D0.10 +*Want "ADB NF +0/+2.0" 40000000 00000000 40000000 00000000 +r 45E0.10 +*Want "ADBR NF +0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 45F0.10 +*Want "ADB NF +0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 4600.10 +*Want "ADBR NF +0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 4610.10 +*Want "ADB NF +0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 4620.10 +*Want "ADBR NF +0/+SNaN" 7FF8A000 00000000 00000000 00000000 +r 4630.10 +*Want "ADB NF +0/+SNaN" 7FF8A000 00000000 00000000 00000000 +r 4640.10 +*Want "ADBR NF +Dnice/-inf" FFF00000 00000000 FFF00000 00000000 +r 4650.10 +*Want "ADB NF +Dnice/-inf" FFF00000 00000000 FFF00000 00000000 +r 4660.10 +*Want "ADBR NF +Dnice/-2.0" C0000000 00000000 C0000000 00000000 +r 4670.10 +*Want "ADB NF +Dnice/-2.0" C0000000 00000000 C0000000 00000000 +r 4680.10 +*Want "ADBR NF +Dnice/-Dnice" 00000000 00000000 00000000 00000000 +r 4690.10 +*Want "ADB NF +Dnice/-Dnice" 00000000 00000000 00000000 00000000 +r 46A0.10 +*Want "ADBR NF +Dnice/-0" 00010000 00000000 5FD00000 00000000 +r 46B0.10 +*Want "ADB NF +Dnice/-0" 00010000 00000000 5FD00000 00000000 +r 46C0.10 +*Want "ADBR NF +Dnice/+0" 00010000 00000000 5FD00000 00000000 +r 46D0.10 +*Want "ADB NF +Dnice/+0" 00010000 00000000 5FD00000 00000000 +r 46E0.10 +*Want "ADBR NF +Dnice/+Dnice" 00020000 00000000 5FE00000 00000000 +r 46F0.10 +*Want "ADB NF +Dnice/+Dnice" 00020000 00000000 5FE00000 00000000 +r 4700.10 +*Want "ADBR NF +Dnice/+2.0" 40000000 00000000 40000000 00000000 +r 4710.10 +*Want "ADB NF +Dnice/+2.0" 40000000 00000000 40000000 00000000 +r 4720.10 +*Want "ADBR NF +Dnice/+inf" 7FF00000 00000000 7FF00000 00000000 +r 4730.10 +*Want "ADB NF +Dnice/+inf" 7FF00000 00000000 7FF00000 00000000 +r 4740.10 +*Want "ADBR NF +Dnice/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 4750.10 +*Want "ADB NF +Dnice/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 4760.10 +*Want "ADBR NF +Dnice/+SNaN" 7FF8A000 00000000 00010000 00000000 +r 4770.10 +*Want "ADB NF +Dnice/+SNaN" 7FF8A000 00000000 00010000 00000000 +r 4780.10 +*Want "ADBR NF +2.0/-inf" FFF00000 00000000 FFF00000 00000000 +r 4790.10 +*Want "ADB NF +2.0/-inf" FFF00000 00000000 FFF00000 00000000 +r 47A0.10 +*Want "ADBR NF +2.0/-2.0" 00000000 00000000 00000000 00000000 +r 47B0.10 +*Want "ADB NF +2.0/-2.0" 00000000 00000000 00000000 00000000 +r 47C0.10 +*Want "ADBR NF +2.0/-Dnice" 40000000 00000000 40000000 00000000 +r 47D0.10 +*Want "ADB NF +2.0/-Dnice" 40000000 00000000 40000000 00000000 +r 47E0.10 +*Want "ADBR NF +2.0/-0" 40000000 00000000 40000000 00000000 +r 47F0.10 +*Want "ADB NF +2.0/-0" 40000000 00000000 40000000 00000000 +r 4800.10 +*Want "ADBR NF +2.0/+0" 40000000 00000000 40000000 00000000 +r 4810.10 +*Want "ADB NF +2.0/+0" 40000000 00000000 40000000 00000000 +r 4820.10 +*Want "ADBR NF +2.0/+Dnice" 40000000 00000000 40000000 00000000 +r 4830.10 +*Want "ADB NF +2.0/+Dnice" 40000000 00000000 40000000 00000000 +r 4840.10 +*Want "ADBR NF +2.0/+2.0" 40100000 00000000 40100000 00000000 +r 4850.10 +*Want "ADB NF +2.0/+2.0" 40100000 00000000 40100000 00000000 +r 4860.10 +*Want "ADBR NF +2.0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 4870.10 +*Want "ADB NF +2.0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 4880.10 +*Want "ADBR NF +2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 4890.10 +*Want "ADB NF +2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 48A0.10 +*Want "ADBR NF +2.0/+SNaN" 7FF8A000 00000000 40000000 00000000 +r 48B0.10 +*Want "ADB NF +2.0/+SNaN" 7FF8A000 00000000 40000000 00000000 +r 48C0.10 +*Want "ADBR NF +inf/-inf" 7FF80000 00000000 7FF00000 00000000 +r 48D0.10 +*Want "ADB NF +inf/-inf" 7FF80000 00000000 7FF00000 00000000 +r 48E0.10 +*Want "ADBR NF +inf/-2.0" 7FF00000 00000000 7FF00000 00000000 +r 48F0.10 +*Want "ADB NF +inf/-2.0" 7FF00000 00000000 7FF00000 00000000 +r 4900.10 +*Want "ADBR NF +inf/-Dnice" 7FF00000 00000000 7FF00000 00000000 +r 4910.10 +*Want "ADB NF +inf/-Dnice" 7FF00000 00000000 7FF00000 00000000 +r 4920.10 +*Want "ADBR NF +inf/-0" 7FF00000 00000000 7FF00000 00000000 +r 4930.10 +*Want "ADB NF +inf/-0" 7FF00000 00000000 7FF00000 00000000 +r 4940.10 +*Want "ADBR NF +inf/+0" 7FF00000 00000000 7FF00000 00000000 +r 4950.10 +*Want "ADB NF +inf/+0" 7FF00000 00000000 7FF00000 00000000 +r 4960.10 +*Want "ADBR NF +inf/+Dnice" 7FF00000 00000000 7FF00000 00000000 +r 4970.10 +*Want "ADB NF +inf/+Dnice" 7FF00000 00000000 7FF00000 00000000 +r 4980.10 +*Want "ADBR NF +inf/+2.0" 7FF00000 00000000 7FF00000 00000000 +r 4990.10 +*Want "ADB NF +inf/+2.0" 7FF00000 00000000 7FF00000 00000000 +r 49A0.10 +*Want "ADBR NF +inf/+inf" 7FF00000 00000000 7FF00000 00000000 +r 49B0.10 +*Want "ADB NF +inf/+inf" 7FF00000 00000000 7FF00000 00000000 +r 49C0.10 +*Want "ADBR NF +inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 49D0.10 +*Want "ADB NF +inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 49E0.10 +*Want "ADBR NF +inf/+SNaN" 7FF8A000 00000000 7FF00000 00000000 +r 49F0.10 +*Want "ADB NF +inf/+SNaN" 7FF8A000 00000000 7FF00000 00000000 +r 4A00.10 +*Want "ADBR NF -QNaN/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 4A10.10 +*Want "ADB NF -QNaN/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 4A20.10 +*Want "ADBR NF -QNaN/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 4A30.10 +*Want "ADB NF -QNaN/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 4A40.10 +*Want "ADBR NF -QNaN/-Dnice" FFF8B000 00000000 FFF8B000 00000000 +r 4A50.10 +*Want "ADB NF -QNaN/-Dnice" FFF8B000 00000000 FFF8B000 00000000 +r 4A60.10 +*Want "ADBR NF -QNaN/-0" FFF8B000 00000000 FFF8B000 00000000 +r 4A70.10 +*Want "ADB NF -QNaN/-0" FFF8B000 00000000 FFF8B000 00000000 +r 4A80.10 +*Want "ADBR NF -QNaN/+0" FFF8B000 00000000 FFF8B000 00000000 +r 4A90.10 +*Want "ADB NF -QNaN/+0" FFF8B000 00000000 FFF8B000 00000000 +r 4AA0.10 +*Want "ADBR NF -QNaN/+Dnice" FFF8B000 00000000 FFF8B000 00000000 +r 4AB0.10 +*Want "ADB NF -QNaN/+Dnice" FFF8B000 00000000 FFF8B000 00000000 +r 4AC0.10 +*Want "ADBR NF -QNaN/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 4AD0.10 +*Want "ADB NF -QNaN/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 4AE0.10 +*Want "ADBR NF -QNaN/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 4AF0.10 +*Want "ADB NF -QNaN/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 4B00.10 +*Want "ADBR NF -QNaN/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 4B10.10 +*Want "ADB NF -QNaN/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 4B20.10 +*Want "ADBR NF -QNaN/+SNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 4B30.10 +*Want "ADB NF -QNaN/+SNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 4B40.10 +*Want "ADBR NF +SNaN/-inf" 7FF8A000 00000000 7FF0A000 00000000 +r 4B50.10 +*Want "ADB NF +SNaN/-inf" 7FF8A000 00000000 7FF0A000 00000000 +r 4B60.10 +*Want "ADBR NF +SNaN/-2.0" 7FF8A000 00000000 7FF0A000 00000000 +r 4B70.10 +*Want "ADB NF +SNaN/-2.0" 7FF8A000 00000000 7FF0A000 00000000 +r 4B80.10 +*Want "ADBR NF +SNaN/-Dnice" 7FF8A000 00000000 7FF0A000 00000000 +r 4B90.10 +*Want "ADB NF +SNaN/-Dnice" 7FF8A000 00000000 7FF0A000 00000000 +r 4BA0.10 +*Want "ADBR NF +SNaN/-0" 7FF8A000 00000000 7FF0A000 00000000 +r 4BB0.10 +*Want "ADB NF +SNaN/-0" 7FF8A000 00000000 7FF0A000 00000000 +r 4BC0.10 +*Want "ADBR NF +SNaN/+0" 7FF8A000 00000000 7FF0A000 00000000 +r 4BD0.10 +*Want "ADB NF +SNaN/+0" 7FF8A000 00000000 7FF0A000 00000000 +r 4BE0.10 +*Want "ADBR NF +SNaN/+Dnice" 7FF8A000 00000000 7FF0A000 00000000 +r 4BF0.10 +*Want "ADB NF +SNaN/+Dnice" 7FF8A000 00000000 7FF0A000 00000000 +r 4C00.10 +*Want "ADBR NF +SNaN/+2.0" 7FF8A000 00000000 7FF0A000 00000000 +r 4C10.10 +*Want "ADB NF +SNaN/+2.0" 7FF8A000 00000000 7FF0A000 00000000 +r 4C20.10 +*Want "ADBR NF +SNaN/+inf" 7FF8A000 00000000 7FF0A000 00000000 +r 4C30.10 +*Want "ADB NF +SNaN/+inf" 7FF8A000 00000000 7FF0A000 00000000 +r 4C40.10 +*Want "ADBR NF +SNaN/-QNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 4C50.10 +*Want "ADB NF +SNaN/-QNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 4C60.10 +*Want "ADBR NF +SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 4C70.10 +*Want "ADB NF +SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 + + +r 4D00.10 +*Want "ADBR/ADB NF -inf/-inf FPCR" 00000001 F8000001 00000001 F8000001 +r 4D10.10 +*Want "ADBR/ADB NF -inf/-2.0 FPCR" 00000001 F8000001 00000001 F8000001 +r 4D20.10 +*Want "ADBR/ADB NF -inf/-Dnice FPCR" 00000001 F8000001 00000001 F8000001 +r 4D30.10 +*Want "ADBR/ADB NF -inf/-0 FPCR" 00000001 F8000001 00000001 F8000001 +r 4D40.10 +*Want "ADBR/ADB NF -inf/+0 FPCR" 00000001 F8000001 00000001 F8000001 +r 4D50.10 +*Want "ADBR/ADB NF -inf/+Dnice FPCR" 00000001 F8000001 00000001 F8000001 +r 4D60.10 +*Want "ADBR/ADB NF -inf/+2.0 FPCR" 00000001 F8000001 00000001 F8000001 +r 4D70.10 +*Want "ADBR/ADB NF -inf/+inf FPCR" 00800003 F8008003 00800003 F8008003 +r 4D80.10 +*Want "ADBR/ADB NF -inf/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 4D90.10 +*Want "ADBR/ADB NF -inf/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 4DA0.10 +*Want "ADBR/ADB NF -2.0/-inf FPCR" 00000001 F8000001 00000001 F8000001 +r 4DB0.10 +*Want "ADBR/ADB NF -2.0/-2.0 FPCR" 00000001 F8000001 00000001 F8000001 +r 4DC0.10 +*Want "ADBR/ADB NF -2.0/-Dnice FPCR" 00080001 F8000801 00080001 F8000801 +r 4DD0.10 +*Want "ADBR/ADB NF -2.0/-0 FPCR" 00000001 F8000001 00000001 F8000001 +r 4DE0.10 +*Want "ADBR/ADB NF -2.0/+0 FPCR" 00000001 F8000001 00000001 F8000001 +r 4DF0.10 +*Want "ADBR/ADB NF -2.0/+Dnice FPCR" 00080001 F8000C01 00080001 F8000C01 +r 4E00.10 +*Want "ADBR/ADB NF -2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4E10.10 +*Want "ADBR/ADB NF -2.0/+inf FPCR" 00000002 F8000002 00000002 F8000002 +r 4E20.10 +*Want "ADBR/ADB NF -2.0/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 4E30.10 +*Want "ADBR/ADB NF -2.0/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 4E40.10 +*Want "ADBR/ADB NF -Dnice/-inf FPCR" 00000001 F8000001 00000001 F8000001 +r 4E50.10 +*Want "ADBR/ADB NF -Dnice/-2.0 FPCR" 00080001 F8000801 00080001 F8000801 +r 4E60.10 +*Want "ADBR/ADB NF -Dnice/-Dnice FPCR" 00000001 F8001001 00000001 F8001001 +r 4E70.10 +*Want "ADBR/ADB NF -Dnice/-0 FPCR" 00000001 F8001001 00000001 F8001001 +r 4E80.10 +*Want "ADBR/ADB NF -Dnice/+0 FPCR" 00000001 F8001001 00000001 F8001001 +r 4E90.10 +*Want "ADBR/ADB NF -Dnice/+Dnice FPCR" 00000000 F8000000 00000000 F8000000 +r 4EA0.10 +*Want "ADBR/ADB NF -Dnice/+2.0 FPCR" 00080002 F8000C02 00080002 F8000C02 +r 4EB0.10 +*Want "ADBR/ADB NF -Dnice/+inf FPCR" 00000002 F8000002 00000002 F8000002 +r 4EC0.10 +*Want "ADBR/ADB NF -Dnice/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 4ED0.10 +*Want "ADBR/ADB NF -Dnice/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 4EE0.10 +*Want "ADBR/ADB NF -0/-inf FPCR" 00000001 F8000001 00000001 F8000001 +r 4EF0.10 +*Want "ADBR/ADB NF -0/-2.0 FPCR" 00000001 F8000001 00000001 F8000001 +r 4F00.10 +*Want "ADBR/ADB NF -0/-Dnice FPCR" 00000001 F8001001 00000001 F8001001 +r 4F10.10 +*Want "ADBR/ADB NF -0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4F20.10 +*Want "ADBR/ADB NF -0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4F30.10 +*Want "ADBR/ADB NF -0/+Dnice FPCR" 00000002 F8001002 00000002 F8001002 +r 4F40.10 +*Want "ADBR/ADB NF -0/+2.0 FPCR" 00000002 F8000002 00000002 F8000002 +r 4F50.10 +*Want "ADBR/ADB NF -0/+inf FPCR" 00000002 F8000002 00000002 F8000002 +r 4F60.10 +*Want "ADBR/ADB NF -0/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 4F70.10 +*Want "ADBR/ADB NF -0/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 4F80.10 +*Want "ADBR/ADB NF +0/-inf FPCR" 00000001 F8000001 00000001 F8000001 +r 4F90.10 +*Want "ADBR/ADB NF +0/-2.0 FPCR" 00000001 F8000001 00000001 F8000001 +r 4FA0.10 +*Want "ADBR/ADB NF +0/-Dnice FPCR" 00000001 F8001001 00000001 F8001001 +r 4FB0.10 +*Want "ADBR/ADB NF +0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4FC0.10 +*Want "ADBR/ADB NF +0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4FD0.10 +*Want "ADBR/ADB NF +0/+Dnice FPCR" 00000002 F8001002 00000002 F8001002 +r 4FE0.10 +*Want "ADBR/ADB NF +0/+2.0 FPCR" 00000002 F8000002 00000002 F8000002 +r 4FF0.10 +*Want "ADBR/ADB NF +0/+inf FPCR" 00000002 F8000002 00000002 F8000002 +r 5000.10 +*Want "ADBR/ADB NF +0/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 5010.10 +*Want "ADBR/ADB NF +0/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 5020.10 +*Want "ADBR/ADB NF +Dnice/-inf FPCR" 00000001 F8000001 00000001 F8000001 +r 5030.10 +*Want "ADBR/ADB NF +Dnice/-2.0 FPCR" 00080001 F8000C01 00080001 F8000C01 +r 5040.10 +*Want "ADBR/ADB NF +Dnice/-Dnice FPCR" 00000000 F8000000 00000000 F8000000 +r 5050.10 +*Want "ADBR/ADB NF +Dnice/-0 FPCR" 00000002 F8001002 00000002 F8001002 +r 5060.10 +*Want "ADBR/ADB NF +Dnice/+0 FPCR" 00000002 F8001002 00000002 F8001002 +r 5070.10 +*Want "ADBR/ADB NF +Dnice/+Dnice FPCR" 00000002 F8001002 00000002 F8001002 +r 5080.10 +*Want "ADBR/ADB NF +Dnice/+2.0 FPCR" 00080002 F8000802 00080002 F8000802 +r 5090.10 +*Want "ADBR/ADB NF +Dnice/+inf FPCR" 00000002 F8000002 00000002 F8000002 +r 50A0.10 +*Want "ADBR/ADB NF +Dnice/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 50B0.10 +*Want "ADBR/ADB NF +Dnice/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 50C0.10 +*Want "ADBR/ADB NF +2.0/-inf FPCR" 00000001 F8000001 00000001 F8000001 +r 50D0.10 +*Want "ADBR/ADB NF +2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 50E0.10 +*Want "ADBR/ADB NF +2.0/-Dnice FPCR" 00080002 F8000C02 00080002 F8000C02 +r 50F0.10 +*Want "ADBR/ADB NF +2.0/-0 FPCR" 00000002 F8000002 00000002 F8000002 +r 5100.10 +*Want "ADBR/ADB NF +2.0/+0 FPCR" 00000002 F8000002 00000002 F8000002 +r 5110.10 +*Want "ADBR/ADB NF +2.0/+Dnice FPCR" 00080002 F8000802 00080002 F8000802 +r 5120.10 +*Want "ADBR/ADB NF +2.0/+2.0 FPCR" 00000002 F8000002 00000002 F8000002 +r 5130.10 +*Want "ADBR/ADB NF +2.0/+inf FPCR" 00000002 F8000002 00000002 F8000002 +r 5140.10 +*Want "ADBR/ADB NF +2.0/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 5150.10 +*Want "ADBR/ADB NF +2.0/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 5160.10 +*Want "ADBR/ADB NF +inf/-inf FPCR" 00800003 F8008003 00800003 F8008003 +r 5170.10 +*Want "ADBR/ADB NF +inf/-2.0 FPCR" 00000002 F8000002 00000002 F8000002 +r 5180.10 +*Want "ADBR/ADB NF +inf/-Dnice FPCR" 00000002 F8000002 00000002 F8000002 +r 5190.10 +*Want "ADBR/ADB NF +inf/-0 FPCR" 00000002 F8000002 00000002 F8000002 +r 51A0.10 +*Want "ADBR/ADB NF +inf/+0 FPCR" 00000002 F8000002 00000002 F8000002 +r 51B0.10 +*Want "ADBR/ADB NF +inf/+Dnice FPCR" 00000002 F8000002 00000002 F8000002 +r 51C0.10 +*Want "ADBR/ADB NF +inf/+2.0 FPCR" 00000002 F8000002 00000002 F8000002 +r 51D0.10 +*Want "ADBR/ADB NF +inf/+inf FPCR" 00000002 F8000002 00000002 F8000002 +r 51E0.10 +*Want "ADBR/ADB NF +inf/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 51F0.10 +*Want "ADBR/ADB NF +inf/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 5200.10 +*Want "ADBR/ADB NF -QNaN/-inf FPCR" 00000003 F8000003 00000003 F8000003 +r 5210.10 +*Want "ADBR/ADB NF -QNaN/-2.0 FPCR" 00000003 F8000003 00000003 F8000003 +r 5220.10 +*Want "ADBR/ADB NF -QNaN/-Dnice FPCR" 00000003 F8000003 00000003 F8000003 +r 5230.10 +*Want "ADBR/ADB NF -QNaN/-0 FPCR" 00000003 F8000003 00000003 F8000003 +r 5240.10 +*Want "ADBR/ADB NF -QNaN/+0 FPCR" 00000003 F8000003 00000003 F8000003 +r 5250.10 +*Want "ADBR/ADB NF -QNaN/+Dnice FPCR" 00000003 F8000003 00000003 F8000003 +r 5260.10 +*Want "ADBR/ADB NF -QNaN/+2.0 FPCR" 00000003 F8000003 00000003 F8000003 +r 5270.10 +*Want "ADBR/ADB NF -QNaN/+inf FPCR" 00000003 F8000003 00000003 F8000003 +r 5280.10 +*Want "ADBR/ADB NF -QNaN/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 5290.10 +*Want "ADBR/ADB NF -QNaN/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 52A0.10 +*Want "ADBR/ADB NF +SNaN/-inf FPCR" 00800003 F8008003 00800003 F8008003 +r 52B0.10 +*Want "ADBR/ADB NF +SNaN/-2.0 FPCR" 00800003 F8008003 00800003 F8008003 +r 52C0.10 +*Want "ADBR/ADB NF +SNaN/-Dnice FPCR" 00800003 F8008003 00800003 F8008003 +r 52D0.10 +*Want "ADBR/ADB NF +SNaN/-0 FPCR" 00800003 F8008003 00800003 F8008003 +r 52E0.10 +*Want "ADBR/ADB NF +SNaN/+0 FPCR" 00800003 F8008003 00800003 F8008003 +r 52F0.10 +*Want "ADBR/ADB NF +SNaN/+Dnice FPCR" 00800003 F8008003 00800003 F8008003 +r 5300.10 +*Want "ADBR/ADB NF +SNaN/+2.0 FPCR" 00800003 F8008003 00800003 F8008003 +r 5310.10 +*Want "ADBR/ADB NF +SNaN/+inf FPCR" 00800003 F8008003 00800003 F8008003 +r 5320.10 +*Want "ADBR/ADB NF +SNaN/-QNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 5330.10 +*Want "ADBR/ADB NF +SNaN/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 + + +r 5400.10 +*Want "ADBR F Ovfl" 7FFFFFFF FFFFFFFF 7FFFFFFF FFFFFFFF +r 5410.10 +*Want "ADB F Ovfl" 7FFFFFFF FFFFFFFF 7FFFFFFF FFFFFFFF +r 5420.10 +*Want "ADBR F Ufl 1" 000FFFFF FFFFFFFF 600FFFFF FFFFFFFE +r 5430.10 +*Want "ADB F Ufl 1" 000FFFFF FFFFFFFF 600FFFFF FFFFFFFE +r 5440.10 +*Want "ADBR F Ufl 2" 0008F0F0 00000000 6001E1E0 00000000 +r 5450.10 +*Want "ADB F Ufl 2" 0008F0F0 00000000 6001E1E0 00000000 +r 5460.10 +*Want "ADBR F Nmin" 00100000 00000000 00100000 00000000 +r 5470.10 +*Want "ADB F Nmin" 00100000 00000000 00100000 00000000 +r 5480.10 +*Want "ADBR F Incr" 3FF00000 00000001 3FF00000 00000001 +r 5490.10 +*Want "ADB F Incr" 3FF00000 00000001 3FF00000 00000001 +r 54A0.10 +*Want "ADBR F Trun" 3FF00000 00000000 3FF00000 00000000 +r 54B0.10 +*Want "ADB F Trun" 3FF00000 00000000 3FF00000 00000000 + + +r 5600.10 +*Want "ADBR/ADB F Ovfl FPCR" 00000003 F8000003 00000003 F8000003 +r 5610.10 +*Want "ADBR/ADB F Ufl 1 FPCR" 00000002 F8001002 00000002 F8001002 +r 5620.10 +*Want "ADBR/ADB F Ufl 2 FPCR" 00000002 F8001002 00000002 F8001002 +r 5630.10 +*Want "ADBR/ADB F Nmin FPCR" 00000002 F8000002 00000002 F8000002 +r 5640.10 +*Want "ADBR/ADB F Incr FPCR" 00080002 F8000C02 00080002 F8000C02 +r 5650.10 +*Want "ADBR/ADB F Trun FPCR" 00080002 F8000802 00080002 F8000802 + + +r 5700.10 +*Want "ADBR/ADB RM +NZ RNTE" 3FF00000 00000000 3FF00000 00000000 +r 5710.10 +*Want "ADBR/ADB RM +NZ RZ" 3FF00000 00000000 3FF00000 00000000 +r 5720.10 +*Want "ADBR/ADB RM +NZ RP" 3FF00000 00000001 3FF00000 00000001 +r 5730.10 +*Want "ADBR/ADB RM +NZ RM" 3FF00000 00000000 3FF00000 00000000 +r 5740.10 +*Want "ADBR/ADB RM +NZ RFS" 3FF00000 00000001 3FF00000 00000001 +r 5750.10 +*Want "ADBR/ADB RM -NZ RNTE" BFF00000 00000000 BFF00000 00000000 +r 5760.10 +*Want "ADBR/ADB RM -NZ RZ" BFF00000 00000000 BFF00000 00000000 +r 5770.10 +*Want "ADBR/ADB RM -NZ RP" BFF00000 00000000 BFF00000 00000000 +r 5780.10 +*Want "ADBR/ADB RM -NZ RM" BFF00000 00000001 BFF00000 00000001 +r 5790.10 +*Want "ADBR/ADB RM -NZ RFS" BFF00000 00000001 BFF00000 00000001 +r 57A0.10 +*Want "ADBR/ADB RM +NA RNTE" 3FF00000 00000001 3FF00000 00000001 +r 57B0.10 +*Want "ADBR/ADB RM +NA RZ" 3FF00000 00000000 3FF00000 00000000 +r 57C0.10 +*Want "ADBR/ADB RM +NA RP" 3FF00000 00000001 3FF00000 00000001 +r 57D0.10 +*Want "ADBR/ADB RM +NA RM" 3FF00000 00000000 3FF00000 00000000 +r 57E0.10 +*Want "ADBR/ADB RM +NA RFS" 3FF00000 00000001 3FF00000 00000001 +r 57F0.10 +*Want "ADBR/ADB RM -NA RNTE" BFF00000 00000001 BFF00000 00000001 +r 5800.10 +*Want "ADBR/ADB RM -NA RZ" BFF00000 00000000 BFF00000 00000000 +r 5810.10 +*Want "ADBR/ADB RM -NA RP" BFF00000 00000000 BFF00000 00000000 +r 5820.10 +*Want "ADBR/ADB RM -NA RM" BFF00000 00000001 BFF00000 00000001 +r 5830.10 +*Want "ADBR/ADB RM -NA RFS" BFF00000 00000001 BFF00000 00000001 +r 5840.10 +*Want "ADBR/ADB RM +TZ RNTE" 3FF00000 00000000 3FF00000 00000000 +r 5850.10 +*Want "ADBR/ADB RM +TZ RZ" 3FF00000 00000000 3FF00000 00000000 +r 5860.10 +*Want "ADBR/ADB RM +TZ RP" 3FF00000 00000001 3FF00000 00000001 +r 5870.10 +*Want "ADBR/ADB RM +TZ RM" 3FF00000 00000000 3FF00000 00000000 +r 5880.10 +*Want "ADBR/ADB RM +TZ RFS" 3FF00000 00000001 3FF00000 00000001 +r 5890.10 +*Want "ADBR/ADB RM -TZ RNTE" BFF00000 00000000 BFF00000 00000000 +r 58A0.10 +*Want "ADBR/ADB RM -TZ RZ" BFF00000 00000000 BFF00000 00000000 +r 58B0.10 +*Want "ADBR/ADB RM -TZ RP" BFF00000 00000000 BFF00000 00000000 +r 58C0.10 +*Want "ADBR/ADB RM -TZ RM" BFF00000 00000001 BFF00000 00000001 +r 58D0.10 +*Want "ADBR/ADB RM -TZ RFS" BFF00000 00000001 BFF00000 00000001 +r 58E0.10 +*Want "ADBR/ADB RM +TA RNTE" 3FF00000 00000002 3FF00000 00000002 +r 58F0.10 +*Want "ADBR/ADB RM +TA RZ" 3FF00000 00000001 3FF00000 00000001 +r 5900.10 +*Want "ADBR/ADB RM +TA RP" 3FF00000 00000002 3FF00000 00000002 +r 5910.10 +*Want "ADBR/ADB RM +TA RM" 3FF00000 00000001 3FF00000 00000001 +r 5920.10 +*Want "ADBR/ADB RM +TA RFS" 3FF00000 00000001 3FF00000 00000001 +r 5930.10 +*Want "ADBR/ADB RM -TA RNTE" BFF00000 00000002 BFF00000 00000002 +r 5940.10 +*Want "ADBR/ADB RM -TA RZ" BFF00000 00000001 BFF00000 00000001 +r 5950.10 +*Want "ADBR/ADB RM -TA RP" BFF00000 00000001 BFF00000 00000001 +r 5960.10 +*Want "ADBR/ADB RM -TA RM" BFF00000 00000002 BFF00000 00000002 +r 5970.10 +*Want "ADBR/ADB RM -TA RFS" BFF00000 00000001 BFF00000 00000001 + + +r 5C00.10 +*Want "ADBR/ADB RM +NZ RNTE, RZ FPCR" 00080002 00080002 00080002 00080002 +r 5C10.10 +*Want "ADBR/ADB RM +NZ RP, RM FPCR" 00080002 00080002 00080002 00080002 +r 5C20.8 +*Want "ADBR/ADB RM +NZ RFS FPCR" 00080002 00080002 +r 5C30.10 +*Want "ADBR/ADB RM +NZ RNTE, RZ FPCR" 00080001 00080001 00080001 00080001 +r 5C40.10 +*Want "ADBR/ADB RM +NZ RP, RM FPCR" 00080001 00080001 00080001 00080001 +r 5C50.8 +*Want "ADBR/ADB RM -NZ RFS FPCR" 00080001 00080001 +r 5C60.10 +*Want "ADBR/ADB RM -NZ RNTE, RZ FPCR" 00080002 00080002 00080002 00080002 +r 5C70.10 +*Want "ADBR/ADB RM -NZ RP, RM FPCR" 00080002 00080002 00080002 00080002 +r 5C80.8 +*Want "ADBR/ADB RM -NZ RFS FPCR" 00080002 00080002 +r 5C90.10 +*Want "ADBR/ADB RM -NZ RNTE, RZ FPCR" 00080001 00080001 00080001 00080001 +r 5CA0.10 +*Want "ADBR/ADB RM -NA RP, RM FPCR" 00080001 00080001 00080001 00080001 +r 5CB0.8 +*Want "ADBR/ADB RM -NA RFS FPCR" 00080001 00080001 +r 5CC0.10 +*Want "ADBR/ADB RM +TZ RNTE, RZ FPCR" 00080002 00080002 00080002 00080002 +r 5CD0.10 +*Want "ADBR/ADB RM +TZ RP, RM FPCR" 00080002 00080002 00080002 00080002 +r 5CE0.8 +*Want "ADBR/ADB RM +TZ RFS FPCR" 00080002 00080002 +r 5CF0.10 +*Want "ADBR/ADB RM -TZ RNTE, RZ FPCR" 00080001 00080001 00080001 00080001 +r 5D00.10 +*Want "ADBR/ADB RM -TZ RP, RM FPCR" 00080001 00080001 00080001 00080001 +r 5D10.8 +*Want "ADBR/ADB RM -TZ RFS FPCR" 00080001 00080001 +r 5D20.10 +*Want "ADBR/ADB RM +TA RNTE, RZ FPCR" 00080002 00080002 00080002 00080002 +r 5D30.10 +*Want "ADBR/ADB RM +TA RP, RM FPCR" 00080002 00080002 00080002 00080002 +r 5D40.8 +*Want "ADBR/ADB RM +TA RFS FPCR" 00080002 00080002 +r 5D50.10 +*Want "ADBR/ADB RM -TA RNTE, RZ FPCR" 00080001 00080001 00080001 00080001 +r 5D60.10 +*Want "ADBR/ADB RM -TA RP, RM FPCR" 00080001 00080001 00080001 00080001 +r 5D70.8 +*Want "ADBR/ADB RM -TA RFS FPCR" 00080001 00080001 + + +r 8000.10 +*Want "AXBR NF -inf/-inf NT" FFFF0000 00000000 00000000 00000000 +r 8010.10 +*Want "AXBR NF -inf/-inf Tr" FFFF0000 00000000 00000000 00000000 +r 8020.10 +*Want "AXBR NF -inf/-2.0 NT" FFFF0000 00000000 00000000 00000000 +r 8030.10 +*Want "AXBR NF -inf/-2.0 Tr" FFFF0000 00000000 00000000 00000000 +r 8040.10 +*Want "AXBR NF -inf/-Dnice NT" FFFF0000 00000000 00000000 00000000 +r 8050.10 +*Want "AXBR NF -inf/-Dnice Tr" FFFF0000 00000000 00000000 00000000 +r 8060.10 +*Want "AXBR NF -inf/-0 NT" FFFF0000 00000000 00000000 00000000 +r 8070.10 +*Want "AXBR NF -inf/-0 Tr" FFFF0000 00000000 00000000 00000000 +r 8080.10 +*Want "AXBR NF -inf/+0 NT" FFFF0000 00000000 00000000 00000000 +r 8090.10 +*Want "AXBR NF -inf/+0 Tr" FFFF0000 00000000 00000000 00000000 +r 80A0.10 +*Want "AXBR NF -inf/+Dnice NT" FFFF0000 00000000 00000000 00000000 +r 80B0.10 +*Want "AXBR NF -inf/+Dnice Tr" FFFF0000 00000000 00000000 00000000 +r 80C0.10 +*Want "AXBR NF -inf/+2.0 NT" FFFF0000 00000000 00000000 00000000 +r 80D0.10 +*Want "AXBR NF -inf/+2.0 Tr" FFFF0000 00000000 00000000 00000000 +r 80E0.10 +*Want "AXBR NF -inf/+inf NT" 7FFF8000 00000000 00000000 00000000 +r 80F0.10 +*Want "AXBR NF -inf/+inf Tr" FFFF0000 00000000 00000000 00000000 +r 8100.10 +*Want "AXBR NF -inf/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 8110.10 +*Want "AXBR NF -inf/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 8120.10 +*Want "AXBR NF -inf/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 8130.10 +*Want "AXBR NF -inf/+SNaN Tr" FFFF0000 00000000 00000000 00000000 +r 8140.10 +*Want "AXBR NF -2.0/-inf NT" FFFF0000 00000000 00000000 00000000 +r 8150.10 +*Want "AXBR NF -2.0/-inf Tr" FFFF0000 00000000 00000000 00000000 +r 8160.10 +*Want "AXBR NF -2.0/-2.0 NT" C0010000 00000000 00000000 00000000 +r 8170.10 +*Want "AXBR NF -2.0/-2.0 Tr" C0010000 00000000 00000000 00000000 +r 8180.10 +*Want "AXBR NF -2.0/-Dnice NT" C0000000 00000000 00000000 00000000 +r 8190.10 +*Want "AXBR NF -2.0/-Dnice Tr" C0000000 00000000 00000000 00000000 +r 81A0.10 +*Want "AXBR NF -2.0/-0 NT" C0000000 00000000 00000000 00000000 +r 81B0.10 +*Want "AXBR NF -2.0/-0 Tr" C0000000 00000000 00000000 00000000 +r 81C0.10 +*Want "AXBR NF -2.0/+0 NT" C0000000 00000000 00000000 00000000 +r 81D0.10 +*Want "AXBR NF -2.0/+0 Tr" C0000000 00000000 00000000 00000000 +r 81E0.10 +*Want "AXBR NF -2.0/+Dnice NT" C0000000 00000000 00000000 00000000 +r 81F0.10 +*Want "AXBR NF -2.0/+Dnice Tr" C0000000 00000000 00000000 00000000 +r 8200.10 +*Want "AXBR NF -2.0/+2.0 NT" 00000000 00000000 00000000 00000000 +r 8210.10 +*Want "AXBR NF -2.0/+2.0 Tr" 00000000 00000000 00000000 00000000 +r 8220.10 +*Want "AXBR NF -2.0/+inf NT" 7FFF0000 00000000 00000000 00000000 +r 8230.10 +*Want "AXBR NF -2.0/+inf Tr" 7FFF0000 00000000 00000000 00000000 +r 8240.10 +*Want "AXBR NF -2.0/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 8250.10 +*Want "AXBR NF -2.0/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 8260.10 +*Want "AXBR NF -2.0/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 8270.10 +*Want "AXBR NF -2.0/+SNaN Tr" C0000000 00000000 00000000 00000000 +r 8280.10 +*Want "AXBR NF -Dnice/-inf NT" FFFF0000 00000000 00000000 00000000 +r 8290.10 +*Want "AXBR NF -Dnice/-inf Tr" FFFF0000 00000000 00000000 00000000 +r 82A0.10 +*Want "AXBR NF -Dnice/-2.0 NT" C0000000 00000000 00000000 00000000 +r 82B0.10 +*Want "AXBR NF -Dnice/-2.0 Tr" C0000000 00000000 00000000 00000000 +r 82C0.10 +*Want "AXBR NF -Dnice/-Dnice NT" 80002000 00000000 00000000 00000000 +r 82D0.10 +*Want "AXBR NF -Dnice/-Dnice Tr" DFFE0000 00000000 00000000 00000000 +r 82E0.10 +*Want "AXBR NF -Dnice/-0 NT" 80001000 00000000 00000000 00000000 +r 82F0.10 +*Want "AXBR NF -Dnice/-0 Tr" DFFD0000 00000000 00000000 00000000 +r 8300.10 +*Want "AXBR NF -Dnice/+0 NT" 80001000 00000000 00000000 00000000 +r 8310.10 +*Want "AXBR NF -Dnice/+0 Tr" DFFD0000 00000000 00000000 00000000 +r 8320.10 +*Want "AXBR NF -Dnice/+Dnice NT" 00000000 00000000 00000000 00000000 +r 8330.10 +*Want "AXBR NF -Dnice/+Dnice Tr" 00000000 00000000 00000000 00000000 +r 8340.10 +*Want "AXBR NF -Dnice/+2.0 NT" 40000000 00000000 00000000 00000000 +r 8350.10 +*Want "AXBR NF -Dnice/+2.0 Tr" 40000000 00000000 00000000 00000000 +r 8360.10 +*Want "AXBR NF -Dnice/+inf NT" 7FFF0000 00000000 00000000 00000000 +r 8370.10 +*Want "AXBR NF -Dnice/+inf Tr" 7FFF0000 00000000 00000000 00000000 +r 8380.10 +*Want "AXBR NF -Dnice/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 8390.10 +*Want "AXBR NF -Dnice/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 83A0.10 +*Want "AXBR NF -Dnice/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 83B0.10 +*Want "AXBR NF -Dnice/+SNaN Tr" 80001000 00000000 00000000 00000000 +r 83C0.10 +*Want "AXBR NF -0/-inf NT" FFFF0000 00000000 00000000 00000000 +r 83D0.10 +*Want "AXBR NF -0/-inf Tr" FFFF0000 00000000 00000000 00000000 +r 83E0.10 +*Want "AXBR NF -0/-2.0 NT" C0000000 00000000 00000000 00000000 +r 83F0.10 +*Want "AXBR NF -0/-2.0 Tr" C0000000 00000000 00000000 00000000 +r 8400.10 +*Want "AXBR NF -0/-Dnice NT" 80001000 00000000 00000000 00000000 +r 8410.10 +*Want "AXBR NF -0/-Dnice Tr" DFFD0000 00000000 00000000 00000000 +r 8420.10 +*Want "AXBR NF -0/-0 NT" 80000000 00000000 00000000 00000000 +r 8430.10 +*Want "AXBR NF -0/-0 Tr" 80000000 00000000 00000000 00000000 +r 8440.10 +*Want "AXBR NF -0/+0 NT" 00000000 00000000 00000000 00000000 +r 8450.10 +*Want "AXBR NF -0/+0 Tr" 00000000 00000000 00000000 00000000 +r 8460.10 +*Want "AXBR NF -0/+Dnice NT" 00001000 00000000 00000000 00000000 +r 8470.10 +*Want "AXBR NF -0/+Dnice Tr" 5FFD0000 00000000 00000000 00000000 +r 8480.10 +*Want "AXBR NF -0/+2.0 NT" 40000000 00000000 00000000 00000000 +r 8490.10 +*Want "AXBR NF -0/+2.0 Tr" 40000000 00000000 00000000 00000000 +r 84A0.10 +*Want "AXBR NF -0/+inf NT" 7FFF0000 00000000 00000000 00000000 +r 84B0.10 +*Want "AXBR NF -0/+inf Tr" 7FFF0000 00000000 00000000 00000000 +r 84C0.10 +*Want "AXBR NF -0/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 84D0.10 +*Want "AXBR NF -0/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 84E0.10 +*Want "AXBR NF -0/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 84F0.10 +*Want "AXBR NF -0/+SNaN Tr" 80000000 00000000 00000000 00000000 +r 8500.10 +*Want "AXBR NF +0/-inf NT" FFFF0000 00000000 00000000 00000000 +r 8510.10 +*Want "AXBR NF +0/-inf Tr" FFFF0000 00000000 00000000 00000000 +r 8520.10 +*Want "AXBR NF +0/-2.0 NT" C0000000 00000000 00000000 00000000 +r 8530.10 +*Want "AXBR NF +0/-2.0 Tr" C0000000 00000000 00000000 00000000 +r 8540.10 +*Want "AXBR NF +0/-Dnice NT" 80001000 00000000 00000000 00000000 +r 8550.10 +*Want "AXBR NF +0/-Dnice Tr" DFFD0000 00000000 00000000 00000000 +r 8560.10 +*Want "AXBR NF +0/-0 NT" 00000000 00000000 00000000 00000000 +r 8570.10 +*Want "AXBR NF +0/-0 Tr" 00000000 00000000 00000000 00000000 +r 8580.10 +*Want "AXBR NF +0/+0 NT" 00000000 00000000 00000000 00000000 +r 8590.10 +*Want "AXBR NF +0/+0 Tr" 00000000 00000000 00000000 00000000 +r 85A0.10 +*Want "AXBR NF +0/+Dnice NT" 00001000 00000000 00000000 00000000 +r 85B0.10 +*Want "AXBR NF +0/+Dnice Tr" 5FFD0000 00000000 00000000 00000000 +r 85C0.10 +*Want "AXBR NF +0/+2.0 NT" 40000000 00000000 00000000 00000000 +r 85D0.10 +*Want "AXBR NF +0/+2.0 Tr" 40000000 00000000 00000000 00000000 +r 85E0.10 +*Want "AXBR NF +0/+inf NT" 7FFF0000 00000000 00000000 00000000 +r 85F0.10 +*Want "AXBR NF +0/+inf Tr" 7FFF0000 00000000 00000000 00000000 +r 8600.10 +*Want "AXBR NF +0/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 8610.10 +*Want "AXBR NF +0/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 8620.10 +*Want "AXBR NF +0/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 8630.10 +*Want "AXBR NF +0/+SNaN Tr" 00000000 00000000 00000000 00000000 +r 8640.10 +*Want "AXBR NF +Dnice/-inf NT" FFFF0000 00000000 00000000 00000000 +r 8650.10 +*Want "AXBR NF +Dnice/-inf Tr" FFFF0000 00000000 00000000 00000000 +r 8660.10 +*Want "AXBR NF +Dnice/-2.0 NT" C0000000 00000000 00000000 00000000 +r 8670.10 +*Want "AXBR NF +Dnice/-2.0 Tr" C0000000 00000000 00000000 00000000 +r 8680.10 +*Want "AXBR NF +Dnice/-Dnice NT" 00000000 00000000 00000000 00000000 +r 8690.10 +*Want "AXBR NF +Dnice/-Dnice Tr" 00000000 00000000 00000000 00000000 +r 86A0.10 +*Want "AXBR NF +Dnice/-0 NT" 00001000 00000000 00000000 00000000 +r 86B0.10 +*Want "AXBR NF +Dnice/-0 Tr" 5FFD0000 00000000 00000000 00000000 +r 86C0.10 +*Want "AXBR NF +Dnice/+0 NT" 00001000 00000000 00000000 00000000 +r 86D0.10 +*Want "AXBR NF +Dnice/+0 Tr" 5FFD0000 00000000 00000000 00000000 +r 86E0.10 +*Want "AXBR NF +Dnice/+Dnice NT" 00002000 00000000 00000000 00000000 +r 86F0.10 +*Want "AXBR NF +Dnice/+Dnice Tr" 5FFE0000 00000000 00000000 00000000 +r 8700.10 +*Want "AXBR NF +Dnice/+2.0 NT" 40000000 00000000 00000000 00000000 +r 8710.10 +*Want "AXBR NF +Dnice/+2.0 Tr" 40000000 00000000 00000000 00000000 +r 8720.10 +*Want "AXBR NF +Dnice/+inf NT" 7FFF0000 00000000 00000000 00000000 +r 8730.10 +*Want "AXBR NF +Dnice/+inf Tr" 7FFF0000 00000000 00000000 00000000 +r 8740.10 +*Want "AXBR NF +Dnice/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 8750.10 +*Want "AXBR NF +Dnice/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 8760.10 +*Want "AXBR NF +Dnice/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 8770.10 +*Want "AXBR NF +Dnice/+SNaN Tr" 00001000 00000000 00000000 00000000 +r 8780.10 +*Want "AXBR NF +2.0/-inf NT" FFFF0000 00000000 00000000 00000000 +r 8790.10 +*Want "AXBR NF +2.0/-inf Tr" FFFF0000 00000000 00000000 00000000 +r 87A0.10 +*Want "AXBR NF +2.0/-2.0 NT" 00000000 00000000 00000000 00000000 +r 87B0.10 +*Want "AXBR NF +2.0/-2.0 Tr" 00000000 00000000 00000000 00000000 +r 87C0.10 +*Want "AXBR NF +2.0/-Dnice NT" 40000000 00000000 00000000 00000000 +r 87D0.10 +*Want "AXBR NF +2.0/-Dnice Tr" 40000000 00000000 00000000 00000000 +r 87E0.10 +*Want "AXBR NF +2.0/-0 NT" 40000000 00000000 00000000 00000000 +r 87F0.10 +*Want "AXBR NF +2.0/-0 Tr" 40000000 00000000 00000000 00000000 +r 8800.10 +*Want "AXBR NF +2.0/+0 NT" 40000000 00000000 00000000 00000000 +r 8810.10 +*Want "AXBR NF +2.0/+0 Tr" 40000000 00000000 00000000 00000000 +r 8820.10 +*Want "AXBR NF +2.0/+Dnice NT" 40000000 00000000 00000000 00000000 +r 8830.10 +*Want "AXBR NF +2.0/+Dnice Tr" 40000000 00000000 00000000 00000000 +r 8840.10 +*Want "AXBR NF +2.0/+2.0 NT" 40010000 00000000 00000000 00000000 +r 8850.10 +*Want "AXBR NF +2.0/+2.0 Tr" 40010000 00000000 00000000 00000000 +r 8860.10 +*Want "AXBR NF +2.0/+inf NT" 7FFF0000 00000000 00000000 00000000 +r 8870.10 +*Want "AXBR NF +2.0/+inf Tr" 7FFF0000 00000000 00000000 00000000 +r 8880.10 +*Want "AXBR NF +2.0/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 8890.10 +*Want "AXBR NF +2.0/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 88A0.10 +*Want "AXBR NF +2.0/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 88B0.10 +*Want "AXBR NF +2.0/+SNaN Tr" 40000000 00000000 00000000 00000000 +r 88C0.10 +*Want "AXBR NF +inf/-inf NT" 7FFF8000 00000000 00000000 00000000 +r 88D0.10 +*Want "AXBR NF +inf/-inf Tr" 7FFF0000 00000000 00000000 00000000 +r 88E0.10 +*Want "AXBR NF +inf/-2.0 NT" 7FFF0000 00000000 00000000 00000000 +r 88F0.10 +*Want "AXBR NF +inf/-2.0 Tr" 7FFF0000 00000000 00000000 00000000 +r 8900.10 +*Want "AXBR NF +inf/-Dnice NT" 7FFF0000 00000000 00000000 00000000 +r 8910.10 +*Want "AXBR NF +inf/-Dnice Tr" 7FFF0000 00000000 00000000 00000000 +r 8920.10 +*Want "AXBR NF +inf/-0 NT" 7FFF0000 00000000 00000000 00000000 +r 8930.10 +*Want "AXBR NF +inf/-0 Tr" 7FFF0000 00000000 00000000 00000000 +r 8940.10 +*Want "AXBR NF +inf/+0 NT" 7FFF0000 00000000 00000000 00000000 +r 8950.10 +*Want "AXBR NF +inf/+0 Tr" 7FFF0000 00000000 00000000 00000000 +r 8960.10 +*Want "AXBR NF +inf/+Dnice NT" 7FFF0000 00000000 00000000 00000000 +r 8970.10 +*Want "AXBR NF +inf/+Dnice Tr" 7FFF0000 00000000 00000000 00000000 +r 8980.10 +*Want "AXBR NF +inf/+2.0 NT" 7FFF0000 00000000 00000000 00000000 +r 8990.10 +*Want "AXBR NF +inf/+2.0 Tr" 7FFF0000 00000000 00000000 00000000 +r 89A0.10 +*Want "AXBR NF +inf/+inf NT" 7FFF0000 00000000 00000000 00000000 +r 89B0.10 +*Want "AXBR NF +inf/+inf Tr" 7FFF0000 00000000 00000000 00000000 +r 89C0.10 +*Want "AXBR NF +inf/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 89D0.10 +*Want "AXBR NF +inf/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 89E0.10 +*Want "AXBR NF +inf/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 89F0.10 +*Want "AXBR NF +inf/+SNaN Tr" 7FFF0000 00000000 00000000 00000000 +r 8A00.10 +*Want "AXBR NF -QNaN/-inf NT" FFFF8B00 00000000 00000000 00000000 +r 8A10.10 +*Want "AXBR NF -QNaN/-inf Tr" FFFF8B00 00000000 00000000 00000000 +r 8A20.10 +*Want "AXBR NF -QNaN/-2.0 NT" FFFF8B00 00000000 00000000 00000000 +r 8A30.10 +*Want "AXBR NF -QNaN/-2.0 Tr" FFFF8B00 00000000 00000000 00000000 +r 8A40.10 +*Want "AXBR NF -QNaN/-Dnice NT" FFFF8B00 00000000 00000000 00000000 +r 8A50.10 +*Want "AXBR NF -QNaN/-Dnice Tr" FFFF8B00 00000000 00000000 00000000 +r 8A60.10 +*Want "AXBR NF -QNaN/-0 NT" FFFF8B00 00000000 00000000 00000000 +r 8A70.10 +*Want "AXBR NF -QNaN/-0 Tr" FFFF8B00 00000000 00000000 00000000 +r 8A80.10 +*Want "AXBR NF -QNaN/+0 NT" FFFF8B00 00000000 00000000 00000000 +r 8A90.10 +*Want "AXBR NF -QNaN/+0 Tr" FFFF8B00 00000000 00000000 00000000 +r 8AA0.10 +*Want "AXBR NF -QNaN/+Dnice NT" FFFF8B00 00000000 00000000 00000000 +r 8AB0.10 +*Want "AXBR NF -QNaN/+Dnice Tr" FFFF8B00 00000000 00000000 00000000 +r 8AC0.10 +*Want "AXBR NF -QNaN/+2.0 NT" FFFF8B00 00000000 00000000 00000000 +r 8AD0.10 +*Want "AXBR NF -QNaN/+2.0 Tr" FFFF8B00 00000000 00000000 00000000 +r 8AE0.10 +*Want "AXBR NF -QNaN/+inf NT" FFFF8B00 00000000 00000000 00000000 +r 8AF0.10 +*Want "AXBR NF -QNaN/+inf Tr" FFFF8B00 00000000 00000000 00000000 +r 8B00.10 +*Want "AXBR NF -QNaN/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 8B10.10 +*Want "AXBR NF -QNaN/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 8B20.10 +*Want "AXBR NF -QNaN/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 8B30.10 +*Want "AXBR NF -QNaN/+SNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 8B40.10 +*Want "AXBR NF +SNaN/-inf NT" 7FFF8A00 00000000 00000000 00000000 +r 8B50.10 +*Want "AXBR NF +SNaN/-inf Tr" 7FFF0A00 00000000 00000000 00000000 +r 8B60.10 +*Want "AXBR NF +SNaN/-2.0 NT" 7FFF8A00 00000000 00000000 00000000 +r 8B70.10 +*Want "AXBR NF +SNaN/-2.0 Tr" 7FFF0A00 00000000 00000000 00000000 +r 8B80.10 +*Want "AXBR NF +SNaN/-Dnice NT" 7FFF8A00 00000000 00000000 00000000 +r 8B90.10 +*Want "AXBR NF +SNaN/-Dnice Tr" 7FFF0A00 00000000 00000000 00000000 +r 8BA0.10 +*Want "AXBR NF +SNaN/-0 NT" 7FFF8A00 00000000 00000000 00000000 +r 8BB0.10 +*Want "AXBR NF +SNaN/-0 Tr" 7FFF0A00 00000000 00000000 00000000 +r 8BC0.10 +*Want "AXBR NF +SNaN/+0 NT" 7FFF8A00 00000000 00000000 00000000 +r 8BD0.10 +*Want "AXBR NF +SNaN/+0 Tr" 7FFF0A00 00000000 00000000 00000000 +r 8BE0.10 +*Want "AXBR NF +SNaN/+Dnice NT" 7FFF8A00 00000000 00000000 00000000 +r 8BF0.10 +*Want "AXBR NF +SNaN/+Dnice Tr" 7FFF0A00 00000000 00000000 00000000 +r 8C00.10 +*Want "AXBR NF +SNaN/+2.0 NT" 7FFF8A00 00000000 00000000 00000000 +r 8C10.10 +*Want "AXBR NF +SNaN/+2.0 Tr" 7FFF0A00 00000000 00000000 00000000 +r 8C20.10 +*Want "AXBR NF +SNaN/+inf NT" 7FFF8A00 00000000 00000000 00000000 +r 8C30.10 +*Want "AXBR NF +SNaN/+inf Tr" 7FFF0A00 00000000 00000000 00000000 +r 8C40.10 +*Want "AXBR NF +SNaN/-QNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 8C50.10 +*Want "AXBR NF +SNaN/-QNaN Tr" 7FFF0A00 00000000 00000000 00000000 +r 8C60.10 +*Want "AXBR NF +SNaN/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 8C70.10 +*Want "AXBR NF +SNaN/+SNaN Tr" 7FFF0A00 00000000 00000000 00000000 + + +r 8D00.8 +*Want "AXBR NF -inf/-inf FPCR" 00000001 F8000001 +r 8D10.8 +*Want "AXBR NF -inf/-2.0 FPCR" 00000001 F8000001 +r 8D20.8 +*Want "AXBR NF -inf/-Dnice FPCR" 00000001 F8000001 +r 8D30.8 +*Want "AXBR NF -inf/-0 FPCR" 00000001 F8000001 +r 8D40.8 +*Want "AXBR NF -inf/+0 FPCR" 00000001 F8000001 +r 8D50.8 +*Want "AXBR NF -inf/+Dnice FPCR" 00000001 F8000001 +r 8D60.8 +*Want "AXBR NF -inf/+2.0 FPCR" 00000001 F8000001 +r 8D70.8 +*Want "AXBR NF -inf/+inf FPCR" 00800003 F8008003 +r 8D80.8 +*Want "AXBR NF -inf/-QNaN FPCR" 00000003 F8000003 +r 8D90.8 +*Want "AXBR NF -inf/+SNaN FPCR" 00800003 F8008003 +r 8DA0.8 +*Want "AXBR NF -2.0/-inf FPCR" 00000001 F8000001 +r 8DB0.8 +*Want "AXBR NF -2.0/-2.0 FPCR" 00000001 F8000001 +r 8DC0.8 +*Want "AXBR NF -2.0/-Dnice FPCR" 00080001 F8000801 +r 8DD0.8 +*Want "AXBR NF -2.0/-0 FPCR" 00000001 F8000001 +r 8DE0.8 +*Want "AXBR NF -2.0/+0 FPCR" 00000001 F8000001 +r 8DF0.8 +*Want "AXBR NF -2.0/+Dnice FPCR" 00080001 F8000C01 +r 8E00.8 +*Want "AXBR NF -2.0/+2.0 FPCR" 00000000 F8000000 +r 8E10.8 +*Want "AXBR NF -2.0/+inf FPCR" 00000002 F8000002 +r 8E20.8 +*Want "AXBR NF -2.0/-QNaN FPCR" 00000003 F8000003 +r 8E30.8 +*Want "AXBR NF -2.0/+SNaN FPCR" 00800003 F8008003 +r 8E40.8 +*Want "AXBR NF -Dnice/-inf FPCR" 00000001 F8000001 +r 8E50.8 +*Want "AXBR NF -Dnice/-2.0 FPCR" 00080001 F8000801 +r 8E60.8 +*Want "AXBR NF -Dnice/-Dnice FPCR" 00000001 F8001001 +r 8E70.8 +*Want "AXBR NF -Dnice/-0 FPCR" 00000001 F8001001 +r 8E80.8 +*Want "AXBR NF -Dnice/+0 FPCR" 00000001 F8001001 +r 8E90.8 +*Want "AXBR NF -Dnice/+Dnice FPCR" 00000000 F8000000 +r 8EA0.8 +*Want "AXBR NF -Dnice/+2.0 FPCR" 00080002 F8000C02 +r 8EB0.8 +*Want "AXBR NF -Dnice/+inf FPCR" 00000002 F8000002 +r 8EC0.8 +*Want "AXBR NF -Dnice/-QNaN FPCR" 00000003 F8000003 +r 8ED0.8 +*Want "AXBR NF -Dnice/+SNaN FPCR" 00800003 F8008003 +r 8EE0.8 +*Want "AXBR NF -0/-inf FPCR" 00000001 F8000001 +r 8EF0.8 +*Want "AXBR NF -0/-2.0 FPCR" 00000001 F8000001 +r 8F00.8 +*Want "AXBR NF -0/-Dnice FPCR" 00000001 F8001001 +r 8F10.8 +*Want "AXBR NF -0/-0 FPCR" 00000000 F8000000 +r 8F20.8 +*Want "AXBR NF -0/+0 FPCR" 00000000 F8000000 +r 8F30.8 +*Want "AXBR NF -0/+Dnice FPCR" 00000002 F8001002 +r 8F40.8 +*Want "AXBR NF -0/+2.0 FPCR" 00000002 F8000002 +r 8F50.8 +*Want "AXBR NF -0/+inf FPCR" 00000002 F8000002 +r 8F60.8 +*Want "AXBR NF -0/-QNaN FPCR" 00000003 F8000003 +r 8F70.8 +*Want "AXBR NF -0/+SNaN FPCR" 00800003 F8008003 +r 8F80.8 +*Want "AXBR NF +0/-inf FPCR" 00000001 F8000001 +r 8F90.8 +*Want "AXBR NF +0/-2.0 FPCR" 00000001 F8000001 +r 8FA0.8 +*Want "AXBR NF +0/-Dnice FPCR" 00000001 F8001001 +r 8FB0.8 +*Want "AXBR NF +0/-0 FPCR" 00000000 F8000000 +r 8FC0.8 +*Want "AXBR NF +0/+0 FPCR" 00000000 F8000000 +r 8FD0.8 +*Want "AXBR NF +0/+Dnice FPCR" 00000002 F8001002 +r 8FE0.8 +*Want "AXBR NF +0/+2.0 FPCR" 00000002 F8000002 +r 8FF0.8 +*Want "AXBR NF +0/+inf FPCR" 00000002 F8000002 +r 9000.8 +*Want "AXBR NF +0/-QNaN FPCR" 00000003 F8000003 +r 9010.8 +*Want "AXBR NF +0/+SNaN FPCR" 00800003 F8008003 +r 9020.8 +*Want "AXBR NF +Dnice/-inf FPCR" 00000001 F8000001 +r 9030.8 +*Want "AXBR NF +Dnice/-2.0 FPCR" 00080001 F8000C01 +r 9040.8 +*Want "AXBR NF +Dnice/-Dnice FPCR" 00000000 F8000000 +r 9050.8 +*Want "AXBR NF +Dnice/-0 FPCR" 00000002 F8001002 +r 9060.8 +*Want "AXBR NF +Dnice/+0 FPCR" 00000002 F8001002 +r 9070.8 +*Want "AXBR NF +Dnice/+Dnice FPCR" 00000002 F8001002 +r 9080.8 +*Want "AXBR NF +Dnice/+2.0 FPCR" 00080002 F8000802 +r 9090.8 +*Want "AXBR NF +Dnice/+inf FPCR" 00000002 F8000002 +r 90A0.8 +*Want "AXBR NF +Dnice/-QNaN FPCR" 00000003 F8000003 +r 90B0.8 +*Want "AXBR NF +Dnice/+SNaN FPCR" 00800003 F8008003 +r 90C0.8 +*Want "AXBR NF +2.0/-inf FPCR" 00000001 F8000001 +r 90D0.8 +*Want "AXBR NF +2.0/-2.0 FPCR" 00000000 F8000000 +r 90E0.8 +*Want "AXBR NF +2.0/-Dnice FPCR" 00080002 F8000C02 +r 90F0.8 +*Want "AXBR NF +2.0/-0 FPCR" 00000002 F8000002 +r 9100.8 +*Want "AXBR NF +2.0/+0 FPCR" 00000002 F8000002 +r 9110.8 +*Want "AXBR NF +2.0/+Dnice FPCR" 00080002 F8000802 +r 9120.8 +*Want "AXBR NF +2.0/+2.0 FPCR" 00000002 F8000002 +r 9130.8 +*Want "AXBR NF +2.0/+inf FPCR" 00000002 F8000002 +r 9140.8 +*Want "AXBR NF +2.0/-QNaN FPCR" 00000003 F8000003 +r 9150.8 +*Want "AXBR NF +2.0/+SNaN FPCR" 00800003 F8008003 +r 9160.8 +*Want "AXBR NF +inf/-inf FPCR" 00800003 F8008003 +r 9170.8 +*Want "AXBR NF +inf/-2.0 FPCR" 00000002 F8000002 +r 9180.8 +*Want "AXBR NF +inf/-Dnice FPCR" 00000002 F8000002 +r 9190.8 +*Want "AXBR NF +inf/-0 FPCR" 00000002 F8000002 +r 91A0.8 +*Want "AXBR NF +inf/+0 FPCR" 00000002 F8000002 +r 91B0.8 +*Want "AXBR NF +inf/+Dnice FPCR" 00000002 F8000002 +r 91C0.8 +*Want "AXBR NF +inf/+2.0 FPCR" 00000002 F8000002 +r 91D0.8 +*Want "AXBR NF +inf/+inf FPCR" 00000002 F8000002 +r 91E0.8 +*Want "AXBR NF +inf/-QNaN FPCR" 00000003 F8000003 +r 91F0.8 +*Want "AXBR NF +inf/+SNaN FPCR" 00800003 F8008003 +r 9200.8 +*Want "AXBR NF -QNaN/-inf FPCR" 00000003 F8000003 +r 9210.8 +*Want "AXBR NF -QNaN/-2.0 FPCR" 00000003 F8000003 +r 9220.8 +*Want "AXBR NF -QNaN/-Dnice FPCR" 00000003 F8000003 +r 9230.8 +*Want "AXBR NF -QNaN/-0 FPCR" 00000003 F8000003 +r 9240.8 +*Want "AXBR NF -QNaN/+0 FPCR" 00000003 F8000003 +r 9250.8 +*Want "AXBR NF -QNaN/+Dnice FPCR" 00000003 F8000003 +r 9260.8 +*Want "AXBR NF -QNaN/+2.0 FPCR" 00000003 F8000003 +r 9270.8 +*Want "AXBR NF -QNaN/+inf FPCR" 00000003 F8000003 +r 9280.8 +*Want "AXBR NF -QNaN/-QNaN FPCR" 00000003 F8000003 +r 9290.8 +*Want "AXBR NF -QNaN/+SNaN FPCR" 00800003 F8008003 +r 92A0.8 +*Want "AXBR NF +SNaN/-inf FPCR" 00800003 F8008003 +r 92B0.8 +*Want "AXBR NF +SNaN/-2.0 FPCR" 00800003 F8008003 +r 92C0.8 +*Want "AXBR NF +SNaN/-Dnice FPCR" 00800003 F8008003 +r 92D0.8 +*Want "AXBR NF +SNaN/-0 FPCR" 00800003 F8008003 +r 92E0.8 +*Want "AXBR NF +SNaN/+0 FPCR" 00800003 F8008003 +r 92F0.8 +*Want "AXBR NF +SNaN/+Dnice FPCR" 00800003 F8008003 +r 9300.8 +*Want "AXBR NF +SNaN/+2.0 FPCR" 00800003 F8008003 +r 9310.8 +*Want "AXBR NF +SNaN/+inf FPCR" 00800003 F8008003 +r 9320.8 +*Want "AXBR NF +SNaN/-QNaN FPCR" 00800003 F8008003 +r 9330.8 +*Want "AXBR NF +SNaN/+SNaN FPCR" 00800003 F8008003 + + +r 9400.10 +*Want "AXBR F Ovfl NT" 7FFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 9410.10 +*Want "AXBR F Ovfl Tr" 7FFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 9420.10 +*Want "AXBR F Ufl 1 NT" 0000FFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 9430.10 +*Want "AXBR F Ufl 1 Tr" 6000FFFF FFFFFFFF FFFFFFFF FFFFFFFE +r 9440.10 +*Want "AXBR F Ufl 2 NT" 00008F0F 00000000 00000000 00000000 +r 9450.10 +*Want "AXBR F Ufl 2 Tr" 60001E1E 00000000 00000000 00000000 +r 9460.10 +*Want "AXBR F Nmin NT" 00010000 00000000 00000000 00000000 +r 9470.10 +*Want "AXBR F Nmin Tr" 00010000 00000000 00000000 00000000 +r 9480.10 +*Want "AXBR F Incr NT" 3FFF0000 00000000 00000000 00000001 +r 9490.10 +*Want "AXBR F Incr Tr" 3FFF0000 00000000 00000000 00000001 +r 94A0.10 +*Want "AXBR F Trun NT" 3FFF0000 00000000 00000000 00000000 +r 94B0.10 +*Want "AXBR F Trun Tr" 3FFF0000 00000000 00000000 00000000 + + +r 9600.08 +*Want "AXBR F Ovfl FPCR" 00000003 F8000003 +r 9610.08 +*Want "AXBR F Ufl 1 FPCR" 00000002 F8001002 +r 9620.08 +*Want "AXBR F Ufl 2 FPCR" 00000002 F8001002 +r 9630.08 +*Want "AXBR F Nmin FPCR" 00000002 F8000002 +r 9640.08 +*Want "AXBR F Incr FPCR" 00080002 F8000C02 +r 9650.08 +*Want "AXBR F Trun FPCR" 00080002 F8000802 + + +r 9700.10 +*Want "AXBR RM +NZ RNTE" 3FFF0000 00000000 00000000 00000000 +r 9710.10 +*Want "AXBR RM +NZ RZ" 3FFF0000 00000000 00000000 00000000 +r 9720.10 +*Want "AXBR RM +NZ RP" 3FFF0000 00000000 00000000 00000001 +r 9730.10 +*Want "AXBR RM +NZ RM" 3FFF0000 00000000 00000000 00000000 +r 9740.10 +*Want "AXBR RM +NZ RFS" 3FFF0000 00000000 00000000 00000001 +r 9750.10 +*Want "AXBR RM -NZ RNTE" BFFF0000 00000000 00000000 00000000 +r 9760.10 +*Want "AXBR RM -NZ RZ" BFFF0000 00000000 00000000 00000000 +r 9770.10 +*Want "AXBR RM -NZ RP" BFFF0000 00000000 00000000 00000000 +r 9780.10 +*Want "AXBR RM -NZ RM" BFFF0000 00000000 00000000 00000001 +r 9790.10 +*Want "AXBR RM -NZ RFS" BFFF0000 00000000 00000000 00000001 +r 97A0.10 +*Want "AXBR RM +NA RNTE" 3FFF0000 00000000 00000000 00000001 +r 97B0.10 +*Want "AXBR RM +NA RZ" 3FFF0000 00000000 00000000 00000000 +r 97C0.10 +*Want "AXBR RM +NA RP" 3FFF0000 00000000 00000000 00000001 +r 97D0.10 +*Want "AXBR RM +NA RM" 3FFF0000 00000000 00000000 00000000 +r 97E0.10 +*Want "AXBR RM +NA RFS" 3FFF0000 00000000 00000000 00000001 +r 97F0.10 +*Want "AXBR RM -NA RNTE" BFFF0000 00000000 00000000 00000001 +r 9800.10 +*Want "AXBR RM -NA RZ" BFFF0000 00000000 00000000 00000000 +r 9810.10 +*Want "AXBR RM -NA RP" BFFF0000 00000000 00000000 00000000 +r 9820.10 +*Want "AXBR RM -NA RM" BFFF0000 00000000 00000000 00000001 +r 9830.10 +*Want "AXBR RM -NA RFS" BFFF0000 00000000 00000000 00000001 +r 9840.10 +*Want "AXBR RM +TZ RNTE" 3FFF0000 00000000 00000000 00000000 +r 9850.10 +*Want "AXBR RM +TZ RZ" 3FFF0000 00000000 00000000 00000000 +r 9860.10 +*Want "AXBR RM +TZ RP" 3FFF0000 00000000 00000000 00000001 +r 9870.10 +*Want "AXBR RM +TZ RM" 3FFF0000 00000000 00000000 00000000 +r 9880.10 +*Want "AXBR RM +TZ RFS" 3FFF0000 00000000 00000000 00000001 +r 9890.10 +*Want "AXBR RM -TZ RNTE" BFFF0000 00000000 00000000 00000000 +r 98A0.10 +*Want "AXBR RM -TZ RZ" BFFF0000 00000000 00000000 00000000 +r 98B0.10 +*Want "AXBR RM -TZ RP" BFFF0000 00000000 00000000 00000000 +r 98C0.10 +*Want "AXBR RM -TZ RM" BFFF0000 00000000 00000000 00000001 +r 98D0.10 +*Want "AXBR RM -TZ RFS" BFFF0000 00000000 00000000 00000001 +r 98E0.10 +*Want "AXBR RM +TA RNTE" 3FFF0000 00000000 00000000 00000002 +r 98F0.10 +*Want "AXBR RM +TA RZ" 3FFF0000 00000000 00000000 00000001 +r 9900.10 +*Want "AXBR RM +TA RP" 3FFF0000 00000000 00000000 00000002 +r 9910.10 +*Want "AXBR RM +TA RM" 3FFF0000 00000000 00000000 00000001 +r 9920.10 +*Want "AXBR RM +TA RFS" 3FFF0000 00000000 00000000 00000001 +r 9930.10 +*Want "AXBR RM -TA RNTE" BFFF0000 00000000 00000000 00000002 +r 9940.10 +*Want "AXBR RM -TA RZ" BFFF0000 00000000 00000000 00000001 +r 9950.10 +*Want "AXBR RM -TA RP" BFFF0000 00000000 00000000 00000001 +r 9960.10 +*Want "AXBR RM -TA RM" BFFF0000 00000000 00000000 00000002 +r 9970.10 +*Want "AXBR RM -TA RFS" BFFF0000 00000000 00000000 00000001 + + + +r 9C00.10 +*Want "AXBR RM +NZ FPCR" 00080002 00080002 00080002 00080002 +r 9C10.04 +*Want "AXBR RM +NZ FPCR" 00080002 +r 9C20.10 +*Want "AXBR RM -NZ FPCR" 00080001 00080001 00080001 00080001 +r 9C30.04 +*Want "AXBR RM -NZ FPCR" 00080001 +r 9C40.10 +*Want "AXBR RM +NA FPCR" 00080002 00080002 00080002 00080002 +r 9C50.04 +*Want "AXBR RM +NA FPCR" 00080002 +r 9C60.10 +*Want "AXBR RM -NA FPCR" 00080001 00080001 00080001 00080001 +r 9C70.04 +*Want "AXBR RM -NA FPCR" 00080001 +r 9C80.10 +*Want "AXBR RM +TZ FPCR" 00080002 00080002 00080002 00080002 +r 9C90.04 +*Want "AXBR RM +TZ FPCR" 00080002 +r 9CA0.10 +*Want "AXBR RM -TZ FPCR" 00080001 00080001 00080001 00080001 +r 9CB0.04 +*Want "AXBR RM -TZ FPCR" 00080001 +r 9CC0.10 +*Want "AXBR RM +TA FPCR" 00080002 00080002 00080002 00080002 +r 9CD0.04 +*Want "AXBR RM +TA FPCR" 00080002 +r 9CE0.10 +*Want "AXBR RM -TA FPCR" 00080001 00080001 00080001 00080001 +r 9CF0.04 +*Want "AXBR RM -TA FPCR" 00080001 + + + + +*Done + diff --git a/tests/bfp-017-loadl.asm b/tests/bfp-017-loadl.asm new file mode 100644 index 000000000..d394f03d0 --- /dev/null +++ b/tests/bfp-017-loadl.asm @@ -0,0 +1,682 @@ + TITLE 'bfp-017-loadl.asm: Test IEEE Load Lengthened' +*********************************************************************** +* +*Testcase IEEE LOAD LENGTHENED +* Test case capability includes IEEE exceptions trappable and +* otherwise. Test results, FPCR flags, and any DXC are saved for all +* tests. Load Lengthened does not set the condition code. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* bfp-017-loadl.asm +* +* This assembly-language source file is part of the +* Hercules Decimal Floating Point Validation Package +* by Stephen R. Orso +* +* Copyright 2016 by Stephen R Orso. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* +* 3. The name of the author may not be used to endorse or promote +* products derived from this software without specific prior written +* permission. +* +* DISCLAMER: THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* HOLDER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* Tests the following three conversion instructions +* LOAD LENGTHENED (short BFP, RRE) +* LOAD LENGTHENED (long BFP, RRE) +* LOAD LENGTHENED (extended BFP, RRE) +* LOAD LENGTHENED (short BFP, RXE) +* LOAD LENGTHENED (long BFP, RXE) +* LOAD LENGTHENED (extended BFP, RXE) +* +* Test data is compiled into this program. The test script that runs +* this program can provide alternative test data through Hercules R +* commands. +* +* Test Case Order +* 1) Short to log BFP non-finite tests, non-trap and trap +* 2) Short to log BFP finite tests, non-trappable +* 3) Long to extended BFP non-finite tests, non-trap and trap +* 4) Long to extended BFP finite tests, non-trappable +* 5) Short to extended BFP non-finite tests, non-trap and trap +* 6) Short to extended BFP finite tests, non-trappable +* +* Two input test data sets are provided, one each for short and long +* precision BFP inputs. The same short BFP inputs are used for +* short to long testing and short to extended testing. +* +* Also tests the following floating point support instructions +* LOAD (Short) +* LOAD (Long) +* LFPC (Load Floating Point Control Register) +* STORE (Short) +* STORE (Long) +* STFPC (Store Floating Point Control Register) +* +*********************************************************************** + SPACE 2 + MACRO + PADCSECT &ENDLABL +.* +.* Macro to pad the CSECT to include result data areas if this test +.* program is not being assembled using asma. asma generates a core +.* image that is loaded by the loadcore command, and because the +.* core image is a binary stored in Github, it makes sense to make +.* this small effort to keep the core image small. +.* + AIF (D'&ENDLABL).GOODPAD + MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + MNOTE *,'No CSECT padding performed' + MEXIT +.* +.GOODPAD ANOP Label valid. See if we're on asma + AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + ORG &ENDLABL-1 Not ASMA. Pad CSECT + MEXIT +.* +.NOPAD ANOP + MNOTE *,'asma detected; no CSECT padding performed' + MEND +* +* Note: for compatibility with the z/CMS test rig, do not change +* or use R11, R14, or R15. Everything else is fair game. +* +BFPLDLEN START 0 Load Lengthened Testing +STRTLABL EQU * +R0 EQU 0 Work register for cc extraction +R1 EQU 1 Available +R2 EQU 2 Holds count of test input values +R3 EQU 3 Points to next test input value(s) +R4 EQU 4 Available +R5 EQU 5 Available +R6 EQU 6 Available +R7 EQU 7 Pointer to next result value(s) +R8 EQU 8 Pointer to next FPCR result +R9 EQU 9 Available +R10 EQU 10 Pointer to test address list +R11 EQU 11 **Reserved for z/CMS test rig +R12 EQU 12 Holds number of test cases in set +R13 EQU 13 Mainline return address +R14 EQU 14 **Return address for z/CMS test rig +R15 EQU 15 **Base register on z/CMS or Hyperion +* +* Floating Point Register equates to keep the cross reference clean +* +FPR0 EQU 0 +FPR1 EQU 1 +FPR2 EQU 2 +FPR3 EQU 3 +FPR4 EQU 4 +FPR5 EQU 5 +FPR6 EQU 6 +FPR7 EQU 7 +FPR8 EQU 8 +FPR9 EQU 9 +FPR10 EQU 10 +FPR11 EQU 11 +FPR12 EQU 12 +FPR13 EQU 13 +FPR14 EQU 14 +FPR15 EQU 15 +* + USING *,R15 +* Above works on real iron (R15=0 after sysclear) +* and in z/CMS (R15 points to start of load module) +* + SPACE 2 +*********************************************************************** +* +* Low core definitions, Restart PSW, and Program Check Routine. +* +*********************************************************************** + SPACE 2 + ORG STRTLABL+X'8E' Program check interrution code +PCINTCD DS H +* +PCOLDPSW EQU STRTLABL+X'150' z/Arch Program check old PSW +* + ORG STRTLABL+X'1A0' z/Arch Restart PSW + DC X'0000000180000000',AD(START) +* + ORG STRTLABL+X'1D0' z/Arch Program check old PSW + DC X'0000000000000000',AD(PROGCHK) +* +* Program check routine. If Data Exception, continue execution at +* the instruction following the program check. Otherwise, hard wait. +* No need to collect data. All interesting DXC stuff is captured +* in the FPCR. +* +PROGCHK DS 0H Program check occured... + CLI PCINTCD+1,X'07' Data Exception? + JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) + LPSWE PCOLDPSW ..yes, resume program execution +PCNOTDTA DS 0H + LTR R14,R14 Return address provided? + BNZR R14 Yes, return to z/CMS test rig. + LPSWE HARDWAIT Not data exception, enter disabled wait. + EJECT +*********************************************************************** +* +* Main program. Enable Advanced Floating Point, process test cases. +* +*********************************************************************** + SPACE 2 +START DS 0H + STCTL R0,R0,CTLR0 Store CR0 to enable AFP + OI CTLR0+1,X'04' Turn on AFP bit + LCTL R0,R0,CTLR0 Reload updated CR0 +* + LA R10,SHORTNF Point to short BFP non-finite test data + BAS R13,LDEBRNF Convert short BFP to long BFP + LA R10,SHORTF Point to short BFP finite test data + BAS R13,LDEBRF Convert short BFP to long BFP +* + LA R10,LONGNF Point to long BFP non-finite test data + BAS R13,LXDBRNF Convert long BFP to integer long BFP + LA R10,LONGF Point to long BFP finite test data + BAS R13,LXDBRF Convert using all rounding mode options +* + LA R10,XTNDNF Point to short BFP non-finite test data + BAS R13,LXEBRNF Convert short BFP to extended BFP + LA R10,XTNDF Point to short BFP finite test data + BAS R13,LXEBRF Convert short BFP to extended BFP +* + LTR R14,R14 Return address provided? + BNZR R14 ..Yes, return to z/CMS test rig. + LPSWE WAITPSW All done +* + DS 0D Ensure correct alignment for psw +WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end +* +CTLR0 DS F +FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags +* +* Input values parameter list, four fullwords: +* 1) Count, +* 2) Address of inputs, +* 3) Address to place results, and +* 4) Address to place DXC/Flags/cc values. +* + ORG STRTLABL+X'300' +SHORTNF DS 0F Short to long BFP non-finite inputs + DC A(SBFPNFCT) + DC A(SBFPNFIN) + DC A(SBFPNFOT) + DC A(SBFPNFFL) +* +SHORTF DS 0F Short to long BFP finite inputs + DC A(SBFPFCT) + DC A(SBFPFIN) + DC A(SBFPFOT) + DC A(SBFPFOF) +* +LONGNF DS 0F Long to extended BFP non-finite inputs + DC A(LBFPNFCT) + DC A(LBFPNFIN) + DC A(LBFPNFOT) + DC A(LBFPNFFL) +* +LONGF DS 0F Long to extended BFP finite inputs + DC A(LBFPFCT) + DC A(LBFPFIN) + DC A(LBFPFOT) + DC A(LBFPFOF) +* +XTNDNF DS 0F Short to extended BFP non-finite inputs + DC A(SBFPNFCT) + DC A(SBFPNFIN) + DC A(XBFPNFOT) + DC A(XBFPNFFL) +* +XTNDF DS 0F Short to extended BFP finite inputs + DC A(SBFPFCT) + DC A(SBFPFIN) + DC A(XBFPFOT) + DC A(XBFPFOF) + EJECT +*********************************************************************** +* +* Load Lengthened Short to Long non-finite tests +* +* Lengthen short BFP inputs to long BFP. Two pairs of results are +* generated, one pair for RRE and one for RXE. Each pair consists of +* a result with all exceptions non-trappable and a second with all +* exceptions trappable. The FPCR is stored for each result. The +* Condition Code in not changed by Load Lengthened and is not stored. +* +*********************************************************************** + SPACE 2 +LDEBRNF DS 0H Convert short BFP inputs to long BFP + LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LE FPR8,0(,R3) Get short BFP test value + LFPC FPCREGNT Set exceptions non-trappable + LDEBR FPR1,FPR8 Lengthen short in FPR8 to long in FPR1 + STD FPR1,0(,R7) Store long BFP result + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LZER FPR1 Eliminate any residual results + LDEBR FPR1,FPR8 Lengthen short in FPR8 to long in FPR1 + STD FPR1,8(,R7) Store long BFP result + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable + LDEB FPR1,0(,R3) Lengthen short BFP to long in FPR1 + STD FPR1,16(,R7) Store long BFP result + STFPC 8(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LZER FPR1 Eliminate any residual results + LDEB FPR1,0(,R3) Lengthen short BFP to long in FPR1 + STD FPR1,24(,R7) Store long BFP result + STFPC 12(R8) Store resulting FPCR flags and DXC +* + LA R3,4(,R3) Point to next input value + LA R7,4*8(,R7) Point to next long BFP result set + LA R8,4*4(,R8) Point to next FPCR result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Load Lengthened Short to Long finite tests +* +* Convert short BFP to integer BFP using each possible rounding mode. +* Ten test results are generated for each input. A 48-byte test result +* section is used to keep results sets aligned on a quad-double word. +* +* The first four tests use rounding modes specified in the FPCR with +* the IEEE Inexact exception supressed. SRNM (2-bit) is used for +* the first two FPCR-controlled tests and SRNMB (3-bit) is used for +* the last two To get full coverage of that instruction pair. +* +* The next six results use instruction-specified rounding modes. +* +* The default rounding mode (0 for RNTE) is not tested in this section; +* prior tests used the default rounding mode. RNTE is tested +* explicitly as a rounding mode in this section. +* +*********************************************************************** + SPACE 2 +LDEBRF LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LE FPR8,0(,R3) Get short BFP test value +* + LFPC FPCREGNT Set exceptions non-trappable + LDEBR FPR1,FPR8 Lengthen short in FPR8 to long in FPR1 + STD FPR1,0(,R7) Store long BFP result + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable + LZER FPR1 Eliminate any residual results + LDEB FPR1,0(,R3) Lengthen short in FPR8 to long in FPR1 + STD FPR1,8(,R7) Store long BFP result + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LA R3,4(,R3) Point to next input value + LA R7,2*8(,R7) Point to next long BFP result set + LA R8,2*4(,R8) Point to next FPCR result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Load Lengthened Long to Extended non-finite tests +* +* Lengthen long BFP inputs to extended BFP. Two pairs of results are +* generated, one pair for RRE and one for RXE. Each pair consists of +* a result with all exceptions non-trappable and a second with all +* exceptions trappable. The FPCR is stored for each result. The +* Condition Code in not changed by Load Lengthened and is not stored. +* +*********************************************************************** + SPACE 2 +LXDBRNF LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LD FPR8,0(,R3) Get long BFP test value + LFPC FPCREGNT Set exceptions non-trappable + LXDBR FPR1,FPR8 Lengthen long in FPR8 to extended in FPR1 + STD FPR1,0(,R7) Store extended BFP result part 1 + STD FPR3,8(,R7) Store extended BFP result part 2 + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LZXR FPR1 Eliminate any residual results + LXDBR FPR1,FPR8 Lengthen long in FPR8 to extended in FPR1 + STD FPR1,16(,R7) Store extended BFP result part 1 + STD FPR3,24(,R7) Store extended BFP result part 2 + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable + LXDB FPR1,0(,R3) Lengthen long BFP to extended in FPR1-3 + STD FPR1,32(,R7) Store extended BFP result part 1 + STD FPR3,40(,R7) Store extended BFP result part 2 + STFPC 8(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LZXR FPR1 Eliminate any residual results + LXDB FPR1,0(,R3) Lengthen long BFP to extended in FPR1-3 + STD FPR1,48(,R7) Store extended BFP result part 1 + STD FPR3,56(,R7) Store extended BFP result part 2 + STFPC 12(R8) Store resulting FPCR flags and DXC +* + LA R3,8(,R3) Point to next input value + LA R7,4*16(,R7) Point to next extended BFP result set + LA R8,4*4(,R8) Point to next FPCR result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert long BFP to integers using each possible rounding mode. +* Ten test results are generated for each input. A 48-byte test result +* section is used to keep results sets aligned on a quad-double word. +* +* The first four tests use rounding modes specified in the FPCR with +* the IEEE Inexact exception supressed. SRNM (2-bit) is used for +* the first two FPCR-controlled tests and SRNMB (3-bit) is used for +* the last two To get full coverage of that instruction pair. +* +* The next six results use instruction-specified rounding modes. +* +* The default rounding mode (0 for RNTE) is not tested in this section; +* prior tests used the default rounding mode. RNTE is tested +* explicitly as a rounding mode in this section. +* +*********************************************************************** + SPACE 2 +LXDBRF LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LD FPR8,0(,R3) Get long BFP test value + LFPC FPCREGNT Set exceptions non-trappable + LXDBR FPR1,FPR8 Lengthen long in FPR8 to extended in FPR1 + STD FPR1,0(,R7) Store extended BFP result part 1 + STD FPR3,8(,R7) Store extended BFP result part 2 + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable + LXDB FPR1,0(,R3) Lengthen long BFP to extended in FPR1-3 + STD FPR1,16(,R7) Store extended BFP result part 1 + STD FPR3,24(,R7) Store extended BFP result part 2 + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LA R3,8(,R3) Point to next input value + LA R7,2*16(,R7) Point to next extended BFP result set + LA R8,2*4(,R8) Point to next FPCR result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Load Lengthened Short to Extended non-finite tests +* +* Lengthen short BFP inputs to extended BFP. Two pairs of results are +* generated, one pair for RRE and one for RXE. Each pair consists of +* a result with all exceptions non-trappable and a second with all +* exceptions trappable. The FPCR is stored for each result. The +* Condition Code in not changed by Load Lengthened and is not stored. +* +*********************************************************************** + SPACE 2 +LXEBRNF LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LE FPR8,0(,R3) Get long BFP test value + LFPC FPCREGNT Set exceptions non-trappable + LXEBR FPR1,FPR8 Lengthen long in FPR8 to extended in FPR1 + STD FPR1,0(,R7) Store extended BFP result part 1 + STD FPR3,8(,R7) Store extended BFP result part 2 + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LZXR FPR1 Eliminate any residual results + LXEBR FPR1,FPR8 Lengthen long in FPR8 to extended in FPR1 + STD FPR1,16(,R7) Store extended BFP result part 1 + STD FPR3,24(,R7) Store extended BFP result part 2 + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable + LXEB FPR1,0(,R3) Lengthen long BFP to extended in FPR1-3 + STD FPR1,32(,R7) Store extended BFP result part 1 + STD FPR3,40(,R7) Store extended BFP result part 2 + STFPC 8(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LZXR FPR1 Eliminate any residual results + LXEB FPR1,0(,R3) Lengthen long BFP to extended in FPR1-3 + STD FPR1,48(,R7) Store extended BFP result part 1 + STD FPR3,56(,R7) Store extended BFP result part 2 + STFPC 12(R8) Store resulting FPCR flags and DXC +* + LA R3,4(,R3) Point to next input value + LA R7,4*16(,R7) Point to next extended BFP result set + LA R8,4*4(,R8) Point to next FPCR result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Convert extended BFP to integers using each possible rounding mode. +* Ten test results are generated for each input. A 48-byte test result +* section is used to keep results sets aligned on a quad-double word. +* +* The first four tests use rounding modes specified in the FPCR with +* the IEEE Inexact exception supressed. SRNM (2-bit) is used for +* the first two FPCR-controlled tests and SRNMB (3-bit) is used for +* the last two To get full coverage of that instruction pair. +* +* The next six results use instruction-specified rounding modes. +* +* The default rounding mode (0 for RNTE) is not tested in this section; +* prior tests used the default rounding mode. RNTE is tested +* explicitly as a rounding mode in this section. +* +*********************************************************************** + SPACE 2 +LXEBRF LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LE FPR8,0(,R3) Get long BFP test value + LFPC FPCREGNT Set exceptions non-trappable + LXEBR FPR1,FPR8 Lengthen long in FPR8 to extended in FPR1 + STD FPR1,0(,R7) Store extended BFP result part 1 + STD FPR3,8(,R7) Store extended BFP result part 2 + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable + LXEB FPR1,0(,R3) Lengthen long BFP to extended in FPR1-3 + STD FPR1,16(,R7) Store extended BFP result part 1 + STD FPR3,24(,R7) Store extended BFP result part 2 + STFPC 8(R8) Store resulting FPCR flags and DXC +* + LA R3,4(,R3) Point to next input value + LA R7,2*16(,R7) Point to next extended BFP result set + LA R8,2*4(,R8) Point to next FPCR result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Short integer inputs for Load Lengthened testing. These values +* correspond to the data classes listed in Figure 19-17 on page 19-21 +* of SA22-7832-10. The values are tested with and without traps +* enabled. +* +* The same values are used for long and extended result creation. +* +*********************************************************************** + SPACE 2 +SBFPNFIN DS 0F Inputs for short BFP non-finite testing + DC X'FF800000' -Infinity + DC X'BF800000' -1.0 + DC X'80000000' -0.0 + DC X'00000000' +0.0 + DC X'3F800000' +1.0 + DC X'7F800000' -Infinity + DC X'7FC10000' QNaN + DC X'7F820000' SNaN +SBFPNFCT EQU (*-SBFPNFIN)/4 Count of short BFP in list + SPACE 3 +*********************************************************************** +* +* Short integer inputs for Load Lengthened testing. These values +* functionally test Load Lengthened operations including preservation +* of all signficant bits in the result and renormalization of subnormal +* (tiny) values. +* +* The same values are used for long and extended result creation. +* +*********************************************************************** + SPACE 2 +SBFPFIN DS 0F Inputs for short BFP finite testing + DC X'FF7FFFFF' Maximum -normal, all bits test + DC X'804FFFFF' maximum -tiny, all bits test + DC X'80000001' minimum -tiny + DC X'BDCCCCCD' -0.1 rounded away from zero + DC X'BDCCCCCC' -0.1 rounded toward zero + DC X'3DCCCCCC' +0.1 rounded toward zero + DC X'3DCCCCCD' +0.1 rounded away from zero + DC X'00000001' minimum +tiny + DC X'004FFFFF' maximum +tiny, all bits test + DC X'7F7FFFFF' maximum +normal, all bits test +SBFPFCT EQU (*-SBFPFIN)/4 Count of short BFP in list +* +*********************************************************************** +* +* Long integer inputs for Load Lengthened testing. These values +* correspond to the data classes listed in Figure 19-17 on page 19-21 +* of SA22-7832-10. The values are tested with and without traps +* enabled. +* +*********************************************************************** + SPACE 2 +LBFPNFIN DS 0D Inputs for long BFP non-finite testing + DC X'FFF0000000000000' -Infinity + DC X'BFF0000000000000' -1.0 + DC X'8000000000000000' -0.0 + DC X'0000000000000000' +0.0 + DC X'3FF0000000000000' +1.0 + DC X'7FF0000000000000' -Infinity + DC X'7FF8100000000000' +QNaN + DC X'7FF0200000000000' +SNaN +LBFPNFCT EQU (*-LBFPNFIN)/8 Count of long BFP in list + SPACE 3 +*********************************************************************** +* +* Long integer inputs for Load Lengthened testing. These values +* functionally test Load Lengthened operations including preservation +* of all signficant bits in the result and renormalization of subnormal +* (tiny) values. +* +*********************************************************************** + SPACE 2 +LBFPFIN DS 0F Inputs for long BFP finite testing + DC X'7FFFFFFFFFFFFFFF' Maximum -normal, all bits test + DC X'800FFFFFFFFFFFFF' Maximum -tiny, all bits test + DC X'8000000000000001' Minimum -tiny + DC X'BFB999999999999A' -0.1 rounded away from zero + DC X'BFB9999999999999' -0.1 rounded toward zero + DC X'3FB9999999999999' +0.1 rounded toward zero + DC X'3FB999999999999A' +0.1 rounded away from zero + DC X'0000000000000001' Minimum +tiny + DC X'000FFFFFFFFFFFFF' Maximum +tiny, all bits test + DC X'7FFFFFFFFFFFFFFF' Maximum +normal, all bits test +LBFPFCT EQU (*-LBFPFIN)/8 Count of long BFP rounding tests * 8 +* +* Locations for results +* +* Results from short -> long Load Lengthened +* +SBFPNFOT EQU STRTLABL+X'1000' Long BFP non-finite results +* ..8 used, room for 8 +SBFPNFFL EQU STRTLABL+X'1100' FPCR flags and DXC from long BFP +* ..8 used, room for 16 +SBFPFOT EQU STRTLABL+X'1200' Long BFP finite test results +* ..10 used, room for 16 +SBFPFOF EQU STRTLABL+X'1300' Long BFP finite FPCR results +* ..10 used, room for 16 +* .. next assignment X'1400' +* +* Results from long -> extended Load Lengthened +* +LBFPNFOT EQU STRTLABL+X'2000' Extended BFP non-finite results +* ..8 used, room for 8 +LBFPNFFL EQU STRTLABL+X'2200' FPCR flags and DXC from extended BFP +* ..8 used, room for 16 +LBFPFOT EQU STRTLABL+X'2300' Extended BFP non-finite test results +* ..10 used, room for 16 +LBFPFOF EQU STRTLABL+X'2500' Extended BFP non-finite FPCR results +* ..10 used, room for 16 +* .. next assignment X'2600' +* +* Results from short -> extended Load Lengthened +* +XBFPNFOT EQU STRTLABL+X'3000' Extended BFP rounded results +* ..8 used, room for 8 +XBFPNFFL EQU STRTLABL+X'3200' FPCR flags and DXC from extended BFP +* ..8 used, room for 16 +XBFPFOT EQU STRTLABL+X'3300' Extd BFP rounding mode test results +* ..10 used, room for 16 +XBFPFOF EQU STRTLABL+X'3500' Extd BFP rounding mode FPCR results +* ..10 used, room for 16 +* .. next assignment X'3500' +* +* +ENDLABL EQU STRTLABL+X'3600' +* Pad CSECT if not running on ASMA for a stand-alone environment + PADCSECT ENDLABL + END diff --git a/tests/bfp-017-loadl.core b/tests/bfp-017-loadl.core new file mode 100644 index 000000000..136b5fab3 Binary files /dev/null and b/tests/bfp-017-loadl.core differ diff --git a/tests/bfp-017-loadl.list b/tests/bfp-017-loadl.list new file mode 100644 index 000000000..12e8b8d15 --- /dev/null +++ b/tests/bfp-017-loadl.list @@ -0,0 +1,830 @@ +ASMA Ver. 0.2.0 bfp-017-loadl.asm: Test IEEE Load Lengthened 28 Sep 2016 13:44:39 Page 1 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 2 *********************************************************************** + 3 * + 4 *Testcase IEEE LOAD LENGTHENED + 5 * Test case capability includes IEEE exceptions trappable and + 6 * otherwise. Test results, FPCR flags, and any DXC are saved for all + 7 * tests. Load Lengthened does not set the condition code. + 8 * + 9 *********************************************************************** + + + 11 *********************************************************************** + 12 * + 13 * Tests the following three conversion instructions + 14 * LOAD LENGTHENED (short BFP, RRE) + 15 * LOAD LENGTHENED (long BFP, RRE) + 16 * LOAD LENGTHENED (extended BFP, RRE) + 17 * LOAD LENGTHENED (short BFP, RXE) + 18 * LOAD LENGTHENED (long BFP, RXE) + 19 * LOAD LENGTHENED (extended BFP, RXE) + 20 * + 21 * Test data is compiled into this program. The test script that runs + 22 * this program can provide alternative test data through Hercules R + 23 * commands. + 24 * + 25 * Test Case Order + 26 * 1) Short to log BFP non-finite tests, non-trap and trap + 27 * 2) Short to log BFP finite tests, non-trappable + 28 * 3) Long to extended BFP non-finite tests, non-trap and trap + 29 * 4) Long to extended BFP finite tests, non-trappable + 30 * 5) Short to extended BFP non-finite tests, non-trap and trap + 31 * 6) Short to extended BFP finite tests, non-trappable + 32 * + 33 * Two input test data sets are provided, one each for short and long + 34 * precision BFP inputs. The same short BFP inputs are used for + 35 * short to long testing and short to extended testing. + 36 * + 37 * Also tests the following floating point support instructions + 38 * LOAD (Short) + 39 * LOAD (Long) + 40 * LFPC (Load Floating Point Control Register) + 41 * STORE (Short) + 42 * STORE (Long) + 43 * STFPC (Store Floating Point Control Register) + 44 * + 45 *********************************************************************** + + + 47 MACRO + 48 PADCSECT &ENDLABL + 49 .* + 50 .* Macro to pad the CSECT to include result data areas if this test + 51 .* program is not being assembled using asma. asma generates a core + ASMA Ver. 0.2.0 bfp-017-loadl.asm: Test IEEE Load Lengthened 28 Sep 2016 13:44:39 Page 2 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 52 .* image that is loaded by the loadcore command, and because the + 53 .* core image is a binary stored in Github, it makes sense to make + 54 .* this small effort to keep the core image small. + 55 .* + 56 AIF (D'&ENDLABL).GOODPAD + 57 MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + 58 MNOTE *,'No CSECT padding performed' + 59 MEXIT + 60 .* + 61 .GOODPAD ANOP Label valid. See if we're on asma + 62 AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + 63 ORG &ENDLABL-1 Not ASMA. Pad CSECT + 64 MEXIT + 65 .* + 66 .NOPAD ANOP + 67 MNOTE *,'asma detected; no CSECT padding performed' + 68 MEND + 69 * + 70 * Note: for compatibility with the z/CMS test rig, do not change + 71 * or use R11, R14, or R15. Everything else is fair game. + 72 * + 0000000000000000 0000000000000687 73 BFPLDLEN START 0 Load Lengthened Testing + 0000000000000000 0000000000000001 74 STRTLABL EQU * + 0000000000000000 0000000000000001 75 R0 EQU 0 Work register for cc extraction + 0000000000000001 0000000000000001 76 R1 EQU 1 Available + 0000000000000002 0000000000000001 77 R2 EQU 2 Holds count of test input values + 0000000000000003 0000000000000001 78 R3 EQU 3 Points to next test input value(s) + 0000000000000004 0000000000000001 79 R4 EQU 4 Available + 0000000000000005 0000000000000001 80 R5 EQU 5 Available + 0000000000000006 0000000000000001 81 R6 EQU 6 Available + 0000000000000007 0000000000000001 82 R7 EQU 7 Pointer to next result value(s) + 0000000000000008 0000000000000001 83 R8 EQU 8 Pointer to next FPCR result + 0000000000000009 0000000000000001 84 R9 EQU 9 Available + 000000000000000A 0000000000000001 85 R10 EQU 10 Pointer to test address list + 000000000000000B 0000000000000001 86 R11 EQU 11 **Reserved for z/CMS test rig + 000000000000000C 0000000000000001 87 R12 EQU 12 Holds number of test cases in set + 000000000000000D 0000000000000001 88 R13 EQU 13 Mainline return address + 000000000000000E 0000000000000001 89 R14 EQU 14 **Return address for z/CMS test rig + 000000000000000F 0000000000000001 90 R15 EQU 15 **Base register on z/CMS or Hyperion + 91 * + 92 * Floating Point Register equates to keep the cross reference clean + 93 * + 0000000000000000 0000000000000001 94 FPR0 EQU 0 + 0000000000000001 0000000000000001 95 FPR1 EQU 1 + 0000000000000002 0000000000000001 96 FPR2 EQU 2 + 0000000000000003 0000000000000001 97 FPR3 EQU 3 + 0000000000000004 0000000000000001 98 FPR4 EQU 4 + 0000000000000005 0000000000000001 99 FPR5 EQU 5 + 0000000000000006 0000000000000001 100 FPR6 EQU 6 + 0000000000000007 0000000000000001 101 FPR7 EQU 7 + 0000000000000008 0000000000000001 102 FPR8 EQU 8 + 0000000000000009 0000000000000001 103 FPR9 EQU 9 + ASMA Ver. 0.2.0 bfp-017-loadl.asm: Test IEEE Load Lengthened 28 Sep 2016 13:44:39 Page 3 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 000000000000000A 0000000000000001 104 FPR10 EQU 10 + 000000000000000B 0000000000000001 105 FPR11 EQU 11 + 000000000000000C 0000000000000001 106 FPR12 EQU 12 + 000000000000000D 0000000000000001 107 FPR13 EQU 13 + 000000000000000E 0000000000000001 108 FPR14 EQU 14 + 000000000000000F 0000000000000001 109 FPR15 EQU 15 + 110 * +0000000000000000 0000000000000000 111 USING *,R15 + 112 * Above works on real iron (R15=0 after sysclear) + 113 * and in z/CMS (R15 points to start of load module) + 114 * + + + 116 *********************************************************************** + 117 * + 118 * Low core definitions, Restart PSW, and Program Check Routine. + 119 * + 120 *********************************************************************** + + +0000000000000000 0000000000000000 000000000000008E 122 ORG STRTLABL+X'8E' Program check interrution code +000000000000008E 0000 123 PCINTCD DS H + 124 * + 0000000000000150 0000000000000001 125 PCOLDPSW EQU STRTLABL+X'150' z/Arch Program check old PSW + 126 * +0000000000000090 0000000000000090 00000000000001A0 127 ORG STRTLABL+X'1A0' z/Arch Restart PSW +00000000000001A0 00000001 80000000 128 DC X'0000000180000000',AD(START) + 129 * +00000000000001B0 00000000000001B0 00000000000001D0 130 ORG STRTLABL+X'1D0' z/Arch Program check old PSW +00000000000001D0 00000000 00000000 131 DC X'0000000000000000',AD(PROGCHK) + 132 * + 133 * Program check routine. If Data Exception, continue execution at + 134 * the instruction following the program check. Otherwise, hard wait. + 135 * No need to collect data. All interesting DXC stuff is captured + 136 * in the FPCR. + 137 * +00000000000001E0 138 PROGCHK DS 0H Program check occured... +00000000000001E0 9507 F08F 000000000000008F 139 CLI PCINTCD+1,X'07' Data Exception? +00000000000001E4 A774 0004 00000000000001EC 140 JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) +00000000000001E8 B2B2 F150 0000000000000150 141 LPSWE PCOLDPSW ..yes, resume program execution +00000000000001EC 142 PCNOTDTA DS 0H +00000000000001EC 12EE 143 LTR R14,R14 Return address provided? +00000000000001EE 077E 144 BNZR R14 Yes, return to z/CMS test rig. +00000000000001F0 B2B2 F248 0000000000000248 145 LPSWE HARDWAIT Not data exception, enter disabled wait. + ASMA Ver. 0.2.0 bfp-017-loadl.asm: Test IEEE Load Lengthened 28 Sep 2016 13:44:39 Page 4 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 147 *********************************************************************** + 148 * + 149 * Main program. Enable Advanced Floating Point, process test cases. + 150 * + 151 *********************************************************************** + + +00000000000001F4 153 START DS 0H +00000000000001F4 B600 F258 0000000000000258 154 STCTL R0,R0,CTLR0 Store CR0 to enable AFP +00000000000001F8 9604 F259 0000000000000259 155 OI CTLR0+1,X'04' Turn on AFP bit +00000000000001FC B700 F258 0000000000000258 156 LCTL R0,R0,CTLR0 Reload updated CR0 + 157 * +0000000000000200 41A0 F300 0000000000000300 158 LA R10,SHORTNF Point to short BFP non-finite test data +0000000000000204 4DD0 F360 0000000000000360 159 BAS R13,LDEBRNF Convert short BFP to long BFP +0000000000000208 41A0 F310 0000000000000310 160 LA R10,SHORTF Point to short BFP finite test data +000000000000020C 4DD0 F3CE 00000000000003CE 161 BAS R13,LDEBRF Convert short BFP to long BFP + 162 * +0000000000000210 41A0 F320 0000000000000320 163 LA R10,LONGNF Point to long BFP non-finite test data +0000000000000214 4DD0 F416 0000000000000416 164 BAS R13,LXDBRNF Convert long BFP to integer long BFP +0000000000000218 41A0 F330 0000000000000330 165 LA R10,LONGF Point to long BFP finite test data +000000000000021C 4DD0 F494 0000000000000494 166 BAS R13,LXDBRF Convert using all rounding mode options + 167 * +0000000000000220 41A0 F340 0000000000000340 168 LA R10,XTNDNF Point to short BFP non-finite test data +0000000000000224 4DD0 F4E0 00000000000004E0 169 BAS R13,LXEBRNF Convert short BFP to extended BFP +0000000000000228 41A0 F350 0000000000000350 170 LA R10,XTNDF Point to short BFP finite test data +000000000000022C 4DD0 F55E 000000000000055E 171 BAS R13,LXEBRF Convert short BFP to extended BFP + 172 * +0000000000000230 12EE 173 LTR R14,R14 Return address provided? +0000000000000232 077E 174 BNZR R14 ..Yes, return to z/CMS test rig. +0000000000000234 B2B2 F238 0000000000000238 175 LPSWE WAITPSW All done + 176 * +0000000000000238 177 DS 0D Ensure correct alignment for psw +0000000000000238 00020000 00000000 178 WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +0000000000000248 00020000 00000000 179 HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end + 180 * +0000000000000258 00000000 181 CTLR0 DS F +000000000000025C 00000000 182 FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +0000000000000260 F8000000 183 FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags + 184 * + 185 * Input values parameter list, four fullwords: + 186 * 1) Count, + 187 * 2) Address of inputs, + 188 * 3) Address to place results, and + 189 * 4) Address to place DXC/Flags/cc values. + 190 * +0000000000000264 0000000000000264 0000000000000300 191 ORG STRTLABL+X'300' +0000000000000300 192 SHORTNF DS 0F Short to long BFP non-finite inputs +0000000000000300 00000008 193 DC A(SBFPNFCT) +0000000000000304 000005AC 194 DC A(SBFPNFIN) +0000000000000308 00001000 195 DC A(SBFPNFOT) +000000000000030C 00001100 196 DC A(SBFPNFFL) + 197 * + ASMA Ver. 0.2.0 bfp-017-loadl.asm: Test IEEE Load Lengthened 28 Sep 2016 13:44:39 Page 5 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000310 198 SHORTF DS 0F Short to long BFP finite inputs +0000000000000310 0000000A 199 DC A(SBFPFCT) +0000000000000314 000005CC 200 DC A(SBFPFIN) +0000000000000318 00001200 201 DC A(SBFPFOT) +000000000000031C 00001300 202 DC A(SBFPFOF) + 203 * +0000000000000320 204 LONGNF DS 0F Long to extended BFP non-finite inputs +0000000000000320 00000008 205 DC A(LBFPNFCT) +0000000000000324 000005F8 206 DC A(LBFPNFIN) +0000000000000328 00002000 207 DC A(LBFPNFOT) +000000000000032C 00002200 208 DC A(LBFPNFFL) + 209 * +0000000000000330 210 LONGF DS 0F Long to extended BFP finite inputs +0000000000000330 0000000A 211 DC A(LBFPFCT) +0000000000000334 00000638 212 DC A(LBFPFIN) +0000000000000338 00002300 213 DC A(LBFPFOT) +000000000000033C 00002500 214 DC A(LBFPFOF) + 215 * +0000000000000340 216 XTNDNF DS 0F Short to extended BFP non-finite inputs +0000000000000340 00000008 217 DC A(SBFPNFCT) +0000000000000344 000005AC 218 DC A(SBFPNFIN) +0000000000000348 00003000 219 DC A(XBFPNFOT) +000000000000034C 00003200 220 DC A(XBFPNFFL) + 221 * +0000000000000350 222 XTNDF DS 0F Short to extended BFP finite inputs +0000000000000350 0000000A 223 DC A(SBFPFCT) +0000000000000354 000005CC 224 DC A(SBFPFIN) +0000000000000358 00003300 225 DC A(XBFPFOT) +000000000000035C 00003500 226 DC A(XBFPFOF) + ASMA Ver. 0.2.0 bfp-017-loadl.asm: Test IEEE Load Lengthened 28 Sep 2016 13:44:39 Page 6 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 228 *********************************************************************** + 229 * + 230 * Load Lengthened Short to Long non-finite tests + 231 * + 232 * Lengthen short BFP inputs to long BFP. Two pairs of results are + 233 * generated, one pair for RRE and one for RXE. Each pair consists of + 234 * a result with all exceptions non-trappable and a second with all + 235 * exceptions trappable. The FPCR is stored for each result. The + 236 * Condition Code in not changed by Load Lengthened and is not stored. + 237 * + 238 *********************************************************************** + + +0000000000000360 240 LDEBRNF DS 0H Convert short BFP inputs to long BFP +0000000000000360 9823 A000 0000000000000000 241 LM R2,R3,0(R10) Get count and address of test input values +0000000000000364 9878 A008 0000000000000008 242 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000368 1222 243 LTR R2,R2 Any test cases? +000000000000036A 078D 244 BZR R13 ..No, return to caller +000000000000036C 0DC0 245 BASR R12,0 Set top of loop + 246 * +000000000000036E 7880 3000 0000000000000000 247 LE FPR8,0(,R3) Get short BFP test value +0000000000000372 B29D F25C 000000000000025C 248 LFPC FPCREGNT Set exceptions non-trappable +0000000000000376 B304 0018 249 LDEBR FPR1,FPR8 Lengthen short in FPR8 to long in FPR1 +000000000000037A 6010 7000 0000000000000000 250 STD FPR1,0(,R7) Store long BFP result +000000000000037E B29C 8000 0000000000000000 251 STFPC 0(R8) Store resulting FPCR flags and DXC + 252 * +0000000000000382 B29D F260 0000000000000260 253 LFPC FPCREGTR Set exceptions trappable +0000000000000386 B374 0010 254 LZER FPR1 Eliminate any residual results +000000000000038A B304 0018 255 LDEBR FPR1,FPR8 Lengthen short in FPR8 to long in FPR1 +000000000000038E 6010 7008 0000000000000008 256 STD FPR1,8(,R7) Store long BFP result +0000000000000392 B29C 8004 0000000000000004 257 STFPC 4(R8) Store resulting FPCR flags and DXC + 258 * +0000000000000396 B29D F25C 000000000000025C 259 LFPC FPCREGNT Set exceptions non-trappable +000000000000039A ED10 3000 0004 0000000000000000 260 LDEB FPR1,0(,R3) Lengthen short BFP to long in FPR1 +00000000000003A0 6010 7010 0000000000000010 261 STD FPR1,16(,R7) Store long BFP result +00000000000003A4 B29C 8008 0000000000000008 262 STFPC 8(R8) Store resulting FPCR flags and DXC + 263 * +00000000000003A8 B29D F260 0000000000000260 264 LFPC FPCREGTR Set exceptions trappable +00000000000003AC B374 0010 265 LZER FPR1 Eliminate any residual results +00000000000003B0 ED10 3000 0004 0000000000000000 266 LDEB FPR1,0(,R3) Lengthen short BFP to long in FPR1 +00000000000003B6 6010 7018 0000000000000018 267 STD FPR1,24(,R7) Store long BFP result +00000000000003BA B29C 800C 000000000000000C 268 STFPC 12(R8) Store resulting FPCR flags and DXC + 269 * +00000000000003BE 4130 3004 0000000000000004 270 LA R3,4(,R3) Point to next input value +00000000000003C2 4170 7020 0000000000000020 271 LA R7,4*8(,R7) Point to next long BFP result set +00000000000003C6 4180 8010 0000000000000010 272 LA R8,4*4(,R8) Point to next FPCR result area +00000000000003CA 062C 273 BCTR R2,R12 Convert next input value. +00000000000003CC 07FD 274 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-017-loadl.asm: Test IEEE Load Lengthened 28 Sep 2016 13:44:39 Page 7 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 276 *********************************************************************** + 277 * + 278 * Load Lengthened Short to Long finite tests + 279 * + 280 * Convert short BFP to integer BFP using each possible rounding mode. + 281 * Ten test results are generated for each input. A 48-byte test result + 282 * section is used to keep results sets aligned on a quad-double word. + 283 * + 284 * The first four tests use rounding modes specified in the FPCR with + 285 * the IEEE Inexact exception supressed. SRNM (2-bit) is used for + 286 * the first two FPCR-controlled tests and SRNMB (3-bit) is used for + 287 * the last two To get full coverage of that instruction pair. + 288 * + 289 * The next six results use instruction-specified rounding modes. + 290 * + 291 * The default rounding mode (0 for RNTE) is not tested in this section; + 292 * prior tests used the default rounding mode. RNTE is tested + 293 * explicitly as a rounding mode in this section. + 294 * + 295 *********************************************************************** + + +00000000000003CE 9823 A000 0000000000000000 297 LDEBRF LM R2,R3,0(R10) Get count and address of test input values +00000000000003D2 9878 A008 0000000000000008 298 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000003D6 1222 299 LTR R2,R2 Any test cases? +00000000000003D8 078D 300 BZR R13 ..No, return to caller +00000000000003DA 0DC0 301 BASR R12,0 Set top of loop + 302 * +00000000000003DC 7880 3000 0000000000000000 303 LE FPR8,0(,R3) Get short BFP test value + 304 * +00000000000003E0 B29D F25C 000000000000025C 305 LFPC FPCREGNT Set exceptions non-trappable +00000000000003E4 B304 0018 306 LDEBR FPR1,FPR8 Lengthen short in FPR8 to long in FPR1 +00000000000003E8 6010 7000 0000000000000000 307 STD FPR1,0(,R7) Store long BFP result +00000000000003EC B29C 8000 0000000000000000 308 STFPC 0(R8) Store resulting FPCR flags and DXC + 309 * +00000000000003F0 B29D F25C 000000000000025C 310 LFPC FPCREGNT Set exceptions non-trappable +00000000000003F4 B374 0010 311 LZER FPR1 Eliminate any residual results +00000000000003F8 ED10 3000 0004 0000000000000000 312 LDEB FPR1,0(,R3) Lengthen short in FPR8 to long in FPR1 +00000000000003FE 6010 7008 0000000000000008 313 STD FPR1,8(,R7) Store long BFP result +0000000000000402 B29C 8004 0000000000000004 314 STFPC 4(R8) Store resulting FPCR flags and DXC + 315 * +0000000000000406 4130 3004 0000000000000004 316 LA R3,4(,R3) Point to next input value +000000000000040A 4170 7010 0000000000000010 317 LA R7,2*8(,R7) Point to next long BFP result set +000000000000040E 4180 8008 0000000000000008 318 LA R8,2*4(,R8) Point to next FPCR result area +0000000000000412 062C 319 BCTR R2,R12 Convert next input value. +0000000000000414 07FD 320 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-017-loadl.asm: Test IEEE Load Lengthened 28 Sep 2016 13:44:39 Page 8 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 322 *********************************************************************** + 323 * + 324 * Load Lengthened Long to Extended non-finite tests + 325 * + 326 * Lengthen long BFP inputs to extended BFP. Two pairs of results are + 327 * generated, one pair for RRE and one for RXE. Each pair consists of + 328 * a result with all exceptions non-trappable and a second with all + 329 * exceptions trappable. The FPCR is stored for each result. The + 330 * Condition Code in not changed by Load Lengthened and is not stored. + 331 * + 332 *********************************************************************** + + +0000000000000416 9823 A000 0000000000000000 334 LXDBRNF LM R2,R3,0(R10) Get count and address of test input values +000000000000041A 9878 A008 0000000000000008 335 LM R7,R8,8(R10) Get address of result area and flag area. +000000000000041E 1222 336 LTR R2,R2 Any test cases? +0000000000000420 078D 337 BZR R13 ..No, return to caller +0000000000000422 0DC0 338 BASR R12,0 Set top of loop + 339 * +0000000000000424 6880 3000 0000000000000000 340 LD FPR8,0(,R3) Get long BFP test value +0000000000000428 B29D F25C 000000000000025C 341 LFPC FPCREGNT Set exceptions non-trappable +000000000000042C B305 0018 342 LXDBR FPR1,FPR8 Lengthen long in FPR8 to extended in FPR1 +0000000000000430 6010 7000 0000000000000000 343 STD FPR1,0(,R7) Store extended BFP result part 1 +0000000000000434 6030 7008 0000000000000008 344 STD FPR3,8(,R7) Store extended BFP result part 2 +0000000000000438 B29C 8000 0000000000000000 345 STFPC 0(R8) Store resulting FPCR flags and DXC + 346 * +000000000000043C B29D F260 0000000000000260 347 LFPC FPCREGTR Set exceptions trappable +0000000000000440 B376 0010 348 LZXR FPR1 Eliminate any residual results +0000000000000444 B305 0018 349 LXDBR FPR1,FPR8 Lengthen long in FPR8 to extended in FPR1 +0000000000000448 6010 7010 0000000000000010 350 STD FPR1,16(,R7) Store extended BFP result part 1 +000000000000044C 6030 7018 0000000000000018 351 STD FPR3,24(,R7) Store extended BFP result part 2 +0000000000000450 B29C 8004 0000000000000004 352 STFPC 4(R8) Store resulting FPCR flags and DXC + 353 * +0000000000000454 B29D F25C 000000000000025C 354 LFPC FPCREGNT Set exceptions non-trappable +0000000000000458 ED10 3000 0005 0000000000000000 355 LXDB FPR1,0(,R3) Lengthen long BFP to extended in FPR1-3 +000000000000045E 6010 7020 0000000000000020 356 STD FPR1,32(,R7) Store extended BFP result part 1 +0000000000000462 6030 7028 0000000000000028 357 STD FPR3,40(,R7) Store extended BFP result part 2 +0000000000000466 B29C 8008 0000000000000008 358 STFPC 8(R8) Store resulting FPCR flags and DXC + 359 * +000000000000046A B29D F260 0000000000000260 360 LFPC FPCREGTR Set exceptions trappable +000000000000046E B376 0010 361 LZXR FPR1 Eliminate any residual results +0000000000000472 ED10 3000 0005 0000000000000000 362 LXDB FPR1,0(,R3) Lengthen long BFP to extended in FPR1-3 +0000000000000478 6010 7030 0000000000000030 363 STD FPR1,48(,R7) Store extended BFP result part 1 +000000000000047C 6030 7038 0000000000000038 364 STD FPR3,56(,R7) Store extended BFP result part 2 +0000000000000480 B29C 800C 000000000000000C 365 STFPC 12(R8) Store resulting FPCR flags and DXC + 366 * +0000000000000484 4130 3008 0000000000000008 367 LA R3,8(,R3) Point to next input value +0000000000000488 4170 7040 0000000000000040 368 LA R7,4*16(,R7) Point to next extended BFP result set +000000000000048C 4180 8010 0000000000000010 369 LA R8,4*4(,R8) Point to next FPCR result area +0000000000000490 062C 370 BCTR R2,R12 Convert next input value. +0000000000000492 07FD 371 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-017-loadl.asm: Test IEEE Load Lengthened 28 Sep 2016 13:44:39 Page 9 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 373 *********************************************************************** + 374 * + 375 * Convert long BFP to integers using each possible rounding mode. + 376 * Ten test results are generated for each input. A 48-byte test result + 377 * section is used to keep results sets aligned on a quad-double word. + 378 * + 379 * The first four tests use rounding modes specified in the FPCR with + 380 * the IEEE Inexact exception supressed. SRNM (2-bit) is used for + 381 * the first two FPCR-controlled tests and SRNMB (3-bit) is used for + 382 * the last two To get full coverage of that instruction pair. + 383 * + 384 * The next six results use instruction-specified rounding modes. + 385 * + 386 * The default rounding mode (0 for RNTE) is not tested in this section; + 387 * prior tests used the default rounding mode. RNTE is tested + 388 * explicitly as a rounding mode in this section. + 389 * + 390 *********************************************************************** + + +0000000000000494 9823 A000 0000000000000000 392 LXDBRF LM R2,R3,0(R10) Get count and address of test input values +0000000000000498 9878 A008 0000000000000008 393 LM R7,R8,8(R10) Get address of result area and flag area. +000000000000049C 1222 394 LTR R2,R2 Any test cases? +000000000000049E 078D 395 BZR R13 ..No, return to caller +00000000000004A0 0DC0 396 BASR R12,0 Set top of loop + 397 * +00000000000004A2 6880 3000 0000000000000000 398 LD FPR8,0(,R3) Get long BFP test value +00000000000004A6 B29D F25C 000000000000025C 399 LFPC FPCREGNT Set exceptions non-trappable +00000000000004AA B305 0018 400 LXDBR FPR1,FPR8 Lengthen long in FPR8 to extended in FPR1 +00000000000004AE 6010 7000 0000000000000000 401 STD FPR1,0(,R7) Store extended BFP result part 1 +00000000000004B2 6030 7008 0000000000000008 402 STD FPR3,8(,R7) Store extended BFP result part 2 +00000000000004B6 B29C 8000 0000000000000000 403 STFPC 0(R8) Store resulting FPCR flags and DXC + 404 * +00000000000004BA B29D F25C 000000000000025C 405 LFPC FPCREGNT Set exceptions non-trappable +00000000000004BE ED10 3000 0005 0000000000000000 406 LXDB FPR1,0(,R3) Lengthen long BFP to extended in FPR1-3 +00000000000004C4 6010 7010 0000000000000010 407 STD FPR1,16(,R7) Store extended BFP result part 1 +00000000000004C8 6030 7018 0000000000000018 408 STD FPR3,24(,R7) Store extended BFP result part 2 +00000000000004CC B29C 8004 0000000000000004 409 STFPC 4(R8) Store resulting FPCR flags and DXC + 410 * +00000000000004D0 4130 3008 0000000000000008 411 LA R3,8(,R3) Point to next input value +00000000000004D4 4170 7020 0000000000000020 412 LA R7,2*16(,R7) Point to next extended BFP result set +00000000000004D8 4180 8008 0000000000000008 413 LA R8,2*4(,R8) Point to next FPCR result area +00000000000004DC 062C 414 BCTR R2,R12 Convert next input value. +00000000000004DE 07FD 415 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-017-loadl.asm: Test IEEE Load Lengthened 28 Sep 2016 13:44:39 Page 10 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 417 *********************************************************************** + 418 * + 419 * Load Lengthened Short to Extended non-finite tests + 420 * + 421 * Lengthen short BFP inputs to extended BFP. Two pairs of results are + 422 * generated, one pair for RRE and one for RXE. Each pair consists of + 423 * a result with all exceptions non-trappable and a second with all + 424 * exceptions trappable. The FPCR is stored for each result. The + 425 * Condition Code in not changed by Load Lengthened and is not stored. + 426 * + 427 *********************************************************************** + + +00000000000004E0 9823 A000 0000000000000000 429 LXEBRNF LM R2,R3,0(R10) Get count and address of test input values +00000000000004E4 9878 A008 0000000000000008 430 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000004E8 1222 431 LTR R2,R2 Any test cases? +00000000000004EA 078D 432 BZR R13 ..No, return to caller +00000000000004EC 0DC0 433 BASR R12,0 Set top of loop + 434 * +00000000000004EE 7880 3000 0000000000000000 435 LE FPR8,0(,R3) Get long BFP test value +00000000000004F2 B29D F25C 000000000000025C 436 LFPC FPCREGNT Set exceptions non-trappable +00000000000004F6 B306 0018 437 LXEBR FPR1,FPR8 Lengthen long in FPR8 to extended in FPR1 +00000000000004FA 6010 7000 0000000000000000 438 STD FPR1,0(,R7) Store extended BFP result part 1 +00000000000004FE 6030 7008 0000000000000008 439 STD FPR3,8(,R7) Store extended BFP result part 2 +0000000000000502 B29C 8000 0000000000000000 440 STFPC 0(R8) Store resulting FPCR flags and DXC + 441 * +0000000000000506 B29D F260 0000000000000260 442 LFPC FPCREGTR Set exceptions trappable +000000000000050A B376 0010 443 LZXR FPR1 Eliminate any residual results +000000000000050E B306 0018 444 LXEBR FPR1,FPR8 Lengthen long in FPR8 to extended in FPR1 +0000000000000512 6010 7010 0000000000000010 445 STD FPR1,16(,R7) Store extended BFP result part 1 +0000000000000516 6030 7018 0000000000000018 446 STD FPR3,24(,R7) Store extended BFP result part 2 +000000000000051A B29C 8004 0000000000000004 447 STFPC 4(R8) Store resulting FPCR flags and DXC + 448 * +000000000000051E B29D F25C 000000000000025C 449 LFPC FPCREGNT Set exceptions non-trappable +0000000000000522 ED10 3000 0006 0000000000000000 450 LXEB FPR1,0(,R3) Lengthen long BFP to extended in FPR1-3 +0000000000000528 6010 7020 0000000000000020 451 STD FPR1,32(,R7) Store extended BFP result part 1 +000000000000052C 6030 7028 0000000000000028 452 STD FPR3,40(,R7) Store extended BFP result part 2 +0000000000000530 B29C 8008 0000000000000008 453 STFPC 8(R8) Store resulting FPCR flags and DXC + 454 * +0000000000000534 B29D F260 0000000000000260 455 LFPC FPCREGTR Set exceptions trappable +0000000000000538 B376 0010 456 LZXR FPR1 Eliminate any residual results +000000000000053C ED10 3000 0006 0000000000000000 457 LXEB FPR1,0(,R3) Lengthen long BFP to extended in FPR1-3 +0000000000000542 6010 7030 0000000000000030 458 STD FPR1,48(,R7) Store extended BFP result part 1 +0000000000000546 6030 7038 0000000000000038 459 STD FPR3,56(,R7) Store extended BFP result part 2 +000000000000054A B29C 800C 000000000000000C 460 STFPC 12(R8) Store resulting FPCR flags and DXC + 461 * +000000000000054E 4130 3004 0000000000000004 462 LA R3,4(,R3) Point to next input value +0000000000000552 4170 7040 0000000000000040 463 LA R7,4*16(,R7) Point to next extended BFP result set +0000000000000556 4180 8010 0000000000000010 464 LA R8,4*4(,R8) Point to next FPCR result area +000000000000055A 062C 465 BCTR R2,R12 Convert next input value. +000000000000055C 07FD 466 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-017-loadl.asm: Test IEEE Load Lengthened 28 Sep 2016 13:44:39 Page 11 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 468 *********************************************************************** + 469 * + 470 * Convert extended BFP to integers using each possible rounding mode. + 471 * Ten test results are generated for each input. A 48-byte test result + 472 * section is used to keep results sets aligned on a quad-double word. + 473 * + 474 * The first four tests use rounding modes specified in the FPCR with + 475 * the IEEE Inexact exception supressed. SRNM (2-bit) is used for + 476 * the first two FPCR-controlled tests and SRNMB (3-bit) is used for + 477 * the last two To get full coverage of that instruction pair. + 478 * + 479 * The next six results use instruction-specified rounding modes. + 480 * + 481 * The default rounding mode (0 for RNTE) is not tested in this section; + 482 * prior tests used the default rounding mode. RNTE is tested + 483 * explicitly as a rounding mode in this section. + 484 * + 485 *********************************************************************** + + +000000000000055E 9823 A000 0000000000000000 487 LXEBRF LM R2,R3,0(R10) Get count and address of test input values +0000000000000562 9878 A008 0000000000000008 488 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000566 1222 489 LTR R2,R2 Any test cases? +0000000000000568 078D 490 BZR R13 ..No, return to caller +000000000000056A 0DC0 491 BASR R12,0 Set top of loop + 492 * +000000000000056C 7880 3000 0000000000000000 493 LE FPR8,0(,R3) Get long BFP test value +0000000000000570 B29D F25C 000000000000025C 494 LFPC FPCREGNT Set exceptions non-trappable +0000000000000574 B306 0018 495 LXEBR FPR1,FPR8 Lengthen long in FPR8 to extended in FPR1 +0000000000000578 6010 7000 0000000000000000 496 STD FPR1,0(,R7) Store extended BFP result part 1 +000000000000057C 6030 7008 0000000000000008 497 STD FPR3,8(,R7) Store extended BFP result part 2 +0000000000000580 B29C 8000 0000000000000000 498 STFPC 0(R8) Store resulting FPCR flags and DXC + 499 * +0000000000000584 B29D F25C 000000000000025C 500 LFPC FPCREGNT Set exceptions non-trappable +0000000000000588 ED10 3000 0006 0000000000000000 501 LXEB FPR1,0(,R3) Lengthen long BFP to extended in FPR1-3 +000000000000058E 6010 7010 0000000000000010 502 STD FPR1,16(,R7) Store extended BFP result part 1 +0000000000000592 6030 7018 0000000000000018 503 STD FPR3,24(,R7) Store extended BFP result part 2 +0000000000000596 B29C 8008 0000000000000008 504 STFPC 8(R8) Store resulting FPCR flags and DXC + 505 * +000000000000059A 4130 3004 0000000000000004 506 LA R3,4(,R3) Point to next input value +000000000000059E 4170 7020 0000000000000020 507 LA R7,2*16(,R7) Point to next extended BFP result set +00000000000005A2 4180 8008 0000000000000008 508 LA R8,2*4(,R8) Point to next FPCR result area +00000000000005A6 062C 509 BCTR R2,R12 Convert next input value. +00000000000005A8 07FD 510 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-017-loadl.asm: Test IEEE Load Lengthened 28 Sep 2016 13:44:39 Page 12 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 512 *********************************************************************** + 513 * + 514 * Short integer inputs for Load Lengthened testing. These values + 515 * correspond to the data classes listed in Figure 19-17 on page 19-21 + 516 * of SA22-7832-10. The values are tested with and without traps + 517 * enabled. + 518 * + 519 * The same values are used for long and extended result creation. + 520 * + 521 *********************************************************************** + + +00000000000005AC 523 SBFPNFIN DS 0F Inputs for short BFP non-finite testing +00000000000005AC FF800000 524 DC X'FF800000' -Infinity +00000000000005B0 BF800000 525 DC X'BF800000' -1.0 +00000000000005B4 80000000 526 DC X'80000000' -0.0 +00000000000005B8 00000000 527 DC X'00000000' +0.0 +00000000000005BC 3F800000 528 DC X'3F800000' +1.0 +00000000000005C0 7F800000 529 DC X'7F800000' -Infinity +00000000000005C4 7FC10000 530 DC X'7FC10000' QNaN +00000000000005C8 7F820000 531 DC X'7F820000' SNaN + 0000000000000008 0000000000000001 532 SBFPNFCT EQU (*-SBFPNFIN)/4 Count of short BFP in list + + + + 534 *********************************************************************** + 535 * + 536 * Short integer inputs for Load Lengthened testing. These values + 537 * functionally test Load Lengthened operations including preservation + 538 * of all signficant bits in the result and renormalization of subnormal + 539 * (tiny) values. + 540 * + 541 * The same values are used for long and extended result creation. + 542 * + 543 *********************************************************************** + + +00000000000005CC 545 SBFPFIN DS 0F Inputs for short BFP finite testing +00000000000005CC FF7FFFFF 546 DC X'FF7FFFFF' Maximum -normal, all bits test +00000000000005D0 804FFFFF 547 DC X'804FFFFF' maximum -tiny, all bits test +00000000000005D4 80000001 548 DC X'80000001' minimum -tiny +00000000000005D8 BDCCCCCD 549 DC X'BDCCCCCD' -0.1 rounded away from zero +00000000000005DC BDCCCCCC 550 DC X'BDCCCCCC' -0.1 rounded toward zero +00000000000005E0 3DCCCCCC 551 DC X'3DCCCCCC' +0.1 rounded toward zero +00000000000005E4 3DCCCCCD 552 DC X'3DCCCCCD' +0.1 rounded away from zero +00000000000005E8 00000001 553 DC X'00000001' minimum +tiny +00000000000005EC 004FFFFF 554 DC X'004FFFFF' maximum +tiny, all bits test +00000000000005F0 7F7FFFFF 555 DC X'7F7FFFFF' maximum +normal, all bits test + 000000000000000A 0000000000000001 556 SBFPFCT EQU (*-SBFPFIN)/4 Count of short BFP in list + 557 * + 558 *********************************************************************** + 559 * + ASMA Ver. 0.2.0 bfp-017-loadl.asm: Test IEEE Load Lengthened 28 Sep 2016 13:44:39 Page 13 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 560 * Long integer inputs for Load Lengthened testing. These values + 561 * correspond to the data classes listed in Figure 19-17 on page 19-21 + 562 * of SA22-7832-10. The values are tested with and without traps + 563 * enabled. + 564 * + 565 *********************************************************************** + + +00000000000005F8 567 LBFPNFIN DS 0D Inputs for long BFP non-finite testing +00000000000005F8 FFF00000 00000000 568 DC X'FFF0000000000000' -Infinity +0000000000000600 BFF00000 00000000 569 DC X'BFF0000000000000' -1.0 +0000000000000608 80000000 00000000 570 DC X'8000000000000000' -0.0 +0000000000000610 00000000 00000000 571 DC X'0000000000000000' +0.0 +0000000000000618 3FF00000 00000000 572 DC X'3FF0000000000000' +1.0 +0000000000000620 7FF00000 00000000 573 DC X'7FF0000000000000' -Infinity +0000000000000628 7FF81000 00000000 574 DC X'7FF8100000000000' +QNaN +0000000000000630 7FF02000 00000000 575 DC X'7FF0200000000000' +SNaN + 0000000000000008 0000000000000001 576 LBFPNFCT EQU (*-LBFPNFIN)/8 Count of long BFP in list + + + + 578 *********************************************************************** + 579 * + 580 * Long integer inputs for Load Lengthened testing. These values + 581 * functionally test Load Lengthened operations including preservation + 582 * of all signficant bits in the result and renormalization of subnormal + 583 * (tiny) values. + 584 * + 585 *********************************************************************** + + +0000000000000638 587 LBFPFIN DS 0F Inputs for long BFP finite testing +0000000000000638 7FFFFFFF FFFFFFFF 588 DC X'7FFFFFFFFFFFFFFF' Maximum -normal, all bits test +0000000000000640 800FFFFF FFFFFFFF 589 DC X'800FFFFFFFFFFFFF' Maximum -tiny, all bits test +0000000000000648 80000000 00000001 590 DC X'8000000000000001' Minimum -tiny +0000000000000650 BFB99999 9999999A 591 DC X'BFB999999999999A' -0.1 rounded away from zero +0000000000000658 BFB99999 99999999 592 DC X'BFB9999999999999' -0.1 rounded toward zero +0000000000000660 3FB99999 99999999 593 DC X'3FB9999999999999' +0.1 rounded toward zero +0000000000000668 3FB99999 9999999A 594 DC X'3FB999999999999A' +0.1 rounded away from zero +0000000000000670 00000000 00000001 595 DC X'0000000000000001' Minimum +tiny +0000000000000678 000FFFFF FFFFFFFF 596 DC X'000FFFFFFFFFFFFF' Maximum +tiny, all bits test +0000000000000680 7FFFFFFF FFFFFFFF 597 DC X'7FFFFFFFFFFFFFFF' Maximum +normal, all bits test + 000000000000000A 0000000000000001 598 LBFPFCT EQU (*-LBFPFIN)/8 Count of long BFP rounding tests * 8 + 599 * + 600 * Locations for results + 601 * + 602 * Results from short -> long Load Lengthened + 603 * + 0000000000001000 0000000000000001 604 SBFPNFOT EQU STRTLABL+X'1000' Long BFP non-finite results + 605 * ..8 used, room for 8 + 0000000000001100 0000000000000001 606 SBFPNFFL EQU STRTLABL+X'1100' FPCR flags and DXC from long BFP + 607 * ..8 used, room for 16 + ASMA Ver. 0.2.0 bfp-017-loadl.asm: Test IEEE Load Lengthened 28 Sep 2016 13:44:39 Page 14 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 0000000000001200 0000000000000001 608 SBFPFOT EQU STRTLABL+X'1200' Long BFP finite test results + 609 * ..10 used, room for 16 + 0000000000001300 0000000000000001 610 SBFPFOF EQU STRTLABL+X'1300' Long BFP finite FPCR results + 611 * ..10 used, room for 16 + 612 * .. next assignment X'1400' + 613 * + 614 * Results from long -> extended Load Lengthened + 615 * + 0000000000002000 0000000000000001 616 LBFPNFOT EQU STRTLABL+X'2000' Extended BFP non-finite results + 617 * ..8 used, room for 8 + 0000000000002200 0000000000000001 618 LBFPNFFL EQU STRTLABL+X'2200' FPCR flags and DXC from extended BFP + 619 * ..8 used, room for 16 + 0000000000002300 0000000000000001 620 LBFPFOT EQU STRTLABL+X'2300' Extended BFP non-finite test results + 621 * ..10 used, room for 16 + 0000000000002500 0000000000000001 622 LBFPFOF EQU STRTLABL+X'2500' Extended BFP non-finite FPCR results + 623 * ..10 used, room for 16 + 624 * .. next assignment X'2600' + 625 * + 626 * Results from short -> extended Load Lengthened + 627 * + 0000000000003000 0000000000000001 628 XBFPNFOT EQU STRTLABL+X'3000' Extended BFP rounded results + 629 * ..8 used, room for 8 + 0000000000003200 0000000000000001 630 XBFPNFFL EQU STRTLABL+X'3200' FPCR flags and DXC from extended BFP + 631 * ..8 used, room for 16 + 0000000000003300 0000000000000001 632 XBFPFOT EQU STRTLABL+X'3300' Extd BFP rounding mode test results + 633 * ..10 used, room for 16 + 0000000000003500 0000000000000001 634 XBFPFOF EQU STRTLABL+X'3500' Extd BFP rounding mode FPCR results + 635 * ..10 used, room for 16 + 636 * .. next assignment X'3500' + 637 * + 638 * + 0000000000003600 0000000000000001 639 ENDLABL EQU STRTLABL+X'3600' + 640 * Pad CSECT if not running on ASMA for a stand-alone environment + 641 PADCSECT ENDLABL + 642+ MNOTE *,'asma detected; no CSECT padding performed' +0000000000000688 643 END + ASMA Ver. 0.2.0 bfp-017-loadl.asm: Test IEEE Load Lengthened 28 Sep 2016 13:44:39 Page 15 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +BFPLDLEN J 000000 1672 73 +CTLR0 F 000258 4 181 154 155 156 +ENDLABL U 003600 1 639 +FPCREGNT X 00025C 4 182 248 259 305 310 341 354 399 405 436 449 494 500 +FPCREGTR X 000260 4 183 253 264 347 360 442 455 +FPR0 U 000000 1 94 +FPR1 U 000001 1 95 249 250 254 255 256 260 261 265 266 267 306 307 311 312 313 342 343 + 348 349 350 355 356 361 362 363 400 401 406 407 437 438 443 444 445 + 450 451 456 457 458 495 496 501 502 +FPR10 U 00000A 1 104 +FPR11 U 00000B 1 105 +FPR12 U 00000C 1 106 +FPR13 U 00000D 1 107 +FPR14 U 00000E 1 108 +FPR15 U 00000F 1 109 +FPR2 U 000002 1 96 +FPR3 U 000003 1 97 344 351 357 364 402 408 439 446 452 459 497 503 +FPR4 U 000004 1 98 +FPR5 U 000005 1 99 +FPR6 U 000006 1 100 +FPR7 U 000007 1 101 +FPR8 U 000008 1 102 247 249 255 303 306 340 342 349 398 400 435 437 444 493 495 +FPR9 U 000009 1 103 +HARDWAIT X 000248 8 179 145 +IMAGE 1 000000 1672 0 +LBFPFCT U 00000A 1 598 211 +LBFPFIN F 000638 4 587 598 212 +LBFPFOF U 002500 1 622 214 +LBFPFOT U 002300 1 620 213 +LBFPNFCT U 000008 1 576 205 +LBFPNFFL U 002200 1 618 208 +LBFPNFIN D 0005F8 8 567 576 206 +LBFPNFOT U 002000 1 616 207 +LDEBRF I 0003CE 4 297 161 +LDEBRNF H 000360 2 240 159 +LONGF F 000330 4 210 165 +LONGNF F 000320 4 204 163 +LXDBRF I 000494 4 392 166 +LXDBRNF I 000416 4 334 164 +LXEBRF I 00055E 4 487 171 +LXEBRNF I 0004E0 4 429 169 +PCINTCD H 00008E 2 123 139 +PCNOTDTA H 0001EC 2 142 140 +PCOLDPSW U 000150 1 125 141 +PROGCHK H 0001E0 2 138 131 +R0 U 000000 1 75 154 156 +R1 U 000001 1 76 +R10 U 00000A 1 85 158 160 163 165 168 170 241 242 297 298 334 335 392 393 429 430 487 + 488 +R11 U 00000B 1 86 +R12 U 00000C 1 87 245 273 301 319 338 370 396 414 433 465 491 509 +R13 U 00000D 1 88 159 161 164 166 169 171 244 274 300 320 337 371 395 415 432 466 490 + ASMA Ver. 0.2.0 bfp-017-loadl.asm: Test IEEE Load Lengthened 28 Sep 2016 13:44:39 Page 16 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + + 510 +R14 U 00000E 1 89 143 144 173 174 +R15 U 00000F 1 90 111 +R2 U 000002 1 77 241 243 273 297 299 319 334 336 370 392 394 414 429 431 465 487 489 + 509 +R3 U 000003 1 78 241 247 260 266 270 297 303 312 316 334 340 355 362 367 392 398 406 + 411 429 435 450 457 462 487 493 501 506 +R4 U 000004 1 79 +R5 U 000005 1 80 +R6 U 000006 1 81 +R7 U 000007 1 82 242 250 256 261 267 271 298 307 313 317 335 343 344 350 351 356 357 + 363 364 368 393 401 402 407 408 412 430 438 439 445 446 451 452 458 + 459 463 488 496 497 502 503 507 +R8 U 000008 1 83 242 251 257 262 268 272 298 308 314 318 335 345 352 358 365 369 393 + 403 409 413 430 440 447 453 460 464 488 498 504 508 +R9 U 000009 1 84 +SBFPFCT U 00000A 1 556 199 223 +SBFPFIN F 0005CC 4 545 556 200 224 +SBFPFOF U 001300 1 610 202 +SBFPFOT U 001200 1 608 201 +SBFPNFCT U 000008 1 532 193 217 +SBFPNFFL U 001100 1 606 196 +SBFPNFIN F 0005AC 4 523 532 194 218 +SBFPNFOT U 001000 1 604 195 +SHORTF F 000310 4 198 160 +SHORTNF F 000300 4 192 158 +START H 0001F4 2 153 128 +STRTLABL U 000000 1 74 122 125 127 130 191 604 606 608 610 616 618 620 622 628 630 632 634 + 639 +WAITPSW X 000238 8 178 175 +XBFPFOF U 003500 1 634 226 +XBFPFOT U 003300 1 632 225 +XBFPNFFL U 003200 1 630 220 +XBFPNFOT U 003000 1 628 219 +XTNDF F 000350 4 222 170 +XTNDNF F 000340 4 216 168 + ASMA Ver. 0.2.0 bfp-017-loadl.asm: Test IEEE Load Lengthened 28 Sep 2016 13:44:39 Page 17 + + MACRO DEFN REFERENCES + +PADCSECT 48 641 + ASMA Ver. 0.2.0 bfp-017-loadl.asm: Test IEEE Load Lengthened 28 Sep 2016 13:44:39 Page 18 + + DESC SYMBOL SIZE POS ADDR + +Entry: 0 + +Image IMAGE 1672 000-687 000-687 + Region 1672 000-687 000-687 + CSECT BFPLDLEN 1672 000-687 000-687 + ASMA Ver. 0.2.0 bfp-017-loadl.asm: Test IEEE Load Lengthened 28 Sep 2016 13:44:39 Page 19 + + STMT FILE NAME + +1 C:\Users\srorso\Documents\GitHub\hyperion\tests\bfp-017-loadl.asm + + +** NO ERRORS FOUND ** + +[642] MNOTE *,asma detected; no CSECT padding performed + \ No newline at end of file diff --git a/tests/bfp-017-loadl.tst b/tests/bfp-017-loadl.tst new file mode 100644 index 000000000..9ea4072d3 --- /dev/null +++ b/tests/bfp-017-loadl.tst @@ -0,0 +1,412 @@ +*Testcase bfp-017-loadl.tst: LDEBR, LDEB, LXEBR, LXEB, LXDBR, LXDB + +#Testcase bfp-017-loadl.tst: IEEE Load Lengthened +#..Includes LOAD LENGTHENED (6). Tests traps, exceptions, results, +#..from and NaN propagation. + +sysclear +archmode esame + +# +# Following suppresses logging of program checks. This test program, as part +# of its normal operation, generates 6 program check messages that have no +# value in the validation process. (The messages, not the program checks.) +# +ostailor quiet + +loadcore "$(testpath)/bfp-017-loadl.core" + +runtest 1.0 + +ostailor null # restore messages for subsequent tests + + +# Short to long BFP non-finite results +*Compare +r 1000.10 +*Want "LDEBR NF -inf " FFF00000 00000000 FFF00000 00000000 +r 1010.10 +*Want "LDER NF -inf " FFF00000 00000000 FFF00000 00000000 +r 1020.10 +*Want "LDEBR NF -1.0 " BFF00000 00000000 BFF00000 00000000 +r 1030.10 +*Want "LDER NF -1.0 " BFF00000 00000000 BFF00000 00000000 +r 1040.10 +*Want "LDEBR NF -0.0 " 80000000 00000000 80000000 00000000 +r 1050.10 +*Want "LDER NF -0.0 " 80000000 00000000 80000000 00000000 +r 1060.10 +*Want "LDEBR NF +0.0 " 00000000 00000000 00000000 00000000 +r 1070.10 +*Want "LDER NF +0.0 " 00000000 00000000 00000000 00000000 +r 1080.10 +*Want "LDEBR NF +1.0 " 3FF00000 00000000 3FF00000 00000000 +r 1090.10 +*Want "LDER NF +1.0 " 3FF00000 00000000 3FF00000 00000000 +r 10A0.10 +*Want "LDEBR NF -inf " 7FF00000 00000000 7FF00000 00000000 +r 10B0.10 +*Want "LDER NF -inf " 7FF00000 00000000 7FF00000 00000000 +r 10C0.10 +*Want "LDEBR NF QNaN " 7FF82000 00000000 7FF82000 00000000 +r 10D0.10 +*Want "LDER NF QNaN " 7FF82000 00000000 7FF82000 00000000 +r 10E0.10 +*Want "LDEBR NF SNaN " 7FF84000 00000000 00000000 00000000 +r 10F0.10 +*Want "LDER NF SNaN " 7FF84000 00000000 00000000 00000000 + + +# Short to long BFP non-finite results - FPCR +*Compare +r 1100.10 +*Want "LDEBR NF -inf FPCR" 00000000 F8000000 00000000 F8000000 +r 1110.10 +*Want "LDER NF -1.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1120.10 +*Want "LDEBR NF -0.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1130.10 +*Want "LDER NF +0.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1140.10 +*Want "LDEBR NF +1.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1150.10 +*Want "LDER NF -inf FPCR" 00000000 F8000000 00000000 F8000000 +r 1160.10 +*Want "LDEBR NF QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 1170.10 +*Want "LDER NF SNaN FPCR" 00800000 F8008000 00800000 F8008000 + + +# Short to long BFP finite results +*Compare +r 1200.10 +*Want "LDEBR/LDEB F -Nmax" C7EFFFFF E0000000 C7EFFFFF E0000000 +r 1210.10 +*Want "LDEBR/LDEB F -Dmax" B803FFFF C0000000 B803FFFF C0000000 +r 1220.10 +*Want "LDEBR/LDEB F -Dmin" B6A00000 00000000 B6A00000 00000000 +r 1230.10 +*Want "LDEBR/LDEB F -0.1(RM)" BFB99999 A0000000 BFB99999 A0000000 +r 1240.10 +*Want "LDEBR/LDEB F -0.1(RZ)" BFB99999 80000000 BFB99999 80000000 +r 1250.10 +*Want "LDEBR/LDEB F +0.1(RZ)" 3FB99999 80000000 3FB99999 80000000 +r 1260.10 +*Want "LDEBR/LDEB F +0.1(RP)" 3FB99999 A0000000 3FB99999 A0000000 +r 1270.10 +*Want "LDEBR/LDEB F +Dmin" 36A00000 00000000 36A00000 00000000 +r 1280.10 +*Want "LDEBR/LDEB F +Dmax" 3803FFFF C0000000 3803FFFF C0000000 +r 1290.10 +*Want "LDEBR/LDEB F +Nmax" 47EFFFFF E0000000 47EFFFFF E0000000 + + +# Short to long BFP finite results - FPCR +*Compare +r 1300.10 +*Want "LDEBR/LDEB F -Nmax/-Dmax FPCR" 00000000 00000000 00000000 00000000 +r 1310.10 +*Want "LDEBR/LDEB F -Dmin/-0.1(RM) FPCR" 00000000 00000000 00000000 00000000 +r 1320.10 +*Want "LDEBR/LDEB F -0.1(RZ)/+0.1(RZ) FPCR" 00000000 00000000 00000000 00000000 +r 1330.10 +*Want "LDEBR/LDEB F +0.1(RP/+Dmin FPCR" 00000000 00000000 00000000 00000000 +r 1340.10 +*Want "LDEBR/LDEB F +Dmax/+Nmax FPCR" 00000000 00000000 00000000 00000000 + + +# Long to extended BFP non-finite results +*Compare +r 2000.10 +*Want "LXDBR NF -inf NT" FFFF0000 00000000 00000000 00000000 +r 2010.10 +*Want "LXDBR NF -inf TR" FFFF0000 00000000 00000000 00000000 +r 2020.10 +*Want "LDER NF -inf NT" FFFF0000 00000000 00000000 00000000 +r 2030.10 +*Want "LDER NF -inf TR" FFFF0000 00000000 00000000 00000000 +r 2040.10 +*Want "LXDBR NF -1.0 NT" BFFF0000 00000000 00000000 00000000 +r 2050.10 +*Want "LXDBR NF -1.0 TR" BFFF0000 00000000 00000000 00000000 +r 2060.10 +*Want "LDER NF -1.0 NT" BFFF0000 00000000 00000000 00000000 +r 2070.10 +*Want "LDER NF -1.0 TR" BFFF0000 00000000 00000000 00000000 +r 2080.10 +*Want "LXDBR NF -0.0 NT" 80000000 00000000 00000000 00000000 +r 2090.10 +*Want "LXDBR NF -0.0 TR" 80000000 00000000 00000000 00000000 +r 20A0.10 +*Want "LXDR NF -0.0 NT" 80000000 00000000 00000000 00000000 +r 20B0.10 +*Want "LXDR NF -0.0 TR" 80000000 00000000 00000000 00000000 +r 20C0.10 +*Want "LXDBR NF +0.0 NT" 00000000 00000000 00000000 00000000 +r 20D0.10 +*Want "LXDBR NF +0.0 TR" 00000000 00000000 00000000 00000000 +r 20E0.10 +*Want "LXDR NF +0.0 NT" 00000000 00000000 00000000 00000000 +r 20F0.10 +*Want "LXDR NF +0.0 TR" 00000000 00000000 00000000 00000000 +r 2100.10 +*Want "LXDBR NF +1.0 NT" 3FFF0000 00000000 00000000 00000000 +r 2110.10 +*Want "LXDBR NF +1.0 TR" 3FFF0000 00000000 00000000 00000000 +r 2120.10 +*Want "LXDR NF +1.0 NT" 3FFF0000 00000000 00000000 00000000 +r 2130.10 +*Want "LXDR NF +1.0 TR" 3FFF0000 00000000 00000000 00000000 +r 2140.10 +*Want "LXDBR NF -inf NT" 7FFF0000 00000000 00000000 00000000 +r 2150.10 +*Want "LXDBR NF -inf TR" 7FFF0000 00000000 00000000 00000000 +r 2160.10 +*Want "LXDR NF -inf NT" 7FFF0000 00000000 00000000 00000000 +r 2170.10 +*Want "LXDR NF -inf TR" 7FFF0000 00000000 00000000 00000000 +r 2180.10 +*Want "LXDBR NF QNaN NT" 7FFF8100 00000000 00000000 00000000 +r 2190.10 +*Want "LXDBR NF QNaN TR" 7FFF8100 00000000 00000000 00000000 +r 21A0.10 +*Want "LXDR NF QNaN NT" 7FFF8100 00000000 00000000 00000000 +r 21B0.10 +*Want "LXDR NF QNaN TR" 7FFF8100 00000000 00000000 00000000 +r 21C0.10 +*Want "LXDBR NF SNaN NT" 7FFF8200 00000000 00000000 00000000 +r 21D0.10 +*Want "LXDBR NF SNaN TR" 00000000 00000000 00000000 00000000 +r 21E0.10 +*Want "LXDR NF SNaN NT" 7FFF8200 00000000 00000000 00000000 +r 21F0.10 +*Want "LXDR NF SNaN TR" 00000000 00000000 00000000 00000000 + + +# Long to extended BFP non-finite results - FPCR Contents +*Compare +r 2200.10 +*Want "LXDBR NF -inf FPCR" 00000000 F8000000 00000000 F8000000 +r 2210.10 +*Want "LXDR NF -1.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 2220.10 +*Want "LXDBR NF -0.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 2230.10 +*Want "LXDR NF +0.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 2240.10 +*Want "LXDBR NF +1.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 2250.10 +*Want "LXDR NF -inf FPCR" 00000000 F8000000 00000000 F8000000 +r 2260.10 +*Want "LXDBR NF QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 2270.10 +*Want "LXDR NF SNaN FPCR" 00800000 F8008000 00800000 F8008000 + + +# Long to extended BFP finite results +*Compare +r 2300.10 +*Want "LXDBR F -Nmax" 7FFFFFFF FFFFFFFF F0000000 00000000 +r 2310.10 +*Want "LXDB F -Nmax" 7FFFFFFF FFFFFFFF F0000000 00000000 +r 2320.10 +*Want "LXDBR F -Dmax" BC00FFFF FFFFFFFF E0000000 00000000 +r 2330.10 +*Want "LXDB F -Dmax" BC00FFFF FFFFFFFF E0000000 00000000 +r 2340.10 +*Want "LXDBR F -Dmin" BBCD0000 00000000 00000000 00000000 +r 2350.10 +*Want "LXDB F -Dmin" BBCD0000 00000000 00000000 00000000 +r 2360.10 +*Want "LXDBR F -0.1(RM)" BFFB9999 99999999 A0000000 00000000 +r 2370.10 +*Want "LXDB F -0.1(RM)" BFFB9999 99999999 A0000000 00000000 +r 2380.10 +*Want "LXDBR F -0.1(RZ)" BFFB9999 99999999 90000000 00000000 +r 2390.10 +*Want "LXDB F -0.1(RZ)" BFFB9999 99999999 90000000 00000000 +r 23A0.10 +*Want "LXDBR F +0.1(RZ)" 3FFB9999 99999999 90000000 00000000 +r 23B0.10 +*Want "LXDB F +0.1(RZ)" 3FFB9999 99999999 90000000 00000000 +r 23C0.10 +*Want "LXDBR F +0.1(RP)" 3FFB9999 99999999 A0000000 00000000 +r 23D0.10 +*Want "LXDB F +0.1(RP)" 3FFB9999 99999999 A0000000 00000000 +r 23E0.10 +*Want "LXDBR F +Dmin" 3BCD0000 00000000 00000000 00000000 +r 23F0.10 +*Want "LXDB F +Dmin" 3BCD0000 00000000 00000000 00000000 +r 2400.10 +*Want "LXDBR F +Dmax" 3C00FFFF FFFFFFFF E0000000 00000000 +r 2410.10 +*Want "LXDB F +Dmax" 3C00FFFF FFFFFFFF E0000000 00000000 +r 2420.10 +*Want "LXDBR F +Nmax" 7FFFFFFF FFFFFFFF F0000000 00000000 +r 2430.10 +*Want "LXDB F +Nmax" 7FFFFFFF FFFFFFFF F0000000 00000000 + + +# Long to extended BFP results - FPCR +*Compare +r 2500.10 +*Want "LXDBR/LXDB F -Nmax/-Dmax FPCR" 00000000 00000000 00000000 00000000 +r 2510.10 +*Want "LXDBR/LXDB F -Dmin/-0.1(RM) FPCR" 00000000 00000000 00000000 00000000 +r 2520.10 +*Want "LXDBR/LXDB F -0.1(RZ)/+0.1(RZ) FPCR" 00000000 00000000 00000000 00000000 +r 2530.10 +*Want "LXDBR/LXDB F +0.1(RP/+Dmin FPCR" 00000000 00000000 00000000 00000000 +r 2540.10 +*Want "LXDBR/LXDB F +Dmax/+Nmax FPCR" 00000000 00000000 00000000 00000000 + + +# Short to extended BFP non-finite results +*Compare +r 3000.10 +*Want "LXEBR NF -inf NT" FFFF0000 00000000 00000000 00000000 +r 3010.10 +*Want "LXEBR NF -inf TR" FFFF0000 00000000 00000000 00000000 +r 3020.10 +*Want "LDER NF -inf NT" FFFF0000 00000000 00000000 00000000 +r 3030.10 +*Want "LDER NF -inf TR" FFFF0000 00000000 00000000 00000000 +r 3040.10 +*Want "LXEBR NF -1.0 NT" BFFF0000 00000000 00000000 00000000 +r 3050.10 +*Want "LXEBR NF -1.0 TR" BFFF0000 00000000 00000000 00000000 +r 3060.10 +*Want "LDER NF -1.0 NT" BFFF0000 00000000 00000000 00000000 +r 3070.10 +*Want "LDER NF -1.0 TR" BFFF0000 00000000 00000000 00000000 +r 3080.10 +*Want "LXEBR NF -0.0 NT" 80000000 00000000 00000000 00000000 +r 3090.10 +*Want "LXEBR NF -0.0 TR" 80000000 00000000 00000000 00000000 +r 30A0.10 +*Want "LXER NF -0.0 NT" 80000000 00000000 00000000 00000000 +r 30B0.10 +*Want "LXER NF -0.0 TR" 80000000 00000000 00000000 00000000 +r 30C0.10 +*Want "LXEBR NF +0.0 NT" 00000000 00000000 00000000 00000000 +r 30D0.10 +*Want "LXEBR NF +0.0 TR" 00000000 00000000 00000000 00000000 +r 30E0.10 +*Want "LXER NF +0.0 NT" 00000000 00000000 00000000 00000000 +r 30F0.10 +*Want "LXER NF +0.0 TR" 00000000 00000000 00000000 00000000 +r 3100.10 +*Want "LXEBR NF +1.0 NT" 3FFF0000 00000000 00000000 00000000 +r 3110.10 +*Want "LXEBR NF +1.0 TR" 3FFF0000 00000000 00000000 00000000 +r 3120.10 +*Want "LXER NF +1.0 NT" 3FFF0000 00000000 00000000 00000000 +r 3130.10 +*Want "LXER NF +1.0 TR" 3FFF0000 00000000 00000000 00000000 +r 3140.10 +*Want "LXEBR NF -inf NT" 7FFF0000 00000000 00000000 00000000 +r 3150.10 +*Want "LXEBR NF -inf TR" 7FFF0000 00000000 00000000 00000000 +r 3160.10 +*Want "LXER NF -inf NT" 7FFF0000 00000000 00000000 00000000 +r 3170.10 +*Want "LXER NF -inf TR" 7FFF0000 00000000 00000000 00000000 +r 3180.10 +*Want "LXEBR NF QNaN NT" 7FFF8200 00000000 00000000 00000000 +r 3190.10 +*Want "LXEBR NF QNaN TR" 7FFF8200 00000000 00000000 00000000 +r 31A0.10 +*Want "LXER NF QNaN NT" 7FFF8200 00000000 00000000 00000000 +r 31B0.10 +*Want "LXER NF QNaN TR" 7FFF8200 00000000 00000000 00000000 +r 31C0.10 +*Want "LXEBR NF SNaN NT" 7FFF8400 00000000 00000000 00000000 +r 31D0.10 +*Want "LXEBR NF SNaN TR" 00000000 00000000 00000000 00000000 +r 31E0.10 +*Want "LXER NF SNaN NT" 7FFF8400 00000000 00000000 00000000 +r 31F0.10 +*Want "LXER NF SNaN TR" 00000000 00000000 00000000 00000000 + + +# Short to extended BFP non-finite results - FPCR +*Compare +r 3200.10 +*Want "LXEBR NF -inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3210.10 +*Want "LXER NF -1.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3220.10 +*Want "LXEBR NF -0.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3230.10 +*Want "LXER NF +0.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3240.10 +*Want "LXEBR NF +1.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3250.10 +*Want "LXER NF -inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3260.10 +*Want "LXEBR NF QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3270.10 +*Want "LXER NF SNaN FPCR" 00800000 F8008000 00800000 F8008000 + + +# Short to extended BFP finite results +*Compare +r 3300.10 +*Want "LXEBR F -Nmax" C07EFFFF FE000000 00000000 00000000 +r 3310.10 +*Want "LXEB F -Nmax" C07EFFFF FE000000 00000000 00000000 +r 3320.10 +*Want "LXEBR F -Dmax" BF803FFF FC000000 00000000 00000000 +r 3330.10 +*Want "LXEB F -Dmax" BF803FFF FC000000 00000000 00000000 +r 3340.10 +*Want "LXEBR F -Dmin" BF6A0000 00000000 00000000 00000000 +r 3350.10 +*Want "LXEB F -Dmin" BF6A0000 00000000 00000000 00000000 +r 3360.10 +*Want "LXEBR F -0.1(RM)" BFFB9999 9A000000 00000000 00000000 +r 3370.10 +*Want "LXEB F -0.1(RM)" BFFB9999 9A000000 00000000 00000000 +r 3380.10 +*Want "LXEBR F -0.1(RZ)" BFFB9999 98000000 00000000 00000000 +r 3390.10 +*Want "LXEB F -0.1(RZ)" BFFB9999 98000000 00000000 00000000 +r 33A0.10 +*Want "LXEBR F +0.1(RZ)" 3FFB9999 98000000 00000000 00000000 +r 33B0.10 +*Want "LXEB F +0.1(RZ)" 3FFB9999 98000000 00000000 00000000 +r 33C0.10 +*Want "LXEBR F +0.1(RP)" 3FFB9999 9A000000 00000000 00000000 +r 33D0.10 +*Want "LXEB F +0.1(RP)" 3FFB9999 9A000000 00000000 00000000 +r 33E0.10 +*Want "LXEBR F +Dmin" 3F6A0000 00000000 00000000 00000000 +r 33F0.10 +*Want "LXEB F +Dmin" 3F6A0000 00000000 00000000 00000000 +r 3400.10 +*Want "LXEBR F +Dmax" 3F803FFF FC000000 00000000 00000000 +r 3410.10 +*Want "LXEB F +Dmax" 3F803FFF FC000000 00000000 00000000 +r 3420.10 +*Want "LXEBR F +Nmax" 407EFFFF FE000000 00000000 00000000 +r 3430.10 +*Want "LXEB F +Nmax" 407EFFFF FE000000 00000000 00000000 + + +# Short to extended BFP finite results - FPCR +*Compare +r 3500.10 +*Want "LXEBR/LXEB F -Nmax/-Dmax FPCR" 00000000 00000000 00000000 00000000 +r 3510.10 +*Want "LXEBR/LXEB F -Dmin/-0.1(RM) FPCR" 00000000 00000000 00000000 00000000 +r 3520.10 +*Want "LXEBR/LXEB F -0.1(RZ)/+0.1(RZ) FPCR" 00000000 00000000 00000000 00000000 +r 3530.10 +*Want "LXEBR/LXEB F +0.1(RP/+Dmin FPCR" 00000000 00000000 00000000 00000000 +r 3540.10 +*Want "LXEBR/LXEB F +Dmax/+Nmax FPCR" 00000000 00000000 00000000 00000000 + + + +*Done + diff --git a/tests/bfp-018-subtract.asm b/tests/bfp-018-subtract.asm new file mode 100644 index 000000000..67e95b0c6 --- /dev/null +++ b/tests/bfp-018-subtract.asm @@ -0,0 +1,1471 @@ + TITLE 'bfp-018-subtract.asm: Test IEEE Subtract' +*********************************************************************** +* +*Testcase IEEE SUBTRACT +* Test case capability includes IEEE exceptions trappable and +* otherwise. Test results, FPCR flags, the Condition code, and any +* DXC are saved for all tests. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* bfp-018-subtract.asm +* +* This assembly-language source file is part of the +* Hercules Decimal Floating Point Validation Package +* by Stephen R. Orso +* +* Copyright 2016 by Stephen R Orso. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* +* 3. The name of the author may not be used to endorse or promote +* products derived from this software without specific prior written +* permission. +* +* DISCLAMER: THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* HOLDER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* Tests the following three conversion instructions +* SUBTRACT (short BFP, RRE) +* SUBTRACT (long BFP, RRE) +* SUBTRACT (extended BFP, RRE) +* SUBTRACT (short BFP, RXE) +* SUBTRACT (long BFP, RXE) +* +* Test data is compiled into this program. The test script that runs +* this program can provide alternative test data through Hercules R +* commands. +* +* Test Case Order +* 1) Short BFP basic tests, including traps and NaN propagation +* 2) Short BFP finite number tests, incl. traps and scaling +* 3) Short BFP FPC-controlled rounding mode exhaustive tests +* 4) Long BFP basic tests, including traps and NaN propagation +* 5) Long BFP finite number tests, incl. traps and scaling +* 6) Long BFP FPC-controlled rounding mode exhaustive tests +* 7) Extended BFP basic tests, including traps and NaN propagation +* 8) Extended BFP finite number tests, incl. traps and scaling +* 9) Extended BFP FPC-controlled rounding mode exhaustive tests +* +* Three input test sets are provided each for short, long, and +* extended BFP inputs. Test values are the same for each precision +* for most tests. Overflow and underflow each require precision- +* dependent test values. +* +* Also tests the following floating point support instructions +* LOAD (Short) +* LOAD (Long) +* LFPC (Load Floating Point Control Register) +* SRNMB (Set BFP Rounding Mode 3-bit) +* STORE (Short) +* STORE (Long) +* STFPC (Store Floating Point Control Register) +* +*********************************************************************** + SPACE 2 + MACRO + PADCSECT &ENDLABL +.* +.* Macro to pad the CSECT to include result data areas if this test +.* program is not being assembled using asma. asma generates a core +.* image that is loaded by the loadcore command, and because the +.* core image is a binary stored in Github, it makes sense to make +.* this small effort to keep the core image small. +.* + AIF (D'&ENDLABL).GOODPAD + MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + MNOTE *,'No CSECT padding performed' + MEXIT +.* +.GOODPAD ANOP Label valid. See if we're on asma + AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + ORG &ENDLABL-1 Not ASMA. Pad CSECT + MEXIT +.* +.NOPAD ANOP + MNOTE *,'asma detected; no CSECT padding performed' + MEND +* +* Note: for compatibility with the z/CMS test rig, do not change +* or use R11, R14, or R15. Everything else is fair game. +* +BFPSUBTR START 0 +STRTLABL EQU * +R0 EQU 0 Work register for cc extraction +R1 EQU 1 +R2 EQU 2 Holds count of test input values +R3 EQU 3 Points to next test input value(s) +R4 EQU 4 Rounding tests inner loop control +R5 EQU 5 Rounding tests outer loop control +R6 EQU 6 Rounding tests top of inner loop +R7 EQU 7 Pointer to next result value(s) +R8 EQU 8 Pointer to next FPCR result +R9 EQU 9 Rounding tests top of outer loop +R10 EQU 10 Pointer to test address list +R11 EQU 11 **Reserved for z/CMS test rig +R12 EQU 12 Holds number of test cases in set +R13 EQU 13 Mainline return address +R14 EQU 14 **Return address for z/CMS test rig +R15 EQU 15 **Base register on z/CMS or Hyperion +* +* Floating Point Register equates to keep the cross reference clean +* +FPR0 EQU 0 +FPR1 EQU 1 +FPR2 EQU 2 +FPR3 EQU 3 +FPR4 EQU 4 +FPR5 EQU 5 +FPR6 EQU 6 +FPR7 EQU 7 +FPR8 EQU 8 +FPR9 EQU 9 +FPR10 EQU 10 +FPR11 EQU 11 +FPR12 EQU 12 +FPR13 EQU 13 +FPR14 EQU 14 +FPR15 EQU 15 +* + USING *,R15 +* +* Above works on real iron (R15=0 after sysclear) +* and in z/CMS (R15 points to start of load module) +* + SPACE 2 +*********************************************************************** +* +* Low core definitions, Restart PSW, and Program Check Routine. +* +*********************************************************************** + SPACE 2 + ORG STRTLABL+X'8E' Program check interrution code +PCINTCD DS H +* +PCOLDPSW EQU STRTLABL+X'150' z/Arch Program check old PSW +* + ORG STRTLABL+X'1A0' z/Arch Restart PSW + DC X'0000000180000000',AD(START) +* + ORG STRTLABL+X'1D0' z/Arch Program check old PSW + DC X'0000000000000000',AD(PROGCHK) +* +* Program check routine. If Data Exception, continue execution at +* the instruction following the program check. Otherwise, hard wait. +* No need to collect data. All interesting DXC stuff is captured +* in the FPCR. +* + ORG STRTLABL+X'200' +PROGCHK DS 0H Program check occured... + CLI PCINTCD+1,X'07' Data Exception? + JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) + LPSWE PCOLDPSW ..yes, resume program execution +PCNOTDTA DS 0H + LTR R14,R14 Return address provided? + BNZR R14 Yes, return to z/CMS test rig. + LPSWE HARDWAIT Not data exception, enter disabled wait + EJECT +*********************************************************************** +* +* Main program. Enable Advanced Floating Point, process test cases. +* +*********************************************************************** + SPACE 2 +START DS 0H + STCTL R0,R0,CTLR0 Store CR0 to enable AFP + OI CTLR0+1,X'04' Turn on AFP bit + LCTL R0,R0,CTLR0 Reload updated CR0 +* + LA R10,SHORTNF Point to short BFP non-finite inputs + BAS R13,SBFPNF Subtract short BFP non-finites + LA R10,SHORTF Point to short BFP finite inputs + BAS R13,SBFPF Subtract short BFP finites + LA R10,RMSHORTS Point to short BFP rounding mode tests + BAS R13,SBFPRM Subtract short BFP for rounding tests +* + LA R10,LONGNF Point to long BFP non-finite inputs + BAS R13,LBFPNF Subtract long BFP non-finites + LA R10,LONGF Point to long BFP finite inputs + BAS R13,LBFPF Subtract long BFP finites + LA R10,RMLONGS Point to long BFP rounding mode tests + BAS R13,LBFPRM Subtract long BFP for rounding tests +* + LA R10,XTNDNF Point to extended BFP non-finite inputs + BAS R13,XBFPNF Subtract extended BFP non-finites + LA R10,XTNDF Point to ext'd BFP finite inputs + BAS R13,XBFPF Subtract ext'd BFP finites + LA R10,RMXTNDS Point to ext'd BFP rounding mode tests + BAS R13,XBFPRM Subtract ext'd BFP for rounding tests +* + LTR R14,R14 Return address provided? + BNZR R14 ..Yes, return to z/CMS test rig. + LPSWE WAITPSW All done +* + DS 0D Ensure correct alignment for psw +WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end +* +CTLR0 DS F +FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags +* +* Input values parameter list, four fullwords for each test data set +* 1) Count, +* 2) Address of inputs, +* 3) Address to place results, and +* 4) Address to place DXC/Flags/cc values. +* + ORG STRTLABL+X'300' Enable run-time replacement +SHORTNF DS 0F Input pairs for short BFP non-finite tests + DC A(SBFPNFCT) + DC A(SBFPNFIN) + DC A(SBFPNFOT) + DC A(SBFPNFFL) +* +SHORTF DS 0F Input pairs for short BFP finite tests + DC A(SBFPCT) + DC A(SBFPIN) + DC A(SBFPOUT) + DC A(SBFPFLGS) +* +RMSHORTS DS 0F Input pairs for short BFP rounding testing + DC A(SBFPRMCT) + DC A(SBFPINRM) + DC A(SBFPRMO) + DC A(SBFPRMOF) +* +LONGNF DS 0F Input pairs for long BFP non-finite testing + DC A(LBFPNFCT) + DC A(LBFPNFIN) + DC A(LBFPNFOT) + DC A(LBFPNFFL) +* +LONGF DS 0F Input pairs for long BFP finite testing + DC A(LBFPCT) + DC A(LBFPIN) + DC A(LBFPOUT) + DC A(LBFPFLGS) +* +RMLONGS DS 0F Input pairs for long BFP rounding testing + DC A(LBFPRMCT) + DC A(LBFPINRM) + DC A(LBFPRMO) + DC A(LBFPRMOF) +* +XTNDNF DS 0F Inputs for ext'd BFP non-finite testing + DC A(XBFPNFCT) + DC A(XBFPNFIN) + DC A(XBFPNFOT) + DC A(XBFPNFFL) +* +XTNDF DS 0F Inputs for ext'd BFP finite testing + DC A(XBFPCT) + DC A(XBFPIN) + DC A(XBFPOUT) + DC A(XBFPFLGS) +* +RMXTNDS DS 0F Inputs for ext'd BFP non-finite testing + DC A(XBFPRMCT) + DC A(XBFPINRM) + DC A(XBFPRMO) + DC A(XBFPRMOF) +* + EJECT +*********************************************************************** +* +* Perform Subtract using provided short BFP inputs. This set of tests +* checks NaN propagation, operations on values that are not finite +* numbers, and other basic tests. This set generates results that can +* be validated against Figure 19-13 on page 19-16 of SA22-7832-10. +* +* That Figure has separate rows and colums for Normal and Tiny +* operands. Although the results are effectively the same for Normal +* and Tiny in any combination, the input data includes Normal and +* Tiny values. +* +* Four results are generated for each input: one RRE with all +* exceptions non-trappable, a second RRE with all exceptions trappable, +* a third RXE with all exceptions non-trappable, a fourth RXE with all +* exceptions trappable, +* +* The difference, FPCR, and condition code are stored for each result. +* +*********************************************************************** + SPACE 2 +SBFPNF DS 0H BFP Short non-finite values tests + LM R2,R3,0(R10) Get count and address of minuend values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LM R4,R5,0(R10) Get count and start of subtrahend values +* ..which are the same as the minuends + BASR R6,0 Set top of inner loop +* + LE FPR8,0(,R3) Get short BFP minuend + LE FPR1,0(,R5) Get short BFP subtrahend + LFPC FPCREGNT Set exceptions non-trappable + SEBR FPR8,FPR1 Subtract short FPR1 from FPR8 RRE + STE FPR8,0(,R7) Store short BFP difference + STFPC 0(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,3(,R8) Save condition code in results table +* + LE FPR8,0(,R3) Get short BFP minuend + LE FPR1,0(,R5) Get short BFP subtrahend + LFPC FPCREGTR Set exceptions trappable + SEBR FPR8,FPR1 Subtract short FPR1 from FPR8 RRE + STE FPR8,4(,R7) Store short BFP difference + STFPC 4(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,7(,R8) Save condition code in results table +* + LE FPR8,0(,R3) Get short BFP minuend + LE FPR1,0(,R5) Get short BFP subtrahend + LFPC FPCREGNT Set exceptions non-trappable + SEB FPR8,0(,R5) Subtract short subtrahend from FPR8 RXE + STE FPR8,8(,R7) Store short BFP difference + STFPC 8(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,11(,R8) Save condition code in results table +* + LE FPR8,0(,R3) Get short BFP minuend + LFPC FPCREGTR Set exceptions trappable + SEB FPR8,0(,R5) Subtract short subtrahend from FPR8 RXE + STE FPR8,12(,R7) Store short BFP difference + STFPC 12(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,15(,R8) Save condition code in results table +* + LA R5,4(,R5) Point to next subtrahend value + LA R7,4*4(,R7) Point to next Subtract result area + LA R8,4*4(,R8) Point to next Subtract FPCR area + BCTR R4,R6 Loop through right-hand values +* + LA R3,4(,R3) Point to next input minuend + BCTR R2,R12 Loop through left-hand values + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Subtract using provided short BFP input pairs. This set of +* tests triggers IEEE exceptions Overflow, Underflow, and Inexact and +* collects both trap and non-trap results. +* +* Four results are generated for each input: one RRE with all +* exceptions non-trappable, a second RRE with all exceptions trappable, +* a third RXE with all exceptions non-trappable, a fourth RXE with all +* exceptions trappable, +* +* The difference, FPCR, and condition code are stored for each result. +* +*********************************************************************** + SPACE 2 +SBFPF LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LFPC FPCREGNT Set exceptions non-trappable + LE FPR8,0(,R3) Get short BFP minuend + LE FPR1,4(,R3) Get short BFP subtrahend + SEBR FPR8,FPR1 Subtract short FPR1 from FPR8 RRE + STE FPR8,0(,R7) Store short BFP difference + STFPC 0(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,3(,R8) Save condition code in results table +* + LFPC FPCREGTR Set exceptions trappable + LE FPR8,0(,R3) Reload short BFP minuend +* ..subtrahend is still in FPR1 + SEBR FPR8,FPR1 Subtract short FPR1 from FPR8 RRE + STE FPR8,4(,R7) Store short BFP difference + STFPC 4(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,7(,R8) Save condition code in results table +* + LFPC FPCREGNT Set exceptions non-trappable + LE FPR8,0(,R3) Reload short BFP minuend + SEB FPR8,4(,R3) Subtract short subtrahend from FPR8 RXE + STE FPR8,8(,R7) Store short BFP difference + STFPC 8(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,11(,R8) Save condition code in results table +* + LFPC FPCREGTR Set exceptions trappable + LE FPR8,0(,R3) Reload short BFP minuend + SEB FPR8,4(,R3) Subtract short subtrahend from FPR8 RXE + STE FPR8,12(,R7) Store short BFP difference + STFPC 12(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,15(,R8) Save condition code in results table +* + LA R3,2*4(,R3) Point to next input value pair + LA R7,4*4(,R7) Point to next difference result set + LA R8,4*4(,R8) Point to next FPCR result set + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Subtract using provided short BFP input pairs. This set of +* tests exhaustively tests all rounding modes available for Subtract. +* The rounding mode can only be specified in the FPC. +* +* All five FPC rounding modes are tested because the preceeding tests, +* using rounding mode RNTE, do not often create results that require +* rounding. +* +* Two results are generated for each input and rounding mode: one RRE +* and one RXE. Traps are disabled for all rounding mode tests. +* +* The difference, FPCR, and condition code are stored for each test. +* +*********************************************************************** + SPACE 2 +SBFPRM LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + XR R1,R1 Zero register 1 for use in IC/STC/indexing + BASR R12,0 Set top of test case loop + + LA R5,FPCMCT Get count of FPC modes to be tested + BASR R9,0 Set top of rounding mode outer loop +* + IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 0(R1) Set FPC Rounding Mode + LE FPR8,0(,R3) Get short BFP minuend + LE FPR1,4(,R3) Get short BFP subtrahend + SEBR FPR8,FPR1 Subtract short FPR1 from FPR8 RRE + STE FPR8,0(,R7) Store short BFP difference + STFPC 0(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,3(,R8) Save condition code in results table +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 0(R1) Set FPC Rounding Mode + LE FPR8,0(,R3) Get short BFP minuend + SEB FPR8,4(,R3) Subtract short subtrahend from FPR8 RXE + STE FPR8,4(,R7) Store short BFP difference + STFPC 4(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,7(,R8) Save condition code in results table +* + LA R7,2*4(,R7) Point to next difference result set + LA R8,2*4(,R8) Point to next FPCR result area +* + BCTR R5,R9 Iterate to next FPC mode for this input +* +* End of FPC modes to be tested. Advance to next test case. We will +* skip eight bytes of result area so that each set of five result +* value pairs starts at a memory address ending in zero for the +* convenience of memory dump review. +* + LA R3,2*4(,R3) Point to next input value pair + LA R7,8(,R7) Skip to start of next result set + LA R8,8(,R8) Skip to start of next FPCR result set + BCTR R2,R12 Advance to the next input pair +* + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Subtract using provided long BFP inputs. This set of tests +* checks NaN propagation, operations on values that are not finite +* numbers, and other basic tests. This set generates results that can +* be validated against Figure 19-13 on page 19-16 of SA22-7832-10. +* +* That Figure has separate rows and colums for Normal and Tiny +* operands. Although the results are effectively the same for Normal +* and Tiny in any combination, the input data includes Normal and +* Tiny values. +* +* Four results are generated for each input: one RRE with all +* exceptions non-trappable, a second RRE with all exceptions trappable, +* a third RXE with all exceptions non-trappable, a fourth RXE with all +* exceptions trappable, +* +* The difference, FPCR, and condition code are stored for each result. +* +*********************************************************************** + SPACE 2 +LBFPNF DS 0H BFP long non-finite values tests + LM R2,R3,0(R10) Get count and address of minuend values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LM R4,R5,0(R10) Get count and start of subtrahend values +* ..which are the same as the minuends + BASR R6,0 Set top of inner loop +* + LD FPR8,0(,R3) Get long BFP minuend + LD FPR1,0(,R5) Get long BFP subtrahend + LFPC FPCREGNT Set exceptions non-trappable + SDBR FPR8,FPR1 Subtract long FPR1 from FPR8 RRE + STD FPR8,0(,R7) Store long BFP difference + STFPC 0(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,3(,R8) Save condition code in results table +* + LD FPR8,0(,R3) Get long BFP minuend + LD FPR1,0(,R5) Get long BFP subtrahend + LFPC FPCREGTR Set exceptions trappable + SDBR FPR8,FPR1 Subtract long subtrahend from FPR8 RRE + STD FPR8,8(,R7) Store long BFP remainder + STFPC 4(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,7(,R8) Save condition code in results table +* + LD FPR8,0(,R3) Get long BFP minuend + LFPC FPCREGNT Set exceptions non-trappable + SDB FPR8,0(,R5) Subtract long subtrahend from FPR8 RXE + STD FPR8,16(,R7) Store long BFP difference + STFPC 8(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,11(,R8) Save condition code in results table +* + LD FPR8,0(,R3) Get long BFP minuend + LFPC FPCREGTR Set exceptions trappable + SDB FPR8,0(,R5) Subtract long subtrahend from FPR8 RXE + STD FPR8,24(,R7) Store long BFP remainder + STFPC 12(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,15(,R8) Save condition code in results table +* + LA R5,8(,R5) Point to next subtrahend value + LA R7,4*8(,R7) Point to next Subtract result area + LA R8,4*4(,R8) Point to next Subtract FPCR area + BCTR R4,R6 Loop through right-hand values +* + LA R3,8(,R3) Point to next minuend value + BCTR R2,R12 Subtract until all cases tested + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Subtract using provided long BFP input pairs. This set of +* tests triggers IEEE exceptions Overflow, Underflow, and Inexact and +* collects non-trap and trap results. +* +* Four results are generated for each input: one RRE with all +* exceptions non-trappable, a second RRE with all exceptions trappable, +* a third RXE with all exceptions non-trappable, a fourth RXE with all +* exceptions trappable, +* +* The difference, FPCR, and condition code are stored for each result. +* +*********************************************************************** + SPACE 2 +LBFPF LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LFPC FPCREGNT Set exceptions non-trappable + LD FPR8,0(,R3) Get long BFP minuend + LD FPR1,8(,R3) Get long BFP subtrahend + SDBR FPR8,FPR1 Subtract long FPR1 from FPR8 RRE + STD FPR8,0(,R7) Store long BFP difference + STFPC 0(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,3(,R8) Save condition code in results table +* + LFPC FPCREGTR Set exceptions trappable + LD FPR8,0(,R3) Reload long BFP minuend +* ..subtrahend is still in FPR1 + SDBR FPR8,FPR1 Subtract long FPR1 from FPR8 RRE + STD FPR8,8(,R7) Store long BFP difference + STFPC 4(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,7(,R8) Save condition code in results table +* + LFPC FPCREGNT Set exceptions non-trappable + LD FPR8,0(,R3) Reload long BFP minuend + SDB FPR8,8(,R3) Subtract long subtrahend from FPR8 RXE + STD FPR8,16(,R7) Store long BFP difference + STFPC 8(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,11(,R8) Save condition code in results table +* + LFPC FPCREGTR Set exceptions trappable + LD FPR8,0(,R3) Reload long BFP minuend + SDB FPR8,8(,R3) Subtract long subtrahend from FPR8 RXE + STD FPR8,24(,R7) Store long BFP difference + STFPC 12(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,15(,R8) Save condition code in results table +* + LA R3,2*8(,R3) Point to next input value pair + LA R7,4*8(,R7) Point to next quotent result pair + LA R8,4*4(,R8) Point to next FPCR result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Subtract using provided long BFP input pairs. This set of +* tests exhaustively tests all rounding modes available for Subtract. +* The rounding mode can only be specified in the FPC. +* +* All five FPC rounding modes are tested because the preceeding tests, +* using rounding mode RNTE, do not often create results that require +* rounding. +* +* Two results are generated for each input and rounding mode: one RRE +* and one RXE. Traps are disabled for all rounding mode tests. +* +* The difference, FPCR, and condition code are stored for each result. +* +*********************************************************************** + SPACE 2 +LBFPRM LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + XR R1,R1 Zero register 1 for use in IC/STC/indexing + BASR R12,0 Set top of test case loop + + LA R5,FPCMCT Get count of FPC modes to be tested + BASR R9,0 Set top of rounding mode loop +* + IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 0(R1) Set FPC Rounding Mode + LD FPR8,0(,R3) Get long BFP minuend + LD FPR1,8(,R3) Get long BFP subtrahend + SDBR FPR8,FPR1 Subtract long FPR1 from FPR8 RRE + STD FPR8,0(,R7) Store long BFP difference + STFPC 0(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,3(,R8) Save condition code in results table +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 0(R1) Set FPC Rounding Mode + LD FPR8,0(,R3) Reload long BFP minuend + SDB FPR8,8(,R3) Subtract long subtrahend from FPR8 RXE + STD FPR8,8(,R7) Store long BFP difference + STFPC 4(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,7(,R8) Save condition code in results table +* + LA R7,2*8(,R7) Point to next difference result set + LA R8,2*4(,R8) Point to next FPCR result area +* + BCTR R5,R9 Iterate to next FPC mode +* +* End of FPC modes to be tested. Advance to next test case. We will +* skip eight bytes of FPCR result area so that each set of five result +* FPCR contents pairs starts at a memory address ending in zero for the +* convenience of memory dump review. +* + LA R3,2*8(,R3) Point to next input value pair + LA R8,8(,R8) Skip to start of next FPCR result area + BCTR R2,R12 Subtract next input value lots of times +* + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Subtract using provided extended BFP inputs. This set of +* tests checks NaN propagation, operations on values that are not +* finite numbers, and other basic tests. This set generates results +* that can be validated against Figure 19-13 on page 19-16 of +* SA22-7832-10. +* +* That Figure has separate rows and colums for Normal and Tiny +* operands. Although the results are effectively the same for Normal +* and Tiny in any combination, the input data includes Normal and +* Tiny values. +* +* Two results are generated for each input: one RRE with all +* exceptions non-trappable, and a second RRE with all exceptions +* trappable. Extended BFP Subtract does not have an RXE format. +* +* The difference, FPCR, and condition code are stored for each result. +* +*********************************************************************** + SPACE 2 +XBFPNF DS 0H BFP extended non-finite values tests + LM R2,R3,0(R10) Get count and address of minuend values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LM R4,R5,0(R10) Get count and start of subtrahend values +* ..which are the same as the minuends + BASR R6,0 Set top of inner loop +* + LD FPR8,0(,R3) Get extended BFP minuend part 1 + LD FPR10,8(,R3) Get extended BFP minuend part 2 + LD FPR1,0(,R5) Get extended BFP subtrahend part 1 + LD FPR3,8(,R5) Get extended BFP subtrahend part 2 + LFPC FPCREGNT Set exceptions non-trappable + SXBR FPR8,FPR1 Subtract extended FPR1-3 from FPR8-10 RRE + STD FPR8,0(,R7) Store extended BFP difference part 1 + STD FPR10,8(,R7) Store extended BFP difference part 2 + STFPC 0(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,3(,R8) Save condition code in results table +* + LD FPR13,0(,R3) Get extended BFP minuend part 1 + LD FPR15,8(,R3) Get extended BFP minuend part 2 + LD FPR1,0(,R5) Get extended BFP subtrahend part 1 + LD FPR3,8(,R5) Get extended BFP subtrahend part 2 + LFPC FPCREGTR Set exceptions trappable + SXBR FPR13,FPR1 Subtract extended FPR1-3 from FPR13-15 RRE + STD FPR13,16(,R7) Store extended BFP difference part 1 + STD FPR15,24(,R7) Store extended BFP difference part 2 + STFPC 4(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,7(,R8) Save condition code in results table +* + LA R5,16(,R5) Point to next subtrahend value + LA R7,32(,R7) Point to next Subtract result area + LA R8,16(,R8) Point to next Subtract FPCR area + BCTR R4,R6 Loop through right-hand values +* + LA R3,16(,R3) Point to next minuend value + BCTR R2,R12 Subtract until all cases tested + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Subtract using provided extended BFP input pairs. This set +* of tests triggers IEEE exceptions Overflow, Underflow, and Inexact +* and collects results when the exceptions do not result in a trap and +* when they do. +* +* Two results are generated for each input: one RRE with all +* exceptions non-trappable and a second RRE with all exceptions +* trappable. There is no RXE format for Subtract in extended +* precision. +* +* The difference, FPCR, and condition code are stored for each result. +* +*********************************************************************** + SPACE 2 +XBFPF LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LFPC FPCREGNT Set exceptions non-trappable + LD FPR13,0(,R3) Get extended BFP minuend part 1 + LD FPR15,8(,R3) Get extended BFP minuend part 2 + LD FPR1,16(,R3) Get extended BFP subtrahend part 1 + LD FPR3,24(,R3) Get extended BFP subtrahend part 2 + SXBR FPR13,FPR1 Subtract extended FPR1-3 from FPR13-15 RRE + STD FPR13,0(,R7) Store extended BFP difference part 1 + STD FPR15,8(,R7) Store extended BFP difference part 2 + STFPC 0(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,3(,R8) Save condition code in results table +* + LFPC FPCREGTR Set exceptions trappable + LD FPR13,0(,R3) Reload extended BFP minuend part 1 + LD FPR15,8(,R3) Reload extended BFP minuend part 2 +* ..subtrahend is still in FPR1-FPR3 + SXBR FPR13,FPR1 Subtract extended FPR1-3 from FPR13-15 RRE + STD FPR13,16(,R7) Store extended BFP difference part 1 + STD FPR15,24(,R7) Store extended BFP difference part 2 + STFPC 4(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,7(,R8) Save condition code in results table +* + LA R3,32(,R3) Point to next input value pair + LA R7,32(,R7) Point to next quotent result pair + LA R8,16(,R8) Point to next FPCR result area + BCTR R2,R12 Convert next input value. +* + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Subtract using provided extended BFP input pairs. This set +* of tests exhaustively tests all rounding modes available for +* Subtract. The rounding mode can only be specified in the FPC. +* +* All five FPC rounding modes are tested because the preceeding tests, +* using rounding mode RNTE, do not often create results that require +* rounding. +* +* Two results are generated for each input and rounding mode: one RRE +* and one RXE. Traps are disabled for all rounding mode tests. +* +* The difference, FPCR, and condition code are stored for each result. +* +*********************************************************************** + SPACE 2 +XBFPRM LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + XR R1,R1 Zero register 1 for use in IC/STC/indexing + BASR R12,0 Set top of test case loop + + LA R5,FPCMCT Get count of FPC modes to be tested + BASR R9,0 Set top of rounding mode loop +* + IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 0(R1) Set FPC Rounding Mode + LD FPR13,0(,R3) Get extended BFP minuend part 1 + LD FPR15,8(,R3) Get extended BFP minuend part 2 + LD FPR1,16(,R3) Get extended BFP subtrahend part 1 + LD FPR3,24(,R3) Get extended BFP subtrahend part 2 + SXBR FPR13,FPR1 Subtract extended FPR1-3 from FPR13-15 RRE + STD FPR13,0(,R7) Store extended BFP difference part 1 + STD FPR15,8(,R7) Store extended BFP difference part 2 + STFPC 0(R8) Store resulting FPCR flags and DXC + IPM R0 Get condition code and program mask + SRL R0,28 Isolate CC in low order byte + STC R0,3(,R8) Save condition code in results table +* + LA R7,16(,R7) Point to next difference result set + LA R8,4(,R8) Point to next FPCR result area +* + BCTR R5,R9 Iterate to next FPC mode +* +* End of FPC modes to be tested. Advance to next test case. We will +* skip eight bytes of FPCR result area so that each set of five result +* FPCR contents pairs starts at a memory address ending in zero for the +* convenience of memory dump review. +* + LA R3,2*16(,R3) Point to next input value pair + LA R8,12(,R8) Skip to start of next FPCR result area + BCTR R2,R12 Subtract next input value lots of times +* + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Table of FPC rounding modes to test difference rounding modes. +* +* The Set BFP Rounding Mode does allow specification of the FPC +* rounding mode as an address, so we shall index into a table of +* BFP rounding modes without bothering with Execute. +* +*********************************************************************** + SPACE 2 +* +* Rounding modes that may be set in the FPCR. The FPCR controls +* rounding of the difference. +* +* These are indexed directly by the loop counter, which counts down. +* So the modes are listed in reverse order here. +* +FPCMODES DS 0C + DC AL1(7) RFS, Round for shorter precision + DC AL1(3) RM, Round to -infinity + DC AL1(2) RP, Round to +infinity + DC AL1(1) RZ, Round to zero + DC AL1(0) RNTE, Round to Nearest, ties to even +FPCMCT EQU *-FPCMODES Count of FPC Modes to be tested +* + EJECT +*********************************************************************** +* +* Short BFP test data sets for Subtract testing. +* +* The first test data set is used for tests of basic functionality, +* NaN propagation, and results from operations involving other than +* finite numbers. +* +* The second test data set is used for testing boundary conditions +* using two finite non-zero values. Each possible condition code +* and type of result (normal, scaled, etc) is created by members of +* this test data set. +* +* The third test data set is used for exhaustive testing of final +* results across the five rounding modes available for the Subtract +* instruction. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* First input test data set, to test operations using non-finite or +* zero inputs. Member values chosen to validate Figure 19-13 on page +* 19-16 of SA22-7832-10. Each value in this table is tested against +* every other value in the table. Ten entries means 100 result sets. +* +*********************************************************************** + SPACE 2 +SBFPNFIN DS 0F Inputs for short BFP non-finite tests + DC X'FF800000' -inf + DC X'C0000000' -2.0 + DC X'80010000' -Dnice + DC X'80000000' -0 + DC X'00000000' +0 + DC X'00010000' -Dnice + DC X'40000000' +2.0 + DC X'7F800000' +inf + DC X'FFCB0000' -QNaN + DC X'7F8A0000' +SNaN +SBFPNFCT EQU (*-SBFPNFIN)/4 Count of short BFP in list + SPACE 3 +*********************************************************************** +* +* Second input test data set. These are finite pairs intended to +* trigger overflow, underflow, and inexact exceptions. Each pair is +* added twice, once non-trappable and once trappable. Trappable +* overflow or underflow yields a scaled result. Trappable inexact +* will show whether the Incremented DXC code is returned. +* +* The following test cases are required: +* 1. Overflow +* 2. Underflow - normal inputs +* 3. Underflow - subnormal inputs +* 4. Normal - from subnormal inputs +* 5. Inexact - incremented +* 6. Inexact - truncated +* +*********************************************************************** + SPACE 2 +SBFPIN DS 0F Inputs for short BFP finite tests +* +* Overflow on subtraction +* + DC X'7F7FFFFF' +Nmax + DC X'FF7FFFFF' -Nmax +* +* Underflow from difference of normals. We will subtract a small +* normal from a slightly larger small normal to generate a subnormal. +* + DC X'00FFFFFF' Very small normal number + DC X'00800000' Smaller normal +* +* Underflow from difference of subnormals. +* + DC X'00040000' Subnormal, < +Dmax + DC X'00000F0F' Smaller subnormal +* +* Normal result from difference of subnormals. +* The result will be greater than +Nmin +* + DC X'007FFFFF' +Dmax + DC X'80000001' -Dmin, result will be +Nmin +* +* Subtract a value from 1.0 such that the added digits are to the right +* of the right-most bit in the stored significand. The result will be +* inexact, and incremented will be determined by the value of the +* bits in the subtrahend. +* + DC X'3F800000' Minuend +1, aka 1.0b0 + DC X'32800000' Subtrahend 1.b-26 +*..Above subtrahend is 1.490116119384765625E-8 +*..nearest is away from zero, incremented. +* + DC X'3F800000' Minuend +1, aka 1.0b0 + DC X'33100000' Subtrahend 1.001b-25 +*..Above subtrahend is 3.35276126861572265625E-8 +*..nearest is toward zero, truncated +* +SBFPCT EQU (*-SBFPIN)/4/2 Count of short BFP in list + SPACE 3 +*********************************************************************** +* +* Third input test data set. These are finite pairs intended to +* test all combinations of rounding mode for the difference and the +* remainder. Values are chosen to create a requirement to round +* to the target precision after the computation and to generate +* varying results depending on the rounding mode in the FPCR. +* +* The result set will have cases that represent each of the following +* +* 1. Positive, nearest magnitude is toward zero. +* 2. Negative, nearest magnitude is toward zero. +* 3. Positive, nearest magnitude is away from zero. +* 4. Negative, nearest magnitude is away from zero. +* 5. Positive, tie, nearest even has greater magnitude +* 6. Negative, tie, nearest even has greater magnitude +* 7. Positive, tie, nearest even has lower magnitude +* 8. Negative, tie, nearest even has lower magnitude +* +* Round For Shorter precision correctness can be determined from the +* above test cases. +* +*********************************************************************** + SPACE 2 +SBFPINRM DS 0F Inputs for short BFP rounding testing +* +* Subtract a value from 1.0 such that the added digits are to the right +* of the right-most bit in the stored significand. The result will be +* inexact, and incremented will be determined by the value of the +* bits in the subtrahend. +* + DC X'3F800000' Minuend +1, aka 1.0b0 + DC X'33100000' Subtrahend 1.001b-25 + DC X'BF800000' Minuend -1, aka -1.0b0 + DC X'B3100000' Subtrahend 1.001b-25 +*..Above subtrahend is 3.35276126861572265625E-8 +*..nearest is toward zero, truncated +* + DC X'3F800000' Minuend +1, aka +1.0b0 + DC X'32800000' Subtrahend 1.b-26 + DC X'BF800000' Minuend -1, aka -1.0b0 + DC X'B2800000' Subtrahend -1.b-26 +*..Above subtrahend is 1.490116119384765625E-8 +*..nearest is away from zero, incremented. +* + DC X'3F800000' Minuend +1, aka +1.0b0 + DC X'33C00000' Subtrahend +1.1b-24 + DC X'BF800000' Minuend -1, aka -1.0b0 + DC X'B3C00000' Subtrahend -1.1b-24 +*..Above subtrahend is 8.94069671630859375E-8 +*..nearest is a tie, nearest even has lower magnitude +* + DC X'3F800000' Minuend +1, aka +1.0b0 + DC X'33000000' Subtrahend +1.0b-25 + DC X'BF800000' Minuend -1, aka -1.0b0 + DC X'B3000000' Subtrahend -1.0b-25 +*..Above subtrahend is 2.98023223876953125E-8 +*..nearest is a tie, nearest even has greater magnitude +* +SBFPRMCT EQU (*-SBFPINRM)/4/2 Count of short BFP rounding tests + EJECT +*********************************************************************** +* +* Long BFP test data sets for Add testing. +* +* The first test data set is used for tests of basic functionality, +* NaN propagation, and results from operations involving other than +* finite numbers. +* +* The second test data set is used for testing boundary conditions +* using two finite non-zero values. Each possible condition code +* and type of result (normal, scaled, etc) is created by members of +* this test data set. +* +* The third test data set is used for exhaustive testing of final +* results across the five rounding modes available for the Add +* instruction. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* First input test data set, to test operations using non-finite or +* zero inputs. Member values chosen to validate Figure 19-13 on page +* 19-16 of SA22-7832-10. Each value in this table is tested against +* every other value in the table. Ten entries means 100 result sets. +* +*********************************************************************** + SPACE 2 +LBFPNFIN DS 0F Inputs for long BFP testing + DC X'FFF0000000000000' -inf + DC X'C000000000000000' -2.0 + DC X'8001000000000000' -Dnice + DC X'8000000000000000' -0 + DC X'0000000000000000' +0 + DC X'0001000000000000' +Dnice + DC X'4000000000000000' +2.0 + DC X'7FF0000000000000' +inf + DC X'FFF8B00000000000' -QNaN + DC X'7FF0A00000000000' +SNaN +LBFPNFCT EQU (*-LBFPNFIN)/8 Count of long BFP in list + SPACE 3 +*********************************************************************** +* +* Second input test data set. These are finite pairs intended to +* trigger overflow, underflow, and inexact exceptions. Each pair is +* added twice, once non-trappable and once trappable. Trappable +* overflow or underflow yields a scaled result. Trappable inexact +* will show whether the Incremented DXC code is returned. +* +* The following test cases are required: +* 1. Overflow +* 2. Underflow - normal inputs +* 3. Underflow - subnormal inputs +* 4. Normal - from subnormal inputs +* 5. Inexact - incremented +* 6. Inexact - truncated +* +*********************************************************************** + SPACE 2 +LBFPIN DS 0D Inputs for long BFP finite tests +* +* Overflow on subtraction +* + DC X'7FFFFFFFFFFFFFFF' +Nmax + DC X'FFFFFFFFFFFFFFFF' +Nmax +* +* Underflow from difference of normals. We wil subtract a small +* normal from a slightly larger normal to generate a subnormal. +* + DC X'001FFFFFFFFFFFFF' Very small normal number + DC X'0010000000000000' Smaller normal negative +* +* Underflow from difference of subnormals. +* + DC X'0008000000000000' Subnormal, < +Dmax + DC X'0000F0F000000000' Smaller subnormal +* +* Normal result from difference of subnormals. +* The result will be greater than +Nmin +* + DC X'000FFFFFFFFFFFFF' +Dmax + DC X'8000000000000001' +Dmin, result will be +Nmin +* +* Subtract a value from 1.0 such that the added digits are to the right +* of the right-most bit in the stored significand. The result will be +* inexact, and incremented will be determined by the value of the +* bits in the subtrahend. +* + DC X'3FF0000000000000' Minuend +1, aka 1.0b0 + DC X'3C80000000000000' Subtrahend 1.0b-55 +*..Above subtrahend is 2.77555756156289135105907917022705078125E-17 +*..nearest is away from zero, incremented. +* + DC X'3FF0000000000000' Minuend +1, aka 1.0b0 + DC X'3C92000000000000' Subtrahend +1.001b-54 +*..Above subtrahend is 6.2450045135165055398829281330108642578125E-17 +*..nearest is toward zero, truncated. +* +LBFPCT EQU (*-LBFPIN)/8/2 Count of long BFP in list + SPACE 3 +*********************************************************************** +* +* Third input test data set. These are finite pairs intended to +* test all combinations of rounding mode for the difference and the +* remainder. Values are chosen to create a requirement to round +* to the target precision after the computation and to generate +* varying results depending on the rounding mode in the FPCR. +* +* The result set will have cases that represent each of the following +* +* 1. Positive, nearest magnitude is toward zero. +* 2. Negative, nearest magnitude is toward zero. +* 3. Positive, nearest magnitude is away from zero. +* 4. Negative, nearest magnitude is away from zero. +* 5. Positive, tie, nearest even has greater magnitude +* 6. Negative, tie, nearest even has greater magnitude +* 7. Positive, tie, nearest even has lower magnitude +* 8. Negative, tie, nearest even has lower magnitude +* +* Round For Shorter precision correctness can be determined from the +* above test cases. +* +*********************************************************************** + SPACE 2 +LBFPINRM DS 0F +* +* Subtract a value from 1.0 such that the added digits are to the right +* of the right-most bit in the stored significand. The result will be +* inexact, and incremented will be determined by the value of the +* bits in the subtrahend. +* + DC X'3FF0000000000000' Minuend +1, aka +1.0b0 + DC X'3C92000000000000' Subtrahend +1.001b-54 + DC X'BFF0000000000000' Minuend -1, aka -1.0b0 + DC X'BC92000000000000' Subtrahend +1.001b-54 +*..Above subtrahend is 6.2450045135165055398829281330108642578125E-17 +*.. ...30859375E-16,nearest is toward zero, truncated. +* + DC X'3FF0000000000000' Minuend +1, aka +1.0b0 + DC X'3C80000000000000' Subtrahend 1.0b-55 + DC X'BFF0000000000000' Minuend -1, aka -1.0b0 + DC X'BC80000000000000' Subtrahend 1.0b-55 +*..Above subtrahend is 2.77555756156289135105907917022705078125E-17 +*..nearest is away from zero, incremented. +* + DC X'3FF0000000000000' Minuend +1, aka +1.0b0 + DC X'3CA8000000000000' Subtrahend +1.1b-53 + DC X'BFF0000000000000' Minuend -1, aka -1.0b0 + DC X'BCA8000000000000' Subtrahend -1.1b-53 +*..Above subtrahend is 1.66533453693773481063544750213623046875E-16 +*..nearest is a tie, nearest even has lower magnitude +* + DC X'3FF0000000000000' Minuend +1, aka +1.0b0 + DC X'3C90000000000000' Subtrahend +1.0b-54 + DC X'BFF0000000000000' Minuend -1, aka -1.0b0 + DC X'BC90000000000000' Subtrahend -1.0b-54 +*..Above subtrahend is 5.5511151231257827021181583404541015625E-17 +*..nearest is a tie, nearest even has greater magnitude +* +LBFPRMCT EQU (*-LBFPINRM)/8/2 Count of long BFP rounding tests + EJECT +*********************************************************************** +* +* Extended BFP test data sets for Add testing. +* +* The first test data set is used for tests of basic functionality, +* NaN propagation, and results from operations involving other than +* finite numbers. +* +* The second test data set is used for testing boundary conditions +* using two finite non-zero values. Each possible condition code +* and type of result (normal, scaled, etc) is created by members of +* this test data set. +* +* The third test data set is used for exhaustive testing of final +* results across the five rounding modes available for the Add +* instruction. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* First input test data set, to test operations using non-finite or +* zero inputs. Member values chosen to validate Figure 19-13 on page +* 19-16 of SA22-7832-10. Each value in this table is tested against +* every other value in the table. Ten entries means 100 result sets. +* +*********************************************************************** + SPACE 2 +XBFPNFIN DS 0F Inputs for extended BFP testing + DC X'FFFF0000000000000000000000000000' -inf + DC X'C0000000000000000000000000000000' -2.0 + DC X'80001000000000000000000000000000' -Dnice + DC X'80000000000000000000000000000000' -0 + DC X'00000000000000000000000000000000' +0 + DC X'00001000000000000000000000000000' +Dnice + DC X'40000000000000000000000000000000' +2.0 + DC X'7FFF0000000000000000000000000000' +inf + DC X'FFFF8B00000000000000000000000000' -QNaN + DC X'7FFF0A00000000000000000000000000' +SNaN +XBFPNFCT EQU (*-XBFPNFIN)/16 Count of extended BFP in list + SPACE 3 +*********************************************************************** +* +* Second input test data set. These are finite pairs intended to +* trigger overflow, underflow, and inexact exceptions. Each pair is +* added twice, once non-trappable and once trappable. Trappable +* overflow or underflow yields a scaled result. Trappable inexact +* will show whether the Incremented DXC code is returned. +* +* The following test cases are required: +* The following test cases are required: +* 1. Overflow +* 2. Underflow - normal inputs +* 3. Underflow - subnormal inputs +* 4. Normal - from subnormal inputs +* 5. Inexact - incremented +* 6. Inexact - truncated +* +*********************************************************************** + SPACE 2 +XBFPIN DS 0F Inputs for extended BFP finite tests +* +* Overflow on subtraction +* + DC X'7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF' +Nmax + DC X'FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF' +Nmax +* +* Underflow from difference of normals. We will subtract a small +* normal from a slightly larger normal to generate a subnormal. +* + DC X'0001FFFFFFFFFFFFFFFFFFFFFFFFFFFF' Very small normal + DC X'00010000000000000000000000000000' Smaller normal +* +* Underflow from difference of subnormals. +* + DC X'00008000000000000000000000000000' Subnormal, < +Dmax + DC X'00000F0F000000000000000000000000' Smaller subnormal +* +* Normal result from difference of subnormals. +* The result will be greater than +Nmin +* + DC X'0000FFFFFFFFFFFFFFFFFFFFFFFFFFFF' +Dmax + DC X'80000000000000000000000000000001' -Dmin +* ...result will be +Nmin +* +* Subtract a value from 1.0 such that the added digits are to the right +* of the right-most bit in the stored significand. The result will be +* inexact, and incremented will be determined by the value of the +* bits in the subtrahend. +* + DC X'3FFF0000000000000000000000000000' +1, aka 1.0b0 + DC X'3F8C0000000000000000000000000000' 1.0b-115 +*..Above subtrahend is 2.407412430484044816319972428231159148172627... +* ...06026923524404992349445819854736328125E-35 +*..nearest is away from zero, incremented. +* + DC X'3FFF0000000000000000000000000000' +1, aka 1.0b0 + DC X'3F8D2000000000000000000000000000' 1.001b-114 +*..Above subtrahend is 5.416677968589100836719937963520108083388410... +* ...8856057792991123278625309467315673828125E-35 +*..nearest is toward zero, truncated +* +XBFPCT EQU (*-XBFPIN)/16/2 Count of extended BFP in list + SPACE 3 +*********************************************************************** +* +* Third input test data set. These are finite pairs intended to +* test all combinations of rounding mode for the difference and the +* remainder. Values are chosen to create a requirement to round +* to the target precision after the computation and to generate +* varying results depending on the rounding mode in the FPCR. +* +* The result set will have cases that represent each of the following +* +* 1. Positive, nearest magnitude is toward zero. +* 2. Negative, nearest magnitude is toward zero. +* 3. Positive, nearest magnitude is away from zero. +* 4. Negative, nearest magnitude is away from zero. +* 5. Positive, tie, nearest even has greater magnitude +* 6. Negative, tie, nearest even has greater magnitude +* 7. Positive, tie, nearest even has lower magnitude +* 8. Negative, tie, nearest even has lower magnitude +* +* Round For Shorter precision correctness can be determined from the +* above test cases. +* +*********************************************************************** + SPACE 2 +XBFPINRM DS 0D +* +* Subtract a value from 1.0 such that the added digits are to the right +* of the right-most bit in the stored significand. The result will be +* inexact, and incremented will be determined by the value of the +* bits in the subtrahend. +* + DC X'3FFF0000000000000000000000000000' +1, aka +1.0b0 + DC X'3F8D2000000000000000000000000000' 1.001b-114 + DC X'BFFF0000000000000000000000000000' -1, aka -1.0b0 + DC X'BF8D2000000000000000000000000000' 1.001b-114 +*..Above subtrahend is 5.416677968589100836719937963520108083388410... +* ...8856057792991123278625309467315673828125E-35 +*..nearest is toward zero +* + DC X'3FFF0000000000000000000000000000' +1, aka +1.0b0 + DC X'3F8C0000000000000000000000000000' 1.0b-115 + DC X'BFFF0000000000000000000000000000' -1, aka -1.0b0 + DC X'BF8C0000000000000000000000000000' 1.0b-115 +*..Above subtrahend is 2.407412430484044816319972428231159148172627... +* ...06026923524404992349445819854736328125E-35 +*..nearest is away from zero +* + DC X'3FFF0000000000000000000000000000' +1, aka +1.0b0 + DC X'3F8E8000000000000000000000000000' +1.1b-113 + DC X'BFFF0000000000000000000000000000' -1, aka -1.0b0 + DC X'BF8E8000000000000000000000000000' -1.0b-114 +*..Above subtrahend is 1.444447458290426889791983456938695488903576... +* ...23616154114642995409667491912841796875E-34 +*..nearest is a tie, nearest even has lower magnitude +* + DC X'3FFF0000000000000000000000000000' +1, aka +1.0b0 + DC X'3F8D0000000000000000000000000000' +1.0b-114 + DC X'BFFF0000000000000000000000000000' -1, aka -1.0b0 + DC X'BF8D0000000000000000000000000000' -1.0b-114 +*..Above subtrahend is 4.814824860968089632639944856462318296345254... +* ...1205384704880998469889163970947265625E-35 +*..nearest is a tie, nearest even has greater magnitude +* +XBFPRMCT EQU (*-XBFPINRM)/16/2 Count of long BFP rounding tests + EJECT +* +* Locations for results +* +SBFPNFOT EQU STRTLABL+X'1000' Short non-finite BFP results +* ..room for 110 tests, 100 used +SBFPNFFL EQU STRTLABL+X'1700' FPCR flags and DXC from short BFP +* ..room for 110 tests, 100 used +* +SBFPOUT EQU STRTLABL+X'1E00' Short BFP finite results +* ..room for 16 tests, 6 used +SBFPFLGS EQU STRTLABL+X'1F00' FPCR flags and DXC from short BFP +* ..room for 16 tests, 6 used +* +SBFPRMO EQU STRTLABL+X'2000' Short BFP rounding mode test results +* ..Room for 16, 8 used. +SBFPRMOF EQU STRTLABL+X'2300' Short BFP rounding mode FPCR results +* ..Room for 16, 8 used. +* ..next location starts at X'2500' +* +LBFPNFOT EQU STRTLABL+X'4000' Long non-finite BFP results +* ..room for 100 tests, 100 used +LBFPNFFL EQU STRTLABL+X'4D00' FPCR flags and DXC from long BFP +* ..room for 100 tests, 100 used +* +LBFPOUT EQU STRTLABL+X'5400' Long BFP finite results +* ..room for 16 tests, 6 used +LBFPFLGS EQU STRTLABL+X'5600' FPCR flags and DXC from long BFP +* ..room for 16 tests, 6 used +* +LBFPRMO EQU STRTLABL+X'5700' Long BFP rounding mode test results +* ..Room for 16, 8 used. +LBFPRMOF EQU STRTLABL+X'5C00' Long BFP rounding mode FPCR results +* ..Room for 16, 8 used. +* ..next location starts at X'5E00' +* +XBFPNFOT EQU STRTLABL+X'8000' Extended non-finite BFP results +* ..room for 100 tests, 100 used +XBFPNFFL EQU STRTLABL+X'8D00' FPCR flags and DXC from ext'd BFP +* ..room for 100 tests, 100 used +* +XBFPOUT EQU STRTLABL+X'9400' Extended BFP finite results +* ..room for 16 tests, 6 used +XBFPFLGS EQU STRTLABL+X'9600' FPCR flags and DXC from ext'd BFP +* ..room for 16 tests, 6 used +* +XBFPRMO EQU STRTLABL+X'9700' Ext'd BFP rounding mode test results +* ..Room for 16, 8 used. +XBFPRMOF EQU STRTLABL+X'9C00' Ext'd BFP rounding mode FPCR results +* ..Room for 16, 8 used. +* ..next location starts at X'9E00' +* +ENDLABL EQU STRTLABL+X'9E00' + PADCSECT ENDLABL + END diff --git a/tests/bfp-018-subtract.core b/tests/bfp-018-subtract.core new file mode 100644 index 000000000..bb5f964d8 Binary files /dev/null and b/tests/bfp-018-subtract.core differ diff --git a/tests/bfp-018-subtract.list b/tests/bfp-018-subtract.list new file mode 100644 index 000000000..85d1b31b0 --- /dev/null +++ b/tests/bfp-018-subtract.list @@ -0,0 +1,1780 @@ +ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 1 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 2 *********************************************************************** + 3 * + 4 *Testcase IEEE SUBTRACT + 5 * Test case capability includes IEEE exceptions trappable and + 6 * otherwise. Test results, FPCR flags, the Condition code, and any + 7 * DXC are saved for all tests. + 8 * + 9 *********************************************************************** + + + 11 *********************************************************************** + 12 * + 13 * Tests the following three conversion instructions + 14 * SUBTRACT (short BFP, RRE) + 15 * SUBTRACT (long BFP, RRE) + 16 * SUBTRACT (extended BFP, RRE) + 17 * SUBTRACT (short BFP, RXE) + 18 * SUBTRACT (long BFP, RXE) + 19 * + 20 * Test data is compiled into this program. The test script that runs + 21 * this program can provide alternative test data through Hercules R + 22 * commands. + 23 * + 24 * Test Case Order + 25 * 1) Short BFP basic tests, including traps and NaN propagation + 26 * 2) Short BFP finite number tests, incl. traps and scaling + 27 * 3) Short BFP FPC-controlled rounding mode exhaustive tests + 28 * 4) Long BFP basic tests, including traps and NaN propagation + 29 * 5) Long BFP finite number tests, incl. traps and scaling + 30 * 6) Long BFP FPC-controlled rounding mode exhaustive tests + 31 * 7) Extended BFP basic tests, including traps and NaN propagation + 32 * 8) Extended BFP finite number tests, incl. traps and scaling + 33 * 9) Extended BFP FPC-controlled rounding mode exhaustive tests + 34 * + 35 * Three input test sets are provided each for short, long, and + 36 * extended BFP inputs. Test values are the same for each precision + 37 * for most tests. Overflow and underflow each require precision- + 38 * dependent test values. + 39 * + 40 * Also tests the following floating point support instructions + 41 * LOAD (Short) + 42 * LOAD (Long) + 43 * LFPC (Load Floating Point Control Register) + 44 * SRNMB (Set BFP Rounding Mode 3-bit) + 45 * STORE (Short) + 46 * STORE (Long) + 47 * STFPC (Store Floating Point Control Register) + 48 * + 49 *********************************************************************** + + + 51 MACRO + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 2 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 52 PADCSECT &ENDLABL + 53 .* + 54 .* Macro to pad the CSECT to include result data areas if this test + 55 .* program is not being assembled using asma. asma generates a core + 56 .* image that is loaded by the loadcore command, and because the + 57 .* core image is a binary stored in Github, it makes sense to make + 58 .* this small effort to keep the core image small. + 59 .* + 60 AIF (D'&ENDLABL).GOODPAD + 61 MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + 62 MNOTE *,'No CSECT padding performed' + 63 MEXIT + 64 .* + 65 .GOODPAD ANOP Label valid. See if we're on asma + 66 AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + 67 ORG &ENDLABL-1 Not ASMA. Pad CSECT + 68 MEXIT + 69 .* + 70 .NOPAD ANOP + 71 MNOTE *,'asma detected; no CSECT padding performed' + 72 MEND + 73 * + 74 * Note: for compatibility with the z/CMS test rig, do not change + 75 * or use R11, R14, or R15. Everything else is fair game. + 76 * + 0000000000000000 0000000000000CDF 77 BFPSUBTR START 0 + 0000000000000000 0000000000000001 78 STRTLABL EQU * + 0000000000000000 0000000000000001 79 R0 EQU 0 Work register for cc extraction + 0000000000000001 0000000000000001 80 R1 EQU 1 + 0000000000000002 0000000000000001 81 R2 EQU 2 Holds count of test input values + 0000000000000003 0000000000000001 82 R3 EQU 3 Points to next test input value(s) + 0000000000000004 0000000000000001 83 R4 EQU 4 Rounding tests inner loop control + 0000000000000005 0000000000000001 84 R5 EQU 5 Rounding tests outer loop control + 0000000000000006 0000000000000001 85 R6 EQU 6 Rounding tests top of inner loop + 0000000000000007 0000000000000001 86 R7 EQU 7 Pointer to next result value(s) + 0000000000000008 0000000000000001 87 R8 EQU 8 Pointer to next FPCR result + 0000000000000009 0000000000000001 88 R9 EQU 9 Rounding tests top of outer loop + 000000000000000A 0000000000000001 89 R10 EQU 10 Pointer to test address list + 000000000000000B 0000000000000001 90 R11 EQU 11 **Reserved for z/CMS test rig + 000000000000000C 0000000000000001 91 R12 EQU 12 Holds number of test cases in set + 000000000000000D 0000000000000001 92 R13 EQU 13 Mainline return address + 000000000000000E 0000000000000001 93 R14 EQU 14 **Return address for z/CMS test rig + 000000000000000F 0000000000000001 94 R15 EQU 15 **Base register on z/CMS or Hyperion + 95 * + 96 * Floating Point Register equates to keep the cross reference clean + 97 * + 0000000000000000 0000000000000001 98 FPR0 EQU 0 + 0000000000000001 0000000000000001 99 FPR1 EQU 1 + 0000000000000002 0000000000000001 100 FPR2 EQU 2 + 0000000000000003 0000000000000001 101 FPR3 EQU 3 + 0000000000000004 0000000000000001 102 FPR4 EQU 4 + 0000000000000005 0000000000000001 103 FPR5 EQU 5 + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 3 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 0000000000000006 0000000000000001 104 FPR6 EQU 6 + 0000000000000007 0000000000000001 105 FPR7 EQU 7 + 0000000000000008 0000000000000001 106 FPR8 EQU 8 + 0000000000000009 0000000000000001 107 FPR9 EQU 9 + 000000000000000A 0000000000000001 108 FPR10 EQU 10 + 000000000000000B 0000000000000001 109 FPR11 EQU 11 + 000000000000000C 0000000000000001 110 FPR12 EQU 12 + 000000000000000D 0000000000000001 111 FPR13 EQU 13 + 000000000000000E 0000000000000001 112 FPR14 EQU 14 + 000000000000000F 0000000000000001 113 FPR15 EQU 15 + 114 * +0000000000000000 0000000000000000 115 USING *,R15 + 116 * + 117 * Above works on real iron (R15=0 after sysclear) + 118 * and in z/CMS (R15 points to start of load module) + 119 * + + + 121 *********************************************************************** + 122 * + 123 * Low core definitions, Restart PSW, and Program Check Routine. + 124 * + 125 *********************************************************************** + + +0000000000000000 0000000000000000 000000000000008E 127 ORG STRTLABL+X'8E' Program check interrution code +000000000000008E 0000 128 PCINTCD DS H + 129 * + 0000000000000150 0000000000000001 130 PCOLDPSW EQU STRTLABL+X'150' z/Arch Program check old PSW + 131 * +0000000000000090 0000000000000090 00000000000001A0 132 ORG STRTLABL+X'1A0' z/Arch Restart PSW +00000000000001A0 00000001 80000000 133 DC X'0000000180000000',AD(START) + 134 * +00000000000001B0 00000000000001B0 00000000000001D0 135 ORG STRTLABL+X'1D0' z/Arch Program check old PSW +00000000000001D0 00000000 00000000 136 DC X'0000000000000000',AD(PROGCHK) + 137 * + 138 * Program check routine. If Data Exception, continue execution at + 139 * the instruction following the program check. Otherwise, hard wait. + 140 * No need to collect data. All interesting DXC stuff is captured + 141 * in the FPCR. + 142 * +00000000000001E0 00000000000001E0 0000000000000200 143 ORG STRTLABL+X'200' +0000000000000200 144 PROGCHK DS 0H Program check occured... +0000000000000200 9507 F08F 000000000000008F 145 CLI PCINTCD+1,X'07' Data Exception? +0000000000000204 A774 0004 000000000000020C 146 JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) +0000000000000208 B2B2 F150 0000000000000150 147 LPSWE PCOLDPSW ..yes, resume program execution +000000000000020C 148 PCNOTDTA DS 0H +000000000000020C 12EE 149 LTR R14,R14 Return address provided? +000000000000020E 077E 150 BNZR R14 Yes, return to z/CMS test rig. +0000000000000210 B2B2 F280 0000000000000280 151 LPSWE HARDWAIT Not data exception, enter disabled wait + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 4 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 153 *********************************************************************** + 154 * + 155 * Main program. Enable Advanced Floating Point, process test cases. + 156 * + 157 *********************************************************************** + + +0000000000000214 159 START DS 0H +0000000000000214 B600 F290 0000000000000290 160 STCTL R0,R0,CTLR0 Store CR0 to enable AFP +0000000000000218 9604 F291 0000000000000291 161 OI CTLR0+1,X'04' Turn on AFP bit +000000000000021C B700 F290 0000000000000290 162 LCTL R0,R0,CTLR0 Reload updated CR0 + 163 * +0000000000000220 41A0 F300 0000000000000300 164 LA R10,SHORTNF Point to short BFP non-finite inputs +0000000000000224 4DD0 F390 0000000000000390 165 BAS R13,SBFPNF Subtract short BFP non-finites +0000000000000228 41A0 F310 0000000000000310 166 LA R10,SHORTF Point to short BFP finite inputs +000000000000022C 4DD0 F44A 000000000000044A 167 BAS R13,SBFPF Subtract short BFP finites +0000000000000230 41A0 F320 0000000000000320 168 LA R10,RMSHORTS Point to short BFP rounding mode tests +0000000000000234 4DD0 F4F0 00000000000004F0 169 BAS R13,SBFPRM Subtract short BFP for rounding tests + 170 * +0000000000000238 41A0 F330 0000000000000330 171 LA R10,LONGNF Point to long BFP non-finite inputs +000000000000023C 4DD0 F572 0000000000000572 172 BAS R13,LBFPNF Subtract long BFP non-finites +0000000000000240 41A0 F340 0000000000000340 173 LA R10,LONGF Point to long BFP finite inputs +0000000000000244 4DD0 F628 0000000000000628 174 BAS R13,LBFPF Subtract long BFP finites +0000000000000248 41A0 F350 0000000000000350 175 LA R10,RMLONGS Point to long BFP rounding mode tests +000000000000024C 4DD0 F6CE 00000000000006CE 176 BAS R13,LBFPRM Subtract long BFP for rounding tests + 177 * +0000000000000250 41A0 F360 0000000000000360 178 LA R10,XTNDNF Point to extended BFP non-finite inputs +0000000000000254 4DD0 F74C 000000000000074C 179 BAS R13,XBFPNF Subtract extended BFP non-finites +0000000000000258 41A0 F370 0000000000000370 180 LA R10,XTNDF Point to ext'd BFP finite inputs +000000000000025C 4DD0 F7D6 00000000000007D6 181 BAS R13,XBFPF Subtract ext'd BFP finites +0000000000000260 41A0 F380 0000000000000380 182 LA R10,RMXTNDS Point to ext'd BFP rounding mode tests +0000000000000264 4DD0 F84C 000000000000084C 183 BAS R13,XBFPRM Subtract ext'd BFP for rounding tests + 184 * +0000000000000268 12EE 185 LTR R14,R14 Return address provided? +000000000000026A 077E 186 BNZR R14 ..Yes, return to z/CMS test rig. +000000000000026C B2B2 F270 0000000000000270 187 LPSWE WAITPSW All done + 188 * +0000000000000270 189 DS 0D Ensure correct alignment for psw +0000000000000270 00020000 00000000 190 WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +0000000000000280 00020000 00000000 191 HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end + 192 * +0000000000000290 00000000 193 CTLR0 DS F +0000000000000294 00000000 194 FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +0000000000000298 F8000000 195 FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags + 196 * + 197 * Input values parameter list, four fullwords for each test data set + 198 * 1) Count, + 199 * 2) Address of inputs, + 200 * 3) Address to place results, and + 201 * 4) Address to place DXC/Flags/cc values. + 202 * +000000000000029C 000000000000029C 0000000000000300 203 ORG STRTLABL+X'300' Enable run-time replacement + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 5 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000300 204 SHORTNF DS 0F Input pairs for short BFP non-finite tests +0000000000000300 0000000A 205 DC A(SBFPNFCT) +0000000000000304 000008B8 206 DC A(SBFPNFIN) +0000000000000308 00001000 207 DC A(SBFPNFOT) +000000000000030C 00001700 208 DC A(SBFPNFFL) + 209 * +0000000000000310 210 SHORTF DS 0F Input pairs for short BFP finite tests +0000000000000310 00000006 211 DC A(SBFPCT) +0000000000000314 000008E0 212 DC A(SBFPIN) +0000000000000318 00001E00 213 DC A(SBFPOUT) +000000000000031C 00001F00 214 DC A(SBFPFLGS) + 215 * +0000000000000320 216 RMSHORTS DS 0F Input pairs for short BFP rounding testing +0000000000000320 00000008 217 DC A(SBFPRMCT) +0000000000000324 00000910 218 DC A(SBFPINRM) +0000000000000328 00002000 219 DC A(SBFPRMO) +000000000000032C 00002300 220 DC A(SBFPRMOF) + 221 * +0000000000000330 222 LONGNF DS 0F Input pairs for long BFP non-finite testing +0000000000000330 0000000A 223 DC A(LBFPNFCT) +0000000000000334 00000950 224 DC A(LBFPNFIN) +0000000000000338 00004000 225 DC A(LBFPNFOT) +000000000000033C 00004D00 226 DC A(LBFPNFFL) + 227 * +0000000000000340 228 LONGF DS 0F Input pairs for long BFP finite testing +0000000000000340 00000006 229 DC A(LBFPCT) +0000000000000344 000009A0 230 DC A(LBFPIN) +0000000000000348 00005400 231 DC A(LBFPOUT) +000000000000034C 00005600 232 DC A(LBFPFLGS) + 233 * +0000000000000350 234 RMLONGS DS 0F Input pairs for long BFP rounding testing +0000000000000350 00000008 235 DC A(LBFPRMCT) +0000000000000354 00000A00 236 DC A(LBFPINRM) +0000000000000358 00005700 237 DC A(LBFPRMO) +000000000000035C 00005C00 238 DC A(LBFPRMOF) + 239 * +0000000000000360 240 XTNDNF DS 0F Inputs for ext'd BFP non-finite testing +0000000000000360 0000000A 241 DC A(XBFPNFCT) +0000000000000364 00000A80 242 DC A(XBFPNFIN) +0000000000000368 00008000 243 DC A(XBFPNFOT) +000000000000036C 00008D00 244 DC A(XBFPNFFL) + 245 * +0000000000000370 246 XTNDF DS 0F Inputs for ext'd BFP finite testing +0000000000000370 00000006 247 DC A(XBFPCT) +0000000000000374 00000B20 248 DC A(XBFPIN) +0000000000000378 00009400 249 DC A(XBFPOUT) +000000000000037C 00009600 250 DC A(XBFPFLGS) + 251 * +0000000000000380 252 RMXTNDS DS 0F Inputs for ext'd BFP non-finite testing +0000000000000380 00000008 253 DC A(XBFPRMCT) +0000000000000384 00000BE0 254 DC A(XBFPINRM) +0000000000000388 00009700 255 DC A(XBFPRMO) + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 6 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +000000000000038C 00009C00 256 DC A(XBFPRMOF) + 257 * + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 7 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 259 *********************************************************************** + 260 * + 261 * Perform Subtract using provided short BFP inputs. This set of tests + 262 * checks NaN propagation, operations on values that are not finite + 263 * numbers, and other basic tests. This set generates results that can + 264 * be validated against Figure 19-13 on page 19-16 of SA22-7832-10. + 265 * + 266 * That Figure has separate rows and colums for Normal and Tiny + 267 * operands. Although the results are effectively the same for Normal + 268 * and Tiny in any combination, the input data includes Normal and + 269 * Tiny values. + 270 * + 271 * Four results are generated for each input: one RRE with all + 272 * exceptions non-trappable, a second RRE with all exceptions trappable, + 273 * a third RXE with all exceptions non-trappable, a fourth RXE with all + 274 * exceptions trappable, + 275 * + 276 * The difference, FPCR, and condition code are stored for each result. + 277 * + 278 *********************************************************************** + + +0000000000000390 280 SBFPNF DS 0H BFP Short non-finite values tests +0000000000000390 9823 A000 0000000000000000 281 LM R2,R3,0(R10) Get count and address of minuend values +0000000000000394 9878 A008 0000000000000008 282 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000398 1222 283 LTR R2,R2 Any test cases? +000000000000039A 078D 284 BZR R13 ..No, return to caller +000000000000039C 0DC0 285 BASR R12,0 Set top of loop + 286 * +000000000000039E 9845 A000 0000000000000000 287 LM R4,R5,0(R10) Get count and start of subtrahend values + 288 * ..which are the same as the minuends +00000000000003A2 0D60 289 BASR R6,0 Set top of inner loop + 290 * +00000000000003A4 7880 3000 0000000000000000 291 LE FPR8,0(,R3) Get short BFP minuend +00000000000003A8 7810 5000 0000000000000000 292 LE FPR1,0(,R5) Get short BFP subtrahend +00000000000003AC B29D F294 0000000000000294 293 LFPC FPCREGNT Set exceptions non-trappable +00000000000003B0 B30B 0081 294 SEBR FPR8,FPR1 Subtract short FPR1 from FPR8 RRE +00000000000003B4 7080 7000 0000000000000000 295 STE FPR8,0(,R7) Store short BFP difference +00000000000003B8 B29C 8000 0000000000000000 296 STFPC 0(R8) Store resulting FPCR flags and DXC +00000000000003BC B222 0000 297 IPM R0 Get condition code and program mask +00000000000003C0 8800 001C 000000000000001C 298 SRL R0,28 Isolate CC in low order byte +00000000000003C4 4200 8003 0000000000000003 299 STC R0,3(,R8) Save condition code in results table + 300 * +00000000000003C8 7880 3000 0000000000000000 301 LE FPR8,0(,R3) Get short BFP minuend +00000000000003CC 7810 5000 0000000000000000 302 LE FPR1,0(,R5) Get short BFP subtrahend +00000000000003D0 B29D F298 0000000000000298 303 LFPC FPCREGTR Set exceptions trappable +00000000000003D4 B30B 0081 304 SEBR FPR8,FPR1 Subtract short FPR1 from FPR8 RRE +00000000000003D8 7080 7004 0000000000000004 305 STE FPR8,4(,R7) Store short BFP difference +00000000000003DC B29C 8004 0000000000000004 306 STFPC 4(R8) Store resulting FPCR flags and DXC +00000000000003E0 B222 0000 307 IPM R0 Get condition code and program mask +00000000000003E4 8800 001C 000000000000001C 308 SRL R0,28 Isolate CC in low order byte +00000000000003E8 4200 8007 0000000000000007 309 STC R0,7(,R8) Save condition code in results table + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 8 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 310 * +00000000000003EC 7880 3000 0000000000000000 311 LE FPR8,0(,R3) Get short BFP minuend +00000000000003F0 7810 5000 0000000000000000 312 LE FPR1,0(,R5) Get short BFP subtrahend +00000000000003F4 B29D F294 0000000000000294 313 LFPC FPCREGNT Set exceptions non-trappable +00000000000003F8 ED80 5000 000B 0000000000000000 314 SEB FPR8,0(,R5) Subtract short subtrahend from FPR8 RXE +00000000000003FE 7080 7008 0000000000000008 315 STE FPR8,8(,R7) Store short BFP difference +0000000000000402 B29C 8008 0000000000000008 316 STFPC 8(R8) Store resulting FPCR flags and DXC +0000000000000406 B222 0000 317 IPM R0 Get condition code and program mask +000000000000040A 8800 001C 000000000000001C 318 SRL R0,28 Isolate CC in low order byte +000000000000040E 4200 800B 000000000000000B 319 STC R0,11(,R8) Save condition code in results table + 320 * +0000000000000412 7880 3000 0000000000000000 321 LE FPR8,0(,R3) Get short BFP minuend +0000000000000416 B29D F298 0000000000000298 322 LFPC FPCREGTR Set exceptions trappable +000000000000041A ED80 5000 000B 0000000000000000 323 SEB FPR8,0(,R5) Subtract short subtrahend from FPR8 RXE +0000000000000420 7080 700C 000000000000000C 324 STE FPR8,12(,R7) Store short BFP difference +0000000000000424 B29C 800C 000000000000000C 325 STFPC 12(R8) Store resulting FPCR flags and DXC +0000000000000428 B222 0000 326 IPM R0 Get condition code and program mask +000000000000042C 8800 001C 000000000000001C 327 SRL R0,28 Isolate CC in low order byte +0000000000000430 4200 800F 000000000000000F 328 STC R0,15(,R8) Save condition code in results table + 329 * +0000000000000434 4150 5004 0000000000000004 330 LA R5,4(,R5) Point to next subtrahend value +0000000000000438 4170 7010 0000000000000010 331 LA R7,4*4(,R7) Point to next Subtract result area +000000000000043C 4180 8010 0000000000000010 332 LA R8,4*4(,R8) Point to next Subtract FPCR area +0000000000000440 0646 333 BCTR R4,R6 Loop through right-hand values + 334 * +0000000000000442 4130 3004 0000000000000004 335 LA R3,4(,R3) Point to next input minuend +0000000000000446 062C 336 BCTR R2,R12 Loop through left-hand values +0000000000000448 07FD 337 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 9 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 339 *********************************************************************** + 340 * + 341 * Perform Subtract using provided short BFP input pairs. This set of + 342 * tests triggers IEEE exceptions Overflow, Underflow, and Inexact and + 343 * collects both trap and non-trap results. + 344 * + 345 * Four results are generated for each input: one RRE with all + 346 * exceptions non-trappable, a second RRE with all exceptions trappable, + 347 * a third RXE with all exceptions non-trappable, a fourth RXE with all + 348 * exceptions trappable, + 349 * + 350 * The difference, FPCR, and condition code are stored for each result. + 351 * + 352 *********************************************************************** + + +000000000000044A 9823 A000 0000000000000000 354 SBFPF LM R2,R3,0(R10) Get count and address of test input values +000000000000044E 9878 A008 0000000000000008 355 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000452 1222 356 LTR R2,R2 Any test cases? +0000000000000454 078D 357 BZR R13 ..No, return to caller +0000000000000456 0DC0 358 BASR R12,0 Set top of loop + 359 * +0000000000000458 B29D F294 0000000000000294 360 LFPC FPCREGNT Set exceptions non-trappable +000000000000045C 7880 3000 0000000000000000 361 LE FPR8,0(,R3) Get short BFP minuend +0000000000000460 7810 3004 0000000000000004 362 LE FPR1,4(,R3) Get short BFP subtrahend +0000000000000464 B30B 0081 363 SEBR FPR8,FPR1 Subtract short FPR1 from FPR8 RRE +0000000000000468 7080 7000 0000000000000000 364 STE FPR8,0(,R7) Store short BFP difference +000000000000046C B29C 8000 0000000000000000 365 STFPC 0(R8) Store resulting FPCR flags and DXC +0000000000000470 B222 0000 366 IPM R0 Get condition code and program mask +0000000000000474 8800 001C 000000000000001C 367 SRL R0,28 Isolate CC in low order byte +0000000000000478 4200 8003 0000000000000003 368 STC R0,3(,R8) Save condition code in results table + 369 * +000000000000047C B29D F298 0000000000000298 370 LFPC FPCREGTR Set exceptions trappable +0000000000000480 7880 3000 0000000000000000 371 LE FPR8,0(,R3) Reload short BFP minuend + 372 * ..subtrahend is still in FPR1 +0000000000000484 B30B 0081 373 SEBR FPR8,FPR1 Subtract short FPR1 from FPR8 RRE +0000000000000488 7080 7004 0000000000000004 374 STE FPR8,4(,R7) Store short BFP difference +000000000000048C B29C 8004 0000000000000004 375 STFPC 4(R8) Store resulting FPCR flags and DXC +0000000000000490 B222 0000 376 IPM R0 Get condition code and program mask +0000000000000494 8800 001C 000000000000001C 377 SRL R0,28 Isolate CC in low order byte +0000000000000498 4200 8007 0000000000000007 378 STC R0,7(,R8) Save condition code in results table + 379 * +000000000000049C B29D F294 0000000000000294 380 LFPC FPCREGNT Set exceptions non-trappable +00000000000004A0 7880 3000 0000000000000000 381 LE FPR8,0(,R3) Reload short BFP minuend +00000000000004A4 ED80 3004 000B 0000000000000004 382 SEB FPR8,4(,R3) Subtract short subtrahend from FPR8 RXE +00000000000004AA 7080 7008 0000000000000008 383 STE FPR8,8(,R7) Store short BFP difference +00000000000004AE B29C 8008 0000000000000008 384 STFPC 8(R8) Store resulting FPCR flags and DXC +00000000000004B2 B222 0000 385 IPM R0 Get condition code and program mask +00000000000004B6 8800 001C 000000000000001C 386 SRL R0,28 Isolate CC in low order byte +00000000000004BA 4200 800B 000000000000000B 387 STC R0,11(,R8) Save condition code in results table + 388 * +00000000000004BE B29D F298 0000000000000298 389 LFPC FPCREGTR Set exceptions trappable + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 10 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000004C2 7880 3000 0000000000000000 390 LE FPR8,0(,R3) Reload short BFP minuend +00000000000004C6 ED80 3004 000B 0000000000000004 391 SEB FPR8,4(,R3) Subtract short subtrahend from FPR8 RXE +00000000000004CC 7080 700C 000000000000000C 392 STE FPR8,12(,R7) Store short BFP difference +00000000000004D0 B29C 800C 000000000000000C 393 STFPC 12(R8) Store resulting FPCR flags and DXC +00000000000004D4 B222 0000 394 IPM R0 Get condition code and program mask +00000000000004D8 8800 001C 000000000000001C 395 SRL R0,28 Isolate CC in low order byte +00000000000004DC 4200 800F 000000000000000F 396 STC R0,15(,R8) Save condition code in results table + 397 * +00000000000004E0 4130 3008 0000000000000008 398 LA R3,2*4(,R3) Point to next input value pair +00000000000004E4 4170 7010 0000000000000010 399 LA R7,4*4(,R7) Point to next difference result set +00000000000004E8 4180 8010 0000000000000010 400 LA R8,4*4(,R8) Point to next FPCR result set +00000000000004EC 062C 401 BCTR R2,R12 Convert next input value. +00000000000004EE 07FD 402 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 11 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 404 *********************************************************************** + 405 * + 406 * Perform Subtract using provided short BFP input pairs. This set of + 407 * tests exhaustively tests all rounding modes available for Subtract. + 408 * The rounding mode can only be specified in the FPC. + 409 * + 410 * All five FPC rounding modes are tested because the preceeding tests, + 411 * using rounding mode RNTE, do not often create results that require + 412 * rounding. + 413 * + 414 * Two results are generated for each input and rounding mode: one RRE + 415 * and one RXE. Traps are disabled for all rounding mode tests. + 416 * + 417 * The difference, FPCR, and condition code are stored for each test. + 418 * + 419 *********************************************************************** + + +00000000000004F0 9823 A000 0000000000000000 421 SBFPRM LM R2,R3,0(R10) Get count and address of test input values +00000000000004F4 9878 A008 0000000000000008 422 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000004F8 1222 423 LTR R2,R2 Any test cases? +00000000000004FA 078D 424 BZR R13 ..No, return to caller +00000000000004FC 1711 425 XR R1,R1 Zero register 1 for use in IC/STC/indexing +00000000000004FE 0DC0 426 BASR R12,0 Set top of test case loop + 427 +0000000000000500 4150 0005 0000000000000005 428 LA R5,FPCMCT Get count of FPC modes to be tested +0000000000000504 0D90 429 BASR R9,0 Set top of rounding mode outer loop + 430 * +0000000000000506 4315 F8AF 00000000000008AF 431 IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode + 432 * +000000000000050A B29D F294 0000000000000294 433 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000050E B2B8 1000 0000000000000000 434 SRNMB 0(R1) Set FPC Rounding Mode +0000000000000512 7880 3000 0000000000000000 435 LE FPR8,0(,R3) Get short BFP minuend +0000000000000516 7810 3004 0000000000000004 436 LE FPR1,4(,R3) Get short BFP subtrahend +000000000000051A B30B 0081 437 SEBR FPR8,FPR1 Subtract short FPR1 from FPR8 RRE +000000000000051E 7080 7000 0000000000000000 438 STE FPR8,0(,R7) Store short BFP difference +0000000000000522 B29C 8000 0000000000000000 439 STFPC 0(R8) Store resulting FPCR flags and DXC +0000000000000526 B222 0000 440 IPM R0 Get condition code and program mask +000000000000052A 8800 001C 000000000000001C 441 SRL R0,28 Isolate CC in low order byte +000000000000052E 4200 8003 0000000000000003 442 STC R0,3(,R8) Save condition code in results table + 443 * +0000000000000532 B29D F294 0000000000000294 444 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000536 B2B8 1000 0000000000000000 445 SRNMB 0(R1) Set FPC Rounding Mode +000000000000053A 7880 3000 0000000000000000 446 LE FPR8,0(,R3) Get short BFP minuend +000000000000053E ED80 3004 000B 0000000000000004 447 SEB FPR8,4(,R3) Subtract short subtrahend from FPR8 RXE +0000000000000544 7080 7004 0000000000000004 448 STE FPR8,4(,R7) Store short BFP difference +0000000000000548 B29C 8004 0000000000000004 449 STFPC 4(R8) Store resulting FPCR flags and DXC +000000000000054C B222 0000 450 IPM R0 Get condition code and program mask +0000000000000550 8800 001C 000000000000001C 451 SRL R0,28 Isolate CC in low order byte +0000000000000554 4200 8007 0000000000000007 452 STC R0,7(,R8) Save condition code in results table + 453 * +0000000000000558 4170 7008 0000000000000008 454 LA R7,2*4(,R7) Point to next difference result set + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 12 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +000000000000055C 4180 8008 0000000000000008 455 LA R8,2*4(,R8) Point to next FPCR result area + 456 * +0000000000000560 0659 457 BCTR R5,R9 Iterate to next FPC mode for this input + 458 * + 459 * End of FPC modes to be tested. Advance to next test case. We will + 460 * skip eight bytes of result area so that each set of five result + 461 * value pairs starts at a memory address ending in zero for the + 462 * convenience of memory dump review. + 463 * +0000000000000562 4130 3008 0000000000000008 464 LA R3,2*4(,R3) Point to next input value pair +0000000000000566 4170 7008 0000000000000008 465 LA R7,8(,R7) Skip to start of next result set +000000000000056A 4180 8008 0000000000000008 466 LA R8,8(,R8) Skip to start of next FPCR result set +000000000000056E 062C 467 BCTR R2,R12 Advance to the next input pair + 468 * +0000000000000570 07FD 469 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 13 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 471 *********************************************************************** + 472 * + 473 * Perform Subtract using provided long BFP inputs. This set of tests + 474 * checks NaN propagation, operations on values that are not finite + 475 * numbers, and other basic tests. This set generates results that can + 476 * be validated against Figure 19-13 on page 19-16 of SA22-7832-10. + 477 * + 478 * That Figure has separate rows and colums for Normal and Tiny + 479 * operands. Although the results are effectively the same for Normal + 480 * and Tiny in any combination, the input data includes Normal and + 481 * Tiny values. + 482 * + 483 * Four results are generated for each input: one RRE with all + 484 * exceptions non-trappable, a second RRE with all exceptions trappable, + 485 * a third RXE with all exceptions non-trappable, a fourth RXE with all + 486 * exceptions trappable, + 487 * + 488 * The difference, FPCR, and condition code are stored for each result. + 489 * + 490 *********************************************************************** + + +0000000000000572 492 LBFPNF DS 0H BFP long non-finite values tests +0000000000000572 9823 A000 0000000000000000 493 LM R2,R3,0(R10) Get count and address of minuend values +0000000000000576 9878 A008 0000000000000008 494 LM R7,R8,8(R10) Get address of result area and flag area. +000000000000057A 1222 495 LTR R2,R2 Any test cases? +000000000000057C 078D 496 BZR R13 ..No, return to caller +000000000000057E 0DC0 497 BASR R12,0 Set top of loop + 498 * +0000000000000580 9845 A000 0000000000000000 499 LM R4,R5,0(R10) Get count and start of subtrahend values + 500 * ..which are the same as the minuends +0000000000000584 0D60 501 BASR R6,0 Set top of inner loop + 502 * +0000000000000586 6880 3000 0000000000000000 503 LD FPR8,0(,R3) Get long BFP minuend +000000000000058A 6810 5000 0000000000000000 504 LD FPR1,0(,R5) Get long BFP subtrahend +000000000000058E B29D F294 0000000000000294 505 LFPC FPCREGNT Set exceptions non-trappable +0000000000000592 B31B 0081 506 SDBR FPR8,FPR1 Subtract long FPR1 from FPR8 RRE +0000000000000596 6080 7000 0000000000000000 507 STD FPR8,0(,R7) Store long BFP difference +000000000000059A B29C 8000 0000000000000000 508 STFPC 0(R8) Store resulting FPCR flags and DXC +000000000000059E B222 0000 509 IPM R0 Get condition code and program mask +00000000000005A2 8800 001C 000000000000001C 510 SRL R0,28 Isolate CC in low order byte +00000000000005A6 4200 8003 0000000000000003 511 STC R0,3(,R8) Save condition code in results table + 512 * +00000000000005AA 6880 3000 0000000000000000 513 LD FPR8,0(,R3) Get long BFP minuend +00000000000005AE 6810 5000 0000000000000000 514 LD FPR1,0(,R5) Get long BFP subtrahend +00000000000005B2 B29D F298 0000000000000298 515 LFPC FPCREGTR Set exceptions trappable +00000000000005B6 B31B 0081 516 SDBR FPR8,FPR1 Subtract long subtrahend from FPR8 RRE +00000000000005BA 6080 7008 0000000000000008 517 STD FPR8,8(,R7) Store long BFP remainder +00000000000005BE B29C 8004 0000000000000004 518 STFPC 4(R8) Store resulting FPCR flags and DXC +00000000000005C2 B222 0000 519 IPM R0 Get condition code and program mask +00000000000005C6 8800 001C 000000000000001C 520 SRL R0,28 Isolate CC in low order byte +00000000000005CA 4200 8007 0000000000000007 521 STC R0,7(,R8) Save condition code in results table + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 14 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 522 * +00000000000005CE 6880 3000 0000000000000000 523 LD FPR8,0(,R3) Get long BFP minuend +00000000000005D2 B29D F294 0000000000000294 524 LFPC FPCREGNT Set exceptions non-trappable +00000000000005D6 ED80 5000 001B 0000000000000000 525 SDB FPR8,0(,R5) Subtract long subtrahend from FPR8 RXE +00000000000005DC 6080 7010 0000000000000010 526 STD FPR8,16(,R7) Store long BFP difference +00000000000005E0 B29C 8008 0000000000000008 527 STFPC 8(R8) Store resulting FPCR flags and DXC +00000000000005E4 B222 0000 528 IPM R0 Get condition code and program mask +00000000000005E8 8800 001C 000000000000001C 529 SRL R0,28 Isolate CC in low order byte +00000000000005EC 4200 800B 000000000000000B 530 STC R0,11(,R8) Save condition code in results table + 531 * +00000000000005F0 6880 3000 0000000000000000 532 LD FPR8,0(,R3) Get long BFP minuend +00000000000005F4 B29D F298 0000000000000298 533 LFPC FPCREGTR Set exceptions trappable +00000000000005F8 ED80 5000 001B 0000000000000000 534 SDB FPR8,0(,R5) Subtract long subtrahend from FPR8 RXE +00000000000005FE 6080 7018 0000000000000018 535 STD FPR8,24(,R7) Store long BFP remainder +0000000000000602 B29C 800C 000000000000000C 536 STFPC 12(R8) Store resulting FPCR flags and DXC +0000000000000606 B222 0000 537 IPM R0 Get condition code and program mask +000000000000060A 8800 001C 000000000000001C 538 SRL R0,28 Isolate CC in low order byte +000000000000060E 4200 800F 000000000000000F 539 STC R0,15(,R8) Save condition code in results table + 540 * +0000000000000612 4150 5008 0000000000000008 541 LA R5,8(,R5) Point to next subtrahend value +0000000000000616 4170 7020 0000000000000020 542 LA R7,4*8(,R7) Point to next Subtract result area +000000000000061A 4180 8010 0000000000000010 543 LA R8,4*4(,R8) Point to next Subtract FPCR area +000000000000061E 0646 544 BCTR R4,R6 Loop through right-hand values + 545 * +0000000000000620 4130 3008 0000000000000008 546 LA R3,8(,R3) Point to next minuend value +0000000000000624 062C 547 BCTR R2,R12 Subtract until all cases tested +0000000000000626 07FD 548 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 15 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 550 *********************************************************************** + 551 * + 552 * Perform Subtract using provided long BFP input pairs. This set of + 553 * tests triggers IEEE exceptions Overflow, Underflow, and Inexact and + 554 * collects non-trap and trap results. + 555 * + 556 * Four results are generated for each input: one RRE with all + 557 * exceptions non-trappable, a second RRE with all exceptions trappable, + 558 * a third RXE with all exceptions non-trappable, a fourth RXE with all + 559 * exceptions trappable, + 560 * + 561 * The difference, FPCR, and condition code are stored for each result. + 562 * + 563 *********************************************************************** + + +0000000000000628 9823 A000 0000000000000000 565 LBFPF LM R2,R3,0(R10) Get count and address of test input values +000000000000062C 9878 A008 0000000000000008 566 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000630 1222 567 LTR R2,R2 Any test cases? +0000000000000632 078D 568 BZR R13 ..No, return to caller +0000000000000634 0DC0 569 BASR R12,0 Set top of loop + 570 * +0000000000000636 B29D F294 0000000000000294 571 LFPC FPCREGNT Set exceptions non-trappable +000000000000063A 6880 3000 0000000000000000 572 LD FPR8,0(,R3) Get long BFP minuend +000000000000063E 6810 3008 0000000000000008 573 LD FPR1,8(,R3) Get long BFP subtrahend +0000000000000642 B31B 0081 574 SDBR FPR8,FPR1 Subtract long FPR1 from FPR8 RRE +0000000000000646 6080 7000 0000000000000000 575 STD FPR8,0(,R7) Store long BFP difference +000000000000064A B29C 8000 0000000000000000 576 STFPC 0(R8) Store resulting FPCR flags and DXC +000000000000064E B222 0000 577 IPM R0 Get condition code and program mask +0000000000000652 8800 001C 000000000000001C 578 SRL R0,28 Isolate CC in low order byte +0000000000000656 4200 8003 0000000000000003 579 STC R0,3(,R8) Save condition code in results table + 580 * +000000000000065A B29D F298 0000000000000298 581 LFPC FPCREGTR Set exceptions trappable +000000000000065E 6880 3000 0000000000000000 582 LD FPR8,0(,R3) Reload long BFP minuend + 583 * ..subtrahend is still in FPR1 +0000000000000662 B31B 0081 584 SDBR FPR8,FPR1 Subtract long FPR1 from FPR8 RRE +0000000000000666 6080 7008 0000000000000008 585 STD FPR8,8(,R7) Store long BFP difference +000000000000066A B29C 8004 0000000000000004 586 STFPC 4(R8) Store resulting FPCR flags and DXC +000000000000066E B222 0000 587 IPM R0 Get condition code and program mask +0000000000000672 8800 001C 000000000000001C 588 SRL R0,28 Isolate CC in low order byte +0000000000000676 4200 8007 0000000000000007 589 STC R0,7(,R8) Save condition code in results table + 590 * +000000000000067A B29D F294 0000000000000294 591 LFPC FPCREGNT Set exceptions non-trappable +000000000000067E 6880 3000 0000000000000000 592 LD FPR8,0(,R3) Reload long BFP minuend +0000000000000682 ED80 3008 001B 0000000000000008 593 SDB FPR8,8(,R3) Subtract long subtrahend from FPR8 RXE +0000000000000688 6080 7010 0000000000000010 594 STD FPR8,16(,R7) Store long BFP difference +000000000000068C B29C 8008 0000000000000008 595 STFPC 8(R8) Store resulting FPCR flags and DXC +0000000000000690 B222 0000 596 IPM R0 Get condition code and program mask +0000000000000694 8800 001C 000000000000001C 597 SRL R0,28 Isolate CC in low order byte +0000000000000698 4200 800B 000000000000000B 598 STC R0,11(,R8) Save condition code in results table + 599 * +000000000000069C B29D F298 0000000000000298 600 LFPC FPCREGTR Set exceptions trappable + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 16 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000006A0 6880 3000 0000000000000000 601 LD FPR8,0(,R3) Reload long BFP minuend +00000000000006A4 ED80 3008 001B 0000000000000008 602 SDB FPR8,8(,R3) Subtract long subtrahend from FPR8 RXE +00000000000006AA 6080 7018 0000000000000018 603 STD FPR8,24(,R7) Store long BFP difference +00000000000006AE B29C 800C 000000000000000C 604 STFPC 12(R8) Store resulting FPCR flags and DXC +00000000000006B2 B222 0000 605 IPM R0 Get condition code and program mask +00000000000006B6 8800 001C 000000000000001C 606 SRL R0,28 Isolate CC in low order byte +00000000000006BA 4200 800F 000000000000000F 607 STC R0,15(,R8) Save condition code in results table + 608 * +00000000000006BE 4130 3010 0000000000000010 609 LA R3,2*8(,R3) Point to next input value pair +00000000000006C2 4170 7020 0000000000000020 610 LA R7,4*8(,R7) Point to next quotent result pair +00000000000006C6 4180 8010 0000000000000010 611 LA R8,4*4(,R8) Point to next FPCR result area +00000000000006CA 062C 612 BCTR R2,R12 Convert next input value. +00000000000006CC 07FD 613 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 17 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 615 *********************************************************************** + 616 * + 617 * Perform Subtract using provided long BFP input pairs. This set of + 618 * tests exhaustively tests all rounding modes available for Subtract. + 619 * The rounding mode can only be specified in the FPC. + 620 * + 621 * All five FPC rounding modes are tested because the preceeding tests, + 622 * using rounding mode RNTE, do not often create results that require + 623 * rounding. + 624 * + 625 * Two results are generated for each input and rounding mode: one RRE + 626 * and one RXE. Traps are disabled for all rounding mode tests. + 627 * + 628 * The difference, FPCR, and condition code are stored for each result. + 629 * + 630 *********************************************************************** + + +00000000000006CE 9823 A000 0000000000000000 632 LBFPRM LM R2,R3,0(R10) Get count and address of test input values +00000000000006D2 9878 A008 0000000000000008 633 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000006D6 1222 634 LTR R2,R2 Any test cases? +00000000000006D8 078D 635 BZR R13 ..No, return to caller +00000000000006DA 1711 636 XR R1,R1 Zero register 1 for use in IC/STC/indexing +00000000000006DC 0DC0 637 BASR R12,0 Set top of test case loop + 638 +00000000000006DE 4150 0005 0000000000000005 639 LA R5,FPCMCT Get count of FPC modes to be tested +00000000000006E2 0D90 640 BASR R9,0 Set top of rounding mode loop + 641 * +00000000000006E4 4315 F8AF 00000000000008AF 642 IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode + 643 * +00000000000006E8 B29D F294 0000000000000294 644 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000006EC B2B8 1000 0000000000000000 645 SRNMB 0(R1) Set FPC Rounding Mode +00000000000006F0 6880 3000 0000000000000000 646 LD FPR8,0(,R3) Get long BFP minuend +00000000000006F4 6810 3008 0000000000000008 647 LD FPR1,8(,R3) Get long BFP subtrahend +00000000000006F8 B31B 0081 648 SDBR FPR8,FPR1 Subtract long FPR1 from FPR8 RRE +00000000000006FC 6080 7000 0000000000000000 649 STD FPR8,0(,R7) Store long BFP difference +0000000000000700 B29C 8000 0000000000000000 650 STFPC 0(R8) Store resulting FPCR flags and DXC +0000000000000704 B222 0000 651 IPM R0 Get condition code and program mask +0000000000000708 8800 001C 000000000000001C 652 SRL R0,28 Isolate CC in low order byte +000000000000070C 4200 8003 0000000000000003 653 STC R0,3(,R8) Save condition code in results table + 654 * +0000000000000710 B29D F294 0000000000000294 655 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000714 B2B8 1000 0000000000000000 656 SRNMB 0(R1) Set FPC Rounding Mode +0000000000000718 6880 3000 0000000000000000 657 LD FPR8,0(,R3) Reload long BFP minuend +000000000000071C ED80 3008 001B 0000000000000008 658 SDB FPR8,8(,R3) Subtract long subtrahend from FPR8 RXE +0000000000000722 6080 7008 0000000000000008 659 STD FPR8,8(,R7) Store long BFP difference +0000000000000726 B29C 8004 0000000000000004 660 STFPC 4(R8) Store resulting FPCR flags and DXC +000000000000072A B222 0000 661 IPM R0 Get condition code and program mask +000000000000072E 8800 001C 000000000000001C 662 SRL R0,28 Isolate CC in low order byte +0000000000000732 4200 8007 0000000000000007 663 STC R0,7(,R8) Save condition code in results table + 664 * +0000000000000736 4170 7010 0000000000000010 665 LA R7,2*8(,R7) Point to next difference result set + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 18 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +000000000000073A 4180 8008 0000000000000008 666 LA R8,2*4(,R8) Point to next FPCR result area + 667 * +000000000000073E 0659 668 BCTR R5,R9 Iterate to next FPC mode + 669 * + 670 * End of FPC modes to be tested. Advance to next test case. We will + 671 * skip eight bytes of FPCR result area so that each set of five result + 672 * FPCR contents pairs starts at a memory address ending in zero for the + 673 * convenience of memory dump review. + 674 * +0000000000000740 4130 3010 0000000000000010 675 LA R3,2*8(,R3) Point to next input value pair +0000000000000744 4180 8008 0000000000000008 676 LA R8,8(,R8) Skip to start of next FPCR result area +0000000000000748 062C 677 BCTR R2,R12 Subtract next input value lots of times + 678 * +000000000000074A 07FD 679 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 19 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 681 *********************************************************************** + 682 * + 683 * Perform Subtract using provided extended BFP inputs. This set of + 684 * tests checks NaN propagation, operations on values that are not + 685 * finite numbers, and other basic tests. This set generates results + 686 * that can be validated against Figure 19-13 on page 19-16 of + 687 * SA22-7832-10. + 688 * + 689 * That Figure has separate rows and colums for Normal and Tiny + 690 * operands. Although the results are effectively the same for Normal + 691 * and Tiny in any combination, the input data includes Normal and + 692 * Tiny values. + 693 * + 694 * Two results are generated for each input: one RRE with all + 695 * exceptions non-trappable, and a second RRE with all exceptions + 696 * trappable. Extended BFP Subtract does not have an RXE format. + 697 * + 698 * The difference, FPCR, and condition code are stored for each result. + 699 * + 700 *********************************************************************** + + +000000000000074C 702 XBFPNF DS 0H BFP extended non-finite values tests +000000000000074C 9823 A000 0000000000000000 703 LM R2,R3,0(R10) Get count and address of minuend values +0000000000000750 9878 A008 0000000000000008 704 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000754 1222 705 LTR R2,R2 Any test cases? +0000000000000756 078D 706 BZR R13 ..No, return to caller +0000000000000758 0DC0 707 BASR R12,0 Set top of loop + 708 * +000000000000075A 9845 A000 0000000000000000 709 LM R4,R5,0(R10) Get count and start of subtrahend values + 710 * ..which are the same as the minuends +000000000000075E 0D60 711 BASR R6,0 Set top of inner loop + 712 * +0000000000000760 6880 3000 0000000000000000 713 LD FPR8,0(,R3) Get extended BFP minuend part 1 +0000000000000764 68A0 3008 0000000000000008 714 LD FPR10,8(,R3) Get extended BFP minuend part 2 +0000000000000768 6810 5000 0000000000000000 715 LD FPR1,0(,R5) Get extended BFP subtrahend part 1 +000000000000076C 6830 5008 0000000000000008 716 LD FPR3,8(,R5) Get extended BFP subtrahend part 2 +0000000000000770 B29D F294 0000000000000294 717 LFPC FPCREGNT Set exceptions non-trappable +0000000000000774 B34B 0081 718 SXBR FPR8,FPR1 Subtract extended FPR1-3 from FPR8-10 RRE +0000000000000778 6080 7000 0000000000000000 719 STD FPR8,0(,R7) Store extended BFP difference part 1 +000000000000077C 60A0 7008 0000000000000008 720 STD FPR10,8(,R7) Store extended BFP difference part 2 +0000000000000780 B29C 8000 0000000000000000 721 STFPC 0(R8) Store resulting FPCR flags and DXC +0000000000000784 B222 0000 722 IPM R0 Get condition code and program mask +0000000000000788 8800 001C 000000000000001C 723 SRL R0,28 Isolate CC in low order byte +000000000000078C 4200 8003 0000000000000003 724 STC R0,3(,R8) Save condition code in results table + 725 * +0000000000000790 68D0 3000 0000000000000000 726 LD FPR13,0(,R3) Get extended BFP minuend part 1 +0000000000000794 68F0 3008 0000000000000008 727 LD FPR15,8(,R3) Get extended BFP minuend part 2 +0000000000000798 6810 5000 0000000000000000 728 LD FPR1,0(,R5) Get extended BFP subtrahend part 1 +000000000000079C 6830 5008 0000000000000008 729 LD FPR3,8(,R5) Get extended BFP subtrahend part 2 +00000000000007A0 B29D F298 0000000000000298 730 LFPC FPCREGTR Set exceptions trappable +00000000000007A4 B34B 00D1 731 SXBR FPR13,FPR1 Subtract extended FPR1-3 from FPR13-15 RRE + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 20 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000007A8 60D0 7010 0000000000000010 732 STD FPR13,16(,R7) Store extended BFP difference part 1 +00000000000007AC 60F0 7018 0000000000000018 733 STD FPR15,24(,R7) Store extended BFP difference part 2 +00000000000007B0 B29C 8004 0000000000000004 734 STFPC 4(R8) Store resulting FPCR flags and DXC +00000000000007B4 B222 0000 735 IPM R0 Get condition code and program mask +00000000000007B8 8800 001C 000000000000001C 736 SRL R0,28 Isolate CC in low order byte +00000000000007BC 4200 8007 0000000000000007 737 STC R0,7(,R8) Save condition code in results table + 738 * +00000000000007C0 4150 5010 0000000000000010 739 LA R5,16(,R5) Point to next subtrahend value +00000000000007C4 4170 7020 0000000000000020 740 LA R7,32(,R7) Point to next Subtract result area +00000000000007C8 4180 8010 0000000000000010 741 LA R8,16(,R8) Point to next Subtract FPCR area +00000000000007CC 0646 742 BCTR R4,R6 Loop through right-hand values + 743 * +00000000000007CE 4130 3010 0000000000000010 744 LA R3,16(,R3) Point to next minuend value +00000000000007D2 062C 745 BCTR R2,R12 Subtract until all cases tested +00000000000007D4 07FD 746 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 21 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 748 *********************************************************************** + 749 * + 750 * Perform Subtract using provided extended BFP input pairs. This set + 751 * of tests triggers IEEE exceptions Overflow, Underflow, and Inexact + 752 * and collects results when the exceptions do not result in a trap and + 753 * when they do. + 754 * + 755 * Two results are generated for each input: one RRE with all + 756 * exceptions non-trappable and a second RRE with all exceptions + 757 * trappable. There is no RXE format for Subtract in extended + 758 * precision. + 759 * + 760 * The difference, FPCR, and condition code are stored for each result. + 761 * + 762 *********************************************************************** + + +00000000000007D6 9823 A000 0000000000000000 764 XBFPF LM R2,R3,0(R10) Get count and address of test input values +00000000000007DA 9878 A008 0000000000000008 765 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000007DE 1222 766 LTR R2,R2 Any test cases? +00000000000007E0 078D 767 BZR R13 ..No, return to caller +00000000000007E2 0DC0 768 BASR R12,0 Set top of loop + 769 * +00000000000007E4 B29D F294 0000000000000294 770 LFPC FPCREGNT Set exceptions non-trappable +00000000000007E8 68D0 3000 0000000000000000 771 LD FPR13,0(,R3) Get extended BFP minuend part 1 +00000000000007EC 68F0 3008 0000000000000008 772 LD FPR15,8(,R3) Get extended BFP minuend part 2 +00000000000007F0 6810 3010 0000000000000010 773 LD FPR1,16(,R3) Get extended BFP subtrahend part 1 +00000000000007F4 6830 3018 0000000000000018 774 LD FPR3,24(,R3) Get extended BFP subtrahend part 2 +00000000000007F8 B34B 00D1 775 SXBR FPR13,FPR1 Subtract extended FPR1-3 from FPR13-15 RRE +00000000000007FC 60D0 7000 0000000000000000 776 STD FPR13,0(,R7) Store extended BFP difference part 1 +0000000000000800 60F0 7008 0000000000000008 777 STD FPR15,8(,R7) Store extended BFP difference part 2 +0000000000000804 B29C 8000 0000000000000000 778 STFPC 0(R8) Store resulting FPCR flags and DXC +0000000000000808 B222 0000 779 IPM R0 Get condition code and program mask +000000000000080C 8800 001C 000000000000001C 780 SRL R0,28 Isolate CC in low order byte +0000000000000810 4200 8003 0000000000000003 781 STC R0,3(,R8) Save condition code in results table + 782 * +0000000000000814 B29D F298 0000000000000298 783 LFPC FPCREGTR Set exceptions trappable +0000000000000818 68D0 3000 0000000000000000 784 LD FPR13,0(,R3) Reload extended BFP minuend part 1 +000000000000081C 68F0 3008 0000000000000008 785 LD FPR15,8(,R3) Reload extended BFP minuend part 2 + 786 * ..subtrahend is still in FPR1-FPR3 +0000000000000820 B34B 00D1 787 SXBR FPR13,FPR1 Subtract extended FPR1-3 from FPR13-15 RRE +0000000000000824 60D0 7010 0000000000000010 788 STD FPR13,16(,R7) Store extended BFP difference part 1 +0000000000000828 60F0 7018 0000000000000018 789 STD FPR15,24(,R7) Store extended BFP difference part 2 +000000000000082C B29C 8004 0000000000000004 790 STFPC 4(R8) Store resulting FPCR flags and DXC +0000000000000830 B222 0000 791 IPM R0 Get condition code and program mask +0000000000000834 8800 001C 000000000000001C 792 SRL R0,28 Isolate CC in low order byte +0000000000000838 4200 8007 0000000000000007 793 STC R0,7(,R8) Save condition code in results table + 794 * +000000000000083C 4130 3020 0000000000000020 795 LA R3,32(,R3) Point to next input value pair +0000000000000840 4170 7020 0000000000000020 796 LA R7,32(,R7) Point to next quotent result pair +0000000000000844 4180 8010 0000000000000010 797 LA R8,16(,R8) Point to next FPCR result area +0000000000000848 062C 798 BCTR R2,R12 Convert next input value. + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 22 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 799 * +000000000000084A 07FD 800 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 23 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 802 *********************************************************************** + 803 * + 804 * Perform Subtract using provided extended BFP input pairs. This set + 805 * of tests exhaustively tests all rounding modes available for + 806 * Subtract. The rounding mode can only be specified in the FPC. + 807 * + 808 * All five FPC rounding modes are tested because the preceeding tests, + 809 * using rounding mode RNTE, do not often create results that require + 810 * rounding. + 811 * + 812 * Two results are generated for each input and rounding mode: one RRE + 813 * and one RXE. Traps are disabled for all rounding mode tests. + 814 * + 815 * The difference, FPCR, and condition code are stored for each result. + 816 * + 817 *********************************************************************** + + +000000000000084C 9823 A000 0000000000000000 819 XBFPRM LM R2,R3,0(R10) Get count and address of test input values +0000000000000850 9878 A008 0000000000000008 820 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000854 1222 821 LTR R2,R2 Any test cases? +0000000000000856 078D 822 BZR R13 ..No, return to caller +0000000000000858 1711 823 XR R1,R1 Zero register 1 for use in IC/STC/indexing +000000000000085A 0DC0 824 BASR R12,0 Set top of test case loop + 825 +000000000000085C 4150 0005 0000000000000005 826 LA R5,FPCMCT Get count of FPC modes to be tested +0000000000000860 0D90 827 BASR R9,0 Set top of rounding mode loop + 828 * +0000000000000862 4315 F8AF 00000000000008AF 829 IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode + 830 * +0000000000000866 B29D F294 0000000000000294 831 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000086A B2B8 1000 0000000000000000 832 SRNMB 0(R1) Set FPC Rounding Mode +000000000000086E 68D0 3000 0000000000000000 833 LD FPR13,0(,R3) Get extended BFP minuend part 1 +0000000000000872 68F0 3008 0000000000000008 834 LD FPR15,8(,R3) Get extended BFP minuend part 2 +0000000000000876 6810 3010 0000000000000010 835 LD FPR1,16(,R3) Get extended BFP subtrahend part 1 +000000000000087A 6830 3018 0000000000000018 836 LD FPR3,24(,R3) Get extended BFP subtrahend part 2 +000000000000087E B34B 00D1 837 SXBR FPR13,FPR1 Subtract extended FPR1-3 from FPR13-15 RRE +0000000000000882 60D0 7000 0000000000000000 838 STD FPR13,0(,R7) Store extended BFP difference part 1 +0000000000000886 60F0 7008 0000000000000008 839 STD FPR15,8(,R7) Store extended BFP difference part 2 +000000000000088A B29C 8000 0000000000000000 840 STFPC 0(R8) Store resulting FPCR flags and DXC +000000000000088E B222 0000 841 IPM R0 Get condition code and program mask +0000000000000892 8800 001C 000000000000001C 842 SRL R0,28 Isolate CC in low order byte +0000000000000896 4200 8003 0000000000000003 843 STC R0,3(,R8) Save condition code in results table + 844 * +000000000000089A 4170 7010 0000000000000010 845 LA R7,16(,R7) Point to next difference result set +000000000000089E 4180 8004 0000000000000004 846 LA R8,4(,R8) Point to next FPCR result area + 847 * +00000000000008A2 0659 848 BCTR R5,R9 Iterate to next FPC mode + 849 * + 850 * End of FPC modes to be tested. Advance to next test case. We will + 851 * skip eight bytes of FPCR result area so that each set of five result + 852 * FPCR contents pairs starts at a memory address ending in zero for the + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 24 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 853 * convenience of memory dump review. + 854 * +00000000000008A4 4130 3020 0000000000000020 855 LA R3,2*16(,R3) Point to next input value pair +00000000000008A8 4180 800C 000000000000000C 856 LA R8,12(,R8) Skip to start of next FPCR result area +00000000000008AC 062C 857 BCTR R2,R12 Subtract next input value lots of times + 858 * +00000000000008AE 07FD 859 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 25 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 861 *********************************************************************** + 862 * + 863 * Table of FPC rounding modes to test difference rounding modes. + 864 * + 865 * The Set BFP Rounding Mode does allow specification of the FPC + 866 * rounding mode as an address, so we shall index into a table of + 867 * BFP rounding modes without bothering with Execute. + 868 * + 869 *********************************************************************** + + + 871 * + 872 * Rounding modes that may be set in the FPCR. The FPCR controls + 873 * rounding of the difference. + 874 * + 875 * These are indexed directly by the loop counter, which counts down. + 876 * So the modes are listed in reverse order here. + 877 * +00000000000008B0 878 FPCMODES DS 0C +00000000000008B0 07 879 DC AL1(7) RFS, Round for shorter precision +00000000000008B1 03 880 DC AL1(3) RM, Round to -infinity +00000000000008B2 02 881 DC AL1(2) RP, Round to +infinity +00000000000008B3 01 882 DC AL1(1) RZ, Round to zero +00000000000008B4 00 883 DC AL1(0) RNTE, Round to Nearest, ties to even + 0000000000000005 0000000000000001 884 FPCMCT EQU *-FPCMODES Count of FPC Modes to be tested + 885 * + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 26 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 887 *********************************************************************** + 888 * + 889 * Short BFP test data sets for Subtract testing. + 890 * + 891 * The first test data set is used for tests of basic functionality, + 892 * NaN propagation, and results from operations involving other than + 893 * finite numbers. + 894 * + 895 * The second test data set is used for testing boundary conditions + 896 * using two finite non-zero values. Each possible condition code + 897 * and type of result (normal, scaled, etc) is created by members of + 898 * this test data set. + 899 * + 900 * The third test data set is used for exhaustive testing of final + 901 * results across the five rounding modes available for the Subtract + 902 * instruction. + 903 * + 904 *********************************************************************** + + + 906 *********************************************************************** + 907 * + 908 * First input test data set, to test operations using non-finite or + 909 * zero inputs. Member values chosen to validate Figure 19-13 on page + 910 * 19-16 of SA22-7832-10. Each value in this table is tested against + 911 * every other value in the table. Ten entries means 100 result sets. + 912 * + 913 *********************************************************************** + + +00000000000008B8 915 SBFPNFIN DS 0F Inputs for short BFP non-finite tests +00000000000008B8 FF800000 916 DC X'FF800000' -inf +00000000000008BC C0000000 917 DC X'C0000000' -2.0 +00000000000008C0 80010000 918 DC X'80010000' -Dnice +00000000000008C4 80000000 919 DC X'80000000' -0 +00000000000008C8 00000000 920 DC X'00000000' +0 +00000000000008CC 00010000 921 DC X'00010000' -Dnice +00000000000008D0 40000000 922 DC X'40000000' +2.0 +00000000000008D4 7F800000 923 DC X'7F800000' +inf +00000000000008D8 FFCB0000 924 DC X'FFCB0000' -QNaN +00000000000008DC 7F8A0000 925 DC X'7F8A0000' +SNaN + 000000000000000A 0000000000000001 926 SBFPNFCT EQU (*-SBFPNFIN)/4 Count of short BFP in list + + + + 928 *********************************************************************** + 929 * + 930 * Second input test data set. These are finite pairs intended to + 931 * trigger overflow, underflow, and inexact exceptions. Each pair is + 932 * added twice, once non-trappable and once trappable. Trappable + 933 * overflow or underflow yields a scaled result. Trappable inexact + 934 * will show whether the Incremented DXC code is returned. + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 27 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 935 * + 936 * The following test cases are required: + 937 * 1. Overflow + 938 * 2. Underflow - normal inputs + 939 * 3. Underflow - subnormal inputs + 940 * 4. Normal - from subnormal inputs + 941 * 5. Inexact - incremented + 942 * 6. Inexact - truncated + 943 * + 944 *********************************************************************** + + +00000000000008E0 946 SBFPIN DS 0F Inputs for short BFP finite tests + 947 * + 948 * Overflow on subtraction + 949 * +00000000000008E0 7F7FFFFF 950 DC X'7F7FFFFF' +Nmax +00000000000008E4 FF7FFFFF 951 DC X'FF7FFFFF' -Nmax + 952 * + 953 * Underflow from difference of normals. We will subtract a small + 954 * normal from a slightly larger small normal to generate a subnormal. + 955 * +00000000000008E8 00FFFFFF 956 DC X'00FFFFFF' Very small normal number +00000000000008EC 00800000 957 DC X'00800000' Smaller normal + 958 * + 959 * Underflow from difference of subnormals. + 960 * +00000000000008F0 00040000 961 DC X'00040000' Subnormal, < +Dmax +00000000000008F4 00000F0F 962 DC X'00000F0F' Smaller subnormal + 963 * + 964 * Normal result from difference of subnormals. + 965 * The result will be greater than +Nmin + 966 * +00000000000008F8 007FFFFF 967 DC X'007FFFFF' +Dmax +00000000000008FC 80000001 968 DC X'80000001' -Dmin, result will be +Nmin + 969 * + 970 * Subtract a value from 1.0 such that the added digits are to the right + 971 * of the right-most bit in the stored significand. The result will be + 972 * inexact, and incremented will be determined by the value of the + 973 * bits in the subtrahend. + 974 * +0000000000000900 3F800000 975 DC X'3F800000' Minuend +1, aka 1.0b0 +0000000000000904 32800000 976 DC X'32800000' Subtrahend 1.b-26 + 977 *..Above subtrahend is 1.490116119384765625E-8 + 978 *..nearest is away from zero, incremented. + 979 * +0000000000000908 3F800000 980 DC X'3F800000' Minuend +1, aka 1.0b0 +000000000000090C 33100000 981 DC X'33100000' Subtrahend 1.001b-25 + 982 *..Above subtrahend is 3.35276126861572265625E-8 + 983 *..nearest is toward zero, truncated + 984 * + 0000000000000006 0000000000000001 985 SBFPCT EQU (*-SBFPIN)/4/2 Count of short BFP in list + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 28 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + + + + 987 *********************************************************************** + 988 * + 989 * Third input test data set. These are finite pairs intended to + 990 * test all combinations of rounding mode for the difference and the + 991 * remainder. Values are chosen to create a requirement to round + 992 * to the target precision after the computation and to generate + 993 * varying results depending on the rounding mode in the FPCR. + 994 * + 995 * The result set will have cases that represent each of the following + 996 * + 997 * 1. Positive, nearest magnitude is toward zero. + 998 * 2. Negative, nearest magnitude is toward zero. + 999 * 3. Positive, nearest magnitude is away from zero. + 1000 * 4. Negative, nearest magnitude is away from zero. + 1001 * 5. Positive, tie, nearest even has greater magnitude + 1002 * 6. Negative, tie, nearest even has greater magnitude + 1003 * 7. Positive, tie, nearest even has lower magnitude + 1004 * 8. Negative, tie, nearest even has lower magnitude + 1005 * + 1006 * Round For Shorter precision correctness can be determined from the + 1007 * above test cases. + 1008 * + 1009 *********************************************************************** + + +0000000000000910 1011 SBFPINRM DS 0F Inputs for short BFP rounding testing + 1012 * + 1013 * Subtract a value from 1.0 such that the added digits are to the right + 1014 * of the right-most bit in the stored significand. The result will be + 1015 * inexact, and incremented will be determined by the value of the + 1016 * bits in the subtrahend. + 1017 * +0000000000000910 3F800000 1018 DC X'3F800000' Minuend +1, aka 1.0b0 +0000000000000914 33100000 1019 DC X'33100000' Subtrahend 1.001b-25 +0000000000000918 BF800000 1020 DC X'BF800000' Minuend -1, aka -1.0b0 +000000000000091C B3100000 1021 DC X'B3100000' Subtrahend 1.001b-25 + 1022 *..Above subtrahend is 3.35276126861572265625E-8 + 1023 *..nearest is toward zero, truncated + 1024 * +0000000000000920 3F800000 1025 DC X'3F800000' Minuend +1, aka +1.0b0 +0000000000000924 32800000 1026 DC X'32800000' Subtrahend 1.b-26 +0000000000000928 BF800000 1027 DC X'BF800000' Minuend -1, aka -1.0b0 +000000000000092C B2800000 1028 DC X'B2800000' Subtrahend -1.b-26 + 1029 *..Above subtrahend is 1.490116119384765625E-8 + 1030 *..nearest is away from zero, incremented. + 1031 * +0000000000000930 3F800000 1032 DC X'3F800000' Minuend +1, aka +1.0b0 +0000000000000934 33C00000 1033 DC X'33C00000' Subtrahend +1.1b-24 +0000000000000938 BF800000 1034 DC X'BF800000' Minuend -1, aka -1.0b0 + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 29 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +000000000000093C B3C00000 1035 DC X'B3C00000' Subtrahend -1.1b-24 + 1036 *..Above subtrahend is 8.94069671630859375E-8 + 1037 *..nearest is a tie, nearest even has lower magnitude + 1038 * +0000000000000940 3F800000 1039 DC X'3F800000' Minuend +1, aka +1.0b0 +0000000000000944 33000000 1040 DC X'33000000' Subtrahend +1.0b-25 +0000000000000948 BF800000 1041 DC X'BF800000' Minuend -1, aka -1.0b0 +000000000000094C B3000000 1042 DC X'B3000000' Subtrahend -1.0b-25 + 1043 *..Above subtrahend is 2.98023223876953125E-8 + 1044 *..nearest is a tie, nearest even has greater magnitude + 1045 * + 0000000000000008 0000000000000001 1046 SBFPRMCT EQU (*-SBFPINRM)/4/2 Count of short BFP rounding tests + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 30 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1048 *********************************************************************** + 1049 * + 1050 * Long BFP test data sets for Add testing. + 1051 * + 1052 * The first test data set is used for tests of basic functionality, + 1053 * NaN propagation, and results from operations involving other than + 1054 * finite numbers. + 1055 * + 1056 * The second test data set is used for testing boundary conditions + 1057 * using two finite non-zero values. Each possible condition code + 1058 * and type of result (normal, scaled, etc) is created by members of + 1059 * this test data set. + 1060 * + 1061 * The third test data set is used for exhaustive testing of final + 1062 * results across the five rounding modes available for the Add + 1063 * instruction. + 1064 * + 1065 *********************************************************************** + + + 1067 *********************************************************************** + 1068 * + 1069 * First input test data set, to test operations using non-finite or + 1070 * zero inputs. Member values chosen to validate Figure 19-13 on page + 1071 * 19-16 of SA22-7832-10. Each value in this table is tested against + 1072 * every other value in the table. Ten entries means 100 result sets. + 1073 * + 1074 *********************************************************************** + + +0000000000000950 1076 LBFPNFIN DS 0F Inputs for long BFP testing +0000000000000950 FFF00000 00000000 1077 DC X'FFF0000000000000' -inf +0000000000000958 C0000000 00000000 1078 DC X'C000000000000000' -2.0 +0000000000000960 80010000 00000000 1079 DC X'8001000000000000' -Dnice +0000000000000968 80000000 00000000 1080 DC X'8000000000000000' -0 +0000000000000970 00000000 00000000 1081 DC X'0000000000000000' +0 +0000000000000978 00010000 00000000 1082 DC X'0001000000000000' +Dnice +0000000000000980 40000000 00000000 1083 DC X'4000000000000000' +2.0 +0000000000000988 7FF00000 00000000 1084 DC X'7FF0000000000000' +inf +0000000000000990 FFF8B000 00000000 1085 DC X'FFF8B00000000000' -QNaN +0000000000000998 7FF0A000 00000000 1086 DC X'7FF0A00000000000' +SNaN + 000000000000000A 0000000000000001 1087 LBFPNFCT EQU (*-LBFPNFIN)/8 Count of long BFP in list + + + + 1089 *********************************************************************** + 1090 * + 1091 * Second input test data set. These are finite pairs intended to + 1092 * trigger overflow, underflow, and inexact exceptions. Each pair is + 1093 * added twice, once non-trappable and once trappable. Trappable + 1094 * overflow or underflow yields a scaled result. Trappable inexact + 1095 * will show whether the Incremented DXC code is returned. + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 31 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1096 * + 1097 * The following test cases are required: + 1098 * 1. Overflow + 1099 * 2. Underflow - normal inputs + 1100 * 3. Underflow - subnormal inputs + 1101 * 4. Normal - from subnormal inputs + 1102 * 5. Inexact - incremented + 1103 * 6. Inexact - truncated + 1104 * + 1105 *********************************************************************** + + +00000000000009A0 1107 LBFPIN DS 0D Inputs for long BFP finite tests + 1108 * + 1109 * Overflow on subtraction + 1110 * +00000000000009A0 7FFFFFFF FFFFFFFF 1111 DC X'7FFFFFFFFFFFFFFF' +Nmax +00000000000009A8 FFFFFFFF FFFFFFFF 1112 DC X'FFFFFFFFFFFFFFFF' +Nmax + 1113 * + 1114 * Underflow from difference of normals. We wil subtract a small + 1115 * normal from a slightly larger normal to generate a subnormal. + 1116 * +00000000000009B0 001FFFFF FFFFFFFF 1117 DC X'001FFFFFFFFFFFFF' Very small normal number +00000000000009B8 00100000 00000000 1118 DC X'0010000000000000' Smaller normal negative + 1119 * + 1120 * Underflow from difference of subnormals. + 1121 * +00000000000009C0 00080000 00000000 1122 DC X'0008000000000000' Subnormal, < +Dmax +00000000000009C8 0000F0F0 00000000 1123 DC X'0000F0F000000000' Smaller subnormal + 1124 * + 1125 * Normal result from difference of subnormals. + 1126 * The result will be greater than +Nmin + 1127 * +00000000000009D0 000FFFFF FFFFFFFF 1128 DC X'000FFFFFFFFFFFFF' +Dmax +00000000000009D8 80000000 00000001 1129 DC X'8000000000000001' +Dmin, result will be +Nmin + 1130 * + 1131 * Subtract a value from 1.0 such that the added digits are to the right + 1132 * of the right-most bit in the stored significand. The result will be + 1133 * inexact, and incremented will be determined by the value of the + 1134 * bits in the subtrahend. + 1135 * +00000000000009E0 3FF00000 00000000 1136 DC X'3FF0000000000000' Minuend +1, aka 1.0b0 +00000000000009E8 3C800000 00000000 1137 DC X'3C80000000000000' Subtrahend 1.0b-55 + 1138 *..Above subtrahend is 2.77555756156289135105907917022705078125E-17 + 1139 *..nearest is away from zero, incremented. + 1140 * +00000000000009F0 3FF00000 00000000 1141 DC X'3FF0000000000000' Minuend +1, aka 1.0b0 +00000000000009F8 3C920000 00000000 1142 DC X'3C92000000000000' Subtrahend +1.001b-54 + 1143 *..Above subtrahend is 6.2450045135165055398829281330108642578125E-17 + 1144 *..nearest is toward zero, truncated. + 1145 * + 0000000000000006 0000000000000001 1146 LBFPCT EQU (*-LBFPIN)/8/2 Count of long BFP in list + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 32 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + + + + 1148 *********************************************************************** + 1149 * + 1150 * Third input test data set. These are finite pairs intended to + 1151 * test all combinations of rounding mode for the difference and the + 1152 * remainder. Values are chosen to create a requirement to round + 1153 * to the target precision after the computation and to generate + 1154 * varying results depending on the rounding mode in the FPCR. + 1155 * + 1156 * The result set will have cases that represent each of the following + 1157 * + 1158 * 1. Positive, nearest magnitude is toward zero. + 1159 * 2. Negative, nearest magnitude is toward zero. + 1160 * 3. Positive, nearest magnitude is away from zero. + 1161 * 4. Negative, nearest magnitude is away from zero. + 1162 * 5. Positive, tie, nearest even has greater magnitude + 1163 * 6. Negative, tie, nearest even has greater magnitude + 1164 * 7. Positive, tie, nearest even has lower magnitude + 1165 * 8. Negative, tie, nearest even has lower magnitude + 1166 * + 1167 * Round For Shorter precision correctness can be determined from the + 1168 * above test cases. + 1169 * + 1170 *********************************************************************** + + +0000000000000A00 1172 LBFPINRM DS 0F + 1173 * + 1174 * Subtract a value from 1.0 such that the added digits are to the right + 1175 * of the right-most bit in the stored significand. The result will be + 1176 * inexact, and incremented will be determined by the value of the + 1177 * bits in the subtrahend. + 1178 * +0000000000000A00 3FF00000 00000000 1179 DC X'3FF0000000000000' Minuend +1, aka +1.0b0 +0000000000000A08 3C920000 00000000 1180 DC X'3C92000000000000' Subtrahend +1.001b-54 +0000000000000A10 BFF00000 00000000 1181 DC X'BFF0000000000000' Minuend -1, aka -1.0b0 +0000000000000A18 BC920000 00000000 1182 DC X'BC92000000000000' Subtrahend +1.001b-54 + 1183 *..Above subtrahend is 6.2450045135165055398829281330108642578125E-17 + 1184 *.. ...30859375E-16,nearest is toward zero, truncated. + 1185 * +0000000000000A20 3FF00000 00000000 1186 DC X'3FF0000000000000' Minuend +1, aka +1.0b0 +0000000000000A28 3C800000 00000000 1187 DC X'3C80000000000000' Subtrahend 1.0b-55 +0000000000000A30 BFF00000 00000000 1188 DC X'BFF0000000000000' Minuend -1, aka -1.0b0 +0000000000000A38 BC800000 00000000 1189 DC X'BC80000000000000' Subtrahend 1.0b-55 + 1190 *..Above subtrahend is 2.77555756156289135105907917022705078125E-17 + 1191 *..nearest is away from zero, incremented. + 1192 * +0000000000000A40 3FF00000 00000000 1193 DC X'3FF0000000000000' Minuend +1, aka +1.0b0 +0000000000000A48 3CA80000 00000000 1194 DC X'3CA8000000000000' Subtrahend +1.1b-53 +0000000000000A50 BFF00000 00000000 1195 DC X'BFF0000000000000' Minuend -1, aka -1.0b0 + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 33 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000A58 BCA80000 00000000 1196 DC X'BCA8000000000000' Subtrahend -1.1b-53 + 1197 *..Above subtrahend is 1.66533453693773481063544750213623046875E-16 + 1198 *..nearest is a tie, nearest even has lower magnitude + 1199 * +0000000000000A60 3FF00000 00000000 1200 DC X'3FF0000000000000' Minuend +1, aka +1.0b0 +0000000000000A68 3C900000 00000000 1201 DC X'3C90000000000000' Subtrahend +1.0b-54 +0000000000000A70 BFF00000 00000000 1202 DC X'BFF0000000000000' Minuend -1, aka -1.0b0 +0000000000000A78 BC900000 00000000 1203 DC X'BC90000000000000' Subtrahend -1.0b-54 + 1204 *..Above subtrahend is 5.5511151231257827021181583404541015625E-17 + 1205 *..nearest is a tie, nearest even has greater magnitude + 1206 * + 0000000000000008 0000000000000001 1207 LBFPRMCT EQU (*-LBFPINRM)/8/2 Count of long BFP rounding tests + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 34 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1209 *********************************************************************** + 1210 * + 1211 * Extended BFP test data sets for Add testing. + 1212 * + 1213 * The first test data set is used for tests of basic functionality, + 1214 * NaN propagation, and results from operations involving other than + 1215 * finite numbers. + 1216 * + 1217 * The second test data set is used for testing boundary conditions + 1218 * using two finite non-zero values. Each possible condition code + 1219 * and type of result (normal, scaled, etc) is created by members of + 1220 * this test data set. + 1221 * + 1222 * The third test data set is used for exhaustive testing of final + 1223 * results across the five rounding modes available for the Add + 1224 * instruction. + 1225 * + 1226 *********************************************************************** + + + 1228 *********************************************************************** + 1229 * + 1230 * First input test data set, to test operations using non-finite or + 1231 * zero inputs. Member values chosen to validate Figure 19-13 on page + 1232 * 19-16 of SA22-7832-10. Each value in this table is tested against + 1233 * every other value in the table. Ten entries means 100 result sets. + 1234 * + 1235 *********************************************************************** + + +0000000000000A80 1237 XBFPNFIN DS 0F Inputs for extended BFP testing +0000000000000A80 FFFF0000 00000000 1238 DC X'FFFF0000000000000000000000000000' -inf +0000000000000A90 C0000000 00000000 1239 DC X'C0000000000000000000000000000000' -2.0 +0000000000000AA0 80001000 00000000 1240 DC X'80001000000000000000000000000000' -Dnice +0000000000000AB0 80000000 00000000 1241 DC X'80000000000000000000000000000000' -0 +0000000000000AC0 00000000 00000000 1242 DC X'00000000000000000000000000000000' +0 +0000000000000AD0 00001000 00000000 1243 DC X'00001000000000000000000000000000' +Dnice +0000000000000AE0 40000000 00000000 1244 DC X'40000000000000000000000000000000' +2.0 +0000000000000AF0 7FFF0000 00000000 1245 DC X'7FFF0000000000000000000000000000' +inf +0000000000000B00 FFFF8B00 00000000 1246 DC X'FFFF8B00000000000000000000000000' -QNaN +0000000000000B10 7FFF0A00 00000000 1247 DC X'7FFF0A00000000000000000000000000' +SNaN + 000000000000000A 0000000000000001 1248 XBFPNFCT EQU (*-XBFPNFIN)/16 Count of extended BFP in list + + + + 1250 *********************************************************************** + 1251 * + 1252 * Second input test data set. These are finite pairs intended to + 1253 * trigger overflow, underflow, and inexact exceptions. Each pair is + 1254 * added twice, once non-trappable and once trappable. Trappable + 1255 * overflow or underflow yields a scaled result. Trappable inexact + 1256 * will show whether the Incremented DXC code is returned. + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 35 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1257 * + 1258 * The following test cases are required: + 1259 * The following test cases are required: + 1260 * 1. Overflow + 1261 * 2. Underflow - normal inputs + 1262 * 3. Underflow - subnormal inputs + 1263 * 4. Normal - from subnormal inputs + 1264 * 5. Inexact - incremented + 1265 * 6. Inexact - truncated + 1266 * + 1267 *********************************************************************** + + +0000000000000B20 1269 XBFPIN DS 0F Inputs for extended BFP finite tests + 1270 * + 1271 * Overflow on subtraction + 1272 * +0000000000000B20 7FFFFFFF FFFFFFFF 1273 DC X'7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF' +Nmax +0000000000000B30 FFFFFFFF FFFFFFFF 1274 DC X'FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF' +Nmax + 1275 * + 1276 * Underflow from difference of normals. We will subtract a small + 1277 * normal from a slightly larger normal to generate a subnormal. + 1278 * +0000000000000B40 0001FFFF FFFFFFFF 1279 DC X'0001FFFFFFFFFFFFFFFFFFFFFFFFFFFF' Very small normal +0000000000000B50 00010000 00000000 1280 DC X'00010000000000000000000000000000' Smaller normal + 1281 * + 1282 * Underflow from difference of subnormals. + 1283 * +0000000000000B60 00008000 00000000 1284 DC X'00008000000000000000000000000000' Subnormal, < +Dmax +0000000000000B70 00000F0F 00000000 1285 DC X'00000F0F000000000000000000000000' Smaller subnormal + 1286 * + 1287 * Normal result from difference of subnormals. + 1288 * The result will be greater than +Nmin + 1289 * +0000000000000B80 0000FFFF FFFFFFFF 1290 DC X'0000FFFFFFFFFFFFFFFFFFFFFFFFFFFF' +Dmax +0000000000000B90 80000000 00000000 1291 DC X'80000000000000000000000000000001' -Dmin + 1292 * ...result will be +Nmin + 1293 * + 1294 * Subtract a value from 1.0 such that the added digits are to the right + 1295 * of the right-most bit in the stored significand. The result will be + 1296 * inexact, and incremented will be determined by the value of the + 1297 * bits in the subtrahend. + 1298 * +0000000000000BA0 3FFF0000 00000000 1299 DC X'3FFF0000000000000000000000000000' +1, aka 1.0b0 +0000000000000BB0 3F8C0000 00000000 1300 DC X'3F8C0000000000000000000000000000' 1.0b-115 + 1301 *..Above subtrahend is 2.407412430484044816319972428231159148172627... + 1302 * ...06026923524404992349445819854736328125E-35 + 1303 *..nearest is away from zero, incremented. + 1304 * +0000000000000BC0 3FFF0000 00000000 1305 DC X'3FFF0000000000000000000000000000' +1, aka 1.0b0 +0000000000000BD0 3F8D2000 00000000 1306 DC X'3F8D2000000000000000000000000000' 1.001b-114 + 1307 *..Above subtrahend is 5.416677968589100836719937963520108083388410... + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 36 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1308 * ...8856057792991123278625309467315673828125E-35 + 1309 *..nearest is toward zero, truncated + 1310 * + 0000000000000006 0000000000000001 1311 XBFPCT EQU (*-XBFPIN)/16/2 Count of extended BFP in list + + + + 1313 *********************************************************************** + 1314 * + 1315 * Third input test data set. These are finite pairs intended to + 1316 * test all combinations of rounding mode for the difference and the + 1317 * remainder. Values are chosen to create a requirement to round + 1318 * to the target precision after the computation and to generate + 1319 * varying results depending on the rounding mode in the FPCR. + 1320 * + 1321 * The result set will have cases that represent each of the following + 1322 * + 1323 * 1. Positive, nearest magnitude is toward zero. + 1324 * 2. Negative, nearest magnitude is toward zero. + 1325 * 3. Positive, nearest magnitude is away from zero. + 1326 * 4. Negative, nearest magnitude is away from zero. + 1327 * 5. Positive, tie, nearest even has greater magnitude + 1328 * 6. Negative, tie, nearest even has greater magnitude + 1329 * 7. Positive, tie, nearest even has lower magnitude + 1330 * 8. Negative, tie, nearest even has lower magnitude + 1331 * + 1332 * Round For Shorter precision correctness can be determined from the + 1333 * above test cases. + 1334 * + 1335 *********************************************************************** + + +0000000000000BE0 1337 XBFPINRM DS 0D + 1338 * + 1339 * Subtract a value from 1.0 such that the added digits are to the right + 1340 * of the right-most bit in the stored significand. The result will be + 1341 * inexact, and incremented will be determined by the value of the + 1342 * bits in the subtrahend. + 1343 * +0000000000000BE0 3FFF0000 00000000 1344 DC X'3FFF0000000000000000000000000000' +1, aka +1.0b0 +0000000000000BF0 3F8D2000 00000000 1345 DC X'3F8D2000000000000000000000000000' 1.001b-114 +0000000000000C00 BFFF0000 00000000 1346 DC X'BFFF0000000000000000000000000000' -1, aka -1.0b0 +0000000000000C10 BF8D2000 00000000 1347 DC X'BF8D2000000000000000000000000000' 1.001b-114 + 1348 *..Above subtrahend is 5.416677968589100836719937963520108083388410... + 1349 * ...8856057792991123278625309467315673828125E-35 + 1350 *..nearest is toward zero + 1351 * +0000000000000C20 3FFF0000 00000000 1352 DC X'3FFF0000000000000000000000000000' +1, aka +1.0b0 +0000000000000C30 3F8C0000 00000000 1353 DC X'3F8C0000000000000000000000000000' 1.0b-115 +0000000000000C40 BFFF0000 00000000 1354 DC X'BFFF0000000000000000000000000000' -1, aka -1.0b0 +0000000000000C50 BF8C0000 00000000 1355 DC X'BF8C0000000000000000000000000000' 1.0b-115 + 1356 *..Above subtrahend is 2.407412430484044816319972428231159148172627... + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 37 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1357 * ...06026923524404992349445819854736328125E-35 + 1358 *..nearest is away from zero + 1359 * +0000000000000C60 3FFF0000 00000000 1360 DC X'3FFF0000000000000000000000000000' +1, aka +1.0b0 +0000000000000C70 3F8E8000 00000000 1361 DC X'3F8E8000000000000000000000000000' +1.1b-113 +0000000000000C80 BFFF0000 00000000 1362 DC X'BFFF0000000000000000000000000000' -1, aka -1.0b0 +0000000000000C90 BF8E8000 00000000 1363 DC X'BF8E8000000000000000000000000000' -1.0b-114 + 1364 *..Above subtrahend is 1.444447458290426889791983456938695488903576... + 1365 * ...23616154114642995409667491912841796875E-34 + 1366 *..nearest is a tie, nearest even has lower magnitude + 1367 * +0000000000000CA0 3FFF0000 00000000 1368 DC X'3FFF0000000000000000000000000000' +1, aka +1.0b0 +0000000000000CB0 3F8D0000 00000000 1369 DC X'3F8D0000000000000000000000000000' +1.0b-114 +0000000000000CC0 BFFF0000 00000000 1370 DC X'BFFF0000000000000000000000000000' -1, aka -1.0b0 +0000000000000CD0 BF8D0000 00000000 1371 DC X'BF8D0000000000000000000000000000' -1.0b-114 + 1372 *..Above subtrahend is 4.814824860968089632639944856462318296345254... + 1373 * ...1205384704880998469889163970947265625E-35 + 1374 *..nearest is a tie, nearest even has greater magnitude + 1375 * + 0000000000000008 0000000000000001 1376 XBFPRMCT EQU (*-XBFPINRM)/16/2 Count of long BFP rounding tests + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 38 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1378 * + 1379 * Locations for results + 1380 * + 0000000000001000 0000000000000001 1381 SBFPNFOT EQU STRTLABL+X'1000' Short non-finite BFP results + 1382 * ..room for 110 tests, 100 used + 0000000000001700 0000000000000001 1383 SBFPNFFL EQU STRTLABL+X'1700' FPCR flags and DXC from short BFP + 1384 * ..room for 110 tests, 100 used + 1385 * + 0000000000001E00 0000000000000001 1386 SBFPOUT EQU STRTLABL+X'1E00' Short BFP finite results + 1387 * ..room for 16 tests, 6 used + 0000000000001F00 0000000000000001 1388 SBFPFLGS EQU STRTLABL+X'1F00' FPCR flags and DXC from short BFP + 1389 * ..room for 16 tests, 6 used + 1390 * + 0000000000002000 0000000000000001 1391 SBFPRMO EQU STRTLABL+X'2000' Short BFP rounding mode test results + 1392 * ..Room for 16, 8 used. + 0000000000002300 0000000000000001 1393 SBFPRMOF EQU STRTLABL+X'2300' Short BFP rounding mode FPCR results + 1394 * ..Room for 16, 8 used. + 1395 * ..next location starts at X'2500' + 1396 * + 0000000000004000 0000000000000001 1397 LBFPNFOT EQU STRTLABL+X'4000' Long non-finite BFP results + 1398 * ..room for 100 tests, 100 used + 0000000000004D00 0000000000000001 1399 LBFPNFFL EQU STRTLABL+X'4D00' FPCR flags and DXC from long BFP + 1400 * ..room for 100 tests, 100 used + 1401 * + 0000000000005400 0000000000000001 1402 LBFPOUT EQU STRTLABL+X'5400' Long BFP finite results + 1403 * ..room for 16 tests, 6 used + 0000000000005600 0000000000000001 1404 LBFPFLGS EQU STRTLABL+X'5600' FPCR flags and DXC from long BFP + 1405 * ..room for 16 tests, 6 used + 1406 * + 0000000000005700 0000000000000001 1407 LBFPRMO EQU STRTLABL+X'5700' Long BFP rounding mode test results + 1408 * ..Room for 16, 8 used. + 0000000000005C00 0000000000000001 1409 LBFPRMOF EQU STRTLABL+X'5C00' Long BFP rounding mode FPCR results + 1410 * ..Room for 16, 8 used. + 1411 * ..next location starts at X'5E00' + 1412 * + 0000000000008000 0000000000000001 1413 XBFPNFOT EQU STRTLABL+X'8000' Extended non-finite BFP results + 1414 * ..room for 100 tests, 100 used + 0000000000008D00 0000000000000001 1415 XBFPNFFL EQU STRTLABL+X'8D00' FPCR flags and DXC from ext'd BFP + 1416 * ..room for 100 tests, 100 used + 1417 * + 0000000000009400 0000000000000001 1418 XBFPOUT EQU STRTLABL+X'9400' Extended BFP finite results + 1419 * ..room for 16 tests, 6 used + 0000000000009600 0000000000000001 1420 XBFPFLGS EQU STRTLABL+X'9600' FPCR flags and DXC from ext'd BFP + 1421 * ..room for 16 tests, 6 used + 1422 * + 0000000000009700 0000000000000001 1423 XBFPRMO EQU STRTLABL+X'9700' Ext'd BFP rounding mode test results + 1424 * ..Room for 16, 8 used. + 0000000000009C00 0000000000000001 1425 XBFPRMOF EQU STRTLABL+X'9C00' Ext'd BFP rounding mode FPCR results + 1426 * ..Room for 16, 8 used. + 1427 * ..next location starts at X'9E00' + 1428 * + 0000000000009E00 0000000000000001 1429 ENDLABL EQU STRTLABL+X'9E00' + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 39 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1430 PADCSECT ENDLABL + 1431+ MNOTE *,'asma detected; no CSECT padding performed' +0000000000000CE0 1432 END + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 40 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +BFPSUBTR J 000000 3296 77 +CTLR0 F 000290 4 193 160 161 162 +ENDLABL U 009E00 1 1429 +FPCMCT U 000005 1 884 428 639 826 +FPCMODES C 0008B0 1 878 884 431 642 829 +FPCREGNT X 000294 4 194 293 313 360 380 433 444 505 524 571 591 644 655 717 770 + 831 +FPCREGTR X 000298 4 195 303 322 370 389 515 533 581 600 730 783 +FPR0 U 000000 1 98 +FPR1 U 000001 1 99 292 294 302 304 312 362 363 373 436 437 504 506 514 516 + 573 574 584 647 648 715 718 728 731 773 775 787 835 837 +FPR10 U 00000A 1 108 714 720 +FPR11 U 00000B 1 109 +FPR12 U 00000C 1 110 +FPR13 U 00000D 1 111 726 731 732 771 775 776 784 787 788 833 837 838 +FPR14 U 00000E 1 112 +FPR15 U 00000F 1 113 727 733 772 777 785 789 834 839 +FPR2 U 000002 1 100 +FPR3 U 000003 1 101 716 729 774 836 +FPR4 U 000004 1 102 +FPR5 U 000005 1 103 +FPR6 U 000006 1 104 +FPR7 U 000007 1 105 +FPR8 U 000008 1 106 291 294 295 301 304 305 311 314 315 321 323 324 361 363 + 364 371 373 374 381 382 383 390 391 392 435 437 438 446 + 447 448 503 506 507 513 516 517 523 525 526 532 534 535 + 572 574 575 582 584 585 592 593 594 601 602 603 646 648 + 649 657 658 659 713 718 719 +FPR9 U 000009 1 107 +HARDWAIT X 000280 8 191 151 +IMAGE 1 000000 3296 0 +LBFPCT U 000006 1 1146 229 +LBFPF I 000628 4 565 174 +LBFPFLGS U 005600 1 1404 232 +LBFPIN D 0009A0 8 1107 1146 230 +LBFPINRM F 000A00 4 1172 1207 236 +LBFPNF H 000572 2 492 172 +LBFPNFCT U 00000A 1 1087 223 +LBFPNFFL U 004D00 1 1399 226 +LBFPNFIN F 000950 4 1076 1087 224 +LBFPNFOT U 004000 1 1397 225 +LBFPOUT U 005400 1 1402 231 +LBFPRM I 0006CE 4 632 176 +LBFPRMCT U 000008 1 1207 235 +LBFPRMO U 005700 1 1407 237 +LBFPRMOF U 005C00 1 1409 238 +LONGF F 000340 4 228 173 +LONGNF F 000330 4 222 171 +PCINTCD H 00008E 2 128 145 +PCNOTDTA H 00020C 2 148 146 +PCOLDPSW U 000150 1 130 147 +PROGCHK H 000200 2 144 136 + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 41 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +R0 U 000000 1 79 160 162 297 298 299 307 308 309 317 318 319 326 327 328 + 366 367 368 376 377 378 385 386 387 394 395 396 440 441 + 442 450 451 452 509 510 511 519 520 521 528 529 530 537 + 538 539 577 578 579 587 588 589 596 597 598 605 606 607 + 651 652 653 661 662 663 722 723 724 735 736 737 779 780 + 781 791 792 793 841 842 843 +R1 U 000001 1 80 425 431 434 445 636 642 645 656 823 829 832 +R10 U 00000A 1 89 164 166 168 171 173 175 178 180 182 281 282 287 354 355 + 421 422 493 494 499 565 566 632 633 703 704 709 764 765 + 819 820 +R11 U 00000B 1 90 +R12 U 00000C 1 91 285 336 358 401 426 467 497 547 569 612 637 677 707 745 + 768 798 824 857 +R13 U 00000D 1 92 165 167 169 172 174 176 179 181 183 284 337 357 402 424 + 469 496 548 568 613 635 679 706 746 767 800 822 859 +R14 U 00000E 1 93 149 150 185 186 +R15 U 00000F 1 94 115 +R2 U 000002 1 81 281 283 336 354 356 401 421 423 467 493 495 547 565 567 + 612 632 634 677 703 705 745 764 766 798 819 821 857 +R3 U 000003 1 82 281 291 301 311 321 335 354 361 362 371 381 382 390 391 + 398 421 435 436 446 447 464 493 503 513 523 532 546 565 + 572 573 582 592 593 601 602 609 632 646 647 657 658 675 + 703 713 714 726 727 744 764 771 772 773 774 784 785 795 + 819 833 834 835 836 855 +R4 U 000004 1 83 287 333 499 544 709 742 +R5 U 000005 1 84 287 292 302 312 314 323 330 428 431 457 499 504 514 525 + 534 541 639 642 668 709 715 716 728 729 739 826 829 848 +R6 U 000006 1 85 289 333 501 544 711 742 +R7 U 000007 1 86 282 295 305 315 324 331 355 364 374 383 392 399 422 438 + 448 454 465 494 507 517 526 535 542 566 575 585 594 603 + 610 633 649 659 665 704 719 720 732 733 740 765 776 777 + 788 789 796 820 838 839 845 +R8 U 000008 1 87 282 296 299 306 309 316 319 325 328 332 355 365 368 375 + 378 384 387 393 396 400 422 439 442 449 452 455 466 494 + 508 511 518 521 527 530 536 539 543 566 576 579 586 589 + 595 598 604 607 611 633 650 653 660 663 666 676 704 721 + 724 734 737 741 765 778 781 790 793 797 820 840 843 846 + 856 +R9 U 000009 1 88 429 457 640 668 827 848 +RMLONGS F 000350 4 234 175 +RMSHORTS F 000320 4 216 168 +RMXTNDS F 000380 4 252 182 +SBFPCT U 000006 1 985 211 +SBFPF I 00044A 4 354 167 +SBFPFLGS U 001F00 1 1388 214 +SBFPIN F 0008E0 4 946 985 212 +SBFPINRM F 000910 4 1011 1046 218 +SBFPNF H 000390 2 280 165 +SBFPNFCT U 00000A 1 926 205 +SBFPNFFL U 001700 1 1383 208 +SBFPNFIN F 0008B8 4 915 926 206 +SBFPNFOT U 001000 1 1381 207 + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 42 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +SBFPOUT U 001E00 1 1386 213 +SBFPRM I 0004F0 4 421 169 +SBFPRMCT U 000008 1 1046 217 +SBFPRMO U 002000 1 1391 219 +SBFPRMOF U 002300 1 1393 220 +SHORTF F 000310 4 210 166 +SHORTNF F 000300 4 204 164 +START H 000214 2 159 133 +STRTLABL U 000000 1 78 127 130 132 135 143 203 1381 1383 1386 1388 1391 1393 1397 1399 + 1402 1404 1407 1409 1413 1415 1418 1420 1423 1425 1429 +WAITPSW X 000270 8 190 187 +XBFPCT U 000006 1 1311 247 +XBFPF I 0007D6 4 764 181 +XBFPFLGS U 009600 1 1420 250 +XBFPIN F 000B20 4 1269 1311 248 +XBFPINRM D 000BE0 8 1337 1376 254 +XBFPNF H 00074C 2 702 179 +XBFPNFCT U 00000A 1 1248 241 +XBFPNFFL U 008D00 1 1415 244 +XBFPNFIN F 000A80 4 1237 1248 242 +XBFPNFOT U 008000 1 1413 243 +XBFPOUT U 009400 1 1418 249 +XBFPRM I 00084C 4 819 183 +XBFPRMCT U 000008 1 1376 253 +XBFPRMO U 009700 1 1423 255 +XBFPRMOF U 009C00 1 1425 256 +XTNDF F 000370 4 246 180 +XTNDNF F 000360 4 240 178 + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 43 + + MACRO DEFN REFERENCES + +PADCSECT 52 1430 + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 44 + + DESC SYMBOL SIZE POS ADDR + +Entry: 0 + +Image IMAGE 3296 000-CDF 000-CDF + Region 3296 000-CDF 000-CDF + CSECT BFPSUBTR 3296 000-CDF 000-CDF + ASMA Ver. 0.2.0 bfp-018-subtract.asm: Test IEEE Subtract 05 Oct 2016 08:34:44 Page 45 + + STMT FILE NAME + +1 C:\Users\srorso\Documents\GitHub\hyperion\tests\bfp-018-subtract.asm + + +** NO ERRORS FOUND ** + +[1431] MNOTE *,asma detected; no CSECT padding performed + \ No newline at end of file diff --git a/tests/bfp-018-subtract.tst b/tests/bfp-018-subtract.tst new file mode 100644 index 000000000..7ff495757 --- /dev/null +++ b/tests/bfp-018-subtract.tst @@ -0,0 +1,2133 @@ +*Testcase bfp-018-subtract.tst: SEBR, SEB, SDBR, SDB, SXBR + +#Testcase bfp-016-add.tst: Subtraction tests SUBTRACT (5) +#..Test cases evaluate NaN propagation, NaN generation, operations +#..using non-finite values, trappable and non-trappable IEEE +#..exceptions, result scaling, and exhaustive rounding testing. + +sysclear +archmode esame + +# +# Following suppresses logging of program checks. This test program, as part +# of its normal operation, generates 230 program check messages that have no +# value in the validation process. (The messages, not the program checks.) +# +ostailor quiet + +loadcore "$(testpath)/bfp-018-subtract.core" + +runtest 1.0 + +ostailor null # restore messages for subsequent tests + + +# Short BFP non-finite test results +*Compare +r 1000.10 +*Want "SEBR/SEB NF -inf/-inf" 7FC00000 FF800000 7FC00000 FF800000 +r 1010.10 +*Want "SEBR/SEB NF -inf/-2.0" FF800000 FF800000 FF800000 FF800000 +r 1020.10 +*Want "SEBR/SEB NF -inf/-Dnice" FF800000 FF800000 FF800000 FF800000 +r 1030.10 +*Want "SEBR/SEB NF -inf/-0" FF800000 FF800000 FF800000 FF800000 +r 1040.10 +*Want "SEBR/SEB NF -inf/+0" FF800000 FF800000 FF800000 FF800000 +r 1050.10 +*Want "SEBR/SEB NF -inf/+Dnice" FF800000 FF800000 FF800000 FF800000 +r 1060.10 +*Want "SEBR/SEB NF -inf/+2.0" FF800000 FF800000 FF800000 FF800000 +r 1070.10 +*Want "SEBR/SEB NF -inf/+inf" FF800000 FF800000 FF800000 FF800000 +r 1080.10 +*Want "SEBR/SEB NF -inf/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1090.10 +*Want "SEBR/SEB NF -inf/+SNaN" 7FCA0000 FF800000 7FCA0000 FF800000 +r 10A0.10 +*Want "SEBR/SEB NF -2.0/-inf" 7F800000 7F800000 7F800000 7F800000 +r 10B0.10 +*Want "SEBR/SEB NF -2.0/-2.0" 00000000 00000000 00000000 00000000 +r 10C0.10 +*Want "SEBR/SEB NF -2.0/-Dnice" C0000000 C0000000 C0000000 C0000000 +r 10D0.10 +*Want "SEBR/SEB NF -2.0/-0" C0000000 C0000000 C0000000 C0000000 +r 10E0.10 +*Want "SEBR/SEB NF -2.0/+0" C0000000 C0000000 C0000000 C0000000 +r 10F0.10 +*Want "SEBR/SEB NF -2.0/+Dnice" C0000000 C0000000 C0000000 C0000000 +r 1100.10 +*Want "SEBR/SEB NF -2.0/+2.0" C0800000 C0800000 C0800000 C0800000 +r 1110.10 +*Want "SEBR/SEB NF -2.0/+inf" FF800000 FF800000 FF800000 FF800000 +r 1120.10 +*Want "SEBR/SEB NF -2.0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1130.10 +*Want "SEBR/SEB NF -2.0/+SNaN" 7FCA0000 C0000000 7FCA0000 C0000000 +r 1140.10 +*Want "SEBR/SEB NF -Dnice/-inf" 7F800000 7F800000 7F800000 7F800000 +r 1150.10 +*Want "SEBR/SEB NF -Dnice/-2.0" 40000000 40000000 40000000 40000000 +r 1160.10 +*Want "SEBR/SEB NF -Dnice/-Dnice" 00000000 00000000 00000000 00000000 +r 1170.10 +*Want "SEBR/SEB NF -Dnice/-0" 80010000 DD000000 80010000 DD000000 +r 1180.10 +*Want "SEBR/SEB NF -Dnice/+0" 80010000 DD000000 80010000 DD000000 +r 1190.10 +*Want "SEBR/SEB NF -Dnice/+Dnice" 80020000 DD800000 80020000 DD800000 +r 11A0.10 +*Want "SEBR/SEB NF -Dnice/+2.0" C0000000 C0000000 C0000000 C0000000 +r 11B0.10 +*Want "SEBR/SEB NF -Dnice/+inf" FF800000 FF800000 FF800000 FF800000 +r 11C0.10 +*Want "SEBR/SEB NF -Dnice/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 11D0.10 +*Want "SEBR/SEB NF -Dnice/+SNaN" 7FCA0000 80010000 7FCA0000 80010000 +r 11E0.10 +*Want "SEBR/SEB NF -0/-inf" 7F800000 7F800000 7F800000 7F800000 +r 11F0.10 +*Want "SEBR/SEB NF -0/-2.0" 40000000 40000000 40000000 40000000 +r 1200.10 +*Want "SEBR/SEB NF -0/-Dnice" 00010000 5D000000 00010000 5D000000 +r 1210.10 +*Want "SEBR/SEB NF -0/-0" 00000000 00000000 00000000 00000000 +r 1220.10 +*Want "SEBR/SEB NF -0/+0" 80000000 80000000 80000000 80000000 +r 1230.10 +*Want "SEBR/SEB NF -0/+Dnice" 80010000 DD000000 80010000 DD000000 +r 1240.10 +*Want "SEBR/SEB NF -0/+2.0" C0000000 C0000000 C0000000 C0000000 +r 1250.10 +*Want "SEBR/SEB NF -0/+inf" FF800000 FF800000 FF800000 FF800000 +r 1260.10 +*Want "SEBR/SEB NF -0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1270.10 +*Want "SEBR/SEB NF -0/+SNaN" 7FCA0000 80000000 7FCA0000 80000000 +r 1280.10 +*Want "SEBR/SEB NF +0/-inf" 7F800000 7F800000 7F800000 7F800000 +r 1290.10 +*Want "SEBR/SEB NF +0/-2.0" 40000000 40000000 40000000 40000000 +r 12A0.10 +*Want "SEBR/SEB NF +0/-Dnice" 00010000 5D000000 00010000 5D000000 +r 12B0.10 +*Want "SEBR/SEB NF +0/-0" 00000000 00000000 00000000 00000000 +r 12C0.10 +*Want "SEBR/SEB NF +0/+0" 00000000 00000000 00000000 00000000 +r 12D0.10 +*Want "SEBR/SEB NF +0/+Dnice" 80010000 DD000000 80010000 DD000000 +r 12E0.10 +*Want "SEBR/SEB NF +0/+2.0" C0000000 C0000000 C0000000 C0000000 +r 12F0.10 +*Want "SEBR/SEB NF +0/+inf" FF800000 FF800000 FF800000 FF800000 +r 1300.10 +*Want "SEBR/SEB NF +0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1310.10 +*Want "SEBR/SEB NF +0/+SNaN" 7FCA0000 00000000 7FCA0000 00000000 +r 1320.10 +*Want "SEBR/SEB NF +Dnice/-inf" 7F800000 7F800000 7F800000 7F800000 +r 1330.10 +*Want "SEBR/SEB NF +Dnice/-2.0" 40000000 40000000 40000000 40000000 +r 1340.10 +*Want "SEBR/SEB NF +Dnice/-Dnice" 00020000 5D800000 00020000 5D800000 +r 1350.10 +*Want "SEBR/SEB NF +Dnice/-0" 00010000 5D000000 00010000 5D000000 +r 1360.10 +*Want "SEBR/SEB NF +Dnice/+0" 00010000 5D000000 00010000 5D000000 +r 1370.10 +*Want "SEBR/SEB NF +Dnice/+Dnice" 00000000 00000000 00000000 00000000 +r 1380.10 +*Want "SEBR/SEB NF +Dnice/+2.0" C0000000 C0000000 C0000000 C0000000 +r 1390.10 +*Want "SEBR/SEB NF +Dnice/+inf" FF800000 FF800000 FF800000 FF800000 +r 13A0.10 +*Want "SEBR/SEB NF +Dnice/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 13B0.10 +*Want "SEBR/SEB NF +Dnice/+SNaN" 7FCA0000 00010000 7FCA0000 00010000 +r 13C0.10 +*Want "SEBR/SEB NF +2.0/-inf" 7F800000 7F800000 7F800000 7F800000 +r 13D0.10 +*Want "SEBR/SEB NF +2.0/-2.0" 40800000 40800000 40800000 40800000 +r 13E0.10 +*Want "SEBR/SEB NF +2.0/-Dnice" 40000000 40000000 40000000 40000000 +r 13F0.10 +*Want "SEBR/SEB NF +2.0/-0" 40000000 40000000 40000000 40000000 +r 1400.10 +*Want "SEBR/SEB NF +2.0/+0" 40000000 40000000 40000000 40000000 +r 1410.10 +*Want "SEBR/SEB NF +2.0/+Dnice" 40000000 40000000 40000000 40000000 +r 1420.10 +*Want "SEBR/SEB NF +2.0/+2.0" 00000000 00000000 00000000 00000000 +r 1430.10 +*Want "SEBR/SEB NF +2.0/+inf" FF800000 FF800000 FF800000 FF800000 +r 1440.10 +*Want "SEBR/SEB NF +2.0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1450.10 +*Want "SEBR/SEB NF +2.0/+SNaN" 7FCA0000 40000000 7FCA0000 40000000 +r 1460.10 +*Want "SEBR/SEB NF +inf/-inf" 7F800000 7F800000 7F800000 7F800000 +r 1470.10 +*Want "SEBR/SEB NF +inf/-2.0" 7F800000 7F800000 7F800000 7F800000 +r 1480.10 +*Want "SEBR/SEB NF +inf/-Dnice" 7F800000 7F800000 7F800000 7F800000 +r 1490.10 +*Want "SEBR/SEB NF +inf/-0" 7F800000 7F800000 7F800000 7F800000 +r 14A0.10 +*Want "SEBR/SEB NF +inf/+0" 7F800000 7F800000 7F800000 7F800000 +r 14B0.10 +*Want "SEBR/SEB NF +inf/+Dnice" 7F800000 7F800000 7F800000 7F800000 +r 14C0.10 +*Want "SEBR/SEB NF +inf/+2.0" 7F800000 7F800000 7F800000 7F800000 +r 14D0.10 +*Want "SEBR/SEB NF +inf/+inf" 7FC00000 7F800000 7FC00000 7F800000 +r 14E0.10 +*Want "SEBR/SEB NF +inf/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 14F0.10 +*Want "SEBR/SEB NF +inf/+SNaN" 7FCA0000 7F800000 7FCA0000 7F800000 +r 1500.10 +*Want "SEBR/SEB NF -QNaN/-inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1510.10 +*Want "SEBR/SEB NF -QNaN/-2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1520.10 +*Want "SEBR/SEB NF -QNaN/-Dnice" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1530.10 +*Want "SEBR/SEB NF -QNaN/-0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1540.10 +*Want "SEBR/SEB NF -QNaN/+0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1550.10 +*Want "SEBR/SEB NF -QNaN/+Dnice" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1560.10 +*Want "SEBR/SEB NF -QNaN/+2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1570.10 +*Want "SEBR/SEB NF -QNaN/+inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1580.10 +*Want "SEBR/SEB NF -QNaN/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1590.10 +*Want "SEBR/SEB NF -QNaN/+SNaN" 7FCA0000 FFCB0000 7FCA0000 FFCB0000 +r 15A0.10 +*Want "SEBR/SEB NF +SNaN/-inf" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 15B0.10 +*Want "SEBR/SEB NF +SNaN/-2.0" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 15C0.10 +*Want "SEBR/SEB NF +SNaN/-Dnice" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 15D0.10 +*Want "SEBR/SEB NF +SNaN/-0" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 15E0.10 +*Want "SEBR/SEB NF +SNaN/+0" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 15F0.10 +*Want "SEBR/SEB NF +SNaN/+Dnice" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1600.10 +*Want "SEBR/SEB NF +SNaN/+2.0" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1610.10 +*Want "SEBR/SEB NF +SNaN/+inf" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1620.10 +*Want "SEBR/SEB NF +SNaN/-QNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1630.10 +*Want "SEBR/SEB NF +SNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 + + +# Short BFP non-finite test results - FPCR +*Compare +r 1700.10 +*Want "SEBR/SEB NF -inf/-inf FPCR" 00800003 F8008003 00800003 F8008003 +r 1710.10 +*Want "SEBR/SEB NF -inf/-2.0 FPCR" 00000001 F8000001 00000001 F8000001 +r 1720.10 +*Want "SEBR/SEB NF -inf/-Dnice FPCR" 00000001 F8000001 00000001 F8000001 +r 1730.10 +*Want "SEBR/SEB NF -inf/-0 FPCR" 00000001 F8000001 00000001 F8000001 +r 1740.10 +*Want "SEBR/SEB NF -inf/+0 FPCR" 00000001 F8000001 00000001 F8000001 +r 1750.10 +*Want "SEBR/SEB NF -inf/+Dnice FPCR" 00000001 F8000001 00000001 F8000001 +r 1760.10 +*Want "SEBR/SEB NF -inf/+2.0 FPCR" 00000001 F8000001 00000001 F8000001 +r 1770.10 +*Want "SEBR/SEB NF -inf/+inf FPCR" 00000001 F8000001 00000001 F8000001 +r 1780.10 +*Want "SEBR/SEB NF -inf/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 1790.10 +*Want "SEBR/SEB NF -inf/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 17A0.10 +*Want "SEBR/SEB NF -2.0/-inf FPCR" 00000002 F8000002 00000002 F8000002 +r 17B0.10 +*Want "SEBR/SEB NF -2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 17C0.10 +*Want "SEBR/SEB NF -2.0/-Dnice FPCR" 00080001 F8000C01 00080001 F8000C01 +r 17D0.10 +*Want "SEBR/SEB NF -2.0/-0 FPCR" 00000001 F8000001 00000001 F8000001 +r 17E0.10 +*Want "SEBR/SEB NF -2.0/+0 FPCR" 00000001 F8000001 00000001 F8000001 +r 17F0.10 +*Want "SEBR/SEB NF -2.0/+Dnice FPCR" 00080001 F8000801 00080001 F8000801 +r 1800.10 +*Want "SEBR/SEB NF -2.0/+2.0 FPCR" 00000001 F8000001 00000001 F8000001 +r 1810.10 +*Want "SEBR/SEB NF -2.0/+inf FPCR" 00000001 F8000001 00000001 F8000001 +r 1820.10 +*Want "SEBR/SEB NF -2.0/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 1830.10 +*Want "SEBR/SEB NF -2.0/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 1840.10 +*Want "SEBR/SEB NF -Dnice/-inf FPCR" 00000002 F8000002 00000002 F8000002 +r 1850.10 +*Want "SEBR/SEB NF -Dnice/-2.0 FPCR" 00080002 F8000C02 00080002 F8000C02 +r 1860.10 +*Want "SEBR/SEB NF -Dnice/-Dnice FPCR" 00000000 F8000000 00000000 F8000000 +r 1870.10 +*Want "SEBR/SEB NF -Dnice/-0 FPCR" 00000001 F8001001 00000001 F8001001 +r 1880.10 +*Want "SEBR/SEB NF -Dnice/+0 FPCR" 00000001 F8001001 00000001 F8001001 +r 1890.10 +*Want "SEBR/SEB NF -Dnice/+Dnice FPCR" 00000001 F8001001 00000001 F8001001 +r 18A0.10 +*Want "SEBR/SEB NF -Dnice/+2.0 FPCR" 00080001 F8000801 00080001 F8000801 +r 18B0.10 +*Want "SEBR/SEB NF -Dnice/+inf FPCR" 00000001 F8000001 00000001 F8000001 +r 18C0.10 +*Want "SEBR/SEB NF -Dnice/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 18D0.10 +*Want "SEBR/SEB NF -Dnice/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 18E0.10 +*Want "SEBR/SEB NF -0/-inf FPCR" 00000002 F8000002 00000002 F8000002 +r 18F0.10 +*Want "SEBR/SEB NF -0/-2.0 FPCR" 00000002 F8000002 00000002 F8000002 +r 1900.10 +*Want "SEBR/SEB NF -0/-Dnice FPCR" 00000002 F8001002 00000002 F8001002 +r 1910.10 +*Want "SEBR/SEB NF -0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1920.10 +*Want "SEBR/SEB NF -0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1930.10 +*Want "SEBR/SEB NF -0/+Dnice FPCR" 00000001 F8001001 00000001 F8001001 +r 1940.10 +*Want "SEBR/SEB NF -0/+2.0 FPCR" 00000001 F8000001 00000001 F8000001 +r 1950.10 +*Want "SEBR/SEB NF -0/+inf FPCR" 00000001 F8000001 00000001 F8000001 +r 1960.10 +*Want "SEBR/SEB NF -0/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 1970.10 +*Want "SEBR/SEB NF -0/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 1980.10 +*Want "SEBR/SEB NF +0/-inf FPCR" 00000002 F8000002 00000002 F8000002 +r 1990.10 +*Want "SEBR/SEB NF +0/-2.0 FPCR" 00000002 F8000002 00000002 F8000002 +r 19A0.10 +*Want "SEBR/SEB NF +0/-Dnice FPCR" 00000002 F8001002 00000002 F8001002 +r 19B0.10 +*Want "SEBR/SEB NF +0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 19C0.10 +*Want "SEBR/SEB NF +0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 19D0.10 +*Want "SEBR/SEB NF +0/+Dnice FPCR" 00000001 F8001001 00000001 F8001001 +r 19E0.10 +*Want "SEBR/SEB NF +0/+2.0 FPCR" 00000001 F8000001 00000001 F8000001 +r 19F0.10 +*Want "SEBR/SEB NF +0/+inf FPCR" 00000001 F8000001 00000001 F8000001 +r 1A00.10 +*Want "SEBR/SEB NF +0/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 1A10.10 +*Want "SEBR/SEB NF +0/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 1A20.10 +*Want "SEBR/SEB NF +Dnice/-inf FPCR" 00000002 F8000002 00000002 F8000002 +r 1A30.10 +*Want "SEBR/SEB NF +Dnice/-2.0 FPCR" 00080002 F8000802 00080002 F8000802 +r 1A40.10 +*Want "SEBR/SEB NF +Dnice/-Dnice FPCR" 00000002 F8001002 00000002 F8001002 +r 1A50.10 +*Want "SEBR/SEB NF +Dnice/-0 FPCR" 00000002 F8001002 00000002 F8001002 +r 1A60.10 +*Want "SEBR/SEB NF +Dnice/+0 FPCR" 00000002 F8001002 00000002 F8001002 +r 1A70.10 +*Want "SEBR/SEB NF +Dnice/+Dnice FPCR" 00000000 F8000000 00000000 F8000000 +r 1A80.10 +*Want "SEBR/SEB NF +Dnice/+2.0 FPCR" 00080001 F8000C01 00080001 F8000C01 +r 1A90.10 +*Want "SEBR/SEB NF +Dnice/+inf FPCR" 00000001 F8000001 00000001 F8000001 +r 1AA0.10 +*Want "SEBR/SEB NF +Dnice/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 1AB0.10 +*Want "SEBR/SEB NF +Dnice/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 1AC0.10 +*Want "SEBR/SEB NF +2.0/-inf FPCR" 00000002 F8000002 00000002 F8000002 +r 1AD0.10 +*Want "SEBR/SEB NF +2.0/-2.0 FPCR" 00000002 F8000002 00000002 F8000002 +r 1AE0.10 +*Want "SEBR/SEB NF +2.0/-Dnice FPCR" 00080002 F8000802 00080002 F8000802 +r 1AF0.10 +*Want "SEBR/SEB NF +2.0/-0 FPCR" 00000002 F8000002 00000002 F8000002 +r 1B00.10 +*Want "SEBR/SEB NF +2.0/+0 FPCR" 00000002 F8000002 00000002 F8000002 +r 1B10.10 +*Want "SEBR/SEB NF +2.0/+Dnice FPCR" 00080002 F8000C02 00080002 F8000C02 +r 1B20.10 +*Want "SEBR/SEB NF +2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1B30.10 +*Want "SEBR/SEB NF +2.0/+inf FPCR" 00000001 F8000001 00000001 F8000001 +r 1B40.10 +*Want "SEBR/SEB NF +2.0/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 1B50.10 +*Want "SEBR/SEB NF +2.0/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 1B60.10 +*Want "SEBR/SEB NF +inf/-inf FPCR" 00000002 F8000002 00000002 F8000002 +r 1B70.10 +*Want "SEBR/SEB NF +inf/-2.0 FPCR" 00000002 F8000002 00000002 F8000002 +r 1B80.10 +*Want "SEBR/SEB NF +inf/-Dnice FPCR" 00000002 F8000002 00000002 F8000002 +r 1B90.10 +*Want "SEBR/SEB NF +inf/-0 FPCR" 00000002 F8000002 00000002 F8000002 +r 1BA0.10 +*Want "SEBR/SEB NF +inf/+0 FPCR" 00000002 F8000002 00000002 F8000002 +r 1BB0.10 +*Want "SEBR/SEB NF +inf/+Dnice FPCR" 00000002 F8000002 00000002 F8000002 +r 1BC0.10 +*Want "SEBR/SEB NF +inf/+2.0 FPCR" 00000002 F8000002 00000002 F8000002 +r 1BD0.10 +*Want "SEBR/SEB NF +inf/+inf FPCR" 00800003 F8008003 00800003 F8008003 +r 1BE0.10 +*Want "SEBR/SEB NF +inf/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 1BF0.10 +*Want "SEBR/SEB NF +inf/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 1C00.10 +*Want "SEBR/SEB NF -QNaN/-inf FPCR" 00000003 F8000003 00000003 F8000003 +r 1C10.10 +*Want "SEBR/SEB NF -QNaN/-2.0 FPCR" 00000003 F8000003 00000003 F8000003 +r 1C20.10 +*Want "SEBR/SEB NF -QNaN/-Dnice FPCR" 00000003 F8000003 00000003 F8000003 +r 1C30.10 +*Want "SEBR/SEB NF -QNaN/-0 FPCR" 00000003 F8000003 00000003 F8000003 +r 1C40.10 +*Want "SEBR/SEB NF -QNaN/+0 FPCR" 00000003 F8000003 00000003 F8000003 +r 1C50.10 +*Want "SEBR/SEB NF -QNaN/+Dnice FPCR" 00000003 F8000003 00000003 F8000003 +r 1C60.10 +*Want "SEBR/SEB NF -QNaN/+2.0 FPCR" 00000003 F8000003 00000003 F8000003 +r 1C70.10 +*Want "SEBR/SEB NF -QNaN/+inf FPCR" 00000003 F8000003 00000003 F8000003 +r 1C80.10 +*Want "SEBR/SEB NF -QNaN/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 1C90.10 +*Want "SEBR/SEB NF -QNaN/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 1CA0.10 +*Want "SEBR/SEB NF +SNaN/-inf FPCR" 00800003 F8008003 00800003 F8008003 +r 1CB0.10 +*Want "SEBR/SEB NF +SNaN/-2.0 FPCR" 00800003 F8008003 00800003 F8008003 +r 1CC0.10 +*Want "SEBR/SEB NF +SNaN/-Dnice FPCR" 00800003 F8008003 00800003 F8008003 +r 1CD0.10 +*Want "SEBR/SEB NF +SNaN/-0 FPCR" 00800003 F8008003 00800003 F8008003 +r 1CE0.10 +*Want "SEBR/SEB NF +SNaN/+0 FPCR" 00800003 F8008003 00800003 F8008003 +r 1CF0.10 +*Want "SEBR/SEB NF +SNaN/+Dnice FPCR" 00800003 F8008003 00800003 F8008003 +r 1D00.10 +*Want "SEBR/SEB NF +SNaN/+2.0 FPCR" 00800003 F8008003 00800003 F8008003 +r 1D10.10 +*Want "SEBR/SEB NF +SNaN/+inf FPCR" 00800003 F8008003 00800003 F8008003 +r 1D20.10 +*Want "SEBR/SEB NF +SNaN/-QNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 1D30.10 +*Want "SEBR/SEB NF +SNaN/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 + + +# Short BFP finite test results +*Compare +r 1E00.10 +*Want "SEBR/SEB F Ovfl" 7F800000 1FFFFFFF 7F800000 1FFFFFFF +r 1E10.10 +*Want "SEBR/SEB F Ufl 1" 007FFFFF 607FFFFE 007FFFFF 607FFFFE +r 1E20.10 +*Want "SEBR/SEB F Ufl 2" 0003F0F1 5DFC3C40 0003F0F1 5DFC3C40 +r 1E30.10 +*Want "SEBR/SEB F Nmin" 00800000 00800000 00800000 00800000 +r 1E40.10 +*Want "SEBR/SEB F Incr" 3F800000 3F800000 3F800000 3F800000 +r 1E50.10 +*Want "SEBR/SEB F Trun" 3F7FFFFF 3F7FFFFF 3F7FFFFF 3F7FFFFF + + +# Short BFP finite test results - FPCR +*Compare +r 1F00.10 +*Want "SEBR/SEB F Ovfl FPCR" 00280002 F8002002 00280002 F8002002 +r 1F10.10 +*Want "SEBR/SEB F Ufl 1 FPCR" 00000002 F8001002 00000002 F8001002 +r 1F20.10 +*Want "SEBR/SEB F Ufl 2 FPCR" 00000002 F8001002 00000002 F8001002 +r 1F30.10 +*Want "SEBR/SEB F Nmin FPCR" 00000002 F8000002 00000002 F8000002 +r 1F40.10 +*Want "SEBR/SEB F Incr FPCR" 00080002 F8000C02 00080002 F8000C02 +r 1F50.10 +*Want "SEBR/SEB F Trun FPCR" 00080002 F8000802 00080002 F8000802 + + +# Short BFP rounding mode test results +*Compare +r 2000.10 +*Want "SEBR/SEB RM +NZ RNTE, RZ" 3F7FFFFF 3F7FFFFF 3F7FFFFF 3F7FFFFF +r 2010.10 +*Want "SEBR/SEB RM +NZ RP, RM" 3F800000 3F800000 3F7FFFFF 3F7FFFFF +r 2020.8 +*Want "SEBR/SEB RM +NZ RFS" 3F7FFFFF 3F7FFFFF +r 2030.10 +*Want "SEBR/SEB RM -NZ RNTE, RZ" BF7FFFFF BF7FFFFF BF7FFFFF BF7FFFFF +r 2040.10 +*Want "SEBR/SEB RM -NZ RP, RM" BF7FFFFF BF7FFFFF BF800000 BF800000 +r 2050.8 +*Want "SEBR/SEB RM -NZ RFS" BF7FFFFF BF7FFFFF +r 2060.10 +*Want "SEBR/SEB RM +NA RNTE, RZ" 3F800000 3F800000 3F7FFFFF 3F7FFFFF +r 2070.10 +*Want "SEBR/SEB RM +NA RP, RM" 3F800000 3F800000 3F7FFFFF 3F7FFFFF +r 2080.8 +*Want "SEBR/SEB RM +NA RFS" 3F7FFFFF 3F7FFFFF +r 2090.10 +*Want "SEBR/SEB RM -NA RNTE, RZ" BF800000 BF800000 BF7FFFFF BF7FFFFF +r 20A0.10 +*Want "SEBR/SEB RM -NA RP, RM" BF7FFFFF BF7FFFFF BF800000 BF800000 +r 20B0.8 +*Want "SEBR/SEB RM -NA RFS" BF7FFFFF BF7FFFFF +r 20C0.10 +*Want "SEBR/SEB RM +TZ RNTE, RZ" 3F7FFFFE 3F7FFFFE 3F7FFFFE 3F7FFFFE +r 20D0.10 +*Want "SEBR/SEB RM +TZ RP, RM" 3F7FFFFF 3F7FFFFF 3F7FFFFE 3F7FFFFE +r 20E0.8 +*Want "SEBR/SEB RM +TZ RFS" 3F7FFFFF 3F7FFFFF +r 20F0.10 +*Want "SEBR/SEB RM -TZ RNTE, RZ" BF7FFFFE BF7FFFFE BF7FFFFE BF7FFFFE +r 2100.10 +*Want "SEBR/SEB RM -TZ RP, RM" BF7FFFFE BF7FFFFE BF7FFFFF BF7FFFFF +r 2110.8 +*Want "SEBR/SEB RM -TZ RFS" BF7FFFFF BF7FFFFF +r 2120.10 +*Want "SEBR/SEB RM +TA RNTE, RZ" 3F800000 3F800000 3F7FFFFF 3F7FFFFF +r 2130.10 +*Want "SEBR/SEB RM +TA RP, RM" 3F800000 3F800000 3F7FFFFF 3F7FFFFF +r 2140.8 +*Want "SEBR/SEB RM +TA RFS" 3F7FFFFF 3F7FFFFF +r 2150.10 +*Want "SEBR/SEB RM -TA RNTE, RZ" BF800000 BF800000 BF7FFFFF BF7FFFFF +r 2160.10 +*Want "SEBR/SEB RM -TA RP, RM" BF7FFFFF BF7FFFFF BF800000 BF800000 +r 2170.8 +*Want "SEBR/SEB RM -TA RFS" BF7FFFFF BF7FFFFF + + +# Short BFP rounding mode test results - FPCR +*Compare +r 2300.10 +*Want "SEBR/SEB RM +NZ RNTE, RZ FPCR" 00080002 00080002 00080002 00080002 +r 2310.10 +*Want "SEBR/SEB RM +NZ RP, RM FPCR" 00080002 00080002 00080002 00080002 +r 2320.08 +*Want "SEBR/SEB RM +NZ RFS FPCR" 00080002 00080002 +r 2330.10 +*Want "SEBR/SEB RM -NZ RNTE, RZ FPCR" 00080001 00080001 00080001 00080001 +r 2340.10 +*Want "SEBR/SEB RM -NZ RP, RM FPCR" 00080001 00080001 00080001 00080001 +r 2350.08 +*Want "SEBR/SEB RM -NZ RFS FPCR" 00080001 00080001 +r 2360.10 +*Want "SEBR/SEB RM +NA RNTE, RZ FPCR" 00080002 00080002 00080002 00080002 +r 2370.10 +*Want "SEBR/SEB RM +NA RP, RM FPCR" 00080002 00080002 00080002 00080002 +r 2380.08 +*Want "SEBR/SEB RM +NA RFS FPCR" 00080002 00080002 +r 2390.10 +*Want "SEBR/SEB RM -NA RNTE, RZ FPCR" 00080001 00080001 00080001 00080001 +r 23A0.10 +*Want "SEBR/SEB RM -NA RP, RM FPCR" 00080001 00080001 00080001 00080001 +r 23B0.08 +*Want "SEBR/SEB RM -NA RFS FPCR" 00080001 00080001 +r 23C0.10 +*Want "SEBR/SEB RM +TZ RNTE, RZ FPCR" 00080002 00080002 00080002 00080002 +r 23D0.10 +*Want "SEBR/SEB RM +TZ RP, RM FPCR" 00080002 00080002 00080002 00080002 +r 23E0.08 +*Want "SEBR/SEB RM +TZ RFS FPCR" 00080002 00080002 +r 23F0.10 +*Want "SEBR/SEB RM -TZ RNTE, RZ FPCR" 00080001 00080001 00080001 00080001 +r 2400.10 +*Want "SEBR/SEB RM -TZ RP, RM FPCR" 00080001 00080001 00080001 00080001 +r 2410.08 +*Want "SEBR/SEB RM -TZ RFS FPCR" 00080001 00080001 +r 2420.10 +*Want "SEBR/SEB RM +TA RNTE, RZ FPCR" 00080002 00080002 00080002 00080002 +r 2430.10 +*Want "SEBR/SEB RM +TA RP, RM FPCR" 00080002 00080002 00080002 00080002 +r 2440.08 +*Want "SEBR/SEB RM +TA RFS FPCR" 00080002 00080002 +r 2450.10 +*Want "SEBR/SEB RM -TA RNTE, RZ FPCR" 00080001 00080001 00080001 00080001 +r 2460.10 +*Want "SEBR/SEB RM -TA RP, RM FPCR" 00080001 00080001 00080001 00080001 +r 2470.08 +*Want "SEBR/SEB RM -TA RFS FPCR" 00080001 00080001 + + +# Long BFP non-finite test results +*Compare +r 4000.10 +*Want "SDBR NF -inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 4010.10 +*Want "SDB NF -inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 4020.10 +*Want "SDBR NF -inf/-2.0" FFF00000 00000000 FFF00000 00000000 +r 4030.10 +*Want "SDB NF -inf/-2.0" FFF00000 00000000 FFF00000 00000000 +r 4040.10 +*Want "SDBR NF -inf/-Dnice" FFF00000 00000000 FFF00000 00000000 +r 4050.10 +*Want "SDB NF -inf/-Dnice" FFF00000 00000000 FFF00000 00000000 +r 4060.10 +*Want "SDBR NF -inf/-0" FFF00000 00000000 FFF00000 00000000 +r 4070.10 +*Want "SDB NF -inf/-0" FFF00000 00000000 FFF00000 00000000 +r 4080.10 +*Want "SDBR NF -inf/+0" FFF00000 00000000 FFF00000 00000000 +r 4090.10 +*Want "SDB NF -inf/+0" FFF00000 00000000 FFF00000 00000000 +r 40A0.10 +*Want "SDBR NF -inf/+Dnice" FFF00000 00000000 FFF00000 00000000 +r 40B0.10 +*Want "SDB NF -inf/+Dnice" FFF00000 00000000 FFF00000 00000000 +r 40C0.10 +*Want "SDBR NF -inf/+2.0" FFF00000 00000000 FFF00000 00000000 +r 40D0.10 +*Want "SDB NF -inf/+2.0" FFF00000 00000000 FFF00000 00000000 +r 40E0.10 +*Want "SDBR NF -inf/+inf" FFF00000 00000000 FFF00000 00000000 +r 40F0.10 +*Want "SDB NF -inf/+inf" FFF00000 00000000 FFF00000 00000000 +r 4100.10 +*Want "SDBR NF -inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 4110.10 +*Want "SDB NF -inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 4120.10 +*Want "SDBR NF -inf/+SNaN" 7FF8A000 00000000 FFF00000 00000000 +r 4130.10 +*Want "SDB NF -inf/+SNaN" 7FF8A000 00000000 FFF00000 00000000 +r 4140.10 +*Want "SDBR NF -2.0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 4150.10 +*Want "SDB NF -2.0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 4160.10 +*Want "SDBR NF -2.0/-2.0" 00000000 00000000 00000000 00000000 +r 4170.10 +*Want "SDB NF -2.0/-2.0" 00000000 00000000 00000000 00000000 +r 4180.10 +*Want "SDBR NF -2.0/-Dnice" C0000000 00000000 C0000000 00000000 +r 4190.10 +*Want "SDB NF -2.0/-Dnice" C0000000 00000000 C0000000 00000000 +r 41A0.10 +*Want "SDBR NF -2.0/-0" C0000000 00000000 C0000000 00000000 +r 41B0.10 +*Want "SDB NF -2.0/-0" C0000000 00000000 C0000000 00000000 +r 41C0.10 +*Want "SDBR NF -2.0/+0" C0000000 00000000 C0000000 00000000 +r 41D0.10 +*Want "SDB NF -2.0/+0" C0000000 00000000 C0000000 00000000 +r 41E0.10 +*Want "SDBR NF -2.0/+Dnice" C0000000 00000000 C0000000 00000000 +r 41F0.10 +*Want "SDB NF -2.0/+Dnice" C0000000 00000000 C0000000 00000000 +r 4200.10 +*Want "SDBR NF -2.0/+2.0" C0100000 00000000 C0100000 00000000 +r 4210.10 +*Want "SDB NF -2.0/+2.0" C0100000 00000000 C0100000 00000000 +r 4220.10 +*Want "SDBR NF -2.0/+inf" FFF00000 00000000 FFF00000 00000000 +r 4230.10 +*Want "SDB NF -2.0/+inf" FFF00000 00000000 FFF00000 00000000 +r 4240.10 +*Want "SDBR NF -2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 4250.10 +*Want "SDB NF -2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 4260.10 +*Want "SDBR NF -2.0/+SNaN" 7FF8A000 00000000 C0000000 00000000 +r 4270.10 +*Want "SDB NF -2.0/+SNaN" 7FF8A000 00000000 C0000000 00000000 +r 4280.10 +*Want "SDBR NF -Dnice/-inf" 7FF00000 00000000 7FF00000 00000000 +r 4290.10 +*Want "SDB NF -Dnice/-inf" 7FF00000 00000000 7FF00000 00000000 +r 42A0.10 +*Want "SDBR NF -Dnice/-2.0" 40000000 00000000 40000000 00000000 +r 42B0.10 +*Want "SDB NF -Dnice/-2.0" 40000000 00000000 40000000 00000000 +r 42C0.10 +*Want "SDBR NF -Dnice/-Dnice" 00000000 00000000 00000000 00000000 +r 42D0.10 +*Want "SDB NF -Dnice/-Dnice" 00000000 00000000 00000000 00000000 +r 42E0.10 +*Want "SDBR NF -Dnice/-0" 80010000 00000000 DFD00000 00000000 +r 42F0.10 +*Want "SDB NF -Dnice/-0" 80010000 00000000 DFD00000 00000000 +r 4300.10 +*Want "SDBR NF -Dnice/+0" 80010000 00000000 DFD00000 00000000 +r 4310.10 +*Want "SDB NF -Dnice/+0" 80010000 00000000 DFD00000 00000000 +r 4320.10 +*Want "SDBR NF -Dnice/+Dnice" 80020000 00000000 DFE00000 00000000 +r 4330.10 +*Want "SDB NF -Dnice/+Dnice" 80020000 00000000 DFE00000 00000000 +r 4340.10 +*Want "SDBR NF -Dnice/+2.0" C0000000 00000000 C0000000 00000000 +r 4350.10 +*Want "SDB NF -Dnice/+2.0" C0000000 00000000 C0000000 00000000 +r 4360.10 +*Want "SDBR NF -Dnice/+inf" FFF00000 00000000 FFF00000 00000000 +r 4370.10 +*Want "SDB NF -Dnice/+inf" FFF00000 00000000 FFF00000 00000000 +r 4380.10 +*Want "SDBR NF -Dnice/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 4390.10 +*Want "SDB NF -Dnice/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 43A0.10 +*Want "SDBR NF -Dnice/+SNaN" 7FF8A000 00000000 80010000 00000000 +r 43B0.10 +*Want "SDB NF -Dnice/+SNaN" 7FF8A000 00000000 80010000 00000000 +r 43C0.10 +*Want "SDBR NF -0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 43D0.10 +*Want "SDB NF -0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 43E0.10 +*Want "SDBR NF -0/-2.0" 40000000 00000000 40000000 00000000 +r 43F0.10 +*Want "SDB NF -0/-2.0" 40000000 00000000 40000000 00000000 +r 4400.10 +*Want "SDBR NF -0/-Dnice" 00010000 00000000 5FD00000 00000000 +r 4410.10 +*Want "SDB NF -0/-Dnice" 00010000 00000000 5FD00000 00000000 +r 4420.10 +*Want "SDBR NF -0/-0" 00000000 00000000 00000000 00000000 +r 4430.10 +*Want "SDB NF -0/-0" 00000000 00000000 00000000 00000000 +r 4440.10 +*Want "SDBR NF -0/+0" 80000000 00000000 80000000 00000000 +r 4450.10 +*Want "SDB NF -0/+0" 80000000 00000000 80000000 00000000 +r 4460.10 +*Want "SDBR NF -0/+Dnice" 80010000 00000000 DFD00000 00000000 +r 4470.10 +*Want "SDB NF -0/+Dnice" 80010000 00000000 DFD00000 00000000 +r 4480.10 +*Want "SDBR NF -0/+2.0" C0000000 00000000 C0000000 00000000 +r 4490.10 +*Want "SDB NF -0/+2.0" C0000000 00000000 C0000000 00000000 +r 44A0.10 +*Want "SDBR NF -0/+inf" FFF00000 00000000 FFF00000 00000000 +r 44B0.10 +*Want "SDB NF -0/+inf" FFF00000 00000000 FFF00000 00000000 +r 44C0.10 +*Want "SDBR NF -0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 44D0.10 +*Want "SDB NF -0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 44E0.10 +*Want "SDBR NF -0/+SNaN" 7FF8A000 00000000 80000000 00000000 +r 44F0.10 +*Want "SDB NF -0/+SNaN" 7FF8A000 00000000 80000000 00000000 +r 4500.10 +*Want "SDBR NF +0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 4510.10 +*Want "SDB NF +0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 4520.10 +*Want "SDBR NF +0/-2.0" 40000000 00000000 40000000 00000000 +r 4530.10 +*Want "SDB NF +0/-2.0" 40000000 00000000 40000000 00000000 +r 4540.10 +*Want "SDBR NF +0/-Dnice" 00010000 00000000 5FD00000 00000000 +r 4550.10 +*Want "SDB NF +0/-Dnice" 00010000 00000000 5FD00000 00000000 +r 4560.10 +*Want "SDBR NF +0/-0" 00000000 00000000 00000000 00000000 +r 4570.10 +*Want "SDB NF +0/-0" 00000000 00000000 00000000 00000000 +r 4580.10 +*Want "SDBR NF +0/+0" 00000000 00000000 00000000 00000000 +r 4590.10 +*Want "SDB NF +0/+0" 00000000 00000000 00000000 00000000 +r 45A0.10 +*Want "SDBR NF +0/+Dnice" 80010000 00000000 DFD00000 00000000 +r 45B0.10 +*Want "SDB NF +0/+Dnice" 80010000 00000000 DFD00000 00000000 +r 45C0.10 +*Want "SDBR NF +0/+2.0" C0000000 00000000 C0000000 00000000 +r 45D0.10 +*Want "SDB NF +0/+2.0" C0000000 00000000 C0000000 00000000 +r 45E0.10 +*Want "SDBR NF +0/+inf" FFF00000 00000000 FFF00000 00000000 +r 45F0.10 +*Want "SDB NF +0/+inf" FFF00000 00000000 FFF00000 00000000 +r 4600.10 +*Want "SDBR NF +0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 4610.10 +*Want "SDB NF +0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 4620.10 +*Want "SDBR NF +0/+SNaN" 7FF8A000 00000000 00000000 00000000 +r 4630.10 +*Want "SDB NF +0/+SNaN" 7FF8A000 00000000 00000000 00000000 +r 4640.10 +*Want "SDBR NF +Dnice/-inf" 7FF00000 00000000 7FF00000 00000000 +r 4650.10 +*Want "SDB NF +Dnice/-inf" 7FF00000 00000000 7FF00000 00000000 +r 4660.10 +*Want "SDBR NF +Dnice/-2.0" 40000000 00000000 40000000 00000000 +r 4670.10 +*Want "SDB NF +Dnice/-2.0" 40000000 00000000 40000000 00000000 +r 4680.10 +*Want "SDBR NF +Dnice/-Dnice" 00020000 00000000 5FE00000 00000000 +r 4690.10 +*Want "SDB NF +Dnice/-Dnice" 00020000 00000000 5FE00000 00000000 +r 46A0.10 +*Want "SDBR NF +Dnice/-0" 00010000 00000000 5FD00000 00000000 +r 46B0.10 +*Want "SDB NF +Dnice/-0" 00010000 00000000 5FD00000 00000000 +r 46C0.10 +*Want "SDBR NF +Dnice/+0" 00010000 00000000 5FD00000 00000000 +r 46D0.10 +*Want "SDB NF +Dnice/+0" 00010000 00000000 5FD00000 00000000 +r 46E0.10 +*Want "SDBR NF +Dnice/+Dnice" 00000000 00000000 00000000 00000000 +r 46F0.10 +*Want "SDB NF +Dnice/+Dnice" 00000000 00000000 00000000 00000000 +r 4700.10 +*Want "SDBR NF +Dnice/+2.0" C0000000 00000000 C0000000 00000000 +r 4710.10 +*Want "SDB NF +Dnice/+2.0" C0000000 00000000 C0000000 00000000 +r 4720.10 +*Want "SDBR NF +Dnice/+inf" FFF00000 00000000 FFF00000 00000000 +r 4730.10 +*Want "SDB NF +Dnice/+inf" FFF00000 00000000 FFF00000 00000000 +r 4740.10 +*Want "SDBR NF +Dnice/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 4750.10 +*Want "SDB NF +Dnice/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 4760.10 +*Want "SDBR NF +Dnice/+SNaN" 7FF8A000 00000000 00010000 00000000 +r 4770.10 +*Want "SDB NF +Dnice/+SNaN" 7FF8A000 00000000 00010000 00000000 +r 4780.10 +*Want "SDBR NF +2.0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 4790.10 +*Want "SDB NF +2.0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 47A0.10 +*Want "SDBR NF +2.0/-2.0" 40100000 00000000 40100000 00000000 +r 47B0.10 +*Want "SDB NF +2.0/-2.0" 40100000 00000000 40100000 00000000 +r 47C0.10 +*Want "SDBR NF +2.0/-Dnice" 40000000 00000000 40000000 00000000 +r 47D0.10 +*Want "SDB NF +2.0/-Dnice" 40000000 00000000 40000000 00000000 +r 47E0.10 +*Want "SDBR NF +2.0/-0" 40000000 00000000 40000000 00000000 +r 47F0.10 +*Want "SDB NF +2.0/-0" 40000000 00000000 40000000 00000000 +r 4800.10 +*Want "SDBR NF +2.0/+0" 40000000 00000000 40000000 00000000 +r 4810.10 +*Want "SDB NF +2.0/+0" 40000000 00000000 40000000 00000000 +r 4820.10 +*Want "SDBR NF +2.0/+Dnice" 40000000 00000000 40000000 00000000 +r 4830.10 +*Want "SDB NF +2.0/+Dnice" 40000000 00000000 40000000 00000000 +r 4840.10 +*Want "SDBR NF +2.0/+2.0" 00000000 00000000 00000000 00000000 +r 4850.10 +*Want "SDB NF +2.0/+2.0" 00000000 00000000 00000000 00000000 +r 4860.10 +*Want "SDBR NF +2.0/+inf" FFF00000 00000000 FFF00000 00000000 +r 4870.10 +*Want "SDB NF +2.0/+inf" FFF00000 00000000 FFF00000 00000000 +r 4880.10 +*Want "SDBR NF +2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 4890.10 +*Want "SDB NF +2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 48A0.10 +*Want "SDBR NF +2.0/+SNaN" 7FF8A000 00000000 40000000 00000000 +r 48B0.10 +*Want "SDB NF +2.0/+SNaN" 7FF8A000 00000000 40000000 00000000 +r 48C0.10 +*Want "SDBR NF +inf/-inf" 7FF00000 00000000 7FF00000 00000000 +r 48D0.10 +*Want "SDB NF +inf/-inf" 7FF00000 00000000 7FF00000 00000000 +r 48E0.10 +*Want "SDBR NF +inf/-2.0" 7FF00000 00000000 7FF00000 00000000 +r 48F0.10 +*Want "SDB NF +inf/-2.0" 7FF00000 00000000 7FF00000 00000000 +r 4900.10 +*Want "SDBR NF +inf/-Dnice" 7FF00000 00000000 7FF00000 00000000 +r 4910.10 +*Want "SDB NF +inf/-Dnice" 7FF00000 00000000 7FF00000 00000000 +r 4920.10 +*Want "SDBR NF +inf/-0" 7FF00000 00000000 7FF00000 00000000 +r 4930.10 +*Want "SDB NF +inf/-0" 7FF00000 00000000 7FF00000 00000000 +r 4940.10 +*Want "SDBR NF +inf/+0" 7FF00000 00000000 7FF00000 00000000 +r 4950.10 +*Want "SDB NF +inf/+0" 7FF00000 00000000 7FF00000 00000000 +r 4960.10 +*Want "SDBR NF +inf/+Dnice" 7FF00000 00000000 7FF00000 00000000 +r 4970.10 +*Want "SDB NF +inf/+Dnice" 7FF00000 00000000 7FF00000 00000000 +r 4980.10 +*Want "SDBR NF +inf/+2.0" 7FF00000 00000000 7FF00000 00000000 +r 4990.10 +*Want "SDB NF +inf/+2.0" 7FF00000 00000000 7FF00000 00000000 +r 49A0.10 +*Want "SDBR NF +inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 49B0.10 +*Want "SDB NF +inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 49C0.10 +*Want "SDBR NF +inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 49D0.10 +*Want "SDB NF +inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 49E0.10 +*Want "SDBR NF +inf/+SNaN" 7FF8A000 00000000 7FF00000 00000000 +r 49F0.10 +*Want "SDB NF +inf/+SNaN" 7FF8A000 00000000 7FF00000 00000000 +r 4A00.10 +*Want "SDBR NF -QNaN/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 4A10.10 +*Want "SDB NF -QNaN/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 4A20.10 +*Want "SDBR NF -QNaN/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 4A30.10 +*Want "SDB NF -QNaN/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 4A40.10 +*Want "SDBR NF -QNaN/-Dnice" FFF8B000 00000000 FFF8B000 00000000 +r 4A50.10 +*Want "SDB NF -QNaN/-Dnice" FFF8B000 00000000 FFF8B000 00000000 +r 4A60.10 +*Want "SDBR NF -QNaN/-0" FFF8B000 00000000 FFF8B000 00000000 +r 4A70.10 +*Want "SDB NF -QNaN/-0" FFF8B000 00000000 FFF8B000 00000000 +r 4A80.10 +*Want "SDBR NF -QNaN/+0" FFF8B000 00000000 FFF8B000 00000000 +r 4A90.10 +*Want "SDB NF -QNaN/+0" FFF8B000 00000000 FFF8B000 00000000 +r 4AA0.10 +*Want "SDBR NF -QNaN/+Dnice" FFF8B000 00000000 FFF8B000 00000000 +r 4AB0.10 +*Want "SDB NF -QNaN/+Dnice" FFF8B000 00000000 FFF8B000 00000000 +r 4AC0.10 +*Want "SDBR NF -QNaN/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 4AD0.10 +*Want "SDB NF -QNaN/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 4AE0.10 +*Want "SDBR NF -QNaN/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 4AF0.10 +*Want "SDB NF -QNaN/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 4B00.10 +*Want "SDBR NF -QNaN/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 4B10.10 +*Want "SDB NF -QNaN/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 4B20.10 +*Want "SDBR NF -QNaN/+SNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 4B30.10 +*Want "SDB NF -QNaN/+SNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 4B40.10 +*Want "SDBR NF +SNaN/-inf" 7FF8A000 00000000 7FF0A000 00000000 +r 4B50.10 +*Want "SDB NF +SNaN/-inf" 7FF8A000 00000000 7FF0A000 00000000 +r 4B60.10 +*Want "SDBR NF +SNaN/-2.0" 7FF8A000 00000000 7FF0A000 00000000 +r 4B70.10 +*Want "SDB NF +SNaN/-2.0" 7FF8A000 00000000 7FF0A000 00000000 +r 4B80.10 +*Want "SDBR NF +SNaN/-Dnice" 7FF8A000 00000000 7FF0A000 00000000 +r 4B90.10 +*Want "SDB NF +SNaN/-Dnice" 7FF8A000 00000000 7FF0A000 00000000 +r 4BA0.10 +*Want "SDBR NF +SNaN/-0" 7FF8A000 00000000 7FF0A000 00000000 +r 4BB0.10 +*Want "SDB NF +SNaN/-0" 7FF8A000 00000000 7FF0A000 00000000 +r 4BC0.10 +*Want "SDBR NF +SNaN/+0" 7FF8A000 00000000 7FF0A000 00000000 +r 4BD0.10 +*Want "SDB NF +SNaN/+0" 7FF8A000 00000000 7FF0A000 00000000 +r 4BE0.10 +*Want "SDBR NF +SNaN/+Dnice" 7FF8A000 00000000 7FF0A000 00000000 +r 4BF0.10 +*Want "SDB NF +SNaN/+Dnice" 7FF8A000 00000000 7FF0A000 00000000 +r 4C00.10 +*Want "SDBR NF +SNaN/+2.0" 7FF8A000 00000000 7FF0A000 00000000 +r 4C10.10 +*Want "SDB NF +SNaN/+2.0" 7FF8A000 00000000 7FF0A000 00000000 +r 4C20.10 +*Want "SDBR NF +SNaN/+inf" 7FF8A000 00000000 7FF0A000 00000000 +r 4C30.10 +*Want "SDB NF +SNaN/+inf" 7FF8A000 00000000 7FF0A000 00000000 +r 4C40.10 +*Want "SDBR NF +SNaN/-QNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 4C50.10 +*Want "SDB NF +SNaN/-QNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 4C60.10 +*Want "SDBR NF +SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 4C70.10 +*Want "SDB NF +SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 + + +# Long BFP non-finite test results - FPCR +*Compare +r 4D00.10 +*Want "SDBR/SDB NF -inf/-inf FPCR" 00800003 F8008003 00800003 F8008003 +r 4D10.10 +*Want "SDBR/SDB NF -inf/-2.0 FPCR" 00000001 F8000001 00000001 F8000001 +r 4D20.10 +*Want "SDBR/SDB NF -inf/-Dnice FPCR" 00000001 F8000001 00000001 F8000001 +r 4D30.10 +*Want "SDBR/SDB NF -inf/-0 FPCR" 00000001 F8000001 00000001 F8000001 +r 4D40.10 +*Want "SDBR/SDB NF -inf/+0 FPCR" 00000001 F8000001 00000001 F8000001 +r 4D50.10 +*Want "SDBR/SDB NF -inf/+Dnice FPCR" 00000001 F8000001 00000001 F8000001 +r 4D60.10 +*Want "SDBR/SDB NF -inf/+2.0 FPCR" 00000001 F8000001 00000001 F8000001 +r 4D70.10 +*Want "SDBR/SDB NF -inf/+inf FPCR" 00000001 F8000001 00000001 F8000001 +r 4D80.10 +*Want "SDBR/SDB NF -inf/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 4D90.10 +*Want "SDBR/SDB NF -inf/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 4DA0.10 +*Want "SDBR/SDB NF -2.0/-inf FPCR" 00000002 F8000002 00000002 F8000002 +r 4DB0.10 +*Want "SDBR/SDB NF -2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4DC0.10 +*Want "SDBR/SDB NF -2.0/-Dnice FPCR" 00080001 F8000C01 00080001 F8000C01 +r 4DD0.10 +*Want "SDBR/SDB NF -2.0/-0 FPCR" 00000001 F8000001 00000001 F8000001 +r 4DE0.10 +*Want "SDBR/SDB NF -2.0/+0 FPCR" 00000001 F8000001 00000001 F8000001 +r 4DF0.10 +*Want "SDBR/SDB NF -2.0/+Dnice FPCR" 00080001 F8000801 00080001 F8000801 +r 4E00.10 +*Want "SDBR/SDB NF -2.0/+2.0 FPCR" 00000001 F8000001 00000001 F8000001 +r 4E10.10 +*Want "SDBR/SDB NF -2.0/+inf FPCR" 00000001 F8000001 00000001 F8000001 +r 4E20.10 +*Want "SDBR/SDB NF -2.0/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 4E30.10 +*Want "SDBR/SDB NF -2.0/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 4E40.10 +*Want "SDBR/SDB NF -Dnice/-inf FPCR" 00000002 F8000002 00000002 F8000002 +r 4E50.10 +*Want "SDBR/SDB NF -Dnice/-2.0 FPCR" 00080002 F8000C02 00080002 F8000C02 +r 4E60.10 +*Want "SDBR/SDB NF -Dnice/-Dnice FPCR" 00000000 F8000000 00000000 F8000000 +r 4E70.10 +*Want "SDBR/SDB NF -Dnice/-0 FPCR" 00000001 F8001001 00000001 F8001001 +r 4E80.10 +*Want "SDBR/SDB NF -Dnice/+0 FPCR" 00000001 F8001001 00000001 F8001001 +r 4E90.10 +*Want "SDBR/SDB NF -Dnice/+Dnice FPCR" 00000001 F8001001 00000001 F8001001 +r 4EA0.10 +*Want "SDBR/SDB NF -Dnice/+2.0 FPCR" 00080001 F8000801 00080001 F8000801 +r 4EB0.10 +*Want "SDBR/SDB NF -Dnice/+inf FPCR" 00000001 F8000001 00000001 F8000001 +r 4EC0.10 +*Want "SDBR/SDB NF -Dnice/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 4ED0.10 +*Want "SDBR/SDB NF -Dnice/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 4EE0.10 +*Want "SDBR/SDB NF -0/-inf FPCR" 00000002 F8000002 00000002 F8000002 +r 4EF0.10 +*Want "SDBR/SDB NF -0/-2.0 FPCR" 00000002 F8000002 00000002 F8000002 +r 4F00.10 +*Want "SDBR/SDB NF -0/-Dnice FPCR" 00000002 F8001002 00000002 F8001002 +r 4F10.10 +*Want "SDBR/SDB NF -0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4F20.10 +*Want "SDBR/SDB NF -0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4F30.10 +*Want "SDBR/SDB NF -0/+Dnice FPCR" 00000001 F8001001 00000001 F8001001 +r 4F40.10 +*Want "SDBR/SDB NF -0/+2.0 FPCR" 00000001 F8000001 00000001 F8000001 +r 4F50.10 +*Want "SDBR/SDB NF -0/+inf FPCR" 00000001 F8000001 00000001 F8000001 +r 4F60.10 +*Want "SDBR/SDB NF -0/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 4F70.10 +*Want "SDBR/SDB NF -0/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 4F80.10 +*Want "SDBR/SDB NF +0/-inf FPCR" 00000002 F8000002 00000002 F8000002 +r 4F90.10 +*Want "SDBR/SDB NF +0/-2.0 FPCR" 00000002 F8000002 00000002 F8000002 +r 4FA0.10 +*Want "SDBR/SDB NF +0/-Dnice FPCR" 00000002 F8001002 00000002 F8001002 +r 4FB0.10 +*Want "SDBR/SDB NF +0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4FC0.10 +*Want "SDBR/SDB NF +0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4FD0.10 +*Want "SDBR/SDB NF +0/+Dnice FPCR" 00000001 F8001001 00000001 F8001001 +r 4FE0.10 +*Want "SDBR/SDB NF +0/+2.0 FPCR" 00000001 F8000001 00000001 F8000001 +r 4FF0.10 +*Want "SDBR/SDB NF +0/+inf FPCR" 00000001 F8000001 00000001 F8000001 +r 5000.10 +*Want "SDBR/SDB NF +0/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 5010.10 +*Want "SDBR/SDB NF +0/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 5020.10 +*Want "SDBR/SDB NF +Dnice/-inf FPCR" 00000002 F8000002 00000002 F8000002 +r 5030.10 +*Want "SDBR/SDB NF +Dnice/-2.0 FPCR" 00080002 F8000802 00080002 F8000802 +r 5040.10 +*Want "SDBR/SDB NF +Dnice/-Dnice FPCR" 00000002 F8001002 00000002 F8001002 +r 5050.10 +*Want "SDBR/SDB NF +Dnice/-0 FPCR" 00000002 F8001002 00000002 F8001002 +r 5060.10 +*Want "SDBR/SDB NF +Dnice/+0 FPCR" 00000002 F8001002 00000002 F8001002 +r 5070.10 +*Want "SDBR/SDB NF +Dnice/+Dnice FPCR" 00000000 F8000000 00000000 F8000000 +r 5080.10 +*Want "SDBR/SDB NF +Dnice/+2.0 FPCR" 00080001 F8000C01 00080001 F8000C01 +r 5090.10 +*Want "SDBR/SDB NF +Dnice/+inf FPCR" 00000001 F8000001 00000001 F8000001 +r 50A0.10 +*Want "SDBR/SDB NF +Dnice/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 50B0.10 +*Want "SDBR/SDB NF +Dnice/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 50C0.10 +*Want "SDBR/SDB NF +2.0/-inf FPCR" 00000002 F8000002 00000002 F8000002 +r 50D0.10 +*Want "SDBR/SDB NF +2.0/-2.0 FPCR" 00000002 F8000002 00000002 F8000002 +r 50E0.10 +*Want "SDBR/SDB NF +2.0/-Dnice FPCR" 00080002 F8000802 00080002 F8000802 +r 50F0.10 +*Want "SDBR/SDB NF +2.0/-0 FPCR" 00000002 F8000002 00000002 F8000002 +r 5100.10 +*Want "SDBR/SDB NF +2.0/+0 FPCR" 00000002 F8000002 00000002 F8000002 +r 5110.10 +*Want "SDBR/SDB NF +2.0/+Dnice FPCR" 00080002 F8000C02 00080002 F8000C02 +r 5120.10 +*Want "SDBR/SDB NF +2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 5130.10 +*Want "SDBR/SDB NF +2.0/+inf FPCR" 00000001 F8000001 00000001 F8000001 +r 5140.10 +*Want "SDBR/SDB NF +2.0/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 5150.10 +*Want "SDBR/SDB NF +2.0/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 5160.10 +*Want "SDBR/SDB NF +inf/-inf FPCR" 00000002 F8000002 00000002 F8000002 +r 5170.10 +*Want "SDBR/SDB NF +inf/-2.0 FPCR" 00000002 F8000002 00000002 F8000002 +r 5180.10 +*Want "SDBR/SDB NF +inf/-Dnice FPCR" 00000002 F8000002 00000002 F8000002 +r 5190.10 +*Want "SDBR/SDB NF +inf/-0 FPCR" 00000002 F8000002 00000002 F8000002 +r 51A0.10 +*Want "SDBR/SDB NF +inf/+0 FPCR" 00000002 F8000002 00000002 F8000002 +r 51B0.10 +*Want "SDBR/SDB NF +inf/+Dnice FPCR" 00000002 F8000002 00000002 F8000002 +r 51C0.10 +*Want "SDBR/SDB NF +inf/+2.0 FPCR" 00000002 F8000002 00000002 F8000002 +r 51D0.10 +*Want "SDBR/SDB NF +inf/+inf FPCR" 00800003 F8008003 00800003 F8008003 +r 51E0.10 +*Want "SDBR/SDB NF +inf/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 51F0.10 +*Want "SDBR/SDB NF +inf/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 5200.10 +*Want "SDBR/SDB NF -QNaN/-inf FPCR" 00000003 F8000003 00000003 F8000003 +r 5210.10 +*Want "SDBR/SDB NF -QNaN/-2.0 FPCR" 00000003 F8000003 00000003 F8000003 +r 5220.10 +*Want "SDBR/SDB NF -QNaN/-Dnice FPCR" 00000003 F8000003 00000003 F8000003 +r 5230.10 +*Want "SDBR/SDB NF -QNaN/-0 FPCR" 00000003 F8000003 00000003 F8000003 +r 5240.10 +*Want "SDBR/SDB NF -QNaN/+0 FPCR" 00000003 F8000003 00000003 F8000003 +r 5250.10 +*Want "SDBR/SDB NF -QNaN/+Dnice FPCR" 00000003 F8000003 00000003 F8000003 +r 5260.10 +*Want "SDBR/SDB NF -QNaN/+2.0 FPCR" 00000003 F8000003 00000003 F8000003 +r 5270.10 +*Want "SDBR/SDB NF -QNaN/+inf FPCR" 00000003 F8000003 00000003 F8000003 +r 5280.10 +*Want "SDBR/SDB NF -QNaN/-QNaN FPCR" 00000003 F8000003 00000003 F8000003 +r 5290.10 +*Want "SDBR/SDB NF -QNaN/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 52A0.10 +*Want "SDBR/SDB NF +SNaN/-inf FPCR" 00800003 F8008003 00800003 F8008003 +r 52B0.10 +*Want "SDBR/SDB NF +SNaN/-2.0 FPCR" 00800003 F8008003 00800003 F8008003 +r 52C0.10 +*Want "SDBR/SDB NF +SNaN/-Dnice FPCR" 00800003 F8008003 00800003 F8008003 +r 52D0.10 +*Want "SDBR/SDB NF +SNaN/-0 FPCR" 00800003 F8008003 00800003 F8008003 +r 52E0.10 +*Want "SDBR/SDB NF +SNaN/+0 FPCR" 00800003 F8008003 00800003 F8008003 +r 52F0.10 +*Want "SDBR/SDB NF +SNaN/+Dnice FPCR" 00800003 F8008003 00800003 F8008003 +r 5300.10 +*Want "SDBR/SDB NF +SNaN/+2.0 FPCR" 00800003 F8008003 00800003 F8008003 +r 5310.10 +*Want "SDBR/SDB NF +SNaN/+inf FPCR" 00800003 F8008003 00800003 F8008003 +r 5320.10 +*Want "SDBR/SDB NF +SNaN/-QNaN FPCR" 00800003 F8008003 00800003 F8008003 +r 5330.10 +*Want "SDBR/SDB NF +SNaN/+SNaN FPCR" 00800003 F8008003 00800003 F8008003 + + +# Long BFP finite test results +*Compare +r 5400.10 +*Want "SDBR F Ovfl" 7FFFFFFF FFFFFFFF 7FFFFFFF FFFFFFFF +r 5410.10 +*Want "SDB F Ovfl" 7FFFFFFF FFFFFFFF 7FFFFFFF FFFFFFFF +r 5420.10 +*Want "SDBR F Ufl 1" 000FFFFF FFFFFFFF 600FFFFF FFFFFFFE +r 5430.10 +*Want "SDB F Ufl 1" 000FFFFF FFFFFFFF 600FFFFF FFFFFFFE +r 5440.10 +*Want "SDBR F Ufl 2" 00070F10 00000000 5FFC3C40 00000000 +r 5450.10 +*Want "SDB F Ufl 2" 00070F10 00000000 5FFC3C40 00000000 +r 5460.10 +*Want "SDBR F Nmin" 00100000 00000000 00100000 00000000 +r 5470.10 +*Want "SDB F Nmin" 00100000 00000000 00100000 00000000 +r 5480.10 +*Want "SDBR F Incr" 3FF00000 00000000 3FF00000 00000000 +r 5490.10 +*Want "SDB F Incr" 3FF00000 00000000 3FF00000 00000000 +r 54A0.10 +*Want "SDBR F Trun" 3FEFFFFF FFFFFFFF 3FEFFFFF FFFFFFFF +r 54B0.10 +*Want "SDB F Trun" 3FEFFFFF FFFFFFFF 3FEFFFFF FFFFFFFF + + +# Long BFP finite test results - FPCR +*Compare +r 5600.10 +*Want "SDBR/SDB F Ovfl FPCR" 00000003 F8000003 00000003 F8000003 +r 5610.10 +*Want "SDBR/SDB F Ufl 1 FPCR" 00000002 F8001002 00000002 F8001002 +r 5620.10 +*Want "SDBR/SDB F Ufl 2 FPCR" 00000002 F8001002 00000002 F8001002 +r 5630.10 +*Want "SDBR/SDB F Nmin FPCR" 00000002 F8000002 00000002 F8000002 +r 5640.10 +*Want "SDBR/SDB F Incr FPCR" 00080002 F8000C02 00080002 F8000C02 +r 5650.10 +*Want "SDBR/SDB F Trun FPCR" 00080002 F8000802 00080002 F8000802 + + +# Long BFP rounding mode test results +*Compare +r 5700.10 +*Want "SDBR/SDB RM +NZ RNTE" 3FEFFFFF FFFFFFFF 3FEFFFFF FFFFFFFF +r 5710.10 +*Want "SDBR/SDB RM +NZ RZ" 3FEFFFFF FFFFFFFF 3FEFFFFF FFFFFFFF +r 5720.10 +*Want "SDBR/SDB RM +NZ RP" 3FF00000 00000000 3FF00000 00000000 +r 5730.10 +*Want "SDBR/SDB RM +NZ RM" 3FEFFFFF FFFFFFFF 3FEFFFFF FFFFFFFF +r 5740.10 +*Want "SDBR/SDB RM +NZ RFS" 3FEFFFFF FFFFFFFF 3FEFFFFF FFFFFFFF +r 5750.10 +*Want "SDBR/SDB RM -NZ RNTE" BFEFFFFF FFFFFFFF BFEFFFFF FFFFFFFF +r 5760.10 +*Want "SDBR/SDB RM -NZ RZ" BFEFFFFF FFFFFFFF BFEFFFFF FFFFFFFF +r 5770.10 +*Want "SDBR/SDB RM -NZ RP" BFEFFFFF FFFFFFFF BFEFFFFF FFFFFFFF +r 5780.10 +*Want "SDBR/SDB RM -NZ RM" BFF00000 00000000 BFF00000 00000000 +r 5790.10 +*Want "SDBR/SDB RM -NZ RFS" BFEFFFFF FFFFFFFF BFEFFFFF FFFFFFFF +r 57A0.10 +*Want "SDBR/SDB RM +NA RNTE" 3FF00000 00000000 3FF00000 00000000 +r 57B0.10 +*Want "SDBR/SDB RM +NA RZ" 3FEFFFFF FFFFFFFF 3FEFFFFF FFFFFFFF +r 57C0.10 +*Want "SDBR/SDB RM +NA RP" 3FF00000 00000000 3FF00000 00000000 +r 57D0.10 +*Want "SDBR/SDB RM +NA RM" 3FEFFFFF FFFFFFFF 3FEFFFFF FFFFFFFF +r 57E0.10 +*Want "SDBR/SDB RM +NA RFS" 3FEFFFFF FFFFFFFF 3FEFFFFF FFFFFFFF +r 57F0.10 +*Want "SDBR/SDB RM -NA RNTE" BFF00000 00000000 BFF00000 00000000 +r 5800.10 +*Want "SDBR/SDB RM -NA RZ" BFEFFFFF FFFFFFFF BFEFFFFF FFFFFFFF +r 5810.10 +*Want "SDBR/SDB RM -NA RP" BFEFFFFF FFFFFFFF BFEFFFFF FFFFFFFF +r 5820.10 +*Want "SDBR/SDB RM -NA RM" BFF00000 00000000 BFF00000 00000000 +r 5830.10 +*Want "SDBR/SDB RM -NA RFS" BFEFFFFF FFFFFFFF BFEFFFFF FFFFFFFF +r 5840.10 +*Want "SDBR/SDB RM +TZ RNTE" 3FEFFFFF FFFFFFFE 3FEFFFFF FFFFFFFE +r 5850.10 +*Want "SDBR/SDB RM +TZ RZ" 3FEFFFFF FFFFFFFE 3FEFFFFF FFFFFFFE +r 5860.10 +*Want "SDBR/SDB RM +TZ RP" 3FEFFFFF FFFFFFFF 3FEFFFFF FFFFFFFF +r 5870.10 +*Want "SDBR/SDB RM +TZ RM" 3FEFFFFF FFFFFFFE 3FEFFFFF FFFFFFFE +r 5880.10 +*Want "SDBR/SDB RM +TZ RFS" 3FEFFFFF FFFFFFFF 3FEFFFFF FFFFFFFF +r 5890.10 +*Want "SDBR/SDB RM -TZ RNTE" BFEFFFFF FFFFFFFE BFEFFFFF FFFFFFFE +r 58A0.10 +*Want "SDBR/SDB RM -TZ RZ" BFEFFFFF FFFFFFFE BFEFFFFF FFFFFFFE +r 58B0.10 +*Want "SDBR/SDB RM -TZ RP" BFEFFFFF FFFFFFFE BFEFFFFF FFFFFFFE +r 58C0.10 +*Want "SDBR/SDB RM -TZ RM" BFEFFFFF FFFFFFFF BFEFFFFF FFFFFFFF +r 58D0.10 +*Want "SDBR/SDB RM -TZ RFS" BFEFFFFF FFFFFFFF BFEFFFFF FFFFFFFF +r 58E0.10 +*Want "SDBR/SDB RM +TA RNTE" 3FF00000 00000000 3FF00000 00000000 +r 58F0.10 +*Want "SDBR/SDB RM +TA RZ" 3FEFFFFF FFFFFFFF 3FEFFFFF FFFFFFFF +r 5900.10 +*Want "SDBR/SDB RM +TA RP" 3FF00000 00000000 3FF00000 00000000 +r 5910.10 +*Want "SDBR/SDB RM +TA RM" 3FEFFFFF FFFFFFFF 3FEFFFFF FFFFFFFF +r 5920.10 +*Want "SDBR/SDB RM +TA RFS" 3FEFFFFF FFFFFFFF 3FEFFFFF FFFFFFFF +r 5930.10 +*Want "SDBR/SDB RM -TA RNTE" BFF00000 00000000 BFF00000 00000000 +r 5940.10 +*Want "SDBR/SDB RM -TA RZ" BFEFFFFF FFFFFFFF BFEFFFFF FFFFFFFF +r 5950.10 +*Want "SDBR/SDB RM -TA RP" BFEFFFFF FFFFFFFF BFEFFFFF FFFFFFFF +r 5960.10 +*Want "SDBR/SDB RM -TA RM" BFF00000 00000000 BFF00000 00000000 +r 5970.10 +*Want "SDBR/SDB RM -TA RFS" BFEFFFFF FFFFFFFF BFEFFFFF FFFFFFFF + + +# Long BFP rounding mode test results - FPCR +*Compare +r 5C00.10 +*Want "SDBR/SDB RM +NZ RNTE, RZ FPCR" 00080002 00080002 00080002 00080002 +r 5C10.10 +*Want "SDBR/SDB RM +NZ RP, RM FPCR" 00080002 00080002 00080002 00080002 +r 5C20.8 +*Want "SDBR/SDB RM +NZ RFS FPCR" 00080002 00080002 +r 5C30.10 +*Want "SDBR/SDB RM +NZ RNTE, RZ FPCR" 00080001 00080001 00080001 00080001 +r 5C40.10 +*Want "SDBR/SDB RM +NZ RP, RM FPCR" 00080001 00080001 00080001 00080001 +r 5C50.8 +*Want "SDBR/SDB RM -NZ RFS FPCR" 00080001 00080001 +r 5C60.10 +*Want "SDBR/SDB RM -NZ RNTE, RZ FPCR" 00080002 00080002 00080002 00080002 +r 5C70.10 +*Want "SDBR/SDB RM -NZ RP, RM FPCR" 00080002 00080002 00080002 00080002 +r 5C80.8 +*Want "SDBR/SDB RM -NZ RFS FPCR" 00080002 00080002 +r 5C90.10 +*Want "SDBR/SDB RM -NZ RNTE, RZ FPCR" 00080001 00080001 00080001 00080001 +r 5CA0.10 +*Want "SDBR/SDB RM -NA RP, RM FPCR" 00080001 00080001 00080001 00080001 +r 5CB0.8 +*Want "SDBR/SDB RM -NA RFS FPCR" 00080001 00080001 +r 5CC0.10 +*Want "SDBR/SDB RM +TZ RNTE, RZ FPCR" 00080002 00080002 00080002 00080002 +r 5CD0.10 +*Want "SDBR/SDB RM +TZ RP, RM FPCR" 00080002 00080002 00080002 00080002 +r 5CE0.8 +*Want "SDBR/SDB RM +TZ RFS FPCR" 00080002 00080002 +r 5CF0.10 +*Want "SDBR/SDB RM -TZ RNTE, RZ FPCR" 00080001 00080001 00080001 00080001 +r 5D00.10 +*Want "SDBR/SDB RM -TZ RP, RM FPCR" 00080001 00080001 00080001 00080001 +r 5D10.8 +*Want "SDBR/SDB RM -TZ RFS FPCR" 00080001 00080001 +r 5D20.10 +*Want "SDBR/SDB RM +TA RNTE, RZ FPCR" 00080002 00080002 00080002 00080002 +r 5D30.10 +*Want "SDBR/SDB RM +TA RP, RM FPCR" 00080002 00080002 00080002 00080002 +r 5D40.8 +*Want "SDBR/SDB RM +TA RFS FPCR" 00080002 00080002 +r 5D50.10 +*Want "SDBR/SDB RM -TA RNTE, RZ FPCR" 00080001 00080001 00080001 00080001 +r 5D60.10 +*Want "SDBR/SDB RM -TA RP, RM FPCR" 00080001 00080001 00080001 00080001 +r 5D70.8 +*Want "SDBR/SDB RM -TA RFS FPCR" 00080001 00080001 + + +# Extended BFP non-finite test results +*Compare +r 8000.10 +*Want "SXBR NF -inf/-inf NT" 7FFF8000 00000000 00000000 00000000 +r 8010.10 +*Want "SXBR NF -inf/-inf Tr" FFFF0000 00000000 00000000 00000000 +r 8020.10 +*Want "SXBR NF -inf/-2.0 NT" FFFF0000 00000000 00000000 00000000 +r 8030.10 +*Want "SXBR NF -inf/-2.0 Tr" FFFF0000 00000000 00000000 00000000 +r 8040.10 +*Want "SXBR NF -inf/-Dnice NT" FFFF0000 00000000 00000000 00000000 +r 8050.10 +*Want "SXBR NF -inf/-Dnice Tr" FFFF0000 00000000 00000000 00000000 +r 8060.10 +*Want "SXBR NF -inf/-0 NT" FFFF0000 00000000 00000000 00000000 +r 8070.10 +*Want "SXBR NF -inf/-0 Tr" FFFF0000 00000000 00000000 00000000 +r 8080.10 +*Want "SXBR NF -inf/+0 NT" FFFF0000 00000000 00000000 00000000 +r 8090.10 +*Want "SXBR NF -inf/+0 Tr" FFFF0000 00000000 00000000 00000000 +r 80A0.10 +*Want "SXBR NF -inf/+Dnice NT" FFFF0000 00000000 00000000 00000000 +r 80B0.10 +*Want "SXBR NF -inf/+Dnice Tr" FFFF0000 00000000 00000000 00000000 +r 80C0.10 +*Want "SXBR NF -inf/+2.0 NT" FFFF0000 00000000 00000000 00000000 +r 80D0.10 +*Want "SXBR NF -inf/+2.0 Tr" FFFF0000 00000000 00000000 00000000 +r 80E0.10 +*Want "SXBR NF -inf/+inf NT" FFFF0000 00000000 00000000 00000000 +r 80F0.10 +*Want "SXBR NF -inf/+inf Tr" FFFF0000 00000000 00000000 00000000 +r 8100.10 +*Want "SXBR NF -inf/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 8110.10 +*Want "SXBR NF -inf/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 8120.10 +*Want "SXBR NF -inf/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 8130.10 +*Want "SXBR NF -inf/+SNaN Tr" FFFF0000 00000000 00000000 00000000 +r 8140.10 +*Want "SXBR NF -2.0/-inf NT" 7FFF0000 00000000 00000000 00000000 +r 8150.10 +*Want "SXBR NF -2.0/-inf Tr" 7FFF0000 00000000 00000000 00000000 +r 8160.10 +*Want "SXBR NF -2.0/-2.0 NT" 00000000 00000000 00000000 00000000 +r 8170.10 +*Want "SXBR NF -2.0/-2.0 Tr" 00000000 00000000 00000000 00000000 +r 8180.10 +*Want "SXBR NF -2.0/-Dnice NT" C0000000 00000000 00000000 00000000 +r 8190.10 +*Want "SXBR NF -2.0/-Dnice Tr" C0000000 00000000 00000000 00000000 +r 81A0.10 +*Want "SXBR NF -2.0/-0 NT" C0000000 00000000 00000000 00000000 +r 81B0.10 +*Want "SXBR NF -2.0/-0 Tr" C0000000 00000000 00000000 00000000 +r 81C0.10 +*Want "SXBR NF -2.0/+0 NT" C0000000 00000000 00000000 00000000 +r 81D0.10 +*Want "SXBR NF -2.0/+0 Tr" C0000000 00000000 00000000 00000000 +r 81E0.10 +*Want "SXBR NF -2.0/+Dnice NT" C0000000 00000000 00000000 00000000 +r 81F0.10 +*Want "SXBR NF -2.0/+Dnice Tr" C0000000 00000000 00000000 00000000 +r 8200.10 +*Want "SXBR NF -2.0/+2.0 NT" C0010000 00000000 00000000 00000000 +r 8210.10 +*Want "SXBR NF -2.0/+2.0 Tr" C0010000 00000000 00000000 00000000 +r 8220.10 +*Want "SXBR NF -2.0/+inf NT" FFFF0000 00000000 00000000 00000000 +r 8230.10 +*Want "SXBR NF -2.0/+inf Tr" FFFF0000 00000000 00000000 00000000 +r 8240.10 +*Want "SXBR NF -2.0/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 8250.10 +*Want "SXBR NF -2.0/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 8260.10 +*Want "SXBR NF -2.0/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 8270.10 +*Want "SXBR NF -2.0/+SNaN Tr" C0000000 00000000 00000000 00000000 +r 8280.10 +*Want "SXBR NF -Dnice/-inf NT" 7FFF0000 00000000 00000000 00000000 +r 8290.10 +*Want "SXBR NF -Dnice/-inf Tr" 7FFF0000 00000000 00000000 00000000 +r 82A0.10 +*Want "SXBR NF -Dnice/-2.0 NT" 40000000 00000000 00000000 00000000 +r 82B0.10 +*Want "SXBR NF -Dnice/-2.0 Tr" 40000000 00000000 00000000 00000000 +r 82C0.10 +*Want "SXBR NF -Dnice/-Dnice NT" 00000000 00000000 00000000 00000000 +r 82D0.10 +*Want "SXBR NF -Dnice/-Dnice Tr" 00000000 00000000 00000000 00000000 +r 82E0.10 +*Want "SXBR NF -Dnice/-0 NT" 80001000 00000000 00000000 00000000 +r 82F0.10 +*Want "SXBR NF -Dnice/-0 Tr" DFFD0000 00000000 00000000 00000000 +r 8300.10 +*Want "SXBR NF -Dnice/+0 NT" 80001000 00000000 00000000 00000000 +r 8310.10 +*Want "SXBR NF -Dnice/+0 Tr" DFFD0000 00000000 00000000 00000000 +r 8320.10 +*Want "SXBR NF -Dnice/+Dnice NT" 80002000 00000000 00000000 00000000 +r 8330.10 +*Want "SXBR NF -Dnice/+Dnice Tr" DFFE0000 00000000 00000000 00000000 +r 8340.10 +*Want "SXBR NF -Dnice/+2.0 NT" C0000000 00000000 00000000 00000000 +r 8350.10 +*Want "SXBR NF -Dnice/+2.0 Tr" C0000000 00000000 00000000 00000000 +r 8360.10 +*Want "SXBR NF -Dnice/+inf NT" FFFF0000 00000000 00000000 00000000 +r 8370.10 +*Want "SXBR NF -Dnice/+inf Tr" FFFF0000 00000000 00000000 00000000 +r 8380.10 +*Want "SXBR NF -Dnice/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 8390.10 +*Want "SXBR NF -Dnice/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 83A0.10 +*Want "SXBR NF -Dnice/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 83B0.10 +*Want "SXBR NF -Dnice/+SNaN Tr" 80001000 00000000 00000000 00000000 +r 83C0.10 +*Want "SXBR NF -0/-inf NT" 7FFF0000 00000000 00000000 00000000 +r 83D0.10 +*Want "SXBR NF -0/-inf Tr" 7FFF0000 00000000 00000000 00000000 +r 83E0.10 +*Want "SXBR NF -0/-2.0 NT" 40000000 00000000 00000000 00000000 +r 83F0.10 +*Want "SXBR NF -0/-2.0 Tr" 40000000 00000000 00000000 00000000 +r 8400.10 +*Want "SXBR NF -0/-Dnice NT" 00001000 00000000 00000000 00000000 +r 8410.10 +*Want "SXBR NF -0/-Dnice Tr" 5FFD0000 00000000 00000000 00000000 +r 8420.10 +*Want "SXBR NF -0/-0 NT" 00000000 00000000 00000000 00000000 +r 8430.10 +*Want "SXBR NF -0/-0 Tr" 00000000 00000000 00000000 00000000 +r 8440.10 +*Want "SXBR NF -0/+0 NT" 80000000 00000000 00000000 00000000 +r 8450.10 +*Want "SXBR NF -0/+0 Tr" 80000000 00000000 00000000 00000000 +r 8460.10 +*Want "SXBR NF -0/+Dnice NT" 80001000 00000000 00000000 00000000 +r 8470.10 +*Want "SXBR NF -0/+Dnice Tr" DFFD0000 00000000 00000000 00000000 +r 8480.10 +*Want "SXBR NF -0/+2.0 NT" C0000000 00000000 00000000 00000000 +r 8490.10 +*Want "SXBR NF -0/+2.0 Tr" C0000000 00000000 00000000 00000000 +r 84A0.10 +*Want "SXBR NF -0/+inf NT" FFFF0000 00000000 00000000 00000000 +r 84B0.10 +*Want "SXBR NF -0/+inf Tr" FFFF0000 00000000 00000000 00000000 +r 84C0.10 +*Want "SXBR NF -0/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 84D0.10 +*Want "SXBR NF -0/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 84E0.10 +*Want "SXBR NF -0/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 84F0.10 +*Want "SXBR NF -0/+SNaN Tr" 80000000 00000000 00000000 00000000 +r 8500.10 +*Want "SXBR NF +0/-inf NT" 7FFF0000 00000000 00000000 00000000 +r 8510.10 +*Want "SXBR NF +0/-inf Tr" 7FFF0000 00000000 00000000 00000000 +r 8520.10 +*Want "SXBR NF +0/-2.0 NT" 40000000 00000000 00000000 00000000 +r 8530.10 +*Want "SXBR NF +0/-2.0 Tr" 40000000 00000000 00000000 00000000 +r 8540.10 +*Want "SXBR NF +0/-Dnice NT" 00001000 00000000 00000000 00000000 +r 8550.10 +*Want "SXBR NF +0/-Dnice Tr" 5FFD0000 00000000 00000000 00000000 +r 8560.10 +*Want "SXBR NF +0/-0 NT" 00000000 00000000 00000000 00000000 +r 8570.10 +*Want "SXBR NF +0/-0 Tr" 00000000 00000000 00000000 00000000 +r 8580.10 +*Want "SXBR NF +0/+0 NT" 00000000 00000000 00000000 00000000 +r 8590.10 +*Want "SXBR NF +0/+0 Tr" 00000000 00000000 00000000 00000000 +r 85A0.10 +*Want "SXBR NF +0/+Dnice NT" 80001000 00000000 00000000 00000000 +r 85B0.10 +*Want "SXBR NF +0/+Dnice Tr" DFFD0000 00000000 00000000 00000000 +r 85C0.10 +*Want "SXBR NF +0/+2.0 NT" C0000000 00000000 00000000 00000000 +r 85D0.10 +*Want "SXBR NF +0/+2.0 Tr" C0000000 00000000 00000000 00000000 +r 85E0.10 +*Want "SXBR NF +0/+inf NT" FFFF0000 00000000 00000000 00000000 +r 85F0.10 +*Want "SXBR NF +0/+inf Tr" FFFF0000 00000000 00000000 00000000 +r 8600.10 +*Want "SXBR NF +0/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 8610.10 +*Want "SXBR NF +0/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 8620.10 +*Want "SXBR NF +0/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 8630.10 +*Want "SXBR NF +0/+SNaN Tr" 00000000 00000000 00000000 00000000 +r 8640.10 +*Want "SXBR NF +Dnice/-inf NT" 7FFF0000 00000000 00000000 00000000 +r 8650.10 +*Want "SXBR NF +Dnice/-inf Tr" 7FFF0000 00000000 00000000 00000000 +r 8660.10 +*Want "SXBR NF +Dnice/-2.0 NT" 40000000 00000000 00000000 00000000 +r 8670.10 +*Want "SXBR NF +Dnice/-2.0 Tr" 40000000 00000000 00000000 00000000 +r 8680.10 +*Want "SXBR NF +Dnice/-Dnice NT" 00002000 00000000 00000000 00000000 +r 8690.10 +*Want "SXBR NF +Dnice/-Dnice Tr" 5FFE0000 00000000 00000000 00000000 +r 86A0.10 +*Want "SXBR NF +Dnice/-0 NT" 00001000 00000000 00000000 00000000 +r 86B0.10 +*Want "SXBR NF +Dnice/-0 Tr" 5FFD0000 00000000 00000000 00000000 +r 86C0.10 +*Want "SXBR NF +Dnice/+0 NT" 00001000 00000000 00000000 00000000 +r 86D0.10 +*Want "SXBR NF +Dnice/+0 Tr" 5FFD0000 00000000 00000000 00000000 +r 86E0.10 +*Want "SXBR NF +Dnice/+Dnice NT" 00000000 00000000 00000000 00000000 +r 86F0.10 +*Want "SXBR NF +Dnice/+Dnice Tr" 00000000 00000000 00000000 00000000 +r 8700.10 +*Want "SXBR NF +Dnice/+2.0 NT" C0000000 00000000 00000000 00000000 +r 8710.10 +*Want "SXBR NF +Dnice/+2.0 Tr" C0000000 00000000 00000000 00000000 +r 8720.10 +*Want "SXBR NF +Dnice/+inf NT" FFFF0000 00000000 00000000 00000000 +r 8730.10 +*Want "SXBR NF +Dnice/+inf Tr" FFFF0000 00000000 00000000 00000000 +r 8740.10 +*Want "SXBR NF +Dnice/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 8750.10 +*Want "SXBR NF +Dnice/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 8760.10 +*Want "SXBR NF +Dnice/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 8770.10 +*Want "SXBR NF +Dnice/+SNaN Tr" 00001000 00000000 00000000 00000000 +r 8780.10 +*Want "SXBR NF +2.0/-inf NT" 7FFF0000 00000000 00000000 00000000 +r 8790.10 +*Want "SXBR NF +2.0/-inf Tr" 7FFF0000 00000000 00000000 00000000 +r 87A0.10 +*Want "SXBR NF +2.0/-2.0 NT" 40010000 00000000 00000000 00000000 +r 87B0.10 +*Want "SXBR NF +2.0/-2.0 Tr" 40010000 00000000 00000000 00000000 +r 87C0.10 +*Want "SXBR NF +2.0/-Dnice NT" 40000000 00000000 00000000 00000000 +r 87D0.10 +*Want "SXBR NF +2.0/-Dnice Tr" 40000000 00000000 00000000 00000000 +r 87E0.10 +*Want "SXBR NF +2.0/-0 NT" 40000000 00000000 00000000 00000000 +r 87F0.10 +*Want "SXBR NF +2.0/-0 Tr" 40000000 00000000 00000000 00000000 +r 8800.10 +*Want "SXBR NF +2.0/+0 NT" 40000000 00000000 00000000 00000000 +r 8810.10 +*Want "SXBR NF +2.0/+0 Tr" 40000000 00000000 00000000 00000000 +r 8820.10 +*Want "SXBR NF +2.0/+Dnice NT" 40000000 00000000 00000000 00000000 +r 8830.10 +*Want "SXBR NF +2.0/+Dnice Tr" 40000000 00000000 00000000 00000000 +r 8840.10 +*Want "SXBR NF +2.0/+2.0 NT" 00000000 00000000 00000000 00000000 +r 8850.10 +*Want "SXBR NF +2.0/+2.0 Tr" 00000000 00000000 00000000 00000000 +r 8860.10 +*Want "SXBR NF +2.0/+inf NT" FFFF0000 00000000 00000000 00000000 +r 8870.10 +*Want "SXBR NF +2.0/+inf Tr" FFFF0000 00000000 00000000 00000000 +r 8880.10 +*Want "SXBR NF +2.0/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 8890.10 +*Want "SXBR NF +2.0/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 88A0.10 +*Want "SXBR NF +2.0/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 88B0.10 +*Want "SXBR NF +2.0/+SNaN Tr" 40000000 00000000 00000000 00000000 +r 88C0.10 +*Want "SXBR NF +inf/-inf NT" 7FFF0000 00000000 00000000 00000000 +r 88D0.10 +*Want "SXBR NF +inf/-inf Tr" 7FFF0000 00000000 00000000 00000000 +r 88E0.10 +*Want "SXBR NF +inf/-2.0 NT" 7FFF0000 00000000 00000000 00000000 +r 88F0.10 +*Want "SXBR NF +inf/-2.0 Tr" 7FFF0000 00000000 00000000 00000000 +r 8900.10 +*Want "SXBR NF +inf/-Dnice NT" 7FFF0000 00000000 00000000 00000000 +r 8910.10 +*Want "SXBR NF +inf/-Dnice Tr" 7FFF0000 00000000 00000000 00000000 +r 8920.10 +*Want "SXBR NF +inf/-0 NT" 7FFF0000 00000000 00000000 00000000 +r 8930.10 +*Want "SXBR NF +inf/-0 Tr" 7FFF0000 00000000 00000000 00000000 +r 8940.10 +*Want "SXBR NF +inf/+0 NT" 7FFF0000 00000000 00000000 00000000 +r 8950.10 +*Want "SXBR NF +inf/+0 Tr" 7FFF0000 00000000 00000000 00000000 +r 8960.10 +*Want "SXBR NF +inf/+Dnice NT" 7FFF0000 00000000 00000000 00000000 +r 8970.10 +*Want "SXBR NF +inf/+Dnice Tr" 7FFF0000 00000000 00000000 00000000 +r 8980.10 +*Want "SXBR NF +inf/+2.0 NT" 7FFF0000 00000000 00000000 00000000 +r 8990.10 +*Want "SXBR NF +inf/+2.0 Tr" 7FFF0000 00000000 00000000 00000000 +r 89A0.10 +*Want "SXBR NF +inf/+inf NT" 7FFF8000 00000000 00000000 00000000 +r 89B0.10 +*Want "SXBR NF +inf/+inf Tr" 7FFF0000 00000000 00000000 00000000 +r 89C0.10 +*Want "SXBR NF +inf/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 89D0.10 +*Want "SXBR NF +inf/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 89E0.10 +*Want "SXBR NF +inf/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 89F0.10 +*Want "SXBR NF +inf/+SNaN Tr" 7FFF0000 00000000 00000000 00000000 +r 8A00.10 +*Want "SXBR NF -QNaN/-inf NT" FFFF8B00 00000000 00000000 00000000 +r 8A10.10 +*Want "SXBR NF -QNaN/-inf Tr" FFFF8B00 00000000 00000000 00000000 +r 8A20.10 +*Want "SXBR NF -QNaN/-2.0 NT" FFFF8B00 00000000 00000000 00000000 +r 8A30.10 +*Want "SXBR NF -QNaN/-2.0 Tr" FFFF8B00 00000000 00000000 00000000 +r 8A40.10 +*Want "SXBR NF -QNaN/-Dnice NT" FFFF8B00 00000000 00000000 00000000 +r 8A50.10 +*Want "SXBR NF -QNaN/-Dnice Tr" FFFF8B00 00000000 00000000 00000000 +r 8A60.10 +*Want "SXBR NF -QNaN/-0 NT" FFFF8B00 00000000 00000000 00000000 +r 8A70.10 +*Want "SXBR NF -QNaN/-0 Tr" FFFF8B00 00000000 00000000 00000000 +r 8A80.10 +*Want "SXBR NF -QNaN/+0 NT" FFFF8B00 00000000 00000000 00000000 +r 8A90.10 +*Want "SXBR NF -QNaN/+0 Tr" FFFF8B00 00000000 00000000 00000000 +r 8AA0.10 +*Want "SXBR NF -QNaN/+Dnice NT" FFFF8B00 00000000 00000000 00000000 +r 8AB0.10 +*Want "SXBR NF -QNaN/+Dnice Tr" FFFF8B00 00000000 00000000 00000000 +r 8AC0.10 +*Want "SXBR NF -QNaN/+2.0 NT" FFFF8B00 00000000 00000000 00000000 +r 8AD0.10 +*Want "SXBR NF -QNaN/+2.0 Tr" FFFF8B00 00000000 00000000 00000000 +r 8AE0.10 +*Want "SXBR NF -QNaN/+inf NT" FFFF8B00 00000000 00000000 00000000 +r 8AF0.10 +*Want "SXBR NF -QNaN/+inf Tr" FFFF8B00 00000000 00000000 00000000 +r 8B00.10 +*Want "SXBR NF -QNaN/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 8B10.10 +*Want "SXBR NF -QNaN/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 8B20.10 +*Want "SXBR NF -QNaN/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 8B30.10 +*Want "SXBR NF -QNaN/+SNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 8B40.10 +*Want "SXBR NF +SNaN/-inf NT" 7FFF8A00 00000000 00000000 00000000 +r 8B50.10 +*Want "SXBR NF +SNaN/-inf Tr" 7FFF0A00 00000000 00000000 00000000 +r 8B60.10 +*Want "SXBR NF +SNaN/-2.0 NT" 7FFF8A00 00000000 00000000 00000000 +r 8B70.10 +*Want "SXBR NF +SNaN/-2.0 Tr" 7FFF0A00 00000000 00000000 00000000 +r 8B80.10 +*Want "SXBR NF +SNaN/-Dnice NT" 7FFF8A00 00000000 00000000 00000000 +r 8B90.10 +*Want "SXBR NF +SNaN/-Dnice Tr" 7FFF0A00 00000000 00000000 00000000 +r 8BA0.10 +*Want "SXBR NF +SNaN/-0 NT" 7FFF8A00 00000000 00000000 00000000 +r 8BB0.10 +*Want "SXBR NF +SNaN/-0 Tr" 7FFF0A00 00000000 00000000 00000000 +r 8BC0.10 +*Want "SXBR NF +SNaN/+0 NT" 7FFF8A00 00000000 00000000 00000000 +r 8BD0.10 +*Want "SXBR NF +SNaN/+0 Tr" 7FFF0A00 00000000 00000000 00000000 +r 8BE0.10 +*Want "SXBR NF +SNaN/+Dnice NT" 7FFF8A00 00000000 00000000 00000000 +r 8BF0.10 +*Want "SXBR NF +SNaN/+Dnice Tr" 7FFF0A00 00000000 00000000 00000000 +r 8C00.10 +*Want "SXBR NF +SNaN/+2.0 NT" 7FFF8A00 00000000 00000000 00000000 +r 8C10.10 +*Want "SXBR NF +SNaN/+2.0 Tr" 7FFF0A00 00000000 00000000 00000000 +r 8C20.10 +*Want "SXBR NF +SNaN/+inf NT" 7FFF8A00 00000000 00000000 00000000 +r 8C30.10 +*Want "SXBR NF +SNaN/+inf Tr" 7FFF0A00 00000000 00000000 00000000 +r 8C40.10 +*Want "SXBR NF +SNaN/-QNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 8C50.10 +*Want "SXBR NF +SNaN/-QNaN Tr" 7FFF0A00 00000000 00000000 00000000 +r 8C60.10 +*Want "SXBR NF +SNaN/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 8C70.10 +*Want "SXBR NF +SNaN/+SNaN Tr" 7FFF0A00 00000000 00000000 00000000 + + +# Extended BFP non-finite test results - FPCR +*Compare +r 8D00.8 +*Want "SXBR NF -inf/-inf FPCR" 00800003 F8008003 +r 8D10.8 +*Want "SXBR NF -inf/-2.0 FPCR" 00000001 F8000001 +r 8D20.8 +*Want "SXBR NF -inf/-Dnice FPCR" 00000001 F8000001 +r 8D30.8 +*Want "SXBR NF -inf/-0 FPCR" 00000001 F8000001 +r 8D40.8 +*Want "SXBR NF -inf/+0 FPCR" 00000001 F8000001 +r 8D50.8 +*Want "SXBR NF -inf/+Dnice FPCR" 00000001 F8000001 +r 8D60.8 +*Want "SXBR NF -inf/+2.0 FPCR" 00000001 F8000001 +r 8D70.8 +*Want "SXBR NF -inf/+inf FPCR" 00000001 F8000001 +r 8D80.8 +*Want "SXBR NF -inf/-QNaN FPCR" 00000003 F8000003 +r 8D90.8 +*Want "SXBR NF -inf/+SNaN FPCR" 00800003 F8008003 +r 8DA0.8 +*Want "SXBR NF -2.0/-inf FPCR" 00000002 F8000002 +r 8DB0.8 +*Want "SXBR NF -2.0/-2.0 FPCR" 00000000 F8000000 +r 8DC0.8 +*Want "SXBR NF -2.0/-Dnice FPCR" 00080001 F8000C01 +r 8DD0.8 +*Want "SXBR NF -2.0/-0 FPCR" 00000001 F8000001 +r 8DE0.8 +*Want "SXBR NF -2.0/+0 FPCR" 00000001 F8000001 +r 8DF0.8 +*Want "SXBR NF -2.0/+Dnice FPCR" 00080001 F8000801 +r 8E00.8 +*Want "SXBR NF -2.0/+2.0 FPCR" 00000001 F8000001 +r 8E10.8 +*Want "SXBR NF -2.0/+inf FPCR" 00000001 F8000001 +r 8E20.8 +*Want "SXBR NF -2.0/-QNaN FPCR" 00000003 F8000003 +r 8E30.8 +*Want "SXBR NF -2.0/+SNaN FPCR" 00800003 F8008003 +r 8E40.8 +*Want "SXBR NF -Dnice/-inf FPCR" 00000002 F8000002 +r 8E50.8 +*Want "SXBR NF -Dnice/-2.0 FPCR" 00080002 F8000C02 +r 8E60.8 +*Want "SXBR NF -Dnice/-Dnice FPCR" 00000000 F8000000 +r 8E70.8 +*Want "SXBR NF -Dnice/-0 FPCR" 00000001 F8001001 +r 8E80.8 +*Want "SXBR NF -Dnice/+0 FPCR" 00000001 F8001001 +r 8E90.8 +*Want "SXBR NF -Dnice/+Dnice FPCR" 00000001 F8001001 +r 8EA0.8 +*Want "SXBR NF -Dnice/+2.0 FPCR" 00080001 F8000801 +r 8EB0.8 +*Want "SXBR NF -Dnice/+inf FPCR" 00000001 F8000001 +r 8EC0.8 +*Want "SXBR NF -Dnice/-QNaN FPCR" 00000003 F8000003 +r 8ED0.8 +*Want "SXBR NF -Dnice/+SNaN FPCR" 00800003 F8008003 +r 8EE0.8 +*Want "SXBR NF -0/-inf FPCR" 00000002 F8000002 +r 8EF0.8 +*Want "SXBR NF -0/-2.0 FPCR" 00000002 F8000002 +r 8F00.8 +*Want "SXBR NF -0/-Dnice FPCR" 00000002 F8001002 +r 8F10.8 +*Want "SXBR NF -0/-0 FPCR" 00000000 F8000000 +r 8F20.8 +*Want "SXBR NF -0/+0 FPCR" 00000000 F8000000 +r 8F30.8 +*Want "SXBR NF -0/+Dnice FPCR" 00000001 F8001001 +r 8F40.8 +*Want "SXBR NF -0/+2.0 FPCR" 00000001 F8000001 +r 8F50.8 +*Want "SXBR NF -0/+inf FPCR" 00000001 F8000001 +r 8F60.8 +*Want "SXBR NF -0/-QNaN FPCR" 00000003 F8000003 +r 8F70.8 +*Want "SXBR NF -0/+SNaN FPCR" 00800003 F8008003 +r 8F80.8 +*Want "SXBR NF +0/-inf FPCR" 00000002 F8000002 +r 8F90.8 +*Want "SXBR NF +0/-2.0 FPCR" 00000002 F8000002 +r 8FA0.8 +*Want "SXBR NF +0/-Dnice FPCR" 00000002 F8001002 +r 8FB0.8 +*Want "SXBR NF +0/-0 FPCR" 00000000 F8000000 +r 8FC0.8 +*Want "SXBR NF +0/+0 FPCR" 00000000 F8000000 +r 8FD0.8 +*Want "SXBR NF +0/+Dnice FPCR" 00000001 F8001001 +r 8FE0.8 +*Want "SXBR NF +0/+2.0 FPCR" 00000001 F8000001 +r 8FF0.8 +*Want "SXBR NF +0/+inf FPCR" 00000001 F8000001 +r 9000.8 +*Want "SXBR NF +0/-QNaN FPCR" 00000003 F8000003 +r 9010.8 +*Want "SXBR NF +0/+SNaN FPCR" 00800003 F8008003 +r 9020.8 +*Want "SXBR NF +Dnice/-inf FPCR" 00000002 F8000002 +r 9030.8 +*Want "SXBR NF +Dnice/-2.0 FPCR" 00080002 F8000802 +r 9040.8 +*Want "SXBR NF +Dnice/-Dnice FPCR" 00000002 F8001002 +r 9050.8 +*Want "SXBR NF +Dnice/-0 FPCR" 00000002 F8001002 +r 9060.8 +*Want "SXBR NF +Dnice/+0 FPCR" 00000002 F8001002 +r 9070.8 +*Want "SXBR NF +Dnice/+Dnice FPCR" 00000000 F8000000 +r 9080.8 +*Want "SXBR NF +Dnice/+2.0 FPCR" 00080001 F8000C01 +r 9090.8 +*Want "SXBR NF +Dnice/+inf FPCR" 00000001 F8000001 +r 90A0.8 +*Want "SXBR NF +Dnice/-QNaN FPCR" 00000003 F8000003 +r 90B0.8 +*Want "SXBR NF +Dnice/+SNaN FPCR" 00800003 F8008003 +r 90C0.8 +*Want "SXBR NF +2.0/-inf FPCR" 00000002 F8000002 +r 90D0.8 +*Want "SXBR NF +2.0/-2.0 FPCR" 00000002 F8000002 +r 90E0.8 +*Want "SXBR NF +2.0/-Dnice FPCR" 00080002 F8000802 +r 90F0.8 +*Want "SXBR NF +2.0/-0 FPCR" 00000002 F8000002 +r 9100.8 +*Want "SXBR NF +2.0/+0 FPCR" 00000002 F8000002 +r 9110.8 +*Want "SXBR NF +2.0/+Dnice FPCR" 00080002 F8000C02 +r 9120.8 +*Want "SXBR NF +2.0/+2.0 FPCR" 00000000 F8000000 +r 9130.8 +*Want "SXBR NF +2.0/+inf FPCR" 00000001 F8000001 +r 9140.8 +*Want "SXBR NF +2.0/-QNaN FPCR" 00000003 F8000003 +r 9150.8 +*Want "SXBR NF +2.0/+SNaN FPCR" 00800003 F8008003 +r 9160.8 +*Want "SXBR NF +inf/-inf FPCR" 00000002 F8000002 +r 9170.8 +*Want "SXBR NF +inf/-2.0 FPCR" 00000002 F8000002 +r 9180.8 +*Want "SXBR NF +inf/-Dnice FPCR" 00000002 F8000002 +r 9190.8 +*Want "SXBR NF +inf/-0 FPCR" 00000002 F8000002 +r 91A0.8 +*Want "SXBR NF +inf/+0 FPCR" 00000002 F8000002 +r 91B0.8 +*Want "SXBR NF +inf/+Dnice FPCR" 00000002 F8000002 +r 91C0.8 +*Want "SXBR NF +inf/+2.0 FPCR" 00000002 F8000002 +r 91D0.8 +*Want "SXBR NF +inf/+inf FPCR" 00800003 F8008003 +r 91E0.8 +*Want "SXBR NF +inf/-QNaN FPCR" 00000003 F8000003 +r 91F0.8 +*Want "SXBR NF +inf/+SNaN FPCR" 00800003 F8008003 +r 9200.8 +*Want "SXBR NF -QNaN/-inf FPCR" 00000003 F8000003 +r 9210.8 +*Want "SXBR NF -QNaN/-2.0 FPCR" 00000003 F8000003 +r 9220.8 +*Want "SXBR NF -QNaN/-Dnice FPCR" 00000003 F8000003 +r 9230.8 +*Want "SXBR NF -QNaN/-0 FPCR" 00000003 F8000003 +r 9240.8 +*Want "SXBR NF -QNaN/+0 FPCR" 00000003 F8000003 +r 9250.8 +*Want "SXBR NF -QNaN/+Dnice FPCR" 00000003 F8000003 +r 9260.8 +*Want "SXBR NF -QNaN/+2.0 FPCR" 00000003 F8000003 +r 9270.8 +*Want "SXBR NF -QNaN/+inf FPCR" 00000003 F8000003 +r 9280.8 +*Want "SXBR NF -QNaN/-QNaN FPCR" 00000003 F8000003 +r 9290.8 +*Want "SXBR NF -QNaN/+SNaN FPCR" 00800003 F8008003 +r 92A0.8 +*Want "SXBR NF +SNaN/-inf FPCR" 00800003 F8008003 +r 92B0.8 +*Want "SXBR NF +SNaN/-2.0 FPCR" 00800003 F8008003 +r 92C0.8 +*Want "SXBR NF +SNaN/-Dnice FPCR" 00800003 F8008003 +r 92D0.8 +*Want "SXBR NF +SNaN/-0 FPCR" 00800003 F8008003 +r 92E0.8 +*Want "SXBR NF +SNaN/+0 FPCR" 00800003 F8008003 +r 92F0.8 +*Want "SXBR NF +SNaN/+Dnice FPCR" 00800003 F8008003 +r 9300.8 +*Want "SXBR NF +SNaN/+2.0 FPCR" 00800003 F8008003 +r 9310.8 +*Want "SXBR NF +SNaN/+inf FPCR" 00800003 F8008003 +r 9320.8 +*Want "SXBR NF +SNaN/-QNaN FPCR" 00800003 F8008003 +r 9330.8 +*Want "SXBR NF +SNaN/+SNaN FPCR" 00800003 F8008003 + + +# Extended BFP finite test results +*Compare +r 9400.10 +*Want "SXBR F Ovfl NT" 7FFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 9410.10 +*Want "SXBR F Ovfl Tr" 7FFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 9420.10 +*Want "SXBR F Ufl 1 NT" 0000FFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 9430.10 +*Want "SXBR F Ufl 1 Tr" 6000FFFF FFFFFFFF FFFFFFFF FFFFFFFE +r 9440.10 +*Want "SXBR F Ufl 2 NT" 000070F1 00000000 00000000 00000000 +r 9450.10 +*Want "SXBR F Ufl 2 Tr" 5FFFC3C4 00000000 00000000 00000000 +r 9460.10 +*Want "SXBR F Nmin NT" 00010000 00000000 00000000 00000000 +r 9470.10 +*Want "SXBR F Nmin Tr" 00010000 00000000 00000000 00000000 +r 9480.10 +*Want "SXBR F Incr NT" 3FFF0000 00000000 00000000 00000000 +r 9490.10 +*Want "SXBR F Incr Tr" 3FFF0000 00000000 00000000 00000000 +r 94A0.10 +*Want "SXBR F Trun NT" 3FFEFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 94B0.10 +*Want "SXBR F Trun Tr" 3FFEFFFF FFFFFFFF FFFFFFFF FFFFFFFF + + +# Extended BFP non-finite test results - FPCR +*Compare +r 9600.8 +*Want "SXBR F Ovfl FPCR" 00000003 F8000003 +r 9610.8 +*Want "SXBR F Ufl 1 FPCR" 00000002 F8001002 +r 9620.8 +*Want "SXBR F Ufl 2 FPCR" 00000002 F8001002 +r 9630.8 +*Want "SXBR F Nmin FPCR" 00000002 F8000002 +r 9640.8 +*Want "SXBR F Incr FPCR" 00080002 F8000C02 +r 9650.8 +*Want "SXBR F Trun FPCR" 00080002 F8000802 + + +# Extended BFP rounding mode test results +*Compare +r 9700.10 +*Want "SXBR RM +NZ RNTE" 3FFEFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 9710.10 +*Want "SXBR RM +NZ RZ" 3FFEFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 9720.10 +*Want "SXBR RM +NZ RP" 3FFF0000 00000000 00000000 00000000 +r 9730.10 +*Want "SXBR RM +NZ RM" 3FFEFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 9740.10 +*Want "SXBR RM +NZ RFS" 3FFEFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 9750.10 +*Want "SXBR RM -NZ RNTE" BFFEFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 9760.10 +*Want "SXBR RM -NZ RZ" BFFEFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 9770.10 +*Want "SXBR RM -NZ RP" BFFEFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 9780.10 +*Want "SXBR RM -NZ RM" BFFF0000 00000000 00000000 00000000 +r 9790.10 +*Want "SXBR RM -NZ RFS" BFFEFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 97A0.10 +*Want "SXBR RM +NA RNTE" 3FFF0000 00000000 00000000 00000000 +r 97B0.10 +*Want "SXBR RM +NA RZ" 3FFEFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 97C0.10 +*Want "SXBR RM +NA RP" 3FFF0000 00000000 00000000 00000000 +r 97D0.10 +*Want "SXBR RM +NA RM" 3FFEFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 97E0.10 +*Want "SXBR RM +NA RFS" 3FFEFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 97F0.10 +*Want "SXBR RM -NA RNTE" BFFF0000 00000000 00000000 00000000 +r 9800.10 +*Want "SXBR RM -NA RZ" BFFEFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 9810.10 +*Want "SXBR RM -NA RP" BFFEFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 9820.10 +*Want "SXBR RM -NA RM" BFFF0000 00000000 00000000 00000000 +r 9830.10 +*Want "SXBR RM -NA RFS" BFFEFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 9840.10 +*Want "SXBR RM +TZ RNTE" 3FFEFFFF FFFFFFFF FFFFFFFF FFFFFFFE +r 9850.10 +*Want "SXBR RM +TZ RZ" 3FFEFFFF FFFFFFFF FFFFFFFF FFFFFFFE +r 9860.10 +*Want "SXBR RM +TZ RP" 3FFEFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 9870.10 +*Want "SXBR RM +TZ RM" 3FFEFFFF FFFFFFFF FFFFFFFF FFFFFFFE +r 9880.10 +*Want "SXBR RM +TZ RFS" 3FFEFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 9890.10 +*Want "SXBR RM -TZ RNTE" BFFEFFFF FFFFFFFF FFFFFFFF FFFFFFFE +r 98A0.10 +*Want "SXBR RM -TZ RZ" BFFEFFFF FFFFFFFF FFFFFFFF FFFFFFFE +r 98B0.10 +*Want "SXBR RM -TZ RP" BFFEFFFF FFFFFFFF FFFFFFFF FFFFFFFE +r 98C0.10 +*Want "SXBR RM -TZ RM" BFFEFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 98D0.10 +*Want "SXBR RM -TZ RFS" BFFEFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 98E0.10 +*Want "SXBR RM +TA RNTE" 3FFF0000 00000000 00000000 00000000 +r 98F0.10 +*Want "SXBR RM +TA RZ" 3FFEFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 9900.10 +*Want "SXBR RM +TA RP" 3FFF0000 00000000 00000000 00000000 +r 9910.10 +*Want "SXBR RM +TA RM" 3FFEFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 9920.10 +*Want "SXBR RM +TA RFS" 3FFEFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 9930.10 +*Want "SXBR RM -TA RNTE" BFFF0000 00000000 00000000 00000000 +r 9940.10 +*Want "SXBR RM -TA RZ" BFFEFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 9950.10 +*Want "SXBR RM -TA RP" BFFEFFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 9960.10 +*Want "SXBR RM -TA RM" BFFF0000 00000000 00000000 00000000 +r 9970.10 +*Want "SXBR RM -TA RFS" BFFEFFFF FFFFFFFF FFFFFFFF FFFFFFFF + + +# Extended BFP rounding mode test results - FPCR +*Compare +r 9C00.10 +*Want "SXBR RM +NZ RNTE, RZ,RP,RM FPCR" 00080002 00080002 00080002 00080002 +r 9C10.4 +*Want "SXBR RM +NZ RFS FPCR" 00080002 +r 9C20.10 +*Want "SXBR RM -NZ RNTE, RZ,RP,RM FPCR" 00080001 00080001 00080001 00080001 +r 9C30.4 +*Want "SXBR RM -NZ RFS FPCR" 00080001 +r 9C40.10 +*Want "SXBR RM +NA RNTE, RZ,RP,RM FPCR" 00080002 00080002 00080002 00080002 +r 9C50.4 +*Want "SXBR RM +NA RFS FPCR" 00080002 +r 9C60.10 +*Want "SXBR RM -NA RNTE, RZ,RP,RM FPCR" 00080001 00080001 00080001 00080001 +r 9C70.4 +*Want "SXBR RM -NA RFS FPCR" 00080001 +r 9C80.10 +*Want "SXBR RM +TZ RNTE, RZ,RP,RM FPCR" 00080002 00080002 00080002 00080002 +r 9C90.4 +*Want "SXBR RM +TZ RFS FPCR" 00080002 +r 9CA0.10 +*Want "SXBR RM -TZ RNTE, RZ,RP,RM FPCR" 00080001 00080001 00080001 00080001 +r 9CB0.4 +*Want "SXBR RM -TZ RFS FPCR" 00080001 +r 9CC0.10 +*Want "SXBR RM +TA RNTE, RZ,RP,RM FPCR" 00080002 00080002 00080002 00080002 +r 9CD0.4 +*Want "SXBR RM +TA RFS FPCR" 00080002 +r 9CE0.10 +*Want "SXBR RM -TA RNTE, RZ,RP,RM FPCR" 00080001 00080001 00080001 00080001 +r 9CF0.4 +*Want "SXBR RM -TA RFS FPCR" 00080001 + + + + + +*Done + diff --git a/tests/bfp-019-multiply.asm b/tests/bfp-019-multiply.asm new file mode 100644 index 000000000..34581ce3f --- /dev/null +++ b/tests/bfp-019-multiply.asm @@ -0,0 +1,1372 @@ + TITLE 'bfp-019-multiply.asm: Test IEEE Multiply' +*********************************************************************** +* +*Testcase IEEE MULTIPLY +* Test case capability includes IEEE exceptions trappable and +* otherwise. Test results, FPCR flags, the Condition code, and any +* DXC are saved for all tests. +* +* The fused multiply operations are not included in this test program, +* nor are the multiply to longer precision instructions. The former +* are excluded to keep test case complexity manageable, and latter +* because they require a slightly different testing profile. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* bfp-019-multiply.asm +* +* This assembly-language source file is part of the +* Hercules Decimal Floating Point Validation Package +* by Stephen R. Orso +* +* Copyright 2016 by Stephen R Orso. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* +* 3. The name of the author may not be used to endorse or promote +* products derived from this software without specific prior written +* permission. +* +* DISCLAMER: THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* HOLDER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* Tests the following three conversion instructions +* MULTIPLY (short BFP, RRE) +* MULTIPLY (long BFP, RRE) +* MULTIPLY (extended BFP, RRE) +* MULTIPLY (short BFP, RXE) +* MULTIPLY (long BFP, RXE) +* +* Test data is compiled into this program. The test script that runs +* this program can provide alternative test data through Hercules R +* commands. +* +* Test Case Order +* 1) Short BFP basic tests, including traps and NaN propagation +* 2) Short BFP finite number tests, incl. traps and scaling +* 3) Short BFP FPC-controlled rounding mode exhaustive tests +* 4) Long BFP basic tests, including traps and NaN propagation +* 5) Long BFP finite number tests, incl. traps and scaling +* 6) Long BFP FPC-controlled rounding mode exhaustive tests +* 7) Extended BFP basic tests, including traps and NaN propagation +* 8) Extended BFP finite number tests, incl. traps and scaling +* 9) Extended BFP FPC-controlled rounding mode exhaustive tests +* +* Three input test sets are provided each for short, long, and +* extended BFP inputs. Test values are the same for each precision +* for most tests. Overflow and underflow each require precision- +* dependent test values. +* +* Also tests the following floating point support instructions +* LOAD (Short) +* LOAD (Long) +* LFPC (Load Floating Point Control Register) +* SRNMB (Set BFP Rounding Mode 3-bit) +* STORE (Short) +* STORE (Long) +* STFPC (Store Floating Point Control Register) +* +*********************************************************************** + SPACE 2 + MACRO + PADCSECT &ENDLABL +.* +.* Macro to pad the CSECT to include result data areas if this test +.* program is not being assembled using asma. asma generates a core +.* image that is loaded by the loadcore command, and because the +.* core image is a binary stored in Github, it makes sense to make +.* this small effort to keep the core image small. +.* + AIF (D'&ENDLABL).GOODPAD + MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + MNOTE *,'No CSECT padding performed' + MEXIT +.* +.GOODPAD ANOP Label valid. See if we're on asma + AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + ORG &ENDLABL-1 Not ASMA. Pad CSECT + MEXIT +.* +.NOPAD ANOP + MNOTE *,'asma detected; no CSECT padding performed' + MEND +* +* Note: for compatibility with the z/CMS test rig, do not change +* or use R11, R14, or R15. Everything else is fair game. +* +BFPMUL START 0 +STRTLABL EQU * +R0 EQU 0 Work register for cc extraction +R1 EQU 1 +R2 EQU 2 Holds count of test input values +R3 EQU 3 Points to next test input value(s) +R4 EQU 4 Rounding tests inner loop control +R5 EQU 5 Rounding tests outer loop control +R6 EQU 6 Rounding tests top of inner loop +R7 EQU 7 Pointer to next result value(s) +R8 EQU 8 Pointer to next FPCR result +R9 EQU 9 Rounding tests top of outer loop +R10 EQU 10 Pointer to test address list +R11 EQU 11 **Reserved for z/CMS test rig +R12 EQU 12 Holds number of test cases in set +R13 EQU 13 Mainline return address +R14 EQU 14 **Return address for z/CMS test rig +R15 EQU 15 **Base register on z/CMS or Hyperion +* +* Floating Point Register equates to keep the cross reference clean +* +FPR0 EQU 0 +FPR1 EQU 1 +FPR2 EQU 2 +FPR3 EQU 3 +FPR4 EQU 4 +FPR5 EQU 5 +FPR6 EQU 6 +FPR7 EQU 7 +FPR8 EQU 8 +FPR9 EQU 9 +FPR10 EQU 10 +FPR11 EQU 11 +FPR12 EQU 12 +FPR13 EQU 13 +FPR14 EQU 14 +FPR15 EQU 15 +* + USING *,R15 +* +* Above works on real iron (R15=0 after sysclear) +* and in z/CMS (R15 points to start of load module) +* + SPACE 2 +*********************************************************************** +* +* Low core definitions, Restart PSW, and Program Check Routine. +* +*********************************************************************** + SPACE 2 + ORG STRTLABL+X'8E' Program check interrution code +PCINTCD DS H +* +PCOLDPSW EQU STRTLABL+X'150' z/Arch Program check old PSW +* + ORG STRTLABL+X'1A0' z/Arch Restart PSW + DC X'0000000180000000',AD(START) +* + ORG STRTLABL+X'1D0' z/Arch Program check old PSW + DC X'0000000000000000',AD(PROGCHK) +* +* Program check routine. If Data Exception, continue execution at +* the instruction following the program check. Otherwise, hard wait. +* No need to collect data. All interesting DXC stuff is captured +* in the FPCR. +* + ORG STRTLABL+X'200' +PROGCHK DS 0H Program check occured... + CLI PCINTCD+1,X'07' Data Exception? + JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) + LPSWE PCOLDPSW ..yes, resume program execution +PCNOTDTA DS 0H + LTR R14,R14 Return address provided? + BNZR R14 Yes, return to z/CMS test rig. + LPSWE HARDWAIT Not data exception, enter disabled wait + EJECT +*********************************************************************** +* +* Main program. Enable Advanced Floating Point, process test cases. +* +*********************************************************************** + SPACE 2 +START DS 0H + STCTL R0,R0,CTLR0 Store CR0 to enable AFP + OI CTLR0+1,X'04' Turn on AFP bit + LCTL R0,R0,CTLR0 Reload updated CR0 +* + LA R10,SHORTNF Point to short BFP non-finite inputs + BAS R13,SBFPNF Multiply short BFP non-finites + LA R10,SHORTF Point to short BFP finite inputs + BAS R13,SBFPF Multiply short BFP finites + LA R10,RMSHORTS Point to short BFP rounding mode tests + BAS R13,SBFPRM Multiply short BFP for rounding tests +* + LA R10,LONGNF Point to long BFP non-finite inputs + BAS R13,LBFPNF Multiply long BFP non-finites + LA R10,LONGF Point to long BFP finite inputs + BAS R13,LBFPF Multiply long BFP finites + LA R10,RMLONGS Point to long BFP rounding mode tests + BAS R13,LBFPRM Multiply long BFP for rounding tests +* + LA R10,XTNDNF Point to extended BFP non-finite inputs + BAS R13,XBFPNF Multiply extended BFP non-finites + LA R10,XTNDF Point to ext'd BFP finite inputs + BAS R13,XBFPF Multiply ext'd BFP finites + LA R10,RMXTNDS Point to ext'd BFP rounding mode tests + BAS R13,XBFPRM Multiply ext'd BFP for rounding tests +* + LTR R14,R14 Return address provided? + BNZR R14 ..Yes, return to z/CMS test rig. + LPSWE WAITPSW All done +* + DS 0D Ensure correct alignment for psw +WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end +* +CTLR0 DS F +FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags +* +* Input values parameter list, four fullwords for each test data set +* 1) Count, +* 2) Address of inputs, +* 3) Address to place results, and +* 4) Address to place DXC/Flags/cc values. +* + ORG STRTLABL+X'300' Enable run-time replacement +SHORTNF DS 0F Input pairs for short BFP non-finite tests + DC A(SBFPNFCT) + DC A(SBFPNFIN) + DC A(SBFPNFOT) + DC A(SBFPNFFL) +* +SHORTF DS 0F Input pairs for short BFP finite tests + DC A(SBFPCT) + DC A(SBFPIN) + DC A(SBFPOUT) + DC A(SBFPFLGS) +* +RMSHORTS DS 0F Input pairs for short BFP rounding testing + DC A(SBFPRMCT) + DC A(SBFPINRM) + DC A(SBFPRMO) + DC A(SBFPRMOF) +* +LONGNF DS 0F Input pairs for long BFP non-finite testing + DC A(LBFPNFCT) + DC A(LBFPNFIN) + DC A(LBFPNFOT) + DC A(LBFPNFFL) +* +LONGF DS 0F Input pairs for long BFP finite testing + DC A(LBFPCT) + DC A(LBFPIN) + DC A(LBFPOUT) + DC A(LBFPFLGS) +* +RMLONGS DS 0F Input pairs for long BFP rounding testing + DC A(LBFPRMCT) + DC A(LBFPINRM) + DC A(LBFPRMO) + DC A(LBFPRMOF) +* +XTNDNF DS 0F Inputs for ext'd BFP non-finite testing + DC A(XBFPNFCT) + DC A(XBFPNFIN) + DC A(XBFPNFOT) + DC A(XBFPNFFL) +* +XTNDF DS 0F Inputs for ext'd BFP finite testing + DC A(XBFPCT) + DC A(XBFPIN) + DC A(XBFPOUT) + DC A(XBFPFLGS) +* +RMXTNDS DS 0F Inputs for ext'd BFP non-finite testing + DC A(XBFPRMCT) + DC A(XBFPINRM) + DC A(XBFPRMO) + DC A(XBFPRMOF) +* + EJECT +*********************************************************************** +* +* Perform Multiply using provided short BFP inputs. This set of tests +* checks NaN propagation, operations on values that are not finite +* numbers, and other basic tests. This set generates results that can +* be validated against Figure 19-23 on page 19-28 of SA22-7832-10. +* +* Four results are generated for each input: one RRE with all +* exceptions non-trappable, a second RRE with all exceptions trappable, +* a third RXE with all exceptions non-trappable, a fourth RXE with all +* exceptions trappable, +* +* The product and FPC contents are stored for each result. +* +*********************************************************************** + SPACE 2 +SBFPNF DS 0H BFP Short non-finite values tests + LM R2,R3,0(R10) Get count and addr of multiplicand values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LM R4,R5,0(R10) Get count and start of multiplier values +* ..which are the same as the multiplicands + BASR R6,0 Set top of inner loop +* + LE FPR8,0(,R3) Get short BFP multiplicand + LE FPR1,0(,R5) Get short BFP multiplier + LFPC FPCREGNT Set exceptions non-trappable + MEEBR FPR8,FPR1 Multiply short FPR8 by FPR1 RRE + STE FPR8,0(,R7) Store short BFP product + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LE FPR8,0(,R3) Get short BFP multiplicand + LE FPR1,0(,R5) Get short BFP multiplier + LFPC FPCREGTR Set exceptions trappable + MEEBR FPR8,FPR1 Multiply short FPR8 by FPR1 RRE + STE FPR8,4(,R7) Store short BFP product + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LE FPR8,0(,R3) Get short BFP multiplicand + LE FPR1,0(,R5) Get short BFP multiplier + LFPC FPCREGNT Set exceptions non-trappable + MEEB FPR8,0(,R5) Multiply short FPR8 by multiplier RXE + STE FPR8,8(,R7) Store short BFP product + STFPC 8(R8) Store resulting FPCR flags and DXC +* + LE FPR8,0(,R3) Get short BFP multiplicand + LFPC FPCREGTR Set exceptions trappable + MEEB FPR8,0(,R5) Multiply short FPR8 by multiplier RXE + STE FPR8,12(,R7) Store short BFP product + STFPC 12(R8) Store resulting FPCR flags and DXC +* + LA R5,4(,R5) Point to next multiplier value + LA R7,4*4(,R7) Point to next Multiply result area + LA R8,4*4(,R8) Point to next Multiply FPCR area + BCTR R4,R6 Loop through right-hand values +* + LA R3,4(,R3) Point to next input multiplicand + BCTR R2,R12 Loop through left-hand values + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Multiply using provided short BFP input pairs. This set of +* tests triggers IEEE exceptions Overflow, Underflow, and Inexact and +* collects both trap and non-trap results. +* +* Four results are generated for each input: one RRE with all +* exceptions non-trappable, a second RRE with all exceptions trappable, +* a third RXE with all exceptions non-trappable, a fourth RXE with all +* exceptions trappable, +* +* The product and FPC contents are stored for each result. +* +*********************************************************************** + SPACE 2 +SBFPF LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LFPC FPCREGNT Set exceptions non-trappable + LE FPR8,0(,R3) Get short BFP multiplicand + LE FPR1,4(,R3) Get short BFP multiplier + MEEBR FPR8,FPR1 Multiply short FPR8 by FPR1 RRE + STE FPR8,0(,R7) Store short BFP product + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LE FPR8,0(,R3) Reload short BFP multiplicand +* ..multiplier is still in FPR1 + MEEBR FPR8,FPR1 Multiply short FPR8 by FPR1 RRE + STE FPR8,4(,R7) Store short BFP product + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable + LE FPR8,0(,R3) Reload short BFP multiplicand + MEEB FPR8,4(,R3) Multiply short FPR8 by multiplier RXE + STE FPR8,8(,R7) Store short BFP product + STFPC 8(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LE FPR8,0(,R3) Reload short BFP multiplicand + MEEB FPR8,4(,R3) Multiply short FPR8 by multiplier RXE + STE FPR8,12(,R7) Store short BFP product + STFPC 12(R8) Store resulting FPCR flags and DXC +* + LA R3,2*4(,R3) Point to next input value pair + LA R7,4*4(,R7) Point to next product result set + LA R8,4*4(,R8) Point to next FPCR result set + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Multiply using provided short BFP input pairs. This set of +* tests exhaustively tests all rounding modes available for Multiply. +* The rounding mode can only be specified in the FPC. +* +* All five FPC rounding modes are tested because the preceeding tests, +* using rounding mode RNTE, do not often create results that require +* rounding. +* +* Two results are generated for each input and rounding mode: one RRE +* and one RXE. Traps are disabled for all rounding mode tests. +* +* The product and FPC contents are stored for each test. +* +*********************************************************************** + SPACE 2 +SBFPRM LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + XR R1,R1 Zero register 1 for use in IC/STC/indexing + BASR R12,0 Set top of test case loop + + LA R5,FPCMCT Get count of FPC modes to be tested + BASR R9,0 Set top of rounding mode outer loop +* + IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 0(R1) Set FPC Rounding Mode + LE FPR8,0(,R3) Get short BFP multiplicand + LE FPR1,4(,R3) Get short BFP multiplier + MEEBR FPR8,FPR1 Multiply short FPR8 by FPR1 RRE + STE FPR8,0(,R7) Store short BFP product + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 0(R1) Set FPC Rounding Mode + LE FPR8,0(,R3) Get short BFP multiplicand + MEEB FPR8,4(,R3) Multiply short FPR8 by multiplier RXE + STE FPR8,4(,R7) Store short BFP product + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LA R7,2*4(,R7) Point to next product result set + LA R8,2*4(,R8) Point to next FPCR result area +* + BCTR R5,R9 Iterate to next FPC mode for this input +* +* End of FPC modes to be tested. Advance to next test case. We will +* skip eight bytes of result area so that each set of five result +* value pairs starts at a memory address ending in zero for the +* convenience of memory dump review. +* + LA R3,2*4(,R3) Point to next input value pair + LA R7,8(,R7) Skip to start of next result set + LA R8,8(,R8) Skip to start of next FPCR result set + BCTR R2,R12 Advance to the next input pair +* + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Multiply using provided long BFP inputs. This set of tests +* checks NaN propagation, operations on values that are not finite +* numbers, and other basic tests. This set generates results that can +* be validated against Figure 19-23 on page 19-28 of SA22-7832-10. +* +* Four results are generated for each input: one RRE with all +* exceptions non-trappable, a second RRE with all exceptions trappable, +* a third RXE with all exceptions non-trappable, a fourth RXE with all +* exceptions trappable, +* +* The product and FPC contents are stored for each result. +* +*********************************************************************** + SPACE 2 +LBFPNF DS 0H BFP long non-finite values tests + LM R2,R3,0(R10) Get count and addr of multiplicand values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LM R4,R5,0(R10) Get count and start of multiplier values +* ..which are the same as the multiplicands + BASR R6,0 Set top of inner loop +* + LD FPR8,0(,R3) Get long BFP multiplicand + LD FPR1,0(,R5) Get long BFP multiplier + LFPC FPCREGNT Set exceptions non-trappable + MDBR FPR8,FPR1 Multiply long FPR8 by FPR1 RRE + STD FPR8,0(,R7) Store long BFP product + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LD FPR8,0(,R3) Get long BFP multiplicand + LD FPR1,0(,R5) Get long BFP multiplier + LFPC FPCREGTR Set exceptions trappable + MDBR FPR8,FPR1 Multiply long multiplier from FPR8 RRE + STD FPR8,8(,R7) Store long BFP remainder + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LD FPR8,0(,R3) Get long BFP multiplicand + LFPC FPCREGNT Set exceptions non-trappable + MDB FPR8,0(,R5) Multiply long FPR8 by multiplier RXE + STD FPR8,16(,R7) Store long BFP product + STFPC 8(R8) Store resulting FPCR flags and DXC +* + LD FPR8,0(,R3) Get long BFP multiplicand + LFPC FPCREGTR Set exceptions trappable + MDB FPR8,0(,R5) Multiply long FPR8 by multiplier RXE + STD FPR8,24(,R7) Store long BFP remainder + STFPC 12(R8) Store resulting FPCR flags and DXC +* + LA R5,8(,R5) Point to next multiplier value + LA R7,4*8(,R7) Point to next Multiply result area + LA R8,4*4(,R8) Point to next Multiply FPCR area + BCTR R4,R6 Loop through right-hand values +* + LA R3,8(,R3) Point to next multiplicand value + BCTR R2,R12 Multiply until all cases tested + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Multiply using provided long BFP input pairs. This set of +* tests triggers IEEE exceptions Overflow, Underflow, and Inexact and +* collects non-trap and trap results. +* +* Four results are generated for each input: one RRE with all +* exceptions non-trappable, a second RRE with all exceptions trappable, +* a third RXE with all exceptions non-trappable, a fourth RXE with all +* exceptions trappable, +* +* The product and FPC contents are stored for each result. +* +*********************************************************************** + SPACE 2 +LBFPF LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LFPC FPCREGNT Set exceptions non-trappable + LD FPR8,0(,R3) Get long BFP multiplicand + LD FPR1,8(,R3) Get long BFP multiplier + MDBR FPR8,FPR1 Multiply long FPR8 by FPR1 RRE + STD FPR8,0(,R7) Store long BFP product + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LD FPR8,0(,R3) Reload long BFP multiplicand +* ..multiplier is still in FPR1 + MDBR FPR8,FPR1 Multiply long FPR8 by FPR1 RRE + STD FPR8,8(,R7) Store long BFP product + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable + LD FPR8,0(,R3) Reload long BFP multiplicand + MDB FPR8,8(,R3) Multiply long FPR8 by multiplier RXE + STD FPR8,16(,R7) Store long BFP product + STFPC 8(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LD FPR8,0(,R3) Reload long BFP multiplicand + MDB FPR8,8(,R3) Multiply long FPR8 by multiplier RXE + STD FPR8,24(,R7) Store long BFP product + STFPC 12(R8) Store resulting FPCR flags and DXC +* + LA R3,2*8(,R3) Point to next input value pair + LA R7,4*8(,R7) Point to next quotent result pair + LA R8,4*4(,R8) Point to next FPCR result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Multiply using provided long BFP input pairs. This set of +* tests exhaustively tests all rounding modes available for Multiply. +* The rounding mode can only be specified in the FPC. +* +* All five FPC rounding modes are tested because the preceeding tests, +* using rounding mode RNTE, do not often create results that require +* rounding. +* +* Two results are generated for each input and rounding mode: one RRE +* and one RXE. Traps are disabled for all rounding mode tests. +* +* The product and FPC contents are stored for each result. +* +*********************************************************************** + SPACE 2 +LBFPRM LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + XR R1,R1 Zero register 1 for use in IC/STC/indexing + BASR R12,0 Set top of test case loop + + LA R5,FPCMCT Get count of FPC modes to be tested + BASR R9,0 Set top of rounding mode loop +* + IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 0(R1) Set FPC Rounding Mode + LD FPR8,0(,R3) Get long BFP multiplicand + LD FPR1,8(,R3) Get long BFP multiplier + MDBR FPR8,FPR1 Multiply long FPR8 by FPR1 RRE + STD FPR8,0(,R7) Store long BFP product + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 0(R1) Set FPC Rounding Mode + LD FPR8,0(,R3) Reload long BFP multiplicand + MDB FPR8,8(,R3) Multiply long FPR8 by multiplier RXE + STD FPR8,8(,R7) Store long BFP product + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LA R7,2*8(,R7) Point to next product result set + LA R8,2*4(,R8) Point to next FPCR result area +* + BCTR R5,R9 Iterate to next FPC mode +* +* End of FPC modes to be tested. Advance to next test case. We will +* skip eight bytes of FPCR result area so that each set of five result +* FPCR contents pairs starts at a memory address ending in zero for the +* convenience of memory dump review. +* + LA R3,2*8(,R3) Point to next input value pair + LA R8,8(,R8) Skip to start of next FPCR result area + BCTR R2,R12 Multiply next input value lots of times +* + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Multiply using provided extended BFP inputs. This set of +* tests checks NaN propagation, operations on values that are not +* finite numbers, and other basic tests. This set generates results +* that can be validated against Figure 19-23 on page 19-28 of +* SA22-7832-10. +* +* Two results are generated for each input: one RRE with all +* exceptions non-trappable, and a second RRE with all exceptions +* trappable. Extended BFP Multiply does not have an RXE format. +* +* The product and FPC contents are stored for each result. +* +*********************************************************************** + SPACE 2 +XBFPNF DS 0H BFP extended non-finite values tests + LM R2,R3,0(R10) Get count and addr of multiplicand values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LM R4,R5,0(R10) Get count and start of multiplier values +* ..which are the same as the multiplicands + BASR R6,0 Set top of inner loop +* + LD FPR8,0(,R3) Get extended BFP multiplicand part 1 + LD FPR10,8(,R3) Get extended BFP multiplicand part 2 + LD FPR1,0(,R5) Get extended BFP multiplier part 1 + LD FPR3,8(,R5) Get extended BFP multiplier part 2 + LFPC FPCREGNT Set exceptions non-trappable + MXBR FPR8,FPR1 Multiply extended FPR8-10 by FPR1-3 RRE + STD FPR8,0(,R7) Store extended BFP product part 1 + STD FPR10,8(,R7) Store extended BFP product part 2 + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LD FPR8,0(,R3) Get extended BFP multiplicand part 1 + LD FPR10,8(,R3) Get extended BFP multiplicand part 2 + LD FPR1,0(,R5) Get extended BFP multiplier part 1 + LD FPR3,8(,R5) Get extended BFP multiplier part 2 + LFPC FPCREGTR Set exceptions trappable + MXBR FPR8,FPR1 Multiply extended FPR8-10 by FPR1-3 RRE + STD FPR8,16(,R7) Store extended BFP product part 1 + STD FPR10,24(,R7) Store extended BFP product part 2 + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LA R5,16(,R5) Point to next multiplier value + LA R7,32(,R7) Point to next Multiply result area + LA R8,16(,R8) Point to next Multiply FPCR area + BCTR R4,R6 Loop through right-hand values +* + LA R3,16(,R3) Point to next multiplicand value + BCTR R2,R12 Multiply until all cases tested + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Multiply using provided extended BFP input pairs. This set +* of tests triggers IEEE exceptions Overflow, Underflow, and Inexact +* and collects results when the exceptions do not result in a trap and +* when they do. +* +* Two results are generated for each input: one RRE with all +* exceptions non-trappable and a second RRE with all exceptions +* trappable. There is no RXE format for Multiply in extended +* precision. +* +* The product and FPC contents are stored for each result. +* +*********************************************************************** + SPACE 2 +XBFPF LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LFPC FPCREGNT Set exceptions non-trappable + LD FPR8,0(,R3) Get extended BFP multiplicand part 1 + LD FPR10,8(,R3) Get extended BFP multiplicand part 2 + LD FPR1,16(,R3) Get extended BFP multiplier part 1 + LD FPR3,24(,R3) Get extended BFP multiplier part 2 + MXBR FPR8,FPR1 Multiply extended FPR8-10 by FPR1-3 RRE + STD FPR8,0(,R7) Store extended BFP product part 1 + STD FPR10,8(,R7) Store extended BFP product part 2 + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LD FPR8,0(,R3) Reload extended BFP multiplicand part 1 + LD FPR10,8(,R3) Reload extended BFP multiplicand part 2 +* ..multiplier is still in FPR1-FPR3 + MXBR FPR8,FPR1 Multiply extended FPR8-10 by FPR1-3 RRE + STD FPR8,16(,R7) Store extended BFP product part 1 + STD FPR10,24(,R7) Store extended BFP product part 2 + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LA R3,32(,R3) Point to next input value pair + LA R7,32(,R7) Point to next quotent result pair + LA R8,16(,R8) Point to next FPCR result area + BCTR R2,R12 Convert next input value. +* + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Multiply using provided extended BFP input pairs. This set +* of tests exhaustively tests all rounding modes available for +* Multiply. The rounding mode can only be specified in the FPC. +* +* All five FPC rounding modes are tested because the preceeding tests, +* using rounding mode RNTE, do not often create results that require +* rounding. +* +* Two results are generated for each input and rounding mode: one RRE +* and one RXE. Traps are disabled for all rounding mode tests. +* +* The product and FPC contents are stored for each result. +* +*********************************************************************** + SPACE 2 +XBFPRM LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + XR R1,R1 Zero register 1 for use in IC/STC/indexing + BASR R12,0 Set top of test case loop + + LA R5,FPCMCT Get count of FPC modes to be tested + BASR R9,0 Set top of rounding mode loop +* + IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 0(R1) Set FPC Rounding Mode + LD FPR8,0(,R3) Get extended BFP multiplicand part 1 + LD FPR10,8(,R3) Get extended BFP multiplicand part 2 + LD FPR1,16(,R3) Get extended BFP multiplier part 1 + LD FPR3,24(,R3) Get extended BFP multiplier part 2 + MXBR FPR8,FPR1 Multiply extended FPR8-10 by FPR1-3 RRE + STD FPR8,0(,R7) Store extended BFP product part 1 + STD FPR10,8(,R7) Store extended BFP product part 2 + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LA R7,16(,R7) Point to next product result set + LA R8,4(,R8) Point to next FPCR result area +* + BCTR R5,R9 Iterate to next FPC mode +* +* End of FPC modes to be tested. Advance to next test case. We will +* skip eight bytes of FPCR result area so that each set of five result +* FPCR contents pairs starts at a memory address ending in zero for the +* convenience of memory dump review. +* + LA R3,2*16(,R3) Point to next input value pair + LA R8,12(,R8) Skip to start of next FPCR result area + BCTR R2,R12 Multiply next input value lots of times +* + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Table of FPC rounding modes to test product rounding modes. +* +* The Set BFP Rounding Mode does allow specification of the FPC +* rounding mode as an address, so we shall index into a table of +* BFP rounding modes without bothering with Execute. +* +*********************************************************************** + SPACE 2 +* +* Rounding modes that may be set in the FPCR. The FPCR controls +* rounding of the product. +* +* These are indexed directly by the loop counter, which counts down. +* So the modes are listed in reverse order here. +* +FPCMODES DS 0C + DC AL1(7) RFS, Round for shorter precision + DC AL1(3) RM, Round to -infinity + DC AL1(2) RP, Round to +infinity + DC AL1(1) RZ, Round to zero + DC AL1(0) RNTE, Round to Nearest, ties to even +FPCMCT EQU *-FPCMODES Count of FPC Modes to be tested +* + EJECT +*********************************************************************** +* +* Short BFP test data sets for Multiply testing. +* +* The first test data set is used for tests of basic functionality, +* NaN propagation, and results from operations involving other than +* finite numbers. +* +* The second test data set is used for testing boundary conditions +* using two finite non-zero values. Each possible type of result +* (normal, scaled, etc) is created by members of this test data set. +* +* The third test data set is used for exhaustive testing of final +* results across the five rounding modes available for the Multiply +* instruction. +* +* The strategy for predictable rounding mode testing is to use a +* multiplicand with some one-bits in the low-order byte and multiply +* that by 1/16 (0.0625). In BFP, this will have the effect of shifting +* the low-order byte out of the target precision representation and +* into the high-order portion of the bits that control rounding. The +* input low-order byte will be determined by the rounding desired. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* First input test data set, to test operations using non-finite or +* zero inputs. Member values chosen to validate Figure 19-23 on page +* 19-28 of SA22-7832-10. Each value in this table is tested against +* every other value in the table. Eight entries means 64 result sets. +* +*********************************************************************** + SPACE 2 +SBFPNFIN DS 0F Inputs for short BFP non-finite tests + DC X'FF800000' -inf + DC X'C0000000' -2.0 + DC X'80000000' -0 + DC X'00000000' +0 + DC X'40000000' +2.0 + DC X'7F800000' +inf + DC X'FFCB0000' -QNaN + DC X'7F8A0000' +SNaN +SBFPNFCT EQU (*-SBFPNFIN)/4 Count of short BFP in list + SPACE 3 +*********************************************************************** +* +* Second input test data set. These are finite pairs intended to +* trigger overflow, underflow, and inexact exceptions. Each pair is +* added twice, once non-trappable and once trappable. Trappable +* overflow or underflow yields a scaled result. Trappable inexact +* will show whether the Incremented DXC code is returned. +* +* The following test cases are required: +* 1. Overflow +* 2. Underflow - normal inputs +* 3. Underflow - subnormal inputs +* 4. Normal - from subnormal inputs +* 5. Inexact - incremented +* 6. Inexact - truncated +* +*********************************************************************** + SPACE 2 +SBFPIN DS 0F Inputs for short BFP finite tests +* +* Overflow on subtraction +* + DC X'7F7FFFFF' +Nmax + DC X'FF7FFFFF' -Nmax +* +* Underflow from product of normals. We will multiply a small normal +* by a slightly smaller normal to generate a subnormal. +* + DC X'00FFFFFF' Very small normal number + DC X'00800000' Smaller normal (+Nmin) +* +* Underflow from the product of subnormals. +* + DC X'00040000' Subnormal, < +Dmax + DC X'00000F0F' Smaller subnormal +* +* We cannot generate a normal result from product of subnormals +* because the result will be smaller than both the multiplicand and the +* multiplier. So we'll try multiplying +Dmax by 2. The result should +* be +Nmin +* + DC X'007FFFFF' +Dmax + DC X'40000000' +2.0 +* +* Multiply a value from 1.0 such that the added digits are to the right +* of the right-most bit in the stored significand. The result will be +* inexact, and incremented will be determined by the value of the +* bits in the multiplier. +* + DC X'3F80000C' Multiplicand 1.000001430511474609375 + DC X'3F880000' Multiplier 1.0625 (1/16) +*..nearest is away from zero, incremented. +* + DC X'3F800007' Multiplicand 1.00000083446502685546875 + DC X'3F880000' Multiplier 1.0625 (1/16) +*..nearest is toward zero, truncated +* +SBFPCT EQU (*-SBFPIN)/4/2 Count of short BFP in list + SPACE 3 +*********************************************************************** +* +* Third input test data set. These are finite pairs intended to +* test all combinations of rounding mode for the product and the +* remainder. Values are chosen to create a requirement to round +* to the target precision after the computation and to generate +* varying results depending on the rounding mode in the FPCR. +* +* The result set will have cases that represent each of the following +* +* 1. Positive, nearest magnitude is toward zero. +* 2. Negative, nearest magnitude is toward zero. +* 3. Positive, nearest magnitude is away from zero. +* 4. Negative, nearest magnitude is away from zero. +* 5. Positive, tie, nearest even has greater magnitude +* 6. Negative, tie, nearest even has greater magnitude +* 7. Positive, tie, nearest even has lower magnitude +* 8. Negative, tie, nearest even has lower magnitude +* +* Round For Shorter precision correctness can be determined from the +* above test cases. +* +*********************************************************************** + SPACE 2 +SBFPINRM DS 0F Inputs for short BFP rounding testing +* +* Multiply a value from 1.0 such that the added digits are to the right +* of the right-most bit in the stored significand. The result will be +* inexact, and incremented will be determined by the value of the +* bits in the multiplier. +* + DC X'3F800007' Multiplicand +1.00000083446502685546875 + DC X'3F880000' Multiplier 1.0625 (1/16) + DC X'BF800007' Multiplicand -1.00000083446502685546875 + DC X'3F880000' Multiplier 1.0625 (1/16) +*..nearest is toward zero, truncated +* + DC X'3F80000C' Multiplicand +1.000001430511474609375 + DC X'3F880000' Multiplier 1.0625 (1/16) + DC X'BF80000C' Multiplicand -1.000001430511474609375 + DC X'3F880000' Multiplier 1.0625 (1/16) +*..nearest is away from zero, incremented. +* + DC X'3F800008' Multiplicand +1.000000476837158203125 + DC X'3F880000' Multiplier 1.0625 (1/16) + DC X'BF800008' Multiplicand -1.000000476837158203125 + DC X'3F880000' Multiplier 1.0625 (1/16) +*..nearest is a tie, nearest even has lower magnitude +* + DC X'3F800018' Multiplicand +1.000002384185791015625 + DC X'3F880000' Multiplier 1.0625 (1/16) + DC X'BF800018' Multiplicand -1.000002384185791015625 + DC X'3F880000' Multiplier 1.0625 (1/16) +*..nearest is a tie, nearest even has greater magnitude +* +SBFPRMCT EQU (*-SBFPINRM)/4/2 Count of short BFP rounding tests + EJECT +*********************************************************************** +* +* Long BFP test data sets for Add testing. +* +* The first test data set is used for tests of basic functionality, +* NaN propagation, and results from operations involving other than +* finite numbers. +* +* The second test data set is used for testing boundary conditions +* using two finite non-zero values. Each possible type of result +* (normal, scaled, etc) is created by members of this test data set. +* +* The third test data set is used for exhaustive testing of final +* results across the five rounding modes available for the Add +* instruction. +* +* See the Short BFP test cases header for a discussion of test case +* selection for rounding mode test case values. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* First input test data set, to test operations using non-finite or +* zero inputs. Member values chosen to validate Figure 19-23 on page +* 19-28 of SA22-7832-10. Each value in this table is tested against +* every other value in the table. Eight entries means 64 result sets. +* +*********************************************************************** + SPACE 2 +LBFPNFIN DS 0F Inputs for long BFP testing + DC X'FFF0000000000000' -inf + DC X'C000000000000000' -2.0 + DC X'8000000000000000' -0 + DC X'0000000000000000' +0 + DC X'4000000000000000' +2.0 + DC X'7FF0000000000000' +inf + DC X'FFF8B00000000000' -QNaN + DC X'7FF0A00000000000' +SNaN +LBFPNFCT EQU (*-LBFPNFIN)/8 Count of long BFP in list + SPACE 3 +*********************************************************************** +* +* Second input test data set. These are finite pairs intended to +* trigger overflow, underflow, and inexact exceptions. Each pair is +* added twice, once non-trappable and once trappable. Trappable +* overflow or underflow yields a scaled result. Trappable inexact +* will show whether the Incremented DXC code is returned. +* +* The following test cases are required: +* 1. Overflow +* 2. Underflow - normal inputs +* 3. Underflow - subnormal inputs +* 4. Normal - from subnormal inputs +* 5. Inexact - incremented +* 6. Inexact - truncated +* +*********************************************************************** + SPACE 2 +LBFPIN DS 0D Inputs for long BFP finite tests +* +* Overflow on multiplication +* + DC X'7FEFFFFFFFFFFFFF' +Nmax + DC X'FFEFFFFFFFFFFFFF' +Nmax +* +* Underflow from product of normals. We wil multiply a small +* normal by a slightly smaller normal to generate a subnormal. +* + DC X'001FFFFFFFFFFFFF' Very small normal number + DC X'0010000000000000' Smaller normal negative +* +* Underflow from product of subnormals. +* + DC X'0008000000000000' Subnormal, < +Dmax + DC X'0000F0F000000000' Smaller subnormal +* +* We cannot generate a normal result from product of subnormals +* because the result will be smaller than both the multiplicand and the +* multiplier. So we'll try multiplying +Dmax by 2. The result should +* be +Nmin +* + DC X'000FFFFFFFFFFFFF' +Dmax + DC X'4000000000000000' +2.0, result should be normal +* +* Multiply a value from 1.0 such that the added digits are to the right +* of the right-most bit in the stored significand. The result will be +* inexact, and incremented will be determined by the value of the +* bits in the multiplier. +* + DC X'3FF000000000000C' Multiplicand +1, aka 1.0b0 + DC X'3FF1000000000000' Multiplier 1.0625 (1/16) +*..nearest is away from zero, incremented. +* + DC X'3FF0000000000007' Multiplicand +1, aka 1.0b0 + DC X'3FF1000000000000' Multiplier 1.0625 (1/16) +*..nearest is toward zero, truncated. +* +LBFPCT EQU (*-LBFPIN)/8/2 Count of long BFP in list + SPACE 3 +*********************************************************************** +* +* Third input test data set. These are finite pairs intended to +* test all combinations of rounding mode for the product and the +* remainder. Values are chosen to create a requirement to round +* to the target precision after the computation and to generate +* varying results depending on the rounding mode in the FPCR. +* +* The result set will have cases that represent each of the following +* +* 1. Positive, nearest magnitude is toward zero. +* 2. Negative, nearest magnitude is toward zero. +* 3. Positive, nearest magnitude is away from zero. +* 4. Negative, nearest magnitude is away from zero. +* 5. Positive, tie, nearest even has greater magnitude +* 6. Negative, tie, nearest even has greater magnitude +* 7. Positive, tie, nearest even has lower magnitude +* 8. Negative, tie, nearest even has lower magnitude +* +* Round For Shorter precision correctness can be determined from the +* above test cases. +* +*********************************************************************** + SPACE 2 +LBFPINRM DS 0F +* +* Multiply a value from 1.0 such that the added digits are to the right +* of the right-most bit in the stored significand. The result will be +* inexact, and incremented will be determined by the value of the +* bits in the multiplier. +* + DC X'3FF0000000000007' Multiplicand + DC X'3FF1000000000000' Multiplier 1.0625 (1/16) + DC X'BFF0000000000007' Multiplicand + DC X'3FF1000000000000' Multiplier 1.0625 (1/16) +*..nearest is toward zero, truncated. +* + DC X'3FF000000000000C' Multiplicand + DC X'3FF1000000000000' Multiplier 1.0625 (1/16) + DC X'BFF000000000000C' Multiplicand + DC X'3FF1000000000000' Multiplier 1.0625 (1/16) +*..nearest is away from zero, incremented. +* + DC X'3FF0000000000008' Multiplicand + DC X'3FF1000000000000' Multiplier 1.0625 (1/16) + DC X'BFF0000000000008' Multiplicand + DC X'3FF1000000000000' Multiplier 1.0625 (1/16) +*..nearest is a tie, nearest even has lower magnitude +* + DC X'3FF0000000000018' Multiplicand +1, aka +1.0b0 + DC X'3FF1000000000000' Multiplier 1.0625 (1/16) + DC X'BFF0000000000018' Multiplicand -1, aka -1.0b0 + DC X'3FF1000000000000' Multiplier 1.0625 (1/16) +*..nearest is a tie, nearest even has greater magnitude +* +LBFPRMCT EQU (*-LBFPINRM)/8/2 Count of long BFP rounding tests + EJECT +*********************************************************************** +* +* Extended BFP test data sets for Add testing. +* +* The first test data set is used for tests of basic functionality, +* NaN propagation, and results from operations involving other than +* finite numbers. +* +* The second test data set is used for testing boundary conditions +* using two finite non-zero values. Each possible type of result +* (normal, scaled, etc) is created by members of this test data set. +* +* The third test data set is used for exhaustive testing of final +* results across the five rounding modes available for the Add +* instruction. +* +* See the Short BFP test cases header for a discussion of test case +* selection for rounding mode test case values. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* First input test data set, to test operations using non-finite or +* zero inputs. Member values chosen to validate Figure 19-23 on page +* 19-28 of SA22-7832-10. Each value in this table is tested against +* every other value in the table. Eight entries means 64 result sets. +* +*********************************************************************** + SPACE 2 +XBFPNFIN DS 0F Inputs for extended BFP testing + DC X'FFFF0000000000000000000000000000' -inf + DC X'C0000000000000000000000000000000' -2.0 + DC X'80000000000000000000000000000000' -0 + DC X'00000000000000000000000000000000' +0 + DC X'40000000000000000000000000000000' +2.0 + DC X'7FFF0000000000000000000000000000' +inf + DC X'FFFF8B00000000000000000000000000' -QNaN + DC X'7FFF0A00000000000000000000000000' +SNaN +XBFPNFCT EQU (*-XBFPNFIN)/16 Count of extended BFP in list + SPACE 3 +*********************************************************************** +* +* Second input test data set. These are finite pairs intended to +* trigger overflow, underflow, and inexact exceptions. Each pair is +* added twice, once non-trappable and once trappable. Trappable +* overflow or underflow yields a scaled result. Trappable inexact +* will show whether the Incremented DXC code is returned. +* +* The following test cases are required: +* The following test cases are required: +* 1. Overflow +* 2. Underflow - normal inputs +* 3. Underflow - subnormal inputs +* 4. Normal - from subnormal inputs +* 5. Inexact - incremented +* 6. Inexact - truncated +* +*********************************************************************** + SPACE 2 +XBFPIN DS 0F Inputs for extended BFP finite tests +* +* Overflow on subtraction +* + DC X'7FFEFFFFFFFFFFFFFFFFFFFFFFFFFFFF' +Nmax + DC X'FFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFF' +Nmax +* +* Underflow from product of normals. We will multiply a small +* normal by a slightly smaller normal to generate a subnormal. +* + DC X'0001FFFFFFFFFFFFFFFFFFFFFFFFFFFF' Very small normal + DC X'00010000000000000000000000000000' Smaller normal +* +* Underflow from product of subnormals. +* + DC X'00008000000000000000000000000000' Subnormal, < +Dmax + DC X'00000F0F000000000000000000000000' Smaller subnormal +* +* We cannot generate a normal result from product of subnormals +* because the result will be smaller than both the multiplicand and the +* multiplier. So we'll try multiplying +Dmax by 2. The result should +* be +Nmin +* + DC X'0000FFFFFFFFFFFFFFFFFFFFFFFFFFFF' +Dmax + DC X'40000000000000000000000000000001' +2.0, +* ...result will be normal +* +* Multiply a value from 1.0 such that the added digits are to the right +* of the right-most bit in the stored significand. The result will be +* inexact, and incremented will be determined by the value of the +* bits in the multiplier. +* + DC X'3FFF000000000000000000000000000C' +1, aka 1.0b0 + DC X'3FFF1000000000000000000000000000' 1.0625 +*..nearest is away from zero, incremented. +* + DC X'3FFF0000000000000000000000000007' +1, aka 1.0b0 + DC X'3FFF1000000000000000000000000000' 1.0625 +*..nearest is toward zero, truncated +* +XBFPCT EQU (*-XBFPIN)/16/2 Count of extended BFP in list + SPACE 3 +*********************************************************************** +* +* Third input test data set. These are finite pairs intended to +* test all combinations of rounding mode for the product and the +* remainder. Values are chosen to create a requirement to round +* to the target precision after the computation and to generate +* varying results depending on the rounding mode in the FPCR. +* +* The result set will have cases that represent each of the following +* +* 1. Positive, nearest magnitude is toward zero. +* 2. Negative, nearest magnitude is toward zero. +* 3. Positive, nearest magnitude is away from zero. +* 4. Negative, nearest magnitude is away from zero. +* 5. Positive, tie, nearest even has greater magnitude +* 6. Negative, tie, nearest even has greater magnitude +* 7. Positive, tie, nearest even has lower magnitude +* 8. Negative, tie, nearest even has lower magnitude +* +* Round For Shorter precision correctness can be determined from the +* above test cases. +* +*********************************************************************** + SPACE 2 +XBFPINRM DS 0D +* +* Multiply a value from 1.0 such that the added digits are to the right +* of the right-most bit in the stored significand. The result will be +* inexact, and incremented will be determined by the value of the +* bits in the multiplier. +* + DC X'3FFF0000000000000000000000000007' +1, aka +1.0b0 + DC X'3FFF1000000000000000000000000000' 1.0625 + DC X'BFFF0000000000000000000000000007' -1, aka -1.0b0 + DC X'3FFF1000000000000000000000000000' 1.0625 +*..nearest is toward zero +* + DC X'3FFF000000000000000000000000000C' +1, aka +1.0b0 + DC X'3FFF1000000000000000000000000000' 1.0625 + DC X'BFFF000000000000000000000000000C' -1, aka -1.0b0 + DC X'3FFF1000000000000000000000000000' 1.0625 +*..nearest is away from zero +* + DC X'3FFF0000000000000000000000000008' +1, aka +1.0b0 + DC X'3FFF1000000000000000000000000000' 1.0625 + DC X'BFFF0000000000000000000000000008' -1, aka -1.0b0 + DC X'3FFF1000000000000000000000000000' 1.0625 +*..nearest is a tie, nearest even has lower magnitude +* + DC X'3FFF0000000000000000000000000018' +1, aka +1.0b0 + DC X'3FFF1000000000000000000000000000' 1.0625 + DC X'BFFF0000000000000000000000000018' -1, aka -1.0b0 + DC X'3FFF1000000000000000000000000000' 1.0625 +*..nearest is a tie, nearest even has greater magnitude +* +XBFPRMCT EQU (*-XBFPINRM)/16/2 Count of long BFP rounding tests + EJECT +* +* Locations for results +* +SBFPNFOT EQU STRTLABL+X'1000' Short non-finite BFP results +* ..room for 64 tests, 64 used +SBFPNFFL EQU STRTLABL+X'1400' FPCR flags and DXC from short BFP +* ..room for 64 tests, 64 used +* +SBFPOUT EQU STRTLABL+X'1800' Short BFP finite results +* ..room for 16 tests, 6 used +SBFPFLGS EQU STRTLABL+X'1900' FPCR flags and DXC from short BFP +* ..room for 16 tests, 6 used +* +SBFPRMO EQU STRTLABL+X'1A00' Short BFP rounding mode test results +* ..Room for 16, 8 used. +SBFPRMOF EQU STRTLABL+X'1D00' Short BFP rounding mode FPCR results +* ..Room for 16, 8 used. +* ..next location starts at X'2000' +* +LBFPNFOT EQU STRTLABL+X'3000' Long non-finite BFP results +* ..room for 64 tests, 64 used +LBFPNFFL EQU STRTLABL+X'3800' FPCR flags and DXC from long BFP +* ..room for 64 tests, 64 used +* +LBFPOUT EQU STRTLABL+X'3C00' Long BFP finite results +* ..room for 16 tests, 6 used +LBFPFLGS EQU STRTLABL+X'3E00' FPCR flags and DXC from long BFP +* ..room for 16 tests, 6 used +* +LBFPRMO EQU STRTLABL+X'4000' Long BFP rounding mode test results +* ..Room for 16, 8 used. +LBFPRMOF EQU STRTLABL+X'4500' Long BFP rounding mode FPCR results +* ..Room for 16, 8 used. +* ..next location starts at X'4800' +* +XBFPNFOT EQU STRTLABL+X'5000' Extended non-finite BFP results +* ..room for 64 tests, 64 used +XBFPNFFL EQU STRTLABL+X'5800' FPCR flags and DXC from ext'd BFP +* ..room for 64 tests, 64 used +* +XBFPOUT EQU STRTLABL+X'5C00' Extended BFP finite results +* ..room for 16 tests, 6 used +XBFPFLGS EQU STRTLABL+X'5E00' FPCR flags and DXC from ext'd BFP +* ..room for 16 tests, 6 used +* +XBFPRMO EQU STRTLABL+X'6000' Ext'd BFP rounding mode test results +* ..Room for 16, 8 used. +XBFPRMOF EQU STRTLABL+X'6500' Ext'd BFP rounding mode FPCR results +* ..Room for 16, 8 used. +* ..next location starts at X'6800' +* +ENDLABL EQU STRTLABL+X'6800' + PADCSECT ENDLABL + END diff --git a/tests/bfp-019-multiply.core b/tests/bfp-019-multiply.core new file mode 100644 index 000000000..95e0828c8 Binary files /dev/null and b/tests/bfp-019-multiply.core differ diff --git a/tests/bfp-019-multiply.list b/tests/bfp-019-multiply.list new file mode 100644 index 000000000..3802a153a --- /dev/null +++ b/tests/bfp-019-multiply.list @@ -0,0 +1,1675 @@ +ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 1 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 2 *********************************************************************** + 3 * + 4 *Testcase IEEE MULTIPLY + 5 * Test case capability includes IEEE exceptions trappable and + 6 * otherwise. Test results, FPCR flags, the Condition code, and any + 7 * DXC are saved for all tests. + 8 * + 9 * The fused multiply operations are not included in this test program, + 10 * nor are the multiply to longer precision instructions. The former + 11 * are excluded to keep test case complexity manageable, and latter + 12 * because they require a slightly different testing profile. + 13 * + 14 *********************************************************************** + + + 16 *********************************************************************** + 17 * + 18 * Tests the following three conversion instructions + 19 * MULTIPLY (short BFP, RRE) + 20 * MULTIPLY (long BFP, RRE) + 21 * MULTIPLY (extended BFP, RRE) + 22 * MULTIPLY (short BFP, RXE) + 23 * MULTIPLY (long BFP, RXE) + 24 * + 25 * Test data is compiled into this program. The test script that runs + 26 * this program can provide alternative test data through Hercules R + 27 * commands. + 28 * + 29 * Test Case Order + 30 * 1) Short BFP basic tests, including traps and NaN propagation + 31 * 2) Short BFP finite number tests, incl. traps and scaling + 32 * 3) Short BFP FPC-controlled rounding mode exhaustive tests + 33 * 4) Long BFP basic tests, including traps and NaN propagation + 34 * 5) Long BFP finite number tests, incl. traps and scaling + 35 * 6) Long BFP FPC-controlled rounding mode exhaustive tests + 36 * 7) Extended BFP basic tests, including traps and NaN propagation + 37 * 8) Extended BFP finite number tests, incl. traps and scaling + 38 * 9) Extended BFP FPC-controlled rounding mode exhaustive tests + 39 * + 40 * Three input test sets are provided each for short, long, and + 41 * extended BFP inputs. Test values are the same for each precision + 42 * for most tests. Overflow and underflow each require precision- + 43 * dependent test values. + 44 * + 45 * Also tests the following floating point support instructions + 46 * LOAD (Short) + 47 * LOAD (Long) + 48 * LFPC (Load Floating Point Control Register) + 49 * SRNMB (Set BFP Rounding Mode 3-bit) + 50 * STORE (Short) + 51 * STORE (Long) + 52 * STFPC (Store Floating Point Control Register) + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 2 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 53 * + 54 *********************************************************************** + + + 56 MACRO + 57 PADCSECT &ENDLABL + 58 .* + 59 .* Macro to pad the CSECT to include result data areas if this test + 60 .* program is not being assembled using asma. asma generates a core + 61 .* image that is loaded by the loadcore command, and because the + 62 .* core image is a binary stored in Github, it makes sense to make + 63 .* this small effort to keep the core image small. + 64 .* + 65 AIF (D'&ENDLABL).GOODPAD + 66 MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + 67 MNOTE *,'No CSECT padding performed' + 68 MEXIT + 69 .* + 70 .GOODPAD ANOP Label valid. See if we're on asma + 71 AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + 72 ORG &ENDLABL-1 Not ASMA. Pad CSECT + 73 MEXIT + 74 .* + 75 .NOPAD ANOP + 76 MNOTE *,'asma detected; no CSECT padding performed' + 77 MEND + 78 * + 79 * Note: for compatibility with the z/CMS test rig, do not change + 80 * or use R11, R14, or R15. Everything else is fair game. + 81 * + 0000000000000000 0000000000000B7F 82 BFPMUL START 0 + 0000000000000000 0000000000000001 83 STRTLABL EQU * + 0000000000000000 0000000000000001 84 R0 EQU 0 Work register for cc extraction + 0000000000000001 0000000000000001 85 R1 EQU 1 + 0000000000000002 0000000000000001 86 R2 EQU 2 Holds count of test input values + 0000000000000003 0000000000000001 87 R3 EQU 3 Points to next test input value(s) + 0000000000000004 0000000000000001 88 R4 EQU 4 Rounding tests inner loop control + 0000000000000005 0000000000000001 89 R5 EQU 5 Rounding tests outer loop control + 0000000000000006 0000000000000001 90 R6 EQU 6 Rounding tests top of inner loop + 0000000000000007 0000000000000001 91 R7 EQU 7 Pointer to next result value(s) + 0000000000000008 0000000000000001 92 R8 EQU 8 Pointer to next FPCR result + 0000000000000009 0000000000000001 93 R9 EQU 9 Rounding tests top of outer loop + 000000000000000A 0000000000000001 94 R10 EQU 10 Pointer to test address list + 000000000000000B 0000000000000001 95 R11 EQU 11 **Reserved for z/CMS test rig + 000000000000000C 0000000000000001 96 R12 EQU 12 Holds number of test cases in set + 000000000000000D 0000000000000001 97 R13 EQU 13 Mainline return address + 000000000000000E 0000000000000001 98 R14 EQU 14 **Return address for z/CMS test rig + 000000000000000F 0000000000000001 99 R15 EQU 15 **Base register on z/CMS or Hyperion + 100 * + 101 * Floating Point Register equates to keep the cross reference clean + 102 * + 0000000000000000 0000000000000001 103 FPR0 EQU 0 + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 3 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 0000000000000001 0000000000000001 104 FPR1 EQU 1 + 0000000000000002 0000000000000001 105 FPR2 EQU 2 + 0000000000000003 0000000000000001 106 FPR3 EQU 3 + 0000000000000004 0000000000000001 107 FPR4 EQU 4 + 0000000000000005 0000000000000001 108 FPR5 EQU 5 + 0000000000000006 0000000000000001 109 FPR6 EQU 6 + 0000000000000007 0000000000000001 110 FPR7 EQU 7 + 0000000000000008 0000000000000001 111 FPR8 EQU 8 + 0000000000000009 0000000000000001 112 FPR9 EQU 9 + 000000000000000A 0000000000000001 113 FPR10 EQU 10 + 000000000000000B 0000000000000001 114 FPR11 EQU 11 + 000000000000000C 0000000000000001 115 FPR12 EQU 12 + 000000000000000D 0000000000000001 116 FPR13 EQU 13 + 000000000000000E 0000000000000001 117 FPR14 EQU 14 + 000000000000000F 0000000000000001 118 FPR15 EQU 15 + 119 * +0000000000000000 0000000000000000 120 USING *,R15 + 121 * + 122 * Above works on real iron (R15=0 after sysclear) + 123 * and in z/CMS (R15 points to start of load module) + 124 * + + + 126 *********************************************************************** + 127 * + 128 * Low core definitions, Restart PSW, and Program Check Routine. + 129 * + 130 *********************************************************************** + + +0000000000000000 0000000000000000 000000000000008E 132 ORG STRTLABL+X'8E' Program check interrution code +000000000000008E 0000 133 PCINTCD DS H + 134 * + 0000000000000150 0000000000000001 135 PCOLDPSW EQU STRTLABL+X'150' z/Arch Program check old PSW + 136 * +0000000000000090 0000000000000090 00000000000001A0 137 ORG STRTLABL+X'1A0' z/Arch Restart PSW +00000000000001A0 00000001 80000000 138 DC X'0000000180000000',AD(START) + 139 * +00000000000001B0 00000000000001B0 00000000000001D0 140 ORG STRTLABL+X'1D0' z/Arch Program check old PSW +00000000000001D0 00000000 00000000 141 DC X'0000000000000000',AD(PROGCHK) + 142 * + 143 * Program check routine. If Data Exception, continue execution at + 144 * the instruction following the program check. Otherwise, hard wait. + 145 * No need to collect data. All interesting DXC stuff is captured + 146 * in the FPCR. + 147 * +00000000000001E0 00000000000001E0 0000000000000200 148 ORG STRTLABL+X'200' +0000000000000200 149 PROGCHK DS 0H Program check occured... +0000000000000200 9507 F08F 000000000000008F 150 CLI PCINTCD+1,X'07' Data Exception? +0000000000000204 A774 0004 000000000000020C 151 JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) +0000000000000208 B2B2 F150 0000000000000150 152 LPSWE PCOLDPSW ..yes, resume program execution +000000000000020C 153 PCNOTDTA DS 0H + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 4 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +000000000000020C 12EE 154 LTR R14,R14 Return address provided? +000000000000020E 077E 155 BNZR R14 Yes, return to z/CMS test rig. +0000000000000210 B2B2 F280 0000000000000280 156 LPSWE HARDWAIT Not data exception, enter disabled wait + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 5 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 158 *********************************************************************** + 159 * + 160 * Main program. Enable Advanced Floating Point, process test cases. + 161 * + 162 *********************************************************************** + + +0000000000000214 164 START DS 0H +0000000000000214 B600 F290 0000000000000290 165 STCTL R0,R0,CTLR0 Store CR0 to enable AFP +0000000000000218 9604 F291 0000000000000291 166 OI CTLR0+1,X'04' Turn on AFP bit +000000000000021C B700 F290 0000000000000290 167 LCTL R0,R0,CTLR0 Reload updated CR0 + 168 * +0000000000000220 41A0 F300 0000000000000300 169 LA R10,SHORTNF Point to short BFP non-finite inputs +0000000000000224 4DD0 F390 0000000000000390 170 BAS R13,SBFPNF Multiply short BFP non-finites +0000000000000228 41A0 F310 0000000000000310 171 LA R10,SHORTF Point to short BFP finite inputs +000000000000022C 4DD0 F41A 000000000000041A 172 BAS R13,SBFPF Multiply short BFP finites +0000000000000230 41A0 F320 0000000000000320 173 LA R10,RMSHORTS Point to short BFP rounding mode tests +0000000000000234 4DD0 F490 0000000000000490 174 BAS R13,SBFPRM Multiply short BFP for rounding tests + 175 * +0000000000000238 41A0 F330 0000000000000330 176 LA R10,LONGNF Point to long BFP non-finite inputs +000000000000023C 4DD0 F4FA 00000000000004FA 177 BAS R13,LBFPNF Multiply long BFP non-finites +0000000000000240 41A0 F340 0000000000000340 178 LA R10,LONGF Point to long BFP finite inputs +0000000000000244 4DD0 F580 0000000000000580 179 BAS R13,LBFPF Multiply long BFP finites +0000000000000248 41A0 F350 0000000000000350 180 LA R10,RMLONGS Point to long BFP rounding mode tests +000000000000024C 4DD0 F5F6 00000000000005F6 181 BAS R13,LBFPRM Multiply long BFP for rounding tests + 182 * +0000000000000250 41A0 F360 0000000000000360 183 LA R10,XTNDNF Point to extended BFP non-finite inputs +0000000000000254 4DD0 F65C 000000000000065C 184 BAS R13,XBFPNF Multiply extended BFP non-finites +0000000000000258 41A0 F370 0000000000000370 185 LA R10,XTNDF Point to ext'd BFP finite inputs +000000000000025C 4DD0 F6CE 00000000000006CE 186 BAS R13,XBFPF Multiply ext'd BFP finites +0000000000000260 41A0 F380 0000000000000380 187 LA R10,RMXTNDS Point to ext'd BFP rounding mode tests +0000000000000264 4DD0 F72C 000000000000072C 188 BAS R13,XBFPRM Multiply ext'd BFP for rounding tests + 189 * +0000000000000268 12EE 190 LTR R14,R14 Return address provided? +000000000000026A 077E 191 BNZR R14 ..Yes, return to z/CMS test rig. +000000000000026C B2B2 F270 0000000000000270 192 LPSWE WAITPSW All done + 193 * +0000000000000270 194 DS 0D Ensure correct alignment for psw +0000000000000270 00020000 00000000 195 WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +0000000000000280 00020000 00000000 196 HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end + 197 * +0000000000000290 00000000 198 CTLR0 DS F +0000000000000294 00000000 199 FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +0000000000000298 F8000000 200 FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags + 201 * + 202 * Input values parameter list, four fullwords for each test data set + 203 * 1) Count, + 204 * 2) Address of inputs, + 205 * 3) Address to place results, and + 206 * 4) Address to place DXC/Flags/cc values. + 207 * +000000000000029C 000000000000029C 0000000000000300 208 ORG STRTLABL+X'300' Enable run-time replacement + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 6 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000300 209 SHORTNF DS 0F Input pairs for short BFP non-finite tests +0000000000000300 00000008 210 DC A(SBFPNFCT) +0000000000000304 0000078C 211 DC A(SBFPNFIN) +0000000000000308 00001000 212 DC A(SBFPNFOT) +000000000000030C 00001400 213 DC A(SBFPNFFL) + 214 * +0000000000000310 215 SHORTF DS 0F Input pairs for short BFP finite tests +0000000000000310 00000006 216 DC A(SBFPCT) +0000000000000314 000007AC 217 DC A(SBFPIN) +0000000000000318 00001800 218 DC A(SBFPOUT) +000000000000031C 00001900 219 DC A(SBFPFLGS) + 220 * +0000000000000320 221 RMSHORTS DS 0F Input pairs for short BFP rounding testing +0000000000000320 00000008 222 DC A(SBFPRMCT) +0000000000000324 000007DC 223 DC A(SBFPINRM) +0000000000000328 00001A00 224 DC A(SBFPRMO) +000000000000032C 00001D00 225 DC A(SBFPRMOF) + 226 * +0000000000000330 227 LONGNF DS 0F Input pairs for long BFP non-finite testing +0000000000000330 00000008 228 DC A(LBFPNFCT) +0000000000000334 0000081C 229 DC A(LBFPNFIN) +0000000000000338 00003000 230 DC A(LBFPNFOT) +000000000000033C 00003800 231 DC A(LBFPNFFL) + 232 * +0000000000000340 233 LONGF DS 0F Input pairs for long BFP finite testing +0000000000000340 00000006 234 DC A(LBFPCT) +0000000000000344 00000860 235 DC A(LBFPIN) +0000000000000348 00003C00 236 DC A(LBFPOUT) +000000000000034C 00003E00 237 DC A(LBFPFLGS) + 238 * +0000000000000350 239 RMLONGS DS 0F Input pairs for long BFP rounding testing +0000000000000350 00000008 240 DC A(LBFPRMCT) +0000000000000354 000008C0 241 DC A(LBFPINRM) +0000000000000358 00004000 242 DC A(LBFPRMO) +000000000000035C 00004500 243 DC A(LBFPRMOF) + 244 * +0000000000000360 245 XTNDNF DS 0F Inputs for ext'd BFP non-finite testing +0000000000000360 00000008 246 DC A(XBFPNFCT) +0000000000000364 00000940 247 DC A(XBFPNFIN) +0000000000000368 00005000 248 DC A(XBFPNFOT) +000000000000036C 00005800 249 DC A(XBFPNFFL) + 250 * +0000000000000370 251 XTNDF DS 0F Inputs for ext'd BFP finite testing +0000000000000370 00000006 252 DC A(XBFPCT) +0000000000000374 000009C0 253 DC A(XBFPIN) +0000000000000378 00005C00 254 DC A(XBFPOUT) +000000000000037C 00005E00 255 DC A(XBFPFLGS) + 256 * +0000000000000380 257 RMXTNDS DS 0F Inputs for ext'd BFP non-finite testing +0000000000000380 00000008 258 DC A(XBFPRMCT) +0000000000000384 00000A80 259 DC A(XBFPINRM) +0000000000000388 00006000 260 DC A(XBFPRMO) + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 7 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +000000000000038C 00006500 261 DC A(XBFPRMOF) + 262 * + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 8 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 264 *********************************************************************** + 265 * + 266 * Perform Multiply using provided short BFP inputs. This set of tests + 267 * checks NaN propagation, operations on values that are not finite + 268 * numbers, and other basic tests. This set generates results that can + 269 * be validated against Figure 19-23 on page 19-28 of SA22-7832-10. + 270 * + 271 * Four results are generated for each input: one RRE with all + 272 * exceptions non-trappable, a second RRE with all exceptions trappable, + 273 * a third RXE with all exceptions non-trappable, a fourth RXE with all + 274 * exceptions trappable, + 275 * + 276 * The product and FPC contents are stored for each result. + 277 * + 278 *********************************************************************** + + +0000000000000390 280 SBFPNF DS 0H BFP Short non-finite values tests +0000000000000390 9823 A000 0000000000000000 281 LM R2,R3,0(R10) Get count and addr of multiplicand values +0000000000000394 9878 A008 0000000000000008 282 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000398 1222 283 LTR R2,R2 Any test cases? +000000000000039A 078D 284 BZR R13 ..No, return to caller +000000000000039C 0DC0 285 BASR R12,0 Set top of loop + 286 * +000000000000039E 9845 A000 0000000000000000 287 LM R4,R5,0(R10) Get count and start of multiplier values + 288 * ..which are the same as the multiplicands +00000000000003A2 0D60 289 BASR R6,0 Set top of inner loop + 290 * +00000000000003A4 7880 3000 0000000000000000 291 LE FPR8,0(,R3) Get short BFP multiplicand +00000000000003A8 7810 5000 0000000000000000 292 LE FPR1,0(,R5) Get short BFP multiplier +00000000000003AC B29D F294 0000000000000294 293 LFPC FPCREGNT Set exceptions non-trappable +00000000000003B0 B317 0081 294 MEEBR FPR8,FPR1 Multiply short FPR8 by FPR1 RRE +00000000000003B4 7080 7000 0000000000000000 295 STE FPR8,0(,R7) Store short BFP product +00000000000003B8 B29C 8000 0000000000000000 296 STFPC 0(R8) Store resulting FPCR flags and DXC + 297 * +00000000000003BC 7880 3000 0000000000000000 298 LE FPR8,0(,R3) Get short BFP multiplicand +00000000000003C0 7810 5000 0000000000000000 299 LE FPR1,0(,R5) Get short BFP multiplier +00000000000003C4 B29D F298 0000000000000298 300 LFPC FPCREGTR Set exceptions trappable +00000000000003C8 B317 0081 301 MEEBR FPR8,FPR1 Multiply short FPR8 by FPR1 RRE +00000000000003CC 7080 7004 0000000000000004 302 STE FPR8,4(,R7) Store short BFP product +00000000000003D0 B29C 8004 0000000000000004 303 STFPC 4(R8) Store resulting FPCR flags and DXC + 304 * +00000000000003D4 7880 3000 0000000000000000 305 LE FPR8,0(,R3) Get short BFP multiplicand +00000000000003D8 7810 5000 0000000000000000 306 LE FPR1,0(,R5) Get short BFP multiplier +00000000000003DC B29D F294 0000000000000294 307 LFPC FPCREGNT Set exceptions non-trappable +00000000000003E0 ED80 5000 0017 0000000000000000 308 MEEB FPR8,0(,R5) Multiply short FPR8 by multiplier RXE +00000000000003E6 7080 7008 0000000000000008 309 STE FPR8,8(,R7) Store short BFP product +00000000000003EA B29C 8008 0000000000000008 310 STFPC 8(R8) Store resulting FPCR flags and DXC + 311 * +00000000000003EE 7880 3000 0000000000000000 312 LE FPR8,0(,R3) Get short BFP multiplicand +00000000000003F2 B29D F298 0000000000000298 313 LFPC FPCREGTR Set exceptions trappable +00000000000003F6 ED80 5000 0017 0000000000000000 314 MEEB FPR8,0(,R5) Multiply short FPR8 by multiplier RXE + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 9 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000003FC 7080 700C 000000000000000C 315 STE FPR8,12(,R7) Store short BFP product +0000000000000400 B29C 800C 000000000000000C 316 STFPC 12(R8) Store resulting FPCR flags and DXC + 317 * +0000000000000404 4150 5004 0000000000000004 318 LA R5,4(,R5) Point to next multiplier value +0000000000000408 4170 7010 0000000000000010 319 LA R7,4*4(,R7) Point to next Multiply result area +000000000000040C 4180 8010 0000000000000010 320 LA R8,4*4(,R8) Point to next Multiply FPCR area +0000000000000410 0646 321 BCTR R4,R6 Loop through right-hand values + 322 * +0000000000000412 4130 3004 0000000000000004 323 LA R3,4(,R3) Point to next input multiplicand +0000000000000416 062C 324 BCTR R2,R12 Loop through left-hand values +0000000000000418 07FD 325 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 10 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 327 *********************************************************************** + 328 * + 329 * Perform Multiply using provided short BFP input pairs. This set of + 330 * tests triggers IEEE exceptions Overflow, Underflow, and Inexact and + 331 * collects both trap and non-trap results. + 332 * + 333 * Four results are generated for each input: one RRE with all + 334 * exceptions non-trappable, a second RRE with all exceptions trappable, + 335 * a third RXE with all exceptions non-trappable, a fourth RXE with all + 336 * exceptions trappable, + 337 * + 338 * The product and FPC contents are stored for each result. + 339 * + 340 *********************************************************************** + + +000000000000041A 9823 A000 0000000000000000 342 SBFPF LM R2,R3,0(R10) Get count and address of test input values +000000000000041E 9878 A008 0000000000000008 343 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000422 1222 344 LTR R2,R2 Any test cases? +0000000000000424 078D 345 BZR R13 ..No, return to caller +0000000000000426 0DC0 346 BASR R12,0 Set top of loop + 347 * +0000000000000428 B29D F294 0000000000000294 348 LFPC FPCREGNT Set exceptions non-trappable +000000000000042C 7880 3000 0000000000000000 349 LE FPR8,0(,R3) Get short BFP multiplicand +0000000000000430 7810 3004 0000000000000004 350 LE FPR1,4(,R3) Get short BFP multiplier +0000000000000434 B317 0081 351 MEEBR FPR8,FPR1 Multiply short FPR8 by FPR1 RRE +0000000000000438 7080 7000 0000000000000000 352 STE FPR8,0(,R7) Store short BFP product +000000000000043C B29C 8000 0000000000000000 353 STFPC 0(R8) Store resulting FPCR flags and DXC + 354 * +0000000000000440 B29D F298 0000000000000298 355 LFPC FPCREGTR Set exceptions trappable +0000000000000444 7880 3000 0000000000000000 356 LE FPR8,0(,R3) Reload short BFP multiplicand + 357 * ..multiplier is still in FPR1 +0000000000000448 B317 0081 358 MEEBR FPR8,FPR1 Multiply short FPR8 by FPR1 RRE +000000000000044C 7080 7004 0000000000000004 359 STE FPR8,4(,R7) Store short BFP product +0000000000000450 B29C 8004 0000000000000004 360 STFPC 4(R8) Store resulting FPCR flags and DXC + 361 * +0000000000000454 B29D F294 0000000000000294 362 LFPC FPCREGNT Set exceptions non-trappable +0000000000000458 7880 3000 0000000000000000 363 LE FPR8,0(,R3) Reload short BFP multiplicand +000000000000045C ED80 3004 0017 0000000000000004 364 MEEB FPR8,4(,R3) Multiply short FPR8 by multiplier RXE +0000000000000462 7080 7008 0000000000000008 365 STE FPR8,8(,R7) Store short BFP product +0000000000000466 B29C 8008 0000000000000008 366 STFPC 8(R8) Store resulting FPCR flags and DXC + 367 * +000000000000046A B29D F298 0000000000000298 368 LFPC FPCREGTR Set exceptions trappable +000000000000046E 7880 3000 0000000000000000 369 LE FPR8,0(,R3) Reload short BFP multiplicand +0000000000000472 ED80 3004 0017 0000000000000004 370 MEEB FPR8,4(,R3) Multiply short FPR8 by multiplier RXE +0000000000000478 7080 700C 000000000000000C 371 STE FPR8,12(,R7) Store short BFP product +000000000000047C B29C 800C 000000000000000C 372 STFPC 12(R8) Store resulting FPCR flags and DXC + 373 * +0000000000000480 4130 3008 0000000000000008 374 LA R3,2*4(,R3) Point to next input value pair +0000000000000484 4170 7010 0000000000000010 375 LA R7,4*4(,R7) Point to next product result set +0000000000000488 4180 8010 0000000000000010 376 LA R8,4*4(,R8) Point to next FPCR result set +000000000000048C 062C 377 BCTR R2,R12 Convert next input value. + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 11 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +000000000000048E 07FD 378 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 12 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 380 *********************************************************************** + 381 * + 382 * Perform Multiply using provided short BFP input pairs. This set of + 383 * tests exhaustively tests all rounding modes available for Multiply. + 384 * The rounding mode can only be specified in the FPC. + 385 * + 386 * All five FPC rounding modes are tested because the preceeding tests, + 387 * using rounding mode RNTE, do not often create results that require + 388 * rounding. + 389 * + 390 * Two results are generated for each input and rounding mode: one RRE + 391 * and one RXE. Traps are disabled for all rounding mode tests. + 392 * + 393 * The product and FPC contents are stored for each test. + 394 * + 395 *********************************************************************** + + +0000000000000490 9823 A000 0000000000000000 397 SBFPRM LM R2,R3,0(R10) Get count and address of test input values +0000000000000494 9878 A008 0000000000000008 398 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000498 1222 399 LTR R2,R2 Any test cases? +000000000000049A 078D 400 BZR R13 ..No, return to caller +000000000000049C 1711 401 XR R1,R1 Zero register 1 for use in IC/STC/indexing +000000000000049E 0DC0 402 BASR R12,0 Set top of test case loop + 403 +00000000000004A0 4150 0005 0000000000000005 404 LA R5,FPCMCT Get count of FPC modes to be tested +00000000000004A4 0D90 405 BASR R9,0 Set top of rounding mode outer loop + 406 * +00000000000004A6 4315 F783 0000000000000783 407 IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode + 408 * +00000000000004AA B29D F294 0000000000000294 409 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000004AE B2B8 1000 0000000000000000 410 SRNMB 0(R1) Set FPC Rounding Mode +00000000000004B2 7880 3000 0000000000000000 411 LE FPR8,0(,R3) Get short BFP multiplicand +00000000000004B6 7810 3004 0000000000000004 412 LE FPR1,4(,R3) Get short BFP multiplier +00000000000004BA B317 0081 413 MEEBR FPR8,FPR1 Multiply short FPR8 by FPR1 RRE +00000000000004BE 7080 7000 0000000000000000 414 STE FPR8,0(,R7) Store short BFP product +00000000000004C2 B29C 8000 0000000000000000 415 STFPC 0(R8) Store resulting FPCR flags and DXC + 416 * +00000000000004C6 B29D F294 0000000000000294 417 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000004CA B2B8 1000 0000000000000000 418 SRNMB 0(R1) Set FPC Rounding Mode +00000000000004CE 7880 3000 0000000000000000 419 LE FPR8,0(,R3) Get short BFP multiplicand +00000000000004D2 ED80 3004 0017 0000000000000004 420 MEEB FPR8,4(,R3) Multiply short FPR8 by multiplier RXE +00000000000004D8 7080 7004 0000000000000004 421 STE FPR8,4(,R7) Store short BFP product +00000000000004DC B29C 8004 0000000000000004 422 STFPC 4(R8) Store resulting FPCR flags and DXC + 423 * +00000000000004E0 4170 7008 0000000000000008 424 LA R7,2*4(,R7) Point to next product result set +00000000000004E4 4180 8008 0000000000000008 425 LA R8,2*4(,R8) Point to next FPCR result area + 426 * +00000000000004E8 0659 427 BCTR R5,R9 Iterate to next FPC mode for this input + 428 * + 429 * End of FPC modes to be tested. Advance to next test case. We will + 430 * skip eight bytes of result area so that each set of five result + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 13 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 431 * value pairs starts at a memory address ending in zero for the + 432 * convenience of memory dump review. + 433 * +00000000000004EA 4130 3008 0000000000000008 434 LA R3,2*4(,R3) Point to next input value pair +00000000000004EE 4170 7008 0000000000000008 435 LA R7,8(,R7) Skip to start of next result set +00000000000004F2 4180 8008 0000000000000008 436 LA R8,8(,R8) Skip to start of next FPCR result set +00000000000004F6 062C 437 BCTR R2,R12 Advance to the next input pair + 438 * +00000000000004F8 07FD 439 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 14 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 441 *********************************************************************** + 442 * + 443 * Perform Multiply using provided long BFP inputs. This set of tests + 444 * checks NaN propagation, operations on values that are not finite + 445 * numbers, and other basic tests. This set generates results that can + 446 * be validated against Figure 19-23 on page 19-28 of SA22-7832-10. + 447 * + 448 * Four results are generated for each input: one RRE with all + 449 * exceptions non-trappable, a second RRE with all exceptions trappable, + 450 * a third RXE with all exceptions non-trappable, a fourth RXE with all + 451 * exceptions trappable, + 452 * + 453 * The product and FPC contents are stored for each result. + 454 * + 455 *********************************************************************** + + +00000000000004FA 457 LBFPNF DS 0H BFP long non-finite values tests +00000000000004FA 9823 A000 0000000000000000 458 LM R2,R3,0(R10) Get count and addr of multiplicand values +00000000000004FE 9878 A008 0000000000000008 459 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000502 1222 460 LTR R2,R2 Any test cases? +0000000000000504 078D 461 BZR R13 ..No, return to caller +0000000000000506 0DC0 462 BASR R12,0 Set top of loop + 463 * +0000000000000508 9845 A000 0000000000000000 464 LM R4,R5,0(R10) Get count and start of multiplier values + 465 * ..which are the same as the multiplicands +000000000000050C 0D60 466 BASR R6,0 Set top of inner loop + 467 * +000000000000050E 6880 3000 0000000000000000 468 LD FPR8,0(,R3) Get long BFP multiplicand +0000000000000512 6810 5000 0000000000000000 469 LD FPR1,0(,R5) Get long BFP multiplier +0000000000000516 B29D F294 0000000000000294 470 LFPC FPCREGNT Set exceptions non-trappable +000000000000051A B31C 0081 471 MDBR FPR8,FPR1 Multiply long FPR8 by FPR1 RRE +000000000000051E 6080 7000 0000000000000000 472 STD FPR8,0(,R7) Store long BFP product +0000000000000522 B29C 8000 0000000000000000 473 STFPC 0(R8) Store resulting FPCR flags and DXC + 474 * +0000000000000526 6880 3000 0000000000000000 475 LD FPR8,0(,R3) Get long BFP multiplicand +000000000000052A 6810 5000 0000000000000000 476 LD FPR1,0(,R5) Get long BFP multiplier +000000000000052E B29D F298 0000000000000298 477 LFPC FPCREGTR Set exceptions trappable +0000000000000532 B31C 0081 478 MDBR FPR8,FPR1 Multiply long multiplier from FPR8 RRE +0000000000000536 6080 7008 0000000000000008 479 STD FPR8,8(,R7) Store long BFP remainder +000000000000053A B29C 8004 0000000000000004 480 STFPC 4(R8) Store resulting FPCR flags and DXC + 481 * +000000000000053E 6880 3000 0000000000000000 482 LD FPR8,0(,R3) Get long BFP multiplicand +0000000000000542 B29D F294 0000000000000294 483 LFPC FPCREGNT Set exceptions non-trappable +0000000000000546 ED80 5000 001C 0000000000000000 484 MDB FPR8,0(,R5) Multiply long FPR8 by multiplier RXE +000000000000054C 6080 7010 0000000000000010 485 STD FPR8,16(,R7) Store long BFP product +0000000000000550 B29C 8008 0000000000000008 486 STFPC 8(R8) Store resulting FPCR flags and DXC + 487 * +0000000000000554 6880 3000 0000000000000000 488 LD FPR8,0(,R3) Get long BFP multiplicand +0000000000000558 B29D F298 0000000000000298 489 LFPC FPCREGTR Set exceptions trappable +000000000000055C ED80 5000 001C 0000000000000000 490 MDB FPR8,0(,R5) Multiply long FPR8 by multiplier RXE +0000000000000562 6080 7018 0000000000000018 491 STD FPR8,24(,R7) Store long BFP remainder + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 15 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000566 B29C 800C 000000000000000C 492 STFPC 12(R8) Store resulting FPCR flags and DXC + 493 * +000000000000056A 4150 5008 0000000000000008 494 LA R5,8(,R5) Point to next multiplier value +000000000000056E 4170 7020 0000000000000020 495 LA R7,4*8(,R7) Point to next Multiply result area +0000000000000572 4180 8010 0000000000000010 496 LA R8,4*4(,R8) Point to next Multiply FPCR area +0000000000000576 0646 497 BCTR R4,R6 Loop through right-hand values + 498 * +0000000000000578 4130 3008 0000000000000008 499 LA R3,8(,R3) Point to next multiplicand value +000000000000057C 062C 500 BCTR R2,R12 Multiply until all cases tested +000000000000057E 07FD 501 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 16 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 503 *********************************************************************** + 504 * + 505 * Perform Multiply using provided long BFP input pairs. This set of + 506 * tests triggers IEEE exceptions Overflow, Underflow, and Inexact and + 507 * collects non-trap and trap results. + 508 * + 509 * Four results are generated for each input: one RRE with all + 510 * exceptions non-trappable, a second RRE with all exceptions trappable, + 511 * a third RXE with all exceptions non-trappable, a fourth RXE with all + 512 * exceptions trappable, + 513 * + 514 * The product and FPC contents are stored for each result. + 515 * + 516 *********************************************************************** + + +0000000000000580 9823 A000 0000000000000000 518 LBFPF LM R2,R3,0(R10) Get count and address of test input values +0000000000000584 9878 A008 0000000000000008 519 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000588 1222 520 LTR R2,R2 Any test cases? +000000000000058A 078D 521 BZR R13 ..No, return to caller +000000000000058C 0DC0 522 BASR R12,0 Set top of loop + 523 * +000000000000058E B29D F294 0000000000000294 524 LFPC FPCREGNT Set exceptions non-trappable +0000000000000592 6880 3000 0000000000000000 525 LD FPR8,0(,R3) Get long BFP multiplicand +0000000000000596 6810 3008 0000000000000008 526 LD FPR1,8(,R3) Get long BFP multiplier +000000000000059A B31C 0081 527 MDBR FPR8,FPR1 Multiply long FPR8 by FPR1 RRE +000000000000059E 6080 7000 0000000000000000 528 STD FPR8,0(,R7) Store long BFP product +00000000000005A2 B29C 8000 0000000000000000 529 STFPC 0(R8) Store resulting FPCR flags and DXC + 530 * +00000000000005A6 B29D F298 0000000000000298 531 LFPC FPCREGTR Set exceptions trappable +00000000000005AA 6880 3000 0000000000000000 532 LD FPR8,0(,R3) Reload long BFP multiplicand + 533 * ..multiplier is still in FPR1 +00000000000005AE B31C 0081 534 MDBR FPR8,FPR1 Multiply long FPR8 by FPR1 RRE +00000000000005B2 6080 7008 0000000000000008 535 STD FPR8,8(,R7) Store long BFP product +00000000000005B6 B29C 8004 0000000000000004 536 STFPC 4(R8) Store resulting FPCR flags and DXC + 537 * +00000000000005BA B29D F294 0000000000000294 538 LFPC FPCREGNT Set exceptions non-trappable +00000000000005BE 6880 3000 0000000000000000 539 LD FPR8,0(,R3) Reload long BFP multiplicand +00000000000005C2 ED80 3008 001C 0000000000000008 540 MDB FPR8,8(,R3) Multiply long FPR8 by multiplier RXE +00000000000005C8 6080 7010 0000000000000010 541 STD FPR8,16(,R7) Store long BFP product +00000000000005CC B29C 8008 0000000000000008 542 STFPC 8(R8) Store resulting FPCR flags and DXC + 543 * +00000000000005D0 B29D F298 0000000000000298 544 LFPC FPCREGTR Set exceptions trappable +00000000000005D4 6880 3000 0000000000000000 545 LD FPR8,0(,R3) Reload long BFP multiplicand +00000000000005D8 ED80 3008 001C 0000000000000008 546 MDB FPR8,8(,R3) Multiply long FPR8 by multiplier RXE +00000000000005DE 6080 7018 0000000000000018 547 STD FPR8,24(,R7) Store long BFP product +00000000000005E2 B29C 800C 000000000000000C 548 STFPC 12(R8) Store resulting FPCR flags and DXC + 549 * +00000000000005E6 4130 3010 0000000000000010 550 LA R3,2*8(,R3) Point to next input value pair +00000000000005EA 4170 7020 0000000000000020 551 LA R7,4*8(,R7) Point to next quotent result pair +00000000000005EE 4180 8010 0000000000000010 552 LA R8,4*4(,R8) Point to next FPCR result area +00000000000005F2 062C 553 BCTR R2,R12 Convert next input value. + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 17 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000005F4 07FD 554 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 18 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 556 *********************************************************************** + 557 * + 558 * Perform Multiply using provided long BFP input pairs. This set of + 559 * tests exhaustively tests all rounding modes available for Multiply. + 560 * The rounding mode can only be specified in the FPC. + 561 * + 562 * All five FPC rounding modes are tested because the preceeding tests, + 563 * using rounding mode RNTE, do not often create results that require + 564 * rounding. + 565 * + 566 * Two results are generated for each input and rounding mode: one RRE + 567 * and one RXE. Traps are disabled for all rounding mode tests. + 568 * + 569 * The product and FPC contents are stored for each result. + 570 * + 571 *********************************************************************** + + +00000000000005F6 9823 A000 0000000000000000 573 LBFPRM LM R2,R3,0(R10) Get count and address of test input values +00000000000005FA 9878 A008 0000000000000008 574 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000005FE 1222 575 LTR R2,R2 Any test cases? +0000000000000600 078D 576 BZR R13 ..No, return to caller +0000000000000602 1711 577 XR R1,R1 Zero register 1 for use in IC/STC/indexing +0000000000000604 0DC0 578 BASR R12,0 Set top of test case loop + 579 +0000000000000606 4150 0005 0000000000000005 580 LA R5,FPCMCT Get count of FPC modes to be tested +000000000000060A 0D90 581 BASR R9,0 Set top of rounding mode loop + 582 * +000000000000060C 4315 F783 0000000000000783 583 IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode + 584 * +0000000000000610 B29D F294 0000000000000294 585 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000614 B2B8 1000 0000000000000000 586 SRNMB 0(R1) Set FPC Rounding Mode +0000000000000618 6880 3000 0000000000000000 587 LD FPR8,0(,R3) Get long BFP multiplicand +000000000000061C 6810 3008 0000000000000008 588 LD FPR1,8(,R3) Get long BFP multiplier +0000000000000620 B31C 0081 589 MDBR FPR8,FPR1 Multiply long FPR8 by FPR1 RRE +0000000000000624 6080 7000 0000000000000000 590 STD FPR8,0(,R7) Store long BFP product +0000000000000628 B29C 8000 0000000000000000 591 STFPC 0(R8) Store resulting FPCR flags and DXC + 592 * +000000000000062C B29D F294 0000000000000294 593 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000630 B2B8 1000 0000000000000000 594 SRNMB 0(R1) Set FPC Rounding Mode +0000000000000634 6880 3000 0000000000000000 595 LD FPR8,0(,R3) Reload long BFP multiplicand +0000000000000638 ED80 3008 001C 0000000000000008 596 MDB FPR8,8(,R3) Multiply long FPR8 by multiplier RXE +000000000000063E 6080 7008 0000000000000008 597 STD FPR8,8(,R7) Store long BFP product +0000000000000642 B29C 8004 0000000000000004 598 STFPC 4(R8) Store resulting FPCR flags and DXC + 599 * +0000000000000646 4170 7010 0000000000000010 600 LA R7,2*8(,R7) Point to next product result set +000000000000064A 4180 8008 0000000000000008 601 LA R8,2*4(,R8) Point to next FPCR result area + 602 * +000000000000064E 0659 603 BCTR R5,R9 Iterate to next FPC mode + 604 * + 605 * End of FPC modes to be tested. Advance to next test case. We will + 606 * skip eight bytes of FPCR result area so that each set of five result + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 19 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 607 * FPCR contents pairs starts at a memory address ending in zero for the + 608 * convenience of memory dump review. + 609 * +0000000000000650 4130 3010 0000000000000010 610 LA R3,2*8(,R3) Point to next input value pair +0000000000000654 4180 8008 0000000000000008 611 LA R8,8(,R8) Skip to start of next FPCR result area +0000000000000658 062C 612 BCTR R2,R12 Multiply next input value lots of times + 613 * +000000000000065A 07FD 614 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 20 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 616 *********************************************************************** + 617 * + 618 * Perform Multiply using provided extended BFP inputs. This set of + 619 * tests checks NaN propagation, operations on values that are not + 620 * finite numbers, and other basic tests. This set generates results + 621 * that can be validated against Figure 19-23 on page 19-28 of + 622 * SA22-7832-10. + 623 * + 624 * Two results are generated for each input: one RRE with all + 625 * exceptions non-trappable, and a second RRE with all exceptions + 626 * trappable. Extended BFP Multiply does not have an RXE format. + 627 * + 628 * The product and FPC contents are stored for each result. + 629 * + 630 *********************************************************************** + + +000000000000065C 632 XBFPNF DS 0H BFP extended non-finite values tests +000000000000065C 9823 A000 0000000000000000 633 LM R2,R3,0(R10) Get count and addr of multiplicand values +0000000000000660 9878 A008 0000000000000008 634 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000664 1222 635 LTR R2,R2 Any test cases? +0000000000000666 078D 636 BZR R13 ..No, return to caller +0000000000000668 0DC0 637 BASR R12,0 Set top of loop + 638 * +000000000000066A 9845 A000 0000000000000000 639 LM R4,R5,0(R10) Get count and start of multiplier values + 640 * ..which are the same as the multiplicands +000000000000066E 0D60 641 BASR R6,0 Set top of inner loop + 642 * +0000000000000670 6880 3000 0000000000000000 643 LD FPR8,0(,R3) Get extended BFP multiplicand part 1 +0000000000000674 68A0 3008 0000000000000008 644 LD FPR10,8(,R3) Get extended BFP multiplicand part 2 +0000000000000678 6810 5000 0000000000000000 645 LD FPR1,0(,R5) Get extended BFP multiplier part 1 +000000000000067C 6830 5008 0000000000000008 646 LD FPR3,8(,R5) Get extended BFP multiplier part 2 +0000000000000680 B29D F294 0000000000000294 647 LFPC FPCREGNT Set exceptions non-trappable +0000000000000684 B34C 0081 648 MXBR FPR8,FPR1 Multiply extended FPR8-10 by FPR1-3 RRE +0000000000000688 6080 7000 0000000000000000 649 STD FPR8,0(,R7) Store extended BFP product part 1 +000000000000068C 60A0 7008 0000000000000008 650 STD FPR10,8(,R7) Store extended BFP product part 2 +0000000000000690 B29C 8000 0000000000000000 651 STFPC 0(R8) Store resulting FPCR flags and DXC + 652 * +0000000000000694 6880 3000 0000000000000000 653 LD FPR8,0(,R3) Get extended BFP multiplicand part 1 +0000000000000698 68A0 3008 0000000000000008 654 LD FPR10,8(,R3) Get extended BFP multiplicand part 2 +000000000000069C 6810 5000 0000000000000000 655 LD FPR1,0(,R5) Get extended BFP multiplier part 1 +00000000000006A0 6830 5008 0000000000000008 656 LD FPR3,8(,R5) Get extended BFP multiplier part 2 +00000000000006A4 B29D F298 0000000000000298 657 LFPC FPCREGTR Set exceptions trappable +00000000000006A8 B34C 0081 658 MXBR FPR8,FPR1 Multiply extended FPR8-10 by FPR1-3 RRE +00000000000006AC 6080 7010 0000000000000010 659 STD FPR8,16(,R7) Store extended BFP product part 1 +00000000000006B0 60A0 7018 0000000000000018 660 STD FPR10,24(,R7) Store extended BFP product part 2 +00000000000006B4 B29C 8004 0000000000000004 661 STFPC 4(R8) Store resulting FPCR flags and DXC + 662 * +00000000000006B8 4150 5010 0000000000000010 663 LA R5,16(,R5) Point to next multiplier value +00000000000006BC 4170 7020 0000000000000020 664 LA R7,32(,R7) Point to next Multiply result area +00000000000006C0 4180 8010 0000000000000010 665 LA R8,16(,R8) Point to next Multiply FPCR area +00000000000006C4 0646 666 BCTR R4,R6 Loop through right-hand values + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 21 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 667 * +00000000000006C6 4130 3010 0000000000000010 668 LA R3,16(,R3) Point to next multiplicand value +00000000000006CA 062C 669 BCTR R2,R12 Multiply until all cases tested +00000000000006CC 07FD 670 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 22 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 672 *********************************************************************** + 673 * + 674 * Perform Multiply using provided extended BFP input pairs. This set + 675 * of tests triggers IEEE exceptions Overflow, Underflow, and Inexact + 676 * and collects results when the exceptions do not result in a trap and + 677 * when they do. + 678 * + 679 * Two results are generated for each input: one RRE with all + 680 * exceptions non-trappable and a second RRE with all exceptions + 681 * trappable. There is no RXE format for Multiply in extended + 682 * precision. + 683 * + 684 * The product and FPC contents are stored for each result. + 685 * + 686 *********************************************************************** + + +00000000000006CE 9823 A000 0000000000000000 688 XBFPF LM R2,R3,0(R10) Get count and address of test input values +00000000000006D2 9878 A008 0000000000000008 689 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000006D6 1222 690 LTR R2,R2 Any test cases? +00000000000006D8 078D 691 BZR R13 ..No, return to caller +00000000000006DA 0DC0 692 BASR R12,0 Set top of loop + 693 * +00000000000006DC B29D F294 0000000000000294 694 LFPC FPCREGNT Set exceptions non-trappable +00000000000006E0 6880 3000 0000000000000000 695 LD FPR8,0(,R3) Get extended BFP multiplicand part 1 +00000000000006E4 68A0 3008 0000000000000008 696 LD FPR10,8(,R3) Get extended BFP multiplicand part 2 +00000000000006E8 6810 3010 0000000000000010 697 LD FPR1,16(,R3) Get extended BFP multiplier part 1 +00000000000006EC 6830 3018 0000000000000018 698 LD FPR3,24(,R3) Get extended BFP multiplier part 2 +00000000000006F0 B34C 0081 699 MXBR FPR8,FPR1 Multiply extended FPR8-10 by FPR1-3 RRE +00000000000006F4 6080 7000 0000000000000000 700 STD FPR8,0(,R7) Store extended BFP product part 1 +00000000000006F8 60A0 7008 0000000000000008 701 STD FPR10,8(,R7) Store extended BFP product part 2 +00000000000006FC B29C 8000 0000000000000000 702 STFPC 0(R8) Store resulting FPCR flags and DXC + 703 * +0000000000000700 B29D F298 0000000000000298 704 LFPC FPCREGTR Set exceptions trappable +0000000000000704 6880 3000 0000000000000000 705 LD FPR8,0(,R3) Reload extended BFP multiplicand part 1 +0000000000000708 68A0 3008 0000000000000008 706 LD FPR10,8(,R3) Reload extended BFP multiplicand part 2 + 707 * ..multiplier is still in FPR1-FPR3 +000000000000070C B34C 0081 708 MXBR FPR8,FPR1 Multiply extended FPR8-10 by FPR1-3 RRE +0000000000000710 6080 7010 0000000000000010 709 STD FPR8,16(,R7) Store extended BFP product part 1 +0000000000000714 60A0 7018 0000000000000018 710 STD FPR10,24(,R7) Store extended BFP product part 2 +0000000000000718 B29C 8004 0000000000000004 711 STFPC 4(R8) Store resulting FPCR flags and DXC + 712 * +000000000000071C 4130 3020 0000000000000020 713 LA R3,32(,R3) Point to next input value pair +0000000000000720 4170 7020 0000000000000020 714 LA R7,32(,R7) Point to next quotent result pair +0000000000000724 4180 8010 0000000000000010 715 LA R8,16(,R8) Point to next FPCR result area +0000000000000728 062C 716 BCTR R2,R12 Convert next input value. + 717 * +000000000000072A 07FD 718 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 23 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 720 *********************************************************************** + 721 * + 722 * Perform Multiply using provided extended BFP input pairs. This set + 723 * of tests exhaustively tests all rounding modes available for + 724 * Multiply. The rounding mode can only be specified in the FPC. + 725 * + 726 * All five FPC rounding modes are tested because the preceeding tests, + 727 * using rounding mode RNTE, do not often create results that require + 728 * rounding. + 729 * + 730 * Two results are generated for each input and rounding mode: one RRE + 731 * and one RXE. Traps are disabled for all rounding mode tests. + 732 * + 733 * The product and FPC contents are stored for each result. + 734 * + 735 *********************************************************************** + + +000000000000072C 9823 A000 0000000000000000 737 XBFPRM LM R2,R3,0(R10) Get count and address of test input values +0000000000000730 9878 A008 0000000000000008 738 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000734 1222 739 LTR R2,R2 Any test cases? +0000000000000736 078D 740 BZR R13 ..No, return to caller +0000000000000738 1711 741 XR R1,R1 Zero register 1 for use in IC/STC/indexing +000000000000073A 0DC0 742 BASR R12,0 Set top of test case loop + 743 +000000000000073C 4150 0005 0000000000000005 744 LA R5,FPCMCT Get count of FPC modes to be tested +0000000000000740 0D90 745 BASR R9,0 Set top of rounding mode loop + 746 * +0000000000000742 4315 F783 0000000000000783 747 IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode + 748 * +0000000000000746 B29D F294 0000000000000294 749 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000074A B2B8 1000 0000000000000000 750 SRNMB 0(R1) Set FPC Rounding Mode +000000000000074E 6880 3000 0000000000000000 751 LD FPR8,0(,R3) Get extended BFP multiplicand part 1 +0000000000000752 68A0 3008 0000000000000008 752 LD FPR10,8(,R3) Get extended BFP multiplicand part 2 +0000000000000756 6810 3010 0000000000000010 753 LD FPR1,16(,R3) Get extended BFP multiplier part 1 +000000000000075A 6830 3018 0000000000000018 754 LD FPR3,24(,R3) Get extended BFP multiplier part 2 +000000000000075E B34C 0081 755 MXBR FPR8,FPR1 Multiply extended FPR8-10 by FPR1-3 RRE +0000000000000762 6080 7000 0000000000000000 756 STD FPR8,0(,R7) Store extended BFP product part 1 +0000000000000766 60A0 7008 0000000000000008 757 STD FPR10,8(,R7) Store extended BFP product part 2 +000000000000076A B29C 8000 0000000000000000 758 STFPC 0(R8) Store resulting FPCR flags and DXC + 759 * +000000000000076E 4170 7010 0000000000000010 760 LA R7,16(,R7) Point to next product result set +0000000000000772 4180 8004 0000000000000004 761 LA R8,4(,R8) Point to next FPCR result area + 762 * +0000000000000776 0659 763 BCTR R5,R9 Iterate to next FPC mode + 764 * + 765 * End of FPC modes to be tested. Advance to next test case. We will + 766 * skip eight bytes of FPCR result area so that each set of five result + 767 * FPCR contents pairs starts at a memory address ending in zero for the + 768 * convenience of memory dump review. + 769 * +0000000000000778 4130 3020 0000000000000020 770 LA R3,2*16(,R3) Point to next input value pair + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 24 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +000000000000077C 4180 800C 000000000000000C 771 LA R8,12(,R8) Skip to start of next FPCR result area +0000000000000780 062C 772 BCTR R2,R12 Multiply next input value lots of times + 773 * +0000000000000782 07FD 774 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 25 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 776 *********************************************************************** + 777 * + 778 * Table of FPC rounding modes to test product rounding modes. + 779 * + 780 * The Set BFP Rounding Mode does allow specification of the FPC + 781 * rounding mode as an address, so we shall index into a table of + 782 * BFP rounding modes without bothering with Execute. + 783 * + 784 *********************************************************************** + + + 786 * + 787 * Rounding modes that may be set in the FPCR. The FPCR controls + 788 * rounding of the product. + 789 * + 790 * These are indexed directly by the loop counter, which counts down. + 791 * So the modes are listed in reverse order here. + 792 * +0000000000000784 793 FPCMODES DS 0C +0000000000000784 07 794 DC AL1(7) RFS, Round for shorter precision +0000000000000785 03 795 DC AL1(3) RM, Round to -infinity +0000000000000786 02 796 DC AL1(2) RP, Round to +infinity +0000000000000787 01 797 DC AL1(1) RZ, Round to zero +0000000000000788 00 798 DC AL1(0) RNTE, Round to Nearest, ties to even + 0000000000000005 0000000000000001 799 FPCMCT EQU *-FPCMODES Count of FPC Modes to be tested + 800 * + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 26 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 802 *********************************************************************** + 803 * + 804 * Short BFP test data sets for Multiply testing. + 805 * + 806 * The first test data set is used for tests of basic functionality, + 807 * NaN propagation, and results from operations involving other than + 808 * finite numbers. + 809 * + 810 * The second test data set is used for testing boundary conditions + 811 * using two finite non-zero values. Each possible type of result + 812 * (normal, scaled, etc) is created by members of this test data set. + 813 * + 814 * The third test data set is used for exhaustive testing of final + 815 * results across the five rounding modes available for the Multiply + 816 * instruction. + 817 * + 818 * The strategy for predictable rounding mode testing is to use a + 819 * multiplicand with some one-bits in the low-order byte and multiply + 820 * that by 1/16 (0.0625). In BFP, this will have the effect of shifting + 821 * the low-order byte out of the target precision representation and + 822 * into the high-order portion of the bits that control rounding. The + 823 * input low-order byte will be determined by the rounding desired. + 824 * + 825 *********************************************************************** + + + 827 *********************************************************************** + 828 * + 829 * First input test data set, to test operations using non-finite or + 830 * zero inputs. Member values chosen to validate Figure 19-23 on page + 831 * 19-28 of SA22-7832-10. Each value in this table is tested against + 832 * every other value in the table. Eight entries means 64 result sets. + 833 * + 834 *********************************************************************** + + +000000000000078C 836 SBFPNFIN DS 0F Inputs for short BFP non-finite tests +000000000000078C FF800000 837 DC X'FF800000' -inf +0000000000000790 C0000000 838 DC X'C0000000' -2.0 +0000000000000794 80000000 839 DC X'80000000' -0 +0000000000000798 00000000 840 DC X'00000000' +0 +000000000000079C 40000000 841 DC X'40000000' +2.0 +00000000000007A0 7F800000 842 DC X'7F800000' +inf +00000000000007A4 FFCB0000 843 DC X'FFCB0000' -QNaN +00000000000007A8 7F8A0000 844 DC X'7F8A0000' +SNaN + 0000000000000008 0000000000000001 845 SBFPNFCT EQU (*-SBFPNFIN)/4 Count of short BFP in list + + + + 847 *********************************************************************** + 848 * + 849 * Second input test data set. These are finite pairs intended to + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 27 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 850 * trigger overflow, underflow, and inexact exceptions. Each pair is + 851 * added twice, once non-trappable and once trappable. Trappable + 852 * overflow or underflow yields a scaled result. Trappable inexact + 853 * will show whether the Incremented DXC code is returned. + 854 * + 855 * The following test cases are required: + 856 * 1. Overflow + 857 * 2. Underflow - normal inputs + 858 * 3. Underflow - subnormal inputs + 859 * 4. Normal - from subnormal inputs + 860 * 5. Inexact - incremented + 861 * 6. Inexact - truncated + 862 * + 863 *********************************************************************** + + +00000000000007AC 865 SBFPIN DS 0F Inputs for short BFP finite tests + 866 * + 867 * Overflow on subtraction + 868 * +00000000000007AC 7F7FFFFF 869 DC X'7F7FFFFF' +Nmax +00000000000007B0 FF7FFFFF 870 DC X'FF7FFFFF' -Nmax + 871 * + 872 * Underflow from product of normals. We will multiply a small normal + 873 * by a slightly smaller normal to generate a subnormal. + 874 * +00000000000007B4 00FFFFFF 875 DC X'00FFFFFF' Very small normal number +00000000000007B8 00800000 876 DC X'00800000' Smaller normal (+Nmin) + 877 * + 878 * Underflow from the product of subnormals. + 879 * +00000000000007BC 00040000 880 DC X'00040000' Subnormal, < +Dmax +00000000000007C0 00000F0F 881 DC X'00000F0F' Smaller subnormal + 882 * + 883 * We cannot generate a normal result from product of subnormals + 884 * because the result will be smaller than both the multiplicand and the + 885 * multiplier. So we'll try multiplying +Dmax by 2. The result should + 886 * be +Nmin + 887 * +00000000000007C4 007FFFFF 888 DC X'007FFFFF' +Dmax +00000000000007C8 40000000 889 DC X'40000000' +2.0 + 890 * + 891 * Multiply a value from 1.0 such that the added digits are to the right + 892 * of the right-most bit in the stored significand. The result will be + 893 * inexact, and incremented will be determined by the value of the + 894 * bits in the multiplier. + 895 * +00000000000007CC 3F80000C 896 DC X'3F80000C' Multiplicand 1.000001430511474609375 +00000000000007D0 3F880000 897 DC X'3F880000' Multiplier 1.0625 (1/16) + 898 *..nearest is away from zero, incremented. + 899 * +00000000000007D4 3F800007 900 DC X'3F800007' Multiplicand 1.00000083446502685546875 + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 28 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000007D8 3F880000 901 DC X'3F880000' Multiplier 1.0625 (1/16) + 902 *..nearest is toward zero, truncated + 903 * + 0000000000000006 0000000000000001 904 SBFPCT EQU (*-SBFPIN)/4/2 Count of short BFP in list + + + + 906 *********************************************************************** + 907 * + 908 * Third input test data set. These are finite pairs intended to + 909 * test all combinations of rounding mode for the product and the + 910 * remainder. Values are chosen to create a requirement to round + 911 * to the target precision after the computation and to generate + 912 * varying results depending on the rounding mode in the FPCR. + 913 * + 914 * The result set will have cases that represent each of the following + 915 * + 916 * 1. Positive, nearest magnitude is toward zero. + 917 * 2. Negative, nearest magnitude is toward zero. + 918 * 3. Positive, nearest magnitude is away from zero. + 919 * 4. Negative, nearest magnitude is away from zero. + 920 * 5. Positive, tie, nearest even has greater magnitude + 921 * 6. Negative, tie, nearest even has greater magnitude + 922 * 7. Positive, tie, nearest even has lower magnitude + 923 * 8. Negative, tie, nearest even has lower magnitude + 924 * + 925 * Round For Shorter precision correctness can be determined from the + 926 * above test cases. + 927 * + 928 *********************************************************************** + + +00000000000007DC 930 SBFPINRM DS 0F Inputs for short BFP rounding testing + 931 * + 932 * Multiply a value from 1.0 such that the added digits are to the right + 933 * of the right-most bit in the stored significand. The result will be + 934 * inexact, and incremented will be determined by the value of the + 935 * bits in the multiplier. + 936 * +00000000000007DC 3F800007 937 DC X'3F800007' Multiplicand +1.00000083446502685546875 +00000000000007E0 3F880000 938 DC X'3F880000' Multiplier 1.0625 (1/16) +00000000000007E4 BF800007 939 DC X'BF800007' Multiplicand -1.00000083446502685546875 +00000000000007E8 3F880000 940 DC X'3F880000' Multiplier 1.0625 (1/16) + 941 *..nearest is toward zero, truncated + 942 * +00000000000007EC 3F80000C 943 DC X'3F80000C' Multiplicand +1.000001430511474609375 +00000000000007F0 3F880000 944 DC X'3F880000' Multiplier 1.0625 (1/16) +00000000000007F4 BF80000C 945 DC X'BF80000C' Multiplicand -1.000001430511474609375 +00000000000007F8 3F880000 946 DC X'3F880000' Multiplier 1.0625 (1/16) + 947 *..nearest is away from zero, incremented. + 948 * +00000000000007FC 3F800008 949 DC X'3F800008' Multiplicand +1.000000476837158203125 + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 29 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000800 3F880000 950 DC X'3F880000' Multiplier 1.0625 (1/16) +0000000000000804 BF800008 951 DC X'BF800008' Multiplicand -1.000000476837158203125 +0000000000000808 3F880000 952 DC X'3F880000' Multiplier 1.0625 (1/16) + 953 *..nearest is a tie, nearest even has lower magnitude + 954 * +000000000000080C 3F800018 955 DC X'3F800018' Multiplicand +1.000002384185791015625 +0000000000000810 3F880000 956 DC X'3F880000' Multiplier 1.0625 (1/16) +0000000000000814 BF800018 957 DC X'BF800018' Multiplicand -1.000002384185791015625 +0000000000000818 3F880000 958 DC X'3F880000' Multiplier 1.0625 (1/16) + 959 *..nearest is a tie, nearest even has greater magnitude + 960 * + 0000000000000008 0000000000000001 961 SBFPRMCT EQU (*-SBFPINRM)/4/2 Count of short BFP rounding tests + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 30 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 963 *********************************************************************** + 964 * + 965 * Long BFP test data sets for Add testing. + 966 * + 967 * The first test data set is used for tests of basic functionality, + 968 * NaN propagation, and results from operations involving other than + 969 * finite numbers. + 970 * + 971 * The second test data set is used for testing boundary conditions + 972 * using two finite non-zero values. Each possible type of result + 973 * (normal, scaled, etc) is created by members of this test data set. + 974 * + 975 * The third test data set is used for exhaustive testing of final + 976 * results across the five rounding modes available for the Add + 977 * instruction. + 978 * + 979 * See the Short BFP test cases header for a discussion of test case + 980 * selection for rounding mode test case values. + 981 * + 982 *********************************************************************** + + + 984 *********************************************************************** + 985 * + 986 * First input test data set, to test operations using non-finite or + 987 * zero inputs. Member values chosen to validate Figure 19-23 on page + 988 * 19-28 of SA22-7832-10. Each value in this table is tested against + 989 * every other value in the table. Eight entries means 64 result sets. + 990 * + 991 *********************************************************************** + + +000000000000081C 993 LBFPNFIN DS 0F Inputs for long BFP testing +000000000000081C FFF00000 00000000 994 DC X'FFF0000000000000' -inf +0000000000000824 C0000000 00000000 995 DC X'C000000000000000' -2.0 +000000000000082C 80000000 00000000 996 DC X'8000000000000000' -0 +0000000000000834 00000000 00000000 997 DC X'0000000000000000' +0 +000000000000083C 40000000 00000000 998 DC X'4000000000000000' +2.0 +0000000000000844 7FF00000 00000000 999 DC X'7FF0000000000000' +inf +000000000000084C FFF8B000 00000000 1000 DC X'FFF8B00000000000' -QNaN +0000000000000854 7FF0A000 00000000 1001 DC X'7FF0A00000000000' +SNaN + 0000000000000008 0000000000000001 1002 LBFPNFCT EQU (*-LBFPNFIN)/8 Count of long BFP in list + + + + 1004 *********************************************************************** + 1005 * + 1006 * Second input test data set. These are finite pairs intended to + 1007 * trigger overflow, underflow, and inexact exceptions. Each pair is + 1008 * added twice, once non-trappable and once trappable. Trappable + 1009 * overflow or underflow yields a scaled result. Trappable inexact + 1010 * will show whether the Incremented DXC code is returned. + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 31 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1011 * + 1012 * The following test cases are required: + 1013 * 1. Overflow + 1014 * 2. Underflow - normal inputs + 1015 * 3. Underflow - subnormal inputs + 1016 * 4. Normal - from subnormal inputs + 1017 * 5. Inexact - incremented + 1018 * 6. Inexact - truncated + 1019 * + 1020 *********************************************************************** + + +0000000000000860 1022 LBFPIN DS 0D Inputs for long BFP finite tests + 1023 * + 1024 * Overflow on multiplication + 1025 * +0000000000000860 7FEFFFFF FFFFFFFF 1026 DC X'7FEFFFFFFFFFFFFF' +Nmax +0000000000000868 FFEFFFFF FFFFFFFF 1027 DC X'FFEFFFFFFFFFFFFF' +Nmax + 1028 * + 1029 * Underflow from product of normals. We wil multiply a small + 1030 * normal by a slightly smaller normal to generate a subnormal. + 1031 * +0000000000000870 001FFFFF FFFFFFFF 1032 DC X'001FFFFFFFFFFFFF' Very small normal number +0000000000000878 00100000 00000000 1033 DC X'0010000000000000' Smaller normal negative + 1034 * + 1035 * Underflow from product of subnormals. + 1036 * +0000000000000880 00080000 00000000 1037 DC X'0008000000000000' Subnormal, < +Dmax +0000000000000888 0000F0F0 00000000 1038 DC X'0000F0F000000000' Smaller subnormal + 1039 * + 1040 * We cannot generate a normal result from product of subnormals + 1041 * because the result will be smaller than both the multiplicand and the + 1042 * multiplier. So we'll try multiplying +Dmax by 2. The result should + 1043 * be +Nmin + 1044 * +0000000000000890 000FFFFF FFFFFFFF 1045 DC X'000FFFFFFFFFFFFF' +Dmax +0000000000000898 40000000 00000000 1046 DC X'4000000000000000' +2.0, result should be normal + 1047 * + 1048 * Multiply a value from 1.0 such that the added digits are to the right + 1049 * of the right-most bit in the stored significand. The result will be + 1050 * inexact, and incremented will be determined by the value of the + 1051 * bits in the multiplier. + 1052 * +00000000000008A0 3FF00000 0000000C 1053 DC X'3FF000000000000C' Multiplicand +1, aka 1.0b0 +00000000000008A8 3FF10000 00000000 1054 DC X'3FF1000000000000' Multiplier 1.0625 (1/16) + 1055 *..nearest is away from zero, incremented. + 1056 * +00000000000008B0 3FF00000 00000007 1057 DC X'3FF0000000000007' Multiplicand +1, aka 1.0b0 +00000000000008B8 3FF10000 00000000 1058 DC X'3FF1000000000000' Multiplier 1.0625 (1/16) + 1059 *..nearest is toward zero, truncated. + 1060 * + 0000000000000006 0000000000000001 1061 LBFPCT EQU (*-LBFPIN)/8/2 Count of long BFP in list + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 32 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + + + + 1063 *********************************************************************** + 1064 * + 1065 * Third input test data set. These are finite pairs intended to + 1066 * test all combinations of rounding mode for the product and the + 1067 * remainder. Values are chosen to create a requirement to round + 1068 * to the target precision after the computation and to generate + 1069 * varying results depending on the rounding mode in the FPCR. + 1070 * + 1071 * The result set will have cases that represent each of the following + 1072 * + 1073 * 1. Positive, nearest magnitude is toward zero. + 1074 * 2. Negative, nearest magnitude is toward zero. + 1075 * 3. Positive, nearest magnitude is away from zero. + 1076 * 4. Negative, nearest magnitude is away from zero. + 1077 * 5. Positive, tie, nearest even has greater magnitude + 1078 * 6. Negative, tie, nearest even has greater magnitude + 1079 * 7. Positive, tie, nearest even has lower magnitude + 1080 * 8. Negative, tie, nearest even has lower magnitude + 1081 * + 1082 * Round For Shorter precision correctness can be determined from the + 1083 * above test cases. + 1084 * + 1085 *********************************************************************** + + +00000000000008C0 1087 LBFPINRM DS 0F + 1088 * + 1089 * Multiply a value from 1.0 such that the added digits are to the right + 1090 * of the right-most bit in the stored significand. The result will be + 1091 * inexact, and incremented will be determined by the value of the + 1092 * bits in the multiplier. + 1093 * +00000000000008C0 3FF00000 00000007 1094 DC X'3FF0000000000007' Multiplicand +00000000000008C8 3FF10000 00000000 1095 DC X'3FF1000000000000' Multiplier 1.0625 (1/16) +00000000000008D0 BFF00000 00000007 1096 DC X'BFF0000000000007' Multiplicand +00000000000008D8 3FF10000 00000000 1097 DC X'3FF1000000000000' Multiplier 1.0625 (1/16) + 1098 *..nearest is toward zero, truncated. + 1099 * +00000000000008E0 3FF00000 0000000C 1100 DC X'3FF000000000000C' Multiplicand +00000000000008E8 3FF10000 00000000 1101 DC X'3FF1000000000000' Multiplier 1.0625 (1/16) +00000000000008F0 BFF00000 0000000C 1102 DC X'BFF000000000000C' Multiplicand +00000000000008F8 3FF10000 00000000 1103 DC X'3FF1000000000000' Multiplier 1.0625 (1/16) + 1104 *..nearest is away from zero, incremented. + 1105 * +0000000000000900 3FF00000 00000008 1106 DC X'3FF0000000000008' Multiplicand +0000000000000908 3FF10000 00000000 1107 DC X'3FF1000000000000' Multiplier 1.0625 (1/16) +0000000000000910 BFF00000 00000008 1108 DC X'BFF0000000000008' Multiplicand +0000000000000918 3FF10000 00000000 1109 DC X'3FF1000000000000' Multiplier 1.0625 (1/16) + 1110 *..nearest is a tie, nearest even has lower magnitude + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 33 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1111 * +0000000000000920 3FF00000 00000018 1112 DC X'3FF0000000000018' Multiplicand +1, aka +1.0b0 +0000000000000928 3FF10000 00000000 1113 DC X'3FF1000000000000' Multiplier 1.0625 (1/16) +0000000000000930 BFF00000 00000018 1114 DC X'BFF0000000000018' Multiplicand -1, aka -1.0b0 +0000000000000938 3FF10000 00000000 1115 DC X'3FF1000000000000' Multiplier 1.0625 (1/16) + 1116 *..nearest is a tie, nearest even has greater magnitude + 1117 * + 0000000000000008 0000000000000001 1118 LBFPRMCT EQU (*-LBFPINRM)/8/2 Count of long BFP rounding tests + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 34 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1120 *********************************************************************** + 1121 * + 1122 * Extended BFP test data sets for Add testing. + 1123 * + 1124 * The first test data set is used for tests of basic functionality, + 1125 * NaN propagation, and results from operations involving other than + 1126 * finite numbers. + 1127 * + 1128 * The second test data set is used for testing boundary conditions + 1129 * using two finite non-zero values. Each possible type of result + 1130 * (normal, scaled, etc) is created by members of this test data set. + 1131 * + 1132 * The third test data set is used for exhaustive testing of final + 1133 * results across the five rounding modes available for the Add + 1134 * instruction. + 1135 * + 1136 * See the Short BFP test cases header for a discussion of test case + 1137 * selection for rounding mode test case values. + 1138 * + 1139 *********************************************************************** + + + 1141 *********************************************************************** + 1142 * + 1143 * First input test data set, to test operations using non-finite or + 1144 * zero inputs. Member values chosen to validate Figure 19-23 on page + 1145 * 19-28 of SA22-7832-10. Each value in this table is tested against + 1146 * every other value in the table. Eight entries means 64 result sets. + 1147 * + 1148 *********************************************************************** + + +0000000000000940 1150 XBFPNFIN DS 0F Inputs for extended BFP testing +0000000000000940 FFFF0000 00000000 1151 DC X'FFFF0000000000000000000000000000' -inf +0000000000000950 C0000000 00000000 1152 DC X'C0000000000000000000000000000000' -2.0 +0000000000000960 80000000 00000000 1153 DC X'80000000000000000000000000000000' -0 +0000000000000970 00000000 00000000 1154 DC X'00000000000000000000000000000000' +0 +0000000000000980 40000000 00000000 1155 DC X'40000000000000000000000000000000' +2.0 +0000000000000990 7FFF0000 00000000 1156 DC X'7FFF0000000000000000000000000000' +inf +00000000000009A0 FFFF8B00 00000000 1157 DC X'FFFF8B00000000000000000000000000' -QNaN +00000000000009B0 7FFF0A00 00000000 1158 DC X'7FFF0A00000000000000000000000000' +SNaN + 0000000000000008 0000000000000001 1159 XBFPNFCT EQU (*-XBFPNFIN)/16 Count of extended BFP in list + + + + 1161 *********************************************************************** + 1162 * + 1163 * Second input test data set. These are finite pairs intended to + 1164 * trigger overflow, underflow, and inexact exceptions. Each pair is + 1165 * added twice, once non-trappable and once trappable. Trappable + 1166 * overflow or underflow yields a scaled result. Trappable inexact + 1167 * will show whether the Incremented DXC code is returned. + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 35 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1168 * + 1169 * The following test cases are required: + 1170 * The following test cases are required: + 1171 * 1. Overflow + 1172 * 2. Underflow - normal inputs + 1173 * 3. Underflow - subnormal inputs + 1174 * 4. Normal - from subnormal inputs + 1175 * 5. Inexact - incremented + 1176 * 6. Inexact - truncated + 1177 * + 1178 *********************************************************************** + + +00000000000009C0 1180 XBFPIN DS 0F Inputs for extended BFP finite tests + 1181 * + 1182 * Overflow on subtraction + 1183 * +00000000000009C0 7FFEFFFF FFFFFFFF 1184 DC X'7FFEFFFFFFFFFFFFFFFFFFFFFFFFFFFF' +Nmax +00000000000009D0 FFFEFFFF FFFFFFFF 1185 DC X'FFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFF' +Nmax + 1186 * + 1187 * Underflow from product of normals. We will multiply a small + 1188 * normal by a slightly smaller normal to generate a subnormal. + 1189 * +00000000000009E0 0001FFFF FFFFFFFF 1190 DC X'0001FFFFFFFFFFFFFFFFFFFFFFFFFFFF' Very small normal +00000000000009F0 00010000 00000000 1191 DC X'00010000000000000000000000000000' Smaller normal + 1192 * + 1193 * Underflow from product of subnormals. + 1194 * +0000000000000A00 00008000 00000000 1195 DC X'00008000000000000000000000000000' Subnormal, < +Dmax +0000000000000A10 00000F0F 00000000 1196 DC X'00000F0F000000000000000000000000' Smaller subnormal + 1197 * + 1198 * We cannot generate a normal result from product of subnormals + 1199 * because the result will be smaller than both the multiplicand and the + 1200 * multiplier. So we'll try multiplying +Dmax by 2. The result should + 1201 * be +Nmin + 1202 * +0000000000000A20 0000FFFF FFFFFFFF 1203 DC X'0000FFFFFFFFFFFFFFFFFFFFFFFFFFFF' +Dmax +0000000000000A30 40000000 00000000 1204 DC X'40000000000000000000000000000001' +2.0, + 1205 * ...result will be normal + 1206 * + 1207 * Multiply a value from 1.0 such that the added digits are to the right + 1208 * of the right-most bit in the stored significand. The result will be + 1209 * inexact, and incremented will be determined by the value of the + 1210 * bits in the multiplier. + 1211 * +0000000000000A40 3FFF0000 00000000 1212 DC X'3FFF000000000000000000000000000C' +1, aka 1.0b0 +0000000000000A50 3FFF1000 00000000 1213 DC X'3FFF1000000000000000000000000000' 1.0625 + 1214 *..nearest is away from zero, incremented. + 1215 * +0000000000000A60 3FFF0000 00000000 1216 DC X'3FFF0000000000000000000000000007' +1, aka 1.0b0 +0000000000000A70 3FFF1000 00000000 1217 DC X'3FFF1000000000000000000000000000' 1.0625 + 1218 *..nearest is toward zero, truncated + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 36 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1219 * + 0000000000000006 0000000000000001 1220 XBFPCT EQU (*-XBFPIN)/16/2 Count of extended BFP in list + + + + 1222 *********************************************************************** + 1223 * + 1224 * Third input test data set. These are finite pairs intended to + 1225 * test all combinations of rounding mode for the product and the + 1226 * remainder. Values are chosen to create a requirement to round + 1227 * to the target precision after the computation and to generate + 1228 * varying results depending on the rounding mode in the FPCR. + 1229 * + 1230 * The result set will have cases that represent each of the following + 1231 * + 1232 * 1. Positive, nearest magnitude is toward zero. + 1233 * 2. Negative, nearest magnitude is toward zero. + 1234 * 3. Positive, nearest magnitude is away from zero. + 1235 * 4. Negative, nearest magnitude is away from zero. + 1236 * 5. Positive, tie, nearest even has greater magnitude + 1237 * 6. Negative, tie, nearest even has greater magnitude + 1238 * 7. Positive, tie, nearest even has lower magnitude + 1239 * 8. Negative, tie, nearest even has lower magnitude + 1240 * + 1241 * Round For Shorter precision correctness can be determined from the + 1242 * above test cases. + 1243 * + 1244 *********************************************************************** + + +0000000000000A80 1246 XBFPINRM DS 0D + 1247 * + 1248 * Multiply a value from 1.0 such that the added digits are to the right + 1249 * of the right-most bit in the stored significand. The result will be + 1250 * inexact, and incremented will be determined by the value of the + 1251 * bits in the multiplier. + 1252 * +0000000000000A80 3FFF0000 00000000 1253 DC X'3FFF0000000000000000000000000007' +1, aka +1.0b0 +0000000000000A90 3FFF1000 00000000 1254 DC X'3FFF1000000000000000000000000000' 1.0625 +0000000000000AA0 BFFF0000 00000000 1255 DC X'BFFF0000000000000000000000000007' -1, aka -1.0b0 +0000000000000AB0 3FFF1000 00000000 1256 DC X'3FFF1000000000000000000000000000' 1.0625 + 1257 *..nearest is toward zero + 1258 * +0000000000000AC0 3FFF0000 00000000 1259 DC X'3FFF000000000000000000000000000C' +1, aka +1.0b0 +0000000000000AD0 3FFF1000 00000000 1260 DC X'3FFF1000000000000000000000000000' 1.0625 +0000000000000AE0 BFFF0000 00000000 1261 DC X'BFFF000000000000000000000000000C' -1, aka -1.0b0 +0000000000000AF0 3FFF1000 00000000 1262 DC X'3FFF1000000000000000000000000000' 1.0625 + 1263 *..nearest is away from zero + 1264 * +0000000000000B00 3FFF0000 00000000 1265 DC X'3FFF0000000000000000000000000008' +1, aka +1.0b0 +0000000000000B10 3FFF1000 00000000 1266 DC X'3FFF1000000000000000000000000000' 1.0625 +0000000000000B20 BFFF0000 00000000 1267 DC X'BFFF0000000000000000000000000008' -1, aka -1.0b0 + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 37 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000B30 3FFF1000 00000000 1268 DC X'3FFF1000000000000000000000000000' 1.0625 + 1269 *..nearest is a tie, nearest even has lower magnitude + 1270 * +0000000000000B40 3FFF0000 00000000 1271 DC X'3FFF0000000000000000000000000018' +1, aka +1.0b0 +0000000000000B50 3FFF1000 00000000 1272 DC X'3FFF1000000000000000000000000000' 1.0625 +0000000000000B60 BFFF0000 00000000 1273 DC X'BFFF0000000000000000000000000018' -1, aka -1.0b0 +0000000000000B70 3FFF1000 00000000 1274 DC X'3FFF1000000000000000000000000000' 1.0625 + 1275 *..nearest is a tie, nearest even has greater magnitude + 1276 * + 0000000000000008 0000000000000001 1277 XBFPRMCT EQU (*-XBFPINRM)/16/2 Count of long BFP rounding tests + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 38 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1279 * + 1280 * Locations for results + 1281 * + 0000000000001000 0000000000000001 1282 SBFPNFOT EQU STRTLABL+X'1000' Short non-finite BFP results + 1283 * ..room for 64 tests, 64 used + 0000000000001400 0000000000000001 1284 SBFPNFFL EQU STRTLABL+X'1400' FPCR flags and DXC from short BFP + 1285 * ..room for 64 tests, 64 used + 1286 * + 0000000000001800 0000000000000001 1287 SBFPOUT EQU STRTLABL+X'1800' Short BFP finite results + 1288 * ..room for 16 tests, 6 used + 0000000000001900 0000000000000001 1289 SBFPFLGS EQU STRTLABL+X'1900' FPCR flags and DXC from short BFP + 1290 * ..room for 16 tests, 6 used + 1291 * + 0000000000001A00 0000000000000001 1292 SBFPRMO EQU STRTLABL+X'1A00' Short BFP rounding mode test results + 1293 * ..Room for 16, 8 used. + 0000000000001D00 0000000000000001 1294 SBFPRMOF EQU STRTLABL+X'1D00' Short BFP rounding mode FPCR results + 1295 * ..Room for 16, 8 used. + 1296 * ..next location starts at X'2000' + 1297 * + 0000000000003000 0000000000000001 1298 LBFPNFOT EQU STRTLABL+X'3000' Long non-finite BFP results + 1299 * ..room for 64 tests, 64 used + 0000000000003800 0000000000000001 1300 LBFPNFFL EQU STRTLABL+X'3800' FPCR flags and DXC from long BFP + 1301 * ..room for 64 tests, 64 used + 1302 * + 0000000000003C00 0000000000000001 1303 LBFPOUT EQU STRTLABL+X'3C00' Long BFP finite results + 1304 * ..room for 16 tests, 6 used + 0000000000003E00 0000000000000001 1305 LBFPFLGS EQU STRTLABL+X'3E00' FPCR flags and DXC from long BFP + 1306 * ..room for 16 tests, 6 used + 1307 * + 0000000000004000 0000000000000001 1308 LBFPRMO EQU STRTLABL+X'4000' Long BFP rounding mode test results + 1309 * ..Room for 16, 8 used. + 0000000000004500 0000000000000001 1310 LBFPRMOF EQU STRTLABL+X'4500' Long BFP rounding mode FPCR results + 1311 * ..Room for 16, 8 used. + 1312 * ..next location starts at X'4800' + 1313 * + 0000000000005000 0000000000000001 1314 XBFPNFOT EQU STRTLABL+X'5000' Extended non-finite BFP results + 1315 * ..room for 64 tests, 64 used + 0000000000005800 0000000000000001 1316 XBFPNFFL EQU STRTLABL+X'5800' FPCR flags and DXC from ext'd BFP + 1317 * ..room for 64 tests, 64 used + 1318 * + 0000000000005C00 0000000000000001 1319 XBFPOUT EQU STRTLABL+X'5C00' Extended BFP finite results + 1320 * ..room for 16 tests, 6 used + 0000000000005E00 0000000000000001 1321 XBFPFLGS EQU STRTLABL+X'5E00' FPCR flags and DXC from ext'd BFP + 1322 * ..room for 16 tests, 6 used + 1323 * + 0000000000006000 0000000000000001 1324 XBFPRMO EQU STRTLABL+X'6000' Ext'd BFP rounding mode test results + 1325 * ..Room for 16, 8 used. + 0000000000006500 0000000000000001 1326 XBFPRMOF EQU STRTLABL+X'6500' Ext'd BFP rounding mode FPCR results + 1327 * ..Room for 16, 8 used. + 1328 * ..next location starts at X'6800' + 1329 * + 0000000000006800 0000000000000001 1330 ENDLABL EQU STRTLABL+X'6800' + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 39 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1331 PADCSECT ENDLABL + 1332+ MNOTE *,'asma detected; no CSECT padding performed' +0000000000000B80 1333 END + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 40 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +BFPMUL J 000000 2944 82 +CTLR0 F 000290 4 198 165 166 167 +ENDLABL U 006800 1 1330 +FPCMCT U 000005 1 799 404 580 744 +FPCMODES C 000784 1 793 799 407 583 747 +FPCREGNT X 000294 4 199 293 307 348 362 409 417 470 483 524 538 585 593 647 694 + 749 +FPCREGTR X 000298 4 200 300 313 355 368 477 489 531 544 657 704 +FPR0 U 000000 1 103 +FPR1 U 000001 1 104 292 294 299 301 306 350 351 358 412 413 469 471 476 478 + 526 527 534 588 589 645 648 655 658 697 699 708 753 755 +FPR10 U 00000A 1 113 644 650 654 660 696 701 706 710 752 757 +FPR11 U 00000B 1 114 +FPR12 U 00000C 1 115 +FPR13 U 00000D 1 116 +FPR14 U 00000E 1 117 +FPR15 U 00000F 1 118 +FPR2 U 000002 1 105 +FPR3 U 000003 1 106 646 656 698 754 +FPR4 U 000004 1 107 +FPR5 U 000005 1 108 +FPR6 U 000006 1 109 +FPR7 U 000007 1 110 +FPR8 U 000008 1 111 291 294 295 298 301 302 305 308 309 312 314 315 349 351 + 352 356 358 359 363 364 365 369 370 371 411 413 414 419 + 420 421 468 471 472 475 478 479 482 484 485 488 490 491 + 525 527 528 532 534 535 539 540 541 545 546 547 587 589 + 590 595 596 597 643 648 649 653 658 659 695 699 700 705 + 708 709 751 755 756 +FPR9 U 000009 1 112 +HARDWAIT X 000280 8 196 156 +IMAGE 1 000000 2944 0 +LBFPCT U 000006 1 1061 234 +LBFPF I 000580 4 518 179 +LBFPFLGS U 003E00 1 1305 237 +LBFPIN D 000860 8 1022 1061 235 +LBFPINRM F 0008C0 4 1087 1118 241 +LBFPNF H 0004FA 2 457 177 +LBFPNFCT U 000008 1 1002 228 +LBFPNFFL U 003800 1 1300 231 +LBFPNFIN F 00081C 4 993 1002 229 +LBFPNFOT U 003000 1 1298 230 +LBFPOUT U 003C00 1 1303 236 +LBFPRM I 0005F6 4 573 181 +LBFPRMCT U 000008 1 1118 240 +LBFPRMO U 004000 1 1308 242 +LBFPRMOF U 004500 1 1310 243 +LONGF F 000340 4 233 178 +LONGNF F 000330 4 227 176 +PCINTCD H 00008E 2 133 150 +PCNOTDTA H 00020C 2 153 151 +PCOLDPSW U 000150 1 135 152 + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 41 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +PROGCHK H 000200 2 149 141 +R0 U 000000 1 84 165 167 +R1 U 000001 1 85 401 407 410 418 577 583 586 594 741 747 750 +R10 U 00000A 1 94 169 171 173 176 178 180 183 185 187 281 282 287 342 343 + 397 398 458 459 464 518 519 573 574 633 634 639 688 689 + 737 738 +R11 U 00000B 1 95 +R12 U 00000C 1 96 285 324 346 377 402 437 462 500 522 553 578 612 637 669 + 692 716 742 772 +R13 U 00000D 1 97 170 172 174 177 179 181 184 186 188 284 325 345 378 400 + 439 461 501 521 554 576 614 636 670 691 718 740 774 +R14 U 00000E 1 98 154 155 190 191 +R15 U 00000F 1 99 120 +R2 U 000002 1 86 281 283 324 342 344 377 397 399 437 458 460 500 518 520 + 553 573 575 612 633 635 669 688 690 716 737 739 772 +R3 U 000003 1 87 281 291 298 305 312 323 342 349 350 356 363 364 369 370 + 374 397 411 412 419 420 434 458 468 475 482 488 499 518 + 525 526 532 539 540 545 546 550 573 587 588 595 596 610 + 633 643 644 653 654 668 688 695 696 697 698 705 706 713 + 737 751 752 753 754 770 +R4 U 000004 1 88 287 321 464 497 639 666 +R5 U 000005 1 89 287 292 299 306 308 314 318 404 407 427 464 469 476 484 + 490 494 580 583 603 639 645 646 655 656 663 744 747 763 +R6 U 000006 1 90 289 321 466 497 641 666 +R7 U 000007 1 91 282 295 302 309 315 319 343 352 359 365 371 375 398 414 + 421 424 435 459 472 479 485 491 495 519 528 535 541 547 + 551 574 590 597 600 634 649 650 659 660 664 689 700 701 + 709 710 714 738 756 757 760 +R8 U 000008 1 92 282 296 303 310 316 320 343 353 360 366 372 376 398 415 + 422 425 436 459 473 480 486 492 496 519 529 536 542 548 + 552 574 591 598 601 611 634 651 661 665 689 702 711 715 + 738 758 761 771 +R9 U 000009 1 93 405 427 581 603 745 763 +RMLONGS F 000350 4 239 180 +RMSHORTS F 000320 4 221 173 +RMXTNDS F 000380 4 257 187 +SBFPCT U 000006 1 904 216 +SBFPF I 00041A 4 342 172 +SBFPFLGS U 001900 1 1289 219 +SBFPIN F 0007AC 4 865 904 217 +SBFPINRM F 0007DC 4 930 961 223 +SBFPNF H 000390 2 280 170 +SBFPNFCT U 000008 1 845 210 +SBFPNFFL U 001400 1 1284 213 +SBFPNFIN F 00078C 4 836 845 211 +SBFPNFOT U 001000 1 1282 212 +SBFPOUT U 001800 1 1287 218 +SBFPRM I 000490 4 397 174 +SBFPRMCT U 000008 1 961 222 +SBFPRMO U 001A00 1 1292 224 +SBFPRMOF U 001D00 1 1294 225 +SHORTF F 000310 4 215 171 + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 42 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +SHORTNF F 000300 4 209 169 +START H 000214 2 164 138 +STRTLABL U 000000 1 83 132 135 137 140 148 208 1282 1284 1287 1289 1292 1294 1298 1300 + 1303 1305 1308 1310 1314 1316 1319 1321 1324 1326 1330 +WAITPSW X 000270 8 195 192 +XBFPCT U 000006 1 1220 252 +XBFPF I 0006CE 4 688 186 +XBFPFLGS U 005E00 1 1321 255 +XBFPIN F 0009C0 4 1180 1220 253 +XBFPINRM D 000A80 8 1246 1277 259 +XBFPNF H 00065C 2 632 184 +XBFPNFCT U 000008 1 1159 246 +XBFPNFFL U 005800 1 1316 249 +XBFPNFIN F 000940 4 1150 1159 247 +XBFPNFOT U 005000 1 1314 248 +XBFPOUT U 005C00 1 1319 254 +XBFPRM I 00072C 4 737 188 +XBFPRMCT U 000008 1 1277 258 +XBFPRMO U 006000 1 1324 260 +XBFPRMOF U 006500 1 1326 261 +XTNDF F 000370 4 251 185 +XTNDNF F 000360 4 245 183 + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 43 + + MACRO DEFN REFERENCES + +PADCSECT 57 1331 + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 44 + + DESC SYMBOL SIZE POS ADDR + +Entry: 0 + +Image IMAGE 2944 000-B7F 000-B7F + Region 2944 000-B7F 000-B7F + CSECT BFPMUL 2944 000-B7F 000-B7F + ASMA Ver. 0.2.0 bfp-019-multiply.asm: Test IEEE Multiply 09 Oct 2016 15:20:37 Page 45 + + STMT FILE NAME + +1 C:\Users\srorso\Documents\GitHub\hyperion\tests\bfp-019-multiply.asm + + +** NO ERRORS FOUND ** + +[1332] MNOTE *,asma detected; no CSECT padding performed + \ No newline at end of file diff --git a/tests/bfp-019-multiply.tst b/tests/bfp-019-multiply.tst new file mode 100644 index 000000000..b23f8a0ee --- /dev/null +++ b/tests/bfp-019-multiply.tst @@ -0,0 +1,1555 @@ +*Testcase bfp-019-multiply.tst: MEEBR, MEEB, MDBR, MDB, MXBR + +#..Test cases evaluate NaN propagation, NaN generation, operations +#..using non-finite values, trappable and non-trappable IEEE +#..exceptions, result scaling, and exhaustive rounding testing. +#..Excludes multiply to increased precision and fused multiply. + +sysclear +archmode esame + +# +# Following suppresses logging of program checks. This test program, as part +# of its normal operation, generates 141 program check messages that have no +# value in the validation process. +# +ostailor quiet + +loadcore "$(testpath)/bfp-019-multiply.core" + +runtest 1.0 + +ostailor null # restore messages for subsequent tests + + +# Short BFP non-finite test results +*Compare +r 1000.10 +*Want "MEEBR/MEEB NF -inf/-inf" 7F800000 7F800000 7F800000 7F800000 +r 1010.10 +*Want "MEEBR/MEEB NF -inf/-2.0" 7F800000 7F800000 7F800000 7F800000 +r 1020.10 +*Want "MEEBR/MEEB NF -inf/-0" 7FC00000 FF800000 7FC00000 FF800000 +r 1030.10 +*Want "MEEBR/MEEB NF -inf/+0" 7FC00000 FF800000 7FC00000 FF800000 +r 1040.10 +*Want "MEEBR/MEEB NF -inf/+2.0" FF800000 FF800000 FF800000 FF800000 +r 1050.10 +*Want "MEEBR/MEEB NF -inf/+inf" FF800000 FF800000 FF800000 FF800000 +r 1060.10 +*Want "MEEBR/MEEB NF -inf/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1070.10 +*Want "MEEBR/MEEB NF -inf/+SNaN" 7FCA0000 FF800000 7FCA0000 FF800000 +r 1080.10 +*Want "MEEBR/MEEB NF -2.0/-inf" 7F800000 7F800000 7F800000 7F800000 +r 1090.10 +*Want "MEEBR/MEEB NF -2.0/-2.0" 40800000 40800000 40800000 40800000 +r 10A0.10 +*Want "MEEBR/MEEB NF -2.0/-0" 00000000 00000000 00000000 00000000 +r 10B0.10 +*Want "MEEBR/MEEB NF -2.0/+0" 80000000 80000000 80000000 80000000 +r 10C0.10 +*Want "MEEBR/MEEB NF -2.0/+2.0" C0800000 C0800000 C0800000 C0800000 +r 10D0.10 +*Want "MEEBR/MEEB NF -2.0/+inf" FF800000 FF800000 FF800000 FF800000 +r 10E0.10 +*Want "MEEBR/MEEB NF -2.0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 10F0.10 +*Want "MEEBR/MEEB NF -2.0/+SNaN" 7FCA0000 C0000000 7FCA0000 C0000000 +r 1100.10 +*Want "MEEBR/MEEB NF -0/-inf" 7FC00000 80000000 7FC00000 80000000 +r 1110.10 +*Want "MEEBR/MEEB NF -0/-2.0" 00000000 00000000 00000000 00000000 +r 1120.10 +*Want "MEEBR/MEEB NF -0/-0" 00000000 00000000 00000000 00000000 +r 1130.10 +*Want "MEEBR/MEEB NF -0/+0" 80000000 80000000 80000000 80000000 +r 1140.10 +*Want "MEEBR/MEEB NF -0/+2.0" 80000000 80000000 80000000 80000000 +r 1150.10 +*Want "MEEBR/MEEB NF -0/+inf" 7FC00000 80000000 7FC00000 80000000 +r 1160.10 +*Want "MEEBR/MEEB NF -0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1170.10 +*Want "MEEBR/MEEB NF -0/+SNaN" 7FCA0000 80000000 7FCA0000 80000000 +r 1180.10 +*Want "MEEBR/MEEB NF +0/-inf" 7FC00000 00000000 7FC00000 00000000 +r 1190.10 +*Want "MEEBR/MEEB NF +0/-2.0" 80000000 80000000 80000000 80000000 +r 11A0.10 +*Want "MEEBR/MEEB NF +0/-0" 80000000 80000000 80000000 80000000 +r 11B0.10 +*Want "MEEBR/MEEB NF +0/+0" 00000000 00000000 00000000 00000000 +r 11C0.10 +*Want "MEEBR/MEEB NF +0/+2.0" 00000000 00000000 00000000 00000000 +r 11D0.10 +*Want "MEEBR/MEEB NF +0/+inf" 7FC00000 00000000 7FC00000 00000000 +r 11E0.10 +*Want "MEEBR/MEEB NF +0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 11F0.10 +*Want "MEEBR/MEEB NF +0/+SNaN" 7FCA0000 00000000 7FCA0000 00000000 +r 1200.10 +*Want "MEEBR/MEEB NF +2.0/-inf" FF800000 FF800000 FF800000 FF800000 +r 1210.10 +*Want "MEEBR/MEEB NF +2.0/-2.0" C0800000 C0800000 C0800000 C0800000 +r 1220.10 +*Want "MEEBR/MEEB NF +2.0/-0" 80000000 80000000 80000000 80000000 +r 1230.10 +*Want "MEEBR/MEEB NF +2.0/+0" 00000000 00000000 00000000 00000000 +r 1240.10 +*Want "MEEBR/MEEB NF +2.0/+2.0" 40800000 40800000 40800000 40800000 +r 1250.10 +*Want "MEEBR/MEEB NF +2.0/+inf" 7F800000 7F800000 7F800000 7F800000 +r 1260.10 +*Want "MEEBR/MEEB NF +2.0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1270.10 +*Want "MEEBR/MEEB NF +2.0/+SNaN" 7FCA0000 40000000 7FCA0000 40000000 +r 1280.10 +*Want "MEEBR/MEEB NF +inf/-inf" FF800000 FF800000 FF800000 FF800000 +r 1290.10 +*Want "MEEBR/MEEB NF +inf/-2.0" FF800000 FF800000 FF800000 FF800000 +r 12A0.10 +*Want "MEEBR/MEEB NF +inf/-0" 7FC00000 7F800000 7FC00000 7F800000 +r 12B0.10 +*Want "MEEBR/MEEB NF +inf/+0" 7FC00000 7F800000 7FC00000 7F800000 +r 12C0.10 +*Want "MEEBR/MEEB NF +inf/+2.0" 7F800000 7F800000 7F800000 7F800000 +r 12D0.10 +*Want "MEEBR/MEEB NF +inf/+inf" 7F800000 7F800000 7F800000 7F800000 +r 12E0.10 +*Want "MEEBR/MEEB NF +inf/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 12F0.10 +*Want "MEEBR/MEEB NF +inf/+SNaN" 7FCA0000 7F800000 7FCA0000 7F800000 +r 1300.10 +*Want "MEEBR/MEEB NF -QNaN/-inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1310.10 +*Want "MEEBR/MEEB NF -QNaN/-2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1320.10 +*Want "MEEBR/MEEB NF -QNaN/-0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1330.10 +*Want "MEEBR/MEEB NF -QNaN/+0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1340.10 +*Want "MEEBR/MEEB NF -QNaN/+2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1350.10 +*Want "MEEBR/MEEB NF -QNaN/+inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1360.10 +*Want "MEEBR/MEEB NF -QNaN/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1370.10 +*Want "MEEBR/MEEB NF -QNaN/+SNaN" 7FCA0000 FFCB0000 7FCA0000 FFCB0000 +r 1380.10 +*Want "MEEBR/MEEB NF +SNaN/-inf" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1390.10 +*Want "MEEBR/MEEB NF +SNaN/-2.0" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 13A0.10 +*Want "MEEBR/MEEB NF +SNaN/-0" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 13B0.10 +*Want "MEEBR/MEEB NF +SNaN/+0" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 13C0.10 +*Want "MEEBR/MEEB NF +SNaN/+2.0" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 13D0.10 +*Want "MEEBR/MEEB NF +SNaN/+inf" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 13E0.10 +*Want "MEEBR/MEEB NF +SNaN/-QNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 13F0.10 +*Want "MEEBR/MEEB NF +SNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 + + +# Short BFP non-finite test results - FPCR contents +*Compare +r 1400.10 +*Want "MEEBR/MEEB NF -inf/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 1410.10 +*Want "MEEBR/MEEB NF -inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1420.10 +*Want "MEEBR/MEEB NF -inf/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 1430.10 +*Want "MEEBR/MEEB NF -inf/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 1440.10 +*Want "MEEBR/MEEB NF -inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1450.10 +*Want "MEEBR/MEEB NF -inf/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 1460.10 +*Want "MEEBR/MEEB NF -inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 1470.10 +*Want "MEEBR/MEEB NF -inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 1480.10 +*Want "MEEBR/MEEB NF -2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 1490.10 +*Want "MEEBR/MEEB NF -2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 14A0.10 +*Want "MEEBR/MEEB NF -2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 14B0.10 +*Want "MEEBR/MEEB NF -2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 14C0.10 +*Want "MEEBR/MEEB NF -2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 14D0.10 +*Want "MEEBR/MEEB NF -2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 14E0.10 +*Want "MEEBR/MEEB NF -2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 14F0.10 +*Want "MEEBR/MEEB NF -2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 1500.10 +*Want "MEEBR/MEEB NF -0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 1510.10 +*Want "MEEBR/MEEB NF -0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1520.10 +*Want "MEEBR/MEEB NF -0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1530.10 +*Want "MEEBR/MEEB NF -0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1540.10 +*Want "MEEBR/MEEB NF -0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1550.10 +*Want "MEEBR/MEEB NF -0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 1560.10 +*Want "MEEBR/MEEB NF -0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 1570.10 +*Want "MEEBR/MEEB NF -0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 1580.10 +*Want "MEEBR/MEEB NF +0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 1590.10 +*Want "MEEBR/MEEB NF +0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 15A0.10 +*Want "MEEBR/MEEB NF +0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 15B0.10 +*Want "MEEBR/MEEB NF +0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 15C0.10 +*Want "MEEBR/MEEB NF +0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 15D0.10 +*Want "MEEBR/MEEB NF +0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 15E0.10 +*Want "MEEBR/MEEB NF +0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 15F0.10 +*Want "MEEBR/MEEB NF +0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 1600.10 +*Want "MEEBR/MEEB NF +2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 1610.10 +*Want "MEEBR/MEEB NF +2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1620.10 +*Want "MEEBR/MEEB NF +2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1630.10 +*Want "MEEBR/MEEB NF +2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1640.10 +*Want "MEEBR/MEEB NF +2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1650.10 +*Want "MEEBR/MEEB NF +2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 1660.10 +*Want "MEEBR/MEEB NF +2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 1670.10 +*Want "MEEBR/MEEB NF +2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 1680.10 +*Want "MEEBR/MEEB NF +inf/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 1690.10 +*Want "MEEBR/MEEB NF +inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 16A0.10 +*Want "MEEBR/MEEB NF +inf/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 16B0.10 +*Want "MEEBR/MEEB NF +inf/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 16C0.10 +*Want "MEEBR/MEEB NF +inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 16D0.10 +*Want "MEEBR/MEEB NF +inf/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 16E0.10 +*Want "MEEBR/MEEB NF +inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 16F0.10 +*Want "MEEBR/MEEB NF +inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 1700.10 +*Want "MEEBR/MEEB NF -QNaN/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 1710.10 +*Want "MEEBR/MEEB NF -QNaN/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1720.10 +*Want "MEEBR/MEEB NF -QNaN/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1730.10 +*Want "MEEBR/MEEB NF -QNaN/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1740.10 +*Want "MEEBR/MEEB NF -QNaN/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1750.10 +*Want "MEEBR/MEEB NF -QNaN/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 1760.10 +*Want "MEEBR/MEEB NF -QNaN/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 1770.10 +*Want "MEEBR/MEEB NF -QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 1780.10 +*Want "MEEBR/MEEB NF +SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 1790.10 +*Want "MEEBR/MEEB NF +SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 17A0.10 +*Want "MEEBR/MEEB NF +SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 17B0.10 +*Want "MEEBR/MEEB NF +SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 17C0.10 +*Want "MEEBR/MEEB NF +SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 17D0.10 +*Want "MEEBR/MEEB NF +SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 17E0.10 +*Want "MEEBR/MEEB NF +SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 17F0.10 +*Want "MEEBR/MEEB NF +SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 + + +# Short BFP finite test results +*Compare +r 1800.10 +*Want "MEEBR/MEEB F Ovfl" FF800000 DF7FFFFE FF800000 DF7FFFFE +r 1810.10 +*Want "MEEBR/MEEB F Ufl 1" 00000000 21FFFFFF 00000000 21FFFFFF +r 1820.10 +*Want "MEEBR/MEEB F Ufl 2" 00000000 1970F000 00000000 1970F000 +r 1830.10 +*Want "MEEBR/MEEB F Nmin" 00FFFFFE 00FFFFFE 00FFFFFE 00FFFFFE +r 1840.10 +*Want "MEEBR/MEEB F Incr" 3F88000D 3F88000D 3F88000D 3F88000D +r 1850.10 +*Want "MEEBR/MEEB F Trun" 3F880007 3F880007 3F880007 3F880007 + + +# Short BFP finite test results - FPCR contents +*Compare +r 1900.10 +*Want "MEEBR/MEEB F Ovfl FPCR" 00280000 F8002800 00280000 F8002800 +r 1910.10 +*Want "MEEBR/MEEB F Ufl 1 FPCR" 00180000 F8001000 00180000 F8001000 +r 1920.10 +*Want "MEEBR/MEEB F Ufl 2 FPCR" 00180000 F8001000 00180000 F8001000 +r 1930.10 +*Want "MEEBR/MEEB F Nmin FPCR" 00000000 F8000000 00000000 F8000000 +r 1940.10 +*Want "MEEBR/MEEB F Incr FPCR" 00080000 F8000C00 00080000 F8000C00 +r 1950.10 +*Want "MEEBR/MEEB F Trun FPCR" 00080000 F8000800 00080000 F8000800 + + +# Short BFP rounding mode test results +*Compare +r 1A00.10 +*Want "MEEBR/MEEB RM +NZ RNTE, RZ" 3F880007 3F880007 3F880007 3F880007 +r 1A10.10 +*Want "MEEBR/MEEB RM +NZ RP, RM" 3F880008 3F880008 3F880007 3F880007 +r 1A20.8 +*Want "MEEBR/MEEB RM +NZ RFS" 3F880007 3F880007 +r 1A30.10 +*Want "MEEBR/MEEB RM -NZ RNTE, RZ" BF880007 BF880007 BF880007 BF880007 +r 1A40.10 +*Want "MEEBR/MEEB RM -NZ RP, RM" BF880007 BF880007 BF880008 BF880008 +r 1A50.8 +*Want "MEEBR/MEEB RM -NZ RFS" BF880007 BF880007 +r 1A60.10 +*Want "MEEBR/MEEB RM +NA RNTE, RZ" 3F88000D 3F88000D 3F88000C 3F88000C +r 1A70.10 +*Want "MEEBR/MEEB RM +NA RP, RM" 3F88000D 3F88000D 3F88000C 3F88000C +r 1A80.8 +*Want "MEEBR/MEEB RM +NA RFS" 3F88000D 3F88000D +r 1A90.10 +*Want "MEEBR/MEEB RM -NA RNTE, RZ" BF88000D BF88000D BF88000C BF88000C +r 1AA0.10 +*Want "MEEBR/MEEB RM -NA RP, RM" BF88000C BF88000C BF88000D BF88000D +r 1AB0.8 +*Want "MEEBR/MEEB RM -NA RFS" BF88000D BF88000D +r 1AC0.10 +*Want "MEEBR/MEEB RM +TZ RNTE, RZ" 3F880008 3F880008 3F880008 3F880008 +r 1AD0.10 +*Want "MEEBR/MEEB RM +TZ RP, RM" 3F880009 3F880009 3F880008 3F880008 +r 1AE0.8 +*Want "MEEBR/MEEB RM +TZ RFS" 3F880009 3F880009 +r 1AF0.10 +*Want "MEEBR/MEEB RM -TZ RNTE, RZ" BF880008 BF880008 BF880008 BF880008 +r 1B00.10 +*Want "MEEBR/MEEB RM -TZ RP, RM" BF880008 BF880008 BF880009 BF880009 +r 1B10.8 +*Want "MEEBR/MEEB RM -TZ RFS" BF880009 BF880009 +r 1B20.10 +*Want "MEEBR/MEEB RM +TA RNTE, RZ" 3F88001A 3F88001A 3F880019 3F880019 +r 1B30.10 +*Want "MEEBR/MEEB RM +TA RP, RM" 3F88001A 3F88001A 3F880019 3F880019 +r 1B40.8 +*Want "MEEBR/MEEB RM +TA RFS" 3F880019 3F880019 +r 1B50.10 +*Want "MEEBR/MEEB RM -TA RNTE, RZ" BF88001A BF88001A BF880019 BF880019 +r 1B60.10 +*Want "MEEBR/MEEB RM -TA RP, RM" BF880019 BF880019 BF88001A BF88001A +r 1B70.8 +*Want "MEEBR/MEEB RM -TA RFS" BF880019 BF880019 + + +# Short BFP rounding mode test results - FPCR contents +*Compare +r 1D00.10 +*Want "MEEBR/MEEB RM +NZ RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r 1D10.10 +*Want "MEEBR/MEEB RM +NZ RP, RM FPCR" 00080002 00080002 00080003 00080003 +r 1D20.8 +*Want "MEEBR/MEEB RM +NZ RFS FPCR" 00080007 00080007 +r 1D30.10 +*Want "MEEBR/MEEB RM -NZ RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r 1D40.10 +*Want "MEEBR/MEEB RM -NZ RP, RM FPCR" 00080002 00080002 00080003 00080003 +r 1D50.8 +*Want "MEEBR/MEEB RM -NZ RFS FPCR" 00080007 00080007 +r 1D60.10 +*Want "MEEBR/MEEB RM +NA RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r 1D70.10 +*Want "MEEBR/MEEB RM +NA RP, RM FPCR" 00080002 00080002 00080003 00080003 +r 1D80.8 +*Want "MEEBR/MEEB RM +NA RFS FPCR" 00080007 00080007 +r 1D90.10 +*Want "MEEBR/MEEB RM -NA RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r 1DA0.10 +*Want "MEEBR/MEEB RM -NA RP, RM FPCR" 00080002 00080002 00080003 00080003 +r 1DB0.8 +*Want "MEEBR/MEEB RM -NA RFS FPCR" 00080007 00080007 +r 1DC0.10 +*Want "MEEBR/MEEB RM +TZ RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r 1DD0.10 +*Want "MEEBR/MEEB RM +TZ RP, RM FPCR" 00080002 00080002 00080003 00080003 +r 1DE0.8 +*Want "MEEBR/MEEB RM +TZ RFS FPCR" 00080007 00080007 +r 1DF0.10 +*Want "MEEBR/MEEB RM -TZ RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r 1E00.10 +*Want "MEEBR/MEEB RM -TZ RP, RM FPCR" 00080002 00080002 00080003 00080003 +r 1E10.8 +*Want "MEEBR/MEEB RM -TZ RFS FPCR" 00080007 00080007 +r 1E20.10 +*Want "MEEBR/MEEB RM +TA RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r 1E30.10 +*Want "MEEBR/MEEB RM +TA RP, RM FPCR" 00080002 00080002 00080003 00080003 +r 1E40.8 +*Want "MEEBR/MEEB RM +TA RFS FPCR" 00080007 00080007 +r 1E50.10 +*Want "MEEBR/MEEB RM -TA RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r 1E60.10 +*Want "MEEBR/MEEB RM -TA RP, RM FPCR" 00080002 00080002 00080003 00080003 +r 1E70.8 +*Want "MEEBR/MEEB RM -TA RFS FPCR" 00080007 00080007 + + +# Long BFP non-finite test results +*Compare +r 3000.10 +*Want "MDBR/MDB NF -inf/-inf NT" 7FF00000 00000000 7FF00000 00000000 +r 3010.10 +*Want "MDBR/MDB NF -inf/-inf Tr" 7FF00000 00000000 7FF00000 00000000 +r 3020.10 +*Want "MDBR/MDB NF -inf/-2.0 NT" 7FF00000 00000000 7FF00000 00000000 +r 3030.10 +*Want "MDBR/MDB NF -inf/-2.0 Tr" 7FF00000 00000000 7FF00000 00000000 +r 3040.10 +*Want "MDBR/MDB NF -inf/-0 NT" 7FF80000 00000000 FFF00000 00000000 +r 3050.10 +*Want "MDBR/MDB NF -inf/-0 Tr" 7FF80000 00000000 FFF00000 00000000 +r 3060.10 +*Want "MDBR/MDB NF -inf/+0 NT" 7FF80000 00000000 FFF00000 00000000 +r 3070.10 +*Want "MDBR/MDB NF -inf/+0 Tr" 7FF80000 00000000 FFF00000 00000000 +r 3080.10 +*Want "MDBR/MDB NF -inf/+2.0 NT" FFF00000 00000000 FFF00000 00000000 +r 3090.10 +*Want "MDBR/MDB NF -inf/+2.0 Tr" FFF00000 00000000 FFF00000 00000000 +r 30A0.10 +*Want "MDBR/MDB NF -inf/+inf NT" FFF00000 00000000 FFF00000 00000000 +r 30B0.10 +*Want "MDBR/MDB NF -inf/+inf Tr" FFF00000 00000000 FFF00000 00000000 +r 30C0.10 +*Want "MDBR/MDB NF -inf/-QNaN NT" FFF8B000 00000000 FFF8B000 00000000 +r 30D0.10 +*Want "MDBR/MDB NF -inf/-QNaN Tr" FFF8B000 00000000 FFF8B000 00000000 +r 30E0.10 +*Want "MDBR/MDB NF -inf/+SNaN NT" 7FF8A000 00000000 FFF00000 00000000 +r 30F0.10 +*Want "MDBR/MDB NF -inf/+SNaN Tr" 7FF8A000 00000000 FFF00000 00000000 +r 3100.10 +*Want "MDBR/MDB NF -2.0/-inf NT" 7FF00000 00000000 7FF00000 00000000 +r 3110.10 +*Want "MDBR/MDB NF -2.0/-inf Tr" 7FF00000 00000000 7FF00000 00000000 +r 3120.10 +*Want "MDBR/MDB NF -2.0/-2.0 NT" 40100000 00000000 40100000 00000000 +r 3130.10 +*Want "MDBR/MDB NF -2.0/-2.0 Tr" 40100000 00000000 40100000 00000000 +r 3140.10 +*Want "MDBR/MDB NF -2.0/-0 NT" 00000000 00000000 00000000 00000000 +r 3150.10 +*Want "MDBR/MDB NF -2.0/-0 Tr" 00000000 00000000 00000000 00000000 +r 3160.10 +*Want "MDBR/MDB NF -2.0/+0 NT" 80000000 00000000 80000000 00000000 +r 3170.10 +*Want "MDBR/MDB NF -2.0/+0 Tr" 80000000 00000000 80000000 00000000 +r 3180.10 +*Want "MDBR/MDB NF -2.0/+2.0 NT" C0100000 00000000 C0100000 00000000 +r 3190.10 +*Want "MDBR/MDB NF -2.0/+2.0 Tr" C0100000 00000000 C0100000 00000000 +r 31A0.10 +*Want "MDBR/MDB NF -2.0/+inf NT" FFF00000 00000000 FFF00000 00000000 +r 31B0.10 +*Want "MDBR/MDB NF -2.0/+inf Tr" FFF00000 00000000 FFF00000 00000000 +r 31C0.10 +*Want "MDBR/MDB NF -2.0/-QNaN NT" FFF8B000 00000000 FFF8B000 00000000 +r 31D0.10 +*Want "MDBR/MDB NF -2.0/-QNaN Tr" FFF8B000 00000000 FFF8B000 00000000 +r 31E0.10 +*Want "MDBR/MDB NF -2.0/+SNaN NT" 7FF8A000 00000000 C0000000 00000000 +r 31F0.10 +*Want "MDBR/MDB NF -2.0/+SNaN Tr" 7FF8A000 00000000 C0000000 00000000 +r 3200.10 +*Want "MDBR/MDB NF -0/-inf NT" 7FF80000 00000000 80000000 00000000 +r 3210.10 +*Want "MDBR/MDB NF -0/-inf Tr" 7FF80000 00000000 80000000 00000000 +r 3220.10 +*Want "MDBR/MDB NF -0/-2.0 NT" 00000000 00000000 00000000 00000000 +r 3230.10 +*Want "MDBR/MDB NF -0/-2.0 Tr" 00000000 00000000 00000000 00000000 +r 3240.10 +*Want "MDBR/MDB NF -0/-0 NT" 00000000 00000000 00000000 00000000 +r 3250.10 +*Want "MDBR/MDB NF -0/-0 Tr" 00000000 00000000 00000000 00000000 +r 3260.10 +*Want "MDBR/MDB NF -0/+0 NT" 80000000 00000000 80000000 00000000 +r 3270.10 +*Want "MDBR/MDB NF -0/+0 Tr" 80000000 00000000 80000000 00000000 +r 3280.10 +*Want "MDBR/MDB NF -0/+2.0 NT" 80000000 00000000 80000000 00000000 +r 3290.10 +*Want "MDBR/MDB NF -0/+2.0 Tr" 80000000 00000000 80000000 00000000 +r 32A0.10 +*Want "MDBR/MDB NF -0/+inf NT" 7FF80000 00000000 80000000 00000000 +r 32B0.10 +*Want "MDBR/MDB NF -0/+inf Tr" 7FF80000 00000000 80000000 00000000 +r 32C0.10 +*Want "MDBR/MDB NF -0/-QNaN NT" FFF8B000 00000000 FFF8B000 00000000 +r 32D0.10 +*Want "MDBR/MDB NF -0/-QNaN Tr" FFF8B000 00000000 FFF8B000 00000000 +r 32E0.10 +*Want "MDBR/MDB NF -0/+SNaN NT" 7FF8A000 00000000 80000000 00000000 +r 32F0.10 +*Want "MDBR/MDB NF -0/+SNaN Tr" 7FF8A000 00000000 80000000 00000000 +r 3300.10 +*Want "MDBR/MDB NF +0/-inf NT" 7FF80000 00000000 00000000 00000000 +r 3310.10 +*Want "MDBR/MDB NF +0/-inf Tr" 7FF80000 00000000 00000000 00000000 +r 3320.10 +*Want "MDBR/MDB NF +0/-2.0 NT" 80000000 00000000 80000000 00000000 +r 3330.10 +*Want "MDBR/MDB NF +0/-2.0 Tr" 80000000 00000000 80000000 00000000 +r 3340.10 +*Want "MDBR/MDB NF +0/-0 NT" 80000000 00000000 80000000 00000000 +r 3350.10 +*Want "MDBR/MDB NF +0/-0 Tr" 80000000 00000000 80000000 00000000 +r 3360.10 +*Want "MDBR/MDB NF +0/+0 NT" 00000000 00000000 00000000 00000000 +r 3370.10 +*Want "MDBR/MDB NF +0/+0 Tr" 00000000 00000000 00000000 00000000 +r 3380.10 +*Want "MDBR/MDB NF +0/+2.0 NT" 00000000 00000000 00000000 00000000 +r 3390.10 +*Want "MDBR/MDB NF +0/+2.0 Tr" 00000000 00000000 00000000 00000000 +r 33A0.10 +*Want "MDBR/MDB NF +0/+inf NT" 7FF80000 00000000 00000000 00000000 +r 33B0.10 +*Want "MDBR/MDB NF +0/+inf Tr" 7FF80000 00000000 00000000 00000000 +r 33C0.10 +*Want "MDBR/MDB NF +0/-QNaN NT" FFF8B000 00000000 FFF8B000 00000000 +r 33D0.10 +*Want "MDBR/MDB NF +0/-QNaN Tr" FFF8B000 00000000 FFF8B000 00000000 +r 33E0.10 +*Want "MDBR/MDB NF +0/+SNaN NT" 7FF8A000 00000000 00000000 00000000 +r 33F0.10 +*Want "MDBR/MDB NF +0/+SNaN Tr" 7FF8A000 00000000 00000000 00000000 +r 3400.10 +*Want "MDBR/MDB NF +2.0/-inf NT" FFF00000 00000000 FFF00000 00000000 +r 3410.10 +*Want "MDBR/MDB NF +2.0/-inf Tr" FFF00000 00000000 FFF00000 00000000 +r 3420.10 +*Want "MDBR/MDB NF +2.0/-2.0 NT" C0100000 00000000 C0100000 00000000 +r 3430.10 +*Want "MDBR/MDB NF +2.0/-2.0 Tr" C0100000 00000000 C0100000 00000000 +r 3440.10 +*Want "MDBR/MDB NF +2.0/-0 NT" 80000000 00000000 80000000 00000000 +r 3450.10 +*Want "MDBR/MDB NF +2.0/-0 Tr" 80000000 00000000 80000000 00000000 +r 3460.10 +*Want "MDBR/MDB NF +2.0/+0 NT" 00000000 00000000 00000000 00000000 +r 3470.10 +*Want "MDBR/MDB NF +2.0/+0 Tr" 00000000 00000000 00000000 00000000 +r 3480.10 +*Want "MDBR/MDB NF +2.0/+2.0 NT" 40100000 00000000 40100000 00000000 +r 3490.10 +*Want "MDBR/MDB NF +2.0/+2.0 Tr" 40100000 00000000 40100000 00000000 +r 34A0.10 +*Want "MDBR/MDB NF +2.0/+inf NT" 7FF00000 00000000 7FF00000 00000000 +r 34B0.10 +*Want "MDBR/MDB NF +2.0/+inf Tr" 7FF00000 00000000 7FF00000 00000000 +r 34C0.10 +*Want "MDBR/MDB NF +2.0/-QNaN NT" FFF8B000 00000000 FFF8B000 00000000 +r 34D0.10 +*Want "MDBR/MDB NF +2.0/-QNaN Tr" FFF8B000 00000000 FFF8B000 00000000 +r 34E0.10 +*Want "MDBR/MDB NF +2.0/+SNaN NT" 7FF8A000 00000000 40000000 00000000 +r 34F0.10 +*Want "MDBR/MDB NF +2.0/+SNaN Tr" 7FF8A000 00000000 40000000 00000000 +r 3500.10 +*Want "MDBR/MDB NF +inf/-inf NT" FFF00000 00000000 FFF00000 00000000 +r 3510.10 +*Want "MDBR/MDB NF +inf/-inf Tr" FFF00000 00000000 FFF00000 00000000 +r 3520.10 +*Want "MDBR/MDB NF +inf/-2.0 NT" FFF00000 00000000 FFF00000 00000000 +r 3530.10 +*Want "MDBR/MDB NF +inf/-2.0 Tr" FFF00000 00000000 FFF00000 00000000 +r 3540.10 +*Want "MDBR/MDB NF +inf/-0 NT" 7FF80000 00000000 7FF00000 00000000 +r 3550.10 +*Want "MDBR/MDB NF +inf/-0 Tr" 7FF80000 00000000 7FF00000 00000000 +r 3560.10 +*Want "MDBR/MDB NF +inf/+0 NT" 7FF80000 00000000 7FF00000 00000000 +r 3570.10 +*Want "MDBR/MDB NF +inf/+0 Tr" 7FF80000 00000000 7FF00000 00000000 +r 3580.10 +*Want "MDBR/MDB NF +inf/+2.0 NT" 7FF00000 00000000 7FF00000 00000000 +r 3590.10 +*Want "MDBR/MDB NF +inf/+2.0 Tr" 7FF00000 00000000 7FF00000 00000000 +r 35A0.10 +*Want "MDBR/MDB NF +inf/+inf NT" 7FF00000 00000000 7FF00000 00000000 +r 35B0.10 +*Want "MDBR/MDB NF +inf/+inf Tr" 7FF00000 00000000 7FF00000 00000000 +r 35C0.10 +*Want "MDBR/MDB NF +inf/-QNaN NT" FFF8B000 00000000 FFF8B000 00000000 +r 35D0.10 +*Want "MDBR/MDB NF +inf/-QNaN Tr" FFF8B000 00000000 FFF8B000 00000000 +r 35E0.10 +*Want "MDBR/MDB NF +inf/+SNaN NT" 7FF8A000 00000000 7FF00000 00000000 +r 35F0.10 +*Want "MDBR/MDB NF +inf/+SNaN Tr" 7FF8A000 00000000 7FF00000 00000000 +r 3600.10 +*Want "MDBR/MDB NF -QNaN/-inf NT" FFF8B000 00000000 FFF8B000 00000000 +r 3610.10 +*Want "MDBR/MDB NF -QNaN/-inf Tr" FFF8B000 00000000 FFF8B000 00000000 +r 3620.10 +*Want "MDBR/MDB NF -QNaN/-2.0 NT" FFF8B000 00000000 FFF8B000 00000000 +r 3630.10 +*Want "MDBR/MDB NF -QNaN/-2.0 Tr" FFF8B000 00000000 FFF8B000 00000000 +r 3640.10 +*Want "MDBR/MDB NF -QNaN/-0 NT" FFF8B000 00000000 FFF8B000 00000000 +r 3650.10 +*Want "MDBR/MDB NF -QNaN/-0 Tr" FFF8B000 00000000 FFF8B000 00000000 +r 3660.10 +*Want "MDBR/MDB NF -QNaN/+0 NT" FFF8B000 00000000 FFF8B000 00000000 +r 3670.10 +*Want "MDBR/MDB NF -QNaN/+0 Tr" FFF8B000 00000000 FFF8B000 00000000 +r 3680.10 +*Want "MDBR/MDB NF -QNaN/+2.0 NT" FFF8B000 00000000 FFF8B000 00000000 +r 3690.10 +*Want "MDBR/MDB NF -QNaN/+2.0 Tr" FFF8B000 00000000 FFF8B000 00000000 +r 36A0.10 +*Want "MDBR/MDB NF -QNaN/+inf NT" FFF8B000 00000000 FFF8B000 00000000 +r 36B0.10 +*Want "MDBR/MDB NF -QNaN/+inf Tr" FFF8B000 00000000 FFF8B000 00000000 +r 36C0.10 +*Want "MDBR/MDB NF -QNaN/-QNaN NT" FFF8B000 00000000 FFF8B000 00000000 +r 36D0.10 +*Want "MDBR/MDB NF -QNaN/-QNaN Tr" FFF8B000 00000000 FFF8B000 00000000 +r 36E0.10 +*Want "MDBR/MDB NF -QNaN/+SNaN NT" 7FF8A000 00000000 FFF8B000 00000000 +r 36F0.10 +*Want "MDBR/MDB NF -QNaN/+SNaN Tr" 7FF8A000 00000000 FFF8B000 00000000 +r 3700.10 +*Want "MDBR/MDB NF +SNaN/-inf NT" 7FF8A000 00000000 7FF0A000 00000000 +r 3710.10 +*Want "MDBR/MDB NF +SNaN/-inf Tr" 7FF8A000 00000000 7FF0A000 00000000 +r 3720.10 +*Want "MDBR/MDB NF +SNaN/-2.0 NT" 7FF8A000 00000000 7FF0A000 00000000 +r 3730.10 +*Want "MDBR/MDB NF +SNaN/-2.0 Tr" 7FF8A000 00000000 7FF0A000 00000000 +r 3740.10 +*Want "MDBR/MDB NF +SNaN/-0 NT" 7FF8A000 00000000 7FF0A000 00000000 +r 3750.10 +*Want "MDBR/MDB NF +SNaN/-0 Tr" 7FF8A000 00000000 7FF0A000 00000000 +r 3760.10 +*Want "MDBR/MDB NF +SNaN/+0 NT" 7FF8A000 00000000 7FF0A000 00000000 +r 3770.10 +*Want "MDBR/MDB NF +SNaN/+0 Tr" 7FF8A000 00000000 7FF0A000 00000000 +r 3780.10 +*Want "MDBR/MDB NF +SNaN/+2.0 NT" 7FF8A000 00000000 7FF0A000 00000000 +r 3790.10 +*Want "MDBR/MDB NF +SNaN/+2.0 Tr" 7FF8A000 00000000 7FF0A000 00000000 +r 37A0.10 +*Want "MDBR/MDB NF +SNaN/+inf NT" 7FF8A000 00000000 7FF0A000 00000000 +r 37B0.10 +*Want "MDBR/MDB NF +SNaN/+inf Tr" 7FF8A000 00000000 7FF0A000 00000000 +r 37C0.10 +*Want "MDBR/MDB NF +SNaN/-QNaN NT" 7FF8A000 00000000 7FF0A000 00000000 +r 37D0.10 +*Want "MDBR/MDB NF +SNaN/-QNaN Tr" 7FF8A000 00000000 7FF0A000 00000000 +r 37E0.10 +*Want "MDBR/MDB NF +SNaN/+SNaN NT" 7FF8A000 00000000 7FF0A000 00000000 +r 37F0.10 +*Want "MDBR/MDB NF +SNaN/+SNaN Tr" 7FF8A000 00000000 7FF0A000 00000000 + + +# Long BFP non-finite test results - FPCR contents +*Compare +r 3800.10 +*Want "MDBR NF -inf/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3810.10 +*Want "MDB NF -inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3820.10 +*Want "MDBR NF -inf/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3830.10 +*Want "MDB NF -inf/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3840.10 +*Want "MDBR NF -inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3850.10 +*Want "MDB NF -inf/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3860.10 +*Want "MDBR NF -inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3870.10 +*Want "MDB NF -inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3880.10 +*Want "MDBR NF -2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3890.10 +*Want "MDB NF -2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 38A0.10 +*Want "MDBR NF -2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 38B0.10 +*Want "MDB NF -2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 38C0.10 +*Want "MDBR NF -2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 38D0.10 +*Want "MDB NF -2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 38E0.10 +*Want "MDBR NF -2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 38F0.10 +*Want "MDB NF -2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3900.10 +*Want "MDBR NF -0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3910.10 +*Want "MDB NF -0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3920.10 +*Want "MDBR NF -0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3930.10 +*Want "MDB NF -0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3940.10 +*Want "MDBR NF -0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3950.10 +*Want "MDB NF -0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3960.10 +*Want "MDBR NF -0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3970.10 +*Want "MDB NF -0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3980.10 +*Want "MDBR NF +0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3990.10 +*Want "MDB NF +0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 39A0.10 +*Want "MDBR NF +0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 39B0.10 +*Want "MDB NF +0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 39C0.10 +*Want "MDBR NF +0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 39D0.10 +*Want "MDB NF +0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 39E0.10 +*Want "MDBR NF +0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 39F0.10 +*Want "MDB NF +0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3A00.10 +*Want "MDBR NF +2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3A10.10 +*Want "MDB NF +2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3A20.10 +*Want "MDBR NF +2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3A30.10 +*Want "MDB NF +2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3A40.10 +*Want "MDBR NF +2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3A50.10 +*Want "MDB NF +2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3A60.10 +*Want "MDBR NF +2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3A70.10 +*Want "MDB NF +2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3A80.10 +*Want "MDBR NF +inf/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3A90.10 +*Want "MDB NF +inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3AA0.10 +*Want "MDBR NF +inf/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3AB0.10 +*Want "MDB NF +inf/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3AC0.10 +*Want "MDBR NF +inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3AD0.10 +*Want "MDB NF +inf/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3AE0.10 +*Want "MDBR NF +inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3AF0.10 +*Want "MDB NF +inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3B00.10 +*Want "MDBR NF -QNaN/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3B10.10 +*Want "MDB NF -QNaN/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3B20.10 +*Want "MDBR NF -QNaN/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3B30.10 +*Want "MDB NF -QNaN/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3B40.10 +*Want "MDBR NF -QNaN/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3B50.10 +*Want "MDB NF -QNaN/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3B60.10 +*Want "MDBR NF -QNaN/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3B70.10 +*Want "MDB NF -QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3B80.10 +*Want "MDBR NF +SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3B90.10 +*Want "MDB NF +SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3BA0.10 +*Want "MDBR NF +SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3BB0.10 +*Want "MDB NF +SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3BC0.10 +*Want "MDBR NF +SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3BD0.10 +*Want "MDB NF +SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3BE0.10 +*Want "MDBR NF +SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3BF0.10 +*Want "MDB NF +SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 + + +# Long BFP finite test results +*Compare +r 3C00.10 +*Want "MDBR F Ovfl NT" FFF00000 00000000 DFEFFFFF FFFFFFFE +r 3C10.10 +*Want "MDB F Ovfl Tr" FFF00000 00000000 DFEFFFFF FFFFFFFE +r 3C20.10 +*Want "MDBR F Ufl 1 NT" 00000000 00000000 203FFFFF FFFFFFFF +r 3C30.10 +*Want "MDB F Ufl 1 Tr" 00000000 00000000 203FFFFF FFFFFFFF +r 3C40.10 +*Want "MDBR F Ufl 2 NT" 00000000 00000000 1FDE1E00 00000000 +r 3C50.10 +*Want "MDB F Ufl 2 Tr" 00000000 00000000 1FDE1E00 00000000 +r 3C60.10 +*Want "MDBR F Nmin NT" 001FFFFF FFFFFFFE 001FFFFF FFFFFFFE +r 3C70.10 +*Want "MDB F Nmin Tr" 001FFFFF FFFFFFFE 001FFFFF FFFFFFFE +r 3C80.10 +*Want "MDBR F Incr NT" 3FF10000 0000000D 3FF10000 0000000D +r 3C90.10 +*Want "MDB F Incr Tr" 3FF10000 0000000D 3FF10000 0000000D +r 3CA0.10 +*Want "MDBR F Trun NT" 3FF10000 00000007 3FF10000 00000007 +r 3CB0.10 +*Want "MDB F Trun Tr" 3FF10000 00000007 3FF10000 00000007 + + +# Long BFP finite test results - FPCR contents +*Compare +r 3E00.10 +*Want "MDBR/MDB F Ovfl FPCR" 00280000 F8002800 00280000 F8002800 +r 3E10.10 +*Want "MDBR/MDB F Ufl 1 FPCR" 00180000 F8001000 00180000 F8001000 +r 3E20.10 +*Want "MDBR/MDB F Ufl 2 FPCR" 00180000 F8001000 00180000 F8001000 +r 3E30.10 +*Want "MDBR/MDB F Nmin FPCR" 00000000 F8000000 00000000 F8000000 +r 3E40.10 +*Want "MDBR/MDB F Incr FPCR" 00080000 F8000C00 00080000 F8000C00 +r 3E50.10 +*Want "MDBR/MDB F Trun FPCR" 00080000 F8000800 00080000 F8000800 + + +# Long BFP rounding mode test results +*Compare +r 4000.10 +*Want "MDBR RM +NZ RNTE" 3FF10000 00000007 3FF10000 00000007 +r 4010.10 +*Want "MDB RM +NZ RZ" 3FF10000 00000007 3FF10000 00000007 +r 4020.10 +*Want "MDBR RM +NZ RP" 3FF10000 00000008 3FF10000 00000008 +r 4030.10 +*Want "MDB RM +NZ RM" 3FF10000 00000007 3FF10000 00000007 +r 4040.10 +*Want "MDBR RM +NZ RFS" 3FF10000 00000007 3FF10000 00000007 +r 4050.10 +*Want "MDB RM -NZ RNTE" BFF10000 00000007 BFF10000 00000007 +r 4060.10 +*Want "MDBR RM -NZ RZ" BFF10000 00000007 BFF10000 00000007 +r 4070.10 +*Want "MDB RM -NZ RP" BFF10000 00000007 BFF10000 00000007 +r 4080.10 +*Want "MDBR RM -NZ RM" BFF10000 00000008 BFF10000 00000008 +r 4090.10 +*Want "MDB RM -NZ RFS" BFF10000 00000007 BFF10000 00000007 +r 40A0.10 +*Want "MDBR RM +NA RNTE" 3FF10000 0000000D 3FF10000 0000000D +r 40B0.10 +*Want "MDB RM +NA RZ" 3FF10000 0000000C 3FF10000 0000000C +r 40C0.10 +*Want "MDBR RM +NA RP" 3FF10000 0000000D 3FF10000 0000000D +r 40D0.10 +*Want "MDB RM +NA RM" 3FF10000 0000000C 3FF10000 0000000C +r 40E0.10 +*Want "MDBR RM +NA RFS" 3FF10000 0000000D 3FF10000 0000000D +r 40F0.10 +*Want "MDB RM -NA RNTE" BFF10000 0000000D BFF10000 0000000D +r 4100.10 +*Want "MDBR RM -NA RZ" BFF10000 0000000C BFF10000 0000000C +r 4110.10 +*Want "MDB RM -NA RP" BFF10000 0000000C BFF10000 0000000C +r 4120.10 +*Want "MDBR RM -NA RM" BFF10000 0000000D BFF10000 0000000D +r 4130.10 +*Want "MDB RM -NA RFS" BFF10000 0000000D BFF10000 0000000D +r 4140.10 +*Want "MDBR RM +TZ RNTE" 3FF10000 00000008 3FF10000 00000008 +r 4150.10 +*Want "MDB RM +TZ RZ" 3FF10000 00000008 3FF10000 00000008 +r 4160.10 +*Want "MDBR RM +TZ RP" 3FF10000 00000009 3FF10000 00000009 +r 4170.10 +*Want "MDB RM +TZ RM" 3FF10000 00000008 3FF10000 00000008 +r 4180.10 +*Want "MDBR RM +TZ RFS" 3FF10000 00000009 3FF10000 00000009 +r 4190.10 +*Want "MDB RM -TZ RNTE" BFF10000 00000008 BFF10000 00000008 +r 41A0.10 +*Want "MDBR RM -TZ RZ" BFF10000 00000008 BFF10000 00000008 +r 41B0.10 +*Want "MDB RM -TZ RP" BFF10000 00000008 BFF10000 00000008 +r 41C0.10 +*Want "MDBR RM -TZ RM" BFF10000 00000009 BFF10000 00000009 +r 41D0.10 +*Want "MDB RM -TZ RFS" BFF10000 00000009 BFF10000 00000009 +r 41E0.10 +*Want "MDBR RM +TA RNTE" 3FF10000 0000001A 3FF10000 0000001A +r 41F0.10 +*Want "MDB RM +TA RZ" 3FF10000 00000019 3FF10000 00000019 +r 4200.10 +*Want "MDBR RM +TA RP" 3FF10000 0000001A 3FF10000 0000001A +r 4210.10 +*Want "MDB RM +TA RM" 3FF10000 00000019 3FF10000 00000019 +r 4220.10 +*Want "MDBR RM +TA RFS" 3FF10000 00000019 3FF10000 00000019 +r 4230.10 +*Want "MDB RM -TA RNTE" BFF10000 0000001A BFF10000 0000001A +r 4240.10 +*Want "MDBR RM -TA RZ" BFF10000 00000019 BFF10000 00000019 +r 4250.10 +*Want "MDB RM -TA RP" BFF10000 00000019 BFF10000 00000019 +r 4260.10 +*Want "MDBR RM -TA RM" BFF10000 0000001A BFF10000 0000001A +r 4270.10 +*Want "MDB RM -TA RFS" BFF10000 00000019 BFF10000 00000019 + + +# Long BFP rounding mode test results - FPCR contents +*Compare +r 4500.10 +*Want "MDBR/MDB RM +NZ RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r 4510.10 +*Want "MDBR/MDB RM +NZ RP, RM FPCR" 00080002 00080002 00080003 00080003 +r 4520.8 +*Want "MDBR/MDB RM +NZ RFS FPCR" 00080007 00080007 +r 4530.10 +*Want "MDBR/MDB RM +NZ RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r 4540.10 +*Want "MDBR/MDB RM +NZ RP, RM FPCR" 00080002 00080002 00080003 00080003 +r 4550.8 +*Want "MDBR/MDB RM -NZ RFS FPCR" 00080007 00080007 +r 4560.10 +*Want "MDBR/MDB RM -NZ RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r 4570.10 +*Want "MDBR/MDB RM -NZ RP, RM FPCR" 00080002 00080002 00080003 00080003 +r 4580.8 +*Want "MDBR/MDB RM -NZ RFS FPCR" 00080007 00080007 +r 4590.10 +*Want "MDBR/MDB RM -NZ RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r 45A0.10 +*Want "MDBR/MDB RM -NA RP, RM FPCR" 00080002 00080002 00080003 00080003 +r 45B0.8 +*Want "MDBR/MDB RM -NA RFS FPCR" 00080007 00080007 +r 45C0.10 +*Want "MDBR/MDB RM +TZ RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r 45D0.10 +*Want "MDBR/MDB RM +TZ RP, RM FPCR" 00080002 00080002 00080003 00080003 +r 45E0.8 +*Want "MDBR/MDB RM +TZ RFS FPCR" 00080007 00080007 +r 45F0.10 +*Want "MDBR/MDB RM -TZ RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r 4600.10 +*Want "MDBR/MDB RM -TZ RP, RM FPCR" 00080002 00080002 00080003 00080003 +r 4610.8 +*Want "MDBR/MDB RM -TZ RFS FPCR" 00080007 00080007 +r 4620.10 +*Want "MDBR/MDB RM +TA RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r 4630.10 +*Want "MDBR/MDB RM +TA RP, RM FPCR" 00080002 00080002 00080003 00080003 +r 4640.8 +*Want "MDBR/MDB RM +TA RFS FPCR" 00080007 00080007 +r 4650.10 +*Want "MDBR/MDB RM -TA RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r 4660.10 +*Want "MDBR/MDB RM -TA RP, RM FPCR" 00080002 00080002 00080003 00080003 +r 4670.8 +*Want "MDBR/MDB RM -TA RFS FPCR" 00080007 00080007 + + +# Extended BFP non-finite test results +*Compare +r 5000.10 +*Want "MXBR NF -inf/-inf NT" 7FFF0000 00000000 00000000 00000000 +r 5010.10 +*Want "MXBR NF -inf/-inf Tr" 7FFF0000 00000000 00000000 00000000 +r 5020.10 +*Want "MXBR NF -inf/-2.0 NT" 7FFF0000 00000000 00000000 00000000 +r 5030.10 +*Want "MXBR NF -inf/-2.0 Tr" 7FFF0000 00000000 00000000 00000000 +r 5040.10 +*Want "MXBR NF -inf/-0 NT" 7FFF8000 00000000 00000000 00000000 +r 5050.10 +*Want "MXBR NF -inf/-0 Tr" FFFF0000 00000000 00000000 00000000 +r 5060.10 +*Want "MXBR NF -inf/+0 NT" 7FFF8000 00000000 00000000 00000000 +r 5070.10 +*Want "MXBR NF -inf/+0 Tr" FFFF0000 00000000 00000000 00000000 +r 5080.10 +*Want "MXBR NF -inf/+2.0 NT" FFFF0000 00000000 00000000 00000000 +r 5090.10 +*Want "MXBR NF -inf/+2.0 Tr" FFFF0000 00000000 00000000 00000000 +r 50A0.10 +*Want "MXBR NF -inf/+inf NT" FFFF0000 00000000 00000000 00000000 +r 50B0.10 +*Want "MXBR NF -inf/+inf Tr" FFFF0000 00000000 00000000 00000000 +r 50C0.10 +*Want "MXBR NF -inf/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 50D0.10 +*Want "MXBR NF -inf/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 50E0.10 +*Want "MXBR NF -inf/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 50F0.10 +*Want "MXBR NF -inf/+SNaN Tr" FFFF0000 00000000 00000000 00000000 +r 5100.10 +*Want "MXBR NF -2.0/-inf NT" 7FFF0000 00000000 00000000 00000000 +r 5110.10 +*Want "MXBR NF -2.0/-inf Tr" 7FFF0000 00000000 00000000 00000000 +r 5120.10 +*Want "MXBR NF -2.0/-2.0 NT" 40010000 00000000 00000000 00000000 +r 5130.10 +*Want "MXBR NF -2.0/-2.0 Tr" 40010000 00000000 00000000 00000000 +r 5140.10 +*Want "MXBR NF -2.0/-0 NT" 00000000 00000000 00000000 00000000 +r 5150.10 +*Want "MXBR NF -2.0/-0 Tr" 00000000 00000000 00000000 00000000 +r 5160.10 +*Want "MXBR NF -2.0/+0 NT" 80000000 00000000 00000000 00000000 +r 5170.10 +*Want "MXBR NF -2.0/+0 Tr" 80000000 00000000 00000000 00000000 +r 5180.10 +*Want "MXBR NF -2.0/+2.0 NT" C0010000 00000000 00000000 00000000 +r 5190.10 +*Want "MXBR NF -2.0/+2.0 Tr" C0010000 00000000 00000000 00000000 +r 51A0.10 +*Want "MXBR NF -2.0/+inf NT" FFFF0000 00000000 00000000 00000000 +r 51B0.10 +*Want "MXBR NF -2.0/+inf Tr" FFFF0000 00000000 00000000 00000000 +r 51C0.10 +*Want "MXBR NF -2.0/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 51D0.10 +*Want "MXBR NF -2.0/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 51E0.10 +*Want "MXBR NF -2.0/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 51F0.10 +*Want "MXBR NF -2.0/+SNaN Tr" C0000000 00000000 00000000 00000000 +r 5200.10 +*Want "MXBR NF -0/-inf NT" 7FFF8000 00000000 00000000 00000000 +r 5210.10 +*Want "MXBR NF -0/-inf Tr" 80000000 00000000 00000000 00000000 +r 5220.10 +*Want "MXBR NF -0/-2.0 NT" 00000000 00000000 00000000 00000000 +r 5230.10 +*Want "MXBR NF -0/-2.0 Tr" 00000000 00000000 00000000 00000000 +r 5240.10 +*Want "MXBR NF -0/-0 NT" 00000000 00000000 00000000 00000000 +r 5250.10 +*Want "MXBR NF -0/-0 Tr" 00000000 00000000 00000000 00000000 +r 5260.10 +*Want "MXBR NF -0/+0 NT" 80000000 00000000 00000000 00000000 +r 5270.10 +*Want "MXBR NF -0/+0 Tr" 80000000 00000000 00000000 00000000 +r 5280.10 +*Want "MXBR NF -0/+2.0 NT" 80000000 00000000 00000000 00000000 +r 5290.10 +*Want "MXBR NF -0/+2.0 Tr" 80000000 00000000 00000000 00000000 +r 52A0.10 +*Want "MXBR NF -0/+inf NT" 7FFF8000 00000000 00000000 00000000 +r 52B0.10 +*Want "MXBR NF -0/+inf Tr" 80000000 00000000 00000000 00000000 +r 52C0.10 +*Want "MXBR NF -0/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 52D0.10 +*Want "MXBR NF -0/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 52E0.10 +*Want "MXBR NF -0/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 52F0.10 +*Want "MXBR NF -0/+SNaN Tr" 80000000 00000000 00000000 00000000 +r 5300.10 +*Want "MXBR NF +0/-inf NT" 7FFF8000 00000000 00000000 00000000 +r 5310.10 +*Want "MXBR NF +0/-inf Tr" 00000000 00000000 00000000 00000000 +r 5320.10 +*Want "MXBR NF +0/-2.0 NT" 80000000 00000000 00000000 00000000 +r 5330.10 +*Want "MXBR NF +0/-2.0 Tr" 80000000 00000000 00000000 00000000 +r 5340.10 +*Want "MXBR NF +0/-0 NT" 80000000 00000000 00000000 00000000 +r 5350.10 +*Want "MXBR NF +0/-0 Tr" 80000000 00000000 00000000 00000000 +r 5360.10 +*Want "MXBR NF +0/+0 NT" 00000000 00000000 00000000 00000000 +r 5370.10 +*Want "MXBR NF +0/+0 Tr" 00000000 00000000 00000000 00000000 +r 5380.10 +*Want "MXBR NF +0/+2.0 NT" 00000000 00000000 00000000 00000000 +r 5390.10 +*Want "MXBR NF +0/+2.0 Tr" 00000000 00000000 00000000 00000000 +r 53A0.10 +*Want "MXBR NF +0/+inf NT" 7FFF8000 00000000 00000000 00000000 +r 53B0.10 +*Want "MXBR NF +0/+inf Tr" 00000000 00000000 00000000 00000000 +r 53C0.10 +*Want "MXBR NF +0/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 53D0.10 +*Want "MXBR NF +0/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 53E0.10 +*Want "MXBR NF +0/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 53F0.10 +*Want "MXBR NF +0/+SNaN Tr" 00000000 00000000 00000000 00000000 +r 5400.10 +*Want "MXBR NF +2.0/-inf NT" FFFF0000 00000000 00000000 00000000 +r 5410.10 +*Want "MXBR NF +2.0/-inf Tr" FFFF0000 00000000 00000000 00000000 +r 5420.10 +*Want "MXBR NF +2.0/-2.0 NT" C0010000 00000000 00000000 00000000 +r 5430.10 +*Want "MXBR NF +2.0/-2.0 Tr" C0010000 00000000 00000000 00000000 +r 5440.10 +*Want "MXBR NF +2.0/-0 NT" 80000000 00000000 00000000 00000000 +r 5450.10 +*Want "MXBR NF +2.0/-0 Tr" 80000000 00000000 00000000 00000000 +r 5460.10 +*Want "MXBR NF +2.0/+0 NT" 00000000 00000000 00000000 00000000 +r 5470.10 +*Want "MXBR NF +2.0/+0 Tr" 00000000 00000000 00000000 00000000 +r 5480.10 +*Want "MXBR NF +2.0/+2.0 NT" 40010000 00000000 00000000 00000000 +r 5490.10 +*Want "MXBR NF +2.0/+2.0 Tr" 40010000 00000000 00000000 00000000 +r 54A0.10 +*Want "MXBR NF +2.0/+inf NT" 7FFF0000 00000000 00000000 00000000 +r 54B0.10 +*Want "MXBR NF +2.0/+inf Tr" 7FFF0000 00000000 00000000 00000000 +r 54C0.10 +*Want "MXBR NF +2.0/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 54D0.10 +*Want "MXBR NF +2.0/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 54E0.10 +*Want "MXBR NF +2.0/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 54F0.10 +*Want "MXBR NF +2.0/+SNaN Tr" 40000000 00000000 00000000 00000000 +r 5500.10 +*Want "MXBR NF +inf/-inf NT" FFFF0000 00000000 00000000 00000000 +r 5510.10 +*Want "MXBR NF +inf/-inf Tr" FFFF0000 00000000 00000000 00000000 +r 5520.10 +*Want "MXBR NF +inf/-2.0 NT" FFFF0000 00000000 00000000 00000000 +r 5530.10 +*Want "MXBR NF +inf/-2.0 Tr" FFFF0000 00000000 00000000 00000000 +r 5540.10 +*Want "MXBR NF +inf/-0 NT" 7FFF8000 00000000 00000000 00000000 +r 5550.10 +*Want "MXBR NF +inf/-0 Tr" 7FFF0000 00000000 00000000 00000000 +r 5560.10 +*Want "MXBR NF +inf/+0 NT" 7FFF8000 00000000 00000000 00000000 +r 5570.10 +*Want "MXBR NF +inf/+0 Tr" 7FFF0000 00000000 00000000 00000000 +r 5580.10 +*Want "MXBR NF +inf/+2.0 NT" 7FFF0000 00000000 00000000 00000000 +r 5590.10 +*Want "MXBR NF +inf/+2.0 Tr" 7FFF0000 00000000 00000000 00000000 +r 55A0.10 +*Want "MXBR NF +inf/+inf NT" 7FFF0000 00000000 00000000 00000000 +r 55B0.10 +*Want "MXBR NF +inf/+inf Tr" 7FFF0000 00000000 00000000 00000000 +r 55C0.10 +*Want "MXBR NF +inf/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 55D0.10 +*Want "MXBR NF +inf/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 55E0.10 +*Want "MXBR NF +inf/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 55F0.10 +*Want "MXBR NF +inf/+SNaN Tr" 7FFF0000 00000000 00000000 00000000 +r 5600.10 +*Want "MXBR NF -QNaN/-inf NT" FFFF8B00 00000000 00000000 00000000 +r 5610.10 +*Want "MXBR NF -QNaN/-inf Tr" FFFF8B00 00000000 00000000 00000000 +r 5620.10 +*Want "MXBR NF -QNaN/-2.0 NT" FFFF8B00 00000000 00000000 00000000 +r 5630.10 +*Want "MXBR NF -QNaN/-2.0 Tr" FFFF8B00 00000000 00000000 00000000 +r 5640.10 +*Want "MXBR NF -QNaN/-0 NT" FFFF8B00 00000000 00000000 00000000 +r 5650.10 +*Want "MXBR NF -QNaN/-0 Tr" FFFF8B00 00000000 00000000 00000000 +r 5660.10 +*Want "MXBR NF -QNaN/+0 NT" FFFF8B00 00000000 00000000 00000000 +r 5670.10 +*Want "MXBR NF -QNaN/+0 Tr" FFFF8B00 00000000 00000000 00000000 +r 5680.10 +*Want "MXBR NF -QNaN/+2.0 NT" FFFF8B00 00000000 00000000 00000000 +r 5690.10 +*Want "MXBR NF -QNaN/+2.0 Tr" FFFF8B00 00000000 00000000 00000000 +r 56A0.10 +*Want "MXBR NF -QNaN/+inf NT" FFFF8B00 00000000 00000000 00000000 +r 56B0.10 +*Want "MXBR NF -QNaN/+inf Tr" FFFF8B00 00000000 00000000 00000000 +r 56C0.10 +*Want "MXBR NF -QNaN/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 56D0.10 +*Want "MXBR NF -QNaN/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 56E0.10 +*Want "MXBR NF -QNaN/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 56F0.10 +*Want "MXBR NF -QNaN/+SNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 5700.10 +*Want "MXBR NF +SNaN/-inf NT" 7FFF8A00 00000000 00000000 00000000 +r 5710.10 +*Want "MXBR NF +SNaN/-inf Tr" 7FFF0A00 00000000 00000000 00000000 +r 5720.10 +*Want "MXBR NF +SNaN/-2.0 NT" 7FFF8A00 00000000 00000000 00000000 +r 5730.10 +*Want "MXBR NF +SNaN/-2.0 Tr" 7FFF0A00 00000000 00000000 00000000 +r 5740.10 +*Want "MXBR NF +SNaN/-0 NT" 7FFF8A00 00000000 00000000 00000000 +r 5750.10 +*Want "MXBR NF +SNaN/-0 Tr" 7FFF0A00 00000000 00000000 00000000 +r 5760.10 +*Want "MXBR NF +SNaN/+0 NT" 7FFF8A00 00000000 00000000 00000000 +r 5770.10 +*Want "MXBR NF +SNaN/+0 Tr" 7FFF0A00 00000000 00000000 00000000 +r 5780.10 +*Want "MXBR NF +SNaN/+2.0 NT" 7FFF8A00 00000000 00000000 00000000 +r 5790.10 +*Want "MXBR NF +SNaN/+2.0 Tr" 7FFF0A00 00000000 00000000 00000000 +r 57A0.10 +*Want "MXBR NF +SNaN/+inf NT" 7FFF8A00 00000000 00000000 00000000 +r 57B0.10 +*Want "MXBR NF +SNaN/+inf Tr" 7FFF0A00 00000000 00000000 00000000 +r 57C0.10 +*Want "MXBR NF +SNaN/-QNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 57D0.10 +*Want "MXBR NF +SNaN/-QNaN Tr" 7FFF0A00 00000000 00000000 00000000 +r 57E0.10 +*Want "MXBR NF +SNaN/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 57F0.10 +*Want "MXBR NF +SNaN/+SNaN Tr" 7FFF0A00 00000000 00000000 00000000 + + +# Extended BFP non-finite test results - FPCR contents +*Compare +r 5800.08 +*Want "MXBR NF -inf/-inf FPCR" 00000000 F8000000 +r 5810.08 +*Want "MXBR NF -inf/-2.0 FPCR" 00000000 F8000000 +r 5820.08 +*Want "MXBR NF -inf/-0 FPCR" 00800000 F8008000 +r 5830.08 +*Want "MXBR NF -inf/+0 FPCR" 00800000 F8008000 +r 5840.08 +*Want "MXBR NF -inf/+2.0 FPCR" 00000000 F8000000 +r 5850.08 +*Want "MXBR NF -inf/+inf FPCR" 00000000 F8000000 +r 5860.08 +*Want "MXBR NF -inf/-QNaN FPCR" 00000000 F8000000 +r 5870.08 +*Want "MXBR NF -inf/+SNaN FPCR" 00800000 F8008000 +r 5880.08 +*Want "MXBR NF -2.0/-inf FPCR" 00000000 F8000000 +r 5890.08 +*Want "MXBR NF -2.0/-2.0 FPCR" 00000000 F8000000 +r 58A0.08 +*Want "MXBR NF -2.0/-0 FPCR" 00000000 F8000000 +r 58B0.08 +*Want "MXBR NF -2.0/+0 FPCR" 00000000 F8000000 +r 58C0.08 +*Want "MXBR NF -2.0/+2.0 FPCR" 00000000 F8000000 +r 58D0.08 +*Want "MXBR NF -2.0/+inf FPCR" 00000000 F8000000 +r 58E0.08 +*Want "MXBR NF -2.0/-QNaN FPCR" 00000000 F8000000 +r 58F0.08 +*Want "MXBR NF -2.0/+SNaN FPCR" 00800000 F8008000 +r 5900.08 +*Want "MXBR NF -0/-inf FPCR" 00800000 F8008000 +r 5910.08 +*Want "MXBR NF -0/-2.0 FPCR" 00000000 F8000000 +r 5920.08 +*Want "MXBR NF -0/-0 FPCR" 00000000 F8000000 +r 5930.08 +*Want "MXBR NF -0/+0 FPCR" 00000000 F8000000 +r 5940.08 +*Want "MXBR NF -0/+2.0 FPCR" 00000000 F8000000 +r 5950.08 +*Want "MXBR NF -0/+inf FPCR" 00800000 F8008000 +r 5960.08 +*Want "MXBR NF -0/-QNaN FPCR" 00000000 F8000000 +r 5970.08 +*Want "MXBR NF -0/+SNaN FPCR" 00800000 F8008000 +r 5980.08 +*Want "MXBR NF +0/-inf FPCR" 00800000 F8008000 +r 5990.08 +*Want "MXBR NF +0/-2.0 FPCR" 00000000 F8000000 +r 59A0.08 +*Want "MXBR NF +0/-0 FPCR" 00000000 F8000000 +r 59B0.08 +*Want "MXBR NF +0/+0 FPCR" 00000000 F8000000 +r 59C0.08 +*Want "MXBR NF +0/+2.0 FPCR" 00000000 F8000000 +r 59D0.08 +*Want "MXBR NF +0/+inf FPCR" 00800000 F8008000 +r 59E0.08 +*Want "MXBR NF +0/-QNaN FPCR" 00000000 F8000000 +r 59F0.08 +*Want "MXBR NF +0/+SNaN FPCR" 00800000 F8008000 +r 5A00.08 +*Want "MXBR NF +2.0/-inf FPCR" 00000000 F8000000 +r 5A10.08 +*Want "MXBR NF +2.0/-2.0 FPCR" 00000000 F8000000 +r 5A20.08 +*Want "MXBR NF +2.0/-0 FPCR" 00000000 F8000000 +r 5A30.08 +*Want "MXBR NF +2.0/+0 FPCR" 00000000 F8000000 +r 5A40.08 +*Want "MXBR NF +2.0/+2.0 FPCR" 00000000 F8000000 +r 5A50.08 +*Want "MXBR NF +2.0/+inf FPCR" 00000000 F8000000 +r 5A60.08 +*Want "MXBR NF +2.0/-QNaN FPCR" 00000000 F8000000 +r 5A70.08 +*Want "MXBR NF +2.0/+SNaN FPCR" 00800000 F8008000 +r 5A80.08 +*Want "MXBR NF +inf/-inf FPCR" 00000000 F8000000 +r 5A90.08 +*Want "MXBR NF +inf/-2.0 FPCR" 00000000 F8000000 +r 5AA0.08 +*Want "MXBR NF +inf/-0 FPCR" 00800000 F8008000 +r 5AB0.08 +*Want "MXBR NF +inf/+0 FPCR" 00800000 F8008000 +r 5AC0.08 +*Want "MXBR NF +inf/+2.0 FPCR" 00000000 F8000000 +r 5AD0.08 +*Want "MXBR NF +inf/+inf FPCR" 00000000 F8000000 +r 5AE0.08 +*Want "MXBR NF +inf/-QNaN FPCR" 00000000 F8000000 +r 5AF0.08 +*Want "MXBR NF +inf/+SNaN FPCR" 00800000 F8008000 +r 5B00.08 +*Want "MXBR NF -QNaN/-inf FPCR" 00000000 F8000000 +r 5B10.08 +*Want "MXBR NF -QNaN/-2.0 FPCR" 00000000 F8000000 +r 5B20.08 +*Want "MXBR NF -QNaN/-0 FPCR" 00000000 F8000000 +r 5B30.08 +*Want "MXBR NF -QNaN/+0 FPCR" 00000000 F8000000 +r 5B40.08 +*Want "MXBR NF -QNaN/+2.0 FPCR" 00000000 F8000000 +r 5B50.08 +*Want "MXBR NF -QNaN/+inf FPCR" 00000000 F8000000 +r 5B60.08 +*Want "MXBR NF -QNaN/-QNaN FPCR" 00000000 F8000000 +r 5B70.08 +*Want "MXBR NF -QNaN/+SNaN FPCR" 00800000 F8008000 +r 5B80.08 +*Want "MXBR NF +SNaN/-inf FPCR" 00800000 F8008000 +r 5B90.08 +*Want "MXBR NF +SNaN/-2.0 FPCR" 00800000 F8008000 +r 5BA0.08 +*Want "MXBR NF +SNaN/-0 FPCR" 00800000 F8008000 +r 5BB0.08 +*Want "MXBR NF +SNaN/+0 FPCR" 00800000 F8008000 +r 5BC0.08 +*Want "MXBR NF +SNaN/+2.0 FPCR" 00800000 F8008000 +r 5BD0.08 +*Want "MXBR NF +SNaN/+inf FPCR" 00800000 F8008000 +r 5BE0.08 +*Want "MXBR NF +SNaN/-QNaN FPCR" 00800000 F8008000 +r 5BF0.08 +*Want "MXBR NF +SNaN/+SNaN FPCR" 00800000 F8008000 + + +# Extended BFP finite test results +*Compare +r 5C00.10 +*Want "MXBR F Ovfl NT" FFFF0000 00000000 00000000 00000000 +r 5C10.10 +*Want "MXBR F Ovfl Tr" DFFEFFFF FFFFFFFF FFFFFFFF FFFFFFFE +r 5C20.10 +*Want "MXBR F Ufl 1 NT" 00000000 00000000 00000000 00000000 +r 5C30.10 +*Want "MXBR F Ufl 1 Tr" 2003FFFF FFFFFFFF FFFFFFFF FFFFFFFF +r 5C40.10 +*Want "MXBR F Ufl 2 NT" 00000000 00000000 00000000 00000000 +r 5C50.10 +*Want "MXBR F Ufl 2 Tr" 1FFDE1E0 00000000 00000000 00000000 +r 5C60.10 +*Want "MXBR F Nmin NT" 00020000 00000000 00000000 00000000 +r 5C70.10 +*Want "MXBR F Nmin Tr" 00020000 00000000 00000000 00000000 +r 5C80.10 +*Want "MXBR F Incr NT" 3FFF1000 00000000 00000000 0000000D +r 5C90.10 +*Want "MXBR F Incr Tr" 3FFF1000 00000000 00000000 0000000D +r 5CA0.10 +*Want "MXBR F Trun NT" 3FFF1000 00000000 00000000 00000007 +r 5CB0.10 +*Want "MXBR F Trun Tr" 3FFF1000 00000000 00000000 00000007 + + +# Extended BFP finite test results - FPCR contents +*Compare +r 5E00.8 +*Want "MXBR F Ovfl FPCR" 00280000 F8002800 +r 5E10.8 +*Want "MXBR F Ufl 1 FPCR" 00180000 F8001000 +r 5E20.8 +*Want "MXBR F Ufl 2 FPCR" 00180000 F8001000 +r 5E30.8 +*Want "MXBR F Nmin FPCR" 00080000 F8000C00 +r 5E40.8 +*Want "MXBR F Incr FPCR" 00080000 F8000C00 +r 5E50.8 +*Want "MXBR F Trun FPCR" 00080000 F8000800 + + +# Extended BFP rounding mode test results +*Compare +r 6000.10 +*Want "MXBR RM +NZ RNTE" 3FFF1000 00000000 00000000 00000007 +r 6010.10 +*Want "MXBR RM +NZ RZ" 3FFF1000 00000000 00000000 00000007 +r 6020.10 +*Want "MXBR RM +NZ RP" 3FFF1000 00000000 00000000 00000008 +r 6030.10 +*Want "MXBR RM +NZ RM" 3FFF1000 00000000 00000000 00000007 +r 6040.10 +*Want "MXBR RM +NZ RFS" 3FFF1000 00000000 00000000 00000007 +r 6050.10 +*Want "MXBR RM -NZ RNTE" BFFF1000 00000000 00000000 00000007 +r 6060.10 +*Want "MXBR RM -NZ RZ" BFFF1000 00000000 00000000 00000007 +r 6070.10 +*Want "MXBR RM -NZ RP" BFFF1000 00000000 00000000 00000007 +r 6080.10 +*Want "MXBR RM -NZ RM" BFFF1000 00000000 00000000 00000008 +r 6090.10 +*Want "MXBR RM -NZ RFS" BFFF1000 00000000 00000000 00000007 +r 60A0.10 +*Want "MXBR RM +NA RNTE" 3FFF1000 00000000 00000000 0000000D +r 60B0.10 +*Want "MXBR RM +NA RZ" 3FFF1000 00000000 00000000 0000000C +r 60C0.10 +*Want "MXBR RM +NA RP" 3FFF1000 00000000 00000000 0000000D +r 60D0.10 +*Want "MXBR RM +NA RM" 3FFF1000 00000000 00000000 0000000C +r 60E0.10 +*Want "MXBR RM +NA RFS" 3FFF1000 00000000 00000000 0000000D +r 60F0.10 +*Want "MXBR RM -NA RNTE" BFFF1000 00000000 00000000 0000000D +r 6100.10 +*Want "MXBR RM -NA RZ" BFFF1000 00000000 00000000 0000000C +r 6110.10 +*Want "MXBR RM -NA RP" BFFF1000 00000000 00000000 0000000C +r 6120.10 +*Want "MXBR RM -NA RM" BFFF1000 00000000 00000000 0000000D +r 6130.10 +*Want "MXBR RM -NA RFS" BFFF1000 00000000 00000000 0000000D +r 6140.10 +*Want "MXBR RM +TZ RNTE" 3FFF1000 00000000 00000000 00000008 +r 6150.10 +*Want "MXBR RM +TZ RZ" 3FFF1000 00000000 00000000 00000008 +r 6160.10 +*Want "MXBR RM +TZ RP" 3FFF1000 00000000 00000000 00000009 +r 6170.10 +*Want "MXBR RM +TZ RM" 3FFF1000 00000000 00000000 00000008 +r 6180.10 +*Want "MXBR RM +TZ RFS" 3FFF1000 00000000 00000000 00000009 +r 6190.10 +*Want "MXBR RM -TZ RNTE" BFFF1000 00000000 00000000 00000008 +r 61A0.10 +*Want "MXBR RM -TZ RZ" BFFF1000 00000000 00000000 00000008 +r 61B0.10 +*Want "MXBR RM -TZ RP" BFFF1000 00000000 00000000 00000008 +r 61C0.10 +*Want "MXBR RM -TZ RM" BFFF1000 00000000 00000000 00000009 +r 61D0.10 +*Want "MXBR RM -TZ RFS" BFFF1000 00000000 00000000 00000009 +r 61E0.10 +*Want "MXBR RM +TA RNTE" 3FFF1000 00000000 00000000 0000001A +r 61F0.10 +*Want "MXBR RM +TA RZ" 3FFF1000 00000000 00000000 00000019 +r 6200.10 +*Want "MXBR RM +TA RP" 3FFF1000 00000000 00000000 0000001A +r 6210.10 +*Want "MXBR RM +TA RM" 3FFF1000 00000000 00000000 00000019 +r 6220.10 +*Want "MXBR RM +TA RFS" 3FFF1000 00000000 00000000 00000019 +r 6230.10 +*Want "MXBR RM -TA RNTE" BFFF1000 00000000 00000000 0000001A +r 6240.10 +*Want "MXBR RM -TA RZ" BFFF1000 00000000 00000000 00000019 +r 6250.10 +*Want "MXBR RM -TA RP" BFFF1000 00000000 00000000 00000019 +r 6260.10 +*Want "MXBR RM -TA RM" BFFF1000 00000000 00000000 0000001A +r 6270.10 +*Want "MXBR RM -TA RFS" BFFF1000 00000000 00000000 00000019 + + +# Extended BFP rounding mode test results - FPCR contents +*Compare +r 6500.10 +*Want "MXBR RM +NZ RNTE, RZ,RP,RM FPCR" 00080000 00080001 00080002 00080003 +r 6510.4 +*Want "MXBR RM +NZ RFS FPCR" 00080007 +r 6520.10 +*Want "MXBR RM -NZ RNTE, RZ,RP,RM FPCR" 00080000 00080001 00080002 00080003 +r 6530.4 +*Want "MXBR RM -NZ RFS FPCR" 00080007 +r 6540.10 +*Want "MXBR RM +NA RNTE, RZ,RP,RM FPCR" 00080000 00080001 00080002 00080003 +r 6550.4 +*Want "MXBR RM +NA RFS FPCR" 00080007 +r 6560.10 +*Want "MXBR RM -NA RNTE, RZ,RP,RM FPCR" 00080000 00080001 00080002 00080003 +r 6570.4 +*Want "MXBR RM -NA RFS FPCR" 00080007 +r 6580.10 +*Want "MXBR RM +TZ RNTE, RZ,RP,RM FPCR" 00080000 00080001 00080002 00080003 +r 6590.4 +*Want "MXBR RM +TZ RFS FPCR" 00080007 +r 65A0.10 +*Want "MXBR RM -TZ RNTE, RZ,RP,RM FPCR" 00080000 00080001 00080002 00080003 +r 65B0.4 +*Want "MXBR RM -TZ RFS FPCR" 00080007 +r 65C0.10 +*Want "MXBR RM +TA RNTE, RZ,RP,RM FPCR" 00080000 00080001 00080002 00080003 +r 65D0.4 +*Want "MXBR RM +TA RFS FPCR" 00080007 +r 65E0.10 +*Want "MXBR RM -TA RNTE, RZ,RP,RM FPCR" 00080000 00080001 00080002 00080003 +r 65F0.4 +*Want "MXBR RM -TA RFS FPCR" 00080007 + + + +*Done + diff --git a/tests/bfp-020-multlonger.asm b/tests/bfp-020-multlonger.asm new file mode 100644 index 000000000..b892bd2a9 --- /dev/null +++ b/tests/bfp-020-multlonger.asm @@ -0,0 +1,454 @@ + TITLE 'bfp-020-multlonger.asm: Test IEEE Multiply' +*********************************************************************** +* +*Testcase IEEE MULTIPLY (to longer precision) +* Test case capability includes IEEE exceptions trappable and +* otherwise. Test results, FPCR flags, the Condition code, and any +* DXC are saved for all tests. +* +* The result precision for each instruction is longer than the input +* operands. As a result, the underflow and overflow exceptions will +* never occur. Further, the results are always exact. There is +* no rounding of the result. +* +* The fused multiply operations are not included in this test program, +* nor are the standard multiply instructions. The former are +* are excluded to keep test case complexity manageable, and latter +* because they require a more extensive testing profile (overflow, +* underflow, rounding). +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* bfp-020-multlonger.asm +* +* This assembly-language source file is part of the +* Hercules Decimal Floating Point Validation Package +* by Stephen R. Orso +* +* Copyright 2016 by Stephen R Orso. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* +* 3. The name of the author may not be used to endorse or promote +* products derived from this software without specific prior written +* permission. +* +* DISCLAMER: THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* HOLDER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* Tests the following five conversion instructions +* MULTIPLY (short BFP, RRE) (short to long) +* MULTIPLY (long BFP, RRE) (long to extended) +* MULTIPLY (short BFP, RXE) (short to long) +* MULTIPLY (long BFP, RXE) (long to extended) +* +* Test data is compiled into this program. The test script that runs +* this program can provide alternative test data through Hercules R +* commands. +* +* Test Case Order +* 1) Short BFP basic tests, including traps and NaN propagation +* 2) Long BFP basic tests, including traps and NaN propagation +* +* One input test sets are provided each for short and long BFP inputs. +* Test values are the same for each precision. +* +* Also tests the following floating point support instructions +* LOAD (Short) +* LOAD (Long) +* LFPC (Load Floating Point Control Register) +* STORE (Short) +* STORE (Long) +* STFPC (Store Floating Point Control Register) +* +*********************************************************************** + SPACE 2 + MACRO + PADCSECT &ENDLABL +.* +.* Macro to pad the CSECT to include result data areas if this test +.* program is not being assembled using asma. asma generates a core +.* image that is loaded by the loadcore command, and because the +.* core image is a binary stored in Github, it makes sense to make +.* this small effort to keep the core image small. +.* + AIF (D'&ENDLABL).GOODPAD + MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + MNOTE *,'No CSECT padding performed' + MEXIT +.* +.GOODPAD ANOP Label valid. See if we're on asma + AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + ORG &ENDLABL-1 Not ASMA. Pad CSECT + MEXIT +.* +.NOPAD ANOP + MNOTE *,'asma detected; no CSECT padding performed' + MEND +* +* Note: for compatibility with the z/CMS test rig, do not change +* or use R11, R14, or R15. Everything else is fair game. +* +BFPMUL2L START 0 +STRTLABL EQU * +R0 EQU 0 Work register for cc extraction +R1 EQU 1 +R2 EQU 2 Holds count of test input values +R3 EQU 3 Points to next test input value(s) +R4 EQU 4 Rounding tests inner loop control +R5 EQU 5 Rounding tests outer loop control +R6 EQU 6 Rounding tests top of inner loop +R7 EQU 7 Pointer to next result value(s) +R8 EQU 8 Pointer to next FPCR result +R9 EQU 9 Rounding tests top of outer loop +R10 EQU 10 Pointer to test address list +R11 EQU 11 **Reserved for z/CMS test rig +R12 EQU 12 Holds number of test cases in set +R13 EQU 13 Mainline return address +R14 EQU 14 **Return address for z/CMS test rig +R15 EQU 15 **Base register on z/CMS or Hyperion +* +* Floating Point Register equates to keep the cross reference clean +* +FPR0 EQU 0 +FPR1 EQU 1 +FPR2 EQU 2 +FPR3 EQU 3 +FPR4 EQU 4 +FPR5 EQU 5 +FPR6 EQU 6 +FPR7 EQU 7 +FPR8 EQU 8 +FPR9 EQU 9 +FPR10 EQU 10 +FPR11 EQU 11 +FPR12 EQU 12 +FPR13 EQU 13 +FPR14 EQU 14 +FPR15 EQU 15 +* + USING *,R15 +* +* Above works on real iron (R15=0 after sysclear) +* and in z/CMS (R15 points to start of load module) +* + SPACE 2 +*********************************************************************** +* +* Low core definitions, Restart PSW, and Program Check Routine. +* +*********************************************************************** + SPACE 2 + ORG STRTLABL+X'8E' Program check interrution code +PCINTCD DS H +* +PCOLDPSW EQU STRTLABL+X'150' z/Arch Program check old PSW +* + ORG STRTLABL+X'1A0' z/Arch Restart PSW + DC X'0000000180000000',AD(START) +* + ORG STRTLABL+X'1D0' z/Arch Program check old PSW + DC X'0000000000000000',AD(PROGCHK) +* +* Program check routine. If Data Exception, continue execution at +* the instruction following the program check. Otherwise, hard wait. +* No need to collect data. All interesting DXC stuff is captured +* in the FPCR. +* + ORG STRTLABL+X'200' +PROGCHK DS 0H Program check occured... + CLI PCINTCD+1,X'07' Data Exception? + JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) + LPSWE PCOLDPSW ..yes, resume program execution +PCNOTDTA DS 0H + LTR R14,R14 Return address provided? + BNZR R14 Yes, return to z/CMS test rig. + LPSWE HARDWAIT Not data exception, enter disabled wait + EJECT +*********************************************************************** +* +* Main program. Enable Advanced Floating Point, process test cases. +* +*********************************************************************** + SPACE 2 +START DS 0H + STCTL R0,R0,CTLR0 Store CR0 to enable AFP + OI CTLR0+1,X'04' Turn on AFP bit + LCTL R0,R0,CTLR0 Reload updated CR0 +* + LA R10,SHORTNF Point to short BFP non-finite inputs + BAS R13,SBFPNF Multiply short BFP non-finites +* + LA R10,LONGNF Point to long BFP non-finite inputs + BAS R13,LBFPNF Multiply long BFP non-finites +* + LTR R14,R14 Return address provided? + BNZR R14 ..Yes, return to z/CMS test rig. + LPSWE WAITPSW All done +* + DS 0D Ensure correct alignment for psw +WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end +* +CTLR0 DS F +FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags +* +* Input values parameter list, four fullwords for each test data set +* 1) Count, +* 2) Address of inputs, +* 3) Address to place results, and +* 4) Address to place DXC/Flags/cc values. +* + ORG STRTLABL+X'300' Enable run-time replacement +SHORTNF DS 0F Input pairs for short BFP non-finite tests + DC A(SBFPNFCT) + DC A(SBFPNFIN) + DC A(LBFPNFOT) + DC A(LBFPNFFL) +* +LONGNF DS 0F Input pairs for long BFP non-finite testing + DC A(LBFPNFCT) + DC A(LBFPNFIN) + DC A(XBFPNFOT) + DC A(XBFPNFFL) +* + EJECT +*********************************************************************** +* +* Perform Multiply using provided short BFP inputs. This set of tests +* checks NaN propagation, operations on values that are not finite +* numbers, and other basic tests. This set generates results that can +* be validated against Figure 19-23 on page 19-28 of SA22-7832-10. +* Each value in this table is tested against every other value in the +* table. Eight entries means 64 result sets. +* +* Four results are generated for each input: one RRE with all +* exceptions non-trappable, a second RRE with all exceptions trappable, +* a third RXE with all exceptions non-trappable, a fourth RXE with all +* exceptions trappable, +* +* The difference, FPCR, and condition code are stored for each result. +* +*********************************************************************** + SPACE 2 +SBFPNF DS 0H BFP Short non-finite values tests + LM R2,R3,0(R10) Get count and addr of multiplicand values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LM R4,R5,0(R10) Get count and start of multiplier values +* ..which are the same as the multiplicands + BASR R6,0 Set top of inner loop +* + LE FPR8,0(,R3) Get short BFP multiplicand + LE FPR1,0(,R5) Get short BFP multiplier + LFPC FPCREGNT Set exceptions non-trappable + MDEBR FPR8,FPR1 Multiply short FPR8 by FPR1 RRE + STD FPR8,0(,R7) Store long BFP product + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LE FPR8,0(,R3) Get short BFP multiplicand + LE FPR1,0(,R5) Get short BFP multiplier + LFPC FPCREGTR Set exceptions trappable + MDEBR FPR8,FPR1 Multiply short FPR8 by FPR1 RRE + STD FPR8,8(,R7) Store long BFP product + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LE FPR8,0(,R3) Get short BFP multiplicand + LFPC FPCREGNT Set exceptions non-trappable + MDEB FPR8,0(,R5) Multiply short FPR8 by multiplier RXE + STD FPR8,16(,R7) Store long BFP product + STFPC 8(R8) Store resulting FPCR flags and DXC +* + LE FPR8,0(,R3) Get short BFP multiplicand + LFPC FPCREGTR Set exceptions trappable + MDEB FPR8,0(,R5) Multiply short FPR8 by multiplier RXE + STD FPR8,24(,R7) Store long BFP product + STFPC 12(R8) Store resulting FPCR flags and DXC +* + LA R5,4(,R5) Point to next multiplier value + LA R7,4*8(,R7) Point to next Multiply result area + LA R8,4*4(,R8) Point to next Multiply FPCR area + BCTR R4,R6 Loop through right-hand values +* + LA R3,4(,R3) Point to next input multiplicand + BCTR R2,R12 Loop through left-hand values + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Multiply using provided long BFP inputs. This set of tests +* checks NaN propagation, operations on values that are not finite +* numbers, and other basic tests. This set generates results that can +* validated against Figure 19-23 on page 19-28 of SA22-7832-10. Each +* value in this table is tested against every other value in the table. +* Eight entries means 64 result sets. +* +* Four results are generated for each input: one RRE with all +* exceptions non-trappable, a second RRE with all exceptions trappable, +* a third RXE with all exceptions non-trappable, a fourth RXE with all +* exceptions trappable, +* +* The difference, FPCR, and condition code are stored for each result. +* +*********************************************************************** + SPACE 2 +LBFPNF DS 0H BFP long non-finite values tests + LM R2,R3,0(R10) Get count and addr of multiplicand values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LM R4,R5,0(R10) Get count and start of multiplier values +* ..which are the same as the multiplicands + BASR R6,0 Set top of inner loop +* + LD FPR8,0(,R3) Get long BFP multiplicand + LD FPR1,0(,R5) Get long BFP multiplier + LFPC FPCREGNT Set exceptions non-trappable + MXDBR FPR8,FPR1 Multiply long FPR8 by FPR1 RRE + STD FPR8,0(,R7) Store extended BFP product part 1 + STD FPR10,8(,R7) Store extended BFP product part 2 + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LD FPR8,0(,R3) Get long BFP multiplicand + LD FPR1,0(,R5) Get long BFP multiplier + LFPC FPCREGTR Set exceptions trappable + MXDBR FPR8,FPR1 Multiply long multiplier from FPR8 RRE + STD FPR8,16(,R7) Store extended BFP product part 1 + STD FPR10,24(,R7) Store extended BFP product part 2 + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LD FPR8,0(,R3) Get long BFP multiplicand + LFPC FPCREGNT Set exceptions non-trappable + MXDB FPR8,0(,R5) Multiply long FPR8 by multiplier RXE + STD FPR8,32(,R7) Store extended BFP product part 1 + STD FPR10,40(,R7) Store extended BFP product part 2 + STFPC 8(R8) Store resulting FPCR flags and DXC +* + LD FPR8,0(,R3) Get long BFP multiplicand + LFPC FPCREGTR Set exceptions trappable + MXDB FPR8,0(,R5) Multiply long FPR8 by multiplier RXE + STD FPR8,48(,R7) Store extended BFP product part 1 + STD FPR10,56(,R7) Store extended BFP product part 2 + STFPC 12(R8) Store resulting FPCR flags and DXC +* + LA R5,8(,R5) Point to next multiplier value + LA R7,4*16(,R7) Point to next Multiply result area + LA R8,4*4(,R8) Point to next Multiply FPCR area + BCTR R4,R6 Loop through right-hand values +* + LA R3,8(,R3) Point to next multiplicand value + BCTR R2,R12 Multiply until all cases tested + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Short BFP test data for Multiply to longer precision testing. +* +* The test data set is used for tests of basic functionality, NaN +* propagation, and results from operations involving other than finite +* numbers. +* +* Member values chosen to validate against Figure 19-23 on page 19-28 +* of SA22-7832-10. Each value in this table is tested against every +* other value in the table. Eight entries means 64 result sets. +* +* Because Multiply to longer precision cannot generate overflow nor +* underflow exceptions and the result is always exact, there are no +* further tests required. Any more extensive testing would be in +* effect a test of Softfloat, not of the the integration of Softfloat +* to Hercules. +* +*********************************************************************** + SPACE 2 +SBFPNFIN DS 0F Inputs for short BFP non-finite tests + DC X'FF800000' -inf + DC X'C0000000' -2.0 + DC X'80000000' -0 + DC X'00000000' +0 + DC X'40000000' +2.0 + DC X'7F800000' +inf + DC X'FFCB0000' -QNaN + DC X'7F8A0000' +SNaN +SBFPNFCT EQU (*-SBFPNFIN)/4 Count of short BFP in list + EJECT +*********************************************************************** +* +* Long BFP test data for Multiply to longer precision testing. +* +* The test data set is used for tests of basic functionality, NaN +* propagation, and results from operations involving other than finite +* numbers. +* +* Member values chosen to validate against Figure 19-23 on page 19-28 +* of SA22-7832-10. Each value in this table is tested against every +* other value in the table. Eight entries means 64 result sets. +* +* Because Multiply to longer precision cannot generate overflow nor +* underflow exceptions and the result is always exact, there are no +* further tests required. Any more extensive testing would be in +* effect a test of Softfloat, not of the the integration of Softfloat +* to Hercules. +* +*********************************************************************** + SPACE 2 +LBFPNFIN DS 0F Inputs for long BFP testing + DC X'FFF0000000000000' -inf + DC X'C000000000000000' -2.0 + DC X'8000000000000000' -0 + DC X'0000000000000000' +0 + DC X'4000000000000000' +2.0 + DC X'7FF0000000000000' +inf + DC X'FFF8B00000000000' -QNaN + DC X'7FF0A00000000000' +SNaN +LBFPNFCT EQU (*-LBFPNFIN)/8 Count of long BFP in list + EJECT +* +* Locations for results +* +LBFPNFOT EQU STRTLABL+X'1000' Short non-finite BFP results +* ..room for 64 tests, 64 used +LBFPNFFL EQU STRTLABL+X'1800' FPCR flags and DXC from short BFP +* ..room for 64 tests, 64 used +* ..next location starts at X'1C00' +* +* +XBFPNFOT EQU STRTLABL+X'2000' Long non-finite BFP results +* ..room for 64 tests, 64 used +XBFPNFFL EQU STRTLABL+X'3000' FPCR flags and DXC from long BFP +* ..room for 64 tests, 64 used +* ..next location starts at X'3400' +* +ENDLABL EQU STRTLABL+X'3400' + PADCSECT ENDLABL + END diff --git a/tests/bfp-020-multlonger.core b/tests/bfp-020-multlonger.core new file mode 100644 index 000000000..4f25df93d Binary files /dev/null and b/tests/bfp-020-multlonger.core differ diff --git a/tests/bfp-020-multlonger.list b/tests/bfp-020-multlonger.list new file mode 100644 index 000000000..eb7a89104 --- /dev/null +++ b/tests/bfp-020-multlonger.list @@ -0,0 +1,559 @@ +ASMA Ver. 0.2.0 bfp-020-multlonger.asm: Test IEEE Multiply 06 Oct 2016 10:16:49 Page 1 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 2 *********************************************************************** + 3 * + 4 *Testcase IEEE MULTIPLY (to longer precision) + 5 * Test case capability includes IEEE exceptions trappable and + 6 * otherwise. Test results, FPCR flags, the Condition code, and any + 7 * DXC are saved for all tests. + 8 * + 9 * The result precision for each instruction is longer than the input + 10 * operands. As a result, the underflow and overflow exceptions will + 11 * never occur. Further, the results are always exact. There is + 12 * no rounding of the result. + 13 * + 14 * The fused multiply operations are not included in this test program, + 15 * nor are the standard multiply instructions. The former are + 16 * are excluded to keep test case complexity manageable, and latter + 17 * because they require a more extensive testing profile (overflow, + 18 * underflow, rounding). + 19 * + 20 *********************************************************************** + + + 22 *********************************************************************** + 23 * + 24 * Tests the following five conversion instructions + 25 * MULTIPLY (short BFP, RRE) (short to long) + 26 * MULTIPLY (long BFP, RRE) (long to extended) + 27 * MULTIPLY (short BFP, RXE) (short to long) + 28 * MULTIPLY (long BFP, RXE) (long to extended) + 29 * + 30 * Test data is compiled into this program. The test script that runs + 31 * this program can provide alternative test data through Hercules R + 32 * commands. + 33 * + 34 * Test Case Order + 35 * 1) Short BFP basic tests, including traps and NaN propagation + 36 * 2) Long BFP basic tests, including traps and NaN propagation + 37 * + 38 * One input test sets are provided each for short and long BFP inputs. + 39 * Test values are the same for each precision. + 40 * + 41 * Also tests the following floating point support instructions + 42 * LOAD (Short) + 43 * LOAD (Long) + 44 * LFPC (Load Floating Point Control Register) + 45 * STORE (Short) + 46 * STORE (Long) + 47 * STFPC (Store Floating Point Control Register) + 48 * + 49 *********************************************************************** + + + 51 MACRO + ASMA Ver. 0.2.0 bfp-020-multlonger.asm: Test IEEE Multiply 06 Oct 2016 10:16:49 Page 2 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 52 PADCSECT &ENDLABL + 53 .* + 54 .* Macro to pad the CSECT to include result data areas if this test + 55 .* program is not being assembled using asma. asma generates a core + 56 .* image that is loaded by the loadcore command, and because the + 57 .* core image is a binary stored in Github, it makes sense to make + 58 .* this small effort to keep the core image small. + 59 .* + 60 AIF (D'&ENDLABL).GOODPAD + 61 MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + 62 MNOTE *,'No CSECT padding performed' + 63 MEXIT + 64 .* + 65 .GOODPAD ANOP Label valid. See if we're on asma + 66 AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + 67 ORG &ENDLABL-1 Not ASMA. Pad CSECT + 68 MEXIT + 69 .* + 70 .NOPAD ANOP + 71 MNOTE *,'asma detected; no CSECT padding performed' + 72 MEND + 73 * + 74 * Note: for compatibility with the z/CMS test rig, do not change + 75 * or use R11, R14, or R15. Everything else is fair game. + 76 * + 0000000000000000 000000000000049B 77 BFPMUL2L START 0 + 0000000000000000 0000000000000001 78 STRTLABL EQU * + 0000000000000000 0000000000000001 79 R0 EQU 0 Work register for cc extraction + 0000000000000001 0000000000000001 80 R1 EQU 1 + 0000000000000002 0000000000000001 81 R2 EQU 2 Holds count of test input values + 0000000000000003 0000000000000001 82 R3 EQU 3 Points to next test input value(s) + 0000000000000004 0000000000000001 83 R4 EQU 4 Rounding tests inner loop control + 0000000000000005 0000000000000001 84 R5 EQU 5 Rounding tests outer loop control + 0000000000000006 0000000000000001 85 R6 EQU 6 Rounding tests top of inner loop + 0000000000000007 0000000000000001 86 R7 EQU 7 Pointer to next result value(s) + 0000000000000008 0000000000000001 87 R8 EQU 8 Pointer to next FPCR result + 0000000000000009 0000000000000001 88 R9 EQU 9 Rounding tests top of outer loop + 000000000000000A 0000000000000001 89 R10 EQU 10 Pointer to test address list + 000000000000000B 0000000000000001 90 R11 EQU 11 **Reserved for z/CMS test rig + 000000000000000C 0000000000000001 91 R12 EQU 12 Holds number of test cases in set + 000000000000000D 0000000000000001 92 R13 EQU 13 Mainline return address + 000000000000000E 0000000000000001 93 R14 EQU 14 **Return address for z/CMS test rig + 000000000000000F 0000000000000001 94 R15 EQU 15 **Base register on z/CMS or Hyperion + 95 * + 96 * Floating Point Register equates to keep the cross reference clean + 97 * + 0000000000000000 0000000000000001 98 FPR0 EQU 0 + 0000000000000001 0000000000000001 99 FPR1 EQU 1 + 0000000000000002 0000000000000001 100 FPR2 EQU 2 + 0000000000000003 0000000000000001 101 FPR3 EQU 3 + 0000000000000004 0000000000000001 102 FPR4 EQU 4 + 0000000000000005 0000000000000001 103 FPR5 EQU 5 + ASMA Ver. 0.2.0 bfp-020-multlonger.asm: Test IEEE Multiply 06 Oct 2016 10:16:49 Page 3 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 0000000000000006 0000000000000001 104 FPR6 EQU 6 + 0000000000000007 0000000000000001 105 FPR7 EQU 7 + 0000000000000008 0000000000000001 106 FPR8 EQU 8 + 0000000000000009 0000000000000001 107 FPR9 EQU 9 + 000000000000000A 0000000000000001 108 FPR10 EQU 10 + 000000000000000B 0000000000000001 109 FPR11 EQU 11 + 000000000000000C 0000000000000001 110 FPR12 EQU 12 + 000000000000000D 0000000000000001 111 FPR13 EQU 13 + 000000000000000E 0000000000000001 112 FPR14 EQU 14 + 000000000000000F 0000000000000001 113 FPR15 EQU 15 + 114 * +0000000000000000 0000000000000000 115 USING *,R15 + 116 * + 117 * Above works on real iron (R15=0 after sysclear) + 118 * and in z/CMS (R15 points to start of load module) + 119 * + + + 121 *********************************************************************** + 122 * + 123 * Low core definitions, Restart PSW, and Program Check Routine. + 124 * + 125 *********************************************************************** + + +0000000000000000 0000000000000000 000000000000008E 127 ORG STRTLABL+X'8E' Program check interrution code +000000000000008E 0000 128 PCINTCD DS H + 129 * + 0000000000000150 0000000000000001 130 PCOLDPSW EQU STRTLABL+X'150' z/Arch Program check old PSW + 131 * +0000000000000090 0000000000000090 00000000000001A0 132 ORG STRTLABL+X'1A0' z/Arch Restart PSW +00000000000001A0 00000001 80000000 133 DC X'0000000180000000',AD(START) + 134 * +00000000000001B0 00000000000001B0 00000000000001D0 135 ORG STRTLABL+X'1D0' z/Arch Program check old PSW +00000000000001D0 00000000 00000000 136 DC X'0000000000000000',AD(PROGCHK) + 137 * + 138 * Program check routine. If Data Exception, continue execution at + 139 * the instruction following the program check. Otherwise, hard wait. + 140 * No need to collect data. All interesting DXC stuff is captured + 141 * in the FPCR. + 142 * +00000000000001E0 00000000000001E0 0000000000000200 143 ORG STRTLABL+X'200' +0000000000000200 144 PROGCHK DS 0H Program check occured... +0000000000000200 9507 F08F 000000000000008F 145 CLI PCINTCD+1,X'07' Data Exception? +0000000000000204 A774 0004 000000000000020C 146 JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) +0000000000000208 B2B2 F150 0000000000000150 147 LPSWE PCOLDPSW ..yes, resume program execution +000000000000020C 148 PCNOTDTA DS 0H +000000000000020C 12EE 149 LTR R14,R14 Return address provided? +000000000000020E 077E 150 BNZR R14 Yes, return to z/CMS test rig. +0000000000000210 B2B2 F248 0000000000000248 151 LPSWE HARDWAIT Not data exception, enter disabled wait + ASMA Ver. 0.2.0 bfp-020-multlonger.asm: Test IEEE Multiply 06 Oct 2016 10:16:49 Page 4 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 153 *********************************************************************** + 154 * + 155 * Main program. Enable Advanced Floating Point, process test cases. + 156 * + 157 *********************************************************************** + + +0000000000000214 159 START DS 0H +0000000000000214 B600 F258 0000000000000258 160 STCTL R0,R0,CTLR0 Store CR0 to enable AFP +0000000000000218 9604 F259 0000000000000259 161 OI CTLR0+1,X'04' Turn on AFP bit +000000000000021C B700 F258 0000000000000258 162 LCTL R0,R0,CTLR0 Reload updated CR0 + 163 * +0000000000000220 41A0 F300 0000000000000300 164 LA R10,SHORTNF Point to short BFP non-finite inputs +0000000000000224 4DD0 F320 0000000000000320 165 BAS R13,SBFPNF Multiply short BFP non-finites + 166 * +0000000000000228 41A0 F310 0000000000000310 167 LA R10,LONGNF Point to long BFP non-finite inputs +000000000000022C 4DD0 F3A6 00000000000003A6 168 BAS R13,LBFPNF Multiply long BFP non-finites + 169 * +0000000000000230 12EE 170 LTR R14,R14 Return address provided? +0000000000000232 077E 171 BNZR R14 ..Yes, return to z/CMS test rig. +0000000000000234 B2B2 F238 0000000000000238 172 LPSWE WAITPSW All done + 173 * +0000000000000238 174 DS 0D Ensure correct alignment for psw +0000000000000238 00020000 00000000 175 WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +0000000000000248 00020000 00000000 176 HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end + 177 * +0000000000000258 00000000 178 CTLR0 DS F +000000000000025C 00000000 179 FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +0000000000000260 F8000000 180 FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags + 181 * + 182 * Input values parameter list, four fullwords for each test data set + 183 * 1) Count, + 184 * 2) Address of inputs, + 185 * 3) Address to place results, and + 186 * 4) Address to place DXC/Flags/cc values. + 187 * +0000000000000264 0000000000000264 0000000000000300 188 ORG STRTLABL+X'300' Enable run-time replacement +0000000000000300 189 SHORTNF DS 0F Input pairs for short BFP non-finite tests +0000000000000300 00000008 190 DC A(SBFPNFCT) +0000000000000304 0000043C 191 DC A(SBFPNFIN) +0000000000000308 00001000 192 DC A(LBFPNFOT) +000000000000030C 00001800 193 DC A(LBFPNFFL) + 194 * +0000000000000310 195 LONGNF DS 0F Input pairs for long BFP non-finite testing +0000000000000310 00000008 196 DC A(LBFPNFCT) +0000000000000314 0000045C 197 DC A(LBFPNFIN) +0000000000000318 00002000 198 DC A(XBFPNFOT) +000000000000031C 00003000 199 DC A(XBFPNFFL) + 200 * + ASMA Ver. 0.2.0 bfp-020-multlonger.asm: Test IEEE Multiply 06 Oct 2016 10:16:49 Page 5 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 202 *********************************************************************** + 203 * + 204 * Perform Multiply using provided short BFP inputs. This set of tests + 205 * checks NaN propagation, operations on values that are not finite + 206 * numbers, and other basic tests. This set generates results that can + 207 * be validated against Figure 19-13 on page 19-16 of SA22-7832-10. + 208 * + 209 * That Figure has separate rows and colums for Normal and Tiny + 210 * operands. Although the results are effectively the same for Normal + 211 * and Tiny in any combination, the input data includes Normal and + 212 * Tiny values. + 213 * + 214 * Four results are generated for each input: one RRE with all + 215 * exceptions non-trappable, a second RRE with all exceptions trappable, + 216 * a third RXE with all exceptions non-trappable, a fourth RXE with all + 217 * exceptions trappable, + 218 * + 219 * The difference, FPCR, and condition code are stored for each result. + 220 * + 221 *********************************************************************** + + +0000000000000320 223 SBFPNF DS 0H BFP Short non-finite values tests +0000000000000320 9823 A000 0000000000000000 224 LM R2,R3,0(R10) Get count and addr of multiplicand values +0000000000000324 9878 A008 0000000000000008 225 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000328 1222 226 LTR R2,R2 Any test cases? +000000000000032A 078D 227 BZR R13 ..No, return to caller +000000000000032C 0DC0 228 BASR R12,0 Set top of loop + 229 * +000000000000032E 9845 A000 0000000000000000 230 LM R4,R5,0(R10) Get count and start of multiplier values + 231 * ..which are the same as the multiplicands +0000000000000332 0D60 232 BASR R6,0 Set top of inner loop + 233 * +0000000000000334 7880 3000 0000000000000000 234 LE FPR8,0(,R3) Get short BFP multiplicand +0000000000000338 7810 5000 0000000000000000 235 LE FPR1,0(,R5) Get short BFP multiplier +000000000000033C B29D F25C 000000000000025C 236 LFPC FPCREGNT Set exceptions non-trappable +0000000000000340 B30C 0081 237 MDEBR FPR8,FPR1 Multiply short FPR8 by FPR1 RRE +0000000000000344 6080 7000 0000000000000000 238 STD FPR8,0(,R7) Store long BFP product +0000000000000348 B29C 8000 0000000000000000 239 STFPC 0(R8) Store resulting FPCR flags and DXC + 240 * +000000000000034C 7880 3000 0000000000000000 241 LE FPR8,0(,R3) Get short BFP multiplicand +0000000000000350 7810 5000 0000000000000000 242 LE FPR1,0(,R5) Get short BFP multiplier +0000000000000354 B29D F260 0000000000000260 243 LFPC FPCREGTR Set exceptions trappable +0000000000000358 B30C 0081 244 MDEBR FPR8,FPR1 Multiply short FPR8 by FPR1 RRE +000000000000035C 6080 7008 0000000000000008 245 STD FPR8,8(,R7) Store long BFP product +0000000000000360 B29C 8004 0000000000000004 246 STFPC 4(R8) Store resulting FPCR flags and DXC + 247 * +0000000000000364 7880 3000 0000000000000000 248 LE FPR8,0(,R3) Get short BFP multiplicand +0000000000000368 B29D F25C 000000000000025C 249 LFPC FPCREGNT Set exceptions non-trappable +000000000000036C ED80 5000 000C 0000000000000000 250 MDEB FPR8,0(,R5) Multiply short FPR8 by multiplier RXE +0000000000000372 6080 7010 0000000000000010 251 STD FPR8,16(,R7) Store long BFP product +0000000000000376 B29C 8008 0000000000000008 252 STFPC 8(R8) Store resulting FPCR flags and DXC + ASMA Ver. 0.2.0 bfp-020-multlonger.asm: Test IEEE Multiply 06 Oct 2016 10:16:49 Page 6 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 253 * +000000000000037A 7880 3000 0000000000000000 254 LE FPR8,0(,R3) Get short BFP multiplicand +000000000000037E B29D F260 0000000000000260 255 LFPC FPCREGTR Set exceptions trappable +0000000000000382 ED80 5000 000C 0000000000000000 256 MDEB FPR8,0(,R5) Multiply short FPR8 by multiplier RXE +0000000000000388 6080 7018 0000000000000018 257 STD FPR8,24(,R7) Store long BFP product +000000000000038C B29C 800C 000000000000000C 258 STFPC 12(R8) Store resulting FPCR flags and DXC + 259 * +0000000000000390 4150 5004 0000000000000004 260 LA R5,4(,R5) Point to next multiplier value +0000000000000394 4170 7020 0000000000000020 261 LA R7,4*8(,R7) Point to next Multiply result area +0000000000000398 4180 8010 0000000000000010 262 LA R8,4*4(,R8) Point to next Multiply FPCR area +000000000000039C 0646 263 BCTR R4,R6 Loop through right-hand values + 264 * +000000000000039E 4130 3004 0000000000000004 265 LA R3,4(,R3) Point to next input multiplicand +00000000000003A2 062C 266 BCTR R2,R12 Loop through left-hand values +00000000000003A4 07FD 267 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-020-multlonger.asm: Test IEEE Multiply 06 Oct 2016 10:16:49 Page 7 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 269 *********************************************************************** + 270 * + 271 * Perform Multiply using provided long BFP inputs. This set of tests + 272 * checks NaN propagation, operations on values that are not finite + 273 * numbers, and other basic tests. This set generates results that can + 274 * be validated against Figure 19-13 on page 19-16 of SA22-7832-10. + 275 * + 276 * That Figure has separate rows and colums for Normal and Tiny + 277 * operands. Although the results are effectively the same for Normal + 278 * and Tiny in any combination, the input data includes Normal and + 279 * Tiny values. + 280 * + 281 * Four results are generated for each input: one RRE with all + 282 * exceptions non-trappable, a second RRE with all exceptions trappable, + 283 * a third RXE with all exceptions non-trappable, a fourth RXE with all + 284 * exceptions trappable, + 285 * + 286 * The difference, FPCR, and condition code are stored for each result. + 287 * + 288 *********************************************************************** + + +00000000000003A6 290 LBFPNF DS 0H BFP long non-finite values tests +00000000000003A6 9823 A000 0000000000000000 291 LM R2,R3,0(R10) Get count and addr of multiplicand values +00000000000003AA 9878 A008 0000000000000008 292 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000003AE 1222 293 LTR R2,R2 Any test cases? +00000000000003B0 078D 294 BZR R13 ..No, return to caller +00000000000003B2 0DC0 295 BASR R12,0 Set top of loop + 296 * +00000000000003B4 9845 A000 0000000000000000 297 LM R4,R5,0(R10) Get count and start of multiplier values + 298 * ..which are the same as the multiplicands +00000000000003B8 0D60 299 BASR R6,0 Set top of inner loop + 300 * +00000000000003BA 6880 3000 0000000000000000 301 LD FPR8,0(,R3) Get long BFP multiplicand +00000000000003BE 6810 5000 0000000000000000 302 LD FPR1,0(,R5) Get long BFP multiplier +00000000000003C2 B29D F25C 000000000000025C 303 LFPC FPCREGNT Set exceptions non-trappable +00000000000003C6 B307 0081 304 MXDBR FPR8,FPR1 Multiply long FPR8 by FPR1 RRE +00000000000003CA 6080 7000 0000000000000000 305 STD FPR8,0(,R7) Store extended BFP product part 1 +00000000000003CE 60A0 7008 0000000000000008 306 STD FPR10,8(,R7) Store extended BFP product part 2 +00000000000003D2 B29C 8000 0000000000000000 307 STFPC 0(R8) Store resulting FPCR flags and DXC + 308 * +00000000000003D6 6880 3000 0000000000000000 309 LD FPR8,0(,R3) Get long BFP multiplicand +00000000000003DA 6810 5000 0000000000000000 310 LD FPR1,0(,R5) Get long BFP multiplier +00000000000003DE B29D F260 0000000000000260 311 LFPC FPCREGTR Set exceptions trappable +00000000000003E2 B307 0081 312 MXDBR FPR8,FPR1 Multiply long multiplier from FPR8 RRE +00000000000003E6 6080 7010 0000000000000010 313 STD FPR8,16(,R7) Store extended BFP product part 1 +00000000000003EA 60A0 7018 0000000000000018 314 STD FPR10,24(,R7) Store extended BFP product part 2 +00000000000003EE B29C 8004 0000000000000004 315 STFPC 4(R8) Store resulting FPCR flags and DXC + 316 * +00000000000003F2 6880 3000 0000000000000000 317 LD FPR8,0(,R3) Get long BFP multiplicand +00000000000003F6 B29D F25C 000000000000025C 318 LFPC FPCREGNT Set exceptions non-trappable +00000000000003FA ED80 5000 0007 0000000000000000 319 MXDB FPR8,0(,R5) Multiply long FPR8 by multiplier RXE + ASMA Ver. 0.2.0 bfp-020-multlonger.asm: Test IEEE Multiply 06 Oct 2016 10:16:49 Page 8 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000400 6080 7020 0000000000000020 320 STD FPR8,32(,R7) Store extended BFP product part 1 +0000000000000404 60A0 7028 0000000000000028 321 STD FPR10,40(,R7) Store extended BFP product part 2 +0000000000000408 B29C 8008 0000000000000008 322 STFPC 8(R8) Store resulting FPCR flags and DXC + 323 * +000000000000040C 6880 3000 0000000000000000 324 LD FPR8,0(,R3) Get long BFP multiplicand +0000000000000410 B29D F260 0000000000000260 325 LFPC FPCREGTR Set exceptions trappable +0000000000000414 ED80 5000 0007 0000000000000000 326 MXDB FPR8,0(,R5) Multiply long FPR8 by multiplier RXE +000000000000041A 6080 7030 0000000000000030 327 STD FPR8,48(,R7) Store extended BFP product part 1 +000000000000041E 60A0 7038 0000000000000038 328 STD FPR10,56(,R7) Store extended BFP product part 2 +0000000000000422 B29C 800C 000000000000000C 329 STFPC 12(R8) Store resulting FPCR flags and DXC + 330 * +0000000000000426 4150 5008 0000000000000008 331 LA R5,8(,R5) Point to next multiplier value +000000000000042A 4170 7040 0000000000000040 332 LA R7,4*16(,R7) Point to next Multiply result area +000000000000042E 4180 8010 0000000000000010 333 LA R8,4*4(,R8) Point to next Multiply FPCR area +0000000000000432 0646 334 BCTR R4,R6 Loop through right-hand values + 335 * +0000000000000434 4130 3008 0000000000000008 336 LA R3,8(,R3) Point to next multiplicand value +0000000000000438 062C 337 BCTR R2,R12 Multiply until all cases tested +000000000000043A 07FD 338 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-020-multlonger.asm: Test IEEE Multiply 06 Oct 2016 10:16:49 Page 9 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 340 *********************************************************************** + 341 * + 342 * Short BFP test data for Multiply to longer precision testing. + 343 * + 344 * The test data set is used for tests of basic functionality, NaN + 345 * propagation, and results from operations involving other than finite + 346 * numbers. + 347 * + 348 * Member values chosen to validate Figure 19-13 on page 19-16 of + 349 * SA22-7832-10. Each value in this table is tested against every other + 350 * value in the table. Eight entries means 64 result sets. + 351 * + 352 * Because Multiply to longer precision cannot generate overflow nor + 353 * underflow exceptions and the result is always exact, there are no + 354 * further tests required. Any more extensive testing would be in + 355 * effect a test of Softfloat, not of the the integration of Softfloat + 356 * to Hercules. + 357 * + 358 *********************************************************************** + + +000000000000043C 360 SBFPNFIN DS 0F Inputs for short BFP non-finite tests +000000000000043C FF800000 361 DC X'FF800000' -inf +0000000000000440 C0000000 362 DC X'C0000000' -2.0 +0000000000000444 80000000 363 DC X'80000000' -0 +0000000000000448 00000000 364 DC X'00000000' +0 +000000000000044C 40000000 365 DC X'40000000' +2.0 +0000000000000450 7F800000 366 DC X'7F800000' +inf +0000000000000454 FFCB0000 367 DC X'FFCB0000' -QNaN +0000000000000458 7F8A0000 368 DC X'7F8A0000' +SNaN + 0000000000000008 0000000000000001 369 SBFPNFCT EQU (*-SBFPNFIN)/4 Count of short BFP in list + ASMA Ver. 0.2.0 bfp-020-multlonger.asm: Test IEEE Multiply 06 Oct 2016 10:16:49 Page 10 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 371 *********************************************************************** + 372 * + 373 * Long BFP test data for Multiply to longer precision testing. + 374 * + 375 * The test data set is used for tests of basic functionality, NaN + 376 * propagation, and results from operations involving other than finite + 377 * numbers. + 378 * + 379 * Member values chosen to validate Figure 19-13 on page 19-16 of + 380 * SA22-7832-10. Each value in this table is tested against every other + 381 * value in the table. Eight entries means 64 result sets. + 382 * + 383 * Because Multiply to longer precision cannot generate overflow nor + 384 * underflow exceptions and the result is always exact, there are no + 385 * further tests required. Any more extensive testing would be in + 386 * effect a test of Softfloat, not of the the integration of Softfloat + 387 * to Hercules. + 388 * + 389 *********************************************************************** + + +000000000000045C 391 LBFPNFIN DS 0F Inputs for long BFP testing +000000000000045C FFF00000 00000000 392 DC X'FFF0000000000000' -inf +0000000000000464 C0000000 00000000 393 DC X'C000000000000000' -2.0 +000000000000046C 80000000 00000000 394 DC X'8000000000000000' -0 +0000000000000474 00000000 00000000 395 DC X'0000000000000000' +0 +000000000000047C 40000000 00000000 396 DC X'4000000000000000' +2.0 +0000000000000484 7FF00000 00000000 397 DC X'7FF0000000000000' +inf +000000000000048C FFF8B000 00000000 398 DC X'FFF8B00000000000' -QNaN +0000000000000494 7FF0A000 00000000 399 DC X'7FF0A00000000000' +SNaN + 0000000000000008 0000000000000001 400 LBFPNFCT EQU (*-LBFPNFIN)/8 Count of long BFP in list + ASMA Ver. 0.2.0 bfp-020-multlonger.asm: Test IEEE Multiply 06 Oct 2016 10:16:49 Page 11 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 402 * + 403 * Locations for results + 404 * + 0000000000001000 0000000000000001 405 LBFPNFOT EQU STRTLABL+X'1000' Short non-finite BFP results + 406 * ..room for 64 tests, 64 used + 0000000000001800 0000000000000001 407 LBFPNFFL EQU STRTLABL+X'1800' FPCR flags and DXC from short BFP + 408 * ..room for 64 tests, 64 used + 409 * ..next location starts at X'1C00' + 410 * + 411 * + 0000000000002000 0000000000000001 412 XBFPNFOT EQU STRTLABL+X'2000' Long non-finite BFP results + 413 * ..room for 64 tests, 64 used + 0000000000003000 0000000000000001 414 XBFPNFFL EQU STRTLABL+X'3000' FPCR flags and DXC from long BFP + 415 * ..room for 64 tests, 64 used + 416 * ..next location starts at X'3400' + 417 * + 0000000000003400 0000000000000001 418 ENDLABL EQU STRTLABL+X'3400' + 419 PADCSECT ENDLABL + 420+ MNOTE *,'asma detected; no CSECT padding performed' +000000000000049C 421 END + ASMA Ver. 0.2.0 bfp-020-multlonger.asm: Test IEEE Multiply 06 Oct 2016 10:16:49 Page 12 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +BFPMUL2L J 000000 1180 77 +CTLR0 F 000258 4 178 160 161 162 +ENDLABL U 003400 1 418 +FPCREGNT X 00025C 4 179 236 249 303 318 +FPCREGTR X 000260 4 180 243 255 311 325 +FPR0 U 000000 1 98 +FPR1 U 000001 1 99 235 237 242 244 302 304 310 312 +FPR10 U 00000A 1 108 306 314 321 328 +FPR11 U 00000B 1 109 +FPR12 U 00000C 1 110 +FPR13 U 00000D 1 111 +FPR14 U 00000E 1 112 +FPR15 U 00000F 1 113 +FPR2 U 000002 1 100 +FPR3 U 000003 1 101 +FPR4 U 000004 1 102 +FPR5 U 000005 1 103 +FPR6 U 000006 1 104 +FPR7 U 000007 1 105 +FPR8 U 000008 1 106 234 237 238 241 244 245 248 250 251 254 256 257 301 304 305 309 312 + 313 317 319 320 324 326 327 +FPR9 U 000009 1 107 +HARDWAIT X 000248 8 176 151 +IMAGE 1 000000 1180 0 +LBFPNF H 0003A6 2 290 168 +LBFPNFCT U 000008 1 400 196 +LBFPNFFL U 001800 1 407 193 +LBFPNFIN F 00045C 4 391 400 197 +LBFPNFOT U 001000 1 405 192 +LONGNF F 000310 4 195 167 +PCINTCD H 00008E 2 128 145 +PCNOTDTA H 00020C 2 148 146 +PCOLDPSW U 000150 1 130 147 +PROGCHK H 000200 2 144 136 +R0 U 000000 1 79 160 162 +R1 U 000001 1 80 +R10 U 00000A 1 89 164 167 224 225 230 291 292 297 +R11 U 00000B 1 90 +R12 U 00000C 1 91 228 266 295 337 +R13 U 00000D 1 92 165 168 227 267 294 338 +R14 U 00000E 1 93 149 150 170 171 +R15 U 00000F 1 94 115 +R2 U 000002 1 81 224 226 266 291 293 337 +R3 U 000003 1 82 224 234 241 248 254 265 291 301 309 317 324 336 +R4 U 000004 1 83 230 263 297 334 +R5 U 000005 1 84 230 235 242 250 256 260 297 302 310 319 326 331 +R6 U 000006 1 85 232 263 299 334 +R7 U 000007 1 86 225 238 245 251 257 261 292 305 306 313 314 320 321 327 328 332 +R8 U 000008 1 87 225 239 246 252 258 262 292 307 315 322 329 333 +R9 U 000009 1 88 +SBFPNF H 000320 2 223 165 +SBFPNFCT U 000008 1 369 190 + ASMA Ver. 0.2.0 bfp-020-multlonger.asm: Test IEEE Multiply 06 Oct 2016 10:16:49 Page 13 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +SBFPNFIN F 00043C 4 360 369 191 +SHORTNF F 000300 4 189 164 +START H 000214 2 159 133 +STRTLABL U 000000 1 78 127 130 132 135 143 188 405 407 412 414 418 +WAITPSW X 000238 8 175 172 +XBFPNFFL U 003000 1 414 199 +XBFPNFOT U 002000 1 412 198 + ASMA Ver. 0.2.0 bfp-020-multlonger.asm: Test IEEE Multiply 06 Oct 2016 10:16:49 Page 14 + + MACRO DEFN REFERENCES + +PADCSECT 52 419 + ASMA Ver. 0.2.0 bfp-020-multlonger.asm: Test IEEE Multiply 06 Oct 2016 10:16:49 Page 15 + + DESC SYMBOL SIZE POS ADDR + +Entry: 0 + +Image IMAGE 1180 000-49B 000-49B + Region 1180 000-49B 000-49B + CSECT BFPMUL2L 1180 000-49B 000-49B + ASMA Ver. 0.2.0 bfp-020-multlonger.asm: Test IEEE Multiply 06 Oct 2016 10:16:49 Page 16 + + STMT FILE NAME + +1 C:\Users\srorso\Documents\GitHub\hyperion\tests\bfp-020-multlonger.asm + + +** NO ERRORS FOUND ** + +[420] MNOTE *,asma detected; no CSECT padding performed + \ No newline at end of file diff --git a/tests/bfp-020-multlonger.tst b/tests/bfp-020-multlonger.tst new file mode 100644 index 000000000..1f9ad47ca --- /dev/null +++ b/tests/bfp-020-multlonger.tst @@ -0,0 +1,1068 @@ +*Testcase bfp-020-multlonger.tst: MDEBR, MDEB, MXDBR, MXDB + +#Testcase bfp-020-multlonger.tst: Multiplication to longer format tests Multiply (4) +#..Includes only multiply to increased precision MDEBR/MDEB and MXDBR/MXDB +#..Test cases evaluate NaN propagation, NaN generation, operations +#..using non-finite values, trappable and non-trappable IEEE +#..exceptions, result scaling, and exhaustive rounding testing. +#..Excludes multiply to same precision and fused multiply. + +sysclear +archmode esame + +# +# Following suppresses logging of program checks. This test program, as part +# of its normal operation, generates 92 program check messages that have no +# value in the validation process. +# +ostailor quiet + +loadcore "$(testpath)/bfp-020-multlonger.core" + +runtest 1.0 + +ostailor null # restore messages for subsequent tests + + +# Short BFP multiply to long results +*Compare +r 1000.10 +*Want "MDEBR NF -inf/-inf" 7FF00000 00000000 7FF00000 00000000 +r 1010.10 +*Want "MDEB NF -inf/-inf" 7FF00000 00000000 7FF00000 00000000 +r 1020.10 +*Want "MDEBR NF -inf/-2.0" 7FF00000 00000000 7FF00000 00000000 +r 1030.10 +*Want "MDEB NF -inf/-2.0" 7FF00000 00000000 7FF00000 00000000 +r 1040.10 +*Want "MDEBR NF -inf/-0" 7FF80000 00000000 FF800000 00000000 +r 1050.10 +*Want "MDEB NF -inf/-0" 7FF80000 00000000 FF800000 00000000 +r 1060.10 +*Want "MDEBR NF -inf/+0" 7FF80000 00000000 FF800000 00000000 +r 1070.10 +*Want "MDEB NF -inf/+0" 7FF80000 00000000 FF800000 00000000 +r 1080.10 +*Want "MDEBR NF -inf/+2.0" FFF00000 00000000 FFF00000 00000000 +r 1090.10 +*Want "MDEB NF -inf/+2.0" FFF00000 00000000 FFF00000 00000000 +r 10A0.10 +*Want "MDEBR NF -inf/+inf" FFF00000 00000000 FFF00000 00000000 +r 10B0.10 +*Want "MDEB NF -inf/+inf" FFF00000 00000000 FFF00000 00000000 +r 10C0.10 +*Want "MDEBR NF -inf/-QNaN" FFF96000 00000000 FFF96000 00000000 +r 10D0.10 +*Want "MDEB NF -inf/-QNaN" FFF96000 00000000 FFF96000 00000000 +r 10E0.10 +*Want "MDEBR NF -inf/+SNaN" 7FF94000 00000000 FF800000 00000000 +r 10F0.10 +*Want "MDEB NF -inf/+SNaN" 7FF94000 00000000 FF800000 00000000 +r 1100.10 +*Want "MDEBR NF -2.0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 1110.10 +*Want "MDEB NF -2.0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 1120.10 +*Want "MDEBR NF -2.0/-2.0" 40100000 00000000 40100000 00000000 +r 1130.10 +*Want "MDEB NF -2.0/-2.0" 40100000 00000000 40100000 00000000 +r 1140.10 +*Want "MDEBR NF -2.0/-0" 00000000 00000000 00000000 00000000 +r 1150.10 +*Want "MDEB NF -2.0/-0" 00000000 00000000 00000000 00000000 +r 1160.10 +*Want "MDEBR NF -2.0/+0" 80000000 00000000 80000000 00000000 +r 1170.10 +*Want "MDEB NF -2.0/+0" 80000000 00000000 80000000 00000000 +r 1180.10 +*Want "MDEBR NF -2.0/+2.0" C0100000 00000000 C0100000 00000000 +r 1190.10 +*Want "MDEB NF -2.0/+2.0" C0100000 00000000 C0100000 00000000 +r 11A0.10 +*Want "MDEBR NF -2.0/+inf" FFF00000 00000000 FFF00000 00000000 +r 11B0.10 +*Want "MDEB NF -2.0/+inf" FFF00000 00000000 FFF00000 00000000 +r 11C0.10 +*Want "MDEBR NF -2.0/-QNaN" FFF96000 00000000 FFF96000 00000000 +r 11D0.10 +*Want "MDEB NF -2.0/-QNaN" FFF96000 00000000 FFF96000 00000000 +r 11E0.10 +*Want "MDEBR NF -2.0/+SNaN" 7FF94000 00000000 C0000000 00000000 +r 11F0.10 +*Want "MDEB NF -2.0/+SNaN" 7FF94000 00000000 C0000000 00000000 +r 1200.10 +*Want "MDEBR NF -0/-inf" 7FF80000 00000000 80000000 00000000 +r 1210.10 +*Want "MDEB NF -0/-inf" 7FF80000 00000000 80000000 00000000 +r 1220.10 +*Want "MDEBR NF -0/-2.0" 00000000 00000000 00000000 00000000 +r 1230.10 +*Want "MDEB NF -0/-2.0" 00000000 00000000 00000000 00000000 +r 1240.10 +*Want "MDEBR NF -0/-0" 00000000 00000000 00000000 00000000 +r 1250.10 +*Want "MDEB NF -0/-0" 00000000 00000000 00000000 00000000 +r 1260.10 +*Want "MDEBR NF -0/+0" 80000000 00000000 80000000 00000000 +r 1270.10 +*Want "MDEB NF -0/+0" 80000000 00000000 80000000 00000000 +r 1280.10 +*Want "MDEBR NF -0/+2.0" 80000000 00000000 80000000 00000000 +r 1290.10 +*Want "MDEB NF -0/+2.0" 80000000 00000000 80000000 00000000 +r 12A0.10 +*Want "MDEBR NF -0/+inf" 7FF80000 00000000 80000000 00000000 +r 12B0.10 +*Want "MDEB NF -0/+inf" 7FF80000 00000000 80000000 00000000 +r 12C0.10 +*Want "MDEBR NF -0/-QNaN" FFF96000 00000000 FFF96000 00000000 +r 12D0.10 +*Want "MDEB NF -0/-QNaN" FFF96000 00000000 FFF96000 00000000 +r 12E0.10 +*Want "MDEBR NF -0/+SNaN" 7FF94000 00000000 80000000 00000000 +r 12F0.10 +*Want "MDEB NF -0/+SNaN" 7FF94000 00000000 80000000 00000000 +r 1300.10 +*Want "MDEBR NF +0/-inf" 7FF80000 00000000 00000000 00000000 +r 1310.10 +*Want "MDEB NF +0/-inf" 7FF80000 00000000 00000000 00000000 +r 1320.10 +*Want "MDEBR NF +0/-2.0" 80000000 00000000 80000000 00000000 +r 1330.10 +*Want "MDEB NF +0/-2.0" 80000000 00000000 80000000 00000000 +r 1340.10 +*Want "MDEBR NF +0/-0" 80000000 00000000 80000000 00000000 +r 1350.10 +*Want "MDEB NF +0/-0" 80000000 00000000 80000000 00000000 +r 1360.10 +*Want "MDEBR NF +0/+0" 00000000 00000000 00000000 00000000 +r 1370.10 +*Want "MDEB NF +0/+0" 00000000 00000000 00000000 00000000 +r 1380.10 +*Want "MDEBR NF +0/+2.0" 00000000 00000000 00000000 00000000 +r 1390.10 +*Want "MDEB NF +0/+2.0" 00000000 00000000 00000000 00000000 +r 13A0.10 +*Want "MDEBR NF +0/+inf" 7FF80000 00000000 00000000 00000000 +r 13B0.10 +*Want "MDEB NF +0/+inf" 7FF80000 00000000 00000000 00000000 +r 13C0.10 +*Want "MDEBR NF +0/-QNaN" FFF96000 00000000 FFF96000 00000000 +r 13D0.10 +*Want "MDEB NF +0/-QNaN" FFF96000 00000000 FFF96000 00000000 +r 13E0.10 +*Want "MDEBR NF +0/+SNaN" 7FF94000 00000000 00000000 00000000 +r 13F0.10 +*Want "MDEB NF +0/+SNaN" 7FF94000 00000000 00000000 00000000 +r 1400.10 +*Want "MDEBR NF +2.0/-inf" FFF00000 00000000 FFF00000 00000000 +r 1410.10 +*Want "MDEB NF +2.0/-inf" FFF00000 00000000 FFF00000 00000000 +r 1420.10 +*Want "MDEBR NF +2.0/-2.0" C0100000 00000000 C0100000 00000000 +r 1430.10 +*Want "MDEB NF +2.0/-2.0" C0100000 00000000 C0100000 00000000 +r 1440.10 +*Want "MDEBR NF +2.0/-0" 80000000 00000000 80000000 00000000 +r 1450.10 +*Want "MDEB NF +2.0/-0" 80000000 00000000 80000000 00000000 +r 1460.10 +*Want "MDEBR NF +2.0/+0" 00000000 00000000 00000000 00000000 +r 1470.10 +*Want "MDEB NF +2.0/+0" 00000000 00000000 00000000 00000000 +r 1480.10 +*Want "MDEBR NF +2.0/+2.0" 40100000 00000000 40100000 00000000 +r 1490.10 +*Want "MDEB NF +2.0/+2.0" 40100000 00000000 40100000 00000000 +r 14A0.10 +*Want "MDEBR NF +2.0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 14B0.10 +*Want "MDEB NF +2.0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 14C0.10 +*Want "MDEBR NF +2.0/-QNaN" FFF96000 00000000 FFF96000 00000000 +r 14D0.10 +*Want "MDEB NF +2.0/-QNaN" FFF96000 00000000 FFF96000 00000000 +r 14E0.10 +*Want "MDEBR NF +2.0/+SNaN" 7FF94000 00000000 40000000 00000000 +r 14F0.10 +*Want "MDEB NF +2.0/+SNaN" 7FF94000 00000000 40000000 00000000 +r 1500.10 +*Want "MDEBR NF +inf/-inf" FFF00000 00000000 FFF00000 00000000 +r 1510.10 +*Want "MDEB NF +inf/-inf" FFF00000 00000000 FFF00000 00000000 +r 1520.10 +*Want "MDEBR NF +inf/-2.0" FFF00000 00000000 FFF00000 00000000 +r 1530.10 +*Want "MDEB NF +inf/-2.0" FFF00000 00000000 FFF00000 00000000 +r 1540.10 +*Want "MDEBR NF +inf/-0" 7FF80000 00000000 7F800000 00000000 +r 1550.10 +*Want "MDEB NF +inf/-0" 7FF80000 00000000 7F800000 00000000 +r 1560.10 +*Want "MDEBR NF +inf/+0" 7FF80000 00000000 7F800000 00000000 +r 1570.10 +*Want "MDEB NF +inf/+0" 7FF80000 00000000 7F800000 00000000 +r 1580.10 +*Want "MDEBR NF +inf/+2.0" 7FF00000 00000000 7FF00000 00000000 +r 1590.10 +*Want "MDEB NF +inf/+2.0" 7FF00000 00000000 7FF00000 00000000 +r 15A0.10 +*Want "MDEBR NF +inf/+inf" 7FF00000 00000000 7FF00000 00000000 +r 15B0.10 +*Want "MDEB NF +inf/+inf" 7FF00000 00000000 7FF00000 00000000 +r 15C0.10 +*Want "MDEBR NF +inf/-QNaN" FFF96000 00000000 FFF96000 00000000 +r 15D0.10 +*Want "MDEB NF +inf/-QNaN" FFF96000 00000000 FFF96000 00000000 +r 15E0.10 +*Want "MDEBR NF +inf/+SNaN" 7FF94000 00000000 7F800000 00000000 +r 15F0.10 +*Want "MDEB NF +inf/+SNaN" 7FF94000 00000000 7F800000 00000000 +r 1600.10 +*Want "MDEBR NF -QNaN/-inf" FFF96000 00000000 FFF96000 00000000 +r 1610.10 +*Want "MDEB NF -QNaN/-inf" FFF96000 00000000 FFF96000 00000000 +r 1620.10 +*Want "MDEBR NF -QNaN/-2.0" FFF96000 00000000 FFF96000 00000000 +r 1630.10 +*Want "MDEB NF -QNaN/-2.0" FFF96000 00000000 FFF96000 00000000 +r 1640.10 +*Want "MDEBR NF -QNaN/-0" FFF96000 00000000 FFF96000 00000000 +r 1650.10 +*Want "MDEB NF -QNaN/-0" FFF96000 00000000 FFF96000 00000000 +r 1660.10 +*Want "MDEBR NF -QNaN/+0" FFF96000 00000000 FFF96000 00000000 +r 1670.10 +*Want "MDEB NF -QNaN/+0" FFF96000 00000000 FFF96000 00000000 +r 1680.10 +*Want "MDEBR NF -QNaN/+2.0" FFF96000 00000000 FFF96000 00000000 +r 1690.10 +*Want "MDEB NF -QNaN/+2.0" FFF96000 00000000 FFF96000 00000000 +r 16A0.10 +*Want "MDEBR NF -QNaN/+inf" FFF96000 00000000 FFF96000 00000000 +r 16B0.10 +*Want "MDEB NF -QNaN/+inf" FFF96000 00000000 FFF96000 00000000 +r 16C0.10 +*Want "MDEBR NF -QNaN/-QNaN" FFF96000 00000000 FFF96000 00000000 +r 16D0.10 +*Want "MDEB NF -QNaN/-QNaN" FFF96000 00000000 FFF96000 00000000 +r 16E0.10 +*Want "MDEBR NF -QNaN/+SNaN" 7FF94000 00000000 FFCB0000 00000000 +r 16F0.10 +*Want "MDEB NF -QNaN/+SNaN" 7FF94000 00000000 FFCB0000 00000000 +r 1700.10 +*Want "MDEBR NF +SNaN/-inf" 7FF94000 00000000 7F8A0000 00000000 +r 1710.10 +*Want "MDEB NF +SNaN/-inf" 7FF94000 00000000 7F8A0000 00000000 +r 1720.10 +*Want "MDEBR NF +SNaN/-2.0" 7FF94000 00000000 7F8A0000 00000000 +r 1730.10 +*Want "MDEB NF +SNaN/-2.0" 7FF94000 00000000 7F8A0000 00000000 +r 1740.10 +*Want "MDEBR NF +SNaN/-0" 7FF94000 00000000 7F8A0000 00000000 +r 1750.10 +*Want "MDEB NF +SNaN/-0" 7FF94000 00000000 7F8A0000 00000000 +r 1760.10 +*Want "MDEBR NF +SNaN/+0" 7FF94000 00000000 7F8A0000 00000000 +r 1770.10 +*Want "MDEB NF +SNaN/+0" 7FF94000 00000000 7F8A0000 00000000 +r 1780.10 +*Want "MDEBR NF +SNaN/+2.0" 7FF94000 00000000 7F8A0000 00000000 +r 1790.10 +*Want "MDEB NF +SNaN/+2.0" 7FF94000 00000000 7F8A0000 00000000 +r 17A0.10 +*Want "MDEBR NF +SNaN/+inf" 7FF94000 00000000 7F8A0000 00000000 +r 17B0.10 +*Want "MDEB NF +SNaN/+inf" 7FF94000 00000000 7F8A0000 00000000 +r 17C0.10 +*Want "MDEBR NF +SNaN/-QNaN" 7FF94000 00000000 7F8A0000 00000000 +r 17D0.10 +*Want "MDEBR NF +SNaN/-QNaN" 7FF94000 00000000 7F8A0000 00000000 +r 17E0.10 +*Want "MDEBR NF +SNaN/+SNaN" 7FF94000 00000000 7F8A0000 00000000 +r 17F0.10 +*Want "MDEB NF +SNaN/+SNaN" 7FF94000 00000000 7F8A0000 00000000 + + +# Short BFP multiply to long results - FPCR contents +*Compare +r 1800.10 +*Want "MDBR NF -inf/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 1810.10 +*Want "MDB NF -inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1820.10 +*Want "MDBR NF -inf/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 1830.10 +*Want "MDB NF -inf/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 1840.10 +*Want "MDBR NF -inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1850.10 +*Want "MDB NF -inf/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 1860.10 +*Want "MDBR NF -inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 1870.10 +*Want "MDB NF -inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 1880.10 +*Want "MDBR NF -2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 1890.10 +*Want "MDB NF -2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 18A0.10 +*Want "MDBR NF -2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 18B0.10 +*Want "MDB NF -2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 18C0.10 +*Want "MDBR NF -2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 18D0.10 +*Want "MDB NF -2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 18E0.10 +*Want "MDBR NF -2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 18F0.10 +*Want "MDB NF -2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 1900.10 +*Want "MDBR NF -0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 1910.10 +*Want "MDB NF -0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1920.10 +*Want "MDBR NF -0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1930.10 +*Want "MDB NF -0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1940.10 +*Want "MDBR NF -0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1950.10 +*Want "MDB NF -0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 1960.10 +*Want "MDBR NF -0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 1970.10 +*Want "MDB NF -0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 1980.10 +*Want "MDBR NF +0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 1990.10 +*Want "MDB NF +0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 19A0.10 +*Want "MDBR NF +0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 19B0.10 +*Want "MDB NF +0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 19C0.10 +*Want "MDBR NF +0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 19D0.10 +*Want "MDB NF +0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 19E0.10 +*Want "MDBR NF +0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 19F0.10 +*Want "MDB NF +0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 1A00.10 +*Want "MDBR NF +2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 1A10.10 +*Want "MDB NF +2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1A20.10 +*Want "MDBR NF +2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1A30.10 +*Want "MDB NF +2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1A40.10 +*Want "MDBR NF +2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1A50.10 +*Want "MDB NF +2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 1A60.10 +*Want "MDBR NF +2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 1A70.10 +*Want "MDB NF +2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 1A80.10 +*Want "MDBR NF +inf/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 1A90.10 +*Want "MDB NF +inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1AA0.10 +*Want "MDBR NF +inf/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 1AB0.10 +*Want "MDB NF +inf/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 1AC0.10 +*Want "MDBR NF +inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1AD0.10 +*Want "MDB NF +inf/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 1AE0.10 +*Want "MDBR NF +inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 1AF0.10 +*Want "MDB NF +inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 1B00.10 +*Want "MDBR NF -QNaN/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 1B10.10 +*Want "MDB NF -QNaN/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1B20.10 +*Want "MDBR NF -QNaN/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1B30.10 +*Want "MDB NF -QNaN/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1B40.10 +*Want "MDBR NF -QNaN/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 1B50.10 +*Want "MDB NF -QNaN/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 1B60.10 +*Want "MDBR NF -QNaN/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 1B70.10 +*Want "MDB NF -QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 1B80.10 +*Want "MDBR NF +SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 1B90.10 +*Want "MDB NF +SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 1BA0.10 +*Want "MDBR NF +SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 1BB0.10 +*Want "MDB NF +SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 1BC0.10 +*Want "MDBR NF +SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 1BD0.10 +*Want "MDB NF +SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 1BE0.10 +*Want "MDBR NF +SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 1BF0.10 +*Want "MDB NF +SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 + + +# Long BFP multiply to extended results +*Compare +r 2000.10 +*Want "MXDBR NF -inf/-inf NT" 7FFF0000 00000000 00000000 00000000 +r 2010.10 +*Want "MXDBR NF -inf/-inf Tr" 7FFF0000 00000000 00000000 00000000 +r 2020.10 +*Want "MXDB NF -inf/-inf NT" 7FFF0000 00000000 00000000 00000000 +r 2030.10 +*Want "MXDB NF -inf/-inf Tr" 7FFF0000 00000000 00000000 00000000 +r 2040.10 +*Want "MXDBR NF -inf/-2.0 NT" 7FFF0000 00000000 00000000 00000000 +r 2050.10 +*Want "MXDBR NF -inf/-2.0 Tr" 7FFF0000 00000000 00000000 00000000 +r 2060.10 +*Want "MXDB NF -inf/-2.0 NT" 7FFF0000 00000000 00000000 00000000 +r 2070.10 +*Want "MXDB NF -inf/-2.0 Tr" 7FFF0000 00000000 00000000 00000000 +r 2080.10 +*Want "MXDBR NF -inf/-0 NT" 7FFF8000 00000000 00000000 00000000 +r 2090.10 +*Want "MXDBR NF -inf/-0 Tr" FFF00000 00000000 00000000 00000000 +r 20A0.10 +*Want "MXDB NF -inf/-0 NT" 7FFF8000 00000000 00000000 00000000 +r 20B0.10 +*Want "MXDB NF -inf/-0 Tr" FFF00000 00000000 00000000 00000000 +r 20C0.10 +*Want "MXDBR NF -inf/+0 NT" 7FFF8000 00000000 00000000 00000000 +r 20D0.10 +*Want "MXDBR NF -inf/+0 Tr" FFF00000 00000000 00000000 00000000 +r 20E0.10 +*Want "MXDB NF -inf/+0 NT" 7FFF8000 00000000 00000000 00000000 +r 20F0.10 +*Want "MXDB NF -inf/+0 Tr" FFF00000 00000000 00000000 00000000 +r 2100.10 +*Want "MXDBR NF -inf/+2.0 NT" FFFF0000 00000000 00000000 00000000 +r 2110.10 +*Want "MXDBR NF -inf/+2.0 Tr" FFFF0000 00000000 00000000 00000000 +r 2120.10 +*Want "MXDB NF -inf/+2.0 NT" FFFF0000 00000000 00000000 00000000 +r 2130.10 +*Want "MXDB NF -inf/+2.0 Tr" FFFF0000 00000000 00000000 00000000 +r 2140.10 +*Want "MXDBR NF -inf/+inf NT" FFFF0000 00000000 00000000 00000000 +r 2150.10 +*Want "MXDBR NF -inf/+inf Tr" FFFF0000 00000000 00000000 00000000 +r 2160.10 +*Want "MXDB NF -inf/+inf NT" FFFF0000 00000000 00000000 00000000 +r 2170.10 +*Want "MXDB NF -inf/+inf Tr" FFFF0000 00000000 00000000 00000000 +r 2180.10 +*Want "MXDBR NF -inf/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 2190.10 +*Want "MXDBR NF -inf/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 21A0.10 +*Want "MXDB NF -inf/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 21B0.10 +*Want "MXDB NF -inf/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 21C0.10 +*Want "MXDBR NF -inf/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 21D0.10 +*Want "MXDBR NF -inf/+SNaN Tr" FFF00000 00000000 00000000 00000000 +r 21E0.10 +*Want "MXDB NF -inf/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 21F0.10 +*Want "MXDB NF -inf/+SNaN Tr" FFF00000 00000000 00000000 00000000 +r 2200.10 +*Want "MXDBR NF -2.0/-inf NT" 7FFF0000 00000000 00000000 00000000 +r 2210.10 +*Want "MXDBR NF -2.0/-inf Tr" 7FFF0000 00000000 00000000 00000000 +r 2220.10 +*Want "MXDB NF -2.0/-inf NT" 7FFF0000 00000000 00000000 00000000 +r 2230.10 +*Want "MXDB NF -2.0/-inf Tr" 7FFF0000 00000000 00000000 00000000 +r 2240.10 +*Want "MXDBR NF -2.0/-2.0 NT" 40010000 00000000 00000000 00000000 +r 2250.10 +*Want "MXDBR NF -2.0/-2.0 Tr" 40010000 00000000 00000000 00000000 +r 2260.10 +*Want "MXDB NF -2.0/-2.0 NT" 40010000 00000000 00000000 00000000 +r 2270.10 +*Want "MXDB NF -2.0/-2.0 Tr" 40010000 00000000 00000000 00000000 +r 2280.10 +*Want "MXDBR NF -2.0/-0 NT" 00000000 00000000 00000000 00000000 +r 2290.10 +*Want "MXDBR NF -2.0/-0 Tr" 00000000 00000000 00000000 00000000 +r 22A0.10 +*Want "MXDB NF -2.0/-0 NT" 00000000 00000000 00000000 00000000 +r 22B0.10 +*Want "MXDB NF -2.0/-0 Tr" 00000000 00000000 00000000 00000000 +r 22C0.10 +*Want "MXDBR NF -2.0/+0 NT" 80000000 00000000 00000000 00000000 +r 22D0.10 +*Want "MXDBR NF -2.0/+0 Tr" 80000000 00000000 00000000 00000000 +r 22E0.10 +*Want "MXDB NF -2.0/+0 NT" 80000000 00000000 00000000 00000000 +r 22F0.10 +*Want "MXDB NF -2.0/+0 Tr" 80000000 00000000 00000000 00000000 +r 2300.10 +*Want "MXDBR NF -2.0/+2.0 NT" C0010000 00000000 00000000 00000000 +r 2310.10 +*Want "MXDBR NF -2.0/+2.0 Tr" C0010000 00000000 00000000 00000000 +r 2320.10 +*Want "MXDB NF -2.0/+2.0 NT" C0010000 00000000 00000000 00000000 +r 2330.10 +*Want "MXDB NF -2.0/+2.0 Tr" C0010000 00000000 00000000 00000000 +r 2340.10 +*Want "MXDBR NF -2.0/+inf NT" FFFF0000 00000000 00000000 00000000 +r 2350.10 +*Want "MXDBR NF -2.0/+inf Tr" FFFF0000 00000000 00000000 00000000 +r 2360.10 +*Want "MXDB NF -2.0/+inf NT" FFFF0000 00000000 00000000 00000000 +r 2370.10 +*Want "MXDB NF -2.0/+inf Tr" FFFF0000 00000000 00000000 00000000 +r 2380.10 +*Want "MXDBR NF -2.0/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 2390.10 +*Want "MXDBR NF -2.0/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 23A0.10 +*Want "MXDB NF -2.0/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 23B0.10 +*Want "MXDB NF -2.0/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 23C0.10 +*Want "MXDBR NF -2.0/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 23D0.10 +*Want "MXDBR NF -2.0/+SNaN Tr" C0000000 00000000 00000000 00000000 +r 23E0.10 +*Want "MXDB NF -2.0/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 23F0.10 +*Want "MXDB NF -2.0/+SNaN Tr" C0000000 00000000 00000000 00000000 +r 2400.10 +*Want "MXDBR NF -0/-inf NT" 7FFF8000 00000000 00000000 00000000 +r 2410.10 +*Want "MXDBR NF -0/-inf Tr" 80000000 00000000 00000000 00000000 +r 2420.10 +*Want "MXDB NF -0/-inf NT" 7FFF8000 00000000 00000000 00000000 +r 2430.10 +*Want "MXDB NF -0/-inf Tr" 80000000 00000000 00000000 00000000 +r 2440.10 +*Want "MXDBR NF -0/-2.0 NT" 00000000 00000000 00000000 00000000 +r 2450.10 +*Want "MXDBR NF -0/-2.0 Tr" 00000000 00000000 00000000 00000000 +r 2460.10 +*Want "MXDB NF -0/-2.0 NT" 00000000 00000000 00000000 00000000 +r 2470.10 +*Want "MXDB NF -0/-2.0 Tr" 00000000 00000000 00000000 00000000 +r 2480.10 +*Want "MXDBR NF -0/-0 NT" 00000000 00000000 00000000 00000000 +r 2490.10 +*Want "MXDBR NF -0/-0 Tr" 00000000 00000000 00000000 00000000 +r 24A0.10 +*Want "MXDB NF -0/-0 NT" 00000000 00000000 00000000 00000000 +r 24B0.10 +*Want "MXDB NF -0/-0 Tr" 00000000 00000000 00000000 00000000 +r 24C0.10 +*Want "MXDBR NF -0/+0 NT" 80000000 00000000 00000000 00000000 +r 24D0.10 +*Want "MXDBR NF -0/+0 Tr" 80000000 00000000 00000000 00000000 +r 24E0.10 +*Want "MXDB NF -0/+0 NT" 80000000 00000000 00000000 00000000 +r 24F0.10 +*Want "MXDB NF -0/+0 Tr" 80000000 00000000 00000000 00000000 +r 2500.10 +*Want "MXDBR NF -0/+2.0 NT" 80000000 00000000 00000000 00000000 +r 2510.10 +*Want "MXDBR NF -0/+2.0 Tr" 80000000 00000000 00000000 00000000 +r 2520.10 +*Want "MXDB NF -0/+2.0 NT" 80000000 00000000 00000000 00000000 +r 2530.10 +*Want "MXDB NF -0/+2.0 Tr" 80000000 00000000 00000000 00000000 +r 2540.10 +*Want "MXDBR NF -0/+inf NT" 7FFF8000 00000000 00000000 00000000 +r 2550.10 +*Want "MXDBR NF -0/+inf Tr" 80000000 00000000 00000000 00000000 +r 2560.10 +*Want "MXDB NF -0/+inf NT" 7FFF8000 00000000 00000000 00000000 +r 2570.10 +*Want "MXDB NF -0/+inf Tr" 80000000 00000000 00000000 00000000 +r 2580.10 +*Want "MXDBR NF -0/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 2590.10 +*Want "MXDBR NF -0/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 25A0.10 +*Want "MXDB NF -0/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 25B0.10 +*Want "MXDB NF -0/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 25C0.10 +*Want "MXDBR NF -0/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 25D0.10 +*Want "MXDBR NF -0/+SNaN Tr" 80000000 00000000 00000000 00000000 +r 25E0.10 +*Want "MXDB NF -0/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 25F0.10 +*Want "MXDB NF -0/+SNaN Tr" 80000000 00000000 00000000 00000000 +r 2600.10 +*Want "MXDBR NF +0/-inf NT" 7FFF8000 00000000 00000000 00000000 +r 2610.10 +*Want "MXDBR NF +0/-inf Tr" 00000000 00000000 00000000 00000000 +r 2620.10 +*Want "MXDB NF +0/-inf NT" 7FFF8000 00000000 00000000 00000000 +r 2630.10 +*Want "MXDB NF +0/-inf Tr" 00000000 00000000 00000000 00000000 +r 2640.10 +*Want "MXDBR NF +0/-2.0 NT" 80000000 00000000 00000000 00000000 +r 2650.10 +*Want "MXDBR NF +0/-2.0 Tr" 80000000 00000000 00000000 00000000 +r 2660.10 +*Want "MXDB NF +0/-2.0 NT" 80000000 00000000 00000000 00000000 +r 2670.10 +*Want "MXDB NF +0/-2.0 Tr" 80000000 00000000 00000000 00000000 +r 2680.10 +*Want "MXDBR NF +0/-0 NT" 80000000 00000000 00000000 00000000 +r 2690.10 +*Want "MXDBR NF +0/-0 Tr" 80000000 00000000 00000000 00000000 +r 26A0.10 +*Want "MXDB NF +0/-0 NT" 80000000 00000000 00000000 00000000 +r 26B0.10 +*Want "MXDB NF +0/-0 Tr" 80000000 00000000 00000000 00000000 +r 26C0.10 +*Want "MXDBR NF +0/+0 NT" 00000000 00000000 00000000 00000000 +r 26D0.10 +*Want "MXDBR NF +0/+0 Tr" 00000000 00000000 00000000 00000000 +r 26E0.10 +*Want "MXDB NF +0/+0 NT" 00000000 00000000 00000000 00000000 +r 26F0.10 +*Want "MXDB NF +0/+0 Tr" 00000000 00000000 00000000 00000000 +r 2700.10 +*Want "MXDBR NF +0/+2.0 NT" 00000000 00000000 00000000 00000000 +r 2710.10 +*Want "MXDBR NF +0/+2.0 Tr" 00000000 00000000 00000000 00000000 +r 2720.10 +*Want "MXDB NF +0/+2.0 NT" 00000000 00000000 00000000 00000000 +r 2730.10 +*Want "MXDB NF +0/+2.0 Tr" 00000000 00000000 00000000 00000000 +r 2740.10 +*Want "MXDBR NF +0/+inf NT" 7FFF8000 00000000 00000000 00000000 +r 2750.10 +*Want "MXDBR NF +0/+inf Tr" 00000000 00000000 00000000 00000000 +r 2760.10 +*Want "MXDB NF +0/+inf NT" 7FFF8000 00000000 00000000 00000000 +r 2770.10 +*Want "MXDB NF +0/+inf Tr" 00000000 00000000 00000000 00000000 +r 2780.10 +*Want "MXDBR NF +0/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 2790.10 +*Want "MXDBR NF +0/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 27A0.10 +*Want "MXDB NF +0/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 27B0.10 +*Want "MXDB NF +0/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 27C0.10 +*Want "MXDBR NF +0/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 27D0.10 +*Want "MXDBR NF +0/+SNaN Tr" 00000000 00000000 00000000 00000000 +r 27E0.10 +*Want "MXDB NF +0/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 27F0.10 +*Want "MXDB NF +0/+SNaN Tr" 00000000 00000000 00000000 00000000 +r 2800.10 +*Want "MXDBR NF +2.0/-inf NT" FFFF0000 00000000 00000000 00000000 +r 2810.10 +*Want "MXDBR NF +2.0/-inf Tr" FFFF0000 00000000 00000000 00000000 +r 2820.10 +*Want "MXDB NF +2.0/-inf NT" FFFF0000 00000000 00000000 00000000 +r 2830.10 +*Want "MXDB NF +2.0/-inf Tr" FFFF0000 00000000 00000000 00000000 +r 2840.10 +*Want "MXDBR NF +2.0/-2.0 NT" C0010000 00000000 00000000 00000000 +r 2850.10 +*Want "MXDBR NF +2.0/-2.0 Tr" C0010000 00000000 00000000 00000000 +r 2860.10 +*Want "MXDB NF +2.0/-2.0 NT" C0010000 00000000 00000000 00000000 +r 2870.10 +*Want "MXDB NF +2.0/-2.0 Tr" C0010000 00000000 00000000 00000000 +r 2880.10 +*Want "MXDBR NF +2.0/-0 NT" 80000000 00000000 00000000 00000000 +r 2890.10 +*Want "MXDBR NF +2.0/-0 Tr" 80000000 00000000 00000000 00000000 +r 28A0.10 +*Want "MXDB NF +2.0/-0 NT" 80000000 00000000 00000000 00000000 +r 28B0.10 +*Want "MXDB NF +2.0/-0 Tr" 80000000 00000000 00000000 00000000 +r 28C0.10 +*Want "MXDBR NF +2.0/+0 NT" 00000000 00000000 00000000 00000000 +r 28D0.10 +*Want "MXDBR NF +2.0/+0 Tr" 00000000 00000000 00000000 00000000 +r 28E0.10 +*Want "MXDB NF +2.0/+0 NT" 00000000 00000000 00000000 00000000 +r 28F0.10 +*Want "MXDB NF +2.0/+0 Tr" 00000000 00000000 00000000 00000000 +r 2900.10 +*Want "MXDBR NF +2.0/+2.0 NT" 40010000 00000000 00000000 00000000 +r 2910.10 +*Want "MXDBR NF +2.0/+2.0 Tr" 40010000 00000000 00000000 00000000 +r 2920.10 +*Want "MXDB NF +2.0/+2.0 NT" 40010000 00000000 00000000 00000000 +r 2930.10 +*Want "MXDB NF +2.0/+2.0 Tr" 40010000 00000000 00000000 00000000 +r 2940.10 +*Want "MXDBR NF +2.0/+inf NT" 7FFF0000 00000000 00000000 00000000 +r 2950.10 +*Want "MXDBR NF +2.0/+inf Tr" 7FFF0000 00000000 00000000 00000000 +r 2960.10 +*Want "MXDB NF +2.0/+inf NT" 7FFF0000 00000000 00000000 00000000 +r 2970.10 +*Want "MXDB NF +2.0/+inf Tr" 7FFF0000 00000000 00000000 00000000 +r 2980.10 +*Want "MXDBR NF +2.0/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 2990.10 +*Want "MXDBR NF +2.0/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 29A0.10 +*Want "MXDB NF +2.0/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 29B0.10 +*Want "MXDB NF +2.0/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 29C0.10 +*Want "MXDBR NF +2.0/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 29D0.10 +*Want "MXDBR NF +2.0/+SNaN Tr" 40000000 00000000 00000000 00000000 +r 29E0.10 +*Want "MXDB NF +2.0/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 29F0.10 +*Want "MXDB NF +2.0/+SNaN Tr" 40000000 00000000 00000000 00000000 +r 2A00.10 +*Want "MXDBR NF +inf/-inf NT" FFFF0000 00000000 00000000 00000000 +r 2A10.10 +*Want "MXDBR NF +inf/-inf Tr" FFFF0000 00000000 00000000 00000000 +r 2A20.10 +*Want "MXDB NF +inf/-inf NT" FFFF0000 00000000 00000000 00000000 +r 2A30.10 +*Want "MXDB NF +inf/-inf Tr" FFFF0000 00000000 00000000 00000000 +r 2A40.10 +*Want "MXDBR NF +inf/-2.0 NT" FFFF0000 00000000 00000000 00000000 +r 2A50.10 +*Want "MXDBR NF +inf/-2.0 Tr" FFFF0000 00000000 00000000 00000000 +r 2A60.10 +*Want "MXDB NF +inf/-2.0 NT" FFFF0000 00000000 00000000 00000000 +r 2A70.10 +*Want "MXDB NF +inf/-2.0 Tr" FFFF0000 00000000 00000000 00000000 +r 2A80.10 +*Want "MXDBR NF +inf/-0 NT" 7FFF8000 00000000 00000000 00000000 +r 2A90.10 +*Want "MXDBR NF +inf/-0 Tr" 7FF00000 00000000 00000000 00000000 +r 2AA0.10 +*Want "MXDB NF +inf/-0 NT" 7FFF8000 00000000 00000000 00000000 +r 2AB0.10 +*Want "MXDB NF +inf/-0 Tr" 7FF00000 00000000 00000000 00000000 +r 2AC0.10 +*Want "MXDBR NF +inf/+0 NT" 7FFF8000 00000000 00000000 00000000 +r 2AD0.10 +*Want "MXDBR NF +inf/+0 Tr" 7FF00000 00000000 00000000 00000000 +r 2AE0.10 +*Want "MXDB NF +inf/+0 NT" 7FFF8000 00000000 00000000 00000000 +r 2AF0.10 +*Want "MXDB NF +inf/+0 Tr" 7FF00000 00000000 00000000 00000000 +r 2B00.10 +*Want "MXDBR NF +inf/+2.0 NT" 7FFF0000 00000000 00000000 00000000 +r 2B10.10 +*Want "MXDBR NF +inf/+2.0 Tr" 7FFF0000 00000000 00000000 00000000 +r 2B20.10 +*Want "MXDB NF +inf/+2.0 NT" 7FFF0000 00000000 00000000 00000000 +r 2B30.10 +*Want "MXDB NF +inf/+2.0 Tr" 7FFF0000 00000000 00000000 00000000 +r 2B40.10 +*Want "MXDBR NF +inf/+inf NT" 7FFF0000 00000000 00000000 00000000 +r 2B50.10 +*Want "MXDBR NF +inf/+inf Tr" 7FFF0000 00000000 00000000 00000000 +r 2B60.10 +*Want "MXDB NF +inf/+inf NT" 7FFF0000 00000000 00000000 00000000 +r 2B70.10 +*Want "MXDB NF +inf/+inf Tr" 7FFF0000 00000000 00000000 00000000 +r 2B80.10 +*Want "MXDBR NF +inf/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 2B90.10 +*Want "MXDBR NF +inf/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 2BA0.10 +*Want "MXDB NF +inf/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 2BB0.10 +*Want "MXDB NF +inf/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 2BC0.10 +*Want "MXDBR NF +inf/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 2BD0.10 +*Want "MXDBR NF +inf/+SNaN Tr" 7FF00000 00000000 00000000 00000000 +r 2BE0.10 +*Want "MXDB NF +inf/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 2BF0.10 +*Want "MXDB NF +inf/+SNaN Tr" 7FF00000 00000000 00000000 00000000 +r 2C00.10 +*Want "MXDBR NF -QNaN/-inf NT" FFFF8B00 00000000 00000000 00000000 +r 2C10.10 +*Want "MXDBR NF -QNaN/-inf Tr" FFFF8B00 00000000 00000000 00000000 +r 2C20.10 +*Want "MXDB NF -QNaN/-inf NT" FFFF8B00 00000000 00000000 00000000 +r 2C30.10 +*Want "MXDB NF -QNaN/-inf Tr" FFFF8B00 00000000 00000000 00000000 +r 2C40.10 +*Want "MXDBR NF -QNaN/-2.0 NT" FFFF8B00 00000000 00000000 00000000 +r 2C50.10 +*Want "MXDBR NF -QNaN/-2.0 Tr" FFFF8B00 00000000 00000000 00000000 +r 2C60.10 +*Want "MXDB NF -QNaN/-2.0 NT" FFFF8B00 00000000 00000000 00000000 +r 2C70.10 +*Want "MXDB NF -QNaN/-2.0 Tr" FFFF8B00 00000000 00000000 00000000 +r 2C80.10 +*Want "MXDBR NF -QNaN/-0 NT" FFFF8B00 00000000 00000000 00000000 +r 2C90.10 +*Want "MXDBR NF -QNaN/-0 Tr" FFFF8B00 00000000 00000000 00000000 +r 2CA0.10 +*Want "MXDB NF -QNaN/-0 NT" FFFF8B00 00000000 00000000 00000000 +r 2CB0.10 +*Want "MXDB NF -QNaN/-0 Tr" FFFF8B00 00000000 00000000 00000000 +r 2CC0.10 +*Want "MXDBR NF -QNaN/+0 NT" FFFF8B00 00000000 00000000 00000000 +r 2CD0.10 +*Want "MXDBR NF -QNaN/+0 Tr" FFFF8B00 00000000 00000000 00000000 +r 2CE0.10 +*Want "MXDB NF -QNaN/+0 NT" FFFF8B00 00000000 00000000 00000000 +r 2CF0.10 +*Want "MXDB NF -QNaN/+0 Tr" FFFF8B00 00000000 00000000 00000000 +r 2D00.10 +*Want "MXDBR NF -QNaN/+2.0 NT" FFFF8B00 00000000 00000000 00000000 +r 2D10.10 +*Want "MXDBR NF -QNaN/+2.0 Tr" FFFF8B00 00000000 00000000 00000000 +r 2D20.10 +*Want "MXDB NF -QNaN/+2.0 NT" FFFF8B00 00000000 00000000 00000000 +r 2D30.10 +*Want "MXDB NF -QNaN/+2.0 Tr" FFFF8B00 00000000 00000000 00000000 +r 2D40.10 +*Want "MXDBR NF -QNaN/+inf NT" FFFF8B00 00000000 00000000 00000000 +r 2D50.10 +*Want "MXDBR NF -QNaN/+inf Tr" FFFF8B00 00000000 00000000 00000000 +r 2D60.10 +*Want "MXDB NF -QNaN/+inf NT" FFFF8B00 00000000 00000000 00000000 +r 2D70.10 +*Want "MXDB NF -QNaN/+inf Tr" FFFF8B00 00000000 00000000 00000000 +r 2D80.10 +*Want "MXDBR NF -QNaN/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 2D90.10 +*Want "MXDBR NF -QNaN/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 2DA0.10 +*Want "MXDB NF -QNaN/-QNaN NT" FFFF8B00 00000000 00000000 00000000 +r 2DB0.10 +*Want "MXDB NF -QNaN/-QNaN Tr" FFFF8B00 00000000 00000000 00000000 +r 2DC0.10 +*Want "MXDBR NF -QNaN/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 2DD0.10 +*Want "MXDBR NF -QNaN/+SNaN Tr" FFF8B000 00000000 00000000 00000000 +r 2DE0.10 +*Want "MXDB NF -QNaN/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 2DF0.10 +*Want "MXDB NF -QNaN/+SNaN Tr" FFF8B000 00000000 00000000 00000000 +r 2E00.10 +*Want "MXDBR NF +SNaN/-inf NT" 7FFF8A00 00000000 00000000 00000000 +r 2E10.10 +*Want "MXDBR NF +SNaN/-inf Tr" 7FF0A000 00000000 00000000 00000000 +r 2E20.10 +*Want "MXDB NF +SNaN/-inf NT" 7FFF8A00 00000000 00000000 00000000 +r 2E30.10 +*Want "MXDB NF +SNaN/-inf Tr" 7FF0A000 00000000 00000000 00000000 +r 2E40.10 +*Want "MXDBR NF +SNaN/-2.0 NT" 7FFF8A00 00000000 00000000 00000000 +r 2E50.10 +*Want "MXDBR NF +SNaN/-2.0 Tr" 7FF0A000 00000000 00000000 00000000 +r 2E60.10 +*Want "MXDB NF +SNaN/-2.0 NT" 7FFF8A00 00000000 00000000 00000000 +r 2E70.10 +*Want "MXDB NF +SNaN/-2.0 Tr" 7FF0A000 00000000 00000000 00000000 +r 2E80.10 +*Want "MXDBR NF +SNaN/-0 NT" 7FFF8A00 00000000 00000000 00000000 +r 2E90.10 +*Want "MXDBR NF +SNaN/-0 Tr" 7FF0A000 00000000 00000000 00000000 +r 2EA0.10 +*Want "MXDB NF +SNaN/-0 NT" 7FFF8A00 00000000 00000000 00000000 +r 2EB0.10 +*Want "MXDB NF +SNaN/-0 Tr" 7FF0A000 00000000 00000000 00000000 +r 2EC0.10 +*Want "MXDBR NF +SNaN/+0 NT" 7FFF8A00 00000000 00000000 00000000 +r 2ED0.10 +*Want "MXDBR NF +SNaN/+0 Tr" 7FF0A000 00000000 00000000 00000000 +r 2EE0.10 +*Want "MXDB NF +SNaN/+0 NT" 7FFF8A00 00000000 00000000 00000000 +r 2EF0.10 +*Want "MXDB NF +SNaN/+0 Tr" 7FF0A000 00000000 00000000 00000000 +r 2F00.10 +*Want "MXDBR NF +SNaN/+2.0 NT" 7FFF8A00 00000000 00000000 00000000 +r 2F10.10 +*Want "MXDBR NF +SNaN/+2.0 Tr" 7FF0A000 00000000 00000000 00000000 +r 2F20.10 +*Want "MXDB NF +SNaN/+2.0 NT" 7FFF8A00 00000000 00000000 00000000 +r 2F30.10 +*Want "MXDB NF +SNaN/+2.0 Tr" 7FF0A000 00000000 00000000 00000000 +r 2F40.10 +*Want "MXDBR NF +SNaN/+inf NT" 7FFF8A00 00000000 00000000 00000000 +r 2F50.10 +*Want "MXDBR NF +SNaN/+inf Tr" 7FF0A000 00000000 00000000 00000000 +r 2F60.10 +*Want "MXDB NF +SNaN/+inf NT" 7FFF8A00 00000000 00000000 00000000 +r 2F70.10 +*Want "MXDB NF +SNaN/+inf Tr" 7FF0A000 00000000 00000000 00000000 +r 2F80.10 +*Want "MXDBR NF +SNaN/-QNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 2F90.10 +*Want "MXDBR NF +SNaN/-QNaN Tr" 7FF0A000 00000000 00000000 00000000 +r 2FA0.10 +*Want "MXDB NF +SNaN/-QNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 2FB0.10 +*Want "MXDB NF +SNaN/-QNaN Tr" 7FF0A000 00000000 00000000 00000000 +r 2FC0.10 +*Want "MXDBR NF +SNaN/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 2FD0.10 +*Want "MXDBR NF +SNaN/+SNaN Tr" 7FF0A000 00000000 00000000 00000000 +r 2FE0.10 +*Want "MXDB NF +SNaN/+SNaN NT" 7FFF8A00 00000000 00000000 00000000 +r 2FF0.10 +*Want "MXDB NF +SNaN/+SNaN Tr" 7FF0A000 00000000 00000000 00000000 + + +# Long BFP multiply to extended results - FPCR contents +*Compare +r 3000.10 +*Want "MXBR NF -inf/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3010.10 +*Want "MXBR NF -inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3020.10 +*Want "MXBR NF -inf/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3030.10 +*Want "MXBR NF -inf/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3040.10 +*Want "MXBR NF -inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3050.10 +*Want "MXBR NF -inf/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3060.10 +*Want "MXBR NF -inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3070.10 +*Want "MXBR NF -inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3080.10 +*Want "MXBR NF -2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3090.10 +*Want "MXBR NF -2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 30A0.10 +*Want "MXBR NF -2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 30B0.10 +*Want "MXBR NF -2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 30C0.10 +*Want "MXBR NF -2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 30D0.10 +*Want "MXBR NF -2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 30E0.10 +*Want "MXBR NF -2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 30F0.10 +*Want "MXBR NF -2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3100.10 +*Want "MXBR NF -0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3110.10 +*Want "MXBR NF -0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3120.10 +*Want "MXBR NF -0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3130.10 +*Want "MXBR NF -0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3140.10 +*Want "MXBR NF -0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3150.10 +*Want "MXBR NF -0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3160.10 +*Want "MXBR NF -0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3170.10 +*Want "MXBR NF -0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3180.10 +*Want "MXBR NF +0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3190.10 +*Want "MXBR NF +0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 31A0.10 +*Want "MXBR NF +0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 31B0.10 +*Want "MXBR NF +0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 31C0.10 +*Want "MXBR NF +0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 31D0.10 +*Want "MXBR NF +0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 31E0.10 +*Want "MXBR NF +0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 31F0.10 +*Want "MXBR NF +0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3200.10 +*Want "MXBR NF +2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3210.10 +*Want "MXBR NF +2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3220.10 +*Want "MXBR NF +2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3230.10 +*Want "MXBR NF +2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3240.10 +*Want "MXBR NF +2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3250.10 +*Want "MXBR NF +2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3260.10 +*Want "MXBR NF +2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3270.10 +*Want "MXBR NF +2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3280.10 +*Want "MXBR NF +inf/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3290.10 +*Want "MXBR NF +inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 32A0.10 +*Want "MXBR NF +inf/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 32B0.10 +*Want "MXBR NF +inf/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 32C0.10 +*Want "MXBR NF +inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 32D0.10 +*Want "MXBR NF +inf/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 32E0.10 +*Want "MXBR NF +inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 32F0.10 +*Want "MXBR NF +inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3300.10 +*Want "MXBR NF -QNaN/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3310.10 +*Want "MXBR NF -QNaN/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3320.10 +*Want "MXBR NF -QNaN/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3330.10 +*Want "MXBR NF -QNaN/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3340.10 +*Want "MXBR NF -QNaN/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3350.10 +*Want "MXBR NF -QNaN/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3360.10 +*Want "MXBR NF -QNaN/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3370.10 +*Want "MXBR NF -QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3380.10 +*Want "MXBR NF +SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3390.10 +*Want "MXBR NF +SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 33A0.10 +*Want "MXBR NF +SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 33B0.10 +*Want "MXBR NF +SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 33C0.10 +*Want "MXBR NF +SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 33D0.10 +*Want "MXBR NF +SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 33E0.10 +*Want "MXBR NF +SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 33F0.10 +*Want "MXBR NF +SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 + + +*Done + diff --git a/tests/bfp-021-multadd.asm b/tests/bfp-021-multadd.asm new file mode 100644 index 000000000..be3ea7e3d --- /dev/null +++ b/tests/bfp-021-multadd.asm @@ -0,0 +1,1114 @@ + TITLE 'bfp-021-multadd.asm: Test IEEE Multiply And Add' +*********************************************************************** +* +*Testcase IEEE MULTIPLY AND ADD +* Test case capability includes IEEE exceptions trappable and +* otherwise. Test results, FPCR flags, the Condition code, and any +* DXC are saved for all tests. +* +* This test program is focused on the four fused Multiply And Add +* instructions. Standard Multiply and Multiply to longer precision +* are tested in other programs. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* bfp-021-multadd.asm +* +* This assembly-language source file is part of the +* Hercules Decimal Floating Point Validation Package +* by Stephen R. Orso +* +* Copyright 2016 by Stephen R Orso. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* +* 3. The name of the author may not be used to endorse or promote +* products derived from this software without specific prior written +* permission. +* +* DISCLAMER: THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* HOLDER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* Tests the following three conversion instructions +* MULTIPLY AND ADD (short BFP, RRE) +* MULTIPLY AND ADD (long BFP, RRE) +* MULTIPLY AND ADD (short BFP, RXE) +* MULTIPLY AND ADD (long BFP, RXE) +* +* +* Test data is compiled into this program. The test script that runs +* this program can provide alternative test data through Hercules R +* commands. +* +* Test Case Order +* 1) Short BFP basic tests, including traps and NaN propagation +* 2) Short BFP finite number tests, including traps and scaling +* 3) Short BFP FPC-controlled rounding mode exhaustive tests +* 4) Long BFP basic tests, including traps and NaN propagation +* 5) Long BFP finite number tests, including traps and scaling +* 6) Long BFP FPC-controlled rounding mode exhaustive tests +* +* Three input test sets are provided each for short and long BFP +* inputs. Test values are the same for each precision for most +* tests. Overflow and underflow each require precision- +* dependent test values. +* +* Review of Softfloat code for multiply and add shows that the +* multiplication and addition are performed in precision-independent +* format. Overflow, underflow, inexact, and incremented are detected +* upon conversion from precision-independent format to the target +* format. As a result, it should not matter whether overflow etc is +* caused by the multiplication or the addition. We will include +* a few test cases where this differs in the finite testing section, +* but that's all. +* +* Also tests the following floating point support instructions +* LOAD (Short) +* LOAD (Long) +* LFPC (Load Floating Point Control Register) +* SRNMB (Set BFP Rounding Mode 3-bit) +* STORE (Short) +* STORE (Long) +* STFPC (Store Floating Point Control Register) +* +*********************************************************************** + SPACE 2 + MACRO + PADCSECT &ENDLABL +.* +.* Macro to pad the CSECT to include result data areas if this test +.* program is not being assembled using asma. asma generates a core +.* image that is loaded by the loadcore command, and because the +.* core image is a binary stored in Github, it makes sense to make +.* this small effort to keep the core image small. +.* + AIF (D'&ENDLABL).GOODPAD + MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + MNOTE *,'No CSECT padding performed' + MEXIT +.* +.GOODPAD ANOP Label valid. See if we're on asma + AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + ORG &ENDLABL-1 Not ASMA. Pad CSECT + MEXIT +.* +.NOPAD ANOP + MNOTE *,'asma detected; no CSECT padding performed' + MEND +* +* Note: for compatibility with the z/CMS test rig, do not change +* or use R11, R14, or R15. Everything else is fair game. +* +BFPMULA START 0 +STRTLABL EQU * +R0 EQU 0 Work register for cc extraction +R1 EQU 1 +R2 EQU 2 Holds count of test input values +R3 EQU 3 Points to next test input value(s) +R4 EQU 4 Rounding tests inner loop control +R5 EQU 5 Rounding tests outer loop control +R6 EQU 6 Rounding tests top of inner loop +R7 EQU 7 Pointer to next result value(s) +R8 EQU 8 Pointer to next FPCR result +R9 EQU 9 Rounding tests top of outer loop +R10 EQU 10 Pointer to test address list +R11 EQU 11 **Reserved for z/CMS test rig +R12 EQU 12 Holds number of test cases in set +R13 EQU 13 Mainline return address +R14 EQU 14 **Return address for z/CMS test rig +R15 EQU 15 **Base register on z/CMS or Hyperion +* +* Floating Point Register equates to keep the cross reference clean +* +FPR0 EQU 0 +FPR1 EQU 1 +FPR2 EQU 2 +FPR3 EQU 3 +FPR4 EQU 4 +FPR5 EQU 5 +FPR6 EQU 6 +FPR7 EQU 7 +FPR8 EQU 8 +FPR9 EQU 9 +FPR10 EQU 10 +FPR11 EQU 11 +FPR12 EQU 12 +FPR13 EQU 13 +FPR14 EQU 14 +FPR15 EQU 15 +* + USING *,R15 +* +* Above works on real iron (R15=0 after sysclear) +* and in z/CMS (R15 points to start of load module) +* + SPACE 2 +*********************************************************************** +* +* Low core definitions, Restart PSW, and Program Check Routine. +* +*********************************************************************** + SPACE 2 + ORG STRTLABL+X'8E' Program check interrution code +PCINTCD DS H +* +PCOLDPSW EQU STRTLABL+X'150' z/Arch Program check old PSW +* + ORG STRTLABL+X'1A0' z/Arch Restart PSW + DC X'0000000180000000',AD(START) +* + ORG STRTLABL+X'1D0' z/Arch Program check old PSW + DC X'0000000000000000',AD(PROGCHK) +* +* Program check routine. If Data Exception, continue execution at +* the instruction following the program check. Otherwise, hard wait. +* No need to collect data. All interesting DXC stuff is captured +* in the FPCR. +* + ORG STRTLABL+X'200' +PROGCHK DS 0H Program check occured... + CLI PCINTCD+1,X'07' Data Exception? + JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) + LPSWE PCOLDPSW ..yes, resume program execution +PCNOTDTA DS 0H + LTR R14,R14 Return address provided? + BNZR R14 Yes, return to z/CMS test rig. + LPSWE HARDWAIT Not data exception, enter disabled wait + EJECT +*********************************************************************** +* +* Main program. Enable Advanced Floating Point, process test cases. +* +*********************************************************************** + SPACE 2 +START DS 0H + STCTL R0,R0,CTLR0 Store CR0 to enable AFP + OI CTLR0+1,X'04' Turn on AFP bit + LCTL R0,R0,CTLR0 Reload updated CR0 +* + LA R10,SHORTNF Point to short BFP non-finite inputs + BAS R13,SBFPNF Multiply short BFP non-finites + LA R10,SHORTF Point to short BFP finite inputs + BAS R13,SBFPF Multiply short BFP finites + LA R10,RMSHORTS Point to short BFP rounding mode tests + BAS R13,SBFPRM Multiply short BFP for rounding tests +* + LA R10,LONGNF Point to long BFP non-finite inputs + BAS R13,LBFPNF Multiply long BFP non-finites + LA R10,LONGF Point to long BFP finite inputs + BAS R13,LBFPF Multiply long BFP finites + LA R10,RMLONGS Point to long BFP rounding mode tests + BAS R13,LBFPRM Multiply long BFP for rounding tests +* + LTR R14,R14 Return address provided? + BNZR R14 ..Yes, return to z/CMS test rig. + LPSWE WAITPSW All done +* + DS 0D Ensure correct alignment for psw +WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end +* +CTLR0 DS F +FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags +* +* Input values parameter list, four fullwords for each test data set +* 1) Count, +* 2) Address of inputs, +* 3) Address to place results, and +* 4) Address to place DXC/Flags/cc values. +* + ORG STRTLABL+X'300' Enable run-time replacement +SHORTNF DS 0F Input pairs for short BFP non-finite tests + DC A(SBFPNFCT) + DC A(SBFPNFIN) + DC A(SBFPNFOT) + DC A(SBFPNFFL) +* +SHORTF DS 0F Input pairs for short BFP finite tests + DC A(SBFPCT) + DC A(SBFPIN) + DC A(SBFPOUT) + DC A(SBFPFLGS) +* +RMSHORTS DS 0F Input pairs for short BFP rounding testing + DC A(SBFPRMCT) + DC A(SBFPINRM) + DC A(SBFPRMO) + DC A(SBFPRMOF) +* +LONGNF DS 0F Input pairs for long BFP non-finite testing + DC A(LBFPNFCT) + DC A(LBFPNFIN) + DC A(LBFPNFOT) + DC A(LBFPNFFL) +* +LONGF DS 0F Input pairs for long BFP finite testing + DC A(LBFPCT) + DC A(LBFPIN) + DC A(LBFPOUT) + DC A(LBFPFLGS) +* +RMLONGS DS 0F Input pairs for long BFP rounding testing + DC A(LBFPRMCT) + DC A(LBFPINRM) + DC A(LBFPRMO) + DC A(LBFPRMOF) +* + EJECT +*********************************************************************** +* +* Perform Multiply And Add using provided short BFP inputs. This set +* of tests checks NaN propagation, operations on values that are not +* finite numbers, and other basic tests. This set generates results +* that can be validated against Figure 19-24 on page 19-39 of +* SA22-7832-10. +* +* Four results are generated for each input: one RRE with all +* exceptions non-trappable, a second RRE with all exceptions trappable, +* a third RXE with all exceptions non-trappable, a fourth RXE with all +* exceptions trappable. +* +* Because this is a three-operand instruction, validation against +* Figure 19-24, effectively an 8 x 8 x 8 table, will generate a +* phenomonal set of results. Namely 512 results of 16 bytes each +* plus 512 FPCR contents of 16 bytes each. +* +* The product and FPCR are stored for each result. +* +*********************************************************************** + SPACE 2 +SBFPNF DS 0H BFP Short non-finite values tests + LM R2,R3,0(R10) Get count and addr of multiplicand values + LM R8,R9,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller +* +SBFPNFLP DS 0H Top of outer loop - Multiplicand + LM R4,R5,0(R10) Get count and start of multiplier values +* ..which are the same as the multiplicands + BASR R12,0 Set top of middle loop +* + DS 0H Top of middle loop - multiplier + LM R6,R7,0(R10) Get count and start of addend values +* ..which are the same as the multiplicands + BASR R1,0 Set top of inner loop - addend +* +* Multiply and Add: R1 = R3 x R2 + R1 +* + LE FPR4,0(,R3) Get short BFP multiplicand + LE FPR1,0(,R5) Get short BFP multiplier +* + LFPC FPCREGNT Set exceptions non-trappable + LE FPR8,0(,R7) Get short BFP addend + MAEBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE + STE FPR8,0(,R8) Store short BFP product-sum + STFPC 0(R9) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LE FPR8,0(,R7) Get short BFP addend + MAEBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE + STE FPR8,4(,R8) Store short BFP product-sum + STFPC 4(R9) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable + LE FPR8,0(,R7) Get short BFP addend + MAEB FPR8,FPR4,0(,R5) Mult. FPR4 by multiplier, add FPR8 RXE + STE FPR8,8(,R8) Store short BFP product-sum + STFPC 8(R9) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LE FPR8,0(,R7) Get short BFP addend + MAEB FPR8,FPR4,0(,R5) Mult. FPR4 by multiplier, add FPR8 RXE + STE FPR8,12(,R8) Store short BFP product-sum + STFPC 12(R9) Store resulting FPCR flags and DXC +* + LA R8,4*4(,R8) Point to next product-sum result area + LA R9,4*4(,R9) Point to next FPCR contents area + LA R7,4(,R7) Point to next addend value + BCTR R6,R1 Loop through addend values +* + LA R5,4(,R5) Point to next multiplier + BCTR R4,R12 Loop through multiplier values +* + LA R3,4(,R3) Point to next multiplicand + BCT R2,SBFPNFLP Loop through multiplicand values + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Multiply And Add using provided short BFP input triples. +* This set of tests triggers IEEE exceptions Overflow, Underflow, and +* Inexact and collects both trap and non-trap results. +* +* Four results are generated for each input: one RRE with all +* exceptions non-trappable, a second RRE with all exceptions trappable, +* a third RXE with all exceptions non-trappable, a fourth RXE with all +* exceptions trappable, +* +* The product and FPCR are stored for each result. +* +*********************************************************************** + SPACE 2 +SBFPF LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LFPC FPCREGNT Set exceptions non-trappable + LE FPR4,0(,R3) Get short BFP multiplicand + LE FPR1,1*4(,R3) Get short BFP multiplier + LE FPR8,2*4(,R3) Get short BFP addend + MAEBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE + STE FPR8,0(,R7) Store short BFP product-sum + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LE FPR8,2*4(,R3) Reload short BFP addend +* ..multiplier is still in FPR1, +* ..multiplicand is still in FPR4 + MAEBR FPR8,FPR4,FPR1 Multiply short FPR8 by FPR1 RRE + STE FPR8,1*4(,R7) Store short BFP product-sum + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable + LE FPR8,2*4(,R3) Reload short BFP addend +* ..multiplicand is still in FPR4 + MAEB FPR8,FPR4,4(,R3) Mult. FPR4 by multiplier, add FPR8 RXE + STE FPR8,2*4(,R7) Store short BFP product + STFPC 8(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LE FPR8,2*4(,R3) Reload short BFP addend +* ..multiplicand is still in FPR4 + MAEB FPR8,FPR4,4(,R3) Mult. FPR4 by multiplier, add FPR8 RXE + STE FPR8,3*4(,R7) Store short BFP product + STFPC 12(R8) Store resulting FPCR flags and DXC +* + LA R3,3*4(,R3) Point to next input value trible + LA R7,4*4(,R7) Point to next product result set + LA R8,4*4(,R8) Point to next FPCR result set + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Multiply And Add using provided short BFP input triples. +* This set of tests exhaustively tests all rounding modes available for +* Multiply And Add. The rounding mode can only be specified in the +* FPC. +* +* All five FPC rounding modes are tested because the preceeding tests, +* using rounding mode RNTE, do not often create results that require +* rounding. +* +* Two results are generated for each input and rounding mode: one RRE +* and one RXE. Traps are disabled for all rounding mode tests. +* +* The product and FPCR are stored for each test. +* +*********************************************************************** + SPACE 2 +SBFPRM LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + XR R1,R1 Zero register 1 for use in IC/STC/indexing + BASR R12,0 Set top of test case loop + + LA R5,FPCMCT Get count of FPC modes to be tested + BASR R9,0 Set top of rounding mode outer loop +* + IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 0(R1) Set FPC Rounding Mode + LE FPR4,0(,R3) Get short BFP multiplicand + LE FPR1,4(,R3) Get short BFP multiplier + LE FPR8,8(,R3) Get short BFP addend + MAEBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE + STE FPR8,0(,R7) Store short BFP product-sum + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 0(R1) Set FPC Rounding Mode + LE FPR8,8(,R3) Get short BFP addend +* ..multiplicand is still in FPR4 + MAEB FPR8,FPR4,4(,R3) Mult. FPR4 by multiplier, add FPR8 RXE + STE FPR8,4(,R7) Store short BFP product-sum + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LA R7,2*4(,R7) Point to next product result set + LA R8,2*4(,R8) Point to next FPCR result area +* + BCTR R5,R9 Iterate to next FPC mode for this input +* +* End of FPC modes to be tested. Advance to next test case. We will +* skip eight bytes of result area so that each set of five result +* value pairs starts at a memory address ending in zero for the +* convenience of memory dump review. +* + LA R3,3*4(,R3) Point to next input value pair triple + LA R7,8(,R7) Skip to start of next result set + LA R8,8(,R8) Skip to start of next FPCR result set + BCTR R2,R12 Advance to the next input pair +* + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Multiply And Add using provided long BFP inputs. This set +* of tests checks NaN propagation, operations on values that are not +* finite numbers, and other basic tests. This set generates results +* that can be validated against Figure 19-24 on page 19-39 of +* SA22-7832-10. +* +* Four results are generated for each input: one RRE with all +* exceptions non-trappable, a second RRE with all exceptions trappable, +* a third RXE with all exceptions non-trappable, a fourth RXE with all +* exceptions trappable. +* +* Because this is a three-operand instruction, validation against +* Figure 19-24, effectively an 8 x 8 x 8 table, will generate a +* phenomonal set of results. Namely 512 results of 16 bytes each +* plus 512 FPCR contents of 16 bytes each. +* +* The product and FPCR are stored for each result. +* +*********************************************************************** + SPACE 2 +LBFPNF DS 0H BFP long non-finite values tests + LM R2,R3,0(R10) Get count and addr of multiplicand values + LM R8,R9,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller +* +LBFPNFLP DS 0H Top of outer loop - Multiplicand + LM R4,R5,0(R10) Get count and start of multiplier values +* ..which are the same as the multiplicands + BASR R12,0 Set top of middle loop +* + DS 0H Top of middle loop - multiplier + LM R6,R7,0(R10) Get count and start of addend values +* ..which are the same as the multiplicands + BASR R1,0 Set top of inner loop - addend +* +* Multiply and Add: R1 = R3 x R2 + R1 +* + LE FPR4,0(,R3) Get long BFP multiplicand + LE FPR1,0(,R5) Get long BFP multiplier +* + LFPC FPCREGNT Set exceptions non-trappable + LD FPR8,0(,R7) Get long BFP addend + MADBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE + STD FPR8,0(,R8) Store long BFP product-sum + STFPC 0(R9) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LE FPR8,0(,R7) Get long BFP addend + MADBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE + STD FPR8,1*8(,R8) Store long BFP product-sum + STFPC 1*4(R9) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable + LE FPR8,0(,R7) Get long BFP addend + MADB FPR8,FPR4,0(,R5) Mult. FPR4 by multiplier, add FPR8 RXE + STD FPR8,2*8(,R8) Store long BFP product-sum + STFPC 2*4(R9) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LE FPR8,0(,R7) Get long BFP addend + MADB FPR8,FPR4,0(,R5) Mult. FPR4 by multiplier, add FPR8 RXE + STD FPR8,3*8(,R8) Store long BFP product-sum + STFPC 3*4(R9) Store resulting FPCR flags and DXC +* + LA R8,4*8(,R8) Point to next product-sum result area + LA R9,4*4(,R9) Point to next FPCR contents area + LA R7,8(,R7) Point to next addend value + BCTR R6,R1 Loop through addend values +* + LA R5,8(,R5) Point to next multiplier + BCTR R4,R12 Loop through multiplier values +* + LA R3,8(,R3) Point to next multiplicand + BCT R2,LBFPNFLP Loop through multiplicand values + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Multiply And Add using provided long BFP input triples. This +* set of tests triggers IEEE exceptions Overflow, Underflow, and +* Inexact and collects non-trap and trap results. +* +* Four results are generated for each input: one RRE with all +* exceptions non-trappable, a second RRE with all exceptions trappable, +* a third RXE with all exceptions non-trappable, a fourth RXE with all +* exceptions trappable, +* +* The product and FPCR are stored for each result. +* +*********************************************************************** + SPACE 2 +LBFPF LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LFPC FPCREGNT Set exceptions non-trappable + LD FPR4,0(,R3) Get long BFP multiplicand + LD FPR1,8(,R3) Get long BFP multiplier + LD FPR8,16(,R3) Get long BFP addend + MADBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE + STD FPR8,0(,R7) Store long BFP product + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LD FPR8,16(,R3) Reload long BFP addend +* ..multiplier is still in FPR1, +* ..multiplicand is still in FFR4 + MADBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE + STD FPR8,8(,R7) Store long BFP product-sum + STFPC 1*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable + LD FPR8,16(,R3) Reload long BFP addend +* ..multiplicand is still in FFR4 + MADB FPR8,FPR4,8(,R3) Mult. FPR4 by multiplier, add FPR8 RXE + STD FPR8,2*8(,R7) Store long BFP product-sum + STFPC 2*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LD FPR8,16(,R3) Reload long BFP addend +* ..multiplicand is still in FFR4 + MADB FPR8,FPR4,8(,R3) Mult. FPR4 by multiplier, add FPR8 RXE + STD FPR8,3*8(,R7) Store long BFP product-sum + STFPC 3*4(R8) Store resulting FPCR flags and DXC +* + LA R3,3*8(,R3) Point to next input value triple + LA R7,4*8(,R7) Point to next product-sum result set + LA R8,4*4(,R8) Point to next FPCR result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Multiply using provided long BFP input pairs. This set of +* tests exhaustively tests all rounding modes available for Multiply. +* The rounding mode can only be specified in the FPC. +* +* All five FPC rounding modes are tested because the preceeding tests, +* using rounding mode RNTE, do not often create results that require +* rounding. +* +* Two results are generated for each input and rounding mode: one RRE +* and one RXE. Traps are disabled for all rounding mode tests. +* +* The product and FPCR are stored for each result. +* +*********************************************************************** + SPACE 2 +LBFPRM LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + XR R1,R1 Zero register 1 for use in IC/STC/indexing + BASR R12,0 Set top of test case loop + + LA R5,FPCMCT Get count of FPC modes to be tested + BASR R9,0 Set top of rounding mode loop +* + IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 0(R1) Set FPC Rounding Mode + LD FPR4,0(,R3) Get long BFP multiplicand + LD FPR1,8(,R3) Get long BFP multiplier + LD FPR8,16(,R3) Get long BFP addend + MADBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE + STD FPR8,0(,R7) Store long BFP product-sum + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 0(R1) Set FPC Rounding Mode + LD FPR8,16(,R3) Reload long BFP addend + MADB FPR8,FPR4,8(,R3) Multiply long FPR8 by multiplier RXE + STD FPR8,8(,R7) Store long BFP product-sum + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LA R7,2*8(,R7) Point to next product result set + LA R8,2*4(,R8) Point to next FPCR result area +* + BCTR R5,R9 Iterate to next FPC mode +* +* End of FPC modes to be tested. Advance to next test case. We will +* skip eight bytes of FPCR result area so that each set of five result +* FPCR contents pairs starts at a memory address ending in zero for the +* convenience of memory dump review. +* + LA R3,3*8(,R3) Point to next input value triple + LA R8,8(,R8) Skip to start of next FPCR result area + BCTR R2,R12 Multiply next input value lots of times +* + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Table of FPC rounding modes to test product rounding modes. +* +* The Set BFP Rounding Mode does allow specification of the FPC +* rounding mode as an address, so we shall index into a table of +* BFP rounding modes without bothering with Execute. +* +*********************************************************************** + SPACE 2 +* +* Rounding modes that may be set in the FPCR. The FPCR controls +* rounding of the product. +* +* These are indexed directly by the loop counter, which counts down. +* So the modes are listed in reverse order here. +* +FPCMODES DS 0C + DC AL1(7) RFS, Round for shorter precision + DC AL1(3) RM, Round to -infinity + DC AL1(2) RP, Round to +infinity + DC AL1(1) RZ, Round to zero + DC AL1(0) RNTE, Round to Nearest, ties to even +FPCMCT EQU *-FPCMODES Count of FPC Modes to be tested +* + EJECT +*********************************************************************** +* +* Short BFP test data sets for Multiply And Add testing. +* +* The first test data set is used for tests of basic functionality, +* NaN propagation, and results from operations involving other than +* finite numbers. The same set of eight values is used as the +* multiplicand, multiplier, and addend, resulting in 8 x 8 x 8 or +* 512 test cases. +* +* The second test data set is used for testing boundary conditions +* using two finite non-zero values. Each possible condition code +* and type of result (normal, scaled, etc) is created by members of +* this test data set. +* +* The third test data set is used for exhaustive testing of final +* results across the five rounding modes available for the Multiply +* instruction. +* +* The strategy for predictable rounding mode testing is to use a +* multiplicand with some one-bits in the low-order byte and multiply +* that by 1/16 (0.0625). In BFP, this will have the effect of shifting +* the low-order byte out of the target precision representation and +* into the high-order portion of the bits that control rounding. The +* input low-order byte will be determined by the rounding desired. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* First input test data set, to test operations using non-finite or +* zero inputs. Member values chosen to validate Figure 19-24 on page +* 19-39 of SA22-7832-10. Each value in this table is used as the +* multiplicand, multiplier, and addend. Eight entries menas 512 result +* sets. +* +*********************************************************************** + SPACE 2 +SBFPNFIN DS 0F Inputs for short BFP non-finite tests + DC X'FF800000' -inf + DC X'C0000000' -2.0 + DC X'80000000' -0 + DC X'00000000' +0 + DC X'40000000' +2.0 + DC X'7F800000' +inf + DC X'FFCB0000' -QNaN + DC X'7F8A0000' +SNaN +SBFPNFCT EQU (*-SBFPNFIN)/4 Count of short BFP in list + SPACE 3 +*********************************************************************** +* +* Second input test data set. These are finite triples intended to +* trigger overflow, underflow, and inexact exceptions. Each triple is +* added twice, once non-trappable and once trappable. Trappable +* overflow or underflow yields a scaled result. Trappable inexact +* will show whether the Incremented DXC code is returned. +* +* The following test cases are required: +* 1. Overflow +* 2. Underflow - normal inputs +* 3. Underflow - subnormal inputs +* 4. Normal - from subnormal inputs +* 5. Inexact - incremented +* 6. Inexact - truncated +* +*********************************************************************** + SPACE 2 +SBFPIN DS 0F Inputs for short BFP finite tests +* +* Overflow on multiplication two ways - once on the multiply, once +* on the addition following the multiplication. +* + DC X'7F7FFFFF' +Nmax multiplicand + DC X'FF7FFFFF' -Nmax multiplier + DC X'7F7FFFFF' Big positive value, won't show up. +* + DC X'7F7FFFFF' +Nmax multiplicand + DC X'3F800000' +1.0 multiplier + DC X'7F7FFFFF' +Nmax addend, triggers overflow +* +* Underflow from product of normals. We will multiply a small normal +* by 0.25 to generate a subnormal. We cannot add another normal +* (positive or negative) and keep the result subnormal, so we will just +* add a subnormal. +* + DC X'00FFFFFF' Very small normal number + DC X'3E800000' 0.25, creates subnormal + DC X'00000001' +Dmin, will appear in result +* +* Underflow from the product of a subnormal and a normal. +* + DC X'3F000000' +0.5 + DC X'007FFFFF' +Dmax Subnormal + DC X'00000001' +Dmin, will appear in result +* +* We cannot generate a normal result from product of subnormals +* because the result will be smaller than both the multiplicand and the +* multiplier. So we'll try multiplying +Dmax by 2. The result should +* be +Nmin plus the addend. +* + DC X'007FFFFF' +Dmax + DC X'40000000' +2.0 + DC X'00400000' +Dmax +* +* Multiply a value from 1.0 such that the added digits are to the right +* of the right-most bit in the stored significand. The result will be +* inexact, and incremented will be determined by the value of the +* bits in the multiplier. We will add 0.5 to this product because +* that value will not cause renormalization. Renormalization would +* shift the rounding bits one to the right, messing up the expected +* rounding. +* + DC X'3F80000C' Multiplicand 1.000001430511474609375 + DC X'3F880000' Multiplier 1.0625 (1 + 1/16) + DC X'3F000000' Plus 0.5 +*..nearest is away from zero, incremented. +* + DC X'3F800007' Multiplicand 1.00000083446502685546875 + DC X'3F880000' Multiplier 1.0625 (1 + 1/16) + DC X'3F000000' Plus 0.5 +*..nearest is toward zero, truncated +* +SBFPCT EQU (*-SBFPIN)/4/3 Count of short BFP in list + SPACE 3 +*********************************************************************** +* +* Third input test data set. These are finite triples intended to +* test all combinations of rounding mode for the product and the +* remainder. Values are chosen to create a requirement to round +* to the target precision after the computation and to generate +* varying results depending on the rounding mode in the FPCR. +* +* The result set will have cases that represent each of the following +* +* 1. Positive, nearest magnitude is toward zero. +* 2. Negative, nearest magnitude is toward zero. +* 3. Positive, nearest magnitude is away from zero. +* 4. Negative, nearest magnitude is away from zero. +* 5. Positive, tie, nearest even has greater magnitude +* 6. Negative, tie, nearest even has greater magnitude +* 7. Positive, tie, nearest even has lower magnitude +* 8. Negative, tie, nearest even has lower magnitude +* +* Round For Shorter precision correctness can be determined from the +* above test cases. +* +*********************************************************************** + SPACE 2 +SBFPINRM DS 0F Inputs for short BFP rounding testing +* +* Multiply a value from 1.0 such that the added digits are to the right +* of the right-most bit in the stored significand. The result will be +* inexact, and incremented will be determined by the value of the +* bits in the multiplier. +* + DC X'3F800007' Multiplicand +1.00000083446502685546875 + DC X'3F880000' Multiplier 1.0625 (1/16) + DC X'3F000000' Addend 0.5 + DC X'BF800007' Multiplicand -1.00000083446502685546875 + DC X'3F880000' Multiplier 1.0625 (1/16) + DC X'BF000000' Addend -0.5 +*..nearest is toward zero, truncated +* + DC X'3F80000C' Multiplicand +1.000001430511474609375 + DC X'3F880000' Multiplier 1.0625 (1/16) + DC X'3F000000' Addend 0.5 + DC X'BF80000C' Multiplicand -1.000001430511474609375 + DC X'3F880000' Multiplier 1.0625 (1/16) + DC X'BF000000' Addend -0.5 +*..nearest is away from zero, incremented. +* + DC X'3F800008' Multiplicand +1.000000476837158203125 + DC X'3F880000' Multiplier 1.0625 (1/16) + DC X'3F000000' Addend 0.5 + DC X'BF800008' Multiplicand -1.000000476837158203125 + DC X'3F880000' Multiplier 1.0625 (1/16) + DC X'BF000000' Addend -0.5 +*..nearest is a tie, nearest even has lower magnitude +* + DC X'3F800018' Multiplicand +1.000002384185791015625 + DC X'3F880000' Multiplier 1.0625 (1/16) + DC X'3F000000' Addend 0.5 + DC X'BF800018' Multiplicand -1.000002384185791015625 + DC X'3F880000' Multiplier 1.0625 (1/16) + DC X'BF000000' Addend -0.5 +*..nearest is a tie, nearest even has greater magnitude +* +SBFPRMCT EQU (*-SBFPINRM)/4/3 Count of short BFP rounding tests + EJECT +*********************************************************************** +* +* Long BFP test data sets for Multiply And Add testing. +* +* The first test data set is used for tests of basic functionality, +* NaN propagation, and results from operations involving other than +* finite numbers. +* +* The second test data set is used for testing boundary conditions +* using two finite non-zero values. Each possible condition code +* and type of result (normal, scaled, etc) is created by members of +* this test data set. +* +* The third test data set is used for exhaustive testing of final +* results across the five rounding modes available for the Add +* instruction. +* +* See the Short BFP test cases header for a discussion of test case +* selection for rounding mode test case values. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* First input test data set, to test operations using non-finite or +* zero inputs. Member values chosen to validate Figure 19-24 on page +* 19-39 of SA22-7832-10. Each value in this table is used as the +* multiplicand, multiplier, and addend. Eight entries menas 512 result +* sets. +* +*********************************************************************** + SPACE 2 +LBFPNFIN DS 0F Inputs for long BFP testing + DC X'FFF0000000000000' -inf + DC X'C000000000000000' -2.0 + DC X'8000000000000000' -0 + DC X'0000000000000000' +0 + DC X'4000000000000000' +2.0 + DC X'7FF0000000000000' +inf + DC X'FFF8B00000000000' -QNaN + DC X'7FF0A00000000000' +SNaN +LBFPNFCT EQU (*-LBFPNFIN)/8 Count of long BFP in list + SPACE 3 +*********************************************************************** +* +* Second input test data set. These are finite triples intended to +* trigger overflow, underflow, and inexact exceptions. Each triples is +* added twice, once non-trappable and once trappable. Trappable +* overflow or underflow yields a scaled result. Trappable inexact +* will show whether the Incremented DXC code is returned. +* +* The following test cases are required: +* 1. Overflow +* 2. Underflow - normal inputs +* 3. Underflow - subnormal inputs +* 4. Normal - from subnormal inputs +* 5. Inexact - incremented +* 6. Inexact - truncated +* +*********************************************************************** + SPACE 2 +LBFPIN DS 0D Inputs for long BFP finite tests +* +* Overflow on multiplication two ways. Once on the muliplication step, +* and then a second time on the addition step. +* + DC X'7FEFFFFFFFFFFFFF' +Nmax + DC X'FFEFFFFFFFFFFFFF' -Nmax + DC X'3FF0000000000000' +1.0 +* + DC X'7FEFFFFFFFFFFFFF' +Nmax + DC X'3FF0000000000000' +1.0 + DC X'7FEFFFFFFFFFFFFF' +Nmax +* +* Underflow from product of normals. We will multiply a small normal +* by 0.25 to generate a subnormal. We cannot add another normal +* (positive or negative) and keep the result subnormal, so we will just +* add a subnormal. +* + DC X'001FFFFFFFFFFFFF' Very small normal number + DC X'3FD0000000000000' 0.25, creates subnormal + DC X'0000000000000001' +Dmin, will appear in result +* +* Underflow from the product of a subnormal and a normal. +* + DC X'3FE0000000000000' +0.5 + DC X'000FFFFFFFFFFFFF' +Dmax subnormal + DC X'0000000000000001' +Dmin, will appear in result +* +* We cannot generate a normal result from product of subnormals +* because the result will be smaller than both the multiplicand and the +* multiplier. So we'll try multiplying +Dmax by 2. The result should +* be +Nmin +* + DC X'000FFFFFFFFFFFFF' +Dmax + DC X'4000000000000000' +2.0, result should be normal + DC X'0008000000000000' A large subnormal +* +* Multiply a value from 1.0 such that the added digits are to the right +* of the right-most bit in the stored significand. The result will be +* inexact, and incremented will be determined by the value of the +* bits in the multiplier. +* + DC X'3FF000000000000C' Multiplicand +1, aka 1.0b0 + DC X'3FF1000000000000' Multiplier 1.0625 (1/16) + DC X'3FE0000000000000' +0.5 +*..nearest is away from zero, incremented. +* + DC X'3FF0000000000007' Multiplicand +1, aka 1.0b0 + DC X'3FF1000000000000' Multiplier 1.0625 (1/16) + DC X'3FE0000000000000' +0.5 +*..nearest is toward zero, truncated. +* +LBFPCT EQU (*-LBFPIN)/8/3 Count of long BFP triples in list + SPACE 3 +*********************************************************************** +* +* Third input test data set. These are finite triples intended to +* test all combinations of rounding mode for the product and the +* remainder. Values are chosen to create a requirement to round +* to the target precision after the computation and to generate +* varying results depending on the rounding mode in the FPCR. +* +* The result set will have cases that represent each of the following +* +* 1. Positive, nearest magnitude is toward zero. +* 2. Negative, nearest magnitude is toward zero. +* 3. Positive, nearest magnitude is away from zero. +* 4. Negative, nearest magnitude is away from zero. +* 5. Positive, tie, nearest even has greater magnitude +* 6. Negative, tie, nearest even has greater magnitude +* 7. Positive, tie, nearest even has lower magnitude +* 8. Negative, tie, nearest even has lower magnitude +* +* Round For Shorter precision correctness can be determined from the +* above test cases. +* +*********************************************************************** + SPACE 2 +LBFPINRM DS 0F +* +* Multiply a value from 1.0 such that the added digits are to the right +* of the right-most bit in the stored significand. The result will be +* inexact, and incremented will be determined by the value of the +* bits in the multiplier. +* + DC X'3FF0000000000007' Multiplicand + DC X'3FF1000000000000' Multiplier 1.0625 (1/16) + DC X'3FE0000000000000' +0.5 + DC X'BFF0000000000007' Multiplicand + DC X'3FF1000000000000' Multiplier 1.0625 (1/16) + DC X'BFE0000000000000' -0.5 +*..nearest is toward zero, truncated. +* + DC X'3FF000000000000C' Multiplicand + DC X'3FF1000000000000' Multiplier 1.0625 (1/16) + DC X'3FE0000000000000' +0.5 + DC X'BFF000000000000C' Multiplicand + DC X'3FF1000000000000' Multiplier 1.0625 (1/16) + DC X'BFE0000000000000' -0.5 +*..nearest is away from zero, incremented. +* + DC X'3FF0000000000008' Multiplicand + DC X'3FF1000000000000' Multiplier 1.0625 (1/16) + DC X'3FE0000000000000' +0.5 + DC X'BFF0000000000008' Multiplicand + DC X'3FF1000000000000' Multiplier 1.0625 (1/16) + DC X'BFE0000000000000' -0.5 +*..nearest is a tie, nearest even has lower magnitude +* + DC X'3FF0000000000018' Multiplicand +1, aka +1.0b0 + DC X'3FF1000000000000' Multiplier 1.0625 (1/16) + DC X'3FE0000000000000' +0.5 + DC X'BFF0000000000018' Multiplicand -1, aka -1.0b0 + DC X'3FF1000000000000' Multiplier 1.0625 (1/16) + DC X'BFE0000000000000' -0.5 +*..nearest is a tie, nearest even has greater magnitude +* +LBFPRMCT EQU (*-LBFPINRM)/8/3 Count of long BFP rounding tests + EJECT +* +* Locations for results +* +SBFPNFOT EQU STRTLABL+X'1000' Short non-finite BFP results +* ..room for 512 tests, 512 used +SBFPNFFL EQU STRTLABL+X'3000' FPCR flags and DXC from short BFP +* ..room for 512 tests, 512 used +* +SBFPOUT EQU STRTLABL+X'5000' Short BFP finite results +* ..room for 16 tests, 7 used +SBFPFLGS EQU STRTLABL+X'5100' FPCR flags and DXC from short BFP +* ..room for 16 tests, 7 used +* +SBFPRMO EQU STRTLABL+X'5200' Short BFP rounding mode test results +* ..Room for 16, 8 used. +SBFPRMOF EQU STRTLABL+X'5500' Short BFP rounding mode FPCR results +* ..Room for 16, 8 used. +* ..next location starts at X'5800' +* +LBFPNFOT EQU STRTLABL+X'6000' Long non-finite BFP results +* ..room for 512 tests, 512 used +LBFPNFFL EQU STRTLABL+X'A000' FPCR flags and DXC from long BFP +* ..room for 512 tests, 512 used +* +LBFPOUT EQU STRTLABL+X'C000' Long BFP finite results +* ..room for 16 tests, 7 used +LBFPFLGS EQU STRTLABL+X'C200' FPCR flags and DXC from long BFP +* ..room for 16 tests, 7 used +* +LBFPRMO EQU STRTLABL+X'C500' Long BFP rounding mode test results +* ..Room for 16, 8 used. +LBFPRMOF EQU STRTLABL+X'CA00' Long BFP rounding mode FPCR results +* ..Room for 16, 8 used. +* ..next location starts at X'CD00' +* +* +ENDLABL EQU STRTLABL+X'C800' + PADCSECT ENDLABL + END diff --git a/tests/bfp-021-multadd.core b/tests/bfp-021-multadd.core new file mode 100644 index 000000000..63bb43abe Binary files /dev/null and b/tests/bfp-021-multadd.core differ diff --git a/tests/bfp-021-multadd.list b/tests/bfp-021-multadd.list new file mode 100644 index 000000000..c55566ea8 --- /dev/null +++ b/tests/bfp-021-multadd.list @@ -0,0 +1,1337 @@ +ASMA Ver. 0.2.0 bfp-021-multadd.asm: Test IEEE Multiply And Add 09 Oct 2016 08:59:54 Page 1 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 2 *********************************************************************** + 3 * + 4 *Testcase IEEE MULTIPLY AND ADD + 5 * Test case capability includes IEEE exceptions trappable and + 6 * otherwise. Test results, FPCR flags, the Condition code, and any + 7 * DXC are saved for all tests. + 8 * + 9 * This test program is focused on the four fused Multiply And Add + 10 * instructions. Standard Multiply and Multiply to longer precision + 11 * are tested in other programs. + 12 * + 13 *********************************************************************** + + + 15 *********************************************************************** + 16 * + 17 * Tests the following three conversion instructions + 18 * MULTIPLY AND ADD (short BFP, RRE) + 19 * MULTIPLY AND ADD (long BFP, RRE) + 20 * MULTIPLY AND ADD (short BFP, RXE) + 21 * MULTIPLY AND ADD (long BFP, RXE) + 22 * + 23 * + 24 * Test data is compiled into this program. The test script that runs + 25 * this program can provide alternative test data through Hercules R + 26 * commands. + 27 * + 28 * Test Case Order + 29 * 1) Short BFP basic tests, including traps and NaN propagation + 30 * 2) Short BFP finite number tests, including traps and scaling + 31 * 3) Short BFP FPC-controlled rounding mode exhaustive tests + 32 * 4) Long BFP basic tests, including traps and NaN propagation + 33 * 5) Long BFP finite number tests, including traps and scaling + 34 * 6) Long BFP FPC-controlled rounding mode exhaustive tests + 35 * + 36 * Three input test sets are provided each for short and long BFP + 37 * inputs. Test values are the same for each precision for most + 38 * tests. Overflow and underflow each require precision- + 39 * dependent test values. + 40 * + 41 * Review of Softfloat code for multiply and add shows that the + 42 * multiplication and addition are performed in precision-independent + 43 * format. Overflow, underflow, inexact, and incremented are detected + 44 * upon conversion from precision-independent format to the target + 45 * format. As a result, it should not matter whether overflow etc is + 46 * caused by the multiplication or the addition. We will include + 47 * a few test cases where this differs in the finite testing section, + 48 * but that's all. + 49 * + 50 * Also tests the following floating point support instructions + 51 * LOAD (Short) + 52 * LOAD (Long) + ASMA Ver. 0.2.0 bfp-021-multadd.asm: Test IEEE Multiply And Add 09 Oct 2016 08:59:54 Page 2 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 53 * LFPC (Load Floating Point Control Register) + 54 * SRNMB (Set BFP Rounding Mode 3-bit) + 55 * STORE (Short) + 56 * STORE (Long) + 57 * STFPC (Store Floating Point Control Register) + 58 * + 59 *********************************************************************** + + + 61 MACRO + 62 PADCSECT &ENDLABL + 63 .* + 64 .* Macro to pad the CSECT to include result data areas if this test + 65 .* program is not being assembled using asma. asma generates a core + 66 .* image that is loaded by the loadcore command, and because the + 67 .* core image is a binary stored in Github, it makes sense to make + 68 .* this small effort to keep the core image small. + 69 .* + 70 AIF (D'&ENDLABL).GOODPAD + 71 MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + 72 MNOTE *,'No CSECT padding performed' + 73 MEXIT + 74 .* + 75 .GOODPAD ANOP Label valid. See if we're on asma + 76 AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + 77 ORG &ENDLABL-1 Not ASMA. Pad CSECT + 78 MEXIT + 79 .* + 80 .NOPAD ANOP + 81 MNOTE *,'asma detected; no CSECT padding performed' + 82 MEND + 83 * + 84 * Note: for compatibility with the z/CMS test rig, do not change + 85 * or use R11, R14, or R15. Everything else is fair game. + 86 * + 0000000000000000 00000000000008D7 87 BFPMULA START 0 + 0000000000000000 0000000000000001 88 STRTLABL EQU * + 0000000000000000 0000000000000001 89 R0 EQU 0 Work register for cc extraction + 0000000000000001 0000000000000001 90 R1 EQU 1 + 0000000000000002 0000000000000001 91 R2 EQU 2 Holds count of test input values + 0000000000000003 0000000000000001 92 R3 EQU 3 Points to next test input value(s) + 0000000000000004 0000000000000001 93 R4 EQU 4 Rounding tests inner loop control + 0000000000000005 0000000000000001 94 R5 EQU 5 Rounding tests outer loop control + 0000000000000006 0000000000000001 95 R6 EQU 6 Rounding tests top of inner loop + 0000000000000007 0000000000000001 96 R7 EQU 7 Pointer to next result value(s) + 0000000000000008 0000000000000001 97 R8 EQU 8 Pointer to next FPCR result + 0000000000000009 0000000000000001 98 R9 EQU 9 Rounding tests top of outer loop + 000000000000000A 0000000000000001 99 R10 EQU 10 Pointer to test address list + 000000000000000B 0000000000000001 100 R11 EQU 11 **Reserved for z/CMS test rig + 000000000000000C 0000000000000001 101 R12 EQU 12 Holds number of test cases in set + 000000000000000D 0000000000000001 102 R13 EQU 13 Mainline return address + 000000000000000E 0000000000000001 103 R14 EQU 14 **Return address for z/CMS test rig + ASMA Ver. 0.2.0 bfp-021-multadd.asm: Test IEEE Multiply And Add 09 Oct 2016 08:59:54 Page 3 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 000000000000000F 0000000000000001 104 R15 EQU 15 **Base register on z/CMS or Hyperion + 105 * + 106 * Floating Point Register equates to keep the cross reference clean + 107 * + 0000000000000000 0000000000000001 108 FPR0 EQU 0 + 0000000000000001 0000000000000001 109 FPR1 EQU 1 + 0000000000000002 0000000000000001 110 FPR2 EQU 2 + 0000000000000003 0000000000000001 111 FPR3 EQU 3 + 0000000000000004 0000000000000001 112 FPR4 EQU 4 + 0000000000000005 0000000000000001 113 FPR5 EQU 5 + 0000000000000006 0000000000000001 114 FPR6 EQU 6 + 0000000000000007 0000000000000001 115 FPR7 EQU 7 + 0000000000000008 0000000000000001 116 FPR8 EQU 8 + 0000000000000009 0000000000000001 117 FPR9 EQU 9 + 000000000000000A 0000000000000001 118 FPR10 EQU 10 + 000000000000000B 0000000000000001 119 FPR11 EQU 11 + 000000000000000C 0000000000000001 120 FPR12 EQU 12 + 000000000000000D 0000000000000001 121 FPR13 EQU 13 + 000000000000000E 0000000000000001 122 FPR14 EQU 14 + 000000000000000F 0000000000000001 123 FPR15 EQU 15 + 124 * +0000000000000000 0000000000000000 125 USING *,R15 + 126 * + 127 * Above works on real iron (R15=0 after sysclear) + 128 * and in z/CMS (R15 points to start of load module) + 129 * + + + 131 *********************************************************************** + 132 * + 133 * Low core definitions, Restart PSW, and Program Check Routine. + 134 * + 135 *********************************************************************** + + +0000000000000000 0000000000000000 000000000000008E 137 ORG STRTLABL+X'8E' Program check interrution code +000000000000008E 0000 138 PCINTCD DS H + 139 * + 0000000000000150 0000000000000001 140 PCOLDPSW EQU STRTLABL+X'150' z/Arch Program check old PSW + 141 * +0000000000000090 0000000000000090 00000000000001A0 142 ORG STRTLABL+X'1A0' z/Arch Restart PSW +00000000000001A0 00000001 80000000 143 DC X'0000000180000000',AD(START) + 144 * +00000000000001B0 00000000000001B0 00000000000001D0 145 ORG STRTLABL+X'1D0' z/Arch Program check old PSW +00000000000001D0 00000000 00000000 146 DC X'0000000000000000',AD(PROGCHK) + 147 * + 148 * Program check routine. If Data Exception, continue execution at + 149 * the instruction following the program check. Otherwise, hard wait. + 150 * No need to collect data. All interesting DXC stuff is captured + 151 * in the FPCR. + 152 * +00000000000001E0 00000000000001E0 0000000000000200 153 ORG STRTLABL+X'200' + ASMA Ver. 0.2.0 bfp-021-multadd.asm: Test IEEE Multiply And Add 09 Oct 2016 08:59:54 Page 4 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000200 154 PROGCHK DS 0H Program check occured... +0000000000000200 9507 F08F 000000000000008F 155 CLI PCINTCD+1,X'07' Data Exception? +0000000000000204 A774 0004 000000000000020C 156 JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) +0000000000000208 B2B2 F150 0000000000000150 157 LPSWE PCOLDPSW ..yes, resume program execution +000000000000020C 158 PCNOTDTA DS 0H +000000000000020C 12EE 159 LTR R14,R14 Return address provided? +000000000000020E 077E 160 BNZR R14 Yes, return to z/CMS test rig. +0000000000000210 B2B2 F268 0000000000000268 161 LPSWE HARDWAIT Not data exception, enter disabled wait + ASMA Ver. 0.2.0 bfp-021-multadd.asm: Test IEEE Multiply And Add 09 Oct 2016 08:59:54 Page 5 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 163 *********************************************************************** + 164 * + 165 * Main program. Enable Advanced Floating Point, process test cases. + 166 * + 167 *********************************************************************** + + +0000000000000214 169 START DS 0H +0000000000000214 B600 F278 0000000000000278 170 STCTL R0,R0,CTLR0 Store CR0 to enable AFP +0000000000000218 9604 F279 0000000000000279 171 OI CTLR0+1,X'04' Turn on AFP bit +000000000000021C B700 F278 0000000000000278 172 LCTL R0,R0,CTLR0 Reload updated CR0 + 173 * +0000000000000220 41A0 F300 0000000000000300 174 LA R10,SHORTNF Point to short BFP non-finite inputs +0000000000000224 4DD0 F360 0000000000000360 175 BAS R13,SBFPNF Multiply short BFP non-finites +0000000000000228 41A0 F310 0000000000000310 176 LA R10,SHORTF Point to short BFP finite inputs +000000000000022C 4DD0 F3F2 00000000000003F2 177 BAS R13,SBFPF Multiply short BFP finites +0000000000000230 41A0 F320 0000000000000320 178 LA R10,RMSHORTS Point to short BFP rounding mode tests +0000000000000234 4DD0 F46C 000000000000046C 179 BAS R13,SBFPRM Multiply short BFP for rounding tests + 180 * +0000000000000238 41A0 F330 0000000000000330 181 LA R10,LONGNF Point to long BFP non-finite inputs +000000000000023C 4DD0 F4DA 00000000000004DA 182 BAS R13,LBFPNF Multiply long BFP non-finites +0000000000000240 41A0 F340 0000000000000340 183 LA R10,LONGF Point to long BFP finite inputs +0000000000000244 4DD0 F56C 000000000000056C 184 BAS R13,LBFPF Multiply long BFP finites +0000000000000248 41A0 F350 0000000000000350 185 LA R10,RMLONGS Point to long BFP rounding mode tests +000000000000024C 4DD0 F5E6 00000000000005E6 186 BAS R13,LBFPRM Multiply long BFP for rounding tests + 187 * +0000000000000250 12EE 188 LTR R14,R14 Return address provided? +0000000000000252 077E 189 BNZR R14 ..Yes, return to z/CMS test rig. +0000000000000254 B2B2 F258 0000000000000258 190 LPSWE WAITPSW All done + 191 * +0000000000000258 192 DS 0D Ensure correct alignment for psw +0000000000000258 00020000 00000000 193 WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +0000000000000268 00020000 00000000 194 HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end + 195 * +0000000000000278 00000000 196 CTLR0 DS F +000000000000027C 00000000 197 FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +0000000000000280 F8000000 198 FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags + 199 * + 200 * Input values parameter list, four fullwords for each test data set + 201 * 1) Count, + 202 * 2) Address of inputs, + 203 * 3) Address to place results, and + 204 * 4) Address to place DXC/Flags/cc values. + 205 * +0000000000000284 0000000000000284 0000000000000300 206 ORG STRTLABL+X'300' Enable run-time replacement +0000000000000300 207 SHORTNF DS 0F Input pairs for short BFP non-finite tests +0000000000000300 00000008 208 DC A(SBFPNFCT) +0000000000000304 00000658 209 DC A(SBFPNFIN) +0000000000000308 00001000 210 DC A(SBFPNFOT) +000000000000030C 00003000 211 DC A(SBFPNFFL) + 212 * +0000000000000310 213 SHORTF DS 0F Input pairs for short BFP finite tests + ASMA Ver. 0.2.0 bfp-021-multadd.asm: Test IEEE Multiply And Add 09 Oct 2016 08:59:54 Page 6 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000310 00000007 214 DC A(SBFPCT) +0000000000000314 00000678 215 DC A(SBFPIN) +0000000000000318 00005000 216 DC A(SBFPOUT) +000000000000031C 00005100 217 DC A(SBFPFLGS) + 218 * +0000000000000320 219 RMSHORTS DS 0F Input pairs for short BFP rounding testing +0000000000000320 00000008 220 DC A(SBFPRMCT) +0000000000000324 000006CC 221 DC A(SBFPINRM) +0000000000000328 00005200 222 DC A(SBFPRMO) +000000000000032C 00005500 223 DC A(SBFPRMOF) + 224 * +0000000000000330 225 LONGNF DS 0F Input pairs for long BFP non-finite testing +0000000000000330 00000008 226 DC A(LBFPNFCT) +0000000000000334 0000072C 227 DC A(LBFPNFIN) +0000000000000338 00006000 228 DC A(LBFPNFOT) +000000000000033C 0000A000 229 DC A(LBFPNFFL) + 230 * +0000000000000340 231 LONGF DS 0F Input pairs for long BFP finite testing +0000000000000340 00000007 232 DC A(LBFPCT) +0000000000000344 00000770 233 DC A(LBFPIN) +0000000000000348 0000C000 234 DC A(LBFPOUT) +000000000000034C 0000C200 235 DC A(LBFPFLGS) + 236 * +0000000000000350 237 RMLONGS DS 0F Input pairs for long BFP rounding testing +0000000000000350 00000008 238 DC A(LBFPRMCT) +0000000000000354 00000818 239 DC A(LBFPINRM) +0000000000000358 0000C500 240 DC A(LBFPRMO) +000000000000035C 0000CA00 241 DC A(LBFPRMOF) + 242 * + ASMA Ver. 0.2.0 bfp-021-multadd.asm: Test IEEE Multiply And Add 09 Oct 2016 08:59:54 Page 7 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 244 *********************************************************************** + 245 * + 246 * Perform Multiply And Add using provided short BFP inputs. This set + 247 * of tests checks NaN propagation, operations on values that are not + 248 * finite numbers, and other basic tests. This set generates results + 249 * that can be validated against Figure 19-24 on page 19-39 of + 250 * SA22-7832-10. + 251 * + 252 * Four results are generated for each input: one RRE with all + 253 * exceptions non-trappable, a second RRE with all exceptions trappable, + 254 * a third RXE with all exceptions non-trappable, a fourth RXE with all + 255 * exceptions trappable. + 256 * + 257 * Because this is a three-operand instruction, validation against + 258 * Figure 19-24, effectively an 8 x 8 x 8 table, will generate a + 259 * phenomonal set of results. Namely 512 results of 16 bytes each + 260 * plus 512 FPCR contents of 16 bytes each. + 261 * + 262 * The product and FPCR are stored for each result. + 263 * + 264 *********************************************************************** + + +0000000000000360 266 SBFPNF DS 0H BFP Short non-finite values tests +0000000000000360 9823 A000 0000000000000000 267 LM R2,R3,0(R10) Get count and addr of multiplicand values +0000000000000364 9889 A008 0000000000000008 268 LM R8,R9,8(R10) Get address of result area and flag area. +0000000000000368 1222 269 LTR R2,R2 Any test cases? +000000000000036A 078D 270 BZR R13 ..No, return to caller + 271 * +000000000000036C 272 SBFPNFLP DS 0H Top of outer loop - Multiplicand +000000000000036C 9845 A000 0000000000000000 273 LM R4,R5,0(R10) Get count and start of multiplier values + 274 * ..which are the same as the multiplicands +0000000000000370 0DC0 275 BASR R12,0 Set top of middle loop + 276 * +0000000000000372 277 DS 0H Top of middle loop - multiplier +0000000000000372 9867 A000 0000000000000000 278 LM R6,R7,0(R10) Get count and start of addend values + 279 * ..which are the same as the multiplicands +0000000000000376 0D10 280 BASR R1,0 Set top of inner loop - addend + 281 * + 282 * Multiply and Add: R1 = R3 x R2 + R1 + 283 * +0000000000000378 7840 3000 0000000000000000 284 LE FPR4,0(,R3) Get short BFP multiplicand +000000000000037C 7810 5000 0000000000000000 285 LE FPR1,0(,R5) Get short BFP multiplier + 286 * +0000000000000380 B29D F27C 000000000000027C 287 LFPC FPCREGNT Set exceptions non-trappable +0000000000000384 7880 7000 0000000000000000 288 LE FPR8,0(,R7) Get short BFP addend +0000000000000388 B30E 8041 289 MAEBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE +000000000000038C 7080 8000 0000000000000000 290 STE FPR8,0(,R8) Store short BFP product-sum +0000000000000390 B29C 9000 0000000000000000 291 STFPC 0(R9) Store resulting FPCR flags and DXC + 292 * +0000000000000394 B29D F280 0000000000000280 293 LFPC FPCREGTR Set exceptions trappable +0000000000000398 7880 7000 0000000000000000 294 LE FPR8,0(,R7) Get short BFP addend + ASMA Ver. 0.2.0 bfp-021-multadd.asm: Test IEEE Multiply And Add 09 Oct 2016 08:59:54 Page 8 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +000000000000039C B30E 8041 295 MAEBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE +00000000000003A0 7080 8004 0000000000000004 296 STE FPR8,4(,R8) Store short BFP product-sum +00000000000003A4 B29C 9004 0000000000000004 297 STFPC 4(R9) Store resulting FPCR flags and DXC + 298 * +00000000000003A8 B29D F27C 000000000000027C 299 LFPC FPCREGNT Set exceptions non-trappable +00000000000003AC 7880 7000 0000000000000000 300 LE FPR8,0(,R7) Get short BFP addend +00000000000003B0 ED40 5000 800E 0000000000000000 301 MAEB FPR8,FPR4,0(,R5) Mult. FPR4 by multiplier, add FPR8 RXE +00000000000003B6 7080 8008 0000000000000008 302 STE FPR8,8(,R8) Store short BFP product-sum +00000000000003BA B29C 9008 0000000000000008 303 STFPC 8(R9) Store resulting FPCR flags and DXC + 304 * +00000000000003BE B29D F280 0000000000000280 305 LFPC FPCREGTR Set exceptions trappable +00000000000003C2 7880 7000 0000000000000000 306 LE FPR8,0(,R7) Get short BFP addend +00000000000003C6 ED40 5000 800E 0000000000000000 307 MAEB FPR8,FPR4,0(,R5) Mult. FPR4 by multiplier, add FPR8 RXE +00000000000003CC 7080 800C 000000000000000C 308 STE FPR8,12(,R8) Store short BFP product-sum +00000000000003D0 B29C 900C 000000000000000C 309 STFPC 12(R9) Store resulting FPCR flags and DXC + 310 * +00000000000003D4 4180 8010 0000000000000010 311 LA R8,4*4(,R8) Point to next product-sum result area +00000000000003D8 4190 9010 0000000000000010 312 LA R9,4*4(,R9) Point to next FPCR contents area +00000000000003DC 4170 7004 0000000000000004 313 LA R7,4(,R7) Point to next addend value +00000000000003E0 0661 314 BCTR R6,R1 Loop through addend values + 315 * +00000000000003E2 4150 5004 0000000000000004 316 LA R5,4(,R5) Point to next multiplier +00000000000003E6 064C 317 BCTR R4,R12 Loop through multiplier values + 318 * +00000000000003E8 4130 3004 0000000000000004 319 LA R3,4(,R3) Point to next multiplicand +00000000000003EC 4620 F36C 000000000000036C 320 BCT R2,SBFPNFLP Loop through multiplicand values +00000000000003F0 07FD 321 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-021-multadd.asm: Test IEEE Multiply And Add 09 Oct 2016 08:59:54 Page 9 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 323 *********************************************************************** + 324 * + 325 * Perform Multiply And Add using provided short BFP input triples. + 326 * This set of tests triggers IEEE exceptions Overflow, Underflow, and + 327 * Inexact and collects both trap and non-trap results. + 328 * + 329 * Four results are generated for each input: one RRE with all + 330 * exceptions non-trappable, a second RRE with all exceptions trappable, + 331 * a third RXE with all exceptions non-trappable, a fourth RXE with all + 332 * exceptions trappable, + 333 * + 334 * The product and FPCR are stored for each result. + 335 * + 336 *********************************************************************** + + +00000000000003F2 9823 A000 0000000000000000 338 SBFPF LM R2,R3,0(R10) Get count and address of test input values +00000000000003F6 9878 A008 0000000000000008 339 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000003FA 1222 340 LTR R2,R2 Any test cases? +00000000000003FC 078D 341 BZR R13 ..No, return to caller +00000000000003FE 0DC0 342 BASR R12,0 Set top of loop + 343 * +0000000000000400 B29D F27C 000000000000027C 344 LFPC FPCREGNT Set exceptions non-trappable +0000000000000404 7840 3000 0000000000000000 345 LE FPR4,0(,R3) Get short BFP multiplicand +0000000000000408 7810 3004 0000000000000004 346 LE FPR1,1*4(,R3) Get short BFP multiplier +000000000000040C 7880 3008 0000000000000008 347 LE FPR8,2*4(,R3) Get short BFP addend +0000000000000410 B30E 8041 348 MAEBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE +0000000000000414 7080 7000 0000000000000000 349 STE FPR8,0(,R7) Store short BFP product-sum +0000000000000418 B29C 8000 0000000000000000 350 STFPC 0(R8) Store resulting FPCR flags and DXC + 351 * +000000000000041C B29D F280 0000000000000280 352 LFPC FPCREGTR Set exceptions trappable +0000000000000420 7880 3008 0000000000000008 353 LE FPR8,2*4(,R3) Reload short BFP addend + 354 * ..multiplier is still in FPR1, + 355 * ..multiplicand is still in FPR4 +0000000000000424 B30E 8041 356 MAEBR FPR8,FPR4,FPR1 Multiply short FPR8 by FPR1 RRE +0000000000000428 7080 7004 0000000000000004 357 STE FPR8,1*4(,R7) Store short BFP product-sum +000000000000042C B29C 8004 0000000000000004 358 STFPC 4(R8) Store resulting FPCR flags and DXC + 359 * +0000000000000430 B29D F27C 000000000000027C 360 LFPC FPCREGNT Set exceptions non-trappable +0000000000000434 7880 3008 0000000000000008 361 LE FPR8,2*4(,R3) Reload short BFP addend + 362 * ..multiplicand is still in FPR4 +0000000000000438 ED40 3004 800E 0000000000000004 363 MAEB FPR8,FPR4,4(,R3) Mult. FPR4 by multiplier, add FPR8 RXE +000000000000043E 7080 7008 0000000000000008 364 STE FPR8,2*4(,R7) Store short BFP product +0000000000000442 B29C 8008 0000000000000008 365 STFPC 8(R8) Store resulting FPCR flags and DXC + 366 * +0000000000000446 B29D F280 0000000000000280 367 LFPC FPCREGTR Set exceptions trappable +000000000000044A 7880 3008 0000000000000008 368 LE FPR8,2*4(,R3) Reload short BFP addend + 369 * ..multiplicand is still in FPR4 +000000000000044E ED40 3004 800E 0000000000000004 370 MAEB FPR8,FPR4,4(,R3) Mult. FPR4 by multiplier, add FPR8 RXE +0000000000000454 7080 700C 000000000000000C 371 STE FPR8,3*4(,R7) Store short BFP product +0000000000000458 B29C 800C 000000000000000C 372 STFPC 12(R8) Store resulting FPCR flags and DXC + 373 * + ASMA Ver. 0.2.0 bfp-021-multadd.asm: Test IEEE Multiply And Add 09 Oct 2016 08:59:54 Page 10 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +000000000000045C 4130 300C 000000000000000C 374 LA R3,3*4(,R3) Point to next input value trible +0000000000000460 4170 7010 0000000000000010 375 LA R7,4*4(,R7) Point to next product result set +0000000000000464 4180 8010 0000000000000010 376 LA R8,4*4(,R8) Point to next FPCR result set +0000000000000468 062C 377 BCTR R2,R12 Convert next input value. +000000000000046A 07FD 378 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-021-multadd.asm: Test IEEE Multiply And Add 09 Oct 2016 08:59:54 Page 11 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 380 *********************************************************************** + 381 * + 382 * Perform Multiply And Add using provided short BFP input triples. + 383 * This set of tests exhaustively tests all rounding modes available for + 384 * Multiply And Add. The rounding mode can only be specified in the + 385 * FPC. + 386 * + 387 * All five FPC rounding modes are tested because the preceeding tests, + 388 * using rounding mode RNTE, do not often create results that require + 389 * rounding. + 390 * + 391 * Two results are generated for each input and rounding mode: one RRE + 392 * and one RXE. Traps are disabled for all rounding mode tests. + 393 * + 394 * The product and FPCR are stored for each test. + 395 * + 396 *********************************************************************** + + +000000000000046C 9823 A000 0000000000000000 398 SBFPRM LM R2,R3,0(R10) Get count and address of test input values +0000000000000470 9878 A008 0000000000000008 399 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000474 1222 400 LTR R2,R2 Any test cases? +0000000000000476 078D 401 BZR R13 ..No, return to caller +0000000000000478 1711 402 XR R1,R1 Zero register 1 for use in IC/STC/indexing +000000000000047A 0DC0 403 BASR R12,0 Set top of test case loop + 404 +000000000000047C 4150 0005 0000000000000005 405 LA R5,FPCMCT Get count of FPC modes to be tested +0000000000000480 0D90 406 BASR R9,0 Set top of rounding mode outer loop + 407 * +0000000000000482 4315 F64F 000000000000064F 408 IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode + 409 * +0000000000000486 B29D F27C 000000000000027C 410 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000048A B2B8 1000 0000000000000000 411 SRNMB 0(R1) Set FPC Rounding Mode +000000000000048E 7840 3000 0000000000000000 412 LE FPR4,0(,R3) Get short BFP multiplicand +0000000000000492 7810 3004 0000000000000004 413 LE FPR1,4(,R3) Get short BFP multiplier +0000000000000496 7880 3008 0000000000000008 414 LE FPR8,8(,R3) Get short BFP addend +000000000000049A B30E 8041 415 MAEBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE +000000000000049E 7080 7000 0000000000000000 416 STE FPR8,0(,R7) Store short BFP product-sum +00000000000004A2 B29C 8000 0000000000000000 417 STFPC 0(R8) Store resulting FPCR flags and DXC + 418 * +00000000000004A6 B29D F27C 000000000000027C 419 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000004AA B2B8 1000 0000000000000000 420 SRNMB 0(R1) Set FPC Rounding Mode +00000000000004AE 7880 3008 0000000000000008 421 LE FPR8,8(,R3) Get short BFP addend + 422 * ..multiplicand is still in FPR4 +00000000000004B2 ED40 3004 800E 0000000000000004 423 MAEB FPR8,FPR4,4(,R3) Mult. FPR4 by multiplier, add FPR8 RXE +00000000000004B8 7080 7004 0000000000000004 424 STE FPR8,4(,R7) Store short BFP product-sum +00000000000004BC B29C 8004 0000000000000004 425 STFPC 4(R8) Store resulting FPCR flags and DXC + 426 * +00000000000004C0 4170 7008 0000000000000008 427 LA R7,2*4(,R7) Point to next product result set +00000000000004C4 4180 8008 0000000000000008 428 LA R8,2*4(,R8) Point to next FPCR result area + 429 * +00000000000004C8 0659 430 BCTR R5,R9 Iterate to next FPC mode for this input + ASMA Ver. 0.2.0 bfp-021-multadd.asm: Test IEEE Multiply And Add 09 Oct 2016 08:59:54 Page 12 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 431 * + 432 * End of FPC modes to be tested. Advance to next test case. We will + 433 * skip eight bytes of result area so that each set of five result + 434 * value pairs starts at a memory address ending in zero for the + 435 * convenience of memory dump review. + 436 * +00000000000004CA 4130 300C 000000000000000C 437 LA R3,3*4(,R3) Point to next input value pair triple +00000000000004CE 4170 7008 0000000000000008 438 LA R7,8(,R7) Skip to start of next result set +00000000000004D2 4180 8008 0000000000000008 439 LA R8,8(,R8) Skip to start of next FPCR result set +00000000000004D6 062C 440 BCTR R2,R12 Advance to the next input pair + 441 * +00000000000004D8 07FD 442 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-021-multadd.asm: Test IEEE Multiply And Add 09 Oct 2016 08:59:54 Page 13 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 444 *********************************************************************** + 445 * + 446 * Perform Multiply And Add using provided long BFP inputs. This set + 447 * of tests checks NaN propagation, operations on values that are not + 448 * finite numbers, and other basic tests. This set generates results + 449 * that can be validated against Figure 19-24 on page 19-39 of + 450 * SA22-7832-10. + 451 * + 452 * Four results are generated for each input: one RRE with all + 453 * exceptions non-trappable, a second RRE with all exceptions trappable, + 454 * a third RXE with all exceptions non-trappable, a fourth RXE with all + 455 * exceptions trappable. + 456 * + 457 * Because this is a three-operand instruction, validation against + 458 * Figure 19-24, effectively an 8 x 8 x 8 table, will generate a + 459 * phenomonal set of results. Namely 512 results of 16 bytes each + 460 * plus 512 FPCR contents of 16 bytes each. + 461 * + 462 * The product and FPCR are stored for each result. + 463 * + 464 *********************************************************************** + + +00000000000004DA 466 LBFPNF DS 0H BFP long non-finite values tests +00000000000004DA 9823 A000 0000000000000000 467 LM R2,R3,0(R10) Get count and addr of multiplicand values +00000000000004DE 9889 A008 0000000000000008 468 LM R8,R9,8(R10) Get address of result area and flag area. +00000000000004E2 1222 469 LTR R2,R2 Any test cases? +00000000000004E4 078D 470 BZR R13 ..No, return to caller + 471 * +00000000000004E6 472 LBFPNFLP DS 0H Top of outer loop - Multiplicand +00000000000004E6 9845 A000 0000000000000000 473 LM R4,R5,0(R10) Get count and start of multiplier values + 474 * ..which are the same as the multiplicands +00000000000004EA 0DC0 475 BASR R12,0 Set top of middle loop + 476 * +00000000000004EC 477 DS 0H Top of middle loop - multiplier +00000000000004EC 9867 A000 0000000000000000 478 LM R6,R7,0(R10) Get count and start of addend values + 479 * ..which are the same as the multiplicands +00000000000004F0 0D10 480 BASR R1,0 Set top of inner loop - addend + 481 * + 482 * Multiply and Add: R1 = R3 x R2 + R1 + 483 * +00000000000004F2 7840 3000 0000000000000000 484 LE FPR4,0(,R3) Get long BFP multiplicand +00000000000004F6 7810 5000 0000000000000000 485 LE FPR1,0(,R5) Get long BFP multiplier + 486 * +00000000000004FA B29D F27C 000000000000027C 487 LFPC FPCREGNT Set exceptions non-trappable +00000000000004FE 6880 7000 0000000000000000 488 LD FPR8,0(,R7) Get long BFP addend +0000000000000502 B31E 8041 489 MADBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE +0000000000000506 6080 8000 0000000000000000 490 STD FPR8,0(,R8) Store long BFP product-sum +000000000000050A B29C 9000 0000000000000000 491 STFPC 0(R9) Store resulting FPCR flags and DXC + 492 * +000000000000050E B29D F280 0000000000000280 493 LFPC FPCREGTR Set exceptions trappable +0000000000000512 7880 7000 0000000000000000 494 LE FPR8,0(,R7) Get long BFP addend + ASMA Ver. 0.2.0 bfp-021-multadd.asm: Test IEEE Multiply And Add 09 Oct 2016 08:59:54 Page 14 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000516 B31E 8041 495 MADBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE +000000000000051A 6080 8008 0000000000000008 496 STD FPR8,1*8(,R8) Store long BFP product-sum +000000000000051E B29C 9004 0000000000000004 497 STFPC 1*4(R9) Store resulting FPCR flags and DXC + 498 * +0000000000000522 B29D F27C 000000000000027C 499 LFPC FPCREGNT Set exceptions non-trappable +0000000000000526 7880 7000 0000000000000000 500 LE FPR8,0(,R7) Get long BFP addend +000000000000052A ED40 5000 801E 0000000000000000 501 MADB FPR8,FPR4,0(,R5) Mult. FPR4 by multiplier, add FPR8 RXE +0000000000000530 6080 8010 0000000000000010 502 STD FPR8,2*8(,R8) Store long BFP product-sum +0000000000000534 B29C 9008 0000000000000008 503 STFPC 2*4(R9) Store resulting FPCR flags and DXC + 504 * +0000000000000538 B29D F280 0000000000000280 505 LFPC FPCREGTR Set exceptions trappable +000000000000053C 7880 7000 0000000000000000 506 LE FPR8,0(,R7) Get long BFP addend +0000000000000540 ED40 5000 801E 0000000000000000 507 MADB FPR8,FPR4,0(,R5) Mult. FPR4 by multiplier, add FPR8 RXE +0000000000000546 6080 8018 0000000000000018 508 STD FPR8,3*8(,R8) Store long BFP product-sum +000000000000054A B29C 900C 000000000000000C 509 STFPC 3*4(R9) Store resulting FPCR flags and DXC + 510 * +000000000000054E 4180 8020 0000000000000020 511 LA R8,4*8(,R8) Point to next product-sum result area +0000000000000552 4190 9010 0000000000000010 512 LA R9,4*4(,R9) Point to next FPCR contents area +0000000000000556 4170 7008 0000000000000008 513 LA R7,8(,R7) Point to next addend value +000000000000055A 0661 514 BCTR R6,R1 Loop through addend values + 515 * +000000000000055C 4150 5008 0000000000000008 516 LA R5,8(,R5) Point to next multiplier +0000000000000560 064C 517 BCTR R4,R12 Loop through multiplier values + 518 * +0000000000000562 4130 3008 0000000000000008 519 LA R3,8(,R3) Point to next multiplicand +0000000000000566 4620 F4E6 00000000000004E6 520 BCT R2,LBFPNFLP Loop through multiplicand values +000000000000056A 07FD 521 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-021-multadd.asm: Test IEEE Multiply And Add 09 Oct 2016 08:59:54 Page 15 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 523 *********************************************************************** + 524 * + 525 * Perform Multiply And Add using provided long BFP input triples. This + 526 * set of tests triggers IEEE exceptions Overflow, Underflow, and + 527 * Inexact and collects non-trap and trap results. + 528 * + 529 * Four results are generated for each input: one RRE with all + 530 * exceptions non-trappable, a second RRE with all exceptions trappable, + 531 * a third RXE with all exceptions non-trappable, a fourth RXE with all + 532 * exceptions trappable, + 533 * + 534 * The product and FPCR are stored for each result. + 535 * + 536 *********************************************************************** + + +000000000000056C 9823 A000 0000000000000000 538 LBFPF LM R2,R3,0(R10) Get count and address of test input values +0000000000000570 9878 A008 0000000000000008 539 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000574 1222 540 LTR R2,R2 Any test cases? +0000000000000576 078D 541 BZR R13 ..No, return to caller +0000000000000578 0DC0 542 BASR R12,0 Set top of loop + 543 * +000000000000057A B29D F27C 000000000000027C 544 LFPC FPCREGNT Set exceptions non-trappable +000000000000057E 6840 3000 0000000000000000 545 LD FPR4,0(,R3) Get long BFP multiplicand +0000000000000582 6810 3008 0000000000000008 546 LD FPR1,8(,R3) Get long BFP multiplier +0000000000000586 6880 3010 0000000000000010 547 LD FPR8,16(,R3) Get long BFP addend +000000000000058A B31E 8041 548 MADBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE +000000000000058E 6080 7000 0000000000000000 549 STD FPR8,0(,R7) Store long BFP product +0000000000000592 B29C 8000 0000000000000000 550 STFPC 0(R8) Store resulting FPCR flags and DXC + 551 * +0000000000000596 B29D F280 0000000000000280 552 LFPC FPCREGTR Set exceptions trappable +000000000000059A 6880 3010 0000000000000010 553 LD FPR8,16(,R3) Reload long BFP addend + 554 * ..multiplier is still in FPR1, + 555 * ..multiplicand is still in FFR4 +000000000000059E B31E 8041 556 MADBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE +00000000000005A2 6080 7008 0000000000000008 557 STD FPR8,8(,R7) Store long BFP product-sum +00000000000005A6 B29C 8004 0000000000000004 558 STFPC 1*4(R8) Store resulting FPCR flags and DXC + 559 * +00000000000005AA B29D F27C 000000000000027C 560 LFPC FPCREGNT Set exceptions non-trappable +00000000000005AE 6880 3010 0000000000000010 561 LD FPR8,16(,R3) Reload long BFP addend + 562 * ..multiplicand is still in FFR4 +00000000000005B2 ED40 3008 801E 0000000000000008 563 MADB FPR8,FPR4,8(,R3) Mult. FPR4 by multiplier, add FPR8 RXE +00000000000005B8 6080 7010 0000000000000010 564 STD FPR8,2*8(,R7) Store long BFP product-sum +00000000000005BC B29C 8008 0000000000000008 565 STFPC 2*4(R8) Store resulting FPCR flags and DXC + 566 * +00000000000005C0 B29D F280 0000000000000280 567 LFPC FPCREGTR Set exceptions trappable +00000000000005C4 6880 3010 0000000000000010 568 LD FPR8,16(,R3) Reload long BFP addend + 569 * ..multiplicand is still in FFR4 +00000000000005C8 ED40 3008 801E 0000000000000008 570 MADB FPR8,FPR4,8(,R3) Mult. FPR4 by multiplier, add FPR8 RXE +00000000000005CE 6080 7018 0000000000000018 571 STD FPR8,3*8(,R7) Store long BFP product-sum +00000000000005D2 B29C 800C 000000000000000C 572 STFPC 3*4(R8) Store resulting FPCR flags and DXC + 573 * + ASMA Ver. 0.2.0 bfp-021-multadd.asm: Test IEEE Multiply And Add 09 Oct 2016 08:59:54 Page 16 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000005D6 4130 3018 0000000000000018 574 LA R3,3*8(,R3) Point to next input value triple +00000000000005DA 4170 7020 0000000000000020 575 LA R7,4*8(,R7) Point to next product-sum result set +00000000000005DE 4180 8010 0000000000000010 576 LA R8,4*4(,R8) Point to next FPCR result area +00000000000005E2 062C 577 BCTR R2,R12 Convert next input value. +00000000000005E4 07FD 578 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-021-multadd.asm: Test IEEE Multiply And Add 09 Oct 2016 08:59:54 Page 17 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 580 *********************************************************************** + 581 * + 582 * Perform Multiply using provided long BFP input pairs. This set of + 583 * tests exhaustively tests all rounding modes available for Multiply. + 584 * The rounding mode can only be specified in the FPC. + 585 * + 586 * All five FPC rounding modes are tested because the preceeding tests, + 587 * using rounding mode RNTE, do not often create results that require + 588 * rounding. + 589 * + 590 * Two results are generated for each input and rounding mode: one RRE + 591 * and one RXE. Traps are disabled for all rounding mode tests. + 592 * + 593 * The product and FPCR are stored for each result. + 594 * + 595 *********************************************************************** + + +00000000000005E6 9823 A000 0000000000000000 597 LBFPRM LM R2,R3,0(R10) Get count and address of test input values +00000000000005EA 9878 A008 0000000000000008 598 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000005EE 1222 599 LTR R2,R2 Any test cases? +00000000000005F0 078D 600 BZR R13 ..No, return to caller +00000000000005F2 1711 601 XR R1,R1 Zero register 1 for use in IC/STC/indexing +00000000000005F4 0DC0 602 BASR R12,0 Set top of test case loop + 603 +00000000000005F6 4150 0005 0000000000000005 604 LA R5,FPCMCT Get count of FPC modes to be tested +00000000000005FA 0D90 605 BASR R9,0 Set top of rounding mode loop + 606 * +00000000000005FC 4315 F64F 000000000000064F 607 IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode + 608 * +0000000000000600 B29D F27C 000000000000027C 609 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000604 B2B8 1000 0000000000000000 610 SRNMB 0(R1) Set FPC Rounding Mode +0000000000000608 6840 3000 0000000000000000 611 LD FPR4,0(,R3) Get long BFP multiplicand +000000000000060C 6810 3008 0000000000000008 612 LD FPR1,8(,R3) Get long BFP multiplier +0000000000000610 6880 3010 0000000000000010 613 LD FPR8,16(,R3) Get long BFP addend +0000000000000614 B31E 8041 614 MADBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE +0000000000000618 6080 7000 0000000000000000 615 STD FPR8,0(,R7) Store long BFP product-sum +000000000000061C B29C 8000 0000000000000000 616 STFPC 0(R8) Store resulting FPCR flags and DXC + 617 * +0000000000000620 B29D F27C 000000000000027C 618 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000624 B2B8 1000 0000000000000000 619 SRNMB 0(R1) Set FPC Rounding Mode +0000000000000628 6880 3010 0000000000000010 620 LD FPR8,16(,R3) Reload long BFP addend +000000000000062C ED40 3008 801E 0000000000000008 621 MADB FPR8,FPR4,8(,R3) Multiply long FPR8 by multiplier RXE +0000000000000632 6080 7008 0000000000000008 622 STD FPR8,8(,R7) Store long BFP product-sum +0000000000000636 B29C 8004 0000000000000004 623 STFPC 4(R8) Store resulting FPCR flags and DXC + 624 * +000000000000063A 4170 7010 0000000000000010 625 LA R7,2*8(,R7) Point to next product result set +000000000000063E 4180 8008 0000000000000008 626 LA R8,2*4(,R8) Point to next FPCR result area + 627 * +0000000000000642 0659 628 BCTR R5,R9 Iterate to next FPC mode + 629 * + 630 * End of FPC modes to be tested. Advance to next test case. We will + ASMA Ver. 0.2.0 bfp-021-multadd.asm: Test IEEE Multiply And Add 09 Oct 2016 08:59:54 Page 18 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 631 * skip eight bytes of FPCR result area so that each set of five result + 632 * FPCR contents pairs starts at a memory address ending in zero for the + 633 * convenience of memory dump review. + 634 * +0000000000000644 4130 3018 0000000000000018 635 LA R3,3*8(,R3) Point to next input value triple +0000000000000648 4180 8008 0000000000000008 636 LA R8,8(,R8) Skip to start of next FPCR result area +000000000000064C 062C 637 BCTR R2,R12 Multiply next input value lots of times + 638 * +000000000000064E 07FD 639 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-021-multadd.asm: Test IEEE Multiply And Add 09 Oct 2016 08:59:54 Page 19 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 641 *********************************************************************** + 642 * + 643 * Table of FPC rounding modes to test product rounding modes. + 644 * + 645 * The Set BFP Rounding Mode does allow specification of the FPC + 646 * rounding mode as an address, so we shall index into a table of + 647 * BFP rounding modes without bothering with Execute. + 648 * + 649 *********************************************************************** + + + 651 * + 652 * Rounding modes that may be set in the FPCR. The FPCR controls + 653 * rounding of the product. + 654 * + 655 * These are indexed directly by the loop counter, which counts down. + 656 * So the modes are listed in reverse order here. + 657 * +0000000000000650 658 FPCMODES DS 0C +0000000000000650 07 659 DC AL1(7) RFS, Round for shorter precision +0000000000000651 03 660 DC AL1(3) RM, Round to -infinity +0000000000000652 02 661 DC AL1(2) RP, Round to +infinity +0000000000000653 01 662 DC AL1(1) RZ, Round to zero +0000000000000654 00 663 DC AL1(0) RNTE, Round to Nearest, ties to even + 0000000000000005 0000000000000001 664 FPCMCT EQU *-FPCMODES Count of FPC Modes to be tested + 665 * + ASMA Ver. 0.2.0 bfp-021-multadd.asm: Test IEEE Multiply And Add 09 Oct 2016 08:59:54 Page 20 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 667 *********************************************************************** + 668 * + 669 * Short BFP test data sets for Multiply And Add testing. + 670 * + 671 * The first test data set is used for tests of basic functionality, + 672 * NaN propagation, and results from operations involving other than + 673 * finite numbers. The same set of eight values is used as the + 674 * multiplicand, multiplier, and addend, resulting in 8 x 8 x 8 or + 675 * 512 test cases. + 676 * + 677 * The second test data set is used for testing boundary conditions + 678 * using two finite non-zero values. Each possible condition code + 679 * and type of result (normal, scaled, etc) is created by members of + 680 * this test data set. + 681 * + 682 * The third test data set is used for exhaustive testing of final + 683 * results across the five rounding modes available for the Multiply + 684 * instruction. + 685 * + 686 * The strategy for predictable rounding mode testing is to use a + 687 * multiplicand with some one-bits in the low-order byte and multiply + 688 * that by 1/16 (0.0625). In BFP, this will have the effect of shifting + 689 * the low-order byte out of the target precision representation and + 690 * into the high-order portion of the bits that control rounding. The + 691 * input low-order byte will be determined by the rounding desired. + 692 * + 693 *********************************************************************** + + + 695 *********************************************************************** + 696 * + 697 * First input test data set, to test operations using non-finite or + 698 * zero inputs. Member values chosen to validate Figure 19-24 on page + 699 * 19-39 of SA22-7832-10. Each value in this table is used as the + 700 * multiplicand, multiplier, and addend. Eight entries menas 512 result + 701 * sets. + 702 * + 703 *********************************************************************** + + +0000000000000658 705 SBFPNFIN DS 0F Inputs for short BFP non-finite tests +0000000000000658 FF800000 706 DC X'FF800000' -inf +000000000000065C C0000000 707 DC X'C0000000' -2.0 +0000000000000660 80000000 708 DC X'80000000' -0 +0000000000000664 00000000 709 DC X'00000000' +0 +0000000000000668 40000000 710 DC X'40000000' +2.0 +000000000000066C 7F800000 711 DC X'7F800000' +inf +0000000000000670 FFCB0000 712 DC X'FFCB0000' -QNaN +0000000000000674 7F8A0000 713 DC X'7F8A0000' +SNaN + 0000000000000008 0000000000000001 714 SBFPNFCT EQU (*-SBFPNFIN)/4 Count of short BFP in list + ASMA Ver. 0.2.0 bfp-021-multadd.asm: Test IEEE Multiply And Add 09 Oct 2016 08:59:54 Page 21 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 716 *********************************************************************** + 717 * + 718 * Second input test data set. These are finite triples intended to + 719 * trigger overflow, underflow, and inexact exceptions. Each triple is + 720 * added twice, once non-trappable and once trappable. Trappable + 721 * overflow or underflow yields a scaled result. Trappable inexact + 722 * will show whether the Incremented DXC code is returned. + 723 * + 724 * The following test cases are required: + 725 * 1. Overflow + 726 * 2. Underflow - normal inputs + 727 * 3. Underflow - subnormal inputs + 728 * 4. Normal - from subnormal inputs + 729 * 5. Inexact - incremented + 730 * 6. Inexact - truncated + 731 * + 732 *********************************************************************** + + +0000000000000678 734 SBFPIN DS 0F Inputs for short BFP finite tests + 735 * + 736 * Overflow on multiplication two ways - once on the multiply, once + 737 * on the addition following the multiplication. + 738 * +0000000000000678 7F7FFFFF 739 DC X'7F7FFFFF' +Nmax multiplicand +000000000000067C FF7FFFFF 740 DC X'FF7FFFFF' -Nmax multiplier +0000000000000680 7F7FFFFF 741 DC X'7F7FFFFF' Big positive value, won't show up. + 742 * +0000000000000684 7F7FFFFF 743 DC X'7F7FFFFF' +Nmax multiplicand +0000000000000688 3F800000 744 DC X'3F800000' +1.0 multiplier +000000000000068C 7F7FFFFF 745 DC X'7F7FFFFF' +Nmax addend, triggers overflow + 746 * + 747 * Underflow from product of normals. We will multiply a small normal + 748 * by 0.25 to generate a subnormal. We cannot add another normal + 749 * (positive or negative) and keep the result subnormal, so we will just + 750 * add a subnormal. + 751 * +0000000000000690 00FFFFFF 752 DC X'00FFFFFF' Very small normal number +0000000000000694 3E800000 753 DC X'3E800000' 0.25, creates subnormal +0000000000000698 00000001 754 DC X'00000001' +Dmin, will appear in result + 755 * + 756 * Underflow from the product of a subnormal and a normal. + 757 * +000000000000069C 3F000000 758 DC X'3F000000' +0.5 +00000000000006A0 007FFFFF 759 DC X'007FFFFF' +Dmax Subnormal +00000000000006A4 00000001 760 DC X'00000001' +Dmin, will appear in result + 761 * + 762 * We cannot generate a normal result from product of subnormals + 763 * because the result will be smaller than both the multiplicand and the + 764 * multiplier. So we'll try multiplying +Dmax by 2. The result should + 765 * be +Nmin plus the addend. + 766 * + ASMA Ver. 0.2.0 bfp-021-multadd.asm: Test IEEE Multiply And Add 09 Oct 2016 08:59:54 Page 22 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000006A8 007FFFFF 767 DC X'007FFFFF' +Dmax +00000000000006AC 40000000 768 DC X'40000000' +2.0 +00000000000006B0 00400000 769 DC X'00400000' +Dmax + 770 * + 771 * Multiply a value from 1.0 such that the added digits are to the right + 772 * of the right-most bit in the stored significand. The result will be + 773 * inexact, and incremented will be determined by the value of the + 774 * bits in the multiplier. We will add 0.5 to this product because + 775 * that value will not cause renormalization. Renormalization would + 776 * shift the rounding bits one to the right, messing up the expected + 777 * rounding. + 778 * +00000000000006B4 3F80000C 779 DC X'3F80000C' Multiplicand 1.000001430511474609375 +00000000000006B8 3F880000 780 DC X'3F880000' Multiplier 1.0625 (1 + 1/16) +00000000000006BC 3F000000 781 DC X'3F000000' Plus 0.5 + 782 *..nearest is away from zero, incremented. + 783 * +00000000000006C0 3F800007 784 DC X'3F800007' Multiplicand 1.00000083446502685546875 +00000000000006C4 3F880000 785 DC X'3F880000' Multiplier 1.0625 (1 + 1/16) +00000000000006C8 3F000000 786 DC X'3F000000' Plus 0.5 + 787 *..nearest is toward zero, truncated + 788 * + 0000000000000007 0000000000000001 789 SBFPCT EQU (*-SBFPIN)/4/3 Count of short BFP in list + + + + 791 *********************************************************************** + 792 * + 793 * Third input test data set. These are finite triples intended to + 794 * test all combinations of rounding mode for the product and the + 795 * remainder. Values are chosen to create a requirement to round + 796 * to the target precision after the computation and to generate + 797 * varying results depending on the rounding mode in the FPCR. + 798 * + 799 * The result set will have cases that represent each of the following + 800 * + 801 * 1. Positive, nearest magnitude is toward zero. + 802 * 2. Negative, nearest magnitude is toward zero. + 803 * 3. Positive, nearest magnitude is away from zero. + 804 * 4. Negative, nearest magnitude is away from zero. + 805 * 5. Positive, tie, nearest even has greater magnitude + 806 * 6. Negative, tie, nearest even has greater magnitude + 807 * 7. Positive, tie, nearest even has lower magnitude + 808 * 8. Negative, tie, nearest even has lower magnitude + 809 * + 810 * Round For Shorter precision correctness can be determined from the + 811 * above test cases. + 812 * + 813 *********************************************************************** + + +00000000000006CC 815 SBFPINRM DS 0F Inputs for short BFP rounding testing + ASMA Ver. 0.2.0 bfp-021-multadd.asm: Test IEEE Multiply And Add 09 Oct 2016 08:59:54 Page 23 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 816 * + 817 * Multiply a value from 1.0 such that the added digits are to the right + 818 * of the right-most bit in the stored significand. The result will be + 819 * inexact, and incremented will be determined by the value of the + 820 * bits in the multiplier. + 821 * +00000000000006CC 3F800007 822 DC X'3F800007' Multiplicand +1.00000083446502685546875 +00000000000006D0 3F880000 823 DC X'3F880000' Multiplier 1.0625 (1/16) +00000000000006D4 3F000000 824 DC X'3F000000' Addend 0.5 +00000000000006D8 BF800007 825 DC X'BF800007' Multiplicand -1.00000083446502685546875 +00000000000006DC 3F880000 826 DC X'3F880000' Multiplier 1.0625 (1/16) +00000000000006E0 BF000000 827 DC X'BF000000' Addend -0.5 + 828 *..nearest is toward zero, truncated + 829 * +00000000000006E4 3F80000C 830 DC X'3F80000C' Multiplicand +1.000001430511474609375 +00000000000006E8 3F880000 831 DC X'3F880000' Multiplier 1.0625 (1/16) +00000000000006EC 3F000000 832 DC X'3F000000' Addend 0.5 +00000000000006F0 BF80000C 833 DC X'BF80000C' Multiplicand -1.000001430511474609375 +00000000000006F4 3F880000 834 DC X'3F880000' Multiplier 1.0625 (1/16) +00000000000006F8 BF000000 835 DC X'BF000000' Addend -0.5 + 836 *..nearest is away from zero, incremented. + 837 * +00000000000006FC 3F800008 838 DC X'3F800008' Multiplicand +1.000000476837158203125 +0000000000000700 3F880000 839 DC X'3F880000' Multiplier 1.0625 (1/16) +0000000000000704 3F000000 840 DC X'3F000000' Addend 0.5 +0000000000000708 BF800008 841 DC X'BF800008' Multiplicand -1.000000476837158203125 +000000000000070C 3F880000 842 DC X'3F880000' Multiplier 1.0625 (1/16) +0000000000000710 BF000000 843 DC X'BF000000' Addend -0.5 + 844 *..nearest is a tie, nearest even has lower magnitude + 845 * +0000000000000714 3F800018 846 DC X'3F800018' Multiplicand +1.000002384185791015625 +0000000000000718 3F880000 847 DC X'3F880000' Multiplier 1.0625 (1/16) +000000000000071C 3F000000 848 DC X'3F000000' Addend 0.5 +0000000000000720 BF800018 849 DC X'BF800018' Multiplicand -1.000002384185791015625 +0000000000000724 3F880000 850 DC X'3F880000' Multiplier 1.0625 (1/16) +0000000000000728 BF000000 851 DC X'BF000000' Addend -0.5 + 852 *..nearest is a tie, nearest even has greater magnitude + 853 * + 0000000000000008 0000000000000001 854 SBFPRMCT EQU (*-SBFPINRM)/4/3 Count of short BFP rounding tests + ASMA Ver. 0.2.0 bfp-021-multadd.asm: Test IEEE Multiply And Add 09 Oct 2016 08:59:54 Page 24 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 856 *********************************************************************** + 857 * + 858 * Long BFP test data sets for Multiply And Add testing. + 859 * + 860 * The first test data set is used for tests of basic functionality, + 861 * NaN propagation, and results from operations involving other than + 862 * finite numbers. + 863 * + 864 * The second test data set is used for testing boundary conditions + 865 * using two finite non-zero values. Each possible condition code + 866 * and type of result (normal, scaled, etc) is created by members of + 867 * this test data set. + 868 * + 869 * The third test data set is used for exhaustive testing of final + 870 * results across the five rounding modes available for the Add + 871 * instruction. + 872 * + 873 * See the Short BFP test cases header for a discussion of test case + 874 * selection for rounding mode test case values. + 875 * + 876 *********************************************************************** + + + 878 *********************************************************************** + 879 * + 880 * First input test data set, to test operations using non-finite or + 881 * zero inputs. Member values chosen to validate Figure 19-24 on page + 882 * 19-39 of SA22-7832-10. Each value in this table is used as the + 883 * multiplicand, multiplier, and addend. Eight entries menas 512 result + 884 * sets. + 885 * + 886 *********************************************************************** + + +000000000000072C 888 LBFPNFIN DS 0F Inputs for long BFP testing +000000000000072C FFF00000 00000000 889 DC X'FFF0000000000000' -inf +0000000000000734 C0000000 00000000 890 DC X'C000000000000000' -2.0 +000000000000073C 80000000 00000000 891 DC X'8000000000000000' -0 +0000000000000744 00000000 00000000 892 DC X'0000000000000000' +0 +000000000000074C 40000000 00000000 893 DC X'4000000000000000' +2.0 +0000000000000754 7FF00000 00000000 894 DC X'7FF0000000000000' +inf +000000000000075C FFF8B000 00000000 895 DC X'FFF8B00000000000' -QNaN +0000000000000764 7FF0A000 00000000 896 DC X'7FF0A00000000000' +SNaN + 0000000000000008 0000000000000001 897 LBFPNFCT EQU (*-LBFPNFIN)/8 Count of long BFP in list + + + + 899 *********************************************************************** + 900 * + 901 * Second input test data set. These are finite triples intended to + 902 * trigger overflow, underflow, and inexact exceptions. Each triples is + 903 * added twice, once non-trappable and once trappable. Trappable + ASMA Ver. 0.2.0 bfp-021-multadd.asm: Test IEEE Multiply And Add 09 Oct 2016 08:59:54 Page 25 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 904 * overflow or underflow yields a scaled result. Trappable inexact + 905 * will show whether the Incremented DXC code is returned. + 906 * + 907 * The following test cases are required: + 908 * 1. Overflow + 909 * 2. Underflow - normal inputs + 910 * 3. Underflow - subnormal inputs + 911 * 4. Normal - from subnormal inputs + 912 * 5. Inexact - incremented + 913 * 6. Inexact - truncated + 914 * + 915 *********************************************************************** + + +0000000000000770 917 LBFPIN DS 0D Inputs for long BFP finite tests + 918 * + 919 * Overflow on multiplication two ways. Once on the muliplication step, + 920 * and then a second time on the addition step. + 921 * +0000000000000770 7FEFFFFF FFFFFFFF 922 DC X'7FEFFFFFFFFFFFFF' +Nmax +0000000000000778 FFEFFFFF FFFFFFFF 923 DC X'FFEFFFFFFFFFFFFF' -Nmax +0000000000000780 3FF00000 00000000 924 DC X'3FF0000000000000' +1.0 + 925 * +0000000000000788 7FEFFFFF FFFFFFFF 926 DC X'7FEFFFFFFFFFFFFF' +Nmax +0000000000000790 3FF00000 00000000 927 DC X'3FF0000000000000' +1.0 +0000000000000798 7FEFFFFF FFFFFFFF 928 DC X'7FEFFFFFFFFFFFFF' +Nmax + 929 * + 930 * Underflow from product of normals. We will multiply a small normal + 931 * by 0.25 to generate a subnormal. We cannot add another normal + 932 * (positive or negative) and keep the result subnormal, so we will just + 933 * add a subnormal. + 934 * +00000000000007A0 001FFFFF FFFFFFFF 935 DC X'001FFFFFFFFFFFFF' Very small normal number +00000000000007A8 3FD00000 00000000 936 DC X'3FD0000000000000' 0.25, creates subnormal +00000000000007B0 00000000 00000001 937 DC X'0000000000000001' +Dmin, will appear in result + 938 * + 939 * Underflow from the product of a subnormal and a normal. + 940 * +00000000000007B8 3FE00000 00000000 941 DC X'3FE0000000000000' +0.5 +00000000000007C0 000FFFFF FFFFFFFF 942 DC X'000FFFFFFFFFFFFF' +Dmax subnormal +00000000000007C8 00000000 00000001 943 DC X'0000000000000001' +Dmin, will appear in result + 944 * + 945 * We cannot generate a normal result from product of subnormals + 946 * because the result will be smaller than both the multiplicand and the + 947 * multiplier. So we'll try multiplying +Dmax by 2. The result should + 948 * be +Nmin + 949 * +00000000000007D0 000FFFFF FFFFFFFF 950 DC X'000FFFFFFFFFFFFF' +Dmax +00000000000007D8 40000000 00000000 951 DC X'4000000000000000' +2.0, result should be normal +00000000000007E0 00080000 00000000 952 DC X'0008000000000000' A large subnormal + 953 * + 954 * Multiply a value from 1.0 such that the added digits are to the right + ASMA Ver. 0.2.0 bfp-021-multadd.asm: Test IEEE Multiply And Add 09 Oct 2016 08:59:54 Page 26 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 955 * of the right-most bit in the stored significand. The result will be + 956 * inexact, and incremented will be determined by the value of the + 957 * bits in the multiplier. + 958 * +00000000000007E8 3FF00000 0000000C 959 DC X'3FF000000000000C' Multiplicand +1, aka 1.0b0 +00000000000007F0 3FF10000 00000000 960 DC X'3FF1000000000000' Multiplier 1.0625 (1/16) +00000000000007F8 3FE00000 00000000 961 DC X'3FE0000000000000' +0.5 + 962 *..nearest is away from zero, incremented. + 963 * +0000000000000800 3FF00000 00000007 964 DC X'3FF0000000000007' Multiplicand +1, aka 1.0b0 +0000000000000808 3FF10000 00000000 965 DC X'3FF1000000000000' Multiplier 1.0625 (1/16) +0000000000000810 3FE00000 00000000 966 DC X'3FE0000000000000' +0.5 + 967 *..nearest is toward zero, truncated. + 968 * + 0000000000000007 0000000000000001 969 LBFPCT EQU (*-LBFPIN)/8/3 Count of long BFP triples in list + + + + 971 *********************************************************************** + 972 * + 973 * Third input test data set. These are finite triples intended to + 974 * test all combinations of rounding mode for the product and the + 975 * remainder. Values are chosen to create a requirement to round + 976 * to the target precision after the computation and to generate + 977 * varying results depending on the rounding mode in the FPCR. + 978 * + 979 * The result set will have cases that represent each of the following + 980 * + 981 * 1. Positive, nearest magnitude is toward zero. + 982 * 2. Negative, nearest magnitude is toward zero. + 983 * 3. Positive, nearest magnitude is away from zero. + 984 * 4. Negative, nearest magnitude is away from zero. + 985 * 5. Positive, tie, nearest even has greater magnitude + 986 * 6. Negative, tie, nearest even has greater magnitude + 987 * 7. Positive, tie, nearest even has lower magnitude + 988 * 8. Negative, tie, nearest even has lower magnitude + 989 * + 990 * Round For Shorter precision correctness can be determined from the + 991 * above test cases. + 992 * + 993 *********************************************************************** + + +0000000000000818 995 LBFPINRM DS 0F + 996 * + 997 * Multiply a value from 1.0 such that the added digits are to the right + 998 * of the right-most bit in the stored significand. The result will be + 999 * inexact, and incremented will be determined by the value of the + 1000 * bits in the multiplier. + 1001 * +0000000000000818 3FF00000 00000007 1002 DC X'3FF0000000000007' Multiplicand +0000000000000820 3FF10000 00000000 1003 DC X'3FF1000000000000' Multiplier 1.0625 (1/16) + ASMA Ver. 0.2.0 bfp-021-multadd.asm: Test IEEE Multiply And Add 09 Oct 2016 08:59:54 Page 27 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000828 3FE00000 00000000 1004 DC X'3FE0000000000000' +0.5 +0000000000000830 BFF00000 00000007 1005 DC X'BFF0000000000007' Multiplicand +0000000000000838 3FF10000 00000000 1006 DC X'3FF1000000000000' Multiplier 1.0625 (1/16) +0000000000000840 BFE00000 00000000 1007 DC X'BFE0000000000000' -0.5 + 1008 *..nearest is toward zero, truncated. + 1009 * +0000000000000848 3FF00000 0000000C 1010 DC X'3FF000000000000C' Multiplicand +0000000000000850 3FF10000 00000000 1011 DC X'3FF1000000000000' Multiplier 1.0625 (1/16) +0000000000000858 3FE00000 00000000 1012 DC X'3FE0000000000000' +0.5 +0000000000000860 BFF00000 0000000C 1013 DC X'BFF000000000000C' Multiplicand +0000000000000868 3FF10000 00000000 1014 DC X'3FF1000000000000' Multiplier 1.0625 (1/16) +0000000000000870 BFE00000 00000000 1015 DC X'BFE0000000000000' -0.5 + 1016 *..nearest is away from zero, incremented. + 1017 * +0000000000000878 3FF00000 00000008 1018 DC X'3FF0000000000008' Multiplicand +0000000000000880 3FF10000 00000000 1019 DC X'3FF1000000000000' Multiplier 1.0625 (1/16) +0000000000000888 3FE00000 00000000 1020 DC X'3FE0000000000000' +0.5 +0000000000000890 BFF00000 00000008 1021 DC X'BFF0000000000008' Multiplicand +0000000000000898 3FF10000 00000000 1022 DC X'3FF1000000000000' Multiplier 1.0625 (1/16) +00000000000008A0 BFE00000 00000000 1023 DC X'BFE0000000000000' -0.5 + 1024 *..nearest is a tie, nearest even has lower magnitude + 1025 * +00000000000008A8 3FF00000 00000018 1026 DC X'3FF0000000000018' Multiplicand +1, aka +1.0b0 +00000000000008B0 3FF10000 00000000 1027 DC X'3FF1000000000000' Multiplier 1.0625 (1/16) +00000000000008B8 3FE00000 00000000 1028 DC X'3FE0000000000000' +0.5 +00000000000008C0 BFF00000 00000018 1029 DC X'BFF0000000000018' Multiplicand -1, aka -1.0b0 +00000000000008C8 3FF10000 00000000 1030 DC X'3FF1000000000000' Multiplier 1.0625 (1/16) +00000000000008D0 BFE00000 00000000 1031 DC X'BFE0000000000000' -0.5 + 1032 *..nearest is a tie, nearest even has greater magnitude + 1033 * + 0000000000000008 0000000000000001 1034 LBFPRMCT EQU (*-LBFPINRM)/8/3 Count of long BFP rounding tests + ASMA Ver. 0.2.0 bfp-021-multadd.asm: Test IEEE Multiply And Add 09 Oct 2016 08:59:54 Page 28 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1036 * + 1037 * Locations for results + 1038 * + 0000000000001000 0000000000000001 1039 SBFPNFOT EQU STRTLABL+X'1000' Short non-finite BFP results + 1040 * ..room for 512 tests, 512 used + 0000000000003000 0000000000000001 1041 SBFPNFFL EQU STRTLABL+X'3000' FPCR flags and DXC from short BFP + 1042 * ..room for 512 tests, 512 used + 1043 * + 0000000000005000 0000000000000001 1044 SBFPOUT EQU STRTLABL+X'5000' Short BFP finite results + 1045 * ..room for 16 tests, 7 used + 0000000000005100 0000000000000001 1046 SBFPFLGS EQU STRTLABL+X'5100' FPCR flags and DXC from short BFP + 1047 * ..room for 16 tests, 7 used + 1048 * + 0000000000005200 0000000000000001 1049 SBFPRMO EQU STRTLABL+X'5200' Short BFP rounding mode test results + 1050 * ..Room for 16, 8 used. + 0000000000005500 0000000000000001 1051 SBFPRMOF EQU STRTLABL+X'5500' Short BFP rounding mode FPCR results + 1052 * ..Room for 16, 8 used. + 1053 * ..next location starts at X'5800' + 1054 * + 0000000000006000 0000000000000001 1055 LBFPNFOT EQU STRTLABL+X'6000' Long non-finite BFP results + 1056 * ..room for 512 tests, 512 used + 000000000000A000 0000000000000001 1057 LBFPNFFL EQU STRTLABL+X'A000' FPCR flags and DXC from long BFP + 1058 * ..room for 512 tests, 512 used + 1059 * + 000000000000C000 0000000000000001 1060 LBFPOUT EQU STRTLABL+X'C000' Long BFP finite results + 1061 * ..room for 16 tests, 7 used + 000000000000C200 0000000000000001 1062 LBFPFLGS EQU STRTLABL+X'C200' FPCR flags and DXC from long BFP + 1063 * ..room for 16 tests, 7 used + 1064 * + 000000000000C500 0000000000000001 1065 LBFPRMO EQU STRTLABL+X'C500' Long BFP rounding mode test results + 1066 * ..Room for 16, 8 used. + 000000000000CA00 0000000000000001 1067 LBFPRMOF EQU STRTLABL+X'CA00' Long BFP rounding mode FPCR results + 1068 * ..Room for 16, 8 used. + 1069 * ..next location starts at X'CD00' + 1070 * + 1071 * + 000000000000C800 0000000000000001 1072 ENDLABL EQU STRTLABL+X'C800' + 1073 PADCSECT ENDLABL + 1074+ MNOTE *,'asma detected; no CSECT padding performed' +00000000000008D8 1075 END + ASMA Ver. 0.2.0 bfp-021-multadd.asm: Test IEEE Multiply And Add 09 Oct 2016 08:59:54 Page 29 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +BFPMULA J 000000 2264 87 +CTLR0 F 000278 4 196 170 171 172 +ENDLABL U 00C800 1 1072 +FPCMCT U 000005 1 664 405 604 +FPCMODES C 000650 1 658 664 408 607 +FPCREGNT X 00027C 4 197 287 299 344 360 410 419 487 499 544 560 609 618 +FPCREGTR X 000280 4 198 293 305 352 367 493 505 552 567 +FPR0 U 000000 1 108 +FPR1 U 000001 1 109 285 289 295 346 348 356 413 415 485 489 495 546 548 556 + 612 614 +FPR10 U 00000A 1 118 +FPR11 U 00000B 1 119 +FPR12 U 00000C 1 120 +FPR13 U 00000D 1 121 +FPR14 U 00000E 1 122 +FPR15 U 00000F 1 123 +FPR2 U 000002 1 110 +FPR3 U 000003 1 111 +FPR4 U 000004 1 112 284 289 295 301 307 345 348 356 363 370 412 415 423 484 + 489 495 501 507 545 548 556 563 570 611 614 621 +FPR5 U 000005 1 113 +FPR6 U 000006 1 114 +FPR7 U 000007 1 115 +FPR8 U 000008 1 116 288 289 290 294 295 296 300 301 302 306 307 308 347 348 + 349 353 356 357 361 363 364 368 370 371 414 415 416 421 + 423 424 488 489 490 494 495 496 500 501 502 506 507 508 + 547 548 549 553 556 557 561 563 564 568 570 571 613 614 + 615 620 621 622 +FPR9 U 000009 1 117 +HARDWAIT X 000268 8 194 161 +IMAGE 1 000000 2264 0 +LBFPCT U 000007 1 969 232 +LBFPF I 00056C 4 538 184 +LBFPFLGS U 00C200 1 1062 235 +LBFPIN D 000770 8 917 969 233 +LBFPINRM F 000818 4 995 1034 239 +LBFPNF H 0004DA 2 466 182 +LBFPNFCT U 000008 1 897 226 +LBFPNFFL U 00A000 1 1057 229 +LBFPNFIN F 00072C 4 888 897 227 +LBFPNFLP H 0004E6 2 472 520 +LBFPNFOT U 006000 1 1055 228 +LBFPOUT U 00C000 1 1060 234 +LBFPRM I 0005E6 4 597 186 +LBFPRMCT U 000008 1 1034 238 +LBFPRMO U 00C500 1 1065 240 +LBFPRMOF U 00CA00 1 1067 241 +LONGF F 000340 4 231 183 +LONGNF F 000330 4 225 181 +PCINTCD H 00008E 2 138 155 +PCNOTDTA H 00020C 2 158 156 +PCOLDPSW U 000150 1 140 157 + ASMA Ver. 0.2.0 bfp-021-multadd.asm: Test IEEE Multiply And Add 09 Oct 2016 08:59:54 Page 30 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +PROGCHK H 000200 2 154 146 +R0 U 000000 1 89 170 172 +R1 U 000001 1 90 280 314 402 408 411 420 480 514 601 607 610 619 +R10 U 00000A 1 99 174 176 178 181 183 185 267 268 273 278 338 339 398 399 + 467 468 473 478 538 539 597 598 +R11 U 00000B 1 100 +R12 U 00000C 1 101 275 317 342 377 403 440 475 517 542 577 602 637 +R13 U 00000D 1 102 175 177 179 182 184 186 270 321 341 378 401 442 470 521 + 541 578 600 639 +R14 U 00000E 1 103 159 160 188 189 +R15 U 00000F 1 104 125 +R2 U 000002 1 91 267 269 320 338 340 377 398 400 440 467 469 520 538 540 + 577 597 599 637 +R3 U 000003 1 92 267 284 319 338 345 346 347 353 361 363 368 370 374 398 + 412 413 414 421 423 437 467 484 519 538 545 546 547 553 + 561 563 568 570 574 597 611 612 613 620 621 635 +R4 U 000004 1 93 273 317 473 517 +R5 U 000005 1 94 273 285 301 307 316 405 408 430 473 485 501 507 516 604 + 607 628 +R6 U 000006 1 95 278 314 478 514 +R7 U 000007 1 96 278 288 294 300 306 313 339 349 357 364 371 375 399 416 + 424 427 438 478 488 494 500 506 513 539 549 557 564 571 + 575 598 615 622 625 +R8 U 000008 1 97 268 290 296 302 308 311 339 350 358 365 372 376 399 417 + 425 428 439 468 490 496 502 508 511 539 550 558 565 572 + 576 598 616 623 626 636 +R9 U 000009 1 98 268 291 297 303 309 312 406 430 468 491 497 503 509 512 + 605 628 +RMLONGS F 000350 4 237 185 +RMSHORTS F 000320 4 219 178 +SBFPCT U 000007 1 789 214 +SBFPF I 0003F2 4 338 177 +SBFPFLGS U 005100 1 1046 217 +SBFPIN F 000678 4 734 789 215 +SBFPINRM F 0006CC 4 815 854 221 +SBFPNF H 000360 2 266 175 +SBFPNFCT U 000008 1 714 208 +SBFPNFFL U 003000 1 1041 211 +SBFPNFIN F 000658 4 705 714 209 +SBFPNFLP H 00036C 2 272 320 +SBFPNFOT U 001000 1 1039 210 +SBFPOUT U 005000 1 1044 216 +SBFPRM I 00046C 4 398 179 +SBFPRMCT U 000008 1 854 220 +SBFPRMO U 005200 1 1049 222 +SBFPRMOF U 005500 1 1051 223 +SHORTF F 000310 4 213 176 +SHORTNF F 000300 4 207 174 +START H 000214 2 169 143 +STRTLABL U 000000 1 88 137 140 142 145 153 206 1039 1041 1044 1046 1049 1051 1055 1057 + 1060 1062 1065 1067 1072 +WAITPSW X 000258 8 193 190 + ASMA Ver. 0.2.0 bfp-021-multadd.asm: Test IEEE Multiply And Add 09 Oct 2016 08:59:54 Page 31 + + MACRO DEFN REFERENCES + +PADCSECT 62 1073 + ASMA Ver. 0.2.0 bfp-021-multadd.asm: Test IEEE Multiply And Add 09 Oct 2016 08:59:54 Page 32 + + DESC SYMBOL SIZE POS ADDR + +Entry: 0 + +Image IMAGE 2264 000-8D7 000-8D7 + Region 2264 000-8D7 000-8D7 + CSECT BFPMULA 2264 000-8D7 000-8D7 + ASMA Ver. 0.2.0 bfp-021-multadd.asm: Test IEEE Multiply And Add 09 Oct 2016 08:59:54 Page 33 + + STMT FILE NAME + +1 C:\Users\srorso\Documents\GitHub\hyperion\tests\bfp-021-multadd.asm + + +** NO ERRORS FOUND ** + +[1074] MNOTE *,asma detected; no CSECT padding performed + \ No newline at end of file diff --git a/tests/bfp-021-multadd.tst b/tests/bfp-021-multadd.tst new file mode 100644 index 000000000..f065de28d --- /dev/null +++ b/tests/bfp-021-multadd.tst @@ -0,0 +1,5488 @@ +*Testcase bfp-021-multadd.tst: MAEBR, MAEB, MADBR, MADB + +#Testcase bfp-021-multadd.tst: Multiplication tests Multiply And Add (4) +#..Test cases evaluate NaN propagation, NaN generation, operations +#..using non-finite values, trappable and non-trappable IEEE +#..exceptions, result scaling, and exhaustive rounding testing. + +sysclear +archmode esame + +# +# Following suppresses logging of program checks. This test program, as part +# of its normal operation, generates 1,210 program check messages that have no +# value in the validation process. (The messages, not the program checks.) +# +ostailor quiet + +loadcore "$(testpath)/bfp-021-multadd.core" + +runtest 1.0 + +ostailor null # restore messages for subsequent tests + + + +# Short BFP Multiply And Add non-finite results +*Compare +r 1000.10 +*Want "MAEBR/MAEB NF -inf/-inf/-inf" 7FC00000 FF800000 7FC00000 FF800000 +r 1010.10 +*Want "MAEBR/MAEB NF -inf/-inf/-2.0" 7F800000 7F800000 7F800000 7F800000 +r 1020.10 +*Want "MAEBR/MAEB NF -inf/-inf/-0" 7F800000 7F800000 7F800000 7F800000 +r 1030.10 +*Want "MAEBR/MAEB NF -inf/-inf/+0" 7F800000 7F800000 7F800000 7F800000 +r 1040.10 +*Want "MAEBR/MAEB NF -inf/-inf/+2.0" 7F800000 7F800000 7F800000 7F800000 +r 1050.10 +*Want "MAEBR/MAEB NF -inf/-inf/+inf" 7F800000 7F800000 7F800000 7F800000 +r 1060.10 +*Want "MAEBR/MAEB NF -inf/-inf/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1070.10 +*Want "MAEBR/MAEB NF -inf/-inf/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1080.10 +*Want "MAEBR/MAEB NF -inf/-2.0/-inf" 7FC00000 FF800000 7FC00000 FF800000 +r 1090.10 +*Want "MAEBR/MAEB NF -inf/-2.0/-2.0" 7F800000 7F800000 7F800000 7F800000 +r 10A0.10 +*Want "MAEBR/MAEB NF -inf/-2.0/-0" 7F800000 7F800000 7F800000 7F800000 +r 10B0.10 +*Want "MAEBR/MAEB NF -inf/-2.0/+0" 7F800000 7F800000 7F800000 7F800000 +r 10C0.10 +*Want "MAEBR/MAEB NF -inf/-2.0/+2.0" 7F800000 7F800000 7F800000 7F800000 +r 10D0.10 +*Want "MAEBR/MAEB NF -inf/-2.0/+inf" 7F800000 7F800000 7F800000 7F800000 +r 10E0.10 +*Want "MAEBR/MAEB NF -inf/-2.0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 10F0.10 +*Want "MAEBR/MAEB NF -inf/-2.0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1100.10 +*Want "MAEBR/MAEB NF -inf/-0/-inf" 7FC00000 FF800000 7FC00000 FF800000 +r 1110.10 +*Want "MAEBR/MAEB NF -inf/-0/-2.0" 7FC00000 C0000000 7FC00000 C0000000 +r 1120.10 +*Want "MAEBR/MAEB NF -inf/-0/-0" 7FC00000 80000000 7FC00000 80000000 +r 1130.10 +*Want "MAEBR/MAEB NF -inf/-0/+0" 7FC00000 00000000 7FC00000 00000000 +r 1140.10 +*Want "MAEBR/MAEB NF -inf/-0/+2.0" 7FC00000 40000000 7FC00000 40000000 +r 1150.10 +*Want "MAEBR/MAEB NF -inf/-0/+inf" 7FC00000 7F800000 7FC00000 7F800000 +r 1160.10 +*Want "MAEBR/MAEB NF -inf/-0/-QNaN" 7FC00000 FFCB0000 7FC00000 FFCB0000 +r 1170.10 +*Want "MAEBR/MAEB NF -inf/-0/+SNaN" 7FC00000 7F8A0000 7FC00000 7F8A0000 +r 1180.10 +*Want "MAEBR/MAEB NF -inf/+0/-inf" 7FC00000 FF800000 7FC00000 FF800000 +r 1190.10 +*Want "MAEBR/MAEB NF -inf/+0/-2.0" 7FC00000 C0000000 7FC00000 C0000000 +r 11A0.10 +*Want "MAEBR/MAEB NF -inf/+0/-0" 7FC00000 80000000 7FC00000 80000000 +r 11B0.10 +*Want "MAEBR/MAEB NF -inf/+0/+0" 7FC00000 00000000 7FC00000 00000000 +r 11C0.10 +*Want "MAEBR/MAEB NF -inf/+0/+2.0" 7FC00000 40000000 7FC00000 40000000 +r 11D0.10 +*Want "MAEBR/MAEB NF -inf/+0/+inf" 7FC00000 7F800000 7FC00000 7F800000 +r 11E0.10 +*Want "MAEBR/MAEB NF -inf/+0/-QNaN" 7FC00000 FFCB0000 7FC00000 FFCB0000 +r 11F0.10 +*Want "MAEBR/MAEB NF -inf/+0/+SNaN" 7FC00000 7F8A0000 7FC00000 7F8A0000 +r 1200.10 +*Want "MAEBR/MAEB NF -inf/+2.0/-inf" FF800000 FF800000 FF800000 FF800000 +r 1210.10 +*Want "MAEBR/MAEB NF -inf/+2.0/-2.0" FF800000 FF800000 FF800000 FF800000 +r 1220.10 +*Want "MAEBR/MAEB NF -inf/+2.0/-0" FF800000 FF800000 FF800000 FF800000 +r 1230.10 +*Want "MAEBR/MAEB NF -inf/+2.0/+0" FF800000 FF800000 FF800000 FF800000 +r 1240.10 +*Want "MAEBR/MAEB NF -inf/+2.0/+2.0" FF800000 FF800000 FF800000 FF800000 +r 1250.10 +*Want "MAEBR/MAEB NF -inf/+2.0/+inf" 7FC00000 7F800000 7FC00000 7F800000 +r 1260.10 +*Want "MAEBR/MAEB NF -inf/+2.0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1270.10 +*Want "MAEBR/MAEB NF -inf/+2.0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1280.10 +*Want "MAEBR/MAEB NF -inf/+inf/-inf" FF800000 FF800000 FF800000 FF800000 +r 1290.10 +*Want "MAEBR/MAEB NF -inf/+inf/-2.0" FF800000 FF800000 FF800000 FF800000 +r 12A0.10 +*Want "MAEBR/MAEB NF -inf/+inf/-0" FF800000 FF800000 FF800000 FF800000 +r 12B0.10 +*Want "MAEBR/MAEB NF -inf/+inf/+0" FF800000 FF800000 FF800000 FF800000 +r 12C0.10 +*Want "MAEBR/MAEB NF -inf/+inf/+2.0" FF800000 FF800000 FF800000 FF800000 +r 12D0.10 +*Want "MAEBR/MAEB NF -inf/+inf/+inf" 7FC00000 7F800000 7FC00000 7F800000 +r 12E0.10 +*Want "MAEBR/MAEB NF -inf/+inf/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 12F0.10 +*Want "MAEBR/MAEB NF -inf/+inf/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1300.10 +*Want "MAEBR/MAEB NF -inf/-QNaN/-inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1310.10 +*Want "MAEBR/MAEB NF -inf/-QNaN/-2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1320.10 +*Want "MAEBR/MAEB NF -inf/-QNaN/-0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1330.10 +*Want "MAEBR/MAEB NF -inf/-QNaN/+0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1340.10 +*Want "MAEBR/MAEB NF -inf/-QNaN/+2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1350.10 +*Want "MAEBR/MAEB NF -inf/-QNaN/+inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1360.10 +*Want "MAEBR/MAEB NF -inf/-QNaN/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1370.10 +*Want "MAEBR/MAEB NF -inf/-QNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1380.10 +*Want "MAEBR/MAEB NF -inf/+SNaN/-inf" 7FCA0000 FF800000 7FCA0000 FF800000 +r 1390.10 +*Want "MAEBR/MAEB NF -inf/+SNaN/-2.0" 7FCA0000 C0000000 7FCA0000 C0000000 +r 13A0.10 +*Want "MAEBR/MAEB NF -inf/+SNaN/-0" 7FCA0000 80000000 7FCA0000 80000000 +r 13B0.10 +*Want "MAEBR/MAEB NF -inf/+SNaN/+0" 7FCA0000 00000000 7FCA0000 00000000 +r 13C0.10 +*Want "MAEBR/MAEB NF -inf/+SNaN/+2.0" 7FCA0000 40000000 7FCA0000 40000000 +r 13D0.10 +*Want "MAEBR/MAEB NF -inf/+SNaN/+inf" 7FCA0000 7F800000 7FCA0000 7F800000 +r 13E0.10 +*Want "MAEBR/MAEB NF -inf/+SNaN/-QNaN" 7FCA0000 FFCB0000 7FCA0000 FFCB0000 +r 13F0.10 +*Want "MAEBR/MAEB NF -inf/+SNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1400.10 +*Want "MAEBR/MAEB NF -2.0/-inf/-inf" 7FC00000 FF800000 7FC00000 FF800000 +r 1410.10 +*Want "MAEBR/MAEB NF -2.0/-inf/-2.0" 7F800000 7F800000 7F800000 7F800000 +r 1420.10 +*Want "MAEBR/MAEB NF -2.0/-inf/-0" 7F800000 7F800000 7F800000 7F800000 +r 1430.10 +*Want "MAEBR/MAEB NF -2.0/-inf/+0" 7F800000 7F800000 7F800000 7F800000 +r 1440.10 +*Want "MAEBR/MAEB NF -2.0/-inf/+2.0" 7F800000 7F800000 7F800000 7F800000 +r 1450.10 +*Want "MAEBR/MAEB NF -2.0/-inf/+inf" 7F800000 7F800000 7F800000 7F800000 +r 1460.10 +*Want "MAEBR/MAEB NF -2.0/-inf/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1470.10 +*Want "MAEBR/MAEB NF -2.0/-inf/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1480.10 +*Want "MAEBR/MAEB NF -2.0/-2.0/-inf" FF800000 FF800000 FF800000 FF800000 +r 1490.10 +*Want "MAEBR/MAEB NF -2.0/-2.0/-2.0" 40000000 40000000 40000000 40000000 +r 14A0.10 +*Want "MAEBR/MAEB NF -2.0/-2.0/-0" 40800000 40800000 40800000 40800000 +r 14B0.10 +*Want "MAEBR/MAEB NF -2.0/-2.0/+0" 40800000 40800000 40800000 40800000 +r 14C0.10 +*Want "MAEBR/MAEB NF -2.0/-2.0/+2.0" 40C00000 40C00000 40C00000 40C00000 +r 14D0.10 +*Want "MAEBR/MAEB NF -2.0/-2.0/+inf" 7F800000 7F800000 7F800000 7F800000 +r 14E0.10 +*Want "MAEBR/MAEB NF -2.0/-2.0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 14F0.10 +*Want "MAEBR/MAEB NF -2.0/-2.0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1500.10 +*Want "MAEBR/MAEB NF -2.0/-0/-inf" FF800000 FF800000 FF800000 FF800000 +r 1510.10 +*Want "MAEBR/MAEB NF -2.0/-0/-2.0" C0000000 C0000000 C0000000 C0000000 +r 1520.10 +*Want "MAEBR/MAEB NF -2.0/-0/-0" 00000000 00000000 00000000 00000000 +r 1530.10 +*Want "MAEBR/MAEB NF -2.0/-0/+0" 00000000 00000000 00000000 00000000 +r 1540.10 +*Want "MAEBR/MAEB NF -2.0/-0/+2.0" 40000000 40000000 40000000 40000000 +r 1550.10 +*Want "MAEBR/MAEB NF -2.0/-0/+inf" 7F800000 7F800000 7F800000 7F800000 +r 1560.10 +*Want "MAEBR/MAEB NF -2.0/-0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1570.10 +*Want "MAEBR/MAEB NF -2.0/-0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1580.10 +*Want "MAEBR/MAEB NF -2.0/+0/-inf" FF800000 FF800000 FF800000 FF800000 +r 1590.10 +*Want "MAEBR/MAEB NF -2.0/+0/-2.0" C0000000 C0000000 C0000000 C0000000 +r 15A0.10 +*Want "MAEBR/MAEB NF -2.0/+0/-0" 80000000 80000000 80000000 80000000 +r 15B0.10 +*Want "MAEBR/MAEB NF -2.0/+0/+0" 00000000 00000000 00000000 00000000 +r 15C0.10 +*Want "MAEBR/MAEB NF -2.0/+0/+2.0" 40000000 40000000 40000000 40000000 +r 15D0.10 +*Want "MAEBR/MAEB NF -2.0/+0/+inf" 7F800000 7F800000 7F800000 7F800000 +r 15E0.10 +*Want "MAEBR/MAEB NF -2.0/+0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 15F0.10 +*Want "MAEBR/MAEB NF -2.0/+0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1600.10 +*Want "MAEBR/MAEB NF -2.0/+2.0/-inf" FF800000 FF800000 FF800000 FF800000 +r 1610.10 +*Want "MAEBR/MAEB NF -2.0/+2.0/-2.0" C0C00000 C0C00000 C0C00000 C0C00000 +r 1620.10 +*Want "MAEBR/MAEB NF -2.0/+2.0/-0" C0800000 C0800000 C0800000 C0800000 +r 1630.10 +*Want "MAEBR/MAEB NF -2.0/+2.0/+0" C0800000 C0800000 C0800000 C0800000 +r 1640.10 +*Want "MAEBR/MAEB NF -2.0/+2.0/+2.0" C0000000 C0000000 C0000000 C0000000 +r 1650.10 +*Want "MAEBR/MAEB NF -2.0/+2.0/+inf" 7F800000 7F800000 7F800000 7F800000 +r 1660.10 +*Want "MAEBR/MAEB NF -2.0/+2.0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1670.10 +*Want "MAEBR/MAEB NF -2.0/+2.0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1680.10 +*Want "MAEBR/MAEB NF -2.0/+inf/-inf" FF800000 FF800000 FF800000 FF800000 +r 1690.10 +*Want "MAEBR/MAEB NF -2.0/+inf/-2.0" FF800000 FF800000 FF800000 FF800000 +r 16A0.10 +*Want "MAEBR/MAEB NF -2.0/+inf/-0" FF800000 FF800000 FF800000 FF800000 +r 16B0.10 +*Want "MAEBR/MAEB NF -2.0/+inf/+0" FF800000 FF800000 FF800000 FF800000 +r 16C0.10 +*Want "MAEBR/MAEB NF -2.0/+inf/+2.0" FF800000 FF800000 FF800000 FF800000 +r 16D0.10 +*Want "MAEBR/MAEB NF -2.0/+inf/+inf" 7FC00000 7F800000 7FC00000 7F800000 +r 16E0.10 +*Want "MAEBR/MAEB NF -2.0/+inf/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 16F0.10 +*Want "MAEBR/MAEB NF -2.0/+inf/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1700.10 +*Want "MAEBR/MAEB NF -2.0/-QNaN/-inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1710.10 +*Want "MAEBR/MAEB NF -2.0/-QNaN/-2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1720.10 +*Want "MAEBR/MAEB NF -2.0/-QNaN/-0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1730.10 +*Want "MAEBR/MAEB NF -2.0/-QNaN/+0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1740.10 +*Want "MAEBR/MAEB NF -2.0/-QNaN/+2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1750.10 +*Want "MAEBR/MAEB NF -2.0/-QNaN/+inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1760.10 +*Want "MAEBR/MAEB NF -2.0/-QNaN/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1770.10 +*Want "MAEBR/MAEB NF -2.0/-QNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1780.10 +*Want "MAEBR/MAEB NF -2.0/+SNaN/-inf" 7FCA0000 FF800000 7FCA0000 FF800000 +r 1790.10 +*Want "MAEBR/MAEB NF -2.0/+SNaN/-2.0" 7FCA0000 C0000000 7FCA0000 C0000000 +r 17A0.10 +*Want "MAEBR/MAEB NF -2.0/+SNaN/-0" 7FCA0000 80000000 7FCA0000 80000000 +r 17B0.10 +*Want "MAEBR/MAEB NF -2.0/+SNaN/+0" 7FCA0000 00000000 7FCA0000 00000000 +r 17C0.10 +*Want "MAEBR/MAEB NF -2.0/+SNaN/+2.0" 7FCA0000 40000000 7FCA0000 40000000 +r 17D0.10 +*Want "MAEBR/MAEB NF -2.0/+SNaN/+inf" 7FCA0000 7F800000 7FCA0000 7F800000 +r 17E0.10 +*Want "MAEBR/MAEB NF -2.0/+SNaN/-QNaN" 7FCA0000 FFCB0000 7FCA0000 FFCB0000 +r 17F0.10 +*Want "MAEBR/MAEB NF -2.0/+SNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1800.10 +*Want "MAEBR/MAEB NF -0/-inf/-inf" 7FC00000 FF800000 7FC00000 FF800000 +r 1810.10 +*Want "MAEBR/MAEB NF -0/-inf/-2.0" 7FC00000 C0000000 7FC00000 C0000000 +r 1820.10 +*Want "MAEBR/MAEB NF -0/-inf/-0" 7FC00000 80000000 7FC00000 80000000 +r 1830.10 +*Want "MAEBR/MAEB NF -0/-inf/+0" 7FC00000 00000000 7FC00000 00000000 +r 1840.10 +*Want "MAEBR/MAEB NF -0/-inf/+2.0" 7FC00000 40000000 7FC00000 40000000 +r 1850.10 +*Want "MAEBR/MAEB NF -0/-inf/+inf" 7FC00000 7F800000 7FC00000 7F800000 +r 1860.10 +*Want "MAEBR/MAEB NF -0/-inf/-QNaN" 7FC00000 FFCB0000 7FC00000 FFCB0000 +r 1870.10 +*Want "MAEBR/MAEB NF -0/-inf/+SNaN" 7FC00000 7F8A0000 7FC00000 7F8A0000 +r 1880.10 +*Want "MAEBR/MAEB NF -0/-2.0/-inf" FF800000 FF800000 FF800000 FF800000 +r 1890.10 +*Want "MAEBR/MAEB NF -0/-2.0/-2.0" C0000000 C0000000 C0000000 C0000000 +r 18A0.10 +*Want "MAEBR/MAEB NF -0/-2.0/-0" 00000000 00000000 00000000 00000000 +r 18B0.10 +*Want "MAEBR/MAEB NF -0/-2.0/+0" 00000000 00000000 00000000 00000000 +r 18C0.10 +*Want "MAEBR/MAEB NF -0/-2.0/+2.0" 40000000 40000000 40000000 40000000 +r 18D0.10 +*Want "MAEBR/MAEB NF -0/-2.0/+inf" 7F800000 7F800000 7F800000 7F800000 +r 18E0.10 +*Want "MAEBR/MAEB NF -0/-2.0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 18F0.10 +*Want "MAEBR/MAEB NF -0/-2.0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1900.10 +*Want "MAEBR/MAEB NF -0/-0/-inf" FF800000 FF800000 FF800000 FF800000 +r 1910.10 +*Want "MAEBR/MAEB NF -0/-0/-2.0" C0000000 C0000000 C0000000 C0000000 +r 1920.10 +*Want "MAEBR/MAEB NF -0/-0/-0" 00000000 00000000 00000000 00000000 +r 1930.10 +*Want "MAEBR/MAEB NF -0/-0/+0" 00000000 00000000 00000000 00000000 +r 1940.10 +*Want "MAEBR/MAEB NF -0/-0/+2.0" 40000000 40000000 40000000 40000000 +r 1950.10 +*Want "MAEBR/MAEB NF -0/-0/+inf" 7F800000 7F800000 7F800000 7F800000 +r 1960.10 +*Want "MAEBR/MAEB NF -0/-0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1970.10 +*Want "MAEBR/MAEB NF -0/-0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1980.10 +*Want "MAEBR/MAEB NF -0/+0/-inf" FF800000 FF800000 FF800000 FF800000 +r 1990.10 +*Want "MAEBR/MAEB NF -0/+0/-2.0" C0000000 C0000000 C0000000 C0000000 +r 19A0.10 +*Want "MAEBR/MAEB NF -0/+0/-0" 80000000 80000000 80000000 80000000 +r 19B0.10 +*Want "MAEBR/MAEB NF -0/+0/+0" 00000000 00000000 00000000 00000000 +r 19C0.10 +*Want "MAEBR/MAEB NF -0/+0/+2.0" 40000000 40000000 40000000 40000000 +r 19D0.10 +*Want "MAEBR/MAEB NF -0/+0/+inf" 7F800000 7F800000 7F800000 7F800000 +r 19E0.10 +*Want "MAEBR/MAEB NF -0/+0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 19F0.10 +*Want "MAEBR/MAEB NF -0/+0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1A00.10 +*Want "MAEBR/MAEB NF -0/+2.0/-inf" FF800000 FF800000 FF800000 FF800000 +r 1A10.10 +*Want "MAEBR/MAEB NF -0/+2.0/-2.0" C0000000 C0000000 C0000000 C0000000 +r 1A20.10 +*Want "MAEBR/MAEB NF -0/+2.0/-0" 80000000 80000000 80000000 80000000 +r 1A30.10 +*Want "MAEBR/MAEB NF -0/+2.0/+0" 00000000 00000000 00000000 00000000 +r 1A40.10 +*Want "MAEBR/MAEB NF -0/+2.0/+2.0" 40000000 40000000 40000000 40000000 +r 1A50.10 +*Want "MAEBR/MAEB NF -0/+2.0/+inf" 7F800000 7F800000 7F800000 7F800000 +r 1A60.10 +*Want "MAEBR/MAEB NF -0/+2.0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1A70.10 +*Want "MAEBR/MAEB NF -0/+2.0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1A80.10 +*Want "MAEBR/MAEB NF -0/+inf/-inf" 7FC00000 FF800000 7FC00000 FF800000 +r 1A90.10 +*Want "MAEBR/MAEB NF -0/+inf/-2.0" 7FC00000 C0000000 7FC00000 C0000000 +r 1AA0.10 +*Want "MAEBR/MAEB NF -0/+inf/-0" 7FC00000 80000000 7FC00000 80000000 +r 1AB0.10 +*Want "MAEBR/MAEB NF -0/+inf/+0" 7FC00000 00000000 7FC00000 00000000 +r 1AC0.10 +*Want "MAEBR/MAEB NF -0/+inf/+2.0" 7FC00000 40000000 7FC00000 40000000 +r 1AD0.10 +*Want "MAEBR/MAEB NF -0/+inf/+inf" 7FC00000 7F800000 7FC00000 7F800000 +r 1AE0.10 +*Want "MAEBR/MAEB NF -0/+inf/-QNaN" 7FC00000 FFCB0000 7FC00000 FFCB0000 +r 1AF0.10 +*Want "MAEBR/MAEB NF -0/+inf/+SNaN" 7FC00000 7F8A0000 7FC00000 7F8A0000 +r 1B00.10 +*Want "MAEBR/MAEB NF -0/-QNaN/-inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1B10.10 +*Want "MAEBR/MAEB NF -0/-QNaN/-2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1B20.10 +*Want "MAEBR/MAEB NF -0/-QNaN/-0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1B30.10 +*Want "MAEBR/MAEB NF -0/-QNaN/+0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1B40.10 +*Want "MAEBR/MAEB NF -0/-QNaN/+2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1B50.10 +*Want "MAEBR/MAEB NF -0/-QNaN/+inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1B60.10 +*Want "MAEBR/MAEB NF -0/-QNaN/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1B70.10 +*Want "MAEBR/MAEB NF -0/-QNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1B80.10 +*Want "MAEBR/MAEB NF -0/+SNaN/-inf" 7FCA0000 FF800000 7FCA0000 FF800000 +r 1B90.10 +*Want "MAEBR/MAEB NF -0/+SNaN/-2.0" 7FCA0000 C0000000 7FCA0000 C0000000 +r 1BA0.10 +*Want "MAEBR/MAEB NF -0/+SNaN/-0" 7FCA0000 80000000 7FCA0000 80000000 +r 1BB0.10 +*Want "MAEBR/MAEB NF -0/+SNaN/+0" 7FCA0000 00000000 7FCA0000 00000000 +r 1BC0.10 +*Want "MAEBR/MAEB NF -0/+SNaN/+2.0" 7FCA0000 40000000 7FCA0000 40000000 +r 1BD0.10 +*Want "MAEBR/MAEB NF -0/+SNaN/+inf" 7FCA0000 7F800000 7FCA0000 7F800000 +r 1BE0.10 +*Want "MAEBR/MAEB NF -0/+SNaN/-QNaN" 7FCA0000 FFCB0000 7FCA0000 FFCB0000 +r 1BF0.10 +*Want "MAEBR/MAEB NF -0/+SNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1C00.10 +*Want "MAEBR/MAEB NF +0/-inf/-inf" 7FC00000 FF800000 7FC00000 FF800000 +r 1C10.10 +*Want "MAEBR/MAEB NF +0/-inf/-2.0" 7FC00000 C0000000 7FC00000 C0000000 +r 1C20.10 +*Want "MAEBR/MAEB NF +0/-inf/-0" 7FC00000 80000000 7FC00000 80000000 +r 1C30.10 +*Want "MAEBR/MAEB NF +0/-inf/+0" 7FC00000 00000000 7FC00000 00000000 +r 1C40.10 +*Want "MAEBR/MAEB NF +0/-inf/+2.0" 7FC00000 40000000 7FC00000 40000000 +r 1C50.10 +*Want "MAEBR/MAEB NF +0/-inf/+inf" 7FC00000 7F800000 7FC00000 7F800000 +r 1C60.10 +*Want "MAEBR/MAEB NF +0/-inf/-QNaN" 7FC00000 FFCB0000 7FC00000 FFCB0000 +r 1C70.10 +*Want "MAEBR/MAEB NF +0/-inf/+SNaN" 7FC00000 7F8A0000 7FC00000 7F8A0000 +r 1C80.10 +*Want "MAEBR/MAEB NF +0/-2.0/-inf" FF800000 FF800000 FF800000 FF800000 +r 1C90.10 +*Want "MAEBR/MAEB NF +0/-2.0/-2.0" C0000000 C0000000 C0000000 C0000000 +r 1CA0.10 +*Want "MAEBR/MAEB NF +0/-2.0/-0" 80000000 80000000 80000000 80000000 +r 1CB0.10 +*Want "MAEBR/MAEB NF +0/-2.0/+0" 00000000 00000000 00000000 00000000 +r 1CC0.10 +*Want "MAEBR/MAEB NF +0/-2.0/+2.0" 40000000 40000000 40000000 40000000 +r 1CD0.10 +*Want "MAEBR/MAEB NF +0/-2.0/+inf" 7F800000 7F800000 7F800000 7F800000 +r 1CE0.10 +*Want "MAEBR/MAEB NF +0/-2.0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1CF0.10 +*Want "MAEBR/MAEB NF +0/-2.0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1D00.10 +*Want "MAEBR/MAEB NF +0/-0/-inf" FF800000 FF800000 FF800000 FF800000 +r 1D10.10 +*Want "MAEBR/MAEB NF +0/-0/-2.0" C0000000 C0000000 C0000000 C0000000 +r 1D20.10 +*Want "MAEBR/MAEB NF +0/-0/-0" 80000000 80000000 80000000 80000000 +r 1D30.10 +*Want "MAEBR/MAEB NF +0/-0/+0" 00000000 00000000 00000000 00000000 +r 1D40.10 +*Want "MAEBR/MAEB NF +0/-0/+2.0" 40000000 40000000 40000000 40000000 +r 1D50.10 +*Want "MAEBR/MAEB NF +0/-0/+inf" 7F800000 7F800000 7F800000 7F800000 +r 1D60.10 +*Want "MAEBR/MAEB NF +0/-0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1D70.10 +*Want "MAEBR/MAEB NF +0/-0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1D80.10 +*Want "MAEBR/MAEB NF +0/+0/-inf" FF800000 FF800000 FF800000 FF800000 +r 1D90.10 +*Want "MAEBR/MAEB NF +0/+0/-2.0" C0000000 C0000000 C0000000 C0000000 +r 1DA0.10 +*Want "MAEBR/MAEB NF +0/+0/-0" 00000000 00000000 00000000 00000000 +r 1DB0.10 +*Want "MAEBR/MAEB NF +0/+0/+0" 00000000 00000000 00000000 00000000 +r 1DC0.10 +*Want "MAEBR/MAEB NF +0/+0/+2.0" 40000000 40000000 40000000 40000000 +r 1DD0.10 +*Want "MAEBR/MAEB NF +0/+0/+inf" 7F800000 7F800000 7F800000 7F800000 +r 1DE0.10 +*Want "MAEBR/MAEB NF +0/+0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1DF0.10 +*Want "MAEBR/MAEB NF +0/+0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1E00.10 +*Want "MAEBR/MAEB NF +0/+2.0/-inf" FF800000 FF800000 FF800000 FF800000 +r 1E10.10 +*Want "MAEBR/MAEB NF +0/+2.0/-2.0" C0000000 C0000000 C0000000 C0000000 +r 1E20.10 +*Want "MAEBR/MAEB NF +0/+2.0/-0" 00000000 00000000 00000000 00000000 +r 1E30.10 +*Want "MAEBR/MAEB NF +0/+2.0/+0" 00000000 00000000 00000000 00000000 +r 1E40.10 +*Want "MAEBR/MAEB NF +0/+2.0/+2.0" 40000000 40000000 40000000 40000000 +r 1E50.10 +*Want "MAEBR/MAEB NF +0/+2.0/+inf" 7F800000 7F800000 7F800000 7F800000 +r 1E60.10 +*Want "MAEBR/MAEB NF +0/+2.0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1E70.10 +*Want "MAEBR/MAEB NF +0/+2.0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1E80.10 +*Want "MAEBR/MAEB NF +0/+inf/-inf" 7FC00000 FF800000 7FC00000 FF800000 +r 1E90.10 +*Want "MAEBR/MAEB NF +0/+inf/-2.0" 7FC00000 C0000000 7FC00000 C0000000 +r 1EA0.10 +*Want "MAEBR/MAEB NF +0/+inf/-0" 7FC00000 80000000 7FC00000 80000000 +r 1EB0.10 +*Want "MAEBR/MAEB NF +0/+inf/+0" 7FC00000 00000000 7FC00000 00000000 +r 1EC0.10 +*Want "MAEBR/MAEB NF +0/+inf/+2.0" 7FC00000 40000000 7FC00000 40000000 +r 1ED0.10 +*Want "MAEBR/MAEB NF +0/+inf/+inf" 7FC00000 7F800000 7FC00000 7F800000 +r 1EE0.10 +*Want "MAEBR/MAEB NF +0/+inf/-QNaN" 7FC00000 FFCB0000 7FC00000 FFCB0000 +r 1EF0.10 +*Want "MAEBR/MAEB NF +0/+inf/+SNaN" 7FC00000 7F8A0000 7FC00000 7F8A0000 +r 1F00.10 +*Want "MAEBR/MAEB NF +0/-QNaN/-inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1F10.10 +*Want "MAEBR/MAEB NF +0/-QNaN/-2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1F20.10 +*Want "MAEBR/MAEB NF +0/-QNaN/-0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1F30.10 +*Want "MAEBR/MAEB NF +0/-QNaN/+0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1F40.10 +*Want "MAEBR/MAEB NF +0/-QNaN/+2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1F50.10 +*Want "MAEBR/MAEB NF +0/-QNaN/+inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1F60.10 +*Want "MAEBR/MAEB NF +0/-QNaN/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1F70.10 +*Want "MAEBR/MAEB NF +0/-QNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1F80.10 +*Want "MAEBR/MAEB NF +0/+SNaN/-inf" 7FCA0000 FF800000 7FCA0000 FF800000 +r 1F90.10 +*Want "MAEBR/MAEB NF +0/+SNaN/-2.0" 7FCA0000 C0000000 7FCA0000 C0000000 +r 1FA0.10 +*Want "MAEBR/MAEB NF +0/+SNaN/-0" 7FCA0000 80000000 7FCA0000 80000000 +r 1FB0.10 +*Want "MAEBR/MAEB NF +0/+SNaN/+0" 7FCA0000 00000000 7FCA0000 00000000 +r 1FC0.10 +*Want "MAEBR/MAEB NF +0/+SNaN/+2.0" 7FCA0000 40000000 7FCA0000 40000000 +r 1FD0.10 +*Want "MAEBR/MAEB NF +0/+SNaN/+inf" 7FCA0000 7F800000 7FCA0000 7F800000 +r 1FE0.10 +*Want "MAEBR/MAEB NF +0/+SNaN/-QNaN" 7FCA0000 FFCB0000 7FCA0000 FFCB0000 +r 1FF0.10 +*Want "MAEBR/MAEB NF +0/+SNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2000.10 +*Want "MAEBR/MAEB NF +2.0/-inf/-inf" FF800000 FF800000 FF800000 FF800000 +r 2010.10 +*Want "MAEBR/MAEB NF +2.0/-inf/-2.0" FF800000 FF800000 FF800000 FF800000 +r 2020.10 +*Want "MAEBR/MAEB NF +2.0/-inf/-0" FF800000 FF800000 FF800000 FF800000 +r 2030.10 +*Want "MAEBR/MAEB NF +2.0/-inf/+0" FF800000 FF800000 FF800000 FF800000 +r 2040.10 +*Want "MAEBR/MAEB NF +2.0/-inf/+2.0" FF800000 FF800000 FF800000 FF800000 +r 2050.10 +*Want "MAEBR/MAEB NF +2.0/-inf/+inf" 7FC00000 7F800000 7FC00000 7F800000 +r 2060.10 +*Want "MAEBR/MAEB NF +2.0/-inf/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2070.10 +*Want "MAEBR/MAEB NF +2.0/-inf/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2080.10 +*Want "MAEBR/MAEB NF +2.0/-2.0/-inf" FF800000 FF800000 FF800000 FF800000 +r 2090.10 +*Want "MAEBR/MAEB NF +2.0/-2.0/-2.0" C0C00000 C0C00000 C0C00000 C0C00000 +r 20A0.10 +*Want "MAEBR/MAEB NF +2.0/-2.0/-0" C0800000 C0800000 C0800000 C0800000 +r 20B0.10 +*Want "MAEBR/MAEB NF +2.0/-2.0/+0" C0800000 C0800000 C0800000 C0800000 +r 20C0.10 +*Want "MAEBR/MAEB NF +2.0/-2.0/+2.0" C0000000 C0000000 C0000000 C0000000 +r 20D0.10 +*Want "MAEBR/MAEB NF +2.0/-2.0/+inf" 7F800000 7F800000 7F800000 7F800000 +r 20E0.10 +*Want "MAEBR/MAEB NF +2.0/-2.0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 20F0.10 +*Want "MAEBR/MAEB NF +2.0/-2.0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2100.10 +*Want "MAEBR/MAEB NF +2.0/-0/-inf" FF800000 FF800000 FF800000 FF800000 +r 2110.10 +*Want "MAEBR/MAEB NF +2.0/-0/-2.0" C0000000 C0000000 C0000000 C0000000 +r 2120.10 +*Want "MAEBR/MAEB NF +2.0/-0/-0" 80000000 80000000 80000000 80000000 +r 2130.10 +*Want "MAEBR/MAEB NF +2.0/-0/+0" 00000000 00000000 00000000 00000000 +r 2140.10 +*Want "MAEBR/MAEB NF +2.0/-0/+2.0" 40000000 40000000 40000000 40000000 +r 2150.10 +*Want "MAEBR/MAEB NF +2.0/-0/+inf" 7F800000 7F800000 7F800000 7F800000 +r 2160.10 +*Want "MAEBR/MAEB NF +2.0/-0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2170.10 +*Want "MAEBR/MAEB NF +2.0/-0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2180.10 +*Want "MAEBR/MAEB NF +2.0/+0/-inf" FF800000 FF800000 FF800000 FF800000 +r 2190.10 +*Want "MAEBR/MAEB NF +2.0/+0/-2.0" C0000000 C0000000 C0000000 C0000000 +r 21A0.10 +*Want "MAEBR/MAEB NF +2.0/+0/-0" 00000000 00000000 00000000 00000000 +r 21B0.10 +*Want "MAEBR/MAEB NF +2.0/+0/+0" 00000000 00000000 00000000 00000000 +r 21C0.10 +*Want "MAEBR/MAEB NF +2.0/+0/+2.0" 40000000 40000000 40000000 40000000 +r 21D0.10 +*Want "MAEBR/MAEB NF +2.0/+0/+inf" 7F800000 7F800000 7F800000 7F800000 +r 21E0.10 +*Want "MAEBR/MAEB NF +2.0/+0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 21F0.10 +*Want "MAEBR/MAEB NF +2.0/+0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2200.10 +*Want "MAEBR/MAEB NF +2.0/+2.0/-inf" FF800000 FF800000 FF800000 FF800000 +r 2210.10 +*Want "MAEBR/MAEB NF +2.0/+2.0/-2.0" 40000000 40000000 40000000 40000000 +r 2220.10 +*Want "MAEBR/MAEB NF +2.0/+2.0/-0" 40800000 40800000 40800000 40800000 +r 2230.10 +*Want "MAEBR/MAEB NF +2.0/+2.0/+0" 40800000 40800000 40800000 40800000 +r 2240.10 +*Want "MAEBR/MAEB NF +2.0/+2.0/+2.0" 40C00000 40C00000 40C00000 40C00000 +r 2250.10 +*Want "MAEBR/MAEB NF +2.0/+2.0/+inf" 7F800000 7F800000 7F800000 7F800000 +r 2260.10 +*Want "MAEBR/MAEB NF +2.0/+2.0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2270.10 +*Want "MAEBR/MAEB NF +2.0/+2.0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2280.10 +*Want "MAEBR/MAEB NF +2.0/+inf/-inf" 7FC00000 FF800000 7FC00000 FF800000 +r 2290.10 +*Want "MAEBR/MAEB NF +2.0/+inf/-2.0" 7F800000 7F800000 7F800000 7F800000 +r 22A0.10 +*Want "MAEBR/MAEB NF +2.0/+inf/-0" 7F800000 7F800000 7F800000 7F800000 +r 22B0.10 +*Want "MAEBR/MAEB NF +2.0/+inf/+0" 7F800000 7F800000 7F800000 7F800000 +r 22C0.10 +*Want "MAEBR/MAEB NF +2.0/+inf/+2.0" 7F800000 7F800000 7F800000 7F800000 +r 22D0.10 +*Want "MAEBR/MAEB NF +2.0/+inf/+inf" 7F800000 7F800000 7F800000 7F800000 +r 22E0.10 +*Want "MAEBR/MAEB NF +2.0/+inf/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 22F0.10 +*Want "MAEBR/MAEB NF +2.0/+inf/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2300.10 +*Want "MAEBR/MAEB NF +2.0/-QNaN/-inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2310.10 +*Want "MAEBR/MAEB NF +2.0/-QNaN/-2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2320.10 +*Want "MAEBR/MAEB NF +2.0/-QNaN/-0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2330.10 +*Want "MAEBR/MAEB NF +2.0/-QNaN/+0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2340.10 +*Want "MAEBR/MAEB NF +2.0/-QNaN/+2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2350.10 +*Want "MAEBR/MAEB NF +2.0/-QNaN/+inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2360.10 +*Want "MAEBR/MAEB NF +2.0/-QNaN/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2370.10 +*Want "MAEBR/MAEB NF +2.0/-QNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2380.10 +*Want "MAEBR/MAEB NF +2.0/+SNaN/-inf" 7FCA0000 FF800000 7FCA0000 FF800000 +r 2390.10 +*Want "MAEBR/MAEB NF +2.0/+SNaN/-2.0" 7FCA0000 C0000000 7FCA0000 C0000000 +r 23A0.10 +*Want "MAEBR/MAEB NF +2.0/+SNaN/-0" 7FCA0000 80000000 7FCA0000 80000000 +r 23B0.10 +*Want "MAEBR/MAEB NF +2.0/+SNaN/+0" 7FCA0000 00000000 7FCA0000 00000000 +r 23C0.10 +*Want "MAEBR/MAEB NF +2.0/+SNaN/+2.0" 7FCA0000 40000000 7FCA0000 40000000 +r 23D0.10 +*Want "MAEBR/MAEB NF +2.0/+SNaN/+inf" 7FCA0000 7F800000 7FCA0000 7F800000 +r 23E0.10 +*Want "MAEBR/MAEB NF +2.0/+SNaN/-QNaN" 7FCA0000 FFCB0000 7FCA0000 FFCB0000 +r 23F0.10 +*Want "MAEBR/MAEB NF +2.0/+SNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2400.10 +*Want "MAEBR/MAEB NF +inf/-inf/-inf" FF800000 FF800000 FF800000 FF800000 +r 2410.10 +*Want "MAEBR/MAEB NF +inf/-inf/-2.0" FF800000 FF800000 FF800000 FF800000 +r 2420.10 +*Want "MAEBR/MAEB NF +inf/-inf/-0" FF800000 FF800000 FF800000 FF800000 +r 2430.10 +*Want "MAEBR/MAEB NF +inf/-inf/+0" FF800000 FF800000 FF800000 FF800000 +r 2440.10 +*Want "MAEBR/MAEB NF +inf/-inf/+2.0" FF800000 FF800000 FF800000 FF800000 +r 2450.10 +*Want "MAEBR/MAEB NF +inf/-inf/+inf" 7FC00000 7F800000 7FC00000 7F800000 +r 2460.10 +*Want "MAEBR/MAEB NF +inf/-inf/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2470.10 +*Want "MAEBR/MAEB NF +inf/-inf/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2480.10 +*Want "MAEBR/MAEB NF +inf/-2.0/-inf" FF800000 FF800000 FF800000 FF800000 +r 2490.10 +*Want "MAEBR/MAEB NF +inf/-2.0/-2.0" FF800000 FF800000 FF800000 FF800000 +r 24A0.10 +*Want "MAEBR/MAEB NF +inf/-2.0/-0" FF800000 FF800000 FF800000 FF800000 +r 24B0.10 +*Want "MAEBR/MAEB NF +inf/-2.0/+0" FF800000 FF800000 FF800000 FF800000 +r 24C0.10 +*Want "MAEBR/MAEB NF +inf/-2.0/+2.0" FF800000 FF800000 FF800000 FF800000 +r 24D0.10 +*Want "MAEBR/MAEB NF +inf/-2.0/+inf" 7FC00000 7F800000 7FC00000 7F800000 +r 24E0.10 +*Want "MAEBR/MAEB NF +inf/-2.0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 24F0.10 +*Want "MAEBR/MAEB NF +inf/-2.0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2500.10 +*Want "MAEBR/MAEB NF +inf/-0/-inf" 7FC00000 FF800000 7FC00000 FF800000 +r 2510.10 +*Want "MAEBR/MAEB NF +inf/-0/-2.0" 7FC00000 C0000000 7FC00000 C0000000 +r 2520.10 +*Want "MAEBR/MAEB NF +inf/-0/-0" 7FC00000 80000000 7FC00000 80000000 +r 2530.10 +*Want "MAEBR/MAEB NF +inf/-0/+0" 7FC00000 00000000 7FC00000 00000000 +r 2540.10 +*Want "MAEBR/MAEB NF +inf/-0/+2.0" 7FC00000 40000000 7FC00000 40000000 +r 2550.10 +*Want "MAEBR/MAEB NF +inf/-0/+inf" 7FC00000 7F800000 7FC00000 7F800000 +r 2560.10 +*Want "MAEBR/MAEB NF +inf/-0/-QNaN" 7FC00000 FFCB0000 7FC00000 FFCB0000 +r 2570.10 +*Want "MAEBR/MAEB NF +inf/-0/+SNaN" 7FC00000 7F8A0000 7FC00000 7F8A0000 +r 2580.10 +*Want "MAEBR/MAEB NF +inf/+0/-inf" 7FC00000 FF800000 7FC00000 FF800000 +r 2590.10 +*Want "MAEBR/MAEB NF +inf/+0/-2.0" 7FC00000 C0000000 7FC00000 C0000000 +r 25A0.10 +*Want "MAEBR/MAEB NF +inf/+0/-0" 7FC00000 80000000 7FC00000 80000000 +r 25B0.10 +*Want "MAEBR/MAEB NF +inf/+0/+0" 7FC00000 00000000 7FC00000 00000000 +r 25C0.10 +*Want "MAEBR/MAEB NF +inf/+0/+2.0" 7FC00000 40000000 7FC00000 40000000 +r 25D0.10 +*Want "MAEBR/MAEB NF +inf/+0/+inf" 7FC00000 7F800000 7FC00000 7F800000 +r 25E0.10 +*Want "MAEBR/MAEB NF +inf/+0/-QNaN" 7FC00000 FFCB0000 7FC00000 FFCB0000 +r 25F0.10 +*Want "MAEBR/MAEB NF +inf/+0/+SNaN" 7FC00000 7F8A0000 7FC00000 7F8A0000 +r 2600.10 +*Want "MAEBR/MAEB NF +inf/+2.0/-inf" 7FC00000 FF800000 7FC00000 FF800000 +r 2610.10 +*Want "MAEBR/MAEB NF +inf/+2.0/-2.0" 7F800000 7F800000 7F800000 7F800000 +r 2620.10 +*Want "MAEBR/MAEB NF +inf/+2.0/-0" 7F800000 7F800000 7F800000 7F800000 +r 2630.10 +*Want "MAEBR/MAEB NF +inf/+2.0/+0" 7F800000 7F800000 7F800000 7F800000 +r 2640.10 +*Want "MAEBR/MAEB NF +inf/+2.0/+2.0" 7F800000 7F800000 7F800000 7F800000 +r 2650.10 +*Want "MAEBR/MAEB NF +inf/+2.0/+inf" 7F800000 7F800000 7F800000 7F800000 +r 2660.10 +*Want "MAEBR/MAEB NF +inf/+2.0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2670.10 +*Want "MAEBR/MAEB NF +inf/+2.0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2680.10 +*Want "MAEBR/MAEB NF +inf/+inf/-inf" 7FC00000 FF800000 7FC00000 FF800000 +r 2690.10 +*Want "MAEBR/MAEB NF +inf/+inf/-2.0" 7F800000 7F800000 7F800000 7F800000 +r 26A0.10 +*Want "MAEBR/MAEB NF +inf/+inf/-0" 7F800000 7F800000 7F800000 7F800000 +r 26B0.10 +*Want "MAEBR/MAEB NF +inf/+inf/+0" 7F800000 7F800000 7F800000 7F800000 +r 26C0.10 +*Want "MAEBR/MAEB NF +inf/+inf/+2.0" 7F800000 7F800000 7F800000 7F800000 +r 26D0.10 +*Want "MAEBR/MAEB NF +inf/+inf/+inf" 7F800000 7F800000 7F800000 7F800000 +r 26E0.10 +*Want "MAEBR/MAEB NF +inf/+inf/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 26F0.10 +*Want "MAEBR/MAEB NF +inf/+inf/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2700.10 +*Want "MAEBR/MAEB NF +inf/-QNaN/-inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2710.10 +*Want "MAEBR/MAEB NF +inf/-QNaN/-2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2720.10 +*Want "MAEBR/MAEB NF +inf/-QNaN/-0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2730.10 +*Want "MAEBR/MAEB NF +inf/-QNaN/+0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2740.10 +*Want "MAEBR/MAEB NF +inf/-QNaN/+2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2750.10 +*Want "MAEBR/MAEB NF +inf/-QNaN/+inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2760.10 +*Want "MAEBR/MAEB NF +inf/-QNaN/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2770.10 +*Want "MAEBR/MAEB NF +inf/-QNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2780.10 +*Want "MAEBR/MAEB NF +inf/+SNaN/-inf" 7FCA0000 FF800000 7FCA0000 FF800000 +r 2790.10 +*Want "MAEBR/MAEB NF +inf/+SNaN/-2.0" 7FCA0000 C0000000 7FCA0000 C0000000 +r 27A0.10 +*Want "MAEBR/MAEB NF +inf/+SNaN/-0" 7FCA0000 80000000 7FCA0000 80000000 +r 27B0.10 +*Want "MAEBR/MAEB NF +inf/+SNaN/+0" 7FCA0000 00000000 7FCA0000 00000000 +r 27C0.10 +*Want "MAEBR/MAEB NF +inf/+SNaN/+2.0" 7FCA0000 40000000 7FCA0000 40000000 +r 27D0.10 +*Want "MAEBR/MAEB NF +inf/+SNaN/+inf" 7FCA0000 7F800000 7FCA0000 7F800000 +r 27E0.10 +*Want "MAEBR/MAEB NF +inf/+SNaN/-QNaN" 7FCA0000 FFCB0000 7FCA0000 FFCB0000 +r 27F0.10 +*Want "MAEBR/MAEB NF +inf/+SNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2800.10 +*Want "MAEBR/MAEB NF -QNaN/-inf/-inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2810.10 +*Want "MAEBR/MAEB NF -QNaN/-inf/-2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2820.10 +*Want "MAEBR/MAEB NF -QNaN/-inf/-0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2830.10 +*Want "MAEBR/MAEB NF -QNaN/-inf/+0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2840.10 +*Want "MAEBR/MAEB NF -QNaN/-inf/+2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2850.10 +*Want "MAEBR/MAEB NF -QNaN/-inf/+inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2860.10 +*Want "MAEBR/MAEB NF -QNaN/-inf/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2870.10 +*Want "MAEBR/MAEB NF -QNaN/-inf/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2880.10 +*Want "MAEBR/MAEB NF -QNaN/-2.0/-inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2890.10 +*Want "MAEBR/MAEB NF -QNaN/-2.0/-2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 28A0.10 +*Want "MAEBR/MAEB NF -QNaN/-2.0/-0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 28B0.10 +*Want "MAEBR/MAEB NF -QNaN/-2.0/+0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 28C0.10 +*Want "MAEBR/MAEB NF -QNaN/-2.0/+2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 28D0.10 +*Want "MAEBR/MAEB NF -QNaN/-2.0/+inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 28E0.10 +*Want "MAEBR/MAEB NF -QNaN/-2.0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 28F0.10 +*Want "MAEBR/MAEB NF -QNaN/-2.0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2900.10 +*Want "MAEBR/MAEB NF -QNaN/-0/-inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2910.10 +*Want "MAEBR/MAEB NF -QNaN/-0/-2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2920.10 +*Want "MAEBR/MAEB NF -QNaN/-0/-0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2930.10 +*Want "MAEBR/MAEB NF -QNaN/-0/+0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2940.10 +*Want "MAEBR/MAEB NF -QNaN/-0/+2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2950.10 +*Want "MAEBR/MAEB NF -QNaN/-0/+inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2960.10 +*Want "MAEBR/MAEB NF -QNaN/-0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2970.10 +*Want "MAEBR/MAEB NF -QNaN/-0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2980.10 +*Want "MAEBR/MAEB NF -QNaN/+0/-inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2990.10 +*Want "MAEBR/MAEB NF -QNaN/+0/-2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 29A0.10 +*Want "MAEBR/MAEB NF -QNaN/+0/-0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 29B0.10 +*Want "MAEBR/MAEB NF -QNaN/+0/+0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 29C0.10 +*Want "MAEBR/MAEB NF -QNaN/+0/+2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 29D0.10 +*Want "MAEBR/MAEB NF -QNaN/+0/+inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 29E0.10 +*Want "MAEBR/MAEB NF -QNaN/+0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 29F0.10 +*Want "MAEBR/MAEB NF -QNaN/+0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2A00.10 +*Want "MAEBR/MAEB NF -QNaN/+2.0/-inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2A10.10 +*Want "MAEBR/MAEB NF -QNaN/+2.0/-2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2A20.10 +*Want "MAEBR/MAEB NF -QNaN/+2.0/-0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2A30.10 +*Want "MAEBR/MAEB NF -QNaN/+2.0/+0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2A40.10 +*Want "MAEBR/MAEB NF -QNaN/+2.0/+2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2A50.10 +*Want "MAEBR/MAEB NF -QNaN/+2.0/+inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2A60.10 +*Want "MAEBR/MAEB NF -QNaN/+2.0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2A70.10 +*Want "MAEBR/MAEB NF -QNaN/+2.0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2A80.10 +*Want "MAEBR/MAEB NF -QNaN/+inf/-inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2A90.10 +*Want "MAEBR/MAEB NF -QNaN/+inf/-2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2AA0.10 +*Want "MAEBR/MAEB NF -QNaN/+inf/-0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2AB0.10 +*Want "MAEBR/MAEB NF -QNaN/+inf/+0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2AC0.10 +*Want "MAEBR/MAEB NF -QNaN/+inf/+2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2AD0.10 +*Want "MAEBR/MAEB NF -QNaN/+inf/+inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2AE0.10 +*Want "MAEBR/MAEB NF -QNaN/+inf/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2AF0.10 +*Want "MAEBR/MAEB NF -QNaN/+inf/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2B00.10 +*Want "MAEBR/MAEB NF -QNaN/-QNaN/-inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2B10.10 +*Want "MAEBR/MAEB NF -QNaN/-QNaN/-2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2B20.10 +*Want "MAEBR/MAEB NF -QNaN/-QNaN/-0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2B30.10 +*Want "MAEBR/MAEB NF -QNaN/-QNaN/+0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2B40.10 +*Want "MAEBR/MAEB NF -QNaN/-QNaN/+2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2B50.10 +*Want "MAEBR/MAEB NF -QNaN/-QNaN/+inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2B60.10 +*Want "MAEBR/MAEB NF -QNaN/-QNaN/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2B70.10 +*Want "MAEBR/MAEB NF -QNaN/-QNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2B80.10 +*Want "MAEBR/MAEB NF -QNaN/+SNaN/-inf" 7FCA0000 FF800000 7FCA0000 FF800000 +r 2B90.10 +*Want "MAEBR/MAEB NF -QNaN/+SNaN/-2.0" 7FCA0000 C0000000 7FCA0000 C0000000 +r 2BA0.10 +*Want "MAEBR/MAEB NF -QNaN/+SNaN/-0" 7FCA0000 80000000 7FCA0000 80000000 +r 2BB0.10 +*Want "MAEBR/MAEB NF -QNaN/+SNaN/+0" 7FCA0000 00000000 7FCA0000 00000000 +r 2BC0.10 +*Want "MAEBR/MAEB NF -QNaN/+SNaN/+2.0" 7FCA0000 40000000 7FCA0000 40000000 +r 2BD0.10 +*Want "MAEBR/MAEB NF -QNaN/+SNaN/+inf" 7FCA0000 7F800000 7FCA0000 7F800000 +r 2BE0.10 +*Want "MAEBR/MAEB NF -QNaN/+SNaN/-QNaN" 7FCA0000 FFCB0000 7FCA0000 FFCB0000 +r 2BF0.10 +*Want "MAEBR/MAEB NF -QNaN/+SNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2C00.10 +*Want "MAEBR/MAEB NF +SNaN/-inf/-inf" 7FCA0000 FF800000 7FCA0000 FF800000 +r 2C10.10 +*Want "MAEBR/MAEB NF +SNaN/-inf/-2.0" 7FCA0000 C0000000 7FCA0000 C0000000 +r 2C20.10 +*Want "MAEBR/MAEB NF +SNaN/-inf/-0" 7FCA0000 80000000 7FCA0000 80000000 +r 2C30.10 +*Want "MAEBR/MAEB NF +SNaN/-inf/+0" 7FCA0000 00000000 7FCA0000 00000000 +r 2C40.10 +*Want "MAEBR/MAEB NF +SNaN/-inf/+2.0" 7FCA0000 40000000 7FCA0000 40000000 +r 2C50.10 +*Want "MAEBR/MAEB NF +SNaN/-inf/+inf" 7FCA0000 7F800000 7FCA0000 7F800000 +r 2C60.10 +*Want "MAEBR/MAEB NF +SNaN/-inf/-QNaN" 7FCA0000 FFCB0000 7FCA0000 FFCB0000 +r 2C70.10 +*Want "MAEBR/MAEB NF +SNaN/-inf/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2C80.10 +*Want "MAEBR/MAEB NF +SNaN/-2.0/-inf" 7FCA0000 FF800000 7FCA0000 FF800000 +r 2C90.10 +*Want "MAEBR/MAEB NF +SNaN/-2.0/-2.0" 7FCA0000 C0000000 7FCA0000 C0000000 +r 2CA0.10 +*Want "MAEBR/MAEB NF +SNaN/-2.0/-0" 7FCA0000 80000000 7FCA0000 80000000 +r 2CB0.10 +*Want "MAEBR/MAEB NF +SNaN/-2.0/+0" 7FCA0000 00000000 7FCA0000 00000000 +r 2CC0.10 +*Want "MAEBR/MAEB NF +SNaN/-2.0/+2.0" 7FCA0000 40000000 7FCA0000 40000000 +r 2CD0.10 +*Want "MAEBR/MAEB NF +SNaN/-2.0/+inf" 7FCA0000 7F800000 7FCA0000 7F800000 +r 2CE0.10 +*Want "MAEBR/MAEB NF +SNaN/-2.0/-QNaN" 7FCA0000 FFCB0000 7FCA0000 FFCB0000 +r 2CF0.10 +*Want "MAEBR/MAEB NF +SNaN/-2.0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2D00.10 +*Want "MAEBR/MAEB NF +SNaN/-0/-inf" 7FCA0000 FF800000 7FCA0000 FF800000 +r 2D10.10 +*Want "MAEBR/MAEB NF +SNaN/-0/-2.0" 7FCA0000 C0000000 7FCA0000 C0000000 +r 2D20.10 +*Want "MAEBR/MAEB NF +SNaN/-0/-0" 7FCA0000 80000000 7FCA0000 80000000 +r 2D30.10 +*Want "MAEBR/MAEB NF +SNaN/-0/+0" 7FCA0000 00000000 7FCA0000 00000000 +r 2D40.10 +*Want "MAEBR/MAEB NF +SNaN/-0/+2.0" 7FCA0000 40000000 7FCA0000 40000000 +r 2D50.10 +*Want "MAEBR/MAEB NF +SNaN/-0/+inf" 7FCA0000 7F800000 7FCA0000 7F800000 +r 2D60.10 +*Want "MAEBR/MAEB NF +SNaN/-0/-QNaN" 7FCA0000 FFCB0000 7FCA0000 FFCB0000 +r 2D70.10 +*Want "MAEBR/MAEB NF +SNaN/-0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2D80.10 +*Want "MAEBR/MAEB NF +SNaN/+0/-inf" 7FCA0000 FF800000 7FCA0000 FF800000 +r 2D90.10 +*Want "MAEBR/MAEB NF +SNaN/+0/-2.0" 7FCA0000 C0000000 7FCA0000 C0000000 +r 2DA0.10 +*Want "MAEBR/MAEB NF +SNaN/+0/-0" 7FCA0000 80000000 7FCA0000 80000000 +r 2DB0.10 +*Want "MAEBR/MAEB NF +SNaN/+0/+0" 7FCA0000 00000000 7FCA0000 00000000 +r 2DC0.10 +*Want "MAEBR/MAEB NF +SNaN/+0/+2.0" 7FCA0000 40000000 7FCA0000 40000000 +r 2DD0.10 +*Want "MAEBR/MAEB NF +SNaN/+0/+inf" 7FCA0000 7F800000 7FCA0000 7F800000 +r 2DE0.10 +*Want "MAEBR/MAEB NF +SNaN/+0/-QNaN" 7FCA0000 FFCB0000 7FCA0000 FFCB0000 +r 2DF0.10 +*Want "MAEBR/MAEB NF +SNaN/+0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2E00.10 +*Want "MAEBR/MAEB NF +SNaN/+2.0/-inf" 7FCA0000 FF800000 7FCA0000 FF800000 +r 2E10.10 +*Want "MAEBR/MAEB NF +SNaN/+2.0/-2.0" 7FCA0000 C0000000 7FCA0000 C0000000 +r 2E20.10 +*Want "MAEBR/MAEB NF +SNaN/+2.0/-0" 7FCA0000 80000000 7FCA0000 80000000 +r 2E30.10 +*Want "MAEBR/MAEB NF +SNaN/+2.0/+0" 7FCA0000 00000000 7FCA0000 00000000 +r 2E40.10 +*Want "MAEBR/MAEB NF +SNaN/+2.0/+2.0" 7FCA0000 40000000 7FCA0000 40000000 +r 2E50.10 +*Want "MAEBR/MAEB NF +SNaN/+2.0/+inf" 7FCA0000 7F800000 7FCA0000 7F800000 +r 2E60.10 +*Want "MAEBR/MAEB NF +SNaN/+2.0/-QNaN" 7FCA0000 FFCB0000 7FCA0000 FFCB0000 +r 2E70.10 +*Want "MAEBR/MAEB NF +SNaN/+2.0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2E80.10 +*Want "MAEBR/MAEB NF +SNaN/+inf/-inf" 7FCA0000 FF800000 7FCA0000 FF800000 +r 2E90.10 +*Want "MAEBR/MAEB NF +SNaN/+inf/-2.0" 7FCA0000 C0000000 7FCA0000 C0000000 +r 2EA0.10 +*Want "MAEBR/MAEB NF +SNaN/+inf/-0" 7FCA0000 80000000 7FCA0000 80000000 +r 2EB0.10 +*Want "MAEBR/MAEB NF +SNaN/+inf/+0" 7FCA0000 00000000 7FCA0000 00000000 +r 2EC0.10 +*Want "MAEBR/MAEB NF +SNaN/+inf/+2.0" 7FCA0000 40000000 7FCA0000 40000000 +r 2ED0.10 +*Want "MAEBR/MAEB NF +SNaN/+inf/+inf" 7FCA0000 7F800000 7FCA0000 7F800000 +r 2EE0.10 +*Want "MAEBR/MAEB NF +SNaN/+inf/-QNaN" 7FCA0000 FFCB0000 7FCA0000 FFCB0000 +r 2EF0.10 +*Want "MAEBR/MAEB NF +SNaN/+inf/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2F00.10 +*Want "MAEBR/MAEB NF +SNaN/-QNaN/-inf" 7FCA0000 FF800000 7FCA0000 FF800000 +r 2F10.10 +*Want "MAEBR/MAEB NF +SNaN/-QNaN/-2.0" 7FCA0000 C0000000 7FCA0000 C0000000 +r 2F20.10 +*Want "MAEBR/MAEB NF +SNaN/-QNaN/-0" 7FCA0000 80000000 7FCA0000 80000000 +r 2F30.10 +*Want "MAEBR/MAEB NF +SNaN/-QNaN/+0" 7FCA0000 00000000 7FCA0000 00000000 +r 2F40.10 +*Want "MAEBR/MAEB NF +SNaN/-QNaN/+2.0" 7FCA0000 40000000 7FCA0000 40000000 +r 2F50.10 +*Want "MAEBR/MAEB NF +SNaN/-QNaN/+inf" 7FCA0000 7F800000 7FCA0000 7F800000 +r 2F60.10 +*Want "MAEBR/MAEB NF +SNaN/-QNaN/-QNaN" 7FCA0000 FFCB0000 7FCA0000 FFCB0000 +r 2F70.10 +*Want "MAEBR/MAEB NF +SNaN/-QNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2F80.10 +*Want "MAEBR/MAEB NF +SNaN/+SNaN/-inf" 7FCA0000 FF800000 7FCA0000 FF800000 +r 2F90.10 +*Want "MAEBR/MAEB NF +SNaN/+SNaN/-2.0" 7FCA0000 C0000000 7FCA0000 C0000000 +r 2FA0.10 +*Want "MAEBR/MAEB NF +SNaN/+SNaN/-0" 7FCA0000 80000000 7FCA0000 80000000 +r 2FB0.10 +*Want "MAEBR/MAEB NF +SNaN/+SNaN/+0" 7FCA0000 00000000 7FCA0000 00000000 +r 2FC0.10 +*Want "MAEBR/MAEB NF +SNaN/+SNaN/+2.0" 7FCA0000 40000000 7FCA0000 40000000 +r 2FD0.10 +*Want "MAEBR/MAEB NF +SNaN/+SNaN/+inf" 7FCA0000 7F800000 7FCA0000 7F800000 +r 2FE0.10 +*Want "MAEBR/MAEB NF +SNaN/+SNaN/-QNaN" 7FCA0000 FFCB0000 7FCA0000 FFCB0000 +r 2FF0.10 +*Want "MAEBR/MAEB NF +SNaN/+SNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 + + +# Short BFP Multiply And Add non-finite results - FPCR Contents +*Compare +r 3000.10 +*Want "MAEBR/MAEB NF -inf/-inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3010.10 +*Want "MAEBR/MAEB NF -inf/-inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3020.10 +*Want "MAEBR/MAEB NF -inf/-inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3030.10 +*Want "MAEBR/MAEB NF -inf/-inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3040.10 +*Want "MAEBR/MAEB NF -inf/-inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3050.10 +*Want "MAEBR/MAEB NF -inf/-inf/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3060.10 +*Want "MAEBR/MAEB NF -inf/-inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3070.10 +*Want "MAEBR/MAEB NF -inf/-inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3080.10 +*Want "MAEBR/MAEB NF -inf/-2.0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3090.10 +*Want "MAEBR/MAEB NF -inf/-2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 30A0.10 +*Want "MAEBR/MAEB NF -inf/-2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 30B0.10 +*Want "MAEBR/MAEB NF -inf/-2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 30C0.10 +*Want "MAEBR/MAEB NF -inf/-2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 30D0.10 +*Want "MAEBR/MAEB NF -inf/-2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 30E0.10 +*Want "MAEBR/MAEB NF -inf/-2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 30F0.10 +*Want "MAEBR/MAEB NF -inf/-2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3100.10 +*Want "MAEBR/MAEB NF -inf/-0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3110.10 +*Want "MAEBR/MAEB NF -inf/-0/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3120.10 +*Want "MAEBR/MAEB NF -inf/-0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3130.10 +*Want "MAEBR/MAEB NF -inf/-0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3140.10 +*Want "MAEBR/MAEB NF -inf/-0/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3150.10 +*Want "MAEBR/MAEB NF -inf/-0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3160.10 +*Want "MAEBR/MAEB NF -inf/-0/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3170.10 +*Want "MAEBR/MAEB NF -inf/-0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3180.10 +*Want "MAEBR/MAEB NF -inf/+0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3190.10 +*Want "MAEBR/MAEB NF -inf/+0/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 31A0.10 +*Want "MAEBR/MAEB NF -inf/+0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 31B0.10 +*Want "MAEBR/MAEB NF -inf/+0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 31C0.10 +*Want "MAEBR/MAEB NF -inf/+0/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 31D0.10 +*Want "MAEBR/MAEB NF -inf/+0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 31E0.10 +*Want "MAEBR/MAEB NF -inf/+0/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 31F0.10 +*Want "MAEBR/MAEB NF -inf/+0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3200.10 +*Want "MAEBR/MAEB NF -inf/+2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3210.10 +*Want "MAEBR/MAEB NF -inf/+2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3220.10 +*Want "MAEBR/MAEB NF -inf/+2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3230.10 +*Want "MAEBR/MAEB NF -inf/+2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3240.10 +*Want "MAEBR/MAEB NF -inf/+2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3250.10 +*Want "MAEBR/MAEB NF -inf/+2.0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3260.10 +*Want "MAEBR/MAEB NF -inf/+2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3270.10 +*Want "MAEBR/MAEB NF -inf/+2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3280.10 +*Want "MAEBR/MAEB NF -inf/+inf/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3290.10 +*Want "MAEBR/MAEB NF -inf/+inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 32A0.10 +*Want "MAEBR/MAEB NF -inf/+inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 32B0.10 +*Want "MAEBR/MAEB NF -inf/+inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 32C0.10 +*Want "MAEBR/MAEB NF -inf/+inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 32D0.10 +*Want "MAEBR/MAEB NF -inf/+inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 32E0.10 +*Want "MAEBR/MAEB NF -inf/+inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 32F0.10 +*Want "MAEBR/MAEB NF -inf/+inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3300.10 +*Want "MAEBR/MAEB NF -inf/-QNaN/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3310.10 +*Want "MAEBR/MAEB NF -inf/-QNaN/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3320.10 +*Want "MAEBR/MAEB NF -inf/-QNaN/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3330.10 +*Want "MAEBR/MAEB NF -inf/-QNaN/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3340.10 +*Want "MAEBR/MAEB NF -inf/-QNaN/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3350.10 +*Want "MAEBR/MAEB NF -inf/-QNaN/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3360.10 +*Want "MAEBR/MAEB NF -inf/-QNaN/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3370.10 +*Want "MAEBR/MAEB NF -inf/-QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3380.10 +*Want "MAEBR/MAEB NF -inf/+SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3390.10 +*Want "MAEBR/MAEB NF -inf/+SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 33A0.10 +*Want "MAEBR/MAEB NF -inf/+SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 33B0.10 +*Want "MAEBR/MAEB NF -inf/+SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 33C0.10 +*Want "MAEBR/MAEB NF -inf/+SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 33D0.10 +*Want "MAEBR/MAEB NF -inf/+SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 33E0.10 +*Want "MAEBR/MAEB NF -inf/+SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 33F0.10 +*Want "MAEBR/MAEB NF -inf/+SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3400.10 +*Want "MAEBR/MAEB NF -2.0/-inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3410.10 +*Want "MAEBR/MAEB NF -2.0/-inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3420.10 +*Want "MAEBR/MAEB NF -2.0/-inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3430.10 +*Want "MAEBR/MAEB NF -2.0/-inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3440.10 +*Want "MAEBR/MAEB NF -2.0/-inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3450.10 +*Want "MAEBR/MAEB NF -2.0/-inf/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3460.10 +*Want "MAEBR/MAEB NF -2.0/-inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3470.10 +*Want "MAEBR/MAEB NF -2.0/-inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3480.10 +*Want "MAEBR/MAEB NF -2.0/-2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3490.10 +*Want "MAEBR/MAEB NF -2.0/-2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 34A0.10 +*Want "MAEBR/MAEB NF -2.0/-2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 34B0.10 +*Want "MAEBR/MAEB NF -2.0/-2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 34C0.10 +*Want "MAEBR/MAEB NF -2.0/-2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 34D0.10 +*Want "MAEBR/MAEB NF -2.0/-2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 34E0.10 +*Want "MAEBR/MAEB NF -2.0/-2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 34F0.10 +*Want "MAEBR/MAEB NF -2.0/-2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3500.10 +*Want "MAEBR/MAEB NF -2.0/-0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3510.10 +*Want "MAEBR/MAEB NF -2.0/-0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3520.10 +*Want "MAEBR/MAEB NF -2.0/-0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3530.10 +*Want "MAEBR/MAEB NF -2.0/-0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3540.10 +*Want "MAEBR/MAEB NF -2.0/-0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3550.10 +*Want "MAEBR/MAEB NF -2.0/-0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3560.10 +*Want "MAEBR/MAEB NF -2.0/-0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3570.10 +*Want "MAEBR/MAEB NF -2.0/-0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3580.10 +*Want "MAEBR/MAEB NF -2.0/+0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3590.10 +*Want "MAEBR/MAEB NF -2.0/+0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 35A0.10 +*Want "MAEBR/MAEB NF -2.0/+0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 35B0.10 +*Want "MAEBR/MAEB NF -2.0/+0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 35C0.10 +*Want "MAEBR/MAEB NF -2.0/+0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 35D0.10 +*Want "MAEBR/MAEB NF -2.0/+0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 35E0.10 +*Want "MAEBR/MAEB NF -2.0/+0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 35F0.10 +*Want "MAEBR/MAEB NF -2.0/+0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3600.10 +*Want "MAEBR/MAEB NF -2.0/+2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3610.10 +*Want "MAEBR/MAEB NF -2.0/+2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3620.10 +*Want "MAEBR/MAEB NF -2.0/+2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3630.10 +*Want "MAEBR/MAEB NF -2.0/+2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3640.10 +*Want "MAEBR/MAEB NF -2.0/+2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3650.10 +*Want "MAEBR/MAEB NF -2.0/+2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3660.10 +*Want "MAEBR/MAEB NF -2.0/+2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3670.10 +*Want "MAEBR/MAEB NF -2.0/+2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3680.10 +*Want "MAEBR/MAEB NF -2.0/+inf/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3690.10 +*Want "MAEBR/MAEB NF -2.0/+inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 36A0.10 +*Want "MAEBR/MAEB NF -2.0/+inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 36B0.10 +*Want "MAEBR/MAEB NF -2.0/+inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 36C0.10 +*Want "MAEBR/MAEB NF -2.0/+inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 36D0.10 +*Want "MAEBR/MAEB NF -2.0/+inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 36E0.10 +*Want "MAEBR/MAEB NF -2.0/+inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 36F0.10 +*Want "MAEBR/MAEB NF -2.0/+inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3700.10 +*Want "MAEBR/MAEB NF -2.0/-QNaN/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3710.10 +*Want "MAEBR/MAEB NF -2.0/-QNaN/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3720.10 +*Want "MAEBR/MAEB NF -2.0/-QNaN/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3730.10 +*Want "MAEBR/MAEB NF -2.0/-QNaN/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3740.10 +*Want "MAEBR/MAEB NF -2.0/-QNaN/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3750.10 +*Want "MAEBR/MAEB NF -2.0/-QNaN/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3760.10 +*Want "MAEBR/MAEB NF -2.0/-QNaN/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3770.10 +*Want "MAEBR/MAEB NF -2.0/-QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3780.10 +*Want "MAEBR/MAEB NF -2.0/+SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3790.10 +*Want "MAEBR/MAEB NF -2.0/+SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 37A0.10 +*Want "MAEBR/MAEB NF -2.0/+SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 37B0.10 +*Want "MAEBR/MAEB NF -2.0/+SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 37C0.10 +*Want "MAEBR/MAEB NF -2.0/+SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 37D0.10 +*Want "MAEBR/MAEB NF -2.0/+SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 37E0.10 +*Want "MAEBR/MAEB NF -2.0/+SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 37F0.10 +*Want "MAEBR/MAEB NF -2.0/+SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3800.10 +*Want "MAEBR/MAEB NF -0/-inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3810.10 +*Want "MAEBR/MAEB NF -0/-inf/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3820.10 +*Want "MAEBR/MAEB NF -0/-inf/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3830.10 +*Want "MAEBR/MAEB NF -0/-inf/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3840.10 +*Want "MAEBR/MAEB NF -0/-inf/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3850.10 +*Want "MAEBR/MAEB NF -0/-inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3860.10 +*Want "MAEBR/MAEB NF -0/-inf/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3870.10 +*Want "MAEBR/MAEB NF -0/-inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3880.10 +*Want "MAEBR/MAEB NF -0/-2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3890.10 +*Want "MAEBR/MAEB NF -0/-2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 38A0.10 +*Want "MAEBR/MAEB NF -0/-2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 38B0.10 +*Want "MAEBR/MAEB NF -0/-2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 38C0.10 +*Want "MAEBR/MAEB NF -0/-2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 38D0.10 +*Want "MAEBR/MAEB NF -0/-2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 38E0.10 +*Want "MAEBR/MAEB NF -0/-2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 38F0.10 +*Want "MAEBR/MAEB NF -0/-2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3900.10 +*Want "MAEBR/MAEB NF -0/-0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3910.10 +*Want "MAEBR/MAEB NF -0/-0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3920.10 +*Want "MAEBR/MAEB NF -0/-0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3930.10 +*Want "MAEBR/MAEB NF -0/-0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3940.10 +*Want "MAEBR/MAEB NF -0/-0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3950.10 +*Want "MAEBR/MAEB NF -0/-0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3960.10 +*Want "MAEBR/MAEB NF -0/-0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3970.10 +*Want "MAEBR/MAEB NF -0/-0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3980.10 +*Want "MAEBR/MAEB NF -0/+0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3990.10 +*Want "MAEBR/MAEB NF -0/+0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 39A0.10 +*Want "MAEBR/MAEB NF -0/+0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 39B0.10 +*Want "MAEBR/MAEB NF -0/+0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 39C0.10 +*Want "MAEBR/MAEB NF -0/+0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 39D0.10 +*Want "MAEBR/MAEB NF -0/+0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 39E0.10 +*Want "MAEBR/MAEB NF -0/+0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 39F0.10 +*Want "MAEBR/MAEB NF -0/+0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3A00.10 +*Want "MAEBR/MAEB NF -0/+2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3A10.10 +*Want "MAEBR/MAEB NF -0/+2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3A20.10 +*Want "MAEBR/MAEB NF -0/+2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3A30.10 +*Want "MAEBR/MAEB NF -0/+2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3A40.10 +*Want "MAEBR/MAEB NF -0/+2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3A50.10 +*Want "MAEBR/MAEB NF -0/+2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3A60.10 +*Want "MAEBR/MAEB NF -0/+2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3A70.10 +*Want "MAEBR/MAEB NF -0/+2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3A80.10 +*Want "MAEBR/MAEB NF -0/+inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3A90.10 +*Want "MAEBR/MAEB NF -0/+inf/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3AA0.10 +*Want "MAEBR/MAEB NF -0/+inf/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3AB0.10 +*Want "MAEBR/MAEB NF -0/+inf/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3AC0.10 +*Want "MAEBR/MAEB NF -0/+inf/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3AD0.10 +*Want "MAEBR/MAEB NF -0/+inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3AE0.10 +*Want "MAEBR/MAEB NF -0/+inf/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3AF0.10 +*Want "MAEBR/MAEB NF -0/+inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3B00.10 +*Want "MAEBR/MAEB NF -0/-QNaN/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3B10.10 +*Want "MAEBR/MAEB NF -0/-QNaN/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3B20.10 +*Want "MAEBR/MAEB NF -0/-QNaN/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3B30.10 +*Want "MAEBR/MAEB NF -0/-QNaN/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3B40.10 +*Want "MAEBR/MAEB NF -0/-QNaN/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3B50.10 +*Want "MAEBR/MAEB NF -0/-QNaN/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3B60.10 +*Want "MAEBR/MAEB NF -0/-QNaN/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3B70.10 +*Want "MAEBR/MAEB NF -0/-QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3B80.10 +*Want "MAEBR/MAEB NF -0/+SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3B90.10 +*Want "MAEBR/MAEB NF -0/+SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3BA0.10 +*Want "MAEBR/MAEB NF -0/+SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3BB0.10 +*Want "MAEBR/MAEB NF -0/+SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3BC0.10 +*Want "MAEBR/MAEB NF -0/+SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3BD0.10 +*Want "MAEBR/MAEB NF -0/+SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3BE0.10 +*Want "MAEBR/MAEB NF -0/+SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3BF0.10 +*Want "MAEBR/MAEB NF -0/+SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3C00.10 +*Want "MAEBR/MAEB NF +0/-inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3C10.10 +*Want "MAEBR/MAEB NF +0/-inf/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3C20.10 +*Want "MAEBR/MAEB NF +0/-inf/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3C30.10 +*Want "MAEBR/MAEB NF +0/-inf/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3C40.10 +*Want "MAEBR/MAEB NF +0/-inf/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3C50.10 +*Want "MAEBR/MAEB NF +0/-inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3C60.10 +*Want "MAEBR/MAEB NF +0/-inf/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3C70.10 +*Want "MAEBR/MAEB NF +0/-inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3C80.10 +*Want "MAEBR/MAEB NF +0/-2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3C90.10 +*Want "MAEBR/MAEB NF +0/-2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3CA0.10 +*Want "MAEBR/MAEB NF +0/-2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3CB0.10 +*Want "MAEBR/MAEB NF +0/-2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3CC0.10 +*Want "MAEBR/MAEB NF +0/-2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3CD0.10 +*Want "MAEBR/MAEB NF +0/-2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3CE0.10 +*Want "MAEBR/MAEB NF +0/-2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3CF0.10 +*Want "MAEBR/MAEB NF +0/-2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3D00.10 +*Want "MAEBR/MAEB NF +0/-0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3D10.10 +*Want "MAEBR/MAEB NF +0/-0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3D20.10 +*Want "MAEBR/MAEB NF +0/-0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3D30.10 +*Want "MAEBR/MAEB NF +0/-0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3D40.10 +*Want "MAEBR/MAEB NF +0/-0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3D50.10 +*Want "MAEBR/MAEB NF +0/-0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3D60.10 +*Want "MAEBR/MAEB NF +0/-0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3D70.10 +*Want "MAEBR/MAEB NF +0/-0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3D80.10 +*Want "MAEBR/MAEB NF +0/+0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3D90.10 +*Want "MAEBR/MAEB NF +0/+0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3DA0.10 +*Want "MAEBR/MAEB NF +0/+0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3DB0.10 +*Want "MAEBR/MAEB NF +0/+0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3DC0.10 +*Want "MAEBR/MAEB NF +0/+0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3DD0.10 +*Want "MAEBR/MAEB NF +0/+0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3DE0.10 +*Want "MAEBR/MAEB NF +0/+0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3DF0.10 +*Want "MAEBR/MAEB NF +0/+0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3E00.10 +*Want "MAEBR/MAEB NF +0/+2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3E10.10 +*Want "MAEBR/MAEB NF +0/+2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3E20.10 +*Want "MAEBR/MAEB NF +0/+2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3E30.10 +*Want "MAEBR/MAEB NF +0/+2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3E40.10 +*Want "MAEBR/MAEB NF +0/+2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3E50.10 +*Want "MAEBR/MAEB NF +0/+2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3E60.10 +*Want "MAEBR/MAEB NF +0/+2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3E70.10 +*Want "MAEBR/MAEB NF +0/+2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3E80.10 +*Want "MAEBR/MAEB NF +0/+inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3E90.10 +*Want "MAEBR/MAEB NF +0/+inf/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3EA0.10 +*Want "MAEBR/MAEB NF +0/+inf/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3EB0.10 +*Want "MAEBR/MAEB NF +0/+inf/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3EC0.10 +*Want "MAEBR/MAEB NF +0/+inf/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3ED0.10 +*Want "MAEBR/MAEB NF +0/+inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3EE0.10 +*Want "MAEBR/MAEB NF +0/+inf/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3EF0.10 +*Want "MAEBR/MAEB NF +0/+inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3F00.10 +*Want "MAEBR/MAEB NF +0/-QNaN/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3F10.10 +*Want "MAEBR/MAEB NF +0/-QNaN/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3F20.10 +*Want "MAEBR/MAEB NF +0/-QNaN/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3F30.10 +*Want "MAEBR/MAEB NF +0/-QNaN/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3F40.10 +*Want "MAEBR/MAEB NF +0/-QNaN/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3F50.10 +*Want "MAEBR/MAEB NF +0/-QNaN/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3F60.10 +*Want "MAEBR/MAEB NF +0/-QNaN/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3F70.10 +*Want "MAEBR/MAEB NF +0/-QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3F80.10 +*Want "MAEBR/MAEB NF +0/+SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3F90.10 +*Want "MAEBR/MAEB NF +0/+SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3FA0.10 +*Want "MAEBR/MAEB NF +0/+SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3FB0.10 +*Want "MAEBR/MAEB NF +0/+SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3FC0.10 +*Want "MAEBR/MAEB NF +0/+SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3FD0.10 +*Want "MAEBR/MAEB NF +0/+SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3FE0.10 +*Want "MAEBR/MAEB NF +0/+SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3FF0.10 +*Want "MAEBR/MAEB NF +0/+SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4000.10 +*Want "MAEBR/MAEB NF +2.0/-inf/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4010.10 +*Want "MAEBR/MAEB NF +2.0/-inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4020.10 +*Want "MAEBR/MAEB NF +2.0/-inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4030.10 +*Want "MAEBR/MAEB NF +2.0/-inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4040.10 +*Want "MAEBR/MAEB NF +2.0/-inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4050.10 +*Want "MAEBR/MAEB NF +2.0/-inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4060.10 +*Want "MAEBR/MAEB NF +2.0/-inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 4070.10 +*Want "MAEBR/MAEB NF +2.0/-inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4080.10 +*Want "MAEBR/MAEB NF +2.0/-2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4090.10 +*Want "MAEBR/MAEB NF +2.0/-2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 40A0.10 +*Want "MAEBR/MAEB NF +2.0/-2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 40B0.10 +*Want "MAEBR/MAEB NF +2.0/-2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 40C0.10 +*Want "MAEBR/MAEB NF +2.0/-2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 40D0.10 +*Want "MAEBR/MAEB NF +2.0/-2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 40E0.10 +*Want "MAEBR/MAEB NF +2.0/-2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 40F0.10 +*Want "MAEBR/MAEB NF +2.0/-2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4100.10 +*Want "MAEBR/MAEB NF +2.0/-0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4110.10 +*Want "MAEBR/MAEB NF +2.0/-0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4120.10 +*Want "MAEBR/MAEB NF +2.0/-0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4130.10 +*Want "MAEBR/MAEB NF +2.0/-0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4140.10 +*Want "MAEBR/MAEB NF +2.0/-0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4150.10 +*Want "MAEBR/MAEB NF +2.0/-0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4160.10 +*Want "MAEBR/MAEB NF +2.0/-0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 4170.10 +*Want "MAEBR/MAEB NF +2.0/-0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4180.10 +*Want "MAEBR/MAEB NF +2.0/+0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4190.10 +*Want "MAEBR/MAEB NF +2.0/+0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 41A0.10 +*Want "MAEBR/MAEB NF +2.0/+0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 41B0.10 +*Want "MAEBR/MAEB NF +2.0/+0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 41C0.10 +*Want "MAEBR/MAEB NF +2.0/+0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 41D0.10 +*Want "MAEBR/MAEB NF +2.0/+0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 41E0.10 +*Want "MAEBR/MAEB NF +2.0/+0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 41F0.10 +*Want "MAEBR/MAEB NF +2.0/+0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4200.10 +*Want "MAEBR/MAEB NF +2.0/+2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4210.10 +*Want "MAEBR/MAEB NF +2.0/+2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4220.10 +*Want "MAEBR/MAEB NF +2.0/+2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4230.10 +*Want "MAEBR/MAEB NF +2.0/+2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4240.10 +*Want "MAEBR/MAEB NF +2.0/+2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4250.10 +*Want "MAEBR/MAEB NF +2.0/+2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4260.10 +*Want "MAEBR/MAEB NF +2.0/+2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 4270.10 +*Want "MAEBR/MAEB NF +2.0/+2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4280.10 +*Want "MAEBR/MAEB NF +2.0/+inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4290.10 +*Want "MAEBR/MAEB NF +2.0/+inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 42A0.10 +*Want "MAEBR/MAEB NF +2.0/+inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 42B0.10 +*Want "MAEBR/MAEB NF +2.0/+inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 42C0.10 +*Want "MAEBR/MAEB NF +2.0/+inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 42D0.10 +*Want "MAEBR/MAEB NF +2.0/+inf/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 42E0.10 +*Want "MAEBR/MAEB NF +2.0/+inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 42F0.10 +*Want "MAEBR/MAEB NF +2.0/+inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4300.10 +*Want "MAEBR/MAEB NF +2.0/-QNaN/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4310.10 +*Want "MAEBR/MAEB NF +2.0/-QNaN/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4320.10 +*Want "MAEBR/MAEB NF +2.0/-QNaN/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4330.10 +*Want "MAEBR/MAEB NF +2.0/-QNaN/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4340.10 +*Want "MAEBR/MAEB NF +2.0/-QNaN/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4350.10 +*Want "MAEBR/MAEB NF +2.0/-QNaN/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4360.10 +*Want "MAEBR/MAEB NF +2.0/-QNaN/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 4370.10 +*Want "MAEBR/MAEB NF +2.0/-QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4380.10 +*Want "MAEBR/MAEB NF +2.0/+SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4390.10 +*Want "MAEBR/MAEB NF +2.0/+SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 43A0.10 +*Want "MAEBR/MAEB NF +2.0/+SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 43B0.10 +*Want "MAEBR/MAEB NF +2.0/+SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 43C0.10 +*Want "MAEBR/MAEB NF +2.0/+SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 43D0.10 +*Want "MAEBR/MAEB NF +2.0/+SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 43E0.10 +*Want "MAEBR/MAEB NF +2.0/+SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 43F0.10 +*Want "MAEBR/MAEB NF +2.0/+SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4400.10 +*Want "MAEBR/MAEB NF +inf/-inf/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4410.10 +*Want "MAEBR/MAEB NF +inf/-inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4420.10 +*Want "MAEBR/MAEB NF +inf/-inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4430.10 +*Want "MAEBR/MAEB NF +inf/-inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4440.10 +*Want "MAEBR/MAEB NF +inf/-inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4450.10 +*Want "MAEBR/MAEB NF +inf/-inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4460.10 +*Want "MAEBR/MAEB NF +inf/-inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 4470.10 +*Want "MAEBR/MAEB NF +inf/-inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4480.10 +*Want "MAEBR/MAEB NF +inf/-2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4490.10 +*Want "MAEBR/MAEB NF +inf/-2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 44A0.10 +*Want "MAEBR/MAEB NF +inf/-2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 44B0.10 +*Want "MAEBR/MAEB NF +inf/-2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 44C0.10 +*Want "MAEBR/MAEB NF +inf/-2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 44D0.10 +*Want "MAEBR/MAEB NF +inf/-2.0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 44E0.10 +*Want "MAEBR/MAEB NF +inf/-2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 44F0.10 +*Want "MAEBR/MAEB NF +inf/-2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4500.10 +*Want "MAEBR/MAEB NF +inf/-0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4510.10 +*Want "MAEBR/MAEB NF +inf/-0/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4520.10 +*Want "MAEBR/MAEB NF +inf/-0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4530.10 +*Want "MAEBR/MAEB NF +inf/-0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4540.10 +*Want "MAEBR/MAEB NF +inf/-0/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4550.10 +*Want "MAEBR/MAEB NF +inf/-0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4560.10 +*Want "MAEBR/MAEB NF +inf/-0/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4570.10 +*Want "MAEBR/MAEB NF +inf/-0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4580.10 +*Want "MAEBR/MAEB NF +inf/+0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4590.10 +*Want "MAEBR/MAEB NF +inf/+0/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 45A0.10 +*Want "MAEBR/MAEB NF +inf/+0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 45B0.10 +*Want "MAEBR/MAEB NF +inf/+0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 45C0.10 +*Want "MAEBR/MAEB NF +inf/+0/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 45D0.10 +*Want "MAEBR/MAEB NF +inf/+0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 45E0.10 +*Want "MAEBR/MAEB NF +inf/+0/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 45F0.10 +*Want "MAEBR/MAEB NF +inf/+0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4600.10 +*Want "MAEBR/MAEB NF +inf/+2.0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4610.10 +*Want "MAEBR/MAEB NF +inf/+2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4620.10 +*Want "MAEBR/MAEB NF +inf/+2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4630.10 +*Want "MAEBR/MAEB NF +inf/+2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4640.10 +*Want "MAEBR/MAEB NF +inf/+2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4650.10 +*Want "MAEBR/MAEB NF +inf/+2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4660.10 +*Want "MAEBR/MAEB NF +inf/+2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 4670.10 +*Want "MAEBR/MAEB NF +inf/+2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4680.10 +*Want "MAEBR/MAEB NF +inf/+inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4690.10 +*Want "MAEBR/MAEB NF +inf/+inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 46A0.10 +*Want "MAEBR/MAEB NF +inf/+inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 46B0.10 +*Want "MAEBR/MAEB NF +inf/+inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 46C0.10 +*Want "MAEBR/MAEB NF +inf/+inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 46D0.10 +*Want "MAEBR/MAEB NF +inf/+inf/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 46E0.10 +*Want "MAEBR/MAEB NF +inf/+inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 46F0.10 +*Want "MAEBR/MAEB NF +inf/+inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4700.10 +*Want "MAEBR/MAEB NF +inf/-QNaN/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4710.10 +*Want "MAEBR/MAEB NF +inf/-QNaN/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4720.10 +*Want "MAEBR/MAEB NF +inf/-QNaN/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4730.10 +*Want "MAEBR/MAEB NF +inf/-QNaN/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4740.10 +*Want "MAEBR/MAEB NF +inf/-QNaN/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4750.10 +*Want "MAEBR/MAEB NF +inf/-QNaN/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4760.10 +*Want "MAEBR/MAEB NF +inf/-QNaN/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 4770.10 +*Want "MAEBR/MAEB NF +inf/-QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4780.10 +*Want "MAEBR/MAEB NF +inf/+SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4790.10 +*Want "MAEBR/MAEB NF +inf/+SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 47A0.10 +*Want "MAEBR/MAEB NF +inf/+SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 47B0.10 +*Want "MAEBR/MAEB NF +inf/+SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 47C0.10 +*Want "MAEBR/MAEB NF +inf/+SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 47D0.10 +*Want "MAEBR/MAEB NF +inf/+SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 47E0.10 +*Want "MAEBR/MAEB NF +inf/+SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 47F0.10 +*Want "MAEBR/MAEB NF +inf/+SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4800.10 +*Want "MAEBR/MAEB NF -QNaN/-inf/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4810.10 +*Want "MAEBR/MAEB NF -QNaN/-inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4820.10 +*Want "MAEBR/MAEB NF -QNaN/-inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4830.10 +*Want "MAEBR/MAEB NF -QNaN/-inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4840.10 +*Want "MAEBR/MAEB NF -QNaN/-inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4850.10 +*Want "MAEBR/MAEB NF -QNaN/-inf/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4860.10 +*Want "MAEBR/MAEB NF -QNaN/-inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 4870.10 +*Want "MAEBR/MAEB NF -QNaN/-inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4880.10 +*Want "MAEBR/MAEB NF -QNaN/-2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4890.10 +*Want "MAEBR/MAEB NF -QNaN/-2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 48A0.10 +*Want "MAEBR/MAEB NF -QNaN/-2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 48B0.10 +*Want "MAEBR/MAEB NF -QNaN/-2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 48C0.10 +*Want "MAEBR/MAEB NF -QNaN/-2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 48D0.10 +*Want "MAEBR/MAEB NF -QNaN/-2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 48E0.10 +*Want "MAEBR/MAEB NF -QNaN/-2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 48F0.10 +*Want "MAEBR/MAEB NF -QNaN/-2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4900.10 +*Want "MAEBR/MAEB NF -QNaN/-0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4910.10 +*Want "MAEBR/MAEB NF -QNaN/-0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4920.10 +*Want "MAEBR/MAEB NF -QNaN/-0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4930.10 +*Want "MAEBR/MAEB NF -QNaN/-0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4940.10 +*Want "MAEBR/MAEB NF -QNaN/-0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4950.10 +*Want "MAEBR/MAEB NF -QNaN/-0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4960.10 +*Want "MAEBR/MAEB NF -QNaN/-0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 4970.10 +*Want "MAEBR/MAEB NF -QNaN/-0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4980.10 +*Want "MAEBR/MAEB NF -QNaN/+0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4990.10 +*Want "MAEBR/MAEB NF -QNaN/+0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 49A0.10 +*Want "MAEBR/MAEB NF -QNaN/+0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 49B0.10 +*Want "MAEBR/MAEB NF -QNaN/+0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 49C0.10 +*Want "MAEBR/MAEB NF -QNaN/+0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 49D0.10 +*Want "MAEBR/MAEB NF -QNaN/+0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 49E0.10 +*Want "MAEBR/MAEB NF -QNaN/+0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 49F0.10 +*Want "MAEBR/MAEB NF -QNaN/+0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4A00.10 +*Want "MAEBR/MAEB NF -QNaN/+2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4A10.10 +*Want "MAEBR/MAEB NF -QNaN/+2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4A20.10 +*Want "MAEBR/MAEB NF -QNaN/+2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4A30.10 +*Want "MAEBR/MAEB NF -QNaN/+2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4A40.10 +*Want "MAEBR/MAEB NF -QNaN/+2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4A50.10 +*Want "MAEBR/MAEB NF -QNaN/+2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4A60.10 +*Want "MAEBR/MAEB NF -QNaN/+2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 4A70.10 +*Want "MAEBR/MAEB NF -QNaN/+2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4A80.10 +*Want "MAEBR/MAEB NF -QNaN/+inf/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4A90.10 +*Want "MAEBR/MAEB NF -QNaN/+inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4AA0.10 +*Want "MAEBR/MAEB NF -QNaN/+inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4AB0.10 +*Want "MAEBR/MAEB NF -QNaN/+inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4AC0.10 +*Want "MAEBR/MAEB NF -QNaN/+inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4AD0.10 +*Want "MAEBR/MAEB NF -QNaN/+inf/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4AE0.10 +*Want "MAEBR/MAEB NF -QNaN/+inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 4AF0.10 +*Want "MAEBR/MAEB NF -QNaN/+inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4B00.10 +*Want "MAEBR/MAEB NF -QNaN/-QNaN/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4B10.10 +*Want "MAEBR/MAEB NF -QNaN/-QNaN/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4B20.10 +*Want "MAEBR/MAEB NF -QNaN/-QNaN/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4B30.10 +*Want "MAEBR/MAEB NF -QNaN/-QNaN/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4B40.10 +*Want "MAEBR/MAEB NF -QNaN/-QNaN/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4B50.10 +*Want "MAEBR/MAEB NF -QNaN/-QNaN/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4B60.10 +*Want "MAEBR/MAEB NF -QNaN/-QNaN/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 4B70.10 +*Want "MAEBR/MAEB NF -QNaN/-QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4B80.10 +*Want "MAEBR/MAEB NF -QNaN/+SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4B90.10 +*Want "MAEBR/MAEB NF -QNaN/+SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4BA0.10 +*Want "MAEBR/MAEB NF -QNaN/+SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4BB0.10 +*Want "MAEBR/MAEB NF -QNaN/+SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4BC0.10 +*Want "MAEBR/MAEB NF -QNaN/+SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4BD0.10 +*Want "MAEBR/MAEB NF -QNaN/+SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4BE0.10 +*Want "MAEBR/MAEB NF -QNaN/+SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4BF0.10 +*Want "MAEBR/MAEB NF -QNaN/+SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4C00.10 +*Want "MAEBR/MAEB NF +SNaN/-inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4C10.10 +*Want "MAEBR/MAEB NF +SNaN/-inf/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4C20.10 +*Want "MAEBR/MAEB NF +SNaN/-inf/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4C30.10 +*Want "MAEBR/MAEB NF +SNaN/-inf/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4C40.10 +*Want "MAEBR/MAEB NF +SNaN/-inf/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4C50.10 +*Want "MAEBR/MAEB NF +SNaN/-inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4C60.10 +*Want "MAEBR/MAEB NF +SNaN/-inf/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4C70.10 +*Want "MAEBR/MAEB NF +SNaN/-inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4C80.10 +*Want "MAEBR/MAEB NF +SNaN/-2.0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4C90.10 +*Want "MAEBR/MAEB NF +SNaN/-2.0/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4CA0.10 +*Want "MAEBR/MAEB NF +SNaN/-2.0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4CB0.10 +*Want "MAEBR/MAEB NF +SNaN/-2.0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4CC0.10 +*Want "MAEBR/MAEB NF +SNaN/-2.0/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4CD0.10 +*Want "MAEBR/MAEB NF +SNaN/-2.0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4CE0.10 +*Want "MAEBR/MAEB NF +SNaN/-2.0/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4CF0.10 +*Want "MAEBR/MAEB NF +SNaN/-2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4D00.10 +*Want "MAEBR/MAEB NF +SNaN/-0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4D10.10 +*Want "MAEBR/MAEB NF +SNaN/-0/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4D20.10 +*Want "MAEBR/MAEB NF +SNaN/-0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4D30.10 +*Want "MAEBR/MAEB NF +SNaN/-0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4D40.10 +*Want "MAEBR/MAEB NF +SNaN/-0/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4D50.10 +*Want "MAEBR/MAEB NF +SNaN/-0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4D60.10 +*Want "MAEBR/MAEB NF +SNaN/-0/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4D70.10 +*Want "MAEBR/MAEB NF +SNaN/-0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4D80.10 +*Want "MAEBR/MAEB NF +SNaN/+0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4D90.10 +*Want "MAEBR/MAEB NF +SNaN/+0/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4DA0.10 +*Want "MAEBR/MAEB NF +SNaN/+0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4DB0.10 +*Want "MAEBR/MAEB NF +SNaN/+0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4DC0.10 +*Want "MAEBR/MAEB NF +SNaN/+0/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4DD0.10 +*Want "MAEBR/MAEB NF +SNaN/+0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4DE0.10 +*Want "MAEBR/MAEB NF +SNaN/+0/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4DF0.10 +*Want "MAEBR/MAEB NF +SNaN/+0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4E00.10 +*Want "MAEBR/MAEB NF +SNaN/+2.0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4E10.10 +*Want "MAEBR/MAEB NF +SNaN/+2.0/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4E20.10 +*Want "MAEBR/MAEB NF +SNaN/+2.0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4E30.10 +*Want "MAEBR/MAEB NF +SNaN/+2.0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4E40.10 +*Want "MAEBR/MAEB NF +SNaN/+2.0/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4E50.10 +*Want "MAEBR/MAEB NF +SNaN/+2.0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4E60.10 +*Want "MAEBR/MAEB NF +SNaN/+2.0/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4E70.10 +*Want "MAEBR/MAEB NF +SNaN/+2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4E80.10 +*Want "MAEBR/MAEB NF +SNaN/+inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4E90.10 +*Want "MAEBR/MAEB NF +SNaN/+inf/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4EA0.10 +*Want "MAEBR/MAEB NF +SNaN/+inf/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4EB0.10 +*Want "MAEBR/MAEB NF +SNaN/+inf/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4EC0.10 +*Want "MAEBR/MAEB NF +SNaN/+inf/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4ED0.10 +*Want "MAEBR/MAEB NF +SNaN/+inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4EE0.10 +*Want "MAEBR/MAEB NF +SNaN/+inf/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4EF0.10 +*Want "MAEBR/MAEB NF +SNaN/+inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4F00.10 +*Want "MAEBR/MAEB NF +SNaN/-QNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4F10.10 +*Want "MAEBR/MAEB NF +SNaN/-QNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4F20.10 +*Want "MAEBR/MAEB NF +SNaN/-QNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4F30.10 +*Want "MAEBR/MAEB NF +SNaN/-QNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4F40.10 +*Want "MAEBR/MAEB NF +SNaN/-QNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4F50.10 +*Want "MAEBR/MAEB NF +SNaN/-QNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4F60.10 +*Want "MAEBR/MAEB NF +SNaN/-QNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4F70.10 +*Want "MAEBR/MAEB NF +SNaN/-QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4F80.10 +*Want "MAEBR/MAEB NF +SNaN/+SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4F90.10 +*Want "MAEBR/MAEB NF +SNaN/+SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4FA0.10 +*Want "MAEBR/MAEB NF +SNaN/+SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4FB0.10 +*Want "MAEBR/MAEB NF +SNaN/+SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4FC0.10 +*Want "MAEBR/MAEB NF +SNaN/+SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4FD0.10 +*Want "MAEBR/MAEB NF +SNaN/+SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4FE0.10 +*Want "MAEBR/MAEB NF +SNaN/+SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4FF0.10 +*Want "MAEBR/MAEB NF +SNaN/+SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 + + +# Short BFP Multiply And Add finite results +*Compare +r 5000.10 +*Want "MAEBR/MAEB F Ovfl 1" FF800000 DF7FFFFE FF800000 DF7FFFFE +r 5010.10 +*Want "MAEBR/MAEB F Ovfl 2" 7F800000 1FFFFFFF 7F800000 1FFFFFFF +r 5020.10 +*Want "MAEBR/MAEB F Ufl 1" 00400001 60000002 00400001 60000002 +r 5030.10 +*Want "MAEBR/MAEB F Ufl 2" 00400000 60000001 00400000 60000001 +r 5040.10 +*Want "MAEBR/MAEB F Nmin" 011FFFFF 011FFFFF 011FFFFF 011FFFFF +r 5050.10 +*Want "MAEBR/MAEB F Incr" 3FC8000D 3FC8000D 3FC8000D 3FC8000D +r 5060.10 +*Want "MAEBR/MAEB F Trun" 3FC80007 3FC80007 3FC80007 3FC80007 + +# Short BFP Multiply And Add finite results - FPCR contents +*Compare +r 5100.10 +*Want "MAEBR/MAEB F Ovfl 1 FPCR" 00280000 F8002800 00280000 F8002800 +r 5110.10 +*Want "MAEBR/MAEB F Ovfl 2 FPCR" 00280000 F8002000 00280000 F8002000 +r 5120.10 +*Want "MAEBR/MAEB F Ufl 1 FPCR" 00180000 F8001C00 00180000 F8001C00 +r 5130.10 +*Want "MAEBR/MAEB F Ufl 2 FPCR" 00180000 F8001000 00180000 F8001000 +r 5140.10 +*Want "MAEBR/MAEB F Nmin FPCR" 00000000 F8000000 00000000 F8000000 +r 5150.10 +*Want "MAEBR/MAEB F Incr FPCR" 00080000 F8000C00 00080000 F8000C00 +r 5160.10 +*Want "MAEBR/MAEB F Trun FPCR" 00080000 F8000800 00080000 F8000800 + + +# Short BFP Multiply And Add rounding mode results +*Compare +r 5200.10 +*Want "MAEBR/MAEB RM +NZ RNTE, RZ" 3FC80007 3FC80007 3FC80007 3FC80007 +r 5210.10 +*Want "MAEBR/MAEB RM +NZ RP, RM" 3FC80008 3FC80008 3FC80007 3FC80007 +r 5220.10 +*Want "MAEBR/MAEB RM +NZ RFS" 3FC80007 3FC80007 00000000 00000000 +r 5230.10 +*Want "MAEBR/MAEB RM -NZ RNTE, RZ" BFC80007 BFC80007 BFC80007 BFC80007 +r 5240.10 +*Want "MAEBR/MAEB RM -NZ RP, RM" BFC80007 BFC80007 BFC80008 BFC80008 +r 5250.10 +*Want "MAEBR/MAEB RM -NZ RFS" BFC80007 BFC80007 00000000 00000000 +r 5260.10 +*Want "MAEBR/MAEB RM +NA RNTE, RZ" 3FC8000D 3FC8000D 3FC8000C 3FC8000C +r 5270.10 +*Want "MAEBR/MAEB RM +NA RP, RM" 3FC8000D 3FC8000D 3FC8000C 3FC8000C +r 5280.10 +*Want "MAEBR/MAEB RM +NA RFS" 3FC8000D 3FC8000D 00000000 00000000 +r 5290.10 +*Want "MAEBR/MAEB RM -NA RNTE, RZ" BFC8000D BFC8000D BFC8000C BFC8000C +r 52A0.10 +*Want "MAEBR/MAEB RM -NA RP, RM" BFC8000C BFC8000C BFC8000D BFC8000D +r 52B0.10 +*Want "MAEBR/MAEB RM -NA RFS" BFC8000D BFC8000D 00000000 00000000 +r 52C0.10 +*Want "MAEBR/MAEB RM +TZ RNTE, RZ" 3FC80008 3FC80008 3FC80008 3FC80008 +r 52D0.10 +*Want "MAEBR/MAEB RM +TZ RP, RM" 3FC80009 3FC80009 3FC80008 3FC80008 +r 52E0.10 +*Want "MAEBR/MAEB RM +TZ RFS" 3FC80009 3FC80009 00000000 00000000 +r 52F0.10 +*Want "MAEBR/MAEB RM -TZ RNTE, RZ" BFC80008 BFC80008 BFC80008 BFC80008 +r 5300.10 +*Want "MAEBR/MAEB RM -TZ RP, RM" BFC80008 BFC80008 BFC80009 BFC80009 +r 5310.10 +*Want "MAEBR/MAEB RM -TZ RFS" BFC80009 BFC80009 00000000 00000000 +r 5320.10 +*Want "MAEBR/MAEB RM +TA RNTE, RZ" 3FC8001A 3FC8001A 3FC80019 3FC80019 +r 5330.10 +*Want "MAEBR/MAEB RM +TA RP, RM" 3FC8001A 3FC8001A 3FC80019 3FC80019 +r 5340.10 +*Want "MAEBR/MAEB RM +TA RFS" 3FC80019 3FC80019 00000000 00000000 +r 5350.10 +*Want "MAEBR/MAEB RM -TA RNTE, RZ" BFC8001A BFC8001A BFC80019 BFC80019 +r 5360.10 +*Want "MAEBR/MAEB RM -TA RP, RM" BFC80019 BFC80019 BFC8001A BFC8001A +r 5370.10 +*Want "MAEBR/MAEB RM -TA RFS" BFC80019 BFC80019 00000000 00000000 + + +# Short BFP Multiply And Add rounding mode results - FPCR contents +*Compare +r 5500.10 +*Want "MAEBR/MAEB RM +NZ RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r 5510.10 +*Want "MAEBR/MAEB RM +NZ RP, RM FPCR" 00080002 00080002 00080003 00080003 +r 5520.10 +*Want "MAEBR/MAEB RM +NZ RFS FPCR" 00080007 00080007 00000000 00000000 +r 5530.10 +*Want "MAEBR/MAEB RM -NZ RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r 5540.10 +*Want "MAEBR/MAEB RM -NZ RP, RM FPCR" 00080002 00080002 00080003 00080003 +r 5550.10 +*Want "MAEBR/MAEB RM -NZ RFS FPCR" 00080007 00080007 00000000 00000000 +r 5560.10 +*Want "MAEBR/MAEB RM +NA RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r 5570.10 +*Want "MAEBR/MAEB RM +NA RP, RM FPCR" 00080002 00080002 00080003 00080003 +r 5580.10 +*Want "MAEBR/MAEB RM +NA RFS FPCR" 00080007 00080007 00000000 00000000 +r 5590.10 +*Want "MAEBR/MAEB RM -NA RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r 55A0.10 +*Want "MAEBR/MAEB RM -NA RP, RM FPCR" 00080002 00080002 00080003 00080003 +r 55B0.10 +*Want "MAEBR/MAEB RM -NA RFS FPCR" 00080007 00080007 00000000 00000000 +r 55C0.10 +*Want "MAEBR/MAEB RM +TZ RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r 55D0.10 +*Want "MAEBR/MAEB RM +TZ RP, RM FPCR" 00080002 00080002 00080003 00080003 +r 55E0.10 +*Want "MAEBR/MAEB RM +TZ RFS FPCR" 00080007 00080007 00000000 00000000 +r 55F0.10 +*Want "MAEBR/MAEB RM -TZ RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r 5600.10 +*Want "MAEBR/MAEB RM -TZ RP, RM FPCR" 00080002 00080002 00080003 00080003 +r 5610.10 +*Want "MAEBR/MAEB RM -TZ RFS FPCR" 00080007 00080007 00000000 00000000 +r 5620.10 +*Want "MAEBR/MAEB RM +TA RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r 5630.10 +*Want "MAEBR/MAEB RM +TA RP, RM FPCR" 00080002 00080002 00080003 00080003 +r 5640.10 +*Want "MAEBR/MAEB RM +TA RFS FPCR" 00080007 00080007 00000000 00000000 +r 5650.10 +*Want "MAEBR/MAEB RM -TA RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r 5660.10 +*Want "MAEBR/MAEB RM -TA RP, RM FPCR" 00080002 00080002 00080003 00080003 +r 5670.10 +*Want "MAEBR/MAEB RM -TA RFS FPCR" 00080007 00080007 00000000 00000000 + + +# Long BFP Multiply And Add non-finite results +*Compare +r 6000.10 +*Want "MADBR NF -inf/-inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 6010.10 +*Want "MADB NF -inf/-inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 6020.10 +*Want "MADBR NF -inf/-inf/-2.0" 7FF00000 00000000 7FF00000 00000000 +r 6030.10 +*Want "MADB NF -inf/-inf/-2.0" 7FF00000 00000000 7FF00000 00000000 +r 6040.10 +*Want "MADBR NF -inf/-inf/-0" 7FF00000 00000000 7FF00000 00000000 +r 6050.10 +*Want "MADB NF -inf/-inf/-0" 7FF00000 00000000 7FF00000 00000000 +r 6060.10 +*Want "MADBR NF -inf/-inf/+0" 7FF00000 00000000 7FF00000 00000000 +r 6070.10 +*Want "MADB NF -inf/-inf/+0" 7FF00000 00000000 7FF00000 00000000 +r 6080.10 +*Want "MADBR NF -inf/-inf/+2.0" 7FF00000 00000000 7FF00000 00000000 +r 6090.10 +*Want "MADB NF -inf/-inf/+2.0" 7FF00000 00000000 7FF00000 00000000 +r 60A0.10 +*Want "MADBR NF -inf/-inf/+inf" 7FF00000 00000000 7FF00000 00000000 +r 60B0.10 +*Want "MADB NF -inf/-inf/+inf" 7FF00000 00000000 7FF00000 00000000 +r 60C0.10 +*Want "MADBR NF -inf/-inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 60D0.10 +*Want "MADB NF -inf/-inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 60E0.10 +*Want "MADBR NF -inf/-inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 60F0.10 +*Want "MADB NF -inf/-inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6100.10 +*Want "MADBR NF -inf/-2.0/-inf" 7FF80000 00000000 FFF00000 00000000 +r 6110.10 +*Want "MADB NF -inf/-2.0/-inf" 7FF80000 00000000 FFF00000 00000000 +r 6120.10 +*Want "MADBR NF -inf/-2.0/-2.0" 7FF00000 00000000 7FF00000 00000000 +r 6130.10 +*Want "MADB NF -inf/-2.0/-2.0" 7FF00000 00000000 7FF00000 00000000 +r 6140.10 +*Want "MADBR NF -inf/-2.0/-0" 7FF00000 00000000 7FF00000 00000000 +r 6150.10 +*Want "MADB NF -inf/-2.0/-0" 7FF00000 00000000 7FF00000 00000000 +r 6160.10 +*Want "MADBR NF -inf/-2.0/+0" 7FF00000 00000000 7FF00000 00000000 +r 6170.10 +*Want "MADB NF -inf/-2.0/+0" 7FF00000 00000000 7FF00000 00000000 +r 6180.10 +*Want "MADBR NF -inf/-2.0/+2.0" 7FF00000 00000000 7FF00000 00000000 +r 6190.10 +*Want "MADB NF -inf/-2.0/+2.0" 7FF00000 00000000 7FF00000 00000000 +r 61A0.10 +*Want "MADBR NF -inf/-2.0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 61B0.10 +*Want "MADB NF -inf/-2.0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 61C0.10 +*Want "MADBR NF -inf/-2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 61D0.10 +*Want "MADB NF -inf/-2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 61E0.10 +*Want "MADBR NF -inf/-2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 61F0.10 +*Want "MADB NF -inf/-2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6200.10 +*Want "MADBR NF -inf/-0/-inf" 7FF80000 00000000 FFF00000 00000000 +r 6210.10 +*Want "MADB NF -inf/-0/-inf" 7FF80000 00000000 FFF00000 00000000 +r 6220.10 +*Want "MADBR NF -inf/-0/-2.0" 7FF80000 00000000 C0000000 00000000 +r 6230.10 +*Want "MADB NF -inf/-0/-2.0" 7FF80000 00000000 C0000000 00000000 +r 6240.10 +*Want "MADBR NF -inf/-0/-0" 7FF80000 00000000 80000000 00000000 +r 6250.10 +*Want "MADB NF -inf/-0/-0" 7FF80000 00000000 80000000 00000000 +r 6260.10 +*Want "MADBR NF -inf/-0/+0" 7FF80000 00000000 00000000 00000000 +r 6270.10 +*Want "MADB NF -inf/-0/+0" 7FF80000 00000000 00000000 00000000 +r 6280.10 +*Want "MADBR NF -inf/-0/+2.0" 7FF80000 00000000 40000000 00000000 +r 6290.10 +*Want "MADB NF -inf/-0/+2.0" 7FF80000 00000000 40000000 00000000 +r 62A0.10 +*Want "MADBR NF -inf/-0/+inf" 7FF80000 00000000 7FF00000 00000000 +r 62B0.10 +*Want "MADB NF -inf/-0/+inf" 7FF80000 00000000 7FF00000 00000000 +r 62C0.10 +*Want "MADBR NF -inf/-0/-QNaN" 7FF80000 00000000 FFF8B000 00000000 +r 62D0.10 +*Want "MADB NF -inf/-0/-QNaN" 7FF80000 00000000 FFF8B000 00000000 +r 62E0.10 +*Want "MADBR NF -inf/-0/+SNaN" 7FF80000 00000000 7FF0A000 00000000 +r 62F0.10 +*Want "MADB NF -inf/-0/+SNaN" 7FF80000 00000000 7FF0A000 00000000 +r 6300.10 +*Want "MADBR NF -inf/+0/-inf" 7FF80000 00000000 FFF00000 00000000 +r 6310.10 +*Want "MADB NF -inf/+0/-inf" 7FF80000 00000000 FFF00000 00000000 +r 6320.10 +*Want "MADBR NF -inf/+0/-2.0" 7FF80000 00000000 C0000000 00000000 +r 6330.10 +*Want "MADB NF -inf/+0/-2.0" 7FF80000 00000000 C0000000 00000000 +r 6340.10 +*Want "MADBR NF -inf/+0/-0" 7FF80000 00000000 80000000 00000000 +r 6350.10 +*Want "MADB NF -inf/+0/-0" 7FF80000 00000000 80000000 00000000 +r 6360.10 +*Want "MADBR NF -inf/+0/+0" 7FF80000 00000000 00000000 00000000 +r 6370.10 +*Want "MADB NF -inf/+0/+0" 7FF80000 00000000 00000000 00000000 +r 6380.10 +*Want "MADBR NF -inf/+0/+2.0" 7FF80000 00000000 40000000 00000000 +r 6390.10 +*Want "MADB NF -inf/+0/+2.0" 7FF80000 00000000 40000000 00000000 +r 63A0.10 +*Want "MADBR NF -inf/+0/+inf" 7FF80000 00000000 7FF00000 00000000 +r 63B0.10 +*Want "MADB NF -inf/+0/+inf" 7FF80000 00000000 7FF00000 00000000 +r 63C0.10 +*Want "MADBR NF -inf/+0/-QNaN" 7FF80000 00000000 FFF8B000 00000000 +r 63D0.10 +*Want "MADB NF -inf/+0/-QNaN" 7FF80000 00000000 FFF8B000 00000000 +r 63E0.10 +*Want "MADBR NF -inf/+0/+SNaN" 7FF80000 00000000 7FF0A000 00000000 +r 63F0.10 +*Want "MADB NF -inf/+0/+SNaN" 7FF80000 00000000 7FF0A000 00000000 +r 6400.10 +*Want "MADBR NF -inf/+2.0/-inf" FFF00000 00000000 FFF00000 00000000 +r 6410.10 +*Want "MADB NF -inf/+2.0/-inf" FFF00000 00000000 FFF00000 00000000 +r 6420.10 +*Want "MADBR NF -inf/+2.0/-2.0" FFF00000 00000000 FFF00000 00000000 +r 6430.10 +*Want "MADB NF -inf/+2.0/-2.0" FFF00000 00000000 FFF00000 00000000 +r 6440.10 +*Want "MADBR NF -inf/+2.0/-0" FFF00000 00000000 FFF00000 00000000 +r 6450.10 +*Want "MADB NF -inf/+2.0/-0" FFF00000 00000000 FFF00000 00000000 +r 6460.10 +*Want "MADBR NF -inf/+2.0/+0" FFF00000 00000000 FFF00000 00000000 +r 6470.10 +*Want "MADB NF -inf/+2.0/+0" FFF00000 00000000 FFF00000 00000000 +r 6480.10 +*Want "MADBR NF -inf/+2.0/+2.0" FFF00000 00000000 FFF00000 00000000 +r 6490.10 +*Want "MADB NF -inf/+2.0/+2.0" FFF00000 00000000 FFF00000 00000000 +r 64A0.10 +*Want "MADBR NF -inf/+2.0/+inf" 7FF80000 00000000 7FF00000 00000000 +r 64B0.10 +*Want "MADB NF -inf/+2.0/+inf" 7FF80000 00000000 7FF00000 00000000 +r 64C0.10 +*Want "MADBR NF -inf/+2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 64D0.10 +*Want "MADB NF -inf/+2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 64E0.10 +*Want "MADBR NF -inf/+2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 64F0.10 +*Want "MADB NF -inf/+2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6500.10 +*Want "MADBR NF -inf/+inf/-inf" FFF00000 00000000 FFF00000 00000000 +r 6510.10 +*Want "MADB NF -inf/+inf/-inf" FFF00000 00000000 FFF00000 00000000 +r 6520.10 +*Want "MADBR NF -inf/+inf/-2.0" FFF00000 00000000 FFF00000 00000000 +r 6530.10 +*Want "MADB NF -inf/+inf/-2.0" FFF00000 00000000 FFF00000 00000000 +r 6540.10 +*Want "MADBR NF -inf/+inf/-0" FFF00000 00000000 FFF00000 00000000 +r 6550.10 +*Want "MADB NF -inf/+inf/-0" FFF00000 00000000 FFF00000 00000000 +r 6560.10 +*Want "MADBR NF -inf/+inf/+0" FFF00000 00000000 FFF00000 00000000 +r 6570.10 +*Want "MADB NF -inf/+inf/+0" FFF00000 00000000 FFF00000 00000000 +r 6580.10 +*Want "MADBR NF -inf/+inf/+2.0" FFF00000 00000000 FFF00000 00000000 +r 6590.10 +*Want "MADB NF -inf/+inf/+2.0" FFF00000 00000000 FFF00000 00000000 +r 65A0.10 +*Want "MADBR NF -inf/+inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 65B0.10 +*Want "MADB NF -inf/+inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 65C0.10 +*Want "MADBR NF -inf/+inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 65D0.10 +*Want "MADB NF -inf/+inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 65E0.10 +*Want "MADBR NF -inf/+inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 65F0.10 +*Want "MADB NF -inf/+inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6600.10 +*Want "MADBR NF -inf/-QNaN/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 6610.10 +*Want "MADB NF -inf/-QNaN/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 6620.10 +*Want "MADBR NF -inf/-QNaN/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 6630.10 +*Want "MADB NF -inf/-QNaN/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 6640.10 +*Want "MADBR NF -inf/-QNaN/-0" FFF8B000 00000000 FFF8B000 00000000 +r 6650.10 +*Want "MADB NF -inf/-QNaN/-0" FFF8B000 00000000 FFF8B000 00000000 +r 6660.10 +*Want "MADBR NF -inf/-QNaN/+0" FFF8B000 00000000 FFF8B000 00000000 +r 6670.10 +*Want "MADB NF -inf/-QNaN/+0" FFF8B000 00000000 FFF8B000 00000000 +r 6680.10 +*Want "MADBR NF -inf/-QNaN/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 6690.10 +*Want "MADB NF -inf/-QNaN/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 66A0.10 +*Want "MADBR NF -inf/-QNaN/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 66B0.10 +*Want "MADB NF -inf/-QNaN/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 66C0.10 +*Want "MADBR NF -inf/-QNaN/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 66D0.10 +*Want "MADB NF -inf/-QNaN/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 66E0.10 +*Want "MADBR NF -inf/-QNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 66F0.10 +*Want "MADB NF -inf/-QNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6700.10 +*Want "MADBR NF -inf/+SNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 6710.10 +*Want "MADB NF -inf/+SNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 6720.10 +*Want "MADBR NF -inf/+SNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 6730.10 +*Want "MADB NF -inf/+SNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 6740.10 +*Want "MADBR NF -inf/+SNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 6750.10 +*Want "MADB NF -inf/+SNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 6760.10 +*Want "MADBR NF -inf/+SNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 6770.10 +*Want "MADB NF -inf/+SNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 6780.10 +*Want "MADBR NF -inf/+SNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 6790.10 +*Want "MADB NF -inf/+SNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 67A0.10 +*Want "MADBR NF -inf/+SNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 67B0.10 +*Want "MADB NF -inf/+SNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 67C0.10 +*Want "MADBR NF -inf/+SNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 67D0.10 +*Want "MADB NF -inf/+SNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 67E0.10 +*Want "MADBR NF -inf/+SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 67F0.10 +*Want "MADB NF -inf/+SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6800.10 +*Want "MADBR NF -2.0/-inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 6810.10 +*Want "MADB NF -2.0/-inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 6820.10 +*Want "MADBR NF -2.0/-inf/-2.0" 7FF00000 00000000 7FF00000 00000000 +r 6830.10 +*Want "MADB NF -2.0/-inf/-2.0" 7FF00000 00000000 7FF00000 00000000 +r 6840.10 +*Want "MADBR NF -2.0/-inf/-0" 7FF00000 00000000 7FF00000 00000000 +r 6850.10 +*Want "MADB NF -2.0/-inf/-0" 7FF00000 00000000 7FF00000 00000000 +r 6860.10 +*Want "MADBR NF -2.0/-inf/+0" 7FF00000 00000000 7FF00000 00000000 +r 6870.10 +*Want "MADB NF -2.0/-inf/+0" 7FF00000 00000000 7FF00000 00000000 +r 6880.10 +*Want "MADBR NF -2.0/-inf/+2.0" 7FF00000 00000000 7FF00000 00000000 +r 6890.10 +*Want "MADB NF -2.0/-inf/+2.0" 7FF00000 00000000 7FF00000 00000000 +r 68A0.10 +*Want "MADBR NF -2.0/-inf/+inf" 7FF00000 00000000 7FF00000 00000000 +r 68B0.10 +*Want "MADB NF -2.0/-inf/+inf" 7FF00000 00000000 7FF00000 00000000 +r 68C0.10 +*Want "MADBR NF -2.0/-inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 68D0.10 +*Want "MADB NF -2.0/-inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 68E0.10 +*Want "MADBR NF -2.0/-inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 68F0.10 +*Want "MADB NF -2.0/-inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6900.10 +*Want "MADBR NF -2.0/-2.0/-inf" FFF00000 00000000 FFF00000 00000000 +r 6910.10 +*Want "MADB NF -2.0/-2.0/-inf" FFF00000 00000000 FFF00000 00000000 +r 6920.10 +*Want "MADBR NF -2.0/-2.0/-2.0" 40000000 00000000 40000000 00000000 +r 6930.10 +*Want "MADB NF -2.0/-2.0/-2.0" 40000000 00000000 40000000 00000000 +r 6940.10 +*Want "MADBR NF -2.0/-2.0/-0" 40100000 00000000 40100000 00000000 +r 6950.10 +*Want "MADB NF -2.0/-2.0/-0" 40100000 00000000 40100000 00000000 +r 6960.10 +*Want "MADBR NF -2.0/-2.0/+0" 40100000 00000000 40100000 00000000 +r 6970.10 +*Want "MADB NF -2.0/-2.0/+0" 40100000 00000000 40100000 00000000 +r 6980.10 +*Want "MADBR NF -2.0/-2.0/+2.0" 40180000 00000000 40180000 00000000 +r 6990.10 +*Want "MADB NF -2.0/-2.0/+2.0" 40180000 00000000 40180000 00000000 +r 69A0.10 +*Want "MADBR NF -2.0/-2.0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 69B0.10 +*Want "MADB NF -2.0/-2.0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 69C0.10 +*Want "MADBR NF -2.0/-2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 69D0.10 +*Want "MADB NF -2.0/-2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 69E0.10 +*Want "MADBR NF -2.0/-2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 69F0.10 +*Want "MADB NF -2.0/-2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6A00.10 +*Want "MADBR NF -2.0/-0/-inf" FFF00000 00000000 FFF00000 00000000 +r 6A10.10 +*Want "MADB NF -2.0/-0/-inf" FFF00000 00000000 FFF00000 00000000 +r 6A20.10 +*Want "MADBR NF -2.0/-0/-2.0" C0000000 00000000 C0000000 00000000 +r 6A30.10 +*Want "MADB NF -2.0/-0/-2.0" C0000000 00000000 C0000000 00000000 +r 6A40.10 +*Want "MADBR NF -2.0/-0/-0" 00000000 00000000 00000000 00000000 +r 6A50.10 +*Want "MADB NF -2.0/-0/-0" 00000000 00000000 00000000 00000000 +r 6A60.10 +*Want "MADBR NF -2.0/-0/+0" 00000000 00000000 00000000 00000000 +r 6A70.10 +*Want "MADB NF -2.0/-0/+0" 00000000 00000000 00000000 00000000 +r 6A80.10 +*Want "MADBR NF -2.0/-0/+2.0" 40000000 00000000 40000000 00000000 +r 6A90.10 +*Want "MADB NF -2.0/-0/+2.0" 40000000 00000000 40000000 00000000 +r 6AA0.10 +*Want "MADBR NF -2.0/-0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 6AB0.10 +*Want "MADB NF -2.0/-0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 6AC0.10 +*Want "MADBR NF -2.0/-0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 6AD0.10 +*Want "MADB NF -2.0/-0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 6AE0.10 +*Want "MADBR NF -2.0/-0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6AF0.10 +*Want "MADB NF -2.0/-0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6B00.10 +*Want "MADBR NF -2.0/+0/-inf" FFF00000 00000000 FFF00000 00000000 +r 6B10.10 +*Want "MADB NF -2.0/+0/-inf" FFF00000 00000000 FFF00000 00000000 +r 6B20.10 +*Want "MADBR NF -2.0/+0/-2.0" C0000000 00000000 C0000000 00000000 +r 6B30.10 +*Want "MADB NF -2.0/+0/-2.0" C0000000 00000000 C0000000 00000000 +r 6B40.10 +*Want "MADBR NF -2.0/+0/-0" 80000000 00000000 80000000 00000000 +r 6B50.10 +*Want "MADB NF -2.0/+0/-0" 80000000 00000000 80000000 00000000 +r 6B60.10 +*Want "MADBR NF -2.0/+0/+0" 00000000 00000000 00000000 00000000 +r 6B70.10 +*Want "MADB NF -2.0/+0/+0" 00000000 00000000 00000000 00000000 +r 6B80.10 +*Want "MADBR NF -2.0/+0/+2.0" 40000000 00000000 40000000 00000000 +r 6B90.10 +*Want "MADB NF -2.0/+0/+2.0" 40000000 00000000 40000000 00000000 +r 6BA0.10 +*Want "MADBR NF -2.0/+0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 6BB0.10 +*Want "MADB NF -2.0/+0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 6BC0.10 +*Want "MADBR NF -2.0/+0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 6BD0.10 +*Want "MADB NF -2.0/+0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 6BE0.10 +*Want "MADBR NF -2.0/+0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6BF0.10 +*Want "MADB NF -2.0/+0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6C00.10 +*Want "MADBR NF -2.0/+2.0/-inf" FFF00000 00000000 FFF00000 00000000 +r 6C10.10 +*Want "MADB NF -2.0/+2.0/-inf" FFF00000 00000000 FFF00000 00000000 +r 6C20.10 +*Want "MADBR NF -2.0/+2.0/-2.0" C0180000 00000000 C0180000 00000000 +r 6C30.10 +*Want "MADB NF -2.0/+2.0/-2.0" C0180000 00000000 C0180000 00000000 +r 6C40.10 +*Want "MADBR NF -2.0/+2.0/-0" C0100000 00000000 C0100000 00000000 +r 6C50.10 +*Want "MADB NF -2.0/+2.0/-0" C0100000 00000000 C0100000 00000000 +r 6C60.10 +*Want "MADBR NF -2.0/+2.0/+0" C0100000 00000000 C0100000 00000000 +r 6C70.10 +*Want "MADB NF -2.0/+2.0/+0" C0100000 00000000 C0100000 00000000 +r 6C80.10 +*Want "MADBR NF -2.0/+2.0/+2.0" C0000000 00000000 C0000000 00000000 +r 6C90.10 +*Want "MADB NF -2.0/+2.0/+2.0" C0000000 00000000 C0000000 00000000 +r 6CA0.10 +*Want "MADBR NF -2.0/+2.0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 6CB0.10 +*Want "MADB NF -2.0/+2.0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 6CC0.10 +*Want "MADBR NF -2.0/+2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 6CD0.10 +*Want "MADB NF -2.0/+2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 6CE0.10 +*Want "MADBR NF -2.0/+2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6CF0.10 +*Want "MADB NF -2.0/+2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6D00.10 +*Want "MADBR NF -2.0/+inf/-inf" FFF00000 00000000 FFF00000 00000000 +r 6D10.10 +*Want "MADB NF -2.0/+inf/-inf" FFF00000 00000000 FFF00000 00000000 +r 6D20.10 +*Want "MADBR NF -2.0/+inf/-2.0" FFF00000 00000000 FFF00000 00000000 +r 6D30.10 +*Want "MADB NF -2.0/+inf/-2.0" FFF00000 00000000 FFF00000 00000000 +r 6D40.10 +*Want "MADBR NF -2.0/+inf/-0" FFF00000 00000000 FFF00000 00000000 +r 6D50.10 +*Want "MADB NF -2.0/+inf/-0" FFF00000 00000000 FFF00000 00000000 +r 6D60.10 +*Want "MADBR NF -2.0/+inf/+0" FFF00000 00000000 FFF00000 00000000 +r 6D70.10 +*Want "MADB NF -2.0/+inf/+0" FFF00000 00000000 FFF00000 00000000 +r 6D80.10 +*Want "MADBR NF -2.0/+inf/+2.0" FFF00000 00000000 FFF00000 00000000 +r 6D90.10 +*Want "MADB NF -2.0/+inf/+2.0" FFF00000 00000000 FFF00000 00000000 +r 6DA0.10 +*Want "MADBR NF -2.0/+inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 6DB0.10 +*Want "MADB NF -2.0/+inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 6DC0.10 +*Want "MADBR NF -2.0/+inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 6DD0.10 +*Want "MADB NF -2.0/+inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 6DE0.10 +*Want "MADBR NF -2.0/+inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6DF0.10 +*Want "MADB NF -2.0/+inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6E00.10 +*Want "MADBR NF -2.0/-QNaN/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 6E10.10 +*Want "MADB NF -2.0/-QNaN/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 6E20.10 +*Want "MADBR NF -2.0/-QNaN/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 6E30.10 +*Want "MADB NF -2.0/-QNaN/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 6E40.10 +*Want "MADBR NF -2.0/-QNaN/-0" FFF8B000 00000000 FFF8B000 00000000 +r 6E50.10 +*Want "MADB NF -2.0/-QNaN/-0" FFF8B000 00000000 FFF8B000 00000000 +r 6E60.10 +*Want "MADBR NF -2.0/-QNaN/+0" FFF8B000 00000000 FFF8B000 00000000 +r 6E70.10 +*Want "MADB NF -2.0/-QNaN/+0" FFF8B000 00000000 FFF8B000 00000000 +r 6E80.10 +*Want "MADBR NF -2.0/-QNaN/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 6E90.10 +*Want "MADB NF -2.0/-QNaN/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 6EA0.10 +*Want "MADBR NF -2.0/-QNaN/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 6EB0.10 +*Want "MADB NF -2.0/-QNaN/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 6EC0.10 +*Want "MADBR NF -2.0/-QNaN/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 6ED0.10 +*Want "MADB NF -2.0/-QNaN/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 6EE0.10 +*Want "MADBR NF -2.0/-QNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6EF0.10 +*Want "MADB NF -2.0/-QNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6F00.10 +*Want "MADBR NF -2.0/+SNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 6F10.10 +*Want "MADB NF -2.0/+SNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 6F20.10 +*Want "MADBR NF -2.0/+SNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 6F30.10 +*Want "MADB NF -2.0/+SNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 6F40.10 +*Want "MADBR NF -2.0/+SNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 6F50.10 +*Want "MADB NF -2.0/+SNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 6F60.10 +*Want "MADBR NF -2.0/+SNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 6F70.10 +*Want "MADB NF -2.0/+SNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 6F80.10 +*Want "MADBR NF -2.0/+SNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 6F90.10 +*Want "MADB NF -2.0/+SNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 6FA0.10 +*Want "MADBR NF -2.0/+SNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 6FB0.10 +*Want "MADB NF -2.0/+SNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 6FC0.10 +*Want "MADBR NF -2.0/+SNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 6FD0.10 +*Want "MADB NF -2.0/+SNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 6FE0.10 +*Want "MADBR NF -2.0/+SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6FF0.10 +*Want "MADB NF -2.0/+SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 7000.10 +*Want "MADBR NF -0/-inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 7010.10 +*Want "MADB NF -0/-inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 7020.10 +*Want "MADBR NF -0/-inf/-2.0" 7FF80000 00000000 C0000000 00000000 +r 7030.10 +*Want "MADB NF -0/-inf/-2.0" 7FF80000 00000000 C0000000 00000000 +r 7040.10 +*Want "MADBR NF -0/-inf/-0" 7FF80000 00000000 80000000 00000000 +r 7050.10 +*Want "MADB NF -0/-inf/-0" 7FF80000 00000000 80000000 00000000 +r 7060.10 +*Want "MADBR NF -0/-inf/+0" 7FF80000 00000000 00000000 00000000 +r 7070.10 +*Want "MADB NF -0/-inf/+0" 7FF80000 00000000 00000000 00000000 +r 7080.10 +*Want "MADBR NF -0/-inf/+2.0" 7FF80000 00000000 40000000 00000000 +r 7090.10 +*Want "MADB NF -0/-inf/+2.0" 7FF80000 00000000 40000000 00000000 +r 70A0.10 +*Want "MADBR NF -0/-inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 70B0.10 +*Want "MADB NF -0/-inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 70C0.10 +*Want "MADBR NF -0/-inf/-QNaN" 7FF80000 00000000 FFF8B000 00000000 +r 70D0.10 +*Want "MADB NF -0/-inf/-QNaN" 7FF80000 00000000 FFF8B000 00000000 +r 70E0.10 +*Want "MADBR NF -0/-inf/+SNaN" 7FF80000 00000000 7FF0A000 00000000 +r 70F0.10 +*Want "MADB NF -0/-inf/+SNaN" 7FF80000 00000000 7FF0A000 00000000 +r 7100.10 +*Want "MADBR NF -0/-2.0/-inf" FFF00000 00000000 FFF00000 00000000 +r 7110.10 +*Want "MADB NF -0/-2.0/-inf" FFF00000 00000000 FFF00000 00000000 +r 7120.10 +*Want "MADBR NF -0/-2.0/-2.0" C0000000 00000000 C0000000 00000000 +r 7130.10 +*Want "MADB NF -0/-2.0/-2.0" C0000000 00000000 C0000000 00000000 +r 7140.10 +*Want "MADBR NF -0/-2.0/-0" 00000000 00000000 00000000 00000000 +r 7150.10 +*Want "MADB NF -0/-2.0/-0" 00000000 00000000 00000000 00000000 +r 7160.10 +*Want "MADBR NF -0/-2.0/+0" 00000000 00000000 00000000 00000000 +r 7170.10 +*Want "MADB NF -0/-2.0/+0" 00000000 00000000 00000000 00000000 +r 7180.10 +*Want "MADBR NF -0/-2.0/+2.0" 40000000 00000000 40000000 00000000 +r 7190.10 +*Want "MADB NF -0/-2.0/+2.0" 40000000 00000000 40000000 00000000 +r 71A0.10 +*Want "MADBR NF -0/-2.0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 71B0.10 +*Want "MADB NF -0/-2.0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 71C0.10 +*Want "MADBR NF -0/-2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 71D0.10 +*Want "MADB NF -0/-2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 71E0.10 +*Want "MADBR NF -0/-2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 71F0.10 +*Want "MADB NF -0/-2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 7200.10 +*Want "MADBR NF -0/-0/-inf" FFF00000 00000000 FFF00000 00000000 +r 7210.10 +*Want "MADB NF -0/-0/-inf" FFF00000 00000000 FFF00000 00000000 +r 7220.10 +*Want "MADBR NF -0/-0/-2.0" C0000000 00000000 C0000000 00000000 +r 7230.10 +*Want "MADB NF -0/-0/-2.0" C0000000 00000000 C0000000 00000000 +r 7240.10 +*Want "MADBR NF -0/-0/-0" 00000000 00000000 00000000 00000000 +r 7250.10 +*Want "MADB NF -0/-0/-0" 00000000 00000000 00000000 00000000 +r 7260.10 +*Want "MADBR NF -0/-0/+0" 00000000 00000000 00000000 00000000 +r 7270.10 +*Want "MADB NF -0/-0/+0" 00000000 00000000 00000000 00000000 +r 7280.10 +*Want "MADBR NF -0/-0/+2.0" 40000000 00000000 40000000 00000000 +r 7290.10 +*Want "MADB NF -0/-0/+2.0" 40000000 00000000 40000000 00000000 +r 72A0.10 +*Want "MADBR NF -0/-0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 72B0.10 +*Want "MADB NF -0/-0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 72C0.10 +*Want "MADBR NF -0/-0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 72D0.10 +*Want "MADB NF -0/-0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 72E0.10 +*Want "MADBR NF -0/-0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 72F0.10 +*Want "MADB NF -0/-0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 7300.10 +*Want "MADBR NF -0/+0/-inf" FFF00000 00000000 FFF00000 00000000 +r 7310.10 +*Want "MADB NF -0/+0/-inf" FFF00000 00000000 FFF00000 00000000 +r 7320.10 +*Want "MADBR NF -0/+0/-2.0" C0000000 00000000 C0000000 00000000 +r 7330.10 +*Want "MADB NF -0/+0/-2.0" C0000000 00000000 C0000000 00000000 +r 7340.10 +*Want "MADBR NF -0/+0/-0" 80000000 00000000 80000000 00000000 +r 7350.10 +*Want "MADB NF -0/+0/-0" 80000000 00000000 80000000 00000000 +r 7360.10 +*Want "MADBR NF -0/+0/+0" 00000000 00000000 00000000 00000000 +r 7370.10 +*Want "MADB NF -0/+0/+0" 00000000 00000000 00000000 00000000 +r 7380.10 +*Want "MADBR NF -0/+0/+2.0" 40000000 00000000 40000000 00000000 +r 7390.10 +*Want "MADB NF -0/+0/+2.0" 40000000 00000000 40000000 00000000 +r 73A0.10 +*Want "MADBR NF -0/+0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 73B0.10 +*Want "MADB NF -0/+0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 73C0.10 +*Want "MADBR NF -0/+0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 73D0.10 +*Want "MADB NF -0/+0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 73E0.10 +*Want "MADBR NF -0/+0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 73F0.10 +*Want "MADB NF -0/+0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 7400.10 +*Want "MADBR NF -0/+2.0/-inf" FFF00000 00000000 FFF00000 00000000 +r 7410.10 +*Want "MADB NF -0/+2.0/-inf" FFF00000 00000000 FFF00000 00000000 +r 7420.10 +*Want "MADBR NF -0/+2.0/-2.0" C0000000 00000000 C0000000 00000000 +r 7430.10 +*Want "MADB NF -0/+2.0/-2.0" C0000000 00000000 C0000000 00000000 +r 7440.10 +*Want "MADBR NF -0/+2.0/-0" 80000000 00000000 80000000 00000000 +r 7450.10 +*Want "MADB NF -0/+2.0/-0" 80000000 00000000 80000000 00000000 +r 7460.10 +*Want "MADBR NF -0/+2.0/+0" 00000000 00000000 00000000 00000000 +r 7470.10 +*Want "MADB NF -0/+2.0/+0" 00000000 00000000 00000000 00000000 +r 7480.10 +*Want "MADBR NF -0/+2.0/+2.0" 40000000 00000000 40000000 00000000 +r 7490.10 +*Want "MADB NF -0/+2.0/+2.0" 40000000 00000000 40000000 00000000 +r 74A0.10 +*Want "MADBR NF -0/+2.0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 74B0.10 +*Want "MADB NF -0/+2.0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 74C0.10 +*Want "MADBR NF -0/+2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 74D0.10 +*Want "MADB NF -0/+2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 74E0.10 +*Want "MADBR NF -0/+2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 74F0.10 +*Want "MADB NF -0/+2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 7500.10 +*Want "MADBR NF -0/+inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 7510.10 +*Want "MADB NF -0/+inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 7520.10 +*Want "MADBR NF -0/+inf/-2.0" 7FF80000 00000000 C0000000 00000000 +r 7530.10 +*Want "MADB NF -0/+inf/-2.0" 7FF80000 00000000 C0000000 00000000 +r 7540.10 +*Want "MADBR NF -0/+inf/-0" 7FF80000 00000000 80000000 00000000 +r 7550.10 +*Want "MADB NF -0/+inf/-0" 7FF80000 00000000 80000000 00000000 +r 7560.10 +*Want "MADBR NF -0/+inf/+0" 7FF80000 00000000 00000000 00000000 +r 7570.10 +*Want "MADB NF -0/+inf/+0" 7FF80000 00000000 00000000 00000000 +r 7580.10 +*Want "MADBR NF -0/+inf/+2.0" 7FF80000 00000000 40000000 00000000 +r 7590.10 +*Want "MADB NF -0/+inf/+2.0" 7FF80000 00000000 40000000 00000000 +r 75A0.10 +*Want "MADBR NF -0/+inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 75B0.10 +*Want "MADB NF -0/+inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 75C0.10 +*Want "MADBR NF -0/+inf/-QNaN" 7FF80000 00000000 FFF8B000 00000000 +r 75D0.10 +*Want "MADB NF -0/+inf/-QNaN" 7FF80000 00000000 FFF8B000 00000000 +r 75E0.10 +*Want "MADBR NF -0/+inf/+SNaN" 7FF80000 00000000 7FF0A000 00000000 +r 75F0.10 +*Want "MADB NF -0/+inf/+SNaN" 7FF80000 00000000 7FF0A000 00000000 +r 7600.10 +*Want "MADBR NF -0/-QNaN/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 7610.10 +*Want "MADB NF -0/-QNaN/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 7620.10 +*Want "MADBR NF -0/-QNaN/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 7630.10 +*Want "MADB NF -0/-QNaN/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 7640.10 +*Want "MADBR NF -0/-QNaN/-0" FFF8B000 00000000 FFF8B000 00000000 +r 7650.10 +*Want "MADB NF -0/-QNaN/-0" FFF8B000 00000000 FFF8B000 00000000 +r 7660.10 +*Want "MADBR NF -0/-QNaN/+0" FFF8B000 00000000 FFF8B000 00000000 +r 7670.10 +*Want "MADB NF -0/-QNaN/+0" FFF8B000 00000000 FFF8B000 00000000 +r 7680.10 +*Want "MADBR NF -0/-QNaN/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 7690.10 +*Want "MADB NF -0/-QNaN/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 76A0.10 +*Want "MADBR NF -0/-QNaN/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 76B0.10 +*Want "MADB NF -0/-QNaN/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 76C0.10 +*Want "MADBR NF -0/-QNaN/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 76D0.10 +*Want "MADB NF -0/-QNaN/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 76E0.10 +*Want "MADBR NF -0/-QNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 76F0.10 +*Want "MADB NF -0/-QNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 7700.10 +*Want "MADBR NF -0/+SNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 7710.10 +*Want "MADB NF -0/+SNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 7720.10 +*Want "MADBR NF -0/+SNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 7730.10 +*Want "MADB NF -0/+SNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 7740.10 +*Want "MADBR NF -0/+SNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 7750.10 +*Want "MADB NF -0/+SNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 7760.10 +*Want "MADBR NF -0/+SNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 7770.10 +*Want "MADB NF -0/+SNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 7780.10 +*Want "MADBR NF -0/+SNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 7790.10 +*Want "MADB NF -0/+SNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 77A0.10 +*Want "MADBR NF -0/+SNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 77B0.10 +*Want "MADB NF -0/+SNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 77C0.10 +*Want "MADBR NF -0/+SNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 77D0.10 +*Want "MADB NF -0/+SNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 77E0.10 +*Want "MADBR NF -0/+SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 77F0.10 +*Want "MADB NF -0/+SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 7800.10 +*Want "MADBR NF +0/-inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 7810.10 +*Want "MADB NF +0/-inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 7820.10 +*Want "MADBR NF +0/-inf/-2.0" 7FF80000 00000000 C0000000 00000000 +r 7830.10 +*Want "MADB NF +0/-inf/-2.0" 7FF80000 00000000 C0000000 00000000 +r 7840.10 +*Want "MADBR NF +0/-inf/-0" 7FF80000 00000000 80000000 00000000 +r 7850.10 +*Want "MADB NF +0/-inf/-0" 7FF80000 00000000 80000000 00000000 +r 7860.10 +*Want "MADBR NF +0/-inf/+0" 7FF80000 00000000 00000000 00000000 +r 7870.10 +*Want "MADB NF +0/-inf/+0" 7FF80000 00000000 00000000 00000000 +r 7880.10 +*Want "MADBR NF +0/-inf/+2.0" 7FF80000 00000000 40000000 00000000 +r 7890.10 +*Want "MADB NF +0/-inf/+2.0" 7FF80000 00000000 40000000 00000000 +r 78A0.10 +*Want "MADBR NF +0/-inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 78B0.10 +*Want "MADB NF +0/-inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 78C0.10 +*Want "MADBR NF +0/-inf/-QNaN" 7FF80000 00000000 FFF8B000 00000000 +r 78D0.10 +*Want "MADB NF +0/-inf/-QNaN" 7FF80000 00000000 FFF8B000 00000000 +r 78E0.10 +*Want "MADBR NF +0/-inf/+SNaN" 7FF80000 00000000 7FF0A000 00000000 +r 78F0.10 +*Want "MADB NF +0/-inf/+SNaN" 7FF80000 00000000 7FF0A000 00000000 +r 7900.10 +*Want "MADBR NF +0/-2.0/-inf" FFF00000 00000000 FFF00000 00000000 +r 7910.10 +*Want "MADB NF +0/-2.0/-inf" FFF00000 00000000 FFF00000 00000000 +r 7920.10 +*Want "MADBR NF +0/-2.0/-2.0" C0000000 00000000 C0000000 00000000 +r 7930.10 +*Want "MADB NF +0/-2.0/-2.0" C0000000 00000000 C0000000 00000000 +r 7940.10 +*Want "MADBR NF +0/-2.0/-0" 80000000 00000000 80000000 00000000 +r 7950.10 +*Want "MADB NF +0/-2.0/-0" 80000000 00000000 80000000 00000000 +r 7960.10 +*Want "MADBR NF +0/-2.0/+0" 00000000 00000000 00000000 00000000 +r 7970.10 +*Want "MADB NF +0/-2.0/+0" 00000000 00000000 00000000 00000000 +r 7980.10 +*Want "MADBR NF +0/-2.0/+2.0" 40000000 00000000 40000000 00000000 +r 7990.10 +*Want "MADB NF +0/-2.0/+2.0" 40000000 00000000 40000000 00000000 +r 79A0.10 +*Want "MADBR NF +0/-2.0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 79B0.10 +*Want "MADB NF +0/-2.0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 79C0.10 +*Want "MADBR NF +0/-2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 79D0.10 +*Want "MADB NF +0/-2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 79E0.10 +*Want "MADBR NF +0/-2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 79F0.10 +*Want "MADB NF +0/-2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 7A00.10 +*Want "MADBR NF +0/-0/-inf" FFF00000 00000000 FFF00000 00000000 +r 7A10.10 +*Want "MADB NF +0/-0/-inf" FFF00000 00000000 FFF00000 00000000 +r 7A20.10 +*Want "MADBR NF +0/-0/-2.0" C0000000 00000000 C0000000 00000000 +r 7A30.10 +*Want "MADB NF +0/-0/-2.0" C0000000 00000000 C0000000 00000000 +r 7A40.10 +*Want "MADBR NF +0/-0/-0" 80000000 00000000 80000000 00000000 +r 7A50.10 +*Want "MADB NF +0/-0/-0" 80000000 00000000 80000000 00000000 +r 7A60.10 +*Want "MADBR NF +0/-0/+0" 00000000 00000000 00000000 00000000 +r 7A70.10 +*Want "MADB NF +0/-0/+0" 00000000 00000000 00000000 00000000 +r 7A80.10 +*Want "MADBR NF +0/-0/+2.0" 40000000 00000000 40000000 00000000 +r 7A90.10 +*Want "MADB NF +0/-0/+2.0" 40000000 00000000 40000000 00000000 +r 7AA0.10 +*Want "MADBR NF +0/-0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 7AB0.10 +*Want "MADB NF +0/-0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 7AC0.10 +*Want "MADBR NF +0/-0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 7AD0.10 +*Want "MADB NF +0/-0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 7AE0.10 +*Want "MADBR NF +0/-0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 7AF0.10 +*Want "MADB NF +0/-0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 7B00.10 +*Want "MADBR NF +0/+0/-inf" FFF00000 00000000 FFF00000 00000000 +r 7B10.10 +*Want "MADB NF +0/+0/-inf" FFF00000 00000000 FFF00000 00000000 +r 7B20.10 +*Want "MADBR NF +0/+0/-2.0" C0000000 00000000 C0000000 00000000 +r 7B30.10 +*Want "MADB NF +0/+0/-2.0" C0000000 00000000 C0000000 00000000 +r 7B40.10 +*Want "MADBR NF +0/+0/-0" 00000000 00000000 00000000 00000000 +r 7B50.10 +*Want "MADB NF +0/+0/-0" 00000000 00000000 00000000 00000000 +r 7B60.10 +*Want "MADBR NF +0/+0/+0" 00000000 00000000 00000000 00000000 +r 7B70.10 +*Want "MADB NF +0/+0/+0" 00000000 00000000 00000000 00000000 +r 7B80.10 +*Want "MADBR NF +0/+0/+2.0" 40000000 00000000 40000000 00000000 +r 7B90.10 +*Want "MADB NF +0/+0/+2.0" 40000000 00000000 40000000 00000000 +r 7BA0.10 +*Want "MADBR NF +0/+0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 7BB0.10 +*Want "MADB NF +0/+0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 7BC0.10 +*Want "MADBR NF +0/+0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 7BD0.10 +*Want "MADB NF +0/+0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 7BE0.10 +*Want "MADBR NF +0/+0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 7BF0.10 +*Want "MADB NF +0/+0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 7C00.10 +*Want "MADBR NF +0/+2.0/-inf" FFF00000 00000000 FFF00000 00000000 +r 7C10.10 +*Want "MADB NF +0/+2.0/-inf" FFF00000 00000000 FFF00000 00000000 +r 7C20.10 +*Want "MADBR NF +0/+2.0/-2.0" C0000000 00000000 C0000000 00000000 +r 7C30.10 +*Want "MADB NF +0/+2.0/-2.0" C0000000 00000000 C0000000 00000000 +r 7C40.10 +*Want "MADBR NF +0/+2.0/-0" 00000000 00000000 00000000 00000000 +r 7C50.10 +*Want "MADB NF +0/+2.0/-0" 00000000 00000000 00000000 00000000 +r 7C60.10 +*Want "MADBR NF +0/+2.0/+0" 00000000 00000000 00000000 00000000 +r 7C70.10 +*Want "MADB NF +0/+2.0/+0" 00000000 00000000 00000000 00000000 +r 7C80.10 +*Want "MADBR NF +0/+2.0/+2.0" 40000000 00000000 40000000 00000000 +r 7C90.10 +*Want "MADB NF +0/+2.0/+2.0" 40000000 00000000 40000000 00000000 +r 7CA0.10 +*Want "MADBR NF +0/+2.0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 7CB0.10 +*Want "MADB NF +0/+2.0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 7CC0.10 +*Want "MADBR NF +0/+2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 7CD0.10 +*Want "MADB NF +0/+2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 7CE0.10 +*Want "MADBR NF +0/+2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 7CF0.10 +*Want "MADB NF +0/+2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 7D00.10 +*Want "MADBR NF +0/+inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 7D10.10 +*Want "MADB NF +0/+inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 7D20.10 +*Want "MADBR NF +0/+inf/-2.0" 7FF80000 00000000 C0000000 00000000 +r 7D30.10 +*Want "MADB NF +0/+inf/-2.0" 7FF80000 00000000 C0000000 00000000 +r 7D40.10 +*Want "MADBR NF +0/+inf/-0" 7FF80000 00000000 80000000 00000000 +r 7D50.10 +*Want "MADB NF +0/+inf/-0" 7FF80000 00000000 80000000 00000000 +r 7D60.10 +*Want "MADBR NF +0/+inf/+0" 7FF80000 00000000 00000000 00000000 +r 7D70.10 +*Want "MADB NF +0/+inf/+0" 7FF80000 00000000 00000000 00000000 +r 7D80.10 +*Want "MADBR NF +0/+inf/+2.0" 7FF80000 00000000 40000000 00000000 +r 7D90.10 +*Want "MADB NF +0/+inf/+2.0" 7FF80000 00000000 40000000 00000000 +r 7DA0.10 +*Want "MADBR NF +0/+inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 7DB0.10 +*Want "MADB NF +0/+inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 7DC0.10 +*Want "MADBR NF +0/+inf/-QNaN" 7FF80000 00000000 FFF8B000 00000000 +r 7DD0.10 +*Want "MADB NF +0/+inf/-QNaN" 7FF80000 00000000 FFF8B000 00000000 +r 7DE0.10 +*Want "MADBR NF +0/+inf/+SNaN" 7FF80000 00000000 7FF0A000 00000000 +r 7DF0.10 +*Want "MADB NF +0/+inf/+SNaN" 7FF80000 00000000 7FF0A000 00000000 +r 7E00.10 +*Want "MADBR NF +0/-QNaN/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 7E10.10 +*Want "MADB NF +0/-QNaN/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 7E20.10 +*Want "MADBR NF +0/-QNaN/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 7E30.10 +*Want "MADB NF +0/-QNaN/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 7E40.10 +*Want "MADBR NF +0/-QNaN/-0" FFF8B000 00000000 FFF8B000 00000000 +r 7E50.10 +*Want "MADB NF +0/-QNaN/-0" FFF8B000 00000000 FFF8B000 00000000 +r 7E60.10 +*Want "MADBR NF +0/-QNaN/+0" FFF8B000 00000000 FFF8B000 00000000 +r 7E70.10 +*Want "MADB NF +0/-QNaN/+0" FFF8B000 00000000 FFF8B000 00000000 +r 7E80.10 +*Want "MADBR NF +0/-QNaN/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 7E90.10 +*Want "MADB NF +0/-QNaN/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 7EA0.10 +*Want "MADBR NF +0/-QNaN/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 7EB0.10 +*Want "MADB NF +0/-QNaN/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 7EC0.10 +*Want "MADBR NF +0/-QNaN/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 7ED0.10 +*Want "MADB NF +0/-QNaN/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 7EE0.10 +*Want "MADBR NF +0/-QNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 7EF0.10 +*Want "MADB NF +0/-QNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 7F00.10 +*Want "MADBR NF +0/+SNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 7F10.10 +*Want "MADB NF +0/+SNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 7F20.10 +*Want "MADBR NF +0/+SNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 7F30.10 +*Want "MADB NF +0/+SNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 7F40.10 +*Want "MADBR NF +0/+SNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 7F50.10 +*Want "MADB NF +0/+SNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 7F60.10 +*Want "MADBR NF +0/+SNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 7F70.10 +*Want "MADB NF +0/+SNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 7F80.10 +*Want "MADBR NF +0/+SNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 7F90.10 +*Want "MADB NF +0/+SNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 7FA0.10 +*Want "MADBR NF +0/+SNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 7FB0.10 +*Want "MADB NF +0/+SNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 7FC0.10 +*Want "MADBR NF +0/+SNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 7FD0.10 +*Want "MADB NF +0/+SNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 7FE0.10 +*Want "MADBR NF +0/+SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 7FF0.10 +*Want "MADB NF +0/+SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8000.10 +*Want "MADBR NF +2.0/-inf/-inf" FFF00000 00000000 FFF00000 00000000 +r 8010.10 +*Want "MADB NF +2.0/-inf/-inf" FFF00000 00000000 FFF00000 00000000 +r 8020.10 +*Want "MADBR NF +2.0/-inf/-2.0" FFF00000 00000000 FFF00000 00000000 +r 8030.10 +*Want "MADB NF +2.0/-inf/-2.0" FFF00000 00000000 FFF00000 00000000 +r 8040.10 +*Want "MADBR NF +2.0/-inf/-0" FFF00000 00000000 FFF00000 00000000 +r 8050.10 +*Want "MADB NF +2.0/-inf/-0" FFF00000 00000000 FFF00000 00000000 +r 8060.10 +*Want "MADBR NF +2.0/-inf/+0" FFF00000 00000000 FFF00000 00000000 +r 8070.10 +*Want "MADB NF +2.0/-inf/+0" FFF00000 00000000 FFF00000 00000000 +r 8080.10 +*Want "MADBR NF +2.0/-inf/+2.0" FFF00000 00000000 FFF00000 00000000 +r 8090.10 +*Want "MADB NF +2.0/-inf/+2.0" FFF00000 00000000 FFF00000 00000000 +r 80A0.10 +*Want "MADBR NF +2.0/-inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 80B0.10 +*Want "MADB NF +2.0/-inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 80C0.10 +*Want "MADBR NF +2.0/-inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 80D0.10 +*Want "MADB NF +2.0/-inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 80E0.10 +*Want "MADBR NF +2.0/-inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 80F0.10 +*Want "MADB NF +2.0/-inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8100.10 +*Want "MADBR NF +2.0/-2.0/-inf" FFF00000 00000000 FFF00000 00000000 +r 8110.10 +*Want "MADB NF +2.0/-2.0/-inf" FFF00000 00000000 FFF00000 00000000 +r 8120.10 +*Want "MADBR NF +2.0/-2.0/-2.0" C0180000 00000000 C0180000 00000000 +r 8130.10 +*Want "MADB NF +2.0/-2.0/-2.0" C0180000 00000000 C0180000 00000000 +r 8140.10 +*Want "MADBR NF +2.0/-2.0/-0" C0100000 00000000 C0100000 00000000 +r 8150.10 +*Want "MADB NF +2.0/-2.0/-0" C0100000 00000000 C0100000 00000000 +r 8160.10 +*Want "MADBR NF +2.0/-2.0/+0" C0100000 00000000 C0100000 00000000 +r 8170.10 +*Want "MADB NF +2.0/-2.0/+0" C0100000 00000000 C0100000 00000000 +r 8180.10 +*Want "MADBR NF +2.0/-2.0/+2.0" C0000000 00000000 C0000000 00000000 +r 8190.10 +*Want "MADB NF +2.0/-2.0/+2.0" C0000000 00000000 C0000000 00000000 +r 81A0.10 +*Want "MADBR NF +2.0/-2.0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 81B0.10 +*Want "MADB NF +2.0/-2.0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 81C0.10 +*Want "MADBR NF +2.0/-2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 81D0.10 +*Want "MADB NF +2.0/-2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 81E0.10 +*Want "MADBR NF +2.0/-2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 81F0.10 +*Want "MADB NF +2.0/-2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8200.10 +*Want "MADBR NF +2.0/-0/-inf" FFF00000 00000000 FFF00000 00000000 +r 8210.10 +*Want "MADB NF +2.0/-0/-inf" FFF00000 00000000 FFF00000 00000000 +r 8220.10 +*Want "MADBR NF +2.0/-0/-2.0" C0000000 00000000 C0000000 00000000 +r 8230.10 +*Want "MADB NF +2.0/-0/-2.0" C0000000 00000000 C0000000 00000000 +r 8240.10 +*Want "MADBR NF +2.0/-0/-0" 80000000 00000000 80000000 00000000 +r 8250.10 +*Want "MADB NF +2.0/-0/-0" 80000000 00000000 80000000 00000000 +r 8260.10 +*Want "MADBR NF +2.0/-0/+0" 00000000 00000000 00000000 00000000 +r 8270.10 +*Want "MADB NF +2.0/-0/+0" 00000000 00000000 00000000 00000000 +r 8280.10 +*Want "MADBR NF +2.0/-0/+2.0" 40000000 00000000 40000000 00000000 +r 8290.10 +*Want "MADB NF +2.0/-0/+2.0" 40000000 00000000 40000000 00000000 +r 82A0.10 +*Want "MADBR NF +2.0/-0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 82B0.10 +*Want "MADB NF +2.0/-0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 82C0.10 +*Want "MADBR NF +2.0/-0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 82D0.10 +*Want "MADB NF +2.0/-0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 82E0.10 +*Want "MADBR NF +2.0/-0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 82F0.10 +*Want "MADB NF +2.0/-0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8300.10 +*Want "MADBR NF +2.0/+0/-inf" FFF00000 00000000 FFF00000 00000000 +r 8310.10 +*Want "MADB NF +2.0/+0/-inf" FFF00000 00000000 FFF00000 00000000 +r 8320.10 +*Want "MADBR NF +2.0/+0/-2.0" C0000000 00000000 C0000000 00000000 +r 8330.10 +*Want "MADB NF +2.0/+0/-2.0" C0000000 00000000 C0000000 00000000 +r 8340.10 +*Want "MADBR NF +2.0/+0/-0" 00000000 00000000 00000000 00000000 +r 8350.10 +*Want "MADB NF +2.0/+0/-0" 00000000 00000000 00000000 00000000 +r 8360.10 +*Want "MADBR NF +2.0/+0/+0" 00000000 00000000 00000000 00000000 +r 8370.10 +*Want "MADB NF +2.0/+0/+0" 00000000 00000000 00000000 00000000 +r 8380.10 +*Want "MADBR NF +2.0/+0/+2.0" 40000000 00000000 40000000 00000000 +r 8390.10 +*Want "MADB NF +2.0/+0/+2.0" 40000000 00000000 40000000 00000000 +r 83A0.10 +*Want "MADBR NF +2.0/+0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 83B0.10 +*Want "MADB NF +2.0/+0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 83C0.10 +*Want "MADBR NF +2.0/+0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 83D0.10 +*Want "MADB NF +2.0/+0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 83E0.10 +*Want "MADBR NF +2.0/+0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 83F0.10 +*Want "MADB NF +2.0/+0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8400.10 +*Want "MADBR NF +2.0/+2.0/-inf" FFF00000 00000000 FFF00000 00000000 +r 8410.10 +*Want "MADB NF +2.0/+2.0/-inf" FFF00000 00000000 FFF00000 00000000 +r 8420.10 +*Want "MADBR NF +2.0/+2.0/-2.0" 40000000 00000000 40000000 00000000 +r 8430.10 +*Want "MADB NF +2.0/+2.0/-2.0" 40000000 00000000 40000000 00000000 +r 8440.10 +*Want "MADBR NF +2.0/+2.0/-0" 40100000 00000000 40100000 00000000 +r 8450.10 +*Want "MADB NF +2.0/+2.0/-0" 40100000 00000000 40100000 00000000 +r 8460.10 +*Want "MADBR NF +2.0/+2.0/+0" 40100000 00000000 40100000 00000000 +r 8470.10 +*Want "MADB NF +2.0/+2.0/+0" 40100000 00000000 40100000 00000000 +r 8480.10 +*Want "MADBR NF +2.0/+2.0/+2.0" 40180000 00000000 40180000 00000000 +r 8490.10 +*Want "MADB NF +2.0/+2.0/+2.0" 40180000 00000000 40180000 00000000 +r 84A0.10 +*Want "MADBR NF +2.0/+2.0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 84B0.10 +*Want "MADB NF +2.0/+2.0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 84C0.10 +*Want "MADBR NF +2.0/+2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 84D0.10 +*Want "MADB NF +2.0/+2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 84E0.10 +*Want "MADBR NF +2.0/+2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 84F0.10 +*Want "MADB NF +2.0/+2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8500.10 +*Want "MADBR NF +2.0/+inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 8510.10 +*Want "MADB NF +2.0/+inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 8520.10 +*Want "MADBR NF +2.0/+inf/-2.0" 7FF00000 00000000 7FF00000 00000000 +r 8530.10 +*Want "MADB NF +2.0/+inf/-2.0" 7FF00000 00000000 7FF00000 00000000 +r 8540.10 +*Want "MADBR NF +2.0/+inf/-0" 7FF00000 00000000 7FF00000 00000000 +r 8550.10 +*Want "MADB NF +2.0/+inf/-0" 7FF00000 00000000 7FF00000 00000000 +r 8560.10 +*Want "MADBR NF +2.0/+inf/+0" 7FF00000 00000000 7FF00000 00000000 +r 8570.10 +*Want "MADB NF +2.0/+inf/+0" 7FF00000 00000000 7FF00000 00000000 +r 8580.10 +*Want "MADBR NF +2.0/+inf/+2.0" 7FF00000 00000000 7FF00000 00000000 +r 8590.10 +*Want "MADB NF +2.0/+inf/+2.0" 7FF00000 00000000 7FF00000 00000000 +r 85A0.10 +*Want "MADBR NF +2.0/+inf/+inf" 7FF00000 00000000 7FF00000 00000000 +r 85B0.10 +*Want "MADB NF +2.0/+inf/+inf" 7FF00000 00000000 7FF00000 00000000 +r 85C0.10 +*Want "MADBR NF +2.0/+inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 85D0.10 +*Want "MADB NF +2.0/+inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 85E0.10 +*Want "MADBR NF +2.0/+inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 85F0.10 +*Want "MADB NF +2.0/+inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8600.10 +*Want "MADBR NF +2.0/-QNaN/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 8610.10 +*Want "MADB NF +2.0/-QNaN/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 8620.10 +*Want "MADBR NF +2.0/-QNaN/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 8630.10 +*Want "MADB NF +2.0/-QNaN/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 8640.10 +*Want "MADBR NF +2.0/-QNaN/-0" FFF8B000 00000000 FFF8B000 00000000 +r 8650.10 +*Want "MADB NF +2.0/-QNaN/-0" FFF8B000 00000000 FFF8B000 00000000 +r 8660.10 +*Want "MADBR NF +2.0/-QNaN/+0" FFF8B000 00000000 FFF8B000 00000000 +r 8670.10 +*Want "MADB NF +2.0/-QNaN/+0" FFF8B000 00000000 FFF8B000 00000000 +r 8680.10 +*Want "MADBR NF +2.0/-QNaN/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 8690.10 +*Want "MADB NF +2.0/-QNaN/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 86A0.10 +*Want "MADBR NF +2.0/-QNaN/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 86B0.10 +*Want "MADB NF +2.0/-QNaN/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 86C0.10 +*Want "MADBR NF +2.0/-QNaN/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 86D0.10 +*Want "MADB NF +2.0/-QNaN/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 86E0.10 +*Want "MADBR NF +2.0/-QNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 86F0.10 +*Want "MADB NF +2.0/-QNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8700.10 +*Want "MADBR NF +2.0/+SNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 8710.10 +*Want "MADB NF +2.0/+SNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 8720.10 +*Want "MADBR NF +2.0/+SNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 8730.10 +*Want "MADB NF +2.0/+SNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 8740.10 +*Want "MADBR NF +2.0/+SNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 8750.10 +*Want "MADB NF +2.0/+SNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 8760.10 +*Want "MADBR NF +2.0/+SNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 8770.10 +*Want "MADB NF +2.0/+SNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 8780.10 +*Want "MADBR NF +2.0/+SNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 8790.10 +*Want "MADB NF +2.0/+SNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 87A0.10 +*Want "MADBR NF +2.0/+SNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 87B0.10 +*Want "MADB NF +2.0/+SNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 87C0.10 +*Want "MADBR NF +2.0/+SNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 87D0.10 +*Want "MADB NF +2.0/+SNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 87E0.10 +*Want "MADBR NF +2.0/+SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 87F0.10 +*Want "MADB NF +2.0/+SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8800.10 +*Want "MADBR NF +inf/-inf/-inf" FFF00000 00000000 FFF00000 00000000 +r 8810.10 +*Want "MADB NF +inf/-inf/-inf" FFF00000 00000000 FFF00000 00000000 +r 8820.10 +*Want "MADBR NF +inf/-inf/-2.0" FFF00000 00000000 FFF00000 00000000 +r 8830.10 +*Want "MADB NF +inf/-inf/-2.0" FFF00000 00000000 FFF00000 00000000 +r 8840.10 +*Want "MADBR NF +inf/-inf/-0" FFF00000 00000000 FFF00000 00000000 +r 8850.10 +*Want "MADB NF +inf/-inf/-0" FFF00000 00000000 FFF00000 00000000 +r 8860.10 +*Want "MADBR NF +inf/-inf/+0" FFF00000 00000000 FFF00000 00000000 +r 8870.10 +*Want "MADB NF +inf/-inf/+0" FFF00000 00000000 FFF00000 00000000 +r 8880.10 +*Want "MADBR NF +inf/-inf/+2.0" FFF00000 00000000 FFF00000 00000000 +r 8890.10 +*Want "MADB NF +inf/-inf/+2.0" FFF00000 00000000 FFF00000 00000000 +r 88A0.10 +*Want "MADBR NF +inf/-inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 88B0.10 +*Want "MADB NF +inf/-inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 88C0.10 +*Want "MADBR NF +inf/-inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 88D0.10 +*Want "MADB NF +inf/-inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 88E0.10 +*Want "MADBR NF +inf/-inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 88F0.10 +*Want "MADB NF +inf/-inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8900.10 +*Want "MADBR NF +inf/-2.0/-inf" FFF00000 00000000 FFF00000 00000000 +r 8910.10 +*Want "MADB NF +inf/-2.0/-inf" FFF00000 00000000 FFF00000 00000000 +r 8920.10 +*Want "MADBR NF +inf/-2.0/-2.0" FFF00000 00000000 FFF00000 00000000 +r 8930.10 +*Want "MADB NF +inf/-2.0/-2.0" FFF00000 00000000 FFF00000 00000000 +r 8940.10 +*Want "MADBR NF +inf/-2.0/-0" FFF00000 00000000 FFF00000 00000000 +r 8950.10 +*Want "MADB NF +inf/-2.0/-0" FFF00000 00000000 FFF00000 00000000 +r 8960.10 +*Want "MADBR NF +inf/-2.0/+0" FFF00000 00000000 FFF00000 00000000 +r 8970.10 +*Want "MADB NF +inf/-2.0/+0" FFF00000 00000000 FFF00000 00000000 +r 8980.10 +*Want "MADBR NF +inf/-2.0/+2.0" FFF00000 00000000 FFF00000 00000000 +r 8990.10 +*Want "MADB NF +inf/-2.0/+2.0" FFF00000 00000000 FFF00000 00000000 +r 89A0.10 +*Want "MADBR NF +inf/-2.0/+inf" 7FF80000 00000000 7FF00000 00000000 +r 89B0.10 +*Want "MADB NF +inf/-2.0/+inf" 7FF80000 00000000 7FF00000 00000000 +r 89C0.10 +*Want "MADBR NF +inf/-2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 89D0.10 +*Want "MADB NF +inf/-2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 89E0.10 +*Want "MADBR NF +inf/-2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 89F0.10 +*Want "MADB NF +inf/-2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8A00.10 +*Want "MADBR NF +inf/-0/-inf" 7FF80000 00000000 FFF00000 00000000 +r 8A10.10 +*Want "MADB NF +inf/-0/-inf" 7FF80000 00000000 FFF00000 00000000 +r 8A20.10 +*Want "MADBR NF +inf/-0/-2.0" 7FF80000 00000000 C0000000 00000000 +r 8A30.10 +*Want "MADB NF +inf/-0/-2.0" 7FF80000 00000000 C0000000 00000000 +r 8A40.10 +*Want "MADBR NF +inf/-0/-0" 7FF80000 00000000 80000000 00000000 +r 8A50.10 +*Want "MADB NF +inf/-0/-0" 7FF80000 00000000 80000000 00000000 +r 8A60.10 +*Want "MADBR NF +inf/-0/+0" 7FF80000 00000000 00000000 00000000 +r 8A70.10 +*Want "MADB NF +inf/-0/+0" 7FF80000 00000000 00000000 00000000 +r 8A80.10 +*Want "MADBR NF +inf/-0/+2.0" 7FF80000 00000000 40000000 00000000 +r 8A90.10 +*Want "MADB NF +inf/-0/+2.0" 7FF80000 00000000 40000000 00000000 +r 8AA0.10 +*Want "MADBR NF +inf/-0/+inf" 7FF80000 00000000 7FF00000 00000000 +r 8AB0.10 +*Want "MADB NF +inf/-0/+inf" 7FF80000 00000000 7FF00000 00000000 +r 8AC0.10 +*Want "MADBR NF +inf/-0/-QNaN" 7FF80000 00000000 FFF8B000 00000000 +r 8AD0.10 +*Want "MADB NF +inf/-0/-QNaN" 7FF80000 00000000 FFF8B000 00000000 +r 8AE0.10 +*Want "MADBR NF +inf/-0/+SNaN" 7FF80000 00000000 7FF0A000 00000000 +r 8AF0.10 +*Want "MADB NF +inf/-0/+SNaN" 7FF80000 00000000 7FF0A000 00000000 +r 8B00.10 +*Want "MADBR NF +inf/+0/-inf" 7FF80000 00000000 FFF00000 00000000 +r 8B10.10 +*Want "MADB NF +inf/+0/-inf" 7FF80000 00000000 FFF00000 00000000 +r 8B20.10 +*Want "MADBR NF +inf/+0/-2.0" 7FF80000 00000000 C0000000 00000000 +r 8B30.10 +*Want "MADB NF +inf/+0/-2.0" 7FF80000 00000000 C0000000 00000000 +r 8B40.10 +*Want "MADBR NF +inf/+0/-0" 7FF80000 00000000 80000000 00000000 +r 8B50.10 +*Want "MADB NF +inf/+0/-0" 7FF80000 00000000 80000000 00000000 +r 8B60.10 +*Want "MADBR NF +inf/+0/+0" 7FF80000 00000000 00000000 00000000 +r 8B70.10 +*Want "MADB NF +inf/+0/+0" 7FF80000 00000000 00000000 00000000 +r 8B80.10 +*Want "MADBR NF +inf/+0/+2.0" 7FF80000 00000000 40000000 00000000 +r 8B90.10 +*Want "MADB NF +inf/+0/+2.0" 7FF80000 00000000 40000000 00000000 +r 8BA0.10 +*Want "MADBR NF +inf/+0/+inf" 7FF80000 00000000 7FF00000 00000000 +r 8BB0.10 +*Want "MADB NF +inf/+0/+inf" 7FF80000 00000000 7FF00000 00000000 +r 8BC0.10 +*Want "MADBR NF +inf/+0/-QNaN" 7FF80000 00000000 FFF8B000 00000000 +r 8BD0.10 +*Want "MADB NF +inf/+0/-QNaN" 7FF80000 00000000 FFF8B000 00000000 +r 8BE0.10 +*Want "MADBR NF +inf/+0/+SNaN" 7FF80000 00000000 7FF0A000 00000000 +r 8BF0.10 +*Want "MADB NF +inf/+0/+SNaN" 7FF80000 00000000 7FF0A000 00000000 +r 8C00.10 +*Want "MADBR NF +inf/+2.0/-inf" 7FF80000 00000000 FFF00000 00000000 +r 8C10.10 +*Want "MADB NF +inf/+2.0/-inf" 7FF80000 00000000 FFF00000 00000000 +r 8C20.10 +*Want "MADBR NF +inf/+2.0/-2.0" 7FF00000 00000000 7FF00000 00000000 +r 8C30.10 +*Want "MADB NF +inf/+2.0/-2.0" 7FF00000 00000000 7FF00000 00000000 +r 8C40.10 +*Want "MADBR NF +inf/+2.0/-0" 7FF00000 00000000 7FF00000 00000000 +r 8C50.10 +*Want "MADB NF +inf/+2.0/-0" 7FF00000 00000000 7FF00000 00000000 +r 8C60.10 +*Want "MADBR NF +inf/+2.0/+0" 7FF00000 00000000 7FF00000 00000000 +r 8C70.10 +*Want "MADB NF +inf/+2.0/+0" 7FF00000 00000000 7FF00000 00000000 +r 8C80.10 +*Want "MADBR NF +inf/+2.0/+2.0" 7FF00000 00000000 7FF00000 00000000 +r 8C90.10 +*Want "MADB NF +inf/+2.0/+2.0" 7FF00000 00000000 7FF00000 00000000 +r 8CA0.10 +*Want "MADBR NF +inf/+2.0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 8CB0.10 +*Want "MADB NF +inf/+2.0/+inf" 7FF00000 00000000 7FF00000 00000000 +r 8CC0.10 +*Want "MADBR NF +inf/+2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 8CD0.10 +*Want "MADB NF +inf/+2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 8CE0.10 +*Want "MADBR NF +inf/+2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8CF0.10 +*Want "MADB NF +inf/+2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8D00.10 +*Want "MADBR NF +inf/+inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 8D10.10 +*Want "MADB NF +inf/+inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 8D20.10 +*Want "MADBR NF +inf/+inf/-2.0" 7FF00000 00000000 7FF00000 00000000 +r 8D30.10 +*Want "MADB NF +inf/+inf/-2.0" 7FF00000 00000000 7FF00000 00000000 +r 8D40.10 +*Want "MADBR NF +inf/+inf/-0" 7FF00000 00000000 7FF00000 00000000 +r 8D50.10 +*Want "MADB NF +inf/+inf/-0" 7FF00000 00000000 7FF00000 00000000 +r 8D60.10 +*Want "MADBR NF +inf/+inf/+0" 7FF00000 00000000 7FF00000 00000000 +r 8D70.10 +*Want "MADB NF +inf/+inf/+0" 7FF00000 00000000 7FF00000 00000000 +r 8D80.10 +*Want "MADBR NF +inf/+inf/+2.0" 7FF00000 00000000 7FF00000 00000000 +r 8D90.10 +*Want "MADB NF +inf/+inf/+2.0" 7FF00000 00000000 7FF00000 00000000 +r 8DA0.10 +*Want "MADBR NF +inf/+inf/+inf" 7FF00000 00000000 7FF00000 00000000 +r 8DB0.10 +*Want "MADB NF +inf/+inf/+inf" 7FF00000 00000000 7FF00000 00000000 +r 8DC0.10 +*Want "MADBR NF +inf/+inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 8DD0.10 +*Want "MADB NF +inf/+inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 8DE0.10 +*Want "MADBR NF +inf/+inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8DF0.10 +*Want "MADB NF +inf/+inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8E00.10 +*Want "MADBR NF +inf/-QNaN/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 8E10.10 +*Want "MADB NF +inf/-QNaN/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 8E20.10 +*Want "MADBR NF +inf/-QNaN/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 8E30.10 +*Want "MADB NF +inf/-QNaN/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 8E40.10 +*Want "MADBR NF +inf/-QNaN/-0" FFF8B000 00000000 FFF8B000 00000000 +r 8E50.10 +*Want "MADB NF +inf/-QNaN/-0" FFF8B000 00000000 FFF8B000 00000000 +r 8E60.10 +*Want "MADBR NF +inf/-QNaN/+0" FFF8B000 00000000 FFF8B000 00000000 +r 8E70.10 +*Want "MADB NF +inf/-QNaN/+0" FFF8B000 00000000 FFF8B000 00000000 +r 8E80.10 +*Want "MADBR NF +inf/-QNaN/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 8E90.10 +*Want "MADB NF +inf/-QNaN/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 8EA0.10 +*Want "MADBR NF +inf/-QNaN/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 8EB0.10 +*Want "MADB NF +inf/-QNaN/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 8EC0.10 +*Want "MADBR NF +inf/-QNaN/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 8ED0.10 +*Want "MADB NF +inf/-QNaN/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 8EE0.10 +*Want "MADBR NF +inf/-QNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8EF0.10 +*Want "MADB NF +inf/-QNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8F00.10 +*Want "MADBR NF +inf/+SNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 8F10.10 +*Want "MADB NF +inf/+SNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 8F20.10 +*Want "MADBR NF +inf/+SNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 8F30.10 +*Want "MADB NF +inf/+SNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 8F40.10 +*Want "MADBR NF +inf/+SNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 8F50.10 +*Want "MADB NF +inf/+SNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 8F60.10 +*Want "MADBR NF +inf/+SNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 8F70.10 +*Want "MADB NF +inf/+SNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 8F80.10 +*Want "MADBR NF +inf/+SNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 8F90.10 +*Want "MADB NF +inf/+SNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 8FA0.10 +*Want "MADBR NF +inf/+SNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 8FB0.10 +*Want "MADB NF +inf/+SNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 8FC0.10 +*Want "MADBR NF +inf/+SNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 8FD0.10 +*Want "MADB NF +inf/+SNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 8FE0.10 +*Want "MADBR NF +inf/+SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8FF0.10 +*Want "MADB NF +inf/+SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9000.10 +*Want "MADBR NF -QNaN/-inf/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 9010.10 +*Want "MADB NF -QNaN/-inf/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 9020.10 +*Want "MADBR NF -QNaN/-inf/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9030.10 +*Want "MADB NF -QNaN/-inf/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9040.10 +*Want "MADBR NF -QNaN/-inf/-0" FFF8B000 00000000 FFF8B000 00000000 +r 9050.10 +*Want "MADB NF -QNaN/-inf/-0" FFF8B000 00000000 FFF8B000 00000000 +r 9060.10 +*Want "MADBR NF -QNaN/-inf/+0" FFF8B000 00000000 FFF8B000 00000000 +r 9070.10 +*Want "MADB NF -QNaN/-inf/+0" FFF8B000 00000000 FFF8B000 00000000 +r 9080.10 +*Want "MADBR NF -QNaN/-inf/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9090.10 +*Want "MADB NF -QNaN/-inf/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 90A0.10 +*Want "MADBR NF -QNaN/-inf/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 90B0.10 +*Want "MADB NF -QNaN/-inf/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 90C0.10 +*Want "MADBR NF -QNaN/-inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 90D0.10 +*Want "MADB NF -QNaN/-inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 90E0.10 +*Want "MADBR NF -QNaN/-inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 90F0.10 +*Want "MADB NF -QNaN/-inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9100.10 +*Want "MADBR NF -QNaN/-2.0/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 9110.10 +*Want "MADB NF -QNaN/-2.0/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 9120.10 +*Want "MADBR NF -QNaN/-2.0/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9130.10 +*Want "MADB NF -QNaN/-2.0/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9140.10 +*Want "MADBR NF -QNaN/-2.0/-0" FFF8B000 00000000 FFF8B000 00000000 +r 9150.10 +*Want "MADB NF -QNaN/-2.0/-0" FFF8B000 00000000 FFF8B000 00000000 +r 9160.10 +*Want "MADBR NF -QNaN/-2.0/+0" FFF8B000 00000000 FFF8B000 00000000 +r 9170.10 +*Want "MADB NF -QNaN/-2.0/+0" FFF8B000 00000000 FFF8B000 00000000 +r 9180.10 +*Want "MADBR NF -QNaN/-2.0/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9190.10 +*Want "MADB NF -QNaN/-2.0/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 91A0.10 +*Want "MADBR NF -QNaN/-2.0/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 91B0.10 +*Want "MADB NF -QNaN/-2.0/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 91C0.10 +*Want "MADBR NF -QNaN/-2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 91D0.10 +*Want "MADB NF -QNaN/-2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 91E0.10 +*Want "MADBR NF -QNaN/-2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 91F0.10 +*Want "MADB NF -QNaN/-2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9200.10 +*Want "MADBR NF -QNaN/-0/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 9210.10 +*Want "MADB NF -QNaN/-0/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 9220.10 +*Want "MADBR NF -QNaN/-0/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9230.10 +*Want "MADB NF -QNaN/-0/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9240.10 +*Want "MADBR NF -QNaN/-0/-0" FFF8B000 00000000 FFF8B000 00000000 +r 9250.10 +*Want "MADB NF -QNaN/-0/-0" FFF8B000 00000000 FFF8B000 00000000 +r 9260.10 +*Want "MADBR NF -QNaN/-0/+0" FFF8B000 00000000 FFF8B000 00000000 +r 9270.10 +*Want "MADB NF -QNaN/-0/+0" FFF8B000 00000000 FFF8B000 00000000 +r 9280.10 +*Want "MADBR NF -QNaN/-0/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9290.10 +*Want "MADB NF -QNaN/-0/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 92A0.10 +*Want "MADBR NF -QNaN/-0/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 92B0.10 +*Want "MADB NF -QNaN/-0/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 92C0.10 +*Want "MADBR NF -QNaN/-0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 92D0.10 +*Want "MADB NF -QNaN/-0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 92E0.10 +*Want "MADBR NF -QNaN/-0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 92F0.10 +*Want "MADB NF -QNaN/-0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9300.10 +*Want "MADBR NF -QNaN/+0/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 9310.10 +*Want "MADB NF -QNaN/+0/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 9320.10 +*Want "MADBR NF -QNaN/+0/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9330.10 +*Want "MADB NF -QNaN/+0/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9340.10 +*Want "MADBR NF -QNaN/+0/-0" FFF8B000 00000000 FFF8B000 00000000 +r 9350.10 +*Want "MADB NF -QNaN/+0/-0" FFF8B000 00000000 FFF8B000 00000000 +r 9360.10 +*Want "MADBR NF -QNaN/+0/+0" FFF8B000 00000000 FFF8B000 00000000 +r 9370.10 +*Want "MADB NF -QNaN/+0/+0" FFF8B000 00000000 FFF8B000 00000000 +r 9380.10 +*Want "MADBR NF -QNaN/+0/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9390.10 +*Want "MADB NF -QNaN/+0/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 93A0.10 +*Want "MADBR NF -QNaN/+0/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 93B0.10 +*Want "MADB NF -QNaN/+0/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 93C0.10 +*Want "MADBR NF -QNaN/+0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 93D0.10 +*Want "MADB NF -QNaN/+0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 93E0.10 +*Want "MADBR NF -QNaN/+0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 93F0.10 +*Want "MADB NF -QNaN/+0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9400.10 +*Want "MADBR NF -QNaN/+2.0/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 9410.10 +*Want "MADB NF -QNaN/+2.0/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 9420.10 +*Want "MADBR NF -QNaN/+2.0/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9430.10 +*Want "MADB NF -QNaN/+2.0/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9440.10 +*Want "MADBR NF -QNaN/+2.0/-0" FFF8B000 00000000 FFF8B000 00000000 +r 9450.10 +*Want "MADB NF -QNaN/+2.0/-0" FFF8B000 00000000 FFF8B000 00000000 +r 9460.10 +*Want "MADBR NF -QNaN/+2.0/+0" FFF8B000 00000000 FFF8B000 00000000 +r 9470.10 +*Want "MADB NF -QNaN/+2.0/+0" FFF8B000 00000000 FFF8B000 00000000 +r 9480.10 +*Want "MADBR NF -QNaN/+2.0/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9490.10 +*Want "MADB NF -QNaN/+2.0/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 94A0.10 +*Want "MADBR NF -QNaN/+2.0/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 94B0.10 +*Want "MADB NF -QNaN/+2.0/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 94C0.10 +*Want "MADBR NF -QNaN/+2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 94D0.10 +*Want "MADB NF -QNaN/+2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 94E0.10 +*Want "MADBR NF -QNaN/+2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 94F0.10 +*Want "MADB NF -QNaN/+2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9500.10 +*Want "MADBR NF -QNaN/+inf/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 9510.10 +*Want "MADB NF -QNaN/+inf/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 9520.10 +*Want "MADBR NF -QNaN/+inf/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9530.10 +*Want "MADB NF -QNaN/+inf/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9540.10 +*Want "MADBR NF -QNaN/+inf/-0" FFF8B000 00000000 FFF8B000 00000000 +r 9550.10 +*Want "MADB NF -QNaN/+inf/-0" FFF8B000 00000000 FFF8B000 00000000 +r 9560.10 +*Want "MADBR NF -QNaN/+inf/+0" FFF8B000 00000000 FFF8B000 00000000 +r 9570.10 +*Want "MADB NF -QNaN/+inf/+0" FFF8B000 00000000 FFF8B000 00000000 +r 9580.10 +*Want "MADBR NF -QNaN/+inf/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9590.10 +*Want "MADB NF -QNaN/+inf/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 95A0.10 +*Want "MADBR NF -QNaN/+inf/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 95B0.10 +*Want "MADB NF -QNaN/+inf/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 95C0.10 +*Want "MADBR NF -QNaN/+inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 95D0.10 +*Want "MADB NF -QNaN/+inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 95E0.10 +*Want "MADBR NF -QNaN/+inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 95F0.10 +*Want "MADB NF -QNaN/+inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9600.10 +*Want "MADBR NF -QNaN/-QNaN/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 9610.10 +*Want "MADB NF -QNaN/-QNaN/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 9620.10 +*Want "MADBR NF -QNaN/-QNaN/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9630.10 +*Want "MADB NF -QNaN/-QNaN/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9640.10 +*Want "MADBR NF -QNaN/-QNaN/-0" FFF8B000 00000000 FFF8B000 00000000 +r 9650.10 +*Want "MADB NF -QNaN/-QNaN/-0" FFF8B000 00000000 FFF8B000 00000000 +r 9660.10 +*Want "MADBR NF -QNaN/-QNaN/+0" FFF8B000 00000000 FFF8B000 00000000 +r 9670.10 +*Want "MADB NF -QNaN/-QNaN/+0" FFF8B000 00000000 FFF8B000 00000000 +r 9680.10 +*Want "MADBR NF -QNaN/-QNaN/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9690.10 +*Want "MADB NF -QNaN/-QNaN/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 96A0.10 +*Want "MADBR NF -QNaN/-QNaN/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 96B0.10 +*Want "MADB NF -QNaN/-QNaN/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 96C0.10 +*Want "MADBR NF -QNaN/-QNaN/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 96D0.10 +*Want "MADB NF -QNaN/-QNaN/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 96E0.10 +*Want "MADBR NF -QNaN/-QNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 96F0.10 +*Want "MADB NF -QNaN/-QNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9700.10 +*Want "MADBR NF -QNaN/+SNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9710.10 +*Want "MADB NF -QNaN/+SNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9720.10 +*Want "MADBR NF -QNaN/+SNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9730.10 +*Want "MADB NF -QNaN/+SNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9740.10 +*Want "MADBR NF -QNaN/+SNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 9750.10 +*Want "MADB NF -QNaN/+SNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 9760.10 +*Want "MADBR NF -QNaN/+SNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 9770.10 +*Want "MADB NF -QNaN/+SNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 9780.10 +*Want "MADBR NF -QNaN/+SNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 9790.10 +*Want "MADB NF -QNaN/+SNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 97A0.10 +*Want "MADBR NF -QNaN/+SNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 97B0.10 +*Want "MADB NF -QNaN/+SNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 97C0.10 +*Want "MADBR NF -QNaN/+SNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 97D0.10 +*Want "MADB NF -QNaN/+SNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 97E0.10 +*Want "MADBR NF -QNaN/+SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 97F0.10 +*Want "MADB NF -QNaN/+SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9800.10 +*Want "MADBR NF +SNaN/-inf/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9810.10 +*Want "MADB NF +SNaN/-inf/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9820.10 +*Want "MADBR NF +SNaN/-inf/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9830.10 +*Want "MADB NF +SNaN/-inf/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9840.10 +*Want "MADBR NF +SNaN/-inf/-0" 7FF8A000 00000000 80000000 00000000 +r 9850.10 +*Want "MADB NF +SNaN/-inf/-0" 7FF8A000 00000000 80000000 00000000 +r 9860.10 +*Want "MADBR NF +SNaN/-inf/+0" 7FF8A000 00000000 00000000 00000000 +r 9870.10 +*Want "MADB NF +SNaN/-inf/+0" 7FF8A000 00000000 00000000 00000000 +r 9880.10 +*Want "MADBR NF +SNaN/-inf/+2.0" 7FF8A000 00000000 40000000 00000000 +r 9890.10 +*Want "MADB NF +SNaN/-inf/+2.0" 7FF8A000 00000000 40000000 00000000 +r 98A0.10 +*Want "MADBR NF +SNaN/-inf/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 98B0.10 +*Want "MADB NF +SNaN/-inf/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 98C0.10 +*Want "MADBR NF +SNaN/-inf/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 98D0.10 +*Want "MADB NF +SNaN/-inf/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 98E0.10 +*Want "MADBR NF +SNaN/-inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 98F0.10 +*Want "MADB NF +SNaN/-inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9900.10 +*Want "MADBR NF +SNaN/-2.0/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9910.10 +*Want "MADB NF +SNaN/-2.0/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9920.10 +*Want "MADBR NF +SNaN/-2.0/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9930.10 +*Want "MADB NF +SNaN/-2.0/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9940.10 +*Want "MADBR NF +SNaN/-2.0/-0" 7FF8A000 00000000 80000000 00000000 +r 9950.10 +*Want "MADB NF +SNaN/-2.0/-0" 7FF8A000 00000000 80000000 00000000 +r 9960.10 +*Want "MADBR NF +SNaN/-2.0/+0" 7FF8A000 00000000 00000000 00000000 +r 9970.10 +*Want "MADB NF +SNaN/-2.0/+0" 7FF8A000 00000000 00000000 00000000 +r 9980.10 +*Want "MADBR NF +SNaN/-2.0/+2.0" 7FF8A000 00000000 40000000 00000000 +r 9990.10 +*Want "MADB NF +SNaN/-2.0/+2.0" 7FF8A000 00000000 40000000 00000000 +r 99A0.10 +*Want "MADBR NF +SNaN/-2.0/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 99B0.10 +*Want "MADB NF +SNaN/-2.0/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 99C0.10 +*Want "MADBR NF +SNaN/-2.0/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 99D0.10 +*Want "MADB NF +SNaN/-2.0/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 99E0.10 +*Want "MADBR NF +SNaN/-2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 99F0.10 +*Want "MADB NF +SNaN/-2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9A00.10 +*Want "MADBR NF +SNaN/-0/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9A10.10 +*Want "MADB NF +SNaN/-0/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9A20.10 +*Want "MADBR NF +SNaN/-0/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9A30.10 +*Want "MADB NF +SNaN/-0/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9A40.10 +*Want "MADBR NF +SNaN/-0/-0" 7FF8A000 00000000 80000000 00000000 +r 9A50.10 +*Want "MADB NF +SNaN/-0/-0" 7FF8A000 00000000 80000000 00000000 +r 9A60.10 +*Want "MADBR NF +SNaN/-0/+0" 7FF8A000 00000000 00000000 00000000 +r 9A70.10 +*Want "MADB NF +SNaN/-0/+0" 7FF8A000 00000000 00000000 00000000 +r 9A80.10 +*Want "MADBR NF +SNaN/-0/+2.0" 7FF8A000 00000000 40000000 00000000 +r 9A90.10 +*Want "MADB NF +SNaN/-0/+2.0" 7FF8A000 00000000 40000000 00000000 +r 9AA0.10 +*Want "MADBR NF +SNaN/-0/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 9AB0.10 +*Want "MADB NF +SNaN/-0/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 9AC0.10 +*Want "MADBR NF +SNaN/-0/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 9AD0.10 +*Want "MADB NF +SNaN/-0/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 9AE0.10 +*Want "MADBR NF +SNaN/-0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9AF0.10 +*Want "MADB NF +SNaN/-0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9B00.10 +*Want "MADBR NF +SNaN/+0/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9B10.10 +*Want "MADB NF +SNaN/+0/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9B20.10 +*Want "MADBR NF +SNaN/+0/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9B30.10 +*Want "MADB NF +SNaN/+0/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9B40.10 +*Want "MADBR NF +SNaN/+0/-0" 7FF8A000 00000000 80000000 00000000 +r 9B50.10 +*Want "MADB NF +SNaN/+0/-0" 7FF8A000 00000000 80000000 00000000 +r 9B60.10 +*Want "MADBR NF +SNaN/+0/+0" 7FF8A000 00000000 00000000 00000000 +r 9B70.10 +*Want "MADB NF +SNaN/+0/+0" 7FF8A000 00000000 00000000 00000000 +r 9B80.10 +*Want "MADBR NF +SNaN/+0/+2.0" 7FF8A000 00000000 40000000 00000000 +r 9B90.10 +*Want "MADB NF +SNaN/+0/+2.0" 7FF8A000 00000000 40000000 00000000 +r 9BA0.10 +*Want "MADBR NF +SNaN/+0/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 9BB0.10 +*Want "MADB NF +SNaN/+0/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 9BC0.10 +*Want "MADBR NF +SNaN/+0/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 9BD0.10 +*Want "MADB NF +SNaN/+0/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 9BE0.10 +*Want "MADBR NF +SNaN/+0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9BF0.10 +*Want "MADB NF +SNaN/+0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9C00.10 +*Want "MADBR NF +SNaN/+2.0/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9C10.10 +*Want "MADB NF +SNaN/+2.0/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9C20.10 +*Want "MADBR NF +SNaN/+2.0/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9C30.10 +*Want "MADB NF +SNaN/+2.0/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9C40.10 +*Want "MADBR NF +SNaN/+2.0/-0" 7FF8A000 00000000 80000000 00000000 +r 9C50.10 +*Want "MADB NF +SNaN/+2.0/-0" 7FF8A000 00000000 80000000 00000000 +r 9C60.10 +*Want "MADBR NF +SNaN/+2.0/+0" 7FF8A000 00000000 00000000 00000000 +r 9C70.10 +*Want "MADB NF +SNaN/+2.0/+0" 7FF8A000 00000000 00000000 00000000 +r 9C80.10 +*Want "MADBR NF +SNaN/+2.0/+2.0" 7FF8A000 00000000 40000000 00000000 +r 9C90.10 +*Want "MADB NF +SNaN/+2.0/+2.0" 7FF8A000 00000000 40000000 00000000 +r 9CA0.10 +*Want "MADBR NF +SNaN/+2.0/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 9CB0.10 +*Want "MADB NF +SNaN/+2.0/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 9CC0.10 +*Want "MADBR NF +SNaN/+2.0/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 9CD0.10 +*Want "MADB NF +SNaN/+2.0/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 9CE0.10 +*Want "MADBR NF +SNaN/+2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9CF0.10 +*Want "MADB NF +SNaN/+2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9D00.10 +*Want "MADBR NF +SNaN/+inf/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9D10.10 +*Want "MADB NF +SNaN/+inf/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9D20.10 +*Want "MADBR NF +SNaN/+inf/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9D30.10 +*Want "MADB NF +SNaN/+inf/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9D40.10 +*Want "MADBR NF +SNaN/+inf/-0" 7FF8A000 00000000 80000000 00000000 +r 9D50.10 +*Want "MADB NF +SNaN/+inf/-0" 7FF8A000 00000000 80000000 00000000 +r 9D60.10 +*Want "MADBR NF +SNaN/+inf/+0" 7FF8A000 00000000 00000000 00000000 +r 9D70.10 +*Want "MADB NF +SNaN/+inf/+0" 7FF8A000 00000000 00000000 00000000 +r 9D80.10 +*Want "MADBR NF +SNaN/+inf/+2.0" 7FF8A000 00000000 40000000 00000000 +r 9D90.10 +*Want "MADB NF +SNaN/+inf/+2.0" 7FF8A000 00000000 40000000 00000000 +r 9DA0.10 +*Want "MADBR NF +SNaN/+inf/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 9DB0.10 +*Want "MADB NF +SNaN/+inf/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 9DC0.10 +*Want "MADBR NF +SNaN/+inf/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 9DD0.10 +*Want "MADB NF +SNaN/+inf/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 9DE0.10 +*Want "MADBR NF +SNaN/+inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9DF0.10 +*Want "MADB NF +SNaN/+inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9E00.10 +*Want "MADBR NF +SNaN/-QNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9E10.10 +*Want "MADB NF +SNaN/-QNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9E20.10 +*Want "MADBR NF +SNaN/-QNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9E30.10 +*Want "MADB NF +SNaN/-QNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9E40.10 +*Want "MADBR NF +SNaN/-QNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 9E50.10 +*Want "MADB NF +SNaN/-QNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 9E60.10 +*Want "MADBR NF +SNaN/-QNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 9E70.10 +*Want "MADB NF +SNaN/-QNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 9E80.10 +*Want "MADBR NF +SNaN/-QNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 9E90.10 +*Want "MADB NF +SNaN/-QNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 9EA0.10 +*Want "MADBR NF +SNaN/-QNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 9EB0.10 +*Want "MADB NF +SNaN/-QNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 9EC0.10 +*Want "MADBR NF +SNaN/-QNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 9ED0.10 +*Want "MADB NF +SNaN/-QNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 9EE0.10 +*Want "MADBR NF +SNaN/-QNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9EF0.10 +*Want "MADB NF +SNaN/-QNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9F00.10 +*Want "MADBR NF +SNaN/+SNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9F10.10 +*Want "MADB NF +SNaN/+SNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9F20.10 +*Want "MADBR NF +SNaN/+SNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9F30.10 +*Want "MADB NF +SNaN/+SNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9F40.10 +*Want "MADBR NF +SNaN/+SNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 9F50.10 +*Want "MADB NF +SNaN/+SNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 9F60.10 +*Want "MADBR NF +SNaN/+SNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 9F70.10 +*Want "MADB NF +SNaN/+SNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 9F80.10 +*Want "MADBR NF +SNaN/+SNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 9F90.10 +*Want "MADB NF +SNaN/+SNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 9FA0.10 +*Want "MADBR NF +SNaN/+SNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 9FB0.10 +*Want "MADB NF +SNaN/+SNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 9FC0.10 +*Want "MADBR NF +SNaN/+SNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 9FD0.10 +*Want "MADB NF +SNaN/+SNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 9FE0.10 +*Want "MADBR NF +SNaN/+SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9FF0.10 +*Want "MADB NF +SNaN/+SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 + + +# Long BFP Multiply And Add non-finite results - FPCR Contents +*Compare +r A000.10 +*Want "MADBR/MADB NF -inf/-inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r A010.10 +*Want "MADBR/MADB NF -inf/-inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A020.10 +*Want "MADBR/MADB NF -inf/-inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r A030.10 +*Want "MADBR/MADB NF -inf/-inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r A040.10 +*Want "MADBR/MADB NF -inf/-inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A050.10 +*Want "MADBR/MADB NF -inf/-inf/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r A060.10 +*Want "MADBR/MADB NF -inf/-inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r A070.10 +*Want "MADBR/MADB NF -inf/-inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A080.10 +*Want "MADBR/MADB NF -inf/-2.0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r A090.10 +*Want "MADBR/MADB NF -inf/-2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A0A0.10 +*Want "MADBR/MADB NF -inf/-2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r A0B0.10 +*Want "MADBR/MADB NF -inf/-2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r A0C0.10 +*Want "MADBR/MADB NF -inf/-2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A0D0.10 +*Want "MADBR/MADB NF -inf/-2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r A0E0.10 +*Want "MADBR/MADB NF -inf/-2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r A0F0.10 +*Want "MADBR/MADB NF -inf/-2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A100.10 +*Want "MADBR/MADB NF -inf/-0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r A110.10 +*Want "MADBR/MADB NF -inf/-0/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r A120.10 +*Want "MADBR/MADB NF -inf/-0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r A130.10 +*Want "MADBR/MADB NF -inf/-0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r A140.10 +*Want "MADBR/MADB NF -inf/-0/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r A150.10 +*Want "MADBR/MADB NF -inf/-0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r A160.10 +*Want "MADBR/MADB NF -inf/-0/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A170.10 +*Want "MADBR/MADB NF -inf/-0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A180.10 +*Want "MADBR/MADB NF -inf/+0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r A190.10 +*Want "MADBR/MADB NF -inf/+0/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r A1A0.10 +*Want "MADBR/MADB NF -inf/+0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r A1B0.10 +*Want "MADBR/MADB NF -inf/+0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r A1C0.10 +*Want "MADBR/MADB NF -inf/+0/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r A1D0.10 +*Want "MADBR/MADB NF -inf/+0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r A1E0.10 +*Want "MADBR/MADB NF -inf/+0/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A1F0.10 +*Want "MADBR/MADB NF -inf/+0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A200.10 +*Want "MADBR/MADB NF -inf/+2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r A210.10 +*Want "MADBR/MADB NF -inf/+2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A220.10 +*Want "MADBR/MADB NF -inf/+2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r A230.10 +*Want "MADBR/MADB NF -inf/+2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r A240.10 +*Want "MADBR/MADB NF -inf/+2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A250.10 +*Want "MADBR/MADB NF -inf/+2.0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r A260.10 +*Want "MADBR/MADB NF -inf/+2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r A270.10 +*Want "MADBR/MADB NF -inf/+2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A280.10 +*Want "MADBR/MADB NF -inf/+inf/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r A290.10 +*Want "MADBR/MADB NF -inf/+inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A2A0.10 +*Want "MADBR/MADB NF -inf/+inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r A2B0.10 +*Want "MADBR/MADB NF -inf/+inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r A2C0.10 +*Want "MADBR/MADB NF -inf/+inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A2D0.10 +*Want "MADBR/MADB NF -inf/+inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r A2E0.10 +*Want "MADBR/MADB NF -inf/+inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r A2F0.10 +*Want "MADBR/MADB NF -inf/+inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A300.10 +*Want "MADBR/MADB NF -inf/-QNaN/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r A310.10 +*Want "MADBR/MADB NF -inf/-QNaN/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A320.10 +*Want "MADBR/MADB NF -inf/-QNaN/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r A330.10 +*Want "MADBR/MADB NF -inf/-QNaN/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r A340.10 +*Want "MADBR/MADB NF -inf/-QNaN/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A350.10 +*Want "MADBR/MADB NF -inf/-QNaN/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r A360.10 +*Want "MADBR/MADB NF -inf/-QNaN/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r A370.10 +*Want "MADBR/MADB NF -inf/-QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A380.10 +*Want "MADBR/MADB NF -inf/+SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r A390.10 +*Want "MADBR/MADB NF -inf/+SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r A3A0.10 +*Want "MADBR/MADB NF -inf/+SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r A3B0.10 +*Want "MADBR/MADB NF -inf/+SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r A3C0.10 +*Want "MADBR/MADB NF -inf/+SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r A3D0.10 +*Want "MADBR/MADB NF -inf/+SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r A3E0.10 +*Want "MADBR/MADB NF -inf/+SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A3F0.10 +*Want "MADBR/MADB NF -inf/+SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A400.10 +*Want "MADBR/MADB NF -2.0/-inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r A410.10 +*Want "MADBR/MADB NF -2.0/-inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A420.10 +*Want "MADBR/MADB NF -2.0/-inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r A430.10 +*Want "MADBR/MADB NF -2.0/-inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r A440.10 +*Want "MADBR/MADB NF -2.0/-inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A450.10 +*Want "MADBR/MADB NF -2.0/-inf/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r A460.10 +*Want "MADBR/MADB NF -2.0/-inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r A470.10 +*Want "MADBR/MADB NF -2.0/-inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A480.10 +*Want "MADBR/MADB NF -2.0/-2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r A490.10 +*Want "MADBR/MADB NF -2.0/-2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A4A0.10 +*Want "MADBR/MADB NF -2.0/-2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r A4B0.10 +*Want "MADBR/MADB NF -2.0/-2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r A4C0.10 +*Want "MADBR/MADB NF -2.0/-2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A4D0.10 +*Want "MADBR/MADB NF -2.0/-2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r A4E0.10 +*Want "MADBR/MADB NF -2.0/-2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r A4F0.10 +*Want "MADBR/MADB NF -2.0/-2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A500.10 +*Want "MADBR/MADB NF -2.0/-0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r A510.10 +*Want "MADBR/MADB NF -2.0/-0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A520.10 +*Want "MADBR/MADB NF -2.0/-0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r A530.10 +*Want "MADBR/MADB NF -2.0/-0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r A540.10 +*Want "MADBR/MADB NF -2.0/-0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A550.10 +*Want "MADBR/MADB NF -2.0/-0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r A560.10 +*Want "MADBR/MADB NF -2.0/-0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r A570.10 +*Want "MADBR/MADB NF -2.0/-0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A580.10 +*Want "MADBR/MADB NF -2.0/+0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r A590.10 +*Want "MADBR/MADB NF -2.0/+0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A5A0.10 +*Want "MADBR/MADB NF -2.0/+0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r A5B0.10 +*Want "MADBR/MADB NF -2.0/+0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r A5C0.10 +*Want "MADBR/MADB NF -2.0/+0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A5D0.10 +*Want "MADBR/MADB NF -2.0/+0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r A5E0.10 +*Want "MADBR/MADB NF -2.0/+0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r A5F0.10 +*Want "MADBR/MADB NF -2.0/+0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A600.10 +*Want "MADBR/MADB NF -2.0/+2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r A610.10 +*Want "MADBR/MADB NF -2.0/+2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A620.10 +*Want "MADBR/MADB NF -2.0/+2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r A630.10 +*Want "MADBR/MADB NF -2.0/+2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r A640.10 +*Want "MADBR/MADB NF -2.0/+2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A650.10 +*Want "MADBR/MADB NF -2.0/+2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r A660.10 +*Want "MADBR/MADB NF -2.0/+2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r A670.10 +*Want "MADBR/MADB NF -2.0/+2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A680.10 +*Want "MADBR/MADB NF -2.0/+inf/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r A690.10 +*Want "MADBR/MADB NF -2.0/+inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A6A0.10 +*Want "MADBR/MADB NF -2.0/+inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r A6B0.10 +*Want "MADBR/MADB NF -2.0/+inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r A6C0.10 +*Want "MADBR/MADB NF -2.0/+inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A6D0.10 +*Want "MADBR/MADB NF -2.0/+inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r A6E0.10 +*Want "MADBR/MADB NF -2.0/+inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r A6F0.10 +*Want "MADBR/MADB NF -2.0/+inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A700.10 +*Want "MADBR/MADB NF -2.0/-QNaN/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r A710.10 +*Want "MADBR/MADB NF -2.0/-QNaN/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A720.10 +*Want "MADBR/MADB NF -2.0/-QNaN/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r A730.10 +*Want "MADBR/MADB NF -2.0/-QNaN/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r A740.10 +*Want "MADBR/MADB NF -2.0/-QNaN/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A750.10 +*Want "MADBR/MADB NF -2.0/-QNaN/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r A760.10 +*Want "MADBR/MADB NF -2.0/-QNaN/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r A770.10 +*Want "MADBR/MADB NF -2.0/-QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A780.10 +*Want "MADBR/MADB NF -2.0/+SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r A790.10 +*Want "MADBR/MADB NF -2.0/+SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r A7A0.10 +*Want "MADBR/MADB NF -2.0/+SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r A7B0.10 +*Want "MADBR/MADB NF -2.0/+SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r A7C0.10 +*Want "MADBR/MADB NF -2.0/+SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r A7D0.10 +*Want "MADBR/MADB NF -2.0/+SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r A7E0.10 +*Want "MADBR/MADB NF -2.0/+SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A7F0.10 +*Want "MADBR/MADB NF -2.0/+SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A800.10 +*Want "MADBR/MADB NF -0/-inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r A810.10 +*Want "MADBR/MADB NF -0/-inf/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r A820.10 +*Want "MADBR/MADB NF -0/-inf/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r A830.10 +*Want "MADBR/MADB NF -0/-inf/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r A840.10 +*Want "MADBR/MADB NF -0/-inf/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r A850.10 +*Want "MADBR/MADB NF -0/-inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r A860.10 +*Want "MADBR/MADB NF -0/-inf/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A870.10 +*Want "MADBR/MADB NF -0/-inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A880.10 +*Want "MADBR/MADB NF -0/-2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r A890.10 +*Want "MADBR/MADB NF -0/-2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A8A0.10 +*Want "MADBR/MADB NF -0/-2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r A8B0.10 +*Want "MADBR/MADB NF -0/-2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r A8C0.10 +*Want "MADBR/MADB NF -0/-2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A8D0.10 +*Want "MADBR/MADB NF -0/-2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r A8E0.10 +*Want "MADBR/MADB NF -0/-2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r A8F0.10 +*Want "MADBR/MADB NF -0/-2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A900.10 +*Want "MADBR/MADB NF -0/-0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r A910.10 +*Want "MADBR/MADB NF -0/-0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A920.10 +*Want "MADBR/MADB NF -0/-0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r A930.10 +*Want "MADBR/MADB NF -0/-0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r A940.10 +*Want "MADBR/MADB NF -0/-0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A950.10 +*Want "MADBR/MADB NF -0/-0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r A960.10 +*Want "MADBR/MADB NF -0/-0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r A970.10 +*Want "MADBR/MADB NF -0/-0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A980.10 +*Want "MADBR/MADB NF -0/+0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r A990.10 +*Want "MADBR/MADB NF -0/+0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A9A0.10 +*Want "MADBR/MADB NF -0/+0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r A9B0.10 +*Want "MADBR/MADB NF -0/+0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r A9C0.10 +*Want "MADBR/MADB NF -0/+0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A9D0.10 +*Want "MADBR/MADB NF -0/+0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r A9E0.10 +*Want "MADBR/MADB NF -0/+0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r A9F0.10 +*Want "MADBR/MADB NF -0/+0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r AA00.10 +*Want "MADBR/MADB NF -0/+2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r AA10.10 +*Want "MADBR/MADB NF -0/+2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r AA20.10 +*Want "MADBR/MADB NF -0/+2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r AA30.10 +*Want "MADBR/MADB NF -0/+2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r AA40.10 +*Want "MADBR/MADB NF -0/+2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r AA50.10 +*Want "MADBR/MADB NF -0/+2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r AA60.10 +*Want "MADBR/MADB NF -0/+2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r AA70.10 +*Want "MADBR/MADB NF -0/+2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r AA80.10 +*Want "MADBR/MADB NF -0/+inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r AA90.10 +*Want "MADBR/MADB NF -0/+inf/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r AAA0.10 +*Want "MADBR/MADB NF -0/+inf/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r AAB0.10 +*Want "MADBR/MADB NF -0/+inf/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r AAC0.10 +*Want "MADBR/MADB NF -0/+inf/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r AAD0.10 +*Want "MADBR/MADB NF -0/+inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r AAE0.10 +*Want "MADBR/MADB NF -0/+inf/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r AAF0.10 +*Want "MADBR/MADB NF -0/+inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r AB00.10 +*Want "MADBR/MADB NF -0/-QNaN/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r AB10.10 +*Want "MADBR/MADB NF -0/-QNaN/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r AB20.10 +*Want "MADBR/MADB NF -0/-QNaN/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r AB30.10 +*Want "MADBR/MADB NF -0/-QNaN/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r AB40.10 +*Want "MADBR/MADB NF -0/-QNaN/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r AB50.10 +*Want "MADBR/MADB NF -0/-QNaN/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r AB60.10 +*Want "MADBR/MADB NF -0/-QNaN/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r AB70.10 +*Want "MADBR/MADB NF -0/-QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r AB80.10 +*Want "MADBR/MADB NF -0/+SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r AB90.10 +*Want "MADBR/MADB NF -0/+SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r ABA0.10 +*Want "MADBR/MADB NF -0/+SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r ABB0.10 +*Want "MADBR/MADB NF -0/+SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r ABC0.10 +*Want "MADBR/MADB NF -0/+SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r ABD0.10 +*Want "MADBR/MADB NF -0/+SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r ABE0.10 +*Want "MADBR/MADB NF -0/+SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r ABF0.10 +*Want "MADBR/MADB NF -0/+SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r AC00.10 +*Want "MADBR/MADB NF +0/-inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r AC10.10 +*Want "MADBR/MADB NF +0/-inf/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r AC20.10 +*Want "MADBR/MADB NF +0/-inf/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r AC30.10 +*Want "MADBR/MADB NF +0/-inf/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r AC40.10 +*Want "MADBR/MADB NF +0/-inf/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r AC50.10 +*Want "MADBR/MADB NF +0/-inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r AC60.10 +*Want "MADBR/MADB NF +0/-inf/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r AC70.10 +*Want "MADBR/MADB NF +0/-inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r AC80.10 +*Want "MADBR/MADB NF +0/-2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r AC90.10 +*Want "MADBR/MADB NF +0/-2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r ACA0.10 +*Want "MADBR/MADB NF +0/-2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r ACB0.10 +*Want "MADBR/MADB NF +0/-2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r ACC0.10 +*Want "MADBR/MADB NF +0/-2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r ACD0.10 +*Want "MADBR/MADB NF +0/-2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r ACE0.10 +*Want "MADBR/MADB NF +0/-2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r ACF0.10 +*Want "MADBR/MADB NF +0/-2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r AD00.10 +*Want "MADBR/MADB NF +0/-0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r AD10.10 +*Want "MADBR/MADB NF +0/-0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r AD20.10 +*Want "MADBR/MADB NF +0/-0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r AD30.10 +*Want "MADBR/MADB NF +0/-0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r AD40.10 +*Want "MADBR/MADB NF +0/-0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r AD50.10 +*Want "MADBR/MADB NF +0/-0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r AD60.10 +*Want "MADBR/MADB NF +0/-0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r AD70.10 +*Want "MADBR/MADB NF +0/-0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r AD80.10 +*Want "MADBR/MADB NF +0/+0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r AD90.10 +*Want "MADBR/MADB NF +0/+0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r ADA0.10 +*Want "MADBR/MADB NF +0/+0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r ADB0.10 +*Want "MADBR/MADB NF +0/+0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r ADC0.10 +*Want "MADBR/MADB NF +0/+0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r ADD0.10 +*Want "MADBR/MADB NF +0/+0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r ADE0.10 +*Want "MADBR/MADB NF +0/+0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r ADF0.10 +*Want "MADBR/MADB NF +0/+0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r AE00.10 +*Want "MADBR/MADB NF +0/+2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r AE10.10 +*Want "MADBR/MADB NF +0/+2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r AE20.10 +*Want "MADBR/MADB NF +0/+2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r AE30.10 +*Want "MADBR/MADB NF +0/+2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r AE40.10 +*Want "MADBR/MADB NF +0/+2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r AE50.10 +*Want "MADBR/MADB NF +0/+2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r AE60.10 +*Want "MADBR/MADB NF +0/+2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r AE70.10 +*Want "MADBR/MADB NF +0/+2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r AE80.10 +*Want "MADBR/MADB NF +0/+inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r AE90.10 +*Want "MADBR/MADB NF +0/+inf/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r AEA0.10 +*Want "MADBR/MADB NF +0/+inf/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r AEB0.10 +*Want "MADBR/MADB NF +0/+inf/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r AEC0.10 +*Want "MADBR/MADB NF +0/+inf/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r AED0.10 +*Want "MADBR/MADB NF +0/+inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r AEE0.10 +*Want "MADBR/MADB NF +0/+inf/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r AEF0.10 +*Want "MADBR/MADB NF +0/+inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r AF00.10 +*Want "MADBR/MADB NF +0/-QNaN/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r AF10.10 +*Want "MADBR/MADB NF +0/-QNaN/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r AF20.10 +*Want "MADBR/MADB NF +0/-QNaN/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r AF30.10 +*Want "MADBR/MADB NF +0/-QNaN/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r AF40.10 +*Want "MADBR/MADB NF +0/-QNaN/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r AF50.10 +*Want "MADBR/MADB NF +0/-QNaN/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r AF60.10 +*Want "MADBR/MADB NF +0/-QNaN/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r AF70.10 +*Want "MADBR/MADB NF +0/-QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r AF80.10 +*Want "MADBR/MADB NF +0/+SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r AF90.10 +*Want "MADBR/MADB NF +0/+SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r AFA0.10 +*Want "MADBR/MADB NF +0/+SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r AFB0.10 +*Want "MADBR/MADB NF +0/+SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r AFC0.10 +*Want "MADBR/MADB NF +0/+SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r AFD0.10 +*Want "MADBR/MADB NF +0/+SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r AFE0.10 +*Want "MADBR/MADB NF +0/+SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r AFF0.10 +*Want "MADBR/MADB NF +0/+SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B000.10 +*Want "MADBR/MADB NF +2.0/-inf/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r B010.10 +*Want "MADBR/MADB NF +2.0/-inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B020.10 +*Want "MADBR/MADB NF +2.0/-inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r B030.10 +*Want "MADBR/MADB NF +2.0/-inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r B040.10 +*Want "MADBR/MADB NF +2.0/-inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B050.10 +*Want "MADBR/MADB NF +2.0/-inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r B060.10 +*Want "MADBR/MADB NF +2.0/-inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r B070.10 +*Want "MADBR/MADB NF +2.0/-inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B080.10 +*Want "MADBR/MADB NF +2.0/-2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r B090.10 +*Want "MADBR/MADB NF +2.0/-2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B0A0.10 +*Want "MADBR/MADB NF +2.0/-2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r B0B0.10 +*Want "MADBR/MADB NF +2.0/-2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r B0C0.10 +*Want "MADBR/MADB NF +2.0/-2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B0D0.10 +*Want "MADBR/MADB NF +2.0/-2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r B0E0.10 +*Want "MADBR/MADB NF +2.0/-2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r B0F0.10 +*Want "MADBR/MADB NF +2.0/-2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B100.10 +*Want "MADBR/MADB NF +2.0/-0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r B110.10 +*Want "MADBR/MADB NF +2.0/-0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B120.10 +*Want "MADBR/MADB NF +2.0/-0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r B130.10 +*Want "MADBR/MADB NF +2.0/-0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r B140.10 +*Want "MADBR/MADB NF +2.0/-0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B150.10 +*Want "MADBR/MADB NF +2.0/-0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r B160.10 +*Want "MADBR/MADB NF +2.0/-0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r B170.10 +*Want "MADBR/MADB NF +2.0/-0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B180.10 +*Want "MADBR/MADB NF +2.0/+0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r B190.10 +*Want "MADBR/MADB NF +2.0/+0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B1A0.10 +*Want "MADBR/MADB NF +2.0/+0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r B1B0.10 +*Want "MADBR/MADB NF +2.0/+0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r B1C0.10 +*Want "MADBR/MADB NF +2.0/+0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B1D0.10 +*Want "MADBR/MADB NF +2.0/+0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r B1E0.10 +*Want "MADBR/MADB NF +2.0/+0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r B1F0.10 +*Want "MADBR/MADB NF +2.0/+0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B200.10 +*Want "MADBR/MADB NF +2.0/+2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r B210.10 +*Want "MADBR/MADB NF +2.0/+2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B220.10 +*Want "MADBR/MADB NF +2.0/+2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r B230.10 +*Want "MADBR/MADB NF +2.0/+2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r B240.10 +*Want "MADBR/MADB NF +2.0/+2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B250.10 +*Want "MADBR/MADB NF +2.0/+2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r B260.10 +*Want "MADBR/MADB NF +2.0/+2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r B270.10 +*Want "MADBR/MADB NF +2.0/+2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B280.10 +*Want "MADBR/MADB NF +2.0/+inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r B290.10 +*Want "MADBR/MADB NF +2.0/+inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B2A0.10 +*Want "MADBR/MADB NF +2.0/+inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r B2B0.10 +*Want "MADBR/MADB NF +2.0/+inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r B2C0.10 +*Want "MADBR/MADB NF +2.0/+inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B2D0.10 +*Want "MADBR/MADB NF +2.0/+inf/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r B2E0.10 +*Want "MADBR/MADB NF +2.0/+inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r B2F0.10 +*Want "MADBR/MADB NF +2.0/+inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B300.10 +*Want "MADBR/MADB NF +2.0/-QNaN/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r B310.10 +*Want "MADBR/MADB NF +2.0/-QNaN/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B320.10 +*Want "MADBR/MADB NF +2.0/-QNaN/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r B330.10 +*Want "MADBR/MADB NF +2.0/-QNaN/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r B340.10 +*Want "MADBR/MADB NF +2.0/-QNaN/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B350.10 +*Want "MADBR/MADB NF +2.0/-QNaN/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r B360.10 +*Want "MADBR/MADB NF +2.0/-QNaN/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r B370.10 +*Want "MADBR/MADB NF +2.0/-QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B380.10 +*Want "MADBR/MADB NF +2.0/+SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r B390.10 +*Want "MADBR/MADB NF +2.0/+SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r B3A0.10 +*Want "MADBR/MADB NF +2.0/+SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r B3B0.10 +*Want "MADBR/MADB NF +2.0/+SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r B3C0.10 +*Want "MADBR/MADB NF +2.0/+SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r B3D0.10 +*Want "MADBR/MADB NF +2.0/+SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r B3E0.10 +*Want "MADBR/MADB NF +2.0/+SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B3F0.10 +*Want "MADBR/MADB NF +2.0/+SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B400.10 +*Want "MADBR/MADB NF +inf/-inf/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r B410.10 +*Want "MADBR/MADB NF +inf/-inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B420.10 +*Want "MADBR/MADB NF +inf/-inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r B430.10 +*Want "MADBR/MADB NF +inf/-inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r B440.10 +*Want "MADBR/MADB NF +inf/-inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B450.10 +*Want "MADBR/MADB NF +inf/-inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r B460.10 +*Want "MADBR/MADB NF +inf/-inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r B470.10 +*Want "MADBR/MADB NF +inf/-inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B480.10 +*Want "MADBR/MADB NF +inf/-2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r B490.10 +*Want "MADBR/MADB NF +inf/-2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B4A0.10 +*Want "MADBR/MADB NF +inf/-2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r B4B0.10 +*Want "MADBR/MADB NF +inf/-2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r B4C0.10 +*Want "MADBR/MADB NF +inf/-2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B4D0.10 +*Want "MADBR/MADB NF +inf/-2.0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r B4E0.10 +*Want "MADBR/MADB NF +inf/-2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r B4F0.10 +*Want "MADBR/MADB NF +inf/-2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B500.10 +*Want "MADBR/MADB NF +inf/-0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r B510.10 +*Want "MADBR/MADB NF +inf/-0/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r B520.10 +*Want "MADBR/MADB NF +inf/-0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r B530.10 +*Want "MADBR/MADB NF +inf/-0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r B540.10 +*Want "MADBR/MADB NF +inf/-0/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r B550.10 +*Want "MADBR/MADB NF +inf/-0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r B560.10 +*Want "MADBR/MADB NF +inf/-0/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B570.10 +*Want "MADBR/MADB NF +inf/-0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B580.10 +*Want "MADBR/MADB NF +inf/+0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r B590.10 +*Want "MADBR/MADB NF +inf/+0/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r B5A0.10 +*Want "MADBR/MADB NF +inf/+0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r B5B0.10 +*Want "MADBR/MADB NF +inf/+0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r B5C0.10 +*Want "MADBR/MADB NF +inf/+0/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r B5D0.10 +*Want "MADBR/MADB NF +inf/+0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r B5E0.10 +*Want "MADBR/MADB NF +inf/+0/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B5F0.10 +*Want "MADBR/MADB NF +inf/+0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B600.10 +*Want "MADBR/MADB NF +inf/+2.0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r B610.10 +*Want "MADBR/MADB NF +inf/+2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B620.10 +*Want "MADBR/MADB NF +inf/+2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r B630.10 +*Want "MADBR/MADB NF +inf/+2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r B640.10 +*Want "MADBR/MADB NF +inf/+2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B650.10 +*Want "MADBR/MADB NF +inf/+2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r B660.10 +*Want "MADBR/MADB NF +inf/+2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r B670.10 +*Want "MADBR/MADB NF +inf/+2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B680.10 +*Want "MADBR/MADB NF +inf/+inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r B690.10 +*Want "MADBR/MADB NF +inf/+inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B6A0.10 +*Want "MADBR/MADB NF +inf/+inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r B6B0.10 +*Want "MADBR/MADB NF +inf/+inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r B6C0.10 +*Want "MADBR/MADB NF +inf/+inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B6D0.10 +*Want "MADBR/MADB NF +inf/+inf/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r B6E0.10 +*Want "MADBR/MADB NF +inf/+inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r B6F0.10 +*Want "MADBR/MADB NF +inf/+inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B700.10 +*Want "MADBR/MADB NF +inf/-QNaN/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r B710.10 +*Want "MADBR/MADB NF +inf/-QNaN/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B720.10 +*Want "MADBR/MADB NF +inf/-QNaN/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r B730.10 +*Want "MADBR/MADB NF +inf/-QNaN/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r B740.10 +*Want "MADBR/MADB NF +inf/-QNaN/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B750.10 +*Want "MADBR/MADB NF +inf/-QNaN/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r B760.10 +*Want "MADBR/MADB NF +inf/-QNaN/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r B770.10 +*Want "MADBR/MADB NF +inf/-QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B780.10 +*Want "MADBR/MADB NF +inf/+SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r B790.10 +*Want "MADBR/MADB NF +inf/+SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r B7A0.10 +*Want "MADBR/MADB NF +inf/+SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r B7B0.10 +*Want "MADBR/MADB NF +inf/+SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r B7C0.10 +*Want "MADBR/MADB NF +inf/+SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r B7D0.10 +*Want "MADBR/MADB NF +inf/+SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r B7E0.10 +*Want "MADBR/MADB NF +inf/+SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B7F0.10 +*Want "MADBR/MADB NF +inf/+SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B800.10 +*Want "MADBR/MADB NF -QNaN/-inf/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r B810.10 +*Want "MADBR/MADB NF -QNaN/-inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B820.10 +*Want "MADBR/MADB NF -QNaN/-inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r B830.10 +*Want "MADBR/MADB NF -QNaN/-inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r B840.10 +*Want "MADBR/MADB NF -QNaN/-inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B850.10 +*Want "MADBR/MADB NF -QNaN/-inf/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r B860.10 +*Want "MADBR/MADB NF -QNaN/-inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r B870.10 +*Want "MADBR/MADB NF -QNaN/-inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B880.10 +*Want "MADBR/MADB NF -QNaN/-2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r B890.10 +*Want "MADBR/MADB NF -QNaN/-2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B8A0.10 +*Want "MADBR/MADB NF -QNaN/-2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r B8B0.10 +*Want "MADBR/MADB NF -QNaN/-2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r B8C0.10 +*Want "MADBR/MADB NF -QNaN/-2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B8D0.10 +*Want "MADBR/MADB NF -QNaN/-2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r B8E0.10 +*Want "MADBR/MADB NF -QNaN/-2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r B8F0.10 +*Want "MADBR/MADB NF -QNaN/-2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B900.10 +*Want "MADBR/MADB NF -QNaN/-0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r B910.10 +*Want "MADBR/MADB NF -QNaN/-0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B920.10 +*Want "MADBR/MADB NF -QNaN/-0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r B930.10 +*Want "MADBR/MADB NF -QNaN/-0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r B940.10 +*Want "MADBR/MADB NF -QNaN/-0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B950.10 +*Want "MADBR/MADB NF -QNaN/-0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r B960.10 +*Want "MADBR/MADB NF -QNaN/-0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r B970.10 +*Want "MADBR/MADB NF -QNaN/-0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B980.10 +*Want "MADBR/MADB NF -QNaN/+0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r B990.10 +*Want "MADBR/MADB NF -QNaN/+0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B9A0.10 +*Want "MADBR/MADB NF -QNaN/+0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r B9B0.10 +*Want "MADBR/MADB NF -QNaN/+0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r B9C0.10 +*Want "MADBR/MADB NF -QNaN/+0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B9D0.10 +*Want "MADBR/MADB NF -QNaN/+0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r B9E0.10 +*Want "MADBR/MADB NF -QNaN/+0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r B9F0.10 +*Want "MADBR/MADB NF -QNaN/+0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BA00.10 +*Want "MADBR/MADB NF -QNaN/+2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r BA10.10 +*Want "MADBR/MADB NF -QNaN/+2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r BA20.10 +*Want "MADBR/MADB NF -QNaN/+2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r BA30.10 +*Want "MADBR/MADB NF -QNaN/+2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r BA40.10 +*Want "MADBR/MADB NF -QNaN/+2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r BA50.10 +*Want "MADBR/MADB NF -QNaN/+2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r BA60.10 +*Want "MADBR/MADB NF -QNaN/+2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r BA70.10 +*Want "MADBR/MADB NF -QNaN/+2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BA80.10 +*Want "MADBR/MADB NF -QNaN/+inf/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r BA90.10 +*Want "MADBR/MADB NF -QNaN/+inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r BAA0.10 +*Want "MADBR/MADB NF -QNaN/+inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r BAB0.10 +*Want "MADBR/MADB NF -QNaN/+inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r BAC0.10 +*Want "MADBR/MADB NF -QNaN/+inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r BAD0.10 +*Want "MADBR/MADB NF -QNaN/+inf/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r BAE0.10 +*Want "MADBR/MADB NF -QNaN/+inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r BAF0.10 +*Want "MADBR/MADB NF -QNaN/+inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BB00.10 +*Want "MADBR/MADB NF -QNaN/-QNaN/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r BB10.10 +*Want "MADBR/MADB NF -QNaN/-QNaN/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r BB20.10 +*Want "MADBR/MADB NF -QNaN/-QNaN/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r BB30.10 +*Want "MADBR/MADB NF -QNaN/-QNaN/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r BB40.10 +*Want "MADBR/MADB NF -QNaN/-QNaN/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r BB50.10 +*Want "MADBR/MADB NF -QNaN/-QNaN/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r BB60.10 +*Want "MADBR/MADB NF -QNaN/-QNaN/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r BB70.10 +*Want "MADBR/MADB NF -QNaN/-QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BB80.10 +*Want "MADBR/MADB NF -QNaN/+SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r BB90.10 +*Want "MADBR/MADB NF -QNaN/+SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BBA0.10 +*Want "MADBR/MADB NF -QNaN/+SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r BBB0.10 +*Want "MADBR/MADB NF -QNaN/+SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r BBC0.10 +*Want "MADBR/MADB NF -QNaN/+SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BBD0.10 +*Want "MADBR/MADB NF -QNaN/+SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r BBE0.10 +*Want "MADBR/MADB NF -QNaN/+SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BBF0.10 +*Want "MADBR/MADB NF -QNaN/+SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BC00.10 +*Want "MADBR/MADB NF +SNaN/-inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r BC10.10 +*Want "MADBR/MADB NF +SNaN/-inf/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BC20.10 +*Want "MADBR/MADB NF +SNaN/-inf/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r BC30.10 +*Want "MADBR/MADB NF +SNaN/-inf/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r BC40.10 +*Want "MADBR/MADB NF +SNaN/-inf/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BC50.10 +*Want "MADBR/MADB NF +SNaN/-inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r BC60.10 +*Want "MADBR/MADB NF +SNaN/-inf/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BC70.10 +*Want "MADBR/MADB NF +SNaN/-inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BC80.10 +*Want "MADBR/MADB NF +SNaN/-2.0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r BC90.10 +*Want "MADBR/MADB NF +SNaN/-2.0/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BCA0.10 +*Want "MADBR/MADB NF +SNaN/-2.0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r BCB0.10 +*Want "MADBR/MADB NF +SNaN/-2.0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r BCC0.10 +*Want "MADBR/MADB NF +SNaN/-2.0/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BCD0.10 +*Want "MADBR/MADB NF +SNaN/-2.0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r BCE0.10 +*Want "MADBR/MADB NF +SNaN/-2.0/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BCF0.10 +*Want "MADBR/MADB NF +SNaN/-2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BD00.10 +*Want "MADBR/MADB NF +SNaN/-0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r BD10.10 +*Want "MADBR/MADB NF +SNaN/-0/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BD20.10 +*Want "MADBR/MADB NF +SNaN/-0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r BD30.10 +*Want "MADBR/MADB NF +SNaN/-0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r BD40.10 +*Want "MADBR/MADB NF +SNaN/-0/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BD50.10 +*Want "MADBR/MADB NF +SNaN/-0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r BD60.10 +*Want "MADBR/MADB NF +SNaN/-0/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BD70.10 +*Want "MADBR/MADB NF +SNaN/-0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BD80.10 +*Want "MADBR/MADB NF +SNaN/+0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r BD90.10 +*Want "MADBR/MADB NF +SNaN/+0/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BDA0.10 +*Want "MADBR/MADB NF +SNaN/+0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r BDB0.10 +*Want "MADBR/MADB NF +SNaN/+0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r BDC0.10 +*Want "MADBR/MADB NF +SNaN/+0/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BDD0.10 +*Want "MADBR/MADB NF +SNaN/+0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r BDE0.10 +*Want "MADBR/MADB NF +SNaN/+0/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BDF0.10 +*Want "MADBR/MADB NF +SNaN/+0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BE00.10 +*Want "MADBR/MADB NF +SNaN/+2.0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r BE10.10 +*Want "MADBR/MADB NF +SNaN/+2.0/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BE20.10 +*Want "MADBR/MADB NF +SNaN/+2.0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r BE30.10 +*Want "MADBR/MADB NF +SNaN/+2.0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r BE40.10 +*Want "MADBR/MADB NF +SNaN/+2.0/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BE50.10 +*Want "MADBR/MADB NF +SNaN/+2.0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r BE60.10 +*Want "MADBR/MADB NF +SNaN/+2.0/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BE70.10 +*Want "MADBR/MADB NF +SNaN/+2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BE80.10 +*Want "MADBR/MADB NF +SNaN/+inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r BE90.10 +*Want "MADBR/MADB NF +SNaN/+inf/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BEA0.10 +*Want "MADBR/MADB NF +SNaN/+inf/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r BEB0.10 +*Want "MADBR/MADB NF +SNaN/+inf/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r BEC0.10 +*Want "MADBR/MADB NF +SNaN/+inf/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BED0.10 +*Want "MADBR/MADB NF +SNaN/+inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r BEE0.10 +*Want "MADBR/MADB NF +SNaN/+inf/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BEF0.10 +*Want "MADBR/MADB NF +SNaN/+inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BF00.10 +*Want "MADBR/MADB NF +SNaN/-QNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r BF10.10 +*Want "MADBR/MADB NF +SNaN/-QNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BF20.10 +*Want "MADBR/MADB NF +SNaN/-QNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r BF30.10 +*Want "MADBR/MADB NF +SNaN/-QNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r BF40.10 +*Want "MADBR/MADB NF +SNaN/-QNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BF50.10 +*Want "MADBR/MADB NF +SNaN/-QNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r BF60.10 +*Want "MADBR/MADB NF +SNaN/-QNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BF70.10 +*Want "MADBR/MADB NF +SNaN/-QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BF80.10 +*Want "MADBR/MADB NF +SNaN/+SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r BF90.10 +*Want "MADBR/MADB NF +SNaN/+SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BFA0.10 +*Want "MADBR/MADB NF +SNaN/+SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r BFB0.10 +*Want "MADBR/MADB NF +SNaN/+SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r BFC0.10 +*Want "MADBR/MADB NF +SNaN/+SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BFD0.10 +*Want "MADBR/MADB NF +SNaN/+SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r BFE0.10 +*Want "MADBR/MADB NF +SNaN/+SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BFF0.10 +*Want "MADBR/MADB NF +SNaN/+SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 + + +# Long BFP Multiply And Add finite results +*Compare +r C000.10 +*Want "MADBR F Ovfl 1" FFF00000 00000000 DFEFFFFF FFFFFFFE +r C010.10 +*Want "MADB F Ovfl 1" FFF00000 00000000 DFEFFFFF FFFFFFFE +r C020.10 +*Want "MADBR F Ovfl 2" 7FF00000 00000000 1FFFFFFF FFFFFFFF +r C030.10 +*Want "MADB F Ovfl 2" 7FF00000 00000000 1FFFFFFF FFFFFFFF +r C040.10 +*Want "MADBR F Ufl 1" 00080000 00000001 60000000 00000002 +r C050.10 +*Want "MADB F Ufl 1" 00080000 00000001 60000000 00000002 +r C060.10 +*Want "MADBR F Ufl 2" 00080000 00000000 60000000 00000001 +r C070.10 +*Want "MADB F Ufl 2" 00080000 00000000 60000000 00000001 +r C080.10 +*Want "MADBR F Nmin" 0023FFFF FFFFFFFF 0023FFFF FFFFFFFF +r C090.10 +*Want "MADB F Nmin" 0023FFFF FFFFFFFF 0023FFFF FFFFFFFF +r C0A0.10 +*Want "MADBR F Incr" 3FF90000 0000000D 3FF90000 0000000D +r C0B0.10 +*Want "MADB F Incr" 3FF90000 0000000D 3FF90000 0000000D +r C0C0.10 +*Want "MADBR F Trun" 3FF90000 00000007 3FF90000 00000007 +r C0D0.10 +*Want "MADB F Trun" 3FF90000 00000007 3FF90000 00000007 + + +# Long BFP Multiply And Add finite results - FPCR contents +*Compare +r C200.10 +*Want "MADBR/MADB F Ovfl 1 FPCR" 00280000 F8002800 00280000 F8002800 +r C210.10 +*Want "MADBR/MADB F Ovfl 2 FPCR" 00280000 F8002000 00280000 F8002000 +r C220.10 +*Want "MADBR/MADB F Ufl 1 FPCR" 00180000 F8001C00 00180000 F8001C00 +r C230.10 +*Want "MADBR/MADB F Ufl 2 FPCR" 00180000 F8001000 00180000 F8001000 +r C240.10 +*Want "MADBR/MADB F Nmin FPCR" 00000000 F8000000 00000000 F8000000 +r C250.10 +*Want "MADBR/MADB F Incr FPCR" 00080000 F8000C00 00080000 F8000C00 +r C260.10 +*Want "MADBR/MADB F Trun FPCR" 00080000 F8000800 00080000 F8000800 + + +# Long BFP Multiply And Add rounding mode results +*Compare +r C500.10 +*Want "MADBR/MADB RM +NZ RNTE" 3FF90000 00000007 3FF90000 00000007 +r C510.10 +*Want "MADBR/MADB RM +NZ RZ" 3FF90000 00000007 3FF90000 00000007 +r C520.10 +*Want "MADBR/MADB RM +NZ RP" 3FF90000 00000008 3FF90000 00000008 +r C530.10 +*Want "MADBR/MADB RM +NZ RM" 3FF90000 00000007 3FF90000 00000007 +r C540.10 +*Want "MADBR/MADB RM +NZ RFS" 3FF90000 00000007 3FF90000 00000007 +r C550.10 +*Want "MADBR/MADB RM -NZ RNTE" BFF90000 00000007 BFF90000 00000007 +r C560.10 +*Want "MADBR/MADB RM -NZ RZ" BFF90000 00000007 BFF90000 00000007 +r C570.10 +*Want "MADBR/MADB RM -NZ RP" BFF90000 00000007 BFF90000 00000007 +r C580.10 +*Want "MADBR/MADB RM -NZ RM" BFF90000 00000008 BFF90000 00000008 +r C590.10 +*Want "MADBR/MADB RM -NZ RFS" BFF90000 00000007 BFF90000 00000007 +r C5A0.10 +*Want "MADBR/MADB RM +NA RNTE" 3FF90000 0000000D 3FF90000 0000000D +r C5B0.10 +*Want "MADBR/MADB RM +NA RZ" 3FF90000 0000000C 3FF90000 0000000C +r C5C0.10 +*Want "MADBR/MADB RM +NA RP" 3FF90000 0000000D 3FF90000 0000000D +r C5D0.10 +*Want "MADBR/MADB RM +NA RM" 3FF90000 0000000C 3FF90000 0000000C +r C5E0.10 +*Want "MADBR/MADB RM +NA RFS" 3FF90000 0000000D 3FF90000 0000000D +r C5F0.10 +*Want "MADBR/MADB RM -NA RNTE" BFF90000 0000000D BFF90000 0000000D +r C600.10 +*Want "MADBR/MADB RM -NA RZ" BFF90000 0000000C BFF90000 0000000C +r C610.10 +*Want "MADBR/MADB RM -NA RP" BFF90000 0000000C BFF90000 0000000C +r C620.10 +*Want "MADBR/MADB RM -NA RM" BFF90000 0000000D BFF90000 0000000D +r C630.10 +*Want "MADBR/MADB RM -NA RFS" BFF90000 0000000D BFF90000 0000000D +r C640.10 +*Want "MADBR/MADB RM +TZ RNTE" 3FF90000 00000008 3FF90000 00000008 +r C650.10 +*Want "MADBR/MADB RM +TZ RZ" 3FF90000 00000008 3FF90000 00000008 +r C660.10 +*Want "MADBR/MADB RM +TZ RP" 3FF90000 00000009 3FF90000 00000009 +r C670.10 +*Want "MADBR/MADB RM +TZ RM" 3FF90000 00000008 3FF90000 00000008 +r C680.10 +*Want "MADBR/MADB RM +TZ RFS" 3FF90000 00000009 3FF90000 00000009 +r C690.10 +*Want "MADBR/MADB RM -TZ RNTE" BFF90000 00000008 BFF90000 00000008 +r C6A0.10 +*Want "MADBR/MADB RM -TZ RZ" BFF90000 00000008 BFF90000 00000008 +r C6B0.10 +*Want "MADBR/MADB RM -TZ RP" BFF90000 00000008 BFF90000 00000008 +r C6C0.10 +*Want "MADBR/MADB RM -TZ RM" BFF90000 00000009 BFF90000 00000009 +r C6D0.10 +*Want "MADBR/MADB RM -TZ RFS" BFF90000 00000009 BFF90000 00000009 +r C6E0.10 +*Want "MADBR/MADB RM +TA RNTE" 3FF90000 0000001A 3FF90000 0000001A +r C6F0.10 +*Want "MADBR/MADB RM +TA RZ" 3FF90000 00000019 3FF90000 00000019 +r C700.10 +*Want "MADBR/MADB RM +TA RP" 3FF90000 0000001A 3FF90000 0000001A +r C710.10 +*Want "MADBR/MADB RM +TA RM" 3FF90000 00000019 3FF90000 00000019 +r C720.10 +*Want "MADBR/MADB RM +TA RFS" 3FF90000 00000019 3FF90000 00000019 +r C730.10 +*Want "MADBR/MADB RM -TA RNTE" BFF90000 0000001A BFF90000 0000001A +r C740.10 +*Want "MADBR/MADB RM -TA RZ" BFF90000 00000019 BFF90000 00000019 +r C750.10 +*Want "MADBR/MADB RM -TA RP" BFF90000 00000019 BFF90000 00000019 +r C760.10 +*Want "MADBR/MADB RM -TA RM" BFF90000 0000001A BFF90000 0000001A +r C770.10 +*Want "MADBR/MADB RM -TA RFS" BFF90000 00000019 BFF90000 00000019 + + +# Long BFP Multiply And Add rounding mode results - FPCR contents +*Compare +r CA00.10 +*Want "MADBR/MADB RM +NZ RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r CA10.10 +*Want "MADBR/MADB RM +NZ RP, RM FPCR" 00080002 00080002 00080003 00080003 +r CA20.10 +*Want "MADBR/MADB RM +NZ RFS FPCR" 00080007 00080007 00000000 00000000 +r CA30.10 +*Want "MADBR/MADB RM -NZ RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r CA40.10 +*Want "MADBR/MADB RM -NZ RP, RM FPCR" 00080002 00080002 00080003 00080003 +r CA50.10 +*Want "MADBR/MADB RM -NZ RFS FPCR" 00080007 00080007 00000000 00000000 +r CA60.10 +*Want "MADBR/MADB RM +NA RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r CA70.10 +*Want "MADBR/MADB RM +NA RP, RM FPCR" 00080002 00080002 00080003 00080003 +r CA80.10 +*Want "MADBR/MADB RM +NA RFS FPCR" 00080007 00080007 00000000 00000000 +r CA90.10 +*Want "MADBR/MADB RM -NA RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r CAA0.10 +*Want "MADBR/MADB RM -NA RP, RM FPCR" 00080002 00080002 00080003 00080003 +r CAB0.10 +*Want "MADBR/MADB RM -NA RFS FPCR" 00080007 00080007 00000000 00000000 +r CAC0.10 +*Want "MADBR/MADB RM +TZ RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r CAD0.10 +*Want "MADBR/MADB RM +TZ RP, RM FPCR" 00080002 00080002 00080003 00080003 +r CAE0.10 +*Want "MADBR/MADB RM +TZ RFS FPCR" 00080007 00080007 00000000 00000000 +r CAF0.10 +*Want "MADBR/MADB RM -TZ RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r CB00.10 +*Want "MADBR/MADB RM -TZ RP, RM FPCR" 00080002 00080002 00080003 00080003 +r CB10.10 +*Want "MADBR/MADB RM -TZ RFS FPCR" 00080007 00080007 00000000 00000000 +r CB20.10 +*Want "MADBR/MADB RM +TA RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r CB30.10 +*Want "MADBR/MADB RM +TA RP, RM FPCR" 00080002 00080002 00080003 00080003 +r CB40.10 +*Want "MADBR/MADB RM +TA RFS FPCR" 00080007 00080007 00000000 00000000 +r CB50.10 +*Want "MADBR/MADB RM -TA RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r CB60.10 +*Want "MADBR/MADB RM -TA RP, RM FPCR" 00080002 00080002 00080003 00080003 +r CB70.10 +*Want "MADBR/MADB RM -TA RFS FPCR" 00080007 00080007 00000000 00000000 + + +*Done + diff --git a/tests/bfp-022-multsub.asm b/tests/bfp-022-multsub.asm new file mode 100644 index 000000000..f21008d86 --- /dev/null +++ b/tests/bfp-022-multsub.asm @@ -0,0 +1,1110 @@ + TITLE 'bfp-022-multsub.asm: Test IEEE Multiply And Subtract' +*********************************************************************** +* +*Testcase IEEE MULTIPLY AND SUBTRACT +* Test case capability includes IEEE exceptions trappable and +* otherwise. Test results, FPCR flags, the Condition code, and any +* DXC are saved for all tests. +* +* This test program is focused on the four fused Multiply And Subtract +* instructions. Standard Multiply and Multiply to longer precision +* are tested in other programs. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* bfp-022-multsub.asm +* +* This assembly-language source file is part of the +* Hercules Decimal Floating Point Validation Package +* by Stephen R. Orso +* +* Copyright 2016 by Stephen R Orso. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* +* 3. The name of the author may not be used to endorse or promote +* products derived from this software without specific prior written +* permission. +* +* DISCLAMER: THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* HOLDER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* Tests the following three conversion instructions +* MULTIPLY AND SUBTRACT (short BFP, RRE) +* MULTIPLY AND SUBTRACT (long BFP, RRE) +* MULTIPLY AND SUBTRACT (short BFP, RXE) +* MULTIPLY AND SUBTRACT (long BFP, RXE) +* +* +* Test data is compiled into this program. The test script that runs +* this program can provide alternative test data through Hercules R +* commands. +* +* Test Case Order +* 1) Short BFP basic tests, including traps and NaN propagation +* 2) Short BFP finite number tests, including traps and scaling +* 3) Short BFP FPC-controlled rounding mode exhaustive tests +* 4) Long BFP basic tests, including traps and NaN propagation +* 5) Long BFP finite number tests, including traps and scaling +* 6) Long BFP FPC-controlled rounding mode exhaustive tests +* +* Three input test sets are provided each for short and long BFP +* inputs. Test values are the same for each precision for most +* tests. Overflow and underflow each require precision- +* dependent test values. +* +* Review of Softfloat code for multiply and add shows that the +* multiplication and addition are performed in precision-independent +* format. Overflow, underflow, inexact, and incremented are detected +* upon conversion from precision-independent format to the target +* format. As a result, it should not matter whether overflow etc is +* caused by the multiplication or the addition. We will include +* a few test cases where this differs in the finite testing section, +* but that's all. +* +* Also tests the following floating point support instructions +* LOAD (Short) +* LOAD (Long) +* LFPC (Load Floating Point Control Register) +* SRNMB (Set BFP Rounding Mode 3-bit) +* STORE (Short) +* STORE (Long) +* STFPC (Store Floating Point Control Register) +* +*********************************************************************** + SPACE 2 + MACRO + PADCSECT &ENDLABL +.* +.* Macro to pad the CSECT to include result data areas if this test +.* program is not being assembled using asma. asma generates a core +.* image that is loaded by the loadcore command, and because the +.* core image is a binary stored in Github, it makes sense to make +.* this small effort to keep the core image small. +.* + AIF (D'&ENDLABL).GOODPAD + MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + MNOTE *,'No CSECT padding performed' + MEXIT +.* +.GOODPAD ANOP Label valid. See if we're on asma + AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + ORG &ENDLABL-1 Not ASMA. Pad CSECT + MEXIT +.* +.NOPAD ANOP + MNOTE *,'asma detected; no CSECT padding performed' + MEND +* +* Note: for compatibility with the z/CMS test rig, do not change +* or use R11, R14, or R15. Everything else is fair game. +* +BFPMULS START 0 +STRTLABL EQU * +R0 EQU 0 Work register for cc extraction +R1 EQU 1 +R2 EQU 2 Holds count of test input values +R3 EQU 3 Points to next test input value(s) +R4 EQU 4 Rounding tests inner loop control +R5 EQU 5 Rounding tests outer loop control +R6 EQU 6 Rounding tests top of inner loop +R7 EQU 7 Pointer to next result value(s) +R8 EQU 8 Pointer to next FPCR result +R9 EQU 9 Rounding tests top of outer loop +R10 EQU 10 Pointer to test address list +R11 EQU 11 **Reserved for z/CMS test rig +R12 EQU 12 Holds number of test cases in set +R13 EQU 13 Mainline return address +R14 EQU 14 **Return address for z/CMS test rig +R15 EQU 15 **Base register on z/CMS or Hyperion +* +* Floating Point Register equates to keep the cross reference clean +* +FPR0 EQU 0 +FPR1 EQU 1 +FPR2 EQU 2 +FPR3 EQU 3 +FPR4 EQU 4 +FPR5 EQU 5 +FPR6 EQU 6 +FPR7 EQU 7 +FPR8 EQU 8 +FPR9 EQU 9 +FPR10 EQU 10 +FPR11 EQU 11 +FPR12 EQU 12 +FPR13 EQU 13 +FPR14 EQU 14 +FPR15 EQU 15 +* + USING *,R15 +* +* Above works on real iron (R15=0 after sysclear) +* and in z/CMS (R15 points to start of load module) +* + SPACE 2 +*********************************************************************** +* +* Low core definitions, Restart PSW, and Program Check Routine. +* +*********************************************************************** + SPACE 2 + ORG STRTLABL+X'8E' Program check interrution code +PCINTCD DS H +* +PCOLDPSW EQU STRTLABL+X'150' z/Arch Program check old PSW +* + ORG STRTLABL+X'1A0' z/Arch Restart PSW + DC X'0000000180000000',AD(START) +* + ORG STRTLABL+X'1D0' z/Arch Program check old PSW + DC X'0000000000000000',AD(PROGCHK) +* +* Program check routine. If Data Exception, continue execution at +* the instruction following the program check. Otherwise, hard wait. +* No need to collect data. All interesting DXC stuff is captured +* in the FPCR. +* + ORG STRTLABL+X'200' +PROGCHK DS 0H Program check occured... + CLI PCINTCD+1,X'07' Data Exception? + JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) + LPSWE PCOLDPSW ..yes, resume program execution +PCNOTDTA DS 0H + LTR R14,R14 Return address provided? + BNZR R14 Yes, return to z/CMS test rig. + LPSWE HARDWAIT Not data exception, enter disabled wait + EJECT +*********************************************************************** +* +* Main program. Enable Advanced Floating Point, process test cases. +* +*********************************************************************** + SPACE 2 +START DS 0H + STCTL R0,R0,CTLR0 Store CR0 to enable AFP + OI CTLR0+1,X'04' Turn on AFP bit + LCTL R0,R0,CTLR0 Reload updated CR0 +* + LA R10,SHORTNF Point to short BFP non-finite inputs + BAS R13,SBFPNF Multiply short BFP non-finites + LA R10,SHORTF Point to short BFP finite inputs + BAS R13,SBFPF Multiply short BFP finites + LA R10,RMSHORTS Point to short BFP rounding mode tests + BAS R13,SBFPRM Multiply short BFP for rounding tests +* + LA R10,LONGNF Point to long BFP non-finite inputs + BAS R13,LBFPNF Multiply long BFP non-finites + LA R10,LONGF Point to long BFP finite inputs + BAS R13,LBFPF Multiply long BFP finites + LA R10,RMLONGS Point to long BFP rounding mode tests + BAS R13,LBFPRM Multiply long BFP for rounding tests +* + LTR R14,R14 Return address provided? + BNZR R14 ..Yes, return to z/CMS test rig. + LPSWE WAITPSW All done +* + DS 0D Ensure correct alignment for psw +WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end +* +CTLR0 DS F +FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags +* +* Input values parameter list, four fullwords for each test data set +* 1) Count, +* 2) Address of inputs, +* 3) Address to place results, and +* 4) Address to place DXC/Flags/cc values. +* + ORG STRTLABL+X'300' Enable run-time replacement +SHORTNF DS 0F Input pairs for short BFP non-finite tests + DC A(SBFPNFCT) + DC A(SBFPNFIN) + DC A(SBFPNFOT) + DC A(SBFPNFFL) +* +SHORTF DS 0F Input pairs for short BFP finite tests + DC A(SBFPCT) + DC A(SBFPIN) + DC A(SBFPOUT) + DC A(SBFPFLGS) +* +RMSHORTS DS 0F Input pairs for short BFP rounding testing + DC A(SBFPRMCT) + DC A(SBFPINRM) + DC A(SBFPRMO) + DC A(SBFPRMOF) +* +LONGNF DS 0F Input pairs for long BFP non-finite testing + DC A(LBFPNFCT) + DC A(LBFPNFIN) + DC A(LBFPNFOT) + DC A(LBFPNFFL) +* +LONGF DS 0F Input pairs for long BFP finite testing + DC A(LBFPCT) + DC A(LBFPIN) + DC A(LBFPOUT) + DC A(LBFPFLGS) +* +RMLONGS DS 0F Input pairs for long BFP rounding testing + DC A(LBFPRMCT) + DC A(LBFPINRM) + DC A(LBFPRMO) + DC A(LBFPRMOF) +* + EJECT +*********************************************************************** +* +* Perform Multiply And Subtract using provided short BFP inputs. This +* set of tests checks NaN propagation, operations on values that are +* not finite numbers, and other basic tests. This set generates +* results that can be validated against Figure 19-24 on page 19-39 of +* SA22-7832-10. +* +* Four results are generated for each input: one RRE with all +* exceptions non-trappable, a second RRE with all exceptions trappable, +* a third RXE with all exceptions non-trappable, a fourth RXE with all +* exceptions trappable. +* +* Because this is a three-operand instruction, validation against +* Figure 19-24, effectively an 8 x 8 x 8 table, will generate a +* phenomonal set of results. Namely 512 results of 16 bytes each +* plus 512 FPCR contents of 16 bytes each. +* +* The product and FPCR are stored for each result. +* +*********************************************************************** + SPACE 2 +SBFPNF DS 0H BFP Short non-finite values tests + LM R2,R3,0(R10) Get count and addr of multiplicand values + LM R8,R9,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller +* +SBFPNFLP DS 0H Top of outer loop - Multiplicand + LM R4,R5,0(R10) Get count and start of multiplier values +* ..which are the same as the multiplicands + BASR R12,0 Set top of middle loop +* + DS 0H Top of middle loop - multiplier + LM R6,R7,0(R10) Get count and start of subtrahend values +* ..which are the same as the multiplicands + BASR R1,0 Set top of inner loop - subtrahend +* +* Multiply and Add: R1 = R3 x R2 + R1 +* + LE FPR4,0(,R3) Get short BFP multiplicand + LE FPR1,0(,R5) Get short BFP multiplier +* + LFPC FPCREGNT Set exceptions non-trappable + LE FPR8,0(,R7) Get short BFP subtrahend + MSEBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE + STE FPR8,0(,R8) Store short BFP product-difference + STFPC 0(R9) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LE FPR8,0(,R7) Get short BFP subtrahend + MSEBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE + STE FPR8,4(,R8) Store short BFP product-difference + STFPC 4(R9) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable + LE FPR8,0(,R7) Get short BFP subtrahend + MSEB FPR8,FPR4,0(,R5) Mult. FPR4 by multiplier, add FPR8 RXE + STE FPR8,8(,R8) Store short BFP product-difference + STFPC 8(R9) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LE FPR8,0(,R7) Get short BFP subtrahend + MSEB FPR8,FPR4,0(,R5) Mult. FPR4 by multiplier, add FPR8 RXE + STE FPR8,12(,R8) Store short BFP product-difference + STFPC 12(R9) Store resulting FPCR flags and DXC +* + LA R8,4*4(,R8) Point to next product-diff. result area + LA R9,4*4(,R9) Point to next FPCR contents area + LA R7,4(,R7) Point to next subtrahend value + BCTR R6,R1 Loop through subtrahend values +* + LA R5,4(,R5) Point to next multiplier + BCTR R4,R12 Loop through multiplier values +* + LA R3,4(,R3) Point to next multiplicand + BCT R2,SBFPNFLP Loop through multiplicand values + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Multiply And Subtract using provided short BFP input triples. +* This set of tests triggers IEEE exceptions Overflow, Underflow, and +* Inexact and collects both trap and non-trap results. +* +* Four results are generated for each input: one RRE with all +* exceptions non-trappable, a second RRE with all exceptions trappable, +* a third RXE with all exceptions non-trappable, a fourth RXE with all +* exceptions trappable, +* +* The product and FPCR are stored for each result. +* +*********************************************************************** + SPACE 2 +SBFPF LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LFPC FPCREGNT Set exceptions non-trappable + LE FPR4,0(,R3) Get short BFP multiplicand + LE FPR1,1*4(,R3) Get short BFP multiplier + LE FPR8,2*4(,R3) Get short BFP subtrahend + MSEBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE + STE FPR8,0(,R7) Store short BFP product-difference + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LE FPR8,2*4(,R3) Reload short BFP subtrahend +* ..multiplier is still in FPR1, +* ..multiplicand is still in FPR4 + MSEBR FPR8,FPR4,FPR1 Multiply short FPR8 by FPR1 RRE + STE FPR8,1*4(,R7) Store short BFP product-difference + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable + LE FPR8,2*4(,R3) Reload short BFP subtrahend +* ..multiplicand is still in FPR4 + MSEB FPR8,FPR4,4(,R3) Mult. FPR4 by multiplier, add FPR8 RXE + STE FPR8,2*4(,R7) Store short BFP product + STFPC 8(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LE FPR8,2*4(,R3) Reload short BFP subtrahend +* ..multiplicand is still in FPR4 + MSEB FPR8,FPR4,4(,R3) Mult. FPR4 by multiplier, add FPR8 RXE + STE FPR8,3*4(,R7) Store short BFP product + STFPC 12(R8) Store resulting FPCR flags and DXC +* + LA R3,3*4(,R3) Point to next input value trible + LA R7,4*4(,R7) Point to next product result set + LA R8,4*4(,R8) Point to next FPCR result set + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Multiply And Subtract using provided short BFP input triples. +* This set of tests exhaustively tests all rounding modes available for +* Multiply And Subtract. The rounding mode can only be specified in +* the FPC. +* +* All five FPC rounding modes are tested because the preceeding tests, +* using rounding mode RNTE, do not often create results that require +* rounding. +* +* Two results are generated for each input and rounding mode: one RRE +* and one RXE. Traps are disabled for all rounding mode tests. +* +* The product and FPCR are stored for each test. +* +*********************************************************************** + SPACE 2 +SBFPRM LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + XR R1,R1 Zero register 1 for use in IC/STC/indexing + BASR R12,0 Set top of test case loop + + LA R5,FPCMCT Get count of FPC modes to be tested + BASR R9,0 Set top of rounding mode outer loop +* + IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 0(R1) Set FPC Rounding Mode + LE FPR4,0(,R3) Get short BFP multiplicand + LE FPR1,4(,R3) Get short BFP multiplier + LE FPR8,8(,R3) Get short BFP subtrahend + MSEBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE + STE FPR8,0(,R7) Store short BFP product-difference + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 0(R1) Set FPC Rounding Mode + LE FPR8,8(,R3) Get short BFP subtrahend +* ..multiplicand is still in FPR4 + MSEB FPR8,FPR4,4(,R3) Mult. FPR4 by multiplier, add FPR8 RXE + STE FPR8,4(,R7) Store short BFP product-difference + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LA R7,2*4(,R7) Point to next product result set + LA R8,2*4(,R8) Point to next FPCR result area +* + BCTR R5,R9 Iterate to next FPC mode for this input +* +* End of FPC modes to be tested. Advance to next test case. We will +* skip eight bytes of result area so that each set of five result +* value pairs starts at a memory address ending in zero for the +* convenience of memory dump review. +* + LA R3,3*4(,R3) Point to next input value pair triple + LA R7,8(,R7) Skip to start of next result set + LA R8,8(,R8) Skip to start of next FPCR result set + BCTR R2,R12 Advance to the next input pair +* + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Multiply And Subtract using provided long BFP inputs. This +* set of tests checks NaN propagation, operations on values that are +* not finite numbers, and other basic tests. This set generates +* results that can be validated against Figure 19-24 on page 19-39 of +* SA22-7832-10. +* +* Four results are generated for each input: one RRE with all +* exceptions non-trappable, a second RRE with all exceptions trappable, +* a third RXE with all exceptions non-trappable, a fourth RXE with all +* exceptions trappable. +* +* Because this is a three-operand instruction, validation against +* Figure 19-24, effectively an 8 x 8 x 8 table, will generate a +* phenomonal set of results. Namely 512 results of 32 bytes each +* plus 512 FPCR contents of 16 bytes each. +* +* The product and FPCR are stored for each result. +* +*********************************************************************** + SPACE 2 +LBFPNF DS 0H BFP long non-finite values tests + LM R2,R3,0(R10) Get count and addr of multiplicand values + LM R8,R9,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller +* +LBFPNFLP DS 0H Top of outer loop - Multiplicand + LM R4,R5,0(R10) Get count and start of multiplier values +* ..which are the same as the multiplicands + BASR R12,0 Set top of middle loop +* + DS 0H Top of middle loop - multiplier + LM R6,R7,0(R10) Get count and start of subtrahend values +* ..which are the same as the multiplicands + BASR R1,0 Set top of inner loop - subtrahend +* +* Multiply and Add: R1 = R3 x R2 + R1 +* + LE FPR4,0(,R3) Get long BFP multiplicand + LE FPR1,0(,R5) Get long BFP multiplier +* + LFPC FPCREGNT Set exceptions non-trappable + LD FPR8,0(,R7) Get long BFP subtrahend + MSDBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE + STD FPR8,0(,R8) Store long BFP product-difference + STFPC 0(R9) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LE FPR8,0(,R7) Get long BFP subtrahend + MSDBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE + STD FPR8,1*8(,R8) Store long BFP product-difference + STFPC 1*4(R9) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable + LE FPR8,0(,R7) Get long BFP subtrahend + MSDB FPR8,FPR4,0(,R5) Mult. FPR4 by multiplier, add FPR8 RXE + STD FPR8,2*8(,R8) Store long BFP product-difference + STFPC 2*4(R9) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LE FPR8,0(,R7) Get long BFP subtrahend + MSDB FPR8,FPR4,0(,R5) Mult. FPR4 by multiplier, add FPR8 RXE + STD FPR8,3*8(,R8) Store long BFP product-difference + STFPC 3*4(R9) Store resulting FPCR flags and DXC +* + LA R8,4*8(,R8) Point to next product-diff. result area + LA R9,4*4(,R9) Point to next FPCR contents area + LA R7,8(,R7) Point to next subtrahend value + BCTR R6,R1 Loop through subtrahend values +* + LA R5,8(,R5) Point to next multiplier + BCTR R4,R12 Loop through multiplier values +* + LA R3,8(,R3) Point to next multiplicand + BCT R2,LBFPNFLP Loop through multiplicand values + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Multiply And Subtract using provided long BFP input triples. +* This set of tests triggers IEEE exceptions Overflow, Underflow, and +* Inexact and collects non-trap and trap results. +* +* Four results are generated for each input: one RRE with all +* exceptions non-trappable, a second RRE with all exceptions trappable, +* a third RXE with all exceptions non-trappable, a fourth RXE with all +* exceptions trappable, +* +* The product and FPCR are stored for each result. +* +*********************************************************************** + SPACE 2 +LBFPF LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + BASR R12,0 Set top of loop +* + LFPC FPCREGNT Set exceptions non-trappable + LD FPR4,0(,R3) Get long BFP multiplicand + LD FPR1,8(,R3) Get long BFP multiplier + LD FPR8,16(,R3) Get long BFP subtrahend + MSDBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE + STD FPR8,0(,R7) Store long BFP product + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LD FPR8,16(,R3) Reload long BFP subtrahend +* ..multiplier is still in FPR1, +* ..multiplicand is still in FFR4 + MSDBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE + STD FPR8,8(,R7) Store long BFP product-difference + STFPC 1*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable + LD FPR8,16(,R3) Reload long BFP subtrahend +* ..multiplicand is still in FFR4 + MSDB FPR8,FPR4,8(,R3) Mult. FPR4 by multiplier, add FPR8 RXE + STD FPR8,2*8(,R7) Store long BFP product-difference + STFPC 2*4(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGTR Set exceptions trappable + LD FPR8,16(,R3) Reload long BFP subtrahend +* ..multiplicand is still in FFR4 + MSDB FPR8,FPR4,8(,R3) Mult. FPR4 by multiplier, add FPR8 RXE + STD FPR8,3*8(,R7) Store long BFP product-difference + STFPC 3*4(R8) Store resulting FPCR flags and DXC +* + LA R3,3*8(,R3) Point to next input value triple + LA R7,4*8(,R7) Point to next product-diff. result set + LA R8,4*4(,R8) Point to next FPCR result area + BCTR R2,R12 Convert next input value. + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Perform Multiply using provided long BFP input pairs. This set of +* tests exhaustively tests all rounding modes available for Multiply. +* The rounding mode can only be specified in the FPC. +* +* All five FPC rounding modes are tested because the preceeding tests, +* using rounding mode RNTE, do not often create results that require +* rounding. +* +* Two results are generated for each input and rounding mode: one RRE +* and one RXE. Traps are disabled for all rounding mode tests. +* +* The product and FPCR are stored for each result. +* +*********************************************************************** + SPACE 2 +LBFPRM LM R2,R3,0(R10) Get count and address of test input values + LM R7,R8,8(R10) Get address of result area and flag area. + LTR R2,R2 Any test cases? + BZR R13 ..No, return to caller + XR R1,R1 Zero register 1 for use in IC/STC/indexing + BASR R12,0 Set top of test case loop + + LA R5,FPCMCT Get count of FPC modes to be tested + BASR R9,0 Set top of rounding mode loop +* + IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 0(R1) Set FPC Rounding Mode + LD FPR4,0(,R3) Get long BFP multiplicand + LD FPR1,8(,R3) Get long BFP multiplier + LD FPR8,16(,R3) Get long BFP subtrahend + MSDBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE + STD FPR8,0(,R7) Store long BFP product-difference + STFPC 0(R8) Store resulting FPCR flags and DXC +* + LFPC FPCREGNT Set exceptions non-trappable, clear flags + SRNMB 0(R1) Set FPC Rounding Mode + LD FPR8,16(,R3) Reload long BFP subtrahend + MSDB FPR8,FPR4,8(,R3) Multiply long FPR8 by multiplier RXE + STD FPR8,8(,R7) Store long BFP product-difference + STFPC 4(R8) Store resulting FPCR flags and DXC +* + LA R7,2*8(,R7) Point to next product result set + LA R8,2*4(,R8) Point to next FPCR result area +* + BCTR R5,R9 Iterate to next FPC mode +* +* End of FPC modes to be tested. Advance to next test case. We will +* skip eight bytes of FPCR result area so that each set of five result +* FPCR contents pairs starts at a memory address ending in zero for the +* convenience of memory dump review. +* + LA R3,3*8(,R3) Point to next input value triple + LA R8,8(,R8) Skip to start of next FPCR result area + BCTR R2,R12 Multiply next input value lots of times +* + BR R13 All converted; return. + EJECT +*********************************************************************** +* +* Table of FPC rounding modes to test product rounding modes. +* +* The Set BFP Rounding Mode does allow specification of the FPC +* rounding mode as an address, so we shall index into a table of +* BFP rounding modes without bothering with Execute. +* +*********************************************************************** + SPACE 2 +* +* Rounding modes that may be set in the FPCR. The FPCR controls +* rounding of the product. +* +* These are indexed directly by the loop counter, which counts down. +* So the modes are listed in reverse order here. +* +FPCMODES DS 0C + DC AL1(7) RFS, Round for shorter precision + DC AL1(3) RM, Round to -infinity + DC AL1(2) RP, Round to +infinity + DC AL1(1) RZ, Round to zero + DC AL1(0) RNTE, Round to Nearest, ties to even +FPCMCT EQU *-FPCMODES Count of FPC Modes to be tested +* + EJECT +*********************************************************************** +* +* Short BFP test data sets for Multiply And Subtract testing. +* +* The first test data set is used for tests of basic functionality, +* NaN propagation, and results from operations involving other than +* finite numbers. The same set of eight values is used as the +* multiplicand, multiplier, and subtrahend, resulting in 8 x 8 x 8 or +* 512 test cases. +* +* The second test data set is used for testing boundary conditions +* using two finite non-zero values. Each possible condition code +* and type of result (normal, scaled, etc) is created by members of +* this test data set. +* +* The third test data set is used for exhaustive testing of final +* results across the five rounding modes available for the Multiply +* instruction. +* +* The strategy for predictable rounding mode testing is to use a +* multiplicand with some one-bits in the low-order byte and multiply +* that by 1/16 (0.0625). In BFP, this will have the effect of shifting +* the low-order byte out of the target precision representation and +* into the high-order portion of the bits that control rounding. The +* input low-order byte will be determined by the rounding desired. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* First input test data set, to test operations using non-finite or +* zero inputs. Member values chosen to validate Figure 19-24 on page +* 19-39 of SA22-7832-10. Each value in this table is used as the +* multiplicand, multiplier, and subtrahend. Eight entries menas 512 +* result sets. +* +*********************************************************************** + SPACE 2 +SBFPNFIN DS 0F Inputs for short BFP non-finite tests + DC X'FF800000' -inf + DC X'C0000000' -2.0 + DC X'80000000' -0 + DC X'00000000' +0 + DC X'40000000' +2.0 + DC X'7F800000' +inf + DC X'FFCB0000' -QNaN + DC X'7F8A0000' +SNaN +SBFPNFCT EQU (*-SBFPNFIN)/4 Count of short BFP in list + SPACE 3 +*********************************************************************** +* +* Second input test data set. These are finite triples intended to +* trigger overflow, underflow, and inexact exceptions. Each triple is +* added twice, once non-trappable and once trappable. Trappable +* overflow or underflow yields a scaled result. Trappable inexact +* will show whether the Incremented DXC code is returned. +* +* The following test cases are required: +* 1. Overflow +* 2. Underflow - normal inputs +* 3. Underflow - subnormal inputs +* 4. Normal - from subnormal inputs +* 5. Inexact - incremented +* 6. Inexact - truncated +* +*********************************************************************** + SPACE 2 +SBFPIN DS 0F Inputs for short BFP finite tests +* +* Overflow on multiplication two ways - once on the multiply, once +* on the addition following the multiplication. +* + DC X'7F7FFFFF' +Nmax multiplicand + DC X'FF7FFFFF' -Nmax multiplier + DC X'7F7FFFFF' Big positive value, won't show up. +* + DC X'7EFFFFFF' +Nmax / 2 multiplicand + DC X'C0000000' -2.0 multiplier + DC X'7F7FFFFF' +Nmax subtrahend, triggers overflow +* +* Underflow from product of normals. We will multiply two small +* normals to generate a subnormal, and then subtract a large subnormal. +* + DC X'00800000' +Nmin + DC X'00800000' +Nmin + DC X'00400001' large subnormal +* +* Underflow from the product of a subnormal and a normal. +* + DC X'3F000000' +0.5 + DC X'007FFFFF' +Dmax Subnormal + DC X'00000001' +Dmin, will appear in result +* +* We cannot generate a normal result from product of subnormals +* because the result will be smaller than both the multiplicand and the +* multiplier. So we'll try multiplying +Dmax by 2. The result should +* be +Nmin plus the subtrahend. +* + DC X'007FFFFF' +Dmax + DC X'40000000' +2.0 + DC X'00400000' +Dmax +* +* Multiply a value from 1.0 such that the added digits are to the right +* of the right-most bit in the stored significand. The result will be +* inexact, and incremented will be determined by the value of the +* bits in the multiplier. We will add 0.5 to this product because +* that value will not cause renormalization. Renormalization would +* shift the rounding bits one to the right, messing up the expected +* rounding. +* + DC X'3F80000C' Multiplicand 1.000001430511474609375 + DC X'BF880000' Multiplier -1.0625 (1 + 1/16) + DC X'3F000000' Minus 0.5 +*..nearest is away from zero, incremented. +* + DC X'3F800007' Multiplicand 1.00000083446502685546875 + DC X'BF880000' Multiplier -1.0625 (1 + 1/16) + DC X'3F000000' Minus 0.5 +*..nearest is toward zero, truncated +* +SBFPCT EQU (*-SBFPIN)/4/3 Count of short BFP in list + SPACE 3 +*********************************************************************** +* +* Third input test data set. These are finite triples intended to +* test all combinations of rounding mode for the product and the +* remainder. Values are chosen to create a requirement to round +* to the target precision after the computation and to generate +* varying results depending on the rounding mode in the FPCR. +* +* The result set will have cases that represent each of the following +* +* 1. Positive, nearest magnitude is toward zero. +* 2. Negative, nearest magnitude is toward zero. +* 3. Positive, nearest magnitude is away from zero. +* 4. Negative, nearest magnitude is away from zero. +* 5. Positive, tie, nearest even has greater magnitude +* 6. Negative, tie, nearest even has greater magnitude +* 7. Positive, tie, nearest even has lower magnitude +* 8. Negative, tie, nearest even has lower magnitude +* +* Round For Shorter precision correctness can be determined from the +* above test cases. +* +*********************************************************************** + SPACE 2 +SBFPINRM DS 0F Inputs for short BFP rounding testing +* +* Multiply a value from 1.0 such that the added digits are to the right +* of the right-most bit in the stored significand. The result will be +* inexact, and incremented will be determined by the value of the +* bits in the multiplier. +* + DC X'3F800007' Multiplicand +1.00000083446502685546875 + DC X'3F880000' Multiplier 1.0625 (1/16) + DC X'BF000000' Subtrahend -0.5 + DC X'BF800007' Multiplicand -1.00000083446502685546875 + DC X'3F880000' Multiplier 1.0625 (1/16) + DC X'3F000000' Subtrahend +0.5 +*..nearest is toward zero, truncated +* + DC X'3F80000C' Multiplicand +1.000001430511474609375 + DC X'3F880000' Multiplier 1.0625 (1/16) + DC X'BF000000' Subtrahend -0.5 + DC X'BF80000C' Multiplicand -1.000001430511474609375 + DC X'3F880000' Multiplier 1.0625 (1/16) + DC X'3F000000' Subtrahend +0.5 +*..nearest is away from zero, incremented. +* + DC X'3F800008' Multiplicand +1.000000476837158203125 + DC X'3F880000' Multiplier 1.0625 (1/16) + DC X'BF000000' Subtrahend -0.5 + DC X'BF800008' Multiplicand -1.000000476837158203125 + DC X'3F880000' Multiplier 1.0625 (1/16) + DC X'3F000000' Subtrahend +0.5 +*..nearest is a tie, nearest even has lower magnitude +* + DC X'3F800018' Multiplicand +1.000002384185791015625 + DC X'3F880000' Multiplier 1.0625 (1/16) + DC X'BF000000' Subtrahend -0.5 + DC X'BF800018' Multiplicand -1.000002384185791015625 + DC X'3F880000' Multiplier 1.0625 (1/16) + DC X'3F000000' Subtrahend +0.5 +*..nearest is a tie, nearest even has greater magnitude +* +SBFPRMCT EQU (*-SBFPINRM)/4/3 Count of short BFP rounding tests + EJECT +*********************************************************************** +* +* Long BFP test data sets for Multiply And Subtract testing. +* +* The first test data set is used for tests of basic functionality, +* NaN propagation, and results from operations involving other than +* finite numbers. +* +* The second test data set is used for testing boundary conditions +* using two finite non-zero values. Each possible condition code +* and type of result (normal, scaled, etc) is created by members of +* this test data set. +* +* The third test data set is used for exhaustive testing of final +* results across the five rounding modes available for the Add +* instruction. +* +* See the Short BFP test cases header for a discussion of test case +* selection for rounding mode test case values. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* First input test data set, to test operations using non-finite or +* zero inputs. Member values chosen to validate Figure 19-24 on page +* 19-39 of SA22-7832-10. Each value in this table is used as the +* multiplicand, multiplier, and subtrahend. Eight entries menas 512 +* result sets. +* +*********************************************************************** + SPACE 2 +LBFPNFIN DS 0F Inputs for long BFP testing + DC X'FFF0000000000000' -inf + DC X'C000000000000000' -2.0 + DC X'8000000000000000' -0 + DC X'0000000000000000' +0 + DC X'4000000000000000' +2.0 + DC X'7FF0000000000000' +inf + DC X'FFF8B00000000000' -QNaN + DC X'7FF0A00000000000' +SNaN +LBFPNFCT EQU (*-LBFPNFIN)/8 Count of long BFP in list + SPACE 3 +*********************************************************************** +* +* Second input test data set. These are finite triples intended to +* trigger overflow, underflow, and inexact exceptions. Each triples is +* added twice, once non-trappable and once trappable. Trappable +* overflow or underflow yields a scaled result. Trappable inexact +* will show whether the Incremented DXC code is returned. +* +* The following test cases are required: +* 1. Overflow +* 2. Underflow - normal inputs +* 3. Underflow - subnormal inputs +* 4. Normal - from subnormal inputs +* 5. Inexact - incremented +* 6. Inexact - truncated +* +*********************************************************************** + SPACE 2 +LBFPIN DS 0D Inputs for long BFP finite tests +* +* Overflow on multiplication two ways. Once on the muliplication step, +* and then a second time on the addition step. +* + DC X'7FEFFFFFFFFFFFFF' +Nmax + DC X'FFEFFFFFFFFFFFFF' -Nmax + DC X'3FF0000000000000' +1.0 +* + DC X'7FDFFFFFFFFFFFFF' +Nmax / 2 + DC X'C000000000000000' -2.0 + DC X'7FEFFFFFFFFFFFFF' +Nmax +* +* Underflow from product of normals. We will multiply two small +* normals to generate a subnormal, and then subtract a large subnormal. +* + DC X'0010000000000000' +Nmin + DC X'0010000000000000' +Nmin + DC X'0008000000000001' A very large subnormal +* +* Underflow from the product of a subnormal and a normal. +* + DC X'3FE0000000000000' +0.5 + DC X'000FFFFFFFFFFFFF' +Dmax subnormal + DC X'0000000000000001' +Dmin, will appear in result +* +* We cannot generate a normal result from product of subnormals +* because the result will be smaller than both the multiplicand and the +* multiplier. So we'll try multiplying +Dmax by 2. The result should +* be +Nmin +* + DC X'000FFFFFFFFFFFFF' +Dmax + DC X'4000000000000000' +2.0, result should be normal + DC X'0008000000000000' A large subnormal +* +* Multiply a value from 1.0 such that the added digits are to the right +* of the right-most bit in the stored significand. The result will be +* inexact, and incremented will be determined by the value of the +* bits in the multiplier. +* + DC X'3FF000000000000C' Multiplicand +1, aka 1.0b0 + DC X'3FF1000000000000' Multiplier 1.0625 (1/16) + DC X'BFE0000000000000' -0.5 +*..nearest is away from zero, incremented. +* + DC X'3FF0000000000007' Multiplicand +1, aka 1.0b0 + DC X'3FF1000000000000' Multiplier 1.0625 (1/16) + DC X'BFE0000000000000' -0.5 +*..nearest is toward zero, truncated. +* +LBFPCT EQU (*-LBFPIN)/8/3 Count of long BFP triples in list + SPACE 3 +*********************************************************************** +* +* Third input test data set. These are finite triples intended to +* test all combinations of rounding mode for the product and the +* remainder. Values are chosen to create a requirement to round +* to the target precision after the computation and to generate +* varying results depending on the rounding mode in the FPCR. +* +* The result set will have cases that represent each of the following +* +* 1. Positive, nearest magnitude is toward zero. +* 2. Negative, nearest magnitude is toward zero. +* 3. Positive, nearest magnitude is away from zero. +* 4. Negative, nearest magnitude is away from zero. +* 5. Positive, tie, nearest even has greater magnitude +* 6. Negative, tie, nearest even has greater magnitude +* 7. Positive, tie, nearest even has lower magnitude +* 8. Negative, tie, nearest even has lower magnitude +* +* Round For Shorter precision correctness can be determined from the +* above test cases. +* +*********************************************************************** + SPACE 2 +LBFPINRM DS 0F +* +* Multiply a value from 1.0 such that the added digits are to the right +* of the right-most bit in the stored significand. The result will be +* inexact, and incremented will be determined by the value of the +* bits in the multiplier. +* + DC X'3FF0000000000007' Multiplicand + DC X'3FF1000000000000' Multiplier 1.0625 (1/16) + DC X'BFE0000000000000' -0.5 + DC X'BFF0000000000007' Multiplicand + DC X'3FF1000000000000' Multiplier 1.0625 (1/16) + DC X'3FE0000000000000' +0.5 +*..nearest is toward zero, truncated. +* + DC X'3FF000000000000C' Multiplicand + DC X'3FF1000000000000' Multiplier 1.0625 (1/16) + DC X'BFE0000000000000' -0.5 + DC X'BFF000000000000C' Multiplicand + DC X'3FF1000000000000' Multiplier 1.0625 (1/16) + DC X'3FE0000000000000' +0.5 +*..nearest is away from zero, incremented. +* + DC X'3FF0000000000008' Multiplicand + DC X'3FF1000000000000' Multiplier 1.0625 (1/16) + DC X'BFE0000000000000' -0.5 + DC X'BFF0000000000008' Multiplicand + DC X'3FF1000000000000' Multiplier 1.0625 (1/16) + DC X'3FE0000000000000' +0.5 +*..nearest is a tie, nearest even has lower magnitude +* + DC X'3FF0000000000018' Multiplicand +1, aka +1.0b0 + DC X'3FF1000000000000' Multiplier 1.0625 (1/16) + DC X'BFE0000000000000' -0.5 + DC X'BFF0000000000018' Multiplicand -1, aka -1.0b0 + DC X'3FF1000000000000' Multiplier 1.0625 (1/16) + DC X'3FE0000000000000' +0.5 +*..nearest is a tie, nearest even has greater magnitude +* +LBFPRMCT EQU (*-LBFPINRM)/8/3 Count of long BFP rounding tests + EJECT +* +* Locations for results +* +SBFPNFOT EQU STRTLABL+X'1000' Short non-finite BFP results +* ..room for 512 tests, 512 used +SBFPNFFL EQU STRTLABL+X'3000' FPCR flags and DXC from short BFP +* ..room for 512 tests, 512 used +* +SBFPOUT EQU STRTLABL+X'5000' Short BFP finite results +* ..room for 16 tests, 7 used +SBFPFLGS EQU STRTLABL+X'5100' FPCR flags and DXC from short BFP +* ..room for 16 tests, 7 used +* +SBFPRMO EQU STRTLABL+X'5200' Short BFP rounding mode test results +* ..Room for 16, 8 used. +SBFPRMOF EQU STRTLABL+X'5500' Short BFP rounding mode FPCR results +* ..Room for 16, 8 used. +* ..next location starts at X'5800' +* +LBFPNFOT EQU STRTLABL+X'6000' Long non-finite BFP results +* ..room for 512 tests, 512 used +LBFPNFFL EQU STRTLABL+X'A000' FPCR flags and DXC from long BFP +* ..room for 512 tests, 512 used +* +LBFPOUT EQU STRTLABL+X'C000' Long BFP finite results +* ..room for 16 tests, 7 used +LBFPFLGS EQU STRTLABL+X'C200' FPCR flags and DXC from long BFP +* ..room for 16 tests, 7 used +* +LBFPRMO EQU STRTLABL+X'C500' Long BFP rounding mode test results +* ..Room for 16, 8 used. +LBFPRMOF EQU STRTLABL+X'CA00' Long BFP rounding mode FPCR results +* ..Room for 16, 8 used. +* ..next location starts at X'CD00' +* +* +ENDLABL EQU STRTLABL+X'C800' + PADCSECT ENDLABL + END diff --git a/tests/bfp-022-multsub.core b/tests/bfp-022-multsub.core new file mode 100644 index 000000000..2f1aba624 Binary files /dev/null and b/tests/bfp-022-multsub.core differ diff --git a/tests/bfp-022-multsub.list b/tests/bfp-022-multsub.list new file mode 100644 index 000000000..86e1f091f --- /dev/null +++ b/tests/bfp-022-multsub.list @@ -0,0 +1,1333 @@ +ASMA Ver. 0.2.0 bfp-022-multsub.asm: Test IEEE Multiply And Subtract 09 Oct 2016 12:34:01 Page 1 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 2 *********************************************************************** + 3 * + 4 *Testcase IEEE MULTIPLY AND SUBTRACT + 5 * Test case capability includes IEEE exceptions trappable and + 6 * otherwise. Test results, FPCR flags, the Condition code, and any + 7 * DXC are saved for all tests. + 8 * + 9 * This test program is focused on the four fused Multiply And Subtract + 10 * instructions. Standard Multiply and Multiply to longer precision + 11 * are tested in other programs. + 12 * + 13 *********************************************************************** + + + 15 *********************************************************************** + 16 * + 17 * Tests the following three conversion instructions + 18 * MULTIPLY AND SUBTRACT (short BFP, RRE) + 19 * MULTIPLY AND SUBTRACT (long BFP, RRE) + 20 * MULTIPLY AND SUBTRACT (short BFP, RXE) + 21 * MULTIPLY AND SUBTRACT (long BFP, RXE) + 22 * + 23 * + 24 * Test data is compiled into this program. The test script that runs + 25 * this program can provide alternative test data through Hercules R + 26 * commands. + 27 * + 28 * Test Case Order + 29 * 1) Short BFP basic tests, including traps and NaN propagation + 30 * 2) Short BFP finite number tests, including traps and scaling + 31 * 3) Short BFP FPC-controlled rounding mode exhaustive tests + 32 * 4) Long BFP basic tests, including traps and NaN propagation + 33 * 5) Long BFP finite number tests, including traps and scaling + 34 * 6) Long BFP FPC-controlled rounding mode exhaustive tests + 35 * + 36 * Three input test sets are provided each for short and long BFP + 37 * inputs. Test values are the same for each precision for most + 38 * tests. Overflow and underflow each require precision- + 39 * dependent test values. + 40 * + 41 * Review of Softfloat code for multiply and add shows that the + 42 * multiplication and addition are performed in precision-independent + 43 * format. Overflow, underflow, inexact, and incremented are detected + 44 * upon conversion from precision-independent format to the target + 45 * format. As a result, it should not matter whether overflow etc is + 46 * caused by the multiplication or the addition. We will include + 47 * a few test cases where this differs in the finite testing section, + 48 * but that's all. + 49 * + 50 * Also tests the following floating point support instructions + 51 * LOAD (Short) + 52 * LOAD (Long) + ASMA Ver. 0.2.0 bfp-022-multsub.asm: Test IEEE Multiply And Subtract 09 Oct 2016 12:34:01 Page 2 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 53 * LFPC (Load Floating Point Control Register) + 54 * SRNMB (Set BFP Rounding Mode 3-bit) + 55 * STORE (Short) + 56 * STORE (Long) + 57 * STFPC (Store Floating Point Control Register) + 58 * + 59 *********************************************************************** + + + 61 MACRO + 62 PADCSECT &ENDLABL + 63 .* + 64 .* Macro to pad the CSECT to include result data areas if this test + 65 .* program is not being assembled using asma. asma generates a core + 66 .* image that is loaded by the loadcore command, and because the + 67 .* core image is a binary stored in Github, it makes sense to make + 68 .* this small effort to keep the core image small. + 69 .* + 70 AIF (D'&ENDLABL).GOODPAD + 71 MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + 72 MNOTE *,'No CSECT padding performed' + 73 MEXIT + 74 .* + 75 .GOODPAD ANOP Label valid. See if we're on asma + 76 AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + 77 ORG &ENDLABL-1 Not ASMA. Pad CSECT + 78 MEXIT + 79 .* + 80 .NOPAD ANOP + 81 MNOTE *,'asma detected; no CSECT padding performed' + 82 MEND + 83 * + 84 * Note: for compatibility with the z/CMS test rig, do not change + 85 * or use R11, R14, or R15. Everything else is fair game. + 86 * + 0000000000000000 00000000000008D7 87 BFPMULS START 0 + 0000000000000000 0000000000000001 88 STRTLABL EQU * + 0000000000000000 0000000000000001 89 R0 EQU 0 Work register for cc extraction + 0000000000000001 0000000000000001 90 R1 EQU 1 + 0000000000000002 0000000000000001 91 R2 EQU 2 Holds count of test input values + 0000000000000003 0000000000000001 92 R3 EQU 3 Points to next test input value(s) + 0000000000000004 0000000000000001 93 R4 EQU 4 Rounding tests inner loop control + 0000000000000005 0000000000000001 94 R5 EQU 5 Rounding tests outer loop control + 0000000000000006 0000000000000001 95 R6 EQU 6 Rounding tests top of inner loop + 0000000000000007 0000000000000001 96 R7 EQU 7 Pointer to next result value(s) + 0000000000000008 0000000000000001 97 R8 EQU 8 Pointer to next FPCR result + 0000000000000009 0000000000000001 98 R9 EQU 9 Rounding tests top of outer loop + 000000000000000A 0000000000000001 99 R10 EQU 10 Pointer to test address list + 000000000000000B 0000000000000001 100 R11 EQU 11 **Reserved for z/CMS test rig + 000000000000000C 0000000000000001 101 R12 EQU 12 Holds number of test cases in set + 000000000000000D 0000000000000001 102 R13 EQU 13 Mainline return address + 000000000000000E 0000000000000001 103 R14 EQU 14 **Return address for z/CMS test rig + ASMA Ver. 0.2.0 bfp-022-multsub.asm: Test IEEE Multiply And Subtract 09 Oct 2016 12:34:01 Page 3 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 000000000000000F 0000000000000001 104 R15 EQU 15 **Base register on z/CMS or Hyperion + 105 * + 106 * Floating Point Register equates to keep the cross reference clean + 107 * + 0000000000000000 0000000000000001 108 FPR0 EQU 0 + 0000000000000001 0000000000000001 109 FPR1 EQU 1 + 0000000000000002 0000000000000001 110 FPR2 EQU 2 + 0000000000000003 0000000000000001 111 FPR3 EQU 3 + 0000000000000004 0000000000000001 112 FPR4 EQU 4 + 0000000000000005 0000000000000001 113 FPR5 EQU 5 + 0000000000000006 0000000000000001 114 FPR6 EQU 6 + 0000000000000007 0000000000000001 115 FPR7 EQU 7 + 0000000000000008 0000000000000001 116 FPR8 EQU 8 + 0000000000000009 0000000000000001 117 FPR9 EQU 9 + 000000000000000A 0000000000000001 118 FPR10 EQU 10 + 000000000000000B 0000000000000001 119 FPR11 EQU 11 + 000000000000000C 0000000000000001 120 FPR12 EQU 12 + 000000000000000D 0000000000000001 121 FPR13 EQU 13 + 000000000000000E 0000000000000001 122 FPR14 EQU 14 + 000000000000000F 0000000000000001 123 FPR15 EQU 15 + 124 * +0000000000000000 0000000000000000 125 USING *,R15 + 126 * + 127 * Above works on real iron (R15=0 after sysclear) + 128 * and in z/CMS (R15 points to start of load module) + 129 * + + + 131 *********************************************************************** + 132 * + 133 * Low core definitions, Restart PSW, and Program Check Routine. + 134 * + 135 *********************************************************************** + + +0000000000000000 0000000000000000 000000000000008E 137 ORG STRTLABL+X'8E' Program check interrution code +000000000000008E 0000 138 PCINTCD DS H + 139 * + 0000000000000150 0000000000000001 140 PCOLDPSW EQU STRTLABL+X'150' z/Arch Program check old PSW + 141 * +0000000000000090 0000000000000090 00000000000001A0 142 ORG STRTLABL+X'1A0' z/Arch Restart PSW +00000000000001A0 00000001 80000000 143 DC X'0000000180000000',AD(START) + 144 * +00000000000001B0 00000000000001B0 00000000000001D0 145 ORG STRTLABL+X'1D0' z/Arch Program check old PSW +00000000000001D0 00000000 00000000 146 DC X'0000000000000000',AD(PROGCHK) + 147 * + 148 * Program check routine. If Data Exception, continue execution at + 149 * the instruction following the program check. Otherwise, hard wait. + 150 * No need to collect data. All interesting DXC stuff is captured + 151 * in the FPCR. + 152 * +00000000000001E0 00000000000001E0 0000000000000200 153 ORG STRTLABL+X'200' + ASMA Ver. 0.2.0 bfp-022-multsub.asm: Test IEEE Multiply And Subtract 09 Oct 2016 12:34:01 Page 4 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000200 154 PROGCHK DS 0H Program check occured... +0000000000000200 9507 F08F 000000000000008F 155 CLI PCINTCD+1,X'07' Data Exception? +0000000000000204 A774 0004 000000000000020C 156 JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) +0000000000000208 B2B2 F150 0000000000000150 157 LPSWE PCOLDPSW ..yes, resume program execution +000000000000020C 158 PCNOTDTA DS 0H +000000000000020C 12EE 159 LTR R14,R14 Return address provided? +000000000000020E 077E 160 BNZR R14 Yes, return to z/CMS test rig. +0000000000000210 B2B2 F268 0000000000000268 161 LPSWE HARDWAIT Not data exception, enter disabled wait + ASMA Ver. 0.2.0 bfp-022-multsub.asm: Test IEEE Multiply And Subtract 09 Oct 2016 12:34:01 Page 5 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 163 *********************************************************************** + 164 * + 165 * Main program. Enable Advanced Floating Point, process test cases. + 166 * + 167 *********************************************************************** + + +0000000000000214 169 START DS 0H +0000000000000214 B600 F278 0000000000000278 170 STCTL R0,R0,CTLR0 Store CR0 to enable AFP +0000000000000218 9604 F279 0000000000000279 171 OI CTLR0+1,X'04' Turn on AFP bit +000000000000021C B700 F278 0000000000000278 172 LCTL R0,R0,CTLR0 Reload updated CR0 + 173 * +0000000000000220 41A0 F300 0000000000000300 174 LA R10,SHORTNF Point to short BFP non-finite inputs +0000000000000224 4DD0 F360 0000000000000360 175 BAS R13,SBFPNF Multiply short BFP non-finites +0000000000000228 41A0 F310 0000000000000310 176 LA R10,SHORTF Point to short BFP finite inputs +000000000000022C 4DD0 F3F2 00000000000003F2 177 BAS R13,SBFPF Multiply short BFP finites +0000000000000230 41A0 F320 0000000000000320 178 LA R10,RMSHORTS Point to short BFP rounding mode tests +0000000000000234 4DD0 F46C 000000000000046C 179 BAS R13,SBFPRM Multiply short BFP for rounding tests + 180 * +0000000000000238 41A0 F330 0000000000000330 181 LA R10,LONGNF Point to long BFP non-finite inputs +000000000000023C 4DD0 F4DA 00000000000004DA 182 BAS R13,LBFPNF Multiply long BFP non-finites +0000000000000240 41A0 F340 0000000000000340 183 LA R10,LONGF Point to long BFP finite inputs +0000000000000244 4DD0 F56C 000000000000056C 184 BAS R13,LBFPF Multiply long BFP finites +0000000000000248 41A0 F350 0000000000000350 185 LA R10,RMLONGS Point to long BFP rounding mode tests +000000000000024C 4DD0 F5E6 00000000000005E6 186 BAS R13,LBFPRM Multiply long BFP for rounding tests + 187 * +0000000000000250 12EE 188 LTR R14,R14 Return address provided? +0000000000000252 077E 189 BNZR R14 ..Yes, return to z/CMS test rig. +0000000000000254 B2B2 F258 0000000000000258 190 LPSWE WAITPSW All done + 191 * +0000000000000258 192 DS 0D Ensure correct alignment for psw +0000000000000258 00020000 00000000 193 WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +0000000000000268 00020000 00000000 194 HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end + 195 * +0000000000000278 00000000 196 CTLR0 DS F +000000000000027C 00000000 197 FPCREGNT DC X'00000000' FPCR, trap all IEEE exceptions, zero flags +0000000000000280 F8000000 198 FPCREGTR DC X'F8000000' FPCR, trap no IEEE exceptions, zero flags + 199 * + 200 * Input values parameter list, four fullwords for each test data set + 201 * 1) Count, + 202 * 2) Address of inputs, + 203 * 3) Address to place results, and + 204 * 4) Address to place DXC/Flags/cc values. + 205 * +0000000000000284 0000000000000284 0000000000000300 206 ORG STRTLABL+X'300' Enable run-time replacement +0000000000000300 207 SHORTNF DS 0F Input pairs for short BFP non-finite tests +0000000000000300 00000008 208 DC A(SBFPNFCT) +0000000000000304 00000658 209 DC A(SBFPNFIN) +0000000000000308 00001000 210 DC A(SBFPNFOT) +000000000000030C 00003000 211 DC A(SBFPNFFL) + 212 * +0000000000000310 213 SHORTF DS 0F Input pairs for short BFP finite tests + ASMA Ver. 0.2.0 bfp-022-multsub.asm: Test IEEE Multiply And Subtract 09 Oct 2016 12:34:01 Page 6 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000310 00000007 214 DC A(SBFPCT) +0000000000000314 00000678 215 DC A(SBFPIN) +0000000000000318 00005000 216 DC A(SBFPOUT) +000000000000031C 00005100 217 DC A(SBFPFLGS) + 218 * +0000000000000320 219 RMSHORTS DS 0F Input pairs for short BFP rounding testing +0000000000000320 00000008 220 DC A(SBFPRMCT) +0000000000000324 000006CC 221 DC A(SBFPINRM) +0000000000000328 00005200 222 DC A(SBFPRMO) +000000000000032C 00005500 223 DC A(SBFPRMOF) + 224 * +0000000000000330 225 LONGNF DS 0F Input pairs for long BFP non-finite testing +0000000000000330 00000008 226 DC A(LBFPNFCT) +0000000000000334 0000072C 227 DC A(LBFPNFIN) +0000000000000338 00006000 228 DC A(LBFPNFOT) +000000000000033C 0000A000 229 DC A(LBFPNFFL) + 230 * +0000000000000340 231 LONGF DS 0F Input pairs for long BFP finite testing +0000000000000340 00000007 232 DC A(LBFPCT) +0000000000000344 00000770 233 DC A(LBFPIN) +0000000000000348 0000C000 234 DC A(LBFPOUT) +000000000000034C 0000C200 235 DC A(LBFPFLGS) + 236 * +0000000000000350 237 RMLONGS DS 0F Input pairs for long BFP rounding testing +0000000000000350 00000008 238 DC A(LBFPRMCT) +0000000000000354 00000818 239 DC A(LBFPINRM) +0000000000000358 0000C500 240 DC A(LBFPRMO) +000000000000035C 0000CA00 241 DC A(LBFPRMOF) + 242 * + ASMA Ver. 0.2.0 bfp-022-multsub.asm: Test IEEE Multiply And Subtract 09 Oct 2016 12:34:01 Page 7 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 244 *********************************************************************** + 245 * + 246 * Perform Multiply And Subtract using provided short BFP inputs. This + 247 * set of tests checks NaN propagation, operations on values that are + 248 * not finite numbers, and other basic tests. This set generates + 249 * results that can be validated against Figure 19-24 on page 19-39 of + 250 * SA22-7832-10. + 251 * + 252 * Four results are generated for each input: one RRE with all + 253 * exceptions non-trappable, a second RRE with all exceptions trappable, + 254 * a third RXE with all exceptions non-trappable, a fourth RXE with all + 255 * exceptions trappable. + 256 * + 257 * Because this is a three-operand instruction, validation against + 258 * Figure 19-24, effectively an 8 x 8 x 8 table, will generate a + 259 * phenomonal set of results. Namely 512 results of 16 bytes each + 260 * plus 512 FPCR contents of 16 bytes each. + 261 * + 262 * The product and FPCR are stored for each result. + 263 * + 264 *********************************************************************** + + +0000000000000360 266 SBFPNF DS 0H BFP Short non-finite values tests +0000000000000360 9823 A000 0000000000000000 267 LM R2,R3,0(R10) Get count and addr of multiplicand values +0000000000000364 9889 A008 0000000000000008 268 LM R8,R9,8(R10) Get address of result area and flag area. +0000000000000368 1222 269 LTR R2,R2 Any test cases? +000000000000036A 078D 270 BZR R13 ..No, return to caller + 271 * +000000000000036C 272 SBFPNFLP DS 0H Top of outer loop - Multiplicand +000000000000036C 9845 A000 0000000000000000 273 LM R4,R5,0(R10) Get count and start of multiplier values + 274 * ..which are the same as the multiplicands +0000000000000370 0DC0 275 BASR R12,0 Set top of middle loop + 276 * +0000000000000372 277 DS 0H Top of middle loop - multiplier +0000000000000372 9867 A000 0000000000000000 278 LM R6,R7,0(R10) Get count and start of subtrahend values + 279 * ..which are the same as the multiplicands +0000000000000376 0D10 280 BASR R1,0 Set top of inner loop - subtrahend + 281 * + 282 * Multiply and Add: R1 = R3 x R2 + R1 + 283 * +0000000000000378 7840 3000 0000000000000000 284 LE FPR4,0(,R3) Get short BFP multiplicand +000000000000037C 7810 5000 0000000000000000 285 LE FPR1,0(,R5) Get short BFP multiplier + 286 * +0000000000000380 B29D F27C 000000000000027C 287 LFPC FPCREGNT Set exceptions non-trappable +0000000000000384 7880 7000 0000000000000000 288 LE FPR8,0(,R7) Get short BFP subtrahend +0000000000000388 B30F 8041 289 MSEBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE +000000000000038C 7080 8000 0000000000000000 290 STE FPR8,0(,R8) Store short BFP product-difference +0000000000000390 B29C 9000 0000000000000000 291 STFPC 0(R9) Store resulting FPCR flags and DXC + 292 * +0000000000000394 B29D F280 0000000000000280 293 LFPC FPCREGTR Set exceptions trappable +0000000000000398 7880 7000 0000000000000000 294 LE FPR8,0(,R7) Get short BFP subtrahend + ASMA Ver. 0.2.0 bfp-022-multsub.asm: Test IEEE Multiply And Subtract 09 Oct 2016 12:34:01 Page 8 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +000000000000039C B30F 8041 295 MSEBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE +00000000000003A0 7080 8004 0000000000000004 296 STE FPR8,4(,R8) Store short BFP product-difference +00000000000003A4 B29C 9004 0000000000000004 297 STFPC 4(R9) Store resulting FPCR flags and DXC + 298 * +00000000000003A8 B29D F27C 000000000000027C 299 LFPC FPCREGNT Set exceptions non-trappable +00000000000003AC 7880 7000 0000000000000000 300 LE FPR8,0(,R7) Get short BFP subtrahend +00000000000003B0 ED40 5000 800F 0000000000000000 301 MSEB FPR8,FPR4,0(,R5) Mult. FPR4 by multiplier, add FPR8 RXE +00000000000003B6 7080 8008 0000000000000008 302 STE FPR8,8(,R8) Store short BFP product-difference +00000000000003BA B29C 9008 0000000000000008 303 STFPC 8(R9) Store resulting FPCR flags and DXC + 304 * +00000000000003BE B29D F280 0000000000000280 305 LFPC FPCREGTR Set exceptions trappable +00000000000003C2 7880 7000 0000000000000000 306 LE FPR8,0(,R7) Get short BFP subtrahend +00000000000003C6 ED40 5000 800F 0000000000000000 307 MSEB FPR8,FPR4,0(,R5) Mult. FPR4 by multiplier, add FPR8 RXE +00000000000003CC 7080 800C 000000000000000C 308 STE FPR8,12(,R8) Store short BFP product-difference +00000000000003D0 B29C 900C 000000000000000C 309 STFPC 12(R9) Store resulting FPCR flags and DXC + 310 * +00000000000003D4 4180 8010 0000000000000010 311 LA R8,4*4(,R8) Point to next product-diff. result area +00000000000003D8 4190 9010 0000000000000010 312 LA R9,4*4(,R9) Point to next FPCR contents area +00000000000003DC 4170 7004 0000000000000004 313 LA R7,4(,R7) Point to next subtrahend value +00000000000003E0 0661 314 BCTR R6,R1 Loop through subtrahend values + 315 * +00000000000003E2 4150 5004 0000000000000004 316 LA R5,4(,R5) Point to next multiplier +00000000000003E6 064C 317 BCTR R4,R12 Loop through multiplier values + 318 * +00000000000003E8 4130 3004 0000000000000004 319 LA R3,4(,R3) Point to next multiplicand +00000000000003EC 4620 F36C 000000000000036C 320 BCT R2,SBFPNFLP Loop through multiplicand values +00000000000003F0 07FD 321 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-022-multsub.asm: Test IEEE Multiply And Subtract 09 Oct 2016 12:34:01 Page 9 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 323 *********************************************************************** + 324 * + 325 * Perform Multiply And Subtract using provided short BFP input triples. + 326 * This set of tests triggers IEEE exceptions Overflow, Underflow, and + 327 * Inexact and collects both trap and non-trap results. + 328 * + 329 * Four results are generated for each input: one RRE with all + 330 * exceptions non-trappable, a second RRE with all exceptions trappable, + 331 * a third RXE with all exceptions non-trappable, a fourth RXE with all + 332 * exceptions trappable, + 333 * + 334 * The product and FPCR are stored for each result. + 335 * + 336 *********************************************************************** + + +00000000000003F2 9823 A000 0000000000000000 338 SBFPF LM R2,R3,0(R10) Get count and address of test input values +00000000000003F6 9878 A008 0000000000000008 339 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000003FA 1222 340 LTR R2,R2 Any test cases? +00000000000003FC 078D 341 BZR R13 ..No, return to caller +00000000000003FE 0DC0 342 BASR R12,0 Set top of loop + 343 * +0000000000000400 B29D F27C 000000000000027C 344 LFPC FPCREGNT Set exceptions non-trappable +0000000000000404 7840 3000 0000000000000000 345 LE FPR4,0(,R3) Get short BFP multiplicand +0000000000000408 7810 3004 0000000000000004 346 LE FPR1,1*4(,R3) Get short BFP multiplier +000000000000040C 7880 3008 0000000000000008 347 LE FPR8,2*4(,R3) Get short BFP subtrahend +0000000000000410 B30F 8041 348 MSEBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE +0000000000000414 7080 7000 0000000000000000 349 STE FPR8,0(,R7) Store short BFP product-difference +0000000000000418 B29C 8000 0000000000000000 350 STFPC 0(R8) Store resulting FPCR flags and DXC + 351 * +000000000000041C B29D F280 0000000000000280 352 LFPC FPCREGTR Set exceptions trappable +0000000000000420 7880 3008 0000000000000008 353 LE FPR8,2*4(,R3) Reload short BFP subtrahend + 354 * ..multiplier is still in FPR1, + 355 * ..multiplicand is still in FPR4 +0000000000000424 B30F 8041 356 MSEBR FPR8,FPR4,FPR1 Multiply short FPR8 by FPR1 RRE +0000000000000428 7080 7004 0000000000000004 357 STE FPR8,1*4(,R7) Store short BFP product-difference +000000000000042C B29C 8004 0000000000000004 358 STFPC 4(R8) Store resulting FPCR flags and DXC + 359 * +0000000000000430 B29D F27C 000000000000027C 360 LFPC FPCREGNT Set exceptions non-trappable +0000000000000434 7880 3008 0000000000000008 361 LE FPR8,2*4(,R3) Reload short BFP subtrahend + 362 * ..multiplicand is still in FPR4 +0000000000000438 ED40 3004 800F 0000000000000004 363 MSEB FPR8,FPR4,4(,R3) Mult. FPR4 by multiplier, add FPR8 RXE +000000000000043E 7080 7008 0000000000000008 364 STE FPR8,2*4(,R7) Store short BFP product +0000000000000442 B29C 8008 0000000000000008 365 STFPC 8(R8) Store resulting FPCR flags and DXC + 366 * +0000000000000446 B29D F280 0000000000000280 367 LFPC FPCREGTR Set exceptions trappable +000000000000044A 7880 3008 0000000000000008 368 LE FPR8,2*4(,R3) Reload short BFP subtrahend + 369 * ..multiplicand is still in FPR4 +000000000000044E ED40 3004 800F 0000000000000004 370 MSEB FPR8,FPR4,4(,R3) Mult. FPR4 by multiplier, add FPR8 RXE +0000000000000454 7080 700C 000000000000000C 371 STE FPR8,3*4(,R7) Store short BFP product +0000000000000458 B29C 800C 000000000000000C 372 STFPC 12(R8) Store resulting FPCR flags and DXC + 373 * + ASMA Ver. 0.2.0 bfp-022-multsub.asm: Test IEEE Multiply And Subtract 09 Oct 2016 12:34:01 Page 10 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +000000000000045C 4130 300C 000000000000000C 374 LA R3,3*4(,R3) Point to next input value trible +0000000000000460 4170 7010 0000000000000010 375 LA R7,4*4(,R7) Point to next product result set +0000000000000464 4180 8010 0000000000000010 376 LA R8,4*4(,R8) Point to next FPCR result set +0000000000000468 062C 377 BCTR R2,R12 Convert next input value. +000000000000046A 07FD 378 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-022-multsub.asm: Test IEEE Multiply And Subtract 09 Oct 2016 12:34:01 Page 11 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 380 *********************************************************************** + 381 * + 382 * Perform Multiply And Subtract using provided short BFP input triples. + 383 * This set of tests exhaustively tests all rounding modes available for + 384 * Multiply And Subtract. The rounding mode can only be specified in + 385 * the FPC. + 386 * + 387 * All five FPC rounding modes are tested because the preceeding tests, + 388 * using rounding mode RNTE, do not often create results that require + 389 * rounding. + 390 * + 391 * Two results are generated for each input and rounding mode: one RRE + 392 * and one RXE. Traps are disabled for all rounding mode tests. + 393 * + 394 * The product and FPCR are stored for each test. + 395 * + 396 *********************************************************************** + + +000000000000046C 9823 A000 0000000000000000 398 SBFPRM LM R2,R3,0(R10) Get count and address of test input values +0000000000000470 9878 A008 0000000000000008 399 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000474 1222 400 LTR R2,R2 Any test cases? +0000000000000476 078D 401 BZR R13 ..No, return to caller +0000000000000478 1711 402 XR R1,R1 Zero register 1 for use in IC/STC/indexing +000000000000047A 0DC0 403 BASR R12,0 Set top of test case loop + 404 +000000000000047C 4150 0005 0000000000000005 405 LA R5,FPCMCT Get count of FPC modes to be tested +0000000000000480 0D90 406 BASR R9,0 Set top of rounding mode outer loop + 407 * +0000000000000482 4315 F64F 000000000000064F 408 IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode + 409 * +0000000000000486 B29D F27C 000000000000027C 410 LFPC FPCREGNT Set exceptions non-trappable, clear flags +000000000000048A B2B8 1000 0000000000000000 411 SRNMB 0(R1) Set FPC Rounding Mode +000000000000048E 7840 3000 0000000000000000 412 LE FPR4,0(,R3) Get short BFP multiplicand +0000000000000492 7810 3004 0000000000000004 413 LE FPR1,4(,R3) Get short BFP multiplier +0000000000000496 7880 3008 0000000000000008 414 LE FPR8,8(,R3) Get short BFP subtrahend +000000000000049A B30F 8041 415 MSEBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE +000000000000049E 7080 7000 0000000000000000 416 STE FPR8,0(,R7) Store short BFP product-difference +00000000000004A2 B29C 8000 0000000000000000 417 STFPC 0(R8) Store resulting FPCR flags and DXC + 418 * +00000000000004A6 B29D F27C 000000000000027C 419 LFPC FPCREGNT Set exceptions non-trappable, clear flags +00000000000004AA B2B8 1000 0000000000000000 420 SRNMB 0(R1) Set FPC Rounding Mode +00000000000004AE 7880 3008 0000000000000008 421 LE FPR8,8(,R3) Get short BFP subtrahend + 422 * ..multiplicand is still in FPR4 +00000000000004B2 ED40 3004 800F 0000000000000004 423 MSEB FPR8,FPR4,4(,R3) Mult. FPR4 by multiplier, add FPR8 RXE +00000000000004B8 7080 7004 0000000000000004 424 STE FPR8,4(,R7) Store short BFP product-difference +00000000000004BC B29C 8004 0000000000000004 425 STFPC 4(R8) Store resulting FPCR flags and DXC + 426 * +00000000000004C0 4170 7008 0000000000000008 427 LA R7,2*4(,R7) Point to next product result set +00000000000004C4 4180 8008 0000000000000008 428 LA R8,2*4(,R8) Point to next FPCR result area + 429 * +00000000000004C8 0659 430 BCTR R5,R9 Iterate to next FPC mode for this input + ASMA Ver. 0.2.0 bfp-022-multsub.asm: Test IEEE Multiply And Subtract 09 Oct 2016 12:34:01 Page 12 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 431 * + 432 * End of FPC modes to be tested. Advance to next test case. We will + 433 * skip eight bytes of result area so that each set of five result + 434 * value pairs starts at a memory address ending in zero for the + 435 * convenience of memory dump review. + 436 * +00000000000004CA 4130 300C 000000000000000C 437 LA R3,3*4(,R3) Point to next input value pair triple +00000000000004CE 4170 7008 0000000000000008 438 LA R7,8(,R7) Skip to start of next result set +00000000000004D2 4180 8008 0000000000000008 439 LA R8,8(,R8) Skip to start of next FPCR result set +00000000000004D6 062C 440 BCTR R2,R12 Advance to the next input pair + 441 * +00000000000004D8 07FD 442 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-022-multsub.asm: Test IEEE Multiply And Subtract 09 Oct 2016 12:34:01 Page 13 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 444 *********************************************************************** + 445 * + 446 * Perform Multiply And Subtract using provided long BFP inputs. This + 447 * set of tests checks NaN propagation, operations on values that are + 448 * not finite numbers, and other basic tests. This set generates + 449 * results that can be validated against Figure 19-24 on page 19-39 of + 450 * SA22-7832-10. + 451 * + 452 * Four results are generated for each input: one RRE with all + 453 * exceptions non-trappable, a second RRE with all exceptions trappable, + 454 * a third RXE with all exceptions non-trappable, a fourth RXE with all + 455 * exceptions trappable. + 456 * + 457 * Because this is a three-operand instruction, validation against + 458 * Figure 19-24, effectively an 8 x 8 x 8 table, will generate a + 459 * phenomonal set of results. Namely 512 results of 32 bytes each + 460 * plus 512 FPCR contents of 16 bytes each. + 461 * + 462 * The product and FPCR are stored for each result. + 463 * + 464 *********************************************************************** + + +00000000000004DA 466 LBFPNF DS 0H BFP long non-finite values tests +00000000000004DA 9823 A000 0000000000000000 467 LM R2,R3,0(R10) Get count and addr of multiplicand values +00000000000004DE 9889 A008 0000000000000008 468 LM R8,R9,8(R10) Get address of result area and flag area. +00000000000004E2 1222 469 LTR R2,R2 Any test cases? +00000000000004E4 078D 470 BZR R13 ..No, return to caller + 471 * +00000000000004E6 472 LBFPNFLP DS 0H Top of outer loop - Multiplicand +00000000000004E6 9845 A000 0000000000000000 473 LM R4,R5,0(R10) Get count and start of multiplier values + 474 * ..which are the same as the multiplicands +00000000000004EA 0DC0 475 BASR R12,0 Set top of middle loop + 476 * +00000000000004EC 477 DS 0H Top of middle loop - multiplier +00000000000004EC 9867 A000 0000000000000000 478 LM R6,R7,0(R10) Get count and start of subtrahend values + 479 * ..which are the same as the multiplicands +00000000000004F0 0D10 480 BASR R1,0 Set top of inner loop - subtrahend + 481 * + 482 * Multiply and Add: R1 = R3 x R2 + R1 + 483 * +00000000000004F2 7840 3000 0000000000000000 484 LE FPR4,0(,R3) Get long BFP multiplicand +00000000000004F6 7810 5000 0000000000000000 485 LE FPR1,0(,R5) Get long BFP multiplier + 486 * +00000000000004FA B29D F27C 000000000000027C 487 LFPC FPCREGNT Set exceptions non-trappable +00000000000004FE 6880 7000 0000000000000000 488 LD FPR8,0(,R7) Get long BFP subtrahend +0000000000000502 B31F 8041 489 MSDBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE +0000000000000506 6080 8000 0000000000000000 490 STD FPR8,0(,R8) Store long BFP product-difference +000000000000050A B29C 9000 0000000000000000 491 STFPC 0(R9) Store resulting FPCR flags and DXC + 492 * +000000000000050E B29D F280 0000000000000280 493 LFPC FPCREGTR Set exceptions trappable +0000000000000512 7880 7000 0000000000000000 494 LE FPR8,0(,R7) Get long BFP subtrahend + ASMA Ver. 0.2.0 bfp-022-multsub.asm: Test IEEE Multiply And Subtract 09 Oct 2016 12:34:01 Page 14 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000516 B31F 8041 495 MSDBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE +000000000000051A 6080 8008 0000000000000008 496 STD FPR8,1*8(,R8) Store long BFP product-difference +000000000000051E B29C 9004 0000000000000004 497 STFPC 1*4(R9) Store resulting FPCR flags and DXC + 498 * +0000000000000522 B29D F27C 000000000000027C 499 LFPC FPCREGNT Set exceptions non-trappable +0000000000000526 7880 7000 0000000000000000 500 LE FPR8,0(,R7) Get long BFP subtrahend +000000000000052A ED40 5000 801F 0000000000000000 501 MSDB FPR8,FPR4,0(,R5) Mult. FPR4 by multiplier, add FPR8 RXE +0000000000000530 6080 8010 0000000000000010 502 STD FPR8,2*8(,R8) Store long BFP product-difference +0000000000000534 B29C 9008 0000000000000008 503 STFPC 2*4(R9) Store resulting FPCR flags and DXC + 504 * +0000000000000538 B29D F280 0000000000000280 505 LFPC FPCREGTR Set exceptions trappable +000000000000053C 7880 7000 0000000000000000 506 LE FPR8,0(,R7) Get long BFP subtrahend +0000000000000540 ED40 5000 801F 0000000000000000 507 MSDB FPR8,FPR4,0(,R5) Mult. FPR4 by multiplier, add FPR8 RXE +0000000000000546 6080 8018 0000000000000018 508 STD FPR8,3*8(,R8) Store long BFP product-difference +000000000000054A B29C 900C 000000000000000C 509 STFPC 3*4(R9) Store resulting FPCR flags and DXC + 510 * +000000000000054E 4180 8020 0000000000000020 511 LA R8,4*8(,R8) Point to next product-diff. result area +0000000000000552 4190 9010 0000000000000010 512 LA R9,4*4(,R9) Point to next FPCR contents area +0000000000000556 4170 7008 0000000000000008 513 LA R7,8(,R7) Point to next subtrahend value +000000000000055A 0661 514 BCTR R6,R1 Loop through subtrahend values + 515 * +000000000000055C 4150 5008 0000000000000008 516 LA R5,8(,R5) Point to next multiplier +0000000000000560 064C 517 BCTR R4,R12 Loop through multiplier values + 518 * +0000000000000562 4130 3008 0000000000000008 519 LA R3,8(,R3) Point to next multiplicand +0000000000000566 4620 F4E6 00000000000004E6 520 BCT R2,LBFPNFLP Loop through multiplicand values +000000000000056A 07FD 521 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-022-multsub.asm: Test IEEE Multiply And Subtract 09 Oct 2016 12:34:01 Page 15 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 523 *********************************************************************** + 524 * + 525 * Perform Multiply And Subtract using provided long BFP input triples. + 526 * This set of tests triggers IEEE exceptions Overflow, Underflow, and + 527 * Inexact and collects non-trap and trap results. + 528 * + 529 * Four results are generated for each input: one RRE with all + 530 * exceptions non-trappable, a second RRE with all exceptions trappable, + 531 * a third RXE with all exceptions non-trappable, a fourth RXE with all + 532 * exceptions trappable, + 533 * + 534 * The product and FPCR are stored for each result. + 535 * + 536 *********************************************************************** + + +000000000000056C 9823 A000 0000000000000000 538 LBFPF LM R2,R3,0(R10) Get count and address of test input values +0000000000000570 9878 A008 0000000000000008 539 LM R7,R8,8(R10) Get address of result area and flag area. +0000000000000574 1222 540 LTR R2,R2 Any test cases? +0000000000000576 078D 541 BZR R13 ..No, return to caller +0000000000000578 0DC0 542 BASR R12,0 Set top of loop + 543 * +000000000000057A B29D F27C 000000000000027C 544 LFPC FPCREGNT Set exceptions non-trappable +000000000000057E 6840 3000 0000000000000000 545 LD FPR4,0(,R3) Get long BFP multiplicand +0000000000000582 6810 3008 0000000000000008 546 LD FPR1,8(,R3) Get long BFP multiplier +0000000000000586 6880 3010 0000000000000010 547 LD FPR8,16(,R3) Get long BFP subtrahend +000000000000058A B31F 8041 548 MSDBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE +000000000000058E 6080 7000 0000000000000000 549 STD FPR8,0(,R7) Store long BFP product +0000000000000592 B29C 8000 0000000000000000 550 STFPC 0(R8) Store resulting FPCR flags and DXC + 551 * +0000000000000596 B29D F280 0000000000000280 552 LFPC FPCREGTR Set exceptions trappable +000000000000059A 6880 3010 0000000000000010 553 LD FPR8,16(,R3) Reload long BFP subtrahend + 554 * ..multiplier is still in FPR1, + 555 * ..multiplicand is still in FFR4 +000000000000059E B31F 8041 556 MSDBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE +00000000000005A2 6080 7008 0000000000000008 557 STD FPR8,8(,R7) Store long BFP product-difference +00000000000005A6 B29C 8004 0000000000000004 558 STFPC 1*4(R8) Store resulting FPCR flags and DXC + 559 * +00000000000005AA B29D F27C 000000000000027C 560 LFPC FPCREGNT Set exceptions non-trappable +00000000000005AE 6880 3010 0000000000000010 561 LD FPR8,16(,R3) Reload long BFP subtrahend + 562 * ..multiplicand is still in FFR4 +00000000000005B2 ED40 3008 801F 0000000000000008 563 MSDB FPR8,FPR4,8(,R3) Mult. FPR4 by multiplier, add FPR8 RXE +00000000000005B8 6080 7010 0000000000000010 564 STD FPR8,2*8(,R7) Store long BFP product-difference +00000000000005BC B29C 8008 0000000000000008 565 STFPC 2*4(R8) Store resulting FPCR flags and DXC + 566 * +00000000000005C0 B29D F280 0000000000000280 567 LFPC FPCREGTR Set exceptions trappable +00000000000005C4 6880 3010 0000000000000010 568 LD FPR8,16(,R3) Reload long BFP subtrahend + 569 * ..multiplicand is still in FFR4 +00000000000005C8 ED40 3008 801F 0000000000000008 570 MSDB FPR8,FPR4,8(,R3) Mult. FPR4 by multiplier, add FPR8 RXE +00000000000005CE 6080 7018 0000000000000018 571 STD FPR8,3*8(,R7) Store long BFP product-difference +00000000000005D2 B29C 800C 000000000000000C 572 STFPC 3*4(R8) Store resulting FPCR flags and DXC + 573 * + ASMA Ver. 0.2.0 bfp-022-multsub.asm: Test IEEE Multiply And Subtract 09 Oct 2016 12:34:01 Page 16 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000005D6 4130 3018 0000000000000018 574 LA R3,3*8(,R3) Point to next input value triple +00000000000005DA 4170 7020 0000000000000020 575 LA R7,4*8(,R7) Point to next product-diff. result set +00000000000005DE 4180 8010 0000000000000010 576 LA R8,4*4(,R8) Point to next FPCR result area +00000000000005E2 062C 577 BCTR R2,R12 Convert next input value. +00000000000005E4 07FD 578 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-022-multsub.asm: Test IEEE Multiply And Subtract 09 Oct 2016 12:34:01 Page 17 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 580 *********************************************************************** + 581 * + 582 * Perform Multiply using provided long BFP input pairs. This set of + 583 * tests exhaustively tests all rounding modes available for Multiply. + 584 * The rounding mode can only be specified in the FPC. + 585 * + 586 * All five FPC rounding modes are tested because the preceeding tests, + 587 * using rounding mode RNTE, do not often create results that require + 588 * rounding. + 589 * + 590 * Two results are generated for each input and rounding mode: one RRE + 591 * and one RXE. Traps are disabled for all rounding mode tests. + 592 * + 593 * The product and FPCR are stored for each result. + 594 * + 595 *********************************************************************** + + +00000000000005E6 9823 A000 0000000000000000 597 LBFPRM LM R2,R3,0(R10) Get count and address of test input values +00000000000005EA 9878 A008 0000000000000008 598 LM R7,R8,8(R10) Get address of result area and flag area. +00000000000005EE 1222 599 LTR R2,R2 Any test cases? +00000000000005F0 078D 600 BZR R13 ..No, return to caller +00000000000005F2 1711 601 XR R1,R1 Zero register 1 for use in IC/STC/indexing +00000000000005F4 0DC0 602 BASR R12,0 Set top of test case loop + 603 +00000000000005F6 4150 0005 0000000000000005 604 LA R5,FPCMCT Get count of FPC modes to be tested +00000000000005FA 0D90 605 BASR R9,0 Set top of rounding mode loop + 606 * +00000000000005FC 4315 F64F 000000000000064F 607 IC R1,FPCMODES-L'FPCMODES(R5) Get next FPC mode + 608 * +0000000000000600 B29D F27C 000000000000027C 609 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000604 B2B8 1000 0000000000000000 610 SRNMB 0(R1) Set FPC Rounding Mode +0000000000000608 6840 3000 0000000000000000 611 LD FPR4,0(,R3) Get long BFP multiplicand +000000000000060C 6810 3008 0000000000000008 612 LD FPR1,8(,R3) Get long BFP multiplier +0000000000000610 6880 3010 0000000000000010 613 LD FPR8,16(,R3) Get long BFP subtrahend +0000000000000614 B31F 8041 614 MSDBR FPR8,FPR4,FPR1 Multiply FPR4 by FPR1, add FPR8 RRE +0000000000000618 6080 7000 0000000000000000 615 STD FPR8,0(,R7) Store long BFP product-difference +000000000000061C B29C 8000 0000000000000000 616 STFPC 0(R8) Store resulting FPCR flags and DXC + 617 * +0000000000000620 B29D F27C 000000000000027C 618 LFPC FPCREGNT Set exceptions non-trappable, clear flags +0000000000000624 B2B8 1000 0000000000000000 619 SRNMB 0(R1) Set FPC Rounding Mode +0000000000000628 6880 3010 0000000000000010 620 LD FPR8,16(,R3) Reload long BFP subtrahend +000000000000062C ED40 3008 801F 0000000000000008 621 MSDB FPR8,FPR4,8(,R3) Multiply long FPR8 by multiplier RXE +0000000000000632 6080 7008 0000000000000008 622 STD FPR8,8(,R7) Store long BFP product-difference +0000000000000636 B29C 8004 0000000000000004 623 STFPC 4(R8) Store resulting FPCR flags and DXC + 624 * +000000000000063A 4170 7010 0000000000000010 625 LA R7,2*8(,R7) Point to next product result set +000000000000063E 4180 8008 0000000000000008 626 LA R8,2*4(,R8) Point to next FPCR result area + 627 * +0000000000000642 0659 628 BCTR R5,R9 Iterate to next FPC mode + 629 * + 630 * End of FPC modes to be tested. Advance to next test case. We will + ASMA Ver. 0.2.0 bfp-022-multsub.asm: Test IEEE Multiply And Subtract 09 Oct 2016 12:34:01 Page 18 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 631 * skip eight bytes of FPCR result area so that each set of five result + 632 * FPCR contents pairs starts at a memory address ending in zero for the + 633 * convenience of memory dump review. + 634 * +0000000000000644 4130 3018 0000000000000018 635 LA R3,3*8(,R3) Point to next input value triple +0000000000000648 4180 8008 0000000000000008 636 LA R8,8(,R8) Skip to start of next FPCR result area +000000000000064C 062C 637 BCTR R2,R12 Multiply next input value lots of times + 638 * +000000000000064E 07FD 639 BR R13 All converted; return. + ASMA Ver. 0.2.0 bfp-022-multsub.asm: Test IEEE Multiply And Subtract 09 Oct 2016 12:34:01 Page 19 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 641 *********************************************************************** + 642 * + 643 * Table of FPC rounding modes to test product rounding modes. + 644 * + 645 * The Set BFP Rounding Mode does allow specification of the FPC + 646 * rounding mode as an address, so we shall index into a table of + 647 * BFP rounding modes without bothering with Execute. + 648 * + 649 *********************************************************************** + + + 651 * + 652 * Rounding modes that may be set in the FPCR. The FPCR controls + 653 * rounding of the product. + 654 * + 655 * These are indexed directly by the loop counter, which counts down. + 656 * So the modes are listed in reverse order here. + 657 * +0000000000000650 658 FPCMODES DS 0C +0000000000000650 07 659 DC AL1(7) RFS, Round for shorter precision +0000000000000651 03 660 DC AL1(3) RM, Round to -infinity +0000000000000652 02 661 DC AL1(2) RP, Round to +infinity +0000000000000653 01 662 DC AL1(1) RZ, Round to zero +0000000000000654 00 663 DC AL1(0) RNTE, Round to Nearest, ties to even + 0000000000000005 0000000000000001 664 FPCMCT EQU *-FPCMODES Count of FPC Modes to be tested + 665 * + ASMA Ver. 0.2.0 bfp-022-multsub.asm: Test IEEE Multiply And Subtract 09 Oct 2016 12:34:01 Page 20 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 667 *********************************************************************** + 668 * + 669 * Short BFP test data sets for Multiply And Subtract testing. + 670 * + 671 * The first test data set is used for tests of basic functionality, + 672 * NaN propagation, and results from operations involving other than + 673 * finite numbers. The same set of eight values is used as the + 674 * multiplicand, multiplier, and subtrahend, resulting in 8 x 8 x 8 or + 675 * 512 test cases. + 676 * + 677 * The second test data set is used for testing boundary conditions + 678 * using two finite non-zero values. Each possible condition code + 679 * and type of result (normal, scaled, etc) is created by members of + 680 * this test data set. + 681 * + 682 * The third test data set is used for exhaustive testing of final + 683 * results across the five rounding modes available for the Multiply + 684 * instruction. + 685 * + 686 * The strategy for predictable rounding mode testing is to use a + 687 * multiplicand with some one-bits in the low-order byte and multiply + 688 * that by 1/16 (0.0625). In BFP, this will have the effect of shifting + 689 * the low-order byte out of the target precision representation and + 690 * into the high-order portion of the bits that control rounding. The + 691 * input low-order byte will be determined by the rounding desired. + 692 * + 693 *********************************************************************** + + + 695 *********************************************************************** + 696 * + 697 * First input test data set, to test operations using non-finite or + 698 * zero inputs. Member values chosen to validate Figure 19-24 on page + 699 * 19-39 of SA22-7832-10. Each value in this table is used as the + 700 * multiplicand, multiplier, and subtrahend. Eight entries menas 512 + 701 * result sets. + 702 * + 703 *********************************************************************** + + +0000000000000658 705 SBFPNFIN DS 0F Inputs for short BFP non-finite tests +0000000000000658 FF800000 706 DC X'FF800000' -inf +000000000000065C C0000000 707 DC X'C0000000' -2.0 +0000000000000660 80000000 708 DC X'80000000' -0 +0000000000000664 00000000 709 DC X'00000000' +0 +0000000000000668 40000000 710 DC X'40000000' +2.0 +000000000000066C 7F800000 711 DC X'7F800000' +inf +0000000000000670 FFCB0000 712 DC X'FFCB0000' -QNaN +0000000000000674 7F8A0000 713 DC X'7F8A0000' +SNaN + 0000000000000008 0000000000000001 714 SBFPNFCT EQU (*-SBFPNFIN)/4 Count of short BFP in list + ASMA Ver. 0.2.0 bfp-022-multsub.asm: Test IEEE Multiply And Subtract 09 Oct 2016 12:34:01 Page 21 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 716 *********************************************************************** + 717 * + 718 * Second input test data set. These are finite triples intended to + 719 * trigger overflow, underflow, and inexact exceptions. Each triple is + 720 * added twice, once non-trappable and once trappable. Trappable + 721 * overflow or underflow yields a scaled result. Trappable inexact + 722 * will show whether the Incremented DXC code is returned. + 723 * + 724 * The following test cases are required: + 725 * 1. Overflow + 726 * 2. Underflow - normal inputs + 727 * 3. Underflow - subnormal inputs + 728 * 4. Normal - from subnormal inputs + 729 * 5. Inexact - incremented + 730 * 6. Inexact - truncated + 731 * + 732 *********************************************************************** + + +0000000000000678 734 SBFPIN DS 0F Inputs for short BFP finite tests + 735 * + 736 * Overflow on multiplication two ways - once on the multiply, once + 737 * on the addition following the multiplication. + 738 * +0000000000000678 7F7FFFFF 739 DC X'7F7FFFFF' +Nmax multiplicand +000000000000067C FF7FFFFF 740 DC X'FF7FFFFF' -Nmax multiplier +0000000000000680 7F7FFFFF 741 DC X'7F7FFFFF' Big positive value, won't show up. + 742 * +0000000000000684 7EFFFFFF 743 DC X'7EFFFFFF' +Nmax / 2 multiplicand +0000000000000688 C0000000 744 DC X'C0000000' -2.0 multiplier +000000000000068C 7F7FFFFF 745 DC X'7F7FFFFF' +Nmax subtrahend, triggers overflow + 746 * + 747 * Underflow from product of normals. We will multiply two small + 748 * normals to generate a subnormal, and then subtract a large subnormal. + 749 * +0000000000000690 00800000 750 DC X'00800000' +Nmin +0000000000000694 00800000 751 DC X'00800000' +Nmin +0000000000000698 00400001 752 DC X'00400001' large subnormal + 753 * + 754 * Underflow from the product of a subnormal and a normal. + 755 * +000000000000069C 3F000000 756 DC X'3F000000' +0.5 +00000000000006A0 007FFFFF 757 DC X'007FFFFF' +Dmax Subnormal +00000000000006A4 00000001 758 DC X'00000001' +Dmin, will appear in result + 759 * + 760 * We cannot generate a normal result from product of subnormals + 761 * because the result will be smaller than both the multiplicand and the + 762 * multiplier. So we'll try multiplying +Dmax by 2. The result should + 763 * be +Nmin plus the subtrahend. + 764 * +00000000000006A8 007FFFFF 765 DC X'007FFFFF' +Dmax +00000000000006AC 40000000 766 DC X'40000000' +2.0 + ASMA Ver. 0.2.0 bfp-022-multsub.asm: Test IEEE Multiply And Subtract 09 Oct 2016 12:34:01 Page 22 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000006B0 00400000 767 DC X'00400000' +Dmax + 768 * + 769 * Multiply a value from 1.0 such that the added digits are to the right + 770 * of the right-most bit in the stored significand. The result will be + 771 * inexact, and incremented will be determined by the value of the + 772 * bits in the multiplier. We will add 0.5 to this product because + 773 * that value will not cause renormalization. Renormalization would + 774 * shift the rounding bits one to the right, messing up the expected + 775 * rounding. + 776 * +00000000000006B4 3F80000C 777 DC X'3F80000C' Multiplicand 1.000001430511474609375 +00000000000006B8 BF880000 778 DC X'BF880000' Multiplier -1.0625 (1 + 1/16) +00000000000006BC 3F000000 779 DC X'3F000000' Minus 0.5 + 780 *..nearest is away from zero, incremented. + 781 * +00000000000006C0 3F800007 782 DC X'3F800007' Multiplicand 1.00000083446502685546875 +00000000000006C4 BF880000 783 DC X'BF880000' Multiplier -1.0625 (1 + 1/16) +00000000000006C8 3F000000 784 DC X'3F000000' Minus 0.5 + 785 *..nearest is toward zero, truncated + 786 * + 0000000000000007 0000000000000001 787 SBFPCT EQU (*-SBFPIN)/4/3 Count of short BFP in list + + + + 789 *********************************************************************** + 790 * + 791 * Third input test data set. These are finite triples intended to + 792 * test all combinations of rounding mode for the product and the + 793 * remainder. Values are chosen to create a requirement to round + 794 * to the target precision after the computation and to generate + 795 * varying results depending on the rounding mode in the FPCR. + 796 * + 797 * The result set will have cases that represent each of the following + 798 * + 799 * 1. Positive, nearest magnitude is toward zero. + 800 * 2. Negative, nearest magnitude is toward zero. + 801 * 3. Positive, nearest magnitude is away from zero. + 802 * 4. Negative, nearest magnitude is away from zero. + 803 * 5. Positive, tie, nearest even has greater magnitude + 804 * 6. Negative, tie, nearest even has greater magnitude + 805 * 7. Positive, tie, nearest even has lower magnitude + 806 * 8. Negative, tie, nearest even has lower magnitude + 807 * + 808 * Round For Shorter precision correctness can be determined from the + 809 * above test cases. + 810 * + 811 *********************************************************************** + + +00000000000006CC 813 SBFPINRM DS 0F Inputs for short BFP rounding testing + 814 * + 815 * Multiply a value from 1.0 such that the added digits are to the right + ASMA Ver. 0.2.0 bfp-022-multsub.asm: Test IEEE Multiply And Subtract 09 Oct 2016 12:34:01 Page 23 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 816 * of the right-most bit in the stored significand. The result will be + 817 * inexact, and incremented will be determined by the value of the + 818 * bits in the multiplier. + 819 * +00000000000006CC 3F800007 820 DC X'3F800007' Multiplicand +1.00000083446502685546875 +00000000000006D0 3F880000 821 DC X'3F880000' Multiplier 1.0625 (1/16) +00000000000006D4 BF000000 822 DC X'BF000000' Subtrahend -0.5 +00000000000006D8 BF800007 823 DC X'BF800007' Multiplicand -1.00000083446502685546875 +00000000000006DC 3F880000 824 DC X'3F880000' Multiplier 1.0625 (1/16) +00000000000006E0 3F000000 825 DC X'3F000000' Subtrahend +0.5 + 826 *..nearest is toward zero, truncated + 827 * +00000000000006E4 3F80000C 828 DC X'3F80000C' Multiplicand +1.000001430511474609375 +00000000000006E8 3F880000 829 DC X'3F880000' Multiplier 1.0625 (1/16) +00000000000006EC BF000000 830 DC X'BF000000' Subtrahend -0.5 +00000000000006F0 BF80000C 831 DC X'BF80000C' Multiplicand -1.000001430511474609375 +00000000000006F4 3F880000 832 DC X'3F880000' Multiplier 1.0625 (1/16) +00000000000006F8 3F000000 833 DC X'3F000000' Subtrahend +0.5 + 834 *..nearest is away from zero, incremented. + 835 * +00000000000006FC 3F800008 836 DC X'3F800008' Multiplicand +1.000000476837158203125 +0000000000000700 3F880000 837 DC X'3F880000' Multiplier 1.0625 (1/16) +0000000000000704 BF000000 838 DC X'BF000000' Subtrahend -0.5 +0000000000000708 BF800008 839 DC X'BF800008' Multiplicand -1.000000476837158203125 +000000000000070C 3F880000 840 DC X'3F880000' Multiplier 1.0625 (1/16) +0000000000000710 3F000000 841 DC X'3F000000' Subtrahend +0.5 + 842 *..nearest is a tie, nearest even has lower magnitude + 843 * +0000000000000714 3F800018 844 DC X'3F800018' Multiplicand +1.000002384185791015625 +0000000000000718 3F880000 845 DC X'3F880000' Multiplier 1.0625 (1/16) +000000000000071C BF000000 846 DC X'BF000000' Subtrahend -0.5 +0000000000000720 BF800018 847 DC X'BF800018' Multiplicand -1.000002384185791015625 +0000000000000724 3F880000 848 DC X'3F880000' Multiplier 1.0625 (1/16) +0000000000000728 3F000000 849 DC X'3F000000' Subtrahend +0.5 + 850 *..nearest is a tie, nearest even has greater magnitude + 851 * + 0000000000000008 0000000000000001 852 SBFPRMCT EQU (*-SBFPINRM)/4/3 Count of short BFP rounding tests + ASMA Ver. 0.2.0 bfp-022-multsub.asm: Test IEEE Multiply And Subtract 09 Oct 2016 12:34:01 Page 24 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 854 *********************************************************************** + 855 * + 856 * Long BFP test data sets for Multiply And Subtract testing. + 857 * + 858 * The first test data set is used for tests of basic functionality, + 859 * NaN propagation, and results from operations involving other than + 860 * finite numbers. + 861 * + 862 * The second test data set is used for testing boundary conditions + 863 * using two finite non-zero values. Each possible condition code + 864 * and type of result (normal, scaled, etc) is created by members of + 865 * this test data set. + 866 * + 867 * The third test data set is used for exhaustive testing of final + 868 * results across the five rounding modes available for the Add + 869 * instruction. + 870 * + 871 * See the Short BFP test cases header for a discussion of test case + 872 * selection for rounding mode test case values. + 873 * + 874 *********************************************************************** + + + 876 *********************************************************************** + 877 * + 878 * First input test data set, to test operations using non-finite or + 879 * zero inputs. Member values chosen to validate Figure 19-24 on page + 880 * 19-39 of SA22-7832-10. Each value in this table is used as the + 881 * multiplicand, multiplier, and subtrahend. Eight entries menas 512 + 882 * result sets. + 883 * + 884 *********************************************************************** + + +000000000000072C 886 LBFPNFIN DS 0F Inputs for long BFP testing +000000000000072C FFF00000 00000000 887 DC X'FFF0000000000000' -inf +0000000000000734 C0000000 00000000 888 DC X'C000000000000000' -2.0 +000000000000073C 80000000 00000000 889 DC X'8000000000000000' -0 +0000000000000744 00000000 00000000 890 DC X'0000000000000000' +0 +000000000000074C 40000000 00000000 891 DC X'4000000000000000' +2.0 +0000000000000754 7FF00000 00000000 892 DC X'7FF0000000000000' +inf +000000000000075C FFF8B000 00000000 893 DC X'FFF8B00000000000' -QNaN +0000000000000764 7FF0A000 00000000 894 DC X'7FF0A00000000000' +SNaN + 0000000000000008 0000000000000001 895 LBFPNFCT EQU (*-LBFPNFIN)/8 Count of long BFP in list + + + + 897 *********************************************************************** + 898 * + 899 * Second input test data set. These are finite triples intended to + 900 * trigger overflow, underflow, and inexact exceptions. Each triples is + 901 * added twice, once non-trappable and once trappable. Trappable + ASMA Ver. 0.2.0 bfp-022-multsub.asm: Test IEEE Multiply And Subtract 09 Oct 2016 12:34:01 Page 25 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 902 * overflow or underflow yields a scaled result. Trappable inexact + 903 * will show whether the Incremented DXC code is returned. + 904 * + 905 * The following test cases are required: + 906 * 1. Overflow + 907 * 2. Underflow - normal inputs + 908 * 3. Underflow - subnormal inputs + 909 * 4. Normal - from subnormal inputs + 910 * 5. Inexact - incremented + 911 * 6. Inexact - truncated + 912 * + 913 *********************************************************************** + + +0000000000000770 915 LBFPIN DS 0D Inputs for long BFP finite tests + 916 * + 917 * Overflow on multiplication two ways. Once on the muliplication step, + 918 * and then a second time on the addition step. + 919 * +0000000000000770 7FEFFFFF FFFFFFFF 920 DC X'7FEFFFFFFFFFFFFF' +Nmax +0000000000000778 FFEFFFFF FFFFFFFF 921 DC X'FFEFFFFFFFFFFFFF' -Nmax +0000000000000780 3FF00000 00000000 922 DC X'3FF0000000000000' +1.0 + 923 * +0000000000000788 7FDFFFFF FFFFFFFF 924 DC X'7FDFFFFFFFFFFFFF' +Nmax / 2 +0000000000000790 C0000000 00000000 925 DC X'C000000000000000' -2.0 +0000000000000798 7FEFFFFF FFFFFFFF 926 DC X'7FEFFFFFFFFFFFFF' +Nmax + 927 * + 928 * Underflow from product of normals. We will multiply two small + 929 * normals to generate a subnormal, and then subtract a large subnormal. + 930 * +00000000000007A0 00100000 00000000 931 DC X'0010000000000000' +Nmin +00000000000007A8 00100000 00000000 932 DC X'0010000000000000' +Nmin +00000000000007B0 00080000 00000001 933 DC X'0008000000000001' A very large subnormal + 934 * + 935 * Underflow from the product of a subnormal and a normal. + 936 * +00000000000007B8 3FE00000 00000000 937 DC X'3FE0000000000000' +0.5 +00000000000007C0 000FFFFF FFFFFFFF 938 DC X'000FFFFFFFFFFFFF' +Dmax subnormal +00000000000007C8 00000000 00000001 939 DC X'0000000000000001' +Dmin, will appear in result + 940 * + 941 * We cannot generate a normal result from product of subnormals + 942 * because the result will be smaller than both the multiplicand and the + 943 * multiplier. So we'll try multiplying +Dmax by 2. The result should + 944 * be +Nmin + 945 * +00000000000007D0 000FFFFF FFFFFFFF 946 DC X'000FFFFFFFFFFFFF' +Dmax +00000000000007D8 40000000 00000000 947 DC X'4000000000000000' +2.0, result should be normal +00000000000007E0 00080000 00000000 948 DC X'0008000000000000' A large subnormal + 949 * + 950 * Multiply a value from 1.0 such that the added digits are to the right + 951 * of the right-most bit in the stored significand. The result will be + 952 * inexact, and incremented will be determined by the value of the + ASMA Ver. 0.2.0 bfp-022-multsub.asm: Test IEEE Multiply And Subtract 09 Oct 2016 12:34:01 Page 26 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 953 * bits in the multiplier. + 954 * +00000000000007E8 3FF00000 0000000C 955 DC X'3FF000000000000C' Multiplicand +1, aka 1.0b0 +00000000000007F0 3FF10000 00000000 956 DC X'3FF1000000000000' Multiplier 1.0625 (1/16) +00000000000007F8 BFE00000 00000000 957 DC X'BFE0000000000000' -0.5 + 958 *..nearest is away from zero, incremented. + 959 * +0000000000000800 3FF00000 00000007 960 DC X'3FF0000000000007' Multiplicand +1, aka 1.0b0 +0000000000000808 3FF10000 00000000 961 DC X'3FF1000000000000' Multiplier 1.0625 (1/16) +0000000000000810 BFE00000 00000000 962 DC X'BFE0000000000000' -0.5 + 963 *..nearest is toward zero, truncated. + 964 * + 0000000000000007 0000000000000001 965 LBFPCT EQU (*-LBFPIN)/8/3 Count of long BFP triples in list + + + + 967 *********************************************************************** + 968 * + 969 * Third input test data set. These are finite triples intended to + 970 * test all combinations of rounding mode for the product and the + 971 * remainder. Values are chosen to create a requirement to round + 972 * to the target precision after the computation and to generate + 973 * varying results depending on the rounding mode in the FPCR. + 974 * + 975 * The result set will have cases that represent each of the following + 976 * + 977 * 1. Positive, nearest magnitude is toward zero. + 978 * 2. Negative, nearest magnitude is toward zero. + 979 * 3. Positive, nearest magnitude is away from zero. + 980 * 4. Negative, nearest magnitude is away from zero. + 981 * 5. Positive, tie, nearest even has greater magnitude + 982 * 6. Negative, tie, nearest even has greater magnitude + 983 * 7. Positive, tie, nearest even has lower magnitude + 984 * 8. Negative, tie, nearest even has lower magnitude + 985 * + 986 * Round For Shorter precision correctness can be determined from the + 987 * above test cases. + 988 * + 989 *********************************************************************** + + +0000000000000818 991 LBFPINRM DS 0F + 992 * + 993 * Multiply a value from 1.0 such that the added digits are to the right + 994 * of the right-most bit in the stored significand. The result will be + 995 * inexact, and incremented will be determined by the value of the + 996 * bits in the multiplier. + 997 * +0000000000000818 3FF00000 00000007 998 DC X'3FF0000000000007' Multiplicand +0000000000000820 3FF10000 00000000 999 DC X'3FF1000000000000' Multiplier 1.0625 (1/16) +0000000000000828 BFE00000 00000000 1000 DC X'BFE0000000000000' -0.5 +0000000000000830 BFF00000 00000007 1001 DC X'BFF0000000000007' Multiplicand + ASMA Ver. 0.2.0 bfp-022-multsub.asm: Test IEEE Multiply And Subtract 09 Oct 2016 12:34:01 Page 27 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000838 3FF10000 00000000 1002 DC X'3FF1000000000000' Multiplier 1.0625 (1/16) +0000000000000840 3FE00000 00000000 1003 DC X'3FE0000000000000' +0.5 + 1004 *..nearest is toward zero, truncated. + 1005 * +0000000000000848 3FF00000 0000000C 1006 DC X'3FF000000000000C' Multiplicand +0000000000000850 3FF10000 00000000 1007 DC X'3FF1000000000000' Multiplier 1.0625 (1/16) +0000000000000858 BFE00000 00000000 1008 DC X'BFE0000000000000' -0.5 +0000000000000860 BFF00000 0000000C 1009 DC X'BFF000000000000C' Multiplicand +0000000000000868 3FF10000 00000000 1010 DC X'3FF1000000000000' Multiplier 1.0625 (1/16) +0000000000000870 3FE00000 00000000 1011 DC X'3FE0000000000000' +0.5 + 1012 *..nearest is away from zero, incremented. + 1013 * +0000000000000878 3FF00000 00000008 1014 DC X'3FF0000000000008' Multiplicand +0000000000000880 3FF10000 00000000 1015 DC X'3FF1000000000000' Multiplier 1.0625 (1/16) +0000000000000888 BFE00000 00000000 1016 DC X'BFE0000000000000' -0.5 +0000000000000890 BFF00000 00000008 1017 DC X'BFF0000000000008' Multiplicand +0000000000000898 3FF10000 00000000 1018 DC X'3FF1000000000000' Multiplier 1.0625 (1/16) +00000000000008A0 3FE00000 00000000 1019 DC X'3FE0000000000000' +0.5 + 1020 *..nearest is a tie, nearest even has lower magnitude + 1021 * +00000000000008A8 3FF00000 00000018 1022 DC X'3FF0000000000018' Multiplicand +1, aka +1.0b0 +00000000000008B0 3FF10000 00000000 1023 DC X'3FF1000000000000' Multiplier 1.0625 (1/16) +00000000000008B8 BFE00000 00000000 1024 DC X'BFE0000000000000' -0.5 +00000000000008C0 BFF00000 00000018 1025 DC X'BFF0000000000018' Multiplicand -1, aka -1.0b0 +00000000000008C8 3FF10000 00000000 1026 DC X'3FF1000000000000' Multiplier 1.0625 (1/16) +00000000000008D0 3FE00000 00000000 1027 DC X'3FE0000000000000' +0.5 + 1028 *..nearest is a tie, nearest even has greater magnitude + 1029 * + 0000000000000008 0000000000000001 1030 LBFPRMCT EQU (*-LBFPINRM)/8/3 Count of long BFP rounding tests + ASMA Ver. 0.2.0 bfp-022-multsub.asm: Test IEEE Multiply And Subtract 09 Oct 2016 12:34:01 Page 28 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1032 * + 1033 * Locations for results + 1034 * + 0000000000001000 0000000000000001 1035 SBFPNFOT EQU STRTLABL+X'1000' Short non-finite BFP results + 1036 * ..room for 512 tests, 512 used + 0000000000003000 0000000000000001 1037 SBFPNFFL EQU STRTLABL+X'3000' FPCR flags and DXC from short BFP + 1038 * ..room for 512 tests, 512 used + 1039 * + 0000000000005000 0000000000000001 1040 SBFPOUT EQU STRTLABL+X'5000' Short BFP finite results + 1041 * ..room for 16 tests, 7 used + 0000000000005100 0000000000000001 1042 SBFPFLGS EQU STRTLABL+X'5100' FPCR flags and DXC from short BFP + 1043 * ..room for 16 tests, 7 used + 1044 * + 0000000000005200 0000000000000001 1045 SBFPRMO EQU STRTLABL+X'5200' Short BFP rounding mode test results + 1046 * ..Room for 16, 8 used. + 0000000000005500 0000000000000001 1047 SBFPRMOF EQU STRTLABL+X'5500' Short BFP rounding mode FPCR results + 1048 * ..Room for 16, 8 used. + 1049 * ..next location starts at X'5800' + 1050 * + 0000000000006000 0000000000000001 1051 LBFPNFOT EQU STRTLABL+X'6000' Long non-finite BFP results + 1052 * ..room for 512 tests, 512 used + 000000000000A000 0000000000000001 1053 LBFPNFFL EQU STRTLABL+X'A000' FPCR flags and DXC from long BFP + 1054 * ..room for 512 tests, 512 used + 1055 * + 000000000000C000 0000000000000001 1056 LBFPOUT EQU STRTLABL+X'C000' Long BFP finite results + 1057 * ..room for 16 tests, 7 used + 000000000000C200 0000000000000001 1058 LBFPFLGS EQU STRTLABL+X'C200' FPCR flags and DXC from long BFP + 1059 * ..room for 16 tests, 7 used + 1060 * + 000000000000C500 0000000000000001 1061 LBFPRMO EQU STRTLABL+X'C500' Long BFP rounding mode test results + 1062 * ..Room for 16, 8 used. + 000000000000CA00 0000000000000001 1063 LBFPRMOF EQU STRTLABL+X'CA00' Long BFP rounding mode FPCR results + 1064 * ..Room for 16, 8 used. + 1065 * ..next location starts at X'CD00' + 1066 * + 1067 * + 000000000000C800 0000000000000001 1068 ENDLABL EQU STRTLABL+X'C800' + 1069 PADCSECT ENDLABL + 1070+ MNOTE *,'asma detected; no CSECT padding performed' +00000000000008D8 1071 END + ASMA Ver. 0.2.0 bfp-022-multsub.asm: Test IEEE Multiply And Subtract 09 Oct 2016 12:34:01 Page 29 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +BFPMULS J 000000 2264 87 +CTLR0 F 000278 4 196 170 171 172 +ENDLABL U 00C800 1 1068 +FPCMCT U 000005 1 664 405 604 +FPCMODES C 000650 1 658 664 408 607 +FPCREGNT X 00027C 4 197 287 299 344 360 410 419 487 499 544 560 609 618 +FPCREGTR X 000280 4 198 293 305 352 367 493 505 552 567 +FPR0 U 000000 1 108 +FPR1 U 000001 1 109 285 289 295 346 348 356 413 415 485 489 495 546 548 556 + 612 614 +FPR10 U 00000A 1 118 +FPR11 U 00000B 1 119 +FPR12 U 00000C 1 120 +FPR13 U 00000D 1 121 +FPR14 U 00000E 1 122 +FPR15 U 00000F 1 123 +FPR2 U 000002 1 110 +FPR3 U 000003 1 111 +FPR4 U 000004 1 112 284 289 295 301 307 345 348 356 363 370 412 415 423 484 + 489 495 501 507 545 548 556 563 570 611 614 621 +FPR5 U 000005 1 113 +FPR6 U 000006 1 114 +FPR7 U 000007 1 115 +FPR8 U 000008 1 116 288 289 290 294 295 296 300 301 302 306 307 308 347 348 + 349 353 356 357 361 363 364 368 370 371 414 415 416 421 + 423 424 488 489 490 494 495 496 500 501 502 506 507 508 + 547 548 549 553 556 557 561 563 564 568 570 571 613 614 + 615 620 621 622 +FPR9 U 000009 1 117 +HARDWAIT X 000268 8 194 161 +IMAGE 1 000000 2264 0 +LBFPCT U 000007 1 965 232 +LBFPF I 00056C 4 538 184 +LBFPFLGS U 00C200 1 1058 235 +LBFPIN D 000770 8 915 965 233 +LBFPINRM F 000818 4 991 1030 239 +LBFPNF H 0004DA 2 466 182 +LBFPNFCT U 000008 1 895 226 +LBFPNFFL U 00A000 1 1053 229 +LBFPNFIN F 00072C 4 886 895 227 +LBFPNFLP H 0004E6 2 472 520 +LBFPNFOT U 006000 1 1051 228 +LBFPOUT U 00C000 1 1056 234 +LBFPRM I 0005E6 4 597 186 +LBFPRMCT U 000008 1 1030 238 +LBFPRMO U 00C500 1 1061 240 +LBFPRMOF U 00CA00 1 1063 241 +LONGF F 000340 4 231 183 +LONGNF F 000330 4 225 181 +PCINTCD H 00008E 2 138 155 +PCNOTDTA H 00020C 2 158 156 +PCOLDPSW U 000150 1 140 157 + ASMA Ver. 0.2.0 bfp-022-multsub.asm: Test IEEE Multiply And Subtract 09 Oct 2016 12:34:01 Page 30 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +PROGCHK H 000200 2 154 146 +R0 U 000000 1 89 170 172 +R1 U 000001 1 90 280 314 402 408 411 420 480 514 601 607 610 619 +R10 U 00000A 1 99 174 176 178 181 183 185 267 268 273 278 338 339 398 399 + 467 468 473 478 538 539 597 598 +R11 U 00000B 1 100 +R12 U 00000C 1 101 275 317 342 377 403 440 475 517 542 577 602 637 +R13 U 00000D 1 102 175 177 179 182 184 186 270 321 341 378 401 442 470 521 + 541 578 600 639 +R14 U 00000E 1 103 159 160 188 189 +R15 U 00000F 1 104 125 +R2 U 000002 1 91 267 269 320 338 340 377 398 400 440 467 469 520 538 540 + 577 597 599 637 +R3 U 000003 1 92 267 284 319 338 345 346 347 353 361 363 368 370 374 398 + 412 413 414 421 423 437 467 484 519 538 545 546 547 553 + 561 563 568 570 574 597 611 612 613 620 621 635 +R4 U 000004 1 93 273 317 473 517 +R5 U 000005 1 94 273 285 301 307 316 405 408 430 473 485 501 507 516 604 + 607 628 +R6 U 000006 1 95 278 314 478 514 +R7 U 000007 1 96 278 288 294 300 306 313 339 349 357 364 371 375 399 416 + 424 427 438 478 488 494 500 506 513 539 549 557 564 571 + 575 598 615 622 625 +R8 U 000008 1 97 268 290 296 302 308 311 339 350 358 365 372 376 399 417 + 425 428 439 468 490 496 502 508 511 539 550 558 565 572 + 576 598 616 623 626 636 +R9 U 000009 1 98 268 291 297 303 309 312 406 430 468 491 497 503 509 512 + 605 628 +RMLONGS F 000350 4 237 185 +RMSHORTS F 000320 4 219 178 +SBFPCT U 000007 1 787 214 +SBFPF I 0003F2 4 338 177 +SBFPFLGS U 005100 1 1042 217 +SBFPIN F 000678 4 734 787 215 +SBFPINRM F 0006CC 4 813 852 221 +SBFPNF H 000360 2 266 175 +SBFPNFCT U 000008 1 714 208 +SBFPNFFL U 003000 1 1037 211 +SBFPNFIN F 000658 4 705 714 209 +SBFPNFLP H 00036C 2 272 320 +SBFPNFOT U 001000 1 1035 210 +SBFPOUT U 005000 1 1040 216 +SBFPRM I 00046C 4 398 179 +SBFPRMCT U 000008 1 852 220 +SBFPRMO U 005200 1 1045 222 +SBFPRMOF U 005500 1 1047 223 +SHORTF F 000310 4 213 176 +SHORTNF F 000300 4 207 174 +START H 000214 2 169 143 +STRTLABL U 000000 1 88 137 140 142 145 153 206 1035 1037 1040 1042 1045 1047 1051 1053 + 1056 1058 1061 1063 1068 +WAITPSW X 000258 8 193 190 + ASMA Ver. 0.2.0 bfp-022-multsub.asm: Test IEEE Multiply And Subtract 09 Oct 2016 12:34:01 Page 31 + + MACRO DEFN REFERENCES + +PADCSECT 62 1069 + ASMA Ver. 0.2.0 bfp-022-multsub.asm: Test IEEE Multiply And Subtract 09 Oct 2016 12:34:01 Page 32 + + DESC SYMBOL SIZE POS ADDR + +Entry: 0 + +Image IMAGE 2264 000-8D7 000-8D7 + Region 2264 000-8D7 000-8D7 + CSECT BFPMULS 2264 000-8D7 000-8D7 + ASMA Ver. 0.2.0 bfp-022-multsub.asm: Test IEEE Multiply And Subtract 09 Oct 2016 12:34:01 Page 33 + + STMT FILE NAME + +1 C:\Users\srorso\Documents\GitHub\hyperion\tests\bfp-022-multsub.asm + + +** NO ERRORS FOUND ** + +[1070] MNOTE *,asma detected; no CSECT padding performed + \ No newline at end of file diff --git a/tests/bfp-022-multsub.tst b/tests/bfp-022-multsub.tst new file mode 100644 index 000000000..18e2fc17f --- /dev/null +++ b/tests/bfp-022-multsub.tst @@ -0,0 +1,5495 @@ +*Testcase bfp-022-multsub.tst: MSEBR, MSEB, MSDBR, MSDB + +#Testcase bfp-022-multsub.tst: Multiplication tests Multiply And Subtract (4) +#..Test cases evaluate NaN propagation, NaN generation, operations +#..using non-finite values, trappable and non-trappable IEEE +#..exceptions, result scaling, and exhaustive rounding testing. + +sysclear +archmode esame + +# +# Following suppresses logging of program checks. This test program, as part +# of its normal operation, generates 1,211 program check messages that have no +# value in the validation process. (The messages, not the program checks.) +# +ostailor quiet + +loadcore "$(testpath)/bfp-022-multsub.core" + +runtest 1.0 + +ostailor null # restore messages for subsequent tests + + + +# Short BFP Multiply And Subtract finite results +*Compare +r 1000.10 +*Want "MSEBR/MSEB NF -inf/-inf/-inf" 7F800000 7F800000 7F800000 7F800000 +r 1010.10 +*Want "MSEBR/MSEB NF -inf/-inf/-2.0" 7F800000 7F800000 7F800000 7F800000 +r 1020.10 +*Want "MSEBR/MSEB NF -inf/-inf/-0" 7F800000 7F800000 7F800000 7F800000 +r 1030.10 +*Want "MSEBR/MSEB NF -inf/-inf/+0" 7F800000 7F800000 7F800000 7F800000 +r 1040.10 +*Want "MSEBR/MSEB NF -inf/-inf/+2.0" 7F800000 7F800000 7F800000 7F800000 +r 1050.10 +*Want "MSEBR/MSEB NF -inf/-inf/+inf" 7FC00000 7F800000 7FC00000 7F800000 +r 1060.10 +*Want "MSEBR/MSEB NF -inf/-inf/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1070.10 +*Want "MSEBR/MSEB NF -inf/-inf/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1080.10 +*Want "MSEBR/MSEB NF -inf/-2.0/-inf" 7F800000 7F800000 7F800000 7F800000 +r 1090.10 +*Want "MSEBR/MSEB NF -inf/-2.0/-2.0" 7F800000 7F800000 7F800000 7F800000 +r 10A0.10 +*Want "MSEBR/MSEB NF -inf/-2.0/-0" 7F800000 7F800000 7F800000 7F800000 +r 10B0.10 +*Want "MSEBR/MSEB NF -inf/-2.0/+0" 7F800000 7F800000 7F800000 7F800000 +r 10C0.10 +*Want "MSEBR/MSEB NF -inf/-2.0/+2.0" 7F800000 7F800000 7F800000 7F800000 +r 10D0.10 +*Want "MSEBR/MSEB NF -inf/-2.0/+inf" 7FC00000 7F800000 7FC00000 7F800000 +r 10E0.10 +*Want "MSEBR/MSEB NF -inf/-2.0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 10F0.10 +*Want "MSEBR/MSEB NF -inf/-2.0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1100.10 +*Want "MSEBR/MSEB NF -inf/-0/-inf" 7FC00000 FF800000 7FC00000 FF800000 +r 1110.10 +*Want "MSEBR/MSEB NF -inf/-0/-2.0" 7FC00000 C0000000 7FC00000 C0000000 +r 1120.10 +*Want "MSEBR/MSEB NF -inf/-0/-0" 7FC00000 80000000 7FC00000 80000000 +r 1130.10 +*Want "MSEBR/MSEB NF -inf/-0/+0" 7FC00000 00000000 7FC00000 00000000 +r 1140.10 +*Want "MSEBR/MSEB NF -inf/-0/+2.0" 7FC00000 40000000 7FC00000 40000000 +r 1150.10 +*Want "MSEBR/MSEB NF -inf/-0/+inf" 7FC00000 7F800000 7FC00000 7F800000 +r 1160.10 +*Want "MSEBR/MSEB NF -inf/-0/-QNaN" 7FC00000 FFCB0000 7FC00000 FFCB0000 +r 1170.10 +*Want "MSEBR/MSEB NF -inf/-0/+SNaN" 7FC00000 7F8A0000 7FC00000 7F8A0000 +r 1180.10 +*Want "MSEBR/MSEB NF -inf/+0/-inf" 7FC00000 FF800000 7FC00000 FF800000 +r 1190.10 +*Want "MSEBR/MSEB NF -inf/+0/-2.0" 7FC00000 C0000000 7FC00000 C0000000 +r 11A0.10 +*Want "MSEBR/MSEB NF -inf/+0/-0" 7FC00000 80000000 7FC00000 80000000 +r 11B0.10 +*Want "MSEBR/MSEB NF -inf/+0/+0" 7FC00000 00000000 7FC00000 00000000 +r 11C0.10 +*Want "MSEBR/MSEB NF -inf/+0/+2.0" 7FC00000 40000000 7FC00000 40000000 +r 11D0.10 +*Want "MSEBR/MSEB NF -inf/+0/+inf" 7FC00000 7F800000 7FC00000 7F800000 +r 11E0.10 +*Want "MSEBR/MSEB NF -inf/+0/-QNaN" 7FC00000 FFCB0000 7FC00000 FFCB0000 +r 11F0.10 +*Want "MSEBR/MSEB NF -inf/+0/+SNaN" 7FC00000 7F8A0000 7FC00000 7F8A0000 +r 1200.10 +*Want "MSEBR/MSEB NF -inf/+2.0/-inf" 7FC00000 FF800000 7FC00000 FF800000 +r 1210.10 +*Want "MSEBR/MSEB NF -inf/+2.0/-2.0" FF800000 FF800000 FF800000 FF800000 +r 1220.10 +*Want "MSEBR/MSEB NF -inf/+2.0/-0" FF800000 FF800000 FF800000 FF800000 +r 1230.10 +*Want "MSEBR/MSEB NF -inf/+2.0/+0" FF800000 FF800000 FF800000 FF800000 +r 1240.10 +*Want "MSEBR/MSEB NF -inf/+2.0/+2.0" FF800000 FF800000 FF800000 FF800000 +r 1250.10 +*Want "MSEBR/MSEB NF -inf/+2.0/+inf" FF800000 FF800000 FF800000 FF800000 +r 1260.10 +*Want "MSEBR/MSEB NF -inf/+2.0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1270.10 +*Want "MSEBR/MSEB NF -inf/+2.0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1280.10 +*Want "MSEBR/MSEB NF -inf/+inf/-inf" 7FC00000 FF800000 7FC00000 FF800000 +r 1290.10 +*Want "MSEBR/MSEB NF -inf/+inf/-2.0" FF800000 FF800000 FF800000 FF800000 +r 12A0.10 +*Want "MSEBR/MSEB NF -inf/+inf/-0" FF800000 FF800000 FF800000 FF800000 +r 12B0.10 +*Want "MSEBR/MSEB NF -inf/+inf/+0" FF800000 FF800000 FF800000 FF800000 +r 12C0.10 +*Want "MSEBR/MSEB NF -inf/+inf/+2.0" FF800000 FF800000 FF800000 FF800000 +r 12D0.10 +*Want "MSEBR/MSEB NF -inf/+inf/+inf" FF800000 FF800000 FF800000 FF800000 +r 12E0.10 +*Want "MSEBR/MSEB NF -inf/+inf/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 12F0.10 +*Want "MSEBR/MSEB NF -inf/+inf/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1300.10 +*Want "MSEBR/MSEB NF -inf/-QNaN/-inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1310.10 +*Want "MSEBR/MSEB NF -inf/-QNaN/-2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1320.10 +*Want "MSEBR/MSEB NF -inf/-QNaN/-0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1330.10 +*Want "MSEBR/MSEB NF -inf/-QNaN/+0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1340.10 +*Want "MSEBR/MSEB NF -inf/-QNaN/+2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1350.10 +*Want "MSEBR/MSEB NF -inf/-QNaN/+inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1360.10 +*Want "MSEBR/MSEB NF -inf/-QNaN/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1370.10 +*Want "MSEBR/MSEB NF -inf/-QNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1380.10 +*Want "MSEBR/MSEB NF -inf/+SNaN/-inf" 7FCA0000 FF800000 7FCA0000 FF800000 +r 1390.10 +*Want "MSEBR/MSEB NF -inf/+SNaN/-2.0" 7FCA0000 C0000000 7FCA0000 C0000000 +r 13A0.10 +*Want "MSEBR/MSEB NF -inf/+SNaN/-0" 7FCA0000 80000000 7FCA0000 80000000 +r 13B0.10 +*Want "MSEBR/MSEB NF -inf/+SNaN/+0" 7FCA0000 00000000 7FCA0000 00000000 +r 13C0.10 +*Want "MSEBR/MSEB NF -inf/+SNaN/+2.0" 7FCA0000 40000000 7FCA0000 40000000 +r 13D0.10 +*Want "MSEBR/MSEB NF -inf/+SNaN/+inf" 7FCA0000 7F800000 7FCA0000 7F800000 +r 13E0.10 +*Want "MSEBR/MSEB NF -inf/+SNaN/-QNaN" 7FCA0000 FFCB0000 7FCA0000 FFCB0000 +r 13F0.10 +*Want "MSEBR/MSEB NF -inf/+SNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1400.10 +*Want "MSEBR/MSEB NF -2.0/-inf/-inf" 7F800000 7F800000 7F800000 7F800000 +r 1410.10 +*Want "MSEBR/MSEB NF -2.0/-inf/-2.0" 7F800000 7F800000 7F800000 7F800000 +r 1420.10 +*Want "MSEBR/MSEB NF -2.0/-inf/-0" 7F800000 7F800000 7F800000 7F800000 +r 1430.10 +*Want "MSEBR/MSEB NF -2.0/-inf/+0" 7F800000 7F800000 7F800000 7F800000 +r 1440.10 +*Want "MSEBR/MSEB NF -2.0/-inf/+2.0" 7F800000 7F800000 7F800000 7F800000 +r 1450.10 +*Want "MSEBR/MSEB NF -2.0/-inf/+inf" 7FC00000 7F800000 7FC00000 7F800000 +r 1460.10 +*Want "MSEBR/MSEB NF -2.0/-inf/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1470.10 +*Want "MSEBR/MSEB NF -2.0/-inf/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1480.10 +*Want "MSEBR/MSEB NF -2.0/-2.0/-inf" 7F800000 7F800000 7F800000 7F800000 +r 1490.10 +*Want "MSEBR/MSEB NF -2.0/-2.0/-2.0" 40C00000 40C00000 40C00000 40C00000 +r 14A0.10 +*Want "MSEBR/MSEB NF -2.0/-2.0/-0" 40800000 40800000 40800000 40800000 +r 14B0.10 +*Want "MSEBR/MSEB NF -2.0/-2.0/+0" 40800000 40800000 40800000 40800000 +r 14C0.10 +*Want "MSEBR/MSEB NF -2.0/-2.0/+2.0" 40000000 40000000 40000000 40000000 +r 14D0.10 +*Want "MSEBR/MSEB NF -2.0/-2.0/+inf" FF800000 FF800000 FF800000 FF800000 +r 14E0.10 +*Want "MSEBR/MSEB NF -2.0/-2.0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 14F0.10 +*Want "MSEBR/MSEB NF -2.0/-2.0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1500.10 +*Want "MSEBR/MSEB NF -2.0/-0/-inf" 7F800000 7F800000 7F800000 7F800000 +r 1510.10 +*Want "MSEBR/MSEB NF -2.0/-0/-2.0" 40000000 40000000 40000000 40000000 +r 1520.10 +*Want "MSEBR/MSEB NF -2.0/-0/-0" 00000000 00000000 00000000 00000000 +r 1530.10 +*Want "MSEBR/MSEB NF -2.0/-0/+0" 00000000 00000000 00000000 00000000 +r 1540.10 +*Want "MSEBR/MSEB NF -2.0/-0/+2.0" C0000000 C0000000 C0000000 C0000000 +r 1550.10 +*Want "MSEBR/MSEB NF -2.0/-0/+inf" FF800000 FF800000 FF800000 FF800000 +r 1560.10 +*Want "MSEBR/MSEB NF -2.0/-0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1570.10 +*Want "MSEBR/MSEB NF -2.0/-0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1580.10 +*Want "MSEBR/MSEB NF -2.0/+0/-inf" 7F800000 7F800000 7F800000 7F800000 +r 1590.10 +*Want "MSEBR/MSEB NF -2.0/+0/-2.0" 40000000 40000000 40000000 40000000 +r 15A0.10 +*Want "MSEBR/MSEB NF -2.0/+0/-0" 00000000 00000000 00000000 00000000 +r 15B0.10 +*Want "MSEBR/MSEB NF -2.0/+0/+0" 80000000 80000000 80000000 80000000 +r 15C0.10 +*Want "MSEBR/MSEB NF -2.0/+0/+2.0" C0000000 C0000000 C0000000 C0000000 +r 15D0.10 +*Want "MSEBR/MSEB NF -2.0/+0/+inf" FF800000 FF800000 FF800000 FF800000 +r 15E0.10 +*Want "MSEBR/MSEB NF -2.0/+0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 15F0.10 +*Want "MSEBR/MSEB NF -2.0/+0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1600.10 +*Want "MSEBR/MSEB NF -2.0/+2.0/-inf" 7F800000 7F800000 7F800000 7F800000 +r 1610.10 +*Want "MSEBR/MSEB NF -2.0/+2.0/-2.0" C0000000 C0000000 C0000000 C0000000 +r 1620.10 +*Want "MSEBR/MSEB NF -2.0/+2.0/-0" C0800000 C0800000 C0800000 C0800000 +r 1630.10 +*Want "MSEBR/MSEB NF -2.0/+2.0/+0" C0800000 C0800000 C0800000 C0800000 +r 1640.10 +*Want "MSEBR/MSEB NF -2.0/+2.0/+2.0" C0C00000 C0C00000 C0C00000 C0C00000 +r 1650.10 +*Want "MSEBR/MSEB NF -2.0/+2.0/+inf" FF800000 FF800000 FF800000 FF800000 +r 1660.10 +*Want "MSEBR/MSEB NF -2.0/+2.0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1670.10 +*Want "MSEBR/MSEB NF -2.0/+2.0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1680.10 +*Want "MSEBR/MSEB NF -2.0/+inf/-inf" 7FC00000 FF800000 7FC00000 FF800000 +r 1690.10 +*Want "MSEBR/MSEB NF -2.0/+inf/-2.0" FF800000 FF800000 FF800000 FF800000 +r 16A0.10 +*Want "MSEBR/MSEB NF -2.0/+inf/-0" FF800000 FF800000 FF800000 FF800000 +r 16B0.10 +*Want "MSEBR/MSEB NF -2.0/+inf/+0" FF800000 FF800000 FF800000 FF800000 +r 16C0.10 +*Want "MSEBR/MSEB NF -2.0/+inf/+2.0" FF800000 FF800000 FF800000 FF800000 +r 16D0.10 +*Want "MSEBR/MSEB NF -2.0/+inf/+inf" FF800000 FF800000 FF800000 FF800000 +r 16E0.10 +*Want "MSEBR/MSEB NF -2.0/+inf/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 16F0.10 +*Want "MSEBR/MSEB NF -2.0/+inf/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1700.10 +*Want "MSEBR/MSEB NF -2.0/-QNaN/-inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1710.10 +*Want "MSEBR/MSEB NF -2.0/-QNaN/-2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1720.10 +*Want "MSEBR/MSEB NF -2.0/-QNaN/-0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1730.10 +*Want "MSEBR/MSEB NF -2.0/-QNaN/+0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1740.10 +*Want "MSEBR/MSEB NF -2.0/-QNaN/+2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1750.10 +*Want "MSEBR/MSEB NF -2.0/-QNaN/+inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1760.10 +*Want "MSEBR/MSEB NF -2.0/-QNaN/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1770.10 +*Want "MSEBR/MSEB NF -2.0/-QNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1780.10 +*Want "MSEBR/MSEB NF -2.0/+SNaN/-inf" 7FCA0000 FF800000 7FCA0000 FF800000 +r 1790.10 +*Want "MSEBR/MSEB NF -2.0/+SNaN/-2.0" 7FCA0000 C0000000 7FCA0000 C0000000 +r 17A0.10 +*Want "MSEBR/MSEB NF -2.0/+SNaN/-0" 7FCA0000 80000000 7FCA0000 80000000 +r 17B0.10 +*Want "MSEBR/MSEB NF -2.0/+SNaN/+0" 7FCA0000 00000000 7FCA0000 00000000 +r 17C0.10 +*Want "MSEBR/MSEB NF -2.0/+SNaN/+2.0" 7FCA0000 40000000 7FCA0000 40000000 +r 17D0.10 +*Want "MSEBR/MSEB NF -2.0/+SNaN/+inf" 7FCA0000 7F800000 7FCA0000 7F800000 +r 17E0.10 +*Want "MSEBR/MSEB NF -2.0/+SNaN/-QNaN" 7FCA0000 FFCB0000 7FCA0000 FFCB0000 +r 17F0.10 +*Want "MSEBR/MSEB NF -2.0/+SNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1800.10 +*Want "MSEBR/MSEB NF -0/-inf/-inf" 7FC00000 FF800000 7FC00000 FF800000 +r 1810.10 +*Want "MSEBR/MSEB NF -0/-inf/-2.0" 7FC00000 C0000000 7FC00000 C0000000 +r 1820.10 +*Want "MSEBR/MSEB NF -0/-inf/-0" 7FC00000 80000000 7FC00000 80000000 +r 1830.10 +*Want "MSEBR/MSEB NF -0/-inf/+0" 7FC00000 00000000 7FC00000 00000000 +r 1840.10 +*Want "MSEBR/MSEB NF -0/-inf/+2.0" 7FC00000 40000000 7FC00000 40000000 +r 1850.10 +*Want "MSEBR/MSEB NF -0/-inf/+inf" 7FC00000 7F800000 7FC00000 7F800000 +r 1860.10 +*Want "MSEBR/MSEB NF -0/-inf/-QNaN" 7FC00000 FFCB0000 7FC00000 FFCB0000 +r 1870.10 +*Want "MSEBR/MSEB NF -0/-inf/+SNaN" 7FC00000 7F8A0000 7FC00000 7F8A0000 +r 1880.10 +*Want "MSEBR/MSEB NF -0/-2.0/-inf" 7F800000 7F800000 7F800000 7F800000 +r 1890.10 +*Want "MSEBR/MSEB NF -0/-2.0/-2.0" 40000000 40000000 40000000 40000000 +r 18A0.10 +*Want "MSEBR/MSEB NF -0/-2.0/-0" 00000000 00000000 00000000 00000000 +r 18B0.10 +*Want "MSEBR/MSEB NF -0/-2.0/+0" 00000000 00000000 00000000 00000000 +r 18C0.10 +*Want "MSEBR/MSEB NF -0/-2.0/+2.0" C0000000 C0000000 C0000000 C0000000 +r 18D0.10 +*Want "MSEBR/MSEB NF -0/-2.0/+inf" FF800000 FF800000 FF800000 FF800000 +r 18E0.10 +*Want "MSEBR/MSEB NF -0/-2.0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 18F0.10 +*Want "MSEBR/MSEB NF -0/-2.0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1900.10 +*Want "MSEBR/MSEB NF -0/-0/-inf" 7F800000 7F800000 7F800000 7F800000 +r 1910.10 +*Want "MSEBR/MSEB NF -0/-0/-2.0" 40000000 40000000 40000000 40000000 +r 1920.10 +*Want "MSEBR/MSEB NF -0/-0/-0" 00000000 00000000 00000000 00000000 +r 1930.10 +*Want "MSEBR/MSEB NF -0/-0/+0" 00000000 00000000 00000000 00000000 +r 1940.10 +*Want "MSEBR/MSEB NF -0/-0/+2.0" C0000000 C0000000 C0000000 C0000000 +r 1950.10 +*Want "MSEBR/MSEB NF -0/-0/+inf" FF800000 FF800000 FF800000 FF800000 +r 1960.10 +*Want "MSEBR/MSEB NF -0/-0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1970.10 +*Want "MSEBR/MSEB NF -0/-0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1980.10 +*Want "MSEBR/MSEB NF -0/+0/-inf" 7F800000 7F800000 7F800000 7F800000 +r 1990.10 +*Want "MSEBR/MSEB NF -0/+0/-2.0" 40000000 40000000 40000000 40000000 +r 19A0.10 +*Want "MSEBR/MSEB NF -0/+0/-0" 00000000 00000000 00000000 00000000 +r 19B0.10 +*Want "MSEBR/MSEB NF -0/+0/+0" 80000000 80000000 80000000 80000000 +r 19C0.10 +*Want "MSEBR/MSEB NF -0/+0/+2.0" C0000000 C0000000 C0000000 C0000000 +r 19D0.10 +*Want "MSEBR/MSEB NF -0/+0/+inf" FF800000 FF800000 FF800000 FF800000 +r 19E0.10 +*Want "MSEBR/MSEB NF -0/+0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 19F0.10 +*Want "MSEBR/MSEB NF -0/+0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1A00.10 +*Want "MSEBR/MSEB NF -0/+2.0/-inf" 7F800000 7F800000 7F800000 7F800000 +r 1A10.10 +*Want "MSEBR/MSEB NF -0/+2.0/-2.0" 40000000 40000000 40000000 40000000 +r 1A20.10 +*Want "MSEBR/MSEB NF -0/+2.0/-0" 00000000 00000000 00000000 00000000 +r 1A30.10 +*Want "MSEBR/MSEB NF -0/+2.0/+0" 80000000 80000000 80000000 80000000 +r 1A40.10 +*Want "MSEBR/MSEB NF -0/+2.0/+2.0" C0000000 C0000000 C0000000 C0000000 +r 1A50.10 +*Want "MSEBR/MSEB NF -0/+2.0/+inf" FF800000 FF800000 FF800000 FF800000 +r 1A60.10 +*Want "MSEBR/MSEB NF -0/+2.0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1A70.10 +*Want "MSEBR/MSEB NF -0/+2.0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1A80.10 +*Want "MSEBR/MSEB NF -0/+inf/-inf" 7FC00000 FF800000 7FC00000 FF800000 +r 1A90.10 +*Want "MSEBR/MSEB NF -0/+inf/-2.0" 7FC00000 C0000000 7FC00000 C0000000 +r 1AA0.10 +*Want "MSEBR/MSEB NF -0/+inf/-0" 7FC00000 80000000 7FC00000 80000000 +r 1AB0.10 +*Want "MSEBR/MSEB NF -0/+inf/+0" 7FC00000 00000000 7FC00000 00000000 +r 1AC0.10 +*Want "MSEBR/MSEB NF -0/+inf/+2.0" 7FC00000 40000000 7FC00000 40000000 +r 1AD0.10 +*Want "MSEBR/MSEB NF -0/+inf/+inf" 7FC00000 7F800000 7FC00000 7F800000 +r 1AE0.10 +*Want "MSEBR/MSEB NF -0/+inf/-QNaN" 7FC00000 FFCB0000 7FC00000 FFCB0000 +r 1AF0.10 +*Want "MSEBR/MSEB NF -0/+inf/+SNaN" 7FC00000 7F8A0000 7FC00000 7F8A0000 +r 1B00.10 +*Want "MSEBR/MSEB NF -0/-QNaN/-inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1B10.10 +*Want "MSEBR/MSEB NF -0/-QNaN/-2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1B20.10 +*Want "MSEBR/MSEB NF -0/-QNaN/-0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1B30.10 +*Want "MSEBR/MSEB NF -0/-QNaN/+0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1B40.10 +*Want "MSEBR/MSEB NF -0/-QNaN/+2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1B50.10 +*Want "MSEBR/MSEB NF -0/-QNaN/+inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1B60.10 +*Want "MSEBR/MSEB NF -0/-QNaN/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1B70.10 +*Want "MSEBR/MSEB NF -0/-QNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1B80.10 +*Want "MSEBR/MSEB NF -0/+SNaN/-inf" 7FCA0000 FF800000 7FCA0000 FF800000 +r 1B90.10 +*Want "MSEBR/MSEB NF -0/+SNaN/-2.0" 7FCA0000 C0000000 7FCA0000 C0000000 +r 1BA0.10 +*Want "MSEBR/MSEB NF -0/+SNaN/-0" 7FCA0000 80000000 7FCA0000 80000000 +r 1BB0.10 +*Want "MSEBR/MSEB NF -0/+SNaN/+0" 7FCA0000 00000000 7FCA0000 00000000 +r 1BC0.10 +*Want "MSEBR/MSEB NF -0/+SNaN/+2.0" 7FCA0000 40000000 7FCA0000 40000000 +r 1BD0.10 +*Want "MSEBR/MSEB NF -0/+SNaN/+inf" 7FCA0000 7F800000 7FCA0000 7F800000 +r 1BE0.10 +*Want "MSEBR/MSEB NF -0/+SNaN/-QNaN" 7FCA0000 FFCB0000 7FCA0000 FFCB0000 +r 1BF0.10 +*Want "MSEBR/MSEB NF -0/+SNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1C00.10 +*Want "MSEBR/MSEB NF +0/-inf/-inf" 7FC00000 FF800000 7FC00000 FF800000 +r 1C10.10 +*Want "MSEBR/MSEB NF +0/-inf/-2.0" 7FC00000 C0000000 7FC00000 C0000000 +r 1C20.10 +*Want "MSEBR/MSEB NF +0/-inf/-0" 7FC00000 80000000 7FC00000 80000000 +r 1C30.10 +*Want "MSEBR/MSEB NF +0/-inf/+0" 7FC00000 00000000 7FC00000 00000000 +r 1C40.10 +*Want "MSEBR/MSEB NF +0/-inf/+2.0" 7FC00000 40000000 7FC00000 40000000 +r 1C50.10 +*Want "MSEBR/MSEB NF +0/-inf/+inf" 7FC00000 7F800000 7FC00000 7F800000 +r 1C60.10 +*Want "MSEBR/MSEB NF +0/-inf/-QNaN" 7FC00000 FFCB0000 7FC00000 FFCB0000 +r 1C70.10 +*Want "MSEBR/MSEB NF +0/-inf/+SNaN" 7FC00000 7F8A0000 7FC00000 7F8A0000 +r 1C80.10 +*Want "MSEBR/MSEB NF +0/-2.0/-inf" 7F800000 7F800000 7F800000 7F800000 +r 1C90.10 +*Want "MSEBR/MSEB NF +0/-2.0/-2.0" 40000000 40000000 40000000 40000000 +r 1CA0.10 +*Want "MSEBR/MSEB NF +0/-2.0/-0" 00000000 00000000 00000000 00000000 +r 1CB0.10 +*Want "MSEBR/MSEB NF +0/-2.0/+0" 80000000 80000000 80000000 80000000 +r 1CC0.10 +*Want "MSEBR/MSEB NF +0/-2.0/+2.0" C0000000 C0000000 C0000000 C0000000 +r 1CD0.10 +*Want "MSEBR/MSEB NF +0/-2.0/+inf" FF800000 FF800000 FF800000 FF800000 +r 1CE0.10 +*Want "MSEBR/MSEB NF +0/-2.0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1CF0.10 +*Want "MSEBR/MSEB NF +0/-2.0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1D00.10 +*Want "MSEBR/MSEB NF +0/-0/-inf" 7F800000 7F800000 7F800000 7F800000 +r 1D10.10 +*Want "MSEBR/MSEB NF +0/-0/-2.0" 40000000 40000000 40000000 40000000 +r 1D20.10 +*Want "MSEBR/MSEB NF +0/-0/-0" 00000000 00000000 00000000 00000000 +r 1D30.10 +*Want "MSEBR/MSEB NF +0/-0/+0" 80000000 80000000 80000000 80000000 +r 1D40.10 +*Want "MSEBR/MSEB NF +0/-0/+2.0" C0000000 C0000000 C0000000 C0000000 +r 1D50.10 +*Want "MSEBR/MSEB NF +0/-0/+inf" FF800000 FF800000 FF800000 FF800000 +r 1D60.10 +*Want "MSEBR/MSEB NF +0/-0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1D70.10 +*Want "MSEBR/MSEB NF +0/-0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1D80.10 +*Want "MSEBR/MSEB NF +0/+0/-inf" 7F800000 7F800000 7F800000 7F800000 +r 1D90.10 +*Want "MSEBR/MSEB NF +0/+0/-2.0" 40000000 40000000 40000000 40000000 +r 1DA0.10 +*Want "MSEBR/MSEB NF +0/+0/-0" 00000000 00000000 00000000 00000000 +r 1DB0.10 +*Want "MSEBR/MSEB NF +0/+0/+0" 00000000 00000000 00000000 00000000 +r 1DC0.10 +*Want "MSEBR/MSEB NF +0/+0/+2.0" C0000000 C0000000 C0000000 C0000000 +r 1DD0.10 +*Want "MSEBR/MSEB NF +0/+0/+inf" FF800000 FF800000 FF800000 FF800000 +r 1DE0.10 +*Want "MSEBR/MSEB NF +0/+0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1DF0.10 +*Want "MSEBR/MSEB NF +0/+0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1E00.10 +*Want "MSEBR/MSEB NF +0/+2.0/-inf" 7F800000 7F800000 7F800000 7F800000 +r 1E10.10 +*Want "MSEBR/MSEB NF +0/+2.0/-2.0" 40000000 40000000 40000000 40000000 +r 1E20.10 +*Want "MSEBR/MSEB NF +0/+2.0/-0" 00000000 00000000 00000000 00000000 +r 1E30.10 +*Want "MSEBR/MSEB NF +0/+2.0/+0" 00000000 00000000 00000000 00000000 +r 1E40.10 +*Want "MSEBR/MSEB NF +0/+2.0/+2.0" C0000000 C0000000 C0000000 C0000000 +r 1E50.10 +*Want "MSEBR/MSEB NF +0/+2.0/+inf" FF800000 FF800000 FF800000 FF800000 +r 1E60.10 +*Want "MSEBR/MSEB NF +0/+2.0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1E70.10 +*Want "MSEBR/MSEB NF +0/+2.0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1E80.10 +*Want "MSEBR/MSEB NF +0/+inf/-inf" 7FC00000 FF800000 7FC00000 FF800000 +r 1E90.10 +*Want "MSEBR/MSEB NF +0/+inf/-2.0" 7FC00000 C0000000 7FC00000 C0000000 +r 1EA0.10 +*Want "MSEBR/MSEB NF +0/+inf/-0" 7FC00000 80000000 7FC00000 80000000 +r 1EB0.10 +*Want "MSEBR/MSEB NF +0/+inf/+0" 7FC00000 00000000 7FC00000 00000000 +r 1EC0.10 +*Want "MSEBR/MSEB NF +0/+inf/+2.0" 7FC00000 40000000 7FC00000 40000000 +r 1ED0.10 +*Want "MSEBR/MSEB NF +0/+inf/+inf" 7FC00000 7F800000 7FC00000 7F800000 +r 1EE0.10 +*Want "MSEBR/MSEB NF +0/+inf/-QNaN" 7FC00000 FFCB0000 7FC00000 FFCB0000 +r 1EF0.10 +*Want "MSEBR/MSEB NF +0/+inf/+SNaN" 7FC00000 7F8A0000 7FC00000 7F8A0000 +r 1F00.10 +*Want "MSEBR/MSEB NF +0/-QNaN/-inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1F10.10 +*Want "MSEBR/MSEB NF +0/-QNaN/-2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1F20.10 +*Want "MSEBR/MSEB NF +0/-QNaN/-0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1F30.10 +*Want "MSEBR/MSEB NF +0/-QNaN/+0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1F40.10 +*Want "MSEBR/MSEB NF +0/-QNaN/+2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1F50.10 +*Want "MSEBR/MSEB NF +0/-QNaN/+inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1F60.10 +*Want "MSEBR/MSEB NF +0/-QNaN/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 1F70.10 +*Want "MSEBR/MSEB NF +0/-QNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 1F80.10 +*Want "MSEBR/MSEB NF +0/+SNaN/-inf" 7FCA0000 FF800000 7FCA0000 FF800000 +r 1F90.10 +*Want "MSEBR/MSEB NF +0/+SNaN/-2.0" 7FCA0000 C0000000 7FCA0000 C0000000 +r 1FA0.10 +*Want "MSEBR/MSEB NF +0/+SNaN/-0" 7FCA0000 80000000 7FCA0000 80000000 +r 1FB0.10 +*Want "MSEBR/MSEB NF +0/+SNaN/+0" 7FCA0000 00000000 7FCA0000 00000000 +r 1FC0.10 +*Want "MSEBR/MSEB NF +0/+SNaN/+2.0" 7FCA0000 40000000 7FCA0000 40000000 +r 1FD0.10 +*Want "MSEBR/MSEB NF +0/+SNaN/+inf" 7FCA0000 7F800000 7FCA0000 7F800000 +r 1FE0.10 +*Want "MSEBR/MSEB NF +0/+SNaN/-QNaN" 7FCA0000 FFCB0000 7FCA0000 FFCB0000 +r 1FF0.10 +*Want "MSEBR/MSEB NF +0/+SNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2000.10 +*Want "MSEBR/MSEB NF +2.0/-inf/-inf" 7FC00000 FF800000 7FC00000 FF800000 +r 2010.10 +*Want "MSEBR/MSEB NF +2.0/-inf/-2.0" FF800000 FF800000 FF800000 FF800000 +r 2020.10 +*Want "MSEBR/MSEB NF +2.0/-inf/-0" FF800000 FF800000 FF800000 FF800000 +r 2030.10 +*Want "MSEBR/MSEB NF +2.0/-inf/+0" FF800000 FF800000 FF800000 FF800000 +r 2040.10 +*Want "MSEBR/MSEB NF +2.0/-inf/+2.0" FF800000 FF800000 FF800000 FF800000 +r 2050.10 +*Want "MSEBR/MSEB NF +2.0/-inf/+inf" FF800000 FF800000 FF800000 FF800000 +r 2060.10 +*Want "MSEBR/MSEB NF +2.0/-inf/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2070.10 +*Want "MSEBR/MSEB NF +2.0/-inf/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2080.10 +*Want "MSEBR/MSEB NF +2.0/-2.0/-inf" 7F800000 7F800000 7F800000 7F800000 +r 2090.10 +*Want "MSEBR/MSEB NF +2.0/-2.0/-2.0" C0000000 C0000000 C0000000 C0000000 +r 20A0.10 +*Want "MSEBR/MSEB NF +2.0/-2.0/-0" C0800000 C0800000 C0800000 C0800000 +r 20B0.10 +*Want "MSEBR/MSEB NF +2.0/-2.0/+0" C0800000 C0800000 C0800000 C0800000 +r 20C0.10 +*Want "MSEBR/MSEB NF +2.0/-2.0/+2.0" C0C00000 C0C00000 C0C00000 C0C00000 +r 20D0.10 +*Want "MSEBR/MSEB NF +2.0/-2.0/+inf" FF800000 FF800000 FF800000 FF800000 +r 20E0.10 +*Want "MSEBR/MSEB NF +2.0/-2.0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 20F0.10 +*Want "MSEBR/MSEB NF +2.0/-2.0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2100.10 +*Want "MSEBR/MSEB NF +2.0/-0/-inf" 7F800000 7F800000 7F800000 7F800000 +r 2110.10 +*Want "MSEBR/MSEB NF +2.0/-0/-2.0" 40000000 40000000 40000000 40000000 +r 2120.10 +*Want "MSEBR/MSEB NF +2.0/-0/-0" 00000000 00000000 00000000 00000000 +r 2130.10 +*Want "MSEBR/MSEB NF +2.0/-0/+0" 80000000 80000000 80000000 80000000 +r 2140.10 +*Want "MSEBR/MSEB NF +2.0/-0/+2.0" C0000000 C0000000 C0000000 C0000000 +r 2150.10 +*Want "MSEBR/MSEB NF +2.0/-0/+inf" FF800000 FF800000 FF800000 FF800000 +r 2160.10 +*Want "MSEBR/MSEB NF +2.0/-0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2170.10 +*Want "MSEBR/MSEB NF +2.0/-0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2180.10 +*Want "MSEBR/MSEB NF +2.0/+0/-inf" 7F800000 7F800000 7F800000 7F800000 +r 2190.10 +*Want "MSEBR/MSEB NF +2.0/+0/-2.0" 40000000 40000000 40000000 40000000 +r 21A0.10 +*Want "MSEBR/MSEB NF +2.0/+0/-0" 00000000 00000000 00000000 00000000 +r 21B0.10 +*Want "MSEBR/MSEB NF +2.0/+0/+0" 00000000 00000000 00000000 00000000 +r 21C0.10 +*Want "MSEBR/MSEB NF +2.0/+0/+2.0" C0000000 C0000000 C0000000 C0000000 +r 21D0.10 +*Want "MSEBR/MSEB NF +2.0/+0/+inf" FF800000 FF800000 FF800000 FF800000 +r 21E0.10 +*Want "MSEBR/MSEB NF +2.0/+0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 21F0.10 +*Want "MSEBR/MSEB NF +2.0/+0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2200.10 +*Want "MSEBR/MSEB NF +2.0/+2.0/-inf" 7F800000 7F800000 7F800000 7F800000 +r 2210.10 +*Want "MSEBR/MSEB NF +2.0/+2.0/-2.0" 40C00000 40C00000 40C00000 40C00000 +r 2220.10 +*Want "MSEBR/MSEB NF +2.0/+2.0/-0" 40800000 40800000 40800000 40800000 +r 2230.10 +*Want "MSEBR/MSEB NF +2.0/+2.0/+0" 40800000 40800000 40800000 40800000 +r 2240.10 +*Want "MSEBR/MSEB NF +2.0/+2.0/+2.0" 40000000 40000000 40000000 40000000 +r 2250.10 +*Want "MSEBR/MSEB NF +2.0/+2.0/+inf" FF800000 FF800000 FF800000 FF800000 +r 2260.10 +*Want "MSEBR/MSEB NF +2.0/+2.0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2270.10 +*Want "MSEBR/MSEB NF +2.0/+2.0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2280.10 +*Want "MSEBR/MSEB NF +2.0/+inf/-inf" 7F800000 7F800000 7F800000 7F800000 +r 2290.10 +*Want "MSEBR/MSEB NF +2.0/+inf/-2.0" 7F800000 7F800000 7F800000 7F800000 +r 22A0.10 +*Want "MSEBR/MSEB NF +2.0/+inf/-0" 7F800000 7F800000 7F800000 7F800000 +r 22B0.10 +*Want "MSEBR/MSEB NF +2.0/+inf/+0" 7F800000 7F800000 7F800000 7F800000 +r 22C0.10 +*Want "MSEBR/MSEB NF +2.0/+inf/+2.0" 7F800000 7F800000 7F800000 7F800000 +r 22D0.10 +*Want "MSEBR/MSEB NF +2.0/+inf/+inf" 7FC00000 7F800000 7FC00000 7F800000 +r 22E0.10 +*Want "MSEBR/MSEB NF +2.0/+inf/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 22F0.10 +*Want "MSEBR/MSEB NF +2.0/+inf/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2300.10 +*Want "MSEBR/MSEB NF +2.0/-QNaN/-inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2310.10 +*Want "MSEBR/MSEB NF +2.0/-QNaN/-2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2320.10 +*Want "MSEBR/MSEB NF +2.0/-QNaN/-0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2330.10 +*Want "MSEBR/MSEB NF +2.0/-QNaN/+0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2340.10 +*Want "MSEBR/MSEB NF +2.0/-QNaN/+2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2350.10 +*Want "MSEBR/MSEB NF +2.0/-QNaN/+inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2360.10 +*Want "MSEBR/MSEB NF +2.0/-QNaN/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2370.10 +*Want "MSEBR/MSEB NF +2.0/-QNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2380.10 +*Want "MSEBR/MSEB NF +2.0/+SNaN/-inf" 7FCA0000 FF800000 7FCA0000 FF800000 +r 2390.10 +*Want "MSEBR/MSEB NF +2.0/+SNaN/-2.0" 7FCA0000 C0000000 7FCA0000 C0000000 +r 23A0.10 +*Want "MSEBR/MSEB NF +2.0/+SNaN/-0" 7FCA0000 80000000 7FCA0000 80000000 +r 23B0.10 +*Want "MSEBR/MSEB NF +2.0/+SNaN/+0" 7FCA0000 00000000 7FCA0000 00000000 +r 23C0.10 +*Want "MSEBR/MSEB NF +2.0/+SNaN/+2.0" 7FCA0000 40000000 7FCA0000 40000000 +r 23D0.10 +*Want "MSEBR/MSEB NF +2.0/+SNaN/+inf" 7FCA0000 7F800000 7FCA0000 7F800000 +r 23E0.10 +*Want "MSEBR/MSEB NF +2.0/+SNaN/-QNaN" 7FCA0000 FFCB0000 7FCA0000 FFCB0000 +r 23F0.10 +*Want "MSEBR/MSEB NF +2.0/+SNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2400.10 +*Want "MSEBR/MSEB NF +inf/-inf/-inf" 7FC00000 FF800000 7FC00000 FF800000 +r 2410.10 +*Want "MSEBR/MSEB NF +inf/-inf/-2.0" FF800000 FF800000 FF800000 FF800000 +r 2420.10 +*Want "MSEBR/MSEB NF +inf/-inf/-0" FF800000 FF800000 FF800000 FF800000 +r 2430.10 +*Want "MSEBR/MSEB NF +inf/-inf/+0" FF800000 FF800000 FF800000 FF800000 +r 2440.10 +*Want "MSEBR/MSEB NF +inf/-inf/+2.0" FF800000 FF800000 FF800000 FF800000 +r 2450.10 +*Want "MSEBR/MSEB NF +inf/-inf/+inf" FF800000 FF800000 FF800000 FF800000 +r 2460.10 +*Want "MSEBR/MSEB NF +inf/-inf/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2470.10 +*Want "MSEBR/MSEB NF +inf/-inf/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2480.10 +*Want "MSEBR/MSEB NF +inf/-2.0/-inf" 7FC00000 FF800000 7FC00000 FF800000 +r 2490.10 +*Want "MSEBR/MSEB NF +inf/-2.0/-2.0" FF800000 FF800000 FF800000 FF800000 +r 24A0.10 +*Want "MSEBR/MSEB NF +inf/-2.0/-0" FF800000 FF800000 FF800000 FF800000 +r 24B0.10 +*Want "MSEBR/MSEB NF +inf/-2.0/+0" FF800000 FF800000 FF800000 FF800000 +r 24C0.10 +*Want "MSEBR/MSEB NF +inf/-2.0/+2.0" FF800000 FF800000 FF800000 FF800000 +r 24D0.10 +*Want "MSEBR/MSEB NF +inf/-2.0/+inf" FF800000 FF800000 FF800000 FF800000 +r 24E0.10 +*Want "MSEBR/MSEB NF +inf/-2.0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 24F0.10 +*Want "MSEBR/MSEB NF +inf/-2.0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2500.10 +*Want "MSEBR/MSEB NF +inf/-0/-inf" 7FC00000 FF800000 7FC00000 FF800000 +r 2510.10 +*Want "MSEBR/MSEB NF +inf/-0/-2.0" 7FC00000 C0000000 7FC00000 C0000000 +r 2520.10 +*Want "MSEBR/MSEB NF +inf/-0/-0" 7FC00000 80000000 7FC00000 80000000 +r 2530.10 +*Want "MSEBR/MSEB NF +inf/-0/+0" 7FC00000 00000000 7FC00000 00000000 +r 2540.10 +*Want "MSEBR/MSEB NF +inf/-0/+2.0" 7FC00000 40000000 7FC00000 40000000 +r 2550.10 +*Want "MSEBR/MSEB NF +inf/-0/+inf" 7FC00000 7F800000 7FC00000 7F800000 +r 2560.10 +*Want "MSEBR/MSEB NF +inf/-0/-QNaN" 7FC00000 FFCB0000 7FC00000 FFCB0000 +r 2570.10 +*Want "MSEBR/MSEB NF +inf/-0/+SNaN" 7FC00000 7F8A0000 7FC00000 7F8A0000 +r 2580.10 +*Want "MSEBR/MSEB NF +inf/+0/-inf" 7FC00000 FF800000 7FC00000 FF800000 +r 2590.10 +*Want "MSEBR/MSEB NF +inf/+0/-2.0" 7FC00000 C0000000 7FC00000 C0000000 +r 25A0.10 +*Want "MSEBR/MSEB NF +inf/+0/-0" 7FC00000 80000000 7FC00000 80000000 +r 25B0.10 +*Want "MSEBR/MSEB NF +inf/+0/+0" 7FC00000 00000000 7FC00000 00000000 +r 25C0.10 +*Want "MSEBR/MSEB NF +inf/+0/+2.0" 7FC00000 40000000 7FC00000 40000000 +r 25D0.10 +*Want "MSEBR/MSEB NF +inf/+0/+inf" 7FC00000 7F800000 7FC00000 7F800000 +r 25E0.10 +*Want "MSEBR/MSEB NF +inf/+0/-QNaN" 7FC00000 FFCB0000 7FC00000 FFCB0000 +r 25F0.10 +*Want "MSEBR/MSEB NF +inf/+0/+SNaN" 7FC00000 7F8A0000 7FC00000 7F8A0000 +r 2600.10 +*Want "MSEBR/MSEB NF +inf/+2.0/-inf" 7F800000 7F800000 7F800000 7F800000 +r 2610.10 +*Want "MSEBR/MSEB NF +inf/+2.0/-2.0" 7F800000 7F800000 7F800000 7F800000 +r 2620.10 +*Want "MSEBR/MSEB NF +inf/+2.0/-0" 7F800000 7F800000 7F800000 7F800000 +r 2630.10 +*Want "MSEBR/MSEB NF +inf/+2.0/+0" 7F800000 7F800000 7F800000 7F800000 +r 2640.10 +*Want "MSEBR/MSEB NF +inf/+2.0/+2.0" 7F800000 7F800000 7F800000 7F800000 +r 2650.10 +*Want "MSEBR/MSEB NF +inf/+2.0/+inf" 7FC00000 7F800000 7FC00000 7F800000 +r 2660.10 +*Want "MSEBR/MSEB NF +inf/+2.0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2670.10 +*Want "MSEBR/MSEB NF +inf/+2.0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2680.10 +*Want "MSEBR/MSEB NF +inf/+inf/-inf" 7F800000 7F800000 7F800000 7F800000 +r 2690.10 +*Want "MSEBR/MSEB NF +inf/+inf/-2.0" 7F800000 7F800000 7F800000 7F800000 +r 26A0.10 +*Want "MSEBR/MSEB NF +inf/+inf/-0" 7F800000 7F800000 7F800000 7F800000 +r 26B0.10 +*Want "MSEBR/MSEB NF +inf/+inf/+0" 7F800000 7F800000 7F800000 7F800000 +r 26C0.10 +*Want "MSEBR/MSEB NF +inf/+inf/+2.0" 7F800000 7F800000 7F800000 7F800000 +r 26D0.10 +*Want "MSEBR/MSEB NF +inf/+inf/+inf" 7FC00000 7F800000 7FC00000 7F800000 +r 26E0.10 +*Want "MSEBR/MSEB NF +inf/+inf/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 26F0.10 +*Want "MSEBR/MSEB NF +inf/+inf/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2700.10 +*Want "MSEBR/MSEB NF +inf/-QNaN/-inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2710.10 +*Want "MSEBR/MSEB NF +inf/-QNaN/-2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2720.10 +*Want "MSEBR/MSEB NF +inf/-QNaN/-0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2730.10 +*Want "MSEBR/MSEB NF +inf/-QNaN/+0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2740.10 +*Want "MSEBR/MSEB NF +inf/-QNaN/+2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2750.10 +*Want "MSEBR/MSEB NF +inf/-QNaN/+inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2760.10 +*Want "MSEBR/MSEB NF +inf/-QNaN/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2770.10 +*Want "MSEBR/MSEB NF +inf/-QNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2780.10 +*Want "MSEBR/MSEB NF +inf/+SNaN/-inf" 7FCA0000 FF800000 7FCA0000 FF800000 +r 2790.10 +*Want "MSEBR/MSEB NF +inf/+SNaN/-2.0" 7FCA0000 C0000000 7FCA0000 C0000000 +r 27A0.10 +*Want "MSEBR/MSEB NF +inf/+SNaN/-0" 7FCA0000 80000000 7FCA0000 80000000 +r 27B0.10 +*Want "MSEBR/MSEB NF +inf/+SNaN/+0" 7FCA0000 00000000 7FCA0000 00000000 +r 27C0.10 +*Want "MSEBR/MSEB NF +inf/+SNaN/+2.0" 7FCA0000 40000000 7FCA0000 40000000 +r 27D0.10 +*Want "MSEBR/MSEB NF +inf/+SNaN/+inf" 7FCA0000 7F800000 7FCA0000 7F800000 +r 27E0.10 +*Want "MSEBR/MSEB NF +inf/+SNaN/-QNaN" 7FCA0000 FFCB0000 7FCA0000 FFCB0000 +r 27F0.10 +*Want "MSEBR/MSEB NF +inf/+SNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2800.10 +*Want "MSEBR/MSEB NF -QNaN/-inf/-inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2810.10 +*Want "MSEBR/MSEB NF -QNaN/-inf/-2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2820.10 +*Want "MSEBR/MSEB NF -QNaN/-inf/-0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2830.10 +*Want "MSEBR/MSEB NF -QNaN/-inf/+0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2840.10 +*Want "MSEBR/MSEB NF -QNaN/-inf/+2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2850.10 +*Want "MSEBR/MSEB NF -QNaN/-inf/+inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2860.10 +*Want "MSEBR/MSEB NF -QNaN/-inf/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2870.10 +*Want "MSEBR/MSEB NF -QNaN/-inf/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2880.10 +*Want "MSEBR/MSEB NF -QNaN/-2.0/-inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2890.10 +*Want "MSEBR/MSEB NF -QNaN/-2.0/-2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 28A0.10 +*Want "MSEBR/MSEB NF -QNaN/-2.0/-0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 28B0.10 +*Want "MSEBR/MSEB NF -QNaN/-2.0/+0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 28C0.10 +*Want "MSEBR/MSEB NF -QNaN/-2.0/+2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 28D0.10 +*Want "MSEBR/MSEB NF -QNaN/-2.0/+inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 28E0.10 +*Want "MSEBR/MSEB NF -QNaN/-2.0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 28F0.10 +*Want "MSEBR/MSEB NF -QNaN/-2.0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2900.10 +*Want "MSEBR/MSEB NF -QNaN/-0/-inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2910.10 +*Want "MSEBR/MSEB NF -QNaN/-0/-2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2920.10 +*Want "MSEBR/MSEB NF -QNaN/-0/-0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2930.10 +*Want "MSEBR/MSEB NF -QNaN/-0/+0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2940.10 +*Want "MSEBR/MSEB NF -QNaN/-0/+2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2950.10 +*Want "MSEBR/MSEB NF -QNaN/-0/+inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2960.10 +*Want "MSEBR/MSEB NF -QNaN/-0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2970.10 +*Want "MSEBR/MSEB NF -QNaN/-0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2980.10 +*Want "MSEBR/MSEB NF -QNaN/+0/-inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2990.10 +*Want "MSEBR/MSEB NF -QNaN/+0/-2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 29A0.10 +*Want "MSEBR/MSEB NF -QNaN/+0/-0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 29B0.10 +*Want "MSEBR/MSEB NF -QNaN/+0/+0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 29C0.10 +*Want "MSEBR/MSEB NF -QNaN/+0/+2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 29D0.10 +*Want "MSEBR/MSEB NF -QNaN/+0/+inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 29E0.10 +*Want "MSEBR/MSEB NF -QNaN/+0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 29F0.10 +*Want "MSEBR/MSEB NF -QNaN/+0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2A00.10 +*Want "MSEBR/MSEB NF -QNaN/+2.0/-inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2A10.10 +*Want "MSEBR/MSEB NF -QNaN/+2.0/-2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2A20.10 +*Want "MSEBR/MSEB NF -QNaN/+2.0/-0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2A30.10 +*Want "MSEBR/MSEB NF -QNaN/+2.0/+0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2A40.10 +*Want "MSEBR/MSEB NF -QNaN/+2.0/+2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2A50.10 +*Want "MSEBR/MSEB NF -QNaN/+2.0/+inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2A60.10 +*Want "MSEBR/MSEB NF -QNaN/+2.0/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2A70.10 +*Want "MSEBR/MSEB NF -QNaN/+2.0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2A80.10 +*Want "MSEBR/MSEB NF -QNaN/+inf/-inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2A90.10 +*Want "MSEBR/MSEB NF -QNaN/+inf/-2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2AA0.10 +*Want "MSEBR/MSEB NF -QNaN/+inf/-0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2AB0.10 +*Want "MSEBR/MSEB NF -QNaN/+inf/+0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2AC0.10 +*Want "MSEBR/MSEB NF -QNaN/+inf/+2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2AD0.10 +*Want "MSEBR/MSEB NF -QNaN/+inf/+inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2AE0.10 +*Want "MSEBR/MSEB NF -QNaN/+inf/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2AF0.10 +*Want "MSEBR/MSEB NF -QNaN/+inf/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2B00.10 +*Want "MSEBR/MSEB NF -QNaN/-QNaN/-inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2B10.10 +*Want "MSEBR/MSEB NF -QNaN/-QNaN/-2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2B20.10 +*Want "MSEBR/MSEB NF -QNaN/-QNaN/-0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2B30.10 +*Want "MSEBR/MSEB NF -QNaN/-QNaN/+0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2B40.10 +*Want "MSEBR/MSEB NF -QNaN/-QNaN/+2.0" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2B50.10 +*Want "MSEBR/MSEB NF -QNaN/-QNaN/+inf" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2B60.10 +*Want "MSEBR/MSEB NF -QNaN/-QNaN/-QNaN" FFCB0000 FFCB0000 FFCB0000 FFCB0000 +r 2B70.10 +*Want "MSEBR/MSEB NF -QNaN/-QNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2B80.10 +*Want "MSEBR/MSEB NF -QNaN/+SNaN/-inf" 7FCA0000 FF800000 7FCA0000 FF800000 +r 2B90.10 +*Want "MSEBR/MSEB NF -QNaN/+SNaN/-2.0" 7FCA0000 C0000000 7FCA0000 C0000000 +r 2BA0.10 +*Want "MSEBR/MSEB NF -QNaN/+SNaN/-0" 7FCA0000 80000000 7FCA0000 80000000 +r 2BB0.10 +*Want "MSEBR/MSEB NF -QNaN/+SNaN/+0" 7FCA0000 00000000 7FCA0000 00000000 +r 2BC0.10 +*Want "MSEBR/MSEB NF -QNaN/+SNaN/+2.0" 7FCA0000 40000000 7FCA0000 40000000 +r 2BD0.10 +*Want "MSEBR/MSEB NF -QNaN/+SNaN/+inf" 7FCA0000 7F800000 7FCA0000 7F800000 +r 2BE0.10 +*Want "MSEBR/MSEB NF -QNaN/+SNaN/-QNaN" 7FCA0000 FFCB0000 7FCA0000 FFCB0000 +r 2BF0.10 +*Want "MSEBR/MSEB NF -QNaN/+SNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2C00.10 +*Want "MSEBR/MSEB NF +SNaN/-inf/-inf" 7FCA0000 FF800000 7FCA0000 FF800000 +r 2C10.10 +*Want "MSEBR/MSEB NF +SNaN/-inf/-2.0" 7FCA0000 C0000000 7FCA0000 C0000000 +r 2C20.10 +*Want "MSEBR/MSEB NF +SNaN/-inf/-0" 7FCA0000 80000000 7FCA0000 80000000 +r 2C30.10 +*Want "MSEBR/MSEB NF +SNaN/-inf/+0" 7FCA0000 00000000 7FCA0000 00000000 +r 2C40.10 +*Want "MSEBR/MSEB NF +SNaN/-inf/+2.0" 7FCA0000 40000000 7FCA0000 40000000 +r 2C50.10 +*Want "MSEBR/MSEB NF +SNaN/-inf/+inf" 7FCA0000 7F800000 7FCA0000 7F800000 +r 2C60.10 +*Want "MSEBR/MSEB NF +SNaN/-inf/-QNaN" 7FCA0000 FFCB0000 7FCA0000 FFCB0000 +r 2C70.10 +*Want "MSEBR/MSEB NF +SNaN/-inf/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2C80.10 +*Want "MSEBR/MSEB NF +SNaN/-2.0/-inf" 7FCA0000 FF800000 7FCA0000 FF800000 +r 2C90.10 +*Want "MSEBR/MSEB NF +SNaN/-2.0/-2.0" 7FCA0000 C0000000 7FCA0000 C0000000 +r 2CA0.10 +*Want "MSEBR/MSEB NF +SNaN/-2.0/-0" 7FCA0000 80000000 7FCA0000 80000000 +r 2CB0.10 +*Want "MSEBR/MSEB NF +SNaN/-2.0/+0" 7FCA0000 00000000 7FCA0000 00000000 +r 2CC0.10 +*Want "MSEBR/MSEB NF +SNaN/-2.0/+2.0" 7FCA0000 40000000 7FCA0000 40000000 +r 2CD0.10 +*Want "MSEBR/MSEB NF +SNaN/-2.0/+inf" 7FCA0000 7F800000 7FCA0000 7F800000 +r 2CE0.10 +*Want "MSEBR/MSEB NF +SNaN/-2.0/-QNaN" 7FCA0000 FFCB0000 7FCA0000 FFCB0000 +r 2CF0.10 +*Want "MSEBR/MSEB NF +SNaN/-2.0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2D00.10 +*Want "MSEBR/MSEB NF +SNaN/-0/-inf" 7FCA0000 FF800000 7FCA0000 FF800000 +r 2D10.10 +*Want "MSEBR/MSEB NF +SNaN/-0/-2.0" 7FCA0000 C0000000 7FCA0000 C0000000 +r 2D20.10 +*Want "MSEBR/MSEB NF +SNaN/-0/-0" 7FCA0000 80000000 7FCA0000 80000000 +r 2D30.10 +*Want "MSEBR/MSEB NF +SNaN/-0/+0" 7FCA0000 00000000 7FCA0000 00000000 +r 2D40.10 +*Want "MSEBR/MSEB NF +SNaN/-0/+2.0" 7FCA0000 40000000 7FCA0000 40000000 +r 2D50.10 +*Want "MSEBR/MSEB NF +SNaN/-0/+inf" 7FCA0000 7F800000 7FCA0000 7F800000 +r 2D60.10 +*Want "MSEBR/MSEB NF +SNaN/-0/-QNaN" 7FCA0000 FFCB0000 7FCA0000 FFCB0000 +r 2D70.10 +*Want "MSEBR/MSEB NF +SNaN/-0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2D80.10 +*Want "MSEBR/MSEB NF +SNaN/+0/-inf" 7FCA0000 FF800000 7FCA0000 FF800000 +r 2D90.10 +*Want "MSEBR/MSEB NF +SNaN/+0/-2.0" 7FCA0000 C0000000 7FCA0000 C0000000 +r 2DA0.10 +*Want "MSEBR/MSEB NF +SNaN/+0/-0" 7FCA0000 80000000 7FCA0000 80000000 +r 2DB0.10 +*Want "MSEBR/MSEB NF +SNaN/+0/+0" 7FCA0000 00000000 7FCA0000 00000000 +r 2DC0.10 +*Want "MSEBR/MSEB NF +SNaN/+0/+2.0" 7FCA0000 40000000 7FCA0000 40000000 +r 2DD0.10 +*Want "MSEBR/MSEB NF +SNaN/+0/+inf" 7FCA0000 7F800000 7FCA0000 7F800000 +r 2DE0.10 +*Want "MSEBR/MSEB NF +SNaN/+0/-QNaN" 7FCA0000 FFCB0000 7FCA0000 FFCB0000 +r 2DF0.10 +*Want "MSEBR/MSEB NF +SNaN/+0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2E00.10 +*Want "MSEBR/MSEB NF +SNaN/+2.0/-inf" 7FCA0000 FF800000 7FCA0000 FF800000 +r 2E10.10 +*Want "MSEBR/MSEB NF +SNaN/+2.0/-2.0" 7FCA0000 C0000000 7FCA0000 C0000000 +r 2E20.10 +*Want "MSEBR/MSEB NF +SNaN/+2.0/-0" 7FCA0000 80000000 7FCA0000 80000000 +r 2E30.10 +*Want "MSEBR/MSEB NF +SNaN/+2.0/+0" 7FCA0000 00000000 7FCA0000 00000000 +r 2E40.10 +*Want "MSEBR/MSEB NF +SNaN/+2.0/+2.0" 7FCA0000 40000000 7FCA0000 40000000 +r 2E50.10 +*Want "MSEBR/MSEB NF +SNaN/+2.0/+inf" 7FCA0000 7F800000 7FCA0000 7F800000 +r 2E60.10 +*Want "MSEBR/MSEB NF +SNaN/+2.0/-QNaN" 7FCA0000 FFCB0000 7FCA0000 FFCB0000 +r 2E70.10 +*Want "MSEBR/MSEB NF +SNaN/+2.0/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2E80.10 +*Want "MSEBR/MSEB NF +SNaN/+inf/-inf" 7FCA0000 FF800000 7FCA0000 FF800000 +r 2E90.10 +*Want "MSEBR/MSEB NF +SNaN/+inf/-2.0" 7FCA0000 C0000000 7FCA0000 C0000000 +r 2EA0.10 +*Want "MSEBR/MSEB NF +SNaN/+inf/-0" 7FCA0000 80000000 7FCA0000 80000000 +r 2EB0.10 +*Want "MSEBR/MSEB NF +SNaN/+inf/+0" 7FCA0000 00000000 7FCA0000 00000000 +r 2EC0.10 +*Want "MSEBR/MSEB NF +SNaN/+inf/+2.0" 7FCA0000 40000000 7FCA0000 40000000 +r 2ED0.10 +*Want "MSEBR/MSEB NF +SNaN/+inf/+inf" 7FCA0000 7F800000 7FCA0000 7F800000 +r 2EE0.10 +*Want "MSEBR/MSEB NF +SNaN/+inf/-QNaN" 7FCA0000 FFCB0000 7FCA0000 FFCB0000 +r 2EF0.10 +*Want "MSEBR/MSEB NF +SNaN/+inf/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2F00.10 +*Want "MSEBR/MSEB NF +SNaN/-QNaN/-inf" 7FCA0000 FF800000 7FCA0000 FF800000 +r 2F10.10 +*Want "MSEBR/MSEB NF +SNaN/-QNaN/-2.0" 7FCA0000 C0000000 7FCA0000 C0000000 +r 2F20.10 +*Want "MSEBR/MSEB NF +SNaN/-QNaN/-0" 7FCA0000 80000000 7FCA0000 80000000 +r 2F30.10 +*Want "MSEBR/MSEB NF +SNaN/-QNaN/+0" 7FCA0000 00000000 7FCA0000 00000000 +r 2F40.10 +*Want "MSEBR/MSEB NF +SNaN/-QNaN/+2.0" 7FCA0000 40000000 7FCA0000 40000000 +r 2F50.10 +*Want "MSEBR/MSEB NF +SNaN/-QNaN/+inf" 7FCA0000 7F800000 7FCA0000 7F800000 +r 2F60.10 +*Want "MSEBR/MSEB NF +SNaN/-QNaN/-QNaN" 7FCA0000 FFCB0000 7FCA0000 FFCB0000 +r 2F70.10 +*Want "MSEBR/MSEB NF +SNaN/-QNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 +r 2F80.10 +*Want "MSEBR/MSEB NF +SNaN/+SNaN/-inf" 7FCA0000 FF800000 7FCA0000 FF800000 +r 2F90.10 +*Want "MSEBR/MSEB NF +SNaN/+SNaN/-2.0" 7FCA0000 C0000000 7FCA0000 C0000000 +r 2FA0.10 +*Want "MSEBR/MSEB NF +SNaN/+SNaN/-0" 7FCA0000 80000000 7FCA0000 80000000 +r 2FB0.10 +*Want "MSEBR/MSEB NF +SNaN/+SNaN/+0" 7FCA0000 00000000 7FCA0000 00000000 +r 2FC0.10 +*Want "MSEBR/MSEB NF +SNaN/+SNaN/+2.0" 7FCA0000 40000000 7FCA0000 40000000 +r 2FD0.10 +*Want "MSEBR/MSEB NF +SNaN/+SNaN/+inf" 7FCA0000 7F800000 7FCA0000 7F800000 +r 2FE0.10 +*Want "MSEBR/MSEB NF +SNaN/+SNaN/-QNaN" 7FCA0000 FFCB0000 7FCA0000 FFCB0000 +r 2FF0.10 +*Want "MSEBR/MSEB NF +SNaN/+SNaN/+SNaN" 7FCA0000 7F8A0000 7FCA0000 7F8A0000 + + +# Short BFP Multiply And Subtract finite results - FPCR contents +*Compare +r 3000.10 +*Want "MSEBR/MSEB NF -inf/-inf/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3010.10 +*Want "MSEBR/MSEB NF -inf/-inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3020.10 +*Want "MSEBR/MSEB NF -inf/-inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3030.10 +*Want "MSEBR/MSEB NF -inf/-inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3040.10 +*Want "MSEBR/MSEB NF -inf/-inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3050.10 +*Want "MSEBR/MSEB NF -inf/-inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3060.10 +*Want "MSEBR/MSEB NF -inf/-inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3070.10 +*Want "MSEBR/MSEB NF -inf/-inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3080.10 +*Want "MSEBR/MSEB NF -inf/-2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3090.10 +*Want "MSEBR/MSEB NF -inf/-2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 30A0.10 +*Want "MSEBR/MSEB NF -inf/-2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 30B0.10 +*Want "MSEBR/MSEB NF -inf/-2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 30C0.10 +*Want "MSEBR/MSEB NF -inf/-2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 30D0.10 +*Want "MSEBR/MSEB NF -inf/-2.0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 30E0.10 +*Want "MSEBR/MSEB NF -inf/-2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 30F0.10 +*Want "MSEBR/MSEB NF -inf/-2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3100.10 +*Want "MSEBR/MSEB NF -inf/-0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3110.10 +*Want "MSEBR/MSEB NF -inf/-0/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3120.10 +*Want "MSEBR/MSEB NF -inf/-0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3130.10 +*Want "MSEBR/MSEB NF -inf/-0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3140.10 +*Want "MSEBR/MSEB NF -inf/-0/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3150.10 +*Want "MSEBR/MSEB NF -inf/-0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3160.10 +*Want "MSEBR/MSEB NF -inf/-0/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3170.10 +*Want "MSEBR/MSEB NF -inf/-0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3180.10 +*Want "MSEBR/MSEB NF -inf/+0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3190.10 +*Want "MSEBR/MSEB NF -inf/+0/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 31A0.10 +*Want "MSEBR/MSEB NF -inf/+0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 31B0.10 +*Want "MSEBR/MSEB NF -inf/+0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 31C0.10 +*Want "MSEBR/MSEB NF -inf/+0/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 31D0.10 +*Want "MSEBR/MSEB NF -inf/+0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 31E0.10 +*Want "MSEBR/MSEB NF -inf/+0/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 31F0.10 +*Want "MSEBR/MSEB NF -inf/+0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3200.10 +*Want "MSEBR/MSEB NF -inf/+2.0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3210.10 +*Want "MSEBR/MSEB NF -inf/+2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3220.10 +*Want "MSEBR/MSEB NF -inf/+2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3230.10 +*Want "MSEBR/MSEB NF -inf/+2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3240.10 +*Want "MSEBR/MSEB NF -inf/+2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3250.10 +*Want "MSEBR/MSEB NF -inf/+2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3260.10 +*Want "MSEBR/MSEB NF -inf/+2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3270.10 +*Want "MSEBR/MSEB NF -inf/+2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3280.10 +*Want "MSEBR/MSEB NF -inf/+inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3290.10 +*Want "MSEBR/MSEB NF -inf/+inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 32A0.10 +*Want "MSEBR/MSEB NF -inf/+inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 32B0.10 +*Want "MSEBR/MSEB NF -inf/+inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 32C0.10 +*Want "MSEBR/MSEB NF -inf/+inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 32D0.10 +*Want "MSEBR/MSEB NF -inf/+inf/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 32E0.10 +*Want "MSEBR/MSEB NF -inf/+inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 32F0.10 +*Want "MSEBR/MSEB NF -inf/+inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3300.10 +*Want "MSEBR/MSEB NF -inf/-QNaN/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3310.10 +*Want "MSEBR/MSEB NF -inf/-QNaN/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3320.10 +*Want "MSEBR/MSEB NF -inf/-QNaN/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3330.10 +*Want "MSEBR/MSEB NF -inf/-QNaN/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3340.10 +*Want "MSEBR/MSEB NF -inf/-QNaN/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3350.10 +*Want "MSEBR/MSEB NF -inf/-QNaN/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3360.10 +*Want "MSEBR/MSEB NF -inf/-QNaN/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3370.10 +*Want "MSEBR/MSEB NF -inf/-QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3380.10 +*Want "MSEBR/MSEB NF -inf/+SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3390.10 +*Want "MSEBR/MSEB NF -inf/+SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 33A0.10 +*Want "MSEBR/MSEB NF -inf/+SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 33B0.10 +*Want "MSEBR/MSEB NF -inf/+SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 33C0.10 +*Want "MSEBR/MSEB NF -inf/+SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 33D0.10 +*Want "MSEBR/MSEB NF -inf/+SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 33E0.10 +*Want "MSEBR/MSEB NF -inf/+SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 33F0.10 +*Want "MSEBR/MSEB NF -inf/+SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3400.10 +*Want "MSEBR/MSEB NF -2.0/-inf/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3410.10 +*Want "MSEBR/MSEB NF -2.0/-inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3420.10 +*Want "MSEBR/MSEB NF -2.0/-inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3430.10 +*Want "MSEBR/MSEB NF -2.0/-inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3440.10 +*Want "MSEBR/MSEB NF -2.0/-inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3450.10 +*Want "MSEBR/MSEB NF -2.0/-inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3460.10 +*Want "MSEBR/MSEB NF -2.0/-inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3470.10 +*Want "MSEBR/MSEB NF -2.0/-inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3480.10 +*Want "MSEBR/MSEB NF -2.0/-2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3490.10 +*Want "MSEBR/MSEB NF -2.0/-2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 34A0.10 +*Want "MSEBR/MSEB NF -2.0/-2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 34B0.10 +*Want "MSEBR/MSEB NF -2.0/-2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 34C0.10 +*Want "MSEBR/MSEB NF -2.0/-2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 34D0.10 +*Want "MSEBR/MSEB NF -2.0/-2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 34E0.10 +*Want "MSEBR/MSEB NF -2.0/-2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 34F0.10 +*Want "MSEBR/MSEB NF -2.0/-2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3500.10 +*Want "MSEBR/MSEB NF -2.0/-0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3510.10 +*Want "MSEBR/MSEB NF -2.0/-0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3520.10 +*Want "MSEBR/MSEB NF -2.0/-0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3530.10 +*Want "MSEBR/MSEB NF -2.0/-0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3540.10 +*Want "MSEBR/MSEB NF -2.0/-0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3550.10 +*Want "MSEBR/MSEB NF -2.0/-0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3560.10 +*Want "MSEBR/MSEB NF -2.0/-0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3570.10 +*Want "MSEBR/MSEB NF -2.0/-0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3580.10 +*Want "MSEBR/MSEB NF -2.0/+0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3590.10 +*Want "MSEBR/MSEB NF -2.0/+0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 35A0.10 +*Want "MSEBR/MSEB NF -2.0/+0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 35B0.10 +*Want "MSEBR/MSEB NF -2.0/+0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 35C0.10 +*Want "MSEBR/MSEB NF -2.0/+0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 35D0.10 +*Want "MSEBR/MSEB NF -2.0/+0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 35E0.10 +*Want "MSEBR/MSEB NF -2.0/+0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 35F0.10 +*Want "MSEBR/MSEB NF -2.0/+0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3600.10 +*Want "MSEBR/MSEB NF -2.0/+2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3610.10 +*Want "MSEBR/MSEB NF -2.0/+2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3620.10 +*Want "MSEBR/MSEB NF -2.0/+2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3630.10 +*Want "MSEBR/MSEB NF -2.0/+2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3640.10 +*Want "MSEBR/MSEB NF -2.0/+2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3650.10 +*Want "MSEBR/MSEB NF -2.0/+2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3660.10 +*Want "MSEBR/MSEB NF -2.0/+2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3670.10 +*Want "MSEBR/MSEB NF -2.0/+2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3680.10 +*Want "MSEBR/MSEB NF -2.0/+inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3690.10 +*Want "MSEBR/MSEB NF -2.0/+inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 36A0.10 +*Want "MSEBR/MSEB NF -2.0/+inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 36B0.10 +*Want "MSEBR/MSEB NF -2.0/+inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 36C0.10 +*Want "MSEBR/MSEB NF -2.0/+inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 36D0.10 +*Want "MSEBR/MSEB NF -2.0/+inf/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 36E0.10 +*Want "MSEBR/MSEB NF -2.0/+inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 36F0.10 +*Want "MSEBR/MSEB NF -2.0/+inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3700.10 +*Want "MSEBR/MSEB NF -2.0/-QNaN/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3710.10 +*Want "MSEBR/MSEB NF -2.0/-QNaN/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3720.10 +*Want "MSEBR/MSEB NF -2.0/-QNaN/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3730.10 +*Want "MSEBR/MSEB NF -2.0/-QNaN/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3740.10 +*Want "MSEBR/MSEB NF -2.0/-QNaN/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3750.10 +*Want "MSEBR/MSEB NF -2.0/-QNaN/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3760.10 +*Want "MSEBR/MSEB NF -2.0/-QNaN/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3770.10 +*Want "MSEBR/MSEB NF -2.0/-QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3780.10 +*Want "MSEBR/MSEB NF -2.0/+SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3790.10 +*Want "MSEBR/MSEB NF -2.0/+SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 37A0.10 +*Want "MSEBR/MSEB NF -2.0/+SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 37B0.10 +*Want "MSEBR/MSEB NF -2.0/+SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 37C0.10 +*Want "MSEBR/MSEB NF -2.0/+SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 37D0.10 +*Want "MSEBR/MSEB NF -2.0/+SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 37E0.10 +*Want "MSEBR/MSEB NF -2.0/+SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 37F0.10 +*Want "MSEBR/MSEB NF -2.0/+SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3800.10 +*Want "MSEBR/MSEB NF -0/-inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3810.10 +*Want "MSEBR/MSEB NF -0/-inf/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3820.10 +*Want "MSEBR/MSEB NF -0/-inf/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3830.10 +*Want "MSEBR/MSEB NF -0/-inf/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3840.10 +*Want "MSEBR/MSEB NF -0/-inf/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3850.10 +*Want "MSEBR/MSEB NF -0/-inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3860.10 +*Want "MSEBR/MSEB NF -0/-inf/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3870.10 +*Want "MSEBR/MSEB NF -0/-inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3880.10 +*Want "MSEBR/MSEB NF -0/-2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3890.10 +*Want "MSEBR/MSEB NF -0/-2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 38A0.10 +*Want "MSEBR/MSEB NF -0/-2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 38B0.10 +*Want "MSEBR/MSEB NF -0/-2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 38C0.10 +*Want "MSEBR/MSEB NF -0/-2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 38D0.10 +*Want "MSEBR/MSEB NF -0/-2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 38E0.10 +*Want "MSEBR/MSEB NF -0/-2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 38F0.10 +*Want "MSEBR/MSEB NF -0/-2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3900.10 +*Want "MSEBR/MSEB NF -0/-0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3910.10 +*Want "MSEBR/MSEB NF -0/-0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3920.10 +*Want "MSEBR/MSEB NF -0/-0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3930.10 +*Want "MSEBR/MSEB NF -0/-0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3940.10 +*Want "MSEBR/MSEB NF -0/-0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3950.10 +*Want "MSEBR/MSEB NF -0/-0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3960.10 +*Want "MSEBR/MSEB NF -0/-0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3970.10 +*Want "MSEBR/MSEB NF -0/-0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3980.10 +*Want "MSEBR/MSEB NF -0/+0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3990.10 +*Want "MSEBR/MSEB NF -0/+0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 39A0.10 +*Want "MSEBR/MSEB NF -0/+0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 39B0.10 +*Want "MSEBR/MSEB NF -0/+0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 39C0.10 +*Want "MSEBR/MSEB NF -0/+0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 39D0.10 +*Want "MSEBR/MSEB NF -0/+0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 39E0.10 +*Want "MSEBR/MSEB NF -0/+0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 39F0.10 +*Want "MSEBR/MSEB NF -0/+0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3A00.10 +*Want "MSEBR/MSEB NF -0/+2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3A10.10 +*Want "MSEBR/MSEB NF -0/+2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3A20.10 +*Want "MSEBR/MSEB NF -0/+2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3A30.10 +*Want "MSEBR/MSEB NF -0/+2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3A40.10 +*Want "MSEBR/MSEB NF -0/+2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3A50.10 +*Want "MSEBR/MSEB NF -0/+2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3A60.10 +*Want "MSEBR/MSEB NF -0/+2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3A70.10 +*Want "MSEBR/MSEB NF -0/+2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3A80.10 +*Want "MSEBR/MSEB NF -0/+inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3A90.10 +*Want "MSEBR/MSEB NF -0/+inf/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3AA0.10 +*Want "MSEBR/MSEB NF -0/+inf/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3AB0.10 +*Want "MSEBR/MSEB NF -0/+inf/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3AC0.10 +*Want "MSEBR/MSEB NF -0/+inf/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3AD0.10 +*Want "MSEBR/MSEB NF -0/+inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3AE0.10 +*Want "MSEBR/MSEB NF -0/+inf/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3AF0.10 +*Want "MSEBR/MSEB NF -0/+inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3B00.10 +*Want "MSEBR/MSEB NF -0/-QNaN/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3B10.10 +*Want "MSEBR/MSEB NF -0/-QNaN/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3B20.10 +*Want "MSEBR/MSEB NF -0/-QNaN/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3B30.10 +*Want "MSEBR/MSEB NF -0/-QNaN/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3B40.10 +*Want "MSEBR/MSEB NF -0/-QNaN/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3B50.10 +*Want "MSEBR/MSEB NF -0/-QNaN/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3B60.10 +*Want "MSEBR/MSEB NF -0/-QNaN/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3B70.10 +*Want "MSEBR/MSEB NF -0/-QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3B80.10 +*Want "MSEBR/MSEB NF -0/+SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3B90.10 +*Want "MSEBR/MSEB NF -0/+SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3BA0.10 +*Want "MSEBR/MSEB NF -0/+SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3BB0.10 +*Want "MSEBR/MSEB NF -0/+SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3BC0.10 +*Want "MSEBR/MSEB NF -0/+SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3BD0.10 +*Want "MSEBR/MSEB NF -0/+SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3BE0.10 +*Want "MSEBR/MSEB NF -0/+SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3BF0.10 +*Want "MSEBR/MSEB NF -0/+SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3C00.10 +*Want "MSEBR/MSEB NF +0/-inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3C10.10 +*Want "MSEBR/MSEB NF +0/-inf/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3C20.10 +*Want "MSEBR/MSEB NF +0/-inf/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3C30.10 +*Want "MSEBR/MSEB NF +0/-inf/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3C40.10 +*Want "MSEBR/MSEB NF +0/-inf/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3C50.10 +*Want "MSEBR/MSEB NF +0/-inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3C60.10 +*Want "MSEBR/MSEB NF +0/-inf/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3C70.10 +*Want "MSEBR/MSEB NF +0/-inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3C80.10 +*Want "MSEBR/MSEB NF +0/-2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3C90.10 +*Want "MSEBR/MSEB NF +0/-2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3CA0.10 +*Want "MSEBR/MSEB NF +0/-2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3CB0.10 +*Want "MSEBR/MSEB NF +0/-2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3CC0.10 +*Want "MSEBR/MSEB NF +0/-2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3CD0.10 +*Want "MSEBR/MSEB NF +0/-2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3CE0.10 +*Want "MSEBR/MSEB NF +0/-2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3CF0.10 +*Want "MSEBR/MSEB NF +0/-2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3D00.10 +*Want "MSEBR/MSEB NF +0/-0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3D10.10 +*Want "MSEBR/MSEB NF +0/-0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3D20.10 +*Want "MSEBR/MSEB NF +0/-0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3D30.10 +*Want "MSEBR/MSEB NF +0/-0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3D40.10 +*Want "MSEBR/MSEB NF +0/-0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3D50.10 +*Want "MSEBR/MSEB NF +0/-0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3D60.10 +*Want "MSEBR/MSEB NF +0/-0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3D70.10 +*Want "MSEBR/MSEB NF +0/-0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3D80.10 +*Want "MSEBR/MSEB NF +0/+0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3D90.10 +*Want "MSEBR/MSEB NF +0/+0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3DA0.10 +*Want "MSEBR/MSEB NF +0/+0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3DB0.10 +*Want "MSEBR/MSEB NF +0/+0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3DC0.10 +*Want "MSEBR/MSEB NF +0/+0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3DD0.10 +*Want "MSEBR/MSEB NF +0/+0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3DE0.10 +*Want "MSEBR/MSEB NF +0/+0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3DF0.10 +*Want "MSEBR/MSEB NF +0/+0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3E00.10 +*Want "MSEBR/MSEB NF +0/+2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3E10.10 +*Want "MSEBR/MSEB NF +0/+2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3E20.10 +*Want "MSEBR/MSEB NF +0/+2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3E30.10 +*Want "MSEBR/MSEB NF +0/+2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3E40.10 +*Want "MSEBR/MSEB NF +0/+2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3E50.10 +*Want "MSEBR/MSEB NF +0/+2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3E60.10 +*Want "MSEBR/MSEB NF +0/+2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3E70.10 +*Want "MSEBR/MSEB NF +0/+2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3E80.10 +*Want "MSEBR/MSEB NF +0/+inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3E90.10 +*Want "MSEBR/MSEB NF +0/+inf/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3EA0.10 +*Want "MSEBR/MSEB NF +0/+inf/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3EB0.10 +*Want "MSEBR/MSEB NF +0/+inf/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3EC0.10 +*Want "MSEBR/MSEB NF +0/+inf/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3ED0.10 +*Want "MSEBR/MSEB NF +0/+inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3EE0.10 +*Want "MSEBR/MSEB NF +0/+inf/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3EF0.10 +*Want "MSEBR/MSEB NF +0/+inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3F00.10 +*Want "MSEBR/MSEB NF +0/-QNaN/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3F10.10 +*Want "MSEBR/MSEB NF +0/-QNaN/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3F20.10 +*Want "MSEBR/MSEB NF +0/-QNaN/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3F30.10 +*Want "MSEBR/MSEB NF +0/-QNaN/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3F40.10 +*Want "MSEBR/MSEB NF +0/-QNaN/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 3F50.10 +*Want "MSEBR/MSEB NF +0/-QNaN/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 3F60.10 +*Want "MSEBR/MSEB NF +0/-QNaN/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 3F70.10 +*Want "MSEBR/MSEB NF +0/-QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3F80.10 +*Want "MSEBR/MSEB NF +0/+SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3F90.10 +*Want "MSEBR/MSEB NF +0/+SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3FA0.10 +*Want "MSEBR/MSEB NF +0/+SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3FB0.10 +*Want "MSEBR/MSEB NF +0/+SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3FC0.10 +*Want "MSEBR/MSEB NF +0/+SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 3FD0.10 +*Want "MSEBR/MSEB NF +0/+SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 3FE0.10 +*Want "MSEBR/MSEB NF +0/+SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 3FF0.10 +*Want "MSEBR/MSEB NF +0/+SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4000.10 +*Want "MSEBR/MSEB NF +2.0/-inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4010.10 +*Want "MSEBR/MSEB NF +2.0/-inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4020.10 +*Want "MSEBR/MSEB NF +2.0/-inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4030.10 +*Want "MSEBR/MSEB NF +2.0/-inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4040.10 +*Want "MSEBR/MSEB NF +2.0/-inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4050.10 +*Want "MSEBR/MSEB NF +2.0/-inf/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4060.10 +*Want "MSEBR/MSEB NF +2.0/-inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 4070.10 +*Want "MSEBR/MSEB NF +2.0/-inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4080.10 +*Want "MSEBR/MSEB NF +2.0/-2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4090.10 +*Want "MSEBR/MSEB NF +2.0/-2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 40A0.10 +*Want "MSEBR/MSEB NF +2.0/-2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 40B0.10 +*Want "MSEBR/MSEB NF +2.0/-2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 40C0.10 +*Want "MSEBR/MSEB NF +2.0/-2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 40D0.10 +*Want "MSEBR/MSEB NF +2.0/-2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 40E0.10 +*Want "MSEBR/MSEB NF +2.0/-2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 40F0.10 +*Want "MSEBR/MSEB NF +2.0/-2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4100.10 +*Want "MSEBR/MSEB NF +2.0/-0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4110.10 +*Want "MSEBR/MSEB NF +2.0/-0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4120.10 +*Want "MSEBR/MSEB NF +2.0/-0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4130.10 +*Want "MSEBR/MSEB NF +2.0/-0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4140.10 +*Want "MSEBR/MSEB NF +2.0/-0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4150.10 +*Want "MSEBR/MSEB NF +2.0/-0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4160.10 +*Want "MSEBR/MSEB NF +2.0/-0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 4170.10 +*Want "MSEBR/MSEB NF +2.0/-0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4180.10 +*Want "MSEBR/MSEB NF +2.0/+0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4190.10 +*Want "MSEBR/MSEB NF +2.0/+0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 41A0.10 +*Want "MSEBR/MSEB NF +2.0/+0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 41B0.10 +*Want "MSEBR/MSEB NF +2.0/+0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 41C0.10 +*Want "MSEBR/MSEB NF +2.0/+0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 41D0.10 +*Want "MSEBR/MSEB NF +2.0/+0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 41E0.10 +*Want "MSEBR/MSEB NF +2.0/+0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 41F0.10 +*Want "MSEBR/MSEB NF +2.0/+0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4200.10 +*Want "MSEBR/MSEB NF +2.0/+2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4210.10 +*Want "MSEBR/MSEB NF +2.0/+2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4220.10 +*Want "MSEBR/MSEB NF +2.0/+2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4230.10 +*Want "MSEBR/MSEB NF +2.0/+2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4240.10 +*Want "MSEBR/MSEB NF +2.0/+2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4250.10 +*Want "MSEBR/MSEB NF +2.0/+2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4260.10 +*Want "MSEBR/MSEB NF +2.0/+2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 4270.10 +*Want "MSEBR/MSEB NF +2.0/+2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4280.10 +*Want "MSEBR/MSEB NF +2.0/+inf/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4290.10 +*Want "MSEBR/MSEB NF +2.0/+inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 42A0.10 +*Want "MSEBR/MSEB NF +2.0/+inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 42B0.10 +*Want "MSEBR/MSEB NF +2.0/+inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 42C0.10 +*Want "MSEBR/MSEB NF +2.0/+inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 42D0.10 +*Want "MSEBR/MSEB NF +2.0/+inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 42E0.10 +*Want "MSEBR/MSEB NF +2.0/+inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 42F0.10 +*Want "MSEBR/MSEB NF +2.0/+inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4300.10 +*Want "MSEBR/MSEB NF +2.0/-QNaN/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4310.10 +*Want "MSEBR/MSEB NF +2.0/-QNaN/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4320.10 +*Want "MSEBR/MSEB NF +2.0/-QNaN/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4330.10 +*Want "MSEBR/MSEB NF +2.0/-QNaN/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4340.10 +*Want "MSEBR/MSEB NF +2.0/-QNaN/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4350.10 +*Want "MSEBR/MSEB NF +2.0/-QNaN/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4360.10 +*Want "MSEBR/MSEB NF +2.0/-QNaN/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 4370.10 +*Want "MSEBR/MSEB NF +2.0/-QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4380.10 +*Want "MSEBR/MSEB NF +2.0/+SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4390.10 +*Want "MSEBR/MSEB NF +2.0/+SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 43A0.10 +*Want "MSEBR/MSEB NF +2.0/+SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 43B0.10 +*Want "MSEBR/MSEB NF +2.0/+SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 43C0.10 +*Want "MSEBR/MSEB NF +2.0/+SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 43D0.10 +*Want "MSEBR/MSEB NF +2.0/+SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 43E0.10 +*Want "MSEBR/MSEB NF +2.0/+SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 43F0.10 +*Want "MSEBR/MSEB NF +2.0/+SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4400.10 +*Want "MSEBR/MSEB NF +inf/-inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4410.10 +*Want "MSEBR/MSEB NF +inf/-inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4420.10 +*Want "MSEBR/MSEB NF +inf/-inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4430.10 +*Want "MSEBR/MSEB NF +inf/-inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4440.10 +*Want "MSEBR/MSEB NF +inf/-inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4450.10 +*Want "MSEBR/MSEB NF +inf/-inf/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4460.10 +*Want "MSEBR/MSEB NF +inf/-inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 4470.10 +*Want "MSEBR/MSEB NF +inf/-inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4480.10 +*Want "MSEBR/MSEB NF +inf/-2.0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4490.10 +*Want "MSEBR/MSEB NF +inf/-2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 44A0.10 +*Want "MSEBR/MSEB NF +inf/-2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 44B0.10 +*Want "MSEBR/MSEB NF +inf/-2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 44C0.10 +*Want "MSEBR/MSEB NF +inf/-2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 44D0.10 +*Want "MSEBR/MSEB NF +inf/-2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 44E0.10 +*Want "MSEBR/MSEB NF +inf/-2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 44F0.10 +*Want "MSEBR/MSEB NF +inf/-2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4500.10 +*Want "MSEBR/MSEB NF +inf/-0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4510.10 +*Want "MSEBR/MSEB NF +inf/-0/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4520.10 +*Want "MSEBR/MSEB NF +inf/-0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4530.10 +*Want "MSEBR/MSEB NF +inf/-0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4540.10 +*Want "MSEBR/MSEB NF +inf/-0/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4550.10 +*Want "MSEBR/MSEB NF +inf/-0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4560.10 +*Want "MSEBR/MSEB NF +inf/-0/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4570.10 +*Want "MSEBR/MSEB NF +inf/-0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4580.10 +*Want "MSEBR/MSEB NF +inf/+0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4590.10 +*Want "MSEBR/MSEB NF +inf/+0/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 45A0.10 +*Want "MSEBR/MSEB NF +inf/+0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 45B0.10 +*Want "MSEBR/MSEB NF +inf/+0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 45C0.10 +*Want "MSEBR/MSEB NF +inf/+0/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 45D0.10 +*Want "MSEBR/MSEB NF +inf/+0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 45E0.10 +*Want "MSEBR/MSEB NF +inf/+0/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 45F0.10 +*Want "MSEBR/MSEB NF +inf/+0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4600.10 +*Want "MSEBR/MSEB NF +inf/+2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4610.10 +*Want "MSEBR/MSEB NF +inf/+2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4620.10 +*Want "MSEBR/MSEB NF +inf/+2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4630.10 +*Want "MSEBR/MSEB NF +inf/+2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4640.10 +*Want "MSEBR/MSEB NF +inf/+2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4650.10 +*Want "MSEBR/MSEB NF +inf/+2.0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4660.10 +*Want "MSEBR/MSEB NF +inf/+2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 4670.10 +*Want "MSEBR/MSEB NF +inf/+2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4680.10 +*Want "MSEBR/MSEB NF +inf/+inf/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4690.10 +*Want "MSEBR/MSEB NF +inf/+inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 46A0.10 +*Want "MSEBR/MSEB NF +inf/+inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 46B0.10 +*Want "MSEBR/MSEB NF +inf/+inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 46C0.10 +*Want "MSEBR/MSEB NF +inf/+inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 46D0.10 +*Want "MSEBR/MSEB NF +inf/+inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 46E0.10 +*Want "MSEBR/MSEB NF +inf/+inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 46F0.10 +*Want "MSEBR/MSEB NF +inf/+inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4700.10 +*Want "MSEBR/MSEB NF +inf/-QNaN/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4710.10 +*Want "MSEBR/MSEB NF +inf/-QNaN/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4720.10 +*Want "MSEBR/MSEB NF +inf/-QNaN/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4730.10 +*Want "MSEBR/MSEB NF +inf/-QNaN/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4740.10 +*Want "MSEBR/MSEB NF +inf/-QNaN/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4750.10 +*Want "MSEBR/MSEB NF +inf/-QNaN/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4760.10 +*Want "MSEBR/MSEB NF +inf/-QNaN/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 4770.10 +*Want "MSEBR/MSEB NF +inf/-QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4780.10 +*Want "MSEBR/MSEB NF +inf/+SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4790.10 +*Want "MSEBR/MSEB NF +inf/+SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 47A0.10 +*Want "MSEBR/MSEB NF +inf/+SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 47B0.10 +*Want "MSEBR/MSEB NF +inf/+SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 47C0.10 +*Want "MSEBR/MSEB NF +inf/+SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 47D0.10 +*Want "MSEBR/MSEB NF +inf/+SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 47E0.10 +*Want "MSEBR/MSEB NF +inf/+SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 47F0.10 +*Want "MSEBR/MSEB NF +inf/+SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4800.10 +*Want "MSEBR/MSEB NF -QNaN/-inf/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4810.10 +*Want "MSEBR/MSEB NF -QNaN/-inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4820.10 +*Want "MSEBR/MSEB NF -QNaN/-inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4830.10 +*Want "MSEBR/MSEB NF -QNaN/-inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4840.10 +*Want "MSEBR/MSEB NF -QNaN/-inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4850.10 +*Want "MSEBR/MSEB NF -QNaN/-inf/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4860.10 +*Want "MSEBR/MSEB NF -QNaN/-inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 4870.10 +*Want "MSEBR/MSEB NF -QNaN/-inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4880.10 +*Want "MSEBR/MSEB NF -QNaN/-2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4890.10 +*Want "MSEBR/MSEB NF -QNaN/-2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 48A0.10 +*Want "MSEBR/MSEB NF -QNaN/-2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 48B0.10 +*Want "MSEBR/MSEB NF -QNaN/-2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 48C0.10 +*Want "MSEBR/MSEB NF -QNaN/-2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 48D0.10 +*Want "MSEBR/MSEB NF -QNaN/-2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 48E0.10 +*Want "MSEBR/MSEB NF -QNaN/-2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 48F0.10 +*Want "MSEBR/MSEB NF -QNaN/-2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4900.10 +*Want "MSEBR/MSEB NF -QNaN/-0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4910.10 +*Want "MSEBR/MSEB NF -QNaN/-0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4920.10 +*Want "MSEBR/MSEB NF -QNaN/-0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4930.10 +*Want "MSEBR/MSEB NF -QNaN/-0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4940.10 +*Want "MSEBR/MSEB NF -QNaN/-0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4950.10 +*Want "MSEBR/MSEB NF -QNaN/-0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4960.10 +*Want "MSEBR/MSEB NF -QNaN/-0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 4970.10 +*Want "MSEBR/MSEB NF -QNaN/-0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4980.10 +*Want "MSEBR/MSEB NF -QNaN/+0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4990.10 +*Want "MSEBR/MSEB NF -QNaN/+0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 49A0.10 +*Want "MSEBR/MSEB NF -QNaN/+0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 49B0.10 +*Want "MSEBR/MSEB NF -QNaN/+0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 49C0.10 +*Want "MSEBR/MSEB NF -QNaN/+0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 49D0.10 +*Want "MSEBR/MSEB NF -QNaN/+0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 49E0.10 +*Want "MSEBR/MSEB NF -QNaN/+0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 49F0.10 +*Want "MSEBR/MSEB NF -QNaN/+0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4A00.10 +*Want "MSEBR/MSEB NF -QNaN/+2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4A10.10 +*Want "MSEBR/MSEB NF -QNaN/+2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4A20.10 +*Want "MSEBR/MSEB NF -QNaN/+2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4A30.10 +*Want "MSEBR/MSEB NF -QNaN/+2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4A40.10 +*Want "MSEBR/MSEB NF -QNaN/+2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4A50.10 +*Want "MSEBR/MSEB NF -QNaN/+2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4A60.10 +*Want "MSEBR/MSEB NF -QNaN/+2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 4A70.10 +*Want "MSEBR/MSEB NF -QNaN/+2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4A80.10 +*Want "MSEBR/MSEB NF -QNaN/+inf/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4A90.10 +*Want "MSEBR/MSEB NF -QNaN/+inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4AA0.10 +*Want "MSEBR/MSEB NF -QNaN/+inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4AB0.10 +*Want "MSEBR/MSEB NF -QNaN/+inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4AC0.10 +*Want "MSEBR/MSEB NF -QNaN/+inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4AD0.10 +*Want "MSEBR/MSEB NF -QNaN/+inf/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4AE0.10 +*Want "MSEBR/MSEB NF -QNaN/+inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 4AF0.10 +*Want "MSEBR/MSEB NF -QNaN/+inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4B00.10 +*Want "MSEBR/MSEB NF -QNaN/-QNaN/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4B10.10 +*Want "MSEBR/MSEB NF -QNaN/-QNaN/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4B20.10 +*Want "MSEBR/MSEB NF -QNaN/-QNaN/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4B30.10 +*Want "MSEBR/MSEB NF -QNaN/-QNaN/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4B40.10 +*Want "MSEBR/MSEB NF -QNaN/-QNaN/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r 4B50.10 +*Want "MSEBR/MSEB NF -QNaN/-QNaN/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r 4B60.10 +*Want "MSEBR/MSEB NF -QNaN/-QNaN/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r 4B70.10 +*Want "MSEBR/MSEB NF -QNaN/-QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4B80.10 +*Want "MSEBR/MSEB NF -QNaN/+SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4B90.10 +*Want "MSEBR/MSEB NF -QNaN/+SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4BA0.10 +*Want "MSEBR/MSEB NF -QNaN/+SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4BB0.10 +*Want "MSEBR/MSEB NF -QNaN/+SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4BC0.10 +*Want "MSEBR/MSEB NF -QNaN/+SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4BD0.10 +*Want "MSEBR/MSEB NF -QNaN/+SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4BE0.10 +*Want "MSEBR/MSEB NF -QNaN/+SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4BF0.10 +*Want "MSEBR/MSEB NF -QNaN/+SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4C00.10 +*Want "MSEBR/MSEB NF +SNaN/-inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4C10.10 +*Want "MSEBR/MSEB NF +SNaN/-inf/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4C20.10 +*Want "MSEBR/MSEB NF +SNaN/-inf/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4C30.10 +*Want "MSEBR/MSEB NF +SNaN/-inf/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4C40.10 +*Want "MSEBR/MSEB NF +SNaN/-inf/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4C50.10 +*Want "MSEBR/MSEB NF +SNaN/-inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4C60.10 +*Want "MSEBR/MSEB NF +SNaN/-inf/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4C70.10 +*Want "MSEBR/MSEB NF +SNaN/-inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4C80.10 +*Want "MSEBR/MSEB NF +SNaN/-2.0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4C90.10 +*Want "MSEBR/MSEB NF +SNaN/-2.0/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4CA0.10 +*Want "MSEBR/MSEB NF +SNaN/-2.0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4CB0.10 +*Want "MSEBR/MSEB NF +SNaN/-2.0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4CC0.10 +*Want "MSEBR/MSEB NF +SNaN/-2.0/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4CD0.10 +*Want "MSEBR/MSEB NF +SNaN/-2.0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4CE0.10 +*Want "MSEBR/MSEB NF +SNaN/-2.0/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4CF0.10 +*Want "MSEBR/MSEB NF +SNaN/-2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4D00.10 +*Want "MSEBR/MSEB NF +SNaN/-0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4D10.10 +*Want "MSEBR/MSEB NF +SNaN/-0/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4D20.10 +*Want "MSEBR/MSEB NF +SNaN/-0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4D30.10 +*Want "MSEBR/MSEB NF +SNaN/-0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4D40.10 +*Want "MSEBR/MSEB NF +SNaN/-0/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4D50.10 +*Want "MSEBR/MSEB NF +SNaN/-0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4D60.10 +*Want "MSEBR/MSEB NF +SNaN/-0/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4D70.10 +*Want "MSEBR/MSEB NF +SNaN/-0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4D80.10 +*Want "MSEBR/MSEB NF +SNaN/+0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4D90.10 +*Want "MSEBR/MSEB NF +SNaN/+0/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4DA0.10 +*Want "MSEBR/MSEB NF +SNaN/+0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4DB0.10 +*Want "MSEBR/MSEB NF +SNaN/+0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4DC0.10 +*Want "MSEBR/MSEB NF +SNaN/+0/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4DD0.10 +*Want "MSEBR/MSEB NF +SNaN/+0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4DE0.10 +*Want "MSEBR/MSEB NF +SNaN/+0/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4DF0.10 +*Want "MSEBR/MSEB NF +SNaN/+0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4E00.10 +*Want "MSEBR/MSEB NF +SNaN/+2.0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4E10.10 +*Want "MSEBR/MSEB NF +SNaN/+2.0/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4E20.10 +*Want "MSEBR/MSEB NF +SNaN/+2.0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4E30.10 +*Want "MSEBR/MSEB NF +SNaN/+2.0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4E40.10 +*Want "MSEBR/MSEB NF +SNaN/+2.0/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4E50.10 +*Want "MSEBR/MSEB NF +SNaN/+2.0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4E60.10 +*Want "MSEBR/MSEB NF +SNaN/+2.0/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4E70.10 +*Want "MSEBR/MSEB NF +SNaN/+2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4E80.10 +*Want "MSEBR/MSEB NF +SNaN/+inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4E90.10 +*Want "MSEBR/MSEB NF +SNaN/+inf/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4EA0.10 +*Want "MSEBR/MSEB NF +SNaN/+inf/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4EB0.10 +*Want "MSEBR/MSEB NF +SNaN/+inf/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4EC0.10 +*Want "MSEBR/MSEB NF +SNaN/+inf/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4ED0.10 +*Want "MSEBR/MSEB NF +SNaN/+inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4EE0.10 +*Want "MSEBR/MSEB NF +SNaN/+inf/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4EF0.10 +*Want "MSEBR/MSEB NF +SNaN/+inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4F00.10 +*Want "MSEBR/MSEB NF +SNaN/-QNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4F10.10 +*Want "MSEBR/MSEB NF +SNaN/-QNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4F20.10 +*Want "MSEBR/MSEB NF +SNaN/-QNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4F30.10 +*Want "MSEBR/MSEB NF +SNaN/-QNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4F40.10 +*Want "MSEBR/MSEB NF +SNaN/-QNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4F50.10 +*Want "MSEBR/MSEB NF +SNaN/-QNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4F60.10 +*Want "MSEBR/MSEB NF +SNaN/-QNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4F70.10 +*Want "MSEBR/MSEB NF +SNaN/-QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4F80.10 +*Want "MSEBR/MSEB NF +SNaN/+SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4F90.10 +*Want "MSEBR/MSEB NF +SNaN/+SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4FA0.10 +*Want "MSEBR/MSEB NF +SNaN/+SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4FB0.10 +*Want "MSEBR/MSEB NF +SNaN/+SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4FC0.10 +*Want "MSEBR/MSEB NF +SNaN/+SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r 4FD0.10 +*Want "MSEBR/MSEB NF +SNaN/+SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r 4FE0.10 +*Want "MSEBR/MSEB NF +SNaN/+SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r 4FF0.10 +*Want "MSEBR/MSEB NF +SNaN/+SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 + + + +# Short BFP Multiply And Subtract finite results +*Compare +r 5000.10 +*Want "MSEBR/MSEB F Ovfl 1" FF800000 DF7FFFFE FF800000 DF7FFFFE +r 5010.10 +*Want "MSEBR/MSEB F Ovfl 2" FF800000 9FFFFFFF FF800000 9FFFFFFF +r 5020.10 +*Want "MSEBR/MSEB F Ufl 1" 80400001 E0000002 80400001 E0000002 +r 5030.10 +*Want "MSEBR/MSEB F Ufl 2" 003FFFFE 5FFFFFFA 003FFFFE 5FFFFFFA +r 5040.10 +*Want "MSEBR/MSEB F Nmin" 00BFFFFE 00BFFFFE 00BFFFFE 00BFFFFE +r 5050.10 +*Want "MSEBR/MSEB F Incr" BFC8000D BFC8000D BFC8000D BFC8000D +r 5060.10 +*Want "MSEBR/MSEB F Trun" BFC80007 BFC80007 BFC80007 BFC80007 + + +# Short BFP Multiply And Subtract finite results - FPCR contents +*Compare +r 5100.10 +*Want "MSEBR/MSEB F Ovfl 1 FPCR" 00280000 F8002800 00280000 F8002800 +r 5110.10 +*Want "MSEBR/MSEB F Ovfl 2 FPCR" 00280000 F8002000 00280000 F8002000 +r 5120.10 +*Want "MSEBR/MSEB F Ufl 1 FPCR" 00180000 F8001C00 00180000 F8001C00 +r 5130.10 +*Want "MSEBR/MSEB F Ufl 2 FPCR" 00180000 F8001000 00180000 F8001000 +r 5140.10 +*Want "MSEBR/MSEB F Nmin FPCR" 00000000 F8000000 00000000 F8000000 +r 5150.10 +*Want "MSEBR/MSEB F Incr FPCR" 00080000 F8000C00 00080000 F8000C00 +r 5160.10 +*Want "MSEBR/MSEB F Trun FPCR" 00080000 F8000800 00080000 F8000800 + + +# Short BFP Multiply And Subtract rounding mode results +*Compare +r 5200.10 +*Want "MSEBR/MSEB RM +NZ RNTE, RZ" 3FC80007 3FC80007 3FC80007 3FC80007 +r 5210.10 +*Want "MSEBR/MSEB RM +NZ RP, RM" 3FC80008 3FC80008 3FC80007 3FC80007 +r 5220.10 +*Want "MSEBR/MSEB RM +NZ RFS" 3FC80007 3FC80007 00000000 00000000 +r 5230.10 +*Want "MSEBR/MSEB RM -NZ RNTE, RZ" BFC80007 BFC80007 BFC80007 BFC80007 +r 5240.10 +*Want "MSEBR/MSEB RM -NZ RP, RM" BFC80007 BFC80007 BFC80008 BFC80008 +r 5250.10 +*Want "MSEBR/MSEB RM -NZ RFS" BFC80007 BFC80007 00000000 00000000 +r 5260.10 +*Want "MSEBR/MSEB RM +NA RNTE, RZ" 3FC8000D 3FC8000D 3FC8000C 3FC8000C +r 5270.10 +*Want "MSEBR/MSEB RM +NA RP, RM" 3FC8000D 3FC8000D 3FC8000C 3FC8000C +r 5280.10 +*Want "MSEBR/MSEB RM +NA RFS" 3FC8000D 3FC8000D 00000000 00000000 +r 5290.10 +*Want "MSEBR/MSEB RM -NA RNTE, RZ" BFC8000D BFC8000D BFC8000C BFC8000C +r 52A0.10 +*Want "MSEBR/MSEB RM -NA RP, RM" BFC8000C BFC8000C BFC8000D BFC8000D +r 52B0.10 +*Want "MSEBR/MSEB RM -NA RFS" BFC8000D BFC8000D 00000000 00000000 +r 52C0.10 +*Want "MSEBR/MSEB RM +TZ RNTE, RZ" 3FC80008 3FC80008 3FC80008 3FC80008 +r 52D0.10 +*Want "MSEBR/MSEB RM +TZ RP, RM" 3FC80009 3FC80009 3FC80008 3FC80008 +r 52E0.10 +*Want "MSEBR/MSEB RM +TZ RFS" 3FC80009 3FC80009 00000000 00000000 +r 52F0.10 +*Want "MSEBR/MSEB RM -TZ RNTE, RZ" BFC80008 BFC80008 BFC80008 BFC80008 +r 5300.10 +*Want "MSEBR/MSEB RM -TZ RP, RM" BFC80008 BFC80008 BFC80009 BFC80009 +r 5310.10 +*Want "MSEBR/MSEB RM -TZ RFS" BFC80009 BFC80009 00000000 00000000 +r 5320.10 +*Want "MSEBR/MSEB RM +TA RNTE, RZ" 3FC8001A 3FC8001A 3FC80019 3FC80019 +r 5330.10 +*Want "MSEBR/MSEB RM +TA RP, RM" 3FC8001A 3FC8001A 3FC80019 3FC80019 +r 5340.10 +*Want "MSEBR/MSEB RM +TA RFS" 3FC80019 3FC80019 00000000 00000000 +r 5350.10 +*Want "MSEBR/MSEB RM -TA RNTE, RZ" BFC8001A BFC8001A BFC80019 BFC80019 +r 5360.10 +*Want "MSEBR/MSEB RM -TA RP, RM" BFC80019 BFC80019 BFC8001A BFC8001A +r 5370.10 +*Want "MSEBR/MSEB RM -TA RFS" BFC80019 BFC80019 00000000 00000000 + + +# Short BFP Multiply And Subtract rounding mode results - FPCR contents +*Compare +r 5500.10 +*Want "MSEBR/MSEB RM +NZ RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r 5510.10 +*Want "MSEBR/MSEB RM +NZ RP, RM FPCR" 00080002 00080002 00080003 00080003 +r 5520.10 +*Want "MSEBR/MSEB RM +NZ RFS FPCR" 00080007 00080007 00000000 00000000 +r 5530.10 +*Want "MSEBR/MSEB RM -NZ RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r 5540.10 +*Want "MSEBR/MSEB RM -NZ RP, RM FPCR" 00080002 00080002 00080003 00080003 +r 5550.10 +*Want "MSEBR/MSEB RM -NZ RFS FPCR" 00080007 00080007 00000000 00000000 +r 5560.10 +*Want "MSEBR/MSEB RM +NA RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r 5570.10 +*Want "MSEBR/MSEB RM +NA RP, RM FPCR" 00080002 00080002 00080003 00080003 +r 5580.10 +*Want "MSEBR/MSEB RM +NA RFS FPCR" 00080007 00080007 00000000 00000000 +r 5590.10 +*Want "MSEBR/MSEB RM -NA RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r 55A0.10 +*Want "MSEBR/MSEB RM -NA RP, RM FPCR" 00080002 00080002 00080003 00080003 +r 55B0.10 +*Want "MSEBR/MSEB RM -NA RFS FPCR" 00080007 00080007 00000000 00000000 +r 55C0.10 +*Want "MSEBR/MSEB RM +TZ RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r 55D0.10 +*Want "MSEBR/MSEB RM +TZ RP, RM FPCR" 00080002 00080002 00080003 00080003 +r 55E0.10 +*Want "MSEBR/MSEB RM +TZ RFS FPCR" 00080007 00080007 00000000 00000000 +r 55F0.10 +*Want "MSEBR/MSEB RM -TZ RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r 5600.10 +*Want "MSEBR/MSEB RM -TZ RP, RM FPCR" 00080002 00080002 00080003 00080003 +r 5610.10 +*Want "MSEBR/MSEB RM -TZ RFS FPCR" 00080007 00080007 00000000 00000000 +r 5620.10 +*Want "MSEBR/MSEB RM +TA RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r 5630.10 +*Want "MSEBR/MSEB RM +TA RP, RM FPCR" 00080002 00080002 00080003 00080003 +r 5640.10 +*Want "MSEBR/MSEB RM +TA RFS FPCR" 00080007 00080007 00000000 00000000 +r 5650.10 +*Want "MSEBR/MSEB RM -TA RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r 5660.10 +*Want "MSEBR/MSEB RM -TA RP, RM FPCR" 00080002 00080002 00080003 00080003 +r 5670.10 +*Want "MSEBR/MSEB RM -TA RFS FPCR" 00080007 00080007 00000000 00000000 + + +# Long BFP Multiply And Subtract non-finite finite results +*Compare +r 6000.10 +*Want "MSDBR NF -inf/-inf/-inf" 7FF00000 00000000 7FF00000 00000000 +r 6010.10 +*Want "MSDB NF -inf/-inf/-inf" 7FF00000 00000000 7FF00000 00000000 +r 6020.10 +*Want "MSDBR NF -inf/-inf/-2.0" 7FF00000 00000000 7FF00000 00000000 +r 6030.10 +*Want "MSDB NF -inf/-inf/-2.0" 7FF00000 00000000 7FF00000 00000000 +r 6040.10 +*Want "MSDBR NF -inf/-inf/-0" 7FF00000 00000000 7FF00000 00000000 +r 6050.10 +*Want "MSDB NF -inf/-inf/-0" 7FF00000 00000000 7FF00000 00000000 +r 6060.10 +*Want "MSDBR NF -inf/-inf/+0" 7FF00000 00000000 7FF00000 00000000 +r 6070.10 +*Want "MSDB NF -inf/-inf/+0" 7FF00000 00000000 7FF00000 00000000 +r 6080.10 +*Want "MSDBR NF -inf/-inf/+2.0" 7FF00000 00000000 7FF00000 00000000 +r 6090.10 +*Want "MSDB NF -inf/-inf/+2.0" 7FF00000 00000000 7FF00000 00000000 +r 60A0.10 +*Want "MSDBR NF -inf/-inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 60B0.10 +*Want "MSDB NF -inf/-inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 60C0.10 +*Want "MSDBR NF -inf/-inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 60D0.10 +*Want "MSDB NF -inf/-inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 60E0.10 +*Want "MSDBR NF -inf/-inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 60F0.10 +*Want "MSDB NF -inf/-inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6100.10 +*Want "MSDBR NF -inf/-2.0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 6110.10 +*Want "MSDB NF -inf/-2.0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 6120.10 +*Want "MSDBR NF -inf/-2.0/-2.0" 7FF00000 00000000 7FF00000 00000000 +r 6130.10 +*Want "MSDB NF -inf/-2.0/-2.0" 7FF00000 00000000 7FF00000 00000000 +r 6140.10 +*Want "MSDBR NF -inf/-2.0/-0" 7FF00000 00000000 7FF00000 00000000 +r 6150.10 +*Want "MSDB NF -inf/-2.0/-0" 7FF00000 00000000 7FF00000 00000000 +r 6160.10 +*Want "MSDBR NF -inf/-2.0/+0" 7FF00000 00000000 7FF00000 00000000 +r 6170.10 +*Want "MSDB NF -inf/-2.0/+0" 7FF00000 00000000 7FF00000 00000000 +r 6180.10 +*Want "MSDBR NF -inf/-2.0/+2.0" 7FF00000 00000000 7FF00000 00000000 +r 6190.10 +*Want "MSDB NF -inf/-2.0/+2.0" 7FF00000 00000000 7FF00000 00000000 +r 61A0.10 +*Want "MSDBR NF -inf/-2.0/+inf" 7FF80000 00000000 7FF00000 00000000 +r 61B0.10 +*Want "MSDB NF -inf/-2.0/+inf" 7FF80000 00000000 7FF00000 00000000 +r 61C0.10 +*Want "MSDBR NF -inf/-2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 61D0.10 +*Want "MSDB NF -inf/-2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 61E0.10 +*Want "MSDBR NF -inf/-2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 61F0.10 +*Want "MSDB NF -inf/-2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6200.10 +*Want "MSDBR NF -inf/-0/-inf" 7FF80000 00000000 FFF00000 00000000 +r 6210.10 +*Want "MSDB NF -inf/-0/-inf" 7FF80000 00000000 FFF00000 00000000 +r 6220.10 +*Want "MSDBR NF -inf/-0/-2.0" 7FF80000 00000000 C0000000 00000000 +r 6230.10 +*Want "MSDB NF -inf/-0/-2.0" 7FF80000 00000000 C0000000 00000000 +r 6240.10 +*Want "MSDBR NF -inf/-0/-0" 7FF80000 00000000 80000000 00000000 +r 6250.10 +*Want "MSDB NF -inf/-0/-0" 7FF80000 00000000 80000000 00000000 +r 6260.10 +*Want "MSDBR NF -inf/-0/+0" 7FF80000 00000000 00000000 00000000 +r 6270.10 +*Want "MSDB NF -inf/-0/+0" 7FF80000 00000000 00000000 00000000 +r 6280.10 +*Want "MSDBR NF -inf/-0/+2.0" 7FF80000 00000000 40000000 00000000 +r 6290.10 +*Want "MSDB NF -inf/-0/+2.0" 7FF80000 00000000 40000000 00000000 +r 62A0.10 +*Want "MSDBR NF -inf/-0/+inf" 7FF80000 00000000 7FF00000 00000000 +r 62B0.10 +*Want "MSDB NF -inf/-0/+inf" 7FF80000 00000000 7FF00000 00000000 +r 62C0.10 +*Want "MSDBR NF -inf/-0/-QNaN" 7FF80000 00000000 FFF8B000 00000000 +r 62D0.10 +*Want "MSDB NF -inf/-0/-QNaN" 7FF80000 00000000 FFF8B000 00000000 +r 62E0.10 +*Want "MSDBR NF -inf/-0/+SNaN" 7FF80000 00000000 7FF0A000 00000000 +r 62F0.10 +*Want "MSDB NF -inf/-0/+SNaN" 7FF80000 00000000 7FF0A000 00000000 +r 6300.10 +*Want "MSDBR NF -inf/+0/-inf" 7FF80000 00000000 FFF00000 00000000 +r 6310.10 +*Want "MSDB NF -inf/+0/-inf" 7FF80000 00000000 FFF00000 00000000 +r 6320.10 +*Want "MSDBR NF -inf/+0/-2.0" 7FF80000 00000000 C0000000 00000000 +r 6330.10 +*Want "MSDB NF -inf/+0/-2.0" 7FF80000 00000000 C0000000 00000000 +r 6340.10 +*Want "MSDBR NF -inf/+0/-0" 7FF80000 00000000 80000000 00000000 +r 6350.10 +*Want "MSDB NF -inf/+0/-0" 7FF80000 00000000 80000000 00000000 +r 6360.10 +*Want "MSDBR NF -inf/+0/+0" 7FF80000 00000000 00000000 00000000 +r 6370.10 +*Want "MSDB NF -inf/+0/+0" 7FF80000 00000000 00000000 00000000 +r 6380.10 +*Want "MSDBR NF -inf/+0/+2.0" 7FF80000 00000000 40000000 00000000 +r 6390.10 +*Want "MSDB NF -inf/+0/+2.0" 7FF80000 00000000 40000000 00000000 +r 63A0.10 +*Want "MSDBR NF -inf/+0/+inf" 7FF80000 00000000 7FF00000 00000000 +r 63B0.10 +*Want "MSDB NF -inf/+0/+inf" 7FF80000 00000000 7FF00000 00000000 +r 63C0.10 +*Want "MSDBR NF -inf/+0/-QNaN" 7FF80000 00000000 FFF8B000 00000000 +r 63D0.10 +*Want "MSDB NF -inf/+0/-QNaN" 7FF80000 00000000 FFF8B000 00000000 +r 63E0.10 +*Want "MSDBR NF -inf/+0/+SNaN" 7FF80000 00000000 7FF0A000 00000000 +r 63F0.10 +*Want "MSDB NF -inf/+0/+SNaN" 7FF80000 00000000 7FF0A000 00000000 +r 6400.10 +*Want "MSDBR NF -inf/+2.0/-inf" 7FF80000 00000000 FFF00000 00000000 +r 6410.10 +*Want "MSDB NF -inf/+2.0/-inf" 7FF80000 00000000 FFF00000 00000000 +r 6420.10 +*Want "MSDBR NF -inf/+2.0/-2.0" FFF00000 00000000 FFF00000 00000000 +r 6430.10 +*Want "MSDB NF -inf/+2.0/-2.0" FFF00000 00000000 FFF00000 00000000 +r 6440.10 +*Want "MSDBR NF -inf/+2.0/-0" FFF00000 00000000 FFF00000 00000000 +r 6450.10 +*Want "MSDB NF -inf/+2.0/-0" FFF00000 00000000 FFF00000 00000000 +r 6460.10 +*Want "MSDBR NF -inf/+2.0/+0" FFF00000 00000000 FFF00000 00000000 +r 6470.10 +*Want "MSDB NF -inf/+2.0/+0" FFF00000 00000000 FFF00000 00000000 +r 6480.10 +*Want "MSDBR NF -inf/+2.0/+2.0" FFF00000 00000000 FFF00000 00000000 +r 6490.10 +*Want "MSDB NF -inf/+2.0/+2.0" FFF00000 00000000 FFF00000 00000000 +r 64A0.10 +*Want "MSDBR NF -inf/+2.0/+inf" FFF00000 00000000 FFF00000 00000000 +r 64B0.10 +*Want "MSDB NF -inf/+2.0/+inf" FFF00000 00000000 FFF00000 00000000 +r 64C0.10 +*Want "MSDBR NF -inf/+2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 64D0.10 +*Want "MSDB NF -inf/+2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 64E0.10 +*Want "MSDBR NF -inf/+2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 64F0.10 +*Want "MSDB NF -inf/+2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6500.10 +*Want "MSDBR NF -inf/+inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 6510.10 +*Want "MSDB NF -inf/+inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 6520.10 +*Want "MSDBR NF -inf/+inf/-2.0" FFF00000 00000000 FFF00000 00000000 +r 6530.10 +*Want "MSDB NF -inf/+inf/-2.0" FFF00000 00000000 FFF00000 00000000 +r 6540.10 +*Want "MSDBR NF -inf/+inf/-0" FFF00000 00000000 FFF00000 00000000 +r 6550.10 +*Want "MSDB NF -inf/+inf/-0" FFF00000 00000000 FFF00000 00000000 +r 6560.10 +*Want "MSDBR NF -inf/+inf/+0" FFF00000 00000000 FFF00000 00000000 +r 6570.10 +*Want "MSDB NF -inf/+inf/+0" FFF00000 00000000 FFF00000 00000000 +r 6580.10 +*Want "MSDBR NF -inf/+inf/+2.0" FFF00000 00000000 FFF00000 00000000 +r 6590.10 +*Want "MSDB NF -inf/+inf/+2.0" FFF00000 00000000 FFF00000 00000000 +r 65A0.10 +*Want "MSDBR NF -inf/+inf/+inf" FFF00000 00000000 FFF00000 00000000 +r 65B0.10 +*Want "MSDB NF -inf/+inf/+inf" FFF00000 00000000 FFF00000 00000000 +r 65C0.10 +*Want "MSDBR NF -inf/+inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 65D0.10 +*Want "MSDB NF -inf/+inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 65E0.10 +*Want "MSDBR NF -inf/+inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 65F0.10 +*Want "MSDB NF -inf/+inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6600.10 +*Want "MSDBR NF -inf/-QNaN/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 6610.10 +*Want "MSDB NF -inf/-QNaN/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 6620.10 +*Want "MSDBR NF -inf/-QNaN/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 6630.10 +*Want "MSDB NF -inf/-QNaN/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 6640.10 +*Want "MSDBR NF -inf/-QNaN/-0" FFF8B000 00000000 FFF8B000 00000000 +r 6650.10 +*Want "MSDB NF -inf/-QNaN/-0" FFF8B000 00000000 FFF8B000 00000000 +r 6660.10 +*Want "MSDBR NF -inf/-QNaN/+0" FFF8B000 00000000 FFF8B000 00000000 +r 6670.10 +*Want "MSDB NF -inf/-QNaN/+0" FFF8B000 00000000 FFF8B000 00000000 +r 6680.10 +*Want "MSDBR NF -inf/-QNaN/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 6690.10 +*Want "MSDB NF -inf/-QNaN/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 66A0.10 +*Want "MSDBR NF -inf/-QNaN/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 66B0.10 +*Want "MSDB NF -inf/-QNaN/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 66C0.10 +*Want "MSDBR NF -inf/-QNaN/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 66D0.10 +*Want "MSDB NF -inf/-QNaN/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 66E0.10 +*Want "MSDBR NF -inf/-QNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 66F0.10 +*Want "MSDB NF -inf/-QNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6700.10 +*Want "MSDBR NF -inf/+SNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 6710.10 +*Want "MSDB NF -inf/+SNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 6720.10 +*Want "MSDBR NF -inf/+SNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 6730.10 +*Want "MSDB NF -inf/+SNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 6740.10 +*Want "MSDBR NF -inf/+SNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 6750.10 +*Want "MSDB NF -inf/+SNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 6760.10 +*Want "MSDBR NF -inf/+SNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 6770.10 +*Want "MSDB NF -inf/+SNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 6780.10 +*Want "MSDBR NF -inf/+SNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 6790.10 +*Want "MSDB NF -inf/+SNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 67A0.10 +*Want "MSDBR NF -inf/+SNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 67B0.10 +*Want "MSDB NF -inf/+SNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 67C0.10 +*Want "MSDBR NF -inf/+SNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 67D0.10 +*Want "MSDB NF -inf/+SNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 67E0.10 +*Want "MSDBR NF -inf/+SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 67F0.10 +*Want "MSDB NF -inf/+SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6800.10 +*Want "MSDBR NF -2.0/-inf/-inf" 7FF00000 00000000 7FF00000 00000000 +r 6810.10 +*Want "MSDB NF -2.0/-inf/-inf" 7FF00000 00000000 7FF00000 00000000 +r 6820.10 +*Want "MSDBR NF -2.0/-inf/-2.0" 7FF00000 00000000 7FF00000 00000000 +r 6830.10 +*Want "MSDB NF -2.0/-inf/-2.0" 7FF00000 00000000 7FF00000 00000000 +r 6840.10 +*Want "MSDBR NF -2.0/-inf/-0" 7FF00000 00000000 7FF00000 00000000 +r 6850.10 +*Want "MSDB NF -2.0/-inf/-0" 7FF00000 00000000 7FF00000 00000000 +r 6860.10 +*Want "MSDBR NF -2.0/-inf/+0" 7FF00000 00000000 7FF00000 00000000 +r 6870.10 +*Want "MSDB NF -2.0/-inf/+0" 7FF00000 00000000 7FF00000 00000000 +r 6880.10 +*Want "MSDBR NF -2.0/-inf/+2.0" 7FF00000 00000000 7FF00000 00000000 +r 6890.10 +*Want "MSDB NF -2.0/-inf/+2.0" 7FF00000 00000000 7FF00000 00000000 +r 68A0.10 +*Want "MSDBR NF -2.0/-inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 68B0.10 +*Want "MSDB NF -2.0/-inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 68C0.10 +*Want "MSDBR NF -2.0/-inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 68D0.10 +*Want "MSDB NF -2.0/-inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 68E0.10 +*Want "MSDBR NF -2.0/-inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 68F0.10 +*Want "MSDB NF -2.0/-inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6900.10 +*Want "MSDBR NF -2.0/-2.0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 6910.10 +*Want "MSDB NF -2.0/-2.0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 6920.10 +*Want "MSDBR NF -2.0/-2.0/-2.0" 40180000 00000000 40180000 00000000 +r 6930.10 +*Want "MSDB NF -2.0/-2.0/-2.0" 40180000 00000000 40180000 00000000 +r 6940.10 +*Want "MSDBR NF -2.0/-2.0/-0" 40100000 00000000 40100000 00000000 +r 6950.10 +*Want "MSDB NF -2.0/-2.0/-0" 40100000 00000000 40100000 00000000 +r 6960.10 +*Want "MSDBR NF -2.0/-2.0/+0" 40100000 00000000 40100000 00000000 +r 6970.10 +*Want "MSDB NF -2.0/-2.0/+0" 40100000 00000000 40100000 00000000 +r 6980.10 +*Want "MSDBR NF -2.0/-2.0/+2.0" 40000000 00000000 40000000 00000000 +r 6990.10 +*Want "MSDB NF -2.0/-2.0/+2.0" 40000000 00000000 40000000 00000000 +r 69A0.10 +*Want "MSDBR NF -2.0/-2.0/+inf" FFF00000 00000000 FFF00000 00000000 +r 69B0.10 +*Want "MSDB NF -2.0/-2.0/+inf" FFF00000 00000000 FFF00000 00000000 +r 69C0.10 +*Want "MSDBR NF -2.0/-2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 69D0.10 +*Want "MSDB NF -2.0/-2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 69E0.10 +*Want "MSDBR NF -2.0/-2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 69F0.10 +*Want "MSDB NF -2.0/-2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6A00.10 +*Want "MSDBR NF -2.0/-0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 6A10.10 +*Want "MSDB NF -2.0/-0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 6A20.10 +*Want "MSDBR NF -2.0/-0/-2.0" 40000000 00000000 40000000 00000000 +r 6A30.10 +*Want "MSDB NF -2.0/-0/-2.0" 40000000 00000000 40000000 00000000 +r 6A40.10 +*Want "MSDBR NF -2.0/-0/-0" 00000000 00000000 00000000 00000000 +r 6A50.10 +*Want "MSDB NF -2.0/-0/-0" 00000000 00000000 00000000 00000000 +r 6A60.10 +*Want "MSDBR NF -2.0/-0/+0" 00000000 00000000 00000000 00000000 +r 6A70.10 +*Want "MSDB NF -2.0/-0/+0" 00000000 00000000 00000000 00000000 +r 6A80.10 +*Want "MSDBR NF -2.0/-0/+2.0" C0000000 00000000 C0000000 00000000 +r 6A90.10 +*Want "MSDB NF -2.0/-0/+2.0" C0000000 00000000 C0000000 00000000 +r 6AA0.10 +*Want "MSDBR NF -2.0/-0/+inf" FFF00000 00000000 FFF00000 00000000 +r 6AB0.10 +*Want "MSDB NF -2.0/-0/+inf" FFF00000 00000000 FFF00000 00000000 +r 6AC0.10 +*Want "MSDBR NF -2.0/-0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 6AD0.10 +*Want "MSDB NF -2.0/-0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 6AE0.10 +*Want "MSDBR NF -2.0/-0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6AF0.10 +*Want "MSDB NF -2.0/-0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6B00.10 +*Want "MSDBR NF -2.0/+0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 6B10.10 +*Want "MSDB NF -2.0/+0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 6B20.10 +*Want "MSDBR NF -2.0/+0/-2.0" 40000000 00000000 40000000 00000000 +r 6B30.10 +*Want "MSDB NF -2.0/+0/-2.0" 40000000 00000000 40000000 00000000 +r 6B40.10 +*Want "MSDBR NF -2.0/+0/-0" 00000000 00000000 00000000 00000000 +r 6B50.10 +*Want "MSDB NF -2.0/+0/-0" 00000000 00000000 00000000 00000000 +r 6B60.10 +*Want "MSDBR NF -2.0/+0/+0" 80000000 00000000 80000000 00000000 +r 6B70.10 +*Want "MSDB NF -2.0/+0/+0" 80000000 00000000 80000000 00000000 +r 6B80.10 +*Want "MSDBR NF -2.0/+0/+2.0" C0000000 00000000 C0000000 00000000 +r 6B90.10 +*Want "MSDB NF -2.0/+0/+2.0" C0000000 00000000 C0000000 00000000 +r 6BA0.10 +*Want "MSDBR NF -2.0/+0/+inf" FFF00000 00000000 FFF00000 00000000 +r 6BB0.10 +*Want "MSDB NF -2.0/+0/+inf" FFF00000 00000000 FFF00000 00000000 +r 6BC0.10 +*Want "MSDBR NF -2.0/+0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 6BD0.10 +*Want "MSDB NF -2.0/+0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 6BE0.10 +*Want "MSDBR NF -2.0/+0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6BF0.10 +*Want "MSDB NF -2.0/+0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6C00.10 +*Want "MSDBR NF -2.0/+2.0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 6C10.10 +*Want "MSDB NF -2.0/+2.0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 6C20.10 +*Want "MSDBR NF -2.0/+2.0/-2.0" C0000000 00000000 C0000000 00000000 +r 6C30.10 +*Want "MSDB NF -2.0/+2.0/-2.0" C0000000 00000000 C0000000 00000000 +r 6C40.10 +*Want "MSDBR NF -2.0/+2.0/-0" C0100000 00000000 C0100000 00000000 +r 6C50.10 +*Want "MSDB NF -2.0/+2.0/-0" C0100000 00000000 C0100000 00000000 +r 6C60.10 +*Want "MSDBR NF -2.0/+2.0/+0" C0100000 00000000 C0100000 00000000 +r 6C70.10 +*Want "MSDB NF -2.0/+2.0/+0" C0100000 00000000 C0100000 00000000 +r 6C80.10 +*Want "MSDBR NF -2.0/+2.0/+2.0" C0180000 00000000 C0180000 00000000 +r 6C90.10 +*Want "MSDB NF -2.0/+2.0/+2.0" C0180000 00000000 C0180000 00000000 +r 6CA0.10 +*Want "MSDBR NF -2.0/+2.0/+inf" FFF00000 00000000 FFF00000 00000000 +r 6CB0.10 +*Want "MSDB NF -2.0/+2.0/+inf" FFF00000 00000000 FFF00000 00000000 +r 6CC0.10 +*Want "MSDBR NF -2.0/+2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 6CD0.10 +*Want "MSDB NF -2.0/+2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 6CE0.10 +*Want "MSDBR NF -2.0/+2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6CF0.10 +*Want "MSDB NF -2.0/+2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6D00.10 +*Want "MSDBR NF -2.0/+inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 6D10.10 +*Want "MSDB NF -2.0/+inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 6D20.10 +*Want "MSDBR NF -2.0/+inf/-2.0" FFF00000 00000000 FFF00000 00000000 +r 6D30.10 +*Want "MSDB NF -2.0/+inf/-2.0" FFF00000 00000000 FFF00000 00000000 +r 6D40.10 +*Want "MSDBR NF -2.0/+inf/-0" FFF00000 00000000 FFF00000 00000000 +r 6D50.10 +*Want "MSDB NF -2.0/+inf/-0" FFF00000 00000000 FFF00000 00000000 +r 6D60.10 +*Want "MSDBR NF -2.0/+inf/+0" FFF00000 00000000 FFF00000 00000000 +r 6D70.10 +*Want "MSDB NF -2.0/+inf/+0" FFF00000 00000000 FFF00000 00000000 +r 6D80.10 +*Want "MSDBR NF -2.0/+inf/+2.0" FFF00000 00000000 FFF00000 00000000 +r 6D90.10 +*Want "MSDB NF -2.0/+inf/+2.0" FFF00000 00000000 FFF00000 00000000 +r 6DA0.10 +*Want "MSDBR NF -2.0/+inf/+inf" FFF00000 00000000 FFF00000 00000000 +r 6DB0.10 +*Want "MSDB NF -2.0/+inf/+inf" FFF00000 00000000 FFF00000 00000000 +r 6DC0.10 +*Want "MSDBR NF -2.0/+inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 6DD0.10 +*Want "MSDB NF -2.0/+inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 6DE0.10 +*Want "MSDBR NF -2.0/+inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6DF0.10 +*Want "MSDB NF -2.0/+inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6E00.10 +*Want "MSDBR NF -2.0/-QNaN/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 6E10.10 +*Want "MSDB NF -2.0/-QNaN/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 6E20.10 +*Want "MSDBR NF -2.0/-QNaN/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 6E30.10 +*Want "MSDB NF -2.0/-QNaN/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 6E40.10 +*Want "MSDBR NF -2.0/-QNaN/-0" FFF8B000 00000000 FFF8B000 00000000 +r 6E50.10 +*Want "MSDB NF -2.0/-QNaN/-0" FFF8B000 00000000 FFF8B000 00000000 +r 6E60.10 +*Want "MSDBR NF -2.0/-QNaN/+0" FFF8B000 00000000 FFF8B000 00000000 +r 6E70.10 +*Want "MSDB NF -2.0/-QNaN/+0" FFF8B000 00000000 FFF8B000 00000000 +r 6E80.10 +*Want "MSDBR NF -2.0/-QNaN/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 6E90.10 +*Want "MSDB NF -2.0/-QNaN/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 6EA0.10 +*Want "MSDBR NF -2.0/-QNaN/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 6EB0.10 +*Want "MSDB NF -2.0/-QNaN/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 6EC0.10 +*Want "MSDBR NF -2.0/-QNaN/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 6ED0.10 +*Want "MSDB NF -2.0/-QNaN/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 6EE0.10 +*Want "MSDBR NF -2.0/-QNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6EF0.10 +*Want "MSDB NF -2.0/-QNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6F00.10 +*Want "MSDBR NF -2.0/+SNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 6F10.10 +*Want "MSDB NF -2.0/+SNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 6F20.10 +*Want "MSDBR NF -2.0/+SNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 6F30.10 +*Want "MSDB NF -2.0/+SNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 6F40.10 +*Want "MSDBR NF -2.0/+SNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 6F50.10 +*Want "MSDB NF -2.0/+SNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 6F60.10 +*Want "MSDBR NF -2.0/+SNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 6F70.10 +*Want "MSDB NF -2.0/+SNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 6F80.10 +*Want "MSDBR NF -2.0/+SNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 6F90.10 +*Want "MSDB NF -2.0/+SNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 6FA0.10 +*Want "MSDBR NF -2.0/+SNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 6FB0.10 +*Want "MSDB NF -2.0/+SNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 6FC0.10 +*Want "MSDBR NF -2.0/+SNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 6FD0.10 +*Want "MSDB NF -2.0/+SNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 6FE0.10 +*Want "MSDBR NF -2.0/+SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 6FF0.10 +*Want "MSDB NF -2.0/+SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 7000.10 +*Want "MSDBR NF -0/-inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 7010.10 +*Want "MSDB NF -0/-inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 7020.10 +*Want "MSDBR NF -0/-inf/-2.0" 7FF80000 00000000 C0000000 00000000 +r 7030.10 +*Want "MSDB NF -0/-inf/-2.0" 7FF80000 00000000 C0000000 00000000 +r 7040.10 +*Want "MSDBR NF -0/-inf/-0" 7FF80000 00000000 80000000 00000000 +r 7050.10 +*Want "MSDB NF -0/-inf/-0" 7FF80000 00000000 80000000 00000000 +r 7060.10 +*Want "MSDBR NF -0/-inf/+0" 7FF80000 00000000 00000000 00000000 +r 7070.10 +*Want "MSDB NF -0/-inf/+0" 7FF80000 00000000 00000000 00000000 +r 7080.10 +*Want "MSDBR NF -0/-inf/+2.0" 7FF80000 00000000 40000000 00000000 +r 7090.10 +*Want "MSDB NF -0/-inf/+2.0" 7FF80000 00000000 40000000 00000000 +r 70A0.10 +*Want "MSDBR NF -0/-inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 70B0.10 +*Want "MSDB NF -0/-inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 70C0.10 +*Want "MSDBR NF -0/-inf/-QNaN" 7FF80000 00000000 FFF8B000 00000000 +r 70D0.10 +*Want "MSDB NF -0/-inf/-QNaN" 7FF80000 00000000 FFF8B000 00000000 +r 70E0.10 +*Want "MSDBR NF -0/-inf/+SNaN" 7FF80000 00000000 7FF0A000 00000000 +r 70F0.10 +*Want "MSDB NF -0/-inf/+SNaN" 7FF80000 00000000 7FF0A000 00000000 +r 7100.10 +*Want "MSDBR NF -0/-2.0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 7110.10 +*Want "MSDB NF -0/-2.0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 7120.10 +*Want "MSDBR NF -0/-2.0/-2.0" 40000000 00000000 40000000 00000000 +r 7130.10 +*Want "MSDB NF -0/-2.0/-2.0" 40000000 00000000 40000000 00000000 +r 7140.10 +*Want "MSDBR NF -0/-2.0/-0" 00000000 00000000 00000000 00000000 +r 7150.10 +*Want "MSDB NF -0/-2.0/-0" 00000000 00000000 00000000 00000000 +r 7160.10 +*Want "MSDBR NF -0/-2.0/+0" 00000000 00000000 00000000 00000000 +r 7170.10 +*Want "MSDB NF -0/-2.0/+0" 00000000 00000000 00000000 00000000 +r 7180.10 +*Want "MSDBR NF -0/-2.0/+2.0" C0000000 00000000 C0000000 00000000 +r 7190.10 +*Want "MSDB NF -0/-2.0/+2.0" C0000000 00000000 C0000000 00000000 +r 71A0.10 +*Want "MSDBR NF -0/-2.0/+inf" FFF00000 00000000 FFF00000 00000000 +r 71B0.10 +*Want "MSDB NF -0/-2.0/+inf" FFF00000 00000000 FFF00000 00000000 +r 71C0.10 +*Want "MSDBR NF -0/-2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 71D0.10 +*Want "MSDB NF -0/-2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 71E0.10 +*Want "MSDBR NF -0/-2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 71F0.10 +*Want "MSDB NF -0/-2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 7200.10 +*Want "MSDBR NF -0/-0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 7210.10 +*Want "MSDB NF -0/-0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 7220.10 +*Want "MSDBR NF -0/-0/-2.0" 40000000 00000000 40000000 00000000 +r 7230.10 +*Want "MSDB NF -0/-0/-2.0" 40000000 00000000 40000000 00000000 +r 7240.10 +*Want "MSDBR NF -0/-0/-0" 00000000 00000000 00000000 00000000 +r 7250.10 +*Want "MSDB NF -0/-0/-0" 00000000 00000000 00000000 00000000 +r 7260.10 +*Want "MSDBR NF -0/-0/+0" 00000000 00000000 00000000 00000000 +r 7270.10 +*Want "MSDB NF -0/-0/+0" 00000000 00000000 00000000 00000000 +r 7280.10 +*Want "MSDBR NF -0/-0/+2.0" C0000000 00000000 C0000000 00000000 +r 7290.10 +*Want "MSDB NF -0/-0/+2.0" C0000000 00000000 C0000000 00000000 +r 72A0.10 +*Want "MSDBR NF -0/-0/+inf" FFF00000 00000000 FFF00000 00000000 +r 72B0.10 +*Want "MSDB NF -0/-0/+inf" FFF00000 00000000 FFF00000 00000000 +r 72C0.10 +*Want "MSDBR NF -0/-0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 72D0.10 +*Want "MSDB NF -0/-0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 72E0.10 +*Want "MSDBR NF -0/-0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 72F0.10 +*Want "MSDB NF -0/-0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 7300.10 +*Want "MSDBR NF -0/+0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 7310.10 +*Want "MSDB NF -0/+0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 7320.10 +*Want "MSDBR NF -0/+0/-2.0" 40000000 00000000 40000000 00000000 +r 7330.10 +*Want "MSDB NF -0/+0/-2.0" 40000000 00000000 40000000 00000000 +r 7340.10 +*Want "MSDBR NF -0/+0/-0" 00000000 00000000 00000000 00000000 +r 7350.10 +*Want "MSDB NF -0/+0/-0" 00000000 00000000 00000000 00000000 +r 7360.10 +*Want "MSDBR NF -0/+0/+0" 80000000 00000000 80000000 00000000 +r 7370.10 +*Want "MSDB NF -0/+0/+0" 80000000 00000000 80000000 00000000 +r 7380.10 +*Want "MSDBR NF -0/+0/+2.0" C0000000 00000000 C0000000 00000000 +r 7390.10 +*Want "MSDB NF -0/+0/+2.0" C0000000 00000000 C0000000 00000000 +r 73A0.10 +*Want "MSDBR NF -0/+0/+inf" FFF00000 00000000 FFF00000 00000000 +r 73B0.10 +*Want "MSDB NF -0/+0/+inf" FFF00000 00000000 FFF00000 00000000 +r 73C0.10 +*Want "MSDBR NF -0/+0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 73D0.10 +*Want "MSDB NF -0/+0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 73E0.10 +*Want "MSDBR NF -0/+0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 73F0.10 +*Want "MSDB NF -0/+0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 7400.10 +*Want "MSDBR NF -0/+2.0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 7410.10 +*Want "MSDB NF -0/+2.0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 7420.10 +*Want "MSDBR NF -0/+2.0/-2.0" 40000000 00000000 40000000 00000000 +r 7430.10 +*Want "MSDB NF -0/+2.0/-2.0" 40000000 00000000 40000000 00000000 +r 7440.10 +*Want "MSDBR NF -0/+2.0/-0" 00000000 00000000 00000000 00000000 +r 7450.10 +*Want "MSDB NF -0/+2.0/-0" 00000000 00000000 00000000 00000000 +r 7460.10 +*Want "MSDBR NF -0/+2.0/+0" 80000000 00000000 80000000 00000000 +r 7470.10 +*Want "MSDB NF -0/+2.0/+0" 80000000 00000000 80000000 00000000 +r 7480.10 +*Want "MSDBR NF -0/+2.0/+2.0" C0000000 00000000 C0000000 00000000 +r 7490.10 +*Want "MSDB NF -0/+2.0/+2.0" C0000000 00000000 C0000000 00000000 +r 74A0.10 +*Want "MSDBR NF -0/+2.0/+inf" FFF00000 00000000 FFF00000 00000000 +r 74B0.10 +*Want "MSDB NF -0/+2.0/+inf" FFF00000 00000000 FFF00000 00000000 +r 74C0.10 +*Want "MSDBR NF -0/+2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 74D0.10 +*Want "MSDB NF -0/+2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 74E0.10 +*Want "MSDBR NF -0/+2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 74F0.10 +*Want "MSDB NF -0/+2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 7500.10 +*Want "MSDBR NF -0/+inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 7510.10 +*Want "MSDB NF -0/+inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 7520.10 +*Want "MSDBR NF -0/+inf/-2.0" 7FF80000 00000000 C0000000 00000000 +r 7530.10 +*Want "MSDB NF -0/+inf/-2.0" 7FF80000 00000000 C0000000 00000000 +r 7540.10 +*Want "MSDBR NF -0/+inf/-0" 7FF80000 00000000 80000000 00000000 +r 7550.10 +*Want "MSDB NF -0/+inf/-0" 7FF80000 00000000 80000000 00000000 +r 7560.10 +*Want "MSDBR NF -0/+inf/+0" 7FF80000 00000000 00000000 00000000 +r 7570.10 +*Want "MSDB NF -0/+inf/+0" 7FF80000 00000000 00000000 00000000 +r 7580.10 +*Want "MSDBR NF -0/+inf/+2.0" 7FF80000 00000000 40000000 00000000 +r 7590.10 +*Want "MSDB NF -0/+inf/+2.0" 7FF80000 00000000 40000000 00000000 +r 75A0.10 +*Want "MSDBR NF -0/+inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 75B0.10 +*Want "MSDB NF -0/+inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 75C0.10 +*Want "MSDBR NF -0/+inf/-QNaN" 7FF80000 00000000 FFF8B000 00000000 +r 75D0.10 +*Want "MSDB NF -0/+inf/-QNaN" 7FF80000 00000000 FFF8B000 00000000 +r 75E0.10 +*Want "MSDBR NF -0/+inf/+SNaN" 7FF80000 00000000 7FF0A000 00000000 +r 75F0.10 +*Want "MSDB NF -0/+inf/+SNaN" 7FF80000 00000000 7FF0A000 00000000 +r 7600.10 +*Want "MSDBR NF -0/-QNaN/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 7610.10 +*Want "MSDB NF -0/-QNaN/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 7620.10 +*Want "MSDBR NF -0/-QNaN/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 7630.10 +*Want "MSDB NF -0/-QNaN/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 7640.10 +*Want "MSDBR NF -0/-QNaN/-0" FFF8B000 00000000 FFF8B000 00000000 +r 7650.10 +*Want "MSDB NF -0/-QNaN/-0" FFF8B000 00000000 FFF8B000 00000000 +r 7660.10 +*Want "MSDBR NF -0/-QNaN/+0" FFF8B000 00000000 FFF8B000 00000000 +r 7670.10 +*Want "MSDB NF -0/-QNaN/+0" FFF8B000 00000000 FFF8B000 00000000 +r 7680.10 +*Want "MSDBR NF -0/-QNaN/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 7690.10 +*Want "MSDB NF -0/-QNaN/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 76A0.10 +*Want "MSDBR NF -0/-QNaN/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 76B0.10 +*Want "MSDB NF -0/-QNaN/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 76C0.10 +*Want "MSDBR NF -0/-QNaN/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 76D0.10 +*Want "MSDB NF -0/-QNaN/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 76E0.10 +*Want "MSDBR NF -0/-QNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 76F0.10 +*Want "MSDB NF -0/-QNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 7700.10 +*Want "MSDBR NF -0/+SNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 7710.10 +*Want "MSDB NF -0/+SNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 7720.10 +*Want "MSDBR NF -0/+SNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 7730.10 +*Want "MSDB NF -0/+SNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 7740.10 +*Want "MSDBR NF -0/+SNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 7750.10 +*Want "MSDB NF -0/+SNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 7760.10 +*Want "MSDBR NF -0/+SNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 7770.10 +*Want "MSDB NF -0/+SNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 7780.10 +*Want "MSDBR NF -0/+SNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 7790.10 +*Want "MSDB NF -0/+SNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 77A0.10 +*Want "MSDBR NF -0/+SNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 77B0.10 +*Want "MSDB NF -0/+SNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 77C0.10 +*Want "MSDBR NF -0/+SNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 77D0.10 +*Want "MSDB NF -0/+SNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 77E0.10 +*Want "MSDBR NF -0/+SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 77F0.10 +*Want "MSDB NF -0/+SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 7800.10 +*Want "MSDBR NF +0/-inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 7810.10 +*Want "MSDB NF +0/-inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 7820.10 +*Want "MSDBR NF +0/-inf/-2.0" 7FF80000 00000000 C0000000 00000000 +r 7830.10 +*Want "MSDB NF +0/-inf/-2.0" 7FF80000 00000000 C0000000 00000000 +r 7840.10 +*Want "MSDBR NF +0/-inf/-0" 7FF80000 00000000 80000000 00000000 +r 7850.10 +*Want "MSDB NF +0/-inf/-0" 7FF80000 00000000 80000000 00000000 +r 7860.10 +*Want "MSDBR NF +0/-inf/+0" 7FF80000 00000000 00000000 00000000 +r 7870.10 +*Want "MSDB NF +0/-inf/+0" 7FF80000 00000000 00000000 00000000 +r 7880.10 +*Want "MSDBR NF +0/-inf/+2.0" 7FF80000 00000000 40000000 00000000 +r 7890.10 +*Want "MSDB NF +0/-inf/+2.0" 7FF80000 00000000 40000000 00000000 +r 78A0.10 +*Want "MSDBR NF +0/-inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 78B0.10 +*Want "MSDB NF +0/-inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 78C0.10 +*Want "MSDBR NF +0/-inf/-QNaN" 7FF80000 00000000 FFF8B000 00000000 +r 78D0.10 +*Want "MSDB NF +0/-inf/-QNaN" 7FF80000 00000000 FFF8B000 00000000 +r 78E0.10 +*Want "MSDBR NF +0/-inf/+SNaN" 7FF80000 00000000 7FF0A000 00000000 +r 78F0.10 +*Want "MSDB NF +0/-inf/+SNaN" 7FF80000 00000000 7FF0A000 00000000 +r 7900.10 +*Want "MSDBR NF +0/-2.0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 7910.10 +*Want "MSDB NF +0/-2.0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 7920.10 +*Want "MSDBR NF +0/-2.0/-2.0" 40000000 00000000 40000000 00000000 +r 7930.10 +*Want "MSDB NF +0/-2.0/-2.0" 40000000 00000000 40000000 00000000 +r 7940.10 +*Want "MSDBR NF +0/-2.0/-0" 00000000 00000000 00000000 00000000 +r 7950.10 +*Want "MSDB NF +0/-2.0/-0" 00000000 00000000 00000000 00000000 +r 7960.10 +*Want "MSDBR NF +0/-2.0/+0" 80000000 00000000 80000000 00000000 +r 7970.10 +*Want "MSDB NF +0/-2.0/+0" 80000000 00000000 80000000 00000000 +r 7980.10 +*Want "MSDBR NF +0/-2.0/+2.0" C0000000 00000000 C0000000 00000000 +r 7990.10 +*Want "MSDB NF +0/-2.0/+2.0" C0000000 00000000 C0000000 00000000 +r 79A0.10 +*Want "MSDBR NF +0/-2.0/+inf" FFF00000 00000000 FFF00000 00000000 +r 79B0.10 +*Want "MSDB NF +0/-2.0/+inf" FFF00000 00000000 FFF00000 00000000 +r 79C0.10 +*Want "MSDBR NF +0/-2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 79D0.10 +*Want "MSDB NF +0/-2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 79E0.10 +*Want "MSDBR NF +0/-2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 79F0.10 +*Want "MSDB NF +0/-2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 7A00.10 +*Want "MSDBR NF +0/-0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 7A10.10 +*Want "MSDB NF +0/-0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 7A20.10 +*Want "MSDBR NF +0/-0/-2.0" 40000000 00000000 40000000 00000000 +r 7A30.10 +*Want "MSDB NF +0/-0/-2.0" 40000000 00000000 40000000 00000000 +r 7A40.10 +*Want "MSDBR NF +0/-0/-0" 00000000 00000000 00000000 00000000 +r 7A50.10 +*Want "MSDB NF +0/-0/-0" 00000000 00000000 00000000 00000000 +r 7A60.10 +*Want "MSDBR NF +0/-0/+0" 80000000 00000000 80000000 00000000 +r 7A70.10 +*Want "MSDB NF +0/-0/+0" 80000000 00000000 80000000 00000000 +r 7A80.10 +*Want "MSDBR NF +0/-0/+2.0" C0000000 00000000 C0000000 00000000 +r 7A90.10 +*Want "MSDB NF +0/-0/+2.0" C0000000 00000000 C0000000 00000000 +r 7AA0.10 +*Want "MSDBR NF +0/-0/+inf" FFF00000 00000000 FFF00000 00000000 +r 7AB0.10 +*Want "MSDB NF +0/-0/+inf" FFF00000 00000000 FFF00000 00000000 +r 7AC0.10 +*Want "MSDBR NF +0/-0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 7AD0.10 +*Want "MSDB NF +0/-0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 7AE0.10 +*Want "MSDBR NF +0/-0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 7AF0.10 +*Want "MSDB NF +0/-0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 7B00.10 +*Want "MSDBR NF +0/+0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 7B10.10 +*Want "MSDB NF +0/+0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 7B20.10 +*Want "MSDBR NF +0/+0/-2.0" 40000000 00000000 40000000 00000000 +r 7B30.10 +*Want "MSDB NF +0/+0/-2.0" 40000000 00000000 40000000 00000000 +r 7B40.10 +*Want "MSDBR NF +0/+0/-0" 00000000 00000000 00000000 00000000 +r 7B50.10 +*Want "MSDB NF +0/+0/-0" 00000000 00000000 00000000 00000000 +r 7B60.10 +*Want "MSDBR NF +0/+0/+0" 00000000 00000000 00000000 00000000 +r 7B70.10 +*Want "MSDB NF +0/+0/+0" 00000000 00000000 00000000 00000000 +r 7B80.10 +*Want "MSDBR NF +0/+0/+2.0" C0000000 00000000 C0000000 00000000 +r 7B90.10 +*Want "MSDB NF +0/+0/+2.0" C0000000 00000000 C0000000 00000000 +r 7BA0.10 +*Want "MSDBR NF +0/+0/+inf" FFF00000 00000000 FFF00000 00000000 +r 7BB0.10 +*Want "MSDB NF +0/+0/+inf" FFF00000 00000000 FFF00000 00000000 +r 7BC0.10 +*Want "MSDBR NF +0/+0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 7BD0.10 +*Want "MSDB NF +0/+0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 7BE0.10 +*Want "MSDBR NF +0/+0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 7BF0.10 +*Want "MSDB NF +0/+0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 7C00.10 +*Want "MSDBR NF +0/+2.0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 7C10.10 +*Want "MSDB NF +0/+2.0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 7C20.10 +*Want "MSDBR NF +0/+2.0/-2.0" 40000000 00000000 40000000 00000000 +r 7C30.10 +*Want "MSDB NF +0/+2.0/-2.0" 40000000 00000000 40000000 00000000 +r 7C40.10 +*Want "MSDBR NF +0/+2.0/-0" 00000000 00000000 00000000 00000000 +r 7C50.10 +*Want "MSDB NF +0/+2.0/-0" 00000000 00000000 00000000 00000000 +r 7C60.10 +*Want "MSDBR NF +0/+2.0/+0" 00000000 00000000 00000000 00000000 +r 7C70.10 +*Want "MSDB NF +0/+2.0/+0" 00000000 00000000 00000000 00000000 +r 7C80.10 +*Want "MSDBR NF +0/+2.0/+2.0" C0000000 00000000 C0000000 00000000 +r 7C90.10 +*Want "MSDB NF +0/+2.0/+2.0" C0000000 00000000 C0000000 00000000 +r 7CA0.10 +*Want "MSDBR NF +0/+2.0/+inf" FFF00000 00000000 FFF00000 00000000 +r 7CB0.10 +*Want "MSDB NF +0/+2.0/+inf" FFF00000 00000000 FFF00000 00000000 +r 7CC0.10 +*Want "MSDBR NF +0/+2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 7CD0.10 +*Want "MSDB NF +0/+2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 7CE0.10 +*Want "MSDBR NF +0/+2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 7CF0.10 +*Want "MSDB NF +0/+2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 7D00.10 +*Want "MSDBR NF +0/+inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 7D10.10 +*Want "MSDB NF +0/+inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 7D20.10 +*Want "MSDBR NF +0/+inf/-2.0" 7FF80000 00000000 C0000000 00000000 +r 7D30.10 +*Want "MSDB NF +0/+inf/-2.0" 7FF80000 00000000 C0000000 00000000 +r 7D40.10 +*Want "MSDBR NF +0/+inf/-0" 7FF80000 00000000 80000000 00000000 +r 7D50.10 +*Want "MSDB NF +0/+inf/-0" 7FF80000 00000000 80000000 00000000 +r 7D60.10 +*Want "MSDBR NF +0/+inf/+0" 7FF80000 00000000 00000000 00000000 +r 7D70.10 +*Want "MSDB NF +0/+inf/+0" 7FF80000 00000000 00000000 00000000 +r 7D80.10 +*Want "MSDBR NF +0/+inf/+2.0" 7FF80000 00000000 40000000 00000000 +r 7D90.10 +*Want "MSDB NF +0/+inf/+2.0" 7FF80000 00000000 40000000 00000000 +r 7DA0.10 +*Want "MSDBR NF +0/+inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 7DB0.10 +*Want "MSDB NF +0/+inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 7DC0.10 +*Want "MSDBR NF +0/+inf/-QNaN" 7FF80000 00000000 FFF8B000 00000000 +r 7DD0.10 +*Want "MSDB NF +0/+inf/-QNaN" 7FF80000 00000000 FFF8B000 00000000 +r 7DE0.10 +*Want "MSDBR NF +0/+inf/+SNaN" 7FF80000 00000000 7FF0A000 00000000 +r 7DF0.10 +*Want "MSDB NF +0/+inf/+SNaN" 7FF80000 00000000 7FF0A000 00000000 +r 7E00.10 +*Want "MSDBR NF +0/-QNaN/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 7E10.10 +*Want "MSDB NF +0/-QNaN/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 7E20.10 +*Want "MSDBR NF +0/-QNaN/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 7E30.10 +*Want "MSDB NF +0/-QNaN/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 7E40.10 +*Want "MSDBR NF +0/-QNaN/-0" FFF8B000 00000000 FFF8B000 00000000 +r 7E50.10 +*Want "MSDB NF +0/-QNaN/-0" FFF8B000 00000000 FFF8B000 00000000 +r 7E60.10 +*Want "MSDBR NF +0/-QNaN/+0" FFF8B000 00000000 FFF8B000 00000000 +r 7E70.10 +*Want "MSDB NF +0/-QNaN/+0" FFF8B000 00000000 FFF8B000 00000000 +r 7E80.10 +*Want "MSDBR NF +0/-QNaN/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 7E90.10 +*Want "MSDB NF +0/-QNaN/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 7EA0.10 +*Want "MSDBR NF +0/-QNaN/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 7EB0.10 +*Want "MSDB NF +0/-QNaN/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 7EC0.10 +*Want "MSDBR NF +0/-QNaN/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 7ED0.10 +*Want "MSDB NF +0/-QNaN/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 7EE0.10 +*Want "MSDBR NF +0/-QNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 7EF0.10 +*Want "MSDB NF +0/-QNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 7F00.10 +*Want "MSDBR NF +0/+SNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 7F10.10 +*Want "MSDB NF +0/+SNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 7F20.10 +*Want "MSDBR NF +0/+SNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 7F30.10 +*Want "MSDB NF +0/+SNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 7F40.10 +*Want "MSDBR NF +0/+SNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 7F50.10 +*Want "MSDB NF +0/+SNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 7F60.10 +*Want "MSDBR NF +0/+SNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 7F70.10 +*Want "MSDB NF +0/+SNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 7F80.10 +*Want "MSDBR NF +0/+SNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 7F90.10 +*Want "MSDB NF +0/+SNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 7FA0.10 +*Want "MSDBR NF +0/+SNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 7FB0.10 +*Want "MSDB NF +0/+SNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 7FC0.10 +*Want "MSDBR NF +0/+SNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 7FD0.10 +*Want "MSDB NF +0/+SNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 7FE0.10 +*Want "MSDBR NF +0/+SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 7FF0.10 +*Want "MSDB NF +0/+SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8000.10 +*Want "MSDBR NF +2.0/-inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 8010.10 +*Want "MSDB NF +2.0/-inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 8020.10 +*Want "MSDBR NF +2.0/-inf/-2.0" FFF00000 00000000 FFF00000 00000000 +r 8030.10 +*Want "MSDB NF +2.0/-inf/-2.0" FFF00000 00000000 FFF00000 00000000 +r 8040.10 +*Want "MSDBR NF +2.0/-inf/-0" FFF00000 00000000 FFF00000 00000000 +r 8050.10 +*Want "MSDB NF +2.0/-inf/-0" FFF00000 00000000 FFF00000 00000000 +r 8060.10 +*Want "MSDBR NF +2.0/-inf/+0" FFF00000 00000000 FFF00000 00000000 +r 8070.10 +*Want "MSDB NF +2.0/-inf/+0" FFF00000 00000000 FFF00000 00000000 +r 8080.10 +*Want "MSDBR NF +2.0/-inf/+2.0" FFF00000 00000000 FFF00000 00000000 +r 8090.10 +*Want "MSDB NF +2.0/-inf/+2.0" FFF00000 00000000 FFF00000 00000000 +r 80A0.10 +*Want "MSDBR NF +2.0/-inf/+inf" FFF00000 00000000 FFF00000 00000000 +r 80B0.10 +*Want "MSDB NF +2.0/-inf/+inf" FFF00000 00000000 FFF00000 00000000 +r 80C0.10 +*Want "MSDBR NF +2.0/-inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 80D0.10 +*Want "MSDB NF +2.0/-inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 80E0.10 +*Want "MSDBR NF +2.0/-inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 80F0.10 +*Want "MSDB NF +2.0/-inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8100.10 +*Want "MSDBR NF +2.0/-2.0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 8110.10 +*Want "MSDB NF +2.0/-2.0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 8120.10 +*Want "MSDBR NF +2.0/-2.0/-2.0" C0000000 00000000 C0000000 00000000 +r 8130.10 +*Want "MSDB NF +2.0/-2.0/-2.0" C0000000 00000000 C0000000 00000000 +r 8140.10 +*Want "MSDBR NF +2.0/-2.0/-0" C0100000 00000000 C0100000 00000000 +r 8150.10 +*Want "MSDB NF +2.0/-2.0/-0" C0100000 00000000 C0100000 00000000 +r 8160.10 +*Want "MSDBR NF +2.0/-2.0/+0" C0100000 00000000 C0100000 00000000 +r 8170.10 +*Want "MSDB NF +2.0/-2.0/+0" C0100000 00000000 C0100000 00000000 +r 8180.10 +*Want "MSDBR NF +2.0/-2.0/+2.0" C0180000 00000000 C0180000 00000000 +r 8190.10 +*Want "MSDB NF +2.0/-2.0/+2.0" C0180000 00000000 C0180000 00000000 +r 81A0.10 +*Want "MSDBR NF +2.0/-2.0/+inf" FFF00000 00000000 FFF00000 00000000 +r 81B0.10 +*Want "MSDB NF +2.0/-2.0/+inf" FFF00000 00000000 FFF00000 00000000 +r 81C0.10 +*Want "MSDBR NF +2.0/-2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 81D0.10 +*Want "MSDB NF +2.0/-2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 81E0.10 +*Want "MSDBR NF +2.0/-2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 81F0.10 +*Want "MSDB NF +2.0/-2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8200.10 +*Want "MSDBR NF +2.0/-0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 8210.10 +*Want "MSDB NF +2.0/-0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 8220.10 +*Want "MSDBR NF +2.0/-0/-2.0" 40000000 00000000 40000000 00000000 +r 8230.10 +*Want "MSDB NF +2.0/-0/-2.0" 40000000 00000000 40000000 00000000 +r 8240.10 +*Want "MSDBR NF +2.0/-0/-0" 00000000 00000000 00000000 00000000 +r 8250.10 +*Want "MSDB NF +2.0/-0/-0" 00000000 00000000 00000000 00000000 +r 8260.10 +*Want "MSDBR NF +2.0/-0/+0" 80000000 00000000 80000000 00000000 +r 8270.10 +*Want "MSDB NF +2.0/-0/+0" 80000000 00000000 80000000 00000000 +r 8280.10 +*Want "MSDBR NF +2.0/-0/+2.0" C0000000 00000000 C0000000 00000000 +r 8290.10 +*Want "MSDB NF +2.0/-0/+2.0" C0000000 00000000 C0000000 00000000 +r 82A0.10 +*Want "MSDBR NF +2.0/-0/+inf" FFF00000 00000000 FFF00000 00000000 +r 82B0.10 +*Want "MSDB NF +2.0/-0/+inf" FFF00000 00000000 FFF00000 00000000 +r 82C0.10 +*Want "MSDBR NF +2.0/-0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 82D0.10 +*Want "MSDB NF +2.0/-0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 82E0.10 +*Want "MSDBR NF +2.0/-0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 82F0.10 +*Want "MSDB NF +2.0/-0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8300.10 +*Want "MSDBR NF +2.0/+0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 8310.10 +*Want "MSDB NF +2.0/+0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 8320.10 +*Want "MSDBR NF +2.0/+0/-2.0" 40000000 00000000 40000000 00000000 +r 8330.10 +*Want "MSDB NF +2.0/+0/-2.0" 40000000 00000000 40000000 00000000 +r 8340.10 +*Want "MSDBR NF +2.0/+0/-0" 00000000 00000000 00000000 00000000 +r 8350.10 +*Want "MSDB NF +2.0/+0/-0" 00000000 00000000 00000000 00000000 +r 8360.10 +*Want "MSDBR NF +2.0/+0/+0" 00000000 00000000 00000000 00000000 +r 8370.10 +*Want "MSDB NF +2.0/+0/+0" 00000000 00000000 00000000 00000000 +r 8380.10 +*Want "MSDBR NF +2.0/+0/+2.0" C0000000 00000000 C0000000 00000000 +r 8390.10 +*Want "MSDB NF +2.0/+0/+2.0" C0000000 00000000 C0000000 00000000 +r 83A0.10 +*Want "MSDBR NF +2.0/+0/+inf" FFF00000 00000000 FFF00000 00000000 +r 83B0.10 +*Want "MSDB NF +2.0/+0/+inf" FFF00000 00000000 FFF00000 00000000 +r 83C0.10 +*Want "MSDBR NF +2.0/+0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 83D0.10 +*Want "MSDB NF +2.0/+0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 83E0.10 +*Want "MSDBR NF +2.0/+0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 83F0.10 +*Want "MSDB NF +2.0/+0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8400.10 +*Want "MSDBR NF +2.0/+2.0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 8410.10 +*Want "MSDB NF +2.0/+2.0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 8420.10 +*Want "MSDBR NF +2.0/+2.0/-2.0" 40180000 00000000 40180000 00000000 +r 8430.10 +*Want "MSDB NF +2.0/+2.0/-2.0" 40180000 00000000 40180000 00000000 +r 8440.10 +*Want "MSDBR NF +2.0/+2.0/-0" 40100000 00000000 40100000 00000000 +r 8450.10 +*Want "MSDB NF +2.0/+2.0/-0" 40100000 00000000 40100000 00000000 +r 8460.10 +*Want "MSDBR NF +2.0/+2.0/+0" 40100000 00000000 40100000 00000000 +r 8470.10 +*Want "MSDB NF +2.0/+2.0/+0" 40100000 00000000 40100000 00000000 +r 8480.10 +*Want "MSDBR NF +2.0/+2.0/+2.0" 40000000 00000000 40000000 00000000 +r 8490.10 +*Want "MSDB NF +2.0/+2.0/+2.0" 40000000 00000000 40000000 00000000 +r 84A0.10 +*Want "MSDBR NF +2.0/+2.0/+inf" FFF00000 00000000 FFF00000 00000000 +r 84B0.10 +*Want "MSDB NF +2.0/+2.0/+inf" FFF00000 00000000 FFF00000 00000000 +r 84C0.10 +*Want "MSDBR NF +2.0/+2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 84D0.10 +*Want "MSDB NF +2.0/+2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 84E0.10 +*Want "MSDBR NF +2.0/+2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 84F0.10 +*Want "MSDB NF +2.0/+2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8500.10 +*Want "MSDBR NF +2.0/+inf/-inf" 7FF00000 00000000 7FF00000 00000000 +r 8510.10 +*Want "MSDB NF +2.0/+inf/-inf" 7FF00000 00000000 7FF00000 00000000 +r 8520.10 +*Want "MSDBR NF +2.0/+inf/-2.0" 7FF00000 00000000 7FF00000 00000000 +r 8530.10 +*Want "MSDB NF +2.0/+inf/-2.0" 7FF00000 00000000 7FF00000 00000000 +r 8540.10 +*Want "MSDBR NF +2.0/+inf/-0" 7FF00000 00000000 7FF00000 00000000 +r 8550.10 +*Want "MSDB NF +2.0/+inf/-0" 7FF00000 00000000 7FF00000 00000000 +r 8560.10 +*Want "MSDBR NF +2.0/+inf/+0" 7FF00000 00000000 7FF00000 00000000 +r 8570.10 +*Want "MSDB NF +2.0/+inf/+0" 7FF00000 00000000 7FF00000 00000000 +r 8580.10 +*Want "MSDBR NF +2.0/+inf/+2.0" 7FF00000 00000000 7FF00000 00000000 +r 8590.10 +*Want "MSDB NF +2.0/+inf/+2.0" 7FF00000 00000000 7FF00000 00000000 +r 85A0.10 +*Want "MSDBR NF +2.0/+inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 85B0.10 +*Want "MSDB NF +2.0/+inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 85C0.10 +*Want "MSDBR NF +2.0/+inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 85D0.10 +*Want "MSDB NF +2.0/+inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 85E0.10 +*Want "MSDBR NF +2.0/+inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 85F0.10 +*Want "MSDB NF +2.0/+inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8600.10 +*Want "MSDBR NF +2.0/-QNaN/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 8610.10 +*Want "MSDB NF +2.0/-QNaN/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 8620.10 +*Want "MSDBR NF +2.0/-QNaN/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 8630.10 +*Want "MSDB NF +2.0/-QNaN/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 8640.10 +*Want "MSDBR NF +2.0/-QNaN/-0" FFF8B000 00000000 FFF8B000 00000000 +r 8650.10 +*Want "MSDB NF +2.0/-QNaN/-0" FFF8B000 00000000 FFF8B000 00000000 +r 8660.10 +*Want "MSDBR NF +2.0/-QNaN/+0" FFF8B000 00000000 FFF8B000 00000000 +r 8670.10 +*Want "MSDB NF +2.0/-QNaN/+0" FFF8B000 00000000 FFF8B000 00000000 +r 8680.10 +*Want "MSDBR NF +2.0/-QNaN/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 8690.10 +*Want "MSDB NF +2.0/-QNaN/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 86A0.10 +*Want "MSDBR NF +2.0/-QNaN/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 86B0.10 +*Want "MSDB NF +2.0/-QNaN/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 86C0.10 +*Want "MSDBR NF +2.0/-QNaN/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 86D0.10 +*Want "MSDB NF +2.0/-QNaN/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 86E0.10 +*Want "MSDBR NF +2.0/-QNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 86F0.10 +*Want "MSDB NF +2.0/-QNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8700.10 +*Want "MSDBR NF +2.0/+SNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 8710.10 +*Want "MSDB NF +2.0/+SNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 8720.10 +*Want "MSDBR NF +2.0/+SNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 8730.10 +*Want "MSDB NF +2.0/+SNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 8740.10 +*Want "MSDBR NF +2.0/+SNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 8750.10 +*Want "MSDB NF +2.0/+SNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 8760.10 +*Want "MSDBR NF +2.0/+SNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 8770.10 +*Want "MSDB NF +2.0/+SNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 8780.10 +*Want "MSDBR NF +2.0/+SNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 8790.10 +*Want "MSDB NF +2.0/+SNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 87A0.10 +*Want "MSDBR NF +2.0/+SNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 87B0.10 +*Want "MSDB NF +2.0/+SNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 87C0.10 +*Want "MSDBR NF +2.0/+SNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 87D0.10 +*Want "MSDB NF +2.0/+SNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 87E0.10 +*Want "MSDBR NF +2.0/+SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 87F0.10 +*Want "MSDB NF +2.0/+SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8800.10 +*Want "MSDBR NF +inf/-inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 8810.10 +*Want "MSDB NF +inf/-inf/-inf" 7FF80000 00000000 FFF00000 00000000 +r 8820.10 +*Want "MSDBR NF +inf/-inf/-2.0" FFF00000 00000000 FFF00000 00000000 +r 8830.10 +*Want "MSDB NF +inf/-inf/-2.0" FFF00000 00000000 FFF00000 00000000 +r 8840.10 +*Want "MSDBR NF +inf/-inf/-0" FFF00000 00000000 FFF00000 00000000 +r 8850.10 +*Want "MSDB NF +inf/-inf/-0" FFF00000 00000000 FFF00000 00000000 +r 8860.10 +*Want "MSDBR NF +inf/-inf/+0" FFF00000 00000000 FFF00000 00000000 +r 8870.10 +*Want "MSDB NF +inf/-inf/+0" FFF00000 00000000 FFF00000 00000000 +r 8880.10 +*Want "MSDBR NF +inf/-inf/+2.0" FFF00000 00000000 FFF00000 00000000 +r 8890.10 +*Want "MSDB NF +inf/-inf/+2.0" FFF00000 00000000 FFF00000 00000000 +r 88A0.10 +*Want "MSDBR NF +inf/-inf/+inf" FFF00000 00000000 FFF00000 00000000 +r 88B0.10 +*Want "MSDB NF +inf/-inf/+inf" FFF00000 00000000 FFF00000 00000000 +r 88C0.10 +*Want "MSDBR NF +inf/-inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 88D0.10 +*Want "MSDB NF +inf/-inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 88E0.10 +*Want "MSDBR NF +inf/-inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 88F0.10 +*Want "MSDB NF +inf/-inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8900.10 +*Want "MSDBR NF +inf/-2.0/-inf" 7FF80000 00000000 FFF00000 00000000 +r 8910.10 +*Want "MSDB NF +inf/-2.0/-inf" 7FF80000 00000000 FFF00000 00000000 +r 8920.10 +*Want "MSDBR NF +inf/-2.0/-2.0" FFF00000 00000000 FFF00000 00000000 +r 8930.10 +*Want "MSDB NF +inf/-2.0/-2.0" FFF00000 00000000 FFF00000 00000000 +r 8940.10 +*Want "MSDBR NF +inf/-2.0/-0" FFF00000 00000000 FFF00000 00000000 +r 8950.10 +*Want "MSDB NF +inf/-2.0/-0" FFF00000 00000000 FFF00000 00000000 +r 8960.10 +*Want "MSDBR NF +inf/-2.0/+0" FFF00000 00000000 FFF00000 00000000 +r 8970.10 +*Want "MSDB NF +inf/-2.0/+0" FFF00000 00000000 FFF00000 00000000 +r 8980.10 +*Want "MSDBR NF +inf/-2.0/+2.0" FFF00000 00000000 FFF00000 00000000 +r 8990.10 +*Want "MSDB NF +inf/-2.0/+2.0" FFF00000 00000000 FFF00000 00000000 +r 89A0.10 +*Want "MSDBR NF +inf/-2.0/+inf" FFF00000 00000000 FFF00000 00000000 +r 89B0.10 +*Want "MSDB NF +inf/-2.0/+inf" FFF00000 00000000 FFF00000 00000000 +r 89C0.10 +*Want "MSDBR NF +inf/-2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 89D0.10 +*Want "MSDB NF +inf/-2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 89E0.10 +*Want "MSDBR NF +inf/-2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 89F0.10 +*Want "MSDB NF +inf/-2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8A00.10 +*Want "MSDBR NF +inf/-0/-inf" 7FF80000 00000000 FFF00000 00000000 +r 8A10.10 +*Want "MSDB NF +inf/-0/-inf" 7FF80000 00000000 FFF00000 00000000 +r 8A20.10 +*Want "MSDBR NF +inf/-0/-2.0" 7FF80000 00000000 C0000000 00000000 +r 8A30.10 +*Want "MSDB NF +inf/-0/-2.0" 7FF80000 00000000 C0000000 00000000 +r 8A40.10 +*Want "MSDBR NF +inf/-0/-0" 7FF80000 00000000 80000000 00000000 +r 8A50.10 +*Want "MSDB NF +inf/-0/-0" 7FF80000 00000000 80000000 00000000 +r 8A60.10 +*Want "MSDBR NF +inf/-0/+0" 7FF80000 00000000 00000000 00000000 +r 8A70.10 +*Want "MSDB NF +inf/-0/+0" 7FF80000 00000000 00000000 00000000 +r 8A80.10 +*Want "MSDBR NF +inf/-0/+2.0" 7FF80000 00000000 40000000 00000000 +r 8A90.10 +*Want "MSDB NF +inf/-0/+2.0" 7FF80000 00000000 40000000 00000000 +r 8AA0.10 +*Want "MSDBR NF +inf/-0/+inf" 7FF80000 00000000 7FF00000 00000000 +r 8AB0.10 +*Want "MSDB NF +inf/-0/+inf" 7FF80000 00000000 7FF00000 00000000 +r 8AC0.10 +*Want "MSDBR NF +inf/-0/-QNaN" 7FF80000 00000000 FFF8B000 00000000 +r 8AD0.10 +*Want "MSDB NF +inf/-0/-QNaN" 7FF80000 00000000 FFF8B000 00000000 +r 8AE0.10 +*Want "MSDBR NF +inf/-0/+SNaN" 7FF80000 00000000 7FF0A000 00000000 +r 8AF0.10 +*Want "MSDB NF +inf/-0/+SNaN" 7FF80000 00000000 7FF0A000 00000000 +r 8B00.10 +*Want "MSDBR NF +inf/+0/-inf" 7FF80000 00000000 FFF00000 00000000 +r 8B10.10 +*Want "MSDB NF +inf/+0/-inf" 7FF80000 00000000 FFF00000 00000000 +r 8B20.10 +*Want "MSDBR NF +inf/+0/-2.0" 7FF80000 00000000 C0000000 00000000 +r 8B30.10 +*Want "MSDB NF +inf/+0/-2.0" 7FF80000 00000000 C0000000 00000000 +r 8B40.10 +*Want "MSDBR NF +inf/+0/-0" 7FF80000 00000000 80000000 00000000 +r 8B50.10 +*Want "MSDB NF +inf/+0/-0" 7FF80000 00000000 80000000 00000000 +r 8B60.10 +*Want "MSDBR NF +inf/+0/+0" 7FF80000 00000000 00000000 00000000 +r 8B70.10 +*Want "MSDB NF +inf/+0/+0" 7FF80000 00000000 00000000 00000000 +r 8B80.10 +*Want "MSDBR NF +inf/+0/+2.0" 7FF80000 00000000 40000000 00000000 +r 8B90.10 +*Want "MSDB NF +inf/+0/+2.0" 7FF80000 00000000 40000000 00000000 +r 8BA0.10 +*Want "MSDBR NF +inf/+0/+inf" 7FF80000 00000000 7FF00000 00000000 +r 8BB0.10 +*Want "MSDB NF +inf/+0/+inf" 7FF80000 00000000 7FF00000 00000000 +r 8BC0.10 +*Want "MSDBR NF +inf/+0/-QNaN" 7FF80000 00000000 FFF8B000 00000000 +r 8BD0.10 +*Want "MSDB NF +inf/+0/-QNaN" 7FF80000 00000000 FFF8B000 00000000 +r 8BE0.10 +*Want "MSDBR NF +inf/+0/+SNaN" 7FF80000 00000000 7FF0A000 00000000 +r 8BF0.10 +*Want "MSDB NF +inf/+0/+SNaN" 7FF80000 00000000 7FF0A000 00000000 +r 8C00.10 +*Want "MSDBR NF +inf/+2.0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 8C10.10 +*Want "MSDB NF +inf/+2.0/-inf" 7FF00000 00000000 7FF00000 00000000 +r 8C20.10 +*Want "MSDBR NF +inf/+2.0/-2.0" 7FF00000 00000000 7FF00000 00000000 +r 8C30.10 +*Want "MSDB NF +inf/+2.0/-2.0" 7FF00000 00000000 7FF00000 00000000 +r 8C40.10 +*Want "MSDBR NF +inf/+2.0/-0" 7FF00000 00000000 7FF00000 00000000 +r 8C50.10 +*Want "MSDB NF +inf/+2.0/-0" 7FF00000 00000000 7FF00000 00000000 +r 8C60.10 +*Want "MSDBR NF +inf/+2.0/+0" 7FF00000 00000000 7FF00000 00000000 +r 8C70.10 +*Want "MSDB NF +inf/+2.0/+0" 7FF00000 00000000 7FF00000 00000000 +r 8C80.10 +*Want "MSDBR NF +inf/+2.0/+2.0" 7FF00000 00000000 7FF00000 00000000 +r 8C90.10 +*Want "MSDB NF +inf/+2.0/+2.0" 7FF00000 00000000 7FF00000 00000000 +r 8CA0.10 +*Want "MSDBR NF +inf/+2.0/+inf" 7FF80000 00000000 7FF00000 00000000 +r 8CB0.10 +*Want "MSDB NF +inf/+2.0/+inf" 7FF80000 00000000 7FF00000 00000000 +r 8CC0.10 +*Want "MSDBR NF +inf/+2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 8CD0.10 +*Want "MSDB NF +inf/+2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 8CE0.10 +*Want "MSDBR NF +inf/+2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8CF0.10 +*Want "MSDB NF +inf/+2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8D00.10 +*Want "MSDBR NF +inf/+inf/-inf" 7FF00000 00000000 7FF00000 00000000 +r 8D10.10 +*Want "MSDB NF +inf/+inf/-inf" 7FF00000 00000000 7FF00000 00000000 +r 8D20.10 +*Want "MSDBR NF +inf/+inf/-2.0" 7FF00000 00000000 7FF00000 00000000 +r 8D30.10 +*Want "MSDB NF +inf/+inf/-2.0" 7FF00000 00000000 7FF00000 00000000 +r 8D40.10 +*Want "MSDBR NF +inf/+inf/-0" 7FF00000 00000000 7FF00000 00000000 +r 8D50.10 +*Want "MSDB NF +inf/+inf/-0" 7FF00000 00000000 7FF00000 00000000 +r 8D60.10 +*Want "MSDBR NF +inf/+inf/+0" 7FF00000 00000000 7FF00000 00000000 +r 8D70.10 +*Want "MSDB NF +inf/+inf/+0" 7FF00000 00000000 7FF00000 00000000 +r 8D80.10 +*Want "MSDBR NF +inf/+inf/+2.0" 7FF00000 00000000 7FF00000 00000000 +r 8D90.10 +*Want "MSDB NF +inf/+inf/+2.0" 7FF00000 00000000 7FF00000 00000000 +r 8DA0.10 +*Want "MSDBR NF +inf/+inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 8DB0.10 +*Want "MSDB NF +inf/+inf/+inf" 7FF80000 00000000 7FF00000 00000000 +r 8DC0.10 +*Want "MSDBR NF +inf/+inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 8DD0.10 +*Want "MSDB NF +inf/+inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 8DE0.10 +*Want "MSDBR NF +inf/+inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8DF0.10 +*Want "MSDB NF +inf/+inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8E00.10 +*Want "MSDBR NF +inf/-QNaN/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 8E10.10 +*Want "MSDB NF +inf/-QNaN/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 8E20.10 +*Want "MSDBR NF +inf/-QNaN/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 8E30.10 +*Want "MSDB NF +inf/-QNaN/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 8E40.10 +*Want "MSDBR NF +inf/-QNaN/-0" FFF8B000 00000000 FFF8B000 00000000 +r 8E50.10 +*Want "MSDB NF +inf/-QNaN/-0" FFF8B000 00000000 FFF8B000 00000000 +r 8E60.10 +*Want "MSDBR NF +inf/-QNaN/+0" FFF8B000 00000000 FFF8B000 00000000 +r 8E70.10 +*Want "MSDB NF +inf/-QNaN/+0" FFF8B000 00000000 FFF8B000 00000000 +r 8E80.10 +*Want "MSDBR NF +inf/-QNaN/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 8E90.10 +*Want "MSDB NF +inf/-QNaN/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 8EA0.10 +*Want "MSDBR NF +inf/-QNaN/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 8EB0.10 +*Want "MSDB NF +inf/-QNaN/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 8EC0.10 +*Want "MSDBR NF +inf/-QNaN/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 8ED0.10 +*Want "MSDB NF +inf/-QNaN/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 8EE0.10 +*Want "MSDBR NF +inf/-QNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8EF0.10 +*Want "MSDB NF +inf/-QNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8F00.10 +*Want "MSDBR NF +inf/+SNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 8F10.10 +*Want "MSDB NF +inf/+SNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 8F20.10 +*Want "MSDBR NF +inf/+SNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 8F30.10 +*Want "MSDB NF +inf/+SNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 8F40.10 +*Want "MSDBR NF +inf/+SNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 8F50.10 +*Want "MSDB NF +inf/+SNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 8F60.10 +*Want "MSDBR NF +inf/+SNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 8F70.10 +*Want "MSDB NF +inf/+SNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 8F80.10 +*Want "MSDBR NF +inf/+SNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 8F90.10 +*Want "MSDB NF +inf/+SNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 8FA0.10 +*Want "MSDBR NF +inf/+SNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 8FB0.10 +*Want "MSDB NF +inf/+SNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 8FC0.10 +*Want "MSDBR NF +inf/+SNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 8FD0.10 +*Want "MSDB NF +inf/+SNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 8FE0.10 +*Want "MSDBR NF +inf/+SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 8FF0.10 +*Want "MSDB NF +inf/+SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9000.10 +*Want "MSDBR NF -QNaN/-inf/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 9010.10 +*Want "MSDB NF -QNaN/-inf/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 9020.10 +*Want "MSDBR NF -QNaN/-inf/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9030.10 +*Want "MSDB NF -QNaN/-inf/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9040.10 +*Want "MSDBR NF -QNaN/-inf/-0" FFF8B000 00000000 FFF8B000 00000000 +r 9050.10 +*Want "MSDB NF -QNaN/-inf/-0" FFF8B000 00000000 FFF8B000 00000000 +r 9060.10 +*Want "MSDBR NF -QNaN/-inf/+0" FFF8B000 00000000 FFF8B000 00000000 +r 9070.10 +*Want "MSDB NF -QNaN/-inf/+0" FFF8B000 00000000 FFF8B000 00000000 +r 9080.10 +*Want "MSDBR NF -QNaN/-inf/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9090.10 +*Want "MSDB NF -QNaN/-inf/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 90A0.10 +*Want "MSDBR NF -QNaN/-inf/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 90B0.10 +*Want "MSDB NF -QNaN/-inf/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 90C0.10 +*Want "MSDBR NF -QNaN/-inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 90D0.10 +*Want "MSDB NF -QNaN/-inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 90E0.10 +*Want "MSDBR NF -QNaN/-inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 90F0.10 +*Want "MSDB NF -QNaN/-inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9100.10 +*Want "MSDBR NF -QNaN/-2.0/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 9110.10 +*Want "MSDB NF -QNaN/-2.0/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 9120.10 +*Want "MSDBR NF -QNaN/-2.0/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9130.10 +*Want "MSDB NF -QNaN/-2.0/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9140.10 +*Want "MSDBR NF -QNaN/-2.0/-0" FFF8B000 00000000 FFF8B000 00000000 +r 9150.10 +*Want "MSDB NF -QNaN/-2.0/-0" FFF8B000 00000000 FFF8B000 00000000 +r 9160.10 +*Want "MSDBR NF -QNaN/-2.0/+0" FFF8B000 00000000 FFF8B000 00000000 +r 9170.10 +*Want "MSDB NF -QNaN/-2.0/+0" FFF8B000 00000000 FFF8B000 00000000 +r 9180.10 +*Want "MSDBR NF -QNaN/-2.0/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9190.10 +*Want "MSDB NF -QNaN/-2.0/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 91A0.10 +*Want "MSDBR NF -QNaN/-2.0/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 91B0.10 +*Want "MSDB NF -QNaN/-2.0/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 91C0.10 +*Want "MSDBR NF -QNaN/-2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 91D0.10 +*Want "MSDB NF -QNaN/-2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 91E0.10 +*Want "MSDBR NF -QNaN/-2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 91F0.10 +*Want "MSDB NF -QNaN/-2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9200.10 +*Want "MSDBR NF -QNaN/-0/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 9210.10 +*Want "MSDB NF -QNaN/-0/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 9220.10 +*Want "MSDBR NF -QNaN/-0/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9230.10 +*Want "MSDB NF -QNaN/-0/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9240.10 +*Want "MSDBR NF -QNaN/-0/-0" FFF8B000 00000000 FFF8B000 00000000 +r 9250.10 +*Want "MSDB NF -QNaN/-0/-0" FFF8B000 00000000 FFF8B000 00000000 +r 9260.10 +*Want "MSDBR NF -QNaN/-0/+0" FFF8B000 00000000 FFF8B000 00000000 +r 9270.10 +*Want "MSDB NF -QNaN/-0/+0" FFF8B000 00000000 FFF8B000 00000000 +r 9280.10 +*Want "MSDBR NF -QNaN/-0/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9290.10 +*Want "MSDB NF -QNaN/-0/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 92A0.10 +*Want "MSDBR NF -QNaN/-0/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 92B0.10 +*Want "MSDB NF -QNaN/-0/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 92C0.10 +*Want "MSDBR NF -QNaN/-0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 92D0.10 +*Want "MSDB NF -QNaN/-0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 92E0.10 +*Want "MSDBR NF -QNaN/-0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 92F0.10 +*Want "MSDB NF -QNaN/-0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9300.10 +*Want "MSDBR NF -QNaN/+0/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 9310.10 +*Want "MSDB NF -QNaN/+0/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 9320.10 +*Want "MSDBR NF -QNaN/+0/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9330.10 +*Want "MSDB NF -QNaN/+0/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9340.10 +*Want "MSDBR NF -QNaN/+0/-0" FFF8B000 00000000 FFF8B000 00000000 +r 9350.10 +*Want "MSDB NF -QNaN/+0/-0" FFF8B000 00000000 FFF8B000 00000000 +r 9360.10 +*Want "MSDBR NF -QNaN/+0/+0" FFF8B000 00000000 FFF8B000 00000000 +r 9370.10 +*Want "MSDB NF -QNaN/+0/+0" FFF8B000 00000000 FFF8B000 00000000 +r 9380.10 +*Want "MSDBR NF -QNaN/+0/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9390.10 +*Want "MSDB NF -QNaN/+0/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 93A0.10 +*Want "MSDBR NF -QNaN/+0/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 93B0.10 +*Want "MSDB NF -QNaN/+0/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 93C0.10 +*Want "MSDBR NF -QNaN/+0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 93D0.10 +*Want "MSDB NF -QNaN/+0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 93E0.10 +*Want "MSDBR NF -QNaN/+0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 93F0.10 +*Want "MSDB NF -QNaN/+0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9400.10 +*Want "MSDBR NF -QNaN/+2.0/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 9410.10 +*Want "MSDB NF -QNaN/+2.0/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 9420.10 +*Want "MSDBR NF -QNaN/+2.0/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9430.10 +*Want "MSDB NF -QNaN/+2.0/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9440.10 +*Want "MSDBR NF -QNaN/+2.0/-0" FFF8B000 00000000 FFF8B000 00000000 +r 9450.10 +*Want "MSDB NF -QNaN/+2.0/-0" FFF8B000 00000000 FFF8B000 00000000 +r 9460.10 +*Want "MSDBR NF -QNaN/+2.0/+0" FFF8B000 00000000 FFF8B000 00000000 +r 9470.10 +*Want "MSDB NF -QNaN/+2.0/+0" FFF8B000 00000000 FFF8B000 00000000 +r 9480.10 +*Want "MSDBR NF -QNaN/+2.0/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9490.10 +*Want "MSDB NF -QNaN/+2.0/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 94A0.10 +*Want "MSDBR NF -QNaN/+2.0/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 94B0.10 +*Want "MSDB NF -QNaN/+2.0/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 94C0.10 +*Want "MSDBR NF -QNaN/+2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 94D0.10 +*Want "MSDB NF -QNaN/+2.0/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 94E0.10 +*Want "MSDBR NF -QNaN/+2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 94F0.10 +*Want "MSDB NF -QNaN/+2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9500.10 +*Want "MSDBR NF -QNaN/+inf/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 9510.10 +*Want "MSDB NF -QNaN/+inf/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 9520.10 +*Want "MSDBR NF -QNaN/+inf/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9530.10 +*Want "MSDB NF -QNaN/+inf/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9540.10 +*Want "MSDBR NF -QNaN/+inf/-0" FFF8B000 00000000 FFF8B000 00000000 +r 9550.10 +*Want "MSDB NF -QNaN/+inf/-0" FFF8B000 00000000 FFF8B000 00000000 +r 9560.10 +*Want "MSDBR NF -QNaN/+inf/+0" FFF8B000 00000000 FFF8B000 00000000 +r 9570.10 +*Want "MSDB NF -QNaN/+inf/+0" FFF8B000 00000000 FFF8B000 00000000 +r 9580.10 +*Want "MSDBR NF -QNaN/+inf/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9590.10 +*Want "MSDB NF -QNaN/+inf/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 95A0.10 +*Want "MSDBR NF -QNaN/+inf/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 95B0.10 +*Want "MSDB NF -QNaN/+inf/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 95C0.10 +*Want "MSDBR NF -QNaN/+inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 95D0.10 +*Want "MSDB NF -QNaN/+inf/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 95E0.10 +*Want "MSDBR NF -QNaN/+inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 95F0.10 +*Want "MSDB NF -QNaN/+inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9600.10 +*Want "MSDBR NF -QNaN/-QNaN/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 9610.10 +*Want "MSDB NF -QNaN/-QNaN/-inf" FFF8B000 00000000 FFF8B000 00000000 +r 9620.10 +*Want "MSDBR NF -QNaN/-QNaN/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9630.10 +*Want "MSDB NF -QNaN/-QNaN/-2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9640.10 +*Want "MSDBR NF -QNaN/-QNaN/-0" FFF8B000 00000000 FFF8B000 00000000 +r 9650.10 +*Want "MSDB NF -QNaN/-QNaN/-0" FFF8B000 00000000 FFF8B000 00000000 +r 9660.10 +*Want "MSDBR NF -QNaN/-QNaN/+0" FFF8B000 00000000 FFF8B000 00000000 +r 9670.10 +*Want "MSDB NF -QNaN/-QNaN/+0" FFF8B000 00000000 FFF8B000 00000000 +r 9680.10 +*Want "MSDBR NF -QNaN/-QNaN/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 9690.10 +*Want "MSDB NF -QNaN/-QNaN/+2.0" FFF8B000 00000000 FFF8B000 00000000 +r 96A0.10 +*Want "MSDBR NF -QNaN/-QNaN/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 96B0.10 +*Want "MSDB NF -QNaN/-QNaN/+inf" FFF8B000 00000000 FFF8B000 00000000 +r 96C0.10 +*Want "MSDBR NF -QNaN/-QNaN/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 96D0.10 +*Want "MSDB NF -QNaN/-QNaN/-QNaN" FFF8B000 00000000 FFF8B000 00000000 +r 96E0.10 +*Want "MSDBR NF -QNaN/-QNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 96F0.10 +*Want "MSDB NF -QNaN/-QNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9700.10 +*Want "MSDBR NF -QNaN/+SNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9710.10 +*Want "MSDB NF -QNaN/+SNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9720.10 +*Want "MSDBR NF -QNaN/+SNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9730.10 +*Want "MSDB NF -QNaN/+SNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9740.10 +*Want "MSDBR NF -QNaN/+SNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 9750.10 +*Want "MSDB NF -QNaN/+SNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 9760.10 +*Want "MSDBR NF -QNaN/+SNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 9770.10 +*Want "MSDB NF -QNaN/+SNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 9780.10 +*Want "MSDBR NF -QNaN/+SNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 9790.10 +*Want "MSDB NF -QNaN/+SNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 97A0.10 +*Want "MSDBR NF -QNaN/+SNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 97B0.10 +*Want "MSDB NF -QNaN/+SNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 97C0.10 +*Want "MSDBR NF -QNaN/+SNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 97D0.10 +*Want "MSDB NF -QNaN/+SNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 97E0.10 +*Want "MSDBR NF -QNaN/+SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 97F0.10 +*Want "MSDB NF -QNaN/+SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9800.10 +*Want "MSDBR NF +SNaN/-inf/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9810.10 +*Want "MSDB NF +SNaN/-inf/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9820.10 +*Want "MSDBR NF +SNaN/-inf/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9830.10 +*Want "MSDB NF +SNaN/-inf/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9840.10 +*Want "MSDBR NF +SNaN/-inf/-0" 7FF8A000 00000000 80000000 00000000 +r 9850.10 +*Want "MSDB NF +SNaN/-inf/-0" 7FF8A000 00000000 80000000 00000000 +r 9860.10 +*Want "MSDBR NF +SNaN/-inf/+0" 7FF8A000 00000000 00000000 00000000 +r 9870.10 +*Want "MSDB NF +SNaN/-inf/+0" 7FF8A000 00000000 00000000 00000000 +r 9880.10 +*Want "MSDBR NF +SNaN/-inf/+2.0" 7FF8A000 00000000 40000000 00000000 +r 9890.10 +*Want "MSDB NF +SNaN/-inf/+2.0" 7FF8A000 00000000 40000000 00000000 +r 98A0.10 +*Want "MSDBR NF +SNaN/-inf/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 98B0.10 +*Want "MSDB NF +SNaN/-inf/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 98C0.10 +*Want "MSDBR NF +SNaN/-inf/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 98D0.10 +*Want "MSDB NF +SNaN/-inf/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 98E0.10 +*Want "MSDBR NF +SNaN/-inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 98F0.10 +*Want "MSDB NF +SNaN/-inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9900.10 +*Want "MSDBR NF +SNaN/-2.0/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9910.10 +*Want "MSDB NF +SNaN/-2.0/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9920.10 +*Want "MSDBR NF +SNaN/-2.0/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9930.10 +*Want "MSDB NF +SNaN/-2.0/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9940.10 +*Want "MSDBR NF +SNaN/-2.0/-0" 7FF8A000 00000000 80000000 00000000 +r 9950.10 +*Want "MSDB NF +SNaN/-2.0/-0" 7FF8A000 00000000 80000000 00000000 +r 9960.10 +*Want "MSDBR NF +SNaN/-2.0/+0" 7FF8A000 00000000 00000000 00000000 +r 9970.10 +*Want "MSDB NF +SNaN/-2.0/+0" 7FF8A000 00000000 00000000 00000000 +r 9980.10 +*Want "MSDBR NF +SNaN/-2.0/+2.0" 7FF8A000 00000000 40000000 00000000 +r 9990.10 +*Want "MSDB NF +SNaN/-2.0/+2.0" 7FF8A000 00000000 40000000 00000000 +r 99A0.10 +*Want "MSDBR NF +SNaN/-2.0/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 99B0.10 +*Want "MSDB NF +SNaN/-2.0/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 99C0.10 +*Want "MSDBR NF +SNaN/-2.0/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 99D0.10 +*Want "MSDB NF +SNaN/-2.0/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 99E0.10 +*Want "MSDBR NF +SNaN/-2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 99F0.10 +*Want "MSDB NF +SNaN/-2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9A00.10 +*Want "MSDBR NF +SNaN/-0/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9A10.10 +*Want "MSDB NF +SNaN/-0/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9A20.10 +*Want "MSDBR NF +SNaN/-0/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9A30.10 +*Want "MSDB NF +SNaN/-0/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9A40.10 +*Want "MSDBR NF +SNaN/-0/-0" 7FF8A000 00000000 80000000 00000000 +r 9A50.10 +*Want "MSDB NF +SNaN/-0/-0" 7FF8A000 00000000 80000000 00000000 +r 9A60.10 +*Want "MSDBR NF +SNaN/-0/+0" 7FF8A000 00000000 00000000 00000000 +r 9A70.10 +*Want "MSDB NF +SNaN/-0/+0" 7FF8A000 00000000 00000000 00000000 +r 9A80.10 +*Want "MSDBR NF +SNaN/-0/+2.0" 7FF8A000 00000000 40000000 00000000 +r 9A90.10 +*Want "MSDB NF +SNaN/-0/+2.0" 7FF8A000 00000000 40000000 00000000 +r 9AA0.10 +*Want "MSDBR NF +SNaN/-0/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 9AB0.10 +*Want "MSDB NF +SNaN/-0/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 9AC0.10 +*Want "MSDBR NF +SNaN/-0/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 9AD0.10 +*Want "MSDB NF +SNaN/-0/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 9AE0.10 +*Want "MSDBR NF +SNaN/-0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9AF0.10 +*Want "MSDB NF +SNaN/-0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9B00.10 +*Want "MSDBR NF +SNaN/+0/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9B10.10 +*Want "MSDB NF +SNaN/+0/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9B20.10 +*Want "MSDBR NF +SNaN/+0/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9B30.10 +*Want "MSDB NF +SNaN/+0/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9B40.10 +*Want "MSDBR NF +SNaN/+0/-0" 7FF8A000 00000000 80000000 00000000 +r 9B50.10 +*Want "MSDB NF +SNaN/+0/-0" 7FF8A000 00000000 80000000 00000000 +r 9B60.10 +*Want "MSDBR NF +SNaN/+0/+0" 7FF8A000 00000000 00000000 00000000 +r 9B70.10 +*Want "MSDB NF +SNaN/+0/+0" 7FF8A000 00000000 00000000 00000000 +r 9B80.10 +*Want "MSDBR NF +SNaN/+0/+2.0" 7FF8A000 00000000 40000000 00000000 +r 9B90.10 +*Want "MSDB NF +SNaN/+0/+2.0" 7FF8A000 00000000 40000000 00000000 +r 9BA0.10 +*Want "MSDBR NF +SNaN/+0/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 9BB0.10 +*Want "MSDB NF +SNaN/+0/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 9BC0.10 +*Want "MSDBR NF +SNaN/+0/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 9BD0.10 +*Want "MSDB NF +SNaN/+0/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 9BE0.10 +*Want "MSDBR NF +SNaN/+0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9BF0.10 +*Want "MSDB NF +SNaN/+0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9C00.10 +*Want "MSDBR NF +SNaN/+2.0/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9C10.10 +*Want "MSDB NF +SNaN/+2.0/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9C20.10 +*Want "MSDBR NF +SNaN/+2.0/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9C30.10 +*Want "MSDB NF +SNaN/+2.0/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9C40.10 +*Want "MSDBR NF +SNaN/+2.0/-0" 7FF8A000 00000000 80000000 00000000 +r 9C50.10 +*Want "MSDB NF +SNaN/+2.0/-0" 7FF8A000 00000000 80000000 00000000 +r 9C60.10 +*Want "MSDBR NF +SNaN/+2.0/+0" 7FF8A000 00000000 00000000 00000000 +r 9C70.10 +*Want "MSDB NF +SNaN/+2.0/+0" 7FF8A000 00000000 00000000 00000000 +r 9C80.10 +*Want "MSDBR NF +SNaN/+2.0/+2.0" 7FF8A000 00000000 40000000 00000000 +r 9C90.10 +*Want "MSDB NF +SNaN/+2.0/+2.0" 7FF8A000 00000000 40000000 00000000 +r 9CA0.10 +*Want "MSDBR NF +SNaN/+2.0/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 9CB0.10 +*Want "MSDB NF +SNaN/+2.0/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 9CC0.10 +*Want "MSDBR NF +SNaN/+2.0/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 9CD0.10 +*Want "MSDB NF +SNaN/+2.0/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 9CE0.10 +*Want "MSDBR NF +SNaN/+2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9CF0.10 +*Want "MSDB NF +SNaN/+2.0/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9D00.10 +*Want "MSDBR NF +SNaN/+inf/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9D10.10 +*Want "MSDB NF +SNaN/+inf/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9D20.10 +*Want "MSDBR NF +SNaN/+inf/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9D30.10 +*Want "MSDB NF +SNaN/+inf/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9D40.10 +*Want "MSDBR NF +SNaN/+inf/-0" 7FF8A000 00000000 80000000 00000000 +r 9D50.10 +*Want "MSDB NF +SNaN/+inf/-0" 7FF8A000 00000000 80000000 00000000 +r 9D60.10 +*Want "MSDBR NF +SNaN/+inf/+0" 7FF8A000 00000000 00000000 00000000 +r 9D70.10 +*Want "MSDB NF +SNaN/+inf/+0" 7FF8A000 00000000 00000000 00000000 +r 9D80.10 +*Want "MSDBR NF +SNaN/+inf/+2.0" 7FF8A000 00000000 40000000 00000000 +r 9D90.10 +*Want "MSDB NF +SNaN/+inf/+2.0" 7FF8A000 00000000 40000000 00000000 +r 9DA0.10 +*Want "MSDBR NF +SNaN/+inf/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 9DB0.10 +*Want "MSDB NF +SNaN/+inf/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 9DC0.10 +*Want "MSDBR NF +SNaN/+inf/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 9DD0.10 +*Want "MSDB NF +SNaN/+inf/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 9DE0.10 +*Want "MSDBR NF +SNaN/+inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9DF0.10 +*Want "MSDB NF +SNaN/+inf/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9E00.10 +*Want "MSDBR NF +SNaN/-QNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9E10.10 +*Want "MSDB NF +SNaN/-QNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9E20.10 +*Want "MSDBR NF +SNaN/-QNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9E30.10 +*Want "MSDB NF +SNaN/-QNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9E40.10 +*Want "MSDBR NF +SNaN/-QNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 9E50.10 +*Want "MSDB NF +SNaN/-QNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 9E60.10 +*Want "MSDBR NF +SNaN/-QNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 9E70.10 +*Want "MSDB NF +SNaN/-QNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 9E80.10 +*Want "MSDBR NF +SNaN/-QNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 9E90.10 +*Want "MSDB NF +SNaN/-QNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 9EA0.10 +*Want "MSDBR NF +SNaN/-QNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 9EB0.10 +*Want "MSDB NF +SNaN/-QNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 9EC0.10 +*Want "MSDBR NF +SNaN/-QNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 9ED0.10 +*Want "MSDB NF +SNaN/-QNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 9EE0.10 +*Want "MSDBR NF +SNaN/-QNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9EF0.10 +*Want "MSDB NF +SNaN/-QNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9F00.10 +*Want "MSDBR NF +SNaN/+SNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9F10.10 +*Want "MSDB NF +SNaN/+SNaN/-inf" 7FF8A000 00000000 FFF00000 00000000 +r 9F20.10 +*Want "MSDBR NF +SNaN/+SNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9F30.10 +*Want "MSDB NF +SNaN/+SNaN/-2.0" 7FF8A000 00000000 C0000000 00000000 +r 9F40.10 +*Want "MSDBR NF +SNaN/+SNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 9F50.10 +*Want "MSDB NF +SNaN/+SNaN/-0" 7FF8A000 00000000 80000000 00000000 +r 9F60.10 +*Want "MSDBR NF +SNaN/+SNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 9F70.10 +*Want "MSDB NF +SNaN/+SNaN/+0" 7FF8A000 00000000 00000000 00000000 +r 9F80.10 +*Want "MSDBR NF +SNaN/+SNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 9F90.10 +*Want "MSDB NF +SNaN/+SNaN/+2.0" 7FF8A000 00000000 40000000 00000000 +r 9FA0.10 +*Want "MSDBR NF +SNaN/+SNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 9FB0.10 +*Want "MSDB NF +SNaN/+SNaN/+inf" 7FF8A000 00000000 7FF00000 00000000 +r 9FC0.10 +*Want "MSDBR NF +SNaN/+SNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 9FD0.10 +*Want "MSDB NF +SNaN/+SNaN/-QNaN" 7FF8A000 00000000 FFF8B000 00000000 +r 9FE0.10 +*Want "MSDBR NF +SNaN/+SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 +r 9FF0.10 +*Want "MSDB NF +SNaN/+SNaN/+SNaN" 7FF8A000 00000000 7FF0A000 00000000 + + + + +# Long BFP Multiply And Subtract non-finite results - FPCR contents +*Compare +r A000.10 +*Want "MSDBR/MSDB NF -inf/-inf/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r A010.10 +*Want "MSDBR/MSDB NF -inf/-inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A020.10 +*Want "MSDBR/MSDB NF -inf/-inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r A030.10 +*Want "MSDBR/MSDB NF -inf/-inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r A040.10 +*Want "MSDBR/MSDB NF -inf/-inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A050.10 +*Want "MSDBR/MSDB NF -inf/-inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r A060.10 +*Want "MSDBR/MSDB NF -inf/-inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r A070.10 +*Want "MSDBR/MSDB NF -inf/-inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A080.10 +*Want "MSDBR/MSDB NF -inf/-2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r A090.10 +*Want "MSDBR/MSDB NF -inf/-2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A0A0.10 +*Want "MSDBR/MSDB NF -inf/-2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r A0B0.10 +*Want "MSDBR/MSDB NF -inf/-2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r A0C0.10 +*Want "MSDBR/MSDB NF -inf/-2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A0D0.10 +*Want "MSDBR/MSDB NF -inf/-2.0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r A0E0.10 +*Want "MSDBR/MSDB NF -inf/-2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r A0F0.10 +*Want "MSDBR/MSDB NF -inf/-2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A100.10 +*Want "MSDBR/MSDB NF -inf/-0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r A110.10 +*Want "MSDBR/MSDB NF -inf/-0/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r A120.10 +*Want "MSDBR/MSDB NF -inf/-0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r A130.10 +*Want "MSDBR/MSDB NF -inf/-0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r A140.10 +*Want "MSDBR/MSDB NF -inf/-0/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r A150.10 +*Want "MSDBR/MSDB NF -inf/-0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r A160.10 +*Want "MSDBR/MSDB NF -inf/-0/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A170.10 +*Want "MSDBR/MSDB NF -inf/-0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A180.10 +*Want "MSDBR/MSDB NF -inf/+0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r A190.10 +*Want "MSDBR/MSDB NF -inf/+0/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r A1A0.10 +*Want "MSDBR/MSDB NF -inf/+0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r A1B0.10 +*Want "MSDBR/MSDB NF -inf/+0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r A1C0.10 +*Want "MSDBR/MSDB NF -inf/+0/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r A1D0.10 +*Want "MSDBR/MSDB NF -inf/+0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r A1E0.10 +*Want "MSDBR/MSDB NF -inf/+0/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A1F0.10 +*Want "MSDBR/MSDB NF -inf/+0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A200.10 +*Want "MSDBR/MSDB NF -inf/+2.0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r A210.10 +*Want "MSDBR/MSDB NF -inf/+2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A220.10 +*Want "MSDBR/MSDB NF -inf/+2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r A230.10 +*Want "MSDBR/MSDB NF -inf/+2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r A240.10 +*Want "MSDBR/MSDB NF -inf/+2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A250.10 +*Want "MSDBR/MSDB NF -inf/+2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r A260.10 +*Want "MSDBR/MSDB NF -inf/+2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r A270.10 +*Want "MSDBR/MSDB NF -inf/+2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A280.10 +*Want "MSDBR/MSDB NF -inf/+inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r A290.10 +*Want "MSDBR/MSDB NF -inf/+inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A2A0.10 +*Want "MSDBR/MSDB NF -inf/+inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r A2B0.10 +*Want "MSDBR/MSDB NF -inf/+inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r A2C0.10 +*Want "MSDBR/MSDB NF -inf/+inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A2D0.10 +*Want "MSDBR/MSDB NF -inf/+inf/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r A2E0.10 +*Want "MSDBR/MSDB NF -inf/+inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r A2F0.10 +*Want "MSDBR/MSDB NF -inf/+inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A300.10 +*Want "MSDBR/MSDB NF -inf/-QNaN/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r A310.10 +*Want "MSDBR/MSDB NF -inf/-QNaN/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A320.10 +*Want "MSDBR/MSDB NF -inf/-QNaN/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r A330.10 +*Want "MSDBR/MSDB NF -inf/-QNaN/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r A340.10 +*Want "MSDBR/MSDB NF -inf/-QNaN/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A350.10 +*Want "MSDBR/MSDB NF -inf/-QNaN/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r A360.10 +*Want "MSDBR/MSDB NF -inf/-QNaN/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r A370.10 +*Want "MSDBR/MSDB NF -inf/-QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A380.10 +*Want "MSDBR/MSDB NF -inf/+SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r A390.10 +*Want "MSDBR/MSDB NF -inf/+SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r A3A0.10 +*Want "MSDBR/MSDB NF -inf/+SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r A3B0.10 +*Want "MSDBR/MSDB NF -inf/+SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r A3C0.10 +*Want "MSDBR/MSDB NF -inf/+SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r A3D0.10 +*Want "MSDBR/MSDB NF -inf/+SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r A3E0.10 +*Want "MSDBR/MSDB NF -inf/+SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A3F0.10 +*Want "MSDBR/MSDB NF -inf/+SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A400.10 +*Want "MSDBR/MSDB NF -2.0/-inf/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r A410.10 +*Want "MSDBR/MSDB NF -2.0/-inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A420.10 +*Want "MSDBR/MSDB NF -2.0/-inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r A430.10 +*Want "MSDBR/MSDB NF -2.0/-inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r A440.10 +*Want "MSDBR/MSDB NF -2.0/-inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A450.10 +*Want "MSDBR/MSDB NF -2.0/-inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r A460.10 +*Want "MSDBR/MSDB NF -2.0/-inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r A470.10 +*Want "MSDBR/MSDB NF -2.0/-inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A480.10 +*Want "MSDBR/MSDB NF -2.0/-2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r A490.10 +*Want "MSDBR/MSDB NF -2.0/-2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A4A0.10 +*Want "MSDBR/MSDB NF -2.0/-2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r A4B0.10 +*Want "MSDBR/MSDB NF -2.0/-2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r A4C0.10 +*Want "MSDBR/MSDB NF -2.0/-2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A4D0.10 +*Want "MSDBR/MSDB NF -2.0/-2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r A4E0.10 +*Want "MSDBR/MSDB NF -2.0/-2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r A4F0.10 +*Want "MSDBR/MSDB NF -2.0/-2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A500.10 +*Want "MSDBR/MSDB NF -2.0/-0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r A510.10 +*Want "MSDBR/MSDB NF -2.0/-0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A520.10 +*Want "MSDBR/MSDB NF -2.0/-0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r A530.10 +*Want "MSDBR/MSDB NF -2.0/-0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r A540.10 +*Want "MSDBR/MSDB NF -2.0/-0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A550.10 +*Want "MSDBR/MSDB NF -2.0/-0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r A560.10 +*Want "MSDBR/MSDB NF -2.0/-0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r A570.10 +*Want "MSDBR/MSDB NF -2.0/-0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A580.10 +*Want "MSDBR/MSDB NF -2.0/+0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r A590.10 +*Want "MSDBR/MSDB NF -2.0/+0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A5A0.10 +*Want "MSDBR/MSDB NF -2.0/+0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r A5B0.10 +*Want "MSDBR/MSDB NF -2.0/+0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r A5C0.10 +*Want "MSDBR/MSDB NF -2.0/+0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A5D0.10 +*Want "MSDBR/MSDB NF -2.0/+0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r A5E0.10 +*Want "MSDBR/MSDB NF -2.0/+0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r A5F0.10 +*Want "MSDBR/MSDB NF -2.0/+0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A600.10 +*Want "MSDBR/MSDB NF -2.0/+2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r A610.10 +*Want "MSDBR/MSDB NF -2.0/+2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A620.10 +*Want "MSDBR/MSDB NF -2.0/+2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r A630.10 +*Want "MSDBR/MSDB NF -2.0/+2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r A640.10 +*Want "MSDBR/MSDB NF -2.0/+2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A650.10 +*Want "MSDBR/MSDB NF -2.0/+2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r A660.10 +*Want "MSDBR/MSDB NF -2.0/+2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r A670.10 +*Want "MSDBR/MSDB NF -2.0/+2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A680.10 +*Want "MSDBR/MSDB NF -2.0/+inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r A690.10 +*Want "MSDBR/MSDB NF -2.0/+inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A6A0.10 +*Want "MSDBR/MSDB NF -2.0/+inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r A6B0.10 +*Want "MSDBR/MSDB NF -2.0/+inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r A6C0.10 +*Want "MSDBR/MSDB NF -2.0/+inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A6D0.10 +*Want "MSDBR/MSDB NF -2.0/+inf/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r A6E0.10 +*Want "MSDBR/MSDB NF -2.0/+inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r A6F0.10 +*Want "MSDBR/MSDB NF -2.0/+inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A700.10 +*Want "MSDBR/MSDB NF -2.0/-QNaN/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r A710.10 +*Want "MSDBR/MSDB NF -2.0/-QNaN/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A720.10 +*Want "MSDBR/MSDB NF -2.0/-QNaN/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r A730.10 +*Want "MSDBR/MSDB NF -2.0/-QNaN/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r A740.10 +*Want "MSDBR/MSDB NF -2.0/-QNaN/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A750.10 +*Want "MSDBR/MSDB NF -2.0/-QNaN/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r A760.10 +*Want "MSDBR/MSDB NF -2.0/-QNaN/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r A770.10 +*Want "MSDBR/MSDB NF -2.0/-QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A780.10 +*Want "MSDBR/MSDB NF -2.0/+SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r A790.10 +*Want "MSDBR/MSDB NF -2.0/+SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r A7A0.10 +*Want "MSDBR/MSDB NF -2.0/+SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r A7B0.10 +*Want "MSDBR/MSDB NF -2.0/+SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r A7C0.10 +*Want "MSDBR/MSDB NF -2.0/+SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r A7D0.10 +*Want "MSDBR/MSDB NF -2.0/+SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r A7E0.10 +*Want "MSDBR/MSDB NF -2.0/+SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A7F0.10 +*Want "MSDBR/MSDB NF -2.0/+SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A800.10 +*Want "MSDBR/MSDB NF -0/-inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r A810.10 +*Want "MSDBR/MSDB NF -0/-inf/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r A820.10 +*Want "MSDBR/MSDB NF -0/-inf/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r A830.10 +*Want "MSDBR/MSDB NF -0/-inf/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r A840.10 +*Want "MSDBR/MSDB NF -0/-inf/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r A850.10 +*Want "MSDBR/MSDB NF -0/-inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r A860.10 +*Want "MSDBR/MSDB NF -0/-inf/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A870.10 +*Want "MSDBR/MSDB NF -0/-inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A880.10 +*Want "MSDBR/MSDB NF -0/-2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r A890.10 +*Want "MSDBR/MSDB NF -0/-2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A8A0.10 +*Want "MSDBR/MSDB NF -0/-2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r A8B0.10 +*Want "MSDBR/MSDB NF -0/-2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r A8C0.10 +*Want "MSDBR/MSDB NF -0/-2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A8D0.10 +*Want "MSDBR/MSDB NF -0/-2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r A8E0.10 +*Want "MSDBR/MSDB NF -0/-2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r A8F0.10 +*Want "MSDBR/MSDB NF -0/-2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A900.10 +*Want "MSDBR/MSDB NF -0/-0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r A910.10 +*Want "MSDBR/MSDB NF -0/-0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A920.10 +*Want "MSDBR/MSDB NF -0/-0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r A930.10 +*Want "MSDBR/MSDB NF -0/-0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r A940.10 +*Want "MSDBR/MSDB NF -0/-0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A950.10 +*Want "MSDBR/MSDB NF -0/-0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r A960.10 +*Want "MSDBR/MSDB NF -0/-0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r A970.10 +*Want "MSDBR/MSDB NF -0/-0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r A980.10 +*Want "MSDBR/MSDB NF -0/+0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r A990.10 +*Want "MSDBR/MSDB NF -0/+0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A9A0.10 +*Want "MSDBR/MSDB NF -0/+0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r A9B0.10 +*Want "MSDBR/MSDB NF -0/+0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r A9C0.10 +*Want "MSDBR/MSDB NF -0/+0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r A9D0.10 +*Want "MSDBR/MSDB NF -0/+0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r A9E0.10 +*Want "MSDBR/MSDB NF -0/+0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r A9F0.10 +*Want "MSDBR/MSDB NF -0/+0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r AA00.10 +*Want "MSDBR/MSDB NF -0/+2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r AA10.10 +*Want "MSDBR/MSDB NF -0/+2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r AA20.10 +*Want "MSDBR/MSDB NF -0/+2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r AA30.10 +*Want "MSDBR/MSDB NF -0/+2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r AA40.10 +*Want "MSDBR/MSDB NF -0/+2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r AA50.10 +*Want "MSDBR/MSDB NF -0/+2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r AA60.10 +*Want "MSDBR/MSDB NF -0/+2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r AA70.10 +*Want "MSDBR/MSDB NF -0/+2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r AA80.10 +*Want "MSDBR/MSDB NF -0/+inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r AA90.10 +*Want "MSDBR/MSDB NF -0/+inf/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r AAA0.10 +*Want "MSDBR/MSDB NF -0/+inf/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r AAB0.10 +*Want "MSDBR/MSDB NF -0/+inf/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r AAC0.10 +*Want "MSDBR/MSDB NF -0/+inf/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r AAD0.10 +*Want "MSDBR/MSDB NF -0/+inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r AAE0.10 +*Want "MSDBR/MSDB NF -0/+inf/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r AAF0.10 +*Want "MSDBR/MSDB NF -0/+inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r AB00.10 +*Want "MSDBR/MSDB NF -0/-QNaN/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r AB10.10 +*Want "MSDBR/MSDB NF -0/-QNaN/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r AB20.10 +*Want "MSDBR/MSDB NF -0/-QNaN/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r AB30.10 +*Want "MSDBR/MSDB NF -0/-QNaN/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r AB40.10 +*Want "MSDBR/MSDB NF -0/-QNaN/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r AB50.10 +*Want "MSDBR/MSDB NF -0/-QNaN/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r AB60.10 +*Want "MSDBR/MSDB NF -0/-QNaN/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r AB70.10 +*Want "MSDBR/MSDB NF -0/-QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r AB80.10 +*Want "MSDBR/MSDB NF -0/+SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r AB90.10 +*Want "MSDBR/MSDB NF -0/+SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r ABA0.10 +*Want "MSDBR/MSDB NF -0/+SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r ABB0.10 +*Want "MSDBR/MSDB NF -0/+SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r ABC0.10 +*Want "MSDBR/MSDB NF -0/+SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r ABD0.10 +*Want "MSDBR/MSDB NF -0/+SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r ABE0.10 +*Want "MSDBR/MSDB NF -0/+SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r ABF0.10 +*Want "MSDBR/MSDB NF -0/+SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r AC00.10 +*Want "MSDBR/MSDB NF +0/-inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r AC10.10 +*Want "MSDBR/MSDB NF +0/-inf/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r AC20.10 +*Want "MSDBR/MSDB NF +0/-inf/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r AC30.10 +*Want "MSDBR/MSDB NF +0/-inf/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r AC40.10 +*Want "MSDBR/MSDB NF +0/-inf/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r AC50.10 +*Want "MSDBR/MSDB NF +0/-inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r AC60.10 +*Want "MSDBR/MSDB NF +0/-inf/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r AC70.10 +*Want "MSDBR/MSDB NF +0/-inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r AC80.10 +*Want "MSDBR/MSDB NF +0/-2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r AC90.10 +*Want "MSDBR/MSDB NF +0/-2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r ACA0.10 +*Want "MSDBR/MSDB NF +0/-2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r ACB0.10 +*Want "MSDBR/MSDB NF +0/-2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r ACC0.10 +*Want "MSDBR/MSDB NF +0/-2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r ACD0.10 +*Want "MSDBR/MSDB NF +0/-2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r ACE0.10 +*Want "MSDBR/MSDB NF +0/-2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r ACF0.10 +*Want "MSDBR/MSDB NF +0/-2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r AD00.10 +*Want "MSDBR/MSDB NF +0/-0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r AD10.10 +*Want "MSDBR/MSDB NF +0/-0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r AD20.10 +*Want "MSDBR/MSDB NF +0/-0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r AD30.10 +*Want "MSDBR/MSDB NF +0/-0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r AD40.10 +*Want "MSDBR/MSDB NF +0/-0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r AD50.10 +*Want "MSDBR/MSDB NF +0/-0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r AD60.10 +*Want "MSDBR/MSDB NF +0/-0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r AD70.10 +*Want "MSDBR/MSDB NF +0/-0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r AD80.10 +*Want "MSDBR/MSDB NF +0/+0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r AD90.10 +*Want "MSDBR/MSDB NF +0/+0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r ADA0.10 +*Want "MSDBR/MSDB NF +0/+0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r ADB0.10 +*Want "MSDBR/MSDB NF +0/+0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r ADC0.10 +*Want "MSDBR/MSDB NF +0/+0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r ADD0.10 +*Want "MSDBR/MSDB NF +0/+0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r ADE0.10 +*Want "MSDBR/MSDB NF +0/+0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r ADF0.10 +*Want "MSDBR/MSDB NF +0/+0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r AE00.10 +*Want "MSDBR/MSDB NF +0/+2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r AE10.10 +*Want "MSDBR/MSDB NF +0/+2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r AE20.10 +*Want "MSDBR/MSDB NF +0/+2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r AE30.10 +*Want "MSDBR/MSDB NF +0/+2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r AE40.10 +*Want "MSDBR/MSDB NF +0/+2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r AE50.10 +*Want "MSDBR/MSDB NF +0/+2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r AE60.10 +*Want "MSDBR/MSDB NF +0/+2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r AE70.10 +*Want "MSDBR/MSDB NF +0/+2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r AE80.10 +*Want "MSDBR/MSDB NF +0/+inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r AE90.10 +*Want "MSDBR/MSDB NF +0/+inf/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r AEA0.10 +*Want "MSDBR/MSDB NF +0/+inf/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r AEB0.10 +*Want "MSDBR/MSDB NF +0/+inf/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r AEC0.10 +*Want "MSDBR/MSDB NF +0/+inf/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r AED0.10 +*Want "MSDBR/MSDB NF +0/+inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r AEE0.10 +*Want "MSDBR/MSDB NF +0/+inf/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r AEF0.10 +*Want "MSDBR/MSDB NF +0/+inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r AF00.10 +*Want "MSDBR/MSDB NF +0/-QNaN/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r AF10.10 +*Want "MSDBR/MSDB NF +0/-QNaN/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r AF20.10 +*Want "MSDBR/MSDB NF +0/-QNaN/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r AF30.10 +*Want "MSDBR/MSDB NF +0/-QNaN/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r AF40.10 +*Want "MSDBR/MSDB NF +0/-QNaN/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r AF50.10 +*Want "MSDBR/MSDB NF +0/-QNaN/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r AF60.10 +*Want "MSDBR/MSDB NF +0/-QNaN/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r AF70.10 +*Want "MSDBR/MSDB NF +0/-QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r AF80.10 +*Want "MSDBR/MSDB NF +0/+SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r AF90.10 +*Want "MSDBR/MSDB NF +0/+SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r AFA0.10 +*Want "MSDBR/MSDB NF +0/+SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r AFB0.10 +*Want "MSDBR/MSDB NF +0/+SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r AFC0.10 +*Want "MSDBR/MSDB NF +0/+SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r AFD0.10 +*Want "MSDBR/MSDB NF +0/+SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r AFE0.10 +*Want "MSDBR/MSDB NF +0/+SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r AFF0.10 +*Want "MSDBR/MSDB NF +0/+SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B000.10 +*Want "MSDBR/MSDB NF +2.0/-inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r B010.10 +*Want "MSDBR/MSDB NF +2.0/-inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B020.10 +*Want "MSDBR/MSDB NF +2.0/-inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r B030.10 +*Want "MSDBR/MSDB NF +2.0/-inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r B040.10 +*Want "MSDBR/MSDB NF +2.0/-inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B050.10 +*Want "MSDBR/MSDB NF +2.0/-inf/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r B060.10 +*Want "MSDBR/MSDB NF +2.0/-inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r B070.10 +*Want "MSDBR/MSDB NF +2.0/-inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B080.10 +*Want "MSDBR/MSDB NF +2.0/-2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r B090.10 +*Want "MSDBR/MSDB NF +2.0/-2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B0A0.10 +*Want "MSDBR/MSDB NF +2.0/-2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r B0B0.10 +*Want "MSDBR/MSDB NF +2.0/-2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r B0C0.10 +*Want "MSDBR/MSDB NF +2.0/-2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B0D0.10 +*Want "MSDBR/MSDB NF +2.0/-2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r B0E0.10 +*Want "MSDBR/MSDB NF +2.0/-2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r B0F0.10 +*Want "MSDBR/MSDB NF +2.0/-2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B100.10 +*Want "MSDBR/MSDB NF +2.0/-0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r B110.10 +*Want "MSDBR/MSDB NF +2.0/-0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B120.10 +*Want "MSDBR/MSDB NF +2.0/-0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r B130.10 +*Want "MSDBR/MSDB NF +2.0/-0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r B140.10 +*Want "MSDBR/MSDB NF +2.0/-0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B150.10 +*Want "MSDBR/MSDB NF +2.0/-0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r B160.10 +*Want "MSDBR/MSDB NF +2.0/-0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r B170.10 +*Want "MSDBR/MSDB NF +2.0/-0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B180.10 +*Want "MSDBR/MSDB NF +2.0/+0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r B190.10 +*Want "MSDBR/MSDB NF +2.0/+0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B1A0.10 +*Want "MSDBR/MSDB NF +2.0/+0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r B1B0.10 +*Want "MSDBR/MSDB NF +2.0/+0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r B1C0.10 +*Want "MSDBR/MSDB NF +2.0/+0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B1D0.10 +*Want "MSDBR/MSDB NF +2.0/+0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r B1E0.10 +*Want "MSDBR/MSDB NF +2.0/+0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r B1F0.10 +*Want "MSDBR/MSDB NF +2.0/+0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B200.10 +*Want "MSDBR/MSDB NF +2.0/+2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r B210.10 +*Want "MSDBR/MSDB NF +2.0/+2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B220.10 +*Want "MSDBR/MSDB NF +2.0/+2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r B230.10 +*Want "MSDBR/MSDB NF +2.0/+2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r B240.10 +*Want "MSDBR/MSDB NF +2.0/+2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B250.10 +*Want "MSDBR/MSDB NF +2.0/+2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r B260.10 +*Want "MSDBR/MSDB NF +2.0/+2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r B270.10 +*Want "MSDBR/MSDB NF +2.0/+2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B280.10 +*Want "MSDBR/MSDB NF +2.0/+inf/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r B290.10 +*Want "MSDBR/MSDB NF +2.0/+inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B2A0.10 +*Want "MSDBR/MSDB NF +2.0/+inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r B2B0.10 +*Want "MSDBR/MSDB NF +2.0/+inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r B2C0.10 +*Want "MSDBR/MSDB NF +2.0/+inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B2D0.10 +*Want "MSDBR/MSDB NF +2.0/+inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r B2E0.10 +*Want "MSDBR/MSDB NF +2.0/+inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r B2F0.10 +*Want "MSDBR/MSDB NF +2.0/+inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B300.10 +*Want "MSDBR/MSDB NF +2.0/-QNaN/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r B310.10 +*Want "MSDBR/MSDB NF +2.0/-QNaN/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B320.10 +*Want "MSDBR/MSDB NF +2.0/-QNaN/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r B330.10 +*Want "MSDBR/MSDB NF +2.0/-QNaN/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r B340.10 +*Want "MSDBR/MSDB NF +2.0/-QNaN/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B350.10 +*Want "MSDBR/MSDB NF +2.0/-QNaN/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r B360.10 +*Want "MSDBR/MSDB NF +2.0/-QNaN/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r B370.10 +*Want "MSDBR/MSDB NF +2.0/-QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B380.10 +*Want "MSDBR/MSDB NF +2.0/+SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r B390.10 +*Want "MSDBR/MSDB NF +2.0/+SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r B3A0.10 +*Want "MSDBR/MSDB NF +2.0/+SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r B3B0.10 +*Want "MSDBR/MSDB NF +2.0/+SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r B3C0.10 +*Want "MSDBR/MSDB NF +2.0/+SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r B3D0.10 +*Want "MSDBR/MSDB NF +2.0/+SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r B3E0.10 +*Want "MSDBR/MSDB NF +2.0/+SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B3F0.10 +*Want "MSDBR/MSDB NF +2.0/+SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B400.10 +*Want "MSDBR/MSDB NF +inf/-inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r B410.10 +*Want "MSDBR/MSDB NF +inf/-inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B420.10 +*Want "MSDBR/MSDB NF +inf/-inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r B430.10 +*Want "MSDBR/MSDB NF +inf/-inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r B440.10 +*Want "MSDBR/MSDB NF +inf/-inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B450.10 +*Want "MSDBR/MSDB NF +inf/-inf/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r B460.10 +*Want "MSDBR/MSDB NF +inf/-inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r B470.10 +*Want "MSDBR/MSDB NF +inf/-inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B480.10 +*Want "MSDBR/MSDB NF +inf/-2.0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r B490.10 +*Want "MSDBR/MSDB NF +inf/-2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B4A0.10 +*Want "MSDBR/MSDB NF +inf/-2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r B4B0.10 +*Want "MSDBR/MSDB NF +inf/-2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r B4C0.10 +*Want "MSDBR/MSDB NF +inf/-2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B4D0.10 +*Want "MSDBR/MSDB NF +inf/-2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r B4E0.10 +*Want "MSDBR/MSDB NF +inf/-2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r B4F0.10 +*Want "MSDBR/MSDB NF +inf/-2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B500.10 +*Want "MSDBR/MSDB NF +inf/-0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r B510.10 +*Want "MSDBR/MSDB NF +inf/-0/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r B520.10 +*Want "MSDBR/MSDB NF +inf/-0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r B530.10 +*Want "MSDBR/MSDB NF +inf/-0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r B540.10 +*Want "MSDBR/MSDB NF +inf/-0/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r B550.10 +*Want "MSDBR/MSDB NF +inf/-0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r B560.10 +*Want "MSDBR/MSDB NF +inf/-0/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B570.10 +*Want "MSDBR/MSDB NF +inf/-0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B580.10 +*Want "MSDBR/MSDB NF +inf/+0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r B590.10 +*Want "MSDBR/MSDB NF +inf/+0/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r B5A0.10 +*Want "MSDBR/MSDB NF +inf/+0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r B5B0.10 +*Want "MSDBR/MSDB NF +inf/+0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r B5C0.10 +*Want "MSDBR/MSDB NF +inf/+0/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r B5D0.10 +*Want "MSDBR/MSDB NF +inf/+0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r B5E0.10 +*Want "MSDBR/MSDB NF +inf/+0/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B5F0.10 +*Want "MSDBR/MSDB NF +inf/+0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B600.10 +*Want "MSDBR/MSDB NF +inf/+2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r B610.10 +*Want "MSDBR/MSDB NF +inf/+2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B620.10 +*Want "MSDBR/MSDB NF +inf/+2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r B630.10 +*Want "MSDBR/MSDB NF +inf/+2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r B640.10 +*Want "MSDBR/MSDB NF +inf/+2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B650.10 +*Want "MSDBR/MSDB NF +inf/+2.0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r B660.10 +*Want "MSDBR/MSDB NF +inf/+2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r B670.10 +*Want "MSDBR/MSDB NF +inf/+2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B680.10 +*Want "MSDBR/MSDB NF +inf/+inf/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r B690.10 +*Want "MSDBR/MSDB NF +inf/+inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B6A0.10 +*Want "MSDBR/MSDB NF +inf/+inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r B6B0.10 +*Want "MSDBR/MSDB NF +inf/+inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r B6C0.10 +*Want "MSDBR/MSDB NF +inf/+inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B6D0.10 +*Want "MSDBR/MSDB NF +inf/+inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r B6E0.10 +*Want "MSDBR/MSDB NF +inf/+inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r B6F0.10 +*Want "MSDBR/MSDB NF +inf/+inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B700.10 +*Want "MSDBR/MSDB NF +inf/-QNaN/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r B710.10 +*Want "MSDBR/MSDB NF +inf/-QNaN/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B720.10 +*Want "MSDBR/MSDB NF +inf/-QNaN/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r B730.10 +*Want "MSDBR/MSDB NF +inf/-QNaN/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r B740.10 +*Want "MSDBR/MSDB NF +inf/-QNaN/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B750.10 +*Want "MSDBR/MSDB NF +inf/-QNaN/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r B760.10 +*Want "MSDBR/MSDB NF +inf/-QNaN/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r B770.10 +*Want "MSDBR/MSDB NF +inf/-QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B780.10 +*Want "MSDBR/MSDB NF +inf/+SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r B790.10 +*Want "MSDBR/MSDB NF +inf/+SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r B7A0.10 +*Want "MSDBR/MSDB NF +inf/+SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r B7B0.10 +*Want "MSDBR/MSDB NF +inf/+SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r B7C0.10 +*Want "MSDBR/MSDB NF +inf/+SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r B7D0.10 +*Want "MSDBR/MSDB NF +inf/+SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r B7E0.10 +*Want "MSDBR/MSDB NF +inf/+SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B7F0.10 +*Want "MSDBR/MSDB NF +inf/+SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B800.10 +*Want "MSDBR/MSDB NF -QNaN/-inf/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r B810.10 +*Want "MSDBR/MSDB NF -QNaN/-inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B820.10 +*Want "MSDBR/MSDB NF -QNaN/-inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r B830.10 +*Want "MSDBR/MSDB NF -QNaN/-inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r B840.10 +*Want "MSDBR/MSDB NF -QNaN/-inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B850.10 +*Want "MSDBR/MSDB NF -QNaN/-inf/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r B860.10 +*Want "MSDBR/MSDB NF -QNaN/-inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r B870.10 +*Want "MSDBR/MSDB NF -QNaN/-inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B880.10 +*Want "MSDBR/MSDB NF -QNaN/-2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r B890.10 +*Want "MSDBR/MSDB NF -QNaN/-2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B8A0.10 +*Want "MSDBR/MSDB NF -QNaN/-2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r B8B0.10 +*Want "MSDBR/MSDB NF -QNaN/-2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r B8C0.10 +*Want "MSDBR/MSDB NF -QNaN/-2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B8D0.10 +*Want "MSDBR/MSDB NF -QNaN/-2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r B8E0.10 +*Want "MSDBR/MSDB NF -QNaN/-2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r B8F0.10 +*Want "MSDBR/MSDB NF -QNaN/-2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B900.10 +*Want "MSDBR/MSDB NF -QNaN/-0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r B910.10 +*Want "MSDBR/MSDB NF -QNaN/-0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B920.10 +*Want "MSDBR/MSDB NF -QNaN/-0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r B930.10 +*Want "MSDBR/MSDB NF -QNaN/-0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r B940.10 +*Want "MSDBR/MSDB NF -QNaN/-0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B950.10 +*Want "MSDBR/MSDB NF -QNaN/-0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r B960.10 +*Want "MSDBR/MSDB NF -QNaN/-0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r B970.10 +*Want "MSDBR/MSDB NF -QNaN/-0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r B980.10 +*Want "MSDBR/MSDB NF -QNaN/+0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r B990.10 +*Want "MSDBR/MSDB NF -QNaN/+0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B9A0.10 +*Want "MSDBR/MSDB NF -QNaN/+0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r B9B0.10 +*Want "MSDBR/MSDB NF -QNaN/+0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r B9C0.10 +*Want "MSDBR/MSDB NF -QNaN/+0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r B9D0.10 +*Want "MSDBR/MSDB NF -QNaN/+0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r B9E0.10 +*Want "MSDBR/MSDB NF -QNaN/+0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r B9F0.10 +*Want "MSDBR/MSDB NF -QNaN/+0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BA00.10 +*Want "MSDBR/MSDB NF -QNaN/+2.0/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r BA10.10 +*Want "MSDBR/MSDB NF -QNaN/+2.0/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r BA20.10 +*Want "MSDBR/MSDB NF -QNaN/+2.0/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r BA30.10 +*Want "MSDBR/MSDB NF -QNaN/+2.0/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r BA40.10 +*Want "MSDBR/MSDB NF -QNaN/+2.0/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r BA50.10 +*Want "MSDBR/MSDB NF -QNaN/+2.0/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r BA60.10 +*Want "MSDBR/MSDB NF -QNaN/+2.0/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r BA70.10 +*Want "MSDBR/MSDB NF -QNaN/+2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BA80.10 +*Want "MSDBR/MSDB NF -QNaN/+inf/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r BA90.10 +*Want "MSDBR/MSDB NF -QNaN/+inf/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r BAA0.10 +*Want "MSDBR/MSDB NF -QNaN/+inf/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r BAB0.10 +*Want "MSDBR/MSDB NF -QNaN/+inf/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r BAC0.10 +*Want "MSDBR/MSDB NF -QNaN/+inf/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r BAD0.10 +*Want "MSDBR/MSDB NF -QNaN/+inf/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r BAE0.10 +*Want "MSDBR/MSDB NF -QNaN/+inf/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r BAF0.10 +*Want "MSDBR/MSDB NF -QNaN/+inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BB00.10 +*Want "MSDBR/MSDB NF -QNaN/-QNaN/-inf FPCR" 00000000 F8000000 00000000 F8000000 +r BB10.10 +*Want "MSDBR/MSDB NF -QNaN/-QNaN/-2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r BB20.10 +*Want "MSDBR/MSDB NF -QNaN/-QNaN/-0 FPCR" 00000000 F8000000 00000000 F8000000 +r BB30.10 +*Want "MSDBR/MSDB NF -QNaN/-QNaN/+0 FPCR" 00000000 F8000000 00000000 F8000000 +r BB40.10 +*Want "MSDBR/MSDB NF -QNaN/-QNaN/+2.0 FPCR" 00000000 F8000000 00000000 F8000000 +r BB50.10 +*Want "MSDBR/MSDB NF -QNaN/-QNaN/+inf FPCR" 00000000 F8000000 00000000 F8000000 +r BB60.10 +*Want "MSDBR/MSDB NF -QNaN/-QNaN/-QNaN FPCR" 00000000 F8000000 00000000 F8000000 +r BB70.10 +*Want "MSDBR/MSDB NF -QNaN/-QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BB80.10 +*Want "MSDBR/MSDB NF -QNaN/+SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r BB90.10 +*Want "MSDBR/MSDB NF -QNaN/+SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BBA0.10 +*Want "MSDBR/MSDB NF -QNaN/+SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r BBB0.10 +*Want "MSDBR/MSDB NF -QNaN/+SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r BBC0.10 +*Want "MSDBR/MSDB NF -QNaN/+SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BBD0.10 +*Want "MSDBR/MSDB NF -QNaN/+SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r BBE0.10 +*Want "MSDBR/MSDB NF -QNaN/+SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BBF0.10 +*Want "MSDBR/MSDB NF -QNaN/+SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BC00.10 +*Want "MSDBR/MSDB NF +SNaN/-inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r BC10.10 +*Want "MSDBR/MSDB NF +SNaN/-inf/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BC20.10 +*Want "MSDBR/MSDB NF +SNaN/-inf/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r BC30.10 +*Want "MSDBR/MSDB NF +SNaN/-inf/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r BC40.10 +*Want "MSDBR/MSDB NF +SNaN/-inf/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BC50.10 +*Want "MSDBR/MSDB NF +SNaN/-inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r BC60.10 +*Want "MSDBR/MSDB NF +SNaN/-inf/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BC70.10 +*Want "MSDBR/MSDB NF +SNaN/-inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BC80.10 +*Want "MSDBR/MSDB NF +SNaN/-2.0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r BC90.10 +*Want "MSDBR/MSDB NF +SNaN/-2.0/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BCA0.10 +*Want "MSDBR/MSDB NF +SNaN/-2.0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r BCB0.10 +*Want "MSDBR/MSDB NF +SNaN/-2.0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r BCC0.10 +*Want "MSDBR/MSDB NF +SNaN/-2.0/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BCD0.10 +*Want "MSDBR/MSDB NF +SNaN/-2.0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r BCE0.10 +*Want "MSDBR/MSDB NF +SNaN/-2.0/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BCF0.10 +*Want "MSDBR/MSDB NF +SNaN/-2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BD00.10 +*Want "MSDBR/MSDB NF +SNaN/-0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r BD10.10 +*Want "MSDBR/MSDB NF +SNaN/-0/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BD20.10 +*Want "MSDBR/MSDB NF +SNaN/-0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r BD30.10 +*Want "MSDBR/MSDB NF +SNaN/-0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r BD40.10 +*Want "MSDBR/MSDB NF +SNaN/-0/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BD50.10 +*Want "MSDBR/MSDB NF +SNaN/-0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r BD60.10 +*Want "MSDBR/MSDB NF +SNaN/-0/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BD70.10 +*Want "MSDBR/MSDB NF +SNaN/-0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BD80.10 +*Want "MSDBR/MSDB NF +SNaN/+0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r BD90.10 +*Want "MSDBR/MSDB NF +SNaN/+0/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BDA0.10 +*Want "MSDBR/MSDB NF +SNaN/+0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r BDB0.10 +*Want "MSDBR/MSDB NF +SNaN/+0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r BDC0.10 +*Want "MSDBR/MSDB NF +SNaN/+0/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BDD0.10 +*Want "MSDBR/MSDB NF +SNaN/+0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r BDE0.10 +*Want "MSDBR/MSDB NF +SNaN/+0/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BDF0.10 +*Want "MSDBR/MSDB NF +SNaN/+0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BE00.10 +*Want "MSDBR/MSDB NF +SNaN/+2.0/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r BE10.10 +*Want "MSDBR/MSDB NF +SNaN/+2.0/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BE20.10 +*Want "MSDBR/MSDB NF +SNaN/+2.0/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r BE30.10 +*Want "MSDBR/MSDB NF +SNaN/+2.0/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r BE40.10 +*Want "MSDBR/MSDB NF +SNaN/+2.0/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BE50.10 +*Want "MSDBR/MSDB NF +SNaN/+2.0/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r BE60.10 +*Want "MSDBR/MSDB NF +SNaN/+2.0/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BE70.10 +*Want "MSDBR/MSDB NF +SNaN/+2.0/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BE80.10 +*Want "MSDBR/MSDB NF +SNaN/+inf/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r BE90.10 +*Want "MSDBR/MSDB NF +SNaN/+inf/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BEA0.10 +*Want "MSDBR/MSDB NF +SNaN/+inf/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r BEB0.10 +*Want "MSDBR/MSDB NF +SNaN/+inf/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r BEC0.10 +*Want "MSDBR/MSDB NF +SNaN/+inf/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BED0.10 +*Want "MSDBR/MSDB NF +SNaN/+inf/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r BEE0.10 +*Want "MSDBR/MSDB NF +SNaN/+inf/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BEF0.10 +*Want "MSDBR/MSDB NF +SNaN/+inf/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BF00.10 +*Want "MSDBR/MSDB NF +SNaN/-QNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r BF10.10 +*Want "MSDBR/MSDB NF +SNaN/-QNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BF20.10 +*Want "MSDBR/MSDB NF +SNaN/-QNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r BF30.10 +*Want "MSDBR/MSDB NF +SNaN/-QNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r BF40.10 +*Want "MSDBR/MSDB NF +SNaN/-QNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BF50.10 +*Want "MSDBR/MSDB NF +SNaN/-QNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r BF60.10 +*Want "MSDBR/MSDB NF +SNaN/-QNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BF70.10 +*Want "MSDBR/MSDB NF +SNaN/-QNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BF80.10 +*Want "MSDBR/MSDB NF +SNaN/+SNaN/-inf FPCR" 00800000 F8008000 00800000 F8008000 +r BF90.10 +*Want "MSDBR/MSDB NF +SNaN/+SNaN/-2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BFA0.10 +*Want "MSDBR/MSDB NF +SNaN/+SNaN/-0 FPCR" 00800000 F8008000 00800000 F8008000 +r BFB0.10 +*Want "MSDBR/MSDB NF +SNaN/+SNaN/+0 FPCR" 00800000 F8008000 00800000 F8008000 +r BFC0.10 +*Want "MSDBR/MSDB NF +SNaN/+SNaN/+2.0 FPCR" 00800000 F8008000 00800000 F8008000 +r BFD0.10 +*Want "MSDBR/MSDB NF +SNaN/+SNaN/+inf FPCR" 00800000 F8008000 00800000 F8008000 +r BFE0.10 +*Want "MSDBR/MSDB NF +SNaN/+SNaN/-QNaN FPCR" 00800000 F8008000 00800000 F8008000 +r BFF0.10 +*Want "MSDBR/MSDB NF +SNaN/+SNaN/+SNaN FPCR" 00800000 F8008000 00800000 F8008000 + + +# Long BFP Multiply And Subtract finite results +*Compare +r C000.10 +*Want "MSDBR F Ovfl 1" FFF00000 00000000 DFEFFFFF FFFFFFFE +r C010.10 +*Want "MSDB F Ovfl 1" FFF00000 00000000 DFEFFFFF FFFFFFFE +r C020.10 +*Want "MSDBR F Ovfl 2" FFF00000 00000000 9FFFFFFF FFFFFFFF +r C030.10 +*Want "MSDB F Ovfl 2" FFF00000 00000000 9FFFFFFF FFFFFFFF +r C040.10 +*Want "MSDBR F Ufl 1" 80080000 00000001 E0000000 00000002 +r C050.10 +*Want "MSDB F Ufl 1" 80080000 00000001 E0000000 00000002 +r C060.10 +*Want "MSDBR F Ufl 2" 0007FFFF FFFFFFFE 5FFFFFFF FFFFFFFA +r C070.10 +*Want "MSDB F Ufl 2" 0007FFFF FFFFFFFE 5FFFFFFF FFFFFFFA +r C080.10 +*Want "MSDBR F Nmin" 0017FFFF FFFFFFFE 0017FFFF FFFFFFFE +r C090.10 +*Want "MSDB F Nmin" 0017FFFF FFFFFFFE 0017FFFF FFFFFFFE +r C0A0.10 +*Want "MSDBR F Incr" 3FF90000 0000000D 3FF90000 0000000D +r C0B0.10 +*Want "MSDB F Incr" 3FF90000 0000000D 3FF90000 0000000D +r C0C0.10 +*Want "MSDBR F Trun" 3FF90000 00000007 3FF90000 00000007 +r C0D0.10 +*Want "MSDB F Trun" 3FF90000 00000007 3FF90000 00000007 + +# Long BFP Multiply And Subtract finite results - FPCR contents +*Compare +r C200.10 +*Want "MSDBR/MSDB F Ovfl 1 FPCR" 00280000 F8002800 00280000 F8002800 +r C210.10 +*Want "MSDBR/MSDB F Ovfl 2 FPCR" 00280000 F8002000 00280000 F8002000 +r C220.10 +*Want "MSDBR/MSDB F Ufl 1 FPCR" 00180000 F8001C00 00180000 F8001C00 +r C230.10 +*Want "MSDBR/MSDB F Ufl 2 FPCR" 00180000 F8001000 00180000 F8001000 +r C240.10 +*Want "MSDBR/MSDB F Nmin FPCR" 00000000 F8000000 00000000 F8000000 +r C250.10 +*Want "MSDBR/MSDB F Incr FPCR" 00080000 F8000C00 00080000 F8000C00 +r C260.10 +*Want "MSDBR/MSDB F Trun FPCR" 00080000 F8000800 00080000 F8000800 + +# Long BFP Multiply And Subtract rounding mode results +*Compare +r C500.10 +*Want "MSDBR/MSDB RM +NZ RNTE" 3FF90000 00000007 3FF90000 00000007 +r C510.10 +*Want "MSDBR/MSDB RM +NZ RZ" 3FF90000 00000007 3FF90000 00000007 +r C520.10 +*Want "MSDBR/MSDB RM +NZ RP" 3FF90000 00000008 3FF90000 00000008 +r C530.10 +*Want "MSDBR/MSDB RM +NZ RM" 3FF90000 00000007 3FF90000 00000007 +r C540.10 +*Want "MSDBR/MSDB RM +NZ RFS" 3FF90000 00000007 3FF90000 00000007 +r C550.10 +*Want "MSDBR/MSDB RM -NZ RNTE" BFF90000 00000007 BFF90000 00000007 +r C560.10 +*Want "MSDBR/MSDB RM -NZ RZ" BFF90000 00000007 BFF90000 00000007 +r C570.10 +*Want "MSDBR/MSDB RM -NZ RP" BFF90000 00000007 BFF90000 00000007 +r C580.10 +*Want "MSDBR/MSDB RM -NZ RM" BFF90000 00000008 BFF90000 00000008 +r C590.10 +*Want "MSDBR/MSDB RM -NZ RFS" BFF90000 00000007 BFF90000 00000007 +r C5A0.10 +*Want "MSDBR/MSDB RM +NA RNTE" 3FF90000 0000000D 3FF90000 0000000D +r C5B0.10 +*Want "MSDBR/MSDB RM +NA RZ" 3FF90000 0000000C 3FF90000 0000000C +r C5C0.10 +*Want "MSDBR/MSDB RM +NA RP" 3FF90000 0000000D 3FF90000 0000000D +r C5D0.10 +*Want "MSDBR/MSDB RM +NA RM" 3FF90000 0000000C 3FF90000 0000000C +r C5E0.10 +*Want "MSDBR/MSDB RM +NA RFS" 3FF90000 0000000D 3FF90000 0000000D +r C5F0.10 +*Want "MSDBR/MSDB RM -NA RNTE" BFF90000 0000000D BFF90000 0000000D +r C600.10 +*Want "MSDBR/MSDB RM -NA RZ" BFF90000 0000000C BFF90000 0000000C +r C610.10 +*Want "MSDBR/MSDB RM -NA RP" BFF90000 0000000C BFF90000 0000000C +r C620.10 +*Want "MSDBR/MSDB RM -NA RM" BFF90000 0000000D BFF90000 0000000D +r C630.10 +*Want "MSDBR/MSDB RM -NA RFS" BFF90000 0000000D BFF90000 0000000D +r C640.10 +*Want "MSDBR/MSDB RM +TZ RNTE" 3FF90000 00000008 3FF90000 00000008 +r C650.10 +*Want "MSDBR/MSDB RM +TZ RZ" 3FF90000 00000008 3FF90000 00000008 +r C660.10 +*Want "MSDBR/MSDB RM +TZ RP" 3FF90000 00000009 3FF90000 00000009 +r C670.10 +*Want "MSDBR/MSDB RM +TZ RM" 3FF90000 00000008 3FF90000 00000008 +r C680.10 +*Want "MSDBR/MSDB RM +TZ RFS" 3FF90000 00000009 3FF90000 00000009 +r C690.10 +*Want "MSDBR/MSDB RM -TZ RNTE" BFF90000 00000008 BFF90000 00000008 +r C6A0.10 +*Want "MSDBR/MSDB RM -TZ RZ" BFF90000 00000008 BFF90000 00000008 +r C6B0.10 +*Want "MSDBR/MSDB RM -TZ RP" BFF90000 00000008 BFF90000 00000008 +r C6C0.10 +*Want "MSDBR/MSDB RM -TZ RM" BFF90000 00000009 BFF90000 00000009 +r C6D0.10 +*Want "MSDBR/MSDB RM -TZ RFS" BFF90000 00000009 BFF90000 00000009 +r C6E0.10 +*Want "MSDBR/MSDB RM +TA RNTE" 3FF90000 0000001A 3FF90000 0000001A +r C6F0.10 +*Want "MSDBR/MSDB RM +TA RZ" 3FF90000 00000019 3FF90000 00000019 +r C700.10 +*Want "MSDBR/MSDB RM +TA RP" 3FF90000 0000001A 3FF90000 0000001A +r C710.10 +*Want "MSDBR/MSDB RM +TA RM" 3FF90000 00000019 3FF90000 00000019 +r C720.10 +*Want "MSDBR/MSDB RM +TA RFS" 3FF90000 00000019 3FF90000 00000019 +r C730.10 +*Want "MSDBR/MSDB RM -TA RNTE" BFF90000 0000001A BFF90000 0000001A +r C740.10 +*Want "MSDBR/MSDB RM -TA RZ" BFF90000 00000019 BFF90000 00000019 +r C750.10 +*Want "MSDBR/MSDB RM -TA RP" BFF90000 00000019 BFF90000 00000019 +r C760.10 +*Want "MSDBR/MSDB RM -TA RM" BFF90000 0000001A BFF90000 0000001A +r C770.10 +*Want "MSDBR/MSDB RM -TA RFS" BFF90000 00000019 BFF90000 00000019 + + +# Long BFP Multiply And Subtract rounding mode results - FPCR contents +*Compare +r CA00.10 +*Want "MSDBR/MSDB RM +NZ RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r CA10.10 +*Want "MSDBR/MSDB RM +NZ RP, RM FPCR" 00080002 00080002 00080003 00080003 +r CA20.10 +*Want "MSDBR/MSDB RM +NZ RFS FPCR" 00080007 00080007 00000000 00000000 +r CA30.10 +*Want "MSDBR/MSDB RM -NZ RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r CA40.10 +*Want "MSDBR/MSDB RM -NZ RP, RM FPCR" 00080002 00080002 00080003 00080003 +r CA50.10 +*Want "MSDBR/MSDB RM -NZ RFS FPCR" 00080007 00080007 00000000 00000000 +r CA60.10 +*Want "MSDBR/MSDB RM +NA RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r CA70.10 +*Want "MSDBR/MSDB RM +NA RP, RM FPCR" 00080002 00080002 00080003 00080003 +r CA80.10 +*Want "MSDBR/MSDB RM +NA RFS FPCR" 00080007 00080007 00000000 00000000 +r CA90.10 +*Want "MSDBR/MSDB RM -NA RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r CAA0.10 +*Want "MSDBR/MSDB RM -NA RP, RM FPCR" 00080002 00080002 00080003 00080003 +r CAB0.10 +*Want "MSDBR/MSDB RM -NA RFS FPCR" 00080007 00080007 00000000 00000000 +r CAC0.10 +*Want "MSDBR/MSDB RM +TZ RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r CAD0.10 +*Want "MSDBR/MSDB RM +TZ RP, RM FPCR" 00080002 00080002 00080003 00080003 +r CAE0.10 +*Want "MSDBR/MSDB RM +TZ RFS FPCR" 00080007 00080007 00000000 00000000 +r CAF0.10 +*Want "MSDBR/MSDB RM -TZ RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r CB00.10 +*Want "MSDBR/MSDB RM -TZ RP, RM FPCR" 00080002 00080002 00080003 00080003 +r CB10.10 +*Want "MSDBR/MSDB RM -TZ RFS FPCR" 00080007 00080007 00000000 00000000 +r CB20.10 +*Want "MSDBR/MSDB RM +TA RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r CB30.10 +*Want "MSDBR/MSDB RM +TA RP, RM FPCR" 00080002 00080002 00080003 00080003 +r CB40.10 +*Want "MSDBR/MSDB RM +TA RFS FPCR" 00080007 00080007 00000000 00000000 +r CB50.10 +*Want "MSDBR/MSDB RM -TA RNTE, RZ FPCR" 00080000 00080000 00080001 00080001 +r CB60.10 +*Want "MSDBR/MSDB RM -TA RP, RM FPCR" 00080002 00080002 00080003 00080003 +r CB70.10 +*Want "MSDBR/MSDB RM -TA RFS FPCR" 00080007 00080007 00000000 00000000 + + +r 1000.2000 + +r 6000.4000 + + +*Done + diff --git a/tests/bfp-023-threads.asm b/tests/bfp-023-threads.asm new file mode 100644 index 000000000..01abd414c --- /dev/null +++ b/tests/bfp-023-threads.asm @@ -0,0 +1,721 @@ + TITLE 'bfp-023-threads.asm: Test IEEE/Softfloat 3a Thread Safety' +*********************************************************************** +* +*Testcase ieee.c/Softfloat 3a thread safety. +* This test case dispatches floating point work on four CPUs. Any +* variation from expected results, as detected by each CPU, shows a +* lack of thread safety. +* +* Each CPU is given a single floating point operation to be performed +* in a loop. Each CPU has a different operation to perform, with a +* different expected result and IEEE flag set from Softfloat. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +* bfp-023-threads.asm +* +* This assembly-language source file is part of the +* Hercules Decimal Floating Point Validation Package +* by Stephen R. Orso +* +* Copyright 2016 by Stephen R Orso. All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* +* 3. The name of the author may not be used to endorse or promote +* products derived from this software without specific prior written +* permission. +* +* DISCLAMER: THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* HOLDER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*********************************************************************** + SPACE 2 +*********************************************************************** +* +*Function/Operation +* - Test Case Processing +* 1) The first CPU is started by the runtest restart command. The +* first CPU: +* a) starts the second CPU using SIGP. +* b) repeats the assigned floating point operation, looking for +* evidence of pre-emptive multitasking and incorrect results. +* c) At the end of a set number of calculations, the other three +* processors are stopped via SIGP. +* d) A hardwait PSW is loaded +* 2) The second CPU is started by the SIGP restart from the first +* CPU. The second CPU: +* a) starts the third CPU using SIGP. +* b) repeats the assigned floating point operation, looking for +* evidence of pre-emptive multitasking and incorrect results. +* c) The floating point operation is repeated until the CPU is +* stopped by the first CPU. +* 3) The third CPU is started by the second, and starts the fourth. +* Otherwise, it operates in the same way that CPU two does. +* 4) The fourth CPU is started by the second. It does not start +* another CPU. Otherwise, it operates in the same way that CPUs +* two and three do. +* +*Entry Points +* - All entries are via the PSW stored in the restart PSW field +* - CPUnBEG, where n is replaced by 0, 1, 2, or 3. Each is the start +* of the CPU-specific code for that CPU. +* +*Input +* - Floating point operands and expected results are compiled into +* the program. +* +*Output +* - All outputs are stored starting at real memory location X'2000' +* - Count of trials performed by each CPU. +* - Count of thread pre-emptions (switches) detected by each CPU. +* Note that not all pre-emptions are detected. +* - Count of trials that returned incorrect results by CPU. +* - Count of trials that returned incorrect FPCR contents by CPU. +* - For each CPU, the last incorrect result and the last incorrect +* FPCR contents. Note that the incorrect result and the incorrect +* FPCR contents may be from different trials. +* +*External Dependencies +* - This program is intended to be run on Hercules as part of the +* 'runtest' facility. +* +*Exit +* Normal- via LPSWE of a disabled wait PSW, address zero +* Abnormal- via LPSWE of a disabled wait PSW, address X'DEAD' +* +*Attributes +* - None +* +*Notes +* - Prefixing is used by this program. +* +* +*********************************************************************** + SPACE 2 + MACRO + PADCSECT &ENDLABL +.* +.* Macro to pad the CSECT to include result data areas if this test +.* program is not being assembled using asma. asma generates a core +.* image that is loaded by the loadcore command, and because the +.* core image is a binary stored in Github, it makes sense to make +.* this small effort to keep the core image small. +.* + AIF (D'&ENDLABL).GOODPAD + MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + MNOTE *,'No CSECT padding performed' + MEXIT +.* +.GOODPAD ANOP Label valid. See if we're on asma + AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + ORG &ENDLABL-1 Not ASMA. Pad CSECT + MEXIT +.* +.NOPAD ANOP + MNOTE *,'asma detected; no CSECT padding performed' + MEND +* +* Note: for compatibility with the z/CMS test rig, do not change +* or use R11, R14, or R15. Everything else is fair game. +* Although this program's use of four processors likely precludes +* its validation in z/CMS. +* +BFPTHRED START 0 +STRTLABL EQU * +R0 EQU 0 Work register for cc extraction +R1 EQU 1 +R2 EQU 2 Holds count of test input values +R3 EQU 3 Points to next test input value(s) +R4 EQU 4 Rounding tests inner loop control +R5 EQU 5 Rounding tests outer loop control +R6 EQU 6 Rounding tests top of inner loop +R7 EQU 7 Pointer to next result value(s) +R8 EQU 8 Pointer to next FPCR result +R9 EQU 9 Rounding tests top of outer loop +R10 EQU 10 Pointer to test address list +R11 EQU 11 **Reserved for z/CMS test rig +R12 EQU 12 Holds number of test cases in set +R13 EQU 13 Mainline return address +R14 EQU 14 **Return address for z/CMS test rig +R15 EQU 15 **Base register on z/CMS or Hyperion +* +* Floating Point Register equates to keep the cross reference clean +* +FPR0 EQU 0 +FPR1 EQU 1 +FPR2 EQU 2 +FPR3 EQU 3 +FPR4 EQU 4 +FPR5 EQU 5 +FPR6 EQU 6 +FPR7 EQU 7 +FPR8 EQU 8 +FPR9 EQU 9 +FPR10 EQU 10 +FPR11 EQU 11 +FPR12 EQU 12 +FPR13 EQU 13 +FPR14 EQU 14 +FPR15 EQU 15 +* +CPU1PRE EQU X'10000' CPU 1 prefix area at 64K +CPU2PRE EQU CPU1PRE+X'2000' CPU 2 prefix area at 64K + 8K +CPU3PRE EQU CPU2PRE+X'2000' CPU 2 prefix area at 64K + 2 * 8K +* + USING *,R15 +* +* Above works on real iron (R15=0 after sysclear) +* and in z/CMS (R15 points to start of load module) +* + SPACE 2 +*********************************************************************** +* +* Low core definitions, Restart PSW, and Program Check Routine. +* +*********************************************************************** + SPACE 2 + ORG STRTLABL+X'8E' Program check interrution code +PCINTCD DS H +* +PCOLDPSW EQU STRTLABL+X'150' z/Arch Program check old PSW +* + ORG STRTLABL+X'1A0' z/Arch Restart PSW +RESTRPSW DC X'0000000180000000',AD(CPU0BEG) 64-bit addr, 4k page +RPSWADR EQU RESTRPSW-STRTLABL+8 Displacement of restart psw address +* + ORG STRTLABL+X'1D0' z/Arch Program check new PSW + DC X'0000000180000000',AD(PROGCHK) +* +******** Following ORG overlays the PC new PSW with a hard wait. +* +** ORG STRTLABL+X'1D0' z/Arch Program check new PSW +** DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end +* +* Program check routine. If Data Exception, continue execution at +* the instruction following the program check. Otherwise, hard wait. +* No need to collect data. All interesting DXC stuff is captured +* in the FPCR. +* + ORG STRTLABL+X'200' +PROGCHK DS 0H Program check occured... + CLI PCINTCD+1,X'07' Data Exception? + JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) + LPSWE PCOLDPSW ..yes, resume program execution +PCNOTDTA DS 0H + LTR R14,R14 Return address provided? + BNZR R14 Yes, return to z/CMS test rig. + LPSWE HARDWAIT Not data exception, enter disabled wait +* + EJECT +*********************************************************************** +* +* Data areas global to all four processors and areas that are per-cpu. +* +* Per-CPU variables are prefixed with 'CPUn' where n is replaced with +* the CPU number, starting with zero. +* +*********************************************************************** + SPACE 2 +* +SIGPREST EQU 6 SIGP order for CPU Restart +SIGPSTOP EQU 5 SIGP order for CPU Stop +SIGPPREF EQU 13 SIGP order for Set Prefix +* + DS 0D Ensure correct alignment for psw +WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end +* +CPU0CR0 DS F CR0, used to turn on AFP +CPU1CR0 DS F CR0, used to turn on AFP +CPU2CR0 DS F CR0, used to turn on AFP +CPU3CR0 DS F CR0, used to turn on AFP +* +CPU0ADR DS H CPU addr returned from STAP, used by SIGP +CPU1ADR DS H CPU addr returned from STAP, used by SIGP +CPU2ADR DS H CPU addr returned from STAP, used by SIGP +CPU3ADR DS H CPU addr returned from STAP, used by SIGP + EJECT +*********************************************************************** +* +* CPU 0 program. Set prefixes, start all processors, enable Additional +* Floating Point Registers, repetitively perform a floating point +* operation, then stop all three other processors and load a hard wait +* PSW. +* +*********************************************************************** + SPACE 2 +CPU0BEG DS 0H Start of processing for CPU zero + STAP CPU0ADR Store CPU address of this processor + LH R1,CPU0ADR Get CPU address + LA R1,1(,R1) Update to next CPU address + STH R1,CPU1ADR Store next CPU address + LA R1,1(,R1) Update to next CPU address + STH R1,CPU2ADR Store next CPU address + LA R1,1(,R1) Update to next CPU address + STH R1,CPU3ADR Store next CPU address +* +* Set up prefixing for each of the three additional CPUs that will +* perform floating point operations. Copy the first 8K to appropriate +* locations for each of the CPUs, modify the restart PSW, and issue +* SIGP Set Prefix for each of them. +* +* Because the entirety of this program fits in less than 8K, prefixing +* is not difficult. +* +* Set Prefix and start CPU 1 + LH R2,CPU1ADR Get next CPU addresss + LG R1,=AD(CPU1PRE) Get address of CPU1 Prefix area + XR R0,R0 Set address of real low core + MVPG R1,R0 Make a copy of low core + SIGP R1,R2,SIGPPREF Set prefix area for CPU 1 + MVC RPSWADR(8,R1),=AD(CPU1BEG) Update restart PSW in prefix + XR R1,R1 Zero SIGP parameter register + SIGP R0,R2,SIGPREST Start next CPU using a Restart command +* +* Set Prefix and start CPU 2 + LH R2,CPU2ADR Get next CPU addresss + LG R1,=AD(CPU2PRE) Get address of CPU1 Prefix area + XR R0,R0 Set address of real low core + MVPG R1,R0 Make a copy of low core + SIGP R1,R2,SIGPPREF Set prefix area for CPU 2 + MVC RPSWADR(8,R1),=AD(CPU2BEG) Update restart PSW in prefix + XR R1,R1 Zero SIGP parameter register + SIGP R0,R2,SIGPREST Start next CPU using a Restart command +* +* Set Prefix and start CPU 3 + LH R2,CPU3ADR Get next CPU addresss + LG R1,=AD(CPU3PRE) Get address of CPU1 Prefix area + XR R0,R0 Set address of real low core + MVPG R1,R0 Make a copy of low core + SIGP R1,R2,SIGPPREF Set prefix area for CPU 3 + MVC RPSWADR(8,R1),=AD(CPU3BEG) Update restart PSW in prefix + XR R1,R1 Zero SIGP parameter register + SIGP R0,R2,SIGPREST Start next CPU using a Restart command +* +* Other processors started. Now perform floating point operations. +* + STCTL R0,R0,CPU0CR0 Store CR0 to enable AFP + OI CPU0CR0+1,X'04' Turn on AFP bit + LCTL R0,R0,CPU0CR0 Reload updated CR0 +* +* Initialize counter for loop control +* + LARL R12,RESAREA Point to shared results area + USING RESAREA,R12 Make results addressable + L R2,=F'10000000' Run loop 10,000,000 times + XR R3,R3 Zero count of loop iterations + LR R4,R3 Zero count of detected pre-emptions + LR R5,R3 Zero count of result errors + LR R6,R3 Zero count of FPCR contents errors + BASR R13,0 Set top of loop +* +* Top of loop. Check for pre-emption, do floating point operation, +* increment count of trips through loop. +* + CLC LASTCPU,CPU0ADR Has another CPU been dispatched + BE CPU0CALC ..not that we can detect...do calc. + MVC LASTCPU,CPU0ADR Update last dispatched CPU + LA R4,1(,R4) Increment count of pre-emption detections + ST R4,CPU0PDET Store updated count +* +CPU0CALC DS 0H Perform floating point operation + LFPC CPU0FPCR Reset FPCR to non-trap, RNTE + LE FPR2,CPU0OP1 Load operand one + FIEBR FPR8,0,FPR2 Floating Point Integer + STE FPR8,CPU0ARES Store actual result + STFPC CPU0AFPC Store actual FPCR contents +* + CLC CPU0ARES,CPU0ER1 Did we get expected results? + BE CPU0CF1C ..Yes, go check FPCR contents + LA R5,1(,R5) Increment result error count + ST R5,CPU0RECT Store updated result error count + MVC CPU0XRES,CPU0ARES Save incorrect result +* +CPU0CF1C DS 0H + CLC CPU0AFPC,CPU0EF1 Did we get expected results? + BE CPU0OPNX ..Yes, do next operation + LA R6,1(,R6) Increment FPCR contents error count + ST R6,CPU0FECT Store updated FPCR contents error count + MVC CPU0XFPC,CPU0AFPC Save incorrect result +* +CPU0OPNX DS 0H Do second floating point operation + LFPC CPU0FPCR Reset FPCR to non-trap, RNTE + LE FPR2,CPU0OP2 Load operand one + FIEBR FPR8,0,FPR2 Floating Point Integer + STE FPR8,CPU0ARES Store actual result + STFPC CPU0AFPC Store actual FPCR contents +* + CLC CPU0ARES,CPU0ER2 Did we get expected results? + BE CPU0CF2C ..Yes, go check FPCR contents + LA R5,1(,R5) Increment result error count + ST R5,CPU0RECT Store updated result error count + MVC CPU0XRES,CPU0ARES Save incorrect result +* +CPU0CF2C DS 0H + CLC CPU0AFPC,CPU0EF2 Did we get expected results? + BE CPU0OPDN ..Yes, end of iteration + LA R6,1(,R6) Increment FPCR contents error count + ST R6,CPU0FECT Store updated FPCR contents error count + MVC CPU0XFPC,CPU0AFPC Save incorrect result +* +CPU0OPDN DS 0H FP op and result checks done + LA R3,1(,R3) Increment loop iteration count + ST R3,CPU0CTR Store updated loop iteration count + BCTR R2,R13 Perform next iteration +* +* Looping completed. Stop other processors and load hardwait PSW. +* + DROP R12 + XR R1,R1 Zero SIGP parameter register +* + LH R2,CPU1ADR Get next CPU addresss + SIGP R0,R2,SIGPSTOP Stop the CPU +* + LH R2,CPU2ADR Get next CPU addresss + SIGP R0,R2,SIGPSTOP Stop the CPU +* + LH R2,CPU3ADR Get next CPU addresss + SIGP R0,R2,SIGPSTOP Stop the CPU +* + LTR R14,R14 Return address provided? + BNZR R14 ..Yes, return to z/CMS test rig. + LPSWE WAITPSW All done +* +* Load Floating Point Integer of 1.5, RNTE. Expect 2.0 and inexact +* +CPU0FPCR DC X'00000000' FPCR, no traps, RNTE +* +CPU0OP1 DC X'3FC00000' +1.5 +CPU0ER1 DC X'40000000' Expected result 2.0 +CPU0EF1 DC X'00080000' Expected FPCR contents flag inexact +* +CPU0OP2 DC X'3F800000' +1.0 +CPU0ER2 DC X'3F800000' Expected 1.0 +CPU0EF2 DC X'00000000' Expected FPCR flag-free, RNTE +* + EJECT +*********************************************************************** +* +* CPU 1 program. Start the next processor, enable Advanced Floating +* Point, and repetitively perform a floating point operation until +* this processor is stopped by CPU 0. +* +*********************************************************************** + SPACE 2 +CPU1BEG DS 0H Start of processing for CPU zero +* + STCTL R0,R0,CPU1CR0 Store CR0 to enable AFP + OI CPU1CR0+1,X'04' Turn on AFP bit + LCTL R0,R0,CPU1CR0 Reload updated CR0 +* +* Perform repetitive operation in a loop +* + LARL R12,RESAREA Point to shared results area + USING RESAREA,R12 Make results addressable + XR R3,R3 Zero count of loop iterations + LR R4,R3 Zero count of detected pre-emptions + LR R5,R3 Zero count of result errors + LR R6,R3 Zero count of FPCR contents errors + BASR R13,0 Set top of loop +* +* Top of loop. Check for pre-emption, do floating point operation, +* increment count of trips through loop. +* + CLC LASTCPU,CPU1ADR Has another CPU been dispatched + BE CPU1CALC ..not that we can detect...do calc. + MVC LASTCPU,CPU1ADR Update last dispatched CPU + LA R4,1(,R4) Increment count of pre-emption detections + ST R4,CPU1PDET Store updated count +* +CPU1CALC DS 0H Perform floating point operation + LFPC CPU1FPCR Reset FPCR to non-trap, RM + LE FPR2,CPU1OP1 Load operand one + FIEBR FPR8,0,FPR2 Convert to Floating Point integer + STE FPR8,CPU1ARES Store actual result + STFPC CPU1AFPC Store actual FPCR contents +* + CLC CPU1ARES,CPU1ER1 Did we get expected results? + BE CPU1CF1C ..Yes, go check FPCR contents + LA R5,1(,R5) Increment result error count + ST R5,CPU1RECT Store updated loop iteration count + MVC CPU1XRES,CPU1ARES Save incorrect result +* +CPU1CF1C DS 0H + CLC CPU1AFPC,CPU1EF1 Did we get expected results? + BE CPU1OPNX ..Yes, end of iteration + LA R6,1(,R6) Increment FPCR contents error count + ST R6,CPU1FECT Store updated loop iteration count + MVC CPU1XFPC,CPU1AFPC Save incorrect result +* +CPU1OPNX DS 0H FP op and result checks done + LFPC CPU1FPCR Reset FPCR to non-trap, RM + LE FPR2,CPU1OP2 Load operand one + FIEBR FPR8,0,FPR2 Convert to Floating Point integer + STE FPR8,CPU1ARES Store actual result + STFPC CPU1AFPC Store actual FPCR contents +* + CLC CPU1ARES,CPU1ER2 Did we get expected results? + BE CPU1CF2C ..Yes, go check FPCR contents + LA R5,1(,R5) Increment result error count + ST R5,CPU1RECT Store updated loop iteration count + MVC CPU1XRES,CPU1ARES Save incorrect result +* +CPU1CF2C DS 0H + CLC CPU1AFPC,CPU1EF2 Did we get expected results? + BE CPU1OPDN ..Yes, end of iteration + LA R6,1(,R6) Increment FPCR contents error count + ST R6,CPU1FECT Store updated loop iteration count + MVC CPU1XFPC,CPU1AFPC Save incorrect result +* +CPU1OPDN DS 0H FP op and result checks done + LA R3,1(,R3) Increment count of loop iterations + ST R3,CPU1CTR Store updated loop iteration count + BR R13 Perform next iteration until CPU stopped +* + DROP R12 +* +* Load Floating Point Integer of 1.5, RZ. Expect 1.0 and inexact +* +CPU1FPCR DC X'00000001' FPCR, no traps, RZ +* +CPU1OP1 DC X'3FC00000' +1.5 +CPU1ER1 DC X'3F800000' Expected 1.0 +CPU1EF1 DC X'00080001' Expected FPCR flag inexact, RM +* +CPU1OP2 DC X'3F800000' +1.0 +CPU1ER2 DC X'3F800000' Expected 1.0 +CPU1EF2 DC X'00000001' Expected FPCR flag-free, RM +* + EJECT +*********************************************************************** +* +* CPU 2 program. Start the next processor, enable Advanced Floating +* Point, and repetitively perform a floating point operation until +* this processor is stopped by CPU 0. +* +*********************************************************************** + SPACE 2 +CPU2BEG DS 0H Start of processing for CPU zero +* + STCTL R0,R0,CPU2CR0 Store CR0 to enable AFP + OI CPU2CR0+1,X'04' Turn on AFP bit + LCTL R0,R0,CPU2CR0 Reload updated CR0 +* +* Perform repetitive operation in a loop +* + LARL R12,RESAREA Point to shared results area + USING RESAREA,R12 Make results addressable + XR R3,R3 Zero count of loop iterations + LR R4,R3 Zero count of detected pre-emptions + LR R5,R3 Zero count of result errors + LR R6,R3 Zero count of FPCR contents errors + BASR R13,0 Set top of loop +* +* Top of loop. Check for pre-emption, do floating point operation, +* increment count of trips through loop. +* + CLC LASTCPU,CPU2ADR Has another CPU been dispatched + BE CPU2CALC ..not that we can detect...do calc. + MVC LASTCPU,CPU2ADR Update last dispatched CPU + LA R4,1(,R4) Increment count of pre-emption detections + ST R4,CPU2PDET Store updated count +* +CPU2CALC DS 0H Perform floating point operation + LFPC CPU2FPCR Reset FPCR to non-trap, RM + LE FPR2,CPU2OP1 Load operand one + FIEBR FPR8,0,FPR2 Convert to Floating Point integer + STE FPR8,CPU2ARES Store actual result + STFPC CPU2AFPC Store actual FPCR contents +* + CLC CPU2ARES,CPU2ERES Did we get expected results? + BE CPU2CFPC ..Yes, go check FPCR contents + LA R5,1(,R5) Increment result error count + ST R5,CPU2RECT Store updated loop iteration count + MVC CPU2XRES,CPU2ARES Save incorrect result +* +CPU2CFPC DS 0H + CLC CPU2AFPC,CPU2EFPC Did we get expected results? + BE CPU2OPDN ..Yes, end of iteration + LA R6,1(,R6) Increment FPCR contents error count + ST R6,CPU2FECT Store updated loop iteration count + MVC CPU2XFPC,CPU2AFPC Save incorrect result +* +CPU2OPDN DS 0H FP op and result checks done + LA R3,1(,R3) Increment count of loop iterations + ST R3,CPU2CTR Store updated loop iteration count + BR R13 Perform next iteration until CPU stopped +* + DROP R12 +* +* Load Floating Point Integer of 1.5, RP. Expect 2.0 and inexact +* +CPU2FPCR DC X'00000002' FPCR, no traps, RP +* +CPU2OP1 DC X'3FC00000' +1.5 +* +CPU2ERES DC X'40000000' Expected 2.0 +CPU2EFPC DC X'00080002' Expected FPCR flag inexact, RM + EJECT +*********************************************************************** +* +* CPU 3 program. Start the next processor, enable Advanced Floating +* Point, and repetitively perform a floating point operation until +* this processor is stopped by CPU 0. +* +*********************************************************************** + SPACE 2 +CPU3BEG DS 0H Start of processing for CPU zero +* + STCTL R0,R0,CPU3CR0 Store CR0 to enable AFP + OI CPU3CR0+1,X'04' Turn on AFP bit + LCTL R0,R0,CPU3CR0 Reload updated CR0 +* +* Perform repetitive operation in a loop +* + LARL R12,RESAREA Point to shared results area + USING RESAREA,R12 Make results addressable + XR R3,R3 Zero count of loop iterations + LR R4,R3 Zero count of detected pre-emptions + LR R5,R3 Zero count of result errors + LR R6,R3 Zero count of FPCR contents errors + BASR R13,0 Set top of loop +* +* Top of loop. Check for pre-emption, do floating point operation, +* increment count of trips through loop. +* + CLC LASTCPU,CPU3ADR Has another CPU been dispatched + BE CPU3CALC ..not that we can detect...do calc. + MVC LASTCPU,CPU3ADR Update last dispatched CPU + LA R4,1(,R4) Increment count of pre-emption detections + ST R4,CPU3PDET Store updated count +* +CPU3CALC DS 0H Perform floating point operation + LFPC CPU3FPCR Reset FPCR to non-trap, RM + LE FPR2,CPU3OP1 Load operand one + FIEBR FPR8,0,FPR2 Convert to Floating Point integer + STE FPR8,CPU3ARES Store actual result + STFPC CPU3AFPC Store actual FPCR contents +* + CLC CPU3ARES,CPU3ERES Did we get expected results? + BE CPU3CFPC ..Yes, go check FPCR contents + LA R5,1(,R5) Increment result error count + ST R5,CPU3RECT Store updated loop iteration count + MVC CPU3XRES,CPU3ARES Save incorrect result +* +CPU3CFPC DS 0H + CLC CPU3AFPC,CPU3EFPC Did we get expected FPCR? + BE CPU3OPDN ..Yes, end of iteration + LA R6,1(,R6) Increment FPCR contents error count + ST R6,CPU3FECT Store updated loop iteration count + MVC CPU3XFPC,CPU3AFPC Save incorrect result +* +CPU3OPDN DS 0H FP op and result checks done + LA R3,1(,R3) Increment count of iterations + ST R3,CPU3CTR Store updated loop iteration count + BR R13 Perform next iteration until CPU stopped + DROP R12 +* +* Load Floating Point Integer of 1.0, RM. Expect 1.0 and no flags +* +CPU3FPCR DC X'00000003' FPCR, no traps, RP +* +CPU3OP1 DC X'3F800000' +1.0 +* +CPU3ERES DC X'3F800000' Expected 1.0 +CPU3EFPC DC X'00000003' Expected FPCR flag-free, RP + SPACE 3 + LTORG + EJECT +* +* Locations for results. Because all four threads use these +* values, they must not be in the area affected by prefixing. +* + ORG STRTLABL+X'2000' Shared tables. +RESAREA DS 0D Start of results area +* +* Loop iteration counter for each CPU +* +CPU0CTR DC F'0' +CPU1CTR DC F'0' +CPU2CTR DC F'0' +CPU3CTR DC F'0' +* +* Pre-emption detection counter for each CPU +* +CPU0PDET DC F'0' +CPU1PDET DC F'0' +CPU2PDET DC F'0' +CPU3PDET DC F'0' +* +* Result error detection counter for each CPU +* +CPU0RECT DC F'0' +CPU1RECT DC F'0' +CPU2RECT DC F'0' +CPU3RECT DC F'0' +* +* FPCR contents error detection counter for each CPU +* +CPU0FECT DC F'0' +CPU1FECT DC F'0' +CPU2FECT DC F'0' +CPU3FECT DC F'0' +* +* Actual Results +* +CPU0ARES DC X'00000000' Actual results +CPU0AFPC DC X'00000000' Actual FPCR contents +* +CPU1ARES DC X'00000000' Actual results +CPU1AFPC DC X'00000000' Actual FPCR contents +* +CPU2ARES DC X'00000000' Actual results +CPU2AFPC DC X'00000000' Actual FPCR contents +* +CPU3ARES DC X'00000000' Actual results +CPU3AFPC DC X'00000000' Actual FPCR contents +* +* Error Results +* +CPU0XRES DC X'00000000' Last error results +CPU0XFPC DC X'00000000' Last error FPCR contents +* +CPU1XRES DC X'00000000' Last error results +CPU1XFPC DC X'00000000' Last error FPCR contents +* +CPU2XRES DC X'00000000' Last error results +CPU2XFPC DC X'00000000' Last error FPCR contents +* +CPU3XRES DC X'00000000' Last error results +CPU3XFPC DC X'00000000' Last error FPCR contents +* +* Following shared variable used for preemption detection. Cannot be +* in the prefixed area, lest each CPU have its own copy. +* +LASTCPU DC H'0' Address of last detected dispatched CPU +* +ENDLABL EQU STRTLABL+X'2200' + PADCSECT ENDLABL + END diff --git a/tests/bfp-023-threads.core b/tests/bfp-023-threads.core new file mode 100644 index 000000000..3c26ba110 Binary files /dev/null and b/tests/bfp-023-threads.core differ diff --git a/tests/bfp-023-threads.list b/tests/bfp-023-threads.list new file mode 100644 index 000000000..5fe97fdb0 --- /dev/null +++ b/tests/bfp-023-threads.list @@ -0,0 +1,942 @@ +ASMA Ver. 0.2.0 bfp-023-threads.asm: Test IEEE/Softfloat 3a Thread Safety 27 Oct 2016 23:07:10 Page 1 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 2 *********************************************************************** + 3 * + 4 *Testcase ieee.c/Softfloat 3a thread safety. + 5 * This test case dispatches floating point work on four CPUs. Any + 6 * variation from expected results, as detected by each CPU, shows a + 7 * lack of thread safety. + 8 * + 9 * Each CPU is given a single floating point operation to be performed + 10 * in a loop. Each CPU has a different operation to perform, with a + 11 * different expected result and IEEE flag set from Softfloat. + 12 * + 13 *********************************************************************** + + + 15 *********************************************************************** + 16 * + 17 *Function/Operation + 18 * - Test Case Processing + 19 * 1) The first CPU is started by the runtest restart command. The + 20 * first CPU: + 21 * a) starts the second CPU using SIGP. + 22 * b) repeats the assigned floating point operation, looking for + 23 * evidence of pre-emptive multitasking and incorrect results. + 24 * c) At the end of a set number of calculations, the other three + 25 * processors are stopped via SIGP. + 26 * d) A hardwait PSW is loaded + 27 * 2) The second CPU is started by the SIGP restart from the first + 28 * CPU. The second CPU: + 29 * a) starts the third CPU using SIGP. + 30 * b) repeats the assigned floating point operation, looking for + 31 * evidence of pre-emptive multitasking and incorrect results. + 32 * c) The floating point operation is repeated until the CPU is + 33 * stopped by the first CPU. + 34 * 3) The third CPU is started by the second, and starts the fourth. + 35 * Otherwise, it operates in the same way that CPU two does. + 36 * 4) The fourth CPU is started by the second. It does not start + 37 * another CPU. Otherwise, it operates in the same way that CPUs + 38 * two and three do. + 39 * + 40 *Entry Points + 41 * - All entries are via the PSW stored in the restart PSW field + 42 * - CPUnBEG, where n is replaced by 0, 1, 2, or 3. Each is the start + 43 * of the CPU-specific code for that CPU. + 44 * + 45 *Input + 46 * - Floating point operands and expected results are compiled into + 47 * the program. + 48 * + 49 *Output + 50 * - All outputs are stored starting at real memory location X'2000' + 51 * - Count of trials performed by each CPU. + 52 * - Count of thread pre-emptions (switches) detected by each CPU. + ASMA Ver. 0.2.0 bfp-023-threads.asm: Test IEEE/Softfloat 3a Thread Safety 27 Oct 2016 23:07:10 Page 2 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 53 * Note that not all pre-emptions are detected. + 54 * - Count of trials that returned incorrect results by CPU. + 55 * - Count of trials that returned incorrect FPCR contents by CPU. + 56 * - For each CPU, the last incorrect result and the last incorrect + 57 * FPCR contents. Note that the incorrect result and the incorrect + 58 * FPCR contents may be from different trials. + 59 * + 60 *External Dependencies + 61 * - This program is intended to be run on Hercules as part of the + 62 * 'runtest' facility. + 63 * + 64 *Exit + 65 * Normal- via LPSWE of a disabled wait PSW, address zero + 66 * Abnormal- via LPSWE of a disabled wait PSW, address X'DEAD' + 67 * + 68 *Attributes + 69 * - None + 70 * + 71 *Notes + 72 * - Prefixing is used by this program. + 73 * + 74 * + 75 *********************************************************************** + + + 77 MACRO + 78 PADCSECT &ENDLABL + 79 .* + 80 .* Macro to pad the CSECT to include result data areas if this test + 81 .* program is not being assembled using asma. asma generates a core + 82 .* image that is loaded by the loadcore command, and because the + 83 .* core image is a binary stored in Github, it makes sense to make + 84 .* this small effort to keep the core image small. + 85 .* + 86 AIF (D'&ENDLABL).GOODPAD + 87 MNOTE 4,'Missing or invalid CSECT padding label ''&ENDLABL''' + 88 MNOTE *,'No CSECT padding performed' + 89 MEXIT + 90 .* + 91 .GOODPAD ANOP Label valid. See if we're on asma + 92 AIF ('&SYSASM' EQ 'A SMALL MAINFRAME ASSEMBLER').NOPAD + 93 ORG &ENDLABL-1 Not ASMA. Pad CSECT + 94 MEXIT + 95 .* + 96 .NOPAD ANOP + 97 MNOTE *,'asma detected; no CSECT padding performed' + 98 MEND + 99 * + 100 * Note: for compatibility with the z/CMS test rig, do not change + 101 * or use R11, R14, or R15. Everything else is fair game. + 102 * Although this program's use of four processors likely precludes + 103 * its validation in z/CMS. + ASMA Ver. 0.2.0 bfp-023-threads.asm: Test IEEE/Softfloat 3a Thread Safety 27 Oct 2016 23:07:10 Page 3 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 104 * + 0000000000000000 0000000000002081 105 BFPTHRED START 0 + 0000000000000000 0000000000000001 106 STRTLABL EQU * + 0000000000000000 0000000000000001 107 R0 EQU 0 Work register for cc extraction + 0000000000000001 0000000000000001 108 R1 EQU 1 + 0000000000000002 0000000000000001 109 R2 EQU 2 Holds count of test input values + 0000000000000003 0000000000000001 110 R3 EQU 3 Points to next test input value(s) + 0000000000000004 0000000000000001 111 R4 EQU 4 Rounding tests inner loop control + 0000000000000005 0000000000000001 112 R5 EQU 5 Rounding tests outer loop control + 0000000000000006 0000000000000001 113 R6 EQU 6 Rounding tests top of inner loop + 0000000000000007 0000000000000001 114 R7 EQU 7 Pointer to next result value(s) + 0000000000000008 0000000000000001 115 R8 EQU 8 Pointer to next FPCR result + 0000000000000009 0000000000000001 116 R9 EQU 9 Rounding tests top of outer loop + 000000000000000A 0000000000000001 117 R10 EQU 10 Pointer to test address list + 000000000000000B 0000000000000001 118 R11 EQU 11 **Reserved for z/CMS test rig + 000000000000000C 0000000000000001 119 R12 EQU 12 Holds number of test cases in set + 000000000000000D 0000000000000001 120 R13 EQU 13 Mainline return address + 000000000000000E 0000000000000001 121 R14 EQU 14 **Return address for z/CMS test rig + 000000000000000F 0000000000000001 122 R15 EQU 15 **Base register on z/CMS or Hyperion + 123 * + 124 * Floating Point Register equates to keep the cross reference clean + 125 * + 0000000000000000 0000000000000001 126 FPR0 EQU 0 + 0000000000000001 0000000000000001 127 FPR1 EQU 1 + 0000000000000002 0000000000000001 128 FPR2 EQU 2 + 0000000000000003 0000000000000001 129 FPR3 EQU 3 + 0000000000000004 0000000000000001 130 FPR4 EQU 4 + 0000000000000005 0000000000000001 131 FPR5 EQU 5 + 0000000000000006 0000000000000001 132 FPR6 EQU 6 + 0000000000000007 0000000000000001 133 FPR7 EQU 7 + 0000000000000008 0000000000000001 134 FPR8 EQU 8 + 0000000000000009 0000000000000001 135 FPR9 EQU 9 + 000000000000000A 0000000000000001 136 FPR10 EQU 10 + 000000000000000B 0000000000000001 137 FPR11 EQU 11 + 000000000000000C 0000000000000001 138 FPR12 EQU 12 + 000000000000000D 0000000000000001 139 FPR13 EQU 13 + 000000000000000E 0000000000000001 140 FPR14 EQU 14 + 000000000000000F 0000000000000001 141 FPR15 EQU 15 + 142 * + 0000000000010000 0000000000000001 143 CPU1PRE EQU X'10000' CPU 1 prefix area at 64K + 0000000000012000 0000000000000001 144 CPU2PRE EQU CPU1PRE+X'2000' CPU 2 prefix area at 64K + 8K + 0000000000014000 0000000000000001 145 CPU3PRE EQU CPU2PRE+X'2000' CPU 2 prefix area at 64K + 2 * 8K + 146 * +0000000000000000 0000000000000000 147 USING *,R15 + 148 * + 149 * Above works on real iron (R15=0 after sysclear) + 150 * and in z/CMS (R15 points to start of load module) + 151 * + + + 153 *********************************************************************** + 154 * + ASMA Ver. 0.2.0 bfp-023-threads.asm: Test IEEE/Softfloat 3a Thread Safety 27 Oct 2016 23:07:10 Page 4 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 155 * Low core definitions, Restart PSW, and Program Check Routine. + 156 * + 157 *********************************************************************** + + +0000000000000000 0000000000000000 000000000000008E 159 ORG STRTLABL+X'8E' Program check interrution code +000000000000008E 0000 160 PCINTCD DS H + 161 * + 0000000000000150 0000000000000001 162 PCOLDPSW EQU STRTLABL+X'150' z/Arch Program check old PSW + 163 * +0000000000000090 0000000000000090 00000000000001A0 164 ORG STRTLABL+X'1A0' z/Arch Restart PSW +00000000000001A0 00000001 80000000 165 RESTRPSW DC X'0000000180000000',AD(CPU0BEG) 64-bit addr, 4k page + 00000000000001A8 0000000000000001 166 RPSWADR EQU RESTRPSW-STRTLABL+8 Displacement of restart psw address + 167 * +00000000000001B0 00000000000001B0 00000000000001D0 168 ORG STRTLABL+X'1D0' z/Arch Program check new PSW +00000000000001D0 00000001 80000000 169 DC X'0000000180000000',AD(PROGCHK) + 170 * + 171 ******** Following ORG overlays the PC new PSW with a hard wait. + 172 * + 173 ** ORG STRTLABL+X'1D0' z/Arch Program check new PSW + 174 ** DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end + 175 * + 176 * Program check routine. If Data Exception, continue execution at + 177 * the instruction following the program check. Otherwise, hard wait. + 178 * No need to collect data. All interesting DXC stuff is captured + 179 * in the FPCR. + 180 * +00000000000001E0 00000000000001E0 0000000000000200 181 ORG STRTLABL+X'200' +0000000000000200 182 PROGCHK DS 0H Program check occured... +0000000000000200 9507 F08F 000000000000008F 183 CLI PCINTCD+1,X'07' Data Exception? +0000000000000204 A774 0004 000000000000020C 184 JNE PCNOTDTA ..no, hardwait (not sure if R15 is ok) +0000000000000208 B2B2 F150 0000000000000150 185 LPSWE PCOLDPSW ..yes, resume program execution +000000000000020C 186 PCNOTDTA DS 0H +000000000000020C 12EE 187 LTR R14,R14 Return address provided? +000000000000020E 077E 188 BNZR R14 Yes, return to z/CMS test rig. +0000000000000210 B2B2 F228 0000000000000228 189 LPSWE HARDWAIT Not data exception, enter disabled wait + 190 * + ASMA Ver. 0.2.0 bfp-023-threads.asm: Test IEEE/Softfloat 3a Thread Safety 27 Oct 2016 23:07:10 Page 5 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 192 *********************************************************************** + 193 * + 194 * Data areas global to all four processors and areas that are per-cpu. + 195 * + 196 * Per-CPU variables are prefixed with 'CPUn' where n is replaced with + 197 * the CPU number, starting with zero. + 198 * + 199 *********************************************************************** + + + 201 * + 0000000000000006 0000000000000001 202 SIGPREST EQU 6 SIGP order for CPU Restart + 0000000000000005 0000000000000001 203 SIGPSTOP EQU 5 SIGP order for CPU Stop + 000000000000000D 0000000000000001 204 SIGPPREF EQU 13 SIGP order for Set Prefix + 205 * +0000000000000218 206 DS 0D Ensure correct alignment for psw +0000000000000218 00020000 00000000 207 WAITPSW DC X'0002000000000000',AD(0) Normal end - disabled wait +0000000000000228 00020000 00000000 208 HARDWAIT DC X'0002000000000000',XL6'00',X'DEAD' Abnormal end + 209 * +0000000000000238 00000000 210 CPU0CR0 DS F CR0, used to turn on AFP +000000000000023C 00000000 211 CPU1CR0 DS F CR0, used to turn on AFP +0000000000000240 00000000 212 CPU2CR0 DS F CR0, used to turn on AFP +0000000000000244 00000000 213 CPU3CR0 DS F CR0, used to turn on AFP + 214 * +0000000000000248 0000 215 CPU0ADR DS H CPU addr returned from STAP, used by SIGP +000000000000024A 0000 216 CPU1ADR DS H CPU addr returned from STAP, used by SIGP +000000000000024C 0000 217 CPU2ADR DS H CPU addr returned from STAP, used by SIGP +000000000000024E 0000 218 CPU3ADR DS H CPU addr returned from STAP, used by SIGP + ASMA Ver. 0.2.0 bfp-023-threads.asm: Test IEEE/Softfloat 3a Thread Safety 27 Oct 2016 23:07:10 Page 6 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 220 *********************************************************************** + 221 * + 222 * CPU 0 program. Set prefixes, start all processors, enable Additional + 223 * Floating Point Registers, repetitively perform a floating point + 224 * operation, then stop all three other processors and load a hard wait + 225 * PSW. + 226 * + 227 *********************************************************************** + + +0000000000000250 229 CPU0BEG DS 0H Start of processing for CPU zero +0000000000000250 B212 F248 0000000000000248 230 STAP CPU0ADR Store CPU address of this processor +0000000000000254 4810 F248 0000000000000248 231 LH R1,CPU0ADR Get CPU address +0000000000000258 4110 1001 0000000000000001 232 LA R1,1(,R1) Update to next CPU address +000000000000025C 4010 F24A 000000000000024A 233 STH R1,CPU1ADR Store next CPU address +0000000000000260 4110 1001 0000000000000001 234 LA R1,1(,R1) Update to next CPU address +0000000000000264 4010 F24C 000000000000024C 235 STH R1,CPU2ADR Store next CPU address +0000000000000268 4110 1001 0000000000000001 236 LA R1,1(,R1) Update to next CPU address +000000000000026C 4010 F24E 000000000000024E 237 STH R1,CPU3ADR Store next CPU address + 238 * + 239 * Set up prefixing for each of the three additional CPUs that will + 240 * perform floating point operations. Copy the first 8K to appropriate + 241 * locations for each of the CPUs, modify the restart PSW, and issue + 242 * SIGP Set Prefix for each of them. + 243 * + 244 * Because the entirety of this program fits in less than 8K, prefixing + 245 * is not difficult. + 246 * + 247 * Set Prefix and start CPU 1 +0000000000000270 4820 F24A 000000000000024A 248 LH R2,CPU1ADR Get next CPU addresss +0000000000000274 E310 F5E8 0004 00000000000005E8 249 LG R1,=AD(CPU1PRE) Get address of CPU1 Prefix area +000000000000027A 1700 250 XR R0,R0 Set address of real low core +000000000000027C B254 0010 251 MVPG R1,R0 Make a copy of low core +0000000000000280 AE12 000D 000000000000000D 252 SIGP R1,R2,SIGPPREF Set prefix area for CPU 1 +0000000000000284 D207 11A8 F5E0 00000000000001A8 00000000000005E0 253 MVC RPSWADR(8,R1),=AD(CPU1BEG) Update restart PSW in prefix +000000000000028A 1711 254 XR R1,R1 Zero SIGP parameter register +000000000000028C AE02 0006 0000000000000006 255 SIGP R0,R2,SIGPREST Start next CPU using a Restart command + 256 * + 257 * Set Prefix and start CPU 2 +0000000000000290 4820 F24C 000000000000024C 258 LH R2,CPU2ADR Get next CPU addresss +0000000000000294 E310 F5F8 0004 00000000000005F8 259 LG R1,=AD(CPU2PRE) Get address of CPU1 Prefix area +000000000000029A 1700 260 XR R0,R0 Set address of real low core +000000000000029C B254 0010 261 MVPG R1,R0 Make a copy of low core +00000000000002A0 AE12 000D 000000000000000D 262 SIGP R1,R2,SIGPPREF Set prefix area for CPU 2 +00000000000002A4 D207 11A8 F608 00000000000001A8 0000000000000608 263 MVC RPSWADR(8,R1),=AD(CPU2BEG) Update restart PSW in prefix +00000000000002AA 1711 264 XR R1,R1 Zero SIGP parameter register +00000000000002AC AE02 0006 0000000000000006 265 SIGP R0,R2,SIGPREST Start next CPU using a Restart command + 266 * + 267 * Set Prefix and start CPU 3 +00000000000002B0 4820 F24E 000000000000024E 268 LH R2,CPU3ADR Get next CPU addresss +00000000000002B4 E310 F5F0 0004 00000000000005F0 269 LG R1,=AD(CPU3PRE) Get address of CPU1 Prefix area +00000000000002BA 1700 270 XR R0,R0 Set address of real low core + ASMA Ver. 0.2.0 bfp-023-threads.asm: Test IEEE/Softfloat 3a Thread Safety 27 Oct 2016 23:07:10 Page 7 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000002BC B254 0010 271 MVPG R1,R0 Make a copy of low core +00000000000002C0 AE12 000D 000000000000000D 272 SIGP R1,R2,SIGPPREF Set prefix area for CPU 3 +00000000000002C4 D207 11A8 F600 00000000000001A8 0000000000000600 273 MVC RPSWADR(8,R1),=AD(CPU3BEG) Update restart PSW in prefix +00000000000002CA 1711 274 XR R1,R1 Zero SIGP parameter register +00000000000002CC AE02 0006 0000000000000006 275 SIGP R0,R2,SIGPREST Start next CPU using a Restart command + 276 * + 277 * Other processors started. Now perform floating point operations. + 278 * +00000000000002D0 B600 F238 0000000000000238 279 STCTL R0,R0,CPU0CR0 Store CR0 to enable AFP +00000000000002D4 9604 F239 0000000000000239 280 OI CPU0CR0+1,X'04' Turn on AFP bit +00000000000002D8 B700 F238 0000000000000238 281 LCTL R0,R0,CPU0CR0 Reload updated CR0 + 282 * + 283 * Initialize counter for loop control + 284 * +00000000000002DC C0C0 0000 0E92 0000000000002000 285 LARL R12,RESAREA Point to shared results area +00000000000002E2 0000000000002000 286 USING RESAREA,R12 Make results addressable +00000000000002E2 5820 F610 0000000000000610 287 L R2,=F'10000000' Run loop 10,000,000 times +00000000000002E6 1733 288 XR R3,R3 Zero count of loop iterations +00000000000002E8 1843 289 LR R4,R3 Zero count of detected pre-emptions +00000000000002EA 1853 290 LR R5,R3 Zero count of result errors +00000000000002EC 1863 291 LR R6,R3 Zero count of FPCR contents errors +00000000000002EE 0DD0 292 BASR R13,0 Set top of loop + 293 * + 294 * Top of loop. Check for pre-emption, do floating point operation, + 295 * increment count of trips through loop. + 296 * +00000000000002F0 D501 C080 F248 0000000000002080 0000000000000248 297 CLC LASTCPU,CPU0ADR Has another CPU been dispatched +00000000000002F6 4780 F308 0000000000000308 298 BE CPU0CALC ..not that we can detect...do calc. +00000000000002FA D201 C080 F248 0000000000002080 0000000000000248 299 MVC LASTCPU,CPU0ADR Update last dispatched CPU +0000000000000300 4140 4001 0000000000000001 300 LA R4,1(,R4) Increment count of pre-emption detections +0000000000000304 5040 C010 0000000000002010 301 ST R4,CPU0PDET Store updated count + 302 * +0000000000000308 303 CPU0CALC DS 0H Perform floating point operation +0000000000000308 B29D F3BC 00000000000003BC 304 LFPC CPU0FPCR Reset FPCR to non-trap, RNTE +000000000000030C 7820 F3C0 00000000000003C0 305 LE FPR2,CPU0OP1 Load operand one +0000000000000310 B357 0082 306 FIEBR FPR8,0,FPR2 Floating Point Integer +0000000000000314 7080 C040 0000000000002040 307 STE FPR8,CPU0ARES Store actual result +0000000000000318 B29C C044 0000000000002044 308 STFPC CPU0AFPC Store actual FPCR contents + 309 * +000000000000031C D503 C040 F3C4 0000000000002040 00000000000003C4 310 CLC CPU0ARES,CPU0ER1 Did we get expected results? +0000000000000322 4780 F334 0000000000000334 311 BE CPU0CF1C ..Yes, go check FPCR contents +0000000000000326 4150 5001 0000000000000001 312 LA R5,1(,R5) Increment result error count +000000000000032A 5050 C020 0000000000002020 313 ST R5,CPU0RECT Store updated result error count +000000000000032E D203 C060 C040 0000000000002060 0000000000002040 314 MVC CPU0XRES,CPU0ARES Save incorrect result + 315 * +0000000000000334 316 CPU0CF1C DS 0H +0000000000000334 D503 C044 F3C8 0000000000002044 00000000000003C8 317 CLC CPU0AFPC,CPU0EF1 Did we get expected results? +000000000000033A 4780 F34C 000000000000034C 318 BE CPU0OPNX ..Yes, do next operation +000000000000033E 4160 6001 0000000000000001 319 LA R6,1(,R6) Increment FPCR contents error count +0000000000000342 5060 C030 0000000000002030 320 ST R6,CPU0FECT Store updated FPCR contents error count +0000000000000346 D203 C064 C044 0000000000002064 0000000000002044 321 MVC CPU0XFPC,CPU0AFPC Save incorrect result + 322 * + ASMA Ver. 0.2.0 bfp-023-threads.asm: Test IEEE/Softfloat 3a Thread Safety 27 Oct 2016 23:07:10 Page 8 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +000000000000034C 323 CPU0OPNX DS 0H Do second floating point operation +000000000000034C B29D F3BC 00000000000003BC 324 LFPC CPU0FPCR Reset FPCR to non-trap, RNTE +0000000000000350 7820 F3CC 00000000000003CC 325 LE FPR2,CPU0OP2 Load operand one +0000000000000354 B357 0082 326 FIEBR FPR8,0,FPR2 Floating Point Integer +0000000000000358 7080 C040 0000000000002040 327 STE FPR8,CPU0ARES Store actual result +000000000000035C B29C C044 0000000000002044 328 STFPC CPU0AFPC Store actual FPCR contents + 329 * +0000000000000360 D503 C040 F3D0 0000000000002040 00000000000003D0 330 CLC CPU0ARES,CPU0ER2 Did we get expected results? +0000000000000366 4780 F378 0000000000000378 331 BE CPU0CF2C ..Yes, go check FPCR contents +000000000000036A 4150 5001 0000000000000001 332 LA R5,1(,R5) Increment result error count +000000000000036E 5050 C020 0000000000002020 333 ST R5,CPU0RECT Store updated result error count +0000000000000372 D203 C060 C040 0000000000002060 0000000000002040 334 MVC CPU0XRES,CPU0ARES Save incorrect result + 335 * +0000000000000378 336 CPU0CF2C DS 0H +0000000000000378 D503 C044 F3D4 0000000000002044 00000000000003D4 337 CLC CPU0AFPC,CPU0EF2 Did we get expected results? +000000000000037E 4780 F390 0000000000000390 338 BE CPU0OPDN ..Yes, end of iteration +0000000000000382 4160 6001 0000000000000001 339 LA R6,1(,R6) Increment FPCR contents error count +0000000000000386 5060 C030 0000000000002030 340 ST R6,CPU0FECT Store updated FPCR contents error count +000000000000038A D203 C064 C044 0000000000002064 0000000000002044 341 MVC CPU0XFPC,CPU0AFPC Save incorrect result + 342 * +0000000000000390 343 CPU0OPDN DS 0H FP op and result checks done +0000000000000390 4130 3001 0000000000000001 344 LA R3,1(,R3) Increment loop iteration count +0000000000000394 5030 C000 0000000000002000 345 ST R3,CPU0CTR Store updated loop iteration count +0000000000000398 062D 346 BCTR R2,R13 Perform next iteration + 347 * + 348 * Looping completed. Stop other processors and load hardwait PSW. + 349 * +000000000000039A 350 DROP R12 +000000000000039A 1711 351 XR R1,R1 Zero SIGP parameter register + 352 * +000000000000039C 4820 F24A 000000000000024A 353 LH R2,CPU1ADR Get next CPU addresss +00000000000003A0 AE02 0005 0000000000000005 354 SIGP R0,R2,SIGPSTOP Stop the CPU + 355 * +00000000000003A4 4820 F24C 000000000000024C 356 LH R2,CPU2ADR Get next CPU addresss +00000000000003A8 AE02 0005 0000000000000005 357 SIGP R0,R2,SIGPSTOP Stop the CPU + 358 * +00000000000003AC 4820 F24E 000000000000024E 359 LH R2,CPU3ADR Get next CPU addresss +00000000000003B0 AE02 0005 0000000000000005 360 SIGP R0,R2,SIGPSTOP Stop the CPU + 361 * +00000000000003B4 12EE 362 LTR R14,R14 Return address provided? +00000000000003B6 077E 363 BNZR R14 ..Yes, return to z/CMS test rig. +00000000000003B8 B2B2 F218 0000000000000218 364 LPSWE WAITPSW All done + 365 * + 366 * Load Floating Point Integer of 1.5, RNTE. Expect 2.0 and inexact + 367 * +00000000000003BC 00000000 368 CPU0FPCR DC X'00000000' FPCR, no traps, RNTE + 369 * +00000000000003C0 3FC00000 370 CPU0OP1 DC X'3FC00000' +1.5 +00000000000003C4 40000000 371 CPU0ER1 DC X'40000000' Expected result 2.0 +00000000000003C8 00080000 372 CPU0EF1 DC X'00080000' Expected FPCR contents flag inexact + 373 * +00000000000003CC 3F800000 374 CPU0OP2 DC X'3F800000' +1.0 + ASMA Ver. 0.2.0 bfp-023-threads.asm: Test IEEE/Softfloat 3a Thread Safety 27 Oct 2016 23:07:10 Page 9 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000003D0 3F800000 375 CPU0ER2 DC X'3F800000' Expected 1.0 +00000000000003D4 00000000 376 CPU0EF2 DC X'00000000' Expected FPCR flag-free, RNTE + 377 * + ASMA Ver. 0.2.0 bfp-023-threads.asm: Test IEEE/Softfloat 3a Thread Safety 27 Oct 2016 23:07:10 Page 10 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 379 *********************************************************************** + 380 * + 381 * CPU 1 program. Start the next processor, enable Advanced Floating + 382 * Point, and repetitively perform a floating point operation until + 383 * this processor is stopped by CPU 0. + 384 * + 385 *********************************************************************** + + +00000000000003D8 387 CPU1BEG DS 0H Start of processing for CPU zero + 388 * +00000000000003D8 B600 F23C 000000000000023C 389 STCTL R0,R0,CPU1CR0 Store CR0 to enable AFP +00000000000003DC 9604 F23D 000000000000023D 390 OI CPU1CR0+1,X'04' Turn on AFP bit +00000000000003E0 B700 F23C 000000000000023C 391 LCTL R0,R0,CPU1CR0 Reload updated CR0 + 392 * + 393 * Perform repetitive operation in a loop + 394 * +00000000000003E4 C0C0 0000 0E0E 0000000000002000 395 LARL R12,RESAREA Point to shared results area +00000000000003EA 0000000000002000 396 USING RESAREA,R12 Make results addressable +00000000000003EA 1733 397 XR R3,R3 Zero count of loop iterations +00000000000003EC 1843 398 LR R4,R3 Zero count of detected pre-emptions +00000000000003EE 1853 399 LR R5,R3 Zero count of result errors +00000000000003F0 1863 400 LR R6,R3 Zero count of FPCR contents errors +00000000000003F2 0DD0 401 BASR R13,0 Set top of loop + 402 * + 403 * Top of loop. Check for pre-emption, do floating point operation, + 404 * increment count of trips through loop. + 405 * +00000000000003F4 D501 C080 F24A 0000000000002080 000000000000024A 406 CLC LASTCPU,CPU1ADR Has another CPU been dispatched +00000000000003FA 4780 F40C 000000000000040C 407 BE CPU1CALC ..not that we can detect...do calc. +00000000000003FE D201 C080 F24A 0000000000002080 000000000000024A 408 MVC LASTCPU,CPU1ADR Update last dispatched CPU +0000000000000404 4140 4001 0000000000000001 409 LA R4,1(,R4) Increment count of pre-emption detections +0000000000000408 5040 C014 0000000000002014 410 ST R4,CPU1PDET Store updated count + 411 * +000000000000040C 412 CPU1CALC DS 0H Perform floating point operation +000000000000040C B29D F49E 000000000000049E 413 LFPC CPU1FPCR Reset FPCR to non-trap, RM +0000000000000410 7820 F4A2 00000000000004A2 414 LE FPR2,CPU1OP1 Load operand one +0000000000000414 B357 0082 415 FIEBR FPR8,0,FPR2 Convert to Floating Point integer +0000000000000418 7080 C048 0000000000002048 416 STE FPR8,CPU1ARES Store actual result +000000000000041C B29C C04C 000000000000204C 417 STFPC CPU1AFPC Store actual FPCR contents + 418 * +0000000000000420 D503 C048 F4A6 0000000000002048 00000000000004A6 419 CLC CPU1ARES,CPU1ER1 Did we get expected results? +0000000000000426 4780 F438 0000000000000438 420 BE CPU1CF1C ..Yes, go check FPCR contents +000000000000042A 4150 5001 0000000000000001 421 LA R5,1(,R5) Increment result error count +000000000000042E 5050 C024 0000000000002024 422 ST R5,CPU1RECT Store updated loop iteration count +0000000000000432 D203 C068 C048 0000000000002068 0000000000002048 423 MVC CPU1XRES,CPU1ARES Save incorrect result + 424 * +0000000000000438 425 CPU1CF1C DS 0H +0000000000000438 D503 C04C F4AA 000000000000204C 00000000000004AA 426 CLC CPU1AFPC,CPU1EF1 Did we get expected results? +000000000000043E 4780 F450 0000000000000450 427 BE CPU1OPNX ..Yes, end of iteration +0000000000000442 4160 6001 0000000000000001 428 LA R6,1(,R6) Increment FPCR contents error count +0000000000000446 5060 C034 0000000000002034 429 ST R6,CPU1FECT Store updated loop iteration count + ASMA Ver. 0.2.0 bfp-023-threads.asm: Test IEEE/Softfloat 3a Thread Safety 27 Oct 2016 23:07:10 Page 11 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +000000000000044A D203 C06C C04C 000000000000206C 000000000000204C 430 MVC CPU1XFPC,CPU1AFPC Save incorrect result + 431 * +0000000000000450 432 CPU1OPNX DS 0H FP op and result checks done +0000000000000450 B29D F49E 000000000000049E 433 LFPC CPU1FPCR Reset FPCR to non-trap, RM +0000000000000454 7820 F4AE 00000000000004AE 434 LE FPR2,CPU1OP2 Load operand one +0000000000000458 B357 0082 435 FIEBR FPR8,0,FPR2 Convert to Floating Point integer +000000000000045C 7080 C048 0000000000002048 436 STE FPR8,CPU1ARES Store actual result +0000000000000460 B29C C04C 000000000000204C 437 STFPC CPU1AFPC Store actual FPCR contents + 438 * +0000000000000464 D503 C048 F4B2 0000000000002048 00000000000004B2 439 CLC CPU1ARES,CPU1ER2 Did we get expected results? +000000000000046A 4780 F47C 000000000000047C 440 BE CPU1CF2C ..Yes, go check FPCR contents +000000000000046E 4150 5001 0000000000000001 441 LA R5,1(,R5) Increment result error count +0000000000000472 5050 C024 0000000000002024 442 ST R5,CPU1RECT Store updated loop iteration count +0000000000000476 D203 C068 C048 0000000000002068 0000000000002048 443 MVC CPU1XRES,CPU1ARES Save incorrect result + 444 * +000000000000047C 445 CPU1CF2C DS 0H +000000000000047C D503 C04C F4B6 000000000000204C 00000000000004B6 446 CLC CPU1AFPC,CPU1EF2 Did we get expected results? +0000000000000482 4780 F494 0000000000000494 447 BE CPU1OPDN ..Yes, end of iteration +0000000000000486 4160 6001 0000000000000001 448 LA R6,1(,R6) Increment FPCR contents error count +000000000000048A 5060 C034 0000000000002034 449 ST R6,CPU1FECT Store updated loop iteration count +000000000000048E D203 C06C C04C 000000000000206C 000000000000204C 450 MVC CPU1XFPC,CPU1AFPC Save incorrect result + 451 * +0000000000000494 452 CPU1OPDN DS 0H FP op and result checks done +0000000000000494 4130 3001 0000000000000001 453 LA R3,1(,R3) Increment count of loop iterations +0000000000000498 5030 C004 0000000000002004 454 ST R3,CPU1CTR Store updated loop iteration count +000000000000049C 07FD 455 BR R13 Perform next iteration until CPU stopped + 456 * +000000000000049E 457 DROP R12 + 458 * + 459 * Load Floating Point Integer of 1.5, RZ. Expect 1.0 and inexact + 460 * +000000000000049E 00000001 461 CPU1FPCR DC X'00000001' FPCR, no traps, RZ + 462 * +00000000000004A2 3FC00000 463 CPU1OP1 DC X'3FC00000' +1.5 +00000000000004A6 3F800000 464 CPU1ER1 DC X'3F800000' Expected 1.0 +00000000000004AA 00080001 465 CPU1EF1 DC X'00080001' Expected FPCR flag inexact, RM + 466 * +00000000000004AE 3F800000 467 CPU1OP2 DC X'3F800000' +1.0 +00000000000004B2 3F800000 468 CPU1ER2 DC X'3F800000' Expected 1.0 +00000000000004B6 00000001 469 CPU1EF2 DC X'00000001' Expected FPCR flag-free, RM + 470 * + ASMA Ver. 0.2.0 bfp-023-threads.asm: Test IEEE/Softfloat 3a Thread Safety 27 Oct 2016 23:07:10 Page 12 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 472 *********************************************************************** + 473 * + 474 * CPU 2 program. Start the next processor, enable Advanced Floating + 475 * Point, and repetitively perform a floating point operation until + 476 * this processor is stopped by CPU 0. + 477 * + 478 *********************************************************************** + + +00000000000004BA 480 CPU2BEG DS 0H Start of processing for CPU zero + 481 * +00000000000004BA B600 F240 0000000000000240 482 STCTL R0,R0,CPU2CR0 Store CR0 to enable AFP +00000000000004BE 9604 F241 0000000000000241 483 OI CPU2CR0+1,X'04' Turn on AFP bit +00000000000004C2 B700 F240 0000000000000240 484 LCTL R0,R0,CPU2CR0 Reload updated CR0 + 485 * + 486 * Perform repetitive operation in a loop + 487 * +00000000000004C6 C0C0 0000 0D9D 0000000000002000 488 LARL R12,RESAREA Point to shared results area +00000000000004CC 0000000000002000 489 USING RESAREA,R12 Make results addressable +00000000000004CC 1733 490 XR R3,R3 Zero count of loop iterations +00000000000004CE 1843 491 LR R4,R3 Zero count of detected pre-emptions +00000000000004D0 1853 492 LR R5,R3 Zero count of result errors +00000000000004D2 1863 493 LR R6,R3 Zero count of FPCR contents errors +00000000000004D4 0DD0 494 BASR R13,0 Set top of loop + 495 * + 496 * Top of loop. Check for pre-emption, do floating point operation, + 497 * increment count of trips through loop. + 498 * +00000000000004D6 D501 C080 F24C 0000000000002080 000000000000024C 499 CLC LASTCPU,CPU2ADR Has another CPU been dispatched +00000000000004DC 4780 F4EE 00000000000004EE 500 BE CPU2CALC ..not that we can detect...do calc. +00000000000004E0 D201 C080 F24C 0000000000002080 000000000000024C 501 MVC LASTCPU,CPU2ADR Update last dispatched CPU +00000000000004E6 4140 4001 0000000000000001 502 LA R4,1(,R4) Increment count of pre-emption detections +00000000000004EA 5040 C018 0000000000002018 503 ST R4,CPU2PDET Store updated count + 504 * +00000000000004EE 505 CPU2CALC DS 0H Perform floating point operation +00000000000004EE B29D F53C 000000000000053C 506 LFPC CPU2FPCR Reset FPCR to non-trap, RM +00000000000004F2 7820 F540 0000000000000540 507 LE FPR2,CPU2OP1 Load operand one +00000000000004F6 B357 0082 508 FIEBR FPR8,0,FPR2 Convert to Floating Point integer +00000000000004FA 7080 C050 0000000000002050 509 STE FPR8,CPU2ARES Store actual result +00000000000004FE B29C C054 0000000000002054 510 STFPC CPU2AFPC Store actual FPCR contents + 511 * +0000000000000502 D503 C050 F544 0000000000002050 0000000000000544 512 CLC CPU2ARES,CPU2ERES Did we get expected results? +0000000000000508 4780 F51A 000000000000051A 513 BE CPU2CFPC ..Yes, go check FPCR contents +000000000000050C 4150 5001 0000000000000001 514 LA R5,1(,R5) Increment result error count +0000000000000510 5050 C028 0000000000002028 515 ST R5,CPU2RECT Store updated loop iteration count +0000000000000514 D203 C070 C050 0000000000002070 0000000000002050 516 MVC CPU2XRES,CPU2ARES Save incorrect result + 517 * +000000000000051A 518 CPU2CFPC DS 0H +000000000000051A D503 C054 F548 0000000000002054 0000000000000548 519 CLC CPU2AFPC,CPU2EFPC Did we get expected results? +0000000000000520 4780 F532 0000000000000532 520 BE CPU2OPDN ..Yes, end of iteration +0000000000000524 4160 6001 0000000000000001 521 LA R6,1(,R6) Increment FPCR contents error count +0000000000000528 5060 C038 0000000000002038 522 ST R6,CPU2FECT Store updated loop iteration count + ASMA Ver. 0.2.0 bfp-023-threads.asm: Test IEEE/Softfloat 3a Thread Safety 27 Oct 2016 23:07:10 Page 13 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +000000000000052C D203 C074 C054 0000000000002074 0000000000002054 523 MVC CPU2XFPC,CPU2AFPC Save incorrect result + 524 * +0000000000000532 525 CPU2OPDN DS 0H FP op and result checks done +0000000000000532 4130 3001 0000000000000001 526 LA R3,1(,R3) Increment count of loop iterations +0000000000000536 5030 C008 0000000000002008 527 ST R3,CPU2CTR Store updated loop iteration count +000000000000053A 07FD 528 BR R13 Perform next iteration until CPU stopped + 529 * +000000000000053C 530 DROP R12 + 531 * + 532 * Load Floating Point Integer of 1.5, RP. Expect 2.0 and inexact + 533 * +000000000000053C 00000002 534 CPU2FPCR DC X'00000002' FPCR, no traps, RP + 535 * +0000000000000540 3FC00000 536 CPU2OP1 DC X'3FC00000' +1.5 + 537 * +0000000000000544 40000000 538 CPU2ERES DC X'40000000' Expected 2.0 +0000000000000548 00080002 539 CPU2EFPC DC X'00080002' Expected FPCR flag inexact, RM + ASMA Ver. 0.2.0 bfp-023-threads.asm: Test IEEE/Softfloat 3a Thread Safety 27 Oct 2016 23:07:10 Page 14 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 541 *********************************************************************** + 542 * + 543 * CPU 3 program. Start the next processor, enable Advanced Floating + 544 * Point, and repetitively perform a floating point operation until + 545 * this processor is stopped by CPU 0. + 546 * + 547 *********************************************************************** + + +000000000000054C 549 CPU3BEG DS 0H Start of processing for CPU zero + 550 * +000000000000054C B600 F244 0000000000000244 551 STCTL R0,R0,CPU3CR0 Store CR0 to enable AFP +0000000000000550 9604 F245 0000000000000245 552 OI CPU3CR0+1,X'04' Turn on AFP bit +0000000000000554 B700 F244 0000000000000244 553 LCTL R0,R0,CPU3CR0 Reload updated CR0 + 554 * + 555 * Perform repetitive operation in a loop + 556 * +0000000000000558 C0C0 0000 0D54 0000000000002000 557 LARL R12,RESAREA Point to shared results area +000000000000055E 0000000000002000 558 USING RESAREA,R12 Make results addressable +000000000000055E 1733 559 XR R3,R3 Zero count of loop iterations +0000000000000560 1843 560 LR R4,R3 Zero count of detected pre-emptions +0000000000000562 1853 561 LR R5,R3 Zero count of result errors +0000000000000564 1863 562 LR R6,R3 Zero count of FPCR contents errors +0000000000000566 0DD0 563 BASR R13,0 Set top of loop + 564 * + 565 * Top of loop. Check for pre-emption, do floating point operation, + 566 * increment count of trips through loop. + 567 * +0000000000000568 D501 C080 F24E 0000000000002080 000000000000024E 568 CLC LASTCPU,CPU3ADR Has another CPU been dispatched +000000000000056E 4780 F580 0000000000000580 569 BE CPU3CALC ..not that we can detect...do calc. +0000000000000572 D201 C080 F24E 0000000000002080 000000000000024E 570 MVC LASTCPU,CPU3ADR Update last dispatched CPU +0000000000000578 4140 4001 0000000000000001 571 LA R4,1(,R4) Increment count of pre-emption detections +000000000000057C 5040 C01C 000000000000201C 572 ST R4,CPU3PDET Store updated count + 573 * +0000000000000580 574 CPU3CALC DS 0H Perform floating point operation +0000000000000580 B29D F5CE 00000000000005CE 575 LFPC CPU3FPCR Reset FPCR to non-trap, RM +0000000000000584 7820 F5D2 00000000000005D2 576 LE FPR2,CPU3OP1 Load operand one +0000000000000588 B357 0082 577 FIEBR FPR8,0,FPR2 Convert to Floating Point integer +000000000000058C 7080 C058 0000000000002058 578 STE FPR8,CPU3ARES Store actual result +0000000000000590 B29C C05C 000000000000205C 579 STFPC CPU3AFPC Store actual FPCR contents + 580 * +0000000000000594 D503 C058 F5D6 0000000000002058 00000000000005D6 581 CLC CPU3ARES,CPU3ERES Did we get expected results? +000000000000059A 4780 F5AC 00000000000005AC 582 BE CPU3CFPC ..Yes, go check FPCR contents +000000000000059E 4150 5001 0000000000000001 583 LA R5,1(,R5) Increment result error count +00000000000005A2 5050 C02C 000000000000202C 584 ST R5,CPU3RECT Store updated loop iteration count +00000000000005A6 D203 C078 C058 0000000000002078 0000000000002058 585 MVC CPU3XRES,CPU3ARES Save incorrect result + 586 * +00000000000005AC 587 CPU3CFPC DS 0H +00000000000005AC D503 C05C F5DA 000000000000205C 00000000000005DA 588 CLC CPU3AFPC,CPU3EFPC Did we get expected FPCR? +00000000000005B2 4780 F5C4 00000000000005C4 589 BE CPU3OPDN ..Yes, end of iteration +00000000000005B6 4160 6001 0000000000000001 590 LA R6,1(,R6) Increment FPCR contents error count +00000000000005BA 5060 C03C 000000000000203C 591 ST R6,CPU3FECT Store updated loop iteration count + ASMA Ver. 0.2.0 bfp-023-threads.asm: Test IEEE/Softfloat 3a Thread Safety 27 Oct 2016 23:07:10 Page 15 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +00000000000005BE D203 C07C C05C 000000000000207C 000000000000205C 592 MVC CPU3XFPC,CPU3AFPC Save incorrect result + 593 * +00000000000005C4 594 CPU3OPDN DS 0H FP op and result checks done +00000000000005C4 4130 3001 0000000000000001 595 LA R3,1(,R3) Increment count of iterations +00000000000005C8 5030 C00C 000000000000200C 596 ST R3,CPU3CTR Store updated loop iteration count +00000000000005CC 07FD 597 BR R13 Perform next iteration until CPU stopped +00000000000005CE 598 DROP R12 + 599 * + 600 * Load Floating Point Integer of 1.0, RM. Expect 1.0 and no flags + 601 * +00000000000005CE 00000003 602 CPU3FPCR DC X'00000003' FPCR, no traps, RP + 603 * +00000000000005D2 3F800000 604 CPU3OP1 DC X'3F800000' +1.0 + 605 * +00000000000005D6 3F800000 606 CPU3ERES DC X'3F800000' Expected 1.0 +00000000000005DA 00000003 607 CPU3EFPC DC X'00000003' Expected FPCR flag-free, RP + + + +00000000000005E0 609 LTORG +00000000000005E0 00000000 000003D8 610 =AD(CPU1BEG) +00000000000005E8 00000000 00010000 611 =AD(CPU1PRE) +00000000000005F0 00000000 00014000 612 =AD(CPU3PRE) +00000000000005F8 00000000 00012000 613 =AD(CPU2PRE) +0000000000000600 00000000 0000054C 614 =AD(CPU3BEG) +0000000000000608 00000000 000004BA 615 =AD(CPU2BEG) +0000000000000610 00989680 616 =F'10000000' + ASMA Ver. 0.2.0 bfp-023-threads.asm: Test IEEE/Softfloat 3a Thread Safety 27 Oct 2016 23:07:10 Page 16 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 618 * + 619 * Locations for results. Because all four threads use these + 620 * values, they must not be in the area affected by prefixing. + 621 * +0000000000000614 0000000000000614 0000000000002000 622 ORG STRTLABL+X'2000' Shared tables. +0000000000002000 623 RESAREA DS 0D Start of results area + 624 * + 625 * Loop iteration counter for each CPU + 626 * +0000000000002000 00000000 627 CPU0CTR DC F'0' +0000000000002004 00000000 628 CPU1CTR DC F'0' +0000000000002008 00000000 629 CPU2CTR DC F'0' +000000000000200C 00000000 630 CPU3CTR DC F'0' + 631 * + 632 * Pre-emption detection counter for each CPU + 633 * +0000000000002010 00000000 634 CPU0PDET DC F'0' +0000000000002014 00000000 635 CPU1PDET DC F'0' +0000000000002018 00000000 636 CPU2PDET DC F'0' +000000000000201C 00000000 637 CPU3PDET DC F'0' + 638 * + 639 * Result error detection counter for each CPU + 640 * +0000000000002020 00000000 641 CPU0RECT DC F'0' +0000000000002024 00000000 642 CPU1RECT DC F'0' +0000000000002028 00000000 643 CPU2RECT DC F'0' +000000000000202C 00000000 644 CPU3RECT DC F'0' + 645 * + 646 * FPCR contents error detection counter for each CPU + 647 * +0000000000002030 00000000 648 CPU0FECT DC F'0' +0000000000002034 00000000 649 CPU1FECT DC F'0' +0000000000002038 00000000 650 CPU2FECT DC F'0' +000000000000203C 00000000 651 CPU3FECT DC F'0' + 652 * + 653 * Actual Results + 654 * +0000000000002040 00000000 655 CPU0ARES DC X'00000000' Actual results +0000000000002044 00000000 656 CPU0AFPC DC X'00000000' Actual FPCR contents + 657 * +0000000000002048 00000000 658 CPU1ARES DC X'00000000' Actual results +000000000000204C 00000000 659 CPU1AFPC DC X'00000000' Actual FPCR contents + 660 * +0000000000002050 00000000 661 CPU2ARES DC X'00000000' Actual results +0000000000002054 00000000 662 CPU2AFPC DC X'00000000' Actual FPCR contents + 663 * +0000000000002058 00000000 664 CPU3ARES DC X'00000000' Actual results +000000000000205C 00000000 665 CPU3AFPC DC X'00000000' Actual FPCR contents + 666 * + 667 * Error Results + 668 * +0000000000002060 00000000 669 CPU0XRES DC X'00000000' Last error results + ASMA Ver. 0.2.0 bfp-023-threads.asm: Test IEEE/Softfloat 3a Thread Safety 27 Oct 2016 23:07:10 Page 17 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000002064 00000000 670 CPU0XFPC DC X'00000000' Last error FPCR contents + 671 * +0000000000002068 00000000 672 CPU1XRES DC X'00000000' Last error results +000000000000206C 00000000 673 CPU1XFPC DC X'00000000' Last error FPCR contents + 674 * +0000000000002070 00000000 675 CPU2XRES DC X'00000000' Last error results +0000000000002074 00000000 676 CPU2XFPC DC X'00000000' Last error FPCR contents + 677 * +0000000000002078 00000000 678 CPU3XRES DC X'00000000' Last error results +000000000000207C 00000000 679 CPU3XFPC DC X'00000000' Last error FPCR contents + 680 * + 681 * Following shared variable used for preemption detection. Cannot be + 682 * in the prefixed area, lest each CPU have its own copy. + 683 * +0000000000002080 0000 684 LASTCPU DC H'0' Address of last detected dispatched CPU + 685 * + 0000000000002200 0000000000000001 686 ENDLABL EQU STRTLABL+X'2200' + 687 PADCSECT ENDLABL + 688+ MNOTE *,'asma detected; no CSECT padding performed' +0000000000002082 689 END + ASMA Ver. 0.2.0 bfp-023-threads.asm: Test IEEE/Softfloat 3a Thread Safety 27 Oct 2016 23:07:10 Page 18 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +BFPTHRED J 000000 8322 105 +CPU0ADR H 000248 2 215 230 231 297 299 +CPU0AFPC X 002044 4 656 308 317 321 328 337 341 +CPU0ARES X 002040 4 655 307 310 314 327 330 334 +CPU0BEG H 000250 2 229 165 +CPU0CALC H 000308 2 303 298 +CPU0CF1C H 000334 2 316 311 +CPU0CF2C H 000378 2 336 331 +CPU0CR0 F 000238 4 210 279 280 281 +CPU0CTR F 002000 4 627 345 +CPU0EF1 X 0003C8 4 372 317 +CPU0EF2 X 0003D4 4 376 337 +CPU0ER1 X 0003C4 4 371 310 +CPU0ER2 X 0003D0 4 375 330 +CPU0FECT F 002030 4 648 320 340 +CPU0FPCR X 0003BC 4 368 304 324 +CPU0OP1 X 0003C0 4 370 305 +CPU0OP2 X 0003CC 4 374 325 +CPU0OPDN H 000390 2 343 338 +CPU0OPNX H 00034C 2 323 318 +CPU0PDET F 002010 4 634 301 +CPU0RECT F 002020 4 641 313 333 +CPU0XFPC X 002064 4 670 321 341 +CPU0XRES X 002060 4 669 314 334 +CPU1ADR H 00024A 2 216 233 248 353 406 408 +CPU1AFPC X 00204C 4 659 417 426 430 437 446 450 +CPU1ARES X 002048 4 658 416 419 423 436 439 443 +CPU1BEG H 0003D8 2 387 253 +CPU1CALC H 00040C 2 412 407 +CPU1CF1C H 000438 2 425 420 +CPU1CF2C H 00047C 2 445 440 +CPU1CR0 F 00023C 4 211 389 390 391 +CPU1CTR F 002004 4 628 454 +CPU1EF1 X 0004AA 4 465 426 +CPU1EF2 X 0004B6 4 469 446 +CPU1ER1 X 0004A6 4 464 419 +CPU1ER2 X 0004B2 4 468 439 +CPU1FECT F 002034 4 649 429 449 +CPU1FPCR X 00049E 4 461 413 433 +CPU1OP1 X 0004A2 4 463 414 +CPU1OP2 X 0004AE 4 467 434 +CPU1OPDN H 000494 2 452 447 +CPU1OPNX H 000450 2 432 427 +CPU1PDET F 002014 4 635 410 +CPU1PRE U 010000 1 143 144 249 +CPU1RECT F 002024 4 642 422 442 +CPU1XFPC X 00206C 4 673 430 450 +CPU1XRES X 002068 4 672 423 443 +CPU2ADR H 00024C 2 217 235 258 356 499 501 +CPU2AFPC X 002054 4 662 510 519 523 +CPU2ARES X 002050 4 661 509 512 516 +CPU2BEG H 0004BA 2 480 263 + ASMA Ver. 0.2.0 bfp-023-threads.asm: Test IEEE/Softfloat 3a Thread Safety 27 Oct 2016 23:07:10 Page 19 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +CPU2CALC H 0004EE 2 505 500 +CPU2CFPC H 00051A 2 518 513 +CPU2CR0 F 000240 4 212 482 483 484 +CPU2CTR F 002008 4 629 527 +CPU2EFPC X 000548 4 539 519 +CPU2ERES X 000544 4 538 512 +CPU2FECT F 002038 4 650 522 +CPU2FPCR X 00053C 4 534 506 +CPU2OP1 X 000540 4 536 507 +CPU2OPDN H 000532 2 525 520 +CPU2PDET F 002018 4 636 503 +CPU2PRE U 012000 1 144 145 259 +CPU2RECT F 002028 4 643 515 +CPU2XFPC X 002074 4 676 523 +CPU2XRES X 002070 4 675 516 +CPU3ADR H 00024E 2 218 237 268 359 568 570 +CPU3AFPC X 00205C 4 665 579 588 592 +CPU3ARES X 002058 4 664 578 581 585 +CPU3BEG H 00054C 2 549 273 +CPU3CALC H 000580 2 574 569 +CPU3CFPC H 0005AC 2 587 582 +CPU3CR0 F 000244 4 213 551 552 553 +CPU3CTR F 00200C 4 630 596 +CPU3EFPC X 0005DA 4 607 588 +CPU3ERES X 0005D6 4 606 581 +CPU3FECT F 00203C 4 651 591 +CPU3FPCR X 0005CE 4 602 575 +CPU3OP1 X 0005D2 4 604 576 +CPU3OPDN H 0005C4 2 594 589 +CPU3PDET F 00201C 4 637 572 +CPU3PRE U 014000 1 145 269 +CPU3RECT F 00202C 4 644 584 +CPU3XFPC X 00207C 4 679 592 +CPU3XRES X 002078 4 678 585 +ENDLABL U 002200 1 686 +FPR0 U 000000 1 126 +FPR1 U 000001 1 127 +FPR10 U 00000A 1 136 +FPR11 U 00000B 1 137 +FPR12 U 00000C 1 138 +FPR13 U 00000D 1 139 +FPR14 U 00000E 1 140 +FPR15 U 00000F 1 141 +FPR2 U 000002 1 128 305 306 325 326 414 415 434 435 507 508 576 577 +FPR3 U 000003 1 129 +FPR4 U 000004 1 130 +FPR5 U 000005 1 131 +FPR6 U 000006 1 132 +FPR7 U 000007 1 133 +FPR8 U 000008 1 134 306 307 326 327 415 416 435 436 508 509 577 578 +FPR9 U 000009 1 135 +HARDWAIT X 000228 8 208 189 + ASMA Ver. 0.2.0 bfp-023-threads.asm: Test IEEE/Softfloat 3a Thread Safety 27 Oct 2016 23:07:10 Page 20 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +IMAGE 1 000000 8322 0 +LASTCPU H 002080 2 684 297 299 406 408 499 501 568 570 +PCINTCD H 00008E 2 160 183 +PCNOTDTA H 00020C 2 186 184 +PCOLDPSW U 000150 1 162 185 +PROGCHK H 000200 2 182 169 +R0 U 000000 1 107 250 251 255 260 261 265 270 271 275 279 281 354 357 360 389 391 482 + 484 551 553 +R1 U 000001 1 108 231 232 233 234 235 236 237 249 251 252 253 254 259 261 262 263 264 + 269 271 272 273 274 351 +R10 U 00000A 1 117 +R11 U 00000B 1 118 +R12 U 00000C 1 119 285 286 350 395 396 457 488 489 530 557 558 598 +R13 U 00000D 1 120 292 346 401 455 494 528 563 597 +R14 U 00000E 1 121 187 188 362 363 +R15 U 00000F 1 122 147 +R2 U 000002 1 109 248 252 255 258 262 265 268 272 275 287 346 353 354 356 357 359 360 +R3 U 000003 1 110 288 289 290 291 344 345 397 398 399 400 453 454 490 491 492 493 526 + 527 559 560 561 562 595 596 +R4 U 000004 1 111 289 300 301 398 409 410 491 502 503 560 571 572 +R5 U 000005 1 112 290 312 313 332 333 399 421 422 441 442 492 514 515 561 583 584 +R6 U 000006 1 113 291 319 320 339 340 400 428 429 448 449 493 521 522 562 590 591 +R7 U 000007 1 114 +R8 U 000008 1 115 +R9 U 000009 1 116 +RESAREA D 002000 8 623 285 286 395 396 488 489 557 558 +RESTRPSW X 0001A0 8 165 166 +RPSWADR U 0001A8 1 166 253 263 273 +SIGPPREF U 00000D 1 204 252 262 272 +SIGPREST U 000006 1 202 255 265 275 +SIGPSTOP U 000005 1 203 354 357 360 +STRTLABL U 000000 1 106 159 162 164 166 168 181 622 686 +WAITPSW X 000218 8 207 364 +=AD(CPU1BEG) A 0005E0 8 610 253 +=AD(CPU1PRE) A 0005E8 8 611 249 +=AD(CPU2BEG) A 000608 8 615 263 +=AD(CPU2PRE) A 0005F8 8 613 259 +=AD(CPU3BEG) A 000600 8 614 273 +=AD(CPU3PRE) A 0005F0 8 612 269 +=F'10000000' F 000610 4 616 287 + ASMA Ver. 0.2.0 bfp-023-threads.asm: Test IEEE/Softfloat 3a Thread Safety 27 Oct 2016 23:07:10 Page 21 + + MACRO DEFN REFERENCES + +PADCSECT 78 687 + ASMA Ver. 0.2.0 bfp-023-threads.asm: Test IEEE/Softfloat 3a Thread Safety 27 Oct 2016 23:07:10 Page 22 + + DESC SYMBOL SIZE POS ADDR + +Entry: 0 + +Image IMAGE 8322 0000-2081 0000-2081 + Region 8322 0000-2081 0000-2081 + CSECT BFPTHRED 8322 0000-2081 0000-2081 + ASMA Ver. 0.2.0 bfp-023-threads.asm: Test IEEE/Softfloat 3a Thread Safety 27 Oct 2016 23:07:10 Page 23 + + STMT FILE NAME + +1 C:\Users\srorso\Documents\GitHub\hyperion\tests\bfp-023-threads.asm + + +** NO ERRORS FOUND ** + +[688] MNOTE *,asma detected; no CSECT padding performed + \ No newline at end of file diff --git a/tests/bfp-023-threads.sptst b/tests/bfp-023-threads.sptst new file mode 100644 index 000000000..9a7c1e675 --- /dev/null +++ b/tests/bfp-023-threads.sptst @@ -0,0 +1,41 @@ +*Testcase bfp-023-threads.tst: Test thread safety of ieee.c/Softfloat 3a + +#Testcase bfp-023-threads.tst: Test thread safety of ieee.c/Softfloat 3a +#..Dispatches floating point work on four CPUs. Deviation from expected +#..results indicates lack of thread safety. + +sysclear +archmode esame + +numcpu 4 # four CPUs required for this test. + +loadcore "$(testpath)/bfp-023-threads.core" + +runtest 240.0 + + +*Compare +r 2000.10 # Loop counts +*Want "Loop iterations by CPU" 00000000 00000000 00000000 00000000 +r 2010.10 +*Want "Pre-emptions detected by CPU" 00000000 00000000 00000000 00000000 + +r 2020.10 +*Want "Result errors by CPU" 00000000 00000000 00000000 00000000 +r 2030.10 +*Want "FPCR contents errors by CPU" 00000000 00000000 00000000 00000000 + +r 2040.10 +*Want "CPU0 Res/FPCR, CPU1 Res/FPCR" 00000000 00000000 00000000 00000000 +r 2050.10 +*Want "CPU2 Res/FPCR, CPU3 Res/FPCR" 00000000 00000000 00000000 00000000 + +r 2060.10 +*Want "CPU0/CPU1 last error" 00000000 00000000 00000000 00000000 +r 2070.10 +*Want "CPU0/CPU1 last error" 00000000 00000000 00000000 00000000 + +numcpu 1 + +*Done + diff --git a/tests/ieee-adds.asm b/tests/ieee-adds.asm deleted file mode 100644 index a4be35f1a..000000000 --- a/tests/ieee-adds.asm +++ /dev/null @@ -1,195 +0,0 @@ -* -*Testcase IEEE CONVERT FROM/TO FIXED 32 (6), ADD (5), 11 instr total -* ADD tests - Binary Floating Point -* -* -* Tests five addition instructions: -* ADD (extended BFP, RRE) -* ADD (long BFP, RRE) -* ADD (long BFP, RXE) -* ADD (short BFP, RRE) -* ADD (short BFP, RXE) -* -* Also tests the following three conversion instructions -* CONVERT FROM FIXED (32 to short BFP, RRE) -* CONVERT FROM FIXED (32 to long BFP, RRE) -* CONVERT FROM FIXED (32 to extended BFP, RRE) -* CONVERT TO FIXED (32 to short BFP, RRE) -* CONVERT TO FIXED (32 to long BFP, RRE) -* CONVERT TO FIXED (32 to extended BFP, RRE) -* -* Also tests the following floating point support instructions -* LOAD (Short) -* LOAD (Long) -* LOAD ZERO (Long) -* STORE (Short) -* STORE (Long) -* -* Convert integers 1, 2, 4, -2 to each BFP floating point format -* Add first and second pairs together (1 + 2, 4 + -2) in each format -* -BFPADDS START 0 -R0 EQU 0 -R1 EQU 1 -R2 EQU 2 -R3 EQU 3 -R4 EQU 4 -R5 EQU 5 -R6 EQU 6 -R7 EQU 7 -R8 EQU 8 -R9 EQU 9 -R10 EQU 10 -R11 EQU 11 -R12 EQU 12 -R13 EQU 13 -R14 EQU 14 -R15 EQU 15 - USING *,0 - ORG BFPADDS+X'1A0' - DC X'0000000180000000',AD(START) z/Arch restart PSW - ORG BFPADDS+X'1D0' - DC X'0002000000000000000000000000DEAD' z/Arch pgm chk new PSW - ORG BFPADDS+X'200' -* -START STCTL R0,R0,CTLR0 Store CR0 to enable AFP - OI CTLR0+1,X'04' Turn on AFP bit - LCTL R0,R0,CTLR0 Reload updated CR0 -* -* convert integers to three BFP formats -* - LA R2,4 Set count of test input values - LA R3,INTVALS point to start of input values - LA R7,SHORTBFP Point to start of short BFP input values - LA R8,LONGBFP Point to start of long BFP input values - LA R9,EXTBFP Point to start of extended BFP input values - BASR R12,0 Set top of loop -* - L R1,0(0,R3) Get integer test value - CEFBR R0,R1 Cvt Int in GPR1 to float in FPR0 - STE R0,0(0,R7) Store short BFP - CDFBR R0,R1 Cvt Int in GPR1 to float in FPR0 - STD R0,0(0,R8) Store long BFP - CXFBR R0,R1 Cvt Int in GPR1 to float in FPR0-FPR2 - STD R0,0(0,R9) Store extended BFP part 1 - STD R2,8(0,R9) Store extended BFP part 2 - LA R3,4(0,R3) point to next input values - LA R7,4(0,R7) Point to next short BFP converted values - LA R8,8(0,R8) Point to next long BFP converted values - LA R9,16(0,R9) Point to next extended BFP converted values - BCTR R2,R12 Convert next input value. -* -* Add pairs of values together -* - LA R2,2 Set count of addition operations - LA R3,SHORTRES Point to start of short BFP results - LA R4,LONGRES Point to start of long BFP results - LA R5,EXTRES Point to start of extended BFP results - LA R7,SHORTBFP Point to start of short BFP input values - LA R8,LONGBFP Point to start of long BFP input values - LA R9,EXTBFP Point to start of extended BFP input values - BASR R12,0 Set top of loop -* -* clear residuals from FPR0-1 -ADDLOOP LZDR R0 Zero FPR0 - clear residuals from FPR0, 1 - LZDR R1 Zero FPR1 -* BFP Short addition RXE and RRE - LE R0,0(0,R7) Get BFP short first of pair - AEB R0,4(0,R7) Add BFP short second of pair - STE R0,0(0,R3) Store short BFP result from RXE - LE R0,0(0,R7) Get BFP short first of pair - LE R1,4(0,R7) Get BFP short second of pair - AEBR R0,R1 Add BFP values, result in FPR0 - STE R0,4(0,R3) Store short BFP from RRE - LA R7,8(0,R7) Point to next short BFP input pair - LA R3,8(0,R3) Point to next short BFP result pair -* BFP Long addition RXE and RRE - LD R0,0(0,R8) Get BFP long first of pair - ADB R0,8(0,R8) Add BFP long second of pair - STD R0,0(0,R4) Store long BFP result from RXE - LD R0,0(0,R8) Get BFP long first of pair - LD R1,8(0,R8) Get BFP long second of pair - ADBR R0,R1 Add BFP values, result in FPR0 - STD R0,8(0,R4) Store long BFP from RRE - LA R8,16(0,R8) Point to next long BFP input pair - LA R4,16(0,R4) Point to next long BFP result pair -* BFP Extended addition RRE - LD R0,0(0,R9) Get BFP ext. 1st half of first of pair - LD R2,8(0,R9) Get BFP ext. 2nd half of first of pair - LD R1,16(0,R9) Get BFP ext. 1st half of second of pair - LD R3,24(0,R9) Get BFP ext. 2nd half of second of pair - AXBR R0,R1 Add BFP values, result in FPR0-FPR2 - STD R0,0(0,R5) Store ext. BFP from RRE - STD R2,8(0,R5) Store ext. BFP from RRE -* - LA R9,32(0,R9) Point to next ext. BFP input pair - LA R5,16(0,R5) Point to next ext. BFP result - BCTR R2,R12 Add next input pair -* -* Convert back to integers -* - LA R2,2 Set count of addition operations - LA R7,SHORTRES Point to start of short BFP results - LA R8,LONGRES Point to start of long BFP results - LA R9,EXTRES Point to start of extended BFP results - LA R3,ISHBFP Point to start of short BFP Integer results - LA R4,ILNBFP Point to start of long BFP integer results - LA R5,IXTBFP Point to start of extended BFP integer results - BASR R12,0 Set top of loop -* - LZDR R0 Zero FPR0 -* Convert shorts back to integer - LE R0,0(0,R7) Get BFP short result first of pair - CFEBR R0,R0 Convert to integer in r0 - ST R0,0(0,R3) Store integer result - LE R0,4(0,R7) Get BFP short result second of pair - CFEBR R0,R0 Convert to integer in r0 - ST R0,4(0,R3) Store integer result -* - LD R0,0(0,R8) Get BFP long result first of pair - CFDBR R0,R0 Convert to integer in r0 - ST R0,0(0,R4) Store integer result - LD R0,8(0,R8) Get BFP long result second of pair - CFDBR R0,R0 Convert to integer in r0 - ST R0,4(0,R4) Store integer result -* - LD R0,0(0,R9) Get BFP ext. 1st half of first of pair - LD R2,8(0,R9) Get BFP ext. 2nd half of first of pair - CFXBR R0,R0 Convert BFP Ext. to Integer-64 - ST R0,0(0,R5) Store integer result lower word -* - LA R7,8(0,R7) Point to next short BFP input pair - LA R3,8(0,R3) Point to next short BFP integer pair - LA R8,16(0,R8) Point to next long BFP input pair - LA R4,8(0,R4) Point to next long BFP integer pair - LA R9,16(0,R9) Point to next ext. BFP input - LA R5,4(0,R5) Point to next ext. BFP integer -* - BCTR R2,R12 Add next input pair -* - LPSWE WAITPSW Load enabled wait PSW -* - ORG BFPADDS+X'3EC' -CTLR0 DS F -WAITPSW DC X'00020000000000000000000000000000' Disabled wait state PSW - normal completion - ORG BFPADDS+X'400' -INTVALS DS 0F - DC F'1' - DC F'2' - DC F'4' - DC F'-2' -* -SHORTBFP DS 4F Four short BFP values -LONGBFP DS 4D Four long BFP values -EXTBFP DS 8D Four extended BPF values -* - ORG BFPADDS+X'500' -SHORTRES DS 4F Four short BFP results -LONGRES DS 4D Four long BFP results -EXTRES DS 4D Two extended BFP results -* -ISHBFP DS 4F Four short BFP results in 32-bit integer form -ILNBFP DS 4F Four long BFP results in 32-bit integer form -IXTBFP DS 4F Four extended BPF results in 32-bit integer form - - END diff --git a/tests/ieee-adds.core b/tests/ieee-adds.core deleted file mode 100644 index 0abdb6166..000000000 Binary files a/tests/ieee-adds.core and /dev/null differ diff --git a/tests/ieee-adds.list b/tests/ieee-adds.list deleted file mode 100644 index aeca144b5..000000000 --- a/tests/ieee-adds.list +++ /dev/null @@ -1,273 +0,0 @@ -ASMA Ver. 0.2.0 23 Jun 2016 09:49:47 Page 1 - - LOC OBJECT CODE ADDR1 ADDR2 STMT - - 1 * - 2 *Testcase IEEE CONVERT FROM/TO FIXED 32 (6), ADD (5), 11 instr total - 3 * ADD tests - Binary Floating Point - 4 * - 5 * - 6 * Tests five addition instructions: - 7 * ADD (extended BFP, RRE) - 8 * ADD (long BFP, RRE) - 9 * ADD (long BFP, RXE) - 10 * ADD (short BFP, RRE) - 11 * ADD (short BFP, RXE) - 12 * - 13 * Also tests the following three conversion instructions - 14 * CONVERT FROM FIXED (32 to short BFP, RRE) - 15 * CONVERT FROM FIXED (32 to long BFP, RRE) - 16 * CONVERT FROM FIXED (32 to extended BFP, RRE) - 17 * CONVERT TO FIXED (32 to short BFP, RRE) - 18 * CONVERT TO FIXED (32 to long BFP, RRE) - 19 * CONVERT TO FIXED (32 to extended BFP, RRE) - 20 * - 21 * Also tests the following floating point support instructions - 22 * LOAD (Short) - 23 * LOAD (Long) - 24 * LOAD ZERO (Long) - 25 * STORE (Short) - 26 * STORE (Long) - 27 * - 28 * Convert integers 1, 2, 4, -2 to each BFP floating point format - 29 * Add first and second pairs together (1 + 2, 4 + -2) in each format - 30 * - 0000000000000000 000000000000057F 31 BFPADDS START 0 - 0000000000000000 0000000000000001 32 R0 EQU 0 - 0000000000000001 0000000000000001 33 R1 EQU 1 - 0000000000000002 0000000000000001 34 R2 EQU 2 - 0000000000000003 0000000000000001 35 R3 EQU 3 - 0000000000000004 0000000000000001 36 R4 EQU 4 - 0000000000000005 0000000000000001 37 R5 EQU 5 - 0000000000000006 0000000000000001 38 R6 EQU 6 - 0000000000000007 0000000000000001 39 R7 EQU 7 - 0000000000000008 0000000000000001 40 R8 EQU 8 - 0000000000000009 0000000000000001 41 R9 EQU 9 - 000000000000000A 0000000000000001 42 R10 EQU 10 - 000000000000000B 0000000000000001 43 R11 EQU 11 - 000000000000000C 0000000000000001 44 R12 EQU 12 - 000000000000000D 0000000000000001 45 R13 EQU 13 - 000000000000000E 0000000000000001 46 R14 EQU 14 - 000000000000000F 0000000000000001 47 R15 EQU 15 -0000000000000000 0000000000000000 48 USING *,0 -0000000000000000 0000000000000000 00000000000001A0 49 ORG BFPADDS+X'1A0' -00000000000001A0 00000001 80000000 50 DC X'0000000180000000',AD(START) z/Arch restart PSW -00000000000001B0 00000000000001B0 00000000000001D0 51 ORG BFPADDS+X'1D0' -00000000000001D0 00020000 00000000 52 DC X'0002000000000000000000000000DEAD' z/Arch pgm chk new PSW - ASMA Ver. 0.2.0 23 Jun 2016 09:49:47 Page 2 - - LOC OBJECT CODE ADDR1 ADDR2 STMT - -00000000000001E0 00000000000001E0 0000000000000200 53 ORG BFPADDS+X'200' - 54 * -0000000000000200 B600 03EC 00000000000003EC 55 START STCTL R0,R0,CTLR0 Store CR0 to enable AFP -0000000000000204 9604 03ED 00000000000003ED 56 OI CTLR0+1,X'04' Turn on AFP bit -0000000000000208 B700 03EC 00000000000003EC 57 LCTL R0,R0,CTLR0 Reload updated CR0 - 58 * - 59 * convert integers to three BFP formats - 60 * -000000000000020C 4120 0004 0000000000000004 61 LA R2,4 Set count of test input values -0000000000000210 4130 0400 0000000000000400 62 LA R3,INTVALS point to start of input values -0000000000000214 4170 0410 0000000000000410 63 LA R7,SHORTBFP Point to start of short BFP input values -0000000000000218 4180 0420 0000000000000420 64 LA R8,LONGBFP Point to start of long BFP input values -000000000000021C 4190 0440 0000000000000440 65 LA R9,EXTBFP Point to start of extended BFP input values -0000000000000220 0DC0 66 BASR R12,0 Set top of loop - 67 * -0000000000000222 5810 3000 0000000000000000 68 L R1,0(0,R3) Get integer test value -0000000000000226 B394 0001 69 CEFBR R0,R1 Cvt Int in GPR1 to float in FPR0 -000000000000022A 7000 7000 0000000000000000 70 STE R0,0(0,R7) Store short BFP -000000000000022E B395 0001 71 CDFBR R0,R1 Cvt Int in GPR1 to float in FPR0 -0000000000000232 6000 8000 0000000000000000 72 STD R0,0(0,R8) Store long BFP -0000000000000236 B396 0001 73 CXFBR R0,R1 Cvt Int in GPR1 to float in FPR0-FPR2 -000000000000023A 6000 9000 0000000000000000 74 STD R0,0(0,R9) Store extended BFP part 1 -000000000000023E 6020 9008 0000000000000008 75 STD R2,8(0,R9) Store extended BFP part 2 -0000000000000242 4130 3004 0000000000000004 76 LA R3,4(0,R3) point to next input values -0000000000000246 4170 7004 0000000000000004 77 LA R7,4(0,R7) Point to next short BFP converted values -000000000000024A 4180 8008 0000000000000008 78 LA R8,8(0,R8) Point to next long BFP converted values -000000000000024E 4190 9010 0000000000000010 79 LA R9,16(0,R9) Point to next extended BFP converted values -0000000000000252 062C 80 BCTR R2,R12 Convert next input value. - 81 * - 82 * Add pairs of values together - 83 * -0000000000000254 4120 0002 0000000000000002 84 LA R2,2 Set count of addition operations -0000000000000258 4130 0500 0000000000000500 85 LA R3,SHORTRES Point to start of short BFP results -000000000000025C 4140 0510 0000000000000510 86 LA R4,LONGRES Point to start of long BFP results -0000000000000260 4150 0530 0000000000000530 87 LA R5,EXTRES Point to start of extended BFP results -0000000000000264 4170 0410 0000000000000410 88 LA R7,SHORTBFP Point to start of short BFP input values -0000000000000268 4180 0420 0000000000000420 89 LA R8,LONGBFP Point to start of long BFP input values -000000000000026C 4190 0440 0000000000000440 90 LA R9,EXTBFP Point to start of extended BFP input values -0000000000000270 0DC0 91 BASR R12,0 Set top of loop - 92 * - 93 * clear residuals from FPR0-1 -0000000000000272 B375 0000 94 ADDLOOP LZDR R0 Zero FPR0 - clear residuals from FPR0, 1 -0000000000000276 B375 0010 95 LZDR R1 Zero FPR1 - 96 * BFP Short addition RXE and RRE -000000000000027A 7800 7000 0000000000000000 97 LE R0,0(0,R7) Get BFP short first of pair -000000000000027E ED00 7004 000A 0000000000000004 98 AEB R0,4(0,R7) Add BFP short second of pair -0000000000000284 7000 3000 0000000000000000 99 STE R0,0(0,R3) Store short BFP result from RXE -0000000000000288 7800 7000 0000000000000000 100 LE R0,0(0,R7) Get BFP short first of pair -000000000000028C 7810 7004 0000000000000004 101 LE R1,4(0,R7) Get BFP short second of pair -0000000000000290 B30A 0001 102 AEBR R0,R1 Add BFP values, result in FPR0 -0000000000000294 7000 3004 0000000000000004 103 STE R0,4(0,R3) Store short BFP from RRE -0000000000000298 4170 7008 0000000000000008 104 LA R7,8(0,R7) Point to next short BFP input pair - ASMA Ver. 0.2.0 23 Jun 2016 09:49:47 Page 3 - - LOC OBJECT CODE ADDR1 ADDR2 STMT - -000000000000029C 4130 3008 0000000000000008 105 LA R3,8(0,R3) Point to next short BFP result pair - 106 * BFP Long addition RXE and RRE -00000000000002A0 6800 8000 0000000000000000 107 LD R0,0(0,R8) Get BFP long first of pair -00000000000002A4 ED00 8008 001A 0000000000000008 108 ADB R0,8(0,R8) Add BFP long second of pair -00000000000002AA 6000 4000 0000000000000000 109 STD R0,0(0,R4) Store long BFP result from RXE -00000000000002AE 6800 8000 0000000000000000 110 LD R0,0(0,R8) Get BFP long first of pair -00000000000002B2 6810 8008 0000000000000008 111 LD R1,8(0,R8) Get BFP long second of pair -00000000000002B6 B31A 0001 112 ADBR R0,R1 Add BFP values, result in FPR0 -00000000000002BA 6000 4008 0000000000000008 113 STD R0,8(0,R4) Store long BFP from RRE -00000000000002BE 4180 8010 0000000000000010 114 LA R8,16(0,R8) Point to next long BFP input pair -00000000000002C2 4140 4010 0000000000000010 115 LA R4,16(0,R4) Point to next long BFP result pair - 116 * BFP Extended addition RRE -00000000000002C6 6800 9000 0000000000000000 117 LD R0,0(0,R9) Get BFP ext. 1st half of first of pair -00000000000002CA 6820 9008 0000000000000008 118 LD R2,8(0,R9) Get BFP ext. 2nd half of first of pair -00000000000002CE 6810 9010 0000000000000010 119 LD R1,16(0,R9) Get BFP ext. 1st half of second of pair -00000000000002D2 6830 9018 0000000000000018 120 LD R3,24(0,R9) Get BFP ext. 2nd half of second of pair -00000000000002D6 B34A 0001 121 AXBR R0,R1 Add BFP values, result in FPR0-FPR2 -00000000000002DA 6000 5000 0000000000000000 122 STD R0,0(0,R5) Store ext. BFP from RRE -00000000000002DE 6020 5008 0000000000000008 123 STD R2,8(0,R5) Store ext. BFP from RRE - 124 * -00000000000002E2 4190 9020 0000000000000020 125 LA R9,32(0,R9) Point to next ext. BFP input pair -00000000000002E6 4150 5010 0000000000000010 126 LA R5,16(0,R5) Point to next ext. BFP result -00000000000002EA 062C 127 BCTR R2,R12 Add next input pair - 128 * - 129 * Convert back to integers - 130 * -00000000000002EC 4120 0002 0000000000000002 131 LA R2,2 Set count of addition operations -00000000000002F0 4170 0500 0000000000000500 132 LA R7,SHORTRES Point to start of short BFP results -00000000000002F4 4180 0510 0000000000000510 133 LA R8,LONGRES Point to start of long BFP results -00000000000002F8 4190 0530 0000000000000530 134 LA R9,EXTRES Point to start of extended BFP results -00000000000002FC 4130 0550 0000000000000550 135 LA R3,ISHBFP Point to start of short BFP Integer results -0000000000000300 4140 0560 0000000000000560 136 LA R4,ILNBFP Point to start of long BFP integer results -0000000000000304 4150 0570 0000000000000570 137 LA R5,IXTBFP Point to start of extended BFP integer results -0000000000000308 0DC0 138 BASR R12,0 Set top of loop - 139 * -000000000000030A B375 0000 140 LZDR R0 Zero FPR0 - 141 * Convert shorts back to integer -000000000000030E 7800 7000 0000000000000000 142 LE R0,0(0,R7) Get BFP short result first of pair -0000000000000312 B398 0000 143 CFEBR R0,R0 Convert to integer in r0 -0000000000000316 5000 3000 0000000000000000 144 ST R0,0(0,R3) Store integer result -000000000000031A 7800 7004 0000000000000004 145 LE R0,4(0,R7) Get BFP short result second of pair -000000000000031E B398 0000 146 CFEBR R0,R0 Convert to integer in r0 -0000000000000322 5000 3004 0000000000000004 147 ST R0,4(0,R3) Store integer result - 148 * -0000000000000326 6800 8000 0000000000000000 149 LD R0,0(0,R8) Get BFP long result first of pair -000000000000032A B399 0000 150 CFDBR R0,R0 Convert to integer in r0 -000000000000032E 5000 4000 0000000000000000 151 ST R0,0(0,R4) Store integer result -0000000000000332 6800 8008 0000000000000008 152 LD R0,8(0,R8) Get BFP long result second of pair -0000000000000336 B399 0000 153 CFDBR R0,R0 Convert to integer in r0 -000000000000033A 5000 4004 0000000000000004 154 ST R0,4(0,R4) Store integer result - 155 * -000000000000033E 6800 9000 0000000000000000 156 LD R0,0(0,R9) Get BFP ext. 1st half of first of pair - ASMA Ver. 0.2.0 23 Jun 2016 09:49:47 Page 4 - - LOC OBJECT CODE ADDR1 ADDR2 STMT - -0000000000000342 6820 9008 0000000000000008 157 LD R2,8(0,R9) Get BFP ext. 2nd half of first of pair -0000000000000346 B39A 0000 158 CFXBR R0,R0 Convert BFP Ext. to Integer-64 -000000000000034A 5000 5000 0000000000000000 159 ST R0,0(0,R5) Store integer result lower word - 160 * -000000000000034E 4170 7008 0000000000000008 161 LA R7,8(0,R7) Point to next short BFP input pair -0000000000000352 4130 3008 0000000000000008 162 LA R3,8(0,R3) Point to next short BFP integer pair -0000000000000356 4180 8010 0000000000000010 163 LA R8,16(0,R8) Point to next long BFP input pair -000000000000035A 4140 4008 0000000000000008 164 LA R4,8(0,R4) Point to next long BFP integer pair -000000000000035E 4190 9010 0000000000000010 165 LA R9,16(0,R9) Point to next ext. BFP input -0000000000000362 4150 5004 0000000000000004 166 LA R5,4(0,R5) Point to next ext. BFP integer - 167 * -0000000000000366 062C 168 BCTR R2,R12 Add next input pair - 169 * -0000000000000368 B2B2 03F0 00000000000003F0 170 LPSWE WAITPSW Load enabled wait PSW - 171 * -000000000000036C 000000000000036C 00000000000003EC 172 ORG BFPADDS+X'3EC' -00000000000003EC 00000000 173 CTLR0 DS F -00000000000003F0 00020000 00000000 174 WAITPSW DC X'00020000000000000000000000000000' Disabled wait state PSW - normal completion -0000000000000400 0000000000000400 0000000000000400 175 ORG BFPADDS+X'400' -0000000000000400 176 INTVALS DS 0F -0000000000000400 00000001 177 DC F'1' -0000000000000404 00000002 178 DC F'2' -0000000000000408 00000004 179 DC F'4' -000000000000040C FFFFFFFE 180 DC F'-2' - 181 * -0000000000000410 00000000 00000000 182 SHORTBFP DS 4F Four short BFP values -0000000000000420 00000000 00000000 183 LONGBFP DS 4D Four long BFP values -0000000000000440 00000000 00000000 184 EXTBFP DS 8D Four extended BPF values - 185 * -0000000000000480 0000000000000480 0000000000000500 186 ORG BFPADDS+X'500' -0000000000000500 00000000 00000000 187 SHORTRES DS 4F Four short BFP results -0000000000000510 00000000 00000000 188 LONGRES DS 4D Four long BFP results -0000000000000530 00000000 00000000 189 EXTRES DS 4D Two extended BFP results - 190 * -0000000000000550 00000000 00000000 191 ISHBFP DS 4F Four short BFP results in 32-bit integer form -0000000000000560 00000000 00000000 192 ILNBFP DS 4F Four long BFP results in 32-bit integer form -0000000000000570 00000000 00000000 193 IXTBFP DS 4F Four extended BPF results in 32-bit integer form - 194 -0000000000000580 195 END - ASMA Ver. 0.2.0 23 Jun 2016 09:49:47 Page 5 - - SYMBOL TYPE VALUE LENGTH DEFN REFERENCES - -ADDLOOP I 000272 4 94 -BFPADDS J 000000 1408 31 49 51 53 172 175 186 -CTLR0 F 0003EC 4 173 55 56 57 -EXTBFP D 000440 8 184 65 90 -EXTRES D 000530 8 189 87 134 -ILNBFP F 000560 4 192 136 -IMAGE 1 000000 1408 0 -INTVALS F 000400 4 176 62 -ISHBFP F 000550 4 191 135 -IXTBFP F 000570 4 193 137 -LONGBFP D 000420 8 183 64 89 -LONGRES D 000510 8 188 86 133 -R0 U 000000 1 32 55 57 69 70 71 72 73 74 94 97 98 99 100 102 103 107 108 - 109 110 112 113 117 121 122 140 142 143 144 145 146 147 149 150 151 - 152 153 154 156 158 159 -R1 U 000001 1 33 68 69 71 73 95 101 102 111 112 119 121 -R10 U 00000A 1 42 -R11 U 00000B 1 43 -R12 U 00000C 1 44 66 80 91 127 138 168 -R13 U 00000D 1 45 -R14 U 00000E 1 46 -R15 U 00000F 1 47 -R2 U 000002 1 34 61 75 80 84 118 123 127 131 157 168 -R3 U 000003 1 35 62 68 76 85 99 103 105 120 135 144 147 162 -R4 U 000004 1 36 86 109 113 115 136 151 154 164 -R5 U 000005 1 37 87 122 123 126 137 159 166 -R6 U 000006 1 38 -R7 U 000007 1 39 63 70 77 88 97 98 100 101 104 132 142 145 161 -R8 U 000008 1 40 64 72 78 89 107 108 110 111 114 133 149 152 163 -R9 U 000009 1 41 65 74 75 79 90 117 118 119 120 125 134 156 157 165 -SHORTBFP F 000410 4 182 63 88 -SHORTRES F 000500 4 187 85 132 -START I 000200 4 55 50 -WAITPSW X 0003F0 16 174 170 - ASMA Ver. 0.2.0 23 Jun 2016 09:49:47 Page 6 - -MACRO DEFN REFERENCES - -No defined macros - ASMA Ver. 0.2.0 23 Jun 2016 09:49:47 Page 7 - - DESC SYMBOL SIZE POS ADDR - -Entry: 0 - -Image IMAGE 1408 000-57F 000-57F - Region 1408 000-57F 000-57F - CSECT BFPADDS 1408 000-57F 000-57F - ASMA Ver. 0.2.0 23 Jun 2016 09:49:47 Page 8 - - STMT FILE NAME - -1 C:\Users\srorso\Documents\GitHub\hyperion\tests\ieee-adds.asm - - -** NO ERRORS FOUND ** - - \ No newline at end of file diff --git a/tests/ieee-adds.tst b/tests/ieee-adds.tst deleted file mode 100644 index 8dcfa0cb3..000000000 --- a/tests/ieee-adds.tst +++ /dev/null @@ -1,95 +0,0 @@ -* -*Testcase ieee-adds.tst: IEEE Add, Convert From/To Fixed -*Message Testcase ieee-adds.tst: IEEE Add, Convert From/To Fixed -*Message ..Includes CONVERT FROM/TO FIXED 32 (6), ADD (5), 11 instr total -* -* ADD tests - Binary Floating Point -* -# -# Tests five addition instructions: -# ADD (extended BFP, RRE) -# ADD (long BFP, RRE) -# ADD (long BFP, RXE) -# ADD (short BFP, RRE) -# ADD (short BFP, RXE) -# -# Also tests the following three conversion instructions -# CONVERT FROM FIXED (32 to short BFP, RRE) -# CONVERT FROM FIXED (32 to long BFP, RRE) -# CONVERT FROM FIXED (32 to extended BFP, RRE) -# CONVERT TO FIXED (32 to short BFP, RRE) -# CONVERT TO FIXED (32 to long BFP, RRE) -# CONVERT TO FIXED (32 to extended BFP, RRE) -# -# Also tests the following floating point support instructions -# LOAD (Short) -# LOAD (Long) -# LOAD ZERO (Long) -# STORE (Short) -# STORE (Long) -# -# Convert integers 1, 2, 4, -2 to each BFP floating point format -# Add first and second pairs together (1 + 2, 4 + -2) in each format -# -sysclear -archmode esame -loadcore "$(testpath)/ieee-adds.core" -runtest .1 - -*Compare -r 410.10 # Inputs converted to BFP short -*Want "CEFBR results 1-4" 3F800000 40000000 40800000 C0000000 - -*Compare -r 420.10 # Inputs converted to BFP long one of two -*Want "CDFBR results 1, 2" 3FF00000 00000000 40000000 00000000 -*Compare -r 430.10 # Inputs converted to BFP long two of two -*Want "CDFBR results 3, 4" 40100000 00000000 C0000000 00000000 - -*Compare -r 440.10 # Inputs converted to BFP ext one of four -*Want "CXFBR result 1" 3FFF0000 00000000 00000000 00000000 -*Compare -r 450.10 # Inputs converted to BFP ext two of four -*Want "CXFBR result 2" 40000000 00000000 00000000 00000000 -*Compare -r 460.10 # Inputs converted to BFP ext three of four -*Want "CXFBR result 3" 40010000 00000000 00000000 00000000 -*Compare -r 470.10 # Inputs converted to BFP ext four of four -*Want "CXFBR result 4" C0000000 00000000 00000000 00000000 - -*Compare -r 500.10 # BFP short sums RXE & RRE -*Want "AEB/AEBR results 1-2" 40400000 40400000 40000000 40000000 - -*Compare -r 510.10 # BFP long sums RXE and RRE result 1 -*Want "ADB/ADBR result 1" 40080000 00000000 40080000 00000000 -*Compare -r 520.10 # BFP long sums RXE and RRE result 2 -*Want "ADB/ADBR result 2" 40000000 00000000 40000000 00000000 - -*Compare -r 530.10 # BFP extended sum RRE result 1 -*Want "AXBR result 1" 40008000 00000000 00000000 00000000 -*Compare -r 540.10 # BFP extended sum RRE result 2 -*Want "AXBR result 2" 40000000 00000000 00000000 00000000 - -*Compare -r 550.10 # Short BFP to Integer results -*Want "CFEBR results 1-4" 00000003 00000003 00000002 00000002 - -*Compare -r 560.10 # Convert long BFP to Integer results -*Want "CFDBR results 1-4" 00000003 00000003 00000002 00000002 - -*Compare -r 570.8 # Convert extended BFP to Integer results -*Want "CFXBR results 1, 2" 00000003 00000002 - - -*Done - diff --git a/tests/ieee-comps.asm b/tests/ieee-comps.asm deleted file mode 100644 index 8901a84c1..000000000 --- a/tests/ieee-comps.asm +++ /dev/null @@ -1,401 +0,0 @@ -* -* For the following tests, the IEEE exception masks in the FPC register are set -* to zero, so no program interruptions. The IEEE status flags are saved and set -* to zero after each test. -* -* 1. COMPARE adjacent pairs of values in the input set (nine values means eight -* comparisons). Save condition code and FPC register IEEE flags byte (byte 1). -* -* 2. COMPARE AND SIGNAL adjacent pairs of values in the input set (nine values -* means eight comparisons). Save condition code and FPC register IEEE flags -* byte (byte 1). -* -* 3. LOAD AND TEST the first eight values in the input set (the nineth value is -* not tested). Save condition code and FPC register IEEE flags byte (byte 1). -* The result from the last LOAD AND TEST is saved to verify conversion of the -* SNaN into a QNaN. -* -* 4. TEST DATA CLASS the first eight values in the input set (the nineth value is -* not tested) using each of two masks specific to the input value. The first -* mask will test true (cc=1) and the second will test false (cc=0). Save the -* condition code; the IEEE flags are not changed by this instruction. -* -* Test data: QNaN, 1, 1, 2, -inf, -SubN, +inf, SNaN, 0. -* Test data class masks: 080, 200, 200, 200, 010, 100, 020, 002. -* -* Expected results in cc/flags format for COMPARE, COMPARE AND SIGNAL, and LOAD AND TEST -* - COMPARE: 3/00 0/00 1/00 2/00 1/00 1/00 3/80 3/80 -* - COMPARE AND SIGNAL: 3/80 0/00 1/00 2/00 1/00 1/00 3/80 3/80 -* - LOAD AND TEST: 3/00 2/00 2/00 2/00 1/00 1/00 2/00 3/80 -* -* Expected results in cc1/cc2 format for TEST DATA CLASS -* - TEST DATA CLASS: 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 -* -* -* Tests 5 COMPARE, 5 COMPARE AND SIGNAL, 3 LOAD AND TEST, and 3 TEST DATA CLASS instructions -* COMPARE (BFP short, RRE) CEBR -* COMPARE (BFP short, RXE) CEB -* COMPARE (BFP long, RRE) CDBR -* COMPARE (BFP long, RXE) CDB -* COMPARE (BFP extended, RRE) CXBR -* COMPARE AND SIGNAL (BFP short, RRE) KEBR -* COMPARE AND SIGNAL (BFP short, RXE) KEB -* COMPARE AND SIGNAL (BFP long, RRE) KDBR -* COMPARE AND SIGNAL (BFP long, RXE) KDB -* COMPARE AND SIGNAL (BFP extended, RRE) KXBR -* LOAD AND TEST (BFP short, RRE) LTEBR -* LOAD AND TEST (BFP long, RRE) LTDBR -* LOAD AND TEST (BFP extended, RRE) LTXBR -* TEST DATA CLASS (BFP short, RRE) LTEBR -* TEST DATA CLASS (BFP long, RRE) LTDBR -* TEST DATA CLASS (BFP extended, RRE) LTXBR -* -* -* Also tests the following floating point support instructions -* EXTRACT FPC -* LOAD (Short) -* LOAD (Long) -* LOAD ZERO (Long) -* STORE (Short) -* STORE (Long) -* SET FPC -* -BFPCOMPS START 0 -R0 EQU 0 -R1 EQU 1 -R2 EQU 2 -R3 EQU 3 -R4 EQU 4 -R5 EQU 5 -R6 EQU 6 -R7 EQU 7 -R8 EQU 8 -R9 EQU 9 -R10 EQU 10 -R11 EQU 11 -R12 EQU 12 -R13 EQU 13 -R14 EQU 14 -R15 EQU 15 - USING *,0 - ORG BFPCOMPS+X'1A0' - DC X'0000000180000000',AD(STARTTST) z/Arch restart PSW - ORG BFPCOMPS+X'1D0' - DC X'0002000000000000000000000000DEAD' z/Arch pgm chk new PSW - ORG BFPCOMPS+X'200' -* -STARTTST STCTL R0,R0,CTLR0 Store CR0 to enable AFP - OI CTLR0+1,X'04' Turn on AFP bit - LCTL R0,R0,CTLR0 Reload updated CR0 - EFPC R0 Save reference copy of FPC - STG R11,SAVER11 Save R11 in case we're on z/CMS - BAS R12,TESTCOMP Perform compares and tests - LG R11,SAVER11 Restore R11 in case we're on z/CMS - LTR R14,R14 Any value in R14? - BNZR R14 ..yes, running on z/CMS, take graceful exit - LPSWE WAITPSW ..no, on bare iron, load disabled wait PSW -* -CTLR0 DS F Control register 0 (bit45 AFP control) -SAVER11 DS D Savearea for R11, needed when on z/CMS -WAITPSW DC X'00020000000000000000000000000000' Disabled PSW - normal completion -* -* BFP Compares, Load and Test, and Test Data Class main processing loop. -* All tests are performed in each iteration of the loop. -* -TESTCOMP DS 0H Process one test case - LA R2,8 Set count of multiplication operations - LA R3,RESULTCC Point cc table, 8 per precision per instruction - LA R4,RESULTFL Point IEEE flags table, 8 per precision per instruction - LA R7,SHORTBFP Point to start of short BFP input values - LA R8,TDCMASKS Point to start of masks for TDC instruction - LA R9,LONGBFP Point to start of long BFP input values - LA R10,EXTDBFP Point to start of extended BFP input values - BASR R13,0 Set top of loop -* - BAS R11,SHORTS Test shorts: CEB/CEBR, KEB/KEBR, LTEBR, and TCEB - BAS R11,LONGS Test longs: CDB/CDBR, KDB/KDBR, LTDBR, and TCDB - BAS R11,EXTDS Test extendeds: CXBR, KXBR, LTXBR, and TCXB - LA R3,1(0,R3) point to next cc table entry - LA R4,1(0,R4) Point to next mask table entry - LA R7,4(0,R7) Point to next short BFP input value - LA R8,4(0,R8) Point to next TDCxx mask pair - LA R9,8(0,R9) Point to next long BFP input value - LA R10,16(0,R10) Point to extended long BFP input value - BCTR R2,R13 Loop through all test cases -* - BR R12 Tests done, return to mainline -* -* Next iteration of short BFP instruction testing; clear residuals from FP registers -* -SHORTS LZDR R0 Zero FPR0 - LZDR R1 Zero FPR1 - LZDR R13 Zero FPR13 - LE R0,0(0,R7) Get BFP short first value - LE R13,4(0,R7) Get BFP short second value - LER R1,R0 Copy second value for CEBR RRE -* Compare value pair using short RXE - SFPC R0 Load reference copy of FPC - CEB R0,4(0,R7) Compare first and second values - IPM R1 Get condition code and program mask - SRL R1,28 Isolate CC in low order byte - STC R1,0(0,R3) Save condition code in results table - EFPC R1 Get result FPC - STCM R1,B'0100',0(R4) Store IEEE Flags in results table -* Compare value pair using short RRE - LFPC R0 Load reference copy of FPC - CEBR R1,R13 Compare first and second values - IPM R1 Get condition code and program mask - SRL R1,28 Isolate CC in low order byte - STC R1,8(0,R3) Save condition code in results table - EFPC R1 Get result FPC - STCM R1,B'0100',8(R4) Store IEEE Flags in results table -* Compare and Signal value pair using short RXE - SFPC R0 Load reference copy of FPC - KEB R0,4(0,R7) Compare first and second values, signal if NaN - IPM R1 Get condition code and program mask - SRL R1,28 Isolate CC in low order byte - STC R1,40(0,R3) Save condition code in results table - EFPC R1 Get result FPC - STCM R1,B'0100',40(R4) Store IEEE Flags in results table -* Compare and Signal value pair using short RRE - LFPC R0 Load reference copy of FPC - KEBR R1,R13 Compare first and second values, signal if NaN - IPM R1 Get condition code and program mask - SRL R1,28 Isolate CC in low order byte - STC R1,48(0,R3) Save condition code in results table - EFPC R1 Get result FPC - STCM R1,B'0100',48(R4) Store IEEE Flags in results table -* Load and Test value short RRE - LFPC R0 Load reference copy of FPC - LTEBR R12,R0 Load and test - STE R12,LTEBRTST Save tested value for SNaN->QNaN test (last iteration) - IPM R1 Get condition code and program mask - SRL R1,28 Isolate CC in low order byte - STC R1,80(0,R3) Save condition code in results table - EFPC R1 Get result FPC - STCM R1,B'0100',80(R4) Store IEEE Flags in results table -* Test Data Class short RRE - LFPC R0 Load reference copy of FPC - LH R1,0(0,R8) Get test data class mask value for True - TCEB R0,0(0,R1) Test Data Class, set condition code - IPM R1 Get condition code and program mask - SRL R1,28 Isolate CC in low order byte - STC R1,104(0,R3) Save condition code in results table - LH R1,2(0,R8) Get test data class mask value for False - TCEB R0,0(0,R1) Test Data Class, set condition code - IPM R1 Get condition code and program mask - SRL R1,28 Isolate CC in low order byte - STC R1,112(0,R3) Save condition code in results table -* - BR R11 Tests done, return to loop control -* -* Next iteration of long BFP instruction testing -* -LONGS LD R0,0(0,R9) Load BFP long first value - LD R13,8(0,R9) Load BFP long second value - LDR R1,R0 Copy second value for CDBR RRE -* Compare value pair using long RXE - SFPC R0 Load reference copy of FPC - CDB R0,8(0,R9) Compare first and second values - IPM R1 Get condition code and program mask - SRL R1,28 Isolate CC in low order byte - STC R1,16(0,R3) Save condition code in results table - EFPC R1 Get result FPC - STCM R1,B'0100',16(R4) Store IEEE Flags in results table -* Compare value pair using long RRE - LFPC R0 Load reference copy of FPC - CDBR R1,R13 Compare first and second values - IPM R1 Get condition code and program mask - SRL R1,28 Isolate CC in low order byte - STC R1,24(0,R3) Save condition code in results table - EFPC R1 Get result FPC - STCM R1,B'0100',24(R4) Store IEEE Flags in results table -* Compare and Signal value pair using long RXE - SFPC R0 Load reference copy of FPC - KDB R0,8(0,R9) Compare first and second values - IPM R1 Get condition code and program mask - SRL R1,28 Isolate CC in low order byte - STC R1,56(0,R3) Save condition code in results table - EFPC R1 Get result FPC - STCM R1,B'0100',56(R4) Store IEEE Flags in results table -* Compare and Signal value pair using long RRE - LFPC R0 Load reference copy of FPC - KDBR R1,R13 Generate RRE s*s=s product - IPM R1 Get condition code and program mask - SRL R1,28 Isolate CC in low order byte - STC R1,64(0,R3) Save condition code in results table - EFPC R1 Get result FPC - STCM R1,B'0100',64(R4) Store IEEE Flags in results table -* Load and Test value long RRE - LFPC R0 Load reference copy of FPC - LTDBR R12,R0 Load and test - STD R12,LTDBRTST Save tested value for SNaN->QNaN test (last iteration) - IPM R1 Get condition code and program mask - SRL R1,28 Isolate CC in low order byte - STC R1,88(0,R3) Save condition code in results table - EFPC R1 Get result FPC - STCM R1,B'0100',88(R4) Store IEEE Flags in results table -* Test Data Class long RRE - LFPC R0 Load reference copy of FPC - LH R1,0(0,R8) Get test data class mask value for True - TCDB R0,0(0,R1) Test Data Class, set condition code - IPM R1 Get condition code and program mask - SRL R1,28 Isolate CC in low order byte - STC R1,120(0,R3) Save condition code in results table - LH R1,2(0,R8) Get test data class mask value for False - TCDB R0,0(0,R1) Test Data Class, set condition code - IPM R1 Get condition code and program mask - SRL R1,28 Isolate CC in low order byte - STC R1,128(0,R3) Save condition code in results table -* - BR R11 Tests done, return to loop control -* -* Next iteration of long BFP instruction testing -* -EXTDS LD R0,0(0,R10) Load BFP extended first value part 1 - LD R2,8(0,R10) Load BFP extended second value part 1 - LD R13,16(0,R10) Load BFP extended first value part 1 - LD R15,24(0,R10) Load BFP extended second value part 1 - LXR R1,R0 Copy second value for CDBR RRE -* Compare value pair using extended RRE - LFPC R0 Load reference copy of FPC - CXBR R1,R13 Compare first and second values - IPM R1 Get condition code and program mask - SRL R1,28 Isolate CC in low order byte - STC R1,32(0,R3) Save condition code in results table - EFPC R1 Get result FPC - STCM R1,B'0100',32(R4) Store IEEE Flags in results table -* Compare and Signal value pair using extended RRE - LFPC R0 Load reference copy of FPC - KXBR R1,R13 Generate RRE s*s=s product - IPM R1 Get condition code and program mask - SRL R1,28 Isolate CC in low order byte - STC R1,72(0,R3) Save condition code in results table - EFPC R1 Get result FPC - STCM R1,B'0100',72(R4) Store IEEE Flags in results table -* Load and Test value extended RRE - LFPC R0 Load reference copy of FPC - LTXBR R12,R0 Load and test - STD R12,LTXBRTST Save tested value for SNaN->QNaN test (last iteration) -* need 2nd half of store - IPM R1 Get condition code and program mask - SRL R1,28 Isolate CC in low order byte - STC R1,96(0,R3) Save condition code in results table - EFPC R1 Get result FPC - STCM R1,B'0100',96(R4) Store IEEE Flags in results table -* Test Data Class extended RRE - LFPC R0 Load reference copy of FPC - LH R1,0(0,R8) Get test data class mask value for True - TCXB R0,0(0,R1) Test Data Class, set condition code - IPM R1 Get condition code and program mask - SRL R1,28 Isolate CC in low order byte - STC R1,136(0,R3) Save condition code in results table - LH R1,2(0,R8) Get test data class mask value for False - TCXB R0,0(0,R1) Test Data Class, set condition code - IPM R1 Get condition code and program mask - SRL R1,28 Isolate CC in low order byte - STC R1,144(0,R3) Save condition code in results table -* - BR R11 Tests done, return to loop control -* -* Short BFP Input values. QNaN, 1, 1, 2, -inf, -2, +inf, SNaN, 0. -* -SHORTBFP DS 0F Ensure fullword alignment for input table - DC X'FFC00000' -QNaN - DC X'3F800000' 1 - DC X'3F800000' 1 - DC X'40000000' 2 - DC X'FF800000' -infinity - DC X'807FFFFF' -subnormal (maximum magnitude) - DC X'7F800000' +infinity - DC X'7F810000' +SNaN - DC X'00000000' 0 -* -* Long BFP Input values. QNaN, 1, 1, 2, -inf, -2, +inf, SNaN, 0. -* -LONGBFP DS 0D - DC X'FFF8000000000000' -QNaN - DC X'3FF0000000000000' 1 - DC X'3FF0000000000000' 1 - DC X'4000000000000000' 2 - DC X'FFF0000000000000' -infinity - DC X'800FFFFFFFFFFFFF' -subnormal (maximum magnitude) - DC X'7FF0000000000000' +infinity - DC X'7FF0100000000000' +SNaN - DC X'0000000000000000' 0 -* -* Extended BFP Input values. QNaN, 1, 1, 2, -inf, -2, +inf, SNaN, 0. -* -EXTDBFP DS 0D - DC X'FFFF8000000000000000000000000000' -QNaN - DC X'3FFF0000000000000000000000000000' 1 - DC X'3FFF0000000000000000000000000000' 1 - DC X'40000000000000000000000000000000' 2 - DC X'FFFF0000000000000000000000000000' -infinity - DC X'8000FFFFFFFFFFFFFFFFFFFFFFFFFFFF' -subnormal (maximum magnitude) - DC X'7FFF0000000000000000000000000000' +infinity - DC X'7FFF0100000000000000000000000000' +SNaN - DC X'00000000000000000000000000000000' 0 -* -* Test data class masks -* Bit meanings are: 0 0 0 0 | +z -z +norm -norm || +subn -sub +inf -inf | +QNaN -QNaN +SNaN -SNaN -* -TDCMASKS DS 0F - DC X'00040000' 0 0 0 0 | 0 0 0 0 || 0 0 0 0 | 0 1 0 0 -QNaN - DC X'02000000' 0 0 0 0 | 0 0 1 0 || 0 0 0 0 | 0 0 0 0 +1 - DC X'02000000' 0 0 0 0 | 0 0 1 0 || 0 0 0 0 | 0 0 0 0 +1 - DC X'02000000' 0 0 0 0 | 0 0 1 0 || 0 0 0 0 | 0 0 0 0 +2 - DC X'00100000' 0 0 0 0 | 0 0 0 0 || 0 0 0 1 | 0 0 0 0 -inf - DC X'00400000' 0 0 0 0 | 0 0 0 0 || 0 1 0 0 | 0 0 0 0 -2 - DC X'00200000' 0 0 0 0 | 0 0 0 0 || 0 0 1 0 | 0 0 0 0 +inf - DC X'00020000' 0 0 0 0 | 0 0 0 0 || 0 0 0 0 | 0 0 2 0 +SNaN - - ORG BFPCOMPS+X'700' -RESULTCC DS 19D 8 Condition codes from each of 19 instructions -* ( +0) COMPARE short RXE results -* ( +8) COMPARE short RRE results -* ( +16) COMPARE long RXE results -* ( +24) COMPARE long RRE results -* ( +32) COMPARE extended RRE result -* -* ( +40) COMPARE AND SIGNAL short RXE results -* ( +48) COMPARE AND SIGNAL short RRE results -* ( +56) COMPARE AND SIGNAL long RXE results -* ( +64) COMPARE AND SIGNAL long RRE results -* ( +72) COMPARE AND SIGNAL extended RRE results -* -* ( +80) LOAD AND TEST short RRE results -* ( +88) LOAD AND TEST long RRE results -* ( +96) LOAD AND TEST extended RRE results -* -* (+104) TEST DATA CLASS short RRE results (True results) -* (+112) TEST DATA CLASS short RRE results (False results) -* (+120) TEST DATA CLASS long RRE results (True results) -* (+128) TEST DATA CLASS long RRE results (False results) -* (+136) TEST DATA CLASS extended RRE results (True results) -* (+144) TEST DATA CLASS extended RRE results (False results) -* - ORG BFPCOMPS+X'800' -RESULTFL DS 13D 8 IEEE flag bytes from each of 13 instructions -* (TEST DATA CLASS does not set IEEE flags) -* ( +0) COMPARE short RXE results -* ( +8) COMPARE short RRE results -* ( +16) COMPARE long RXE results -* ( +24) COMPARE long RRE results -* ( +32) COMPARE extended RRE result -* -* ( +40) COMPARE AND SIGNAL short RXE results -* ( +48) COMPARE AND SIGNAL short RRE results -* ( +56) COMPARE AND SIGNAL long RXE results -* ( +64) COMPARE AND SIGNAL long RRE results -* ( +72) COMPARE AND SIGNAL extended RRE results -* -* ( +80) LOAD AND TEST short RRE results -* ( +88) LOAD AND TEST long RRE results -* ( +96) LOAD AND TEST extended RRE results -* - ORG BFPCOMPS+X'900' -LTXBRTST DS 2D LOAD AND TEST Extended result (to test conversion of SNaN into QNaN) -LTDBRTST DS D LOAD AND TEST Long result (to test conversion of SNaN into QNaN) -LTEBRTST DS F LOAD AND TEST Short result (to test conversion of SNaN into QNaN) - END \ No newline at end of file diff --git a/tests/ieee-comps.core b/tests/ieee-comps.core deleted file mode 100644 index 6a473bb67..000000000 Binary files a/tests/ieee-comps.core and /dev/null differ diff --git a/tests/ieee-comps.list b/tests/ieee-comps.list deleted file mode 100644 index 5afeb8b57..000000000 --- a/tests/ieee-comps.list +++ /dev/null @@ -1,505 +0,0 @@ -ASMA Ver. 0.2.0 23 Jun 2016 09:49:48 Page 1 - - LOC OBJECT CODE ADDR1 ADDR2 STMT - - 1 * - 2 * For the following tests, the IEEE exception masks in the FPC register are set - 3 * to zero, so no program interruptions. The IEEE status flags are saved and set - 4 * to zero after each test. - 5 * - 6 * 1. COMPARE adjacent pairs of values in the input set (nine values means eight - 7 * comparisons). Save condition code and FPC register IEEE flags byte (byte 1). - 8 * - 9 * 2. COMPARE AND SIGNAL adjacent pairs of values in the input set (nine values - 10 * means eight comparisons). Save condition code and FPC register IEEE flags - 11 * byte (byte 1). - 12 * - 13 * 3. LOAD AND TEST the first eight values in the input set (the nineth value is - 14 * not tested). Save condition code and FPC register IEEE flags byte (byte 1). - 15 * The result from the last LOAD AND TEST is saved to verify conversion of the - 16 * SNaN into a QNaN. - 17 * - 18 * 4. TEST DATA CLASS the first eight values in the input set (the nineth value is - 19 * not tested) using each of two masks specific to the input value. The first - 20 * mask will test true (cc=1) and the second will test false (cc=0). Save the - 21 * condition code; the IEEE flags are not changed by this instruction. - 22 * - 23 * Test data: QNaN, 1, 1, 2, -inf, -SubN, +inf, SNaN, 0. - 24 * Test data class masks: 080, 200, 200, 200, 010, 100, 020, 002. - 25 * - 26 * Expected results in cc/flags format for COMPARE, COMPARE AND SIGNAL, and LOAD AND TEST - 27 * - COMPARE: 3/00 0/00 1/00 2/00 1/00 1/00 3/80 3/80 - 28 * - COMPARE AND SIGNAL: 3/80 0/00 1/00 2/00 1/00 1/00 3/80 3/80 - 29 * - LOAD AND TEST: 3/00 2/00 2/00 2/00 1/00 1/00 2/00 3/80 - 30 * - 31 * Expected results in cc1/cc2 format for TEST DATA CLASS - 32 * - TEST DATA CLASS: 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 - 33 * - 34 * - 35 * Tests 5 COMPARE, 5 COMPARE AND SIGNAL, 3 LOAD AND TEST, and 3 TEST DATA CLASS instructions - 36 * COMPARE (BFP short, RRE) CEBR - 37 * COMPARE (BFP short, RXE) CEB - 38 * COMPARE (BFP long, RRE) CDBR - 39 * COMPARE (BFP long, RXE) CDB - 40 * COMPARE (BFP extended, RRE) CXBR - 41 * COMPARE AND SIGNAL (BFP short, RRE) KEBR - 42 * COMPARE AND SIGNAL (BFP short, RXE) KEB - 43 * COMPARE AND SIGNAL (BFP long, RRE) KDBR - 44 * COMPARE AND SIGNAL (BFP long, RXE) KDB - 45 * COMPARE AND SIGNAL (BFP extended, RRE) KXBR - 46 * LOAD AND TEST (BFP short, RRE) LTEBR - 47 * LOAD AND TEST (BFP long, RRE) LTDBR - 48 * LOAD AND TEST (BFP extended, RRE) LTXBR - 49 * TEST DATA CLASS (BFP short, RRE) LTEBR - 50 * TEST DATA CLASS (BFP long, RRE) LTDBR - 51 * TEST DATA CLASS (BFP extended, RRE) LTXBR - 52 * - ASMA Ver. 0.2.0 23 Jun 2016 09:49:48 Page 2 - - LOC OBJECT CODE ADDR1 ADDR2 STMT - - 53 * - 54 * Also tests the following floating point support instructions - 55 * EXTRACT FPC - 56 * LOAD (Short) - 57 * LOAD (Long) - 58 * LOAD ZERO (Long) - 59 * STORE (Short) - 60 * STORE (Long) - 61 * SET FPC - 62 * - 0000000000000000 000000000000091B 63 BFPCOMPS START 0 - 0000000000000000 0000000000000001 64 R0 EQU 0 - 0000000000000001 0000000000000001 65 R1 EQU 1 - 0000000000000002 0000000000000001 66 R2 EQU 2 - 0000000000000003 0000000000000001 67 R3 EQU 3 - 0000000000000004 0000000000000001 68 R4 EQU 4 - 0000000000000005 0000000000000001 69 R5 EQU 5 - 0000000000000006 0000000000000001 70 R6 EQU 6 - 0000000000000007 0000000000000001 71 R7 EQU 7 - 0000000000000008 0000000000000001 72 R8 EQU 8 - 0000000000000009 0000000000000001 73 R9 EQU 9 - 000000000000000A 0000000000000001 74 R10 EQU 10 - 000000000000000B 0000000000000001 75 R11 EQU 11 - 000000000000000C 0000000000000001 76 R12 EQU 12 - 000000000000000D 0000000000000001 77 R13 EQU 13 - 000000000000000E 0000000000000001 78 R14 EQU 14 - 000000000000000F 0000000000000001 79 R15 EQU 15 -0000000000000000 0000000000000000 80 USING *,0 -0000000000000000 0000000000000000 00000000000001A0 81 ORG BFPCOMPS+X'1A0' -00000000000001A0 00000001 80000000 82 DC X'0000000180000000',AD(STARTTST) z/Arch restart PSW -00000000000001B0 00000000000001B0 00000000000001D0 83 ORG BFPCOMPS+X'1D0' -00000000000001D0 00020000 00000000 84 DC X'0002000000000000000000000000DEAD' z/Arch pgm chk new PSW -00000000000001E0 00000000000001E0 0000000000000200 85 ORG BFPCOMPS+X'200' - 86 * -0000000000000200 B600 0228 0000000000000228 87 STARTTST STCTL R0,R0,CTLR0 Store CR0 to enable AFP -0000000000000204 9604 0229 0000000000000229 88 OI CTLR0+1,X'04' Turn on AFP bit -0000000000000208 B700 0228 0000000000000228 89 LCTL R0,R0,CTLR0 Reload updated CR0 -000000000000020C B38C 0000 90 EFPC R0 Save reference copy of FPC -0000000000000210 E3B0 0230 0024 0000000000000230 91 STG R11,SAVER11 Save R11 in case we're on z/CMS -0000000000000216 4DC0 0248 0000000000000248 92 BAS R12,TESTCOMP Perform compares and tests -000000000000021A E3B0 0230 0004 0000000000000230 93 LG R11,SAVER11 Restore R11 in case we're on z/CMS -0000000000000220 12EE 94 LTR R14,R14 Any value in R14? -0000000000000222 077E 95 BNZR R14 ..yes, running on z/CMS, take graceful exit -0000000000000224 B2B2 0238 0000000000000238 96 LPSWE WAITPSW ..no, on bare iron, load disabled wait PSW - 97 * -0000000000000228 00000000 98 CTLR0 DS F Control register 0 (bit45 AFP control) -0000000000000230 00000000 00000000 99 SAVER11 DS D Savearea for R11, needed when on z/CMS -0000000000000238 00020000 00000000 100 WAITPSW DC X'00020000000000000000000000000000' Disabled PSW - normal completion - 101 * - 102 * BFP Compares, Load and Test, and Test Data Class main processing loop. - 103 * All tests are performed in each iteration of the loop. - 104 * - ASMA Ver. 0.2.0 23 Jun 2016 09:49:48 Page 3 - - LOC OBJECT CODE ADDR1 ADDR2 STMT - -0000000000000248 105 TESTCOMP DS 0H Process one test case -0000000000000248 4120 0008 0000000000000008 106 LA R2,8 Set count of multiplication operations -000000000000024C 4130 0700 0000000000000700 107 LA R3,RESULTCC Point cc table, 8 per precision per instruction -0000000000000250 4140 0800 0000000000000800 108 LA R4,RESULTFL Point IEEE flags table, 8 per precision per instruction -0000000000000254 4170 04D8 00000000000004D8 109 LA R7,SHORTBFP Point to start of short BFP input values -0000000000000258 4180 05D8 00000000000005D8 110 LA R8,TDCMASKS Point to start of masks for TDC instruction -000000000000025C 4190 0500 0000000000000500 111 LA R9,LONGBFP Point to start of long BFP input values -0000000000000260 41A0 0548 0000000000000548 112 LA R10,EXTDBFP Point to start of extended BFP input values -0000000000000264 0DD0 113 BASR R13,0 Set top of loop - 114 * -0000000000000266 4DB0 028E 000000000000028E 115 BAS R11,SHORTS Test shorts: CEB/CEBR, KEB/KEBR, LTEBR, and TCEB -000000000000026A 4DB0 036A 000000000000036A 116 BAS R11,LONGS Test longs: CDB/CDBR, KDB/KDBR, LTDBR, and TCDB -000000000000026E 4DB0 043A 000000000000043A 117 BAS R11,EXTDS Test extendeds: CXBR, KXBR, LTXBR, and TCXB -0000000000000272 4130 3001 0000000000000001 118 LA R3,1(0,R3) point to next cc table entry -0000000000000276 4140 4001 0000000000000001 119 LA R4,1(0,R4) Point to next mask table entry -000000000000027A 4170 7004 0000000000000004 120 LA R7,4(0,R7) Point to next short BFP input value -000000000000027E 4180 8004 0000000000000004 121 LA R8,4(0,R8) Point to next TDCxx mask pair -0000000000000282 4190 9008 0000000000000008 122 LA R9,8(0,R9) Point to next long BFP input value -0000000000000286 41A0 A010 0000000000000010 123 LA R10,16(0,R10) Point to extended long BFP input value -000000000000028A 062D 124 BCTR R2,R13 Loop through all test cases - 125 * -000000000000028C 07FC 126 BR R12 Tests done, return to mainline - 127 * - 128 * Next iteration of short BFP instruction testing; clear residuals from FP registers - 129 * -000000000000028E B375 0000 130 SHORTS LZDR R0 Zero FPR0 -0000000000000292 B375 0010 131 LZDR R1 Zero FPR1 -0000000000000296 B375 00D0 132 LZDR R13 Zero FPR13 -000000000000029A 7800 7000 0000000000000000 133 LE R0,0(0,R7) Get BFP short first value -000000000000029E 78D0 7004 0000000000000004 134 LE R13,4(0,R7) Get BFP short second value -00000000000002A2 3810 135 LER R1,R0 Copy second value for CEBR RRE - 136 * Compare value pair using short RXE -00000000000002A4 B384 0000 137 SFPC R0 Load reference copy of FPC -00000000000002A8 ED00 7004 0009 0000000000000004 138 CEB R0,4(0,R7) Compare first and second values -00000000000002AE B222 0010 139 IPM R1 Get condition code and program mask -00000000000002B2 8810 001C 000000000000001C 140 SRL R1,28 Isolate CC in low order byte -00000000000002B6 4210 3000 0000000000000000 141 STC R1,0(0,R3) Save condition code in results table -00000000000002BA B38C 0010 142 EFPC R1 Get result FPC -00000000000002BE BE14 4000 0000000000000000 143 STCM R1,B'0100',0(R4) Store IEEE Flags in results table - 144 * Compare value pair using short RRE -00000000000002C2 B29D 0000 0000000000000000 145 LFPC R0 Load reference copy of FPC -00000000000002C6 B309 001D 146 CEBR R1,R13 Compare first and second values -00000000000002CA B222 0010 147 IPM R1 Get condition code and program mask -00000000000002CE 8810 001C 000000000000001C 148 SRL R1,28 Isolate CC in low order byte -00000000000002D2 4210 3008 0000000000000008 149 STC R1,8(0,R3) Save condition code in results table -00000000000002D6 B38C 0010 150 EFPC R1 Get result FPC -00000000000002DA BE14 4008 0000000000000008 151 STCM R1,B'0100',8(R4) Store IEEE Flags in results table - 152 * Compare and Signal value pair using short RXE -00000000000002DE B384 0000 153 SFPC R0 Load reference copy of FPC -00000000000002E2 ED00 7004 0008 0000000000000004 154 KEB R0,4(0,R7) Compare first and second values, signal if NaN -00000000000002E8 B222 0010 155 IPM R1 Get condition code and program mask -00000000000002EC 8810 001C 000000000000001C 156 SRL R1,28 Isolate CC in low order byte - ASMA Ver. 0.2.0 23 Jun 2016 09:49:48 Page 4 - - LOC OBJECT CODE ADDR1 ADDR2 STMT - -00000000000002F0 4210 3028 0000000000000028 157 STC R1,40(0,R3) Save condition code in results table -00000000000002F4 B38C 0010 158 EFPC R1 Get result FPC -00000000000002F8 BE14 4028 0000000000000028 159 STCM R1,B'0100',40(R4) Store IEEE Flags in results table - 160 * Compare and Signal value pair using short RRE -00000000000002FC B29D 0000 0000000000000000 161 LFPC R0 Load reference copy of FPC -0000000000000300 B308 001D 162 KEBR R1,R13 Compare first and second values, signal if NaN -0000000000000304 B222 0010 163 IPM R1 Get condition code and program mask -0000000000000308 8810 001C 000000000000001C 164 SRL R1,28 Isolate CC in low order byte -000000000000030C 4210 3030 0000000000000030 165 STC R1,48(0,R3) Save condition code in results table -0000000000000310 B38C 0010 166 EFPC R1 Get result FPC -0000000000000314 BE14 4030 0000000000000030 167 STCM R1,B'0100',48(R4) Store IEEE Flags in results table - 168 * Load and Test value short RRE -0000000000000318 B29D 0000 0000000000000000 169 LFPC R0 Load reference copy of FPC -000000000000031C B302 00C0 170 LTEBR R12,R0 Load and test -0000000000000320 70C0 0918 0000000000000918 171 STE R12,LTEBRTST Save tested value for SNaN->QNaN test (last iteration) -0000000000000324 B222 0010 172 IPM R1 Get condition code and program mask -0000000000000328 8810 001C 000000000000001C 173 SRL R1,28 Isolate CC in low order byte -000000000000032C 4210 3050 0000000000000050 174 STC R1,80(0,R3) Save condition code in results table -0000000000000330 B38C 0010 175 EFPC R1 Get result FPC -0000000000000334 BE14 4050 0000000000000050 176 STCM R1,B'0100',80(R4) Store IEEE Flags in results table - 177 * Test Data Class short RRE -0000000000000338 B29D 0000 0000000000000000 178 LFPC R0 Load reference copy of FPC -000000000000033C 4810 8000 0000000000000000 179 LH R1,0(0,R8) Get test data class mask value for True -0000000000000340 ED00 1000 0010 0000000000000000 180 TCEB R0,0(0,R1) Test Data Class, set condition code -0000000000000346 B222 0010 181 IPM R1 Get condition code and program mask -000000000000034A 8810 001C 000000000000001C 182 SRL R1,28 Isolate CC in low order byte -000000000000034E 4210 3068 0000000000000068 183 STC R1,104(0,R3) Save condition code in results table -0000000000000352 4810 8002 0000000000000002 184 LH R1,2(0,R8) Get test data class mask value for False -0000000000000356 ED00 1000 0010 0000000000000000 185 TCEB R0,0(0,R1) Test Data Class, set condition code -000000000000035C B222 0010 186 IPM R1 Get condition code and program mask -0000000000000360 8810 001C 000000000000001C 187 SRL R1,28 Isolate CC in low order byte -0000000000000364 4210 3070 0000000000000070 188 STC R1,112(0,R3) Save condition code in results table - 189 * -0000000000000368 07FB 190 BR R11 Tests done, return to loop control - 191 * - 192 * Next iteration of long BFP instruction testing - 193 * -000000000000036A 6800 9000 0000000000000000 194 LONGS LD R0,0(0,R9) Load BFP long first value -000000000000036E 68D0 9008 0000000000000008 195 LD R13,8(0,R9) Load BFP long second value -0000000000000372 2810 196 LDR R1,R0 Copy second value for CDBR RRE - 197 * Compare value pair using long RXE -0000000000000374 B384 0000 198 SFPC R0 Load reference copy of FPC -0000000000000378 ED00 9008 0019 0000000000000008 199 CDB R0,8(0,R9) Compare first and second values -000000000000037E B222 0010 200 IPM R1 Get condition code and program mask -0000000000000382 8810 001C 000000000000001C 201 SRL R1,28 Isolate CC in low order byte -0000000000000386 4210 3010 0000000000000010 202 STC R1,16(0,R3) Save condition code in results table -000000000000038A B38C 0010 203 EFPC R1 Get result FPC -000000000000038E BE14 4010 0000000000000010 204 STCM R1,B'0100',16(R4) Store IEEE Flags in results table - 205 * Compare value pair using long RRE -0000000000000392 B29D 0000 0000000000000000 206 LFPC R0 Load reference copy of FPC -0000000000000396 B319 001D 207 CDBR R1,R13 Compare first and second values -000000000000039A B222 0010 208 IPM R1 Get condition code and program mask - ASMA Ver. 0.2.0 23 Jun 2016 09:49:48 Page 5 - - LOC OBJECT CODE ADDR1 ADDR2 STMT - -000000000000039E 8810 001C 000000000000001C 209 SRL R1,28 Isolate CC in low order byte -00000000000003A2 4210 3018 0000000000000018 210 STC R1,24(0,R3) Save condition code in results table -00000000000003A6 B38C 0010 211 EFPC R1 Get result FPC -00000000000003AA BE14 4018 0000000000000018 212 STCM R1,B'0100',24(R4) Store IEEE Flags in results table - 213 * Compare and Signal value pair using long RXE -00000000000003AE B384 0000 214 SFPC R0 Load reference copy of FPC -00000000000003B2 ED00 9008 0018 0000000000000008 215 KDB R0,8(0,R9) Compare first and second values -00000000000003B8 B222 0010 216 IPM R1 Get condition code and program mask -00000000000003BC 8810 001C 000000000000001C 217 SRL R1,28 Isolate CC in low order byte -00000000000003C0 4210 3038 0000000000000038 218 STC R1,56(0,R3) Save condition code in results table -00000000000003C4 B38C 0010 219 EFPC R1 Get result FPC -00000000000003C8 BE14 4038 0000000000000038 220 STCM R1,B'0100',56(R4) Store IEEE Flags in results table - 221 * Compare and Signal value pair using long RRE -00000000000003CC B29D 0000 0000000000000000 222 LFPC R0 Load reference copy of FPC -00000000000003D0 B318 001D 223 KDBR R1,R13 Generate RRE s*s=s product -00000000000003D4 B222 0010 224 IPM R1 Get condition code and program mask -00000000000003D8 8810 001C 000000000000001C 225 SRL R1,28 Isolate CC in low order byte -00000000000003DC 4210 3040 0000000000000040 226 STC R1,64(0,R3) Save condition code in results table -00000000000003E0 B38C 0010 227 EFPC R1 Get result FPC -00000000000003E4 BE14 4040 0000000000000040 228 STCM R1,B'0100',64(R4) Store IEEE Flags in results table - 229 * Load and Test value long RRE -00000000000003E8 B29D 0000 0000000000000000 230 LFPC R0 Load reference copy of FPC -00000000000003EC B312 00C0 231 LTDBR R12,R0 Load and test -00000000000003F0 60C0 0910 0000000000000910 232 STD R12,LTDBRTST Save tested value for SNaN->QNaN test (last iteration) -00000000000003F4 B222 0010 233 IPM R1 Get condition code and program mask -00000000000003F8 8810 001C 000000000000001C 234 SRL R1,28 Isolate CC in low order byte -00000000000003FC 4210 3058 0000000000000058 235 STC R1,88(0,R3) Save condition code in results table -0000000000000400 B38C 0010 236 EFPC R1 Get result FPC -0000000000000404 BE14 4058 0000000000000058 237 STCM R1,B'0100',88(R4) Store IEEE Flags in results table - 238 * Test Data Class long RRE -0000000000000408 B29D 0000 0000000000000000 239 LFPC R0 Load reference copy of FPC -000000000000040C 4810 8000 0000000000000000 240 LH R1,0(0,R8) Get test data class mask value for True -0000000000000410 ED00 1000 0011 0000000000000000 241 TCDB R0,0(0,R1) Test Data Class, set condition code -0000000000000416 B222 0010 242 IPM R1 Get condition code and program mask -000000000000041A 8810 001C 000000000000001C 243 SRL R1,28 Isolate CC in low order byte -000000000000041E 4210 3078 0000000000000078 244 STC R1,120(0,R3) Save condition code in results table -0000000000000422 4810 8002 0000000000000002 245 LH R1,2(0,R8) Get test data class mask value for False -0000000000000426 ED00 1000 0011 0000000000000000 246 TCDB R0,0(0,R1) Test Data Class, set condition code -000000000000042C B222 0010 247 IPM R1 Get condition code and program mask -0000000000000430 8810 001C 000000000000001C 248 SRL R1,28 Isolate CC in low order byte -0000000000000434 4210 3080 0000000000000080 249 STC R1,128(0,R3) Save condition code in results table - 250 * -0000000000000438 07FB 251 BR R11 Tests done, return to loop control - 252 * - 253 * Next iteration of long BFP instruction testing - 254 * -000000000000043A 6800 A000 0000000000000000 255 EXTDS LD R0,0(0,R10) Load BFP extended first value part 1 -000000000000043E 6820 A008 0000000000000008 256 LD R2,8(0,R10) Load BFP extended second value part 1 -0000000000000442 68D0 A010 0000000000000010 257 LD R13,16(0,R10) Load BFP extended first value part 1 -0000000000000446 68F0 A018 0000000000000018 258 LD R15,24(0,R10) Load BFP extended second value part 1 -000000000000044A B365 0010 259 LXR R1,R0 Copy second value for CDBR RRE - 260 * Compare value pair using extended RRE - ASMA Ver. 0.2.0 23 Jun 2016 09:49:48 Page 6 - - LOC OBJECT CODE ADDR1 ADDR2 STMT - -000000000000044E B29D 0000 0000000000000000 261 LFPC R0 Load reference copy of FPC -0000000000000452 B349 001D 262 CXBR R1,R13 Compare first and second values -0000000000000456 B222 0010 263 IPM R1 Get condition code and program mask -000000000000045A 8810 001C 000000000000001C 264 SRL R1,28 Isolate CC in low order byte -000000000000045E 4210 3020 0000000000000020 265 STC R1,32(0,R3) Save condition code in results table -0000000000000462 B38C 0010 266 EFPC R1 Get result FPC -0000000000000466 BE14 4020 0000000000000020 267 STCM R1,B'0100',32(R4) Store IEEE Flags in results table - 268 * Compare and Signal value pair using extended RRE -000000000000046A B29D 0000 0000000000000000 269 LFPC R0 Load reference copy of FPC -000000000000046E B348 001D 270 KXBR R1,R13 Generate RRE s*s=s product -0000000000000472 B222 0010 271 IPM R1 Get condition code and program mask -0000000000000476 8810 001C 000000000000001C 272 SRL R1,28 Isolate CC in low order byte -000000000000047A 4210 3048 0000000000000048 273 STC R1,72(0,R3) Save condition code in results table -000000000000047E B38C 0010 274 EFPC R1 Get result FPC -0000000000000482 BE14 4048 0000000000000048 275 STCM R1,B'0100',72(R4) Store IEEE Flags in results table - 276 * Load and Test value extended RRE -0000000000000486 B29D 0000 0000000000000000 277 LFPC R0 Load reference copy of FPC -000000000000048A B342 00C0 278 LTXBR R12,R0 Load and test -000000000000048E 60C0 0900 0000000000000900 279 STD R12,LTXBRTST Save tested value for SNaN->QNaN test (last iteration) - 280 * need 2nd half of store -0000000000000492 B222 0010 281 IPM R1 Get condition code and program mask -0000000000000496 8810 001C 000000000000001C 282 SRL R1,28 Isolate CC in low order byte -000000000000049A 4210 3060 0000000000000060 283 STC R1,96(0,R3) Save condition code in results table -000000000000049E B38C 0010 284 EFPC R1 Get result FPC -00000000000004A2 BE14 4060 0000000000000060 285 STCM R1,B'0100',96(R4) Store IEEE Flags in results table - 286 * Test Data Class extended RRE -00000000000004A6 B29D 0000 0000000000000000 287 LFPC R0 Load reference copy of FPC -00000000000004AA 4810 8000 0000000000000000 288 LH R1,0(0,R8) Get test data class mask value for True -00000000000004AE ED00 1000 0012 0000000000000000 289 TCXB R0,0(0,R1) Test Data Class, set condition code -00000000000004B4 B222 0010 290 IPM R1 Get condition code and program mask -00000000000004B8 8810 001C 000000000000001C 291 SRL R1,28 Isolate CC in low order byte -00000000000004BC 4210 3088 0000000000000088 292 STC R1,136(0,R3) Save condition code in results table -00000000000004C0 4810 8002 0000000000000002 293 LH R1,2(0,R8) Get test data class mask value for False -00000000000004C4 ED00 1000 0012 0000000000000000 294 TCXB R0,0(0,R1) Test Data Class, set condition code -00000000000004CA B222 0010 295 IPM R1 Get condition code and program mask -00000000000004CE 8810 001C 000000000000001C 296 SRL R1,28 Isolate CC in low order byte -00000000000004D2 4210 3090 0000000000000090 297 STC R1,144(0,R3) Save condition code in results table - 298 * -00000000000004D6 07FB 299 BR R11 Tests done, return to loop control - 300 * - 301 * Short BFP Input values. QNaN, 1, 1, 2, -inf, -2, +inf, SNaN, 0. - 302 * -00000000000004D8 303 SHORTBFP DS 0F Ensure fullword alignment for input table -00000000000004D8 FFC00000 304 DC X'FFC00000' -QNaN -00000000000004DC 3F800000 305 DC X'3F800000' 1 -00000000000004E0 3F800000 306 DC X'3F800000' 1 -00000000000004E4 40000000 307 DC X'40000000' 2 -00000000000004E8 FF800000 308 DC X'FF800000' -infinity -00000000000004EC 807FFFFF 309 DC X'807FFFFF' -subnormal (maximum magnitude) -00000000000004F0 7F800000 310 DC X'7F800000' +infinity -00000000000004F4 7F810000 311 DC X'7F810000' +SNaN -00000000000004F8 00000000 312 DC X'00000000' 0 - ASMA Ver. 0.2.0 23 Jun 2016 09:49:48 Page 7 - - LOC OBJECT CODE ADDR1 ADDR2 STMT - - 313 * - 314 * Long BFP Input values. QNaN, 1, 1, 2, -inf, -2, +inf, SNaN, 0. - 315 * -0000000000000500 316 LONGBFP DS 0D -0000000000000500 FFF80000 00000000 317 DC X'FFF8000000000000' -QNaN -0000000000000508 3FF00000 00000000 318 DC X'3FF0000000000000' 1 -0000000000000510 3FF00000 00000000 319 DC X'3FF0000000000000' 1 -0000000000000518 40000000 00000000 320 DC X'4000000000000000' 2 -0000000000000520 FFF00000 00000000 321 DC X'FFF0000000000000' -infinity -0000000000000528 800FFFFF FFFFFFFF 322 DC X'800FFFFFFFFFFFFF' -subnormal (maximum magnitude) -0000000000000530 7FF00000 00000000 323 DC X'7FF0000000000000' +infinity -0000000000000538 7FF01000 00000000 324 DC X'7FF0100000000000' +SNaN -0000000000000540 00000000 00000000 325 DC X'0000000000000000' 0 - 326 * - 327 * Extended BFP Input values. QNaN, 1, 1, 2, -inf, -2, +inf, SNaN, 0. - 328 * -0000000000000548 329 EXTDBFP DS 0D -0000000000000548 FFFF8000 00000000 330 DC X'FFFF8000000000000000000000000000' -QNaN -0000000000000558 3FFF0000 00000000 331 DC X'3FFF0000000000000000000000000000' 1 -0000000000000568 3FFF0000 00000000 332 DC X'3FFF0000000000000000000000000000' 1 -0000000000000578 40000000 00000000 333 DC X'40000000000000000000000000000000' 2 -0000000000000588 FFFF0000 00000000 334 DC X'FFFF0000000000000000000000000000' -infinity -0000000000000598 8000FFFF FFFFFFFF 335 DC X'8000FFFFFFFFFFFFFFFFFFFFFFFFFFFF' -subnormal (maximum magnitude) -00000000000005A8 7FFF0000 00000000 336 DC X'7FFF0000000000000000000000000000' +infinity -00000000000005B8 7FFF0100 00000000 337 DC X'7FFF0100000000000000000000000000' +SNaN -00000000000005C8 00000000 00000000 338 DC X'00000000000000000000000000000000' 0 - 339 * - 340 * Test data class masks - 341 * Bit meanings are: 0 0 0 0 | +z -z +norm -norm || +subn -sub +inf -inf | +QNaN -QNaN +SNaN -SNaN - 342 * -00000000000005D8 343 TDCMASKS DS 0F -00000000000005D8 00040000 344 DC X'00040000' 0 0 0 0 | 0 0 0 0 || 0 0 0 0 | 0 1 0 0 -QNaN -00000000000005DC 02000000 345 DC X'02000000' 0 0 0 0 | 0 0 1 0 || 0 0 0 0 | 0 0 0 0 +1 -00000000000005E0 02000000 346 DC X'02000000' 0 0 0 0 | 0 0 1 0 || 0 0 0 0 | 0 0 0 0 +1 -00000000000005E4 02000000 347 DC X'02000000' 0 0 0 0 | 0 0 1 0 || 0 0 0 0 | 0 0 0 0 +2 -00000000000005E8 00100000 348 DC X'00100000' 0 0 0 0 | 0 0 0 0 || 0 0 0 1 | 0 0 0 0 -inf -00000000000005EC 00400000 349 DC X'00400000' 0 0 0 0 | 0 0 0 0 || 0 1 0 0 | 0 0 0 0 -2 -00000000000005F0 00200000 350 DC X'00200000' 0 0 0 0 | 0 0 0 0 || 0 0 1 0 | 0 0 0 0 +inf -00000000000005F4 00020000 351 DC X'00020000' 0 0 0 0 | 0 0 0 0 || 0 0 0 0 | 0 0 2 0 +SNaN - 352 -00000000000005F8 00000000000005F8 0000000000000700 353 ORG BFPCOMPS+X'700' -0000000000000700 00000000 00000000 354 RESULTCC DS 19D 8 Condition codes from each of 19 instructions - 355 * ( +0) COMPARE short RXE results - 356 * ( +8) COMPARE short RRE results - 357 * ( +16) COMPARE long RXE results - 358 * ( +24) COMPARE long RRE results - 359 * ( +32) COMPARE extended RRE result - 360 * - 361 * ( +40) COMPARE AND SIGNAL short RXE results - 362 * ( +48) COMPARE AND SIGNAL short RRE results - 363 * ( +56) COMPARE AND SIGNAL long RXE results - 364 * ( +64) COMPARE AND SIGNAL long RRE results - ASMA Ver. 0.2.0 23 Jun 2016 09:49:48 Page 8 - - LOC OBJECT CODE ADDR1 ADDR2 STMT - - 365 * ( +72) COMPARE AND SIGNAL extended RRE results - 366 * - 367 * ( +80) LOAD AND TEST short RRE results - 368 * ( +88) LOAD AND TEST long RRE results - 369 * ( +96) LOAD AND TEST extended RRE results - 370 * - 371 * (+104) TEST DATA CLASS short RRE results (True results) - 372 * (+112) TEST DATA CLASS short RRE results (False results) - 373 * (+120) TEST DATA CLASS long RRE results (True results) - 374 * (+128) TEST DATA CLASS long RRE results (False results) - 375 * (+136) TEST DATA CLASS extended RRE results (True results) - 376 * (+144) TEST DATA CLASS extended RRE results (False results) - 377 * -0000000000000798 0000000000000798 0000000000000800 378 ORG BFPCOMPS+X'800' -0000000000000800 00000000 00000000 379 RESULTFL DS 13D 8 IEEE flag bytes from each of 13 instructions - 380 * (TEST DATA CLASS does not set IEEE flags) - 381 * ( +0) COMPARE short RXE results - 382 * ( +8) COMPARE short RRE results - 383 * ( +16) COMPARE long RXE results - 384 * ( +24) COMPARE long RRE results - 385 * ( +32) COMPARE extended RRE result - 386 * - 387 * ( +40) COMPARE AND SIGNAL short RXE results - 388 * ( +48) COMPARE AND SIGNAL short RRE results - 389 * ( +56) COMPARE AND SIGNAL long RXE results - 390 * ( +64) COMPARE AND SIGNAL long RRE results - 391 * ( +72) COMPARE AND SIGNAL extended RRE results - 392 * - 393 * ( +80) LOAD AND TEST short RRE results - 394 * ( +88) LOAD AND TEST long RRE results - 395 * ( +96) LOAD AND TEST extended RRE results - 396 * -0000000000000868 0000000000000868 0000000000000900 397 ORG BFPCOMPS+X'900' -0000000000000900 00000000 00000000 398 LTXBRTST DS 2D LOAD AND TEST Extended result (to test conversion of SNaN into QNaN) -0000000000000910 00000000 00000000 399 LTDBRTST DS D LOAD AND TEST Long result (to test conversion of SNaN into QNaN) -0000000000000918 00000000 400 LTEBRTST DS F LOAD AND TEST Short result (to test conversion of SNaN into QNaN) -000000000000091C 401 END - ASMA Ver. 0.2.0 23 Jun 2016 09:49:48 Page 9 - - SYMBOL TYPE VALUE LENGTH DEFN REFERENCES - -BFPCOMPS J 000000 2332 63 81 83 85 353 378 397 -CTLR0 F 000228 4 98 87 88 89 -EXTDBFP D 000548 8 329 112 -EXTDS I 00043A 4 255 117 -IMAGE 1 000000 2332 0 -LONGBFP D 000500 8 316 111 -LONGS I 00036A 4 194 116 -LTDBRTST D 000910 8 399 232 -LTEBRTST F 000918 4 400 171 -LTXBRTST D 000900 8 398 279 -R0 U 000000 1 64 87 89 90 130 133 135 137 138 145 153 154 161 169 170 178 180 185 - 194 196 198 199 206 214 215 222 230 231 239 241 246 255 259 261 269 - 277 278 287 289 294 -R1 U 000001 1 65 131 135 139 140 141 142 143 146 147 148 149 150 151 155 156 157 158 - 159 162 163 164 165 166 167 172 173 174 175 176 179 180 181 182 183 - 184 185 186 187 188 196 200 201 202 203 204 207 208 209 210 211 212 - 216 217 218 219 220 223 224 225 226 227 228 233 234 235 236 237 240 - 241 242 243 244 245 246 247 248 249 259 262 263 264 265 266 267 270 - 271 272 273 274 275 281 282 283 284 285 288 289 290 291 292 293 294 - 295 296 297 -R10 U 00000A 1 74 112 123 255 256 257 258 -R11 U 00000B 1 75 91 93 115 116 117 190 251 299 -R12 U 00000C 1 76 92 126 170 171 231 232 278 279 -R13 U 00000D 1 77 113 124 132 134 146 162 195 207 223 257 262 270 -R14 U 00000E 1 78 94 95 -R15 U 00000F 1 79 258 -R2 U 000002 1 66 106 124 256 -R3 U 000003 1 67 107 118 141 149 157 165 174 183 188 202 210 218 226 235 244 249 265 - 273 283 292 297 -R4 U 000004 1 68 108 119 143 151 159 167 176 204 212 220 228 237 267 275 285 -R5 U 000005 1 69 -R6 U 000006 1 70 -R7 U 000007 1 71 109 120 133 134 138 154 -R8 U 000008 1 72 110 121 179 184 240 245 288 293 -R9 U 000009 1 73 111 122 194 195 199 215 -RESULTCC D 000700 8 354 107 -RESULTFL D 000800 8 379 108 -SAVER11 D 000230 8 99 91 93 -SHORTBFP F 0004D8 4 303 109 -SHORTS I 00028E 4 130 115 -STARTTST I 000200 4 87 82 -TDCMASKS F 0005D8 4 343 110 -TESTCOMP H 000248 2 105 92 -WAITPSW X 000238 16 100 96 - ASMA Ver. 0.2.0 23 Jun 2016 09:49:48 Page 10 - -MACRO DEFN REFERENCES - -No defined macros - ASMA Ver. 0.2.0 23 Jun 2016 09:49:48 Page 11 - - DESC SYMBOL SIZE POS ADDR - -Entry: 0 - -Image IMAGE 2332 000-91B 000-91B - Region 2332 000-91B 000-91B - CSECT BFPCOMPS 2332 000-91B 000-91B - ASMA Ver. 0.2.0 23 Jun 2016 09:49:48 Page 12 - - STMT FILE NAME - -1 C:\Users\srorso\Documents\GitHub\hyperion\tests\ieee-comps.asm - - -** NO ERRORS FOUND ** - - \ No newline at end of file diff --git a/tests/ieee-comps.tst b/tests/ieee-comps.tst deleted file mode 100644 index 6c29e885c..000000000 --- a/tests/ieee-comps.tst +++ /dev/null @@ -1,158 +0,0 @@ - -*Testcase ieee-comps.tst: IEEE Compare, Load and Test, Test Data Class -*Message Testcase ieee-comps.tst: IEEE Compare, Load and Test, Test Data Class -*Message ..Includes COMPARE (5), COMPARE AND SIGNAL (5), LOAD AND TEST (3), -*Message .. TEST DATA CLASS (3), 16 instructions total. -*Message ..Test case values include infinities, a subnormal, a QNaN, and an SNaN - -# see ieee-comps.asm for test case processing details - -sysclear -archmode esame -loadcore "$(testpath)/ieee-comps.core" -runtest .1 - -# the following symbol definitions must match the first digit of the corresponding -# ORG statement in the ieee-comps.asm and .list files - -defsym res1 "7" # Condition codes -defsym res2 "8" # IEEE flags -defsym res3 "9" # SNaN->QNaN test results - -r $(res1)00.98 # Condition codes -r $(res2)00.90 # IEEE flags -r $(res3)00.20 # SNaN->QNaN test results - -# Short instruction expected results - -*Compare -r $(res1)00.8 # BFP Short Compare RXE condition codes, expecting 3 0 1 2 1 1 3 3 -*Want "CEB cc" 03000102 01010303 -*Compare -r $(res2)00.8 # BFP Short Compare RXE IEEE Flags, expecting 00, 00, 00, 00, 00, 80, 80 -*Want "CEB IEEE Flags" 00000000 00008080 - -*Compare -r $(res1)08.8 # BFP Short Compare RRE condition codes, expecting 3 0 1 2 1 1 3 3 -*Want "CEBR cc" 03000102 01010303 -*Compare -r $(res2)08.8 # BFP Short Compare RRE IEEE Flags, expecting 00, 00, 00, 00, 00, 80, 80 -*Want "CEBR IEEE Flags" 00000000 00008080 - -*Compare -r $(res1)28.8 # BFP Short Compare and Signal RXE condition codes, expecting 3 0 1 2 1 1 3 3 -*Want "KEB cc" 03000102 01010303 -*Compare -r $(res2)28.8 # BFP Short Compare and Signal RXE IEEE Flags, expecting 80, 00, 00, 00, 00, 80, 80 -*Want "KEB IEEE Flags" 80000000 00008080 - -*Compare -r $(res1)30.8 # BFP Short Compare and Signal RRE condition codes, expecting 3 0 1 2 1 1 3 3 -*Want "KEBR cc" 03000102 01010303 -*Compare -r $(res2)30.8 # BFP Short Compare and Signal RRE IEEE Flags, expecting 80, 00, 00, 00, 00, 80, 80 -*Want "KEBR IEEE Flags" 80000000 00008080 - -*Compare -r $(res1)50.8 # BFP Short Load and Test RRE condition codes, expecting 3 2 2 2 1 1 2 3 -*Want "LTEBR cc" 03020202 01010203 -*Compare -r $(res2)50.8 # BFP Short Load and Test RRE IEEE Flags, expecting 00, 00, 00, 00, 00, 00, 80 -*Want "LTEBR IEEE Flags" 00000000 00000080 - -*Compare -r $(res3)18.4 # BFP Short Load and Test RRE SNaN->QNaN, expecting 7FC10000 -*Want "LTEBR SNaN->QNaN" 7FC10000 - -*Compare -r $(res1)68.8 # BFP Short Test Data Class condition codes, expecting 1 1 1 1 1 1 1 1 -*Want "TCEB cc 1/2" 01010101 01010101 -*Compare -r $(res1)70.8 # BFP Short Test Data Class condition codes, expecting 0 0 0 0 0 0 0 0 -*Want "TCEB cc 2/2" 00000000 00000000 - - -# Long instruction expected results (same as the shorts except for the QNaN) - -*Compare -r $(res1)10.8 # BFP Long Compare RXE condition codes, expecting 3 0 1 2 1 1 3 3 -*Want "CDB cc" 03000102 01010303 -*Compare -r $(res2)10.8 # BFP Long Compare RXE IEEE Flags, expecting 00, 00, 00, 00, 00, 80, 80 -*Want "CDB IEEE Flags" 00000000 00008080 - -*Compare -r $(res1)18.8 # BFP Long Compare RRE condition codes, expecting 3 0 1 2 1 1 3 3 -*Want "CDBR cc" 03000102 01010303 -*Compare -r $(res2)18.8 # BFP Long Compare RRE IEEE Flags, expecting 00, 00, 00, 00, 00, 80, 80 -*Want "CDBR IEEE Flags" 00000000 00008080 - -*Compare -r $(res1)38.8 # BFP Long Compare and Signal RXE condition codes, expecting 3 0 1 2 1 1 3 3 -*Want "KDB cc" 03000102 01010303 -*Compare -r $(res2)38.8 # BFP Long Compare and Signal RXE IEEE Flags, expecting 00, 00, 00, 00, 00, 80, 80 -*Want "KDB IEEE Flags" 80000000 00008080 - -*Compare -r $(res1)40.8 # BFP Long Compare and Signal RRE condition codes, expecting 3 0 1 2 1 1 3 3 -*Want "KDBR cc" 03000102 01010303 -*Compare -r $(res2)40.8 # BFP Long Compare and Signal RRE IEEE Flags, expecting 80, 00, 00, 00, 00, 80, 80 -*Want "KDBR IEEE Flags" 80000000 00008080 - -*Compare -r $(res1)58.8 # BFP Long Load and Test RRE condition codes, expecting 3 2 2 2 1 1 2 3 -*Want "LTDBR cc" 03020202 01010203 -*Compare -r $(res2)58.8 # BFP Long Load and Test RRE IEEE Flags, expecting 00, 00, 00, 00, 00, 00, 80 -*Want "LTDBR IEEE Flags" 00000000 00000080 -*Compare -r $(res3)10.8 # BFP Long Load and Test RRE SNaN->QNaN, expecting 7FF81000 00000000 -*Want "LTDBR SNaN->QNaN" 7FF81000 00000000 - -*Compare -r $(res1)78.8 # BFP Long Test Data Class condition codes, expecting 1 1 1 1 1 1 1 1 -*Want "TCDB cc 1/2" 01010101 01010101 -*Compare -r $(res1)80.8 # BFP Long Test Data Class condition codes, expecting 0 0 0 0 0 0 0 0 -*Want "TCDB cc 2/2" 00000000 00000000 - - - -# Extended instruction expected results (same as the shorts except for the QNaN) - -*Compare -r $(res1)20.8 # BFP extended Compare RRE condition codes, expecting 3 0 1 2 1 1 3 3 -*Want "CXBR cc" 03000102 01010303 -*Compare -r $(res2)20.8 # BFP extended Compare RRE IEEE Flags, expecting 00, 00, 00, 00, 00, 80, 80 -*Want "CXBR IEEE Flags" 00000000 00008080 - -*Compare -r $(res1)48.8 # BFP extended Compare and Signal RRE condition codes, expecting 3 0 1 2 1 1 3 3 -*Want "KXBR cc" 03000102 01010303 -*Compare -r $(res2)48.8 # BFP extended Compare and Signal RRE IEEE Flags, expecting 80, 00, 00, 00, 00, 80, 80 -*Want "KXBR IEEE Flags" 80000000 00008080 - -*Compare -r $(res1)60.8 # BFP extended Load and Test RRE condition codes, expecting 3 2 2 2 1 1 2 3 -*Want "LTXBR cc" 03020202 01010203 -*Compare -r $(res2)60.8 # BFP extended Load and Test RRE IEEE Flags, expecting 00, 00, 00, 00, 00, 00, 80 -*Want "LTXBR IEEE Flags" 00000000 00000080 -*Compare -r $(res3)00.10 # BFP extended Load and Test RRE SNaN->QNaN, expecting 7FFF8100 00000000 00000000 00000000 -*Want "LTXBR SNaN->QNaN" 7FFF8100 00000000 00000000 00000000 - -*Compare -r $(res1)88.8 # BFP extended Test Data Class condition codes, expecting 1 1 1 1 1 1 1 1 -*Want "TCXB cc 1/2" 01010101 01010101 -*Compare -r $(res1)90.8 # BFP extended Test Data Class condition codes, expecting 0 0 0 0 0 0 0 0 -*Want "TCXB cc 2/2" 00000000 00000000 - - -*Done diff --git a/tests/ieee-div-nans.asm b/tests/ieee-div-nans.asm deleted file mode 100644 index 882e29829..000000000 --- a/tests/ieee-div-nans.asm +++ /dev/null @@ -1,164 +0,0 @@ -* -* Divide adjacent pairs of values in the input set (six values means five results). -* -* Test data: 2, 0, QNaN(1), QNaN(2), SNaN(3), SNaN(4). -* Expected Results +inf, QNaN(1), QNaN(1), SNaN(3), SNaN(3). -* -* NaN payload--in parentheses--is used to confirm that the right NaN ends up in the result. -* -* Tests seven division instructions: -* DIVIDE (BFP short RRE) DEBR -* DIVIDE (BFP short RXE) DEB -* DIVIDE (BFP long, RRE) DDBR -* DIVIDE (BFP long, RXE) DDB -* DIVIDE (BFP extended, RRE) DXBR -* -* Interrupts are masked; no program checks are expected -* -* Also tests the following floating point support instructions -* LOAD (Short) -* LOAD (Long) -* LOAD ZERO (Long) -* STORE (Short) -* STORE (Long) -* -BFPDIVNA START 0 -R0 EQU 0 -R1 EQU 1 -R2 EQU 2 -R3 EQU 3 -R4 EQU 4 -R5 EQU 5 -R6 EQU 6 -R7 EQU 7 -R8 EQU 8 -R9 EQU 9 -R10 EQU 10 -R11 EQU 11 -R12 EQU 12 -R13 EQU 13 -R14 EQU 14 -R15 EQU 15 - USING *,0 - ORG BFPDIVNA+X'1A0' - DC X'0000000180000000',AD(STARTNAN) z/Arch restart PSW - ORG BFPDIVNA+X'1D0' - DC X'0002000000000000000000000000DEAD' z/Arch pgm chk new PSW - ORG BFPDIVNA+X'200' -* -* Mainline program. -* -STARTNAN STCTL R0,R0,CTLR0 Store CR0 to enable AFP - OI CTLR0+1,X'04' Turn on AFP bit - LCTL R0,R0,CTLR0 Reload updated CR0 - BAS R12,TESTDIV Perform divisions - LPSWE WAITPSW All done, load disabled wait PSW -* -* BFP Division Short RXE and RRE using NaNs as inputs. -* -* We cannot use Load Rounded to shrink extended BFP into the shorts needed -* for this test because Load Rounded will convert the SNaNs into QNaNs -* -TESTDIV DS 0H - LA R2,5 Set count of division operations - LA R3,SHORTRES Point to start of short BFP quotients - LA R7,SHORTBFP Point to start of short BFP input values - BASR R13,0 Set top of loop for short BFP tests -* -* Top of loop -* Clear residuals from FPR0, 4, 5 - LZDR R0 Zero FPR0 - LZDR R4 Zero FPR4 -* Collect dividend and divisor, do four divisions, store quotients. - LE R0,0(0,R7) Get BFP ext dividend - LDR R5,R0 Duplicate dividend for RRE test - LE R4,4(0,R7) Get BFP ext divisor for RRE test - DEB R0,4(0,R7) Generate RXE - DEBR R5,R4 Generate RRE - STE R0,0(0,R3) Store short BFP RXE - STE R5,4(0,R3) Store short BFP RRE - LA R7,4(0,R7) Point to next short BFP input pair - LA R3,8(0,R3) Point to next short BFP result pair - BCTR R2,R13 Loop through all short BFP test cases - B TESTLONG Go test long BFP division. -* -* BFP Division long RXE and RRE -* -TESTLONG DS 0H - LA R2,5 Set count of division operations - LA R3,LONGRES Point to start of long BFP quotients - LA R7,LONGBFP Point to start of extended BFP input values - BASR R13,0 Set top of loop for long BFP tests -* Top of loop -* Collect dividend and divisor, do two divisions, store quotients - LD R0,0(0,R7) Get BFP ext dividend - LDR R5,R0 Save dividend for RRE - LD R4,8(0,R7) Get BFP ext divisor - DDB R0,8(0,R7) Generate RXE long - DDBR R5,R4 Generate RRE long - STD R0,0(0,R3) Store long BFP RXE quotient - STD R5,8(0,R3) Store long BFP RRE quotient - LA R7,8(0,R7) Point to next long BFP input pair - LA R3,16(0,R3) Point to next long BFP result pair - BCTR R2,R13 Loop through all long test cases - B TESTEXT Skip across patch area -* -* BFP division extended, RRE only. -* -TESTEXT DS 0H - LA R2,5 Set count of division operations - LA R4,EXTDRES Point to start of extended BFP quotients - LA R7,EXTDBFP Point to start of extended BFP input values - BASR R13,0 Set top of loop for l*l tests -* Top of loop -* Collect dividend & divisor, do division and Load FP Integer, store results. - LD R0,0(0,R7) Get BFP ext dividend part 1 - LD R2,8(0,R7) Get BFP ext dividend part 2 - LD R13,16(0,R7) Get BFP ext divisor part 1 - LD R15,24(0,R7) Get BFP ext divisor part 2 - DXBR R0,R13 Generate RRE extended quotient - STD R0,0(0,R4) Store extended BFP RRE quotient part 1 - STD R2,8(0,R4) Store extended BFP RRE quotient part 2 - LA R7,16(0,R7) Point to next extended BFP input pair - LA R4,16(0,R4) Point to next extended BFP result - BCTR R2,R13 Loop through all test cases -* - BR R12 Tests done, return to mainline -* -* -* -CTLR0 DS F Control register 0 (bit45 AFP control) -WAITPSW DC X'00020000000000000000000000000000' Disabled wait state PSW - normal completion -* - ORG BFPDIVNA+X'300' -SHORTBFP DS 0D 6 short BFP (Room for 8) - DC X'40000000' DC 2 - DC X'00000000' DC 0 - DC X'7FC10000' QNaN(1) - DC X'7FC20000' QNaN(2) - DC X'7F830000' SNaN(3) - DC X'7F840000' SNaN(4) -* - ORG BFPDIVNA+X'320' -LONGBFP DS 0D 6 long BFP (Room for 8) - DC X'4000000000000000' 2 - DC X'0000000000000000' 0 - DC X'7FF8100000000000' QNaN(1) - DC X'7FF8200000000000' QNaN(2) - DC X'7FF0300000000000' SNaN(3) - DC X'7FF0400000000000' SNaN(4) -* - ORG BFPDIVNA+X'360' -EXTDBFP DS 0D 6 Extended BFP (Room for 8, but not 9) - DC X'40000000000000000000000000000000' 2 - DC X'00000000000000000000000000000000' 0 - DC X'7FFF8100000000000000000000000000' QNaN(1) - DC X'7FFF8200000000000000000000000000' QNaN(2) - DC X'7FFF0300000000000000000000000000' SNaN(3) - DC X'7FFF0400000000000000000000000000' SNaN(4) -* - ORG BFPDIVNA+X'400' -SHORTRES DS 8D Results from short divide, five pairs, room for 8 -LONGRES DS 16D Results from long divide, five pairs, room for 8 - ORG BFPDIVNA+X'500' -EXTDRES DS 16D Results from extended divide, five results, room for 8 diff --git a/tests/ieee-div-nans.core b/tests/ieee-div-nans.core deleted file mode 100644 index a41463f80..000000000 Binary files a/tests/ieee-div-nans.core and /dev/null differ diff --git a/tests/ieee-div-nans.list b/tests/ieee-div-nans.list deleted file mode 100644 index e4e44c648..000000000 --- a/tests/ieee-div-nans.list +++ /dev/null @@ -1,238 +0,0 @@ -ASMA Ver. 0.2.0 23 Jun 2016 09:49:49 Page 1 - - LOC OBJECT CODE ADDR1 ADDR2 STMT - - 1 * - 2 * Divide adjacent pairs of values in the input set (six values means five results). - 3 * - 4 * Test data: 2, 0, QNaN(1), QNaN(2), SNaN(3), SNaN(4). - 5 * Expected Results +inf, QNaN(1), QNaN(1), SNaN(3), SNaN(3). - 6 * - 7 * NaN payload--in parentheses--is used to confirm that the right NaN ends up in the result. - 8 * - 9 * Tests seven division instructions: - 10 * DIVIDE (BFP short RRE) DEBR - 11 * DIVIDE (BFP short RXE) DEB - 12 * DIVIDE (BFP long, RRE) DDBR - 13 * DIVIDE (BFP long, RXE) DDB - 14 * DIVIDE (BFP extended, RRE) DXBR - 15 * - 16 * Interrupts are masked; no program checks are expected - 17 * - 18 * Also tests the following floating point support instructions - 19 * LOAD (Short) - 20 * LOAD (Long) - 21 * LOAD ZERO (Long) - 22 * STORE (Short) - 23 * STORE (Long) - 24 * - 0000000000000000 000000000000057F 25 BFPDIVNA START 0 - 0000000000000000 0000000000000001 26 R0 EQU 0 - 0000000000000001 0000000000000001 27 R1 EQU 1 - 0000000000000002 0000000000000001 28 R2 EQU 2 - 0000000000000003 0000000000000001 29 R3 EQU 3 - 0000000000000004 0000000000000001 30 R4 EQU 4 - 0000000000000005 0000000000000001 31 R5 EQU 5 - 0000000000000006 0000000000000001 32 R6 EQU 6 - 0000000000000007 0000000000000001 33 R7 EQU 7 - 0000000000000008 0000000000000001 34 R8 EQU 8 - 0000000000000009 0000000000000001 35 R9 EQU 9 - 000000000000000A 0000000000000001 36 R10 EQU 10 - 000000000000000B 0000000000000001 37 R11 EQU 11 - 000000000000000C 0000000000000001 38 R12 EQU 12 - 000000000000000D 0000000000000001 39 R13 EQU 13 - 000000000000000E 0000000000000001 40 R14 EQU 14 - 000000000000000F 0000000000000001 41 R15 EQU 15 -0000000000000000 0000000000000000 42 USING *,0 -0000000000000000 0000000000000000 00000000000001A0 43 ORG BFPDIVNA+X'1A0' -00000000000001A0 00000001 80000000 44 DC X'0000000180000000',AD(STARTNAN) z/Arch restart PSW -00000000000001B0 00000000000001B0 00000000000001D0 45 ORG BFPDIVNA+X'1D0' -00000000000001D0 00020000 00000000 46 DC X'0002000000000000000000000000DEAD' z/Arch pgm chk new PSW -00000000000001E0 00000000000001E0 0000000000000200 47 ORG BFPDIVNA+X'200' - 48 * - 49 * Mainline program. - 50 * -0000000000000200 B600 02C4 00000000000002C4 51 STARTNAN STCTL R0,R0,CTLR0 Store CR0 to enable AFP -0000000000000204 9604 02C5 00000000000002C5 52 OI CTLR0+1,X'04' Turn on AFP bit - ASMA Ver. 0.2.0 23 Jun 2016 09:49:49 Page 2 - - LOC OBJECT CODE ADDR1 ADDR2 STMT - -0000000000000208 B700 02C4 00000000000002C4 53 LCTL R0,R0,CTLR0 Reload updated CR0 -000000000000020C 4DC0 0214 0000000000000214 54 BAS R12,TESTDIV Perform divisions -0000000000000210 B2B2 02C8 00000000000002C8 55 LPSWE WAITPSW All done, load disabled wait PSW - 56 * - 57 * BFP Division Short RXE and RRE using NaNs as inputs. - 58 * - 59 * We cannot use Load Rounded to shrink extended BFP into the shorts needed - 60 * for this test because Load Rounded will convert the SNaNs into QNaNs - 61 * -0000000000000214 62 TESTDIV DS 0H -0000000000000214 4120 0005 0000000000000005 63 LA R2,5 Set count of division operations -0000000000000218 4130 0400 0000000000000400 64 LA R3,SHORTRES Point to start of short BFP quotients -000000000000021C 4170 0300 0000000000000300 65 LA R7,SHORTBFP Point to start of short BFP input values -0000000000000220 0DD0 66 BASR R13,0 Set top of loop for short BFP tests - 67 * - 68 * Top of loop - 69 * Clear residuals from FPR0, 4, 5 -0000000000000222 B375 0000 70 LZDR R0 Zero FPR0 -0000000000000226 B375 0040 71 LZDR R4 Zero FPR4 - 72 * Collect dividend and divisor, do four divisions, store quotients. -000000000000022A 7800 7000 0000000000000000 73 LE R0,0(0,R7) Get BFP ext dividend -000000000000022E 2850 74 LDR R5,R0 Duplicate dividend for RRE test -0000000000000230 7840 7004 0000000000000004 75 LE R4,4(0,R7) Get BFP ext divisor for RRE test -0000000000000234 ED00 7004 000D 0000000000000004 76 DEB R0,4(0,R7) Generate RXE -000000000000023A B30D 0054 77 DEBR R5,R4 Generate RRE -000000000000023E 7000 3000 0000000000000000 78 STE R0,0(0,R3) Store short BFP RXE -0000000000000242 7050 3004 0000000000000004 79 STE R5,4(0,R3) Store short BFP RRE -0000000000000246 4170 7004 0000000000000004 80 LA R7,4(0,R7) Point to next short BFP input pair -000000000000024A 4130 3008 0000000000000008 81 LA R3,8(0,R3) Point to next short BFP result pair -000000000000024E 062D 82 BCTR R2,R13 Loop through all short BFP test cases -0000000000000250 47F0 0254 0000000000000254 83 B TESTLONG Go test long BFP division. - 84 * - 85 * BFP Division long RXE and RRE - 86 * -0000000000000254 87 TESTLONG DS 0H -0000000000000254 4120 0005 0000000000000005 88 LA R2,5 Set count of division operations -0000000000000258 4130 0440 0000000000000440 89 LA R3,LONGRES Point to start of long BFP quotients -000000000000025C 4170 0320 0000000000000320 90 LA R7,LONGBFP Point to start of extended BFP input values -0000000000000260 0DD0 91 BASR R13,0 Set top of loop for long BFP tests - 92 * Top of loop - 93 * Collect dividend and divisor, do two divisions, store quotients -0000000000000262 6800 7000 0000000000000000 94 LD R0,0(0,R7) Get BFP ext dividend -0000000000000266 2850 95 LDR R5,R0 Save dividend for RRE -0000000000000268 6840 7008 0000000000000008 96 LD R4,8(0,R7) Get BFP ext divisor -000000000000026C ED00 7008 001D 0000000000000008 97 DDB R0,8(0,R7) Generate RXE long -0000000000000272 B31D 0054 98 DDBR R5,R4 Generate RRE long -0000000000000276 6000 3000 0000000000000000 99 STD R0,0(0,R3) Store long BFP RXE quotient -000000000000027A 6050 3008 0000000000000008 100 STD R5,8(0,R3) Store long BFP RRE quotient -000000000000027E 4170 7008 0000000000000008 101 LA R7,8(0,R7) Point to next long BFP input pair -0000000000000282 4130 3010 0000000000000010 102 LA R3,16(0,R3) Point to next long BFP result pair -0000000000000286 062D 103 BCTR R2,R13 Loop through all long test cases -0000000000000288 47F0 028C 000000000000028C 104 B TESTEXT Skip across patch area - ASMA Ver. 0.2.0 23 Jun 2016 09:49:49 Page 3 - - LOC OBJECT CODE ADDR1 ADDR2 STMT - - 105 * - 106 * BFP division extended, RRE only. - 107 * -000000000000028C 108 TESTEXT DS 0H -000000000000028C 4120 0005 0000000000000005 109 LA R2,5 Set count of division operations -0000000000000290 4140 0500 0000000000000500 110 LA R4,EXTDRES Point to start of extended BFP quotients -0000000000000294 4170 0360 0000000000000360 111 LA R7,EXTDBFP Point to start of extended BFP input values -0000000000000298 0DD0 112 BASR R13,0 Set top of loop for l*l tests - 113 * Top of loop - 114 * Collect dividend & divisor, do division and Load FP Integer, store results. -000000000000029A 6800 7000 0000000000000000 115 LD R0,0(0,R7) Get BFP ext dividend part 1 -000000000000029E 6820 7008 0000000000000008 116 LD R2,8(0,R7) Get BFP ext dividend part 2 -00000000000002A2 68D0 7010 0000000000000010 117 LD R13,16(0,R7) Get BFP ext divisor part 1 -00000000000002A6 68F0 7018 0000000000000018 118 LD R15,24(0,R7) Get BFP ext divisor part 2 -00000000000002AA B34D 000D 119 DXBR R0,R13 Generate RRE extended quotient -00000000000002AE 6000 4000 0000000000000000 120 STD R0,0(0,R4) Store extended BFP RRE quotient part 1 -00000000000002B2 6020 4008 0000000000000008 121 STD R2,8(0,R4) Store extended BFP RRE quotient part 2 -00000000000002B6 4170 7010 0000000000000010 122 LA R7,16(0,R7) Point to next extended BFP input pair -00000000000002BA 4140 4010 0000000000000010 123 LA R4,16(0,R4) Point to next extended BFP result -00000000000002BE 062D 124 BCTR R2,R13 Loop through all test cases - 125 * -00000000000002C0 07FC 126 BR R12 Tests done, return to mainline - 127 * - 128 * - 129 * -00000000000002C4 00000000 130 CTLR0 DS F Control register 0 (bit45 AFP control) -00000000000002C8 00020000 00000000 131 WAITPSW DC X'00020000000000000000000000000000' Disabled wait state PSW - normal completion - 132 * -00000000000002D8 00000000000002D8 0000000000000300 133 ORG BFPDIVNA+X'300' -0000000000000300 134 SHORTBFP DS 0D 6 short BFP (Room for 8) -0000000000000300 40000000 135 DC X'40000000' DC 2 -0000000000000304 00000000 136 DC X'00000000' DC 0 -0000000000000308 7FC10000 137 DC X'7FC10000' QNaN(1) -000000000000030C 7FC20000 138 DC X'7FC20000' QNaN(2) -0000000000000310 7F830000 139 DC X'7F830000' SNaN(3) -0000000000000314 7F840000 140 DC X'7F840000' SNaN(4) - 141 * -0000000000000318 0000000000000318 0000000000000320 142 ORG BFPDIVNA+X'320' -0000000000000320 143 LONGBFP DS 0D 6 long BFP (Room for 8) -0000000000000320 40000000 00000000 144 DC X'4000000000000000' 2 -0000000000000328 00000000 00000000 145 DC X'0000000000000000' 0 -0000000000000330 7FF81000 00000000 146 DC X'7FF8100000000000' QNaN(1) -0000000000000338 7FF82000 00000000 147 DC X'7FF8200000000000' QNaN(2) -0000000000000340 7FF03000 00000000 148 DC X'7FF0300000000000' SNaN(3) -0000000000000348 7FF04000 00000000 149 DC X'7FF0400000000000' SNaN(4) - 150 * -0000000000000350 0000000000000350 0000000000000360 151 ORG BFPDIVNA+X'360' -0000000000000360 152 EXTDBFP DS 0D 6 Extended BFP (Room for 8, but not 9) -0000000000000360 40000000 00000000 153 DC X'40000000000000000000000000000000' 2 -0000000000000370 00000000 00000000 154 DC X'00000000000000000000000000000000' 0 -0000000000000380 7FFF8100 00000000 155 DC X'7FFF8100000000000000000000000000' QNaN(1) -0000000000000390 7FFF8200 00000000 156 DC X'7FFF8200000000000000000000000000' QNaN(2) - ASMA Ver. 0.2.0 23 Jun 2016 09:49:49 Page 4 - - LOC OBJECT CODE ADDR1 ADDR2 STMT - -00000000000003A0 7FFF0300 00000000 157 DC X'7FFF0300000000000000000000000000' SNaN(3) -00000000000003B0 7FFF0400 00000000 158 DC X'7FFF0400000000000000000000000000' SNaN(4) - 159 * -00000000000003C0 00000000000003C0 0000000000000400 160 ORG BFPDIVNA+X'400' -0000000000000400 00000000 00000000 161 SHORTRES DS 8D Results from short divide, five pairs, room for 8 -0000000000000440 00000000 00000000 162 LONGRES DS 16D Results from long divide, five pairs, room for 8 -00000000000004C0 00000000000004C0 0000000000000500 163 ORG BFPDIVNA+X'500' -0000000000000500 00000000 00000000 164 EXTDRES DS 16D Results from extended divide, five results, room for 8 - ASMA Ver. 0.2.0 23 Jun 2016 09:49:49 Page 5 - - SYMBOL TYPE VALUE LENGTH DEFN REFERENCES - -BFPDIVNA J 000000 1408 25 43 45 47 133 142 151 160 163 -CTLR0 F 0002C4 4 130 51 52 53 -EXTDBFP D 000360 8 152 111 -EXTDRES D 000500 8 164 110 -IMAGE 1 000000 1408 0 -LONGBFP D 000320 8 143 90 -LONGRES D 000440 8 162 89 -R0 U 000000 1 26 51 53 70 73 74 76 78 94 95 97 99 115 119 120 -R1 U 000001 1 27 -R10 U 00000A 1 36 -R11 U 00000B 1 37 -R12 U 00000C 1 38 54 126 -R13 U 00000D 1 39 66 82 91 103 112 117 119 124 -R14 U 00000E 1 40 -R15 U 00000F 1 41 118 -R2 U 000002 1 28 63 82 88 103 109 116 121 124 -R3 U 000003 1 29 64 78 79 81 89 99 100 102 -R4 U 000004 1 30 71 75 77 96 98 110 120 121 123 -R5 U 000005 1 31 74 77 79 95 98 100 -R6 U 000006 1 32 -R7 U 000007 1 33 65 73 75 76 80 90 94 96 97 101 111 115 116 117 118 122 -R8 U 000008 1 34 -R9 U 000009 1 35 -SHORTBFP D 000300 8 134 65 -SHORTRES D 000400 8 161 64 -STARTNAN I 000200 4 51 44 -TESTDIV H 000214 2 62 54 -TESTEXT H 00028C 2 108 104 -TESTLONG H 000254 2 87 83 -WAITPSW X 0002C8 16 131 55 - ASMA Ver. 0.2.0 23 Jun 2016 09:49:49 Page 6 - -MACRO DEFN REFERENCES - -No defined macros - ASMA Ver. 0.2.0 23 Jun 2016 09:49:49 Page 7 - - DESC SYMBOL SIZE POS ADDR - -Entry: 0 - -Image IMAGE 1408 000-57F 000-57F - Region 1408 000-57F 000-57F - CSECT BFPDIVNA 1408 000-57F 000-57F - ASMA Ver. 0.2.0 23 Jun 2016 09:49:49 Page 8 - - STMT FILE NAME - -1 C:\Users\srorso\Documents\GitHub\hyperion\tests\ieee-div-nans.asm - - -** NO ERRORS FOUND ** - - \ No newline at end of file diff --git a/tests/ieee-div-nans.tst b/tests/ieee-div-nans.tst deleted file mode 100644 index a01d25fdb..000000000 --- a/tests/ieee-div-nans.tst +++ /dev/null @@ -1,80 +0,0 @@ - -*Testcase ieee-div-nans.tst: IEEE-NaNs Test DIVIDE with zero, QNaNs and SNaNs -*Message Testcase ieee-div-nans.tst: IEEE Division with zero and NaNs -*Message ..Test case values include zero, QNaNs, and SNaNs - -sysclear -archmode esame -loadcore "$(testpath)/ieee-div-nans.core" -runtest .1 - -r 400.40 # Display short BFP results in test log -r 440.80 # Display long BFP results in test log -r 500.80 # Display extended BFP results in test log - -*Compare -r 400.10 # BFP Short quotients part 1 Expecting +inf, +inf, QNaN(1), QNaN(1) -*Want "DEB/DEBR NaN 1/4" 7F800000 7F800000 7FC10000 7FC10000 -*Compare -r 410.10 # BFP Short quotients part 2 Expecting QNaN(1), QNaN(1), QNaN(3), QNaN(3) -*Want "DEB/DEBR NaN 2/4" 7FC10000 7FC10000 7FC30000 7FC30000 -*Compare -r 420.10 # BFP Short quotients part 3 Expecting QNaN(3), QNaN(3), 0, 0 -*Want "DEB/DEBR NaN 3/4" 7FC30000 7FC30000 00000000 00000000 -*Compare -r 430.10 # BFP Short quotients part 4 Expecting QNaN(3), QNaN(3), 0, 0 -*Want "DEB/DEBR NaN 4/4" 00000000 00000000 00000000 00000000 - -*Compare -r 440.10 # BFP Long quotients part 1 Expecting +inf, +inf -*Want "DDB/DDBR NaN 1/8" 7FF00000 00000000 7FF00000 00000000 -*Compare -r 450.10 # BFP Long quotients part 2 Expecting QNaN(1), QNaN(1) -*Want "DDB/DDBR NaN 2/8" 7FF81000 00000000 7FF81000 00000000 -*Compare -r 460.10 # BFP Long quotients part 3 Expecting QNaN(1), QNaN(1) -*Want "DDB/DDBR NaN 3/8" 7FF81000 00000000 7FF81000 00000000 -*Compare -r 470.10 # BFP Long quotients part 4 Expecting QNaN(3), QNaN(3) -*Want "DDB/DDBR NaN 4/8" 7FF83000 00000000 7FF83000 00000000 -*Compare -r 480.10 # BFP Long quotients part 5 Expecting QNaN(3), QNaN(3) -*Want "DDB/DDBR NaN 5/8" 7FF83000 00000000 7FF83000 00000000 -*Compare -r 490.10 # BFP Long quotients part 6 Expecting 0, 0 -*Want "DDB/DDBR NaN 6/8" 00000000 00000000 00000000 00000000 -*Compare -r 4A0.10 # BFP Long quotients part 7 Expecting 0, 0 -*Want "DDB/DDBR NaN 7/8" 00000000 00000000 00000000 00000000 -*Compare -r 4B0.10 # BFP Long quotients part 8 Expecting 0, 0 -*Want "DDB/DDBR NaN 8/8" 00000000 00000000 00000000 00000000 - -*Compare -r 500.10 # BFP Extended quotients part 1 Expecting +inf -*Want "DXBR NaN 1/8" 7FFF0000 00000000 00000000 00000000 -*Compare -r 510.10 # BFP Extended quotients part 2 Expecting QNaN(1) -*Want "DXBR NaN 2/8" 7FFF8100 00000000 00000000 00000000 -*Compare -r 520.10 # BFP Extended quotients part 3 Expecting QNaN(1) -*Want "DXBR NaN 3/8" 7FFF8100 00000000 00000000 00000000 -*Compare -r 530.10 # BFP Extended quotients part 4 Expecting QNaN(3) -*Want "DXBR NaN 4/8" 7FFF8300 00000000 00000000 00000000 -*Compare -r 540.10 # BFP Extended quotients part 5 Expecting QNaN(3) -*Want "DXBR NaN 5/8" 7FFF8300 00000000 00000000 00000000 -*Compare -r 550.10 # BFP Extended quotients part 6 Expecting 0 -*Want "DXBR NaN 6/8" 00000000 00000000 00000000 00000000 -*Compare -r 560.10 # BFP Extended quotients part 7 Expecting 0 -*Want "DXBR NaN 7/8" 00000000 00000000 00000000 00000000 -*Compare -r 570.10 # BFP Extended quotients part 8 Expecting 0 -*Want "DXBR NaN 8/8" 00000000 00000000 00000000 00000000 - - -*Done - diff --git a/tests/ieee-divs.asm b/tests/ieee-divs.asm deleted file mode 100644 index dcfc7bf7f..000000000 --- a/tests/ieee-divs.asm +++ /dev/null @@ -1,203 +0,0 @@ -* -* Divide adjacent pairs of values in the input set (five values means four -* quotients). Test data: 1, 2, 4, -2, -2; expected quotients 0.5, 0.5, -2, 1 -* Load Floating Point Integer of the above result set. Expected values 0, 0, -2, 1 -* For short and long BFP, divide adjacent pairs using DIVIDE TO INTEGER. -* Expected quotient/remainder pairs: 0/1, 0/2, 2/0, 1/-0 (Yes, minus zero) -* -* Tests seven division instructions: -* DIVIDE (BFP short RRE) DEBR -* DIVIDE (BFP short RXE) DEB -* DIVIDE (BFP long, RRE) DDBR -* DIVIDE (BFP long, RXE) DDB -* DIVIDE (BFP extended, RRE) DXBR -* DIVIDE TO INTEGER (BFP short RRE) DIEBR -* DIVIDE TO INTEGER (BFP long RRE) DIDBR -* -* Also tests the following six conversion instructions -* LOAD ROUNDED (long BFP to short BFP, RRE) LEDBR -* LOAD ROUNDED (extended BFP to short BFP, RRE) LEXBR -* LOAD ROUNDED (extended BFP to long BFP, RRE) LDXBR -* LOAD FP INTEGER (BFP short RRE) FIEBR -* LOAD FP INTEGER (BFP long RRE) FIDBR -* LOAD FP INTEGER (BFP extended RRE) FIXBR -* -* Intermediate results from the Load Rounded instructions are not saved. Because -* zero is not present in the test set, any error in Load Rounded will appear in -* the resulting quotients, remainders, and integer floating point values. -* -* Also tests the following floating point support instructions -* LOAD (Short) -* LOAD (Long) -* LOAD ZERO (Long) -* STORE (Short) -* STORE (Long) -* -* -* -BFPDIVS START 0 -R0 EQU 0 -R1 EQU 1 -R2 EQU 2 -R3 EQU 3 -R4 EQU 4 -R5 EQU 5 -R6 EQU 6 -R7 EQU 7 -R8 EQU 8 -R9 EQU 9 -R10 EQU 10 -R11 EQU 11 -R12 EQU 12 -R13 EQU 13 -R14 EQU 14 -R15 EQU 15 - USING *,0 -* - ORG BFPDIVS+X'1A0' - DC X'0000000180000000',AD(STARTDIV) z/Arch restart PSW - ORG BFPDIVS+X'1D0' - DC X'0002000000000000000000000000DEAD' z/Arch pgm chk new PSW - ORG BFPDIVS+X'200' -* -* Mainline program. -STARTDIV STCTL R0,R0,CTLR0 Store CR0 to enable AFP - OI CTLR0+1,X'04' Turn on AFP bit - LCTL R0,R0,CTLR0 Reload updated CR0 - BAS R12,TESTDIV Perform divisions - LPSWE WAITPSW All done, load disabled wait PSW -* -* BFP Division Short RXE and RRE -* Use Load Rounded to shrink extended BFP into the shorts needed for this test. -* - ORG BFPDIVS+X'600' -TESTDIV DS 0H - LA R2,4 Set count of division operations - LA R3,SHORTRES Point to start of short BFP quotients - LA R4,SHORTDTI Point to short Divide Integer quotients and remainders - LA R5,SHORTLFP Point to short Load Floating Point Integer results - LA R7,EXTBFPIN Point to start of extended BFP input values - BASR R13,0 Set top of loop for short BFP tests -* -* Top of loop; clear residuals from FPR1, 4, 5, 8, 9. - LZDR R1 Zero FPR1 - LZDR R4 Zero FPR4 - LZDR R5 Zero FPR5 - LZDR R8 Zero FPR8 - LZDR R9 Zero FPR9 -* Collect dividend and divisor, do four divisions, store quotients. - LD R0,0(0,R7) Get BFP ext dividend part 1 - LD R2,8(0,R7) Get BFP ext dividend part 2 - LD R13,16(0,R7) Get BFP ext divisor part 1 - LD R15,24(0,R7) Get BFP ext divisor part 2 - LDXBR R1,R0 Round dividend for RXE to long - LEDBR R1,R1 Round dividend for RXE to short - LEXBR R5,R0 Round dividend for RRE - LER R9,R5 Save dividend for Divide to Integer - LEXBR R4,R13 Round divisor for RRE - STE R4,0(0,R3) Save divisor for RXE - DIEBR R9,R8,R4 Divide to Integer, quotient in R8, remainder in R9 - DEB R1,0(0,R3) Generate RXE - DEBR R5,R4 Generate RRE - FIEBR R4,0,R5 Load result as Floating Point Integer - STE R1,0(0,R3) Store short BFP RXE - STE R5,4(0,R3) Store short BFP RRE - STE R8,0(0,R4) Store divide to integer quotient - STE R9,4(0,R4) Store divide to integer remainder - STE R4,0(0,R5) Store load FP integer result - LA R7,16(0,R7) Point to next extended BFP input pair - LA R3,8(0,R3) Point to next short BFP result pair - LA R4,8(0,R4) Point to next Divide to Integer result - LA R5,4(0,R5) Point to next Load FP Integer result - BCTR R2,R13 Loop through all short BFP test cases -* -* BFP Division long RXE and RRE -* Use Load Rounded to shrink extended BFP input into the longs needed for this test. -* -TESTLONG DS 0H - LA R2,4 Set count of division operations - LA R3,LONGRES Point to start of long BFP quotients - LA R4,LONGDTI Point to short Divide Integer quotients and remainders - LA R5,LONGLFP Point to short Load Floating Point Integer results - LA R7,EXTBFPIN Point to start of extended BFP input values - BASR R13,0 Set top of loop for long BFP tests -* Top of loop -* Collect dividend and divisor, shorten them, do four divisions, store quotients - LD R0,0(0,R7) Get BFP ext dividend part 1 - LD R2,8(0,R7) Get BFP ext dividend part 2 - LD R13,16(0,R7) Get BFP ext divisor part 1 - LD R15,24(0,R7) Get BFP ext divisor part 2 - LDXBR R1,R0 Round dividend for RXE - LDXBR R5,R0 Round dividend for RRE - LDR R9,R5 Save dividend for divide to Integer - LDXBR R4,R13 Round divisor for RRE - STD R4,0(0,R3) Save divisor for RXE - DIDBR R9,R8,R4 Divide to Integer, quotient in R8, remainder in R9 - DDB R1,0(0,R3) Generate RXE long - DDBR R5,R4 Generate RRE long - FIDBR R4,0,R5 Load result as Floating Point Integer - STD R1,0(0,R3) Store long BFP RXE quotient - STD R5,8(0,R3) Store long BFP RRE quotient - STD R8,0(0,R4) Store long BFP divide to integer quotient - STD R9,8(0,R4) Store long BFP divide to integer remainder - STD R4,0(0,R5) Store long BFP load FP integer result - LA R7,16(0,R7) Point to next extended BFP input pair - LA R3,16(0,R3) Point to next long BFP result pair - LA R4,16(0,R4) Point to next long BFP divide to integer quotient and remainder - LA R5,8(0,R5) Point to next long BFP Load FP Integer result - BCTR R2,R13 Loop through all long test cases -* -* BFP division extended, RRE only. We do two divisions per input pair so we can -* test a diversity of Load Rounded instructions. -* -TESTEXT DS 0H - LA R2,4 Set count of division operations - LA R4,EXTDRES Point to start of extended BFP quotients - LA R5,EXTLFP Point to start of extended Load FP Integer results - LA R7,EXTBFPIN Point to start of extended BFP input values - BASR R13,0 Set top of loop for l*l tests -* Top of loop -* Collect dividend & divisor, do division and Load FP Integer, store results. - LD R0,0(0,R7) Get BFP ext dividend part 1 - LD R2,8(0,R7) Get BFP ext dividend part 2 - LD R13,16(0,R7) Get BFP ext divisor part 1 - LD R15,24(0,R7) Get BFP ext divisor part 2 - DXBR R0,R13 Generate RRE extended quotient - FIXBR R1,0,R0 create Load FP Integer result - STD R0,0(0,R4) Store extended BFP RRE quotient part 1 - STD R2,8(0,R4) Store extended BFP RRE quotient part 2 - STD R1,0(0,R5) Store extended BFP Load FP Integer part 1 - STD R3,8(0,R5) Store extended BFP Load FP Integer part 2 - LA R7,16(0,R7) Point to next extended BFP input pair - LA R4,16(0,R4) Point to next extended BFP result - LA R5,16(0,R5) Point to next extended BFP Load FP Result - BCTR R2,R13 Loop through all test cases -* - BR R12 Tests done, return to mainline -* -* -CTLR0 DS F Control register 0 (bit45 AFP control) - DS 0D Ensure doubleword alignment -WAITPSW DC X'00020000000000000000000000000000' Disabled wait state PSW - normal completion -* - ORG BFPDIVS+X'300' -EXTBFPIN DS 0D - DC X'3FFF0000000000000000000000000000' 1.0 BFP Extended - DC X'40000000000000000000000000000000' 2.0 BFP Extended - DC X'40010000000000000000000000000000' 4.0 BFP Extended - DC X'C0000000000000000000000000000000' -2.0 BFP Extended - DC X'C0000000000000000000000000000000' -2.0 BFP Extended -* - ORG BFPDIVS+X'420' -SHORTRES DS 8F 420.20 Results from short divide, four pairs -LONGRES DS 8D 440.40 Results from long divide, four pairs -EXTDRES DS 8D 480.40 Results from extended divide, four results -SHORTDTI DS 8F 4C0.20 Results from short Divide to Integer, four quotient/remainder pairs -SHORTLFP DS 4F 4E0.10 Results from short Load Floating Point Integer, four results -* - ORG BFPDIVS+X'500' -LONGDTI DS 8D 500.40 Results from long Divide to Integer, four quotient/remainder pairs -LONGLFP DS 4D 540.20 Results from long Load Floating Point Integer, four results -EXTLFP DS 8D 560.40 Results from Extended Load Floating Point Integer, four results -* - END \ No newline at end of file diff --git a/tests/ieee-divs.core b/tests/ieee-divs.core deleted file mode 100644 index 8c8457811..000000000 Binary files a/tests/ieee-divs.core and /dev/null differ diff --git a/tests/ieee-divs.list b/tests/ieee-divs.list deleted file mode 100644 index c63b0f2a4..000000000 --- a/tests/ieee-divs.list +++ /dev/null @@ -1,283 +0,0 @@ -ASMA Ver. 0.2.0 23 Jun 2016 09:49:49 Page 1 - - LOC OBJECT CODE ADDR1 ADDR2 STMT - - 1 * - 2 * Divide adjacent pairs of values in the input set (five values means four - 3 * quotients). Test data: 1, 2, 4, -2, -2; expected quotients 0.5, 0.5, -2, 1 - 4 * Load Floating Point Integer of the above result set. Expected values 0, 0, -2, 1 - 5 * For short and long BFP, divide adjacent pairs using DIVIDE TO INTEGER. - 6 * Expected quotient/remainder pairs: 0/1, 0/2, 2/0, 1/-0 (Yes, minus zero) - 7 * - 8 * Tests seven division instructions: - 9 * DIVIDE (BFP short RRE) DEBR - 10 * DIVIDE (BFP short RXE) DEB - 11 * DIVIDE (BFP long, RRE) DDBR - 12 * DIVIDE (BFP long, RXE) DDB - 13 * DIVIDE (BFP extended, RRE) DXBR - 14 * DIVIDE TO INTEGER (BFP short RRE) DIEBR - 15 * DIVIDE TO INTEGER (BFP long RRE) DIDBR - 16 * - 17 * Also tests the following six conversion instructions - 18 * LOAD ROUNDED (long BFP to short BFP, RRE) LEDBR - 19 * LOAD ROUNDED (extended BFP to short BFP, RRE) LEXBR - 20 * LOAD ROUNDED (extended BFP to long BFP, RRE) LDXBR - 21 * LOAD FP INTEGER (BFP short RRE) FIEBR - 22 * LOAD FP INTEGER (BFP long RRE) FIDBR - 23 * LOAD FP INTEGER (BFP extended RRE) FIXBR - 24 * - 25 * Intermediate results from the Load Rounded instructions are not saved. Because - 26 * zero is not present in the test set, any error in Load Rounded will appear in - 27 * the resulting quotients, remainders, and integer floating point values. - 28 * - 29 * Also tests the following floating point support instructions - 30 * LOAD (Short) - 31 * LOAD (Long) - 32 * LOAD ZERO (Long) - 33 * STORE (Short) - 34 * STORE (Long) - 35 * - 36 * - 37 * - 0000000000000000 0000000000000757 38 BFPDIVS START 0 - 0000000000000000 0000000000000001 39 R0 EQU 0 - 0000000000000001 0000000000000001 40 R1 EQU 1 - 0000000000000002 0000000000000001 41 R2 EQU 2 - 0000000000000003 0000000000000001 42 R3 EQU 3 - 0000000000000004 0000000000000001 43 R4 EQU 4 - 0000000000000005 0000000000000001 44 R5 EQU 5 - 0000000000000006 0000000000000001 45 R6 EQU 6 - 0000000000000007 0000000000000001 46 R7 EQU 7 - 0000000000000008 0000000000000001 47 R8 EQU 8 - 0000000000000009 0000000000000001 48 R9 EQU 9 - 000000000000000A 0000000000000001 49 R10 EQU 10 - 000000000000000B 0000000000000001 50 R11 EQU 11 - 000000000000000C 0000000000000001 51 R12 EQU 12 - 000000000000000D 0000000000000001 52 R13 EQU 13 - ASMA Ver. 0.2.0 23 Jun 2016 09:49:49 Page 2 - - LOC OBJECT CODE ADDR1 ADDR2 STMT - - 000000000000000E 0000000000000001 53 R14 EQU 14 - 000000000000000F 0000000000000001 54 R15 EQU 15 -0000000000000000 0000000000000000 55 USING *,0 - 56 * -0000000000000000 0000000000000000 00000000000001A0 57 ORG BFPDIVS+X'1A0' -00000000000001A0 00000001 80000000 58 DC X'0000000180000000',AD(STARTDIV) z/Arch restart PSW -00000000000001B0 00000000000001B0 00000000000001D0 59 ORG BFPDIVS+X'1D0' -00000000000001D0 00020000 00000000 60 DC X'0002000000000000000000000000DEAD' z/Arch pgm chk new PSW -00000000000001E0 00000000000001E0 0000000000000200 61 ORG BFPDIVS+X'200' - 62 * - 63 * Mainline program. -0000000000000200 B600 0744 0000000000000744 64 STARTDIV STCTL R0,R0,CTLR0 Store CR0 to enable AFP -0000000000000204 9604 0745 0000000000000745 65 OI CTLR0+1,X'04' Turn on AFP bit -0000000000000208 B700 0744 0000000000000744 66 LCTL R0,R0,CTLR0 Reload updated CR0 -000000000000020C 4DC0 0600 0000000000000600 67 BAS R12,TESTDIV Perform divisions -0000000000000210 B2B2 0748 0000000000000748 68 LPSWE WAITPSW All done, load disabled wait PSW - 69 * - 70 * BFP Division Short RXE and RRE - 71 * Use Load Rounded to shrink extended BFP into the shorts needed for this test. - 72 * -0000000000000214 0000000000000214 0000000000000600 73 ORG BFPDIVS+X'600' -0000000000000600 74 TESTDIV DS 0H -0000000000000600 4120 0004 0000000000000004 75 LA R2,4 Set count of division operations -0000000000000604 4130 0420 0000000000000420 76 LA R3,SHORTRES Point to start of short BFP quotients -0000000000000608 4140 04C0 00000000000004C0 77 LA R4,SHORTDTI Point to short Divide Integer quotients and remainders -000000000000060C 4150 04E0 00000000000004E0 78 LA R5,SHORTLFP Point to short Load Floating Point Integer results -0000000000000610 4170 0300 0000000000000300 79 LA R7,EXTBFPIN Point to start of extended BFP input values -0000000000000614 0DD0 80 BASR R13,0 Set top of loop for short BFP tests - 81 * - 82 * Top of loop; clear residuals from FPR1, 4, 5, 8, 9. -0000000000000616 B375 0010 83 LZDR R1 Zero FPR1 -000000000000061A B375 0040 84 LZDR R4 Zero FPR4 -000000000000061E B375 0050 85 LZDR R5 Zero FPR5 -0000000000000622 B375 0080 86 LZDR R8 Zero FPR8 -0000000000000626 B375 0090 87 LZDR R9 Zero FPR9 - 88 * Collect dividend and divisor, do four divisions, store quotients. -000000000000062A 6800 7000 0000000000000000 89 LD R0,0(0,R7) Get BFP ext dividend part 1 -000000000000062E 6820 7008 0000000000000008 90 LD R2,8(0,R7) Get BFP ext dividend part 2 -0000000000000632 68D0 7010 0000000000000010 91 LD R13,16(0,R7) Get BFP ext divisor part 1 -0000000000000636 68F0 7018 0000000000000018 92 LD R15,24(0,R7) Get BFP ext divisor part 2 -000000000000063A B345 0010 93 LDXBR R1,R0 Round dividend for RXE to long -000000000000063E B344 0011 94 LEDBR R1,R1 Round dividend for RXE to short -0000000000000642 B346 0050 95 LEXBR R5,R0 Round dividend for RRE -0000000000000646 3895 96 LER R9,R5 Save dividend for Divide to Integer -0000000000000648 B346 004D 97 LEXBR R4,R13 Round divisor for RRE -000000000000064C 7040 3000 0000000000000000 98 STE R4,0(0,R3) Save divisor for RXE -0000000000000650 B353 8094 99 DIEBR R9,R8,R4 Divide to Integer, quotient in R8, remainder in R9 -0000000000000654 ED10 3000 000D 0000000000000000 100 DEB R1,0(0,R3) Generate RXE -000000000000065A B30D 0054 101 DEBR R5,R4 Generate RRE -000000000000065E B357 0045 102 FIEBR R4,0,R5 Load result as Floating Point Integer -0000000000000662 7010 3000 0000000000000000 103 STE R1,0(0,R3) Store short BFP RXE -0000000000000666 7050 3004 0000000000000004 104 STE R5,4(0,R3) Store short BFP RRE - ASMA Ver. 0.2.0 23 Jun 2016 09:49:49 Page 3 - - LOC OBJECT CODE ADDR1 ADDR2 STMT - -000000000000066A 7080 4000 0000000000000000 105 STE R8,0(0,R4) Store divide to integer quotient -000000000000066E 7090 4004 0000000000000004 106 STE R9,4(0,R4) Store divide to integer remainder -0000000000000672 7040 5000 0000000000000000 107 STE R4,0(0,R5) Store load FP integer result -0000000000000676 4170 7010 0000000000000010 108 LA R7,16(0,R7) Point to next extended BFP input pair -000000000000067A 4130 3008 0000000000000008 109 LA R3,8(0,R3) Point to next short BFP result pair -000000000000067E 4140 4008 0000000000000008 110 LA R4,8(0,R4) Point to next Divide to Integer result -0000000000000682 4150 5004 0000000000000004 111 LA R5,4(0,R5) Point to next Load FP Integer result -0000000000000686 062D 112 BCTR R2,R13 Loop through all short BFP test cases - 113 * - 114 * BFP Division long RXE and RRE - 115 * Use Load Rounded to shrink extended BFP input into the longs needed for this test. - 116 * -0000000000000688 117 TESTLONG DS 0H -0000000000000688 4120 0004 0000000000000004 118 LA R2,4 Set count of division operations -000000000000068C 4130 0440 0000000000000440 119 LA R3,LONGRES Point to start of long BFP quotients -0000000000000690 4140 0500 0000000000000500 120 LA R4,LONGDTI Point to short Divide Integer quotients and remainders -0000000000000694 4150 0540 0000000000000540 121 LA R5,LONGLFP Point to short Load Floating Point Integer results -0000000000000698 4170 0300 0000000000000300 122 LA R7,EXTBFPIN Point to start of extended BFP input values -000000000000069C 0DD0 123 BASR R13,0 Set top of loop for long BFP tests - 124 * Top of loop - 125 * Collect dividend and divisor, shorten them, do four divisions, store quotients -000000000000069E 6800 7000 0000000000000000 126 LD R0,0(0,R7) Get BFP ext dividend part 1 -00000000000006A2 6820 7008 0000000000000008 127 LD R2,8(0,R7) Get BFP ext dividend part 2 -00000000000006A6 68D0 7010 0000000000000010 128 LD R13,16(0,R7) Get BFP ext divisor part 1 -00000000000006AA 68F0 7018 0000000000000018 129 LD R15,24(0,R7) Get BFP ext divisor part 2 -00000000000006AE B345 0010 130 LDXBR R1,R0 Round dividend for RXE -00000000000006B2 B345 0050 131 LDXBR R5,R0 Round dividend for RRE -00000000000006B6 2895 132 LDR R9,R5 Save dividend for divide to Integer -00000000000006B8 B345 004D 133 LDXBR R4,R13 Round divisor for RRE -00000000000006BC 6040 3000 0000000000000000 134 STD R4,0(0,R3) Save divisor for RXE -00000000000006C0 B35B 8094 135 DIDBR R9,R8,R4 Divide to Integer, quotient in R8, remainder in R9 -00000000000006C4 ED10 3000 001D 0000000000000000 136 DDB R1,0(0,R3) Generate RXE long -00000000000006CA B31D 0054 137 DDBR R5,R4 Generate RRE long -00000000000006CE B35F 0045 138 FIDBR R4,0,R5 Load result as Floating Point Integer -00000000000006D2 6010 3000 0000000000000000 139 STD R1,0(0,R3) Store long BFP RXE quotient -00000000000006D6 6050 3008 0000000000000008 140 STD R5,8(0,R3) Store long BFP RRE quotient -00000000000006DA 6080 4000 0000000000000000 141 STD R8,0(0,R4) Store long BFP divide to integer quotient -00000000000006DE 6090 4008 0000000000000008 142 STD R9,8(0,R4) Store long BFP divide to integer remainder -00000000000006E2 6040 5000 0000000000000000 143 STD R4,0(0,R5) Store long BFP load FP integer result -00000000000006E6 4170 7010 0000000000000010 144 LA R7,16(0,R7) Point to next extended BFP input pair -00000000000006EA 4130 3010 0000000000000010 145 LA R3,16(0,R3) Point to next long BFP result pair -00000000000006EE 4140 4010 0000000000000010 146 LA R4,16(0,R4) Point to next long BFP divide to integer quotient and remainder -00000000000006F2 4150 5008 0000000000000008 147 LA R5,8(0,R5) Point to next long BFP Load FP Integer result -00000000000006F6 062D 148 BCTR R2,R13 Loop through all long test cases - 149 * - 150 * BFP division extended, RRE only. We do two divisions per input pair so we can - 151 * test a diversity of Load Rounded instructions. - 152 * -00000000000006F8 153 TESTEXT DS 0H -00000000000006F8 4120 0004 0000000000000004 154 LA R2,4 Set count of division operations -00000000000006FC 4140 0480 0000000000000480 155 LA R4,EXTDRES Point to start of extended BFP quotients -0000000000000700 4150 0560 0000000000000560 156 LA R5,EXTLFP Point to start of extended Load FP Integer results - ASMA Ver. 0.2.0 23 Jun 2016 09:49:49 Page 4 - - LOC OBJECT CODE ADDR1 ADDR2 STMT - -0000000000000704 4170 0300 0000000000000300 157 LA R7,EXTBFPIN Point to start of extended BFP input values -0000000000000708 0DD0 158 BASR R13,0 Set top of loop for l*l tests - 159 * Top of loop - 160 * Collect dividend & divisor, do division and Load FP Integer, store results. -000000000000070A 6800 7000 0000000000000000 161 LD R0,0(0,R7) Get BFP ext dividend part 1 -000000000000070E 6820 7008 0000000000000008 162 LD R2,8(0,R7) Get BFP ext dividend part 2 -0000000000000712 68D0 7010 0000000000000010 163 LD R13,16(0,R7) Get BFP ext divisor part 1 -0000000000000716 68F0 7018 0000000000000018 164 LD R15,24(0,R7) Get BFP ext divisor part 2 -000000000000071A B34D 000D 165 DXBR R0,R13 Generate RRE extended quotient -000000000000071E B347 0010 166 FIXBR R1,0,R0 create Load FP Integer result -0000000000000722 6000 4000 0000000000000000 167 STD R0,0(0,R4) Store extended BFP RRE quotient part 1 -0000000000000726 6020 4008 0000000000000008 168 STD R2,8(0,R4) Store extended BFP RRE quotient part 2 -000000000000072A 6010 5000 0000000000000000 169 STD R1,0(0,R5) Store extended BFP Load FP Integer part 1 -000000000000072E 6030 5008 0000000000000008 170 STD R3,8(0,R5) Store extended BFP Load FP Integer part 2 -0000000000000732 4170 7010 0000000000000010 171 LA R7,16(0,R7) Point to next extended BFP input pair -0000000000000736 4140 4010 0000000000000010 172 LA R4,16(0,R4) Point to next extended BFP result -000000000000073A 4150 5010 0000000000000010 173 LA R5,16(0,R5) Point to next extended BFP Load FP Result -000000000000073E 062D 174 BCTR R2,R13 Loop through all test cases - 175 * -0000000000000740 07FC 176 BR R12 Tests done, return to mainline - 177 * - 178 * -0000000000000744 00000000 179 CTLR0 DS F Control register 0 (bit45 AFP control) -0000000000000748 180 DS 0D Ensure doubleword alignment -0000000000000748 00020000 00000000 181 WAITPSW DC X'00020000000000000000000000000000' Disabled wait state PSW - normal completion - 182 * -0000000000000758 0000000000000758 0000000000000300 183 ORG BFPDIVS+X'300' -0000000000000300 184 EXTBFPIN DS 0D -0000000000000300 3FFF0000 00000000 185 DC X'3FFF0000000000000000000000000000' 1.0 BFP Extended -0000000000000310 40000000 00000000 186 DC X'40000000000000000000000000000000' 2.0 BFP Extended -0000000000000320 40010000 00000000 187 DC X'40010000000000000000000000000000' 4.0 BFP Extended -0000000000000330 C0000000 00000000 188 DC X'C0000000000000000000000000000000' -2.0 BFP Extended -0000000000000340 C0000000 00000000 189 DC X'C0000000000000000000000000000000' -2.0 BFP Extended - 190 * -0000000000000350 0000000000000350 0000000000000420 191 ORG BFPDIVS+X'420' -0000000000000420 00000000 00000000 192 SHORTRES DS 8F 420.20 Results from short divide, four pairs -0000000000000440 00000000 00000000 193 LONGRES DS 8D 440.40 Results from long divide, four pairs -0000000000000480 00000000 00000000 194 EXTDRES DS 8D 480.40 Results from extended divide, four results -00000000000004C0 00000000 00000000 195 SHORTDTI DS 8F 4C0.20 Results from short Divide to Integer, four quotient/remainder pairs -00000000000004E0 00000000 00000000 196 SHORTLFP DS 4F 4E0.10 Results from short Load Floating Point Integer, four results - 197 * -00000000000004F0 00000000000004F0 0000000000000500 198 ORG BFPDIVS+X'500' -0000000000000500 00000000 00000000 199 LONGDTI DS 8D 500.40 Results from long Divide to Integer, four quotient/remainder pairs -0000000000000540 00000000 00000000 200 LONGLFP DS 4D 540.20 Results from long Load Floating Point Integer, four results -0000000000000560 00000000 00000000 201 EXTLFP DS 8D 560.40 Results from Extended Load Floating Point Integer, four results - 202 * -00000000000005A0 203 END - ASMA Ver. 0.2.0 23 Jun 2016 09:49:49 Page 5 - - SYMBOL TYPE VALUE LENGTH DEFN REFERENCES - -BFPDIVS J 000000 1880 38 57 59 61 73 183 191 198 -CTLR0 F 000744 4 179 64 65 66 -EXTBFPIN D 000300 8 184 79 122 157 -EXTDRES D 000480 8 194 155 -EXTLFP D 000560 8 201 156 -IMAGE 1 000000 1880 0 -LONGDTI D 000500 8 199 120 -LONGLFP D 000540 8 200 121 -LONGRES D 000440 8 193 119 -R0 U 000000 1 39 64 66 89 93 95 126 130 131 161 165 166 167 -R1 U 000001 1 40 83 93 94 100 103 130 136 139 166 169 -R10 U 00000A 1 49 -R11 U 00000B 1 50 -R12 U 00000C 1 51 67 176 -R13 U 00000D 1 52 80 91 97 112 123 128 133 148 158 163 165 174 -R14 U 00000E 1 53 -R15 U 00000F 1 54 92 129 164 -R2 U 000002 1 41 75 90 112 118 127 148 154 162 168 174 -R3 U 000003 1 42 76 98 100 103 104 109 119 134 136 139 140 145 170 -R4 U 000004 1 43 77 84 97 98 99 101 102 105 106 107 110 120 133 134 135 137 138 - 141 142 143 146 155 167 168 172 -R5 U 000005 1 44 78 85 95 96 101 102 104 107 111 121 131 132 137 138 140 143 147 - 156 169 170 173 -R6 U 000006 1 45 -R7 U 000007 1 46 79 89 90 91 92 108 122 126 127 128 129 144 157 161 162 163 164 - 171 -R8 U 000008 1 47 86 99 105 135 141 -R9 U 000009 1 48 87 96 99 106 132 135 142 -SHORTDTI F 0004C0 4 195 77 -SHORTLFP F 0004E0 4 196 78 -SHORTRES F 000420 4 192 76 -STARTDIV I 000200 4 64 58 -TESTDIV H 000600 2 74 67 -TESTEXT H 0006F8 2 153 -TESTLONG H 000688 2 117 -WAITPSW X 000748 16 181 68 - ASMA Ver. 0.2.0 23 Jun 2016 09:49:49 Page 6 - -MACRO DEFN REFERENCES - -No defined macros - ASMA Ver. 0.2.0 23 Jun 2016 09:49:49 Page 7 - - DESC SYMBOL SIZE POS ADDR - -Entry: 0 - -Image IMAGE 1880 000-757 000-757 - Region 1880 000-757 000-757 - CSECT BFPDIVS 1880 000-757 000-757 - ASMA Ver. 0.2.0 23 Jun 2016 09:49:49 Page 8 - - STMT FILE NAME - -1 C:\Users\srorso\Documents\GitHub\hyperion\tests\ieee-divs.asm - - -** NO ERRORS FOUND ** - - \ No newline at end of file diff --git a/tests/ieee-divs.tst b/tests/ieee-divs.tst deleted file mode 100644 index 3251911ed..000000000 --- a/tests/ieee-divs.tst +++ /dev/null @@ -1,99 +0,0 @@ -*Testcase ieee-divs.tst: Load and Divide tests -*Message Testcase ieee-divs.tst: LOAD ROUNDED (3), LOAD FP INTEGER (3), -*Message ..DIVIDE (5), DIVIDE TO INTEGER (2), 13 instructions total -*Message ..Test case values generate integer and fractional results. - -sysclear -archmode esame -loadcore "$(testpath)/ieee-divs.core" -runtest .1 - -r 420.20 # Display short BFP results in test log -r 4C0.20 # Display short BFP Divide to Integer results in test log -r 4E0.10 # Display short BFP Load FP Integer results in test log -r 440.40 # Display long BFP results in test log -r 500.40 # Display long BFP Divide to Integer results in test log -r 540.20 # Display long BFP Load FP Integer results in test log -r 480.40 # Display extended BFP results in test log -r 560.40 # Display extended BFP Load FP Integer results in test log - -*Compare -r 420.10 # BFP Short quotients part 1 Expecting 0.5 0.5 0.5 0.5 -*Want "DEB/DEBR test pairs 1-2" 3F000000 3F000000 3F000000 3F000000 -*Compare -r 430.10 # BFP Short quotients part 2 Expecting -2 -2 1 1 -*Want "DEB/DEBR test pairs 3-4" C0000000 C0000000 3F800000 3F800000 - -*Compare -r 4C0.10 # BFP Short Divide to Integer part 1 Expecting 0.0 1.0 0.0 2.0 -*Want "DIEBR tests 1-2" 00000000 3F800000 00000000 40000000 -*Compare -r 4D0.10 # BFP Short Divide to Integer part 2 Expecting -2.0 0.0 1.0 -0.0 -*Want "DIEBR tests 3-4" C0000000 00000000 3F800000 80000000 -# Yup, -0. Remainder sign in DIEBR is exclusive or of divisor and dividend signs. - -*Compare -r 4E0.10 # BFP Short Load FP Integer Expecting 0.0 0.0 -2.0 1.0 -*Want "FIEBR tests 1-4" 00000000 00000000 C0000000 3F800000 - -*Compare -r 440.10 # BFP Long quotients part 1 Expecting 0.5 0.5 -*Want "DDB/DDBR test pair 1" 3FE00000 00000000 3FE00000 00000000 -*Compare -r 450.10 # BFP Long quotients part 2 Expecting 0.5 0.5 -*Want "DDB/DDBR test pair 2" 3FE00000 00000000 3FE00000 00000000 -*Compare -r 460.10 # BFP Long quotients part 3 Expecting -2.0 -2.0 -*Want "DDB/DDBR test pair 3" C0000000 00000000 C0000000 00000000 -*Compare -r 470.10 # BFP Long quotients part 4 Expecting 1.0 1.0 -*Want "DDB/DDBR test pair 4" 3FF00000 00000000 3FF00000 00000000 - -*Compare -r 500.10 # BFP Long divide to integer part 1 Expecting 0.0 1.0 -*Want "DIDBR test 1" 00000000 00000000 3FF00000 00000000 -*Compare -r 510.10 # BFP Long divide to integer part 2 Expecting 0.0 2.0 -*Want "DIDBR test 2" 00000000 00000000 40000000 00000000 -*Compare -r 520.10 # BFP Long divide to integer part 3 Expecting -2.0 0.0 -*Want "DIDBR test 3" C0000000 00000000 00000000 00000000 -*Compare -r 530.10 # BFP Long divide to integer part 4 Expecting 1.0 -0 -*Want "DIDBR test 4" 3FF00000 00000000 80000000 00000000 - -*Compare -r 540.10 # BFP Long Load FP Integer Expecting 0.0 0.0 -*Want "FIDBR test 1" 00000000 00000000 00000000 00000000 -*Compare -r 550.10 # Short Load FP Integer Expecting -2.0 1.0 -*Want "FIDBR test 2" C0000000 00000000 3FF00000 00000000 - -*Compare -r 480.10 # BFP Extended quotients part 1 -*Want "DXBR test 1" 3FFE0000 00000000 00000000 00000000 -*Compare -r 490.10 # BFP Extended quotients part 2 -*Want "DXBR test 2" 3FFE0000 00000000 00000000 00000000 -*Compare -r 4A0.10 # BFP Extended quotients part 3 -*Want "DXBR test 3" C0000000 00000000 00000000 00000000 -*Compare -r 4B0.10 # BFP Extended quotients part 4 -*Want "DXBR test 4" 3FFF0000 00000000 00000000 00000000 - -*Compare -r 560.10 # BFP Extended load FP integer part 1 Expecting 0.0 -*Want "FIXBR test 1" 00000000 00000000 00000000 00000000 -*Compare -r 570.10 # BFP Extended load FP integer part 2 Expecting 0.0 -*Want "FIXBR test 2" 00000000 00000000 00000000 00000000 -*Compare -r 580.10 # BFP Extended load FP integer part 3 Expecting -2.0 -*Want "FIXBR test 3" C0000000 00000000 00000000 00000000 -*Compare -r 590.10 # BFP Extended load FP integer part 4 Expecting 1.0 -*Want "FIXBR test 4" 3FFF0000 00000000 00000000 00000000 - -*Done - diff --git a/tests/ieee-mults.asm b/tests/ieee-mults.asm deleted file mode 100644 index 8f3d706bd..000000000 --- a/tests/ieee-mults.asm +++ /dev/null @@ -1,242 +0,0 @@ -* -* 1. Multiply adjacent pairs of values in the input set (five values means four -* products). -* Test data: 1, 2, 4, -2, -2; expected products 2, 8, -8, 4 -* -* 2. Multiply adjacent pairs of values in the input set and add the first value -* in the pair to the product (five values means four results). -* Test data: 1, 2, 4, -2, -2; expected results 3, 10, -4, 2 -* -* 3. Multiply adjacent pairs of values in the input set and subtract the first -* value in the pair from the product (five values means four results). -* Test data: 1, 2, 4, -2, -2; expected results 1, 6, -12, 6 -* -* Tests 17 multiplication instructions: -* MULTIPLY (BFP short x short -> short, RRE) MEEBR -* MULTIPLY (BFP short x short -> short, RXE) MEEB -* MULTIPLY (BFP short x short -> long, RRE) MDEBR -* MULTIPLY (BFP short x short -> long, RXE) MDEB -* MULTIPLY (BFP long x long -> long, RRE) MDBR -* MULTIPLY (BFP long x long -> long, RXE) MDB -* MULTIPLY (BFP long x long -> extended, RRE) MXDBR -* MULTIPLY (BFP long x long -> extended, RXE) MXDB -* MULTIPLY (BFP long x long -> extended, RRE) MXDBR -* MULTIPLY AND ADD (BFP short x short -> short, RRE) MAEBR -* MULTIPLY AND ADD (BFP short x short -> short, RXE) MAEB -* MULTIPLY AND ADD (BFP long x long -> long, RRE) MADBR -* MULTIPLY AND ADD (BFP long x long -> long, RXE) MADB -* MULTIPLY AND SUBTRACT (BFP short x short -> short, RRE) MSEBR -* MULTIPLY AND SUBTRACT (BFP short x short -> short, RXE) MSEB -* MULTIPLY AND SUBTRACT (BFP long x long -> long, RRE) MSDBR -* MULTIPLY AND SUBTRACT (BFP long x long -> long, RXE) MSDB -* -* Also tests the following six conversion instructions -* LOAD LENGTHENED (short BFP to long BFP, RXE) -* LOAD LENGTHENED (short BFP to extended BFP, RXE) -* LOAD LENGTHENED (long BFP to extended BFP, RXE) -* LOAD LENGTHENED (short BFP to long BFP, RRE) -* LOAD LENGTHENED (short BFP to extended BFP, RRE) -* LOAD LENGTHENED (long BFP to extended BFP, RRE) -* -* Intermediate results from the Load Lengthened instructions are not saved. Because -* zero is not present in the input test set, any error in Load Lengthened will appear -* in the resulting products -* -* Also tests the following floating point support instructions -* LOAD (Short) -* LOAD (Long) -* LOAD ZERO (Long) -* STORE (Short) -* STORE (Long) -* -BFPMULTS START 0 -R0 EQU 0 -R1 EQU 1 -R2 EQU 2 -R3 EQU 3 -R4 EQU 4 -R5 EQU 5 -R6 EQU 6 -R7 EQU 7 -R8 EQU 8 -R9 EQU 9 -R10 EQU 10 -R11 EQU 11 -R12 EQU 12 -R13 EQU 13 -R14 EQU 14 -R15 EQU 15 - USING *,0 - ORG BFPMULTS+X'1A0' - DC X'0000000180000000',AD(STARTMUL) z/Arch restart PSW - ORG BFPMULTS+X'1D0' - DC X'0002000000000000000000000000DEAD' z/Arch pgm chk new PSW - ORG BFPMULTS+X'200' -* -* -STARTMUL STCTL R0,R0,CTLR0 Store CR0 to enable AFP - OI CTLR0+1,X'04' Turn on AFP bit - LCTL R0,R0,CTLR0 Reload updated CR0 - BAL R12,TESTMULT Perform multiplications - LPSWE WAITPSW All done, load disabled wait PSW -* -* BFP Multiplication Short x Short -> Short & Short x Short -> Long, RXE and RRE -* - ORG BFPMULTS+X'600' -TESTMULT DS 0H - LA R2,4 Set count of multiplication operations - LA R3,SHORTRES Point to start of short BFP products - LA R4,LONGRES1 Point to start of long BFP products - LA R5,SHORTMAD Point to start of short BFP Mult-Add results - LA R6,SHORTMSB Point to start of short BFP Mult-Sub results - LA R7,SHORTBFP Point to start of short BFP input values - BASR R13,0 Set top of loop -* Top of loop; clear residuals from FP registers - LZDR R0 Zero FPR0 - LZDR R1 Zero FPR1 - LZDR R4 Zero FPR4 - LZDR R5 Zero FPR5 - LZDR R13 Zero FPR13 -* Collect multiplicand and multiplier, do four multiplications, store results. - LE R0,0(0,R7) Get BFP short multiplicand - LE R13,4(0,R7) Get BFP short multiplier - LER R1,R0 Copy multiplicand for s*s->s RRE - LER R4,R0 Copy multiplicand for s*s->l RXE - LER R5,R0 Copy multiplicand for s*s->l RRE - MEEB R0,4(0,R7) Generate RXE s*s->s product - MEEBR R1,R13 Generate RRE s*s->s product - MDEB R4,4(0,R7) Generate RXE s*s->l product - MDEBR R5,R13 Generate RRE s*s->l product - STE R0,0(0,R3) Store short BFP RXE s*s->s product - STE R1,4(0,R3) Store short BFP RRE s*s->s product - STE R4,0(0,R4) Store short BFP RXE s*s->l product - STE R5,8(0,R4) Store short BFP RRE s*s->l product - LE R0,0(0,R7) Reload BFP short multiplicand for mult-add RXE - LER R1,R0 Copy multiplicand for mult-add RRE - MAEB R0,R0,4(0,R7) Multiply third by second, add to first RXE - MAEBR R1,R13,R1 Multiply third by second, add to the first RRE - STE R0,0(0,R5) Store short BFP RXE mult-add result - STE R1,4(0,R5) Store short BFP RRE mult-add result - LE R0,0(0,R7) Reload BFP short multiplicand for mult-sub RXE - LER R1,R0 Copy multiplicand for mult-sub RRE - MSEB R0,R0,4(0,R7) Multiply third by second, subtract the first RXE - MSEBR R1,R13,R1 Multiply third by second, subtract the first RRE - STE R0,0(0,R6) Store short BFP RXE mult-sub result - STE R1,4(0,R6) Store short BFP RRE mult-sub result - LA R7,4(0,R7) Point to next short BFP input pair - LA R3,8(0,R3) Point to next short BFP product pair - LA R4,16(0,R4) Point to next long BFP product pair - LA R5,8(0,R5) Point to next short BFP mult-add result pair - LA R6,8(0,R6) Point to next short BFP mult-sub result pair - BCTR R2,R13 Loop through all s*s test cases -* -* BFP Multiplication long x long -> long & long x long -> extended, RXE and RRE -* Use Load Lengthened to expand Short BFP into the longs needed for this test. -* -TESTLONG DS 0H - LA R2,4 Set count of multiplication operations - LA R3,LONGRES2 Point to start of long BFP products - LA R4,EXTDRES1 Point to start of extended BFP products - LA R5,LONGMAD Point to start of long BFP Mult-Add results - LA R6,LONGMSB Point to start of long BFP Mult-Sub results - LA R7,SHORTBFP Point to start of short BFP input values - BASR R13,0 Set top of loop for l*l tests -* Top of loop; clear residuals from FP registers - LZDR R0 Zero FPR0 - LZDR R1 Zero FPR1 - LZDR R4 Zero FPR4 - LZDR R5 Zero FPR5 - LZDR R13 Zero FPR13 -* Collect multiplicand and multiplier, lengthen them, do four multiplications, store results. - LE R0,0(0,R7) Get BFP short multiplicand - LDEB R13,4(0,R7) Lengthen BFP short multiplier into long RXE - STD R13,0(0,R3) Store for use in MDB/MXDB tests - STD R13,0(0,R5) Store for use in MADB/MADBR tests - STD R13,0(0,R6) Store for use in MSDB/MSDBR tests - LDEBR R1,R0 Lengthen multiplicand for l*l->l RRE - LDEBR R4,R0 Lengthen multiplicand for l*l->e RXE - LDEBR R5,R0 Lengthen multiplicand for l*l->e RRE - LDEBR R0,R0 Lengthen multiplicand for l*l->l RXE (This one must be last in the list) - LDR R15,R0 Save long multiplicand for MADB/MADBR/MSDB/MSDBR tests - MDB R0,0(0,R3) Generate RXE l*l->l product - MDBR R1,R13 Generate RRE l*l->l product - MXDB R4,0(0,R3) Generate RXE l*l->e product - MXDBR R5,R13 Generate RRE l*l->e product - STD R0,0(0,R3) Store BFP RXE l*l->l product - STD R1,8(0,R3) Store BFP RRE l*l->l product - STD R4,0(0,R4) Store BFP RXE l*l->e product part 1 - STD R6,8(0,R4) Store BFP RXE l*l->e product part 2 - STD R5,16(0,R4) Store BFP RRE l*l->e product part 1 - STD R7,24(0,R4) Store BFP RRE l*l->e product part 2 - LDR R0,R15 Reload BFP long multiplicand for mult-add RXE - LDR R1,R0 Copy multiplicand for mult-add RRE - MADB R0,R0,0(0,R5) Multiply third by second, add to first RXE - MADBR R1,R13,R1 Multiply third by second, add to the first RRE - STD R0,0(0,R5) Store long BFP RXE mult-add result - STD R1,8(0,R5) Store long BFP RRE mult-add result - LDR R0,R15 Reload BFP long multiplicand for mult-sub RXE - LDR R1,R0 Copy multiplicand for mult-sub RRE - MSDB R0,R0,0(0,R6) Multiply third by second, subtract the first RXE - MSDBR R1,R13,R1 Multiply third by second, subtract the first RRE - STD R0,0(0,R6) Store long BFP RXE mult-sub result - STD R1,8(0,R6) Store long BFP RRE mult-sub result - LA R7,4(0,R7) Point to next short BFP input pair - LA R3,16(0,R3) Point to next long BFP product pair - LA R4,32(0,R4) Point to next extended BFP product pair - LA R5,16(0,R5) Point to next long BFP mult-add result pair - LA R6,16(0,R6) Point to next long BFP mult-sub result pair - BCTR R2,R13 Loop through all l*l cases -* -* BFP Multiplication extended x extended -> extended, RRE only. We do two multiplies -* per input pair so we can test a diversity of Load Lengthened instructions -* -TESTEXT DS 0H - LA R2,4 Set count of multiplication operations - LA R4,EXTDRES2 Point to start of extended BFP results - LA R7,SHORTBFP Point to start of short BFP input values - BASR R13,0 Set top of loop for e*e tests -* Top of loop -* Collect multiplicand and multiplier, lengthen them, do two multiplications, store results. - LE R0,0(0,R7) Get BFP short multiplicand - LXEBR R1,R0 Lengthen multiplicand into R1-R3 for e*e->e RRE (2) - LDEBR R0,R0 lengthen multiplicand to long - STD R0,0(0,R4) Save for test of LXDB RXE - LXDB R0,0(0,R4) Load long multiplicand, lengthen for e*e->e RRE (1) - LXEB R13,4(0,R7) Lengthen BFP short multiplier into ext - LDEB R12,4(0,R7) lengthen short multiplier into long - LXDBR R12,R12 Lengthen long multiplier into ext - MXBR R0,R13 Generate RRE (s->e) * (s->e) -> e - MXBR R1,R12 Generate RRE (s->l->e) * (s->l->e) -> e - STD R0,0(0,R4) Store BFP RRE e*e->e from short part 1 - STD R2,8(0,R4) Store BFP RRE e*e->e ..part 2 - STD R1,16(0,R4) Store BFP RRE e*e->e from short->long part 1 - STD R3,24(0,R4) Store BFP RRE e*e->e ..part 2 - LA R7,4(0,R7) Point to next short BFP input pair - LA R4,32(0,R4) Point to next extended BFP result pair - BCTR R2,R13 Loop through all e*e cases -* - BR R12 Tests done, return to mainline -* -* -* - DS 0D Ensure correct alignment for PSW -WAITPSW DC X'00020000000000000000000000000000' Disabled wait state PSW - normal completion -CTLR0 DS F Control register 0 (bit45 AFP control) -* - ORG BFPMULTS+X'400' -SHORTBFP DS 0F Ensure alignment - DC X'3F800000' 1 in short BFP - DC X'40000000' 2 - DC X'40800000' 4 - DC X'C0000000' -2 - DC X'C0000000' -2 -* -LONGMAD EQU BFPMULTS+X'300' 300.40 Results from (l*l)+l->l -LONGMSB EQU BFPMULTS+X'340' 340.40 Results from (l*l)-l->l -SHORTRES EQU BFPMULTS+X'420' 420.20 Results from s*s->s -LONGRES1 EQU BFPMULTS+X'440' 440.40 Results from s*s->l -LONGRES2 EQU BFPMULTS+X'480' 480.40 Results from l*l->l -SHORTMAD EQU BFPMULTS+X'4C0' 4C0.20 Results from (s*s)+s->s -SHORTMSB EQU BFPMULTS+X'4E0' 4E0.20 Results from (s*s)-s->s -EXTDRES1 EQU BFPMULTS+X'500' 500.80 Results from l*l->e -EXTDRES2 EQU BFPMULTS+X'580' 580.80 Results from e*e->e diff --git a/tests/ieee-mults.core b/tests/ieee-mults.core deleted file mode 100644 index 9762a8ac9..000000000 Binary files a/tests/ieee-mults.core and /dev/null differ diff --git a/tests/ieee-mults.list b/tests/ieee-mults.list deleted file mode 100644 index 12ca0be48..000000000 --- a/tests/ieee-mults.list +++ /dev/null @@ -1,331 +0,0 @@ -ASMA Ver. 0.2.0 23 Jun 2016 09:49:50 Page 1 - - LOC OBJECT CODE ADDR1 ADDR2 STMT - - 1 * - 2 * 1. Multiply adjacent pairs of values in the input set (five values means four - 3 * products). - 4 * Test data: 1, 2, 4, -2, -2; expected products 2, 8, -8, 4 - 5 * - 6 * 2. Multiply adjacent pairs of values in the input set and add the first value - 7 * in the pair to the product (five values means four results). - 8 * Test data: 1, 2, 4, -2, -2; expected results 3, 10, -4, 2 - 9 * - 10 * 3. Multiply adjacent pairs of values in the input set and subtract the first - 11 * value in the pair from the product (five values means four results). - 12 * Test data: 1, 2, 4, -2, -2; expected results 1, 6, -12, 6 - 13 * - 14 * Tests 17 multiplication instructions: - 15 * MULTIPLY (BFP short x short -> short, RRE) MEEBR - 16 * MULTIPLY (BFP short x short -> short, RXE) MEEB - 17 * MULTIPLY (BFP short x short -> long, RRE) MDEBR - 18 * MULTIPLY (BFP short x short -> long, RXE) MDEB - 19 * MULTIPLY (BFP long x long -> long, RRE) MDBR - 20 * MULTIPLY (BFP long x long -> long, RXE) MDB - 21 * MULTIPLY (BFP long x long -> extended, RRE) MXDBR - 22 * MULTIPLY (BFP long x long -> extended, RXE) MXDB - 23 * MULTIPLY (BFP long x long -> extended, RRE) MXDBR - 24 * MULTIPLY AND ADD (BFP short x short -> short, RRE) MAEBR - 25 * MULTIPLY AND ADD (BFP short x short -> short, RXE) MAEB - 26 * MULTIPLY AND ADD (BFP long x long -> long, RRE) MADBR - 27 * MULTIPLY AND ADD (BFP long x long -> long, RXE) MADB - 28 * MULTIPLY AND SUBTRACT (BFP short x short -> short, RRE) MSEBR - 29 * MULTIPLY AND SUBTRACT (BFP short x short -> short, RXE) MSEB - 30 * MULTIPLY AND SUBTRACT (BFP long x long -> long, RRE) MSDBR - 31 * MULTIPLY AND SUBTRACT (BFP long x long -> long, RXE) MSDB - 32 * - 33 * Also tests the following six conversion instructions - 34 * LOAD LENGTHENED (short BFP to long BFP, RXE) - 35 * LOAD LENGTHENED (short BFP to extended BFP, RXE) - 36 * LOAD LENGTHENED (long BFP to extended BFP, RXE) - 37 * LOAD LENGTHENED (short BFP to long BFP, RRE) - 38 * LOAD LENGTHENED (short BFP to extended BFP, RRE) - 39 * LOAD LENGTHENED (long BFP to extended BFP, RRE) - 40 * - 41 * Intermediate results from the Load Lengthened instructions are not saved. Because - 42 * zero is not present in the input test set, any error in Load Lengthened will appear - 43 * in the resulting products - 44 * - 45 * Also tests the following floating point support instructions - 46 * LOAD (Short) - 47 * LOAD (Long) - 48 * LOAD ZERO (Long) - 49 * STORE (Short) - 50 * STORE (Long) - 51 * - 0000000000000000 00000000000007DB 52 BFPMULTS START 0 - ASMA Ver. 0.2.0 23 Jun 2016 09:49:50 Page 2 - - LOC OBJECT CODE ADDR1 ADDR2 STMT - - 0000000000000000 0000000000000001 53 R0 EQU 0 - 0000000000000001 0000000000000001 54 R1 EQU 1 - 0000000000000002 0000000000000001 55 R2 EQU 2 - 0000000000000003 0000000000000001 56 R3 EQU 3 - 0000000000000004 0000000000000001 57 R4 EQU 4 - 0000000000000005 0000000000000001 58 R5 EQU 5 - 0000000000000006 0000000000000001 59 R6 EQU 6 - 0000000000000007 0000000000000001 60 R7 EQU 7 - 0000000000000008 0000000000000001 61 R8 EQU 8 - 0000000000000009 0000000000000001 62 R9 EQU 9 - 000000000000000A 0000000000000001 63 R10 EQU 10 - 000000000000000B 0000000000000001 64 R11 EQU 11 - 000000000000000C 0000000000000001 65 R12 EQU 12 - 000000000000000D 0000000000000001 66 R13 EQU 13 - 000000000000000E 0000000000000001 67 R14 EQU 14 - 000000000000000F 0000000000000001 68 R15 EQU 15 -0000000000000000 0000000000000000 69 USING *,0 -0000000000000000 0000000000000000 00000000000001A0 70 ORG BFPMULTS+X'1A0' -00000000000001A0 00000001 80000000 71 DC X'0000000180000000',AD(STARTMUL) z/Arch restart PSW -00000000000001B0 00000000000001B0 00000000000001D0 72 ORG BFPMULTS+X'1D0' -00000000000001D0 00020000 00000000 73 DC X'0002000000000000000000000000DEAD' z/Arch pgm chk new PSW -00000000000001E0 00000000000001E0 0000000000000200 74 ORG BFPMULTS+X'200' - 75 * - 76 * -0000000000000200 B600 07D8 00000000000007D8 77 STARTMUL STCTL R0,R0,CTLR0 Store CR0 to enable AFP -0000000000000204 9604 07D9 00000000000007D9 78 OI CTLR0+1,X'04' Turn on AFP bit -0000000000000208 B700 07D8 00000000000007D8 79 LCTL R0,R0,CTLR0 Reload updated CR0 -000000000000020C 45C0 0600 0000000000000600 80 BAL R12,TESTMULT Perform multiplications -0000000000000210 B2B2 07C8 00000000000007C8 81 LPSWE WAITPSW All done, load disabled wait PSW - 82 * - 83 * BFP Multiplication Short x Short -> Short & Short x Short -> Long, RXE and RRE - 84 * -0000000000000214 0000000000000214 0000000000000600 85 ORG BFPMULTS+X'600' -0000000000000600 86 TESTMULT DS 0H -0000000000000600 4120 0004 0000000000000004 87 LA R2,4 Set count of multiplication operations -0000000000000604 4130 0420 0000000000000420 88 LA R3,SHORTRES Point to start of short BFP products -0000000000000608 4140 0440 0000000000000440 89 LA R4,LONGRES1 Point to start of long BFP products -000000000000060C 4150 04C0 00000000000004C0 90 LA R5,SHORTMAD Point to start of short BFP Mult-Add results -0000000000000610 4160 04E0 00000000000004E0 91 LA R6,SHORTMSB Point to start of short BFP Mult-Sub results -0000000000000614 4170 0400 0000000000000400 92 LA R7,SHORTBFP Point to start of short BFP input values -0000000000000618 0DD0 93 BASR R13,0 Set top of loop - 94 * Top of loop; clear residuals from FP registers -000000000000061A B375 0000 95 LZDR R0 Zero FPR0 -000000000000061E B375 0010 96 LZDR R1 Zero FPR1 -0000000000000622 B375 0040 97 LZDR R4 Zero FPR4 -0000000000000626 B375 0050 98 LZDR R5 Zero FPR5 -000000000000062A B375 00D0 99 LZDR R13 Zero FPR13 - 100 * Collect multiplicand and multiplier, do four multiplications, store results. -000000000000062E 7800 7000 0000000000000000 101 LE R0,0(0,R7) Get BFP short multiplicand -0000000000000632 78D0 7004 0000000000000004 102 LE R13,4(0,R7) Get BFP short multiplier -0000000000000636 3810 103 LER R1,R0 Copy multiplicand for s*s->s RRE -0000000000000638 3840 104 LER R4,R0 Copy multiplicand for s*s->l RXE - ASMA Ver. 0.2.0 23 Jun 2016 09:49:50 Page 3 - - LOC OBJECT CODE ADDR1 ADDR2 STMT - -000000000000063A 3850 105 LER R5,R0 Copy multiplicand for s*s->l RRE -000000000000063C ED00 7004 0017 0000000000000004 106 MEEB R0,4(0,R7) Generate RXE s*s->s product -0000000000000642 B317 001D 107 MEEBR R1,R13 Generate RRE s*s->s product -0000000000000646 ED40 7004 000C 0000000000000004 108 MDEB R4,4(0,R7) Generate RXE s*s->l product -000000000000064C B30C 005D 109 MDEBR R5,R13 Generate RRE s*s->l product -0000000000000650 7000 3000 0000000000000000 110 STE R0,0(0,R3) Store short BFP RXE s*s->s product -0000000000000654 7010 3004 0000000000000004 111 STE R1,4(0,R3) Store short BFP RRE s*s->s product -0000000000000658 7040 4000 0000000000000000 112 STE R4,0(0,R4) Store short BFP RXE s*s->l product -000000000000065C 7050 4008 0000000000000008 113 STE R5,8(0,R4) Store short BFP RRE s*s->l product -0000000000000660 7800 7000 0000000000000000 114 LE R0,0(0,R7) Reload BFP short multiplicand for mult-add RXE -0000000000000664 3810 115 LER R1,R0 Copy multiplicand for mult-add RRE -0000000000000666 ED00 7004 000E 0000000000000004 116 MAEB R0,R0,4(0,R7) Multiply third by second, add to first RXE -000000000000066C B30E 10D1 117 MAEBR R1,R13,R1 Multiply third by second, add to the first RRE -0000000000000670 7000 5000 0000000000000000 118 STE R0,0(0,R5) Store short BFP RXE mult-add result -0000000000000674 7010 5004 0000000000000004 119 STE R1,4(0,R5) Store short BFP RRE mult-add result -0000000000000678 7800 7000 0000000000000000 120 LE R0,0(0,R7) Reload BFP short multiplicand for mult-sub RXE -000000000000067C 3810 121 LER R1,R0 Copy multiplicand for mult-sub RRE -000000000000067E ED00 7004 000F 0000000000000004 122 MSEB R0,R0,4(0,R7) Multiply third by second, subtract the first RXE -0000000000000684 B30F 10D1 123 MSEBR R1,R13,R1 Multiply third by second, subtract the first RRE -0000000000000688 7000 6000 0000000000000000 124 STE R0,0(0,R6) Store short BFP RXE mult-sub result -000000000000068C 7010 6004 0000000000000004 125 STE R1,4(0,R6) Store short BFP RRE mult-sub result -0000000000000690 4170 7004 0000000000000004 126 LA R7,4(0,R7) Point to next short BFP input pair -0000000000000694 4130 3008 0000000000000008 127 LA R3,8(0,R3) Point to next short BFP product pair -0000000000000698 4140 4010 0000000000000010 128 LA R4,16(0,R4) Point to next long BFP product pair -000000000000069C 4150 5008 0000000000000008 129 LA R5,8(0,R5) Point to next short BFP mult-add result pair -00000000000006A0 4160 6008 0000000000000008 130 LA R6,8(0,R6) Point to next short BFP mult-sub result pair -00000000000006A4 062D 131 BCTR R2,R13 Loop through all s*s test cases - 132 * - 133 * BFP Multiplication long x long -> long & long x long -> extended, RXE and RRE - 134 * Use Load Lengthened to expand Short BFP into the longs needed for this test. - 135 * -00000000000006A6 136 TESTLONG DS 0H -00000000000006A6 4120 0004 0000000000000004 137 LA R2,4 Set count of multiplication operations -00000000000006AA 4130 0480 0000000000000480 138 LA R3,LONGRES2 Point to start of long BFP products -00000000000006AE 4140 0500 0000000000000500 139 LA R4,EXTDRES1 Point to start of extended BFP products -00000000000006B2 4150 0300 0000000000000300 140 LA R5,LONGMAD Point to start of long BFP Mult-Add results -00000000000006B6 4160 0340 0000000000000340 141 LA R6,LONGMSB Point to start of long BFP Mult-Sub results -00000000000006BA 4170 0400 0000000000000400 142 LA R7,SHORTBFP Point to start of short BFP input values -00000000000006BE 0DD0 143 BASR R13,0 Set top of loop for l*l tests - 144 * Top of loop; clear residuals from FP registers -00000000000006C0 B375 0000 145 LZDR R0 Zero FPR0 -00000000000006C4 B375 0010 146 LZDR R1 Zero FPR1 -00000000000006C8 B375 0040 147 LZDR R4 Zero FPR4 -00000000000006CC B375 0050 148 LZDR R5 Zero FPR5 -00000000000006D0 B375 00D0 149 LZDR R13 Zero FPR13 - 150 * Collect multiplicand and multiplier, lengthen them, do four multiplications, store results. -00000000000006D4 7800 7000 0000000000000000 151 LE R0,0(0,R7) Get BFP short multiplicand -00000000000006D8 EDD0 7004 0004 0000000000000004 152 LDEB R13,4(0,R7) Lengthen BFP short multiplier into long RXE -00000000000006DE 60D0 3000 0000000000000000 153 STD R13,0(0,R3) Store for use in MDB/MXDB tests -00000000000006E2 60D0 5000 0000000000000000 154 STD R13,0(0,R5) Store for use in MADB/MADBR tests -00000000000006E6 60D0 6000 0000000000000000 155 STD R13,0(0,R6) Store for use in MSDB/MSDBR tests -00000000000006EA B304 0010 156 LDEBR R1,R0 Lengthen multiplicand for l*l->l RRE - ASMA Ver. 0.2.0 23 Jun 2016 09:49:50 Page 4 - - LOC OBJECT CODE ADDR1 ADDR2 STMT - -00000000000006EE B304 0040 157 LDEBR R4,R0 Lengthen multiplicand for l*l->e RXE -00000000000006F2 B304 0050 158 LDEBR R5,R0 Lengthen multiplicand for l*l->e RRE -00000000000006F6 B304 0000 159 LDEBR R0,R0 Lengthen multiplicand for l*l->l RXE (This one must be last in the list) -00000000000006FA 28F0 160 LDR R15,R0 Save long multiplicand for MADB/MADBR/MSDB/MSDBR tests -00000000000006FC ED00 3000 001C 0000000000000000 161 MDB R0,0(0,R3) Generate RXE l*l->l product -0000000000000702 B31C 001D 162 MDBR R1,R13 Generate RRE l*l->l product -0000000000000706 ED40 3000 0007 0000000000000000 163 MXDB R4,0(0,R3) Generate RXE l*l->e product -000000000000070C B307 005D 164 MXDBR R5,R13 Generate RRE l*l->e product -0000000000000710 6000 3000 0000000000000000 165 STD R0,0(0,R3) Store BFP RXE l*l->l product -0000000000000714 6010 3008 0000000000000008 166 STD R1,8(0,R3) Store BFP RRE l*l->l product -0000000000000718 6040 4000 0000000000000000 167 STD R4,0(0,R4) Store BFP RXE l*l->e product part 1 -000000000000071C 6060 4008 0000000000000008 168 STD R6,8(0,R4) Store BFP RXE l*l->e product part 2 -0000000000000720 6050 4010 0000000000000010 169 STD R5,16(0,R4) Store BFP RRE l*l->e product part 1 -0000000000000724 6070 4018 0000000000000018 170 STD R7,24(0,R4) Store BFP RRE l*l->e product part 2 -0000000000000728 280F 171 LDR R0,R15 Reload BFP long multiplicand for mult-add RXE -000000000000072A 2810 172 LDR R1,R0 Copy multiplicand for mult-add RRE -000000000000072C ED00 5000 001E 0000000000000000 173 MADB R0,R0,0(0,R5) Multiply third by second, add to first RXE -0000000000000732 B31E 10D1 174 MADBR R1,R13,R1 Multiply third by second, add to the first RRE -0000000000000736 6000 5000 0000000000000000 175 STD R0,0(0,R5) Store long BFP RXE mult-add result -000000000000073A 6010 5008 0000000000000008 176 STD R1,8(0,R5) Store long BFP RRE mult-add result -000000000000073E 280F 177 LDR R0,R15 Reload BFP long multiplicand for mult-sub RXE -0000000000000740 2810 178 LDR R1,R0 Copy multiplicand for mult-sub RRE -0000000000000742 ED00 6000 001F 0000000000000000 179 MSDB R0,R0,0(0,R6) Multiply third by second, subtract the first RXE -0000000000000748 B31F 10D1 180 MSDBR R1,R13,R1 Multiply third by second, subtract the first RRE -000000000000074C 6000 6000 0000000000000000 181 STD R0,0(0,R6) Store long BFP RXE mult-sub result -0000000000000750 6010 6008 0000000000000008 182 STD R1,8(0,R6) Store long BFP RRE mult-sub result -0000000000000754 4170 7004 0000000000000004 183 LA R7,4(0,R7) Point to next short BFP input pair -0000000000000758 4130 3010 0000000000000010 184 LA R3,16(0,R3) Point to next long BFP product pair -000000000000075C 4140 4020 0000000000000020 185 LA R4,32(0,R4) Point to next extended BFP product pair -0000000000000760 4150 5010 0000000000000010 186 LA R5,16(0,R5) Point to next long BFP mult-add result pair -0000000000000764 4160 6010 0000000000000010 187 LA R6,16(0,R6) Point to next long BFP mult-sub result pair -0000000000000768 062D 188 BCTR R2,R13 Loop through all l*l cases - 189 * - 190 * BFP Multiplication extended x extended -> extended, RRE only. We do two multiplies - 191 * per input pair so we can test a diversity of Load Lengthened instructions - 192 * -000000000000076A 193 TESTEXT DS 0H -000000000000076A 4120 0004 0000000000000004 194 LA R2,4 Set count of multiplication operations -000000000000076E 4140 0580 0000000000000580 195 LA R4,EXTDRES2 Point to start of extended BFP results -0000000000000772 4170 0400 0000000000000400 196 LA R7,SHORTBFP Point to start of short BFP input values -0000000000000776 0DD0 197 BASR R13,0 Set top of loop for e*e tests - 198 * Top of loop - 199 * Collect multiplicand and multiplier, lengthen them, do two multiplications, store results. -0000000000000778 7800 7000 0000000000000000 200 LE R0,0(0,R7) Get BFP short multiplicand -000000000000077C B306 0010 201 LXEBR R1,R0 Lengthen multiplicand into R1-R3 for e*e->e RRE (2) -0000000000000780 B304 0000 202 LDEBR R0,R0 lengthen multiplicand to long -0000000000000784 6000 4000 0000000000000000 203 STD R0,0(0,R4) Save for test of LXDB RXE -0000000000000788 ED00 4000 0005 0000000000000000 204 LXDB R0,0(0,R4) Load long multiplicand, lengthen for e*e->e RRE (1) -000000000000078E EDD0 7004 0006 0000000000000004 205 LXEB R13,4(0,R7) Lengthen BFP short multiplier into ext -0000000000000794 EDC0 7004 0004 0000000000000004 206 LDEB R12,4(0,R7) lengthen short multiplier into long -000000000000079A B305 00CC 207 LXDBR R12,R12 Lengthen long multiplier into ext -000000000000079E B34C 000D 208 MXBR R0,R13 Generate RRE (s->e) * (s->e) -> e - ASMA Ver. 0.2.0 23 Jun 2016 09:49:50 Page 5 - - LOC OBJECT CODE ADDR1 ADDR2 STMT - -00000000000007A2 B34C 001C 209 MXBR R1,R12 Generate RRE (s->l->e) * (s->l->e) -> e -00000000000007A6 6000 4000 0000000000000000 210 STD R0,0(0,R4) Store BFP RRE e*e->e from short part 1 -00000000000007AA 6020 4008 0000000000000008 211 STD R2,8(0,R4) Store BFP RRE e*e->e ..part 2 -00000000000007AE 6010 4010 0000000000000010 212 STD R1,16(0,R4) Store BFP RRE e*e->e from short->long part 1 -00000000000007B2 6030 4018 0000000000000018 213 STD R3,24(0,R4) Store BFP RRE e*e->e ..part 2 -00000000000007B6 4170 7004 0000000000000004 214 LA R7,4(0,R7) Point to next short BFP input pair -00000000000007BA 4140 4020 0000000000000020 215 LA R4,32(0,R4) Point to next extended BFP result pair -00000000000007BE 062D 216 BCTR R2,R13 Loop through all e*e cases - 217 * -00000000000007C0 07FC 218 BR R12 Tests done, return to mainline - 219 * - 220 * - 221 * -00000000000007C8 222 DS 0D Ensure correct alignment for PSW -00000000000007C8 00020000 00000000 223 WAITPSW DC X'00020000000000000000000000000000' Disabled wait state PSW - normal completion -00000000000007D8 00000000 224 CTLR0 DS F Control register 0 (bit45 AFP control) - 225 * -00000000000007DC 00000000000007DC 0000000000000400 226 ORG BFPMULTS+X'400' -0000000000000400 227 SHORTBFP DS 0F Ensure alignment -0000000000000400 3F800000 228 DC X'3F800000' 1 in short BFP -0000000000000404 40000000 229 DC X'40000000' 2 -0000000000000408 40800000 230 DC X'40800000' 4 -000000000000040C C0000000 231 DC X'C0000000' -2 -0000000000000410 C0000000 232 DC X'C0000000' -2 - 233 * - 0000000000000300 0000000000000000 234 LONGMAD EQU BFPMULTS+X'300' 300.40 Results from (l*l)+l->l - 0000000000000340 0000000000000000 235 LONGMSB EQU BFPMULTS+X'340' 340.40 Results from (l*l)-l->l - 0000000000000420 0000000000000000 236 SHORTRES EQU BFPMULTS+X'420' 420.20 Results from s*s->s - 0000000000000440 0000000000000000 237 LONGRES1 EQU BFPMULTS+X'440' 440.40 Results from s*s->l - 0000000000000480 0000000000000000 238 LONGRES2 EQU BFPMULTS+X'480' 480.40 Results from l*l->l - 00000000000004C0 0000000000000000 239 SHORTMAD EQU BFPMULTS+X'4C0' 4C0.20 Results from (s*s)+s->s - 00000000000004E0 0000000000000000 240 SHORTMSB EQU BFPMULTS+X'4E0' 4E0.20 Results from (s*s)-s->s - 0000000000000500 0000000000000000 241 EXTDRES1 EQU BFPMULTS+X'500' 500.80 Results from l*l->e - 0000000000000580 0000000000000000 242 EXTDRES2 EQU BFPMULTS+X'580' 580.80 Results from e*e->e - ASMA Ver. 0.2.0 23 Jun 2016 09:49:50 Page 6 - - SYMBOL TYPE VALUE LENGTH DEFN REFERENCES - -BFPMULTS J 000000 2012 52 70 72 74 85 226 234 235 236 237 238 239 240 241 242 -CTLR0 F 0007D8 4 224 77 78 79 -EXTDRES1 U 000500 0 241 139 -EXTDRES2 U 000580 0 242 195 -IMAGE 1 000000 2012 0 -LONGMAD U 000300 0 234 140 -LONGMSB U 000340 0 235 141 -LONGRES1 U 000440 0 237 89 -LONGRES2 U 000480 0 238 138 -R0 U 000000 1 53 77 79 95 101 103 104 105 106 110 114 115 116 118 120 121 122 124 - 145 151 156 157 158 159 160 161 165 171 172 173 175 177 178 179 181 - 200 201 202 203 204 208 210 -R1 U 000001 1 54 96 103 107 111 115 117 119 121 123 125 146 156 162 166 172 174 176 - 178 180 182 201 209 212 -R10 U 00000A 1 63 -R11 U 00000B 1 64 -R12 U 00000C 1 65 80 206 207 209 218 -R13 U 00000D 1 66 93 99 102 107 109 117 123 131 143 149 152 153 154 155 162 164 174 - 180 188 197 205 208 216 -R14 U 00000E 1 67 -R15 U 00000F 1 68 160 171 177 -R2 U 000002 1 55 87 131 137 188 194 211 216 -R3 U 000003 1 56 88 110 111 127 138 153 161 163 165 166 184 213 -R4 U 000004 1 57 89 97 104 108 112 113 128 139 147 157 163 167 168 169 170 185 195 - 203 204 210 211 212 213 215 -R5 U 000005 1 58 90 98 105 109 113 118 119 129 140 148 154 158 164 169 173 175 176 - 186 -R6 U 000006 1 59 91 124 125 130 141 155 168 179 181 182 187 -R7 U 000007 1 60 92 101 102 106 108 114 116 120 122 126 142 151 152 170 183 196 200 - 205 206 214 -R8 U 000008 1 61 -R9 U 000009 1 62 -SHORTBFP F 000400 4 227 92 142 196 -SHORTMAD U 0004C0 0 239 90 -SHORTMSB U 0004E0 0 240 91 -SHORTRES U 000420 0 236 88 -STARTMUL I 000200 4 77 71 -TESTEXT H 00076A 2 193 -TESTLONG H 0006A6 2 136 -TESTMULT H 000600 2 86 80 -WAITPSW X 0007C8 16 223 81 - ASMA Ver. 0.2.0 23 Jun 2016 09:49:50 Page 7 - -MACRO DEFN REFERENCES - -No defined macros - ASMA Ver. 0.2.0 23 Jun 2016 09:49:50 Page 8 - - DESC SYMBOL SIZE POS ADDR - -Entry: 0 - -Image IMAGE 2012 000-7DB 000-7DB - Region 2012 000-7DB 000-7DB - CSECT BFPMULTS 2012 000-7DB 000-7DB - ASMA Ver. 0.2.0 23 Jun 2016 09:49:50 Page 9 - - STMT FILE NAME - -1 C:\Users\srorso\Documents\GitHub\hyperion\tests\ieee-mults.asm - - -** NO ERRORS FOUND ** - - \ No newline at end of file diff --git a/tests/ieee-mults.tst b/tests/ieee-mults.tst deleted file mode 100644 index 173ad7a8f..000000000 --- a/tests/ieee-mults.tst +++ /dev/null @@ -1,136 +0,0 @@ -*Testcase ieee-mults.tst: Load Lengthened and Multiply tests -*Message Testcase ieee-divs.tst: Load Lengthened and Multiply tests -*Message ..includes LOAD LENGTHENED (6), MULTIPLY (9), MULTIPLY AND ADD (4) -*Message ..MULTPLY AND SUBTRACT (4), 23 instr total -*Message ..Test case values generate only integer results. - -sysclear -archmode esame -loadcore "$(testpath)/ieee-mults.core" -runtest .1 - -*Compare -r 420.10 # BFP Short Products part 1 Expecting 2 2 8 8 -*Want "MEEB/MEEBR tests 1, 2" 40000000 40000000 41000000 41000000 -*Compare -r 430.10 # BFP Short Products part 2 -8 -8 4 4 -*Want "MEEB/MEEBR tests 3, 4" C1000000 C1000000 40800000 40800000 - -*Compare -r 4C0.10 # BFP Short M-Add part 1 Expecting 3 3 10 10 -*Want "MAEB/MAEBR tests 1, 2" 40400000 40400000 41200000 41200000 -*Compare -r 4D0.10 # BFP Short M-Add part 2 Expecting -4, -4, 2, 2 -*Want "MAEB/MAEBR tests 3, 4" C0800000 C0800000 40000000 40000000 - -*Compare -r 4E0.10 # BFP Short M-Sub part 1 Expecting 1, 1, 6, 6 -*Want "MSEB/MSEBR tests 1, 2" 3F800000 3F800000 40C00000 40C00000 -*Compare -r 4F0.10 # BFP Short M-Sub part 2 Expecting -12, -12, 6, 6 -*Want "MSEB/MSEBR tests 3, 4" C1400000 C1400000 40C00000 40C00000 - -*Compare -r 440.10 # BFP Long products from short x short part 1 Expecting 2.0 2.0 -*Want "MDEB/MDEBR test 1" 40000000 00000000 40000000 00000000 -*Compare -r 450.10 # BFP Long products from short x short part 2 Expecting 8.0 8.0 -*Want "MDEB/MDEBR test 2" 40200000 00000000 40200000 00000000 -*Compare -r 460.10 # BFP Long products from short x short part 3 Expecting -8.0 -8.0 -*Want "MDEB/MDEBR test 3" C0200000 00000000 C0200000 00000000 -*Compare -r 470.10 # BFP Long products from short x short part 4 Expecting 4.0 4.0 -*Want "MDEB/MDEBR test 4" 40100000 00000000 40100000 00000000 - -*Compare -r 480.10 # BFP Long products from long x long part 1 -*Want "MDB/MDBR test 1" 40000000 00000000 40000000 00000000 -*Compare -r 490.10 # BFP Long products from long x long part 2 -*Want "MDB/MDBR test 2" 40200000 00000000 40200000 00000000 -*Compare -r 4A0.10 # BFP Long products from long x long part 3 -*Want "MDB/MDBR test 3" C0200000 00000000 C0200000 00000000 -*Compare -r 4B0.10 # BFP Long products from long x long part 4 -*Want "MDB/MDBR test 4" 40100000 00000000 40100000 00000000 - -*Compare -r 300.10 # BFP Long M-Add part 1 Expecting 3 3 -*Want "MADB/MADBR test 1" 40080000 00000000 40080000 00000000 -*Compare -r 310.10 # BFP Long M-Add part 2 Expecting 10 10 -*Want "MADB/MADBR test 2" 40240000 00000000 40240000 00000000 -*Compare -r 320.10 # BFP Long M-Add part 3 Expecting -4, -4 -*Want "MADB/MADBR test 3" C0100000 00000000 C0100000 00000000 -*Compare -r 330.10 # BFP Long M-Add part 4 Expecting 2, 2 -*Want "MADB/MADBR test 4" 40000000 00000000 40000000 00000000 - -*Compare -r 340.10 # BFP Long M-Sub part 1 Expecting 1, 1 -*Want "MSDB/MSDBR test 1" 3FF00000 00000000 3FF00000 00000000 -*Compare -r 350.10 # BFP Long M-Sub part 2 Expecting 6, 6 -*Want "MSDB/MSDBR test 2" 40180000 00000000 40180000 00000000 -*Compare -r 360.10 # BFP Long M-Sub part 3 Expecting -12, -12 -*Want "MSDB/MSDBR test 3" C0280000 00000000 C0280000 00000000 -*Compare -r 370.10 # BFP Long M-Sub part 4 Expecting 6, 6 -*Want "MSDB/MSDBR test 4" 40180000 00000000 40180000 00000000 - -*Compare -r 500.10 # BFP Extended products from long x long part 1a -*Want "MXDBR test 1a" 40000000 00000000 00000000 00000000 -*Compare -r 510.10 # BFP Extended products from long x long part 1b -*Want "MXDBR test 1b" 40000000 00000000 00000000 00000000 -*Compare -r 520.10 # BFP Extended products from long x long part 2a -*Want "MXDBR test 2a" 40020000 00000000 00000000 00000000 -*Compare -r 530.10 # BFP Extended products from long x long part 2b -*Want "MXDBR test 2b" 40020000 00000000 00000000 00000000 -*Compare -r 540.10 # BFP Extended products from long x long part 3a -*Want "MXDBR test 3a" C0020000 00000000 00000000 00000000 -*Compare -r 550.10 # BFP Extended products from long x long part 3b -*Want "MXDBR test 3b" C0020000 00000000 00000000 00000000 -*Compare -r 560.10 # BFP Extended products from long x long part 4a -*Want "MXDBR test 4a" 40010000 00000000 00000000 00000000 -*Compare -r 570.10 # BFP Extended products from long x long part 4b -*Want "MXDBR test 4b" 40010000 00000000 00000000 00000000 - -*Compare -r 580.10 # BFP Extended products from extended x extended part 1a -*Want "MXBR test 1a" 40000000 00000000 00000000 00000000 -*Compare -r 590.10 # BFP Extended products from extended x extended part 1b -*Want "MXBR test 1b" 40000000 00000000 00000000 00000000 -*Compare -r 5A0.10 # BFP Extended products from extended x extended part 2a -*Want "MXBR test 2a" 40020000 00000000 00000000 00000000 -*Compare -r 5B0.10 # BFP Extended products from extended x extended part 2b -*Want "MXBR test 2b" 40020000 00000000 00000000 00000000 -*Compare -r 5C0.10 # BFP Extended products from extended x extended part 3a -*Want "MXBR test 3a" C0020000 00000000 00000000 00000000 -*Compare -r 5D0.10 # BFP Extended products from extended x extended part 3b -*Want "MXBR test 3b" C0020000 00000000 00000000 00000000 -*Compare -r 5E0.10 # BFP Extended products from extended x extended part 4a -*Want "MXBR test 4a" 40010000 00000000 00000000 00000000 -*Compare -r 5F0.10 # BFP Extended products from extended x extended part 4b -*Want "MXBR test 4b" 40010000 00000000 00000000 00000000 - -*Done - diff --git a/tests/ieee-sqrts.asm b/tests/ieee-sqrts.asm deleted file mode 100644 index 9732e3430..000000000 --- a/tests/ieee-sqrts.asm +++ /dev/null @@ -1,243 +0,0 @@ -* -* Tests five square root instructions: -* SQUARE ROOT (extended BFP, RRE) -* SQUARE ROOT (long BFP, RRE) -* SQUARE ROOT (long BFP, RXE) -* SQUARE ROOT (short BFP, RRE) -* SQUARE ROOT (short BFP, RXE) -* -* Also tests the following twelve conversion instructions -* CONVERT FROM FIXED (32 to short BFP, RRE) -* CONVERT FROM FIXED (32 to long BFP, RRE) -* CONVERT FROM FIXED (32 to extended BFP, RRE) -* CONVERT TO FIXED (32 to short BFP, RRE) -* CONVERT TO FIXED (32 to long BFP, RRE) -* CONVERT TO FIXED (32 to extended BFP, RRE) -* CONVERT FROM FIXED (64 to short BFP, RRE) -* CONVERT FROM FIXED (64 to long BFP, RRE) -* CONVERT FROM FIXED (64 to extended BFP, RRE) -* CONVERT TO FIXED (64 to short BFP, RRE) -* CONVERT TO FIXED (64 to long BFP, RRE) -* CONVERT TO FIXED (64 to extended BFP, RRE) -* -* Also tests the following floating point support instructions -* LOAD (Short) -* LOAD (Long) -* LOAD ZERO (Long) -* STORE (Short) -* STORE (Long) -* -* Convert integers 1, 2, 4, 16 to each BFP floating point format -* Take the square root of each in each BFP format -* Convert back to integers (Note: SQRT(2) will/should round) -* Because all inputs must be positive, we'll use this rig to test -* logical (unsigned) conversions when that support is added to -* Hercules. And we will test 32 and 64 bit logical conversions. -* The comments will still say "integers" though. -* -BFPSQRTS START 0 -R0 EQU 0 -R1 EQU 1 -R2 EQU 2 -R3 EQU 3 -R4 EQU 4 -R5 EQU 5 -R6 EQU 6 -R7 EQU 7 -R8 EQU 8 -R9 EQU 9 -R10 EQU 10 -R11 EQU 11 -R12 EQU 12 -R13 EQU 13 -R14 EQU 14 -R15 EQU 15 - USING *,0 - ORG BFPSQRTS+X'1A0' - DC X'0000000180000000',AD(STARTNAN) z/Arch restart PSW - ORG BFPSQRTS+X'1D0' - DC X'0002000000000000000000000000DEAD' z/Arch pgm chk new PSW - ORG BFPSQRTS+X'200' -* -* Mainline program. -* -STARTNAN STCTL R0,R0,CTLR0 Store CR0 to enable AFP - OI CTLR0+1,X'04' Turn on AFP bit - LCTL R0,R0,CTLR0 Reload updated CR0 - BAL R12,CVTINPUT Convert inputs to binary formats - BAL R12,TESTSQRT Perform subtractions - BAL R12,CVTOUTS Convert results to integers - LPSWE WAITPSW All done, load enabled wait PSW - DS 0D Ensure correct alignment for PSW -* -* -WAITPSW DC X'00020000000000000000000000000000' Disabled wait state PSW - normal completion -CTLR0 DS F Control register 0 (bit45 AFP control) -* - ORG BFPSQRTS+X'480' -* asma does not support doubleword integers, so we'll just do F'0' then F'value' -INTVALS DS 0D Four doublewords - DC F'0' - DC F'1' first test integer - DC F'0' - DC F'2' second test integer - DC F'0' - DC F'4' third test integer - DC F'0' - DC F'16' fourth test integer -* -SHORTBFP EQU BFPSQRTS+X'410' 4F 410.10 four test cases in short bfp -LONGBFP EQU BFPSQRTS+X'420' 4D 420.20 four test cases in long bfp -EXTBFP EQU BFPSQRTS+X'440' 8D 440.40 four test cases in extended bfp - -SHORTRES EQU BFPSQRTS+X'500' 8F 500.20 Short square root results (4 pairs, RXE & RRE) -LONGRES EQU BFPSQRTS+X'520' 8D 520.40 Long square root results (4 pairs, RXE & RRE) -EXTRES EQU BFPSQRTS+X'560' 8D 560.40 Extended square root results (4, RRE only) -* -ISHBFP EQU BFPSQRTS+X'A00' 8D A00.40 Convert short BFP to Integer results -ILNBFP EQU BFPSQRTS+X'A40' 8D A40.40 Convert long BFP to Integer results -IXTBFP EQU BFPSQRTS+X'A80' 8F A80.20 Convert extended BFP to Integer results - ORG BFPSQRTS+X'800' -* -* -* -* Take square roots of the four test cases in each precision -* -TESTSQRT DS 0H -* Calculate square roots of values - LA R2,4 Set count of square root operations - LA R3,SHORTRES Point to start of short BFP results - LA R4,LONGRES Point to start of long BFP results - LA R5,EXTRES Point to start of extended BFP results - LA R7,SHORTBFP Point to start of short BFP input values - LA R8,LONGBFP Point to start of long BFP input values - LA R9,EXTBFP Point to start of extended BFP input values - BASR R13,0 Set top of loop -* Top of loop; clear residuals from FPR0-1 -SQRTLOOP LZDR R0 Zero FPR0 - LZDR R1 Zero FPR1 -* BFP Short square root RXE and RRE - SQEB R0,0(0,R7) Put square root of test case in FPR0 - STE R0,0(0,R3) Store short BFP result from RXE - LE R1,0(0,R7) Get test case for RRE instruction - SQEBR R0,R1 Add BFP values, result in FPR0 - STE R0,4(0,R3) Store short BFP from RRE - LA R7,4(0,R7) Point to next short BFP test case - LA R3,8(0,R3) Point to next short BFP result pair -* BFP Long square root RXE and RRE - SQDB R0,0(0,R8) Square root BFP long test case - STD R0,0(0,R4) Store long BFP result from RXE - LD R1,0(0,R8) Get BFP long test case - SQDBR R0,R1 Take square root, result in FPR0 - STD R0,8(0,R4) Store long BFP from RRE - LA R8,8(0,R8) Point to next long BFP test case - LA R4,16(0,R4) Point to next long BFP result pair -* BFP Extended square root RRE - LD R1,0(0,R9) Get BFP ext. 1st half of test case - LD R3,8(0,R9) Get BFP ext. 2nd half of test case - SQXBR R0,R1 Add BFP values, result in FPR0-FPR2 - STD R0,0(0,R5) Store ext. BFP from RRE - STD R2,8(0,R5) Store ext. BFP from RRE - LA R9,16(0,R9) Point to next ext. BFP input - LA R5,16(0,R5) Point to next ext. BFP result - BCTR R2,R13 Square root next input pair - BR R12 Return to caller -* -* Convert Integer test cases to each format of BFP. Half will be converted as -* 32-bit unsigned integers, and the rest as 64-bit unsigned integers. -* -CVTINPUT DS 0H - LA R2,2 Set count of test input values - LA R3,INTVALS point to start of input values - LA R7,SHORTBFP Point to start of short BFP input values - LA R8,LONGBFP Point to start of long BFP input values - LA R9,EXTBFP Point to start of extended BFP input values - BASR R13,0 Set top of loop -* convert integers to three BFP formats. 32 bit first, then 64 -CVTLOOP L R1,4(0,R3) Get integer test value - CEFBR R0,R1 Cvt Int in GPR1 to float in FPR0 - STE R0,0(0,R7) Store short BFP - CDFBR R0,R1 Cvt Int in GPR1 to float in FPR0 - STD R0,0(0,R8) Store long BFP - CXFBR R0,R1 Cvt Int in GPR1 to float in FPR0-FPR2 - STD R0,0(0,R9) Store extended BFP part 1 - STD R2,8(0,R9) Store extended BFP part 2 - LG R1,8(0,R3) Get integer test value - CEGBR R0,R1 Cvt Int in GPR1 to float in FPR0 - STE R0,4(0,R7) Store short BFP - CDGBR R0,R1 Cvt Int in GPR1 to float in FPR0 - STD R0,8(0,R8) Store long BFP - CXGBR R0,R1 Cvt Int in GPR1 to float in FPR0-FPR2 - STD R0,16(0,R9) Store extended BFP part 1 - STD R2,24(0,R9) Store extended BFP part 2 - LA R3,16(0,R3) point to next input value pair - LA R7,8(0,R7) Point to next pair of short BFP converted values - LA R8,16(0,R8) Point to next pair of long BFP converted values - LA R9,32(0,R9) Point to next pair of extended BFP converted values - BCTR R2,R13 Convert next input value pair. - BR R12 All converted, return to main line. -* -* Convert back to integers -* -CVTOUTS DS 0H - LA R2,2 Set count of square root result pairs - LA R7,SHORTRES Point to start of short BFP results - LA R8,LONGRES Point to start of long BFP results - LA R9,EXTRES Point to start of extended BFP results - LA R3,ISHBFP Point to start of short BFP Integer results - LA R4,ILNBFP Point to start of long BFP integer results - LA R5,IXTBFP Point to start of extended BFP integer results - BASR R13,0 Set top of loop -* -* Convert shorts back to integer -* -INTLOOP LZDR R0 Zero FPR0 - LE R0,0(0,R7) Get BFP short result RXE - CFEBR R0,R0 Convert to integer in r0 - ST R0,4(0,R3) Store integer result - LE R0,4(0,R7) Get BFP short result RRE - CFEBR R0,R0 Convert to integer in r0 - ST R0,12(0,R3) Store integer result -* - LE R0,8(0,R7) Get BFP short result RXE - CGEBR R0,R0 Convert to integer 64 in r0 - STG R0,16(0,R3) Store integer result - LE R0,12(0,R7) Get BFP short result RRE - CGEBR R0,R0 Convert to integer 64 in r0 - STG R0,24(0,R3) Store integer result -* - LD R0,0(0,R8) Get BFP long result RXE - CFDBR R0,R0 Convert to integer in r0 - ST R0,4(0,R4) Store integer result - LD R0,8(0,R8) Get BFP long result RRE - CFDBR R0,R0 Convert to integer in r0 - ST R0,12(0,R4) Store integer result -* - LD R0,16(0,R8) Get BFP long result RXE - CGDBR R0,R0 Convert to integer 64 in r0 - STG R0,16(0,R4) Store integer result - LD R0,24(0,R8) Get BFP long result RRE - CGDBR R0,R0 Convert to integer 64 in r0 - STG R0,24(0,R4) Store integer result -* - LD R0,0(0,R9) Get BFP ext. 1st half - LD R2,8(0,R9) Get BFP ext. 2nd half - CFXBR R0,R0 Convert BFP Ext. to Integer-32 - ST R0,4(0,R5) Store integer result lower word -* - LD R0,16(0,R9) Get BFP ext. 1st half - LD R2,24(0,R9) Get BFP ext. 2nd half - CGXBR R0,R0 Convert BFP Ext. to Integer-64 - STG R0,8(0,R5) Store integer result -* - LA R7,16(0,R7) Point to next short BFP result pair - LA R3,32(0,R3) Point to next short BFP integer pair - LA R8,32(0,R8) Point to next long BFP result pair - LA R4,32(0,R4) Point to next long BFP integer pair - LA R9,32(0,R9) Point to next ext. BFP result - LA R5,16(0,R5) Point to next ext. BFP integer -* - BCTR R2,R13 Convert next pair of BFP values - BR R12 Return to caller -* - END \ No newline at end of file diff --git a/tests/ieee-sqrts.core b/tests/ieee-sqrts.core deleted file mode 100644 index 07ab142d4..000000000 Binary files a/tests/ieee-sqrts.core and /dev/null differ diff --git a/tests/ieee-sqrts.list b/tests/ieee-sqrts.list deleted file mode 100644 index 5d6831993..000000000 --- a/tests/ieee-sqrts.list +++ /dev/null @@ -1,331 +0,0 @@ -ASMA Ver. 0.2.0 23 Jun 2016 09:49:51 Page 1 - - LOC OBJECT CODE ADDR1 ADDR2 STMT - - 1 * - 2 * Tests five square root instructions: - 3 * SQUARE ROOT (extended BFP, RRE) - 4 * SQUARE ROOT (long BFP, RRE) - 5 * SQUARE ROOT (long BFP, RXE) - 6 * SQUARE ROOT (short BFP, RRE) - 7 * SQUARE ROOT (short BFP, RXE) - 8 * - 9 * Also tests the following twelve conversion instructions - 10 * CONVERT FROM FIXED (32 to short BFP, RRE) - 11 * CONVERT FROM FIXED (32 to long BFP, RRE) - 12 * CONVERT FROM FIXED (32 to extended BFP, RRE) - 13 * CONVERT TO FIXED (32 to short BFP, RRE) - 14 * CONVERT TO FIXED (32 to long BFP, RRE) - 15 * CONVERT TO FIXED (32 to extended BFP, RRE) - 16 * CONVERT FROM FIXED (64 to short BFP, RRE) - 17 * CONVERT FROM FIXED (64 to long BFP, RRE) - 18 * CONVERT FROM FIXED (64 to extended BFP, RRE) - 19 * CONVERT TO FIXED (64 to short BFP, RRE) - 20 * CONVERT TO FIXED (64 to long BFP, RRE) - 21 * CONVERT TO FIXED (64 to extended BFP, RRE) - 22 * - 23 * Also tests the following floating point support instructions - 24 * LOAD (Short) - 25 * LOAD (Long) - 26 * LOAD ZERO (Long) - 27 * STORE (Short) - 28 * STORE (Long) - 29 * - 30 * Convert integers 1, 2, 4, 16 to each BFP floating point format - 31 * Take the square root of each in each BFP format - 32 * Convert back to integers (Note: SQRT(2) will/should round) - 33 * Because all inputs must be positive, we'll use this rig to test - 34 * logical (unsigned) conversions when that support is added to - 35 * Hercules. And we will test 32 and 64 bit logical conversions. - 36 * The comments will still say "integers" though. - 37 * - 0000000000000000 00000000000009B5 38 BFPSQRTS START 0 - 0000000000000000 0000000000000001 39 R0 EQU 0 - 0000000000000001 0000000000000001 40 R1 EQU 1 - 0000000000000002 0000000000000001 41 R2 EQU 2 - 0000000000000003 0000000000000001 42 R3 EQU 3 - 0000000000000004 0000000000000001 43 R4 EQU 4 - 0000000000000005 0000000000000001 44 R5 EQU 5 - 0000000000000006 0000000000000001 45 R6 EQU 6 - 0000000000000007 0000000000000001 46 R7 EQU 7 - 0000000000000008 0000000000000001 47 R8 EQU 8 - 0000000000000009 0000000000000001 48 R9 EQU 9 - 000000000000000A 0000000000000001 49 R10 EQU 10 - 000000000000000B 0000000000000001 50 R11 EQU 11 - 000000000000000C 0000000000000001 51 R12 EQU 12 - 000000000000000D 0000000000000001 52 R13 EQU 13 - ASMA Ver. 0.2.0 23 Jun 2016 09:49:51 Page 2 - - LOC OBJECT CODE ADDR1 ADDR2 STMT - - 000000000000000E 0000000000000001 53 R14 EQU 14 - 000000000000000F 0000000000000001 54 R15 EQU 15 -0000000000000000 0000000000000000 55 USING *,0 -0000000000000000 0000000000000000 00000000000001A0 56 ORG BFPSQRTS+X'1A0' -00000000000001A0 00000001 80000000 57 DC X'0000000180000000',AD(STARTNAN) z/Arch restart PSW -00000000000001B0 00000000000001B0 00000000000001D0 58 ORG BFPSQRTS+X'1D0' -00000000000001D0 00020000 00000000 59 DC X'0002000000000000000000000000DEAD' z/Arch pgm chk new PSW -00000000000001E0 00000000000001E0 0000000000000200 60 ORG BFPSQRTS+X'200' - 61 * - 62 * Mainline program. - 63 * -0000000000000200 B600 0230 0000000000000230 64 STARTNAN STCTL R0,R0,CTLR0 Store CR0 to enable AFP -0000000000000204 9604 0231 0000000000000231 65 OI CTLR0+1,X'04' Turn on AFP bit -0000000000000208 B700 0230 0000000000000230 66 LCTL R0,R0,CTLR0 Reload updated CR0 -000000000000020C 45C0 0882 0000000000000882 67 BAL R12,CVTINPUT Convert inputs to binary formats -0000000000000210 45C0 0800 0000000000000800 68 BAL R12,TESTSQRT Perform subtractions -0000000000000214 45C0 08EE 00000000000008EE 69 BAL R12,CVTOUTS Convert results to integers -0000000000000218 B2B2 0220 0000000000000220 70 LPSWE WAITPSW All done, load enabled wait PSW -0000000000000220 71 DS 0D Ensure correct alignment for PSW - 72 * - 73 * -0000000000000220 00020000 00000000 74 WAITPSW DC X'00020000000000000000000000000000' Disabled wait state PSW - normal completion -0000000000000230 00000000 75 CTLR0 DS F Control register 0 (bit45 AFP control) - 76 * -0000000000000234 0000000000000234 0000000000000480 77 ORG BFPSQRTS+X'480' - 78 * asma does not support doubleword integers, so we'll just do F'0' then F'value' -0000000000000480 79 INTVALS DS 0D Four doublewords -0000000000000480 00000000 80 DC F'0' -0000000000000484 00000001 81 DC F'1' first test integer -0000000000000488 00000000 82 DC F'0' -000000000000048C 00000002 83 DC F'2' second test integer -0000000000000490 00000000 84 DC F'0' -0000000000000494 00000004 85 DC F'4' third test integer -0000000000000498 00000000 86 DC F'0' -000000000000049C 00000010 87 DC F'16' fourth test integer - 88 * - 0000000000000410 0000000000000000 89 SHORTBFP EQU BFPSQRTS+X'410' 4F 410.10 four test cases in short bfp - 0000000000000420 0000000000000000 90 LONGBFP EQU BFPSQRTS+X'420' 4D 420.20 four test cases in long bfp - 0000000000000440 0000000000000000 91 EXTBFP EQU BFPSQRTS+X'440' 8D 440.40 four test cases in extended bfp - 92 - 0000000000000500 0000000000000000 93 SHORTRES EQU BFPSQRTS+X'500' 8F 500.20 Short square root results (4 pairs, RXE & RRE) - 0000000000000520 0000000000000000 94 LONGRES EQU BFPSQRTS+X'520' 8D 520.40 Long square root results (4 pairs, RXE & RRE) - 0000000000000560 0000000000000000 95 EXTRES EQU BFPSQRTS+X'560' 8D 560.40 Extended square root results (4, RRE only) - 96 * - 0000000000000A00 0000000000000000 97 ISHBFP EQU BFPSQRTS+X'A00' 8D A00.40 Convert short BFP to Integer results - 0000000000000A40 0000000000000000 98 ILNBFP EQU BFPSQRTS+X'A40' 8D A40.40 Convert long BFP to Integer results - 0000000000000A80 0000000000000000 99 IXTBFP EQU BFPSQRTS+X'A80' 8F A80.20 Convert extended BFP to Integer results -00000000000004A0 00000000000004A0 0000000000000800 100 ORG BFPSQRTS+X'800' - 101 * - 102 * - 103 * - 104 * Take square roots of the four test cases in each precision - ASMA Ver. 0.2.0 23 Jun 2016 09:49:51 Page 3 - - LOC OBJECT CODE ADDR1 ADDR2 STMT - - 105 * -0000000000000800 106 TESTSQRT DS 0H - 107 * Calculate square roots of values -0000000000000800 4120 0004 0000000000000004 108 LA R2,4 Set count of square root operations -0000000000000804 4130 0500 0000000000000500 109 LA R3,SHORTRES Point to start of short BFP results -0000000000000808 4140 0520 0000000000000520 110 LA R4,LONGRES Point to start of long BFP results -000000000000080C 4150 0560 0000000000000560 111 LA R5,EXTRES Point to start of extended BFP results -0000000000000810 4170 0410 0000000000000410 112 LA R7,SHORTBFP Point to start of short BFP input values -0000000000000814 4180 0420 0000000000000420 113 LA R8,LONGBFP Point to start of long BFP input values -0000000000000818 4190 0440 0000000000000440 114 LA R9,EXTBFP Point to start of extended BFP input values -000000000000081C 0DD0 115 BASR R13,0 Set top of loop - 116 * Top of loop; clear residuals from FPR0-1 -000000000000081E B375 0000 117 SQRTLOOP LZDR R0 Zero FPR0 -0000000000000822 B375 0010 118 LZDR R1 Zero FPR1 - 119 * BFP Short square root RXE and RRE -0000000000000826 ED00 7000 0014 0000000000000000 120 SQEB R0,0(0,R7) Put square root of test case in FPR0 -000000000000082C 7000 3000 0000000000000000 121 STE R0,0(0,R3) Store short BFP result from RXE -0000000000000830 7810 7000 0000000000000000 122 LE R1,0(0,R7) Get test case for RRE instruction -0000000000000834 B314 0001 123 SQEBR R0,R1 Add BFP values, result in FPR0 -0000000000000838 7000 3004 0000000000000004 124 STE R0,4(0,R3) Store short BFP from RRE -000000000000083C 4170 7004 0000000000000004 125 LA R7,4(0,R7) Point to next short BFP test case -0000000000000840 4130 3008 0000000000000008 126 LA R3,8(0,R3) Point to next short BFP result pair - 127 * BFP Long square root RXE and RRE -0000000000000844 ED00 8000 0015 0000000000000000 128 SQDB R0,0(0,R8) Square root BFP long test case -000000000000084A 6000 4000 0000000000000000 129 STD R0,0(0,R4) Store long BFP result from RXE -000000000000084E 6810 8000 0000000000000000 130 LD R1,0(0,R8) Get BFP long test case -0000000000000852 B315 0001 131 SQDBR R0,R1 Take square root, result in FPR0 -0000000000000856 6000 4008 0000000000000008 132 STD R0,8(0,R4) Store long BFP from RRE -000000000000085A 4180 8008 0000000000000008 133 LA R8,8(0,R8) Point to next long BFP test case -000000000000085E 4140 4010 0000000000000010 134 LA R4,16(0,R4) Point to next long BFP result pair - 135 * BFP Extended square root RRE -0000000000000862 6810 9000 0000000000000000 136 LD R1,0(0,R9) Get BFP ext. 1st half of test case -0000000000000866 6830 9008 0000000000000008 137 LD R3,8(0,R9) Get BFP ext. 2nd half of test case -000000000000086A B316 0001 138 SQXBR R0,R1 Add BFP values, result in FPR0-FPR2 -000000000000086E 6000 5000 0000000000000000 139 STD R0,0(0,R5) Store ext. BFP from RRE -0000000000000872 6020 5008 0000000000000008 140 STD R2,8(0,R5) Store ext. BFP from RRE -0000000000000876 4190 9010 0000000000000010 141 LA R9,16(0,R9) Point to next ext. BFP input -000000000000087A 4150 5010 0000000000000010 142 LA R5,16(0,R5) Point to next ext. BFP result -000000000000087E 062D 143 BCTR R2,R13 Square root next input pair -0000000000000880 07FC 144 BR R12 Return to caller - 145 * - 146 * Convert Integer test cases to each format of BFP. Half will be converted as - 147 * 32-bit unsigned integers, and the rest as 64-bit unsigned integers. - 148 * -0000000000000882 149 CVTINPUT DS 0H -0000000000000882 4120 0002 0000000000000002 150 LA R2,2 Set count of test input values -0000000000000886 4130 0480 0000000000000480 151 LA R3,INTVALS point to start of input values -000000000000088A 4170 0410 0000000000000410 152 LA R7,SHORTBFP Point to start of short BFP input values -000000000000088E 4180 0420 0000000000000420 153 LA R8,LONGBFP Point to start of long BFP input values -0000000000000892 4190 0440 0000000000000440 154 LA R9,EXTBFP Point to start of extended BFP input values -0000000000000896 0DD0 155 BASR R13,0 Set top of loop - 156 * convert integers to three BFP formats. 32 bit first, then 64 - ASMA Ver. 0.2.0 23 Jun 2016 09:49:51 Page 4 - - LOC OBJECT CODE ADDR1 ADDR2 STMT - -0000000000000898 5810 3004 0000000000000004 157 CVTLOOP L R1,4(0,R3) Get integer test value -000000000000089C B394 0001 158 CEFBR R0,R1 Cvt Int in GPR1 to float in FPR0 -00000000000008A0 7000 7000 0000000000000000 159 STE R0,0(0,R7) Store short BFP -00000000000008A4 B395 0001 160 CDFBR R0,R1 Cvt Int in GPR1 to float in FPR0 -00000000000008A8 6000 8000 0000000000000000 161 STD R0,0(0,R8) Store long BFP -00000000000008AC B396 0001 162 CXFBR R0,R1 Cvt Int in GPR1 to float in FPR0-FPR2 -00000000000008B0 6000 9000 0000000000000000 163 STD R0,0(0,R9) Store extended BFP part 1 -00000000000008B4 6020 9008 0000000000000008 164 STD R2,8(0,R9) Store extended BFP part 2 -00000000000008B8 E310 3008 0004 0000000000000008 165 LG R1,8(0,R3) Get integer test value -00000000000008BE B3A4 0001 166 CEGBR R0,R1 Cvt Int in GPR1 to float in FPR0 -00000000000008C2 7000 7004 0000000000000004 167 STE R0,4(0,R7) Store short BFP -00000000000008C6 B3A5 0001 168 CDGBR R0,R1 Cvt Int in GPR1 to float in FPR0 -00000000000008CA 6000 8008 0000000000000008 169 STD R0,8(0,R8) Store long BFP -00000000000008CE B3A6 0001 170 CXGBR R0,R1 Cvt Int in GPR1 to float in FPR0-FPR2 -00000000000008D2 6000 9010 0000000000000010 171 STD R0,16(0,R9) Store extended BFP part 1 -00000000000008D6 6020 9018 0000000000000018 172 STD R2,24(0,R9) Store extended BFP part 2 -00000000000008DA 4130 3010 0000000000000010 173 LA R3,16(0,R3) point to next input value pair -00000000000008DE 4170 7008 0000000000000008 174 LA R7,8(0,R7) Point to next pair of short BFP converted values -00000000000008E2 4180 8010 0000000000000010 175 LA R8,16(0,R8) Point to next pair of long BFP converted values -00000000000008E6 4190 9020 0000000000000020 176 LA R9,32(0,R9) Point to next pair of extended BFP converted values -00000000000008EA 062D 177 BCTR R2,R13 Convert next input value pair. -00000000000008EC 07FC 178 BR R12 All converted, return to main line. - 179 * - 180 * Convert back to integers - 181 * -00000000000008EE 182 CVTOUTS DS 0H -00000000000008EE 4120 0002 0000000000000002 183 LA R2,2 Set count of square root result pairs -00000000000008F2 4170 0500 0000000000000500 184 LA R7,SHORTRES Point to start of short BFP results -00000000000008F6 4180 0520 0000000000000520 185 LA R8,LONGRES Point to start of long BFP results -00000000000008FA 4190 0560 0000000000000560 186 LA R9,EXTRES Point to start of extended BFP results -00000000000008FE 4130 0A00 0000000000000A00 187 LA R3,ISHBFP Point to start of short BFP Integer results -0000000000000902 4140 0A40 0000000000000A40 188 LA R4,ILNBFP Point to start of long BFP integer results -0000000000000906 4150 0A80 0000000000000A80 189 LA R5,IXTBFP Point to start of extended BFP integer results -000000000000090A 0DD0 190 BASR R13,0 Set top of loop - 191 * - 192 * Convert shorts back to integer - 193 * -000000000000090C B375 0000 194 INTLOOP LZDR R0 Zero FPR0 -0000000000000910 7800 7000 0000000000000000 195 LE R0,0(0,R7) Get BFP short result RXE -0000000000000914 B398 0000 196 CFEBR R0,R0 Convert to integer in r0 -0000000000000918 5000 3004 0000000000000004 197 ST R0,4(0,R3) Store integer result -000000000000091C 7800 7004 0000000000000004 198 LE R0,4(0,R7) Get BFP short result RRE -0000000000000920 B398 0000 199 CFEBR R0,R0 Convert to integer in r0 -0000000000000924 5000 300C 000000000000000C 200 ST R0,12(0,R3) Store integer result - 201 * -0000000000000928 7800 7008 0000000000000008 202 LE R0,8(0,R7) Get BFP short result RXE -000000000000092C B3A8 0000 203 CGEBR R0,R0 Convert to integer 64 in r0 -0000000000000930 E300 3010 0024 0000000000000010 204 STG R0,16(0,R3) Store integer result -0000000000000936 7800 700C 000000000000000C 205 LE R0,12(0,R7) Get BFP short result RRE -000000000000093A B3A8 0000 206 CGEBR R0,R0 Convert to integer 64 in r0 -000000000000093E E300 3018 0024 0000000000000018 207 STG R0,24(0,R3) Store integer result - 208 * - ASMA Ver. 0.2.0 23 Jun 2016 09:49:51 Page 5 - - LOC OBJECT CODE ADDR1 ADDR2 STMT - -0000000000000944 6800 8000 0000000000000000 209 LD R0,0(0,R8) Get BFP long result RXE -0000000000000948 B399 0000 210 CFDBR R0,R0 Convert to integer in r0 -000000000000094C 5000 4004 0000000000000004 211 ST R0,4(0,R4) Store integer result -0000000000000950 6800 8008 0000000000000008 212 LD R0,8(0,R8) Get BFP long result RRE -0000000000000954 B399 0000 213 CFDBR R0,R0 Convert to integer in r0 -0000000000000958 5000 400C 000000000000000C 214 ST R0,12(0,R4) Store integer result - 215 * -000000000000095C 6800 8010 0000000000000010 216 LD R0,16(0,R8) Get BFP long result RXE -0000000000000960 B3A9 0000 217 CGDBR R0,R0 Convert to integer 64 in r0 -0000000000000964 E300 4010 0024 0000000000000010 218 STG R0,16(0,R4) Store integer result -000000000000096A 6800 8018 0000000000000018 219 LD R0,24(0,R8) Get BFP long result RRE -000000000000096E B3A9 0000 220 CGDBR R0,R0 Convert to integer 64 in r0 -0000000000000972 E300 4018 0024 0000000000000018 221 STG R0,24(0,R4) Store integer result - 222 * -0000000000000978 6800 9000 0000000000000000 223 LD R0,0(0,R9) Get BFP ext. 1st half -000000000000097C 6820 9008 0000000000000008 224 LD R2,8(0,R9) Get BFP ext. 2nd half -0000000000000980 B39A 0000 225 CFXBR R0,R0 Convert BFP Ext. to Integer-32 -0000000000000984 5000 5004 0000000000000004 226 ST R0,4(0,R5) Store integer result lower word - 227 * -0000000000000988 6800 9010 0000000000000010 228 LD R0,16(0,R9) Get BFP ext. 1st half -000000000000098C 6820 9018 0000000000000018 229 LD R2,24(0,R9) Get BFP ext. 2nd half -0000000000000990 B3AA 0000 230 CGXBR R0,R0 Convert BFP Ext. to Integer-64 -0000000000000994 E300 5008 0024 0000000000000008 231 STG R0,8(0,R5) Store integer result - 232 * -000000000000099A 4170 7010 0000000000000010 233 LA R7,16(0,R7) Point to next short BFP result pair -000000000000099E 4130 3020 0000000000000020 234 LA R3,32(0,R3) Point to next short BFP integer pair -00000000000009A2 4180 8020 0000000000000020 235 LA R8,32(0,R8) Point to next long BFP result pair -00000000000009A6 4140 4020 0000000000000020 236 LA R4,32(0,R4) Point to next long BFP integer pair -00000000000009AA 4190 9020 0000000000000020 237 LA R9,32(0,R9) Point to next ext. BFP result -00000000000009AE 4150 5010 0000000000000010 238 LA R5,16(0,R5) Point to next ext. BFP integer - 239 * -00000000000009B2 062D 240 BCTR R2,R13 Convert next pair of BFP values -00000000000009B4 07FC 241 BR R12 Return to caller - 242 * -00000000000009B6 243 END - ASMA Ver. 0.2.0 23 Jun 2016 09:49:51 Page 6 - - SYMBOL TYPE VALUE LENGTH DEFN REFERENCES - -BFPSQRTS J 000000 2486 38 56 58 60 77 89 90 91 93 94 95 97 98 99 100 -CTLR0 F 000230 4 75 64 65 66 -CVTINPUT H 000882 2 149 67 -CVTLOOP I 000898 4 157 -CVTOUTS H 0008EE 2 182 69 -EXTBFP U 000440 0 91 114 154 -EXTRES U 000560 0 95 111 186 -ILNBFP U 000A40 0 98 188 -IMAGE 1 000000 2486 0 -INTLOOP I 00090C 4 194 -INTVALS D 000480 8 79 151 -ISHBFP U 000A00 0 97 187 -IXTBFP U 000A80 0 99 189 -LONGBFP U 000420 0 90 113 153 -LONGRES U 000520 0 94 110 185 -R0 U 000000 1 39 64 66 117 120 121 123 124 128 129 131 132 138 139 158 159 160 161 - 162 163 166 167 168 169 170 171 194 195 196 197 198 199 200 202 203 - 204 205 206 207 209 210 211 212 213 214 216 217 218 219 220 221 223 - 225 226 228 230 231 -R1 U 000001 1 40 118 122 123 130 131 136 138 157 158 160 162 165 166 168 170 -R10 U 00000A 1 49 -R11 U 00000B 1 50 -R12 U 00000C 1 51 67 68 69 144 178 241 -R13 U 00000D 1 52 115 143 155 177 190 240 -R14 U 00000E 1 53 -R15 U 00000F 1 54 -R2 U 000002 1 41 108 140 143 150 164 172 177 183 224 229 240 -R3 U 000003 1 42 109 121 124 126 137 151 157 165 173 187 197 200 204 207 234 -R4 U 000004 1 43 110 129 132 134 188 211 214 218 221 236 -R5 U 000005 1 44 111 139 140 142 189 226 231 238 -R6 U 000006 1 45 -R7 U 000007 1 46 112 120 122 125 152 159 167 174 184 195 198 202 205 233 -R8 U 000008 1 47 113 128 130 133 153 161 169 175 185 209 212 216 219 235 -R9 U 000009 1 48 114 136 137 141 154 163 164 171 172 176 186 223 224 228 229 237 -SHORTBFP U 000410 0 89 112 152 -SHORTRES U 000500 0 93 109 184 -SQRTLOOP I 00081E 4 117 -STARTNAN I 000200 4 64 57 -TESTSQRT H 000800 2 106 68 -WAITPSW X 000220 16 74 70 - ASMA Ver. 0.2.0 23 Jun 2016 09:49:51 Page 7 - -MACRO DEFN REFERENCES - -No defined macros - ASMA Ver. 0.2.0 23 Jun 2016 09:49:51 Page 8 - - DESC SYMBOL SIZE POS ADDR - -Entry: 0 - -Image IMAGE 2486 000-9B5 000-9B5 - Region 2486 000-9B5 000-9B5 - CSECT BFPSQRTS 2486 000-9B5 000-9B5 - ASMA Ver. 0.2.0 23 Jun 2016 09:49:51 Page 9 - - STMT FILE NAME - -1 C:\Users\srorso\Documents\GitHub\hyperion\tests\ieee-sqrts.asm - - -** NO ERRORS FOUND ** - - \ No newline at end of file diff --git a/tests/ieee-sqrts.tst b/tests/ieee-sqrts.tst deleted file mode 100644 index a8947834c..000000000 --- a/tests/ieee-sqrts.tst +++ /dev/null @@ -1,142 +0,0 @@ -* -*Testcase ieee-sqrts.tst: IEEE Square Root, Convert From/To Fixed -*Message Testcase ieee-sqrts.tst: IEEE Square Root, Convert From/To Fixed -*Message ..Includes SQUARE ROOT (5), CONVERT FROM/TO FIXED 32 (6), 11 instr total -* -* SQUARE ROOT tests - Binary Floating Point -* -# -# Tests five square root instructions: -# SQUARE ROOT (extended BFP, RRE) -# SQUARE ROOT (long BFP, RRE) -# SQUARE ROOT (long BFP, RXE) -# SQUARE ROOT (short BFP, RRE) -# SQUARE ROOT (short BFP, RXE) -# -# Also tests the following twelve conversion instructions -# CONVERT FROM FIXED (32 to short BFP, RRE) -# CONVERT FROM FIXED (32 to long BFP, RRE) -# CONVERT FROM FIXED (32 to extended BFP, RRE) -# CONVERT TO FIXED (32 to short BFP, RRE) -# CONVERT TO FIXED (32 to long BFP, RRE) -# CONVERT TO FIXED (32 to extended BFP, RRE) -# CONVERT FROM FIXED (64 to short BFP, RRE) -# CONVERT FROM FIXED (64 to long BFP, RRE) -# CONVERT FROM FIXED (64 to extended BFP, RRE) -# CONVERT TO FIXED (64 to short BFP, RRE) -# CONVERT TO FIXED (64 to long BFP, RRE) -# CONVERT TO FIXED (64 to extended BFP, RRE) -# -# Also tests the following floating point support instructions -# LOAD (Short) -# LOAD (Long) -# LOAD ZERO (Long) -# STORE (Short) -# STORE (Long) -# -# Convert integers 1, 2, 4, 16 to each BFP floating point format -# Take the square root of each in each BFP format -# Convert back to integers (Note: SQRT(2) will/should round) -# Because all inputs must be positive, we'll use this rig to test -# logical (unsigned) conversions when that support is added to -# Hercules. And we will test 32 and 64 bit logical conversions. -# The comments will still say "integers" though. -# -sysclear -archmode esame -loadcore "$(testpath)/ieee-sqrts.core" -runtest .1 - -*Compare -r 410.10 # Inputs converted to BFP short -*Want "CEFBR/CEGBR test pairs 1-2" 3F800000 40000000 40800000 41800000 - -*Compare -r 420.10 # Inputs converted to BFP long one of two -*Want "CDFBR/CDGBR test pair 1" 3FF00000 00000000 40000000 00000000 -*Compare -r 430.10 # Inputs converted to BFP long two of two -*Want "CDFBR/CDGBR test pair 2" 40100000 00000000 40300000 00000000 - -*Compare -r 440.10 # Inputs converted to BFP ext one of four -*Want "CXFBR test 1" 3FFF0000 00000000 00000000 00000000 -*Compare -r 450.10 # Inputs converted to BFP ext two of four -*Want "CXGBR test 1" 40000000 00000000 00000000 00000000 -*Compare -r 460.10 # Inputs converted to BFP ext three of four -*Want "CXFBR test 2" 40010000 00000000 00000000 00000000 -*Compare -r 470.10 # Inputs converted to BFP ext four of four -*Want "CXGBR test 2" 40030000 00000000 00000000 00000000 - -*Compare -r 500.10 # BFP short square roots RXE and RRE part 1 -*Want "SQEB/SQEBR Tests 1-2" 3F800000 3F800000 3FB504F3 3FB504F3 -*Compare -r 510.10 # BFP short square roots RXE and RRE part 2 -*Want "SQEB/SQEBR Tests 3-4" 40000000 40000000 40800000 40800000 - -*Compare -r 520.10 # BFP long square roots RXE and RRE part 1 -*Want "SQDB/SQDBR Test 1" 3FF00000 00000000 3FF00000 00000000 -*Compare -r 530.10 # BFP long square roots RXE and RRE part 2 -*Want "SQDB/SQDBR Test 2" 3FF6A09E 667F3BCD 3FF6A09E 667F3BCD -*Compare -r 540.10 # BFP long square roots RXE and RRE part 3 -*Want "SQDB/SQDBR Test 3" 40000000 00000000 40000000 00000000 -*Compare -r 550.10 # BFP long square roots RXE and RRE part 4 -*Want "SQDB/SQDBR Test 4" 40100000 00000000 40100000 00000000 - -*Compare -r 560.10 # BFP extended square roots RRE part 1 -*Want "SQXBR test 1" 3FFF0000 00000000 00000000 00000000 -*Compare -r 570.10 # BFP extended square roots RRE part 2 -*Want "SQXBR test 2" 3FFF6A09 E667F3BC C908B2FB 1366EA95 -*Compare -r 580.10 # BFP extended square roots RRE part 3 -*Want "SQXBR test 3" 40000000 00000000 00000000 00000000 -*Compare -r 590.10 # BFP extended square roots RRE part 4 -*Want "SQXBR test 4" 40010000 00000000 00000000 00000000 - - -*Compare -r A00.10 # Short BFP to Integer results part 1 -*Want "CFEBR Test pair 1" 00000000 00000001 00000000 00000001 -*Compare -r A10.10 # Short BFP to Integer results part 2 -*Want "CGEBR Test pair 1" 00000000 00000001 00000000 00000001 -*Compare -r A20.10 # Short BFP to Integer results part 3 -*Want "CFEBR Test pair 2" 00000000 00000002 00000000 00000002 -*Compare -r A30.10 # Short BFP to Integer results part 4 -*Want "CGEBR Test pair 2" 00000000 00000004 00000000 00000004 - -*Compare -r A40.10 # Convert long BFP to Integer results part 1 -*Want "CFDBR Test pair 1" 00000000 00000001 00000000 00000001 -*Compare -r A50.10 # Convert long BFP to Integer results part 2 -*Want "CGDBR Test pair 1" 00000000 00000001 00000000 00000001 -*Compare -r A60.10 # Convert long BFP to Integer results part 3 -*Want "CFDBR Test pair 2" 00000000 00000002 00000000 00000002 -*Compare -r A70.10 # Convert long BFP to Integer results part 4 -*Want "CGDBR Test pair 2" 00000000 00000004 00000000 00000004 - -*Compare -r A80.10 # Convert extended BFP to Integer results part 1 -*Want "CFXBR/CGXBR Test Pair 1" 00000000 00000001 00000000 00000001 -*Compare -r A90.10 # Convert extended BFP to Integer results part 2 -*Want "CFXBR/CGXBR Test Pair 2" 00000000 00000002 00000000 00000004 - -*Done - diff --git a/tests/ieee-subs.asm b/tests/ieee-subs.asm deleted file mode 100644 index 2f08f226d..000000000 --- a/tests/ieee-subs.asm +++ /dev/null @@ -1,202 +0,0 @@ -* -* Tests five subtraction instructions: -* SUBTRACT (extended BFP, RRE) -* SUBTRACT (long BFP, RRE) -* SUBTRACT (long BFP, RXE) -* SUBTRACT (short BFP, RRE) -* SUBTRACT (short BFP, RXE) -* -* Also tests the following six conversion instructions -* CONVERT FROM FIXED (64 to short BFP, RRE) -* CONVERT FROM FIXED (64 to long BFP, RRE) -* CONVERT FROM FIXED (64 to extended BFP, RRE) -* CONVERT TO FIXED (64 to short BFP, RRE) -* CONVERT TO FIXED (64 to long BFP, RRE) -* CONVERT TO FIXED (64 to extended BFP, RRE) -* -* Also tests the following floating point support instructions -* LOAD (Short) -* LOAD (Long) -* LOAD ZERO (Long) -* STORE (Short) -* STORE (Long) -* -* Convert integers 2, 1, 4, and -2 to each BFP floating point format -* Subtract the second from the first (2 - 1, 4 - -2) in each format -* Convert the results back to integers (none should round) -* -BFPSUBS START 0 -R0 EQU 0 -R1 EQU 1 -R2 EQU 2 -R3 EQU 3 -R4 EQU 4 -R5 EQU 5 -R6 EQU 6 -R7 EQU 7 -R8 EQU 8 -R9 EQU 9 -R10 EQU 10 -R11 EQU 11 -R12 EQU 12 -R13 EQU 13 -R14 EQU 14 -R15 EQU 15 - USING *,0 - ORG BFPSUBS+X'1A0' - DC X'0000000180000000',AD(STARTSUB) z/Arch restart PSW - ORG BFPSUBS+X'1D0' - DC X'0002000000000000000000000000DEAD' z/Arch pgm chk new PSW - ORG BFPSUBS+X'200' -STARTSUB STCTL R0,R0,CTLR0 Store CR0 to enable AFP - OI CTLR0+1,X'04' Turn on AFP bit - LCTL R0,R0,CTLR0 Reload updated CR0 - BAS R12,CVTINPUT Convert inputs to binary formats - BAS R12,TESTSUB Perform subtractions - BAS R12,CVTOUTS Convert results to integers - LPSWE WAITPSW All done, load enabled wait PSW -* -* -* Subtract pairs of values from each other -TESTSUB DS 0H - LA R2,2 Set count of subtraction operations - LA R3,SHORTRES Point to start of short BFP results - LA R4,LONGRES Point to start of long BFP results - LA R5,EXTRES Point to start of extended BFP results - LA R7,SHORTBFP Point to start of short BFP input values - LA R8,LONGBFP Point to start of long BFP input values - LA R9,EXTBFP Point to start of extended BFP input values -* Top of loop; clear residuals from FPR0-1 -SUBLOOP LZDR R0 Zero FPR0 - LZDR R1 Zero FPR1 -* BFP Short subtraction RXE and RRE - LE R0,0(0,R7) Get BFP short first of pair - SEB R0,4(0,R7) Subtract BFP short second of pair - STE R0,0(0,R3) Store short BFP result from RXE - LE R0,0(0,R7) Get BFP short first of pair - LE R1,4(0,R7) Get BFP short second of pair - SEBR R0,R1 Subtract BFP values, result in FPR0 - STE R0,4(0,R3) Store short BFP from RRE - LA R7,8(0,R7) Point to next short BFP input pair - LA R3,8(0,R3) Point to next short BFP result pair -* BFP Long subtraction RXE and RRE - LD R0,0(0,R8) Get BFP long first of pair - SDB R0,8(0,R8) Subtract BFP long second of pair - STD R0,0(0,R4) Store long BFP result from RXE - LD R0,0(0,R8) Get BFP long first of pair - LD R1,8(0,R8) Get BFP long second of pair - SDBR R0,R1 Subtract BFP values, result in FPR0 - STD R0,8(0,R4) Store long BFP from RRE - LA R8,16(0,R8) Point to next long BFP input pair - LA R4,16(0,R4) Point to next long BFP result pair -* BFP Extended subtraction RRE - LD R0,0(0,R9) Get BFP ext. 1st half of first of pair - LD R2,8(0,R9) Get BFP ext. 2nd half of first of pair - LD R1,16(0,R9) Get BFP ext. 1st half of second of pair - LD R3,24(0,R9) Get BFP ext. 2nd half of second of pair - SXBR R0,R1 Subtract BFP values, result in FPR0-FPR2 - STD R0,0(0,R5) Store ext. BFP from RRE - STD R2,8(0,R5) Store ext. BFP from RRE - LA R9,32(0,R9) Point to next ext. BFP input pair - LA R5,16(0,R5) Point to next ext. BFP result -* - BCT R2,SUBLOOP Subtract next input pair - BR R12 Tests done, return to mainline -* -* -* - DS 0D Ensure correct alignment for PSW -WAITPSW DC X'00020000000000000000000000000000' Disabled wait state PSW - normal completion -CTLR0 DS F Control register 0 (bit45 AFP control) -* - ORG BFPSUBS+X'480' -INTVALS DS 0D Ensure alignment for 64-bit ints - DC F'0',F'2' 2 first test integer - DC F'0',F'1' 1 second test integer - DC F'0',F'4' 4 third test integer - DC F'-1',F'-2' -2 fourth test integer -* -SHORTBFP EQU BFPSUBS+X'410' 410.10 test inputs in short bfp - -LONGBFP EQU BFPSUBS+X'420' 420.20 test inputs in long bfp - -EXTBFP EQU BFPSUBS+X'440' 440.40 test inputs in extended bfp - -SHORTRES EQU BFPSUBS+X'500' 500.10 Short subtraction results (2 pairs, RXE & RRE) -LONGRES EQU BFPSUBS+X'510' 510.20 Long subtraction results (2 pairs, RXE & RRE) -EXTRES EQU BFPSUBS+X'530' 530.20 Extended subtraction results (1 pair, RRE only) - -ISHBFP EQU BFPSUBS+X'550' 550.20 Convert short BFP to 64-bit Integer results -ILNBFP EQU BFPSUBS+X'570' 570.20 Convert long BFP to 64-bit Integer results -IXTBFP EQU BFPSUBS+X'590' 590.10 Convert extended BFP to 64-bit Integer results -* -* -* Subroutine: convert 64-bit integers into BFP in all precisions -* - ORG BFPSUBS+X'800' -CVTINPUT DS 0H Input conversion routine - LA R2,4 Set count of 64-bit test input values - LA R3,INTVALS point to start of input values - LA R7,SHORTBFP Point to start of short BFP input values - LA R8,LONGBFP Point to start of long BFP input values - LA R9,EXTBFP Point to start of extended BFP input values - BASR R13,0 Set top of loop -* convert integers to three BFP formats -CVTLOOP LG R1,0(0,R3) Get integer test value - CEGBR R0,R1 Cvt Int in GPR1 to short float in FPR0 - STE R0,0(0,R7) Store short BFP - CDGBR R0,R1 Cvt Int in GPR1 to long float in FPR0 - STD R0,0(0,R8) Store long BFP - CXGBR R0,R1 Cvt Int in GPR1 to ext float in FPR0-FPR2 - STD R0,0(0,R9) Store extended BFP part 1 - STD R2,8(0,R9) Store extended BFP part 2 - LA R3,8(0,R3) point to next input values - LA R7,4(0,R7) Point to next short BFP converted values - LA R8,8(0,R8) Point to next long BFP converted values - LA R9,16(0,R9) Point to next extended BFP converted values - BCTR R2,R13 Convert next input value. - BR R12 Conversion done, return to mainline -* -* -* Convert back to integers -* -CVTOUTS DS 0H - LA R2,2 Set count of subtraction operations - LA R7,SHORTRES Point to start of short BFP results - LA R8,LONGRES Point to start of long BFP results - LA R9,EXTRES Point to start of extended BFP results - LA R3,ISHBFP Point to start of short BFP Integer results - LA R4,ILNBFP Point to start of long BFP integer results - LA R5,IXTBFP Point to start of extended BFP integer results - BASR R13,0 Set top of loop -* -INTLOOP LZDR R0 Zero FPR0 -* Convert shorts back to integer - LE R0,0(0,R7) Get BFP short result first of pair - CGEBR R0,R0 Convert to integer in r0 - STG R0,0(0,R3) Store integer result - LE R0,4(0,R7) Get BFP short result second of pair -* - CGEBR R0,R0 Convert to integer in r0 - STG R0,8(0,R3) Store integer result -* - LD R0,0(0,R8) Get BFP long result first of pair - CGDBR R0,R0 Convert to integer in r0 - STG R0,0(0,R4) Store integer result - LD R0,8(0,R8) Get BFP long result second of pair - CGDBR R0,R0 Convert to integer in r0 - STG R0,8(0,R4) Store integer result -* - LD R0,0(0,R9) Get BFP ext. 1st half of first of pair - LD R2,8(0,R9) Get BFP ext. 2nd half of first of pair - CGXBR R0,R0 Convert BFP Ext. to Integer-64 - STG R0,0(0,R5) Store integer result lower word -* - LA R7,8(0,R7) Point to next short BFP input pair - LA R3,16(0,R3) Point to next short BFP integer pair - LA R8,16(0,R8) Point to next long BFP input pair - LA R4,16(0,R4) Point to next long BFP integer pair - LA R9,16(0,R9) Point to next ext. BFP input - LA R5,8(0,R5) Point to next ext. BFP integer - BCTR R2,R13 Subtract next input pair - BR R12 Conversion done, return to mainline diff --git a/tests/ieee-subs.core b/tests/ieee-subs.core deleted file mode 100644 index 146fdf1a6..000000000 Binary files a/tests/ieee-subs.core and /dev/null differ diff --git a/tests/ieee-subs.list b/tests/ieee-subs.list deleted file mode 100644 index b974c6f2c..000000000 --- a/tests/ieee-subs.list +++ /dev/null @@ -1,285 +0,0 @@ -ASMA Ver. 0.2.0 23 Jun 2016 09:49:51 Page 1 - - LOC OBJECT CODE ADDR1 ADDR2 STMT - - 1 * - 2 * Tests five subtraction instructions: - 3 * SUBTRACT (extended BFP, RRE) - 4 * SUBTRACT (long BFP, RRE) - 5 * SUBTRACT (long BFP, RXE) - 6 * SUBTRACT (short BFP, RRE) - 7 * SUBTRACT (short BFP, RXE) - 8 * - 9 * Also tests the following six conversion instructions - 10 * CONVERT FROM FIXED (64 to short BFP, RRE) - 11 * CONVERT FROM FIXED (64 to long BFP, RRE) - 12 * CONVERT FROM FIXED (64 to extended BFP, RRE) - 13 * CONVERT TO FIXED (64 to short BFP, RRE) - 14 * CONVERT TO FIXED (64 to long BFP, RRE) - 15 * CONVERT TO FIXED (64 to extended BFP, RRE) - 16 * - 17 * Also tests the following floating point support instructions - 18 * LOAD (Short) - 19 * LOAD (Long) - 20 * LOAD ZERO (Long) - 21 * STORE (Short) - 22 * STORE (Long) - 23 * - 24 * Convert integers 2, 1, 4, and -2 to each BFP floating point format - 25 * Subtract the second from the first (2 - 1, 4 - -2) in each format - 26 * Convert the results back to integers (none should round) - 27 * - 0000000000000000 00000000000008D3 28 BFPSUBS START 0 - 0000000000000000 0000000000000001 29 R0 EQU 0 - 0000000000000001 0000000000000001 30 R1 EQU 1 - 0000000000000002 0000000000000001 31 R2 EQU 2 - 0000000000000003 0000000000000001 32 R3 EQU 3 - 0000000000000004 0000000000000001 33 R4 EQU 4 - 0000000000000005 0000000000000001 34 R5 EQU 5 - 0000000000000006 0000000000000001 35 R6 EQU 6 - 0000000000000007 0000000000000001 36 R7 EQU 7 - 0000000000000008 0000000000000001 37 R8 EQU 8 - 0000000000000009 0000000000000001 38 R9 EQU 9 - 000000000000000A 0000000000000001 39 R10 EQU 10 - 000000000000000B 0000000000000001 40 R11 EQU 11 - 000000000000000C 0000000000000001 41 R12 EQU 12 - 000000000000000D 0000000000000001 42 R13 EQU 13 - 000000000000000E 0000000000000001 43 R14 EQU 14 - 000000000000000F 0000000000000001 44 R15 EQU 15 -0000000000000000 0000000000000000 45 USING *,0 -0000000000000000 0000000000000000 00000000000001A0 46 ORG BFPSUBS+X'1A0' -00000000000001A0 00000001 80000000 47 DC X'0000000180000000',AD(STARTSUB) z/Arch restart PSW -00000000000001B0 00000000000001B0 00000000000001D0 48 ORG BFPSUBS+X'1D0' -00000000000001D0 00020000 00000000 49 DC X'0002000000000000000000000000DEAD' z/Arch pgm chk new PSW -00000000000001E0 00000000000001E0 0000000000000200 50 ORG BFPSUBS+X'200' -0000000000000200 B600 02C8 00000000000002C8 51 STARTSUB STCTL R0,R0,CTLR0 Store CR0 to enable AFP -0000000000000204 9604 02C9 00000000000002C9 52 OI CTLR0+1,X'04' Turn on AFP bit - ASMA Ver. 0.2.0 23 Jun 2016 09:49:51 Page 2 - - LOC OBJECT CODE ADDR1 ADDR2 STMT - -0000000000000208 B700 02C8 00000000000002C8 53 LCTL R0,R0,CTLR0 Reload updated CR0 -000000000000020C 4DC0 0800 0000000000000800 54 BAS R12,CVTINPUT Convert inputs to binary formats -0000000000000210 4DC0 021C 000000000000021C 55 BAS R12,TESTSUB Perform subtractions -0000000000000214 4DC0 084C 000000000000084C 56 BAS R12,CVTOUTS Convert results to integers -0000000000000218 B2B2 02B8 00000000000002B8 57 LPSWE WAITPSW All done, load enabled wait PSW - 58 * - 59 * - 60 * Subtract pairs of values from each other -000000000000021C 61 TESTSUB DS 0H -000000000000021C 4120 0002 0000000000000002 62 LA R2,2 Set count of subtraction operations -0000000000000220 4130 0500 0000000000000500 63 LA R3,SHORTRES Point to start of short BFP results -0000000000000224 4140 0510 0000000000000510 64 LA R4,LONGRES Point to start of long BFP results -0000000000000228 4150 0530 0000000000000530 65 LA R5,EXTRES Point to start of extended BFP results -000000000000022C 4170 0410 0000000000000410 66 LA R7,SHORTBFP Point to start of short BFP input values -0000000000000230 4180 0420 0000000000000420 67 LA R8,LONGBFP Point to start of long BFP input values -0000000000000234 4190 0440 0000000000000440 68 LA R9,EXTBFP Point to start of extended BFP input values - 69 * Top of loop; clear residuals from FPR0-1 -0000000000000238 B375 0000 70 SUBLOOP LZDR R0 Zero FPR0 -000000000000023C B375 0010 71 LZDR R1 Zero FPR1 - 72 * BFP Short subtraction RXE and RRE -0000000000000240 7800 7000 0000000000000000 73 LE R0,0(0,R7) Get BFP short first of pair -0000000000000244 ED00 7004 000B 0000000000000004 74 SEB R0,4(0,R7) Subtract BFP short second of pair -000000000000024A 7000 3000 0000000000000000 75 STE R0,0(0,R3) Store short BFP result from RXE -000000000000024E 7800 7000 0000000000000000 76 LE R0,0(0,R7) Get BFP short first of pair -0000000000000252 7810 7004 0000000000000004 77 LE R1,4(0,R7) Get BFP short second of pair -0000000000000256 B30B 0001 78 SEBR R0,R1 Subtract BFP values, result in FPR0 -000000000000025A 7000 3004 0000000000000004 79 STE R0,4(0,R3) Store short BFP from RRE -000000000000025E 4170 7008 0000000000000008 80 LA R7,8(0,R7) Point to next short BFP input pair -0000000000000262 4130 3008 0000000000000008 81 LA R3,8(0,R3) Point to next short BFP result pair - 82 * BFP Long subtraction RXE and RRE -0000000000000266 6800 8000 0000000000000000 83 LD R0,0(0,R8) Get BFP long first of pair -000000000000026A ED00 8008 001B 0000000000000008 84 SDB R0,8(0,R8) Subtract BFP long second of pair -0000000000000270 6000 4000 0000000000000000 85 STD R0,0(0,R4) Store long BFP result from RXE -0000000000000274 6800 8000 0000000000000000 86 LD R0,0(0,R8) Get BFP long first of pair -0000000000000278 6810 8008 0000000000000008 87 LD R1,8(0,R8) Get BFP long second of pair -000000000000027C B31B 0001 88 SDBR R0,R1 Subtract BFP values, result in FPR0 -0000000000000280 6000 4008 0000000000000008 89 STD R0,8(0,R4) Store long BFP from RRE -0000000000000284 4180 8010 0000000000000010 90 LA R8,16(0,R8) Point to next long BFP input pair -0000000000000288 4140 4010 0000000000000010 91 LA R4,16(0,R4) Point to next long BFP result pair - 92 * BFP Extended subtraction RRE -000000000000028C 6800 9000 0000000000000000 93 LD R0,0(0,R9) Get BFP ext. 1st half of first of pair -0000000000000290 6820 9008 0000000000000008 94 LD R2,8(0,R9) Get BFP ext. 2nd half of first of pair -0000000000000294 6810 9010 0000000000000010 95 LD R1,16(0,R9) Get BFP ext. 1st half of second of pair -0000000000000298 6830 9018 0000000000000018 96 LD R3,24(0,R9) Get BFP ext. 2nd half of second of pair -000000000000029C B34B 0001 97 SXBR R0,R1 Subtract BFP values, result in FPR0-FPR2 -00000000000002A0 6000 5000 0000000000000000 98 STD R0,0(0,R5) Store ext. BFP from RRE -00000000000002A4 6020 5008 0000000000000008 99 STD R2,8(0,R5) Store ext. BFP from RRE -00000000000002A8 4190 9020 0000000000000020 100 LA R9,32(0,R9) Point to next ext. BFP input pair -00000000000002AC 4150 5010 0000000000000010 101 LA R5,16(0,R5) Point to next ext. BFP result - 102 * -00000000000002B0 4620 0238 0000000000000238 103 BCT R2,SUBLOOP Subtract next input pair -00000000000002B4 07FC 104 BR R12 Tests done, return to mainline - ASMA Ver. 0.2.0 23 Jun 2016 09:49:51 Page 3 - - LOC OBJECT CODE ADDR1 ADDR2 STMT - - 105 * - 106 * - 107 * -00000000000002B8 108 DS 0D Ensure correct alignment for PSW -00000000000002B8 00020000 00000000 109 WAITPSW DC X'00020000000000000000000000000000' Disabled wait state PSW - normal completion -00000000000002C8 00000000 110 CTLR0 DS F Control register 0 (bit45 AFP control) - 111 * -00000000000002CC 00000000000002CC 0000000000000480 112 ORG BFPSUBS+X'480' -0000000000000480 113 INTVALS DS 0D Ensure alignment for 64-bit ints -0000000000000480 00000000 00000002 114 DC F'0',F'2' 2 first test integer -0000000000000488 00000000 00000001 115 DC F'0',F'1' 1 second test integer -0000000000000490 00000000 00000004 116 DC F'0',F'4' 4 third test integer -0000000000000498 FFFFFFFF FFFFFFFE 117 DC F'-1',F'-2' -2 fourth test integer - 118 * - 0000000000000410 0000000000000000 119 SHORTBFP EQU BFPSUBS+X'410' 410.10 test inputs in short bfp - 120 - 0000000000000420 0000000000000000 121 LONGBFP EQU BFPSUBS+X'420' 420.20 test inputs in long bfp - 122 - 0000000000000440 0000000000000000 123 EXTBFP EQU BFPSUBS+X'440' 440.40 test inputs in extended bfp - 124 - 0000000000000500 0000000000000000 125 SHORTRES EQU BFPSUBS+X'500' 500.10 Short subtraction results (2 pairs, RXE & RRE) - 0000000000000510 0000000000000000 126 LONGRES EQU BFPSUBS+X'510' 510.20 Long subtraction results (2 pairs, RXE & RRE) - 0000000000000530 0000000000000000 127 EXTRES EQU BFPSUBS+X'530' 530.20 Extended subtraction results (1 pair, RRE only) - 128 - 0000000000000550 0000000000000000 129 ISHBFP EQU BFPSUBS+X'550' 550.20 Convert short BFP to 64-bit Integer results - 0000000000000570 0000000000000000 130 ILNBFP EQU BFPSUBS+X'570' 570.20 Convert long BFP to 64-bit Integer results - 0000000000000590 0000000000000000 131 IXTBFP EQU BFPSUBS+X'590' 590.10 Convert extended BFP to 64-bit Integer results - 132 * - 133 * - 134 * Subroutine: convert 64-bit integers into BFP in all precisions - 135 * -00000000000004A0 00000000000004A0 0000000000000800 136 ORG BFPSUBS+X'800' -0000000000000800 137 CVTINPUT DS 0H Input conversion routine -0000000000000800 4120 0004 0000000000000004 138 LA R2,4 Set count of 64-bit test input values -0000000000000804 4130 0480 0000000000000480 139 LA R3,INTVALS point to start of input values -0000000000000808 4170 0410 0000000000000410 140 LA R7,SHORTBFP Point to start of short BFP input values -000000000000080C 4180 0420 0000000000000420 141 LA R8,LONGBFP Point to start of long BFP input values -0000000000000810 4190 0440 0000000000000440 142 LA R9,EXTBFP Point to start of extended BFP input values -0000000000000814 0DD0 143 BASR R13,0 Set top of loop - 144 * convert integers to three BFP formats -0000000000000816 E310 3000 0004 0000000000000000 145 CVTLOOP LG R1,0(0,R3) Get integer test value -000000000000081C B3A4 0001 146 CEGBR R0,R1 Cvt Int in GPR1 to short float in FPR0 -0000000000000820 7000 7000 0000000000000000 147 STE R0,0(0,R7) Store short BFP -0000000000000824 B3A5 0001 148 CDGBR R0,R1 Cvt Int in GPR1 to long float in FPR0 -0000000000000828 6000 8000 0000000000000000 149 STD R0,0(0,R8) Store long BFP -000000000000082C B3A6 0001 150 CXGBR R0,R1 Cvt Int in GPR1 to ext float in FPR0-FPR2 -0000000000000830 6000 9000 0000000000000000 151 STD R0,0(0,R9) Store extended BFP part 1 -0000000000000834 6020 9008 0000000000000008 152 STD R2,8(0,R9) Store extended BFP part 2 -0000000000000838 4130 3008 0000000000000008 153 LA R3,8(0,R3) point to next input values -000000000000083C 4170 7004 0000000000000004 154 LA R7,4(0,R7) Point to next short BFP converted values -0000000000000840 4180 8008 0000000000000008 155 LA R8,8(0,R8) Point to next long BFP converted values -0000000000000844 4190 9010 0000000000000010 156 LA R9,16(0,R9) Point to next extended BFP converted values - ASMA Ver. 0.2.0 23 Jun 2016 09:49:51 Page 4 - - LOC OBJECT CODE ADDR1 ADDR2 STMT - -0000000000000848 062D 157 BCTR R2,R13 Convert next input value. -000000000000084A 07FC 158 BR R12 Conversion done, return to mainline - 159 * - 160 * - 161 * Convert back to integers - 162 * -000000000000084C 163 CVTOUTS DS 0H -000000000000084C 4120 0002 0000000000000002 164 LA R2,2 Set count of subtraction operations -0000000000000850 4170 0500 0000000000000500 165 LA R7,SHORTRES Point to start of short BFP results -0000000000000854 4180 0510 0000000000000510 166 LA R8,LONGRES Point to start of long BFP results -0000000000000858 4190 0530 0000000000000530 167 LA R9,EXTRES Point to start of extended BFP results -000000000000085C 4130 0550 0000000000000550 168 LA R3,ISHBFP Point to start of short BFP Integer results -0000000000000860 4140 0570 0000000000000570 169 LA R4,ILNBFP Point to start of long BFP integer results -0000000000000864 4150 0590 0000000000000590 170 LA R5,IXTBFP Point to start of extended BFP integer results -0000000000000868 0DD0 171 BASR R13,0 Set top of loop - 172 * -000000000000086A B375 0000 173 INTLOOP LZDR R0 Zero FPR0 - 174 * Convert shorts back to integer -000000000000086E 7800 7000 0000000000000000 175 LE R0,0(0,R7) Get BFP short result first of pair -0000000000000872 B3A8 0000 176 CGEBR R0,R0 Convert to integer in r0 -0000000000000876 E300 3000 0024 0000000000000000 177 STG R0,0(0,R3) Store integer result -000000000000087C 7800 7004 0000000000000004 178 LE R0,4(0,R7) Get BFP short result second of pair - 179 * -0000000000000880 B3A8 0000 180 CGEBR R0,R0 Convert to integer in r0 -0000000000000884 E300 3008 0024 0000000000000008 181 STG R0,8(0,R3) Store integer result - 182 * -000000000000088A 6800 8000 0000000000000000 183 LD R0,0(0,R8) Get BFP long result first of pair -000000000000088E B3A9 0000 184 CGDBR R0,R0 Convert to integer in r0 -0000000000000892 E300 4000 0024 0000000000000000 185 STG R0,0(0,R4) Store integer result -0000000000000898 6800 8008 0000000000000008 186 LD R0,8(0,R8) Get BFP long result second of pair -000000000000089C B3A9 0000 187 CGDBR R0,R0 Convert to integer in r0 -00000000000008A0 E300 4008 0024 0000000000000008 188 STG R0,8(0,R4) Store integer result - 189 * -00000000000008A6 6800 9000 0000000000000000 190 LD R0,0(0,R9) Get BFP ext. 1st half of first of pair -00000000000008AA 6820 9008 0000000000000008 191 LD R2,8(0,R9) Get BFP ext. 2nd half of first of pair -00000000000008AE B3AA 0000 192 CGXBR R0,R0 Convert BFP Ext. to Integer-64 -00000000000008B2 E300 5000 0024 0000000000000000 193 STG R0,0(0,R5) Store integer result lower word - 194 * -00000000000008B8 4170 7008 0000000000000008 195 LA R7,8(0,R7) Point to next short BFP input pair -00000000000008BC 4130 3010 0000000000000010 196 LA R3,16(0,R3) Point to next short BFP integer pair -00000000000008C0 4180 8010 0000000000000010 197 LA R8,16(0,R8) Point to next long BFP input pair -00000000000008C4 4140 4010 0000000000000010 198 LA R4,16(0,R4) Point to next long BFP integer pair -00000000000008C8 4190 9010 0000000000000010 199 LA R9,16(0,R9) Point to next ext. BFP input -00000000000008CC 4150 5008 0000000000000008 200 LA R5,8(0,R5) Point to next ext. BFP integer -00000000000008D0 062D 201 BCTR R2,R13 Subtract next input pair -00000000000008D2 07FC 202 BR R12 Conversion done, return to mainline - ASMA Ver. 0.2.0 23 Jun 2016 09:49:51 Page 5 - - SYMBOL TYPE VALUE LENGTH DEFN REFERENCES - -BFPSUBS J 000000 2260 28 46 48 50 112 119 121 123 125 126 127 129 130 131 136 -CTLR0 F 0002C8 4 110 51 52 53 -CVTINPUT H 000800 2 137 54 -CVTLOOP I 000816 6 145 -CVTOUTS H 00084C 2 163 56 -EXTBFP U 000440 0 123 68 142 -EXTRES U 000530 0 127 65 167 -ILNBFP U 000570 0 130 169 -IMAGE 1 000000 2260 0 -INTLOOP I 00086A 4 173 -INTVALS D 000480 8 113 139 -ISHBFP U 000550 0 129 168 -IXTBFP U 000590 0 131 170 -LONGBFP U 000420 0 121 67 141 -LONGRES U 000510 0 126 64 166 -R0 U 000000 1 29 51 53 70 73 74 75 76 78 79 83 84 85 86 88 89 93 97 - 98 146 147 148 149 150 151 173 175 176 177 178 180 181 183 184 185 - 186 187 188 190 192 193 -R1 U 000001 1 30 71 77 78 87 88 95 97 145 146 148 150 -R10 U 00000A 1 39 -R11 U 00000B 1 40 -R12 U 00000C 1 41 54 55 56 104 158 202 -R13 U 00000D 1 42 143 157 171 201 -R14 U 00000E 1 43 -R15 U 00000F 1 44 -R2 U 000002 1 31 62 94 99 103 138 152 157 164 191 201 -R3 U 000003 1 32 63 75 79 81 96 139 145 153 168 177 181 196 -R4 U 000004 1 33 64 85 89 91 169 185 188 198 -R5 U 000005 1 34 65 98 99 101 170 193 200 -R6 U 000006 1 35 -R7 U 000007 1 36 66 73 74 76 77 80 140 147 154 165 175 178 195 -R8 U 000008 1 37 67 83 84 86 87 90 141 149 155 166 183 186 197 -R9 U 000009 1 38 68 93 94 95 96 100 142 151 152 156 167 190 191 199 -SHORTBFP U 000410 0 119 66 140 -SHORTRES U 000500 0 125 63 165 -STARTSUB I 000200 4 51 47 -SUBLOOP I 000238 4 70 103 -TESTSUB H 00021C 2 61 55 -WAITPSW X 0002B8 16 109 57 - ASMA Ver. 0.2.0 23 Jun 2016 09:49:51 Page 6 - -MACRO DEFN REFERENCES - -No defined macros - ASMA Ver. 0.2.0 23 Jun 2016 09:49:51 Page 7 - - DESC SYMBOL SIZE POS ADDR - -Entry: 0 - -Image IMAGE 2260 000-8D3 000-8D3 - Region 2260 000-8D3 000-8D3 - CSECT BFPSUBS 2260 000-8D3 000-8D3 - ASMA Ver. 0.2.0 23 Jun 2016 09:49:51 Page 8 - - STMT FILE NAME - -1 C:\Users\srorso\Documents\GitHub\hyperion\tests\ieee-subs.asm - - -** NO ERRORS FOUND ** - - \ No newline at end of file diff --git a/tests/ieee-subs.tst b/tests/ieee-subs.tst deleted file mode 100644 index 858dbf50d..000000000 --- a/tests/ieee-subs.tst +++ /dev/null @@ -1,75 +0,0 @@ -* -*Testcase ieee-subs.tst: IEEE Subtract, Convert From/To Fixed -*Message Testcase ieee-subs.tst: IEEE subtract, Convert From/To Fixed -*Message ..Includes SUBTRACT (5), CONVERT FROM/TO FIXED 32 (6), 11 instr total -* -* -* SUBTRACT tests - Binary Floating Point -* -sysclear -archmode esame -loadcore "$(testpath)/ieee-subs.core" -runtest .1 - -*Compare -r 410.10 # Inputs converted to BFP short 2 1 4 -2 -*Want "CEGBR tests 1-4" 40000000 3F800000 40800000 C0000000 - -*Compare -r 420.10 # Inputs converted to BFP long part 1 -*Want "CDGBR tests 1-2" 40000000 00000000 3FF00000 00000000 -*Compare -r 430.10 # Inputs converted to BFP long part 2 -*Want "CDGBR tests 3-4" 40100000 00000000 C0000000 00000000 - -*Compare -r 440.10 # Inputs converted to BFP ext part 1 -*Want "CXGBR tests 1" 40000000 00000000 00000000 00000000 -*Compare -r 450.10 # Inputs converted to BFP ext part 2 -*Want "CXGBR tests 2" 3FFF0000 00000000 00000000 00000000 -*Compare -r 460.10 # Inputs converted to BFP ext part 3 -*Want "CXGBR tests 3" 40010000 00000000 00000000 00000000 -*Compare -r 470.10 # Inputs converted to BFP ext part 4 -*Want "CXGBR tests 4" C0000000 00000000 00000000 00000000 - -*Compare -r 500.10 # BFP short differences RXE and RRE -*Want "SEB/SEBR test pairs 1-2" 3F800000 3F800000 40C00000 40C00000 - -*Compare -r 510.10 # BFP long differences RXE and RRE part 1 -*Want "SDB/SDBR test pair 1" 3FF00000 00000000 3FF00000 00000000 -*Compare -r 520.10 # BFP long differences RXE and RRE part 2 -*Want "SDB/SDBR test pair 2" 40180000 00000000 40180000 00000000 - -*Compare -r 530.10 # BFP extended differences RRE part 1 -*Want "SXBR test 1" 3FFF0000 00000000 00000000 00000000 -*Compare -r 540.10 # BFP extended differences RRE part 2 -*Want "SXBR test 1" 40018000 00000000 00000000 00000000 - -*Compare -r 550.10 # Short BFP to Integer results part 1 -*Want "CGEB/CGEBR test pair 1" 00000000 00000001 00000000 00000001 -*Compare -r 560.10 # Short BFP to Integer results part 2 -*Want "CGEB/CGEBR test pair 2" 00000000 00000006 00000000 00000006 - -*Compare -r 570.10 # Convert long BFP to Integer results part 1 -*Want "CGDB/CGDBR test pair 1" 00000000 00000001 00000000 00000001 -*Compare -r 580.10 # Convert long BFP to Integer results part 2 -*Want "CGDB/CGDBR test pair 2" 00000000 00000006 00000000 00000006 - -*Compare -r 590.10 # Convert extended BFP to Integer results -*Want "CGXBR tests 1-2" 00000000 00000001 00000000 00000006 - -*Done - diff --git a/tests/pfpo.asm b/tests/pfpo.asm new file mode 100644 index 000000000..e45c51390 --- /dev/null +++ b/tests/pfpo.asm @@ -0,0 +1,54 @@ +* PFPO TITLE 'Perform floating point operation. ESA and z mode.' + +* This file was put into the public domain 2016-05-05 +* by John P. Hartmann. You can use it for anything you like, +* as long as this notice remains. + +* Note that this test runs in problem state. As a result STFL is +* not a good idea; nor is lpsw for that matter. + +* So we terminate by SVC, and we determine architecture mode +* by seeing where the restart old psw was stored. + +pfpo start 0 + using pfpo,15 + + dc a(x'00090000',go) ESA restart new PSW at 0 +ropsw390 ds 0xl8 ESA/390 Restart old psw + ds x'ffffffffffffffff' If no longer ones, then ESA/390 mode + + org pfpo+x'60' ESA SVC new PSW + dc x'000a0000',a(x'0') normal end of job + + org pfpo+x'68' ESA program new + dc x'000a0000',a(x'deaddead') + + org pfpo+x'120' +ropswz ds 0xl16 z/Arch Restart old psw + dc 16x'ff' If no longer ones, then z/Arch mode + + org pfpo+x'1a0' z restart new PSW + dc x'0001000180000000',ad(go) + + org pfpo+x'1c0' z SVC Program new + dc x'0002000180000000',ad(0) + + org pfpo+x'1d0' z Program new + dc x'0002000180000000',ad(x'deaddead') + + using pfpo,15 + org pfpo+x'200' +go ds 0h + cli ropsw390,x'ff' Running in ESA/390 mode? + bne eoj ..yes, no PFPO support, skip instruction execution + sr 3,3 clear r3 for later condition code store + l 0,=a(x'80000000') Test for invalid function + pfpo + ipm 3 collect condition code from PSW + st 3,condcode +eoj ds 0h + svc 0 load hardwait psw. + ltorg + org pfpo+x'300' +condcode dc f'0' + end diff --git a/tests/pfpo.core b/tests/pfpo.core new file mode 100644 index 000000000..9dcef463b Binary files /dev/null and b/tests/pfpo.core differ diff --git a/tests/pfpo.list b/tests/pfpo.list new file mode 100644 index 000000000..56e3b26c7 --- /dev/null +++ b/tests/pfpo.list @@ -0,0 +1,99 @@ +ASMA Ver. 0.2.0 28 Oct 2016 21:32:58 Page 1 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + + 1 * PFPO TITLE 'Perform floating point operation. ESA and z mode.' + 2 + 3 * This file was put into the public domain 2016-05-05 + 4 * by John P. Hartmann. You can use it for anything you like, + 5 * as long as this notice remains. + 6 + 7 * Note that this test runs in problem state. As a result STFL is + 8 * not a good idea; nor is lpsw for that matter. + 9 + 10 * So we terminate by SVC, and we determine architecture mode + 11 * by seeing where the restart old psw was stored. + 12 + 0000000000000000 0000000000000303 13 pfpo start 0 +0000000000000000 0000000000000000 14 using pfpo,15 + 15 +0000000000000000 00090000 00000200 16 dc a(x'00090000',go) ESA restart new PSW at 0 +0000000000000008 17 ropsw390 ds 0xl8 ESA/390 Restart old psw +0000000000000008 00000000 00000000 18 ds x'ffffffffffffffff' If no longer ones, then ESA/390 mode + 19 +0000000000000010 0000000000000010 0000000000000060 20 org pfpo+x'60' ESA SVC new PSW +0000000000000060 000A0000 00000000 21 dc x'000a0000',a(x'0') normal end of job + 22 +0000000000000068 0000000000000068 0000000000000068 23 org pfpo+x'68' ESA program new +0000000000000068 000A0000 DEADDEAD 24 dc x'000a0000',a(x'deaddead') + 25 +0000000000000070 0000000000000070 0000000000000120 26 org pfpo+x'120' +0000000000000120 27 ropswz ds 0xl16 z/Arch Restart old psw +0000000000000120 FFFFFFFF FFFFFFFF 28 dc 16x'ff' If no longer ones, then z/Arch mode + 29 +0000000000000130 0000000000000130 00000000000001A0 30 org pfpo+x'1a0' z restart new PSW +00000000000001A0 00010001 80000000 31 dc x'0001000180000000',ad(go) + 32 +00000000000001B0 00000000000001B0 00000000000001C0 33 org pfpo+x'1c0' z SVC Program new +00000000000001C0 00020001 80000000 34 dc x'0002000180000000',ad(0) + 35 +00000000000001D0 00000000000001D0 00000000000001D0 36 org pfpo+x'1d0' z Program new +00000000000001D0 00020001 80000000 37 dc x'0002000180000000',ad(x'deaddead') + 38 +00000000000001E0 0000000000000000 39 using pfpo,15 +00000000000001E0 00000000000001E0 0000000000000200 40 org pfpo+x'200' +0000000000000200 41 go ds 0h +0000000000000200 95FF F008 0000000000000008 42 cli ropsw390,x'ff' Running in ESA/390 mode? +0000000000000204 4770 F218 0000000000000218 43 bne eoj ..yes, no PFPO support, skip instruction execution +0000000000000208 1B33 44 sr 3,3 clear r3 for later condition code store +000000000000020A 5800 F21C 000000000000021C 45 l 0,=a(x'80000000') Test for invalid function +000000000000020E 010A 46 pfpo +0000000000000210 B222 0030 47 ipm 3 collect condition code from PSW +0000000000000214 5030 F300 0000000000000300 48 st 3,condcode +0000000000000218 49 eoj ds 0h +0000000000000218 0A00 50 svc 0 load hardwait psw. +000000000000021C 51 ltorg +000000000000021C 80000000 52 =a(x'80000000') + ASMA Ver. 0.2.0 28 Oct 2016 21:32:58 Page 2 + + LOC OBJECT CODE ADDR1 ADDR2 STMT + +0000000000000220 0000000000000220 0000000000000300 53 org pfpo+x'300' +0000000000000300 00000000 54 condcode dc f'0' +0000000000000304 55 end + ASMA Ver. 0.2.0 28 Oct 2016 21:32:58 Page 3 + + SYMBOL TYPE VALUE LENGTH DEFN REFERENCES + +CONDCODE F 000300 4 54 48 +EOJ H 000218 2 49 43 +GO H 000200 2 41 16 31 +IMAGE 1 000000 772 0 +PFPO J 000000 772 13 20 23 26 30 33 36 40 53 14 39 +ROPSW390 X 000008 8 17 42 +ROPSWZ X 000120 16 27 +=a(x'80000000') A 00021C 4 52 45 + ASMA Ver. 0.2.0 28 Oct 2016 21:32:58 Page 4 + +MACRO DEFN REFERENCES + +No defined macros + ASMA Ver. 0.2.0 28 Oct 2016 21:32:58 Page 5 + + DESC SYMBOL SIZE POS ADDR + +Entry: 0 + +Image IMAGE 772 000-303 000-303 + Region 772 000-303 000-303 + CSECT PFPO 772 000-303 000-303 + ASMA Ver. 0.2.0 28 Oct 2016 21:32:58 Page 6 + + STMT FILE NAME + +1 C:\Users\srorso\Documents\GitHub\hyperion\tests\pfpo.asm + + +** NO ERRORS FOUND ** + + \ No newline at end of file diff --git a/tests/pfpo.tst b/tests/pfpo.tst new file mode 100644 index 000000000..fc1b19c68 --- /dev/null +++ b/tests/pfpo.tst @@ -0,0 +1,32 @@ + +# This file was put into the public domain 2016-10-28 +# by John P. Hartmann. You can use it for anything you like, +# as long as this notice remains. + +*Testcase pfpo-esa +sysclear +archlvl esa/390 + +# when run in ESA/390 mode, the test skips the PFPO instruction + +loadcore "$(testpath)/pfpo.core" + +runtest .1 + +*Done + +*Testcase pfpo-z +sysclear +archlvl esame + +# when run in z/Arch mode, PFPO is attempted. +# An operation exception is expected. + +loadcore "$(testpath)/pfpo.core" +*Program 0001 +runtest .1 +gpr + +*Done + + diff --git a/util/WSMInstallScript.nsi b/util/WSMInstallScript.nsi new file mode 100644 index 000000000..6bf047559 --- /dev/null +++ b/util/WSMInstallScript.nsi @@ -0,0 +1,183 @@ +; Copyright 2016 by Stephen Orso. All rights reserved. + +; Redistribution and use of this script, with or without modification, +; are permitted provided that the following conditions are met: +; +; 1. Redistributions of this script must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; +; 2. The name of the author may not be used to endorse or promote +; products derived from this script, including packages created +; by this script, without specific prior written permission. +; +; DISCLAMER: THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +; PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +; HOLDER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +; PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +; OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + +; Opportunities for improvement: +; Sections currently glob the target installation from the contents +; of the source binaries. Specifying files individually would +; cause this script compile to fail, alerting the installer builder +; that the source binaries are incorrect or incomplete. +; Create the environment variables upon request through registry +; changes that are supported by NSIS. Add this capability through +; a new section group/section. +; Create uninstall, which might remove the files and the environment +; variables. +; Register the installation in Windows Control Panel Programs and +; features, along with the uninstall. + +; NSIS installer global options + +Name "Windows Support Modules For Hercules" +Caption "Install WSF for Hercules" +OutFile WinSup4H.exe +Icon hercmisc.ico +ShowInstDetails show +BrandingText " " +InstallDir $EXEDIR + +; change the define below to point to the directory containing your +; updated build of the Windows Support Modules before compiling this +; script to create the installer. + +!define winbuild_source "c:\common\github\winbuild" + + +; Initialization Script: +; Be certain the person doing the installation understands that these +; modules are required only to build Hercules from source on Windows. + + Function .onInit + MessageBox MB_YESNO|MB_ICONQUESTION \ + "Installation of the Windows Support Files for Hercules is \ + required only if you are building Hercules from source on \ + Windows. It is not required for the Hercules installable \ + distribution.$\r$\n$\r$\n\ + Do you wish to continue with the installation?" \ + IDYES NoAbort + MessageBox MB_OK|MB_ICONSTOP \ + "The Windows Support Files for Hercules will not be installed." + Abort ; causes installer to quit. + NoAbort: + FunctionEnd + + +; Completion Script: +; Remind the person installing to set the environment variables as +; needed if the installation was to other than the recommended +; directory. Helpfully create a batch file with the needed +; commands. + + Function .onInstSuccess + FileOpen $0 $INSTDIR\winbuild\WSMSetEnv.cmd w + StrCpy $1 'echo off$\r$\n$\r$\n' + FileWrite $0 $1 + StrCpy $1 ':: WSMSetEnv.cmd: permanently set Hercules build variables to point to$\r$\n' + FileWrite $0 $1 + StrCpy $1 ':: installed location of Windows Support Modules for Hercules builds$\r$\n$\r$\n' + FileWrite $0 $1 + StrCpy $1 'echo Environment variables eeee about to be permanently set...$\r$\n' + FileWrite $0 $1 + StrCpy $1 'echo Ctrl-c to abort, space to continue$\r$\npause$\r$\n$\r$\n' + FileWrite $0 $1 + StrCpy $1 'setx BZIP2_DIR $INSTDIR\winbuild\bzip2$\r$\n' + FileWrite $0 $1 + StrCpy $1 'setx PCRE_DIR $INSTDIR\winbuild\pcre$\r$\n' + FileWrite $0 $1 + StrCpy $1 'setx ZLIB_DIR $INSTDIR\winbuild\zlib$\r$\n' + FileWrite $0 $1 + FileClose $0 + MessageBox MB_OK|MB_ICONEXCLAMATION \ + "If you installed the modules in other than the recommended \ + location, be certain to add or update the following Windows \ + Environment variables with the install directory you chose.$\r$\n$\r$\n\ + $\t BZIP2_DIR=$INSTDIR\winbuild\bzip2$\r$\n\ + $\t PCRE_DIR=$INSTDIR\winbuild\pcre$\r$\n\ + $\t ZLIB_DIR=$INSTDIR\winbuild\zlib$\r$\n$\r$\n\ + A command file WSMSetEnv.cmd has been created to permanently \ + set these environment variables in $INSTDIR\winbuild." + + FunctionEnd + + +; Somewhat jocular license acceptance page + +Page license + LicenseText "Use of this product requires donation of your first-born child to the Hyperion Project." + LicenseData WSMInstallScriptLicense.rtf + LicenseForceSelection radiobuttons "I accept" "I decline" + + +; Components page, generated by NSIS from Section Group and Sections below + +Page components + ComponentText "Check the modules you wish to install and uncheck the \ + modules you do not require. Click Next to Continue." \ + "" \ + "Installation of all modules is recommended$\r$\n$\r$\n\ + Pcre is used for the Hercules Automated Operator.$\r$\n$\r$\n\ + Bzip2 and zlip are used for disk and tape volume compression." + + +; Solicit directory to which modules are to be installed. + +Page directory + DirText "Specify the directory for the Windows Support Modules.$\r$\n$\r$\n\ + You should install the Windows Support Modules at the same \ + level as the Hercules build directory." \ + "Windows Support Files install directory" + + +; Install stuff + +Page instfiles + +; No uninstallation stuff here. + +UninstPage uninstConfirm + +UninstPage instfiles + +; All modules are in one section group. + +SectionGroup /e "Windows Support Modules" + + +Section "bzip2" ; installation section for bzip2 module. + +; AddSize 1220 + SetOutPath $INSTDIR\winbuild\bzip2 + file /r ${winbuild_source}\bzip2\*.* + +SectionEnd + + +Section "pcre" ; installation section for pcre module. + +; AddSize 332 + SetOutPath $INSTDIR\winbuild\pcre + file /r ${winbuild_source}\pcre\*.* + +SectionEnd + + +Section "zlib" ; installation section for zlib module. + +; AddSize 1420 + SetOutPath $INSTDIR\winbuild\zlib + file /r ${winbuild_source}\zlib\*.* + +SectionEnd + + +SectionGroupEnd \ No newline at end of file diff --git a/util/WSMInstallScriptLicense.rtf b/util/WSMInstallScriptLicense.rtf new file mode 100644 index 000000000..353ecf376 Binary files /dev/null and b/util/WSMInstallScriptLicense.rtf differ