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cpu.h
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cpu.h
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/*
* Copyright (c) 2002-2003 NONAKA Kimihiro
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
Intel Architecture 32-bit Processor Interpreter Engine for Pentium
Copyright by Yui/Studio Milmake 1999-2000
Copyright by Norio HATTORI 2000,2001
Copyright by NONAKA Kimihiro 2002-2004
*/
#ifndef IA32_CPU_CPU_H__
#define IA32_CPU_CPU_H__
#if defined(_MSC_VER) && (_MSC_VER >= 1400)
#pragma warning( disable : 4065 )
#pragma warning( disable : 4996 )
#endif
//#include "../../common.h"
#ifdef __BIG_ENDIAN__
#define BYTESEX_BIG
#else
#define BYTESEX_LITTLE
#endif
#ifndef REG8
#define REG8 UINT8
#endif
#ifndef REG16
#define REG16 UINT16
#endif
#ifndef LOADINTELDWORD
#define LOADINTELDWORD(a) (((UINT32)(((UINT8*)(a))[0]) ) | \
((UINT32)(((UINT8*)(a))[1]) << 8) | \
((UINT32)(((UINT8*)(a))[2]) << 16) | \
((UINT32)(((UINT8*)(a))[3]) << 24))
#endif
#ifndef LOADINTELWORD
#define LOADINTELWORD(a) (((UINT16)((UINT8*)(a))[0]) | ((UINT16)(((UINT8*)(a))[1]) << 8))
#endif
#ifndef STOREINTELDWORD
#define STOREINTELDWORD(a, b) *(((UINT8*)(a))+0) = (UINT8)((b) ); \
*(((UINT8*)(a))+1) = (UINT8)((b)>> 8); \
*(((UINT8*)(a))+2) = (UINT8)((b)>>16); \
*(((UINT8*)(a))+3) = (UINT8)((b)>>24)
#endif
#ifndef STOREINTELWORD
#define STOREINTELWORD(a, b) *(((UINT8*)(a))+0) = (UINT8)((b) ); \
*(((UINT8*)(a))+1) = (UINT8)((b)>>8)
#endif
#ifndef LOW16
#define LOW16(a) ((UINT16)(a))
#endif
#ifndef INLINE
#ifdef __cplusplus
#define INLINE inline
#else
#define INLINE __inline
#endif
#endif
#ifndef __ASSERT
#define __ASSERT assert
#endif
#define _MALLOC(a, b) malloc(a)
#define _MFREE(a) free(a)
#define msgbox(a, b)
#ifndef TRACEOUT
#define TRACEOUT(a)
#endif
#define VERBOSE(a)
#define PARTSCALL __fastcall
#define CPUCALL __fastcall
#define MEMCALL __fastcall
#define DMACCALL __fastcall
#define IOOUTCALL __fastcall
#define IOINPCALL __fastcall
#define SUPPORT_FPU_DOSBOX
#define SUPPORT_FPU_DOSBOX2
#define SUPPORT_FPU_SOFTFLOAT
#define USE_FPU
#define USE_MMX
#define USE_3DNOW
#define USE_SSE
#define USE_SSE2
#define USE_SSE3
#define USE_TSC
#define USE_FASTPAGING
#define USE_VME
#define IA32_REBOOT_ON_PANIC
#define CPU_USE_JIT
enum {
FPU_TYPE_SOFTFLOAT = 0, /* Berkeley SoftFloat */
FPU_TYPE_DOSBOX = 1, /* DOSBox FPU */
FPU_TYPE_DOSBOX2 = 2 /* DOSBox FPU+INT64 */
};
#ifndef SINT64
#define SINT64 int64
#endif
#ifndef SINT32
#define SINT32 int32
#endif
#ifndef SINT16
#define SINT16 int16
#endif
#ifndef int64
#define int64 INT64
#endif
#ifndef int32
#define int32 INT32
#endif
#ifndef int16
#define int16 INT16
#endif
//#include "interface.h"
#if defined(SUPPORT_FPU_SOFTFLOAT)
#include "softfloat.h"
#endif
//#ifdef __cplusplus
//extern "C" {
//#endif
typedef union {
#if defined(BYTESEX_LITTLE)
struct {
UINT8 l;
UINT8 h;
UINT8 _hl;
UINT8 _hh;
} b;
struct {
UINT16 w;
UINT16 _hw;
} w;
#elif defined(BYTESEX_BIG)
struct {
UINT8 _hh;
UINT8 _hl;
UINT8 h;
UINT8 l;
} b;
struct {
UINT16 _hw;
UINT16 w;
} w;
#endif
UINT32 d;
} REG32;
typedef union {
UINT8 b[10];
UINT16 w[5];
struct {
UINT32 l[2];
UINT16 h;
} d;
} REG80;
//#ifdef __cplusplus
//}
//#endif
#include "segments.h"
//#ifdef __cplusplus
//extern "C" {
//#endif
enum {
CPU_EAX_INDEX = 0,
CPU_ECX_INDEX = 1,
CPU_EDX_INDEX = 2,
CPU_EBX_INDEX = 3,
CPU_ESP_INDEX = 4,
CPU_EBP_INDEX = 5,
CPU_ESI_INDEX = 6,
CPU_EDI_INDEX = 7,
CPU_REG_NUM
};
enum {
CPU_ES_INDEX = 0,
CPU_CS_INDEX = 1,
CPU_SS_INDEX = 2,
CPU_DS_INDEX = 3,
CPU_SEGREG286_NUM = 4,
CPU_FS_INDEX = 4,
CPU_GS_INDEX = 5,
CPU_SEGREG_NUM
};
enum {
CPU_TEST_REG_NUM = 8
};
enum {
CPU_DEBUG_REG_NUM = 8,
CPU_DEBUG_REG_INDEX_NUM = 4
};
enum {
MAX_PREFIX = 8
};
typedef struct {
REG32 reg[CPU_REG_NUM];
UINT16 sreg[CPU_SEGREG_NUM];
REG32 eflags;
REG32 eip;
REG32 prev_eip;
REG32 prev_esp;
UINT32 tr[CPU_TEST_REG_NUM];
UINT32 dr[CPU_DEBUG_REG_NUM];
} CPU_REGS;
typedef struct {
UINT16 gdtr_limit;
UINT16 pad0;
UINT32 gdtr_base;
UINT16 idtr_limit;
UINT16 pad1;
UINT32 idtr_base;
UINT16 ldtr;
UINT16 tr;
UINT32 cr0;
UINT32 cr1;
UINT32 cr2;
UINT32 cr3;
UINT32 cr4;
UINT32 mxcsr;
} CPU_SYSREGS;
typedef struct {
descriptor_t sreg[CPU_SEGREG_NUM];
descriptor_t ldtr;
descriptor_t tr;
UINT32 adrsmask;
UINT32 ovflag;
UINT8 ss_32;
UINT8 resetreq;
UINT8 trap;
UINT8 page_wp;
UINT8 protected_mode;
UINT8 paging;
UINT8 vm86;
UINT8 user_mode;
UINT8 hlt;
UINT8 bp; /* break point bitmap */
UINT8 bp_ev; /* break point event */
UINT8 backout_sp; /* backout ESP, when exception */
UINT32 pde_base;
UINT32 ioaddr; /* I/O bitmap linear address */
UINT16 iolimit; /* I/O bitmap count */
UINT8 nerror; /* double fault/ triple fault */
UINT8 prev_exception;
} CPU_STAT;
typedef struct {
UINT8 op_32;
UINT8 as_32;
UINT8 rep_used;
UINT8 seg_used;
UINT32 seg_base;
} CPU_INST;
/* FPU */
enum {
FPU_REG_NUM = 8,
XMM_REG_NUM = 8
};
typedef struct {
UINT16 seg;
UINT16 pad;
UINT32 offset;
} FPU_PTR;
typedef struct {
UINT16 control; // 䃌 W X ^ [
UINT16 status; // X e [ ^ X W X ^ [
UINT16 op; // I y R [ h W X ^ [
UINT16 tag; // ^ O [ h W X ^ [
FPU_PTR inst; // X g ߃| C ^ W X ^ [
FPU_PTR data; // X g f [ ^ | C ^ W X ^ [
} FPU_REGS_S;
#if 0
typedef struct {
UINT8 valid;
UINT8 sign;
UINT8 zero;
UINT8 inf;
UINT8 nan;
UINT8 denorm;
SINT16 exp;
UINT64 num;
} FP_REG;
typedef struct {
UINT8 top;
UINT8 pc;
UINT8 rc;
UINT8 dmy[1];
FP_REG reg[FPU_REG_NUM]; // R0 to R7
} FPU_STAT;
#else
typedef enum {
TAG_Valid = 0,
TAG_Zero = 1,
TAG_Weird = 2,
TAG_Empty = 3
} FP_TAG;
typedef enum {
ROUND_Nearest = 0,
ROUND_Down = 1,
ROUND_Up = 2,
ROUND_Chop = 3
} FP_RND;
typedef union {
floatx80 d;
double d64;
struct {
UINT32 lower;
SINT32 upper;
SINT16 ext;
} l;
struct {
UINT32 lower;
UINT32 upper;
SINT16 ext;
} ul;
SINT64 ll;
UINT8 b[10];
} FP_REG;
typedef union {
struct {
UINT32 m1;
UINT32 m2;
UINT16 m3;
} ul32;
struct {
UINT32 m1;
UINT32 m2;
SINT16 m3;
} l32;
struct {
UINT64 m12;
UINT16 m3;
} ul64;
struct {
UINT64 m12;
SINT16 m3;
} l64;
} FP_INT_REG;
typedef union {
float f[4];
double d[2];
UINT8 ul8[16];
UINT16 ul16[8];
UINT32 ul32[4];
UINT64 ul64[2];
} XMM_REG;
typedef struct {
UINT8 top;
UINT8 pc;
UINT8 rc;
UINT8 dmy[1];
FP_REG reg[FPU_REG_NUM+1]; // R0 to R7 +
FP_TAG tag[FPU_REG_NUM+1]; // R0 to R7 +
FP_RND round;
#ifdef SUPPORT_FPU_DOSBOX2 // XXX: Ԃ m ɂ 邽 ߗp
FP_INT_REG int_reg[FPU_REG_NUM+1];
UINT8 int_regvalid[FPU_REG_NUM+1];
#endif
#ifdef USE_SSE
XMM_REG xmm_reg[XMM_REG_NUM+1]; // xmm0 to xmm7
#endif
#ifdef USE_MMX
UINT8 mmxenable;
#endif
} FPU_STAT_S;
#endif
typedef struct {
CPU_REGS cpu_regs;
CPU_SYSREGS cpu_sysregs;
CPU_STAT cpu_stat;
CPU_INST cpu_inst;
CPU_INST cpu_inst_default;
#if defined(USE_FPU)
FPU_REGS_S fpu_regs;
FPU_STAT_S fpu_stat;
#endif
/* protected by cpu shut */
UINT8 cpu_type;
UINT8 itfbank;
UINT16 ram_d0;
SINT32 remainclock;
SINT32 baseclock;
UINT32 clock;
#if defined(USE_TSC)
UINT64 cpu_tsc;
#endif
} I386STAT;
typedef struct {
UINT8 *ext;
UINT32 extsize;
UINT8 *extbase; /* = ext - 0x100000 */
UINT32 extlimit16mb; /* = extsize + 0x100000 (MAX:16MB) */
UINT32 extlimit4gb; /* = extsize + 0x100000 */
UINT32 inport;
UINT8 *ems[4];
} I386EXT;
typedef struct {
I386STAT s; /* STATsave'ed */
I386EXT e;
} I386CORE;
#define I386CPUID_VERSION 1
typedef struct {
UINT32 version; // CPUID o [ W i X e [ g Z [ u ݊ ێ 邽 ߗp jI386CPUID_VERSION ŐV
char cpu_vendor[16]; // x _ [ i12byte j
UINT32 cpu_family; // t @ ~
UINT32 cpu_model; // f
UINT32 cpu_stepping; // X e b s O
UINT32 cpu_feature; // @ \ t O
UINT32 cpu_feature_ex; // g @ \ t O
char cpu_brandstring[64]; // u h i48byte j
UINT32 cpu_brandid; // u hID
UINT32 cpu_feature_ecx; // ECX @ \ t O
UINT32 cpu_eflags_mask; // EFLAGS } X N(1 ̂Ƃ 낪 } X N )
UINT8 allow_movCS; // mov cs,xx
UINT8 reserved8[3]; // ̊g ̂ ߂ɂƂ肠
UINT32 reserved[30]; // ̊g ̂ ߂ɂƂ肠 32bit*31 p ӂ Ă
UINT8 fpu_type; // FPU
} I386CPUID;
#define I386MSR_VERSION 1
typedef struct {
UINT64 ia32_sysenter_cs; // SYSENTER CS W X ^
UINT64 ia32_sysenter_esp; // SYSENTER ESP W X ^
UINT64 ia32_sysenter_eip; // SYSENTER EIP W X ^
} I386MSR_REG;
typedef struct {
UINT32 version; // MSR o [ W i X e [ g Z [ u ݊ ێ 邽 ߗp jI386MSR_VERSION ŐV
union{
UINT64 regs[32]; // ̊g ̂ ߂ɂƂ肠 64bit*32 p ӂ Ă
I386MSR_REG reg;
};
} I386MSR;
extern I386CORE i386core;
extern I386CPUID i386cpuid;
extern I386MSR i386msr;
#define CPU_STATSAVE i386core.s
#define CPU_ADRSMASK i386core.s.cpu_stat.adrsmask
#define CPU_RESETREQ i386core.s.cpu_stat.resetreq
#define CPU_REMCLOCK i386core.s.remainclock
#define CPU_BASECLOCK i386core.s.baseclock
#define CPU_CLOCK i386core.s.clock
#define CPU_ITFBANK i386core.s.itfbank
#define CPU_RAM_D000 i386core.s.ram_d0
#define CPU_TYPE i386core.s.cpu_type
#define CPUTYPE_V30 0x01
#define CPU_EXTMEM i386core.e.ext
#define CPU_EXTMEMSIZE i386core.e.extsize
#define CPU_EXTMEMBASE i386core.e.extbase
#define CPU_EXTLIMIT16 i386core.e.extlimit16mb
#define CPU_EXTLIMIT i386core.e.extlimit4gb
#define CPU_INPADRS i386core.e.inport
#define CPU_EMSPTR i386core.e.ems
#ifndef __cplusplus
extern sigjmp_buf exec_1step_jmpbuf;
#endif
//#define CPU_REALCLOCK 49920000
#define CPU_REALCLOCK 50000000
/*
* CPUID
*/
/*** vendor ***/
#define CPU_VENDOR_INTEL "GenuineIntel"
#define CPU_VENDOR_AMD "AuthenticAMD"
#define CPU_VENDOR_AMD2 "AMDisbetter!"
#define CPU_VENDOR_CYRIX "CyrixInstead"
#define CPU_VENDOR_NEXGEN "NexGenDriven"
#define CPU_VENDOR_CENTAUR "CentaurHauls"
#define CPU_VENDOR_TRANSMETA "GenuineTMx86"
#define CPU_VENDOR_TRANSMETA2 "TransmetaCPU"
#define CPU_VENDOR_NSC "Geode by NSC"
#define CPU_VENDOR_RISE "RiseRiseRise"
#define CPU_VENDOR_UMC "UMC UMC UMC "
#define CPU_VENDOR_SIS "SiS SiS SiS "
#define CPU_VENDOR_VIA "VIA VIA VIA "
#define CPU_VENDOR_NEKOPRO "Neko Project"
// f t H g ݒ
#define CPU_VENDOR CPU_VENDOR_INTEL
/*** version ***/
#define CPU_PENTIUM_4_FAMILY 15
#define CPU_PENTIUM_4_MODEL 2 /* Pentium 4 */
#define CPU_PENTIUM_4_STEPPING 4
#define CPU_PENTIUM_M_FAMILY 6
#define CPU_PENTIUM_M_MODEL 9 /* Pentium M */
#define CPU_PENTIUM_M_STEPPING 5
#define CPU_PENTIUM_III_FAMILY 6
#define CPU_PENTIUM_III_MODEL 7 /* Pentium III */
#define CPU_PENTIUM_III_STEPPING 2
#define CPU_PENTIUM_II_FAMILY 6
#define CPU_PENTIUM_II_MODEL 3 /* Pentium II */
#define CPU_PENTIUM_II_STEPPING 3
#define CPU_PENTIUM_PRO_FAMILY 6
#define CPU_PENTIUM_PRO_MODEL 1 /* Pentium Pro */
#define CPU_PENTIUM_PRO_STEPPING 1
#define CPU_MMX_PENTIUM_FAMILY 5
#define CPU_MMX_PENTIUM_MODEL 4 /* MMX Pentium */
#define CPU_MMX_PENTIUM_STEPPING 4
#define CPU_PENTIUM_FAMILY 5
#define CPU_PENTIUM_MODEL 2 /* Pentium */
#define CPU_PENTIUM_STEPPING 5
#define CPU_I486DX_FAMILY 4
#define CPU_I486DX_MODEL 1 /* 486DX */
#define CPU_I486DX_STEPPING 3
#define CPU_I486SX_FAMILY 4
#define CPU_I486SX_MODEL 2 /* 486SX */
#define CPU_I486SX_STEPPING 3
#define CPU_80386_FAMILY 3
#define CPU_80386_MODEL 0 /* 80386 */
#define CPU_80386_STEPPING 8
#define CPU_80286_FAMILY 2
#define CPU_80286_MODEL 1 /* 80286 */
#define CPU_80286_STEPPING 1
#define CPU_AMD_K7_ATHLON_XP_FAMILY 6
#define CPU_AMD_K7_ATHLON_XP_MODEL 6 /* AMD K7 Athlon XP */
#define CPU_AMD_K7_ATHLON_XP_STEPPING 2
#define CPU_AMD_K7_ATHLON_FAMILY 6
#define CPU_AMD_K7_ATHLON_MODEL 1 /* AMD K7 Athlon */
#define CPU_AMD_K7_ATHLON_STEPPING 2
#define CPU_AMD_K6_III_FAMILY 5
#define CPU_AMD_K6_III_MODEL 9 /* AMD K6-III */
#define CPU_AMD_K6_III_STEPPING 1
#define CPU_AMD_K6_2_FAMILY 5
#define CPU_AMD_K6_2_MODEL 8 /* AMD K6-2 */
#define CPU_AMD_K6_2_STEPPING 12
/*** feature ***/
#define CPU_FEATURE_FPU (1 << 0)
#define CPU_FEATURE_VME (1 << 1)
#define CPU_FEATURE_DE (1 << 2)
#define CPU_FEATURE_PSE (1 << 3)
#define CPU_FEATURE_TSC (1 << 4)
#define CPU_FEATURE_MSR (1 << 5)
#define CPU_FEATURE_PAE (1 << 6)
#define CPU_FEATURE_MCE (1 << 7)
#define CPU_FEATURE_CX8 (1 << 8)
#define CPU_FEATURE_APIC (1 << 9)
/* (1 << 10) */
#define CPU_FEATURE_SEP (1 << 11)
#define CPU_FEATURE_MTRR (1 << 12)
#define CPU_FEATURE_PGE (1 << 13)
#define CPU_FEATURE_MCA (1 << 14)
#define CPU_FEATURE_CMOV (1 << 15)
#define CPU_FEATURE_FGPAT (1 << 16)
#define CPU_FEATURE_PSE36 (1 << 17)
#define CPU_FEATURE_PN (1 << 18)
#define CPU_FEATURE_CLFSH (1 << 19)
/* (1 << 20) */
#define CPU_FEATURE_DS (1 << 21)
#define CPU_FEATURE_ACPI (1 << 22)
#define CPU_FEATURE_MMX (1 << 23)
#define CPU_FEATURE_FXSR (1 << 24)
#define CPU_FEATURE_SSE (1 << 25)
#define CPU_FEATURE_SSE2 (1 << 26)
#define CPU_FEATURE_SS (1 << 27)
#define CPU_FEATURE_HTT (1 << 28)
#define CPU_FEATURE_TM (1 << 29)
/* (1 << 30) */
#define CPU_FEATURE_PBE (1 << 31)
//#define CPU_FEATURE_XMM CPU_FEATURE_SSE
#if defined(USE_FPU)
#define CPU_FEATURE_FPU_FLAG CPU_FEATURE_FPU
#else
#define CPU_FEATURE_FPU_FLAG 0
#endif
#if defined(USE_TSC)
#define CPU_FEATURE_TSC_FLAG CPU_FEATURE_TSC
#else
#define CPU_FEATURE_TSC_FLAG 0
#endif
#if defined(USE_VME)
#define CPU_FEATURE_VME_FLAG CPU_FEATURE_VME
#else
#define CPU_FEATURE_VME_FLAG 0
#endif
#if defined(USE_MMX)&&defined(USE_FPU)
#define CPU_FEATURE_MMX_FLAG CPU_FEATURE_MMX|CPU_FEATURE_FXSR
#else
#define CPU_FEATURE_MMX_FLAG 0
#endif
#if defined(USE_MMX)&&defined(USE_FPU)&&defined(USE_SSE)
#define CPU_FEATURE_SSE_FLAG CPU_FEATURE_SSE|CPU_FEATURE_CLFSH
#else
#define CPU_FEATURE_SSE_FLAG 0
#endif
#if defined(USE_MMX)&&defined(USE_FPU)&&defined(USE_SSE)&&defined(USE_SSE2)
#define CPU_FEATURE_SSE2_FLAG CPU_FEATURE_SSE2
#else
#define CPU_FEATURE_SSE2_FLAG 0
#endif
/* g p ł @ \ S */
#define CPU_FEATURES_ALL (CPU_FEATURE_FPU_FLAG|CPU_FEATURE_CX8|CPU_FEATURE_TSC_FLAG|CPU_FEATURE_VME_FLAG|CPU_FEATURE_CMOV|CPU_FEATURE_MMX_FLAG|CPU_FEATURE_SSE_FLAG|CPU_FEATURE_SSE2_FLAG|CPU_FEATURE_SEP)
#define CPU_FEATURES_PENTIUM_4 (CPU_FEATURE_FPU|CPU_FEATURE_CX8|CPU_FEATURE_TSC|CPU_FEATURE_VME_FLAG|CPU_FEATURE_CMOV|CPU_FEATURE_FXSR|CPU_FEATURE_MMX|CPU_FEATURE_CLFSH|CPU_FEATURE_SSE|CPU_FEATURE_SSE2)
#define CPU_FEATURES_PENTIUM_M (CPU_FEATURE_FPU|CPU_FEATURE_CX8|CPU_FEATURE_TSC|CPU_FEATURE_VME_FLAG|CPU_FEATURE_CMOV|CPU_FEATURE_FXSR|CPU_FEATURE_MMX|CPU_FEATURE_CLFSH|CPU_FEATURE_SSE|CPU_FEATURE_SSE2)
#define CPU_FEATURES_PENTIUM_III (CPU_FEATURE_FPU|CPU_FEATURE_CX8|CPU_FEATURE_TSC|CPU_FEATURE_VME_FLAG|CPU_FEATURE_CMOV|CPU_FEATURE_FXSR|CPU_FEATURE_MMX|CPU_FEATURE_CLFSH|CPU_FEATURE_SSE)
#define CPU_FEATURES_PENTIUM_II (CPU_FEATURE_FPU|CPU_FEATURE_CX8|CPU_FEATURE_TSC|CPU_FEATURE_VME_FLAG|CPU_FEATURE_CMOV|CPU_FEATURE_FXSR|CPU_FEATURE_MMX)
#define CPU_FEATURES_PENTIUM_PRO (CPU_FEATURE_FPU|CPU_FEATURE_CX8|CPU_FEATURE_TSC|CPU_FEATURE_VME_FLAG|CPU_FEATURE_CMOV|CPU_FEATURE_FXSR)
#define CPU_FEATURES_MMX_PENTIUM (CPU_FEATURE_FPU|CPU_FEATURE_CX8|CPU_FEATURE_TSC|CPU_FEATURE_VME_FLAG|CPU_FEATURE_MMX)
#define CPU_FEATURES_PENTIUM (CPU_FEATURE_FPU|CPU_FEATURE_CX8|CPU_FEATURE_TSC|CPU_FEATURE_VME_FLAG)
#define CPU_FEATURES_I486DX (CPU_FEATURE_FPU)
#define CPU_FEATURES_I486SX (0)
#define CPU_FEATURES_80386 (0)
#define CPU_FEATURES_80286 (0)
#define CPU_FEATURES_AMD_K7_ATHLON_XP (CPU_FEATURE_FPU|CPU_FEATURE_CX8|CPU_FEATURE_TSC|CPU_FEATURE_VME_FLAG|CPU_FEATURE_CMOV|CPU_FEATURE_FXSR|CPU_FEATURE_MMX|CPU_FEATURE_CLFSH|CPU_FEATURE_SSE)
#define CPU_FEATURES_AMD_K7_ATHLON (CPU_FEATURE_FPU|CPU_FEATURE_CX8|CPU_FEATURE_TSC|CPU_FEATURE_VME_FLAG|CPU_FEATURE_CMOV|CPU_FEATURE_MMX)
#define CPU_FEATURES_AMD_K6_III (CPU_FEATURE_FPU|CPU_FEATURE_CX8|CPU_FEATURE_TSC|CPU_FEATURE_VME_FLAG|CPU_FEATURE_MMX)
#define CPU_FEATURES_AMD_K6_2 (CPU_FEATURE_FPU|CPU_FEATURE_CX8|CPU_FEATURE_TSC|CPU_FEATURE_VME_FLAG|CPU_FEATURE_MMX)
/*** extended feature ***/
#define CPU_FEATURE_EX_SYSCALL (1 << 11)
#define CPU_FEATURE_EX_XDBIT (1 << 20)
#define CPU_FEATURE_EX_EM64T (1 << 29)
#define CPU_FEATURE_EX_E3DNOW (1 << 30)
#define CPU_FEATURE_EX_3DNOW (1 << 31)
#if defined(USE_MMX)&&defined(USE_FPU)&&defined(USE_3DNOW)
#define CPU_FEATURE_EX_3DNOW_FLAG CPU_FEATURE_EX_3DNOW
#else
#define CPU_FEATURE_EX_3DNOW_FLAG 0
#endif
#if defined(USE_MMX)&&defined(USE_FPU)&&defined(USE_3DNOW)&&defined(USE_SSE)
#define CPU_FEATURE_EX_E3DNOW_FLAG CPU_FEATURE_EX_E3DNOW
#else
#define CPU_FEATURE_EX_E3DNOW_FLAG 0
#endif
/* g p ł @ \ S */
#define CPU_FEATURES_EX_ALL (CPU_FEATURE_EX_3DNOW_FLAG|CPU_FEATURE_EX_E3DNOW_FLAG)
#define CPU_FEATURES_EX_PENTIUM_4 (0)
#define CPU_FEATURES_EX_PENTIUM_M (0)
#define CPU_FEATURES_EX_PENTIUM_III (0)
#define CPU_FEATURES_EX_PENTIUM_II (0)
#define CPU_FEATURES_EX_PENTIUM_PRO (0)
#define CPU_FEATURES_EX_MMX_PENTIUM (0)
#define CPU_FEATURES_EX_PENTIUM (0)
#define CPU_FEATURES_EX_I486DX (0)
#define CPU_FEATURES_EX_I486SX (0)
#define CPU_FEATURES_EX_80386 (0)
#define CPU_FEATURES_EX_80286 (0)
#define CPU_FEATURES_EX_AMD_K6_2 (CPU_FEATURE_EX_3DNOW)
#define CPU_FEATURES_EX_AMD_K6_III (CPU_FEATURE_EX_3DNOW)
#define CPU_FEATURES_EX_AMD_K7_ATHLON (CPU_FEATURE_EX_3DNOW|CPU_FEATURE_EX_E3DNOW)
#define CPU_FEATURES_EX_AMD_K7_ATHLON_XP (CPU_FEATURE_EX_3DNOW|CPU_FEATURE_EX_E3DNOW)
/*** ECX feature ***/
#define CPU_FEATURE_ECX_SSE3 (1 << 0)
#define CPU_FEATURE_ECX_PCLMULDQ (1 << 1)
#define CPU_FEATURE_ECX_DTES64 (1 << 2)
#define CPU_FEATURE_ECX_MONITOR (1 << 3)
#define CPU_FEATURE_ECX_DSCPL (1 << 4)
#define CPU_FEATURE_ECX_VMX (1 << 5)
#define CPU_FEATURE_ECX_SMX (1 << 6)
#define CPU_FEATURE_ECX_EST (1 << 7)
#define CPU_FEATURE_ECX_TM2 (1 << 8)
#define CPU_FEATURE_ECX_SSSE3 (1 << 9)
#define CPU_FEATURE_ECX_CNXT1D (1 << 10)
/* (1 << 11) */
/* (1 << 12) */
#define CPU_FEATURE_ECX_CX16 (1 << 13)
#define CPU_FEATURE_ECX_xTPR (1 << 14)
#define CPU_FEATURE_ECX_PDCM (1 << 15)
/* (1 << 16) */
/* (1 << 17) */
#define CPU_FEATURE_ECX_DCA (1 << 18)
#define CPU_FEATURE_ECX_SSE4_1 (1 << 19)
#define CPU_FEATURE_ECX_SSE4_2 (1 << 20)
#define CPU_FEATURE_ECX_x2APIC (1 << 21)
#define CPU_FEATURE_ECX_MOVBE (1 << 22)
#define CPU_FEATURE_ECX_POPCNT (1 << 23)
/* (1 << 24) */
#define CPU_FEATURE_ECX_AES (1 << 25)
#define CPU_FEATURE_ECX_XSAVE (1 << 26)
#define CPU_FEATURE_ECX_OSXSAVE (1 << 27)
/* (1 << 28) */
/* (1 << 29) */
/* (1 << 30) */
/* (1 << 31) */
#if defined(USE_MMX)&&defined(USE_FPU)&&defined(USE_SSE)&&defined(USE_SSE2)&&defined(USE_SSE3)
#define CPU_FEATURE_ECX_SSE3_FLAG CPU_FEATURE_ECX_SSE3
#else
#define CPU_FEATURE_ECX_SSE3_FLAG 0
#endif
/* g p ł @ \ S */
#define CPU_FEATURES_ECX_ALL (CPU_FEATURE_ECX_SSE3_FLAG)
#define CPU_FEATURES_ECX_PENTIUM_4 (CPU_FEATURE_ECX_SSE3)
#define CPU_FEATURES_ECX_PENTIUM_M (0)
#define CPU_FEATURES_ECX_PENTIUM_III (0)
#define CPU_FEATURES_ECX_PENTIUM_II (0)
#define CPU_FEATURES_ECX_PENTIUM_PRO (0)
#define CPU_FEATURES_ECX_MMX_PENTIUM (0)
#define CPU_FEATURES_ECX_PENTIUM (0)
#define CPU_FEATURES_ECX_I486DX (0)
#define CPU_FEATURES_ECX_I486SX (0)
#define CPU_FEATURES_ECX_80386 (0)
#define CPU_FEATURES_ECX_80286 (0)
#define CPU_FEATURES_ECX_AMD_K6_2 (0)
#define CPU_FEATURES_ECX_AMD_K6_III (0)
#define CPU_FEATURES_ECX_AMD_K7_ATHLON (0)
#define CPU_FEATURES_ECX_AMD_K7_ATHLON_XP (0)
/* EFLAGS MASK */
#define CPU_EFLAGS_MASK_PENTIUM_4 (0)
#define CPU_EFLAGS_MASK_PENTIUM_M (0)
#define CPU_EFLAGS_MASK_PENTIUM_III (0)
#define CPU_EFLAGS_MASK_PENTIUM_II (0)
#define CPU_EFLAGS_MASK_PENTIUM_PRO (0)
#define CPU_EFLAGS_MASK_MMX_PENTIUM (0)
#define CPU_EFLAGS_MASK_PENTIUM (0)
#define CPU_EFLAGS_MASK_I486DX (0)
#define CPU_EFLAGS_MASK_I486SX (0)
#define CPU_EFLAGS_MASK_80386 ((1 << 18))
#define CPU_EFLAGS_MASK_80286 ((1 << 18))
#define CPU_EFLAGS_MASK_AMD_K6_2 (0)
#define CPU_EFLAGS_MASK_AMD_K6_III (0)
#define CPU_EFLAGS_MASK_AMD_K7_ATHLON (0)
#define CPU_EFLAGS_MASK_AMD_K7_ATHLON_XP (0)
/* brand string */
#define CPU_BRAND_STRING_PENTIUM_4 "Intel(R) Pentium(R) 4 CPU "
#define CPU_BRAND_STRING_PENTIUM_M "Intel(R) Pentium(R) M processor "
#define CPU_BRAND_STRING_PENTIUM_III "Intel(R) Pentium(R) III CPU "
#define CPU_BRAND_STRING_PENTIUM_II "Intel(R) Pentium(R) II CPU "
#define CPU_BRAND_STRING_PENTIUM_PRO "Intel(R) Pentium(R) Pro CPU "
#define CPU_BRAND_STRING_MMX_PENTIUM "Intel(R) Pentium(R) with MMX "
#define CPU_BRAND_STRING_PENTIUM "Intel(R) Pentium(R) Processor "
#define CPU_BRAND_STRING_I486DX "Intel(R) i486DX Processor "
#define CPU_BRAND_STRING_I486SX "Intel(R) i486SX Processor "
#define CPU_BRAND_STRING_80386 "Intel(R) 80386 Processor "
#define CPU_BRAND_STRING_80286 "Intel(R) 80286 Processor "
#define CPU_BRAND_STRING_AMD_K6_2 "AMD-K6(tm) 3D processor "
#define CPU_BRAND_STRING_AMD_K6_III "AMD-K6(tm) 3D+ Processor "
#define CPU_BRAND_STRING_AMD_K7_ATHLON "AMD-K7(tm) Processor "
#define CPU_BRAND_STRING_AMD_K7_ATHLON_XP "AMD Athlon(tm) XP "
#define CPU_BRAND_STRING_NEKOPRO "Neko Processor " // J X ^ ݒ
#define CPU_BRAND_STRING_NEKOPRO2 "Neko Processor II " // S @ \ g p \
/* brand id */
#define CPU_BRAND_ID_PENTIUM_4 0x9
#define CPU_BRAND_ID_PENTIUM_M 0x16
#define CPU_BRAND_ID_PENTIUM_III 0x2
#define CPU_BRAND_ID_PENTIUM_II 0
#define CPU_BRAND_ID_PENTIUM_PRO 0
#define CPU_BRAND_ID_MMX_PENTIUM 0
#define CPU_BRAND_ID_PENTIUM 0
#define CPU_BRAND_ID_I486DX 0
#define CPU_BRAND_ID_I486SX 0
#define CPU_BRAND_ID_80386 0
#define CPU_BRAND_ID_80286 0
#define CPU_BRAND_ID_AMD_K6_2 0
#define CPU_BRAND_ID_AMD_K6_III 0
#define CPU_BRAND_ID_AMD_K7_ATHLON 0
#define CPU_BRAND_ID_AMD_K7_ATHLON_XP 0
#define CPU_BRAND_ID_NEKOPRO 0 // J X ^ ݒ
#define CPU_BRAND_ID_NEKOPRO2 0 // S @ \ g p \
#define CPU_BRAND_ID_AUTO 0xffffffff // BrandID ݒ i ߋ o [ W Ƃ̌݊ ێ p j
// CPUID f t H g ݒ
#if defined(USE_FPU)
#if defined(USE_SSE3)
#define CPU_FAMILY CPU_PENTIUM_III_FAMILY
#define CPU_MODEL CPU_PENTIUM_III_MODEL /* Pentium III */
#define CPU_STEPPING CPU_PENTIUM_III_STEPPING
#define CPU_FEATURES CPU_FEATURES_PENTIUM_III
#define CPU_FEATURES_EX CPU_FEATURES_EX_PENTIUM_III
#define CPU_FEATURES_ECX CPU_FEATURES_ECX_PENTIUM_III
#define CPU_BRAND_STRING CPU_BRAND_STRING_PENTIUM_III
#define CPU_BRAND_ID CPU_BRAND_ID_PENTIUM_III
#define CPU_EFLAGS_MASK CPU_EFLAGS_MASK_PENTIUM_III
//#define CPU_FAMILY CPU_PENTIUM_4_FAMILY
//#define CPU_MODEL CPU_PENTIUM_4_MODEL /* Pentium 4 */
//#define CPU_STEPPING CPU_PENTIUM_4_STEPPING
//#define CPU_FEATURES CPU_FEATURES_PENTIUM_4
//#define CPU_FEATURES_EX CPU_FEATURES_EX_PENTIUM_4
//#define CPU_FEATURES_ECX CPU_FEATURES_ECX_PENTIUM_4
//#define CPU_BRAND_STRING CPU_BRAND_STRING_PENTIUM_4
//#define CPU_BRAND_ID CPU_BRAND_ID_PENTIUM_4
//#define CPU_EFLAGS_MASK CPU_EFLAGS_MASK_PENTIUM_4
#elif defined(USE_SSE2)
#define CPU_FAMILY CPU_PENTIUM_III_FAMILY
#define CPU_MODEL CPU_PENTIUM_III_MODEL /* Pentium III */
#define CPU_STEPPING CPU_PENTIUM_III_STEPPING
#define CPU_FEATURES CPU_FEATURES_PENTIUM_III
#define CPU_FEATURES_EX CPU_FEATURES_EX_PENTIUM_III
#define CPU_FEATURES_ECX CPU_FEATURES_ECX_PENTIUM_III
#define CPU_BRAND_STRING CPU_BRAND_STRING_PENTIUM_III
#define CPU_BRAND_ID CPU_BRAND_ID_PENTIUM_III
#define CPU_EFLAGS_MASK CPU_EFLAGS_MASK_PENTIUM_III
//#define CPU_FAMILY CPU_PENTIUM_M_FAMILY
//#define CPU_MODEL CPU_PENTIUM_M_MODEL /* Pentium M */
//#define CPU_STEPPING CPU_PENTIUM_M_STEPPING
//#define CPU_FEATURES CPU_FEATURES_PENTIUM_M
//#define CPU_FEATURES_EX CPU_FEATURES_EX_PENTIUM_M
//#define CPU_FEATURES_ECX CPU_FEATURES_ECX_PENTIUM_M
//#define CPU_BRAND_STRING CPU_BRAND_STRING_PENTIUM_M
//#define CPU_BRAND_ID CPU_BRAND_ID_PENTIUM_M
//#define CPU_EFLAGS_MASK CPU_EFLAGS_MASK_PENTIUM_M
#elif defined(USE_SSE)
#define CPU_FAMILY CPU_PENTIUM_III_FAMILY
#define CPU_MODEL CPU_PENTIUM_III_MODEL /* Pentium III */
#define CPU_STEPPING CPU_PENTIUM_III_STEPPING
#define CPU_FEATURES CPU_FEATURES_PENTIUM_III
#define CPU_FEATURES_EX CPU_FEATURES_EX_PENTIUM_III
#define CPU_FEATURES_ECX CPU_FEATURES_ECX_PENTIUM_III
#define CPU_BRAND_STRING CPU_BRAND_STRING_PENTIUM_III
#define CPU_BRAND_ID CPU_BRAND_ID_PENTIUM_III
#define CPU_EFLAGS_MASK CPU_EFLAGS_MASK_PENTIUM_III
#elif defined(USE_MMX)
#define CPU_FAMILY CPU_PENTIUM_II_FAMILY
#define CPU_MODEL CPU_PENTIUM_II_MODEL /* Pentium II */
#define CPU_STEPPING CPU_PENTIUM_II_STEPPING
#define CPU_FEATURES CPU_FEATURES_PENTIUM_II
#define CPU_FEATURES_EX CPU_FEATURES_EX_PENTIUM_II
#define CPU_FEATURES_ECX CPU_FEATURES_ECX_PENTIUM_II
#define CPU_BRAND_STRING CPU_BRAND_STRING_PENTIUM_II
#define CPU_BRAND_ID CPU_BRAND_ID_PENTIUM_II
#define CPU_EFLAGS_MASK CPU_EFLAGS_MASK_PENTIUM_II
#else
#define CPU_FAMILY CPU_PENTIUM_FAMILY
#define CPU_MODEL CPU_PENTIUM_MODEL /* Pentium */
#define CPU_STEPPING CPU_PENTIUM_STEPPING
#define CPU_FEATURES CPU_FEATURES_PENTIUM
#define CPU_FEATURES_EX CPU_FEATURES_EX_PENTIUM
#define CPU_FEATURES_ECX CPU_FEATURES_ECX_PENTIUM
#define CPU_BRAND_STRING CPU_BRAND_STRING_PENTIUM
#define CPU_BRAND_ID CPU_BRAND_ID_PENTIUM
#define CPU_EFLAGS_MASK CPU_EFLAGS_MASK_PENTIUM
#endif
#else
#define CPU_FAMILY CPU_I486SX_FAMILY
#define CPU_MODEL CPU_I486SX_MODEL /* 486SX */
#define CPU_STEPPING CPU_I486SX_STEPPING
#define CPU_FEATURES CPU_FEATURES_I486SX
#define CPU_FEATURES_EX CPU_FEATURES_EX_I486SX
#define CPU_FEATURES_ECX CPU_FEATURES_ECX_I486SX
#define CPU_BRAND_STRING CPU_BRAND_STRING_I486SX
#define CPU_BRAND_ID CPU_BRAND_ID_I486SX
#define CPU_EFLAGS_MASK CPU_EFLAGS_MASK_I486SX
#endif
#define CPU_REGS_BYTEL(n) CPU_STATSAVE.cpu_regs.reg[(n)].b.l
#define CPU_REGS_BYTEH(n) CPU_STATSAVE.cpu_regs.reg[(n)].b.h
#define CPU_REGS_WORD(n) CPU_STATSAVE.cpu_regs.reg[(n)].w.w
#define CPU_REGS_DWORD(n) CPU_STATSAVE.cpu_regs.reg[(n)].d
#define CPU_REGS_SREG(n) CPU_STATSAVE.cpu_regs.sreg[(n)]
#define CPU_STAT_SREG(n) CPU_STATSAVE.cpu_stat.sreg[(n)]
#define CPU_STAT_SREGBASE(n) CPU_STAT_SREG((n)).u.seg.segbase
#define CPU_STAT_SREGLIMIT(n) CPU_STAT_SREG((n)).u.seg.limit
#define CPU_AL CPU_REGS_BYTEL(CPU_EAX_INDEX)
#define CPU_CL CPU_REGS_BYTEL(CPU_ECX_INDEX)
#define CPU_DL CPU_REGS_BYTEL(CPU_EDX_INDEX)
#define CPU_BL CPU_REGS_BYTEL(CPU_EBX_INDEX)
#define CPU_AH CPU_REGS_BYTEH(CPU_EAX_INDEX)
#define CPU_CH CPU_REGS_BYTEH(CPU_ECX_INDEX)
#define CPU_DH CPU_REGS_BYTEH(CPU_EDX_INDEX)
#define CPU_BH CPU_REGS_BYTEH(CPU_EBX_INDEX)
#define CPU_AX CPU_REGS_WORD(CPU_EAX_INDEX)
#define CPU_CX CPU_REGS_WORD(CPU_ECX_INDEX)
#define CPU_DX CPU_REGS_WORD(CPU_EDX_INDEX)