Fix Verilog test infrastructure and restore DDC test coverage & performance capture

[iamdarshg]

Background

CI test orchestration exists but is currently brittle. The DDC (digital_downconverter) is not reliably tested in CI because of missing Python/cocotb dependencies, inconsistent test discovery, and removed performance artifacts.

Observed issues-

1. Missing cocotb-pytest module-

• Symptom: Tests failing with ModuleNotFound error

2. run_all_tests.sh expects a cocotb test for each module and has brittle fallback behavior. For DDC we have a Verilog TB (verilog/digital_downconverter_tb.v) but no cocotb test, so CI might skip or fail coverage for the DDC.
3. Verilog testbench incompatibilities with Verilator

• Some TBs use constructs or initial-block patterns that Verilator flags (procedural ROM initialization issues, use of non-blocking assignments in initial blocks, very long timeouts).
• This requires either testbench rework or explicit compilation fixes.

Primary priority is to fix the cocotb benches via conversion to verilator. I think the best approach is to entirely rewrite the verilog testing, to better capture the requirements of this Software Defined Radio.

What are these requirements?

• It must be able to take in raw 12-bit adc samples via 13 wires- one clock and 12 data pins at 105 MSPS or higher
• It must be able to convert all of these points into the frequency domain, via 4096 or ideally 8192 point FFT.
• It must be able to generate the correct packets and pass them on to the ethernet controller via the GMII interface.

For more info regarding the requirements and condition of the FPGA, see the schematic in te hardware section.