diff --git a/hal/src/peripherals/adc/builder.rs b/hal/src/peripherals/adc/builder.rs
index baaa62e74b83..cb81c09d3b7c 100644
--- a/hal/src/peripherals/adc/builder.rs
+++ b/hal/src/peripherals/adc/builder.rs
@@ -245,7 +245,6 @@ impl AdcBuilder {
     }
 
     /// Turn the builder into an ADC
-    #[hal_cfg("adc-d5x")]
     #[inline]
     pub fn enable<I: AdcInstance, PS: crate::clock::v2::pclk::PclkSourceId>(
         self,
@@ -256,16 +255,4 @@ impl AdcBuilder {
         let settings = self.to_settings()?;
         Adc::new(adc, settings, clk, pclk).map_err(|e| e.into())
     }
-
-    #[hal_cfg(any("adc-d11", "adc-d21"))]
-    #[inline]
-    pub fn enable<I: AdcInstance>(
-        self,
-        adc: I::Instance,
-        pm: &mut crate::pac::Pm,
-        clock: &crate::clock::AdcClock,
-    ) -> Result<Adc<I>, BuilderError> {
-        let settings = self.to_settings()?;
-        Adc::new(adc, settings, pm, clock).map_err(|e| e.into())
-    }
 }
diff --git a/hal/src/peripherals/adc/d11/mod.rs b/hal/src/peripherals/adc/d11/mod.rs
index d43d76012144..be5753932679 100644
--- a/hal/src/peripherals/adc/d11/mod.rs
+++ b/hal/src/peripherals/adc/d11/mod.rs
@@ -22,6 +22,8 @@ impl PrimaryAdc for Adc0 {}
 impl AdcInstance for Adc0 {
     type Instance = pac::Adc;
 
+    type ClockId = crate::clock::v2::pclk::ids::Adc0;
+
     #[cfg(feature = "async")]
     type Interrupt = crate::async_hal::interrupts::ADC;
 
@@ -30,11 +32,6 @@ impl AdcInstance for Adc0 {
         &p.adc
     }
 
-    #[inline]
-    fn enable_pm(pm: &mut pac::Pm) {
-        pm.apbcmask().modify(|_, w| w.adc_().set_bit());
-    }
-
     #[inline]
     fn calibrate(instance: &Self::Instance) {
         instance.calib().write(|w| unsafe {
diff --git a/hal/src/peripherals/adc/mod.rs b/hal/src/peripherals/adc/mod.rs
index c34b560ad113..267baa0c5779 100644
--- a/hal/src/peripherals/adc/mod.rs
+++ b/hal/src/peripherals/adc/mod.rs
@@ -140,14 +140,10 @@ pub trait AdcInstance {
     // The Adc0 and Adc1 PAC types implement Deref
     type Instance: Deref<Target = adc0::RegisterBlock>;
 
-    #[hal_cfg("adc-d5x")]
     type ClockId: crate::clock::v2::apb::ApbId + crate::clock::v2::pclk::PclkId;
 
     fn peripheral_reg_block(p: &mut Peripherals) -> &adc0::RegisterBlock;
 
-    #[hal_cfg(any("adc-d11", "adc-d21"))]
-    fn enable_pm(pm: &mut pac::Pm);
-
     fn calibrate(instance: &Self::Instance);
 
     #[cfg(feature = "async")]
@@ -162,16 +158,6 @@ where
     const CHANNEL: u8;
 }
 
-/// ADC Instance
-#[hal_cfg(any("adc-d11", "adc-d21"))]
-pub struct Adc<I: AdcInstance> {
-    adc: I::Instance,
-    cfg: AdcSettings,
-    discard: bool,
-}
-
-/// ADC Instance
-#[hal_cfg("adc-d5x")]
 pub struct Adc<I: AdcInstance> {
     adc: I::Instance,
     _apbclk: crate::clock::v2::apb::ApbClk<I::ClockId>,
@@ -191,18 +177,18 @@ impl<I: AdcInstance> Adc<I> {
     /// ## Important
     ///
     /// This function will return `Err` if the clock source provided
-    /// is faster than 100 MHz, since this is the maximum frequency for
-    /// GCLK_ADCx as per the datasheet.
+    /// is faster than 100 MHz (D5x) or 48Mhz (D21/D11), since this
+    /// is the maximum frequency for GCLK_ADCx as per the datasheet.
     ///
     /// The [`new`](Self::new) function currently takes an `&` reference to a
     /// [`Pclk`](crate::clock::v2::pclk::Pclk). In the future this will likely
     /// change to taking full ownership of it; in the meantime, you must ensure
     /// that the PCLK is enabled for the `Adc` struct's lifetime.
     ///
-    /// NOTE: If you plan to run the chip above 100°C, then the maximum GCLK
+    /// NOTE (D5x specific): If you plan to run the chip above 100°C, then the maximum GCLK
     /// frequency for the ADC is restricted to 90Mhz for stable performance.
-    #[hal_cfg("adc-d5x")]
     #[inline]
+    #[atsamd_hal_macros::hal_macro_helper]
     pub(crate) fn new<PS: crate::clock::v2::pclk::PclkSourceId>(
         adc: I::Instance,
         settings: AdcSettings,
@@ -218,44 +204,20 @@ impl<I: AdcInstance> Adc<I> {
         // at the time of creation of the Adc struct; however we can't guarantee
         // that the clock will stay enabled for the duration of its lifetime.
 
+        #[hal_cfg("adc-d5x")]
         if pclk.freq() > fugit::HertzU32::from_raw(100_000_000) {
             // Clock source is too fast
             return Err(Error::ClockTooFast);
         }
-
-        let mut new_adc = Self {
-            adc,
-            _apbclk: clk,
-            cfg: settings,
-            discard: true,
-        };
-        new_adc.configure(settings);
-        Ok(new_adc)
-    }
-
-    /// Construct a new ADC instance
-    ///
-    /// ## Important
-    ///
-    /// This function will return [Error::ClockTooFast] if the clock source
-    /// provided is faster than 48 MHz, since this is the maximum frequency
-    /// for the ADC as per the datasheet.
-    #[hal_cfg(any("adc-d11", "adc-d21"))]
-    #[inline]
-    pub(crate) fn new(
-        adc: I::Instance,
-        settings: AdcSettings,
-        pm: &mut pac::Pm,
-        clock: &crate::clock::AdcClock,
-    ) -> Result<Self, Error> {
-        if (clock.freq() as crate::time::Hertz).to_Hz() > 48_000_000 {
+        #[hal_cfg(any("adc-d21", "adc-d11"))]
+        if pclk.freq() > fugit::HertzU32::from_raw(48_000_000) {
             // Clock source is too fast
             return Err(Error::ClockTooFast);
         }
 
-        I::enable_pm(pm);
         let mut new_adc = Self {
             adc,
+            _apbclk: clk,
             cfg: settings,
             discard: true,
         };
@@ -412,16 +374,7 @@ impl<I: AdcInstance> Adc<I> {
         Ok(())
     }
 
-    /// Return the underlying ADC PAC object.
-    #[hal_cfg(any("adc-d11", "adc-d21"))]
-    #[inline]
-    pub fn free(mut self) -> I::Instance {
-        self.software_reset();
-        self.adc
-    }
-
     /// Return the underlying ADC PAC object and the enabled APB ADC clock.
-    #[hal_cfg("adc-d5x")]
     #[inline]
     pub fn free(mut self) -> (I::Instance, crate::clock::v2::apb::ApbClk<I::ClockId>) {
         self.software_reset();