core: arm: refactor feat_crc32_implemented

igoropaniuk · igoropaniuk · commit a3d836918415 · 2024-02-17T16:33:09.000+01:00
1. Add support for checking CRC32 HW instruction in aarch32.
2. Use newly defined masks for aarch64.

Signed-off-by: Igor Opaniuk &lt;igor.opaniuk@foundries.io&gt;
diff --git a/core/arch/arm/include/arm.h b/core/arch/arm/include/arm.h
@@ -181,10 +181,9 @@ static inline unsigned int feat_pan_implemented(void)
 static inline bool feat_crc32_implemented(void)
 {
 #ifdef ARM32
-	return false;
+	return read_id_isar5() & ID_ISAR5_CRC32;
 #else
-	return ((read_id_aa64isar0_el1() >> ID_AA64ISAR0_EL1_CRC32_SHIFT) &
-		ID_AA64ISAR0_EL1_CRC32_MASK) == FEAT_CRC32_IMPLEMENTED;
+	return read_id_aa64isar0_el1() & ID_AA64ISAR0_CRC32;
 #endif
 }
 
diff --git a/core/arch/arm/include/arm64.h b/core/arch/arm/include/arm64.h
@@ -257,11 +257,6 @@
 #define FEAT_PAN2_IMPLEMENTED		U(0x2)
 #define FEAT_PAN3_IMPLEMENTED		U(0x3)
 
-#define ID_AA64ISAR0_EL1_CRC32_MASK	UL(0xf)
-#define ID_AA64ISAR0_EL1_CRC32_SHIFT	U(16)
-#define FEAT_CRC32_NOT_IMPLEMENTED	U(0x0)
-#define FEAT_CRC32_IMPLEMENTED		U(0x1)
-
 #define ID_AA64ISAR1_GPI_SHIFT		U(28)
 #define ID_AA64ISAR1_GPI_MASK		U(0xf)
 #define ID_AA64ISAR1_GPI_NI		U(0x0)

Original file line number	Diff line number	Diff line change
`@@ -181,10 +181,9 @@ static inline unsigned int feat_pan_implemented(void)`
`181`	`181`	`static inline bool feat_crc32_implemented(void)`
`182`	`182`	`{`
`183`	`183`	`#ifdef ARM32`
`184`		`- return false;`
	`184`	`+ return read_id_isar5() & ID_ISAR5_CRC32;`
`185`	`185`	`#else`
`186`		`- return ((read_id_aa64isar0_el1() >> ID_AA64ISAR0_EL1_CRC32_SHIFT) &`
`187`		`- ID_AA64ISAR0_EL1_CRC32_MASK) == FEAT_CRC32_IMPLEMENTED;`
	`186`	`+ return read_id_aa64isar0_el1() & ID_AA64ISAR0_CRC32;`
`188`	`187`	`#endif`
`189`	`188`	`}`
`190`	`189`