Address code review comments

Author: bowenxue-intel

sycl/include/sycl/device_aspect_macros.hpp

@@ -624,6 +624,6 @@
 #endif
 
 #ifndef __SYCL_ANY_DEVICE_HAS_ext_intel_fpga_task_sequence__
-// __SYCL_ASPECT(ext_oneapi_tangle_group, 61)
+// __SYCL_ASPECT(ext_intel_fpga_task_sequence__, 61)
 #define __SYCL_ANY_DEVICE_HAS_ext_intel_fpga_task_sequence__ 0
 #endif

sycl/include/sycl/ext/intel/experimental/fpga_kernel_properties.hpp

@@ -108,11 +108,11 @@ inline constexpr fpga_cluster_key::value_t<option> fpga_cluster;
 
 inline constexpr fpga_cluster_key::value_t<
     fpga_cluster_options_enum::stall_free>
-    use_stall_free_clusters;
+    stall_free_clusters;
 
 inline constexpr fpga_cluster_key::value_t<
     fpga_cluster_options_enum::stall_enable>
-    use_stall_enable_clusters;
+    stall_enable_clusters;
 
 } // namespace ext::intel::experimental
 

sycl/include/sycl/ext/intel/experimental/task_sequence.hpp

@@ -1,4 +1,3 @@
-/* INTEL_CUSTOMIZATION */
 //==--------------------------- task_sequence.hpp --------------------------==//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
@@ -60,17 +59,17 @@ class task_sequence<
         &f, pipelined, fpga_cluster, response_capacity, invocation_capacity);
 #else
     throw exception{make_error_code(errc::feature_not_supported),
-                    "task_sequence is not supported on host device"};
+                    "task_sequence is not supported on the host"};
 #endif
   }
 
-  void async(ArgsT... Args) {
+  void async([[maybe_unused]] ArgsT... Args) {
 #if defined(__SYCL_DEVICE_ONLY__)
     ++outstanding;
     __spirv_TaskSequenceAsyncINTEL(taskSequence, Args...);
 #else
     throw exception{make_error_code(errc::feature_not_supported),
-                    "task_sequence is not supported on host device"};
+                    "task_sequence is not supported on the host"};
 #endif
   }
 
@@ -80,7 +79,7 @@ class task_sequence<
     return __spirv_TaskSequenceGetINTEL<ReturnT>(taskSequence);
 #else
     throw exception{make_error_code(errc::feature_not_supported),
-                    "task_sequence is not supported on host device"};
+                    "task_sequence is not supported on the host"};
 #endif
   }
 
@@ -91,11 +90,8 @@ class task_sequence<
         get();
     }
     __spirv_TaskSequenceReleaseINTEL(taskSequence);
-#else
-    // throw exception{make_error_code(errc::feature_not_supported),
-    //                 "task_sequence is not supported on host device"};
-    // Destructor shouldn't throw exception.
 #endif
+    // Destructor shouldn't throw exception.
   }
 
   template <typename propertyT> static constexpr bool has_property() {

sycl/include/sycl/ext/intel/experimental/task_sequence_properties.hpp

@@ -1,4 +1,3 @@
-/* INTEL_CUSTOMIZATION */
 //==-- task_sequence_properties.hpp - Specific properties of task_sequence -==//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.

sycl/test-e2e/TaskSequence/concurrent-loops.cpp

@@ -89,9 +89,6 @@ int main() {
     q.wait();
   }
 
-  if (abs(out[0] - golden) < 0.001)
-    std::cout << "PASSED\n";
-  else
-    std::cout << "FAILED\n";
+  assert(abs(out[0] - golden) < 0.001);
   return 0;
 }

sycl/test-e2e/TaskSequence/in-order-async-get.cpp

@@ -61,14 +61,9 @@ int main() {
   }
 
   // verification
-  bool passed = true;
   for (int i = 0; i < kNumInputs; ++i) {
-    if (abs(results[i] - golden[i]) > 0.0001)
-      passed = false;
+    assert(abs(results[i] - golden[i]) < 0.001);
   }
-  if (passed)
-    std::cout << "PASSED\n";
-  else
-    std::cout << "FAILED\n";
+
   return 0;
 }

sycl/test-e2e/TaskSequence/mult-and-add.cpp

@@ -37,9 +37,5 @@ int main() {
   });
   myQueue.wait();
 
-  // Check result:
-  if (result == 1 * 2 + 3 * 4)
-    std::cout << "PASSED\n";
-  else
-    std::cout << "FAILED\n";
+  assert(result == (1 * 2 + 3 * 4));
 }

sycl/test-e2e/TaskSequence/multi-kernel-task-function-reuse.cpp

@@ -74,13 +74,7 @@ int main() {
     q.wait();
   }
 
-  if (out[0] == golden)
-    std::cout << "PASSED sequential test" << std::endl;
-  else
-    std::cout << "FAILED" << std::endl;
-
-  if (out[1] == golden)
-    std::cout << "PASSED parallel test" << std::endl;
-  else
-    std::cout << "FAILED" << std::endl;
+  assert(out[0] == golden);
+  assert(out[1] == golden);
+  return 0;
 }

sycl/test-e2e/TaskSequence/producer-consumer.cpp

@@ -56,11 +56,6 @@ int main() {
   int sum = 0;
   for (int i = 0; i < kSize; ++i)
     sum += i * i + 42;
-  if (result == sum) {
-    std::cout << "PASSED\n";
-    return 0;
-  } else {
-    std::cout << "FAILED\n";
-    return 1;
-  }
+  assert(result == sum);
+  return 0;
 }

sycl/test-e2e/TaskSequence/struct-array-args-and-return.cpp

@@ -168,8 +168,6 @@ int main() {
     });
     q.wait();
   }
-  bool passed = check(res_struct) && check(res_array);
-  std::cout << (passed ? "PASSED\n" : "FAILED\n");
-
+  assert(check(res_struct) && check(res_array));
   return 0;
 }

sycl/test/check_device_code/task_sequence_intel_no_explicit_get.cpp

@@ -28,7 +28,7 @@ int main() {
     cgh.single_task([=]() {
       int d1[kSize], d2[kSize];
       task_sequence<arrayAdd,
-                    decltype(properties{pipelined<0>, use_stall_enable_clusters,
+                    decltype(properties{pipelined<0>, stall_enable_clusters,
                                         invocation_capacity<1>,
                                         response_capacity<1>})>
           arrayAddTask;

sycl/test/extensions/properties/properties_kernel_fpga.cpp

@@ -81,12 +81,12 @@ int main() {
                    intel::experimental::register_map_interface_options_enum::
                        do_not_wait_for_done_write>)>);
   static_assert(
-      std::is_same_v<decltype(intel::experimental::use_stall_enable_clusters),
+      std::is_same_v<decltype(intel::experimental::stall_enable_clusters),
                      decltype(intel::experimental::fpga_cluster<
                               intel::experimental::fpga_cluster_options_enum::
                                   stall_enable>)>);
   static_assert(
-      std::is_same_v<decltype(intel::experimental::use_stall_free_clusters),
+      std::is_same_v<decltype(intel::experimental::stall_free_clusters),
                      decltype(intel::experimental::fpga_cluster<
                               intel::experimental::fpga_cluster_options_enum::
                                   stall_free>)>);
@@ -95,7 +95,7 @@ int main() {
   using PS = decltype(oneapi::experimental::properties(
       intel::experimental::streaming_interface_remove_downstream_stall,
       intel::experimental::pipelined<1>,
-      intel::experimental::use_stall_enable_clusters));
+      intel::experimental::stall_enable_clusters));
   static_assert(oneapi::experimental::is_property_list_v<PS>);
   static_assert(
       PS::has_property<intel::experimental::streaming_interface_key>());
@@ -116,7 +116,7 @@ int main() {
   using PR = decltype(oneapi::experimental::properties(
       intel::experimental::register_map_interface_wait_for_done_write,
       intel::experimental::pipelined<0>,
-      intel::experimental::use_stall_free_clusters));
+      intel::experimental::stall_free_clusters));
   static_assert(oneapi::experimental::is_property_list_v<PR>);
   static_assert(
       PR::has_property<intel::experimental::register_map_interface_key>());

sycl/test/extensions/task_sequence/task_sequence_properties.cpp

@@ -12,11 +12,11 @@ void dummyTask() {}
 static task_sequence<dummyTask,
                      decltype(properties(balanced, response_capacity<0>,
                                          invocation_capacity<0>, pipelined<-1>,
-                                         use_stall_free_clusters))>
+                                         stall_free_clusters))>
     TaskSequence1;
 static task_sequence<
     dummyTask, decltype(properties(response_capacity<2>, invocation_capacity<3>,
-                                   pipelined<1>, use_stall_enable_clusters))>
+                                   pipelined<1>, stall_enable_clusters))>
     TaskSequence2;
 static task_sequence<dummyTask, decltype(properties(pipelined<0>))>
     TaskSequence3;
@@ -52,8 +52,8 @@ int main() {
   static_assert(is_property_value<decltype(pipelined<-1>)>::value);
   static_assert(is_property_value<decltype(pipelined<0>)>::value);
   static_assert(is_property_value<decltype(pipelined<1>)>::value);
-  static_assert(is_property_value<decltype(use_stall_enable_clusters)>::value);
-  static_assert(is_property_value<decltype(use_stall_free_clusters)>::value);
+  static_assert(is_property_value<decltype(stall_enable_clusters)>::value);
+  static_assert(is_property_value<decltype(stall_free_clusters)>::value);
 
   checkIsPropertyOf<decltype(TaskSequence1)>();
   static_assert(TaskSequence1.has_property<balanced_key>());
@@ -68,7 +68,7 @@ int main() {
                 invocation_capacity<0>);
   static_assert(TaskSequence1.get_property<pipelined_key>() == pipelined<-1>);
   static_assert(TaskSequence1.get_property<fpga_cluster_key>() ==
-                use_stall_free_clusters);
+                stall_free_clusters);
 
   checkIsPropertyOf<decltype(TaskSequence2)>();
   static_assert(!TaskSequence2.has_property<balanced_key>());
@@ -82,7 +82,7 @@ int main() {
                 invocation_capacity<3>);
   static_assert(TaskSequence2.get_property<pipelined_key>() == pipelined<1>);
   static_assert(TaskSequence2.get_property<fpga_cluster_key>() ==
-                use_stall_enable_clusters);
+                stall_enable_clusters);
 
   checkIsPropertyOf<decltype(TaskSequence3)>();
   static_assert(!TaskSequence3.has_property<balanced_key>());