Is pcm supported for Core i7?

[vimalk78]

Is pcm supported for Core i7? or is it supported for Core processors in general? or does it support only Xeon?

I am using pcm-power on my laptop with below processor

$ lscpu 
Architecture:            x86_64
  CPU op-mode(s):        32-bit, 64-bit
  Address sizes:         39 bits physical, 48 bits virtual
  Byte Order:            Little Endian
CPU(s):                  16
  On-line CPU(s) list:   0-15
Vendor ID:               GenuineIntel
  Model name:            11th Gen Intel(R) Core(TM) i7-11850H @ 2.50GHz
    CPU family:          6
    Model:               141
    Thread(s) per core:  2
    Core(s) per socket:  8
    Socket(s):           1
    Stepping:            1
    CPU(s) scaling MHz:  30%
    CPU max MHz:         4800.0000
    CPU min MHz:         800.0000

i am getting following error

Unsupported processor model (140).

[vimalk78]

perhaps same as #298 ?

[rdementi]

the main pcm utility should be supported on your CPU. For pcm-power this is the answer: https://github.com/intel/pcm/blob/master/doc/FAQ.md#q5

[vimalk78]

actually i have been using pcm-senseor-server and connecting the prometheus + grafana to it to view the metrics. But that grafana doesn't show Socket Energy Consumption. It shows 'No Data' message.

i compiled the pcm-sensor-server locally and using that.

[rdementi]

does the pcm command line utility show the energy consumption? Could you post a screenshot from the pcm output?

[vimalk78]

it seems to show power values

$ sudo pcm

 Intel(r) Performance Counter Monitor (2023-07-14 10:01:29 +0200 ID=ccc53261)



=====  Processor information  =====
Linux arch_perfmon flag  : yes
Hybrid processor         : no
IBRS and IBPB supported  : yes
STIBP supported          : yes
Spec arch caps supported : yes
Max CPUID level          : 27
CPU model number         : 141
Number of physical cores: 8
Number of logical cores: 16
Number of online logical cores: 16
Threads (logical cores) per physical core: 2
Num sockets: 1
Physical cores per socket: 8
Last level cache slices per socket: 8
Core PMU (perfmon) version: 5
Number of core PMU generic (programmable) counters: 8
Width of generic (programmable) counters: 48 bits
Number of core PMU fixed counters: 4
Width of fixed counters: 48 bits
Nominal core frequency: 2500000000 Hz
IBRS enabled in the kernel   : yes
STIBP enabled in the kernel  : no
The processor is not susceptible to Rogue Data Cache Load: yes
The processor supports enhanced IBRS                     : yes
Package thermal spec power: 45 Watt; Package minimum power: 0 Watt; Package maximum power: 0 Watt;

INFO: Linux perf interface to program uncore PMUs is NOT present

 Closed perf event handles
Trying to use Linux perf events...
Successfully programmed on-core PMU using Linux perf

Detected 11th Gen Intel(R) Core(TM) i7-11850H @ 2.50GHz "Intel(r) microarchitecture codename Tiger Lake" stepping 1 microcode level 0x46

 EXEC  : instructions per nominal CPU cycle
 IPC   : instructions per CPU cycle
 FREQ  : relation to nominal CPU frequency='unhalted clock ticks'/'invariant timer ticks' (includes Intel Turbo Boost)
 AFREQ : relation to nominal CPU frequency while in active state (not in power-saving C state)='unhalted clock ticks'/'invariant timer ticks while in C0-state'  (includes Intel Turbo Boost)
 L3MISS: L3 (read) cache misses 
 L2MISS: L2 (read) cache misses (including other core's L2 cache *hits*) 
 L3HIT : L3 (read) cache hit ratio (0.00-1.00)
 L2HIT : L2 cache hit ratio (0.00-1.00)
 L3MPI : number of L3 (read) cache misses per instruction
 L2MPI : number of L2 (read) cache misses per instruction
 READ  : bytes read from main memory controller (in GBytes)
 WRITE : bytes written to main memory controller (in GBytes)
 TEMP  : Temperature reading in 1 degree Celsius relative to the TjMax temperature (thermal headroom): 0 corresponds to the max temperature
 energy: Energy in Joules


 Core (SKT) | EXEC | IPC  | FREQ  | AFREQ | L3MISS | L2MISS | L3HIT | L2HIT | L3MPI | L2MPI |  TEMP

   0    0     0.03   1.08   0.02    0.43      45 K    109 K    0.54    0.29  0.0007  0.0017     56
   1    0     0.00   0.35   0.01    0.51      10 K     44 K    0.73    0.32  0.0021  0.0087     56
   2    0     0.00   0.37   0.01    0.45      31 K     70 K    0.52    0.28  0.0033  0.0075     54
   3    0     0.01   0.97   0.01    0.52      24 K     56 K    0.52    0.43  0.0009  0.0020     56
   4    0     0.00   0.34   0.01    0.43      40 K     92 K    0.54    0.42  0.0055  0.0124     56
   5    0     0.00   0.35   0.01    0.44      57 K     95 K    0.37    0.37  0.0050  0.0083     55
   6    0     0.01   0.50   0.03    0.81      32 K     80 K    0.58    0.58  0.0010  0.0025     57
   7    0     0.00   0.47   0.01    0.43      21 K     50 K    0.53    0.70  0.0019  0.0045     56
   8    0     0.01   0.49   0.02    0.53      50 K    110 K    0.51    0.43  0.0021  0.0046     56
   9    0     0.00   0.45   0.01    0.49      31 K     82 K    0.60    0.49  0.0039  0.0102     56
  10    0     0.00   0.64   0.01    0.62      15 K     43 K    0.62    0.32  0.0016  0.0046     54
  11    0     0.00   0.40   0.01    0.48      24 K     55 K    0.51    0.38  0.0029  0.0066     56
  12    0     0.01   0.92   0.01    0.46      16 K     39 K    0.53    0.34  0.0010  0.0023     56
  13    0     0.07   1.01   0.07    1.05     173 K    402 K    0.56    0.83  0.0009  0.0022     55
  14    0     0.01   0.76   0.01    0.57      34 K     74 K    0.52    0.34  0.0017  0.0037     57
  15    0     0.01   0.61   0.01    0.50      44 K    102 K    0.54    0.54  0.0020  0.0046     56
---------------------------------------------------------------------------------------------------------------
 SKT    0     0.01   0.73   0.02    0.60     656 K   1513 K    0.54    0.66  0.0014  0.0032     50
---------------------------------------------------------------------------------------------------------------
 TOTAL  *     0.01   0.73   0.02    0.60     656 K   1513 K    0.54    0.66  0.0014  0.0032     N/A

 Instructions retired:  467 M ; Active cycles:  644 M ; Time (TSC): 2497 Mticks ; C0 (active,non-halted) core residency: 2.69 %

 C1 core residency: 7.96 %; C3 core residency: 0.00 %; C6 core residency: 0.00 %; C7 core residency: 89.35 %;
 C0 package residency: 41.20 %; C2 package residency: 56.77 %; C3 package residency: 2.04 %; C6 package residency: 0.00 %; C7 package residency: 0.00 %; C8 package residency: 0.00 %; C9 package residency: 0.00 %; C10 package residency: 0.00 %;
                             ┌───────────────────────────────────────────────────────────────────────────────┐
 Core    C-state distribution│0011111177777777777777777777777777777777777777777777777777777777777777777777777│
                             └───────────────────────────────────────────────────────────────────────────────┘
                             ┌────────────────────────────────────────────────────────────────────────────────┐
 Package C-state distribution│00000000000000000000000000000000022222222222222222222222222222222222222222222233│
                             └────────────────────────────────────────────────────────────────────────────────┘

 PHYSICAL CORE IPC                 : 1.45 => corresponds to 29.03 % utilization for cores in active state
 Instructions per nominal CPU cycle: 0.02 => corresponds to 0.47 % core utilization over time interval
 Pipeline stalls: Frontend bound: 40 %, bad Speculation: 9 %, Backend bound: 33 %, Retiring: 15 %
                             ┌─────────────────────────────────────────────────────────────────────────────────┐
 Pipeline stall distribution │FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFSSSSSSSSBBBBBBBBBBBBBBBBBBBBBBBBBBBRRRRRRRRRRRRR│
                             └─────────────────────────────────────────────────────────────────────────────────┘

 SMI count: 0
---------------------------------------------------------------------------------------------------------------
MEM (GB)->|  READ |  WRITE | CPU energy |
---------------------------------------------------------------------------------------------------------------
 SKT   0     0.58     0.20       3.79
---------------------------------------------------------------------------------------------------------------

 EXEC  : instructions per nominal CPU cycle
 IPC   : instructions per CPU cycle
 FREQ  : relation to nominal CPU frequency='unhalted clock ticks'/'invariant timer ticks' (includes Intel Turbo Boost)
 AFREQ : relation to nominal CPU frequency while in active state (not in power-saving C state)='unhalted clock ticks'/'invariant timer ticks while in C0-state'  (includes Intel Turbo Boost)
 L3MISS: L3 (read) cache misses 
 L2MISS: L2 (read) cache misses (including other core's L2 cache *hits*) 
 L3HIT : L3 (read) cache hit ratio (0.00-1.00)
 L2HIT : L2 cache hit ratio (0.00-1.00)
 L3MPI : number of L3 (read) cache misses per instruction
 L2MPI : number of L2 (read) cache misses per instruction
 READ  : bytes read from main memory controller (in GBytes)
 WRITE : bytes written to main memory controller (in GBytes)
 TEMP  : Temperature reading in 1 degree Celsius relative to the TjMax temperature (thermal headroom): 0 corresponds to the max temperature
 energy: Energy in Joules


 Core (SKT) | EXEC | IPC  | FREQ  | AFREQ | L3MISS | L2MISS | L3HIT | L2HIT | L3MPI | L2MPI |  TEMP

   0    0     0.00   0.36   0.01    0.40      34 K    104 K    0.63    0.28  0.0033  0.0098     56
   1    0     0.00   0.98   0.00    0.41    8349       24 K    0.61    0.31  0.0008  0.0023     57
   2    0     0.00   0.37   0.01    0.43      27 K     56 K    0.48    0.25  0.0036  0.0074     55
   3    0     0.03   1.48   0.02    0.43      38 K     77 K    0.48    0.26  0.0005  0.0010     57
   4    0     0.04   0.89   0.04    0.78     151 K    270 K    0.43    0.79  0.0015  0.0027     56
   5    0     0.01   0.48   0.02    0.46     106 K    313 K    0.66    0.53  0.0046  0.0137     57
   6    0     0.01   0.64   0.01    0.47      35 K     65 K    0.44    0.51  0.0024  0.0044     57
   7    0     0.00   0.44   0.01    0.41      30 K     59 K    0.46    0.50  0.0030  0.0059     57
   8    0     0.02   1.17   0.02    0.46      43 K     89 K    0.49    0.40  0.0008  0.0016     56
   9    0     0.01   0.68   0.01    0.60      31 K    220 K    0.86    0.57  0.0018  0.0128     57
  10    0     0.00   0.47   0.00    0.42      16 K     34 K    0.49    0.25  0.0028  0.0062     55
  11    0     0.00   0.27   0.00    0.46      20 K     37 K    0.42    0.23  0.0066  0.0120     57
  12    0     0.01   0.97   0.01    0.42      25 K     48 K    0.45    0.36  0.0013  0.0024     56
  13    0     0.00   0.50   0.01    0.41      21 K     36 K    0.40    0.31  0.0031  0.0053     57
  14    0     0.01   0.75   0.01    0.44      28 K     51 K    0.44    0.28  0.0015  0.0027     57
  15    0     0.00   0.50   0.01    0.46      31 K     61 K    0.47    0.40  0.0036  0.0070     57
---------------------------------------------------------------------------------------------------------------
 SKT    0     0.01   0.79   0.01    0.49     651 K   1553 K    0.57    0.57  0.0017  0.0040     51
---------------------------------------------------------------------------------------------------------------
 TOTAL  *     0.01   0.79   0.01    0.49     651 K   1553 K    0.57    0.57  0.0017  0.0040     N/A

 Instructions retired:  387 M ; Active cycles:  490 M ; Time (TSC): 2497 Mticks ; C0 (active,non-halted) core residency: 2.49 %

 C1 core residency: 5.79 %; C3 core residency: 0.00 %; C6 core residency: 0.00 %; C7 core residency: 91.72 %;
 C0 package residency: 38.29 %; C2 package residency: 59.52 %; C3 package residency: 2.19 %; C6 package residency: 0.00 %; C7 package residency: 0.00 %; C8 package residency: 0.00 %; C9 package residency: 0.00 %; C10 package residency: 0.00 %;
                             ┌────────────────────────────────────────────────────────────────────────────────┐
 Core    C-state distribution│00111117777777777777777777777777777777777777777777777777777777777777777777777777│
                             └────────────────────────────────────────────────────────────────────────────────┘
                             ┌─────────────────────────────────────────────────────────────────────────────────┐
 Package C-state distribution│000000000000000000000000000000022222222222222222222222222222222222222222222222233│
                             └─────────────────────────────────────────────────────────────────────────────────┘

[rdementi]

could you post the full output? The data values are cut off

[vimalk78]

could you post the full output? The data values are cut off

updated comment

[rdementi]

actually i have been using pcm-senseor-server and connecting the prometheus + grafana to it to view the metrics. But that grafana doesn't show Socket Energy Consumption. It shows 'No Data' message.

i compiled the pcm-sensor-server locally and using that.

do other metrics show up and just "Socket Energy Consumption" is missing?

[vimalk78]

do other metrics show up and just "Socket Energy Consumption" is missing?

the charts which are zero are:

• all Memory Bandwidth related charts
• QPI Data traffic related charts
• Socket0 Energy Consumption

Sharing screenshots of all charts

[vimalk78]

pcm-power reports "Unsupported processor model". Can you add support for pcm-power for my CPU?

Answer: most likely you have a client CPU which does not have required hardware performance monitoring units. PCM-power can not work without them.

if pcm can report power, it means CPU has what is needed to read power. (perhaps RAPL). then pcm-sensor-server also should be able to read power. .right?

[opcm]

correct. Thank you for reporting the issue.

[vimalk78]

is there something i can contribute to fix the issue (if it is a minor issue) ?

[opcm]

if possible, it would be greatly appreciated if you could take the time to investigate what is missing in the pcm-sensor-server code for client CPU (the metric is already supported for server CPUs). If you are able to identify a solution, we would welcome your contribution via a pull request.