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Resolve race condition in RohdConnector during interactive debug and SV timeout #15

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mkorbel1 opened this issue Feb 8, 2023 · 0 comments
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mkorbel1 commented Feb 8, 2023

There is a block of code in rohd_connector.py which is designed to detect whether there was a timeout waiting for the SystemVerilog simulator to complete a tick:

            if not ready_to_read and self.mid_tick:
                # not necessarily an error, since maybe SV simulator called $finish
                print('Timeout waiting for tick to complete in Simulator!', flush=True)
                self.shutdown()
                break

This code is only necessary because sometimes simulators appear to not properly indicate to cocotb that the simulation has ended, so a graceful shutdown cannot be achieved (cocotb/cocotb#3121).

The race condition appears if ROHD is being interactively debugged and fails to send the entirety of a tick's information (i.e. not ready_to_read) even though a tick is ongoing (i.e. self.mid_tick).

For most users, unless actively debugging ROHD Cosim itself, this will not be often hit.

@mkorbel1 mkorbel1 added the bug Something isn't working label Feb 8, 2023
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