Enable cosim access to hierarchically reference signals in SystemVerilog modules and submodules

[mkorbel1]

There's already support for accessing registered ports of ExternalSystemVerilogModules, but it would be cool to be able to access other non-port signals in modules or submodules in the SystemVerilog.

This opens the question of "listening" to other signals in addition to just driving them. Also, this could overlap with inputs, should we be able to listen to those as well? What about handling of infinite loops of listening?

What if you have a ROHD module, within a SystemVerilog module, within a ROHD module? To access relative signals from ROHD to ROHD would require context of their relative hierarchies.