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Add testing for 0-width input and output ports #9

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mkorbel1 opened this issue Feb 8, 2023 · 0 comments

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mkorbel1 commented Feb 8, 2023

Testing for 0-width ports it blocked pending intel/rohd#57.

Some code for testing it is already started in cosim_test.dart.

mkorbel1 mentioned this issue

Consts that inferWidth to 0-width generate SystemVerilog with 0-width intel/rohd#527

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