Generated SV-UVM code from ROHD-VF?

[svenka3]

Hello
I browsed through the counter TB code here and couldn't stop thinking it is quite similar to a classical UVM code. Wondering if this gets translated to UVM under the hood or is that a possibility- somewhere I read ROHD can be thought of as a "generator" hence wondering

Thanks

[mkorbel1]

@svenka3 great question! You're right that ROHD is a generator framework, and that ROHD-VF enables testbenches built with similar structure as UVM. However, ROHD-VF is not able to be converted or translated into SystemVerilog UVM.

ROHD hardware designs are convertible to SystemVerilog because practically all downstream tools (e.g. synthesis) accept SystemVerilog as an input. ROHD designs represent actual hardware, and for them to be useful for real products they have to be able to convert into an intermediate representation that can eventually produce hardware (or be programmed onto an FPGA).

ROHD-VF not translating into UVM may at first seem like a limitation, but it's actually a good thing. Testbenches are software, and they should be written in a fully featured programming language. By writing your testbench in Dart with ROHD-VF, you are unlocking a world of software which is difficult to access from SystemVerilog UVM. If all code in ROHD-VF was convertible to UVM, then you'd be limited to only what could be equivalently represented in UVM.