From 982856b33cb4600b2e0cede8cee951e3bf0b32e6 Mon Sep 17 00:00:00 2001 From: Nirvedh Meshram Date: Tue, 7 Jan 2025 12:11:42 -0600 Subject: [PATCH] [DO NOT MERGE] Add Barrier to fix race issue from different layout Signed-off-by: Nirvedh Meshram --- .../iree/compiler/Codegen/Common/GPU/GPUDistributeForall.cpp | 3 +++ .../Codegen/LLVMGPU/test/ROCDL/pipeline_tile_and_fuse.mlir | 1 + 2 files changed, 4 insertions(+) diff --git a/compiler/src/iree/compiler/Codegen/Common/GPU/GPUDistributeForall.cpp b/compiler/src/iree/compiler/Codegen/Common/GPU/GPUDistributeForall.cpp index 334427cfffb97..1f5bb5068f3aa 100644 --- a/compiler/src/iree/compiler/Codegen/Common/GPU/GPUDistributeForall.cpp +++ b/compiler/src/iree/compiler/Codegen/Common/GPU/GPUDistributeForall.cpp @@ -127,7 +127,10 @@ LogicalResult resolveGPUMappedForallOp(RewriterBase &rewriter, Value ub = getValueOrCreateConstantIndexOp(rewriter, loc, totalLoopTripCount); Value step = rewriter.create(loc, flatTotalNumWorkers); + // This needs to be landed properly do not merge. + rewriter.create(loc); auto forLoop = rewriter.create(loc, lb, ub, step, ValueRange{}); + rewriter.create(loc); Block *loopBody = forLoop.getBody(); // Get the replacement IDs for the forall iterator ids. diff --git a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/pipeline_tile_and_fuse.mlir b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/pipeline_tile_and_fuse.mlir index f71add60f4b1a..886b39bfc500c 100644 --- a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/pipeline_tile_and_fuse.mlir +++ b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/pipeline_tile_and_fuse.mlir @@ -908,6 +908,7 @@ hal.executable public @main { // for loop. // CHECK: vector.transfer_write %{{.*}}, %[[B2]]{{.*}} memref<10x1xf32, #hal.descriptor_type> // CHECK-NEXT: } +// CHECK-NEXT: gpu.barrier // CHECK-NEXT: } {mapping = [#iree_codegen.workgroup_mapping]} // CHECK-NEXT: return