From 8414c7f699a72de92a04d1ae09330608aa2c1c20 Mon Sep 17 00:00:00 2001
From: Wojciech Zabolotny <wzab@HPAIRWZ.lan>
Date: Tue, 26 Dec 2023 16:28:41 +0100
Subject: [PATCH] The changes below enable running "localtest" or "bootstrap"
 in j1b/verilator directory on machines running Debian/testing Linux. Without
 those changes, the Python package needed for simulations could not be built
 and locally installed properly. To use that modified version, you should
 create a virtual environment, activate it and install both setuptools and
 build in it: python3 -m venv env . env/bin/activate pip3 install --upgrade
 setuptools pip3 install --upgrade build

---
 j1b/verilator/Makefile       | 2 +-
 j1b/verilator/pyproject.toml | 7 +++++++
 j1b/verilator/setup.py       | 2 +-
 j1b/verilator/sim_main.cpp   | 3 ++-
 j1b/verilator/vsim.cpp       | 3 ++-
 5 files changed, 13 insertions(+), 4 deletions(-)
 create mode 100644 j1b/verilator/pyproject.toml

diff --git a/j1b/verilator/Makefile b/j1b/verilator/Makefile
index c6485e9..dd29669 100644
--- a/j1b/verilator/Makefile
+++ b/j1b/verilator/Makefile
@@ -12,7 +12,7 @@ obj_dir/Vj1b obj_dir/Vj1b__ALL.a: $(VERILOGS) sim_main.cpp Makefile
 	$(MAKE) -C ..
 
 build/lib/python/vsimj1b.so: setup.py obj_dir/Vj1b__ALL.a vsim.cpp
-	python setup.py install --home build
+	pip3 install .
 
 clean:
 	rm -rf build
diff --git a/j1b/verilator/pyproject.toml b/j1b/verilator/pyproject.toml
new file mode 100644
index 0000000..1b32622
--- /dev/null
+++ b/j1b/verilator/pyproject.toml
@@ -0,0 +1,7 @@
+[project]
+name = "vsimj1b"
+version = "0.1.0"
+[build-system]
+requires = ["setuptools"]
+build-backend = "setuptools.build_meta"
+
diff --git a/j1b/verilator/setup.py b/j1b/verilator/setup.py
index ef76e6f..d7836c7 100644
--- a/j1b/verilator/setup.py
+++ b/j1b/verilator/setup.py
@@ -8,7 +8,7 @@
     Extension('vsimj1b',
               ['vsim.cpp'],
               depends=["obj_dir/Vv3__ALL.a"],
-              extra_objects=["obj_dir/verilated.o", "obj_dir/Vj1b__ALL.a"],
+              extra_objects=["obj_dir/verilated.o", "obj_dir/verilated_threads.o", "obj_dir/Vj1b__ALL.a"],
               include_dirs=["obj_dir",
                             "/usr/local/share/verilator/include/",
                             "/usr/share/verilator/include/",
diff --git a/j1b/verilator/sim_main.cpp b/j1b/verilator/sim_main.cpp
index a2eeff0..5037f49 100644
--- a/j1b/verilator/sim_main.cpp
+++ b/j1b/verilator/sim_main.cpp
@@ -1,5 +1,6 @@
 #include <stdio.h>
 #include "Vj1b.h"
+#include "Vj1b___024root.h"
 #include "verilated_vcd_c.h"
 
 int main(int argc, char **argv)
@@ -20,7 +21,7 @@ int main(int argc, char **argv)
         fprintf(stderr, "invalid hex value at line %d\n", i + 1);
         exit(1);
       }
-      top->v__DOT__ram[i] = v;
+      top->rootp->v__DOT__ram[i] = v;
     }
 
     top->resetq = 0;
diff --git a/j1b/verilator/vsim.cpp b/j1b/verilator/vsim.cpp
index 728bedb..c39dfb5 100644
--- a/j1b/verilator/vsim.cpp
+++ b/j1b/verilator/vsim.cpp
@@ -1,5 +1,6 @@
 #include <assert.h>
 #include "Vj1b.h"
+#include "Vj1b___024root.h"
 #include "verilated.h"
 #define VCD 0
 #if VCD
@@ -59,7 +60,7 @@ Vj1b_init(v3 *self, PyObject *args, PyObject *kwds)
       fprintf(stderr, "invalid hex value at line %d\n", i + 1);
       exit(1);
     }
-    self->dut->v__DOT__ram[i] = v;
+    self->dut->rootp->v__DOT__ram[i] = v;
   }
 
   return 0;